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EK-HS571-TM-001

July 1986

498 pages

Original

19MB

Document:	HSC50/70 Hardware Technical Manual
Order Number:	EK-HS571-TM
Revision:	001
Pages:	498
Original Filename:

OCR Text

EK-HS5 71-1M-OO 1

HSC50/70
Hardware Technical
Manual

Prepared by Educational Services
of
Digital Equipment Corporation

July 1986

Digital Equipment Corporation makes no representation that use of its products with those of other
manufacturers will not infringe existing or future patent rights. The descriptions contained herein dOl not
imply the granting of a license to make use or sell equipment or software as described in this manual.
Digital Equipment Corporation assumes no responsiblity or liability for the proper performance of other
manufacturers' products used with its products.
Digital Equipment Corporation believes that information in this publication: is accurate as of its publication date. Such information is subject to change without notice. Digital E9uipment Corporation is not
responsible for any inadvertent errors.
.
Class A Computing Devices;
NOTICE: This equipment generates, uses, and may emit radio frequency; energy. It has been tested
and found to comply with the limits for a Class A computing device pursuant to Subpart J of Part 15 of
FCC rules for operation in a cOlnmercial environment. This equipment, when operated in a residential
area, may cause interference to radio/TV communications. In such event the user (owner), at his own
expense, my be required to take corrective measures.

Copyright ©1986 by Digital Equipment Corporation
All Rights Reserved.
Printed in U.S.A.
The postpaid READER'S COMMENTS form on the last page of this documen.t requests the user's critical
evaluation to assist in preparing future documentation.
The following are trademarks of Digital Equipnlent Corporation:
DEC
DECUS
DIGITAL
PDP
UNIBUS
VT
RC25

DECnet
DECsystem-l0
DECSYSTEM-20
RSX
VMS
RA60
TA78-81

VAX
RA80

TU78-81
KDB50

UDA50
HSC
MASSBUS
RA80
RA81
KDA50-Q

'.IDI!ID"~D
i:J
~ U~

This document was prepared using an in-house documentation production system. All page composition
and make-up was performed by TEX, the typesetting system developed by Donald E. Knuth at Stanford
University. TEX is a registered trademark of the American Mathematical Society.

TABLE OF CONTENTS

1)reface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CHAPTER 1

•

xxv

OVERVIEW

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2 THE HSC SUBSYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.3 HSC SUBSYSTEM COMMUNICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.4 THE HSC AS A NODE ON A CLUSTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.5 REFERENCE DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ~ . . . 1-5
CHAPTER 2

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

2.1 ][NTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2 PHYSICAL CHARACTERISTICS OF HSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.:2.1 AC Power Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.:2.2 Power Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.:2.3 Blower And Airflow Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.:2.4 Console Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.:2.5 Load Device.
2-3
2.:2.6 Operator Control Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
0

•

2.3 ]FUNCTIONAL CHARACTERISTICS OF HSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.3.1 HSC50 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.3.2 HSC70 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.3.3 Input/Output Control Processor Module (HSC50) . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.3.4 Input/Output Control Processor (HSC70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-12
2.3.5 Memory Module (HSC50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.3.6 Memory Module (HSC70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.3.7 Data Channel Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.3.8 Host Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-22
2.3.9 Port Processor Module (K.pli) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2.3.10 Port Buffer Module (PI LA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-23
2.3.11 Port Link Module (LINK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-24
2.3.12 Backplane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.3.12.1 HSC50 Backplane Jacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2.3.12.2 HSC70 Backplane Jacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2.3.13 Operator Control Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-30
CHAPTER 3

BACKPLANE BUSES AND CONTROL SIGNALS

3.1 ][NTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.2 HSC50/70 BUS DIFFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.3 PROGRAM BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.3.1 Program Bus Master-Slave Relationship . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 3-5

iii

3.3.2 HSC50/70 Program Bus Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-~;
3.3.3 Program Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.3.4 Program Bus Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.3.4.1 Program Bus Interrupt Protocol (HSC70 Only). . . . . . . . . . . . . . . . . . . . . . .. 3-10
3.3.4.2 Program Bus Mastership Protocol (HSC70 Only) . . . . . . . . . . . . . . . . . . . . .. 3-13
3.3.4.3 Program Bus Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
3.3.4.4 Program Bus DATI Cycle . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .. 3-16
3.3.4.5 Program Bus DATa and DATOB Cycle . . . . . . . . . . . . . . . . . . . : . . . . . . . . 3-18
3.3.4.6 Program Bus DATIO and DATIOB Cycles ., . . . . . . . . . . . . . . . . . . . . . . .. 3-21
3.4 BUS REQUESTORS . '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . . . 3-21
3.5 CONTROL BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . ..
3.5.1 Control Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.5.2 Control Bus Cycles . . . . . . . . . . . . . ~ . . . . . . . . . . . . . . . . " . . . . . . . . . . ..
3.5.2.1 Control Bus Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . ..
3.5.2.2 Control Bus Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.5.2.3 Control Bus Interrupt Cycle . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . ..
3.5.2.4 Control Bus Lock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.2.5 Control Bus Non-Memory Access (NMA) Cycle . . . . . . . . . . . . . . . . . . . . . .
3.5.2.6 Control Bus Refresh Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-23
3-24
3-25
3-25
3-28
3-29
3-31
3-31
3-31

3.6 DATA BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . . .
3.6.1 Data Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.6.2 Data Bus Cycles .. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . ..
3.6.2.1 Data Bus Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.6.2.2 Data Bus Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.6.2.3 Data Bus NMA Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . ..

3-32
3-33
3-34
3-34
3-36
3-37

3.7 S ENABLE i L LINES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .. 3-38
3.8 STATUS <7:0> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38
3.9 CLK A HAND CLK B H LINES . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . "

3-38

3.10 CLK CTL H LINE

3-38

3.11 CLEAR x H LINE

3-38

3.12 HOST CLR H LINE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . . . 3-39
3.13 SLOW CYCLE L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. " . . . . . . . . . . .. 3-39
3.14 BASE AND ENA IN AND OUT LINES . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .. 3-39
CHAPTER 4

HOST INTERFACE OVERVIEW

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . . . . 4-1
4.2 PACKET FORMATS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.2.1 Information Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . . . . 4-1
4.2.1.1 Bit Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.2.1.2 Character Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.2.1.3 Packet Type/Length (High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.2.1.4 Packet Length (Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.2.1.5 Destination (True And Complement) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.2.1.6 SOtLrce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.2.1.7 Body . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.2.1.8 Cyclic Redundancy Check (CRC) Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.2.1.9 Trailer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.2.2 Acknowledge/Negative Acknowledge (ACK/NACK) Packet . . . . . . . . . . . . . . . . . . . 4-4
4.3 HOIST INTERFACE (K.ci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.3.1 Port Link Module (Link) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.3.2 Port Buffer Module (PI LA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-10
4.3.3 Port Processor Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-10

CHAPTER 5

PORT LINK MODULE

5.1 PORT LINK MODULE FUNCTIONAL OVERVlEW . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1.1 Infonnation Packet Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.1.2 ACK/NACK Packet Transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.1.3 Infonnation Packet Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.1.4 ACK/NACK Packet Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.2 RECEIVE AND TRANSMIT CHANNELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.2.1 Receive Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.2.1.1 CI Carrier Detection and Path Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.2.1.2 Carrier Detect Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.2.1.3 Receive Path Select Multiplexor - ECL Logic. . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.2.1.4 Manchester Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.2.1.4.1 Phase Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.2.1.4.2 Decoder Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.2.1.5 Sync Character Detect Enable PAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.2.1.6 Byte Framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.2.1.7 RCVR CLK Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.2.1.8 CRC Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-16
5.2.1.9 Destination Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
5.2.1.10 ACK Source Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
5.2.1.11 Receive Data Parity and Channel Output . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
5.2.2 Transmit Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-18
5.2.2.1 Transmit Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-18
5.2.2.2 Bit Sync, Sync Character, and Trailer Bytes . . . . . . . . . . . . . . . . . . . . . . . .. 5-18
5.2.2.3 ACK Packet Inserts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-21
5.2.2.3.1 Packet Type Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-21
5.2.2.3.2 Source Byte .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-21
5.2.2.3.3 Destination Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-21
5.2.2.4 Destination Address Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-21
5.2.2.5 Transmit Data Parity Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-21
5.2.2.6 CRC Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-21
5.2.2.7 XMIT CLK Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
5.2.2.8 Parallel To Serial Data Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-24

5.2.2.9 Manchester Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
5.2.2.10 XMIT ECL Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-24
5.3 CRC GENERATOR AND CHECKER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
5.3.1 CRC Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-26
5.3.2 CRC Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
5.4 ARBITRATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . ..
5.4.1 Arbitration Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.2 Arbitration Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . '.' . . . . . . . . . . . ..
5.4.3 Arbitration Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '.' . . . . . . . . . . . ..
5.4.3.1 Arbitration Countdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.4.3.1.1 LINK Arbitration Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.3.2 Carrier Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . '.' . . . . . . . . . . . ..
5.4.3.3 Receive Channel Busy - Arbitration Condition . . . . . . . . . . . . . . . . . . . . . . .
5.4.3.4 Successful Arbitration Inhibited . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . ..

5-28
5-28
5-28
5-30
5-32
5-32
5-32
5-33
5-33

5.5 LINK FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '.' . . . . . . . . . . . .. 5-33
5.5.1 LINK Control Information and Maintenance Functions . . . . . . '.' . . . . . . . . . . . .. 5-33
5.6 LINK INTERFACE SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35
5.7 LINK OPERATING STATES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,
5.7.1 Message Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.7.1.1 Transmit Control Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.7.1.2 Transmit Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.2 ACK Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.2.1 ACK Receive PAL States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.2.2 Sync Character Detect Enable PAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.3 Message Receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.7.4 ACK Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-35
5-39
5-41
5-41
5-44
5-44
5-46
5-47
5-49

5.8 STATUS LEDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51
CHAPTER 6

PORT BUFFER MODULE (PILA)

6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.2 PORT LINK INTERFACE (PLI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.3 OPERATIONS BETWEEN PILA AND LINK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.3.1 Receive Operation from LINK to PILA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.3.2 Transmit Operation from PILA to LINK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
6.4 PLI LINK CONTROL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
6.4.1 Load Transmit Buffer: LINK CONTROL <3:0> = 0001 . . . . . . . . . . . . . . . . . . . .
6.4.2 Transmit: LINK CONTROL < 3:0 > = 0011 . . . . . . . . . . . . . . . . . . . . . . . . . . ..
6.4.3 Reset Transmit Status: LINK CONTROL < 3:0 > = 0100 . . . . . . . . . . . . . . . . . . . .
6.4.4 Abort Transmission: LINK CONTROL < 3:0 > = 0101 . . . . . . . . . . . . . . . . . . . ..
6.4.5 Enable Link Control: LINK CONTROL <3:0> = 0110 . . . . . . . . . . . . . . . . . . . . .
6.4.6 Disable Link Control: LINK CONTROL <3:0> = 0111 . . . . . . . . . . . . . . . . . . . .
6.4.7 Read Receiver Status: LINK CONTROL <3:0> = 1000 . . . . . . . . . . . . . . . . . . . .

6-10
6-10
6-10
6-12
6-12
6-13
6-14
6-14

6.4.8 Read Transmitter Status: LINK CONTROL < 3:0> = 1001 . . . . . . . . . . . . . . . . ..
6.4.9 Read Buffer: LINK CONTROL <3:0> = 1010 . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.10 Read Node Address: LINK CONTROL <3:0> = 1011 . . . . . . . . . . . . . . . . . . . .
6.4.11 Read Switches: LINK CONTROL <3:0> = 1100 . . . . . . . . . . . . . . . . . . . . . . .
6.4.12 Set Mode: LINK CONTROL <3:0>= 1101 . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.13 Select Buffer: LINK CONTROL < 3:0 > = 1110 . . . . . . . . . . . . . . . . . . . . . . . ..
6.4.14 Sync: LINK CONTROL <3:0> = 1111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-16
6-18
6-19
6-19
6-20
6-22
6-22

6.5 STATUS LEDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
CHAPTBR 7

PORT PROCESSOR MODULE

7.1 Il'JTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.2 STATUS LEDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.3 M1CROINSTRUCTION WORD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.4 PORT PROCESSOR MODULE BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
7.5 SEQUENCERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
7.6 TEST MULTIPLEXER . . . . . . . . . . . . " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.7 PROGRAIv[ ADDRESS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.8 CONTROL STORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.9 ARITHMETIC AND LOGIC UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.10 PIPELINING CONCEPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
7.11 K.pli PIPELINE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
7.12 PIPELINE TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
7.13 SCRATCHPAD MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
7.14 STATUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
7.15 STATUS BUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
7.16 CONTROL BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19
7.17 DATA BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
7.1 ~7.1 Data Bus Data Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-21
7.1~7.2 Data Bus Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
7.18 PLI INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
7.18.1 PLI Data Bus and PLI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.18.2 PLI Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.18.3 PLI Interface Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

7-24
7-24
7-27
7-34

7.19 CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-35
7.20 DATA PARITY GENERATION AND CHECK LOGIC . . . . . . . . . . . . . . . . . . . . . . . . 7-36
7.21 INSTRUCTION PARITY CHECKER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 -36
7.22 DESTINATION DECODER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36
vii

7-36

7.23 IOC LATCHES

7.24 SOURCE DECODER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .. 7-3?
7.25 MICROINSTRUCTION DETAILED DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 7-3?
7.25.1 C Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " . , . . . . . . . . .. 7-39
7.25.2 AD Field . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . . " . , . . . . . . . . .. 7-39
7.25.3 AF Field . . . . . . . . . . . . . ' . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . .. 7-40
7.25.4 AS Field . . . . . . . . . . . . . . " . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . .. 7-40
7.25.5 AB Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " . , . . . . . . . . .. 7-41
7.25.6 + Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " . , . . . . . . . . . . 7-41
7.25.7 RB Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . .. 7-42
7.25.8 TEST Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-42
7.25.9 BD Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . 7-43
7.25.10 @ Field . . . . . . . . . . . . . . : . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . . . 7-44
7.25.11 IOC Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-44
7.25.12 RA Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . .. 7-45
7.25.13 BS Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .. 7-45
7.25.14 SField . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-45
7.25.15 $ Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-46
7.25.16 K Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . .. 7-46
7.25.17 P Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4'7
7.25.18 BA Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-47
7.25.19 Destination and Branch Field Combinations . . . . . . . . . . . . . . . , . . . . . . . . . . 7-4'7
7.25.19.1 Writing Control Bus Address Transceivers . . . . . . . . . . . . . . . . . . . . . . . . 7-47
7.25.19.2 Writing Data Bus Address Transceivers and Counter. . . . . . . . . . . . . . . . .. 7-47
j'

•

••

7.26 HARDWARE DETECTED ERRORS . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . 7-48
CHAPTER 8

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.2 LED INDICATORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.2.1 P.ioc Diagnostic OK LEOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.2.2 RUN LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . . . . 8-3
8.2.3 State LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. " . . . . . . . . . . . . . 8-3
8.3 HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE BLOCK DIAGRAM . . . . . . 8-3
8.4 F-l1 BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . . . . 8-3
8.4.1 Memory Management Unit Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
8.4.1.1 Memory Management Status Register 0 . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 8-7
8.4.1.2 Memory Management Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
8.4.1.3 Memory Management Status Register 2 . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 8-8
8.4.1.4 Memory Management Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
8.4.2 Bus Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 8-9
8.4.3 Data-Address Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 8-9
8.4.4 Microinstruction Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 8-9
8.5 MICRO-ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . . . . 8-9

viii

8.6 INTERRUPT LOGIC

8-10

8.7 ADDRESS DECODE

8-11

8.8 BOOTSTRAP PROM

8-11

8. 9 TU~;8 INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
8.9.1 Parallel P joc Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
8.9.2 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-14
8.10 CONSOLE TERMINAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14
8.11 SERIAL NUMBER REGISTER

8-15

8.12 ER:ROR ADDRESS REGISTER

8-15

8.13 SVVITCH/DISPLAY REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-15
8.14 PIO CONTROL AND STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
8.15 K [NIT AND STATUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-19
8.16 THE INTERFACE TO CONTROL MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.16.1 Control Memory Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1.6.1.1 Control Menlory Window Address Selection. . . . . . . . . . . . . . . . . . . . . . ..
8.1.6.1.2 Control Window Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8.1.6.1.3 Control Window Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8.16.2 Control Bus Interface . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . ..
8.1.6.2.1 Control Bus Data Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8.16.2.2 Control Menlory Address Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.16.3 Control Bus Arbitrator and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8.16.4 Interrupt Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8.165 Lock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

8-20
8-21
8-21
8-24
8-26
8-26
8-27
8-27
8-28
8-28
8-28

8.17 DATA MEMORY INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28
8.17.1 Data Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-29
8.17.1.1 Data Bus Transceivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-29
8.17.1.2 Data Bus Address Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29
8.17.1.2.1 Data Bus Address Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ." 8-29
8.17.1.2.2 Data Bus Address Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29
8.17.2 Data Bus Arbitrator and Timing
8-30
8.18 1101 PAGE ADDRESS UTILIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30
8.19 I/O PAGE REGISTER FORMAT SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-32

CHAPTER 9

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.2 LED INDICATORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.2.1 P.ioj Diagnostic OK LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.2.2 RUN LI~D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.2.3 State LED ....
9-3
9.2.4 Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
0

• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •

9.3 HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE BLOC:;K DIAGRAM . . . . . . 9-3
9.4 P.ioj CONTROL LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9.4.1 DC]ll Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9.4.1.1 Cache Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9.4.1.2 Cache Hit/Miss Register . . . . . . . . . . . . . . . . . . . . ' . . . . . . . . . . . . . . . . . . 9-10
9.4.1.3 CPU Error Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
9.4.1.4 Programmable Interrupt Request Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
9.4.1. 5 Memory Management Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
9.4.1.5.1 Memory Management Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
9.4.1.5.2 Memory Management Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
9.4.1.5.3 Memory Management Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
9.4.1.5.4 Memory Management Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
9.4.1.6 Micro-ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
9.4.2 Input Register and Output Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-14
9.4.3 State Sequencer ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-15
9.4.4 Cache Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-15
9.4.4.1 Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15
9.4.4.2 Memory System Error Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-15
9.4.5 Cache Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
9.4.6 Direct Memory Access Register . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . .. 9-18
9.4.7 Program Memory Bus Receivers . . . . . . . . . . ; . . . . . . . . . . . . . . . . . . . . . . . .. 9-18
9.4.8 Program Memory Bus Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18
9.4.9 Maintenance Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-19
9.5 INTERRUPT LOGIC

9-21

9.6 BOOTSTRAP PROM

9-22

9.7 CONSOLE TERMINAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-22
9.8 AUXILIARY SERIAL INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26
9.9 110 PAGE ADDRESS DECODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26
9.10 PIO CONTROL AND STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-26
9.11 SWITCH/DISPLAY REGISTER . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . . . . . 9-28
9.12 K INIT AND STATUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "

9-30

9.13 ERROR ADDRESS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . :. . . . . . . . . . . . . . . 9-31
9.14 SERIAL NUMBER REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-31
9.15 CONTROL MEMORY INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.15.1 Control Memory Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.15.1.1 Control Memory Window Address Selection . . . . . . . . . . . . . . . . . . . . . . . .
9.15.1.2 Control Window Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
9.15.1.3 Control Window Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.15.2 Control Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
9.15.2.1 Control Bus Data Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
9.15.2.2 Control Memory Address Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . .

9-32
9-32
9-33
9-36
9-38
9-39
9-39
9-39

9.15.3 Control Bus Arbitrator and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-40
9.15.4 Interrupt Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-40
9. Jl5.5 Lock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ; . . . . . . . . .. 9-41
9.16 DATA MEMORY INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.16.1 Data Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
9.16.1.1 Data Bus Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
9.16.1.2 Data Bus Address Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
9.16.1.2.1 Data Bus Address Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.16.1.2.2 Data Bus Address Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.16.2 Data Bus Arbitrator and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

9-41
9-41
9-41
9-41
9-41
9-42
9-42

9.17 110 PAGE ADDRESS UTILIZATION

9-42

9.18 110 PAGE REGISTER FORMAT SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , 9-47
CHAPTER 10

HSC50 MEMORY MODULE

10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-1
10.2 STATUS LED. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-2
10.3 CONTROL MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3.1 RAS/CAS Multiplexor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
10.3.2 8-Bit Refresh Address Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
10.3.3 Select Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
10.3.4 Timing Logic and RAM Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3.5 Data Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3.6 Data Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
10.3.7 Control Memory Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
10.3.7.1 Control Memory Idle Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
10.3.7.2 Control Menlory Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
10.3.7.3 Control Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
10.3.7.4 Control Memory Refresh Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10-2
10-4
10-4
10-4
10-4
10-5
10-5
10-5
10-5
10-5
10-7
10-7

10.4 DATA MEMORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-7
10.4.1 Address Receiver/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
10.4.2 Timing Logic and RAM Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
10.4.3 Select Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
10.4.4 Bank Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
10.4.5 Data Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
10.4.6 Data Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
10.4.7 Data Memory Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
10.4.7.1 Idle Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
10.4.7.2 Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
10.4.7.3 Data Menlory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
10.5 PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
10.5.1 BDAL Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
10.5.2 CAS and RAS Address Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
10.5.3 RAM Address Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15

10.5.4 8-Bit Refresh Address Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
10.5.5 Address Decode Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10.5.6 Write Byte Decode and RAM Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10.5.7 Memory Request Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10.5.8 RAM Timing Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10.5.9 Bank Select Logic and Program Memory RAM Driver . . . . . . . . . . . . . . . . . . . . . 10-17
10.5.10 Data Driver Control and BRPLY Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10.5.11 Data Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10.5.12 Program Memory Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18
10.5.12.1 Program Memory Write Cycle . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . . . 10-18
10.5.12.2 Program Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18
10.5.12.3 Program Memory Read-Modify-Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . 10-21
10.5.12.4 Program Memory Refresh Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21
10.6 JUMPER AND DIPSHUNT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23
CHAPTER 11

HSC70 MEMORY MODULE

11.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , 11-1
11.2 STATUS LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . .. 11-1
11.3 CONTROL MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . . .
11.3.1 Address Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.3.2 Control Memory Eight Bit Refresh Address Counter. . . . . . . . . . . . . . . . . . . . ..
11.3.3 Control Memory Timing Logic and RAM Drivers. . . . . . . . . . .. . . . . . . . . . . ..
11.3.4 Control Memory Data Receivers . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . ..
11.3.5 Control Memory Data Drivers . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . ..

11-3
11-4
11-4
11-4
11-4
11-4

11.4 CONTROL MEMORY CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
11.4.1 Control Memory Idle Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.4.2 Control Memory Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
11.4.3 Control Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
11.4.4 Control Memory Refresh Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11-5
11-5
11-5
11-5
11-8

11.5 DATA MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11.5.1 Data Memory Address Receiver/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11.5.2 Data Memory Timing Logic and RAM Drivers. . . . . . . . . . . . . . . . . . . . . . . . .. 11-8
11.5.3 Data Memory Select Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-8
11.5.4 Data Memory Bank Select Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
11.5.5 Data Memory Data Receivers . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . 11-11
11.5.6 Data Memory Data Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
11.5.7 DATA MEMORY CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
11.5.7.1 Data Memory Idle Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
11.5.7.2 Data Memory Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
11.5.7.3 Data Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
11.6 PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
11.6.1 Program Memory BDAL Buffer . . . . . . . . . . . . . . . . . . . . . . . '. . . . . . . . . . . . . 11-16
11.6.2 Program Memory Rowand Column Address Latches . . . . . . . . . . . . . . . . . . . . . 11-16
11.6.3 Program Memory RAM Address Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16
xii

11.6.4 PrograITI Memory Data Driver Control and Reply Logic . . . . . . . . . . . . . . . . . . . . 11-16
11.6.5 PrograITI Memory Data Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16
11.6.6 PrograIn Memory Eight Bit Refresh Address Counter . . . . . . . . . . . . . . . . . . . . . 11-17
11.6.:7 PrograIn Memory Address Decode Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
11.6.8 Prograrn Memory Write Byte Decode and RAM Driver Logic . . . . . . . . . . . . . . . . 11-17
11.6.9 Progranl Memory Request Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
11.6.10 Program Memory RAM Timing Logic . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . 11-17
11.6.11 Program Memory Bank Select Logic and Program Memory RAM Driver" . . . . . . . 11-17
11.6.12 PROGRAM MEMORY CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
11.6.12.1 Program Memory Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
11.6.12.2 Program Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
11.6.12.3 Program Memory Refresh Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
11.7 FLOPPY DISK CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
11.7.1 Floppy Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-22
11.7.1.1 Command and Status Register (CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-22
11.7.1.2 Memory Address Register O/Track Register (MARO/TREG) . . . . . . . . . . . . . . . 11-24
11.7.1.2.1 MARO <15:8>, Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25
11.7.1.2.2 Track Register < 07:00 >, Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25
11.7.1.3 Memory Address Register lISector Register (MARlISREG) . . . . . . . . . . . . . . 11-25
11.7.1.3.1 MARl < 15:08>, Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25
11.7.1.3.2 Sector Register <07:00>, Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . 11-25
11.7.1.4 Memory Address Register 2/Data Register (MAR2/DREG) . . . . . . . . . . . . . . . 11-25
11.7.1.4.1 MAR2 <21:16> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25
11.7.1.4.2 MAR2, Bit 15, Module OK LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25
11.7.1.4.3 MAR2, Bit 14, Enable DMA Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26
11. 7.2 Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26
11.7.3 K.rx Floppy Controller Block Diagram .. , . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26
11.7.3.1 Program Bus Register Selector, Synchronizer, Register Control PAL . . . . . . . . 11-26
11.7.3.2 Program Bus Transceivers and Vector Control, High Address Driver . . . . . . . . 11-26
11.7.3.3 Parity Generator/Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26
11.7.3.4 Interrupt Control and Vector Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27
11.7.3.5 DMA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27
11.7.3.6 Disk Read PAL, Disk Write PAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27
11.7.3.7 Memory Address Register (MAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27
11.7.3.8 Non-existent Memory Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27
11.7.3.9 Floppy Disk Controller 2797 (FDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27
11.7.3.10 RBUF/XBUF Register (MDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30
11.7.3.11 Disk Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30
11.7.3.12 Command and Status Register (CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30
11.7.3.13 Error Register Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30
11.7.3.14 Cable Driver and Cable Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31
11.7.4: Floppy Disk Controller Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31
11.7.4.1 Floppy Disk Controller Disk Seeks (Type I Commands) . . . . . . . . . . . . . . . . 11-31
11.7.4.1.1 Restore Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33
11.7.4.1.2 Seek Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33
11.7.4.1.3 Step Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33
xiii

11.7.4.1.4 Step In Command . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . 11-33
11.7.4.1.5 Step Out Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-34
11.7.4.2 Floppy Disk Controller Disk Reads and Disk Writes (Type II Commands) ~ .... 11-34
11.7.4.2.1 Read Sector Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-34
11.7.4.2.2 Write Sector Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-35
11.7.4.3 Type III Commands . . . . . . . . . . . . . . . . . . . . . . . : . . . . . . . . . . . . . . . . 11-37
11.7.4.3.1 Read Address Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-37
11.7.4.3.2 Read Track Command . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . 11-37
11.7.4.3.3 Write Track Command (Formatting) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-37
11.7.4.3.4 Status Register Summary . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . 11-37
11.7.4.4 Type IV Commands . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . 11-38
11.8 JUMPER CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-38
CHAPTER 12

DATA CHANNEL MODULE

12.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

••••••••••••••

12-1

12.2 STATUS LEDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.3 MICROINSTRUCTION WORD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-2
12.4 DATA CHANNEL MODULE BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.5 CONTROL AND INTERFACE THE TO REST OF THE HSC . . . . . . . . . . . . . . . . . .. 12-5
12.5.1 Sequencers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2-8
12.5.2 Test Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
12.5.3 Program Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
12.5.4 Control Store and Associated Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
12.5.4.1 Control Store and Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
12.5.4.2 Instruction Parity Checker . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . 12-12
12.5.4.3 ALU Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
12.5.4.4 Bus Source Control . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . 12-12
12.5.4.5 Bus Destination Control . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . 12-13
12.5.4.6 IOC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15
12.5.5 Arithmetic and Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . 12-18
12.5.6 Pipelining Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20
12.5.7 K.sdi/K.sti Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . 12-20
12.5.8 Pipeline Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . 12-22
12.5.9 Scratchpad RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . 12-23
12.5.10 Upper Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23
12.5.11 Lower Control Register . . . . . . . . . . . . . . . . . . . . . . . . . ,. . . . . . . . . . . . . . . 12-25
12.5.12 Diagnostic Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .' . . . . . . . . . . . . . . 12-27
12.5.13 Control Error Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-29
12.5.14 Data Error Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-30
12.5.15 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-32
12.5.16 Control Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . . . . . 12-33
12.5.17 Data Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-33
12.5.17.1 Data Bus Data Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-35
12.5.17.2 Data Bus Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-35
I

xiv

•

••

12.5.18 Sector/Index PALs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-40
12.6 INPUT AND OUTPUT TO THE STANDARD DISK/TAPE INTERCONNECT . . . . . . . . 12-41
12.6.1 Send Level 2 Commands to a Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-42
12.6.2 Receive Level 2 Responses from a Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-43
12.6.3 Send Levell Commands to a Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-43
12.6.4 Send Data to a Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-45
12.6.5 Receive Data from a Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-46
12.6.6 Send Real-Time Controller State to a Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-47
12.6.7 Receiving Real-Time Drive State from a Drive . . . . . . . . . . . . . . . . . . . . . . . . . . 12-51
12.7 MICROINSTRUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-52
12.7.1 C' Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-52
12.7.2 AD Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-53
12.7.3 AF Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-54
12.7.4 AS Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-54
12.7.5 AB Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-55
12.7.6 + Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-55
12.7.7 RB Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-55
12.7.8 TEST Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-56
12.7.9 BD Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-59
12.7.10 @ Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-59
12.7.11 IOC Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-59
12.7.12 RA Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-60
12.7.13 BS Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-60
12.7.14 S Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-61
12.7.15 $ Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-61
12.7.16 K Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-61
12.7.17 P Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 12-62
12.7.18 BA Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-62
12.7.19 Destination and Branch Field Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . 12-62
12.7.19.1 Write Control Bus Address Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . 12-62
12.7.19.2 Write Data Bus Address Transceivers and Counter . . . . . . . . . . . . . . . . . . . 12-63
CHAPTER 13

POWER SYSTEM

13.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-1
13.2 AC POWER CONTROLLER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-1
13.3 AIRFLOW SENSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-1
13.4 POWER SUPPLIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
13.4.1 Main Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
13.4.1.1 Main Power Supply-Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
13.4.1.2 Main Power Supply-Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16
13.4.2 Auxiliary Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16
13.5 INTERACTION BETWEEN MAIN AND AUXILIARY POWER SUPPLIES . . . . . . . . . . . 13-16
13.6 PROTECTION CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17

13.6.1 Over Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17
13.6.2 Over Current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17'
13.6.3 Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18
13.6.4 Ripple and Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18
13.7 POWER FAIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19
13.8 DC POWER SWITCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19
13.9 POWER INDICATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-20
FIGURES
1-1 HSC Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . 1-2
1-2 HSC Subsystem in a Cluster ....., . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
2-1 HSC Components ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2:
2-2 HSC50 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . 2-6
2-3 HSC70 Functional Bl0ck Diagram . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . 2-8
2-4 Input/Output Control Processor Module (HSC50) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2-5 22 Bit Address Allocation (HSC50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2-6 Input/Output Control Processor Module (HSC70) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2-7 22 Bit Address Allocation (HSC70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2-8 Memory Module (HSC50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . 2-16
2-9 Memory Module (HSC70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2-10 Data Channel Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . 2-19
2-11 HSC50 Module Utilization Label Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... 2-20
2-12 HSC70 Module Utilization Label Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2-13 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . 2-22
2-14 Port Processor Module (K. pli) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2-15 Port Buffer Module (PILA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2-16 Port Link Module (LINK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
2-17 HSC50 Backplane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
2-18 HSC70 Backplane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . 2-29
2-19 Operator Control Panel Switches . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . 2-31
2-20 HSC50 Operator Control Panel Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
2-21 HSC70 Operator Control Panel Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
3-1 Program Bus Interrupt Request/Acknowledge Sequence . . . . . . . . . . . . . . . . . . . . . . . 3-11
3-2 Program Bus Interrupt Protocol Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-12
3-3 Program Bus DMA Request/Grant Sequencing .... : . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3-4 Program Bus Request/Grant Bus Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
3-5 Program Bus DATI Flow Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
3-6 Program Bus DATI Timing Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
3-7 Program Bus DATO or DATOB Flow Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
3-8 Program Bus DATO or DATOB Timing Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
3-9 Program Bus DATIO or DATIOB Bus Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
3-10 HSC50 Control Bus Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
3-11 HSC70 Control Bus Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... 3-27
3-12 HSC50 Control Bus Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-28
3-13 pjoclP.ioj Control Bus Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
3-14 Control Bus Interrupt Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30
3-15 Control Bus Lock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32

xvi

3-16 Data Bus Read Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... 3-35
3-17 Data Bus Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3,-37
4-1 Information Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4-2 ACK/NACK Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4-3 Host Interface (K.ci) Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4-4 Host Interface (K.ci) Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
5-1 LINK Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5-2 Receive Channel Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5-3· Receive Path Select Multiplexor-ECL Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5-4 Phase Encoded Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5-5 Manchester Decoder Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5-6 Byte Framer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5-7 RCVR Serial Shift Register (Enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
5-8 Byte Framer Timing Diagram . . . . . . . . . . . . . .". . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
5-9 RCVR CLK Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
5-10 RCVR CLK Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
5-11 Transmit Channel Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
5-12 Sync/Trailer PROM Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-20
5-13 XMIT CLK Generator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
5-14 XMIT CLK Generator Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
5-15 N[anchester Encoder Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
5-16 XMIT ECL Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... 5-26
5-17 CRC Generator/Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27
5-18 CI Bus Arbitration Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
5-19 CI Bus Arbitration Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
5-20 LINK Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34
5-21 LINK Interface Signals . . . . . . . . . . . . . . ., . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36
5-22 Interface Flow Diagram - Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37
5-23 Interface Flow Diagram - Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38
5-24 N[essage Transmit State Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40
5-25 Transmit Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42
5-26 Transmit Status . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43
5-27 ACK Receive State Logic . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45
5-28 Sync Character Detect Enable PAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46
5-29 ]V[essage Receive State Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48
5-30 ACK Transmit State Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-50
6-1 Port Buffer Module Block Diagram(PILA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6-2 P1LI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6-3 Receive Buffers ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6-4 Transmit Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
6-5 Liink Control Command Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
6-6 Transmit Buffer Load ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
6-7 Unk Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
6-8 Receiver Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
6-9 Transmitter Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
6-10 Rleceive or Transmit Buffer Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
6-11 Rlead Switches and Node Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
6-12 Pl[LA Mode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,6-21
7-1 Mficroinstruction Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7-2 Port Processor Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
xvii

7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13
7-14
7-15
7-16
7-17
7-18
7-19
7-20
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
8-11
8-12
8-13
8-14
8-15
8-16
8-17
8-18
8-19
8-20
8-21
8-22
8-23
8-24
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8

2911 Sequencer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . 'l-8
2901 ALU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
K.pli Double Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . . . 7··12
Pipeline Timing for an Instruction Fetch-Execute Sequence . . . . . . . . " . . . . . . . . . . . . 7··14
Generation of LD CRAM ADR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7··15
Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . . . 7··16
Status Bus Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... 7··18
Control Memory Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7··20
Data Bus Address Transceivers and Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7··22
Generating the Data Bus Address . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . ... 7··23
PLI Interface Registers and Control . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . . . . . 7-·25
PLI Interface Double Byte Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-·29
PLI Interface Single Byte Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7..30
PLI Interface Double Byte Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 7--31
PLI Interface Single Byte Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-·32
PLI Portion of the Test Select Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-·33
Generation of Parity Error Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-·38
Microinstruction Word Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-·39
P joc LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
HSC50 Input/Output Control Processor Module Block Diagram . . . . . . . . . . . . . . . . . 8-4
F-ll Processor Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
Memory Management Status Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
Memory Management Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
Receiver Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
Receiver Data Buffer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
Transmitter Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
Transmitter Data Buffer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
Low Error Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
High Error Address Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... 8-15
Indicators and Switches on the Operator Control Panel . . . . . . . . . . . . . . . . . . . . . .. 8-16
Switch/Display Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... 8-16
Pio Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
K INIT Register . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... 8-20
WADR Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22
Window Address Register Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23
WADR Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24
Control Window Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25
Low Control Memory Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27
P.ioc Control Bus Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28
Data Bus Address Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30
110 Page Register Format Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-33
P.ioj LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
HSC70 Input/Output Control Processor Module Block Diagram . . . . . . . . . . . . . . . . . 9-4
P.ioj Control Logic Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
DC}ll Block Diagranl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
Cache Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
Cache Hit/Miss Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
CPU Error Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . . . . . . 9-11
Programmable Interrupt Request Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
xviii

9-9 Memory Management Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
9-10 Memory Management Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
9-11 Memory Management Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
9-12 Clock Register .... ,;,"~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15
9-13 Memory System Error Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
9-14 Logical Subdivision of a 22-bit Physical Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
9-15 Organization of each 29-bit Cache Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
9-16 Program Memory Bus Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19
9-17 Program Memory Bus Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
9-18 Maintenance Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
9-19 Receiver Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-23
9-20 Receiver Data Buffer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-23
9-21 Transmitter Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24
9-22 Transmitter Data Buffer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25
9-23 Pio Control and Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26
9-24 Indicators and Switches on the Operator Control Panel . . . . . . . . . . . . . . . . . . . . . . . 9-28
9-25 Switch/Display Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-29
9-26 K INIT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-30
9-27 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-30
9-28 Low Error Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-31
9-29 High Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-32
9-30 WADR Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-33
9-31 Window Address Register Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-35
9-32 WADR Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-36
9-33 Control Window Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-37
9-34 Low Control Memory Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-39
9-35 P.ioj Control Bus Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-40
9-36 Data Bus Address Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-42
9-37 110 Page Register Fornlat Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-48
10-1 HSC50 Memory Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10-2 Control Memory Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10-3 Control Memory Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
10-4 Control Memory Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
10-5 Control Memory Refresh Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10-6 Data Melnory Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
10-7 Data Melnory Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
10-8 Data Memory Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
10-9 Program Memory Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
10-10 Program Memory Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19
10-11 Program Memory Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20
10-12 Program Memory Refresh Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22
11-1 M.std2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11-2 Control Memory Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11-3 Control Memory Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
11-4 Control Memory Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11-5 Control Memory Refresh Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11-6 Data Memory Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
11-7 Data Memory Write Cycle Tinling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
11-8 Data Memory Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
11-9 Program Memory Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15

xix

11-10 Program Memory Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
11-11 Program Memory Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20
11-12 Program Memory Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21
11-13 Floppy Register Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23
11-14 K.rx Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-28
12-1 Microinstruction Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12-2 Data Channel Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12-3 2911 Sequencer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12-4 Force Lower Sequencer to Vector 37778 Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
12-5 ALU Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .. 12-13
12-6 Bus Source Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1~~
12-7 Bus Destination Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15
12-8 IOC Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16
12-9 2901 ALU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19
12-10 K.sdi/K.sti Double Pipe lining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21
12-11 Pipeline Timing for an Instruction Fetch-Execute Sequence . . . . . . . . . . . . . . . . . . . . . 12-22
12-12 Upper Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-24
12-13 Lower Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-26
12-14 Diagnostic Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28
12-15 Control Error Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-29
12-16 Data Error Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-31
12-17 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-32
12-18 Control Memory Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-34
12-19 Data Bus Address Transceivers and Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-36
12-20 Generating the Data Bus Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... 12-38
12-21 SectorlIndex Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-40
12-22 Send Level 2 Commands to a Drive Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 12-42
12-23 Receive Level 2 Responses from a Drive Block Diagram . . . . . . . . . . . . . . . . . . . . . . 12-43
12-24 Send Level 1 Commands to a Drive Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 12-44
12-25 Send Data to a Drive Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-45
12-26 Receive Data from a Drive Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-46
12-27 K.sdi Real-Time Controller State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-48
12-28 K.sti Real-Time Controller State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-49
12-29 Send Real-Time Controller State to a Drive Block Diagram. . . . . . . . . . . . . . . . . . . . . 12-50
12-30 Receiving Real-Time Drive State frOlu a Drive Block Diagram . . . . . . . . . . . . . . . . . . . 12-52
12-31 Microinstruction Word Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-53
13-1 HSC50 Inside Rear View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13-2 HSC70 Inside Rear View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ; . . . . . . . . . . . . 13-3
13-3 HSC50 AC Power Controller (120/208 Vac)-Front View . . . . . . . . . . . . . . . . . . . . . . 13-4
13-4 HSC50 AC Power Controller (120/208 Vac)-Rear View . . . . . . . . . . . . . . . . . . . . . . . 13-5
13-5 HSC50 AC Power Controller (380-415 Vac)-Front View . . . . . . . . . . . . . . . . . . . . . . 13-6
13-6 HSC50 AC Power Controller (380-415 Vac)-Rear View . . . . . . . . . . . . . . . . . . . . . . . 13-7
13-7 HSC70 AC Power Controller-Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
13-8 HSC70 AC Power Controller-Top View . . . . . . . . . . . . . . . . . . . ; . . . . . . . . . . . . 13-9
13-9 Airflow Sensor Cabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
13-10 HSC50-lnside Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12
13-11 HSC70-Inside Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13
13-12 HSC50 Internal Cabling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14:
13-13 HSC70 Internal Cabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15
13-14 Power Supply Ripple and Noise Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18
xx

13-15 Power Fail Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21
13-·16 HSC50 DC Power Switch Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-22
TABLES

1-1
1-2
2-1
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
5-1
5-2
5-3
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13
7-14
7-15
7-16
7-17
7-18
7-19
7-20
7-21

HSC Subsystem Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Reference Documentation . . . . . . . . . . . . . . . . . . ; . . . . . . . . . . . . . . . . . . . . . . . 1-5
M:odule Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
HSC50/70 Signal Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Program Bus Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Program Bus Signals Which are Identical to Q-Bus Signals . . . . . . . . . . . . . . . . . . . . 3-7
Program Bus Signals Which Differ From Q-Bus Signals . . . . . . . . . . . . . . . . . . . . . . 3-8
Program Bus Data Transfer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Requestor Number Backplane Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
Control Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
Control Bus Cycle Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
Data Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-33
LINK States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
LINK Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... 5-15
N Load Multiplexor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... 5-30
PLI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Path and Buffer Selection by Data Lines 7 and 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
Link Control Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
Receiver Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
Transmit Status Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... 6-18
Module Revision Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-19
Mode Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
Mode Bit 0 and 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
Data Lines < 6:0 > Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
Microinstruction Word Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
ALU Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
Status Registers Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
K"pli Revision Level Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
Definitions of Status Bus Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19
Control of Data Transfers Between the K.pli and the PILA . . . . . . . . . . . . . . . . . . . . 7-26
Directly Connected Status Indicators to the Test Select Multiplexers . . . . . . . . . . . . . . 7-27
PLI Interface Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-34
Control Register Bit Definition .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-35
IOC Latch Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36
Decoding of Bits in the AD Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-40
Decoding of Bits in the AF Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-40
Decoding of Bits in the AS Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-41
Decode of the Bit in the AB Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-41
Decode of the Bit in the + Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-42
Decode of the Bits in the TEST Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-43
Decode of the Bits in the BD Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-44
Decode of the Bits in the IOC field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-44
Decode of the Bits in the BS field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-45
Decode of the Selected Test Condition and TST COND TR . . . . . . . . . . . . . . . . . . . 7-46
Decode of Input Signals for Sequencer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 7-46
xxi

7-22
7-23
7-24
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
8-11
8-12
8-13
8-14
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
9-15
9-16
9-17
9-18
9-19
9-20
9-21
10-1
10-2
10-3
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9

Control Memory Cycles Initiated from Decode of the BA Field . . . . . . . . . . . . . . . . . 7-4:7
Decoding of BR ADR < 10:09> to Generate DNMA . . . . . . . . . . . . . . . . . . . . . . . . 7-48
Hardware Detected Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-48
Memory Management Status Register 0 Bit Description . . . . . . . . . . . . . . . . . . . . . . 8-7
Memory Management Register 3 Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
Interrupt and Trap Vectors for F-11 P.ioc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
Receiver Status Register Bit Description . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 8-12
Read Data Buffer Register Bit Description . . . . . . . . . . . . . . . . . . . .
. . . . . . . 8-12
Transmitter Status Register Bit Description . . . . . . . . . . . . . . .
. . . . . . . 8-13
Transmitter Data Buffer Register Bit Description . . . . . . . . . . .
. . . . . . . 8-13
TU58 Serial Interface Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 8-14
Switch/Display Register Bit Description . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 8-17
Pio Control and Status Register Bit Description . . . . . . . . . . . . . . . . . . . . .
. .8-18
K INIT Register Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19
Status Register Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20
110 Page Address of Window Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2:3
110 Page Address Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30
Cache Control Register Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
CPU Error Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
Program Interrupt Request Register Bit Description . . . . . . . . . . . . . . . . . .
.. 9-11
Memory Management Register 0 Bit Description ..
. . . . . . . . . . . . . . . . . . . . . 9-12
. . . . . . . . . . . . . . . . . . . . . 9-14
Memory Management Register 3 Bit Description ..
Memory System Error Register Bit Description ... . . . . . . . . . . . . . . . . . . . . . . . . 9-16
. . . . . . . . . . . . . . . . . . . . 9-18
Response of the Cache to Various Conditions . . . .
Maintenance Register Bit Description . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 9-2:1
Interrupt and Trap Vectors for J-l1 P.ioj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2:1
Receiver Status Register Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-23
Receiver Data Buffer Register Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24
Transmitter Status Register Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .... 9-24
Baud Rate Select for a DC319 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2:5
Transmitter Data Buffer Register Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2:6
Pio Control and Status Register Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2:7
Switch/Display Register Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2:9
K IN IT Register Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-30
Status Register Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-31
I/O Page Address of Window Address Registers . . . . . . . . . . . . . . . . . . . .
. . 9-34
Low Control Memory Address Register Bit Description . . . . . . . . . . . . . . .
. .9-4:0
110 Page Address Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 9-43
Size of Memory and Type of RAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 .. 1
Data Memory Bank Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-·11
HSC50 Memory Module Jumper and Dipshunt Configuration . . . . . . . . . . . . . . . . . . 10-23
Memory Bank Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-·11
Program Memory Bank Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-·16
Command and Status Register Bit Assignments (High Byte) . . . . . . . . . .
. . . . . . . 11-·24
Floppy Disk Controller Command Summary .... . . . . . . . . . . . . . . .
. . . . . . . 11--32
Head Positioning Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 11--32
Head Positioning Command Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11--33
Read Sector Command Argunlents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-·34
Status for Type II and Type III Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11··35
Write Sector Command Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-·36
xxii

11-10 Status Register Sunlmary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-37
11-11 HSC70 Memory Module Jumper Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-39
12-1 IVlicroinstruction Word Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12-2 IOC Control Bit Description . . . . . . . . . . ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16
12-3 ALU Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20
12-4 Upper Control Register Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-25
12-5 Lower Control Register Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-27
12-6 Diagnostic Register Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-27
12-7 Control Error Register Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-30
12-8 Data Error Register Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-31
12-9 Sector/Index Register Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-40
12-10 Decoding Bits in the AD Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-53
12-11 Decoding Bits in the AF Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-54
12-12 Decoding Bits in the AS Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-54
12-13 Decode the Bit in the AB Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-55
12-14 Decode the Bit in the + Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... 12-55
12-15 Decode the Bits in the TEST Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-56
12-16 Description of the Bits to the Upper Test Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . 12-57
12-17 Description of the Bits to the Lower Test Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . 12-58
12-18 Decode the bits in the BD Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-59
12-19 Decode the Bits in the IOC Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-60
12-20 Decode the Bits in the BS Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-60
12-21 Decode the Selected Test Condition and TST COND TR . . . . . . . . . . . . . . . . . . . . . 12-61
12-22 Decode Input Signals for Sequencer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-62
12-23 Control Memory Cycles Initiated from Decode the BA Field . . . . . . . . . . . . . . . . . . . 12-63
12-24 Decoding BR ADR < 10:09 > To Generate DNMA . . . . . . . . . . . . . . . . . . . . . . . . . . 12-63
13-1 IVlain Power Supply Outputs-Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
13-2 IVlain Power Supply Outputs-Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16
13-3 Over Voltage Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-17
13-4 Dead Short Current of the Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18

xxiii

Preface
This manual provides a technical description of the HSC50/70 subsystem and is for use by support level
field service representatives. It includes:
•

A block diagram description of the HSC50 and HSC50 hardware

•

A block diagram description of each module in the HSC50/70

•

A description of the buses in the HSC50 and HSC70

•

A description of the power system

All informlation in this manual is informational and designed to help field service personnel understand
the HSC50 and HSC70 components and their interrelationships. Reader knowledge in the following
areas is assumed:
•

Digital Storage Architecture (DSA)

•

l\Jass Storage Control Protocol (MSCP) and Tape Mass Storage Control Protocol (TMSCP)

•

External cabling - Standard Disk Interface (SDI), Standard Tape Interface (STI) and Computer
Interconnect (CI)

•

Basic HSC50 and HSC70 operation

The following information is not included in this manual:

•
•
•
•
•
•
•
•

User information
Utilities and diagnostics
Installation
Service information
Software information
Special chip description
PAL equations
Boot PROM listings

For source~ material on these and other subjects not within the scope of this manual, refer to the related
documentation list at the end of Chapter 1.
NOTE
Because this manual covers both the HSC50 and
HSC70, the acronym HSC is used when both servers
perform the same function.

xxv

OVERVIEW

CHAPTER 1
OVERVIEW

1.1 INTRODUCTION
This chapter gives you an overview of what the HSC mass storage server is capable of doing and how
it works in a subsystem and in a cluster.
1.2 THE HSC SUBSYSTEM
The HSC mass storage server is a stand-alone controller in the Digital Storage Architecture (DSA). See
Figure 1-1. The HSC:
•

Connects to the hosts(s) via a Computer Interconnect (CI) Bus.

•

Follows the rules of System Communications Architecture (SCA) and System Communications
Services (SCS) because it is a passive node on a cluster. (A passive node does not initiate
commands on the CI Bus.)

•

Receives Mass Storage Control Protocol (MSCP) commands from a host and returns MSCP
end messages. It sends MSCP error messages and MSCP attention messages to the host when
appropriate.

•

Provides:
•

MSCP disk server

•

MSCP tape server

•

Diagnostics and Utilities Protocol (DUP) server

•

Serves Inultiple hosts since it is part of a CI cluster. The HSC is the first DEC mass storage
server to do so.

•

Manages both disk units and tape formatters. By using the Digital Storage Architecture, you
can add new types of mass storage units to the controller when the units become available.

•

Runs its own self-contained tests on initialization. If the tests pass, it loads and runs more
comprehensive self-tests. If these tests pass, it then boots the functional software or off-line
diagnostic software from the load device.

1-1

<
m

l:J

:e
Figure 1-1 USC Subsystem

CONSOLE
TERMINAL

LOAD
DEVICE

I SOl

HSC

......
I

I",)

STI
HOST

CI- - - - - ,
1--(MSCP)
(TMSCP)
(DUP)

r--I
STAR
COUPLER

MAGTAPE
FORMATTER

I
I
I

------

---,
I
I
I

I
I

I
I
I

IL _ _ _ _ _ _ _ _ _ _ _ _ _ _ .I

SHADOW
SET

DUAL
PORTED
RA
SERIES
DRIVES

CX-911A

OVERVIEW

•

Runs in-line diagnostics in parallel with the function of an MSCP server. Some in-line diagnostics test the disk and tape units and some test the HSC itself. These diagnostics can be
initiated in several ways:
•

Automatically (spawned by error thresholds)

•

Periodically (started by internal software timer)

•

On Demand (initiated via the local terminal)

•

Via OUP commands (from the host)

There are no host resident (on-line) diagnostics for either the HSC or the disk or tape units.
However, the HSC echoes a CI Bus exerciser test packet sent from a host.
•

Runs its own set of local utilities in parallel with the MSCP server. They can be initiated
m,anually from the local terminal or via a OUP command from a host.

•

Runs off-line diagnostics. These off-line diagnostics are loaded from the internal HSC load
device and run in off-line mode. While in this mode, the server does not respond to the CI
and, therefore, is not functioning as an MSCP server. These off-line diagnostics are selected
and run by the operator via the local terminal. They test only the HSC itself, not the disk or
tape units. The only way to get back to the normal user mode is to reboot using the HSC
functional software.

•

M:anages the IIO operations by initiating seeks and head switches necessary to select the proper
track. It also monitors rotational position, checks headers, reads/writes data, checks for errors,
provides error handling, etc.

•

R1esequences the command queue for faster throughput.

•

Fragments long transfers for faster throughput.

•

Revectors bad blocks.

•

Provides server-initiated bad block replacement (CIBBR).

•

Provides local shadowing. Shadowing is maintaining data on two identical disk drives instead
of only one. Thus, if a drive fails, the data stored on that drive is available from another
m.ember of the shadow set.

•

Provides tape backup/restore without using host resources.

•

M(anages tape I/O operations.

•

Ensures data integrity with the following types of data integrity checks:
•

Cyclic redundancy check (CRC) on all CI packets

•

Error detection check (EDC) on all data blocks

•

Error correction code (ECC) on all data blocks

•

Byte parity on all internal memory and buses

•

Provides an Operator Control Panel (OCP) fault code display and a red/green LED display on
mlost modules upon detecting a fatal error.

•

Provides physical and electrical isolation. It is the first DEC mass storage server to be packaged
in its own cabinet with its own backplane, power supplies, and cooling. The CI cables to the
host(s) are point to point from the Star Coupler. The SOIlSTI cables to the units are radially
connected, and all are transformer isolated. This means some components of the subsystem
can be disconnected and replaced without having to power down the other components.

1-3

OVERVIEW

•

Has no knowledge of file structure. The HSC responds to any legal command from any host.
File structure, file management, and file protection are host responsibilities.

1.3 HSC SUBSYSTEM COMMUNICATIONS
Figure 1-1 shows the different buses, protocol, and devices that communicate with the HSC subsystem.
Within the subsystem, there are certain protocols that have been standardized. Table 1-1 describes what
communications and/or protocol take place in the HSC subsystem.

Table 1-1

HSC Subsystem Communications

Device

Description

The CI bus carries three different protocols between the host and the controller:
Mass Storage Control Protocol (MSCP) defines the protocol used between
the host and the HSC for disks.
Tape Mass Storage Control Protocol (TMSCP) defines the protocol used
between the host and the HSC for the tape formatters.
Diagnostics and Utilities Protocol (DUP) defines the protocol used by the
host/controller to communicate between the host terminal and the HSC
software for running diagnostics and utilities. This allows an operator to
run the diagnostics and utilities from a host tenninal.

SOl

Standard Disk Interconnect (SDI) defines the:
Protocol used between the HSC and the disk unit.
Cable and signals used between the HSC and the disk unit.
Responsibilities of the HSC and disk unit.

DSDF

Digital Standard Disk Format (DSDF) defines the layout and format of the
disk unit.

STI

Standard Tape Interconnect (STI) defines the:
Protocol used between the HSC and the tape formatter.
Cable and signals used between the HSC and the tape formatter.
Responsibilities of the HSC and tape formatter.

ANSI

ANSI defines the format used on mag tape.

Load Device

The HSC loads the function software or diag;nostic software source into
memory via the load device.

Console Terminal

The console ternlinal is used to run the diagnostics or utilities.

1-4

OVERVIEW

1.4 THE HSC AS A NODE ON A CLUSTER
The HSC is a passive node on a cluster. Figure 1-2 shows a cluster with two HSCs cabled to dual ported
disk drives and tape formatters. In this configuration, you can take an HSC off line without disturbing
host cOlnputer or storage unit operations. A cluster can be made up of all VAXs or Large Computer
Group (LCG) systems.
1.5 REFERENCE DOCUMENTATION
This manual contains HSC50 and HSC70 hardware technical description. Other documents cover different subjects. All are listed in Table 1-2.

Table 1·-2

Reference Documentation

Designclltion

Description

AA-GJ\.1rEAA-TK

HSC User Guide-contains information on operator controls and utility programs.

EK-HSC70-SV

HSC70 Service Manual - contains information necessary for effective service and
maintenance of the product.

EK-HSC70-MG

HSC70 Pocket Maintenance Guide - this guide is a subset of the service manual.

EK-HSS71-TM

HSC50170 Hardware Technical Manual - contains hardware theory of operation
for the HSC50 and HSC70. Distribution is limited to internal support level
personnel.

EK-HSS72-TM

HSC50170 Software Technical Manual - contains software descriptions and internal
software and microcode flows for the HSC50 and HSC70. Distribution is limited
to internal support level personnel.

EK-HSS74-TM

HSC50lHSC70 Chip Description Technical Manual - contains information on special
chips, PAL equations, and Boot PROM listings for the HSC50 and HSC70.

EK-HSC70-IP

HSC70 Illustrated Breakdown-·a collection of illustrations that relate the part to the
part number.

EK-881PC-UG

881 Power Controller User Guide-contains information on the operation of the 881
Power Controller.

MP-01422

HSC50 Field Print Set-contains the engineering assembly drawings and circuit
.
schematics of the HSC50.

MP-01426

HSC70 Field Print Set-contains the engineering assembly drawings and circuit
schematics of the HSC70.

Manuals beginning with EK can be ordered from Printing and Circulation Services, 10 Forbes Road,
Northboro, Massachusetts 01532. The rest of the manuals and print sets can be ordered from the
Software Distribution Center, 20 Forbes Road (NR4), Northboro, Massachusetts 01532.

Figure 1-2 HSC Subsystem in a Cluster

o
<
m
l:J

LOAD
DEVICE

HOST

:sm
:e

CONSOLE
TERMINAL

I SOl
3

HSC

STI

HOST

(MSCP)
(TMSCP)
(DUP)

0'\

A
-,-1

J
STAR
COUPLER

HOST

MAGTAPE
FORMATTER

J
STI

I
I

r---

1------- ---,
I

DSDF

I
I

1-_-_. -------I

SHADOW
SET

DSDF

----

DSDF

I
I
I

_ _ _ _ .JI

DUAL
PORTED
RA
SERIES
DRIVES

t--

HSC

! SOl

HOST

I
LOAD
DEVICE

CONSOLE
TERMINAL

CX-9S3A

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

CHAPTER 2
HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

2.1 INTRODUCTION
The first part of this chapter describes the physical characteristics of the HSC. The second part of the
chapter de'scribes the functional characteristics of each module in the HSC.
2.2 PHYSICAL CHARACTERISTICS OF HSC
Figure 2-1 shows the physical components of the HSC. These components are:
AC power controller
N[ain power supply
Auxiliary power supply
Blower for the logic modules
Airflow sensor for the blower
Logic module set
Four CI coax connectors
SlDIISTI port connectors
Twenty four for HSC50
Thirty two for HSC70
Operator Control Panel (OCP)
Load device
TU58 for HSC50
Floppy disk for HSC70
Connector for a console terminal
2.2.1
AC Pow~r Controller
The three-phase input ac power controller provides single-phase ac power to the main power supply,
auxiliary power supply, and the blower for the logic. The HSC has one of the following ac power
controllers:
HSC50-AA-70-19122-01 for 120/208 Vac
HSC50-AB-70-20613-01 for 380/415 Vac
HSC70-AA-881A for 120/208 Vac
HSC70-AB-881B for 380/415 Vac
All four ac power controllers use the Digital Power Sequencing Bus for ac power sequencing. (For more
infornlation on the ac power controllers, refer to Chapter 13.)

2-1

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

Figure 2-1 USC Components

CI A REC
CI A TRANS
LOGIC MODULES
CI B REC
DC

CI B TRANS
AC
MAIN PS
AC
POWER
CONTROLLER

SDI/STI
PORTS

AC
~----------~ AUXPS

AIRFLOW
SENSOR

SIG

AC
AC SEa
CX-336B:

2.2.2
Power Supplies
There are two power supplies in the HSC: the main and auxiliary. The main power supply is always
installed in the HSC50. If the HSC50 has more than eight modules installed, you will see an auxiliary
power supply. The HSC70 always has both power supplies. The two power supplies provide the
following voltages:
.

+ 12 volts (main power supply only)
-5.2 volts (main power supply only)
+ 5 volts (both power supplies are in parallel)
You cannot adjust these power supplies in the field. (For more information on the power supplies, refer
to Chapter 13.)

2-2

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

2.2.3
Blower And Airflow Sensor
The blower provides cooling for the logic modules. It receives ac power from the ac power controller.
The airflow sensor monitors the velocity of the exhausted air through the outlet duct. The airflow sensor
switch is self heating and requires cool air to stay open. If the blower stops, the sensor switch closes
and energizes a relay that does one of the following:
Trips the main circuit breaker in the ac power controller of the HSC50 to remove ac power
De-energizes a relay in the ac power controller of the HSC70 to remove ac power
2.2.4
Console Terminal
The HSC has its own console terminal. It allows you to:
Run diagnostics
Run utilities
Receive error printouts
Receive crash dumps
The following terminals are shipped with the HSC:
LA 12 with HSC50
VT220 and LA50 with HSC70
2.2.5
Load Device
The HSC has a load device that performs the following functions:
Loads operational software
Stores system parameters
Loads diagnostics
Records crash exception information for HSC50
Records crash dumps for HSC70
The following are the two load devices:
TU5S for the HSC50
Floppy disk for the HSC70
2.2.6
Operator Control Panel
The OpE~rator Control Panel provides an operator interface to the HSC. The panel contains the following
indicators and switches:
State indicator
Power indicator
Init indicator/switch
Fault indicator/switch
Online indicator/switch
Two blank indicators/unused switches
Secure/Enable indicator/switch

2-3

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

2.3 FUNCTIONAL CHARACTERISTICS OF HSC
This section describes the functional characteristics of the HSC. First, let's look at the various names of
modules and terms you will see in this section. Table 2-1 shows you the various names of the modules
used in the HSC50 and HSC70.

Table 2-1

Module Nomenclature

Module
Name

Engineering
Name

Module
Designation

Port Link

LINK
or
Interprocessor
Link
Interface

LOIOO

Port Buffer

PILA

LOl09

Port Processor

K.pli

LOl07-YA

Host Interface
K.ci

Consists of Port Link, Port Buffer, and Port
Processor Modules

Disk Data Channel

K.sdi

LOl08-YA

Tape Data Channel

K.sti

LOl08-YB

Data Channel

Disk Data Channel
Tape Data Channel

lnput/Output Control
Processor (HSC50)

P.ioc

LOl05

Input/Output Control
Processor (HSC70)

P.ioj

LOllI

Memory (HSC50)

M.std

LOl06

Memory (HSC70)

M.std2

LOl17

M.ctl

Control Memory

M.prog

Program Memory
Private Memory

M.data

Data Memory

K.rx

Floppy Disk Controller

2-4

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

Table 2-1 (Cont.)

Module Nomenclature

Module
Name

Engineering
Name

Module
Designation

Requestor

Any module that requests the use of an internal HSC bus

A K.sdi, K.sti, or K.pli

RO
R9

Requestor 0 through 9 (lowest priority is 0,
highest is 9)

P.ioc
P.ioj

K.pli

R2-R9

K.sdi or K.sti

HSC50 Block Diagram
2.3.1
Figure 2-2 is a functional block diagram of the HSC50. The module set consists of the following modules:
Port Link Module (LINK)
Port Buffer Module (PILA)
Port Processor Module (K. pli)
Data Channel Module (K.sdi or K.sti)
~Aemory Module (M.std)
1/0 Control Processor (P .ioc)
Also notice that the HSC50 has:
A console terminal
An Operator Control Panel (OCP)
A dual TU58 load device
HSC70 Block Diagram
2.3.2
Figure 2-3 is a functional block diagram of the HSC70. The HSC70 has different features than the
HSC50. The HSC70 features are described below:
•

A new 110 Control Processor Module (P .ioj)

•

A new Memory Module (M.std2)

•

A new load device (floppy disk drive)

•

Two more data channel modules (eight maximum)

•

I\Tew backplane
NOTE
You cannot upgrade an HSC50 to an HSC70.

2-5

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

Figure 2-2

HSCSO Functional Block Diagram

FORMATTER

TA
TAPE
FORMATTER

K.ci

STI

SDI

CI PATH A
LINK

PILA

K.pli

K.sdi

K.sti

L0100

L0109

L0107-YA

L0108-YA

L0108-YB

DATABUS

r------- -- -- -- ------------~

-- -- --

PLI

~-----------------~
~____________________~ ~______~-------------C~TROL~US-------------,

~~---------------------------1 TO 6 DATA CHANNEL MODULES
CX-1085A
Sheet 1 of 2

(Continued on next page)
2-6

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

Figure :Z-2 (Cont.)

HSC50 Functional Block Diagram

STI

A
TAPE
FORMATTER
-{

STI

PROGRAM BUS

PROGRAM
MEMORY
1,.0106

SOl

K.xxx

K.sdi

L01xx-x

L0108-YA

DATA

P.ioc

OCP

L0105

o 0 [[ill

CONTROL

CONTROL BUS
DUAL TU58

--------------------------~~

eX-l085A

Sheet 2 of 2

2-7

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

Figure 2-3 HSC70 Functional Block Diagram

FORMATTER

TA
TAPE
FORMATTER

K.ci

SOl

STI

CI PATH A
LINK

PILA

K.pli

K.sdi

K.sti

L0100

L0109

L0107-YA

L0108-YA

L0108-YB

1 - - - - - -- -- -

PLI
~------

----~

-- -- --- -- -- -----------------

CONTROL BUS------------~

~--------------------~ ~---------------------

\----------1 TO 8 DATA CHANNEL MODULES

CX-1086A.
Sheet 1 of 2

(Continued on next page)

2-8

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

Figure 2-3 (Cont.)

HSC70 Functional Block Diagram

--0
STI

FLOPPY DISK
DRIVES

FLOPPY
CONTROLLER

PROGRAM BUS

PROGRAM
M.std2
LOl17

SDI

K.xxx

K.sdi

LOlxx-x

L0108-YA

DATA

P.ioj
LOlll

OCP

[IT]

CONTROL

DATA BUS

CONTROL BUS

----------.----------~/
CX-l086A

Sheet 2 of 2

2-9

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

2.3.3
Input/Output Control Processor Module (HSCSO)
The HSCSO Input/Output Control Processor Module (Pjoc) provides a function similar to that of a CPU
in a computer system. The CPU is an F-II chip set that performs the standard PDP-11134 instruction
set. The L series hex height module (LOI0S) is in slot one of the backplane. This module contains the
following (Figure 2-4):
•

ROM (for self-test and booting software)

•

Memory Management Unit (MMU)

•

Line clock (fixed frequency)

•

10 register (serial number)

•

110 page registers

•

DC power supply voltage monitor

•

Control and Data Bus arbitration logic

•

Parity generation and checking for the three memories

•

Control Memory Windows (simplifies the addressing scheme of the F-II when accessing Control Memory)

The pjoc uses the following interfaces:
•

Status Bus (status of each K)

•

Status Enable (enable status of K to Status Bus)

•

IN IT (initialize each K)

•

Power fail signal from the power supplies (ac dropping) for a standard PFI (trap to 24)

•

Program Bus (termination and arbitration on P joc)

•

Control Bus (termination and arbitration on P joc)

•

Data Bus (termination and arbitration on P.ioc)

•

IN IT for K. pli (initialize the P .ioc)

•

Operator Control Panel (OCP) through the switch/display register in the 110 page

•

TUS8 controller through a serial port

•

Console terminal through a serial port

•

Four LEOs for module status

The pjoc has four LEOs that help you troubleshoot the HSCSO. Figure 2-4 shows the location of the
LEOs. The following describes the function of each LED:
•

The top yellow LED is the State indicator (this LED and the State indicator on the OCP blink
to indicate normal operation)

•

Next to the top yellow LED is the RUN indicator (blinks once each time the F-II fetches an
instruction)

•

The red LED is the Diagnostic/Testing Fail indicator (initialized on and then turned off by the
software after passing diagnostics)

•

The green LED is the Diagnostic Passed indicator (turned on when the red LED is turned off)

2-10

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

Figure 2-4 Input/Output Control Processor Module (HSC50)

STATUS BUS

PROGRAM BUS

~------'I,.--.t

DATA BUS

STATUS ENABLE I

I
CONTROL BUS

POWER FAIL - - , . . .

F - 11
ROM
MMU
LINE CLOCK
POWER SUPPLY MONITOR
CONTROL MEMORY WINDOWS

~_ _

INIT FROM
K.ci

OCP

CONSOLE
TERMINAL

o
o
o

YELLOW LED
YELLOW LED
RED LED
GREEN LED
CX-1087A

2-11

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

The 22-bit Address Bus allows the F-11 to address up to 4 Mbytes of memory. Figure 2-5 shows the
starting address of the memories and the 110 page.
Figure 2-5 22 Bit Address Allocation (HSCSO)
17777777
17760000

I/O PAGE
8 KBYTES

17757777
17000000

UNDEFINED
248 KBYTES

16777777

CONTROL
MEMORY
256 KBYTES
SPACE
(128 KBYTES
IMPLEMENTED)

16000000
15777777

14000000
13777777

00000000

DATA
MEMORY
512 KBYTES
SPACE
(128 KBYTES
IMPLEMENTED)
PROGRAM
MEMORY
3.0 MBYTES
SPACE
(256 KBYTES
IMPLEMENTED)
CXO-1127A

2.3.4
Input/Output Control Processor (HSC70)
The HSC70 Input/Output Control Processor Module (P .ioj) provides a function similar to that of a CPU
in a computer system. The CPU is a J-11 chip set that performs the standard PDP-11170 instruction
set. The L series hex height module (L0111) is in slot one of the backplane. This module contains the
following (Figure 2-6):
•

ROM (for self-test and booting software)

•

8 Kbyte instruction cache

•

Line clock (fixed frequency)

•

ID register (serial number)

•

110 page registers

•

DC power supply voltage monitor

•

Control and Data Bus arbitration logic

•

Parity generation and checking for the three Inen10ries

2-12

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

Figure 2-6

Input/Output Control Processor Module (HSC70)

STATUS BUS

PROGRAM BUS

DATA BUS

STATUS ENABLEI

I
CONTROL BUS
INIT

POWER FAIL--.....

J - 11
ROM
POWER SUPPLY MONITOR
LINE CLOCK
ID REGISTER
CONTROL MEMORY WINDOWS
CACHE CONTROL

....- -

INIT FROM
K.ci

OCP

CONSOLE
TERMINAL

0
0
0
0
0
0

YELLOW LED
YELLOW LED
YELLOW LED
YELLOW LED
YELLOW LED
YELLOW LED

RED LED

GREEN LED
CX-1088A

•

Control Memory Windows (simplifies the addressing scheme of the J-ll when accessing Control Memory)

The P .ioc uses the following interfaces:
•

Status Bus (status of each K)

•

Status Enable (enable status of K to Status Bus)

•

INIT (initialize each K)

•

PlOwer fail signal frOln the power supplies (ac dropping) for a standard PFI (trap to 24)

•

Plrogram Bus (termination and arbitration on P .ioj)

2-13

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

•

Control Bus (termination and arbitration on P .ioj)

•

Data Bus (termination and arbitration on P .ioj)

•

INIT for K. pH (initialize the P .ioj)

•

Operator Control Panel (OCP) through the Switch/Display Register in the 110 page

•

Console terminal through a serial port

•

Eight LEOs for module status

The P.ioj has eight LEOs that help you troubleshoot the HSC70. Figure 2-6 shows the location of the
LEOs. The following describes the function of the LEOs.
•

The top yellow LED is on at power up and then turned off by the initialization microroutine in
the J-l1. When the J-ll enters .uODT, the J-ll turns on the LED. When the J-ll exits .uODT,
the J-11 turns off the LED.

•

The next yellow LED is on at power up and then turned off by the initialization microroutine
in the J-11. The micro routine turns the LED off after testing that Program Memory:
•

Location 000000008 does not generate a non-existent memory (NXM)

•

Location 177777008 does generate an NXM

•

The next yellow LED is on at power up and then turned off by the initialization micro routine
in the J-l1. The microroutine turns the LED off after testing that the 110 address of the console
terminal is not an NXM address.

•

The next yellow LED is on at power up and then turned off by the initialization microroutine
in the J-l1. The microroutine turns the LED off after initializing the J-ll chip set and testing
the CPU error register.

•

The next yellow LED is the State indicator (this LED and the State indicator on the OCP blink
to indicate normal operation)

•

The next yellow LED is the RUN indicator (blinks once each time the J-11 fetches an instruction)

•

The red LED is the Diagnostic/Testing Fail indicator (initialized on and then turned off by the
software after passing diagnostics)

•

The green LED is the Diagnostic Passed indicator (turned on when the red LED is turned IOff)

2-14

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

The 22·,Bit Address Bus allows the J-11 to address up to 4 Mbytes of memory. Figure 2-7 shows the
starting address of memories and the 110 page.
Figure 2-7 22 Bit Address Allocation (HSC70)

17777777
17760000

I/O PAGE
8 KBYTES

17757777
17000000

UNDEFINED
248 KBYTES

16777777

CONTROL
MEMORY
256 KBYTES
SPACE
(256 KBYTES
IMPLEMENTED)

16000000
15777777

14000000
13777777

00000000

DATA
MEMORY
512 KBYTES
SPACE
(512 KBYTES
IMPLEMENTED)
PROGRAM
MEMORY
3.0 MBYTES
SPACE
(1.0 MBYTES
IMPLEMENTED)
CXO-1128A

2.3.5
Memory Module (HSC50)
The HSC50 Memory Module (M.std) contains the following three memories (Figure 2-8):
•

Progranl Memory-used for program storage for the P .ioc-256 Kbytes

•

Data Memory-used for data buffers-128 Kbytes

•

Control Memory-used for control blocks - 128 Kbytes

This module is an L0106 hex height module and is in slot two of the backplane.
The Memory Module has no self-test; however, the following modules test the memory module:
P.ioc
K.sdi/K.sti
K.pli

2-15

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

Figure 2-8

Memory Module (HSC50)

PROGRAM
MEMORY
256 KBYTES
DYNAMIC

DATA
MEMORY
128 KBYTES
STATIC

DATA BUS

CONTROL
MEMORY
128 KBYTES
DYNAMIC

CONTROL BUS

PROGRAM MEMORY ACTIVE
DATA MEMORY ACTIVE
CONTROL MEMORY ACTIVE

GREEN LED

--CX-l089A

2-16

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

The word structure is a 16-bit data word plus high-byte and low-byte parity bits. The Memory Module
provides no parity generation or checking. Those responsibilities belong to the modules that access the
memories. The m.emories interface to the following buses:
Program Memory Bus
Control Memory Bus
Data Memory Bus
The Mernory Module has one green LED that indicates memory activity. (Refer to Figure 2-8.) The
condition shown is an OR of the three memory cycles.
2.3.6
Memory Module (HSC70)
The HSC70 Memory Module (M.std2) contains the following logic (Figure 2-9):
•

Program Memory-used for program storage for the P.ioj-1.0 Mbytes

•

Data Melnory-used for data buffers-256 Kbytes

•

Control Memory-used for control blocks-512 Kbytes

•

Floppy Disk Controller

This module is an LOl17 hex height module and is in slot two of the backplane.
The Floppy Disk Controller controls the two floppy disk drives. The I/O Control Processor issues
comnlands to and checks status of the controller through the 110 page via the Program Bus.
The MelTLOry Module has no self-test; however, the following modules test the memory nlodule:
P.ioj
K.sdi/K.sti
K.pli
The word structure is a 16-bit data word plus high-byte and low-byte parity bits. The Memory Module
provides no parity generation or checking. Those responsibilities lay in the modules that access the
memories. The memories interface to the following buses:
Program Memory Bus
Control Memory Bus
Data Memory Bus
The Mem.ory Module has three LEDs located near the bottom (Figure 2-9). The following describes the
function of the LEDs:
•

The red LED is the Diagnostic/Testing Fail indicator (initialized on and then turned off by the
lPjoj after the memory module passes tests performed by the P.ioj, K.sdi/K.sti, and K.pli)

•

The yellow LED is the memory active indicator (the condition shown is an OR of the three
Jnemory cycles)

•

The green LED is the Diagnostic Passed indicator (turned on when the red LED is turned off)

2.3.7
Data Ch,annel Module
The Data Channel modules are the interface between the disk and tape formatters and the HSC. The
differences between the disk and tape modules are the contents of the ROMs and one jumper. The
ROMs contain the microcode for the microprocessors.
.

2-17

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

Figure 2-9

Memory Module (HSC70)

FLOPPY DISK
CONTROLLER

PROGRAM
MEMORY
1.0 MBYTE
DYNAMIC

DATA
MEMORY
512 KBYTES
STATIC

DATA BUS

CONTROL
MEMORY
256 KBYTES + 256 KBYTES
DYNAMIC

PROGRAM MEMORY ACTIVE
DATA MEMORY ACTIVE
CONTROL MEMORY ACTIVE

~_ _

J--g_

RED LED
YELLOW LED
GREEN LED
CX-l090A

2-18

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

There are two types of data channel modules:
Disk Data Channel-LOI08-YA-HSC5X-BA-K.sdi
Tape Data Channel-LOI08-YB-HSC5X-CA-K.sti
The Data Channel modules are in the following slots on the backplane:
4, 6, 7, 8, 9, or 10 for the HSC50
3, 4, 5, 6, 7, 8, 9, or 10 for the HSC70
The Data Channel uses the following interfaces (Figure 2-10):
•

The Control Memory Bus is the interface to the Control Memory.

•

The Data Memory Bus is the interface to the Data Memory.

•

The IN IT from the P.ioclP.ioj initializes the Data Channel module. When the P.ioclP.ioj asserts
the INIT signaC the Data Channel is held in a cleared state. When the P .ioclP .ioj negates the
INIT signaC the Data Channel starts its self-test, and the result of the test is put into a Status
Register on the Data Channel. This register is then enabled onto the Status Bus when the
P.ioclP.ioj asserts STATUS ENABLE.

Figure 2-10

Data Channel Module

SDI/STI PORT 0
SDI/STI PORT 1
SDI/STI PORT 2
SDI/STI PORT 3

INIT FROM
P. ioc/P. ioj
STATUS ENABLE
FROM P. ioc/P.ioj

STATUS BUS

o
o

RED LED
GREEN LED
CX-341B

2-19

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

•

The STATUS ENABLE from the P.ioC/P.ioj enables the data channel status onto the Status Bus.

•

The Status Bus is the interface to the P.ioC/P.ioj for the Data Channel status.

•

The SDIISTI PORT is the interface to the disk drives or tape formatters. Each Data Channel
has four ports. However, the data channel only transfers data on one port at a time, but it can
be doing other operations on the other three ports (for example, a seek).

The HSC has a priority scheme between the Data Channels, K.pli, and P.ioc for Control and Data
Memory access. The slot the module is in determines its priority. The Module Utilization Label (located
above the modules) shows the requestor priority on the Control and Data Buses.
Figure 2-11 is an example of the Module Utilization Label on an HSC50. Notice that the priority is
shown in the row Req. (The lowest priority is zero.) The P.ioc is priority zero (RO). The Data Channel
Module in slot four is priority seven (R7). The R in R7 is another way of expressing the word requestor.
You should read R7 as requestor 7.

Figure 2-11

HSCSO Module Utilization Label Example

>-I
Mod

Req
Slot

~
co

14 13

c
c
co
..c:

o
o
I

co
~

o~>~
Q).-

~>~
o
Q).-

.....IC::O

Bkhd

c
c
co
..c:

.....IC::O

12 11

10 9

c
0

.....Ill:::::"

+-'

o .. u
06;0

B
1

a:
e

CX-283A

Figure 2-12 is an example of the Module Utilization Label on an HSC70. Notice that the priority is
shown in the row Req. The P. ioj is priority zero (RO). The Data Channel Module in slot four is priority
eight (RS).

2-20

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

Figure 2-·12

HSC70 Module Utilbmtion Label Example

....

..c
00

Mod
Bkhd

Req
Slot

114 13 12 11

!9 >-I

..c

co
..c

c
co
..c

••

0 0co .. 0

.....

0..

(1)

..... >0..

..c

co
0

>-I

!9co

(1)

c
c

>-I

u
!9

co
Oco

u
!9
co
0

~;;~
0(1)·-le:o

~;;~ ~ (1)._
;; ~
0(1)·- 0
-le:O-le:o

c
c:

>-I

!9co >I

Ii:

«
«I
co

~;;~ o (1).::::
0(1)·-le:o -le:o
~

(1)

c
c
co
..c

~
0

r--..

;; ~ ....... E

ifi

+-'

....... U

;; ifio

o (1) co
-le:I-

-le:I-

10 9

0(1)

;;

(1)

-le:~

eX-889A

During write and read operations, the K.sdi checks the error detection code (EDC) and generates or
checks the error correction code (ECC). On a write operation, the K.sdi checks the EDC on each block
of data it processes. It generates the ECC and appends it to each block (after the EDC) as it leaves the
K.sdi on its way to the disk. On a read operation, the K.sdi checks EDC on each block of data from the
disk then checks and strips the ECC. If there is an ECe error, the Disk Data Channel and the P.ioclP.ioj
make the correction.
The K.sti does not generate ECC, and it uses a different scheme for EDC. Because tape formatters do
not use EeC, no ECC is generated by the K.sti. The K.sti does not write EDC with each record, but it
generates an EDC for each 512 bytes during a write operation. The tape formatter generates and sends
an EDC every 512 bytes on a read operation.
NOTE
The EDC sent to a tape formatter is never written
on the tape media. The tape formatter strips off the
EDC before sending the data to the tape drive. The
tape formatter appends the EDC to the data before
sending it to the HSC.
Figure 2-10 shows the two LEDs on the Data Channel Module. The following describes the function of
the LEOs:
•

The red LED is the Diagnostic/Testing Fail indicator (turned on when the P.ioC/P.ioj initializes
the K.sdi/K.sti and turned off after the K.sdi/K.sti passes its diagnostics)

•

The green LED is the Diagnostic Passed indicator (turned on when the red LED is turned off)

2-21

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

2.3.8
Host Interface
The modules in slots 12, 13, and 14 of the HSC are the Host Interface (Figure 2-13). They are the:

•

Port Processor Module (K.pli)
Port Buffer Module (PILA)
Port Link Module (LINK)

Figure 2-13

Host Interface

,------------------,I
HOST INTERFACE

I
I
PLI

t..

CONTROL BUS

DATA BUS

PORT
PROCESSOR

PORT
BUFFER

,
III

t..

PORT
LINK

)

CI
BUS
A

CI
BUS

- - - - - - - - --- I-

___ -.J

.Ir

CX-949A

These three modules are the interface between the CI and the rest of the HSC. The modules have their
own interface:
•

The Port/Link Interface (PLI) is the data transfer path between the K. pH and PILA and is the
control path for the PI LA and LINK. The K. pli controls the PILA and LINK in a master slave
relationship.

•

The Interprocessor Link Interface (ILl) is the data path between the PI LA and LINK.

2-22

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

2.3.9
Port Processor Module (K.pli)
The Port Processor Module (K.pli) provides the intelligence for the host interface modules. Also, this
module is the interface between the K.ci and the rest of the HSC through the Control Bus, the Data
Bus, and the Status Bus. This module is an L0107 hex height module and is in slot 12.
The K,pli uses the following interfaces (Figure 2-14):
•

The PLI is the interface between the modules in the K.ci.

•

The Control Memory Bus is the interface to the Control Memory.

•

The Data Memory Bus is the interface to the Data Memory.

•

The INIT is how the P .ioc!P .ioj initializes the K. plio When the P .ioc!P .ioj asserts the INIT signal,
the K.pli is held in a cleared state. When the P.ioc!P.ioj negates the IN IT signal, the K.pli starts
its self-test and the result of the test is put into a Status Register on the K. plio This register is
then enabled onto the Status Bus when the P.ioc!P.ioj asserts STATUS ENABLE.

•

The STATUS ENABLE frOin the P.ioc!P.ioj enables the K.pli status onto the Status Bus.

•

The Status Bus is the interface to the P.ioclP.ioj for the K.pli status.

•

The HOST INIT signal initializes the P.ioc!P.ioj causing it to reboot. A host sending a reset
causes the K. pli to generate the HOST INIT signal.

The K,pli has three LEDs that help you troubleshoot the HSC. Figure 2-14 shows the location of the
LEDs. The following describes the function of the LEDs:
•

The red LED is the Diagnostic/Testing Fail indicator (turned on when the P.ioc!P.ioj initializes
the K.pli and turned off after the K.pli passes its diagnostics)

•

The yellow LED indicates that the P.ioc!P.ioj is asserting INIT (only on some early the C-rev
etch modules)

•

The green LED is the Diagnostic Passed indicator (turned on when the red LED is turned off)

2.3.10
Port lBuffer Module (PI LA)
The Port Buffer Module (PILA) provides buffering for data and message packets. There are two 1-Kbyte
buffers for transmit packets and two 1-Kbyte buffers for receive packets. The PILA communicates with
the LINK via the ILl and with both the LINK and K.pli via the PLI. This L0109 hex height module is in
slot 13.
The PILA has no self-test, but the K.pli tests it and lights the LEDs. Figure 2-15 shows the three LEDs
on the PILA. The following describes the function of the .LEDs:
•

The top yellow LED is a test point indicator. This LED is only found on some early E-rev etch
modules.

•

The red LED is the Diagnostic!Testing Fail indicator. The K.pli controls this indicator.

•

The green LED is the Diagnostic Passed indicator. The K.pli turns this LED on when it turns
the red LED off.

2-23

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

Figure 2-14

Port Processor Module (K.pli)

INIT FROM
P. ioe/P. ioj

STATUS ENABLE
FROM P.ioc/P.ioj

PLI

STATUS BUS

o
o

TO P. ioe

HOST INIT TO
P. ioe/P. ioj
RED LED
GREEN LED

CX-342B

2.3.11
Port Link Module (LINK)
The Port Link Module (LINK) is the same module used in many of the products that interface to a CI.
It performs the following functions:
•

Interfaces to the dual-path CI bus

•

Contains CI arbitration logic

•

Contains the node address switches

•

Generates/checks CI packet CRC

•

Interfaces to the ILl and PLI buses

This L0100 hex height module is in slot 14.
This module has no self-test, but the K.pli tests it. Figure 2-16 shows the two LEDs on the LINK. The
following describes the function of the LEOs:

2-24

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

Figure 2-15

Port Buffer Module (PILA)

TRANS
BUFF
A

III

TRANS
BUFF
B

PLI
TO/FROM K.pli

TO/FROM LINK
PLI

o:J
o:J
!UFF

TO/FROM LINK

~UFF

0
0

RED LED
GREEN LED
CX·343B

•

The red LED is the maintenance loop indicator. When the K. pli enables the loop back in the
LINK, it lights this LED.

•

The green LED is the local activity indicator. It lights when there is an incoming or outgoing
packet.

2.3.12
Backplane
The backplane is a 14-slot, 4-layer, pressed pin arrangement that provides pinning for L series modules.
It provides power for the modules and signal buses. The power voltages are:

+ 12 volts
+5 volts
-5.2 volts
The following describes the buses on the backplane:
•

The Program Bus is the interface between Program Memory and the P .ioclP .ioj. (The K.rx in
the HSC70 also uses this bus.)

2-25

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

Figure 2-16

Port Link Module (LINK)

D
D

NODE

III
SWITCHES

TO/FROM
PILA BUFFER

CI A REC
CI A TRANS

PLI

CI B REC

TO/FROM K.pli
AND PI LA BUFFER

CI B TRANS

o
o

GREEN LED
RED LED

CX-344B

•

The Data Bus is the interface between Data Memory and the following modules:
P .ioclP .ioj
K.pli
K.sdi
K.sti

•

The Control Bus is the interface between Control Memory and the following modules:
P .ioclP .ioj
K.pli
K.sdi
K.sti

•

The Status Bus is the interface between the P .ioc/P .ioj and the Status Bus Register of following
modules:
K.pli
K.sdi
K.sti

•

The STATUS ENABLE signals enable the status of the Ks onto the Status Bus.

2-26

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

•

The INIT signals initialize the Ks when assE~rted.

•

The HOST INIT signal initializes the P .ioclP .ioj.

•

The ILL Bus is the interface between the LINK and the PILA.

•

The PLI bus is the interface between the LINK, PILA, and K.pli.

There are four coax cables from the rear bulkhead CI connectors to the backplane pins for the LINK.
There are four SDI/STI port cables, in a harness, from the rear bulkhead for each of the:
Six Data Channel slots (HSCSO)
Eight Data Channel slots (HSC70)
HSC50 Backplane Jacks
2.3.12.1
Figure 2,-17 shows the location of the jacks on the back of the HSCSO backplane. The following describes
the purpose of each jack:
•

Jl1 goes to the following units:
Console Terminal
Operator Control Panel
TUS8 tape drives

•

J12 has the following wires from the main power supply:

+ 12.0 volts
+ 12.0 volts, + S.O volts, and -S.2 volts sense wires
POWER FAIL signal
•

J13 has the following wires from the auxiliary power supply:

+ S volt sense wire
POWER FAIL signal
2.3.12.2
HSC70 Backplane Jacks
Figure 2-18 shows the location of the jacks on the back of the HSC70 backplane. The following describes
the purpose of each jack:
•

J11 goes to the console terminal

•

J12 goes to the Operator Control Panel

•

J13 has the following wires from the two power supplies:

+ 12.0 volts
+ 12.0 volts, + S.O volts, and -S.2 volts sense wires
POWER FAIL signals
•

J18 goes to the floppy disk drives

2-27

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

Figure 2-17

HSC50 Backplane

I~I
I~I

:@:
:@:
:®:

:@:
:@:

:@:

I@I
I
I

I@I

I@I
I
I

:@:

I@I
I
I

I@I
. I
I

i@:

I
J 11
J12

01111111111111111111110 tTllllllllll J13

o
CX-1084A

2-28

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

Figure 2-1.8

HSC70 Backplane

I,?,I
I~I

I~I
I~I

I@
I@I
1
1

I@I
1\311

I@I

I@I
1

J'I2

J 14

@
J15

@
J16

J11

[!ttWD¥1 13

J17

c'--------------~~~======~~~--------------~
o
0
CX-1091A

2-29

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

2.3.13
Operator Control Panel
The P.ioclP.ioj reads the switches and controls the indicators on the Operator Control Panel (OCP).
Figure 2-19 shows how the P.ioclP.ioj controls the indicators on the OCP. Figure 2-20 shows how the
pjoc controls the indicators on the OCP. Figure 2-21 shows how the P.ioj controls the indicators on
the OCP. For information on the function of each switch and indicator, refer to the HSC User Guide or
HSC70 Service Manual.
The switches go to the following logic:
•

•

The INIT and SECURE/ENABLE switch go to the following logic:
•

F-11 or J-ll to start the booting process

•

Terminal UARTs to do a terminalloopback

•

Control and Status Register (PIa CSR) for position of SECURE/ENABLE switch

The rest of the switches are read into the Switch and Display Register (SWDR) where the
software can act upon them

The indicators are controlled by the logic on the P .ioclP .ioj. The Voltage Monitor Circuit controls the
POWER indicator. If all voltages are within tolerance, the POWER indicator is lit. Notice in Figure 2-21
that the POWER FAIL signal also controls the POWER indicator. When asserted, the POWER FAIL signal
turns off the POWER indicator. The software controls the other indicators through the following logic:
•

Control and Status Register (PIa CSR) for the ST ATE indicator

•

Switch Display Register (SWDR) for the other of the indicators

2-30

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

Figure 2-19

Operator Control Panel Switches
OCP
INIT

P.ioc/P.ioj
S/E

:£
I

-..

LOOPBACK
.. TERMINAL

BYPASSI NG UART
PIO CSR

LED

FAULT

INIT P.ioc/P.ioj

=-1 TERM ENABLE I

4'--.l~

...- LAMP TEST
+V

SWDR
SW4

..-

ONLINE

X -

..-

-...

4'--.1...

-==
-

SW3

SW2
SW1

SWO

CX-345B

2··31

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

Figure 2-20

HSCSO Operator Control Panel Indicators
OCP

P.ioc

+ 12

+5
- 5.2

VOLTAGE
MONITOR
CIRCUIT

POWER

PIO CSR
STATE

LED

SWDR
LAMP 4

INIT

LAMP 3

FAULT

LAMP 2

ONLINE

LAMP 1

LAMP 0

LAMP TEST FROM
FAULT SWITCH

STATE

eX-346B

2-32

HSC50 AND HSC70 BLOCK DIAGRAM OVERVIEW

Figure 2-21

HSC70 Operator Control Panel Indicators
OCP

P.ioj

+ 12
+5
- 5.2

VOLTAGE
MONITOR
CI RCUIT
POWER

POWER FAI L
PIO CSR
LED

STATE

SWDR
LAMP 4

INIT

LAMP 3

FAULT

LAMP 2

ONLINE

LAMP 1

LAMP 0

LAMP TEST FROM
FAULT SWITCH

STATE
CX-1092A

2-33

BACKPLANE BUSES AND CONTROL SIGNALS

CHAPTER 3
BACKPLANE BUSES AND CONTROL SIGNALS

3.1 INTRODUCTION
This chapter describes the buses and other control signals physically located on the backplane of the
HSC. All backplane signals are described with the following exceptions:
•

The Floppy Disk Controller (K.rx) signals on connector C even numbered pins 6 through 38
are discussed in Chapter 11.

•

The host interface (K.ci) signals on the Band C connectors of slots 13 and 14 and the C
connector of slot 12 are discussed in Chapters 5, 6, and 7.

•

The console terminal and Operator Control Panel (OCP) signals on the odd numbered pins of
connector C in slot 1 are discussed in Chapter 8 and 9.

Descriptions and timing diagrams for the Program Bus, Control Bus, and Data Bus are presented in this
chapter. The other miscellaneous control signals discussed are:

•
•
•
•
•
•
•

•

S ENABLE i L
STATUS <7:0> L
CLK A Hand CLK B H
CLK CTL H
CLEAR x H
HOST CLR
SLOW CYCLE
Control and Data BASE IN and BASE OUT lines

3.2

HSC50/70 BUS DIFFERENCES
The buses on the backplanes of the HSC50 and HSC70 are functionally identical but differ in some
signal names and in implementation of the arbitration logic. Table 3-1 lists each backplane signal name
that has a different name on the HSC50 than on the HSC70. The arbitration for buses on the HSC50 is
covered in Chapter 8 and for the HSC70 in Chapter 9 since the arbitrators are located on the P.ioC/P.ioj
modulE!.

NOTE
The descriptions in this chapter are for both HSCs.
Where the HSC50 signals differ from the HSC70 signals, a note will follow that description.

3-1

BACKPLANE BUSES AND CONTROL SIGNALS

Table 3-1

HSCSO/70 Signal Differences
Slotl 8ackp lane

HSCSO Signal Name

HSC70 Signal Name

Pin Number

CGRANT 0 L

CGRANT 9 L

B381

CGRANT L

CGRANT 8 L

B36

CREFR CLK L

SLOW CYCLE L

B86

CREFR REQ L

SPARE 5

B87

CREQ 0 L

CREQ 9 L

B37

CREQUEST L

CREQ 8 L

B35

OGRANT 0 L

OGRANT 9 L

A52

OGRANT L

OGRANT 8 L

A50

OREQ 0 L

OREQ 9 L

A5l

OREQUEST L

OREQ 8 L

A49

PBASE OUT 0 L

BIRQ 4 L

lC76

PBASE OUT 1 L

BIAK L

lC78

PBASE OUT 2 L

BOMR L

lC80

PBASE OUT 3 L

BOMGO L

lC82

PBASE OUT 4 L

BSACK L

lC84

PBASE OUT 5 L

SPARE 3

lC86

PENA L

SPARE 4

lC88

PBASE IN 0 L

BIRQ 4 L

2C75

PBASE IN 1 L

BIAK L

2C77

PBASE IN 2 L

BOMR L

2C79

PBASE IN 3 L

BOMGO L

2C8l

PBASE IN 4 L

BSACK L

2C83

PBASE IN 5 L

SPARE 3

2C85

S ENABLE 0 L

S ENABLE 9 L

B77

S ENABLE i L

S ENABLE 8 L

B76

SINGLE STEP L

TEST BOOTSTRAP L

COS

1 Where slot numbers are not specified before a pin number, the signal is on multiple slots and the number given is for tht!
P.ioc/P.ioj slot.

3-2

BACKPLANE BUSES AND CONTROL SIGNALS

Table 3-1 (Cont.)

HSCSO/70 Signal Differences

HSC50 Signal Name

HSC70 Signal Name

Slot/Backplane
Pin Number

SWAP MEM BANK H

SWAP PMEM BANK H

C70

SWAP MEM BOARD H

SWAP CMEM BANK H

C68

Tl PRESENT +

A UXI PRESENT +

lC35

Tl RCV +

AUXI RCV +

lC43

Tl RCV-

AUXI RCV-

lC41

'II XMTR OUT +

AUXI XMT +

lC37

Tl XMTR OUT-

AUXI XMT-

lC39

T2 PRESENT +

AUX2 PRESENT +

lC45

T2 RCV +

AUX2 RCV +

lC43

T2 RCV-

AUX2 RCV-

lC41

T2 XMTR OUT +

AUX2 XMT +

lC37

T2 XMTR OUT-

AUX2 XMT-

lC39

FLOPPY SPARE

2C6

IN USE L

2C8

DRV SEL 3 L

2CI0

INDEX L

2C12

DRV SEL 0 L

2C14

DRV SEL 1 L

2C16

DRV SEL 2 L

2C18

MOTOR ENB L

2C20

DIR SEL L

2C22

STEP L

2C24

WRDATA L

2C26

WR GATE L

2C28

TRACK 0 L

2C30

3-3

BACKPLANE BUSES AND CONTROL SIGNALS

Table 3-1 (Cont.)

HSCSO/70 Signal Differences

HSCSO Signal Name

HSC70 Signal Name

Slot/Backplane
Pin Number

WR PROT L

2C32

RD DATA L

2C34

SIDE SEL L

2C36

READY L

2C38

3.3 PROGRAM BUS
This section describes the Program Bus and the timing for its various cycles. The Program Bus is an
asynchronous bus etched on the backplane between slots 1 and 2 on conne~tor C.
Timing on the Program Bus for the HSCSO is about 10% faster than the Q-Bus implementation on the
KDF11-A because some of the deskewing delays have been shortened. Timing on the Progranl Bus for
the HSC70 is identical to the Q-Bus implementation on the KDJ11-A.
The Program Bus is a subset of the Q22 Bus, with several signals added. The Q22 Bus is a Q-Bus expanded to 22 addressing bits. In this chapter, where Program Bus differs from the Q-Bus, the differences
will be pointed out.
NOTE

You cannot plug a Q-Bus option into the backplane
of an HSC.
The Program Bus has 22 bits of addressing and a 16 bit data word. The address and data are multiplexed
over the same lines during different times in the bus cycle. There are no parity lines for the address.
The data lines have byte parity which is transnlitted on lines 16 and 17 of the address/data lines during
the data portion of the cycle.
The F-11/J-11s use the Program Bus to gain access to the following logic and buses:
•

Program Memory (M. prog)

•

Floppy Disk Controller (K.rx) (HSC70 only)

•

Control Memory (through Control Bus cycles)

•

Data Memory (through Data Bus cycles)

•

Control Memory Windows

•

Console terminal

•

Auxiliary asynchronous ports (used for TUS8 on HSC50)

•

Bootstrap proms

3-4

BACKPLANE BUSES AND CONTROL SIGNALS

•

I/O page system registers which include:
•

PIOCSR

•

Switch/Display register

•

K Init and Status registers

•

Error Address registers'

•

Serial Number register
NOTE
You may want to refer to the block diagrams in
Chapters 8 and 9 to see how the F-ll and J-ll use
the Program Bus.

However, the only devices directly on the Program Bus are the F-Il1J-ll, Program Memory, and K.rx.
The data and address signals for the other devices and registers are interfaced to the Program Bus through
the INlBUS and OUTBUS drivers. On the HSC70 another set of transceivers, the BIBUS XCEIVERS,
interface the serial ports and bootstrap proms to the data lines of the Program Bus.
The F-Il1J-ll initiates a normal memory cycle on the Program Bus when addressing Control or Data
Memories, but a separate bus cycle is performed on the Control or Data Bus within the Program Bus cycle.
The exltra bus cycle is transparent to the P.ioc/P.ioj.
The K.rx uses the Program Bus to access Program Memory using direct menl0ry access (DMA).
NOTE
This chapter covers only the activity on the Program
Bus. For details about the P.ioclP.ioj registers and
interfaces see Chapters 8 and 9.
3.3.1
Program Bus Master-Slave Relationship
Communication on the Program Bus is asynchronous but remains interlocked because of the masterslave rdationship. The bus master has control of the bus. Only the P.ioC/P.ioj or K.rx may become bus
master, but any device on the Program Bus may become slave.
.
The bus master initiates bus transactions, and the slave device responds by using bus protocol to
acknowledge the transaction, receive data, or transmit data. Communication on the Progranl Bus is
interlocked because the slave device must respond to the control signals issued by the bus master
before the transfer is complete.
If comlnunications on the Program Bus break down because the slave does not respond to the bus

master, the master aborts the current bus cycle and traps to 0048 as a NXM error.
HSC50/70 Program Bus Differences
3.3.2
The HSC50/70 Program Buses have the following differences:
•

The HSC70 bus has DMA capabilities; the HSC50 does not.

•

The HSC50 and the HSC70 have the ability to swap banks for the Program Memory, but only
the HSC70 can swap banks in Control Memory (M.ctl). The HSC50 also has circuitry to swap
memory slots in the event that two memory boards are used ..

•

The HSC50 has PBASE OUT and PBASE IN signals which could be used for multiple memory
boards. The HSC70 does not have the multiple memory module capability on the Program
Bus.

3-5

BACKPLANE BUSES AND CONTROL SIGNALS

NOTE
There are no configurations of the HSC with multiple memory boards. The multiple memory board
feature is described here for informational purposes
only.
Program Bus Signals
3.3.3
Table 3-2 summarizes the Program Bus signals on the HSC50/70.

Table 3-2

Program Bus Signal Names

Quantity

Function

Bus Signal Mnemonic

Data/address lines

BDAL < 15:00 >

Parity/address lines

BDAL < 17:16>

Address lines

BDAL <21:18>

Bus control lines

BSYNC
BDIN
BWTBT
BBS7
BRPLY

DMA control lines

BDMR*
BDMGO*
BSACK*

Interrupt control lines

BIRQ 4*
BIAK*

Processor control lines

BPOK
BDCOK
BINIT
PREFR CLK

Memory bank control lines

SWAP CMEM BANK*
SWAP PMEM BANK*
SWAP MEM BANK**
SWAP MEM BOARD**

Memory board base address

PBASE OUT <5:0>**
PBASE IN <5:0>**
PENA OUT**

* HSC70 only
** HSC50 only

Table 3-3 describes the signals on the Program Bus which are identical to their counterparts on the
Q-Bus.

3-6

BACKPLANE BUSES AND CONTROL SIGNALS

Table 3-3 Program Bus Signals Which are Identical to Q-Bus Signals
Signal Mn4~monic

Signal Function

BOAL < 15;:00> L

Address lines for first part of bus cycle. Oata lines for second part of cycle.

BOAL < 21:18 > L

Address lines 18 through 21.

BRPLY L

Slave devices assert BRPLY L in response to BOIN L or BOOUT Land
(for non I/O page references) valid parity on BOAL < 17:00 > L, indicating
their ability to transfer data according to the appropriate protocol. BRPLY
L is also asserted during interrupt acknowledge (IAK) transactions.

BSYNC L

Synchronize - The bus master device asserts BSYNC L, indicating it has
placed an address on the bus. The transfer is in process until the master
negates BSYNC L.

BOOUT L

Data output - BOOUT, when asserted, implies that valid data is available
on BOAL < 15:00> L, and that an output transfer, with respect to the bus
master device, is taking place.

BOIN L

Data input - Used for two types of bus operations. When asserted during
BSYNC L time, BOIN L implies an input transfer with respect to the current bus master and requires a response, BRPL Y L, from the addressed
slave. Also, on the HSC70 the J-ll initiates interrupt service for the K.rx
by asserting BOIN L followed by BlACK L.

BWTBT L

Write/Byte - BWTBT L is used in two ways to control a bus cycle. It is
asserted during the address portion of a cycle to indicate that an output
cycle rather than an input cycle is to follow. It is asserted during the Oata
portion of a write cycle to indicate a byte rather than a word transfer is to
take place.

BBS7 L

Bank 7 select - When the bus master asserts an address, it asserts this
signal to reference the I/O page. The I/O page address is placed on BOAL
<12:00> L and the address bits fronl BOAL <21:13> are ignored.

BINIT L

Initialize - This signal provides a system reset. All devices on the bus
are to return to a known, initial state. Registers are reset to zero, all bus
drivers are disabled, and logic is reset to state 0, ready to be addressed
for operations.

BIRQ 4 L*

Interrupt request priority level 4 is used by the K.rx to interrupt the J-l1.

BIAK L*

Asserted by the J-ll to acknowledge an interrupt from K.rx.

BOMR L*

Direct Memory Access (DMA) request - The K.rx asserts this signal to
request bus mastership.

3-7

BACKPLANE BUSES AND CONTROL SIGNALS

Table 3-3 (Cont.)

Program Bus Signals Which are Identical to Q-Bus Signals

Signal Mnemonic

Signal Function

BDMGO L*

Direct memory access grant - The J-11 asserts this signal to grant bus nlastership to the K.rx in response to BDMR L. The K.rx acknowledges the
grant by asserting BSACK L after BRPL Y Land BSYNC L are both negated.

BSACK L*

The K.rx asserts this signal in response to the BDMGO L signal indicating
it accepts bus mastership. The K.rx remains bus master until it negates
BSACK L.

* HSC70 only
Table 3-4 describes those signals that differ from their counterparts in the Q-Bus.

Table 3-4

Program Bus Signals Which Differ From Q-Bus Signals

Signal Name

Description

PREFR CLK L

66.7 KHz clock (15.0 microsecond period) is used by the Program Menlory for timing Refresh Cycles. To simplify the design of the Memory
Module, logic is provided on the P.ioclP.ioj to eliminate any synchronization problems between this signal and BSYNC L at the Memory
Module.

BDCOK H

Consists of three elements. The first is a wakeup circuit which keeps
the P.ioclP.ioj initialized until the + 5.0 volt power is stabilized. The
second is a dc voltage monitor circuit which checks for the existence
of + 5.0 volts, -5.2 volts, and + 12.0 volts. If any voltage is missing,
the P .ioclP .ioj is held in the initialize state. When these two circuits are
satisfied, the P.ioclP.ioj is enabled and the Power lamp on the Operator
Control Panel is turned on. The third component is a receiver input for
the INIT switch on the Operator Control Panel; depressing this switch
will initialize the P .ioclP .ioj.

BDAL < 17:16> L

During the data portion of a bus cycle, BDAL 17 contains the actual odd
parity bit for BDAL < 15:08> and BDAL 16 contains the odd parity bit
for < 07:00 >. Parity on the Program Memory Bus is not encoded as on
the Q-Bus. The parity bits are generated and received by the P.ioclP.ioj
or K.rx.

SWAP CMEM BANK H*

Used by the HSC70 Control Memory to select which half of the Control
Memory DRAMs is used.

SWAP PMEM BANK H*

U sed by the HSC70 Program Memory to swap the base address of its
two banks.

SWAP MEM BOARD H**

Unused. This signal would have caused the first two Memory Boards
in the HSC to swap base addresses if multiple Memory Modules had
been used.

3-8

BACKPLANE BUSES AND CONTROL SIGNALS

Table 31-4 (Cont.)

Program Bus Signals Which Differ From Q-Bus Signals

Signal Name

Description

SWAP MEM BANK H**

Causes Program Memory .to swap the base address of its two banks of
Program Memory.

PBASE OUT <5:0>**

Asserted high on P.ioc. These signals were in the original design for
more then one memory module. The PBASE OUT signals on the P joc
become the PBASE IN signals to the Memory Module. The PBASE IN
signals go through a base memory adder circuit on the M'emory Module
and then become PBASE OUT.

PBASE IN <5:0>**

Refer to PBASE OUT signals above.

PEN A OUT**

Asserted low on P .ioc. ThIs signal was in the original design for more
then one memory module.

*Signals only in the HSC70
** Signals only in HSC50

3.3.4
Program Bus Transactions
During the protocol specifications, bus signals are referred to in different ways. The following is a list
of the conventions used:
1.

Most signals on the backplane etch are asserted low and referred to with a prefix character B
and a suffix L. For example:
•

BSYNC L, BWTBT L, BBS7 L, BDAL < 21:00 > L

•

BPOK Hand BDCOK H are asserted high

A signal name without a prefix or suffix is used when timing, polarity, and physical location
are unimportant. For example:
•

SYNC for BSYNC

WTBT for BWBT

•

DAL <21:00> or the OAL lines for BOAL <21:00>

Receivers and drivers are considered part of the bus. Signal inputs to drivers are referred to
with a prefix character T for transmit. For example:
•

TSYNC

•

TWTBT

•

TOAL <21:00>

Signal outputs of receivers are referred to with the prefix character R for received. For example:
•

RSYNC

•

RWTBT

•

ROAL<21:00>

Program Memory signals feeding the receivers and drivers are labeled with a prefix character
PM in the print sets. The prefix character R is used in this book.

3··9

BACKPLANE BUSES AND CONTROL SIGNALS

If a reference is made to a Control or Data Bus address, a cycle will be requested, arbitrated,
and perfornled on the respective bus. The timing diagrams do not take the other bus cycles
into account. See Sections 3.5.2 and 3.6.2 for cycle information on the Control and Data Buse:s
that occur within the Program Bus cycles.

The conventions listed in items 3, 4, and 5 above are used when timing is important. The timing is
referenced to a receiver output or a driver input. For example:
After receipt of the negation of RDIN, the slave negates its TRPLY (0 nanoseconds minimum, 8000 nanoseconds maximum). It must maintain valid data on its TDAL lines until
o nanoseconds (minimum) after the negation of RDIN, and must negate its TDAL lines
100 nanoseconds (maximum) after the negation of its TRPLY.
3.3.4.1
Program Bus Interrupt Protocol (HSC70 Only)
The only interrupt used on the Program Bus is a level 4 interrupt generated by the K.rx. Control Bus
and asynchronous line interrupts are contained within the P .ioj logic and do not use the BIRQ lines on
the Program Bus.
The K.rx interrupts the P.ioj for service when it has completed work, is ready, or has an error. When the
J-I1 acknowledges the interrupt, the K.rx supplies an interrupt vector address (2308 ) that the J-11 uses
to retrieve a new processor status word (PSW) and a new program counter value (PC). The old PSW and
PC are stored on the stack while the J-11 services the interrupt.
Interrupt protocol on the Program Bus has three phases: the interrupt request phase, the interrupt
acknowledge phase, and the interrupt vector transfer phase. The operations performed by the processor
and interrupting device are shown in Figure 3-1.

3-10

BACKPLANE BUSES AND CONTROL SIGNALS

Figure 3-1

Program Bus Interrupt Request! Acknowledge Sequence

DEVICE (K.rx)
INITIATE REQUEST
• Assert BIRQ L
STROBE INTERRUPTS
• ASi3ert BDIN L
RECEIVE BDIN L
• Store "Interrupt
Sending" in device

GRANT REQUEST
• Pause and assert
BIAKO L

_______________

RECEIVE BIAKO L
• Place vector on
BDAL<15:00> L
,. Assert BRPLY L
___________ • Negate BIRQ L
RECEIVE VECTOR AND 4TERMINATE RE(~UEST
• Input vector address
• Nel~ate BDIN Land_
BIAKO L
________

~ COMPLETE VECTOR TRANSFER
• Remove vector from
BDAL bus
_________ • Nega t e BRPL Y L
PROCESS THE INTERRUPT ~
• Save interrupted program PC
and PSW on stack
• Load new PC and PSW from
vector addressed location
• Execute interrupt service
routine for the device
CXO-1160A
Interrupt protocol timing is shown in Figure 3-2. Following is a description of the timing during the
interrupt.

3-11

BACKPLANE BUSES AND CONTROL SIGNALS

Figure 3-2

Program Bus Interrupt Protocol Timing

------I MINUS
INTERRUPT LATENCY
SERVICE TIME
T IRQ

R DIN

R IAKI

T RPLY
125 ns MAXIMUM
T DAL

--I

J--

I-- 100 ns MAXIMUM

______________________________(_4_)__________________________)(~-----V~E-C-T-O-R----~)(

R SYNC

(UNASSERTED)

R BS7

(UNASSERTED)

(4)

NOTES:
1. TIMING SHOWN AT REQUESTING DEVICE BUS DRIVER INPUTS
AND BUS RECEIVER OUTPUTS.
2. SIGNAL NAME PREFIXES ARE DEFINED BELOW:
T = BUS DRIVER INPUT
R = BUS RECEIVER OUTPUT
3. BUS DRIVER OUTPUT AND BUS RECEIVER INPUT SIGNAL NAMES
INCLUDE A "B" PREFIX.
CX-517A

4. DON'T CARE CONDITION.

The interrupt request phase starts when the K.rx asserts an interrupt request TIRQ4 L. During the
interrupt acknowledge phase, the K.rx accepts the RIAKO signal on the leading edge of RDIN.
During the interrupt vector transfer phase, the K.rx asserts RRPLY. The vector address must be stable on
BDAL <08:02> 125 nanoseconds (maximum) after TRPLY is asserted. The J-ll then receives the assertion of RRPLY within 200 nanoseconds (minimum). It then inputs the vector address and negates both
TDIN and TIAKO. The K.rx negates TRPLY after the negation of RIAKI and removes the vector address
from TDAL < 08:02 > 100 nanoseconds (maximum) after TRPLY negates. Because vector addresses must
be between 0008 and 7748 , the high order TDAL lines remain inactive.

3-12

BACKPLANE BUSES AND CONTROL SIGNALS

3.3.4.2
Program Bus Mastership Protocol (HSC70 Only)
The D~IA capability allows direct data transfers between the K.rx and memory. The K.rx becomes bus
master by asserting BDMR L. The P.ioj then grants the bus to the K.rx by asserting BDMG L.
A DMA transaction is divided into three phases: the bus mastership acquisition, the data transfer, and
the bus mastership relinquish. The protocol for a DMA transaction is shown in Figure 3-3.
Figure ~~-3

Program Bus DMA Request/Grant Sequencing

PROGESSOR (J -11)

BUSMASTER (K.rx)
REQUEST BUS
• Assert BDMR L

,
GRANT BUS GONTROL. - - - - - - • Near the end of the
c:urrent bus cycle
(BRPLY L is negated),
assert BDMGO Land
inhibit new processor
generated BSYNC L for
the duration of the
DMA operation

AGKNOWLEDGE BUS
MASTERSHIP
• Receive BDMG
• Wait for negation
of BSYNC Land BRPLY L
• Assert BSACK L
Negate BDMR L
TERMINATE GRANT SEQUENCE..-------O

• Negate BDMGO L and wait
for the DMA operation to
be complE!ted
EXECUTE A DMA DATA
TRANSFER
• Address memory and
transfer data
• Release the bus by
terminating BSACK L
and BSYNC L
RE8UME PROCESSOR OPERATION'---------• Enable processor generated
BSYNC L (processor is bus
master) or issue another
grant if BDMR L is asserted
CXO-11.61A

The bus cycle tinling is shown in Figure 3-4. Following is a description of the timing when the K.rx is
requesting and releasing the Program Bus.

3-13

BACKPLANE BUSES AND CONTROL SIGNALS

Figure 3-4

Program Bus Request/Grant Bus Cycle Timing
SECOND
REQUEST
DMA LATENCY

T DMR

R DMG

T SACK

R/T SYNC

ns MINIMUM

R/T RPL Y

....1

T DAL
(ALSO BS7,
WTBT, REF)

r-0 ns MINIMUM
j4- 0 ns MINIMUM

__________________A

ADDR

100 ns MAXIMUM

X------D-A-T-A------\

NOTES:
1. TIMING SHOWN AT REQUESTING DEVICE BUS DRIVER INPUTS
AND BUS RECEIVER OUTPUTS.

2. SIGNAL NAME PREFIXES ARE DEFINED BELOW:
T = BUS DRIVER INPUT
R = BUS RECEIVER OUTPUT

3. BUS DRIVER OUTPUT AND BUS RECEIVER INPUT SIGNAL NAMES
INCLUDE A "B" PREFIX.
CX-520A

During bus acquisition, the K.rx requests the bus by asserting BDMR. The processor arbitration logic
responds with TDMG. The K.rx asserts BSACK in response. If the processor does not receive a response
to the DMA grant, it clears the grant and rearbitrates the bus.
During the data transfer phase, the K.rx keeps BSACK asserted. At the end of the data transfer, the
K.rx relinquishes the bus by negating BSACK. TSYNC is negated 300 nanoseconds (maximum) after
TSACK is negated.

3-14

BACKPLANE BUSES AND CONTROL SIGNALS

3.3.4.3
rprogram Bus Data Transfers
The current bus master initiates a data transfer by placing the slave address and appropriate control
signals on the bus. It then waits for a response from the slave before continuing with the transfer.
The Program Bus data word is 16-bits wide and is comprised of the low byte and the high byte. The low
byte is BDAL < 07:00 >, and the high byte is BDAL < 15:08>. Bits 16 and 17 supply odd parity. Bit 16
is the low byte parity bit and bit 17 is the high byte parity bit. Bits <21:18> are not active during the
data portion of a cycle.
Program Bus addressing is accomplished using the BDAL lines and the BBS7 signal. If BBS7 is asserted
during the address portion of the cycle, the bus master is addressing an I/O page address, and the
address in the I/O page is found on BDAL lines < 12:00 >. If BBS7 is not asserted, the bus master is
addressing memory, and the address is found on DAL < 21:00 >. The I/O addresses are in the top 8
Kbytes of addressing (177700008 through 177777778 ),
The Program Bus supports five of the seven types of data transfers available on the Q-Bus. Table 3-5
lists the transfer types supported on the Program Bus.

Table 3-5

Program Bus Data Transfer Types

Bus Cycle
Mnemonk

Description

Function With Respect
to Bus Master

DATI

Data word input

Read word

DATO

Data word output

Write word

DATOB

Data byte output

Write byte

DATIO

Data word input/output

Read word, modify, write word

DATIOB

Data word input/byte output

Read word, modify, write byte

The address portion of the transfer is made up of an address set-up time and an address hold time.
During the address set-up time the bus master does the following:
•

Asserts TDAL < 21:00 > with the desired slave device address bits

•

Asserts TBS7 if a device in the I/O page is being addressed

•

Asserts TWTBT if the cycle is a data out bus cycle

•

Asserts TSYNC 150 nanoseconds (minimum) after gating TDAL, TBS7 and TWTBT onto the
bus

The slave address, RBS7 and RWTBT are asserted at the slave bus receiver for at least 75 nanoseconds
before RSYNC becomes active. Devices in the I/O page ignore the 9 high order address bits RDAL
< 21:13> and instead decode RBS7 along with the 13 low order address bits. An active RWTBT signal indicates a data-out operation follows, while an inactive RWTBT indicates a data-in or DATIO(B)
operation.
The address hold time starts after RSYNC is asserted. The slave device uses the active RSYNC to clock
RDAL address bits RBS7 and RWTBT into its internal logic. RDAL <21:00>, RBS7, and RWTBT will
stay active for 25 nanoseconds (minimum) after RSYNC becomes active. TSYNC stays active for the
duration olf the bus cycle.

3-15

BACKPLANE BUSES AND CONTROL SIGNALS

The following sections describe the cycles performed on the Program Bus. All cycles use the above
addressing portion within the cycle. The addressing portion will not be repeated in the description of
the cycle.
3.3.4.4
Program Bus DATI Cycle
The DATI bus cycle is a read operation because a 16-bit data word moves from the slave to the master.
The DATI bus cycle operations are shown in Figure 3-5 in flow format.
Figure 3-5

Program Bus DATI Flow Cycle

SLAVE DEVICE
(MEMORY OR DEVICE)

BUS MASTER
(PROCESSOR OR DEVICE)
ADDRESS SLAVE DEVICE
• Assert BDAL <21:00>
with the address and
• Assert BBS7 if the
address is in the I/O
page
• Assert BSYNC L __

.. DECODE ADDRESS
• Store "DEVICE
SELECTED" operation
REQUEST DATA
• Remove the address
from BDAL <21:00> and
negate BBS7 L
• Assert BDIN L
SEND DATA
• Place data on BDAL
<15:00>
_________ • Assert BRPLY L
TERMINATE INPUT TRANSFER~
• Accept data and respond
by negating BDIN L - _ __
"OPERATION COMPLETED
• Negate BRPLY L
TERMINATE BUS CYCLE
• Negate BSYNC L
CXO-1162A
The timing diagram for a DATI Program Bus cycle is shown in Figure 3-6. Following is a description of
the timing relationships.

3-16

BACKPLANE BUSES AND CONTROL SIGNALS

Figure 3-6 Program Bus DATI Timing Cycle

TfR DAL

~ T ADDR

1'-

-.t

X. . .____---(4-)---,~
X
....II --------' . . .- - - - - - - - - - - - R DATA

kl50 ns
I
MIN I MUM--!
I

TSYNC

(4)

200 ns

MAXIMUM

-...j

r--"'----...;...,...-. .-----:::::::::::::-=--=--20-0-n-S-M-I-N-1
.
M-U-M-----~--~~~:::::::::::=

--+-----------~

100 ns MINIMUM
8 ps MAXIMUM

CLOCKDATA

200 ns MINIMUM

T DIN

1+-_'---- 300 ns MIN I MUM ---~

R RPLY

T BS7

- I;:
----;(

TWTBT

150 ns
MINIMUM

100 ns MINIMUM
(4)

(4)

TIMING AT MASTER DEVICE

RfT OAL

_(_4)_ _ _

R ADDR==X

-IX'-___

____
(4_)_ _ _

~MINIMUM
25 ns

T_DA_T_A
___

125 ns MAXIMUM

~X
(4)
1'100 ns MAXIMUM
j+- a ns MINIMUM

R SYNC

R DIN

T RPLY

R BS7

RWTBT

(4)

~....._____~!C~

_(_4)____

_______________

(_4)________________________

TIMING AT SLAVE DEVICE
NOTES:
1. TIMING SHOWN AT MASTER AND SLAVE DEVICE
BUS DRIVER INPUTS AND BUS RECEIVER OUTPUTS.
2. SIGNAL NAME PREFIXES ARE DEFINED BELOW:
T = BUS DRIVER INPUT
R = BUS RECEIVER OUTPUT

3. BUS DRIVER OUTPUT AND BUS RECEIVER INPUT
SIGNAL NAMES INCLUDE A "B" PREFIX.

4. DON'T CARE CONDITION.

CX-521A

3-17

BACKPLANE BUSES AND CONTROL SIGNALS

During a DATI operation, the master:
•

Gates the slave address to the bus and negates TWTBT.

•

Asserts TSYNC 150 nanoseconds (minimum) after the slave address is gated.

•

Asserts TDIN 100 nanoseconds (minimum) after the assertion of TSYNC.

When the slave receives DIN it:
•

Asserts TRPL Y after RDIN. A bus timeout occurs if TRPL Y is not asserted within 8000 nanoseconds.

•

Gates TDATA onto the bus 125 nanoseconds (maximum) after TRPLY.

In response to the reply signal from the slave, the master:
•

Has valid RDATA 200 nanoseconds (maximum) after RRPLY.

•

Negates TDIN 200 nanoseconds (n1inimum) after RRPLY.

After receiving the negation of the data in signal, the slave:
•

Negates TRPLY after RDIN is negated.

•

Negates TDATA 100 nanoseconds (maximum) after it negates TRPLY.

To complete the transfer, the master:
•

Negates TSYNC after RRPLY is negated.

Program Bus DATa and DATOB Cycle
3.3.4.5
The DATO(B) bus cycle is a write operation because a 16-bit data word for DATO or 8-bit data byte for
DATOB moves from the master to the slave.
Figure 3-7 gives the flow for a DATO(B) cycle.

3-18

BACKPLANE BUSES AND CONTROL SIGNALS

Figure 3-7

Program Bus DATO or DATOB Flow Cycle

BUS MASTER
OR DEVICE)
ADDRESS SLAVE DEVICE
• Assert BDAL <21:00>
with the address and
• Assert BBS1 if the
address is in the I/O
page
• Assert BWTBT L (Write
cycle)
• ASl3ert BSYNC L

SLAVE DEVICE
(MEMORY OR DEVICE)

~PROCESSOR

--------------- DECODE ADDRESS
• Store "DEVICE
.SELECTED" operation
REQUEST DATA
• Remove the address
from BDAL <21:00> and
negate BBS" L
• Negate BWTBT L (leave asserted if
this is a DATOB)
• Place data on BDAL <15:00>
• ASl3ert BDOUT L _ _

~-----"''''''TAKE DATA

• Receive data from
the BDAL lines
_________ • Assert BRPLY L
TERMINATE OUTPUT TRANSFER'----• Remove data from the
BDAL lines
• Nel~ate BDOUT L ________

~OPERATION COMPLETED
_________ • Negate BRPLY L

TERMINATE BUS CYCLE ...-----• Nel~ate BSYNC L

..
CXO-1163A

Figure 3-8 shows the timing diagram for the DATO(B) cycle. Following is a description of the timing
relationships.

3-19

BACKPLANE BUSES AND CONTROL SIGNALS

Figure 3-8

T DAL

Program Bus DATO or DATOS Timing Cycle

xr-----T-DA-TA------1

TADDR

~,~~~~~1 r-_--!~

_ _1_0_0n_sM_I_N_IM_U_M
____

0 ns MINIMUM
(4)

_+_- -~.:.:.M:.:.I:.:.Nl.:.:.;I~:.:.;oU~n~

TSYNC

Bps ~

I r--------___\.

MAX I MUM
T DOUT

~t.....-._ _

300 ns MINIMUM

R RPLY

T BS7

(4)

TWTBT

(4)

ASSERTION = BYTE

---.I

100 ns MINIMUM

100 ns
MINIMUM

TIMING AT MASTER DEVICE

R DAL

_(_4_)_ _..J

R ADDR

R DATA

(4)

~25 ns MINIMUM

25 ns MINIMUM
R SYNC

100 ns MINIMUM-'c:150 ns MINIMUM
R DOUT

~_ _ _-I-_......l~ i300nSMINIMUM
T RPLY

R BS7

(4)

R WTBT

ASSERTION = BYTE

1==

(4)

25 ns MINIMUM

TIMING AT SLAVE DEVICE
NOTES:
1. TIMING SHOWN AT MASTER AND SLAVE DEVICE
BUS DRIVER INPUTS AND BUS RECEIVER OUTPUTS.

2. SIGNAL NAME PREFIXES ARE DEFINED BELOW:

3. BUS DRIVER OUTPUT AND BUS RECEIVER INPUT
SIGNAL NAMES INCLUDE A "B" PREFIX.

4. DON'T CARE CONDITION.

T = BUS DRIVER INPUT
R = BUS RECEIVER OUTPUT
CX-522A

3-20

BACKPLANE BUSES AND CONTROL SIGNALS

The data transfer portion of a DATO(B) is made up of a data set-up time and a data hold time.
During the data set-up time, the master:
•

Places the data on TDAL < 15:00 > 100 nanoseconds (minimum) after asserting TSYNC, and
TDAL < 17:16> supplies parity error detection.

•

Negates TWTBT 100 nanoseconds (minimum) after TSYNC is asserted. Keeps TWTBT asserted
for DATOB.

•

Asserts TDOUT 100 nanoseconds (minimum) and 8 microseconds (maximum) after the TDAL
and TWTBT lines are stable.

The slave responds to TDOUT by accepting the data and asserting TRPLY. This completes the data
set-up time.
During the data hold time the following operations occur:
•

The master receives RRPLY and negates TDOUT 150 nanoseconds (minimum) later.

•

The master keeps the TDAL lines stable for at least 100 nanoseconds after negating TDOUT.

•

The slave senses the negation of RDOUT and negates TRPLY.

•

The master negates TSYNC after RRPL Y is negated.

The DATO(B) bus cycle is now complete.
During the DATOB cycle, BWTBT is asserted and BDAL a L informs the slave to write either the upper
or lower byte. If BDAL a L is not asserted, the lower byte will be written.
Program Bus DATIO and DATIOB Cycles
3.3.4.6
The protocol for aDA TIO(B) is identical to the addressing and data transfer portions of the DATI
and DATO(B) bus cycles and is illustrated in Figure 3-9. After addressing the device, a DATI cycle is
perforrned as explained earlier; however, BSYNC L is not negated. BSYNC L remains active for an
output word or byte transfer. The bus master maintains at least 200 nanoseconds between BRPL Y L
negation during the DATI cycle and BDOUT L assertion. When the bus master negates BSYNC L, the
cycle terminates as described for DATO(B).
3.4 BUS REQUESTORS
A requestor in the HSC is defined as a module which has the necessary hardware to request the Control
or Data Bus. A requestor is anyone of the following modules:
•

I/O Control Processor (P joclP joj)

•

Port Processor Module (K. pli)

•

Disk Data Channel (K.sdi)

•

Tape Data Channel (K.sti)

There Jmay be a maximuIn of ten requestors on the HSC70 or eight requestors on the HSC50. The
requestor priorities on the Data Bus and Control Bus are determined by backplane slot location and the
priorities of a given requestor are the same on both buses. (Control Bus requestor 5 is also Data Bus
requestor 5.) Table 3-6 gives the slot and requestor number relationship.

3-21

BACKPLANE BUSES AND CONTROL SIGNALS

Figure 3-9

Program Bus DATIO or DATIOB Bus Cycle

BUS MASTER
(PROCESSOR OR DEVICE)

SLAVE DEVICE
(MEMORY OR DEVICE)

ADDRESS SLAVE DEVICE
• Assert BDAL <21:00>
with the address and
• Ass~rt BBS7 if the
address is in the I/O
page
• Assert BSYNC L_

-----

.. DECODE ADDRESS
• Store "DEVICE
......_ - - - - - - - - - - - - SELECTED" operation
REQUEST DATA ....
• Remove the address
from BDAL <21:00> and
negate BBS7 L
• Assert BDIN L _____
• SEND DATA
• Place data on BDAL <15:00>
______ • Assert BRPLY L
TERMINATE INPUT TRANSFER..-----• Accept data a respond
by negating BDIN L _ _ _ _ _
~COMPLETE INPUT TRANSFER

• Remove data
____- - - - - - - - - - - - - . Negate BRPLY L
OUTPUT DATA ....
....
• Place output data on
BDAL <15:00>
• Assert BWTBT L if an output
byte transfer
• Assert BDOUT L _____________
~TAKE DATA
• Receive data from
the BDAL lines
_______ • Assert BRPLY L

TERMINATE OUTPUT TRANSFER"-----• Remove data from the
BDAL lines
• Negate BDOUT L_____________
~OPERATION COMPLETED
__________ • Negate BRPLY L

TERMINATE BUS CYCLE~
• Negate BSYNC L
(and BWTBT L if in
a DATIOB bus cycle)
CXO-1164A

3-22

BACKPLANE BUSES AND CONTROL SIGNALS

Table 3-6

Reguestor Number Backplane Slots

Slot
Number

HSC50
Requestor

HSC70
Requestor

Requestor Type

P .ioclP .ioj

K.sdi or K.sti

3
4

5
6

K.sdi or K.sti

K.pli

All arbitration for the Control and Data Buses takes place on the P .ioclP .ioj module in slot 1. In the
HSC50, the P.ioc module gains ownership of the Control or Data Bus using the request and grant signals
on the backplane the same as other requestors. In the HSC70, the P .ioj does not use any backplane pins
to send and receive the request and grant signals to itself. Instead, the HSC70 P.ioj request and grant
signals are contained entirely within the module and the extra backplane lines are redefined as signals
for the two additional requestors.
The Memory Module is the only module on the Control and Data Buses that is not a requestor. The
Port Link Module (LINK) and Port Buffer Module (PILA) do not connect to the Control and Data Buses.
3.5 CONTROL BUS
The Control Bus is a synchronous, 6.6 Mbyte/sec (300 nanosecond cycle) bus. The P.ioclP.ioj, the K.pli,
the K.sdi, and the K.sti modules use the Control Bus to access the control structures in Control Memory.
The Control Bus deals with word addresses and has 17 significant address bits with no parity. The data
word on the Control Bus is 16 bits wide with two parity bits. For writing purposes, the data word is
divided into two 9··bit bytes.

3-23

BACKPLANE BUSES AND CONTROL SIGNALS

3.5.1
Control Bus Signals
Table 3-7 describes the Control Bus signals. All of the signals on the Control Bus, except CTIMING H,
are asserted low.

Table 3-7

Control Bus Signals

Signal

Description

CDATA <15:00> L

16 data lines

CDATA HP L

Odd parity for CDATA <15:08>

CDATA LP L

Odd parity for CDATA < 07:00 >

CADR <16:00> L

17 address lines (word address)

CWRTH L

Write enable line for CDATA <15:08,HP>

CWRTL L

Write enable line for CDATA <07:00,LP>

CREQ x L

1 request line per requestor

CGRANT x L

1 grant line per requestor

CACK L

Positive acknowledge from memory

CTIMING H

Timing for clocking data

CCYCLE <2:0> L

3 encoded bits to indicate the desired cycle

CERR L

Indicates illegal CYCLE < 2:0 > line encoding
NOTE

x is 0 through 7 for the HSC50 and 1 through 9 for
the HSC70
Termination of all Control Bus signals is provided on the P.ioclP.ioj module. All lines are terminated
with a resistor divider consisting of a 330 ohm pull-up resistor to + 5 volts and a 680 ohm pull-down
resistor to ground with the following exceptions:
•

•

HSC50 only:
•

The signal CACK L is terminated with an equivalent 165 ohm pull-up resistor to + 5
volts and a 680 ohm pull-down resistor to ground.

•

The signal CGRANT < 7:0 > Land CREQ < 7:0 > L are terminated with a 390 ohm
pull-up resistor to + 5 volts and a 620 ohm pull-down resistor to ground.

HSC70 only-the signals CGRANT < 9:1> Land CREQ < 6:2 > L are terminated with a 390
ohm pull-up resistor to + 5 volts and a 620 ohm pull-down resistor to ground.

3-24

BACKPLANE BUSES AND CONTROL SIGNALS

3..5.2
Control Bus Cycles
A Conltrol Bus cycle is defined as the time a requestor has its associated CGRANT signal asserted from
the arbitrator on the P.ioclP.ioj module. Arbitration is performed on fixed 300 nanosecond boundaries.
Once the requestor receives a grant from the arbitrator, it has control of the Control Bus for one 300
nanosecond cycle. No requestor may attempt to obtain two successive Control Bus cycles except during
a Control Bus lock cycle. Each requestor must negate its associated CREQ L for at least one bus cycle
after receiving an asserted CGRANT x L.
When granted access to the Control Bus, a requestor may perform one of four types of cycles. The
cycles are determined by the code in CCYCLE < 2:0 >. Table 3-8 shows the coding for each of the
cycles.

Table 3-8

Control Bus Cycle Encoding

CCYCLE
<2:0>
210

Bus Cycle Definition

001

Normal control memory reference (read or write)

010

Interrupt cycle

100

Lock (read-and-set) cycle

111

NMA cycle

The arbitrator contains logic to detect valid CCYCLE codes. If an illegal CCYCLE code (000, 011, 101, or
11.0) is detected on any Control Bus cycle, the CERR L line will be asserted by this logic on the arbitrator.
The arbitrator then prevents the alteration of Control Memory by inhibiting the assertion of CTIMING
H. Each requestor samples CERR L after performing a Control Bus cycle to verify proper operation of
the CCYCLE lines.
The following sections describe each type of cycle.
3.5.2.1
Control Bus Read Cycle
Once a requestor is granted the Control Bus, a read cycle will be performed if the requestor puts a
normal cycle code (001) on the CCYCLE lines and negates both CWRTH Land CWRTL L during the
cycle. CWRTH Land CWRTL L are the only signalis that distinguish a read cycle from a write cycle. If
either is asserted, a write cycle will be performed instead of a read cycle. The data word is read from
Cantrall Memory on CD AT A < 15:00,HP,LP >.
The foHowing numbered list refers to events in Figure 3-10 and gives a description of the tinling during
an HSC50 Control Bus read cycle.

3-25

BACKPLANE BUSES AND CONTROL SIGNALS

Figure 3-10

HSCSO Control Bus Read Timing

CLK AlB
50 ONLY
20 MAX
80 MIN--..,

---.I r--

CREQ x L

CGRANT xL

M I - - - - 300 NOM - -......

...j ~26MAX
CADR <16: 00> L
1'--55 MAX

CTIMING H _ _ _ _ _ _ _ _..F200 NOM=-;:J..._ _ __

T-SU = 30 MIN
CDATA < 15: 00, HP, LP> L
14-15 MAX
CACK L

------------~I

___m____~

NOTES: 1. ALL VALUES IN NANOSECONDS
2. ONE CHARACTER = 10 NANOSECONDS (APPROX.)
a CREQ x L MAY BE NEGATED ANY TIME AFTER
THE ASSERTION OF CGRANT x L
4. X = 0 THROUGH 7 FOR THE HSC50
X = 1 THROUGH 9 FOR THE HSC70
CX-1101A

When a cycle is desired, a requestor asserts its request line (CREQ x L) no later than 20 nanoseconds after the negative transition of the backplane clock and awaits the result of arbitration
(performed on the P.ioC/P.ioj module).

When successful, the selected requestor receives an asserted grant line (CGRANT x L). The
requestor now has control of the Control Bus until the grant is negated.

The requestor must immediately enable its CADR < 16:00> L, and CCYCLE < 2:0 > L drivers
onto the bus and leave thenl enabled for the duration of the grant. CCYCLE < 2:0 > must be
equal to 1 for a read cycle.

The requestor uses the negation of CTIMING H to strobe the data into its receiver latches.

The data from Control Memory is gated onto the CDATA < 15:00,HP,LP> L lines.

3-26

BACKPLANE BUSES AND CONTROL'SIGNALS

During the bus cycle, the requestor must sample CACK L (to determine a successful memory
reference). Note that CACK L is derived fronl CTIMING H.

The timing relationship for the HSC70 Control Menlory cycle is different than the HSC50. Figure 3-11
shows the HSC70 Control Bus Timing. The differences are that CGRANT is qualified 50 nanoseconds
later than on the HSC50 and the CGRANT signal is qualified on a different edge of CLK AlB. This is
true for all HSC70 Control Memory cycles.
Figure 3-11

HSC70 Control Bus Read Timing

___n,---_

~_n

eLK AlB
700NLY

GREO xL

.....----3oo NOM --~

CGRANT x L

----...J I+- 26 MAX
CAD R < 16 : 00 > L

r---

GTIMING H

55 MAX

~200NOM~~-------

_______________

T-SU = 30 MIN
CDATA < 15: 00, HP, LP > L
j4-15 MAX

CACK L

NOTES:

~15 MAX

------il____1

1. ALL VALUES IN NANOSECONDS
2. ONE CHARACTER = 10 NANOSECONDS (APPROX.)
a CREO x L MAY BE NEGATED ANY TIME AFTER
THE ASSERTION OF CGRANT x L
4. X
0 THROUGH 7 FOR THE HSC50
X
1 THROUGH 9 FOR THE HSC70
CX-ll02A

3-27

BACKPLANE BUSES AND CONTROL SIGNALS

3.5.2.2
Control Bus Write Cycle
Once a requestor is granted the Control Bus, a write cycle will be performed if the requestor puts a
normal cycle code (001) on the CCYCLE lines and asserts either CWRTH L or CWRTL L during the
,cycle. If CWRTH L is asserted, CD AT A < 15:08> L will be written to Control Memory. If CWRTL L
is asserted, CD AT A < 07: 00> will be written to Control Memory. The upper and lower 9-bit bytes are
written independently, though at the same time with the same control signals. CWRTH Land CWRTL
L are the only signals that distinguish a write cycle from a read cycle.
The following numbered list refers to events in Figure 3-12 and gives a description of the timing during a
Control Bus write cycle. The timing for an HSC70 is different for CLK AlB and CREQ x L (Figure 3--11).

Figure 3-12

HSC50 Control Bus Write Cycle

CLK AlB

CREO xL

.....---300 NOM --~

CGRANT xL

CAD R < 16 : 00 > L

CDATA < 15: 00, HP, LP > L

II
200 NOM=-:t~--_

f4-55 MAX

__________F

CTIMING

--..l

1--15 MAX

j 14-

15 MAX

----------~I~_I----~I

CACK L

NOTES:

1. ALL VALUES IN NANOSECONDS
2. ONE CHARACTER = 10 NANOSECONDS (APPROX.)
CREO x L MAY BE NEGATED ANY TIME AFTER
THE ASSERTION OF CGRANT x L
4. X
0 THROUGH 7 FOR THE HSC50
X
1 THROUGH 9 FOR THE HSC70

CX-ll03A

3-28

BACKPLANE BUSES AND CONTROL SIGNALS

When the cycle is desired, the requestor asserts its request line (CREQ x L) no later that
20 nanoseconds after the negative transition of the backplane clock and awaits the result of
arbitration (performed on the P.ioclP.ioj module).

When successful, the selected requestor receives an asserted grant line (CGRANT x L). The
requestor now has control of the Control Bus until the grant is negated.

The requestor must immediately enable its CADR < 16:00> L drivers, CCYCLE < 2:0 > L
drivers, CD AT A < 15:00,HP,LP > L, and CWRTH/L L drivers onto the bus and leave them
enabled for the duration of the grant. CCYCLE < 2:0 > L must be equal to 1 for a write operation.
CWRTH L will be asserted if CDATA < 15:08,HP> are to be written, and CWRTL L will be
asserted if CDATA <07:00,LP> are to be written.

During the bus cycle, the requestor must sample CACK L (to determine a successful memory
reference). Note that CACK L is derived from CTIMING H, so special attention must be paid
when this signal is sampled.

3.5.2.3
Control Bus Interrupt Cycle
The only means for any requestor to interrupt the P.ioclP.ioj is through the Control Bus interrupt cycle.
The K sends an interrupt Inask that informs the P .ioclP .ioj the BR level on which it is interrupting. The
P.ioclP.ioj then turns the interrupt level into an interrupt vector which it passes to the P.ioc/P.ioj through
the interrupt logic. The P.ioclP.ioj uses the interrupt vector as an entry into an interrupt service routine.
Multiple interrupts may be generated on a single cycle.
Once it has been granted use of the Control Bus, the requestor performs an interrupt cycle by driving
the interrupt code (010) onto the CCYCLE lines. The requestor drives the interrupt mask onto the data
lines and the cycle is performed as a normal write-to-memory (though there will be no memory access).
The P.ioclP.ioj accepts the data lines but ignores parity. The CADR lines are unused during the interrupt
cycle. The arbitrator is responsible for asserting CACK L at the proper time to prevent requestors from
getting a non-existent memory error. The arbitrator disables memory access by not asserting CTIMING
L.
Figure 3-13 gives the bit definitions for the interrupt mask.
Figure 3-13

P.ioclP.ioj Control Bus Interrupt Mask

I 1 1 1 1 1 1 1 1 1 1 1 17 t:I~L I 41
15 14 13 12 11

10 09 08 07 06 05 04 03 02 01 00
CX-ll04A

The following numbered list refers to the events in Figure 3-14 and gives a description of the timing
during a Control Bus interrupt cycle.

3-29

BACKPLANE BUSES AND CONTROL SIGNALS

Figure 3-14

Control Bus Interrupt Cycle

ClK AlB
20MAX ~
80 MIN --..,

t+-

III

CR EO x l

30 MAX

~E9:fgl~

--J r---

CGRANT x l .

J..

300 NOM----II
......

j ~30MAX
CDATA<03:00>l

J.--25MAX

CACK l

NOTES:

1. All VALUES IN NANOSECONDS
2. ONE CHARACTER = 10 NANOSECONDS (APPROX.)
CREO x l MAY BE NEGATED ANY TIME AFTER
THE ASSERTION OF CGRANT x l
4. X = 0 THROUGH 7 FOR THE HSC50
X = 1 THROUGH 9 FOR THE HSC70

CX-1105A

When a cycle is desired, the requestor asserts its request line (CREQ x L) no later than 20
nanoseconds after the negative transition of the backplane clock and awaits the result of arbitration (performed on the P.ioclP.ioj module).

When successful, the selected· requestor receives an asserted grant line (CGRANT x L). The
requestor now has control of the Control Bus until the grant is negated.

The requestor must immediately enable its CCYCLE < 2:0 > L drivers, CDATA < 15:00> L,
and CWRTL L drivers onto the bus and leave them enabled for the duration of the grant
CCYCLE <2:0> L must contain the interrupt code (010) and CDATA <03:00> L must have
one or more bits set to interrupt at the desired BR level.

During the bus cycle, the requestor must sample CACK L (which has been generated by the
arbitrator).

The interrupt logic on the P .ioclP .ioj module turns the interrupt level into an interrupt vector
and services the associated interrupt queue when the interrupt is recognized.

3-30

BACKPLANE BUSES AND CONTROL SIGNALS

3.5.2.4
Control Bus Lock Cycle
The requestors use the Control Bus lock cycle to allocate a software structure in Control Memory so
that another requestor may not access that structure. The requestor keeps a lock on a structure until it
finishes its operation.

When the 1008 code is asserted on CCYCLE < 2:0> during the Control Bus cycle, a lock cycle will be
performed at the designated address. The lock cycle performs a read cycle for the requestor, but the
contents of the addressed memory location are rewritten by the arbitrator with a value of 1000008 , The
writing of the addressed memory location occurs during the next successive cycle on the bus after the
read cycle (under control of the arbitrator). These two cycles cannot interrupted by any requestor.
Refer to Figure 3-15 for tin1ing relationships during a lock cycle.
Note that the GRANT line will remain asserted during both bus cycles, so that the requestor mus.t leave
the address on the bus for the write-to-memory portion of the cycle. Thus the requestor must not detect
the completion of the request until CGRANT x L is negated. The requestor is responsible for clocking
the data from the read-from-memory part of the request into its receiver latches with the first negation
of CTIMING H during the cycle, just as in a normal read cycle.
Since a lock cycle appears to the memory to be a normal read cycle followed by a normal write, the
memory need not do anything special to accommodate this feature. However, as with any normal cycle,
the memory must respond with the assertion of CACK L, and the requestor must check for the assertion
of CACK L.
3.5.2.5
Control Bus Non-Memory Access (NMA) Cycle
The requestors use the non-memory access cycle for diagnosing the operation of the CADR and CDAT A
lines.

Requestors execute an NMA cycle after being granted the Control Bus by putting the 1118 code out on
the CCYCLE lines. All timing signals are used the same as for a normal cycle, except that the arbitrator
inhibits the assertion of CTIMING H. Without the assertion of CTIMING H, all Control Memory is
inhibited. A requestor Inay execute either a read NMA cycle or a write NMA cycle.
The arbitrator asserts CACK L during a Control Bus NMA cycle to prevent undesirable non-existent
memory errors from occurring in any requestor.
3.5.2.6
Control Bus Refresh Cycle
Since dynamic RAMS are used in Control Memory, a refresh cycle is necessary. The refresh signals
reserve a Control Bus cycle for all the RAMS on the Memory Module to perform a refresh. The refresh
cycle occurs every 15 microseconds and has the highest priority on the Control Bus.

On the HSC70, only one signal (CREFR GRANT L) is present on the backplane for the refresh cycle.
The arbitration request and the clock signal do not go onto the backplane. On the HSC50, CREFR REQ
Land CREFR CLK L also are driven onto the backplane.
The P.ioclP.ioj generates CREFRESH CLK H as a 66.7 KHz square wave (15 microsecond period) to
indicate when a refresh cycle is to be performed. On the HSC70 this signal is used to directly request
the Control Bus refresh cycle.
On the HSC50, the signal goes onto the backplane as CREFR CLK L on pin B86. In slot one on the
HSC50, pin B86 is tied to pin B87 and comes back into the P.ioc module as CREFR REQ L. The Control
Bus arbitrator then issues a refresh grant signal (CREFR GRANT L), with the same timing as any of the
CGRANT n L signals.
The Control Memory logic uses the assertion of CREFR GRANT L to .initiate an internal refresh cycle.
The arbitrator may not assert any CGRANT signals while CREFR GRANT L is asserted.

3-31

BACKPLANE BUSES AND CONTROL SIGNALS

Figure 3-15

Control Bus Lock Cycle

CLK AlB

CREQ x L

I . . __. .

&M""'""""
.................

CGRANT x L

CA D R < 16 : 00 > L

u L
o W:i?ff~:lZA

CTIMING H

CDATA < 15: 00, HP, LP > L
CACK L
NOTES:

______n

1. REFER TO FIGURES 3-10 AND 3-12 FOR ACTUAL TIMES
2. DATA SUPPLIED BY ARBITRATOR DURING WRITE PORTION
OF CYCLE
3. * = REQUESTOR IS RESPONSIBLE FOR LATCHING DATA
READ AT THIS POINT
4. X = 0 THROUGH 7 FOR HSC50
X = 1 THROUGH 9 FOR HSC70
5. CCYCLE LINES MUST BE DRIVEN FOR THE ENTIRE
LOCK CYCLE
6. THE MEMORY DRIVES THE DATA LINES DURING THE
FIRST HALF OF THE CYCLE; THE ARBITRATOR
DRIVES THE WRITE STROBES AND THE DATA
LINES DURING THE SECOND HALF
CX-1106A

3.6 DATA BUS
The Data Bus is a synchronous, 13.3 Mbyte/second (150 nanosecond cycle) bus etched on the backplane
from slot 1 to slot 12 within the A connector blocks. It is used by the P.ioC/P.ioj, the K.pli, the K.sdi,
and the K.sti modules to access Data Memory (M.data).
The Data Bus deals with word addresses and has 18 significant address bits with no parity bits. The
data word is 16 bits wide with 2 parity bits and, for writing purposes, is divided into two 9-bit bytes.
All arbitration for the Data Bus takes place on the P.ioC/P.ioj module in slot one. In the HSC50, the P.ioc
module gains ownership of the Data Bus by using the request and grant signals on the backplane the
same as other requestors. In the HSC70, the P.ioj DREQUEST and DGRANT signals are on the module
and the extra backplane lines ate redefined as signals for the two additional requestors.

3-32

BACKPLANE BUSES AND CONTROL SIGNALS

3.6.1
Data Bus Signals
Table 3-9 lists and describes the Data Bus signals. All of the signals on the Data Bus, except DNMA,
are asserted low.

Table 3-9

Data Bus Signals

Signal

Description

DDATA < 15:00> L

16 data lines

DDATA HP L

High byte parity for DDATA < 15:08> lines

DDATA LP L

Low byte parity for DDATA <07:00> lines

DADR < 17:00> L

18 address lines (word address)

DWRTH L

Write line for upper byte

DWRTL L

Write line for lower byte

DREQ xL

1 request line per requestor

DGRANT x L

1 grant line per requestor

DTIMING L

Timing reference from arbitrator for write cycles

DACKL

Acknowledge line (positive acknowledge from memory)

DNMAH

Non-memory-access line (used for diagnostic purposes)
NOTE
x is 0 through 7 for the HSCSO and 1 through 9 for
the HSC70

-----,---------------------------------------------------------------------------The P.iloC/P.ioj rnodule provides the termination for all Data Bus signals. All signals are terminated with
a 330 ohm pull-up resistor to + 5 volts and a 680 ohm pull-down resistor to ground, with the following
exceptions:
•

•

HSC50:
•

DREQUEST x L signals are terminated with 3.9K ohm pull-up resistors to + 5 volts

•

DNMA H is terminated with an equivalent 165 ohm pull-up resistor to + 5 volts and
a 680 ohm pull-down resistor to ground

HSC70:
•

DNMA H is terminated with a 200 ohm pull-up resistor to + 5 volts

•

DWRTH Land DWRTL L are terminated with a 220 ohm pull-up resistor to + 5 volts

•

DREQ < 9:0 > L are terminated with a lK ohm pull-up resistor to + 5 volts

3-33

BACKPLANE BUSES AND CONTROL SIGNALS

3.6.2
Data Bus Cycles
A Data Bus cycle is defined as the time a requestor has its associated DGRANT signal asserted by
the arbitrator on the P.ioclP.ioj module. Arbitration is performed on fixed 150:.nanosecond boundaries.
Once the requestor receives a grant from the arbitrator, it has control of the Data Bus for one 150nanosecond cycle. No requestor may attempt to obtain two successive Data Bus cycles. Each requestor
negates DREQ x L for at least one clock cycle after receiving an asserted DGRANT x L.
When granted access to the Data Bus, a requestor may perform one of the following cycles:
•

Read

•

Write

•

Non-memory access (NMA)

The following sections describe each type of cycle.
3.6.2.1

Data Bus Read Cycle

Once a requestor has been granted the Data Bus, a read cycle will be performed if DWRTH Land DWRTL
L are negated while the requestor asserts DADR < 17:00 >. The diagnostic signal DNMA H must also
be negated for Data Memory to place data from the specified address on the DDATA < 15:00,HP,LP>
lines.
The following numbered list refers to the events in Figure 3-16 and gives a description of the timing
during a nornlal Data Bus read cycle.

When a cycle is desired, a requestor asserts its request line (DREQ x L) no later than 19 nanoseconds after the positive transition of CLK B H and awaits the result of arbitration (performed
on the P.ioclP.ioj module).

When successful, the selected requestor receives an asserted grant line (DGRANT x L) at least
9 nanoseconds before the negative transition of CLK B H.

The requestor clocks this asserted grant directly into a flop with this negative transition. This
synchronized grant defines a Data Bus cycle for that requestor, and· it has possession of the
Data Bus until the grant is dro·pped.

U sing this internally synchronized grant, the requestor then asserts the desired address onto
the appropriate lines and negates DNMA H, DWRTH L, and DWRTL L. These signals must
remain stable for the duration of the bus cycle.

Data Memory asserts DACK L if the address is within its range.

Data Memory puts data out on the DDATA lines. The requestor uses the negation of its internal
grant to strobe the data into its buffer.

At the end of the bus cycle, the requestor, using its internally synchronized grant, will latch the
data and address fronl the bus lines and sample the DACK L signal. A requestor is responsible
for post-checking parity accesses.

3-34

BACKPLANE BUSES AND CONTROL SIGNALS

Figure 3-16

Data Bus Read Timing

14-- TCYC = 150

---.,------ir:

C LK B H

TP = 50

- - - 1....1

19MAX--J
-90 MIN (NOTE 3) 1

DREQ x L

~I-----'

--....j

22 MAX
9 MIN

DGRANT x L

Internal Grant L

DADR < 15 : 00 > L

23 MAX

----------~L

DACK L

________

DDATA < 15: 00 > L
NOTES:

1. ALL VALUES IN NANOSECONDS
2. ONE CHARACTER = 5 NANOSECONDS (APPROX.)
3.

DREQ i L MAY BE ASSERTED AT
AFTER

THE

PRECEDING

LEAST

10 NANOSECONDS

NEGATIVE TRANSITION OF

CLK B H (UP TO 90 NANOSECONDS BEFORE THE
POSITIVE TRANSITION OF CLK B H)

CX-1107A

3-35

BACKPLANE BUSES AND CONTROL SIGNALS

3.6.2.2
Data Bus Write Cycle
A write cycle is performed when the granted requestor asserts either DWRTH L or DWRTL L during
the Data Bus cycle. With DWRTH L asserted, DDATA < 15:08,HP> will be written to the high byte of
the location in Data Memory specified by the address on the DADR < 17:00> lines. When DWRTL L
is asserted, DDATA <07:00,LP> are written to the low byte of the specified address. When both lines
are asserted, DDATA <15:00,HP,LP> are all written into the memory word specified by the address
lines.
A requestor is responsible for pre-generating parity on write-to-memory accesses. A parity bit is generated and stored separately for each byte. Data Memory does not check or generate parity, but only
stores the parity bits as part of the data.
The following numbered list refers to the events in Figure 3-17 and gives a description of the tiIning
during a normal Control Bus write cycle.

When a cycle is desire, a requestor asserts its request line (DREQ x L) no later than 19 nanoseconds after the positive transition of CLK B H and awaits the result of arbitration (performed
on the P.ioclP.ioj module).

When successful, the selected requestor receives an asserted grant line (DGRANT x L) at least
9 nanoseconds before the negative transition of CLK B H.

The requestor clocks this asserted grant directly into a flop with this negative transition. This
synchronized grant defines a Data Bus cycle for that requestor, and it has possession of the
Data Bus until the grant is dropped.

Using this internally synchronized grant, the requestor then asserts the desired address onto
the appropriate lines and negates DNMA H.

The arbitrator on the P.ioclP.ioj asserts DTIMING L to enable the drivers on the requestor for
DDATA <15:00>.

Data Memory asserts the DACK L signal if the address is within its range.

3-36

BACKPLANE BUSES AND CONTROL SIGNALS

Figun~ 3-17

Data Bus Write Timing

TCYC = 150 --I~-.l1

~----ir--. TP = 50

ClK B H

19 MAX-......J

·90 MIN (NOTE 3)

DREQ x l

~I-----II

---....l

22 MAX

--I~l,--"-

DGRANT x l

9 MIN

....----150 NOM ----~

t nternal Grant l

23 MAX

DADR < 17 : 00> l

14-40 MAX

.....~ 125 NOM
DTIMING l ------I..--I

=-+I

DACK l

DDATA < 15: 00> l

NOTES:

1. All VALUES IN NANOSECONDS
2. ONE CHARACTER = 5 NANOSECONDS (APPROX.)
3. DREQ x l MAY BE ASSERTED AT lEAST 10 NANOSECONDS
AFTER THE PRECEDING NEGATIVE TRANSITION OF
ClK B H (UP TO 90 NANOSECONDS BEFORE THE
POSITIVE TRANSITION OF ClK B H)
CX-ll0SA

3.6.2.3
Data Bus NMA Cycle
An Nl\,1A cycle on the Data Bus is initiated by a requestor to check proper operation of its Data Bus
transceivers. The requestor drives the data and address onto the bus and then reads it back. The NMA
cycle rnay be performed on any Data Bus cycle.

3-37

BACKPLANE BUSES AND CONTROL SIGNALS

For an NMA cycle, all timing signals are used in the same way as in a normal cycle, except that DNMA H
is asserted. The assertion of DNMA H disables all Data Memory references and causes the arbitrator to
assert DACK L with the proper timing. This latter event is necessary to prevent undesirable non-existent
memory errors from occurring in any requestors.
3.7 S ENABLE i L LINES
These lines, one per requestor, enable the STATUS < 7:0 > conditions onto the backplane for use by
the P .ioclP .ioj. The line to each requestor is terminated on the P .ioclP .ioj so as to default to the negated
(high) state.
3.8 STATUS <7:0>
STATUS <7:0> are used by the P.ioclP.ioj to determine the status of a K. The P.ioclP.ioj reads the
STATUS lines from each requestor slot by asserting the associated S ENABLE x L line. The STATUS
lines are polled by the P .ioclP .ioj during HSC initialization or when a requestor informs the P .ioc/P .ioj
that an abnormal condition exists.

There is no hardware generation or checking for parity on the STATUS lines. However, the microcode on
the K.pli, K.sdi, and K.sti codes parity into the status codes using bit 7. The software is then responsible
for ensuring that odd parity exists in the received code. For instance, if a requestor is reporting a code
468 , the code in the STATUS <7:0> will be 0468 , If the requestor is passing a code 47s , STATUS
< 7:0> will be encoded as a 2478 ,
During the initialization polling, if a requestor is not present in the associated slot, a 377s will be
returned. If a requestor is present but has failed its self test, a code of lxxs or 3xxs will be returned. If
the requestor has passed its self test, it returns a code indicating what type of requestor it is. For the
codes and meanings of the status byte, refer to the service manual.
3.9 CLK A Hand CLK B H LINES
The clock lines provide the base frequency for the majority of logic in the HSC so that it may run as a
completely synchronous system. All requestors use CLK B H to clock both D REQ x Land D GRANT
x L to eliminate any possibility of clock skew in this time-critical area.
3.10 CLK CTL H LINE
When asserted, the CLK CTL H line is used to define which CLK AlB H cycle is to be used for the
upper (control) microsequencer as opposed to the lower (data) nlicrosequencer in the Ks. This allows
repeatable inter-K synchronization to assure that Ks make requests at predictable times with respect to
other Ks.

This line is generated so that it changes synchronously with the rising edge of CLK AlB H. Ks strobe
the CLK CTL signal into a flop with the falling edge of CLK AlB H prior to any use of the signal.
3.11 CLEAR x H LINE
The CLEAR x H line (where x is 1 through 7 for an HSC50 and 1 through 9 for an HSC70) is used a.s
a.n unconditional clear and disable on each requestor. This clear is not dependent on a microsequencer
controlled clear, and it clears any logic on the requestor that can be cleared. Since there is a unique
version of this signal for every requestor, each requestor can be selectively cleared for diagnostic purposes or forcibly disabled for recovery purposes. Every requestor terminates this line so that it defaults
to the asserted state. When there is no P.ioclP.ioj module installed in the backplane, all requestors are
cleared.

3-38

BACKPLANE BUSES AND CONTROL SIGNALS

3.12 HOST CLR H LINE
The K. pH asserts HOST CLR H to clear out the P. ioclP.ioj in response to a low level host interface clear.
The term.ination for this signal is on the P .ioclP .ioj module and defaults to the inactive (low) state.

The K.pli asserts HOST CLEAR H when a host CPU sends a specially defined sequence of two commands.
3.13 SLOW CYCLE L
Pin B86 slots 1 through 12 have the signal line SLOW CYCLE L in the HSC70 only, but the signal is not
used and is grounded. Hardware circuits are present on the HSC70 Memory Module board to allow a
faster cyde time on the Data Bus and Control Bus if the SLOW CYCLE L signal is not asserted.
3.14 BASE AND ENA IN AND OUT LINES
The CBASE IN, DBASE IN, CBASE OUT, DBASE OUT, ENA IN, AND ENA OUT lines are not used
in any implementation of the HSC. These lines are for the possibility that more memory than is present
on one Inemory module is required.

3-39

HOST INTERFACE OVERVIEW

CHAPTER 4
HOST INTERFACE OVERVIEW

4.1 INTRODUCTION
This chapter introduces you to the function of the three host interface (K.ci) modules. The first part
describes the format of the packets that the K.ci sends and receives over the Computer Interconnect
Bus (CI). The second part of the chapter gives you an overview of how the three K.ci modules work
together to process the packets.
You should think of a packet as a burst of information sent between nodes on the cluster. This packet
may be a Mass Storage Control Protocol (MSCP) command, a datagranl, or other information sent
between nodes. Think of this packet as a letter that you want to send to someone. Before you send
the letter, you must put it in an envelope. The envelope around the letter protects it and also carries
the address of the sender and receiver. The following sections describe the format of the packets or
envelopes.
4.2 PACKET FORMATS
The following sections describe the formats of the two types of packets: information and ACK/NACK
(acknowledge/negative acknowledge).
4.2.1
Information Packet
Figure 4-1 illustrates the format of an information packet. The information packet carries both messages
and data across the CI Bus. The LINK puts the synchronization bytes at the beginning of the packet and
the Cycllic Redundancy Check (CRC) and trailer at the end. The Host Processor Module (K.pli) supplies
the following parts of the packet:
Packet type
Packet length
Destination
Source
Body
Note in Figure 4-1 that the body portion represents the letter and all of the other parts represent the
envelope.
4.2.1.1
Bit Synchronization
The first five bytes of the information packet contain bit synchronization (sync) bytes. The bytes are 55
hexadecimal, an alternating pattern of Is and as. This pattern allows the LINK to detect that information
is on the CI Bus and then synchronizes the Manchester Decoder for receipt of useful data. The LINK
inserts these bit synchronization bytes into the packet during transmission.

4-1

HOST INTERFACE OVERVIEW

Figure 4-1

Information Packet Format

BIT SYNC (55 HEX)
BIT SYNC (55 HEX)
BIT SYNC (55 HEX)
GENERATED
OR USED
BY LINK

BIT SYNC (55 HEX)

BIT SYNC (55 HEX)
CHAR SYNC (96 HEX)
PACKET TVPEILENGTH (HIGH)

LOADED OR
READ BY PORT
PROCESSOR

PACKET LENGTH (LOW)
DESTINATION (TRUE)

DESTINATION (COMPLEMENT)
SOURCE
BODY
MINIMUM OF 12 BYTES
MAXIMUM OF 384 BYTES
CRC-O
CRC-1
CRC-2
CRC-3

GENERATED
OR USED
BY LINK

TRAILER (00 HEX)
TRAILER (00 HEX)
TRAILER (00 HEX)
TRAILER (00 HEX)
TRAILER (00 HEX)
TRAILER (00 HEX)
CX-1147A

4-2

FIRST BYTE
TRANSMITTED

HOST INTERFACE OVERVIEW

4.2.1.2
Character Synchronization
The character synchronization (Char Sync) byte (96 hexadecimal) indicates the start of useful data in the
packet. VVhen the LINK recognizes the synchronization character during packet reception, it starts the
framing of the serial data into eight-bit bytes. The LINK inserts the synchronization character into the
packet during transmission.
4.2.1.3
Packet Type/Length (High)
The packet type and length (high) byte contains:
•

The type of packet (information packet)

•

The upper (high) four bits of a 12-bit packet length word

Bits < 7:4 > (packet type) contain Os. Bits < 3:0 > contain the upper four bits of the 12-bit word that
specifies the packet length. Information packets vary in length from seven bytes to a maximum of one
Kbyte in one-byte increments. The packet length specified by the 12-bit packet length word includes all
data from the packet type and length (high) byte up to and including the last byte of the body.
NOTE
The buffers in the Port Buffer Module (PI LA) limit
the packets to one Kbyte.

The Port Processor Module (K. pli) supplies the packet type and length (high) byte as part of the packet
before sending it to the PILA.
Packet Length (Low)
4.2.1.4
The packet length (low) byte contains the low eight bits of the 12-bit packet length word. The K.pli
supplies this byte as part of the packet before sending it to the PILA.
Destination (True And Complement)
4.2.1.5
The destination bytes contain the 8-bit address of the destination node. (The destination represents the
address on an envelope.) The K.pli supplies two destination bytes:
•

True node address value

•

Complement of the true node address value

This redundant destination address eliminates a single logic failure in a node from replying to a packet
that was not sent to it. With a single address decode circuit, a logic failure could cause a node to decode
another node's address, resulting in both nodes transmitting an acknowledge packet at the same time.
This type of failure would result in a collision on the CI Bus and would be seen as a no response by the
transmitting node.
4.2.1.6
SourcE~
The source byte contains the 8-bit address of the HSC. The K.pli provides the source byte as part of
the packet before sending it to the PILA. (The source is like the return address on the envelope.)
4.2.1.7
Body
The body contains the data and port-processed protocol information. The K.pli supplies the body
portion of the packet before sending it to PILA. The body has a minimum of 12 bytes, a maximum of
384 bytes. (The body is like the letter in the envelope.)

4-3

HOST INTERFACE OVERVIEW

4.2.1.8
Cyclic Redundancy Check (CRC) Bytes
The CRC bytes contain the coefficients of the CRC polynomial. During a packet transmission, the CRC
logic generates the CRC coefficients (starting with the packet type and length (high) byte). These four
bytes make up a 32-bit longword. During packet reception, the LINK regenerates the CRC coefficiE~nts
and then compares them with the four incoming CRC bytes. An error-free packet results in an exact match between the two longwords. The LINK supplies the four CRC bytes of the packet during
transmission.
4.2.1.9
Trailer
The trailer consists of six bytes of all Os. These bytes insure that all bits of a received packet have been
shifted through the LINK before it senses the end of packet reception. The LINK supplies the trailer
portion of the packet during transmission.
4.2.2
Acknowledge/Negative Acknowledge (ACK/NACK) Packet
Figure 4-2 illustrates the format of ACK and NACK packets. The LINK sends ACK and NACK packets
to inform the transmitting node that the packet arrived without data loss or bus collision (CRC checked
OK). If the HSC successfully accepted the packet into the buffers in the PILA, the LINK returns an
ACK packet indicating a successful bus transaction and storage in the PILA. If the receiver buffers in
the PILA were full, the LINK returns a negative acknowledge (NACK) packet indicating that the packet
was successfully received but not accepted. The transmitting node must then retransmit the packet.
The LINK generates and transmits the entire ACK (or NACK) packet. An ACK/NACK packet differs
from an information packet in the following three ways:

•

The ACK/NACK packet has no body. An ACK/NACK packet only acknowledges reception of
an information packet. It does not transfer messages or data as such.

•

The ACK/NACK packet has no packet length word. All ACK and NACK packets are the same
length. Therefore, bits < 3:0 > of the packet type and length (high) byte contain Os and the
packet length (low) byte contains Os.

•

The ACK/NACK packet type bits < 7:4 > are different. The packet type and length (high) byte
specify the type of packet, as follows:
•

Bit 7 equals a 1 indicating an ACK/NACK packet

•

Bit 6 equals a 1 for an ACK packet, 0 for a NACK packet

4.3 HOST INTERFACE (K.ci)
The host interface (K.ci) consists of three modules:

•

Port Link Module (LINK)

•

Port Buffer Module (PI LA)

•

Port Processor Module (K.pli)

These modules are the interface between the HSC internal buses and the CI Bus. Figure 4-3 illustrates
the host interface modules. Communication and data transfer between the LINK, PILA, and K.pli are
over the PORT/LINK Interface (PLI). The K.pli controls all communications and data transfers between
these three modules. The Interprocessor Link Interface (ILl) allows communication and data transfer
between the PILA and the LINK.

4-4

HOST INTERFACE OVERVIEW

Figure 4-2

ACK/NACK Packet Format

BIT SYNC (56 HEX)

FIRST BYTE
TRANSMITTED

-BIT SYNC (56 HEX)
BIT SYNC (55 HEX)
BIT SYNC (55 HEX)
BIT SYNC (55 HEX)
CHAR SYNC (96 HEX)
PACKET TYPE
1 x 0 0

I0 0 0 0

0 0 0 0

DESTINATION (TRUE)
DESTINATION (COMPLEMENT)
SOURCE
CRC-O
CRC-l
CRC-2
CRC-3
TRAILER (00 HEX)
TRAILER (00 REX)
TRAILER (00 HEX)
TRAILER (00 HEX)
TRAILER (00 HEX)
TRAILER (00 HEX)
CX-1148A

4-5

HOST INTERFACE OVERVIEW

Figure 4-3

Host Interface (K.ci) Modules

r------------------II
HOST INTERFACE

I
I
PLI

...

JI
I
!\

PORT
PROCESSOR

CONTROL BUS

DATA BUS

"
~

PORT
BUFFER

[

)
r
III
II..

PORT
LINK

•

CI
BUS
A

CI
BUS

- - - - - - - 1- --- - ~-----'

CX-949A

The K.ci, an intelligent interface, performs the function of a buffered communications port. It utilizes control structures in the HSC memory to transfer messages and blocks of data between the HSC
memory and other nodes within the CI cluster. By providing data buffering, address translation, and
serial encoding and decoding, the K.ci reduces the amount of overhead software processing required
to complete high-level intercomputer communications.
Figure 4-4 shows a block diagram of the K.ci, and the following sections describe this figure.

4-6

HOST INTERFACE OVERVIEW

4.3.1
Port Link Module (Link)
The LINK provides the interface to the CI Bus and services both CI paths. This module contains a
transmit path and a receive path with CRC functions shared between the two channels. The LINK can
transmit or receive over only one CI path at a time due to the common CRC logic used by both channels.
The LINK gets data packets from the buffers in the PI LA over the XMIT DATA BUS. The LINK appends
to the packets the bit and character synchronization, eRC, and trailer.
The translnit path consists of the:
Transmitter
Manchester Encoder
Path Select
The LINK transmitter converts the data packet from a byte format to a 70-megabit-per-second serial
format. The Manchester Encoder then encodes the information. The Manchester Encoder combines the
serial data with a bit rate clock to produce a m.odulated (phase encoded) carrier for the CI Bus. The Path
Select logi.c, under K. pli microcode control, selects the CI path (A or B) for the transmission.
The receiver path consists of the:
Carrier Detect
l\tlanchester Decode
:Receiver
Destination Decode
The Carrier Detect logic monitors the two CI paths and connects the receiver channel to the active
path. The logic selects the active path and routes the packet to the Receiver. The Receiver converts the
packet data from a 70 megabit-per-second serial format to a byte format. The K. pH routes the packet
information to an empty PILA buffer over the RCVR DATA bus (part of the ILl Bus). The Destination
Decode logic compares the destination byte of the packet against the node address to determine if the
HSC should process the packet. If the HSC should not process the packet, the LINK stops processing
the packet. If the HSC should process the packet, the LINK finishes processing the packet. The CRC
logic validates the packet by checking the packet data against the packet CRC bytes.
After receiving the packet, the LINK can respond in three different ways:
•

If buffers are available in the PILA and the CRC check passed, the LINK will return an ACK
packet.

•

If the PILA buffers are full but the CRC check passed, the LINK will return an NACK packet.

•

If the CRe check does not pass, the LINK will not respond. Therefore, the sending node will
send the packet again.

4-7

HOST INTERFACE OVERVIEW

Figure 4-4

Host Interface (K.ci) Block Diagram
PILA

LINK

-<JCI-A

I
PATH
SELECT

HEADER/
TRAILER
XMIT
DATA

'r---'--f- - - - - I I
MANCHESTER
ENCODER

I
I

_-----_,,""7
7:0
I
,
TRANSMITTER

PLI
DATA

7:0
A

XMIT

A
BUFFER

rv-

(lK)

ADDRESS
COUNTER

ACK/NACK
LOGIC

XMIT
B

BUFFER

(lK)

ADDRESS

\r COUNTER \r

CRC

tit.

------n
NODE
ADDRESS

'---------II

RCVR

A
BUFFER

DESTINATION
DECODE

~ ADDRESS

i'r COUNTER ~

(lK)

\r~

RCVR

~ B

BUFFER
MANCHESTER ~
DECODER

-<JCI-B

RECEIVER

(lK)
RCVR
DATA

f
i...--

--[>-

CARRIER
DETECT

l/L ADDRESS

~ COUNTER

7:0
LINK
CONTROL
LOGIC

PLI

PILA
CONTROL
LOGIC

BUS

CX-950A

Sheet 1 of 2

(Continued on next page)

4-8

HOST INTERFACE OVERVIEW

Figure 4-4 (Cont.)

Host Interface (K.ci) Block Diagram

K.pli

DIN
15:00

D OUT
15:00
..
~--------------------~------~'I

~ P~I: :~;~~~
INTER FACE
HEGISTER
15:08

t~~
:}~

~
rrI

~t~

~ill:

SCRATCH-

4'--P_A_D_ _.....

PLI
INTERFACE
r~EGISTER

7:0

r---t\

CONTROL
SEQUENCER

ff-

ALU

rvI PROGRAM ~ CONTROL
~

ADDRESS

Lf\

I
I

DATA
SEQUENCER

STORE

"\
~

I--

MICRO
INST
REGISTER
I--I-I-.

D IN BUS

CX-950A
Sheet 2 of 2

4-9

HOST INTERFACE OVERVIEW

4.3.2
Port Buffer Module (PILA)
The Port Buffer Module (PILA) provides buffering for the data packets transferred through the K.ci. The
PILA contains two transmit and two receive buffers (A and B). Each buffer has a capacity of one Kbyte.
When data packets are being transmitted, the K.pli loads the Transmit A Buffer over the PLI DATA bus.
The K.pli loads Transmit B Buffer while the LINK transmits the packet in Transmit A Buffer. Likewise,
the K.pli routes a received data packet to the Receive A Buffer over the RCVR DATA bus. If the LINK
accepts another packet before Receive A Buffer empties, the K.pli routes the packet to Receive B Buffer.
The control sequencer in the K.pli controls the packet transfers over the PLI and ILl Buses.
Port Processor Module
4.3.3
The port processor (K.pli) contains two logic groups:
•

Two sequencers and a shared arithmetic logic unit (ALU)

•

Interface between the PILA and the rest of the HSC

The two sequencers alternately and independently access the common control store. The two sequencers, in conjunction with the control store and ALU, control different portions of the external
interfaces and have separate and independent functions. The data sequencer handles all of a data transfers between data memory and the PLI interface. The control sequencer has responsibility for all other
work the K.pli must do. This work includes:
•

Examining queues for work to do

•

Acquiring and retiring buffers

The K.pli obtains or passes data to and from the PILA, Control Bus, and Data Bus. The Control and
Data Buses are 16 bits wide, as are the two internal buses, D IN and D OUT. However, the PLI DATA
bus is only 8-bits wide. The PLI Interface Registers convert from 8-bit to 16-bit on a transfer from the
PI LA to the K. plio Also, the PLI Interface Registers convert from 16-bit to 8-bit on a transfer from the
K. pli to the PILA.

4-10

PORT LINK MODULE

CHAPTER 5
PORT LINK MODULE

5.1 PORT LINK MODULE FUNCTIONAL OVERVIEW
The Port Link Module (LINK) (L0100) provides the interface to the Computer Interconnect (CI) Bus. This
module is functionally divided into a transmit path and a receive path with a cyclic redundancy check
(CRC) function shared between the two paths. Due to the common CRC logic used by both paths, the
LINK can transmit or receive over only one CI Bus (A path or B path) at a time. Figure 5-1 is a simplified
block diagram of the LINK nlodule.

The LINK receives data packets from the Port Buffer Module (PILA) over the XMIT DATA bus. The
LINK appends a header and a trailer to each packet. Headers contain both source and destination
information for the packet. Node address switches on the LINK provide the node with its address on
the CI Bus. The packet header contains this address as a source identification. The trailer following the
packet body keeps fhe receiver logic active while the LINK processes the last data bytes.
The CRC Logic uses the packet data bytes to generate four CRC bytes and appends them to the data
packet. The receiving node checks the generated CRC bytes for transmission errors.
The LINK also converts the data packet from a byte format to a 70-megabit-per-second serial format
using Manchester encoding. In order to produce a modulated (phase encoded) carrier for the CI Bus,
the Manchester Encoder combines the serial data with the bit rate clock.
The Transmit (XMIT) Path Select Logic, under microcode control, selects the CI transmission path (A
or B). Carrier Detection Logic monitors the two CI paths and connects the receiver channel to the active
path.
Serial data from the CI is Manchester decoded, separating the signal into its clock and data components.
These components are applied to the LINK receiver. It, in turn, converts the packet data from a 70
megabit-per-second serial format to a 8-bit parallel byte format. The LINK receiver then presents the
packet data to the CRC Logic for validation. CRC Logic checks the packet data against the packet CRC
bytes.
If a CRC error is detected, no response (ACK or NACK - acknowledge or no acknowledge) is returned
to the transmitting node. If no CRC error exists, the packet is sent to the PILA over the RCVR DATA
bus. If the PI LA can accept the packet, the LINK returns an ACK message to the transmitting node.
If the buffers on the PILA module are full and cannot accept the packet, the LINK returns a NACK

message to the transmitting node. That node then retransmits the packet.
LINK Control Logic receives commands from the Port Processor Module (K. pli) to select and start LINK
operations. This logic also senses signal conditions controlling data packet transfers through the LINK.
For timing operations on the receive and transmit channels, a receive clock (RCVR CLK) and a transmit
clock (XMIT CLK) are generated on the LINK.

5-1

"'U

:IJ

-f

Figure 5-1 LINK Simplified Block Diagram

"3:

SYNC/
TRAILER
PROM

o
c

(E)

BUS
(FROM PILA) XMIT DATA (7:0>

XMIT
DATA
INPUT
LATCH

I -

(E)

(R)

I "::==:;l

.. ACK
TYPE

LOGIC
(E)

ACK
SOURCE
LOGIC
(E)

-----r------------...,--------I
(TO PI LA) ....

ACK
DESTINATION
LOGIC
(D)

(T)

TO
CI BUS

_ _

""------'

CI B X MIT

r----------.J

f-----+

CIA XMIT

... MANCHESTER
XMIT
ENCODER
ME DATA PATH
(T)
--=- SELECT
LOGIC l

""------' XMIT CLK

r---'--.., ,..---'---, r'-

(FROM PILA) RCVR BUFFERS FULL

f---+l

r - -....... XMIT SERIAL

r-X-M-I-T..... TDATA XMIT
DATA
XMIT DATA BUS<7:0> DATA <7:0> SERIAL
4
~
REG
=- SHIFT
REG

c:
rm

CRC
t......., GENERATOR
CRC

TRANSMIT CHANNEL

~ CHECKER

RECEIVE CHANNEL

----

TO MESSAGE
L-(U..:,.'V..;)_ _.-t-----t:.. R ECE I VE STATE
CRCSTATUS LOGICANDPILA

ACK
~ SOURCE
COMPARE

(D)

NODE
~ DESTINATION
ADDRESS
COMPARE
SWITCHES t--~-+--I_~ (D)
(K)

(TO PILA) _ RCVR DATA<7:0>

R. CVR
r - - - - . . , RCVR SERIAL D A T A r - - - - - RDAT<7:0>
BYTE
..
1.~--------1 MANCHESTER
! . J - L . - - - - - - -.........--t FRAMER I.
DECODER
OUTPUT ...

~E~G

ME
_DATA

RCVR
PATH

CIA RCVR

14- SEL

(PI

MDECODER CLOCK ....(_S)_ _ _- - I

MUX
(S)

CIB RCVR

r-If-----,---

SYNC

•
RCVR
CLK
...
_f-R_C_V_R_C_L_K_ _ _ _ _-I GEN
(N)

NOTE: LETTER DESIGNATIONS IN PARENTHESES REFER TO ENGINEERING DRAWiNGS CONTAiNiNG CORRESPONDING LOGIC.

,r
-

FROM
} CIBUS

CARRIER DETECT!
MUX SELECT
LOGIC
(S)

CX-951A

PORT LINK MODULE

The following sections describe the four LINK operations with the transmit and receive channels functioning according to the specific packet type being processed. These four operations are described in
the order of occurrence:
Reception of an information packet
Transmission of an ACKINACK packet
Transmission of an information packet
Reception of an ACKINACK packet
5.1.1
Information Packet Reception
Data packets on the CI Bus are in serial format alt a serial bit rate of 70 MHz. Data is Manchester
encoded (phase encoded) where the clock is incorporated into the modulated signal. CI paths A and B
are input to a RCVR Path Select Mux in the LINK. Carrier Detect Logic monitors both CI paths. When
the logic senses the initial presence of signals on one of the paths enabled by the K. pli, it switches the
multiplexor to the active path, selecting CIA RCVR or CIB RCVR for the Manchester Decoder. The K. pli
can also select an internal path where the nlultiplexor selects the output from the translnit channel and
loops it back into the port. The K.pli uses this feature for maintenance operations.
The multiplexor output is applied to the Manchester Decoder where the signal clock is extracted from
the modulated signal. The Manchester Decoder outputs the data (RCVR SERIAL DATA) and the clock
(MDECODER CLOCK) to the Byte Framer containing the sync character detector.
The Byte Framer performs serial-to-parallel conversion of signal data. The sync character detector enables the framer. The framer, when enabled, outputs a data byte (RDAT < 7:0 » for every eight serial
bits received from the Manchester Decoder. A RCVR CLK generator develops RCVR CLK which times
the data transfers through the LINK receive channel. SYNC from the Byte Fralner synchronizes RCVR
CLK with the data bytes and approxinlately centers RCVR CLK within the asserted time period of RDAT
< 7:00>. RDAT < 7:00 > data bytes are clocked into the RCVR output register and sent to the PILA as
RCVR DATA <7:00>.
Correct packet destination is verified by the Destination Compare Logic. Packet destination bytes are
compared to the node address set into the LINK node address switches. If they do not conlpare, the
receiver is cleared and reception is terminated.
The packet source byte is extracted from the incOlning packet and placed into the ACK destination
register. When the LINK transmits an ACK packet in response to the infoflnation packet being received,
it uses the address in that register (source of the infornlation packet) as the ACK destination.
The packet bytes extending frOln the packet type and length (high) byte up to and including the last byte
of the body are checked by the CRC. The CRC algorithm acts on the bytes and generates a 32-bit CRC
longword. The four CRC bytes in the packet are compared to the generated longword. If the packet is
error free, CRC STATUS is asserted to the message receive logic.
After the packet trailer passes through the LINK, the Carrier Detect Logic senses the end of the packet
and informs the ACK Transmit Logic. This logic initiates transnlission of the ACK packet.
5.1.2
ACK/NACK Packet Transmission
ACKINACK packets are generated and transmitted entirely by the LINK. No packet infornlation is

received from the PILA as XMIT DATA < 7:00 >.
The ACK Transrnit Logic initiates the transmit operation by enabling the Sync/Trailer PROM. This Sync
/Trailer PROM outputs five 8-bit-sync bytes and a sync character byte onto the XMIT DATA bus (XMIT
DATA BUS < 7:00 ». The ACK Type Logic is enabled and outputs the packet type byte onto the
XMIT DATA bus. The PILA signal RCVR BUFFERS FULL is sampled at the start of information packet
reception. If RCVR BUFFERS FULL is true, the PILA cannot accept the information packet just received.
In this case, the ACK Type Logic outputs the code for a NACK packet. If RCVR BUFFERS FULL is
false, the logic outputs the code for an ACK type packet.

5-3

PORT LINK MODULE

LINK Control Logic then enables the output of the ACK Destination Register which outputs the two
destination bytes onto the XMIT DATA bus. The destination value used is the source address taken
from the information packet just received. ACK Source Logic is enabled and the node address from the
node address switches is transferred to the XMIT D ATABus as the source byte.
The ACK/NACK packet is transferred to the BUS TDATA Bus via the XMIT Data Register. Starting with
the packet type byte, the packet is also input into the CRC generator where a 32-bit CRC longword is
generated. After the source byte is input to the CRC generator, the LINK Control Logic gates the CRe
longword (a byte at a tin1e) onto the BUS TDAT A Bus. The four CRC bytes are thus inserted into the
ACK/NACK packet.
Finally, the ACK Transmit Logic reenables the Sync/Trailer PROM outputting six trailer bytes onto the
XMIT DATA Bus and completing the ACK/NACK packet.
'
Sending the ACK/NACK packet fron1 the BUS TDAT A Bus through the XMIT Shift Register converts the
signal data from parallel to serial. Data bytes input to the register are shifted out serially at a 70 MHz bit
rate to the Manchester Encoder as XMIT SERIAL DATA. Serial Shift Register Logic also generates XMIT
CLK. This signal times the data transfer through the LINK transmit channel. XMIT CLK and the serial
data are synchronized within the shift register. The Manchester Encoder combines data from XMIT
SERIAL DATA with the bit rate clock producing a phase-encoded carrier. It then outputs the modulated
carrier (ME DATA) to the CI Bus. ACK Transmit Logic selects the saIne CI path used by the information
packet just received. In addition, ME DATA can follow an internal loop path into the receive channel.
This feature is used for maintenance testing and is possible only if the LINK is in internal loop mode
and the receiver inputs from the CI Bus are disabled.
5.1.3
Information Packet Transmission
All information packets are generated by the K.pli and input to the LINK transmit channel from the
PILA. Information packet bytes inserted by the LINK are:
Five 8-bit sync bytes
One 8-bit character sync byte
Four 8-bit CRC bytes
Six 8-bit trailer bytes
Information packet transfers use some of the functions described in the previous section, and they
operate as described.
Using the Message Transmit Logic, the K.pli initiates the transmit operation. When the transmit operation is initiated, the LINK enables the Sync/Trailer PROM. This signal outputs five 8-bit sync bytes
and an 8-bit sync character byte onto the XMIT DATA Bus. The packet type and length (high) byte, the
packet length (low) byte, and the destination bytes are provided by the K. plio
When the destination bytes are on the XMIT DATA Bus, the LINK enters the destination address into
the ACK Source Compare Logic. When the ACK/NACK response packet is received from the target
node, the packet source byte is conlpared with the contents of the compare logic. If the correct node
responded, a match is obtained.
The K.pli, not the LINK, inserts the source byte. The K.pli reads the node address switches on the
LINK. The source byte is an input to the XMIT DATA Bus from the PILA.
The K.pli generates the body before sending it to the LINK.
The eRe Generator produces the four 8-bit eRe bytes just as for an ACK/NACK transmission. However,
the information packet body is also input to the CRC Generator and contributes to the CRC longword
generation. Finally, the LINK Message Transmit Logic reenables the Sync/Trailer PROM. This signal
outputs the six trailer bytes onto the XMIT DATA Bus, completing the information packet.

5-4

PORT LINK MODULE

ACK/NACK Packet Reception
Transfer of an ACKINACK packet through the receive channel utilizes most of the functions described
in the previous section. These functions also operate as described. With regard to the LINK receive
channel, the basic difference between an ACK/NACK packet and an information packet is the use of
the packelt source byte. In ACK/NACK reception, the source byte is not entered into the Destination
Register but is applied to the ACK Source Compare Logic. This logic currently contains the destination
address of the information packet just transmitted. The source byte is compared to the destination
address and matches if the correct nodes are involved in the data transfer.
5.1.4

5.2 RECEIVE AND TRANSMIT CHANNELS
The following sections describe receive channel and transmit channel hardware. Hardware control is
a function of K.pli commands, the type of operation being executed, and conditions sensed by the
logic (for example, errors) during the operation. Hardware control is implemented by Programmable
Array Logic (PAL) defining various hardware states during each operation. The states are represented
in four diagrams in the engineering drawing set. (Operations represented in these diagrams an~ shown
in Table 5-1 and described in Section 5.7.)

Table 5-1

LINK States

Operation

Number of States

Infornlation Packet Reception

ACK Packet Transmission

Infornlation Packet Transmission

ACK Packet Reception

5.2.1
Receive Channel
Figure 5-2 is a block diagram of the receive channel and should be referenced throughout this section.

5-5

PORT LINK MODULE

Figure 5-2

Receive Channel Block Diagram

ACK
SOURCE
COMPARE

ACK SOURCE CMP

(D)

CRC STATUS

MR STATE C
CNODE
ADDRESS
<7:0>

AR STATE B

~L-____~~__~TRUE

DESTINATION
r-----I~ COMPARE

(D)

NODE
ADDRESS
COMPLEMENT
<7:0>
)--.------If--------l.... DESTI NA TION
COMPARE
1 - - - - - 1... (D)

NODE ADDRESS<3:0>

MR STATE D

MDECODER
CLOCK

AR STATE C

RDAT REG<7:0>

RCVR
SERIAL
DATA

RCVR DATA 6

RCVR
DATA
RCVR
___<_7_:_0>
........~ 0 UTPUT
D
DATA
REG
(F)

RCVR
DATA
___
PA_R_I_T_Y--I RCVR

RDAT
REG
<7:0>

RCVR
ClK

RDAT
<7:0>

RCVR D
DATA
REG
(F)
C

ENA SYNC DET

CHAR SYNC
EXT SYNC

DATA
PARITY
FF
(F)

RCVR
DATA
PARITY
GEN

VALID RCVR PARITY

(F)

NOTE: lETTER DESIGNATIONS IN PARENTHESES REFER TO ENGINEERING DRAWINGS CONTAINING CORRESPONDING lOGIC.
CX-952A

Sheet 1 of 2

(Continued on next page)

5-6

PORT LINK MODULE

Figure 5-2 (Cont.)

Receive Channel Block Diagram

DST CMP

DECODER
FF
(S)

MDE(;ODER

MR STATE D

AR STATE F

/(J) (

CLo:~l

(S)

/
:~
10.7 NS

ME DATA

CIA
RCVR

f~} FROM

RCVR
_ PATH
SELECT
MUX

ReVR PATHSELB

RCVR

jr-

MSG END+'"HTO

RCVR PATH SEL A
ENASY !\IC
DET

CARRIER
DETECT
A
(S)

FORCE PATH A
SYNC CHAR
DETECT
ENABLE
PAL

FORCE PATH B

CARRIER
DET B

D
ICCS PATH
SELECTED

r-r-r--

LE ~

ICCS
PATH B

ICCS PATH
B CDET

(J)

CARRIER
SELECT
STATE
PAL

i4-f-J

Cj4-

CARRIER
DET A

(J)

---

------.
D

A CDET

(J)

C
10....--

RCVR CLK

CARRIER
DETECT
B
(S)

•

L-

SET

~
(S)

CAR
DET B
C ..
FF

leCSPATH~

CI BUS

SET
CAR
DET A
FF

I-L-

RCVR
CLK

(5)

~ '"'"l
r'---.

RCVR A ENABLE

RCVR B ENABLE

RCVR B ENABLE
ENA INT MLOOP

INT MLOOP

M
~

MXSTATEA
CX-952A

Sheet 2 of 2

5·-7

PORT LINK MODULE

Receive channel hardware contains both transistor-transistor logic (TTL) and emitter-coupled logic (ECL).
The Carrier Detection/Path Selection Logic, Manchester Decoder, Byte Framer and Sync Character
Detector all use ECL logic. For those unfamiliar with ECL logic, the Receive Path Select Multiplexor is
described in Section 5.2.1.3.
CI Carrier Detection and Path Selection
5.2.1.1
The Carrier Detection/Path Selection Logic 1110nitors CI Bus activity and, when activity is detected,
selects the active path as an input to the LINK receive channel. The K.pli, through the LINK control
PALs, specifies which receive channel can receive signal inputs from the CI Bus. These PALs enable
the receive channels by asserting RCVR A ENABLE or RCVR B ENABLE.
5.2.1.2
Carrier Detect logic
The Carrier Detect Logic is identical on both paths A and B. If a carrier is present on CI path A, the
Carrier Detect A Logic sets the carrier detect A flip-flop. If the K.pli has enabled channel A (RCVR A
ENABLE true), ICCS PATH A CDET is asserted and a flip-flop on the next RCVR CLK asserts CARRIER
DET A. The flip-flop outputs CARRIER DET A to the Carrier Select State PAL. If the current state of the
port permits opening a receive channel, the Carrier State Select PAL asserts ICeS PATH SELECTED
and negates ICCS PATH B. RCVR PATH SEL A directs the Receive Path Select Multiplexor to select CI
path A for the multiplexor input. If activity is sensed on CI path B, similar logic selects CI path B for
the multiplexor input (but not A and B at the same time.)
LINK Control Logic signals, FORCE PATH A and FORCE PATH B, force a corresponding path selection
from the Carrier Select State PAL. When the K.pli commands a message transn1.ission, the transmission
path is reserved in the receive channel waiting to receive the ACK response.
The K.pli, through the LINK control PALs, can also select the internal maintenance loop (INT MLOOP)
where ME DATA from the transnlit channel is selected for the multiplexor input. The true state of INT
MLOOP inhibits both RCVR PATH A and RVCVR PATH B causing the nlultiplexor to select the ME
DATA input signal.
5.2.1.3
Receive Path Select Multiplexor - ECl logic
The Receive Path Select Multiplexor is shown in Figure 5-3 and also on sheet S of the engineering
drawing set. If RCVR PATH SEL A is true, the output of OR gate A can follow the CIA RCVR signal
input.
The signal RCVR PATH SEL B is false holding the output of OR gate B low. In ECL logic, a signal low is
the non-active state and a high is the active state. Any gate connected to a common line can pull up the
line to the active state. Thus, OR gate B is held inactive (low) while OR gate A transfers the CIA RCVR
signal to the Manchester Decoder. The true state of RCVR PATH SEL A also holds the LOOP OR gate
in the inactive state.
If RCVR PATH SEL B is true (RCVR PATH SEL A false), OR gate A and the LOOP OR gate are held

inactive. OR gate B transfers CIB RCVR to the Manchester Decoder.
5.2.1.4
Manchester Decoder
Phase encoding and Manchester Decoder Logic are discussed in the following sections.

5-8

PORT LINK MODULE

Figure 5-3

Receive Path Select Multiplexor-Eel logic
A

CIA RCVR
RCVR PATH SEL A

ME DATA

RCVR PATH SEL B
CIB RCVR
CX-953A

5.2.1.4.1
Phase Encoding
Phase encoding is a modulation technique where a signal phase reversal occurs for each bit of information (Figure 5-4).
•

When the input is binary 1, there is a negative transition at bit cell center.

•

When the input is binary 0, there is a positive transition at bit cell center.

•

When the binary value (either 0 or 1) is the same as the previous cell, the cell must start with
a level reversal.

•

If the binary value is different than the previous cell, there is no reversal at the start of the cell.

Note in Figure 5-4 that consecutive ones or consecutive zeros cause phase reversals to occur at twice
the data rate. Alternate ones and zeros cause signal transitions to occur at the data rate.
Phase (Manchester) encoding presents high read integrity, an advantage over other types of encoding.
A positive pulse is always binary 0 and a negative pulse is always binary 1.

Figure 5-4~

Phase Encoded Data

I
0

LSl
I

B. ALTERNATE 1s AND Os

A. CONSECUTIVE 1s AND Os
MR·14456

5-9

PORT LINK MODULE

5.2.1.4.2
Decoder Logic
The Manchester Decoder separates the 70 MHz bit rate clock (MDECODER CLOCK) and data (RCVR
SERIAL DATA) from the input. The decoder consists of a flip-flop with the signal data from the Receive
Path Select Multiplexor as the D input. The flip-flop clock input is derived from XORing the delayed
output of the Receive Path Select Multiplexor (delayed 10.7 ns) with the output of the decoder flip-flop.
Figure 5-5 illustrates the action of the decoder logic. Signal data from the Receive Path Select Multiplexor
is shown with one or zero transitions at the center of each bit cell. With a 70 MHz bit rate, the width of
the bit cells is 14.28 ns. Delay line output is seen as the signal data delayed 10.7 ns. XORing the delayed
data with the flip-flop output (RCVR SERIAL DATA) generates the MDECODER CLOCK waveform.
The MDECODER CLOCK is at 70 MHz with a 14.28 ns period. The XOR action generates the clock's
rising edge one quarter into each bit cell. This centers the rising edge in the valid strobe area (first half
of the bit cell).
.
Figure 5-5

Manchester Decoder Timing Diagram
BIT CELL = 14.28 NS

OUTPUT FROM RECEIVER
PATH SELECT MUX
DELAY LINE OUTPUT
MDECODER CLOCK

RCVR SERIAL DATA

o
o

o
e
o

DELAY = 10.7 NS
DECODER FLIP-FLOP SET TIME

DECODER FLIP-FLOP RESET TIME
VALID STROBE AREA
MR·14457

5.2.1.5
Sync Character Detect Enable PAL
The purpose of the Sync Character Detect Enable PAL is to assert ENA SYNC DET to the Byte Framer
when a packet is expected. The PAL asserts ENA SYNC DET immediately after information packet
transmissions in anticipation of the ACK (or NACK) response. The PAL monitors CARRIER DET A and
CARRIER DET B and asserts ENA SYNC DET when it senses that a signal carrier is being received.
The PAL negates ENA SYNC DET during node transn1issions (FORCE PATH A, FORCE PATH B) so
the LINK does not respond to its own transn1issions.
The Byte Fran1er contains a sync detector enabled by ENA SYNC DET. When the sync detector finds
a packet sync character it recognizes a packet is being received. When the detector recognizes the
sync character, it enables the Byte Framer to process the packet bytes. By keeping the detector disabled
except when a packet is detected, the Sync Character Detect PAL prevents the detector from erroneously

5-10

PORT LINK MODULE

recognizing noise as a sync character. The Sync Character Detect Enable PAL is discussed in more detail
in Section 5.7.2.2.
5~2.1.6
Byte Framer
The Byte Framer is enabled when it receives the sync character byte. When the framer recognizes the
sync character, it begins serial signal data conversion from the Manchester Decoder into 8-bit data bytes
for the RDAT Bus.

As shown in Figure 5-6, RCVR SERIAL DATA is input to the RCVR Serial Shift Register. This register
is held in the load state by the negated state of E197R2 so no data is shifted into the register. When the
LINK receive channel senses data on the CI Bus, the Sync Character Detect Enable PAL also senses it.
If the PAL determines this is a valid time to receive a packet, it asserts ENA SYNC DET to the SYNC

ENA flip-flop. On the next RCVR CLK, the flip-flop outputs SYNC ENA to another flip-flop that asserts
E197-R2 to the RCVR serial shift register. The true state of E197-R2 enables the register by changing
its state from load to shift. RCVR SERIAL DATA is shifted into the register at the 70 MHz bit rate by
MDECODER CLOCK.
Figure 5-7 is a timing diagram of the RCVR Serial Shift Register.
The RCVR Serial Shift Register outputs 8-bit bytes onto a data bus and sends them to the RCVR input
register. The sync detector monitors the data looking for the sync character byte on the bus. When the
detector recognizes the sync character, it asserts E198-3 to the sync flip-flop. The next MDECODER
CLOCK that clocks the last bit into the register also sets the sync flip-flop. SYNC is asserted when the
sync character is in the shift register and not one clock pulse later.
When SYNC is asserted, the External Framer Shift Register switches the RCVR Input Register from
the hold state to the load state (for one clock pulse) every eight MDECODER CLOCK pulses. RCVR
SERIAL OAT A continues to shift into the RCVR Serial Shift Register. Every eight clock pulses a data
byte is present in the shift register and on the data bus. At this time, the External Framer Shift Register
switches the RCVR Input Register from hold to load. The next MDECODER CLOCK pulse loads the
data byte into the register. The 07 input to the External Framer Shift Register is tied high. Before the
assertion of SYNC, the framer register is in the load state and the R7 output is true. The true state of
the R7 output keeps the RCVR Input Register in the load state. When SYNC is asserted, the franler
shift register starts to shift. The 1 at R7 is shifted in and through the framer shift register. Every eight
MDECODER CLOCK pulses, the 1 is shifted through to the R7 output, switching the RCVR input register
to the load state for one clock pulse. As seen in Figure 5-7, a data byte is on the data bus when the
RCVR Input Register is loaded. The tinling for the first three bytes of a packet is shown in Figure 5-8.
5.2.1.7
RCVR CLK Generator
Figure .5-9 is a block diagram of the RCVR CLK Generator. The RCVR CLK is derived from a crystalcontroilled 70 MHz oscillator. The RCVR CLK pulses time and controls the operation of the receive
channel logic. When a signal packet is received, the RCVR CLK and packet bytes are synchronized by
the SYNC signal received from the Byte Framer.
The oultput from the 70 MHz oscillator is doubled to 140 MHz by a Frequency Doubler. (The 140 MHz
is used by the Manchester Encoder in the transmit channel.) The 140 MHz is divided down to 35 MHz
and aplPlied to a shift register consisting of four flip-flops. The shift register divides the 35 MHz by 4,
outputting RCVR CLK at a frequency of 8.75 MHz (time period equals 114.28 ns). Table 5-2 lists the
frequency and periods of the LINK clocks. The XMIT CLK discussed in Section 5.2.2.7 is included in
the tablle.

"1J

::D

-t

!:
z

"3:

o
o

c:
rm
Figure 5-6

Byte Framer Block Diagram
SYNC

.. D

EN A
SY NC DET -

RC VR ClK

SYNC
ENA
FF
(J)

SYNC

ENA -

D
SYNC
ENA
FF
(P)

E197-R2

~ lOAD/SHIFT
RCVR
SERIAL
SHIFT
REG
(P)

~C
MDECODER CLOCK ..
RCVR SERIAL DATA

ClK

(DATA<7:0>1

RDAT _
D
<7:0>

(DATA<7:1>1

RCVR
INPUT
REG
(P)

..- SHIFT IN

SYNC
DETECTOR
(P)

IE198-®- 0

SYNC
FF
(PI

SYNC

lOAD/SHIFT

..- D7
EXTERNAL
FRAMER
SHIFT REG
(P)

~ C

HOLD/lOAD

~ ClK

.. ClK
MDECODER CLOCK

SHIFT IN

NOTE: lETTER DESIGNATIONS IN PARENTHESES REFER TO ENGINEERING DRAWINGS CONTAINING CORRESPONDING lOGIC.
CX-956A

Figure 5-7 RCVR Serial Shift Register (Enable)
RCVR ClK
(8.75 MHZ)
ENA SYNC DET

SYNC ENA

E 197-R2

STATE OF RCVR
SERIAL SHIFT REG.

lOAD

------------------~~

SHIFT

MDECODER CLOCK
(70 MHZ)

RCVR SERIAL SHIFT REGISTER STARTS TO SHIFT.
MR·14460

:u
-I

C
Z

o
o

::D

-I

Z
::
o
o
c:

Figure 5-8

Byte Framer Timing Diagram

m
MDECODER
CLOCK· 70 MHZ
E198·3

:;.:
,
I

SYNC

STATE OF
EXTERNAL FRAMER

C)~
I I

I I
I I

I
I

SHIFT

0-1

I I

I
I I

I I

~I__________~rl~----------~rl~----------~rl~----------~~

E199·R7
STATE OF RCVR
INPUT REGISTER

LOAD

r1:
~---------'
I
HOLD

LOAD

0-1

n II

0--1

RDAT <7:0> _ _ _ _ _ _ _"--_ _ _ _ _ _ _-.JFPACKET LENGTH/TYPE BYTE=+=-PACKET LENGTH BYTE

•

SYNC CHARACTER BYTE IN SYNC DETECTOR.

•

LAST BIT OF SYNC CHARACTER BYTE CLOCKED INTO RCVR SERIAL SHIFT REGISTER

•

SYNC CHARACTEH BYTE IN RCVR SERIALSHIFT REGISTER.

•

FIRST BIT OF PACKET LENGTH/TYPE BYTE CLOCKED INTO RCVR SERIAL SHIFT REGISTER

0-1

TRUE DEST. BYTE

.,====

C) LAST BIT OF PACKET LENGTH/TYPE BYTE CLOCKED INTO RCVR SERIAL SHIFT REGISTER.

o
o
o

PACKET LENGTH/TYPE BYTE IN RCVR SERIAL SHIFT REGISTER.
EXTERNAL FRAMER SHIFT REGISTER STARTS TO SHIFT.
(DATA <7:0» CLOCKED INTO RCVR INPUT REGISTER.
TK·8612

PORT LINK MODULE

Figure S-9

RCVR CLK Generator

FF
(N)

35 MHZ

(N)

RCVR ClK

~~------------------------------------~ClK

(FROM BYTE

_ _ _ _S_Y_N_C_ _.....

FR.t~MER)

SYNC E153-~

D SYNC t--~---I

(N)

ClK

RCVR TEST ClK

EXT SYNC

35 MHZ
CHAR

(N)

[

DISABLE

D FF
FF

RCV~

(N)

' - - - -........ ClK

RCVR ClK

140 MHZ

OMHZ
:TAlOSC

70 MHZ

FREQ.
DOUBLER

140 MHZ

-;'-2
(T)

(T)

SYNC

(A)

70MHZ

..- TO MANCHESTER ENCO DER

rr
-

-;'-2
(T)

35MHZ

NOTE:
lETTEFl DESIGNATIONS IN PARENTHESES REFER TO
ENGINEERING DRAWINGS CONTAINING CORRESPONDING
lOGIC.
CX-1034A

Table 5·-2

LINK Clocks

Frequency (MHz)

Period (ns)

Clock

70.00

14.28

MDECODER CLOCK

35.00

28.57

8.75

114.28

RCVR CLK

8.75

114.28

XMIT CLK

5-15

PORT LINK MODULE

The shift register shifts a logic low through the flip-flop chain. When the low is in the rightmost flip-flop,
the other three flip-flops are set. Outputs from the three set flip-flops are ANDed together conditioning
the first flip-flop to reset on the next clock pulse and reinsert the low into the flip-flop chain. The cycle
is then repeated.
The left and right portions of Figure 5-10 illustrate the operation cycle of the shift register. (The center
portion illustrates the synchronization function.) Waveforms I, 2, 3, and 4 relate to the corresponding
points in Figure 5-9. Also shown are the MDECODER CLOCK and SYNC from the Byte Framer and
the time periods when the RDAT (7:0) bytes are in the RCVR Input Register. These three signals are
time related and are shown as they appear in the Byte Framer timing diagram (Figure 5-8). The 35 MHz
clock and the shift register wavefornls are time related to each other but are. independent of the Byte
Framer timing. The SYNC signal is used to synchronize shift register action with the data bytes from
the Byte Framer.
As shown in Figure 5-9, when SYNC is asserted, the 35 MHz clock that asserts E151-3 sets two sync
flip-flops. The next 35 MHz clock sets a pulse width flip-flop that negates E151-3, forming an E151-3
pulse to the shift register. The E151-3 pulse synchronizes the register by forCing a reset condition on
the first flip-flop and a set condition on the other three flip-flops. The next 35 MHz clock places the
register into the conditioned state, introducing a logic low into the first flip-flop. Regardless of where
the register is in its cycle, it is restarted at the beginning of the cycle. The assertion of SYNC followed
by the assertion of E151-3 is illustrated in Figure 5-10. Note that conditions forced onto the shift register
by the E151-3 pulse are clocked in by the next 35 MHz clock pulse (the first flip-flop is reset and the
other three are set). As seen in Figure 5-10, the logic low had reached the second flip-flop when the
register cycle was interrupted and reset to its starting point. From this point on the register cycles are in
synchronization with the byte frame. This results in the generation of RCVR eLK pulses approximately
centered in the tinle period when the packet bytes (RDAT < 7:0 » are in the RCVR input register.
l

5.2.1.8
CRC Check
The packet bytes on the RDAT A Bus, up to and including the four 8-bit CRe bytes, are input to the
CRC Checker. If no errors are detected by the checker, it asserts CRC STATUS to the Message Receive
State Logic, indicating reception of a valid, error-free packet.
5.2.1.9
Destination Compare
The node address and the complement of the node address are set into two 8-contact node address
switches. Outputs from these address switches permit a destination compare. The 8-bit output of the
complement node address switch is sent to the True Destination Compare Logic as CNODE ADDRESS
< 7:0 >; the 8-bit output of the true node address switch is sent to the Complement Destination Compare
Logic as NODE ADDRESS < 7:0 >.
True destination and complement destination bytes go from the RDAT Bus to both destination compare
logic circuits. The state PALs enable the compare logic outputs so that when the true destination byte is
on the RDAT Bus, the output of the True Destination Compare Logic is enabled. If the true destination
byte matches CNODE ADDRESS < 7:0 > from the complement node address switch, TDST CMP is
asserted indicating a true address match. Likewise, when the complement destination byte is on the
RDAT Bus, the output of the Complement Destination Compare Logic is enabled. If the complement
destination byte matches NODE ADDRESS < 7:0 > from the true node address switch, CDST CMP is
asserted indicating a complenlentary address match. Both true and complem.ent destination matches
assert DST CMP to the message receive and ACK Receive State Logic.
A polarity reversal in the compare logic applies the output of the true node address switch to the
Complement Destination Compare Logic and applies the output of the complement node address switch
to the True Destination Compare Logic. The output of the node address switches is coupled by XOR
gates to the compare logic. This allows swapping the true address and theconlplement address for
maintenance testing.

5-16

Figure 5-10 RCVR elK Synchronization

ole
r1

o
010
14

MDECODER
CLOCK (70 MHZ)
35 MHZ

SYNC

E153-9

EXT SYNC

E151-3

L...------II
I

L-

G)--.-J
RCVR CLK - - - - ,
(8.75 MHZ)
..._ _ _ _ _ _ _ _-1

~
o
o
e
o
o
o
o
o
o

RDAT<7:0>*

IN RCVR INPUT REG
FOR THIS PERIOD

)-+1RDAT<7:0>**}4
IN RCVR INPUT REG
FOR THIS PERIOD

LAST BIT OF SYNC CHARACTER BYTE CLOCKED INTO RCVR SERIAL SHIFT REGISTER_

* PACKET TYPE/LENGTH BYTE

** PACKET LENGTH BYTE

SYNC CHARACTER BYTE IN RCVR SERIAL SHIFT REGISTER.

"'tJ

lJ
-I

FIRST BIT OF PACKET LENGTH/TYPE BYTE CLOCKED INTO RCVR SERIAL SHIFT REGISTER.

LAST BIT OF PACKET LENGTH/TYPE BYTE CLOCKED INTO RCVR SERIAL SHIFT REGISTER.

:::-::

PACKET LENGTH/TYPE BYTE IN RCVR SERIAL SHIFT REGISTER.

FIRST BIT OF PACKET LENGTH BYTE CLOCKED INTO RCVR SERIAL SHIFT REGISTER.

c:
rm

LAST BIT OF PACKET LENGTH BYTE CLOCKED INTO RCVR SERIAL SHIFT REGISTER.
PACKET LENGTH BYTE IN RCVR SERIAL SHIFT REGISTER.
FIRST BIT OF TRUE DESTINATION BYTE CLOCKED INTO RCVR SERIAL SHIFT REGISTER.
MA-14461

PORT LINK MODULE

5.2.1.10
ACK Source Comparison
ACK source compare logic is used only during ACK packet reception. An ACK packet is transmitted
from its source acknowledging an infornlation packet transmitted from this node. While the infornlation
packet is in the transmit channel, the destination address is saved and sent to the ACK source compare
logic.
ACK Source Compare Logic receives inputs from the transmit channel and the RDAT Bus. When the
source byte of the ACK packet is on the RDAT Bus, compare logic output is sampled. ACK SOURCE
CMP is asserted if the source address of the ACK packet matches the destination address of the preceding information packet.
5.2.1.11
Receive Data Parity and Channel Output
The Receiver Output Data Register transfers data bytes from the RDAT Bus to the Packet Buffer. These
bytes are output from the register as RCVR DATA < 7:0 >. In addition, the data bytes are sent from
the RDAT Bus into a Receiver Data Parity Generator where odd parity is generated on each byte. A
ninth input to the parity generator (VALID RCVR PARITY) permits introduction of parity errors used for
maintenance testing. Parity generator output is applied to a parity flip-flop that outputs RCVR DATA
PARITY to the packet buffer.
Transmit Channel
5.2.2
The transmit channel takes the data on the XMIT DATA BUS < 7:0 > and puts it in a serial format for
transmission over the CI data paths. Refer to Figure 5-11.
5.2.2.1
Transmit Data Input
Transmit data (XMIT DATA < 7:0 » from the PILA is put into the transmit. channel by the XMIT Data
Input Latch and then transferred to the XMIT Data Bus as XMIT DATA BUS < 7:0 >.
This latch is transparent because the data on the bus follows the XMIT DATA. < 7:0 > as long as the latch
is enabled. ENA XMIT DATA LATCH from the Transmit Control Logic and XMIT CLK high enable the
XMIT data input latch. When XMIT CLK is low, this latch is disabled (closed).
5.2.2.2
Bit Sync, Sync Character, and Trailer Bytes
Bit synchronization bytes, trailer bytes, and the sync character byte reside in a 32 by 8 PROM. ENA
SYNC/TR from the Transmit Control Logic enables PROM output. A 5-bit address input to the PROM
selects the output bytes placed onto the XMIT Data Bus.
Figure 5-12 diagrams the 32 eight-bit locations in the Sync/Trailer PROM.
The five 8-bit sync bytes and the sync character byte are located in the upper area of PROM space. The
lower part of PROM is reserved for a possible header extension to 16 bytes (15 bytes of bit synchronization and one sync character byte). Note in Figure 5-12 that the bit sync bytes, starting at address 10101,
alternate with six trailer bytes starting at address 10100. PROM address bits < A4:Al > are obtained
from a binary counter enabled by ENA SYNC/TR CNT from the Transmit Control Logic. When this
signal is false, the counter is loaded with starting address 1010. When the signal is asserted, the counter
counts up from 1010, addressing every other PROM location. The least significant address bit of the
PROM (AO) is SEL TRAILER from the Transmit Control Logic. When SEL TRAILER is false, PROM sync
bytes are addressed. When SEL TRAILER is true, PROM trailer bytes are addressed.
Address bits < A4:A2 > are monitored and assert LAST SYNC to the Translnit Control Logic when
all three bits are true. As shown in Figure 5-12, this occurs when the last sync byte (sync byte 5) is
addressed.
:
When the binary counter has counted past the last trailer byte or past the sync character byte, it overflows
and asserts SYNC/TR GONE to the PAL Logic.
'
5-18

Figure 5-11 Transmit Channel Block Diagram
ENA SYNC/TR

XMIT DATA PARITY

ENA XMIT DATA PARITY

SEl TRAilER (AO)
(BiNARY 1010)
.-------~ D

XMITClK

SYNC/
TRAilER
PROM

BINARY
COUNTER
(E)

lOAD
ENA SYNC/TR
C
__
NT
_ _ _ _L-_~EN

XMIT ClK

(32X8)
(A4-A 1)

(A4-AO)

(E)

1--_---L_--,----1~ ADD R

XMITClK

...J~

lAST
SYNC

~X~M-I--T--" XMIT

~~~~~~~~~-~~-~D

XMIT
ClK

~~~:l . -_ _...,

SERIAL
SHIFT
REG

ENA XMIT DATA REG

ENA XMIT DATA lATCH
_X_M_IT_DA_TA_<_7:_0_>_~ D

XMIT
DATA
PARITY
CHKR
(E)

LATCH
FF
(B)
ClK

1~6%~TR

I,-C_l_K_ _ _

. -_ _...,TDATA
PARITY

1-----1~ D

>--l..---..--~ D

XMIT
DATA
REG
(E)

(R)

70
MHZ

SHIFT/lOAD

r----1

70MHZ

~ g~~ERATOR
L ___ ...J

i-j- - - - - - "

140 MHZ

ENA ACK TYPE
ENA ACK CDST

PAL
STATE
lOGIC
(l)

BUSY

MR STATE E
(C)

XMIT ClK

(E)

RDATA REG<7:0>

RCVR ClK

XMIT
ClK
GEN

ACK
TYPE
lOGIC

ClK ACK DST REG

IN~

E18311

XMIT ClK

ENA ACK SRC

B DRIVER ENA

-----1-+~ ClK

ClK

-=C~N.:..:O:..:D:..:E:...:A~D:...:D:...:R:..:.-E:...:S:...:S~<.:..c7-,:O:":'->_ _ _ _ _--I( E)

A DRIVER ENA

SERIAL
DATA
FF
(T)

D
MANCHESTER
ENCODER
FF
(T)

ME
DATA

XMIT
ECl
DRIVERS

CIB
XMIT

}

TOCI
BUS

D
COMPLEMENT
ACK
DESTINATION
REG
(D)
elK

D
DESTINATION
ADR REG
(D)

ClK
ClK DST
ADR REG

ENA ACK TDST

"'U

TRUE ACK
DESTINATION
REG
(D)

::0

-t

z
::
o
o

MX STATE I

"
C

NOTE: lETTER DESIGNATIONS IN PARENTHESES REFER TO ENGINEERING DRAWINGS CONTAINING CORRESPONDING lOGIC.

CX-961A

rm'

PORT LINK MODULE

Figure 5-12

Sync/Trailer PROM Space
(HEX)

1
1

SYNC CHARACTER

(96)

TRAILER

(00)

BIT SYNC BYTE 5

(55)

1
0

-0
0

TRAILER

(00)
(55)

BIT SYNC BYTE 4

TRAILER

(,00)

BIT SYNC BYTE 3

(55)

START HERE
FOR HEADER ......... 1

0
0

TRAILER

(00)

BIT SYNC BYTE 2

(55)

TRAILER

(00)

o
o

BIT SYNC BYTE 1

(55)

TRAILER

(00)

BIT SYNC BYTE

(55)

(00)

START HERE -... 1
FOR TRAILER
1

TRAILER

BIT SYNC BYTE

(55)

o
o

TRAILER

(00)

BIT SYNC BYTE

(55)

TRAILER

(00)

BIT SYNC BYTE

(55)

0
0

-1.. ..Q..

TRAILER

(00)

BIT SYNC BYTE

(55)

TRAILER

(00)

BIT SYNC BYTE

(55)

o
o

TRAILER

(00)

-1.. .1-

BIT SYNC BYTE

(55)

TRAILER

(00)

BIT SYNC BYTE

(55)

TRAILER

(00)

100

BIT SYNC BYTE

(55)

010

TRAILER

(00)

001

BIT SYNC BYTE

(55)

TRAILER

(00)

0
0

t~A2
t!=:~

~-----A3
1---_ _ _ _ _ _

A4
TK-8598

5-20

PORT LINK MODULE

5.2.2.3
ACK Packet Inserts
The LINK inserts the packet type, source, and destination bytes into the ACK packet. When information
packets are transmitted, the K.pli inserts these bytes and LINK hardware is not involved.
5.2.2.3.1
Packet Type Byte
The packet type byte is obtained from the ACK Type Logic outputting a one in bit position seven to
signify an ACK (or NACK) packet. Bit position six is a function of BUSY, a signal derived from the
packet buffer RCVR BUFFERS FULL. BUSY is asserted when the receive buffers in the PILA are full
and cannot accept the information message just received. This causes a one in bit position six signifying
NACK packet transmission. If BUSY is false, bit position six is zero indicating ACK packet transnlission.
Remaining bits in the ACK type logic < 5:0 > are always zero.
5.2.2.3.2
Source Byte
The ACK source byte is the complement node address (CNODE ADDRESS < 7:0 » obtained from the
complement node address switch on the LINK. This source byte is gated onto XMIT Data Bus by ENA
ACK SRC from the PAL State Logic.
5.2.2.3.3
Destination Bytes
ACK destination bytes are derived from the source byte of the associated information packet. This
source byte is taken from the RDAT Bus in the receive channel and clocked into the Destination Address
Registers !by CLK ACK DST REG. RDAT REG <7:0> is entered directly into the True ACK Destination
Register and the inverse is entered into the Complement ACK Destination Register. The true destination
byte and the complement destination byte are gated to the XMIT data bus by ENA ACK TDST and ENA
ACK CDST, respectively. PAL State Logic asserts the gating signals for inserting the bytes into the ACK
packet at Ithe appropriate tim.es.
5.2.2.4
Destination Address Register
This regislter saves the destination address of the infonnation packet being transferred. CLK DST ADR
REG is asserted at the correct tinle to clock the true destination byte into the register. The destination
byte is compared with the source of the ACK packet in the receive channel. A match indicates the
correct node responded to the message transmission.
Transmit Data Parity Check
5.2.2.5
Data from: the BUS TDATA Bus is applied to the XMIT Data Parity Checker where packet bytes are
checked. Parity bits, XMIT DATA PARITY, sent from the packet buffer, are applied to a latch flip-flop
as TDATA PARITY LATCH. An OR feedback network holds TDATA PARITY LATCH true for both
transmissions of XMIT CLK, allowing the latch flip-flop to set (if parity is one). The latch flip-flop
outputs the parity bit (TDATA PARITY) to the parity checker. Parity is then checked when ENA XMIT
DATA PARITY is asserted and enables the parity checker output. TDAT A PARITY ERROR is asserted
to the Message State Logic when a parity error occurs.
5.2.2.6
CRC Generation
Packet bytes on the XMIT Data Bus, starting with the packet type byte and ending with the last byte of
the body, are input to the CRC Generator. The generator produces a 32-bit CRC longword unique to
the packet: being transmitted. This longword is inserted into the packet one byte at a time at the end of
the packet body.

5-21

PORT LINK MODULE

5.2.2.7
XMIT ClK Generator
Figure 5-13 is a block diagram of the XMIT CLK Generator. XMIT CLK is derived from a 70 MHz input
received from a crystal oscillator network in the RCVR CLK Generator. The Transmit Clock Generator
produces XMIT eLK pulses at 8.75 MHz (period = 114.28 ns). It also outputs an RO pulse to load the
XMIT Serial Shift Register from the TDATA Bus.

Figure 5-13

XMIT ClK Generator Block Diagram
RO

XMIT TEST elK
XMIT elK DISABLE
XMIT elK

~--,----...

>------10
XMIT
elK
FF
70MHZ

XMIT
FRAMER
SHIFT
<R7:RO>
REG
70 MHZ

elK

<R6:RO>

elK
SHIFT IN

Mll-14464

Timing for the XMIT eLK Generator and the XMTR Framer Shift Register is illustrated in Figure 5--14.
The XMTR Framer Shift Register is clocked at 70 MHz with an 8-bit parallel output < R7:RO >. The
inverses of bits < R6:RO > are ANDed so that when all seven bits are false, a one is input to the Framer
Shift Register. This one is clocked up to the R7 output, at which time another one is generated for the
Framer Shift Register. Figure 5-14 illustrates the time relationship of XMIT eLK relative to Framer Shift
Register outputs.
R6 and R7 from the Framer Shift Register are applied to the D input of the XMIT eLK flip-flop causing it
to set for two 70 MHz clocks. Output of the flip-flop is XMIT CLK. For maintenance testing, the output
of the XMIT eLK flip-flop can be disabled and an xMIT TEST CLK substituted.

5-22

Figure 5-14 XMIT eLK Generator Timing Diagram
70 MHZ

(J1

.JRoL
I
I
JR1L
I
I
.JR2L
I
JR3L

XMIT
FRAMER
SHIFT
REGISTER

I
I

...JROL
I
I
I

_1R4l_

JR5L

JR1L
I
JR2

I
I

I
I
I

I
I
o IN SHIFT
(E 186-1)

(E173-3)

XMIT elK

~~IIFTTS~:~Al

_ _ _ _ _ _ _ _ _ _ _ _ _ _----'

I
...
1-------"~-----114.28 N S - - - - - - - - - - t
F28.6
1---.....;.1----,

----------------~

NS===i

~--------------------~

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~fLoAol'_

______~SH I.;...FT~
......

_______

__lfLOADl

SHIFT

CX-1035A

:0
-4

C
Z

"o==
o

c:
r-

PORT LINK MODULE

5.2.2.8
Parallel To Serial Data Conversion
Eight-bit data bytes from the TDATA Bus are input to the XMIT Serial Shift Register. Every eighth 70
MHz clock cycle RO from the XMIT CLK Generator is asserted, loading the shift register with a data byte
from the TDATA Bus. After loading, the register returns to the shift state, sending out the data byte a
bit at a time as XMIT SERIAL DATA. As the last bit is shifted out, RO is asserted again, loading the next
packet byte into the serial shift register. Figure 5-14 illustrates load and shift timing of the serial shift
register.
XMIT SERIAL DATA is applied to a serial data flip-flop clocked by 70 MHz. Output fronl this flip-flop
(E183-11) is sent to the Manchester Encoder.
5.2.2.9
Manchester Encoder
The Manchester Encoder modulates the serial data with the Data Bit Rate Clock, producing the signal
format placed on the CI Bus. Encoder logic XORs E183-11 (serial data flip-flop output) with the 70 MHz
clock. Output of the XOR gate is inverted and applied to the Manchester Encoder flip-flop. This flipflop is clocked at 140 MHz or twice the data rate, as required for phase encoded data (Section 5.2.1.4).
Output of the encoder flip-flop (ME DATA) is the packet data ready for transmission onto the CI Bus.
Manchester encoder timing is illustrated in Figure 5-15. E183-11 output of the serial data flip-flop is
shown for the example data bits. After E183-11 is XORed with the 70 MHz dock, the inverse of the
XOR output is used for the encoder flip-flop input. Clocking the encoder flip-flop at 140 MHz results
in the ME DATA waveform. ME DATA signal format is identical to that of the serial data received from
the CI Bus in Figure 5-5.
5.2.2.10
XMIT ECl Drivers
Figure 5-16 diagrams an ME DATA transfer to the CI Bus by the XMIT ECL drivers. Note the XMIT
drivers are divided into two channels feeding the CI Bus A and B paths. The K. pli selects the path using
the Transmit Control Logic to enable the driver in the selected channel.
ME DATA is routed to drivers in both channels and through coupling transformers to the CI Bus as CIA
XMIT and CIB XMIT. When the Transmit Control Logic selects channel A, signal A DRIVER ENA is
asserted (B DRIVER ENA false) and in turn asserts E151-1 from the channel A AND gate. Assertion of
E151-1 causes outputs from both channel A XOR gates and enables the channel A driver. In the same
manner, assertion of B DRIVER ENA asserts E151-2 output of the channel B AND gate and enable the
channel B driver.
Redundancy in driver enabling logic prevents a single component failure from causing simultaneous
enabling of the A and B channels. If, due to a logic component failure, the outputs of both channel A
and channel B are asserted (E151-1 and E151-2 true), one of the channel A XOR gates and one of the
channel B XOR gates are inhibited. The enabling inputs to the channel drivers are held high inhibiting
the drivers and isolating the node from the CI Bus. Operation of ECL logic is described in Section 5.2.1.3.
During internal maintenance loop operation, the Port Control Logic disables both output drivers. In this
state, ME DATA from the transmit channel is looped back into the receive channel. The port asserts INT
MLOOP, inhibiting both E151 AND gates and shutting off the output drivers. In addition, signal lines
into both A and B channel drivers are held high by INT MLOOP inhibiting any signal data variations
into the drivers.
5.3 eRC GENERATOR AND CHECKER
The LINK is responsible for cyclic redundancy generation and checking. This eRC logic is cornman to
both the receive and transmit paths of the CI Bus. Figure 5-17 is a block diagram of the CRC Generator
and Checker.

5-24

Figure 5-15

Manchester Encoder Timing Diagram

DATA BITS

70MHZ

E 183-11

(J1

LIL-J

XOR

r--LJI

XOR

'----------lIn
I

II"-------iLJ
I

I
I

LsI

140 MHZ

I
ME DATA

~
I

0
1

LsI

"'BIT CELL = 14.28 NS

CX-965A
"U

::D

"o3:
o

c:
r-

m·

PORT LINK MODULE

Figure 5-16

XMIT Eel Drivers

CIA XMIT

INT MLOOP

III'

ME DATA
CIS XMIT

NOTE:
THE LOGIC IN THIS FIGURE IS CONTAINED
ON SHEET T OF THE ENGINEERING DRAWINGS.
MR-14466

5.3.1
eRe Generator
Packet bytes from the XMIT Data Bus in the transmit channel are input to the eRe Input Multiplexor
as XMIT DATA BUS <7:0>. Transnlit Control Logic asserts XMIT CRC 'ENA to the multiplexor for
selecting the bytes from the transmit channel. The multiplexor output is sent to the CRC Input Register
that outputs the bytes as NEW DATA < 7:0 >.
Using an XOR gate, NEW DATA < 7:0 > is applied to a CRC lookup table. Lookup Table Logic is
applied to a CRe Register that outputs CRe < 31:00 >. Note the CRe Register initially is preset to all
ones. CRe <31:00> is looped back into the Lookup Table Logic in two parts: the first three bytes (CRC
< 23:00 » are applied directly to the logic, and the uppermost byte (eRe <31 :24» is XORed with the
new input byte from the CRC Input Register. Thus, new data bytes are continuously integrated into the
compilation of the previous data bytes. In this way, the CRC-generated longword is always a function
of the packet bytes received from the transmit channel.
The CRe longword is also coupled by four sets of drivers to the BUS TDATA Bus in the transmit
channel. When enabled, each driver places a byte onto the BUS TDAT A Bus to insert a eRC byte into
the packet being transmitted. These drivers are enabled from a CRC byte counter that receives a SHIFT
IN input (E29-5) when the last packet body byte is on the BUS TDATA Bus. Input is shifted through
the counter by eRC CLOCK asserting RO through R3 in sequence. RO through R3 are enabled at the
appropriate time through the PAL State Logic.

5-26

Figure 5-17 CRC Generator/Checker

CRC STATUS

r---.... CRC TABLE
CRC <31:00>

.-<_3_'_:00_>_...... 0

XMIT DATA
BUS <7:0>

CRC
lOOKUP
TABLE

o CRC
ROAT REG <7:0>

eRC
REG
(U)

(H)

INPUT
REG

ENA CRC TABLE

elK

eRe <31 :24> V~_ _ _.--_.::.BU.::.S:::.....:..T.::.O:...:A.:..:TA:....:-<.;::7~:0:::>:....,.

CRe <23:16>

V'>---~

CRC <15:08> V>--+-+--I

(U)

CRC <07:00> V>-+-+-+-'
ENA XMIT
DATA REG
(CRC ClK)

(CRC ClK)

U1
!

-...;J

lOOP
MX STATE

E29-5 (START
eRe BYTES OUT)
ENACRe 1 OUT

(U)

MR
STATE H

e
MR
STATE H

AR
STATE G

VALID ReVR
(e)

STATUS

ENAeRe 3 OUT
(e)

MR STATE B

MAX eRC 3

AR STATE B

FF
(U)
AR STATE D
AR STATE H
MR STATE H
B

MR CRC 3

ICCS PATH SELECTED

K
ClR

PORT LINK MODULE

In addition, ENA XMIT DATA REG must be false before the RO AND gate is enabled to place the first
eRe byte (eRe < 7:0 » onto the BUS TDATA Bus. This ensures the BUS TDATA Bus is isolated from
the XMIT Data Register before eRC logic is connected to the bus (Figure 5-11). Likewise, each AND
gate must be disabled in sequence before the next AND gate can be enabled, ensuring only one source
drives the TDATA Bus at a time. CRC Generator Logic is clocked by CRC CLOCK (seen as XMIT CLK
during the transmit states).
5.3.2
CRC Checker
Packet bytes from the RDA T Register Bus in the receive channel are input to the CRC Input Multiplexor
as RDAT REG <7:0>. Transmit Control Logic negates the XMIT CRC ENA input to the multiplexor
selecting the bytes from the receive channel. The multiplexor output is sent to the CRC Input Register
which outputs the bytes as NEW DATA < 7:0 >.
eRC logic generates the CRC longword as described in previous sections. The last four bytes input to
the CRe become the CRe longword generated for the packet. When the CRe longword is entered into
the CRC lookup table, if the packet is error free, an output of DEBB 28E3 (hex) results. The longword
value is checked by a CRC comparator that asserts CRC STATUS if the proper value is obtained.
5.4 ARBITRATION
To prevent collisions on the bus, only one node at a time should transmit. When the K.pli commands a
node to transmit an information packet, the LINK enters an arbitration process to gain control of the bus.
This process is not necessary for ACK packet transmission as it is assumed the bus has already been
acquired for such transfers. As explained in following sections, bus acquisition by a node is accomplished
by taking turns between the competing nodes through the arbitration process .. No hardware or software
control allows a node to seize the bus and exclude other nodes.
5.4.1
Arbitration Process
In the arbitration process, a node counts down a specific number of bus quiet slots. A quiet slot is a
time period approximately 800 ns in length with no activity on the bus. This is sufficient time for a
one-way trip on the bus and to detect a carrier presence. This quiet slot is the'time period allocated for
an arbitrating node to detect transnlission by another node.
When a node conlpletes its quiet slot countdown (reaches zero), it wins the bus and may transmit. If
the node detects bus activity before the countdown is completed, the arbitration process is interrupted
and restarted when the bus is again quiet. When several nodes are competing for the bus, all arbitration countdowns other than that of the winner are interrupted. All losing nodes restart countdowns
simultaneously when the bus is again quiet, placing them in synchronization with each other.
5.4.2
Arbitration Algorithm
The arbitration countdown is a dual count round robin algorithm giving the the bus to the lower nUlltbered node when more than one node is attempting transmission. This algorithm is illustrated in
Figure 5-18. Other nodes, however, can each access the bus before the winning node can gain the bus
again. This process is implemented by the number of quiet slots each node must count.
The number of quiet slots counted down is determined by the number of the node attenlpting transmission or by the number of the node that last had the bus. A node may count N + I + 1 quiet slots
or I + 1 slots where:
N = 16 (maximum number of allowable nodes)
I = node number

5-28

Figure 5-18

CI Bus Arbitration Flowchart

LOAD N+I +1 INTO
COUNTDOWN
COUNTER

(J1

N
...0

'til

...r:u

o
C

c:
rm·
CX-1036A

PORT LINK MODULE

When a node begins arbitration, it counts N + I + 1. If the countdown is interrupted, the node
determines the number of the winning node. When the winning node is a higher number, the node
restarts an N + I + 1 countdown. If the winning node is a lower number, the node restarts its countdown
at I + 1. When several nodes are competing for the bus, the lowest numbered node wins the bus but
it must count down N + I + 1 to win the bus again. Higher nodes restart arbitration with the I + 1
countdown, and all win the bus before the first winner can once more gain the bus. As each node wins
the bus, the N number is added to its countdown value and the next higher numbered nodes wins the
bus. Thus, each competing node has a turn at the bus, starting with the lowest numbered node and
going to the highest. Note whenever a node completes its co.untdown (reaches zero), it checks whether
the receiver is free (ALT PATH BUSY false) before transmitting. Transmission from a node does not
occur unless the node receiver is free to accept the ACK response. Although the node completed its
countdown and gained one path on the bus, the node receiver could be busy receiving a packet on the
other path. When this happens, the transl11ission is delayed by loading 16 into the node counter and
continuing the countdown.
5.4.3
Arbitration Logic
Figure 5-19 is a block diagram of the Arbitration Logic. Prior to receiving a transmit command from
the K. pli, the LINK is in the idle state (MX STATE A). In this state, LOAD ARB COUNT true loads the
arbitrator for the quiet slot countdown. The basic slot counter is loaded with 1001 2 ; the down counter
is loaded with N + I + 1.
This down counter contains two sections: the lower four bits and the fifth bit. The four-bit section is
loaded with the node address (NODE ADDRESS < 3:0 ». The fifth-bit section is loaded from an N load
multiplexor that supplies the N term in the arbitration countdown expression. Multiplexor select inputs
are shown in Table 5-3.

Table 5-3

N Load Multiplexor Selection

Select Code
MX STATE A

SEL PATH CARRIER

Input Selected

True

False

True (load arb.)

N Load FF

False

Latch FF

X = Does not matter what the input is
While the LINK is idling in MX ST ATE A, the multiplexor selects the + V input to load a one into
the fifth-bit section of the down counter. The one represents the N term in the N + 1 countdown
expression. When the LINK shifts to MX STATE -H, LOAD ARB COUNT negates and the arbitrator
starts its countdown. The slot counter is clocked from 1001 2 by XMIT CLK and outputs BASIC SLOT
after seven clock pulses. BASIC SLOT is looped back, reloading the counter with 1001 2 and the cycle
is repeated. The time period of XMIT CLK is 114.28 ns so BASIC SLOT is asserted every 800 ns (7 X
114.28).
Each time BASIC SLOT is asserted, it enables the four-bit section of the down counter which is deere·
mented by XMIT CLK. When this section of the down counter reaches zero, the next assertion of BASIC
SLOT asserts the carry (CRY) output decrementing the fifth-bit section. If the fifth-bit section contains a
one (N + I + 1 count), the one becomes a zero, the four-bit section becomes all ones, and the countdown continues. If the fifth-bit section contains a zero (I + 1 count), the CRY output goes true asserting
5-30

Figure 5-19 CI Bus Arbitration Block Diagram
FORCE CARRIER

(K)

CARRIER DET B

~l~O~A~D~A~R~B~C~O~U~N~T______~__________________~

SEL PATH CARRIER
D

CARRIER
FF
(M)

lATCH
FF

XMIT ClK

MX STATE B

(K)

MX STATE A
CARRIER DET A

SET
CNODE ADDRESS(3:0>

XMIT ClK

N
LOAD
FF
(K)

N
LOAD
MUX
(K)

------______________

~~~~~~~~----~A

U"1
I

VJ
.....

1001

----i~IN

XMIT CLK

A<B
NODE
ADDR
CMP

IT<1 PLUS 1>

(K)

BASIC
SLOT
COUNTER

AlTPATHBUSY

DOWN
ADD <3:0>
COUNTER
<3:0>

(K)

ClK
lOAD

CRY
DOWN
COUNTER
LOAD <4>

ARBC = 0

XMIT ClK

ARB
FF
(K)

(K)

ClK

-0

MX STATE B

:D
-I

DlYD HDR TO
RCVR ACTIVE

NOTE: LETTER DESIGNATIONS IN PARENTHESES REFER TO ENGINEERING DRAWINGS CONTAINING CORRESPONDING lOGIC.
CX-966A

"3:

o
c

c:
r-

PORT LINK MODULE

ARBC = 0 (arbitration counter equals zero) setting the ARB flip-flop on the next XMIT CLK cycle. If the
alternate bus path is not busy (ALT PATH BUSY false), ARB and ARB OK assert indicating a successful
countdown and causing the LINK to shift to MX STATE C.
Note that when the counter reaches zero, one more assertion of BASIC SLOT is required to assert the
CRY output and cause ARB to go true. This additional assertion of BASIC SLOT represents the one
term in the two countdown expressions.
5.4.3.1
Arbitration Countdown
If a carrier from another node is detected during the countdown, the arbitrator is reloaded and the
countdown restarted. The node address comparator determines whether the interrupting (winning)
node is a higher- or lower-numbered node to determine the new countdown value. (See Section 5.4 for
a general description of the arbitrator.)
5.4.3.1.1
LINK Arbitration Comparator
The comparator compares the node address with ARB CMP ADD < 3:0 > from the four-bit section of
the down counter and asserts LT or less than (I PLUS 1) if this node number is less than the winning
node number. For example, assume this node is number five and the winner is node number two.
ARB CMP ADD < 3:0> is counted down to three. The comparator A input is, greater than the B input;
therefore, LT (I PLUS 1) is false. This node is not less than the winning node. If the winning node is
node seven, for instance, ARB CMP ADD < 3:0 > is 14 (as the fifth bit was decremented). Comparator
A input is less than the B input; therefore, LT (I PLUS 1) is true. This node is less than the winning
node. The LT (I PLUS 1) signal determines which countdown value is reloaded into the down counter
for the next countdown.
5.4.3.2
Carrier Detection
When a carrier is detected (interrupting the countdown), CARRIER DET A or CARRIER DET B is asserted. If the carrier is detected on the SEL TP ATH selected by the LINK Control PAL, SEL PATH
CARRIER is asserted. In turn, this asserts LOAD ARB COUNT and reloads the basic slot counter and
both sections of the down counter. The fifth-bit section of the down counter is again loaded from the
N Load Multiplexor. However, in this case the multiplexor selects its input from the N Load Flip-Flop
(Table 5-3)
During the countdown, SEL PATH CARRIER false holds the N Load Flip-Flop reset. When this signal
asserts, the J input to the flip-flop checks LT (I PLUS 1) from the node comparator. If LT (I PLUS 1)
is true (this node less than the winning node), the flip-flop is set and a one is loaded into the fifth-bit
section. If LT (I PLUS 1) is false, the opposite occurs. Output fronl the N Load Multiplexor is latched
in a latch flip-flop. When SEL PATH CARRIER is negated, the N Load Multiplexor selects the output of
the latch flip-flop, thus maintaining the fifth-bit selection after SEL PATH CARRIER is negated.
In the case where the winning node is greater than this node, LT (I PLUS 1) is false and the fifth bit
section of the counter is loaded with a zero. Likewise when node zero is bepten by node 15, it must
appear that it was beaten by a lower node and restart its countdown as I + 1. However, in this case, LT
(I PLUS 1) is true. Logic in the N Load Flip-Flop forces a zero into the fifth bit section of the counter
when node zero is beaten by node 15. When this is node zero (CNODE ADDRESS < 3:0> equals all
ones) and it has just been beaten by node 15 (ARB CMP ADD < 3:0> equalS all ones), the AND gate
transferring LT (I PLUS 1) into the N Load Flip-Flop is inhibited and the flip-flop remains reset. A zero
is reloaded into the fifth-bit section of the down counter and node 0 does an I + 1 countdown.

5-32

PORT LINK MODULE

5.4.3.3
Receive Channel Busy - Arbitration Condition
If the LINK receive channel is busy on the the alternate bus path, RCVR ACTIVE is true, causing ALT
PATH BUSY true. This condition inhibits the assertion of ARB and loads 16 into the down counter.
AL T PATH BUSY loads only the fifth-bit section of the down counter and the four-bit section remains
enabled in count mode. ALT PATH BUSY generates the 16 by disabling the N Load Multiplexor causing
a zero output into the fifth-bit section. With the countdown successfully completed, the four-bit section
. is all zeros. As the fifth-bit section is loaded with a zero, the four-bit section is decremented to all ones.
Thus, when the entire counter is enabled again, it contains a count of 16.
5.4.3.4
Successful Arbitration Inhibited
The true state of RCVR ACTIVE inhibits a successful arbitration by reasserting AL T PATH BUSY. RCVR
ACTIVE negates after the message on the alternate path has been received. The transmission that is
arbitrating on the bus, however, still cannot be allowed because the transmit channel must be used to
transmit an ACK response. At this point in the message, the receive state sequence is state I. Hence,
MR STATE I keeps ALT PATH BUSY true inhibiting the assertion of ARB.
The signal DLYD HDR TO being false also inhibits successful arbitration. This signal is false if a transmission is occurring from this node (A DRIVER ENA or B DRIVER ENA true).
5.5 LINK FUNCTIONS
LINK function cornmands are carried from the K. pli by four LINK control lines (LINK CONTROL
< 3:0 » and eight port data lines (PORT DATA < 7:0 » (Figure 5-20). The K. pli asserts SELECT when
a valid function exists on the LINK control lines. A function decoder decodes the LINK control lines
and outputs the specific function commanded by the K.pli. LINK function conlmands are:
•

>eMIT FCN-initiates arbitration and transmission on one of the CI paths. The CI path used is
selected by port data bit seven (0 = path A; 1 = path B).

•

RESET XMIT STATUS-resets transmission status bits at the end of a transmission operation.

•

ABORT XMIT FCN--aborts a currently active transmission operation.

The LINK Mode Control PAL receives the LINK control and port data lines from the K. plio The port
data lines carry control information related to the function commands and specify various maintenance
functions for the LINK.
5.5.1
LINK Control Information and Maintenance Functions
LINK control information and maintenance functions are described as follows:
•

XMIT PATH B SEL-This signal selects the CI path associated with the XMIT FCN command.

•

RCVR A ENABLE-This signal enables path A in the LINK receiver making the node accessible
on CI path A.

•

RCVR B ENABLE-This signal enables path B in the LINK receiver making the node accessible
on CI path B.

•

EXT MLOOP-This maintenance function allows the LINK to receive its own transmission by
looping on the selected CI path.

•

INT MLOOP-This maintenance function allows the LINK to receive its own transmission
by looping inside the transmit drivers and input receiver detectors. This operation does not
interfere with the CI operation of other nodes.

•

FORCE CARRIER-This maintenance function causes the LINK to see a detected carrier.

•

FORCE ARB-This maintenance function causes the LINK to force a successful arbitration.

5-33

....

"o3:
C

c:
rm

Figure 5-20 LINK Functions
FORCE CARRIER

PORT DATA <7:0>

SWAP TRUE/COMP ADR

LINK CONTROL<2:0>

RCVR A ENABLE

LINK CONTROL 3
SELECT

LINK
MODE
CONTROL
PAL

RCVR B ENABLE
VALID RCVR PARITY
EXT MLOOP

(M)

LOOP
INT MLOOP
FORCE ARB
XMIT PATH B SEL

......- - - - - - - - - - -... D FF
(M)

XMITCLK

SEL TPATH B

FORCE PATH B

SEL TPATHA

FORCE PATH A

XMIT FCN
FUNCTION
DECODER

RESET XMIT STATUS

(M)

ABORT XMIT FeN

ARBOK

NOTE: LETTER DESIGNATIONS IN PARENTHESES REFER TO ENGINEERING DRAWINGS CONTAINING CORRESPONDING LOGIC.
CX-967A

PORT LINK MODULE

•

VALID RCVR PARITY-This maintenance function generates parity errors in the receive channel.

•

SWAP TRUE/COMP ADR-This maintenance function causes the true and complementary
address sources to be swapped, resulting in an address mismatch.

SEL TPATH A or SEL TPATH B, the transmission path select signal, asserts a corresponding FORCE
PATH signal after the node successfully arbitrates for the bus (ARB OK true). The FORCE PATH signal
enables the corresponding path in the receive channel preparatory to ACK response reception.
5.6 Ll[NK INTERFACE SIGNALS
Figure 5-21 shows the LINK interface signals, mostly used to interface with the PILA. Figure 5-22 and
Figure 5-23 are flow diagrams of typical error-free transn1it and receive operations. Interface signals
are preceded by an asterisk, and some other signals, internal to the LINK, are included to complete
the flow. These two flow diagrams utilize most of the LINK interface signals and explain their basic
functions. Interface signals not included in the diagrams are the three clocks (XMIT CLK, PORT CLK,
RCVR eLK), the node address (NODE ADDRESS < 7:0 », and INITIALIZE, explained as follows:

•

PORT eLK-received from the PILA. Used in both the PILA and the LINK.

•

XMIT eLK-generated in the LINK. Used in both the PILA and the LINK.

•

RCVR eLK-generated in the LINK. Used in both the PILA and the LINK.

•

NODE ADDRESS < 7:0 > - Sent to the K.pli via the PILA and inserted into the transmitted
packet as the source byte.

•

INITIALIZE - used for system initialization.

5.7 LINK OPERATING STATES
The following descriptions of the four LINK operations utilize the state diagrams contained in the
engineering drawing set. Various states are shown in the diagrams as circles. A path looping back into
a circle holds the LINK in that state as long as the signal condition in that loopback path is true. The
LINK goes to its next state if the signal condition shown in the connecting path to the next state is true.
Where no loopback paths are shown, the LINK stays in that state for one clock pulse, perforn1s the
indicated task(s) and proceeds to the next state.

Also included in the drawing set is a XMIT/RCVR state flow diagram. This diagram indicates flows for
the following:
•

Message transmission

•

ACK reception operation

•

Message reception

•

ACK transmission operation

•

Use of PALs

•

Sequence shifts from one PAL to another during operation execution

In addiition, this diagraln indicates two basic points in LINK operations:
•

An ACK receive sequence is part of the message transmit sequence (sequence is not complete
until the ACK receive sequence is done)

•

An ACK transmit sequence is part of the message receive sequence (sequence is not complete
until the ACK transmit sequence is done)

5-35

PORT LINK MODULE

Figure 5-21

LINK Interface Signals

INITIALIZE
SELECT
LINK CONTROl<3:0>
PORT DATA<7:0>
PORT
BUFFER

(PILA)

-..

XMIT DATA ENABLE

XMIT DATA<7:0>
XMIT BUFFER EMPTY

-..
-

XMIT ATTENTION

r ... RESET XMIT STATUS
_L -II- XMIT FCN

- , - - ..... XMIT PATH B SEl
1---" RCVR A ENABLE
I

-.. I

, - - ..... RCVR B ENABLE

XMIT STATUS<7:0>

I
I

RCVR A ENABLE

RCVR B ENABLE

LINK

...J

VALID RCVR DATA
RCVR BUFFERS FUll
RCVR DATA<7:0>
RCVR DATA PARITY
PACKET lENGTH
RCVR PACKET END
VALID RCVR STATUS

-...

CRC STATUS
ICCS PATH B

PORT ClK

-..

NODE ADDRESS 7:0>

XMIT DATA PARITY

..--

-..

XMIT ClK

;

RCVR ClK

CX-968A

5-36

PORT LINK MODULE

Figure 5-22

Interface Flow Diagram - Transmit Operation

•
•
•
•
•
•
•
•

Start

CRC bytes are
inserted in the to
packet.

*SELECT
A valid function exists on
LINK CONTROL lin·es.
*LlNK CONTROL<3:0>
XMIT FCN
Port commands
a transmit function via
LINK CONTROL lines.
*PORT D.A.TA<7:0>
XMIT PATH B SEL
K.pLi selects transmit path
via PORT DATA lines.

•
•
•
•

Link arbitrates for
the selected bus.

Trailer bytes are
inserted in the
packet.

SYNC/TR GONE
Packet has been
transmitted.

WACK
Wait for ACK response.

ACK RCVD
ACK response has been
successfu Ily received.

Link transmits header (bit
sync bytes and sync
character byte).

*XMIT DATA ENABLE
Link is ready to receive
data from the PI LA.

*XMIT ATTENTION
An ACK response has
been detected.

*XMIT STATUS<7:0>
Transmit status
available to the K.pLi.

*XMIT DATA<7:0>
*XMIT DATA PARITY
Packet bytes (with
parity) are transferred
from the PI LA to the
link.

*LlNK CONTROL<3:0>
RESET XMIT STATUS
Command (via LI N K
CONTROL lines) to
reset most of XMIT
ST A TUS bits.

•

*XMIT BUFFER EMPTY
All packet bytes have
been received from the
PI LA.

(

•)

Done

* Interface signal
CX-969A

5-37

PORT LINK MODULE

Figure 5-23

Interface Flow Diagram - Receive Operation

(

Start

*PORT DATA<7:0>
*RCYR A ENABLE
*RCYR B ENABLE
K.pLi selects receiver path
via PORT DATA lines.

t
ICCS PATH SELECTED
Carrier is detected on bus.

CHAR SYNC
Carrier is a valid packet.

*RCYR PACKET END
Last byte of packet
body has been
transferred to PI LA.

t
*YALID RCYR STATUS
Yalid receiver status
information is available·
I
to the K.pLi.
*CRC STATUS
Indicates CRC status on
received packet.
*ICCS PATH B
Indicates over which CI
path the packet was
received.

*YALID RCYR DATA
Yalid packet data ready
to be transferred to
PILA.

•

TACK
Transmit an ACK
(or NACK) packet.

*RCYR BUFFERS FULL
True if PI LA receive
buffers are full.

I
ACK DONE
ACK (or NACK) packet
has been transmitted.

*RCYR DATA<7:0>
*RCYR DATA PARITY
Packet bytes (with
parity) are transferred
from link to PI LA .

Done

•

*PACKET LENGTH
Data being transferred
to PI LA specifies length
of received packet.

I
* I nterface signal

CX-970A

5-38

PORT· LINK MODULE

5.7.1
Message Transmit
Figure 5-24 illustrates the Message Transmit State Logic and is used in conjunction with the MESSAGE
XMIT state diagram in the engineering drawing set. Two PALs are used for the message XMIT state
sequence.
'The K.pli signal INITIALIZE asserts TIN IT, initializing the LINK and asserting MX STATE A (transmit
idle state) from PAL number one. When the K.pli conlmands a transmit function, XMIT FCN is asserted
from the LINK Control PAL asserting TXMIT and transferring the LINK to state B. The LINK then
arbitrates for the bus in state B. When the arbitration is successful, ARB is asserted and the LINK
transfe:rs to state C.
In state C, the LINK transmits the bit synchronization bytes and the sync character byte. After the sync
character byte is transmitted, SYNC/TR GONE is asserted and moves the LINK to state D.
In stat(~ D the eRC Generator is enabled (except for maintenance loop operations), the second MSG
XMIT State PAL is enabled, and the LINK goes to state E. PAL number one remains in state E for
the rem.ainder of the transmission if no parity error occurs. In case of parity error, PE is asserted and
transfers the LINK to state F.
When the LINK is placed in state F, PAL number two is reset and XMIT ATTENTION asserted to the
K.pli which ternlinates the transmission of the packet. The LINK then returns to state A.
PAL number two moves from its idle state (G) to state H when Pal number one asserts MX STATE
D. Frolm state H the LINK goes to state I where the destination byte is clocked into the destination
address register . At this point, the LINK transfers to state J where it waits for transmission of the packet
body. 1Nhen the last byte of the body is transmitted, XMIT BUFFER EMPTY is received from the PILA
transferring the LINK to state K (if this is not a maintenance operation). If this is a maintenance operation
(LOOP true), the LINK goes directly to state L.
CRC bytes are transmitted in state K. MAX CRC 3 is asserted when the last CRC byte is transmitted,
causing the LINK to transfer to state L. In this state, the packet trailer bytes are transmitted. Following
this transmission, SYNC/TR GONE is asserted and transfers the LINK to state M.
The LINK completes its transmission in state M and waits for completion of the ACK receive sequence.
AR STATE D or AR STATE H (fronl the ACK Receive State Logic) asserted indicates the end of the
ACK receive sequence. Either of these signals asserts ACK RCVD to both PALs, returning them to their
idle states. ACK RCVD also negates TXMIT completing the message XMIT sequence.
When the LINK enters state M, WACK 0Nait for ACK) is asserted to the ACK Receive State Logic
enabling the ACK RCVR PAL to start the ACK receive sequence. When the ACK response is received,
ACK RCVD is asserted and WACK is negated.
The K.pli can abort the transmission by asserting ABORT XMIT FCN over the LINK control lines. This
signal asserts XMIT STATUS 4 and then TABORT with two flip-flops. T ABORT resets both XMIT PALs
to their idle states.
The MSG XMIT sequence is also reset by HEADER TIME OUT which asserts ABORT RCVR to PAL
number one. The MSG RCVR State Logic asserts HEADER TIME OUT when a carrier is detected but
SYNC CHAR does not occur.

5-·39

:0
-I

....

Figure 5-24 Message Transmit State Logic
B

MX STATE F

AR STATE 0

....--

AR STATE H

J B r------tJ

FF
RCVR ClK C (B)

K ClR

ACK RCVD

c:::

....

(M)

MR ;TATE MT
INITIALIZE
PORT ClK
XMIT FCN

SET
J

XMIT
C FF
K (B)

~
XMIT FLAG
~~cr----~~~D

FF
(B)

XMIT ClK

SYNC/TR
GONE

MX STATE A

ARB

MX STATE B

TXMIT

MX STATE C

lOOP

MX STATE 0

MSG
XMIT
STATE
PAL
(A-F)
(B)

TABORT

ClR

fMx STATE M C

TINIT
A

ACK RCVD

MX STATE E
MX STATE F

MX STATE M
C
U1
I

XMITClK

TDATA PARITY ERROR

XMIT DATA ENABLE

ABORT RCVR

I (A)

Gr-

ClK

~
MX STATE G

L..--

XMIT STATUS 4
-- 0

TABORT
FF
A

(B)

XMITClK

MX STATE H

MX STATE 0
MX STATE F
ACK RCVD

MAX CRC 3
SYNC/TR GONE
.,--"-

FF
(B)

XMIT ClK

TINIT
MR STATE F

MX STATE K
MX STATE l
MX STATE M

~X~M~IT~C=lK~_ _ _~ClK

~_--.... ABORT

HEADERTIMEOUT~J

,....-------L..... D

RCVR

FF
(B)

RCVR ClK C (B)
NOTE:
lETTER DESIGNATIONS IN PARENTHESES REFER TO
ENGINEERING DRAWINGS CONTAINING CORRESPONDING
lOGIC.

MX STATE I
MX STATE J

(B) .

lOOP
XMIT BUFFER EMPTY
INITIALIZE
- - -....... 0

MSG
XMIT
STATE
PAL
G-M . _.

XMITClK

C
ClR

ACK RCVD

(B)

WACK

f-----+

PORT LINK MODULE

5.7.1.1
Transmit Control Logic
Figure 5-25 illustrates the logic controlling the data flow through the transmit channel shown in Figure 5-11. The state signals generated by the XMIT State PALs regulate these control signals. Assertion
and negation of the control signals can be related to the task(s) performed in the various states. (Refer
to the XMIT state diagrams in the engineering print set.) ENA SYNC/TR CNT enables the Sync/Trailer
Counter to start counting. ENA SYNC/TR gates the bit sync bytes and the trailer bytes onto theXMIT
DATA Bus. This signal is negated by ENA XMIT DATA LATCH which gates the packet bytes from the
PILA onto the XMIT DATA Bus and asserts EN A XMIT OAT A PARITY.
The ENA XMIT DATA REG isolates the BUS TDATA Bus from the XMIT DATA Bus while the CRC bytes
are being placed onto the TDAT A Bus. TINIT initially asserts ENA XMIT DATA REG which passes the
packet bytes onto the BUS TDATA Bus until XMIT BUFFER EMPTY is received from the PILA. XMIT
BUFFER EMPTY negates ENA XMIT OAT A REG which remains negated until all the CRC bytes are
placed onto the BUS TDATA Bus. When this occurs, MX STATE L is asserted thereby reasserting ENA
XMIT DATA REG for the trailer bytes. MX STATE L also asserts SEL TRAILER, gating the trailer bytes
out of the Sync/Trailer PROM onto the XMIT DATA Bus.
A DRIVER ENA and B DRIVER ENA enable the drivers that output the transmitted packet onto the
selected CI path. During a message XMIT operation, the selected DRIVER ENA signal is asserted by
the SEL TPATH signal selected by the K.pli via the LINK control lines and by MX STATE C. When
SYNC/TR GONE is asserted during the MX STATE L, the DRIVER ENA signal is negated. During an
ACK XMIT operation, the selected DRIVER ENA signal is asserted by AX STATE B and LAST RCVR =
B. LAST RCVR = B is true if the last message arrived on CI path B (ICCS PATH B true). In this case, B
DRIVER ENA is asserted to transmit the ACK over the same path as it was received. Conversely, if the
message was received on CI path A, A DRIVER ENA is asserted, transmitting the ACK over CI path A.
When SYNC/TR GONE is asserted, the DRIVER ENA signal is negated during AX STATE H.
5.7.1.2
Transmit Status
Eight transmit status bits (XMIT STATUS < 7:0 » indicate transmit operation status (Figure 5-26). These
bits are available to the K. pH along with XMIT ATTENTION.
XMIT ATTENTION is asserted when an ACK or NACK response is received from the destination node.
It is also asserted when the destination node does not respond (ACK packet tinleout occurs), when a
transmit parity error occurs, or when an abort transnlission command is issued (ABORT XMIT FCN is
asserted).

5-41

Figure 5-25 Transmit Control Logic

'1J

:u
-I

ENA CRC 3 OUT

XMIT BUFFER EMPTY

ENA XMIT DATA REG

"os:

AX STATE F
XMIT ClK

C (C)

AX STATE H

c:
~

MX STATE l
RCAR DROP
SEl TRAilER

TINIT

AX STATE B
ENA SYNC/TR

MX STATE C
ENA ACK SRC

XMIT
DATA
ENABLE

lAST SYNC
U"l

ENA XMIT DATA PARITY

MX STATE C

MX STATE C
MX STATE l

AX STATE H

--------1 C (C)
XMIT BUFFER EMPTY

ENA SYNC/TR CNT

AX STATE B
FF
(C)

K
XMIT ClK
C

MX STATE l
AX STATE H

A
DRIVER
ENA

lOOP

....-----.-IJ

MX STATE C
AX STATE B

AX STATE H

- - - - - I C (U)

C (M)

/""""""""...,....,..;-+tK

MX STATE l
ICCS PATH B
MR STATE H
MR STATE M

RCVR ClK

':'

FF
C (J)
K ClR

J
FF

lAST RCVR = B

- - - - - ' - -..... C (M)

>------1 K

DlYD MX C
FF
(B)

XMIT ClK

AX STATE B

INT MlOOP

MX STATE C

B
DRIVER
ENA

XMIT CRC ENA

NOTE:
lETTER DESIGNATIONS IN PARENTHESES REFER TO
ENGINEERING DRAWINGS CONTAINING CORRESPONDING
lOG'"
MR·.

Figure 5-26 Transmit Status
XMIT STATUS 7

TDATA PARITY

CARRIER DET B

XMIT STATUS 6

CARRIER DET A

XMIT STATUS 5

ABORT XMIT FCN

XMIT STATUS 4

RESET XMIT STATUS

TINIT
XMIT STATUS 3

ARBC = 0

MR STATE J
BUSY
XMIT STATUS 2 (NACK)

AR STATE B

XMIT STATUS 1 (ACK)
RCVR ClK
RCVR DATA 6
CRC STATUS

XMIT
STATUS 0

MX STATE A

o"
::u

AR STATE H
AR STATE F

AR STATE D

ACK SOURCE CMP

AR STATE H

I--_ _'--I~D

PORT ClK

K
ClR

(l)

ATTENTION

TWO

_R_C_V_R_C_l_K_ _ _---i... C (l)
RCVR ClK

-I

......_ _ XMIT

C
Z

"
s:

CLOCK
PULSES
C ClR

o
c:
r0-

Ar--C~l-E-A-R-X-M-IT-S~T~A-T-U~S---L--------~-~C-l-E-A-R_X_M_I_T~S~T~A_T~US~_ _ _ _~_ _ _ _ _ _~

NOTE: lETTER DESIGNATIONS IN PARENTHESES REFER TO ENGINEERING DRAWINGS CONTAINING CORRESPONDING lOGIC.
CX-972A

PORT LINK MODULE

The XMIT STATUS bits are asserted as follows:
XMIT STATUS 7

This bit is set if a data parity error is detected on the BUS TOATA Bus in the
transmit channel during a transmission. A parity error asserts XMIT ATTENTION to the K.pli which then aborts the transmission.

XMIT STATUS 6

When set, this bit indicates a carrier present on CI Bus A.

XMIT STATUS 5

When set, this bit indicates a carrier present on CI Bus B.

XMIT STATUS 4

This bit is set when the K.pli commands a transmission abort (ABORT XMIT
FCN) via the LINK control lines.

XMIT STATUS 3

This bit is set when an arbitration countdown reaches zero. It does not necessarily mean a transnlission will occur (Section 5.4).

XMIT STATUS 2

This bit is set when a NACK is received from the destination node. A NACK
response asserts XMIT ATTENTION to the K.pli.

XMIT STATUS 1

This bit is set when an ACK is received from the destination node. An ACK
response asserts XMIT ATTENTION to the K. plio

XMIT STATUS 0

This bit is set when a transmit operation is in progress or whenever XMIT
ATTENTION is asserted.

5.7.2
ACK Receive
Figure 5-27 illustrates the ACK Receive State Logic and is used in conjunction with the ACK RCVR state
diagram in the engineering drawing set. Two PALs are used for the ACK RCVR state sequence.
5.7.2.1
ACK Receive PAL States
INITIALIZE from the K.pli initializes the receive channel and asserts RINIT in both ACK RCVR PALs
placing them in their idle states (state A for PAL number one; state E for PAL number two). The LINK
is transferred to AR ST ATE B when the following three conditions exist:
•

PAL number one senses a valid packet is being received (CHAR SYNC true).

•

The receiver is waiting for an ACK response (WACK ~rue).

•

The package is an ACK (RDAT REG 7 = 1) rather than a message packet.

The packet true destination byte is checked in state B. If a match is obtained (OST CMP true), the
LINK transfers to state C. PAL number one remains in state C until the ACK RECVR state sequence
is complete. In state E, ACK RCVR State PAL number two is enabled (AR ST ATE E is asserted) and
the complement destination byte is checked. If a destination match is obtain~d (OST CMP true), PAL
number two moves to state F.
State 0 of PAL number one is a receiver clear state, entered if an improper! response is obtained in
states A, B, or C. State 0 is entered from state A if CHAR SYNC and WACK are true but RDAT REG
7 = 0 (a message packet, not an ACK response). State D is entered from state B if a true destination
mismatch occurred; from state C if a complementary destination mismatch occurred. After clearing the
various receiver functions, PAL number one returns to the idle state A. In state F, the packet source byte
is checked. If this is not a maintenance operation (INT MLOOP false), the LINK then passes to state G.
If INT MLOOP is true (a maintenance operation), the LINK goes to state H.

5-44

PORT LINK MODULE

Figure 5·-27 ACK Receive State Logic
AR STATE A

WACK ..

CHAR SYNC __

AR STATE 8

...

AR STATE C

ICCS PATH SELECTED

RDAT REG 7-=,
EXT MlOOP ...
INT MlOOP ____
RINIT ...
DST CMP

AR STATE D
ACK
RCVR
STATE
PAL
(A-D)

-..

....

...

(8)

ACK TO ...

·..

ACK
TIMEOUT
COUNTER

..-

RCVR ClK _...

4>0=

11CVR ClK

CLR
ClK

L
...

MAX CRC 3
RCVR ClK

I\IOTE:

ClK

ENA

lETTER DESIGNATIONS IN PARENTHESES REFER TO
ENGINEERING DRAWINGS CONTAINING CORRESPONDING
lOGIC.

5-45

AR STATE E _
ACK
RCVR
STATE
PAL
(E-H)

--..

AR STATE F
AR STATE G AR STATE H -

(8)

ClK

CX-973A

PORT LINK MODULE

In state G the CRC bytes are input to the CRC Checker for CRC error checking. When MAX eRC 3 is
asserted (last CRC byte into the CRC Checker), the LINK moves to state H. this is the last state in the
ACK RCVR sequence. In this state, receive functions are cleared and then both PALs return to the idle
state. The last state in a MESSAGE XMIT state sequence is state M. When MX STATE M is asserted,
an ACK timeout counter is enabled and starts counting. After 3.66 microseconds, if the ACK RCVR
sequence is not completed, the counter asserts ACK TO, terminating the sequence and returning both
PALs to the idle state. The K.pli then reads status bits to determine the problem.
5.7.2.2
Sync Character Detect Enable PAL
The Sync Character Detect Enable PAL (Figure 5-28) enables the Sync Character Detector when a packet
is expected and inhibits the detector when transmitting from this node. In the figure, ENA SYNC DET
is asserted by any of five signals applied to an output OR gate. The Sync Character Detector should be
enabled during the following times:
•

During an internal maintenance loop operation

•

After a transmission when an ACK packet is expected

•

During message packet transmission from another node (taking care not to respond to transmissions from this node - ACK packet)

Figure 5-28

Sync Character Detect Enable PAL
INT MLOOP
WACK
CARRIER DET A

ICCS PATH B
CARRIER DET B

ENA
SYNC
DET

(LAST PATH A)

(LAST PATH B)

NOTE
2

FORCE PATH A
FORCE PATH B
NOTE:

1. THE LOGIC IN THIS FIGURE IS CONTAINED ON SHEET J OF THE ENGINEERING DRAWINGS.
2. SIGNALS GENERATED INTERNALLY
CX-974A

5-46

PORT LINK MODULE

When in maintenance loop operation, INT MLOOP is true and enables the Sync Character Detector.
Two signals enable the Sync Detector when an ACK packet is received. One is generated by ANDing
CARRIER DET A with the negated state of ICCS PATH B while the other is generated by ANDing
CARRIER DET 13 with the asserted state of ICCS PATH B. Thus, the two gates search for a carrier
presence in both CI paths. Enabling the two gates is restricted to ACK packets by ACK ENA that is
asserted while waiting for an ACK packet ryv ACK true) and after a loss of carrier is sensed. (The carrier
lost would be a message transmit carrier from this node.) ICCS PATH B (true or false) enables one
of the AND gates in the ACK ENA logic. When that gate senses a loss of carrier (CARRIER DET is
negated), ACK ENA is asserted and is latched. The next time a carrier is sensed (ACK response), the
output AND gah:~ is enabled and asserts ENA SYNC DET via the output OR gate.
These last two signals enable the sync detector when a message packet is received. They are generated
by AND gates enabled when the node is not transmitting a message packet (both FORCE PATH signals
false) and a carrier is detected on one of the CI paths. The gates are inhibited by trailer delay (TR DL Y)
true at ACK transmission end when the packet trailer is under transmission.
5.7.3
Message Receive
Figure 5-29 illustrates the Message Receive State Logic. It is used in conjunction with the MSG RCVR
state diagram in the engineering drawing set. Two PALs are used for the message receiver state sequence.
The signal INITIALIZE from the K. pli asserts ABORT + INIT FCN which asserts RINIT. RINIT initializes
the Receive Channel Logic and places the two MSG RCVR state PALs into their idle states (state A
for PAL number one and state M for PAL number two). When the receiver is not disabled due to
transmission frOln the transmit channel (RXMIT false), a valid packet is in the receive channel (CHAR
SYNC true) and the packet is recognized as a message (RDAT REG 7 = 0) and not an ACK. PAL number
one transfers to MR ST ATE B.
In MR STATE B, VALID RCVR DATA is asserted to the PILA indicating a valid packet is being received.
PACKEr LENGTH is asserted to the PILA indicating the byte being transferred contains packet length
information. Also, the CRC Checker is enabled and starts receiving the packet bytes. The LINK moves
to MR STATE C on the next clock pulse.
The true destination byte is checked in MR STATE C and if a l\l1atch is obtained (DST CMP true), the
LINK Inoves to state D . PACKET LENGTH remains asserted in state C as the byte being transferred to
the PILA contains packet length information.
In MR STATE D the complement destination byte is checked and if a match is obtained (OST CMP
true), the LINK :moves to MR STATE E. In this state the packet source byte is clocked into the True
and COInplement ACK Destination Registers to serve as the ACK response destination. The next RCVR
eLK pulse moves the LINK to MR STATE G. For the remainder of the MSG RCVR state sequence, PAL
number one remains in MR ST ATE G. Assertion of MR ST ATE G moves PAL number two from its idle
state (state M) to state H when its condition signal (RCVR PACKET END) is asserted.
If any of the following three condition tests made by PAL number one fails, the LINK is transferred to

MR STATE F:
•

While in state A with RXMIT false, CHAR SYNC is asserted but RDAT REG = 1 (this is an
ACK packet).

•

A true destination mismatch occurred in state C.

•

A complement destination mismatch occurred in state D.

5-47

Figure 5-29

Message Receive State Logic

l:J

-t

ICes PATH SELECTED

"3:

PATH SEl TO

CHAR SYNC

VALID RCVR DATA

MSG END + HTO

VALID RCVR STATUS

RINIT

RCAR DROP
ICes PATH SELECTED
PACKET lENGTH

XMIT STATUS 4

RDAT REG 7

INITIALIZE

RCVR ACTIVE
B

MR STATE D
MR STATE E

CHAR SYNC
DSTCMP

C
MR STATE F

HEADER
TIME
OUT
COUNTER

{JJ

MR STATE G

RCVR ClK

HEADERS TIME OUT
MR STATE F
MR STATE K

(J)

MR STATE l

lOAD

AR STATE D
AR STATE H

(J)

MX STATE C

RCVR ClK
ABORT
+ INIT FCN
A }-----+--t D

CHAR SYNC

INT MlOOP
lOOP
MR CRC3

MSG
RCVR
STATE
PAL
(H-M)
(A)

CRCSTATUS
ACK DONE
AX STATE H

RCVR ClK

ClK

DlYD HDR TO

RESET RCVR
NOTE: lETTER DESIGNATIONS IN PARENTHESES REFER TO ENGINEERING DRAWINGS CONTAINING CORRESPONDING lOGIC.
CX-975A

PORT LINK MODULE

Receive logic is cleared in MR STATE F and PAL number one returns to the idle state (state A) on
the next lRCVR CLK pulse. PAL number two remains in idle state (state M) while the packet body is
transferred to the PILA. After the last body byte is sent to it, the PILA asserts RCVR PACKET END and
PAL number two goes to MR STATE H. Packet CRe bytes are input to the CRC checker in state H.
When the last byte is in the checker, MR CRC 3 is asserted. With no CRC error, CRC STATUS is true
when MR CRC 3 is asserted and the LINK moves to state I. In case of CRC error, CRC OK is false and
the LINK goes to state L. In state L the MSG RCVR state sequence is aborted. The receive channel is
cleared and both PALs move to their idle states (PAL number one to state A and PAL number two to
state M).
The message receive state sequence remains in state I while the LINK transmits the ACK response. MR
STATE I its asserted and in turn asserts TACK (transmit ACK) to the ACK transmit state PAL, initiating
the ACK transmit sequence. When ACK transmission is complete, AX STATE H is negated asserting
ACK DONE to message receiver PAL number two. The assertion of ACK DONE moves the LINK to
MR STATE K. In this state, the receive channel is cleared and PAL number one is returned to its idle
state (state A). The next RCVR CLK pulse returns PAL number two to its idle state (state M).
The Message Receive State Logic contains a header tinleout counter to prevent receive channel hangups.
This counter is turned on by ICCS PATH SELECTED (removes the counter LOAD signal) and cleared by
CHAR SYNC. It starts counting when a carrier is detected and is cleared when the carrier is recognized
as a valid packet. If CHAR SYNC fails to assert, the counter times out in 3.66 microseconds and outputs
HEADER TIME OUT. Assertion of that signal causes MSG END + HTO to assert, thereby asserting
CLEAR RCVR to reset the receive logic.
A flip-flop enables and disables the header timeout counter at the RCVR CLK rate. The four-bit counter
is extended to five bits, producing the 3.66 microsecond timeout period (32 X 114.28 ns = 3.66 microseconds). This counter is disabled by WACK. When the transmit channel is transmitting a message
packet, WACK is asserted in MX STATE M. Thus, WACK prevents carrier detection from starting the
header tiIneout period. Signals other than MSG END + HTO assert CLEAR RCVR. One such signal,
RCAR DROP (receive carrier dropped), is asserted if a carrier is lost during a message reception. ICCS
PATH SELECTED is asserted before and negated after CHAR SYNC. If a receive carrier is prematurely
lost, ICCS PATH SELECTED is negated while CHAR SYNC is still true, causing assertion of RCAR
DROP. Note CHAR SYNC is not applied to the ANDing operation until MR STATE E sets a flip-flop
gating CHAR SYNC to the RCAR DROP signal AND gate. Delaying CHAR SYNC until MR STATE E
allows thE:~ packet header to pass before the node looks for carrier dropout.
5.7.4
ACK Transmit
Figure 5-30 illustrates ACK Transmit State Logic and is used in conjunction with the ACK XMIT state
diagram in the engineering drawing set.
The signal INITIALIZE from the K. pli asserts TINIT initializing the LINK and asserting AX STATE A
from the ACK XMIT PAL. AX STATE A is the ACK transmit idle state. When TACK (transmit ACK)
arrives from the MSG RCVR State PAL, the LINK goes to AX ST ATE B. In this state the Sync/Trailer
PROM Logic is enabled and outputs the bit synchronization bytes and the sync character byte onto the
XMIT DATA Bus. The selected transmit driver is also enabled. When SYNC/TR GONE is asserted, the
LINK transfers to state C.
The LINK is in AX STATE C for one XMIT CLK pulse. While in this state, the ACK type byte is placed
onto the XMIT DATA Bus and the CRC Generator is enabled. The next clock pulse moves the LINK
to state D. In AX STATE D the ACK true destination byte is placed onto the XMIT DATA Bus. The
LINK then advances to AX STATE E where the ACK complement destination byte is placed on the
XMIT DATA Bus. The LINK then moves to state F. The ACK source byte is placed on the XMIT DATA
Bus in AX STATE F. The LINK moves to state G where CRC bytes (generated by the CRC Generator)
are output onto the BUS TDATA Bus. When the last CRC byte is placed onto the bus, MAX CRC 3
is asserted. and moves the LINK to state H. In that state the Sync/Trailer PROM is enabled again and

5-49

PORT LINK MODULE

Figure 5-30 ACK Transmit State Logic

TACK

AX STATE A

INT MlOOP

AX STATE B

TABORT

AX STATE C

1:-.0

AX STATE 0

I _

ACK
XMIT
STATE
PAL
(A-H)
(A)

TINIT

MX STATE M

SYNC/TR GONE
MAX CRe 3

XMITClK

- C

AX STATE E

AX STATE F

I . -

AX STATE G

ClK

AX STATE H

ENA ACK TYPE
~------------------------------------------,---.

ENA ACK TDST

AX STATE 0

B ~-------------------------i

~------------------------------,---.

ENA ACK COST

AX STATE E

C ~------------------------------------~
~----"

. ---..... ENA ACK SRC

AX STATE F

o ~------------------------------------------------~
NOTE:
lETTER DESIGNATIONS IN PARENTHESES REFER TO
ENGINEERING DRAWINGS CONTAINING CORRESPONDING
lOGIC.
MR·14473

the packet trailer bytes are output from the PROM onto the XMIT DATA Bus. After the trailer bytes are
placed on the bus, SYNC/TR GONE is asserted and returns ACK XMIT PAL to its idle state (state A).
Note in Figure 5-30 that assertion of each gate coupling a byte to the XMIT DATA Bus depends on
negation of the gate that coupled the preceding byte to the bus. This ensures only one source drives
the XMIT DAT A Bus at one time.

5-50

PORT LINK MODULE

5.8 STATUS LEOS
The LINK has two status LEOs: a green LED and a red LED.

The green LED is CI Active. The LED lights when the K.pli selects a CI Bus (A or B) path.
The red LED is Module Failure. When the K.pli puts the LINK in maintenance mode, the LED lights.
In maintenance mode, the output of the transmitter is wrapped around into the receiver (shown on
Figure :>-1 as ME DATA). The maintenance mode allows the K.pli to transmit data and check that data
verifying the LINK logic.

5-51

PORT BUFFER MODULE (PILA)

CHAPTER 6
PORT BUFFER MODULE (PI LA)

6.1 INTRODUCTION
The Port Buffer Module is one of three modules that make up the Host Interface. The Port Buffer
Module, or Port Interface-to-Link Adapter (PILA), contains four 1 Kbyte (8-bit bytes) RAM buffers, two
1 Kbyte buffers for reception, and two 1 Kbyte buffers for transmission. The buffers provide temporary
storage between the 70 megabit-per-second CI Bus and the Port Processor Module (K. pli).
As the Link Interface Module (LINK) receives a packet, it loads the PILA receive buffers. The K.pli
reads the receive buffers, reformats the data, and sends it to the HSC memory via the Control Bus or
Data Bus.
The K.pli lloads packet data into the transmit buffers. After the entire packet has been loaded, the K.pli
commands the LINK to transmit the packet. The LINK then reads the transmit buffer as it transmits the
packet.
The Port Link Interface (PLI) carries communications and data transfers between the K.pli and the PILA.
All data and PLI functions are controlled by the K.pli.
The Interprocessor Link Interface (ILl) carries communications and data transfers between the PI LA and
the LINK. All data and ILl functions are controlled by the LINK. Figure 6-1 shows the block diagram
of the PILA. The following paragraphs describe the interfaces and the operation of the PILA.

6-1

PORT BUFFER MODULE (PILA)

Figure 6-1

Port Buffer Module Block Diagram(PILA)
XMT
STATUS

RCVR STATUS

8
RD XMT STAT

RD RCVR STAT
PLI DATA

7:0,P

PLI D 7:0,P

COMMAND
DECODER

o
1
2
3
4
5

TRANSMIT
ABORT XMIT

6
7

PLI LINK CONTROL 0 SO

8
PLI LINK CONTROL 1 S1

10
11
12 13
14
15
P06

, ___j-P_L_I_L_IN_K~C~O~N~T~R~O~L~3
....
S3
SELECT

L---J---------~----~EN

XMIT DATA ENABLE
VALID RCVR STATUS
CRC STATUS

c::::::J
c::::::J

ICCS PATH B

RD RCV STAT
RD XMT STAT
RD BFR
RD NODE ADR
RD PI LA SW
SET MODE
SEL BUF
SYNC

PLI LINK CONTROL 2 S2

XMT DATA RDY
XMT
PACKET END
+3V
XMT B
XMIT DAT PARITY
VALID RCVR DATA

REC DATA P

LD T BFR

PLI RECEIVE DATA PAR
P03

CONTROL

TA CLK ___~TA
WR TA
LD TA ADR
CONTROLt--_ _ TA CS
RD TA
TA ADR CLR
TA EMPTY
INC ADR TA
TRANSMIT
ENO TA
PLI D 0
CLK OUT TA
LD T BFR
XMT A RDY D
AlB --rttt-f
ABORT XMT
XMT A

T DATA EN
LOAD/R EAD

P06

i"""

~
P06
XMT

~
06

RCVR DATA EN
T DATA EN

1F
OA

VALID R STAT

CRC STAT

CI PATH B

RCVR P

OB
OC
OD

TB CLK-++t+ttt-fTB
RDY
LD TB ADR
CONTROL
XMT B
RD TB
XMT B RDY D
WR T6
TB EMPTY
t----TB CS
t----TB ADR CLR
t----INC ADR TB
t----ENO TB
t----CLK OUT TB
P07
RA CLK- RA

RECEIVE r---CONTROL ~

RCVR DATA PARITY

DATA ENMAINT MODE--.....

IP07

LD RA ADR- CONTROL~BUF A FULL
LD LO
L...L-D--H-I

RD RA-

I-CRC ERR A
~RA AD R CLR

--------.-1

I-WR RA
I-RA CS
r-INC ADR RA
r-CLK OUT RA

DEC LEN
STOP

DECODER
0 -LD RA ADR
SET MODE-"'""""--r++-t-H
,......----------IS1
1 -LD RB ADR
PLI D O--,.-t++-t-H
EN
2 -LD TA ADR
SEL BUF
P LI D 5--.-1-++++1-1
3 -LD TB ADR
A/B-,......t-+I~I-I-I
Q LOAD/READ
D
P06
V
ALI
D
STAT
-r-li-+++++-+-II-f
RCVR/XMIT
Q
DECODER
CRC STAT T+t-t-t-+l~1-I-I
A/B
o -RD RA
Q
SO
1 -RD TA
P06
2 -RD RB
-RD TB
Q

.--------------1 SO
PLI D 0
PLI D 1
PLI D 2
SEL BUF
PLI D 4
PLI D 6
PLI D 7
SET MODE

Q
Q

XMT DATA

P06

----pog

P06

CX-l039A
Sheet 1 of 2

(Continued on next page)

6-2

PORT BUFFER MODULE (PILA)

Figure 6-1 (Cont.)

c:=:: )

Port Buffer Module Block Diagram(PILA)

III NODE ADDRESS 7:0 ~
·P05

.s. P051
RD XMT

RD NODE ADR
PLI D 7:0,P

XMIT
DATA
0-7,P

Q
D
lK X 9
TA
, BUFFER
ADR
POl
10

I--

PLI D 6:3
D
r--

,....
PLI D

6:3

Q
D
ADR
CNT

ADR
CNT

Q~
D
lK X 9 f - - RA
BUFFER

ADRp03

RD RAJ

P'LI D 6:3
D

ADR
CNT

P04

POl

lK X 9
RB
BUFFER
ADR
P04

PLI D

7:0,P

PLI D 6:3

ADR
CNT

RD RBJ

-;f- fa

P02

[

CNT/
CMPR

RCVR 7:0.P

CRC ERR A
eRC ERR B
RB ADR ClR
WR RB
RB CS
INC ADR RB
ClK OUT RB
BUF B FUll

CRC
CHECK

BYTE
CNT
P02

XMIT DATA

CRC ERR

P06

XMIT
BUFFER
EMPTY .r---'\

)

7:0,P

XMIT ClK
PLI CLOCK

TRANSMIT
CLOCK
GENERATOR

TA ClK
TB ClK

MAINT MODE
XMT A
XMT B
P06,P07
RCVR ClK

RECEIVE
STATUS

BUF A FUll
P07

7:0,P

S 0
P04

RB
CONTROL

III RCVR DATA

D
Q
lK X 9
TB
BUFFER
ADR
POl

RCVR PACKET END . c - - l

MAINT MODE~

P03

BYTE
CNT

P03
..,

rI-

POl

(

P06,P07

RECEIVE
CLOCK
GENERATOR

A FIRST
RCVR BUFFERS FUll

RA ClK
RB ClK
RCVR ClK

P06,P07

CX-1039A

Sheet 2 of 2

6-3

)

PORT BUFFER MODULE (PILA)

6.2 PORT LINK INTERFACE (PLI)
The K.pli controls the PILA and LINK via the Port Link Interface (PLI). Also, the K.pli and PILA pass
data over the PLI. Figure 6-2 shows the PLI signals, and Table 6-1 describes the PLI signals.
Figure 6-2

PLI Signals

PLI DATA

I\r...
-

PLI SELECT

PLI

I\r

\
I

7:0

LINK CONTROL

3:0

PLI XMTR ATTENTION
PLI RCVR BUFFER A FULL
LINK
AND
PILA

PLI RCVR BUFFER B FULL
PLI TRANSMIT DATA PAR
PLI RECEIVE DATA PAR

-...
~

-...

K.pli

PLI CLOCK
PLI INITIALIZE

TRANSMITTER STATUS LINES

RECEIVER STATUS LINES

\
I
\
I
CX-ll09A

6-4

PORT BUFFER MODULE (PILA)

Table 6-1

PLI Signal Description

Signal

Description

PLI DATA <7:0>

Transfers data from PI LA to K. pli PLI Input Buffer and data from K. pli
PLI Output Buffer to PILA. Also transfers control and status between the
K.pli and LINK/PILA. The direction and type of information transferred
is determined by the code on PLI LINK CONTROL < 3:0 > lines.

PLI SELECT

Asserted by the select PLI command. Acts as an enable for the PLI LINK
CONTROL < 3:0> lines.

PLI LINK CONTROL
<3:0>

Asserted by a combination of D OUT < 03:00> to the PLI Control Register
on the K.pli. The PLI SELECT signal enables these lines. Section 6.4
describes the commands and functions encoded in these lines.

PLI XMTR ATTENTION

Asserts PLI XMTR ATTENTION in the K. plio The LINK asserts PLI XMTR
ATTENTION when there is a response to a transmit command in normal
or loop modes. The K.pli can then read the transmitter status bits with the
read transmitter status command (Section 6.4.8).
PLI XMTR ATTENTION is cleared by INITIALIZE and the reset transmit
status command.
When set, PLI XMTR ATTENTION enables transmit status bits 7,4,2, and
1. When reset, PLI XMTR ATTENTION disables transmit status bits 7, 4,
2, and 1.

PLI RCVR BUFFER A
FULL

Asserts PLI RCVR BUFFER A FULL in the K.pli. Asserted when a valid
packet has been stored in Receive Buffer A. Asserted by INITIALIZE to
prevent the LINK from putting packets in the buffer until it is enabled.
Negated when the buffer is enabled by a set mode command from the
K.pli.

PLI RCVR BUFFER B
FULL

Asserts PLI RCVR BUFFER B FULL in the K.pli. Asserted when a valid
packet has been stored in Receive Buffer B. Asserted by INITIALIZE to
prevent the LINK from putting packets in the buffer until it is enabled.
Negated when the buffer is enabled by a set mode command from the
K.pli.

PLI TRANSMIT DATA
PAR

The K.pli Data Parity Generation Logic generates the PLI TRANSMIT
DATA PAR signal when it sends data to the PILA. The PILA stores the
parity bit (odd).

PLI RECEIVE DATA
PAR

The PLI RECEIVE DATA PAR bit (odd) is generated by the LINK when the
receive buffer is written. The PILA does not check receive data parity; it is
checked by the K.pli Data Parity Check Logic. The PILA generates parity
on all read operations except the read buffer command (when it passes
on the LINK generated parity).

6-5

PORT BUFFER MODULE (PILA)

Table 6-1 (Cont.)

PLI Signal Description

Signal

Description

PLI CLOCK

The K. pli Control Logic generates the PLI CLOCK signal at the K. pH CLK3
time on every micro cycle . All PILA flags and ;status signals are synchronized to this clock. Signals are asserted and strobed by the clock's trailing
edge.

PLI INITIALIZE

Forces the initialization of the LINK and PILA. The PILA provides a maintenance mode that allows transmit data to be looped back into the receive
buffer for diagnostic purposes. INITIALIZE puts the PILA into maintenance mode, setting both the Receive Buffer, A Full Flag (BUFA FULL)
and Receive Buffer B Full Flag (BUFB FULL) to prevent the LINK from
loading the buffers until the K.pli enables the receive buffers. INITIALIZE
also resets the status of CRC error (CRC ERR), first buffer (FIRST BUF),
Buffer A Bus (BUSB BUFA), and Buffer B Bus (BUSB BUFB), and disables
any read or write operations.

6.3 OPERATIONS BETWEEN PILA AND LINK
The LINK loads the received packet into the receive buffers on the PILA and sends packets in the
transmit buffers over the CI Bus. The PILA provides dual, independent 1 Kbyte receive buffers (RA and
RB) and dual, independent 1 Kbyte transmit buffers (TA and TB) as temporary storage for packets. The
following sections describe how the LINK loads a receive buffer during a receive operation and how
the LINK gets the packet from a transmit buffer during a transn1it operation.
6.3.1
Receive Operation from LINK to PILA
During a receive operation, the LINK puts the bytes of the incoming packet into one of the receive
buffers. Figure 6-3 illustrates the receive buffer circuits and the following list describes the circuits:
•

Counter/Comparator-loaded with the packet length from the incoming packet and then down
counted as the logic puts each byte of the packet into the buffer. (Refer to Chapter 4 for the
packet format.)
,

•

Address Counter-initially zero. Incremented each time the logic puts a byte of the packet into
the buffer.

•

Buffer-RA and RB are the 1 Kbyte receive buffers for storage of the incoming packet bytes.

The following list describes a receive operation (a packet from the LINK going to Receive Buffer A):
1.

The LINK recognizes that the incoming data is valid when it receives the CHAR SYNC.

The LINK assembles the first byte (PACKET TYPE/LENGTH (HIGH» and places the byte on
the ILIC RCVR DATA lines < 7:0 > to the Receiver Data Multiplexer.

The output of the multiplexer is an input to the Counter/Comparator and the input buffer of
Receive Buffer A (RA).

The LINK then generates a clock pulse that asserts the following signals on the PILA:
•

RA ADR CLR clears the Address Counter for the buffer

•

LD HI strobes the packet length high byte into the Counter/Comparator

6-6

Figure 6-3

Receive Buffers
COUNTER/
COMPARATOR

I " .... n

rlLJ;F
""n

RCVR PACKET END

I\V.._ - - - - - - ,

F/F

ctc

'I'

...

RA DATA<7:0>,P

LOAD 14-- LD HI
0AD
LD LO
CNT
DEC LEN

--0
WR

RA
RAM

RA~ EN

P03

-----

RD RA.,. EN

P03

ADDRESS COUNTER
CTR
INC ADR RA" CET
LD RA ADR ... LOAD
RA ADR CLR..:t CLR
RA ADRS

<11 :00>

~--------Vrl

ILiF RCVR
~
DATA PARITY(1) ...... 1 " \

BFR

JI------1

P07 I

P03

PARITY ~V

PLI 0 <6:3>

XMIT DATA......

) 0

~--------Yr

- - - - - . . ,..fI

P03

ADR

WR RA--. WR

P03

PLI DATA<7:0>
F/F

F/F
P01

-'--

RCVR DATA
MUX

LINK

J...---~~u~

-:-v

1--

~D
WR RB -

~ EN

ILiC RCVR DATA(7:0> 0

RB
RAM

P04

ADDRESS
COUNTER
CTR

P04

XMI;:~;A :~,::

R B DATA <7:0>
....,_p_ _ _ _ _ _ _---v
.. 0

P04

~
L-..-,I
.. EN

RB CS

WR RB--'-

PARITY
GENERATOR

RB ADRS<11:00>
-y

INC ADR RB'- CET
LD RB ADR.- LOAD
RB ADR CLR+ CLR P04

RD RB--. EN

PARGEN
P04

114214314-

ODD

::D

-I

REC DATA P

P03 5 "r-~I---XMIT DATA PARITY
6~

."
."

P03

m
::D

LINK CONTROL 1
_
1

,,~~
"I4--XMIT

LINK CONTROL 2

K.pli

c:
r-

PLI RECEIVE DATA PAR

CX-1031A

PORT BUFFER MODULE (PILA)

•

WR RA strobes data from the multiplexer into location zero of the Receiver Buffer A

•

INC RA ADR increments the address counter to location one

The LINK assembles the next byte, PACKET LENGTH (LOW), and generates the clock pulse
that strobes the byte into the Counter/Conlparator and into the buffer and then increments th(~
Address Counter.

As the LINK strobes each received byte into the receive buffer and increments the Address
Counter, the signal DEC LEN decrements the Counter/Comparator. '

When the Counter decrements to two, the Comparator asserts the signal RCVR PACKET END .

RCVR PACKET END signals the LINK to check the packet CRC.

The LINK asserts RCVR BUFFER A FULL to the K.pli.

To learn how the K.pli removes the data from the buffer, refer to Section 6.4.9 and Chapter 7.
6.3.2
Transmit Operation from PILA to LINK
During a transmit operation, the LINK takes the bytes of a packet from one of the transmit buffers and
sends the packet over the CI Bus. The K.pli puts the packet into a buffer before it commands the LINK
to send the packet. (Filling the buffers is described in Section 6.4.1 and Chapter 7.) The LINK then
gets the packet one byte at a tinle, serializes the bytes, and sends the packet over the CI Bus. Figure 6-4
illustrates the transmit buffers on the PILA, and the following list describes the circuits:
•

Address Counter-initializes to zero and increments each time the LINK takes a byte from the
buffer

•

Byte Register-contains the byte count of the buffer

•

Byte Counter-initializes to the count of the Byte Register and decrements each time the LINK
takes a byte from the buffer

•

Buffer-TA and TB are the 1-Kbyte transmit buffers for storage of packets

The following list describes a transmit operation (the LINK takes bytes of the packet from Transmit
Buffer A on the PILA):
•

Before starting the transmit operation, the K. pH loads the packet into Transmit Buffer A, and
the Byte Register contains the number of bytes in the buffer

•

When the K. pli commands the LINK to transmit, the transmit command asserts the following
signals:
•

RA ADR CLR-clears the Address Counter and strobes the Byte Register into the Byte
Counter

•

TA CS-enables the output of the buffer

•

ENO TA-enables to output of the buffer to the LINK

•

The LINK strobes the byte on the XMIT DATA lines into its transmitter logic

•

The LINK then asserts a signal to increment the Address Counter and decrement the Byte
Counter

•

When the Byte Counter reaches zero, the signal XMIT BUFFER EMPTY causes the LINK to
append the CRC bytes

6-8

Figure 6-4 Transmit Buffers

FORciA~~~~~;~ ~DJTRANSMIT
DATA PAR H

F/F
T PAR H_ D F/F

-oL.-/
PLI D < 7:0>

..
' D
v
EN

r
WR TA

PLI D <6:3»

TA DATA <7:0>,P
TA
RAM

~----~

P01

ADDRESS
COUNTER
CTR
D

P01

J\
)

r---

ENOTA

TA ADRS (11:00»
.

INC ADR TA ~~ET
LD TA ADR ~ LOAD
TA ADR CLR ~ CLR

ADR

TA CS ...... EN
- WR
BYTE
REGISTER

BYTE
COUNTER
CTR

P01

F/F

~-'\ D

BFR

XMT A RDY --;.. CRY
EN P01
XMT A .... CNT P01
!--~~~------------~- LOAD
F/F
F/F
~D

~EN

P01

r- GND

COUT~

~
K.pli

Rt----------J\\ D

PLI DATA <7:0>

•

TB DATA <7:0> ,P

I--------~

TB
RAM

LEN P02
WR TB

ADDRESS
COUNTER
CTR

.
J

P01

lEN

P02

BFR

PLI D <6:3>

-\D

1\
XMIT DATA <7:0>, PARITY)

END TB

, D
R TB ADRS
00-11
, ADR
,j
vINC ADR TB ___ CET
TB CS-. EN
LD TB ADR--' LOAD
~----.... WR
P02
TB ADR CLR-~ CLR P02
BYTE
REGISTER
F/F

XMIT BUFFER
)-E_M_P_T_Y______--t..~ LI N K

-4
OJ
C

EN P05
BYTE
COUNTER
CTR

RD XMT

J
c
cr-

' D

t-------.......,"I C OUT ~

... EN P02

XMT B RDY-' CRY
XMT B-' CNT P02

-=u

~------------------------------~-~LOAD

r~.

PLI DATA <7:0>
CX-l038A

PORT BUFFER MODULE (PILA)

6.4 PLI LINK CONTROL
The K.pli controls the LINK and PILA via the LINK CONTROL <3:0> lines on the PLI. The following
sections describe the commands encoded on these lines. Codes of LINK CONTROL < 3:0> = 0000
and 0010 are not used. Figure 6-5 shows the command decoder on the PILA.
6.4.1
Load Transmit Buffer: LINK CONTROL <3:0> = 0001
Before issuing the load transmit buffer command to the PILA, the K. pli first selects the buffer with the
select buffer command (code 1110). The load transmit buffer command then loads the data from the
DATA <7:0> lines (and the associated parity bit for the DATA lines) into the selected buffer (Figure
6-4). As long as both the load transmit buffer command and SELECT are asserted, the K.pli loads bytes
into the PILA with each PLI clock. The Address Counter is incremented at the end of each cycle during
which the load command is asserted. The signal WR TA strobes the data into the buffer and also strobes
the Address Counter into the Byte Register (which is the byte count).
The K.pli starts loading the transmit buffers at location 0 and goes to location n-1 (Figure 6-6). If XMIT
OFFSET is set, then the transmit buffers are loaded from location 0 + offset to location n + offset-I,
where n = the number of bytes loaded into the buffer by the K.pli.
Loading the transmitter buffers is described in Chapter 7.
6.4.2
Transmit: LINK CONTROL < 3:0> = 0011
The transmit command performs the following operations:
•

Selects the transmit buffer to be transmitted

•

Clears its address counter to zero

•

Initiates the LINK CI arbitration on the CI path selected by the command

Upon successful CI Bus arbitration, the selected buffer is transmitted. The LINK checks data parity. If a
parity error occurs, the transmission is aborted. The path and buffer. are selected by DATA lines 7 and
o as shown in Table 6-2.

Table 6-2

Path and Buffer Selection by Data Lines 7 and 0

Data Line 7

Data Line 0

CI Path

Transmit Buffer

6-10

Figure 6-5

Link Control Command Decoder
READ

COMMAND
DECODER
11--LD T BFR
31--TRANSMIT
5 f--ABORT XMIT
81--RD RCV STAT
9 f--RD XMT STAT
10
11 f--RD NODE ADR
12 f--RD PI LA SW
13
14
15 f--SYNC

PLI LI NK CONTROL 3_

PLI LINK CONTROL 2_

PLI LINK CONTROL 1_

K.pli

PLI LINK CONTROL 0_

--...
--

PLI SELECT

BFR

..
PLI DATA <7:0>

P06

-y

r=-EN
GND

... D

PLI 0 1

.. D

PLI D 2

... D

R I--READ

SEL BUF

P01

.. LOAD

XMIT

~ EN

0 - R D RA
1 ~RDTA
2 ~RD RB
3 I--r-RD TB

P06

RST ........ CLR

RD BFR
LOAD
ADDRESS
DECODER
DEC
PLI D 1
PLI D 0

o '---LD RA ADR

S1
S2

SEL BUF
0
1
2
3
4
5
6
7

CTR

pU D 0

BUFFER
DECODER
DEC
S2

1 '---LD RB ADR
2 -LD TA ADR
3 -LD TB ADR

RD XMIT

EN
P06
CTR

PLI D 4
PLI D 6
PLI D 7

-D
D
SET MODE ..
LOAD

R -FORCE ZERO PAR
."

R -MANT MODEl RED LED
R -GREEN LED

-t
OJ

."
."

RST----' CLR
P06

CX-1040A

o
C

!r-

PORT BUFFER MODULE (PI LA)

Figure 6-6 Transmit Buffer Load

LOCATION 0

PACKET TYPE/LENGTH (HIGH)
PACKET LENGTH (LOW)
DESTINATION (TRUE)
DESTINATION (COMPLEMENT)
DIRECTION

SOURCE

LOAD
BODY (BYTE 0)

J
LOCATION N-1

BODY (BYTE N)
CX~1110A

The transmit command does one of the following:
1.

Initiates transmission of a newly loaded buffer.

Retransmits a previously loaded buffer (according to the buffer and path indicated with the
command and regardless of previous transmit commands on the same buffer):
•

On the same CI path (for retry)

•

On an alternate CI path (for recovery)

Only one transmit command can be issued and executed at a time. Therefore, the transmission must
be completed or aborted, and the transmit status must be cleared before a second transmit command
can be issued.
6.4.3
Reset Transmit Status: LINK CONTROL < 3:0> = 0100
The reset transmit status command is not used by the PILA; it is used by the! LINK. This command is
always issued at the end of a transmission sequence-that is, in response to XMTR ATTN after reading
the transmit status. It resets all transmit status bits except 5 and 6. The transmi~ status bits are described
in Section 6.4.8.
6.4.4
Abort Transmission: LINK CONTROL < 3:0> = 0101
The abort transmission command causes the PILA to abort a currently active transmission (by disabling
the Transmit Address Counter and Output Register) and causes the link to set bit 4 (transmission aborted)
in the transmit status. XMTR ATTN is also asserted by the LINK. If XMTR ATTN is asserted when the
abort transmission command is issued, the abort is ignored.

6-12

PORT BUFFER MODULE (PILA)

6.4.5
Enable Link Control: LINK CONTROL < 3:0> = 0110
The enable link control command is not used by the PILA; it is used by the LINK. It enables the LINK
controls indicated by ones in D ATA < 7: 0> lines. The controls are shown in Figure 6-7 and described
in Table 6-3.

Table 6-3

Link Control Bit Description

Bit

State
Of Bit

Description

Enables LINK receiver path B, nlaking the node accessible to CI path B.

N ode ignores traffic on CI path B. INITIALIZE disables receiver path B.

Used in LINK internal nlaintenance loop mode. Forces the LINK to see a detected
carrier, starting header time-out logic and stopping the arbitration sequence.

Disables this function. Also disabled by INITIALIZE.

Forces the LINK to generate odd parity on received data. INITIALIZE also forces
odd parity.

Causes the LINK to generate even parity on received data.

External maintenance loop enable allows the LINK to receive its own transmission
by looping on the selected CI path.

Takes the LINK out of external maintenance loop mode.

Internal maintenance loop enable allows the LINK to receive its own transmission
by looping inside the CI driver/receiver.

Takes the LINK out of internal maintenance loop mode.

Causes the LINK to force successful arbitration and to transmit immediately when
the transmit command (0011) is received from the K.pli. Should not be used on-line.

Causes the LINK to perform normal arbitration in response to a transmit command.
INITIALIZE causes the link to perform normal arbitration.
1

Causes the true and complement node addresses to be swapped.
Causes the true and complement node addresses to be their normal values. INITIALIZE sets the node addresses to their nornlal values.

Enables LINK receiver path A, making the node accessible to CI path A.
The node ignores traffic on CI path A. INITIALIZE disables receiver path A.

6-13

PORT BUFFER MODULE (PILA)

Figure 6-7

Link Control Bits

RCVR
B ENA

FORCE
CDET

VALID
RPAR

EXTM
LOOP

INTM
LOOP

FORCE
ARB

SWAP
ADR

RCVR
A ENA

•

CX-1111A

6.4.6
Disable Link Control: LINK CONTROL < 3:0> = 0111
The disable link control command is not used by the PILA; it is used by the LINK. It disables the LINK
controls indicated by zeros in DATA <7:0> lines. The controls are shown in Figure 6-7 and described
in Table 6-3.
6.4.7
Read Receiver Status: LINK CONTROL <3:0> = 1000
The read receiver status command enables the receiver status bits in the PILA onto the DATA < 7:0 >
lines. The read receiver status command only reads eight of the receiver bits; CDA and CDB are read
by the read transmitter status command (Section 6.4.8). All receiver status bits are synchronized to the
PLI clock. Figure 6-8 shows the receiver status bits, and Table 6-4 describes[ the bits.

Table 6-4

Receiver Status Bits

Bit

Name

Description

RCVRA
ENABLE

Set by an enable link control command (0110) with bit 0 set.

CRC ERR

When set, indicates that the LINK detected a CRC error on the received message or data packet. CRC is neither generated nor checked
on PILA internal loop mode ACK packets. This bit is never set in PI LA
maintenance mode.
The PILA uses dual CRC latches to indicate the CRC error for each
receive buffer. Therefore, to select the CRC latch, a select buffer command (0011) must be issued before the read receiver status command.
CRC error is cleared by asserting INITIALIZE, or by releasing the
buffer.

6-14

PORT BUFFER MODULE (PILA)

Table 6-4 (Cont.)

Receiver Status Bits

Bit

Name

Description

RCVR B ENABLE

Set by an enable link control command (0110) with bit 7 set.

BUFFER B BUS

Indicates the CI path that carried the last received packet in Receiver
Buffer B, where:

o = CI path A
1 = CI path B
Valid only while PLI RCVR BUFFER B FULL is set. Cleared by INITIALIZE.
3

BUFFER A BUS

Indicates the CI path that carried the last received packet in Receiver
Buffer A, where:

o = CI path A
1 = CI path B
Valid only while PLI RCVR BUFFER A FULL is set. Cleared by INITIALIZE.
2

FIRST BUFFER

Indicates the buffer first filled when both RECEIVE BUFFER A FULL
and RECEIVE BUFFER B FULL are either both set or both cleared,
where:

o = Buffer B was filled first
1 = Buffer A was filled first
FIRST BUFFER is cleared by INITIALIZE.
1

PLI RCVR BUFFER B
FULL

Set when a valid packet has been stored in Receive Buffer B. This
bit remains asserted until Receive Buffer B has been enabled (by set
mode command - 1101). PLI RVCR BUFFER B FULL is also set by
INITIALIZE (to prevent receptions until enabled). This status bit is
also sent to the K.pli as a separate PLI line.

PLI RVCR BUFFER A
FULL

Set when a valid packet has been stored in Receive Buffer A. This
bit remains asserted until Receive Buffer A has been enabled (by set
mode command-1101). PLI RCVR BUFFER A FULL is also set by
INITIALIZE (to prevent receptions until enabled). This status bit is
also sent to the K.PLI as a separate PLI line.

6-15

PORT BUFFER MODULE (PILA)

Figure 6-8

Receiver Status Bits

RCVR BUFFER A FULL
RCVR BUFFER B FULL

LINK

P06 BUF A FULL

PLI RCVR BUFFER A FULL

DATA 0

P07 BUF B FULL

PLI RCVR BUFFER B FULL

PORT DATA 1

P07 A FIRST

FIRST BUFFER

PORT DATA 2

P07 BUSB BFR A

BUFFER A BUS

PORT DATA 3

P07 BUSB BFR B

D R

BUFFER B BUS

PORT DATA

ILiM RCVR B ENABLE

D R

RCVR B ENABLE

PORT DATA 5

P06 CRC ERR

D R

CRC ERR

PORT DATA 6

ILiM RCVR A ENABLE

D R

RCVR A ENABLE

PORT DATA 7

GND

K.pli

P06 RD RCV

BUF B BUF A
RCVR B BUF B BUF A FIRST
RCVR A CRC
FULL
BUFFER FULL
BUS*
ENABLE* ERROR ENABLE* BUS*
7

* ORIGINATES ON LINK
CX-1112A

6.4.8
Read Transmitter Status: LINK CONTROL < 3:0> = 1001
The read transmitter status command enables the transmit status from the PILA onto the DATA < 7:0 >
lines. Bits COB and CDA are receiver status bits. All the status bits originate on the LINK and are
synchronized to the PLI clock. Figure 6-9 shows the transmitter status bits, and Table 6-5 describes the
bits.

6-16

PORT BUFFER MODULE (PllA)

Figure 6··9 Transmitter Status Bits
P05
BFR

P05
F/F

f-- III XMIT STATUS 2 f--

f--

III XMIT STATUS

III XMIT STATUS 4

III XMIT STATUS 7

LINK

XMTR BUSY

PORT DATA

ACK

PORT DATA 1 -

OEST BUSY

PORT DATA

ARBIT RATE

PORT DATA 3 -

XMIT A BaRT

PORT DATA 4':"'"

COA

PORT DATA 5 -

COB

PORT DATA 6 -

XBU F PE

PORT DATA 7 -

P06 RO XMT STAT

CLR

K.pli

P05
F/F
-- III XMIT ATTENTION

- - III XMIT STATUS 0

- 0

R f--I

'-- III XMIT STATUS 3

f--

III XMIT STATUS 5

III XMIT STATUS 6

PLI

XMTR ATTENTION

-----I

R -

- 0 R
GNO - EN

f---

·XBUF
PE

COB

COA

XMIT
ABORT

ARBITRATE

OEST
BUSY

ACK

XMTR
BUSY

o
CX-1113A

6-17

PORT BUFFER MODULE (PILA)

Table 6-5

Transmit Status Bit Description

Bit

Name

Description

XBUF PE

Set if the LINK detects a parity error on the transmit data during a translTlission. A parity error asserts XMTR ATTN and aborts the transmission.
Cleared by INITIALIZE and the reset transmit status command (0100).

CDB*

Indicates the state of the carrier on CI path B, where:

o = Carrier B off
1 = Carrier B on

CDA*

Indicates the state of the carrier on CI path A, where:

o = Carrier A off
1 = Carrier A on
4

XMIT ABORT

Set when a transmission is aborted by the abort transmission command
(0101). Asserts XMTR ATTN.

Cleared by INITIALIZE and the reset transmit status command (0100).
3

ARBITRATE

Set when the arbitration count has expired after a transmit command (0011).
Cleared by INITIALIZE and the reset transn1it status command (0100).

DEST BUSY

Set by a NACK packet from the destination node. Asserts XMTR ATTN.
Cleared by INITIALIZE and the reset transmit status command (0100).

ACK

Set by an ACK packet from the destination node. Asserts XMTR ATTN.
Cleared by INITIALIZE and the reset transmit status command (0100).

XMTR BUSY

Set by a transmit command (0011). Indicates that a transmit sequence is in
progress or that XMTR ATTN is asserted. Not set in synchronization with
the PLI clock.
Cleared by INITIALIZE and the reset transmit status command (0100).

Note: Those bits marked with an asterisk (*) are receive buffer status bits.

6.4.9
Read Buffer: LINK CONTROL < 3:0 > = 1010
The read buffer command enables the contents of the currently addressed. location in the receive or
transmit buffer onto the DATA <7:0> lines. The buffer is selected by the last select buffer command
(1110). The Address Counter for the selected buffer is incremented at the end of each cycle during
which the read buffer command is asserted. The parity bit for the read data is passed to the K. pH on
the PLI RECEIVE DATA PAR line. The read buffer command reads receive or transmit data starting at
location 0 + offset. Offset can be any value from 0 to 15. The data is read sequentially starting with the
first byte received or loaded and ending with the last byte received or loaded, as shown in Figure 6-10.
The read buffer command is also described in Chapter 7.

6-18

PORT BUFFER MODULE (PI LA)

Figure 6-10

Receive or Transmit Buffer Read

LOCATION 0

PACKET TYPE/LENGTH (HIGH)
PACKET LENGTH (LOW)
DESTINATION (TRUE)
DESTINATION (COMPLEMENT)
SOURCE

DIRECTION
OF
READ

BODY (BYTE 0)

J
LOCATION N-1

BODY (BYTE N)

CX-1114A

6.4.10
Read Node Address: LINK CONTROL <3:0> = 1011
The read node address command reads the 8-bit CI node address from the LINK's node address dip
switch onto the DATA <7:0> lines (Figure 6-11). Parity is generated by the PILA and passed on the
PLI RECEIVE D AT A PAR line.
6.4.11
Read Switches: LINK CONTROL <3:0> = 1100
The read switches command reads the revision level of the PILA from the 8-bit dip switch onto the the
DATA <7:0> lines (Figure 6-11). (All ones indicate the absence of the PILA.) Bits 7 through 5 indicate
the module revision level as shown in Table 6-6.

Table 6-6

Module Revision Level

Revision Letter

o
o
o

OlD

Bits 4 thlrough 0 indicate the rework level, with up to 32 engineering change orders allowed before a
new etch is required. Parity is generated by the PILA and passed on the PLI RECEIVE DATA PAR line.

6-19

PORT BUFFER MODULE (PI LA)

Figure 6-11

Read Switches and Node Address

P05
BFR

III

NODE ADDRESS 0- A

PORT DATA 0

III

NODE ADDRESS 1- A

PORT DATA

III

NODE ADDRESS

2- A

PORT DATA 2

III

NODE ADDRESS

3- A

PORT DATA 3
PORT DATA 4

LINK

K.pli

III

NODE ADDRESS

4- B

III

NODE ADDRESS 5- B

PORT DATA 5
PORT DAiA 6
PORT DATA 7

III

NODE ADDRESS

6- B

III

NODE ADDRESS 7- B

RD NODE ADR -

P05
BFR

GND

f--

2 0- A

r----

3 0- A

Y t--

4 0- A

00-

RD PILA SW

CX-1115A

6.4.12
Set Mode: LINK CONTROL <3:0> = 1101
The set mode command allows diagnostics to examine the PI LA internal logic for fault isolation. The
command functions are asserted on DATA < 7:0 > lines as shown in Figure 6-12 and described in
Table 6-7.

6-20

PORT BUFFER MODULE (PILA)

Figure 6-·12

PIlA Mode Bits

GREEN MAINT
MODE
LED
ENA
7

ENA
RCVR

ZERO
PAR

RA
OR
RB
3

o
CX-1116A

Table 6-7

Mode Bit Description

Bit

I~unction

Description

Indicate Operational Status

K.pli sets and resets the green LED on the PI LA to provide a
visible indication of the PILA operational status.

Enable Maintenance Mode

Allows the transmit data to be looped into the receive buffer.
Maintenance mode inhibits the SELECT line from the PILA
to the LINK. Therefore, the LINK will not respond to any
commands from the PILA. The red LED on the PILA indicates
that the PILA is in maintenance mode.

Enable Receive Buffer

When set, releases Receive Buffer A or B (selected by bit 0) by
clearing RECEIVER BUFFER A FULL or RECEIVER BUFFER
B FULL. The buffer can then be used to store incoming CI
packets. This signal also clears the CRC error flag.
This bit does not affect receive buffer full flags unless set.

Zero Parity

Not used

Receive Buffer A or B

Valid only in maintenance mode. It must be zero to pass
good transmit data parity. This bit is set to allow parity logic
to be checked; when set, it forces the transmit buffer parity
bit to zero (does not invert parity).

If not set, bit 0 releases Receive Buffer A; if set, bit 0 releases

Receive Buffer B. Valid only when bit 5 is set. (See Table 6-8.)

6-21

PORT BUFFER MODULE (PILA)

Table 6-8

Mode Bit 0 and 5

Bit 0

Bit 5

Description

No effect on receive buffer full flags

Release Receive Buffer A and clear RECEIVE BUFFER A FULL

Release Receive Buffer B and clear RECEIVE BUFFE~ B FULL

x = Does not matter whether it is a 1 or 0
Select Buffer: LINK CONTROL < 3:0> = 1110
6.4.13
The select buffer command either selects the receive or transmit buffer. It selects the receive buffer
to be read by subsequent read buffer commands (1010). It selects the transmit buffer to be loaded by
subsequent load transmit buffer commands (0001). DATA <6:0> lines are asserted by the K.pli and
defined in Table 6-9.

Table 6-9
Data
Line
6543

Data Lines < 6:0 > Definitions

Description

Load Transmit Buffer A and load offset address

Offset

Load Transnlit Buffer B and load offset address

Address

Read Receive Buffer A and load offset address

Bits

Read Receive Buffer B and load offset address

3210

Read Transmit Buffer A and load offset address

Read Transmit Buffer B and load offset address

Offset address in DATA <6:3> are the offset from address O. The K.pli cannot load an address offset greater than 15 into the address counter of the receive or transmit buffers and, therefore, cannot
randomly access the buffers with an address greater than 15.
The two receive buffers are read-only; that is, they cannot be directly loaded by PLI commands. Either
receive buffer can be loaded with data from either transmit buffer when the K. pH issues a transmit
command and the packet buffer is in maintenance mode.
6.4.14
Sync: LINK CONTROL <3:0> = 1111
The sync command causes an output from the PILA command decoder. The K. pH can use this output
to synchronize measurements.

6-22

PORT BUFFER MODULE (PILA)

6.5 STATUS LEOS
The yellow LED is a test point indicator. This LED is found only on some early E-rev etch modules.
Associated with this LED is a test point that is accessible fron1 the upper-right corner of the board (top
handle-edge when n10dule is inserted vertically). The LED and test point circuit allow you to detect logic
levels. The circuit is capable of operating to 25 MHz, slowing down pulses to a rate of about 10 Hz. The
LED being on indicates a logic high; the LED being off indicates a logic low.
The red LED is forced off by INITIALIZE and automatically turns on after INITIALIZE to visibly indicate
that the PILA is in Maintenance Mode (the initial state after INIT). When the K.pli gives the SET MODE
command to leave maintenance mode, this LED turns off. In maintenance mode, the output of the
transmit buffer is wrapped around into the receive buffer. The diagnostic software in the K. pli tests
the buffers in the PILA before testing the wrap mode in the LINK. When the K.pli puts the PILA in
maintenance mode, it sets the the RECEIVE BUFFER A and B FULL so that it cannot receive anything
from the LINK.
The green LED is forced off by INITIALIZE. Otherwise, it is set or reset by the K.pli diagnostic software
to visibly indicate the PILA operational status.

6-23

PORT PROCESSOR MODULE

CHAPTER 7
PORT PROCESSOR MODULE

7.1 INTRODUCTION
This chapter contains the logical and functional description of the Port Processor Module (K. pli). The
K.pli is the controller for the Port Buffer Module (PILA) and the Port Link Module (LINK).
The K.pli is an L series extended hex nlodule that controls the interconnect between the HSC internal
Control and Data Buses and the Computer Interconnect Bus (CI). It uses several of the 2900-family bitslice devices supported by medium/small scale integration transistor/transistor logic. The architecture of
K. pli consists of 2900-family components organized as dual sequencers alternately accessing a con1mon
control store and supporting a single 16-bit data path.
The K.pli does not use control registers to communicate with the P.ioc and other controllers in HSC.
Communications between K. pli and the P .ioc and other controllers of the subsystem are perfornled
using mernory resident control structures.
The functional and diagnostic microcode are resident in PROM Control Store.

7.2 STATUS LEOS
The red and green LEOs indicate the status of the K.pli module. The module powers up with the red
LED on and the green LED off. Upon successfu1 completion of the power-up diagnostics, the red LED
is turned off and the green LED is turned on.
7.3 MICROINSTRUCTION WORD
The microinstruction word from Control Store controls the operation of the K. plio The microinstruction
word is 48 bits wide. Each word is divided into sixteen fields and each field controls different portions
of the K.pli hardware. Figure 7-1 shows the fields and their positions in the microinstruction word.
Table 7-1 contains a brief description of each field. Section 7.25 has a detailed description of each field.

7-1

PORT PROCESSOR MODULE

Figure 7-1

Microinstruction Word

47 46

41 40

44 43

IOC
BD

TEST

38 37 36 35

RA/BS

LITERAL

28 27

25 24 23

20 19

BRANCH ADDRESS (BA)

15 14 13

CX-1224A

Table 7-1

Microinstruction Word Field Description

Field

Description

The C field is the carry into the ALU for the current microinstruction. It
steers the literal to the high byte for AF fields 3 through 7.

The AD field, ALU destination, determines the routing of the ALU output
data internal to the 2901.

The AF field, ALU function, determines the basic operation to be performed by the ALU.

The AS field, ALU source, selects two of the five possible sources for
the ALU.

The AB field, ALU to BUS, determines whether the D OUT lines will be
driven by the 2901 ALU or if the D IN contents will be transferred to the
D OUT lines to bypass the ALU. It also enables or disables the BS field
decoders.

7-2

PORT PROCESSOR MODULE

Table 7-1 (Cont.)

Microinstruction Word Field Description

Field

Description

The + field, EXEC IF COND TRUE, is one bit long. This bit is combined
with the following signals to generate INHIBIT EXEC (inhibit execute).
•

TST COND TR (test condition true)

•

COND EXC (conditional execute) ($ field)

INHIBIT EXEC prevents:
•

Any ALU operation of each instruction for which it is active

•

The lac Latches from being enabled

•

The destination decoders from being enabled

The RB field, B Port Register, selects one of the sixteen internal 2901
registers to be read and/or written by the 2901 ALU. If the AS field
contains a value of 58 or 78 , the A Port Register field (RA field) is forced
to the same value as the RB field.

TEST

The TEST field, TEST CONDITION < 03:00 >, selects one of sixteen
signals for the conditional operations of the sequencers. The hardware
includes two separate selectors, one for each of the two sequencers.

The BD field, bus destination, selects the register that will be written
with the data on the D OUT lines.

The @ field, lac EN ABLE, permits the lac field to modify the lac
Latches when set. This bit is not set when using the LITERAL field.

lac

The lac field, input/output control, if enabled by laC ENABLE(@),
modifies the lac Latches. Bits < 22:20 > select the desired latch, and bit
23 sets or clears that latch.

The RA field, A Port Register, selects one of the sixteen internal 2901
registers to be operated on by the ALU. The RA field is a shared field
and is only enabled if the AS field does not equal 5 or 7 and bit AB does
not specify the LITERAL field.

The BS field, bus source, selects one of the eight K. pli registers which
are external to the ALU. The contents of the selected register are enabled
onto the 0 IN lines, routed through the input multiplexer, and presented
to the 0 inputs of the 2901 ALU.

The S field, test sense, is XORed with the output of the Control and Data
Test Select multiplexer to generate TST COND TR (test condition true).
TST COND TR is then combined with branch address equal to 77778
and JUMP CNTL 1 to determine whether the sequencer will output the
Program Counter, the Stack, or the Branch Address.

7-3

PORT PROCESSOR MODULE

Table 7-1 (Cont.)

Microinstruction Word Field Description

Field

Description

The $ field, conditional execute, enables all instructions when clear.
When set this bit enables the conditional execution of the IOC, bus
destination, and ALU instructions.

The K field, jump controL is logically combined with TST COND TR and
BR ADR < 11:00 > equal to all ones (77778) to control the next operation
of the 2911 Sequencers.

The P field, instruction parity, is the single parity bit for the 48-bit microinstruction word.

The BA field, branch address, provides the instruction address for conditional and unconditional branches and subroutine calls. Also, during the
execution of certain instructions, this field provides supplemental data
and control information.

7.4 PORT PROCESSOR MODULE BLOCK DIAGRAM
Figure 7-2 is a block diagram of the K.pli showing the principal hardware elements and data paths. Each
of these elements will be described in the following sections.
7.5 SEQUENCERS
In the lower-left-hand corner of Figure 7-2 you will see the two sequencers. The use of these two
sequencers which alternately and independently access a common Control Store is the heart of the
K.pli architecture. The two sequencers, in conjunction with the Control Store and Arithmetic and Logic
Unit (ALU), are designated Control Sequencer and Data Sequencer. Each sequencer controls different
portions of the external interfaces, and each has separate and independent ftinctions.

The Data Sequencer handles all aspects of a data transfer between Data Memory and the PILA buffers.
During a data transfer, the Data Sequencer is busy (at the maximum data rate); at all other times it is
idle.
The Control Sequencer is responsible for all other work the K.pli does, incluq.ing examining queues for
work to do, acquiring and retiring buffers, and so on. The activity level of thIs sequencer is fairly high
and fairly constant.
.
One sequencer does not help out or share the work assigned to the other. Each sequencer has its own
job to do.
With a clock period of 150 nanoseconds, each sequencer has an apparent micro-cycle time of 300
nanoseconds. As a result, no effective time is lost by either sequencer when executing a branch since
the branching sequencer is accessing Control Store while the other sequencer is executing.

7-4

PORT PROCESSOR MODULE

The sequencers are the control section of the K. plio Each sequencer consists of three 2911 bit-slice
devices connected to form a 12-bit address. Figure 7--3 is a block diagram of one 2911. Each bit-slice is
4 bits wide and consists of the following logic:
•

Program Counter Register

•

Incrementer

•

Four Register Stack

•

Stack Pointer

•

Next Address Multiplexer

•

Internal logic to control these functions

The 12-hit address allows the sequencer to address 4 Kwords of Control Store. This address always
points to the next instruction by automatically increlnenting after the instruction fetch. The stack is 12bits wide and 4 words deep and is used along with the stack pointer during call and return operations.
The internal multiplexer within the sequencers is capable of choosing one of the following for output to
the program address register:
•

The Stack

•

The Program Counter Register

•

The branch address supplied from the Control Store

As connected on the K.pli, the sequencers perform the following operations:
•

CONTINUE-Increments the Progranl Counter Register by one and places the new address
on the SEQ ADR <11:00> lines.

•

RETURN FROM SUBROUTINE (pop stack)-Writes the Program Counter Register with the
current value of the stack and gates this value to the SEQ ADR < 11:00 > lines. The Stack
Pointer is then decremented.

•

JUMP TO BRANCH ADDRESS-Writes the Program Counter Register with the current value
of the branch address (supplied externally) and gates this address to the SEQ ADR < 11:00 >.
The Stack and Stack Pointer are not affected.

•

SUBROUTINE CALL (push stack)-Increments the Stack Pointer and pushes the current value
of the Program Counter Register onto the Stack. Writes the Program Counter Register with the
Icurrent value of BR ADR < 11:00 > and gates this address to SEQ ADR < 11:00>.

7-5

PORT PROCESSOR MODULE

Figure 7-2

Port Processor Module Block Diagram
DADR 16
DADR 17
DNMA
ALWAYS ZERO
ALWAYS ZERO
DATA NXM
DATA PAR ERR
DBUS OVRRN

ClK
ClK CTl
STOP
INH EXEC

CLOCK
CONTROL

RAM ERR
PLI ERR
REVISION
lEVEL
SWITCHES
RD DATA ERR

DEST ClK
SQNCR ClK
AlU ClK
CNTL PROC
DATA PROC

CNTl PROC ClR
DATA PROC ClR
COMBINED ClR
CLEAR IN

ROll--'
1
CLEAR I N - - - - - I
EXTERNAL STOP---.,
INSTR STOP--J

RAM ERR
PLI ER R
REVISION
lEVEL
SWITCHES
RD CNTl ERR

CLEAR
EXT RESET

15
EN

CADR 00
CCYClE 0
CCYClE 1
CCYClE 2
CBUS ERROR
CNTL NXM
CDATA PAR ERR
INSTR PAR ERR

INHIBIT EXEC

TST COND TR

RESET
CONTROL

PLI elK

Pli INITIALIZE
ClK PLI CNTl
D OUT 15
lWR PROC
INH EXEC
RD CNTl ERR
RD DATA ERR

D OUT 11:00

SEQADR 11:00

LD PADR REG

PROM 00-47

INSTRUCTION
PARITY
CHECKER
P6

CONTROL
STORE
4K BY 48

COMMON STATUS

PAR ERR INH

CARRY IN
PROM 44-46
PROM 41-43
PROM 38-40
PROM 37
PROM 36 D Q
PROM 14 D Q

PROM 25-27 D Q
INST
REG
ADRS

TST COND TR

ClK Pli CNTl
lD PLI DATA
lD RAM DATA
lD CRAM ADR
lD STATUS
SET CREQ
lD CNTl ADR
lD CNTl DATA
lD DRAM ADR
lD DADR REG
WRT DATA XCVRS
lD DATA BUS

~======1 S
ENA CNTl;
ENA DATA
INH EXEC

PADR
REG
CONTROL
SEQUENCER
2911

AlU DEST 2:0
AlU FUNC 2:0
AlU SOURCE 2:0
AlU TO BUS
EXEC IF COND TRUE
COND EXC
DEST
DECODER
BUS DEST 2:0

DEST ClK

P4
PROM 23 D
PROM 20-22 D

Q:~::::::::~~~~~~~:::::::SET
Q~

10C
10C SEl 2:0

PROM 24 D Q

COMMON 10C 7
COMMON 10C 6
ONE BYTE
EN STATUS
ROll
lTS GRN
CNTL PROC FLAG
RD MODE
PLI RVRS
PROC FLAG

CNTl PROC-----~-
lD PADR REG --r-r'T'""~"'/
PAR ERR INH

DATA
SEQUENCER
2911
ENA DATA

PROM 28-31~===~;-)
PROM 151----...,

PROM 13

ROll

PROM 00-11

BR ADR 11:00

P5,6

~~~~~~~~~~DATA

B REG 3:0
PROC FLAG
A REG 3:0
BUS SRC 3:0

SOURCE
DECODER

t=======Is
ENA CNTl

JUMP CNTl l

ENA DATA

TEST FOR TRUE

AlU TO BUS

TEST COND 3:0

RD PLI DATA
RD RAM DATA
RD CNTl ERR
RD CNTl ADR
RD CNTL DATA
RD DATA ERR
RD DADR REG
RD DATA BUS

eX-1056A

Sheet 1 of 2

(Continued on next page)

7-6

PORT PROCESSOR MODULE

Figure 7-,2 (Cont,,)

Port Processor Module Block Diagram

STATUS 7:0
B REG 3:0

D OUT 15:00

SET laC,
lac SEL 2:0

S ENABLE
ALU STATUS

D IN 15:00

ALU TO BUS
CARRY IN

ALU SRC 2:0,
ALU DEST 2:0,
ALU FUNC 2:0,
CARRY IN

CCYCLE 2:0

D IN 15:00

PAR TEST

DATA
PARITY
GENERATION

,...:D~O:.:::U.!.T...:1..!.1~:o~o_._ _-I~~gl;H ECK

La PARITY OUT
HI PARITY OUT
PAR ER ROR

DNMA
DBUS
ADDRESS
D OUT 15:00

D IN 15:00

~=======::::1D

SCRATCHPAD
512 X 18

D OUT 8:0

D OUT 15:08

D IN 15:08

D OUT 8:0

D OUT 7:0
DIN 7:0

PLI LINK CONTROL 3:0
D OUT 15:00
CONTROL
REGISTER

SEND TO PLI
PLI SEL 0
PLI SEL 1
DIAG MODE
INSTR PAR TEST
La PAR TEST
HI PAR TEST
INSTR STOP
HOST CLR

D GRANT
D TIMING

DBUS
CONTROL

RD DATA BUS
WRT DATA XCVRS
RD MODE

DGRNT
DREG ACTIVE

P2
SEND TO PLI
PLI RVRS
DIAG MODE
ONE BYTE
INHIBIT EXEC
RD PLI DATA
LD PLI DATA
START PLI

------l.__P:..;L;,;.I..:;S:.:;.E.;:.LE:.;C:.;T-(
PLI
CONTROL

SEND HI BYTE
SEND La BYTE
HI BYTE CLK
La BYTE CLK
HI BYTE TIME

P10

CX-1056A
Sheet 2 of 2

7-7

PORT PROCESSOR MODULE

Figure 7-3 2911 Sequencer Block Diagram

-f\
11

PUP
EN

STACK POINTER

FOUR REGISTER STACK

~
BR ADR

J.7

~SO
-

~ S1

",t

"'.7 "-.7'

RNEXT ADDRESS
F

~
REGISTER

MULTIPLEXER

~ ZERO

INCREMENTER

"'1'1
SEQUENCE ADDRESS
CX-1235A

7-8

PORT PROCESSOR MODULE

7.6 TEST MULTIPLEXER
The sequencers must have the ability to test different conditions on the K. pli, PILA, and LINK. Figure 7-2
shows two multiplexers just above the two sequencers. They are two separate 16-input multiplexers to
select test conditions for the two sequencers. Bits 31 through 28 of the Control Store generate TEST
COND < 3:0 > which select one of the 16 inputs. Either the true or the complement of the selected
test condition may be selected. This is accomplished by the TEST FOR TRUE (bit 15 from the Control
Store). A synchronization circuit is included to guarantee correct testing of asynchronous test conditions.
Available test conditions include:

•

PORT ILINK Interface (PLI) status

•

Arithmetic Logic Unit (ALU) status

•

[nput/Output Control (laC) Latches

•

Error indicators

7.7 PROGRAM ADDRESS REGISTER
The sequencers address the Control Store through the Program Address Register shown in Figure 7-2.
This register alternately accepts the outputs of one sequencer or the other on each clock cycle and
presents the instruction address to the Control Store for the fetch operation. The fetch cycle for one
sequencer occurs in parallel with the execute cycle of the other sequencer.

The sequencer outputs may be disabled and the Program Address Register forcibly written from the
ALU by LD PADR REG. For example, the ALU may execute a calculated jump by calculating the jump
address from a table and writing the data to the Program Address Register from D OUT < 11 :00>.
During this time, the outputs of the sequencers are disabled.
7.8 CONTROL STORE
The PROM Control Store is shown in Figure 7'-2 to the right of tbe sequencers. All microcode instructions
are contained in the Control Store. It is 48 bits wide (including parity). The Control Store consists of
twelve 2K by 8 PROMs, with a maximum access time of 90 nanoseconds. One microinstruction is
fetched from the Control Store during each 150 nanosecond clock cycle. At the end of the clock cycle,
the microinstruction is written into the latch where it is held for the following execution cycle.

The Cont:rol Sequencer has the ability, in diagnostic mode, to command the Data Sequencer to fetch
and test parity consecutively in all Control Store locations. This is accomplished with the ROLL signal
on the output of the lac latches.
A detailed description of each of the bits in the microinstruction is covered in Section 7.25.
7.9 ARITHMETIC AND LOGIC UNIT
Figure 7-2 shows the Arithmetic and Logic Unit (ALU) in the upper-right-hand side. The ALU is implemented with four 2901 bit-slice devices, providing a 16-bit data path. The 2901 bit-slice ALU chip
can perform addition, subtraction, and logic operations. Its internal data paths and registers are four
bits wide (Figure 7-4). Nine control signals and eight register-select lines determine the ALU function,
operand source, and destination.

The ALU has the following characteristics:
•

A 2-port RAM comprised of 16 registers. The RAM registers are read via their A or B Data Out
JPorts.

•

A 4-bit shift register on the RAM data input. The output of this register is connected in ring
counter fashion to the input.

•

A 4-bit Q register for assisting with multiplication and division algorithms.

7-9

PORT PROCESSOR MODULE

Figure 7-4

2901 ALU Block Diagram

..
A REG 3:0
RAM
16 ADDRESSABLE
REGISTERS
B REG 3:0
A
DATA
OUT

B
DATA
OUT

LOGIC 0
DIRECT INPUT

ALU SOURCE
OPERAND DECODE

R
ALU SOURCE 2:0

ALU FUNCTION
DECODE

C IN
8-FUNCTION ALU

C N+4
F S (SIGN)

OVERFLOW
F=OOOO

ALU FUNC 2:0

OUTPUT DATA SELECTOR

ALU DESTINATION
DECODE

D OUT

ALU DEST 2:0
CX-1236A

7-10

PORT PROCESSOR MODULE

•

A 4-bit shift register on the Q register input.

•

A multiplexer that selects the output of the Q register shifter or the ALU output for input to
the Q Register.

•

Two multiplexers that select the ALU inputs. These inputs may be the direct input, the A or B
RAM, logic zero, or the Q Register.

•

An output multiplexer capable of selecting the ALU output or port A of the RAM and gating it
to D OUT.

•

A 2-input ALU capable of performing the operations shown in Table 7-2.

Table 7-2

ALU Operations

Operation

Operands Used

Addition

R + S
R + S + 1

Subtraction

R-S
S-R
R-S-1
S-R-1

Logical OR

ROR S

Logical AND

RAND S

Logical NOTRS

(NOT R) AND S

Logical XOR

R XOR S

Logical XNOR

R XNOR S

Organization of the 2901 is such that shift operations are separate from, and independent of, the arithmetic and logical operations and are effective only on the inputs to the internal Q and RAM registers.
The resullts of ALU operations are not shifted at the Y outputs. The ALU state flags reflect the ALU
results before any shift.
Shifts may be performed at the RAM register inputs or at the inputs of both the RAM and Q registers
in one instruction. All are sixteen bit shifts, and the ALU carry is never affected by any shift operation.
Shifts performed on the Q register are end off; that is, on a left shift the contents of bit 15 are lost, and
on a right shift the contents of bit 00 are lost. Shifts performed on the RAM registers are circular; that
is, on a left shift the contents of bit 15 appear in bit 00, and on a right shift the contents of bit 00 appear
in bit 15.
7.10 PIPELINING CONCEPTS
Now that you have read about the elements that make up the computing power on the K.pli, let's look
at how the sequencers, Program Address Register, Control Store, and the Instruction Register form
a pipeline. Pipelined designs decrease instruction cycle time by performing fetch and execute operations in parallel (Figure 7-5). The Instruction Register holds the current microinstruction that controls
the processing section and helps the control sections select the next address. Thus, the processing
sections are operating on the current microinstruction while the control sections are fetching the next
microinstruction from the Control Store.

7-11

"'tJ

:lJ

-t

"'tJ
:lJ

o
(')

en
en

:lJ

Figure 7-5

s:
o

K.pli Double Pipelining

I"""

CONTROL
SEQUENCER
PROGRAM
ADDRESS
REGISTER

CONTROL
STORE

INSTRUCTION
REGISTER

DATA
SEQUENCER

BR ADR 11:00
TEST FOR TRUE
TEST COND 3:0

CX-1058A

PORT PROCESSOR MODULE

7.11 K.lPli PIPELINE
The K.pli uses a form of microinstruction/address/status pipelining (double pipelining). Registers are
provided for the current microinstruction (Instruction Register), the sequencer address (Program Address
Register), and the ALU/real-time status (Test Select multiplexers). These three registers provide the
double pipelining design with three parallel paths. These paths simultaneously perform the following
operations:
•

The current microinstruction is gated into the Instruction Register. It controls the ALU along
with the branch address of the Control and Data Sequencers.

•

The sequencers generate a new value for the Program Address Register.

•

The current value in the Program Address Register fetches the next microinstruction for the
Control Store. Control Store bits < 31:28 > select the test conditions for the Test Select multiplexers.

7.12 PI1~ELINE TIMING
Figure 7-6 shows the timing for a instruction fetch-execute sequence. The SQNCR CLK supplies the
timing fOlr all the control timing. CNTL PROC is high when the Control Sequencer is active. CNTL PROC
is low when the Data Sequencer is active. The timing in Figure 7-6 starts with the Control Processor
gating the address on SEQ ADR < 11:00 >. Then the following steps occur:
•

•

On the high to low transition of CNTL PROC:
•

The address from the Control Sequencer is clocked into the Program Address Register

•

The Data Sequencer gates its program address onto SEQ AD R < 11: 00 >

•

The Control Store accesses the microinstruction for the Control Sequencer

On the high to low transition the next CNTL PROC signal:
•

The microinstruction word is clocked into the Instruction Register to be used by the
Control Sequencer in its next cycle

•

The program address of the Data Sequencer is clocked into the Program Address
Register

•

The Control Sequencer gates its program address onto SEQ ADR < 11 :00 >

The steps listed above tend to indicate an order of operation. However, SQNCR CLK occurs at the
same tim.e on the sequencers, Program Address Register, and Instruction Register. As a result, their
operations occur simultaneously.
7.13 SCRATCHPAD MEMORY
The K.pli has a Scratchpad Memory of 512 words of 16 data bits and 2 parity bits. The memory is written
or read under microcode control (Figure 7-2). Included are two 9-bit Scratchpad address registers, one
for each ()f the two sequencers:
•

CRAM ADRS

•

DRAM ADRS

The address registers are loaded, but not read, by microcode. The Scratchpad data may be accessed by
either sequencer.

7-13

PORT PROCESSOR MODULE

Figure 7-6

Pipeline Timing for an Instruction Fetch-Execute Sequence

SONCR CLK L

100

CNTL PROC H

100

ADDRESS C I

I
I
I

2911 j.LPC CONTENTS
(CNTL PROC)

2911 }LPC CONTENTS (DATA PROC)

I
I

CLOCK INTO PADR REGISTER - - - - I.~I
.

ADDRESS 0 I
.. I

I
I

ADDRESS C+2
I

ADDRESS 0+1

I ADDRESS 0+2

I
I

PADR REGISTER CONTENTS

I
I

ADDRESS C+1

\I
FETCH C I

FETCH 0 I
CLOCK INTO INSTRUCTION REGISTER------~------1..
~1

,
,

INSTRUCTION REGISTER CONTENTS

I
EXECUTE C I

CLOCK INTO TARGET REGISTER - - - - - - - - - - - - I..
~I

\I
FETCH C+1 J

FETCH 0+1 I

FETCH C+2

EXECUTE oj
... ,
I

EXECUTE C+1 EXECUTE C+2
I

RESULTC I

RESULT C+1

TARGET REGISTER CONTENTS (CNTL PROC)

TARGET REGISTER CONTENTS (DATA PROC)

RESULTD

CX-1237A

Because of the lack of decoding bits, some signals have to be shared. The generation of LD CRAM
ADR is one of these signals (Figure 7-7). The decode of a 7 from the Control Sequencer Bus Destination
Decoder enables LD STATUS or LD CRAM ADR depending on the state of the EN STATUS signal
from the Control IOC Latch bit 3. If IOC 3 is set, the Control Sequencer Scratchpad Address Register
is written to.
7.14 STATUS REGISTERS
The Control and Data Sequencers read the two Status Registers to determine status in the K. pli or PLI
Interface. Figure 7-2 shows the two registers in the center top of the block diagram. Figure 7-8 shows
the two registers. These two registers are made up of different pieces of logiC throughout the K. plio

7-14

PORT PROCESSOR MODULE

Figure 7-7

Generation of LD CRAM ADR
CONTROL
IOC
LATCH

EN STATUS L
3FD-----------------------~--~------_Q

LD STATUS L

P3
LD CRAM ADR L

CONTROL SEQ
BUS DESTINATIONS

7Fp-------------__________________

P3
CX-1059A

The RD CNTL ERR signal reads the six status bits associated with Control Memory, Scratchpad, and
PLI Interface accesses. It also reads the CCYCLE lines, the Control Memory Address least significant
bit, and the six revision level bits. Control error bits 4, 5, 6, 7, and 8 are automatically cleared following
a RD CNTL ERR. They are also cleared if the Control Sequencer writes the Control Register with data
bit 15 set:.
The RD DATA ERR signal reads the five status bits associated with Data Memory, Scratchpad, and PLI
Interface accesses. It also reads the DNMA bit, the two most significant Data Address bits, and the
six revision level bits. Data error bits 5, 6, 7, and 9 are automatically cleared following a RD DATA
ERR signal. They are also cleared if the Data Sequencer writes the Control Register with data bit 15 set.
Table 7-3 shows the bit assignments of these two registers.

7-15

PORT PROCESSOR MODULE

Figure 7-8

Status Registers

DADR 16
DADR 17
DNMA
ALWAYS ZERO

ALWAYS ZERO
DATA NXM
DATA PAR ERR
DBUS OVRRN

4
5
6
7

RAM ERR
PLI ER R
REVISION
LEVEL
SWITCHES

8
9

RD DATA ERR

CADR 00
CCYCLE 0
CCYCLE 1
CCYCLE 2
CBUS ERROR
CNTL NXM
CDATA PAR ERR
INSTR PAR ERR

1
2
3

10
15
EN

o
1
2
3
4

5
6
7

P1
RAM ERR
PLI ERR
REVISION
LEVEL
SWITCHES
RD CNTL ERR

8
9
10
15
EN
P8
D OUT 15:00

CX-1060A

7-16

PORT PROCESSOR MODULE

Table 7-3

Status Registers Bit Assignment

Control Sequencer

Data Bit

Data Sequencer

CADR 00

DIN 00

DADR 16

CCYCLE 0

DIN 01

DADR 17

CCYCLE 1

D IN 02

DNMA

CCYCLE 2

DIN 03

Always zero

CBUS ERROR

DIN 04

Always zero

CNTL NXM

DIN 05

DATA NXM

CDATA PAR ERR

DIN 06

DATA PAR ERR

INSTR PAR ERR

DIN 07

DBUS OVRRN

RAM ERR

DIN 08

RAM ERR

PLIERR

DIN 09

PLI ERR

Revision level

D IN < 10:15>

Revision level

The following error bits are ORed together into CNTL ERR SUM signal that is an input to the Control
Test Select multiplexer:
•

CBUS ERROR

•

CDATA PAR ERR

•

CNTL NXM

•

INSTR PAR ERR

•

RAM ERR

The following error bits are ORed together into DATA ERR SUM signal that is an input to the Data Test
Select multiplexer:
•

PLI ERR

•

DBUS OVRRN

•

RAM ERR

•

DATA PAR ERR

•

DATA NXM

The six r,evision level bits are encoded to represent K.pli revision levels shown in Table 7-4.
NOTE

Switches 7 and 8 are not used.

7-17

PORT PROCESSOR MODULE

Table 7~4

K.pli Revision Level Switches

Switch Number

Board Rev. C

7.15 STATUS BUS REGISTER
The Status Bus Register is gated onto the backplane by the P .ioc to check the status of the host interface
modules. This register is written to by K. pH microcode after every major state change within the K. pH
microcode. The Status Bus Register is shown in the upper-right-hand corner of Figure 7-2. The Status
Bus Register is written to by microcode from 0 OUT < 14:08,HP >. Notice that bit 7 is the parity bit for
the other 7 bits. Figure 7-9 shows the Status Bus Register and Table 7-5 describes the bits.
Figure 7-9

Status Bus Register

AOY r-- STATUS 00
D OUT 08

D OUT 10 D OUT 09

DO
D1
D2

D OUT 11

D OUT 12

STATUS 02

A3Y

STATUS 03

BOY

r- STATUS 04

B1Y

r- STATUS 05

B2Y

STATUS 06

B3Y

STATUS 07

STATUS 01

rC EN

- D5
6R
D6
D OUT 14 7R
HI PARITY OUT D7
CLEAR IN --c ClR
lD STATUS ClK

A2Y A1Y

D OUT 13

TO
P.ioc/P.ioj

B2
B3
-0

EN
P8

S ENABLE l
(FROM P.ioc/P.ioj)

CX-1061A

7-18

PORT PROCESSOR MODULE

Table 7-5

Definitions of Status Bus Register Bits

Status Bus Register Bits

Initial state resulting from clearing the K. (Note the bad
parity indication.)

Value resulting if no K is present. (Note the bad parity
indication.)

K.pli passed its internal diagnostics.

K. pli has declared a structure error in the system and performed an interrupt cycle on the Control Bus with priority
7. The error was detected by operational microcode. The E
is the error code. Refer to the service manual for the error
code.

A fault was detected by the diagnostics. The F is the failing
test number. Refer to the service manual for the failing test
numbers.

P is the Parity bit
Because of the lack of decoding bits, some signals have to be shared. The generation of LD STATUS
is one of these signals (Figure 7-7). The decode of a 7 from the Control Sequencer Bus Destination
Decoder enables LD STATUS or LD CRAM ADR depending on the state of the EN STATUS signal
from the Control IOC Latch bit 3. If IOC 3 is reset, the Status Bus Register is written to.
7.16 CONTROL BUS INTERFACE
The Control Bus Interface is associated with the Control Sequencer and is used to access the HSC Control
Memory that contains the control structures defining the work to be performed by K. plio The Control
Sequencer scans predefined areas of this memory for work and manipulates the control structures. The
K.pli is capable of maintaining data rates up to 2.22 megabytes per second on this bus. For Control
Bus timing information, refer to Chapter 3. The Control Bus Interface is shown in the upper-right-hand
corner of Figure 7-2.
The interface is implemented with 2917 A type latched bus transceivers plus a separate byte parity
generator, which is shared with the:
•

Data Memory Interface

•

PLI Interface

•

Scratchpad

The Control Bus Address Transceivers are read or written by microcode. When a Control Memory
write is performed, the hardware provides an automatic wrap around so that the contents may be read
and verified. These transceivers are latches only. The Control Bus Address must be incremented by
microcodle and rewritten for each Control Memory access. Note that the result obtained from reading
the Control Bus Address does not have the same organization required when writing it (Figure 7-10).
The valwe obtained from reading the transceivers is the address used in the last completed bus cycle.

7-19

"o-t
"
o
JJ
JJ

(')

en
en
o
JJ

s:
o

Figure 7-10 Control Memory Address Register

c:
r0-

m
QUAD
XCVR

REC

RD CNTL ADR L
CADR CLK L

QUAD
XCVR

0
1
2
3

D IN 15 H
D IN 14 H
D IN 13 H
D IN 12 H

EN
LATCH

REC

0
1
2
3

DIN 11 H
D IN 10 H
D IN 09 H
D IN 08 H

EN
LATCH

REC

QUAD
XCVR

0
1
2
3

D IN 07 H
D IN 06 H
D IN 05 H
D IN 04 H

REC

EN
LATCH

QUAD
XCVR

D IN 03 H
D IN 02 H
D IN 01 H
D IN 00 H
RD CNTL ERR L

REC

0
1
2
3

D IN 00 H
D IN 01 H
D IN 02 H
D IN 03 H

EN
LATCH

""-l
I

N
0

CADR 16 L
CADR 15 L
CADR 14 l
CADR 13 L

D OUT 15 H
D OUT 14 H
D OUT 13 H
D OUT 12 H
CGRANT l
lD CNTl ADR l

0
1
2
3

BUS

0
1
2 XMIT
3
EN
ClK

CADR 12 L
CADR 11 L
CADR 10 l
CADR 09 L

0
1
2
3

D OUT 11 H
D OUT 10 H
D OUT 09 H
D OUT 08 H

0
1
2 XMIT
3
EN
ClK

BUS

CADR 08 L
CADR 07 L
CADR 06 L
CADR 05 l

0
1
2
3

D OUT 07 H
D OUT 06 H
D OUT 05 H
D OUT 04 H

0
1
2 XMIT
3
EN
ClK

BUS

CADR 04 L
CADR 03 l
CADR 02 l
CADR 01 l

0
1
2
3

D OUT 03 H
D OUT 02 H
D OUT 01 H
D OUT 00 H

0
1
XMIT
2
3
EN
ClK

BUS

CADR 00 L
CCYClE 0 l
CCYClE 1 L
CCYClE 2 l

0
1
2
3

BR ADR 11 H
BR ADR 10 H
BR ADR 09 H
BR ADR 08 H

0
1
2 XMIT
3
EN
ClK

BUS

CX-l062A

PORT PROCESSOR MODULE

The Control Bus Data Transceivers may be read or written by microcode. When a Control Memory
write is performed, the hardware provides automatic wrap around so that the contents may be read and
verified. This read is in exactly the same organization as a word that was gated to the data transceivers
(including parity). The value obtained does not represent what is actually in memory as a result of the
bus write (although this would be the typical result), but only what the K.pli transceivers placed on the
backplane bus lines during the bus cycle.
Control ~r1emory Cycles are initiated when SET CREQ is specified in Control Store BUS DEST < 2:0>.
During execution of this instruction BR ADR < 10:8> determine the type of bus cycle to be performed,
and BR ADR 11 controls the least significant address bit (Figure 7-10).
7.17 DATA BUS INTERFACE
The Data Bus Interface is similar to the Control Bus interface, except that it is associated with the Data
Sequencer and is used to access the HSC Data Memory during data transfers. Data to be sent to the
node on the CI is read from Data Memory, while data obtained from the node is written into Data
Memory ]prior to being routed to the next process associated with the data transfer. The K.pli is capable
of maintaining data rates up to 6.66 megabytes per second on this bus. For Data Bus timing information
refer to Chapter 3.
7.17.1
Data Bus Data Transceivers
The Data Bus Data Transceivers are read or written by microcode, and the value obtained when reading
the Data Transceivers has exactly the same format as that required to write them. When a Data Memory
write is performed, the hardware provides an automatic wrap around so that the data and address
contents may be read and verified. The value obtained does not represent what is actually in memory
as a result of the bus write (although this would be the typical result), but only what the transceivers
placed on the backplane bus lines during the bus cycle.
Data Bus cycles are initiated by either write loading (which initiates a write cycle) or reading (which
initiates at read cycle) the Data Bus Data Transc;,eivers.
The Data Bus Data. Transceiver Drivers are controlled by the RD MODE signal from Data lac Latch bit
3. If RD ~v10DE H is low, these drivers will not drive the bus. If RD MODE H is high, these drivers will
be gated onto the bus during each Data Bus cycle. This is true regardless of whether a cycle is initiated
by a write load or a read of the data transceivers.
NOTE
The term read refers to the PILA, not to Data Memory.
7.17.2
Data Bus Address
This interface consists of 2917 A-type latched bus transceivers, but it includes an up/down counter for the
address. The Data Bus Address Transceivers and counter are written by microcode, and the transceivers
may be f€!ad by microcode. Note that the result obtained from reading the Data Bus Address Transceivers
does not have the same organization as that required when writing it (Figure 7-11). The value obtained
from reading the transceivers is the address used in the last completed bus cycle.
The Data Bus address is 18 bits wide. The twelve least significant address bits are derived from a counter
which is ,automatically incremented (or decremented) at the end of each Data Bus cycle. Normally, the
address i.s written prior to beginning a block transfer, and it need not be rewritten while the block
transfer is in progress. However, this counter will not cross 4 Kword boundaries.

7-21

Figure 7-11 Data Bus Address Transceivers and Counter

QUAD
XCVR

o r - 0 IN 15 H

~ ~ ~ :~ ~i ~

REC

---< EN
--;-c LATCH

r----------------ct

DADR
oAoR
DAoR
oAoR

15 l
14 l
13 l
12 l

--- -c
-c

-<1
2
-<l3

DAoR 11 l
DADR 10 l
DADR 09 l
oAoR os l

BUS

--cl
--cl

DAoR 07 l --C a
DAoR 06 l ~ 1
oADR 05 l --cl 2
DADR 04 l --C 3

8US

'---

----

r---------1r+_+-+-~-------c1I

'---

~-------1r+_+-+-_+------t

J
UP/DOWN
COUNTER

UP/DOWN
COUNTER
R8
o OUT 06 H - 08
R4

R8
o OUT 02 H - 08

R4
o OUT 01 H - 04

o OUT 05 H - 04
R2
o OUT 0 4 H - 02
R1
o OUT 03 H - 01

R2
o OUT 00 H - 02

r - - - 01

, - ClK

- : . . . - UP/oRN
-

EN
lOAD

DAoR 03 l
DAoR 02 l
DADR 01 l
oADR 00 l

EN
ClK

--c 1
--c 2
--c 3

...------1 1
.-----~ 2

r-----_+-f--+-t---c1I EN
~----+-f--t-t----I ClK

"----

r-- 0 IN 00 H

+3.0VA ~
DNMA H --c
DAoR 17 l --c
DADR 16 l -<l

8RADR09H~
BR ADR 10

0
1
2
3

BUS

c::

L:: ~

o OUT 12 H -I-- 2 XMIT
o OUT 11 H -I-- 3
EN
lo DAoR REG l r--L-_
ClK _...1

-:!:-

R8 r -

D8
R4

r - - - 04

R2
02

r- 01

RIP ClK 0--ClK
UP/oRN

RIP ClK
ClK
UP/oRN

EN
lOAD

60 FF
RO
o OUT 04 H-- DO

Rl
o OUT 03 H - 01
R2
D OUT 02 H - 02
R3
D OUT 01 H - D3
R4
D OUT 00 H - D4
R5

!I~

CLEAR IN l
LD DADR REG L

D5
ClR
ClK

(')
CJ)
CJ)

UP/DOWN
COUNTER

"V
:D

BUS

XM IT

RD DATA ERR l--< EN
lATCH

-c 0

r-......--------..... a

.--------------1 a
.--------------i
1
......__________~ 2 XMIT
.-------1 3

3
EN
ClK

3r------------------_i

f---

BUS

~~------------------___i REC ~ ~ ~ :~ g~ ~

REC

~-------------<lI EN
~---------------d lATCH

I----

1
2 XMIT

-<l EN
ClK

DREQ FF H

lD DADR REG l

r---------------------d, lATCH
....--

o
o I--- 0 IN 03 H

O~-------------_i

~ ~ ~ :~ g~ ~

QUAD
XCVR

r---

3 r - DIN 04 H

-a

o OUT 10 H - - 0
o OUT 09 H -- - 1
o OUT os H -- _ 2 XMIT
o OUT 07 H - - 3

PLI RVRS H

REC

~------------------------_qEN

1
--cl 2
--cl 3

lo DADR REG l -

~ ~ ~ :~ ~~ ~

r---------------~EN
LATCH

QUAD
XCVR
o r - 0 IN 07 H

3 I-- 0 IN os H

3 r - 0 IN 12 H
RD DAoR REG l
DGRNT l

r-- 0 IN 11 H

r---

QUAD
XCVR

CX-1063A

PORT PROCESSOR MODULE

Figure 7-12 shows a simplified block diagram of how the Data Bus address is encoded. When the
microcode asserts LD DADR REG, the following registers are written to:
•

D OUT < 04:00 > are gated into the five bit latch

•

D OUT <06:00> are gated into the counter bits <11:05>

•

D OUT < 12:07> are gated into Data Bus Address Transceivers

•

The previous contents of the 5-bit latch are gated into counter bit < 04:00 >

Figure 7-12

Generating the Data Bus Address

MSB

BF BUS

LSB

'--y---'
NOT USED

I4312110
I II
LATCH

111 110 19 1 8 1 ~y:y= 1 4 1 3 1 2 1 1 0

DNMA

MSB

DATA BUS ADDRESS TRANSCEIVERS

LSB
CX-1216A

7-23

PORT PROCESSOR MODULE

Note that counter bits < 04:00 > are derived from the latch, not directly from the 0 OUT lines. In order
to correctly write the entire address, LD DADR REG must be executed twice. The first write would
place the desired contents of address < 04:00 > on 0 OUT < 04:00 >. The second write should place
the desired contents of address < 17:05> on 0 OUT < 12:00 >.
The procedure to start a data transfer is:
1.

Write the least significant five address bits

Write the remainder of the address

Perform one dunlmy data read (if it is a memory read operation)

Move a data word, conditioned on completion of previous word

Repeat the above step until the transfer is complete

7.18 PLI INTERFACE
The PLI Interface interconnects the K. pli to the LINK and PILA which it controls. This interface provides
paths between modules for:
•

Data transfer

•

Status transfer

•

Control between K. pli, PILA, and LINK

This interface is capable of data rates up to 6.66 megabytes per second.
7.18.1
PLI Data Bus and PLI Control
The PLI Data Bus is bidirectional and consists of eight data lines and two parity lines. This bus is used
to:
•

Transfer data to and from the PILA buffers

•

Receive status from the PI LA and LINK

•

Transfer commands to the PILA and LINK

The microcode determines how it is going to use the PLI Data Bus and sets: the PLI LINK CONTROL
< 03:00 > before issuing a read or a write to the PLI Data Bus.
The PLI Data Bus logic consists of a 16-bit PLI Data Transmit Register, a 16-bit PH Data Receive Register,
and the logic to:
•

Transfer 16-bits from the PLI Data Transmit Register to the PILA over the 8-bit PLI Data Bus
(This is accomplished by transferring two bytes of 8-bits each.)

•

Transfer two 8-bit bytes from the PI LA to the PLI Data Receive Register

The PLI Data Bus logic is located in the middle-right of Figure 7-2. The PLI Control logic is located in
the lower-right corner of the block diagram.
The following three signals control how the data is transferred between the K. pH and the PILA (Figure 7-13).
•

SEND TO PLI

•

ONE BYTE

•

PLI RVRS

7-24

Figure 7-13

PLI Interface Registers and Control
PLI DATA
TRANSMIT REGISTER

D OUT 15:08

SEND HI BYTE l

r- ClK

D OUT 07:00
EN
ClK

lD PLI DATA l

PLI DATA
RECEIVER REGISTER

SEND TO PLI H

cI- J"-

l H'

<r-

SEND lO BYTE l

-../

SQNCR ClK l

-{>-J

INHIBI T EXEC H STAR T SlCT l -

HI BYTE ClK l

-i~
./

lO BYTE ClK l

--.S

~
J

p---

U ,-

lI-

D IN 07:00

rrr-

'II

----<l EN

ClK

-<l EN

'1J

+3V

::0

RD PLI DATA l -

'1J

::0

ZERO ENA ~~ PLI SELECT l
DIAG MODE l
HI BYTE TIME H

en
en

1 J

'-K
ClR PLI l

ClK

PLlRVRSH-~
C

PLI DATA 07:00

I-

PLI~~

START
PLI DATA l

..
r--< EN

b- I~

HI BYTE T IMEH

.II

D IN 15:08

::u

ONE BYTE H
CX-1064A

o
c

c:
rm

PORT PROCESSOR MODULE

Table 7-6 describes what happens with the data for the different configurations of these three signals.

Table 7-6 Control of Data Transfers Between the K'Eli and the PILA
SEND TO PLI

ONE BYTE

PLI RVRS

Description

The RD PLI DATA signal initiates a two-byte transfer from the PI LA to the K. plio The first byte is
gated into the low byte and the second byte is
gated into the high byte of the 16-bit PLI Interface
Receive Register.

The START PLI signal initiates a two-byte transfer from the K. pli to the PILA. The low byte (bits
< 07:00 » of the 16-bit PLI Interface Transmit Register is sent before the most significant byte (bits
< 15:08».

The RD PLI OAT A signal initiates a one-byte transfer from the PILA to the K. plio The byte is gated
into the low byte of thePLI Interface Receive Register. All zeros are gated into the high byte of the
K. pli register.

The START PLI signal initiates a one-byte transfer
from the K. pH to the PILA. The low byte of the PLI
Interface Transmit Register is sent to the PILA.

The RD PLI DATA signal initiates a one-byte transfer from the PILA to the K.pH. The byte is gated
into the high byte of the PLI Interface Receive Register. All zeros are gated into the low byte of the
K.pli register.

The START PLI signal initiates a one-byte transfer
from the K. pli to the PILA. The high byte of the PLI
Interface Transmit Register K. pli register is sent to
the PILA.

The RD PLI OAT A signal initiates a two-byte transfer from the PILA to the K. plio The first byte is
gated into the high byte, and the second byte is
gated into the low byte of the PLI Interface Receive
Register.

The START PLI signal initiates a two-byte transfer
from the K.pli to the PILA. The high byte of the
PLI Interface Transmit Register is sent before the
the low byte.

The timing for double byte and single byte reads and writes are shown in the following figures:
•

PLI Interface Double Byte Read (Figure 7-14)

•

PLI Interface Single Byte Read (Figure 7-15)

7-26

PORT PROCESSOR MODULE

•

PLI Interface Double Byte Write (Figure 7-16)

•

PLI Interface Single Byte Read (Figure 7-17)

PLI Status
7.18.2
In order to perform its job, the K.pli must check the status in the PILA and LINK. This is accomplished
in one of two ways:
•

Over the PLI Data Bus using one of the following commands generated by the Control Register:
•

Read receive status

•

Read transmitter status

These two commands are described in Chapter 6.
•

Through the Test Select multiplexers described in this section.

The Test Select multiplexer has 19 PLI status indicator inputs (Figure 7-18). Three status indicators are
directly selected a.nd generated from the Control Register (Section 7.19). The other 16 status indicators
are multiiplexed through multiplexers, PI LA Status Select 0 and 1. The status pair to be selected is
determined by:
•

SEND TO PLI

•

PLI SEL 1

•

PLI SEL 0

Table 7-7 describes the function of these status indicators.

Table 7-~r

Directly Connected Status Indicators to the Test Select Multiplexers

Signal

Description

Enable ARB

Indicates whether the LINK Arbitration logic is enabled or disabled.

PLI RECEIVER STATUS 1

This line is a spare input to the PLI Test Select multiplexer.

FIRST BUFFER

Indicates which buffer was filled first when both RECEIVE BUFFER
A FULL and RECEIVE BUFFER B FULL are both set or both cleared,
where:

o = Buffer B was filled first
1 = Buffer A was filled first
BUFFER A BUS

Indicates the CI path that carried the last received packet in Receiver
Buffer A, where:

o = CI path A
1 = CI path B
XMTR BUSY

The LINK asserts this line when a transmit sequence is in progress
or when XMTR ATTN is asserted.

ACK

The LINK asserts this line when it receives an ACK packet from the
destination node.

7-27

PORT PROCESSOR MODULE

Table 7-7 (Cont.)

Directly Connected Status Indicators to the Test Select Multiplexers

Signal

Description

DEST BUSY

The LINK asserts this line when it receives a NACK packet from the
destination node.

ARBITRATE

The LINK asserts this line when the arbitration count has expired
after a transmit command.

RCVR A EN

The LINK asserts this line when receiver ;path A is enabled.

RCVR B EN

The LINK asserts this line when receiver ;path B is enabled.

BUFFER B BUS

Indicates the CI path that carried the last received packet in Receiver
Buffer B on the PILA, where:

o = CI path A
1 = CI path B
XMIT ABORT

The LINK asserts this line when a transmission is aborted by the
abort transmission command.

CRC ERROR

The LINK asserts this line when it detects a CRC error on the received message or data packet.

CDA

Indicates the state of the carrier on CI path A, where:

o = Carrier A off
1 = Carrier A on

CDB

Indicates the state of the carrier on CI path B, where:

o = Carrier B off
1 = Carrier B on
XBUF PE

The LINK asserts this line when it detects a parity error in the transmit data during a transmission. A parity error asserts XMTR ATTN
and aborts the transmission.

PLI XMTR ATTENTION

The LINK asserts this line when there is a response to a transmit
command. The response may be caused by an ACK, NAK, transmit
parity error, or transmit abort.

PLI RCVR BUFFER A FULL

The PILA asserts this line when Receive Buffer A, in the PILA, contains a valid block of data or a packet (in the PILA).

PLI RCVR BUFFER B FULL

The PILA asserts this line when Receive l3uffer B, in the PILA, contains a valid block of data, or a packet.

7-28

PORT PROCESSOR MODULE

Figure 7-14

PLI Interface Double Byte Read Timing Diagram

CLK PLI CNTL H

LOAD CONTROL REGISTER
D OUT 1!5:00 H
SEND TO PLI H
RD PLI DATA l

,
,

D IN 15:00 H

BYTE 2 3

START SlCT l
PLI SELECT FF l

PLI SE lECT l

HI BYTE TIME H
ZERO ENA l
lO BYTE ClK l

HI BYTE ClK L

ClK BYTE 0

... ,

"'1

,
50

1
CLKBYTE1------~

"'1

PLI DAT,A 7:0 H

(

BYTE 0

1
... 1

ClK BYTE 3

BYTE 1

BYTE 2

BYTE 3

>--

CX-1238A

7-29

PORT PROCESSOR MODULE

Figure 7-15

PLI Interface Single Byte Read Timing Diagram

---'r5Ol

P_l_I_C_l_K_H_ _

100

ClK PLI CNTl H

lOAD CONTROL REGISTER----~
D OUT 15:00 H
SEND TO PLI H
RD PLI DATA l

140

D IN 15:00 H

BYTE O.ZERO

START SlCT l

PLI SELECT FF l

140

140
I
11

150

PLI SELECT l

HI BYTE TIME H
ZERO ENA l
I

lO BYTE ClK l

1L2£J

HI BYTE ClK l

ClK BYTE 0

--I

I
I
ClK BYTE 1
1

II2£J
I
--I

1L2£J1
~

PLI DATA 7:0 H

7-30

BYTE 0

I~~

ClK ZERO

I
I
I

ClK ZERO

BYTE 1

"'1

)-CX-1239A

PORT PROCESSOR MODULE

Figure ,r-16

PLI Interface Double Byte Write Timing Diagram

ClK PL./ CNTl H
I

lO,L\D CONTROL REGISTER--~
D OUT 15:00 H
I

BYTE 0, BYTE 1

SEND TO PLI H
lD PLI DATA l

BYTE 2, BYTE 3
I

I
I

I
I
I

~~----~--~---~~,----~--~--~--~I

START PLI l

lATCH BYTE 0, BYTE 1~

lATCH BYTE 2,3 ~ I
I

START SlCT l

--------------------------------~~

PLI SELECT FF l

600
Pli SELECT l

600
ZERO ENA l

HI BYTE TIME H
SEND lO BYTE l
SEND HI BYTE l
I
I

r-...:...I----.~--.:..---"""'r"'~....:.I---~-...;.I-""""'""

PLI DATA 7: 0 H

- - - - - - - - - - - - - - - - - - - - - - c : ( BYTE 0 X BYTE 1 X BYTE 2 X BYTE 3
I

lO BYTE ClK l

WRAP BYTE 0 - -.........1 WRAP BYTE 2 ----1.,..-11
I

HI BYTE ClK l

I
I

I
I
I
I
WRAP BYTE 1 ---I"~I WRAP BYTE 3 ---I"~I

CX-1240A

7-31

PORT PROCESSOR MODULE

Figure 7-17

PLI Interface Single Byte Write Timing Diagram

PLI ClK H

f50l

100

I50l

100

. . I1
. .....__-,n,,--_
. . .n -----'I
I

n~_

ClK PLI CNTl H

1....

lOAD CONTROL REGISTER -----~
D OUT 15:00 H

BYTE 0,1

SEND TO PLI H
lD PLI DATA l

l2£J I
I

lATCH BYTE 0, BYTE 1 ~ I
START PLI l
I

140

START SlCT l
i

PLI SELECT FF l

III~-----I--I------~I
300
,---

PLI SE lECT l

160
ZERO ENA l

HI BYTE TIME H

150
I

SEND lO BYTE l

I
150

SEND HI BYTE l

PLI DATA 7:0 H

lO BYTE ClK l

I
150

X BYTE 1 >-

BYTE 0
I

I
WRAP BYTE 0

HI BYTE ClK l

.. I
I

I~
I

WRAP BYTE 1

"'1
CX-1241A

7-32

PORT PROCESSOR MODULE

Figure 7-·18

PLI Portion of the Test Select Multiplexer
PI LA STATUS SE LECT 0
ENABLE ARB H
PLI RECEIVE STATUS 1 H
FIRST BUFFER H
BUFFER A BUS H
XMTR BUSY H
ACK H
OEST BUSY H
ARBITRATE H
SENO TO PLI H
PLI SEL 1 H
PLI SEL 0 H

00
10

20
30

40
50
60

70
4
2

SEL

GRO

RCVR A EN H
RCVR B EN H
CRC ERROR H
BUFFER B BUS I:l
XMIT ABORT H
COA H
COB H
XBUF PE H

SENO TO PLI H
PLI SE.L 1 H
PLI SEL 0 H

4
2
1

PI LA STATUS SE LECT 1

GRO

20
30

40
50
60

SEL

PLI RCVR BUFFER A FULL H
PLI RCVR BUFFER B FULL H
PLI XMTR ATTENTION H

P3
CX-1065A

7-33

PORT PROCESSOR MODULE

7.18.3
PLI Interface Control
The PLI Interface is controlled by seven signals that are outputs from various blocks shown in Figure 7-2.
These seven signals:
•

Determine what is gated onto the PLI Data Bus
•

Data to or from a PILA buffer

•

Status from the LINK or PILA

•

Commands to the LINK or PILA

•

Determine the direction of transfer on the PLI Data Bus

•

Determine the correct time to clock the PLI Data Bus into the receivers

•

Initialize the LINK and PI LA

Table 7-8 describes the seven signals that control the PLI Interface.

Table 7-8

PLI Interface Control Signals

Signal

Description

PLI LINK CONTROL <3:0>

These four signals control the LINK and PILA, including their activity on the PLI Interface. They are continuously driven but are
acted upon only when PLI SELECT is asserted. Refer to Chapters 5
and 6 to learn how the modules use these four signals. These signals are shown on the block diagram (Figure 7-2) as an output of
the Control Register.

SEND TO PLI

This signal determines the direction of data transfers on the PLI
Data Bus. It also determines whether the PLI Receive Status or
PLI Transmit Status lines are selected for microcode testing. This
signal is shown on the block diagram as an output of the Control
Register.

PLI SELECT

This signal is asserted for each data byte transferred. It is negated
if the K.pli is in diagnostic mode. The signal is not directly controlled by microcode. It is asserted as part of the one- or two-byte
sequence following a LD PLI DATA or RD PLI DATA. Except for
INITIALIZE, the LINK and PI LA will respond to the PLI Interface
signals only when PLI SELECT is asserted.

PLI INITIALIZE

This signal forces the initialization of the LINK and PILA. It clears
the error indicators, buffer status, interface status, and disables the
receivers. This signal is asserted following a clear from the P.ioc
or a clear from the Data or Control Sequencer. PLI INITIALIZE is
shown in the upper-left corner of the block diagram (Figure 7-2)
as an output from the Reset Control Logic.

7-34

PORT PROCESSOR MODULE

7.19 CONTROL REGISTER
The Control Register contains:
•

PLI Interface Control

•

P joc Reset

•

Control Store Parity Test Logic

•

Data Parity Test Logic

The Control Register is located in the lower right of Figure 7-2. Each control bit is described in Table 7-9.

Table 7 -~)

Control Register Bit Definition

Bit

Definition

PLI LINK CONTROL <3:0>

These four bits control the LINK and PILA, including their activity
on the PLI Interface. These four lines are continuously driven but are
acted upon only when PLI SELECT is asserted. Refer to Chapters 5
and 6 to learn how the modules use these four signals.

SEND TO PLI

This bit determines the direction of data transfers on the PLI Data
Bus. It also determines whether the PLI Receive Status or PLI Transmit Status lines are selected for microcode testing.

PLI SEL 011

These two bits, with SEND TO PLI, select two of the sixteen PLI
Status lines to pla.ce on the PI LA Status Select 0, 1 lines for selection
by the Test Select multiplexer logic.

DIAG MODE

This bit, when set, negates the PLI SELECT line (Table 7-8). It also
permits writing of bits < 15:08> of this register. This bit must be set
in order to write bits < 15:08> successfully. When cleared, this bit
forcibly clears bits < 15:08>. Diagnostic mode is not to be confused
with the maintenance or diagnostic modes of the LINK or PILA, nor
with software or microcode diagnostic modes. Setting this bit affects
internal K.pli hardware only.

INSTR PAR TEST

This bit, when set, inverts the sensing of the Control Store parity
bit, thus forcing instruction parity errors.

LO PAR TEST

This bit, when set, inverts the sensing of the low byte data parity
test logic.

HI PAR TEST

This bit, when set, inverts the sensing of the high byte data parity
test logic.

INSTR STOP

This bit, when set, stops all clocks in the K. plio

HOST ClLR

These two bits, if both are set, forcibly clear the P.ioc.

7-35

PORT PROCESSOR MODULE

7.20 DATA PARITY GENERATION AND CHECK LOGIC
The Data Parity Generation and Check Logic generates and checks parity for the two bytes on D OUT
and the two bytes on D IN. The logic generates La PARITY OUT and HI PARITY OUT that go along
with the D OUT signals. The PAR ERROR is generated when either D IN byte fails parity. This logic is
located in the right center of Figure 7-2.
7.21 INSTRUCTION PARITY CHECKER
The Instruction Parity Checker checks for odd parity over the 48 bits of the instruction from the Control
Store. This parity bit is gated to the Test Select multiplexer. The odd parity bit for the 48 bits of the
instruction word is bit 12. The Instruction Parity Checker is located at the top of the Control Store in
Figure 7-2.
If a parity error is detected in the Control Store and the K.pli is in diagnostic mode, execution of that

instruction is inhibited, and the sequencer active at that time is forced to a recovery routine. This trap
forces the Program Address Register to 77768 for the Control Sequencer or 77778 for the Data Sequencer
(the last two words of the Control Store), where branches to the appropriate service routine are located.
Asserting the vector address is accomplished by PAR ERR INH inhibiting the output of the sequencer
to the Program Address Register (Figure 7-19). This gates all ones into the Program Address Register
inputs. However, if the parity error was from the Control Sequencer, SEQ ADR 00 is forced low by
CNTL PROC and PAR ERR INH. This scheme gives us the two parity error trap vectors.
If a Control Store parity error is detected when K. pli is in normal mode, the internal clock will be

stopped, resulting in a complete halt of all K.pli operations. Recovery will occur only when the pjoc
initializes the module.
7.22 DESTINATION DECODER
The Destination Decoder (DEST DECODER) decodes bits < 27:25> from Control Store to write registers
(for example, LD RAM DATA) or start timing (for example, SET CREQ). Signals ENA DATA and ENA
CNTL control which destination decoder is selected. The Dest Decoder is located on the output of the
Control Store in Figure 7-2.
7.23 IOC LATCHES
Each microcode instruction can set, or clear, one of the lac Latches. These latches may not be set or
cleared if the literal field, to the ALU, is being used. Modification of these latches is specified if lac
ENABLE is set. Table 7-10 describes each bit in the lac Latches.

Table 7-10

IOC Latch Bit Description

Bit

Definition

COMMON lac 7/6

These two bits are set or cleared by either sequencer. These bits are two of
the inputs to the Test Select multiplexers of the two sequencers. They are used
as microcode control and status flags or for communication between the two
sequencers.

ONE BYTE

This bit is set or cleared by either sequencer. When set, a write or read of the
PLI Data Register resulf.s in a single byte transfer on the PLI Data Bus. When
this bit is clear, a write or read of the PLI Data Register results in a two byte
transfer across the PLI Data bus.

7-36

PORT PROCESSOR MODULE

Table 7-10 (Cant.)

IOC Latch Bit Description

Bit

Definition

EN STATUS

This bit is set or cleared by the Control Sequencer only It determines which
of the two registers is written to by the Control Sequencer when BUS DEST
decodes a seven. If this bit is clear, the Status Bus Register is written. If it
is set, the Scratchpad Address register will be written. ()peration of the Data
Sequencer is not affected by this bit.

ROLL

This bit is set or cleared by the Control Sequencer on] y. When clear, both
sequencers operate normally. When set, the Data Sequencer is prevented from
executing all ALU, 110, and branch operations. The Control Sequencer forces
the Data Sequencer to fetch and check all instructions of the 4 Kword Control
Store for proper parity.

LTS GRN

This bit is set or cleared by the Control Sequencer only. This bit controls the
two LEOs. When set, the green LED is on and the red LED is off. When this
bit is clear, the red LED is on and the green LED is off.

CNTL PROC FLAG

This bit is set or cleared by the Control Sequencer only, and it is inverted
and used as an input to the Data Test Select multiplexel. This bit is used for
microcode communication from the Control Sequencer to the Data Sequencer.

RD MODE

This bit is set or cleared by the Data Sequencer only. It controls the drivers of
the K.pli Data Bus Data Transceivers. If set, this bit pennits the gating of the
drivers onto the Data Bus during any bus cycle. If clear, it prevents the gating
of the drivers onto the Data Bus.

PLI RVRS

This bit is set or cleared by the Data Sequencer only. [t controls the count
direction of the Data Bus Address Counter and the odd! even byte sequence
on the PLI Data Bus. When this bit is clear, the Data Bus Address Counter will
increment, and the PLI Interface logic will transfer the low byte first. When it
is set, the counter will decrement, and the PLI interface logic will transfer the
high byte first.

DATA PROC FLAG

This bit is set or cleared by the Data Sequencer only, and it is an input to the
Control Test Select multiplexer. This bit is used for microcode comnlunication
from the Data Sequencer to the Control Sequencer.

7.24 SOURCE DECODER
The Source Decoder decodes bits < 19:18> from Control Store to read from the different registers. Each
sequencer has its own set of decoders (ENA CNTL or ENA DATA). The Source Decoder is located on
the output of the Control Store in Figure 7-2.
7.25 MICROINSTRUCTION DETAILED DESCRIPTION
This section describes the organization and purposes of the fields within the microinstruction word. The
microinstruction word is 48 bits wide. The microinstruction word is divided into SIxteen fields, each of
which controls different portions of the K.pli hardware. Figure 7-20 shows the fields and their positions
within the microinstruction word. The following sections describe each of these fidds.

7-37

o
::u
~

Figure 7-19

::u

Generation of Parity Error Vectors

(')

(J)

::u

CNTL PROC H

PAR ERR INH L
CTL
SEQUENCER

+5V +5V +5V +5V

)

2911

OUTPUTS

DO
01
02
03

---<l ZERO

PAR ERR INH L
DEADBAND L

=D-c

2
1

2911

I
I

- PADR 02

R3 I"- PADR 03

L _!:':J

OUTPUTS

L __ .!~

LD PADR REG L
CNTL PROC H

R1 f-- PADR 01

I
I

DATA
SEQUENCER

I
I

OF 0
1F 0
2F .....
3F 0 - -

RO I"- PADR 00

.....
OUT EN
....

\~.

YO
Y1
Y2
Y3

PROGRAM
ADDRESS
REGISTER

YO
Y1
Y2
Y3

~
~

ZERO

-"" OUT EN

"'"

L_ - -!~

CX-l057A

PORT PROCESSOR MODULE

Figure 7-20

Microinstruction Word Description

Ie I

47 46

41 40

44 43

IABI + I
38 37 36 35

IOC
TEST

28 27

RA/BS

LITERAL

25 24 23

20 19

BRANCH ADDRESS (BA)

15 14 13

00
CX-1224A

7.25.1
C Field
The C field is the carry into the ALU for the current microinstruction. It steers the literal to the high
byte for AF fields 3 through 7.
AD Field
7.25.2
The AD field, ALU destination, determines the routing of the ALU output data internal to the 290l.
Table 7-11 describes the decoding of the three bits in the AD field.

7-39

PORT PROCESSOR MODULE

Table 7-11

Decoding of Bits in the AD Field

Decode

Description

ALU to Q Register

No destination (sets conditions only)

ALU to RB, output RA (RB if AS equals 5 or 7)

ALU to RB

ALU/2 to RB, Q/2 to Q (right shift)

ALU/2 to RB (right shift)

ALU *2 to RB, Q*2 to Q (left shift)

ALU *2 to RB (left shift)

7.25.3
AF Field
The AF field, ALU function, determines the operation to be performed by the ALU. Table 7-12 describes
the decoding of the three bits in the AF field. The Rand S are the inputs to the ALU (Figure 7-4).

Table 7-12

Decoding of Bits in the AF Field

Decode

Mnemonic

ALU Function

ADD

R plus S

SUBR

S minus R

SUBS

R minus S

R OR S

AND

RAND S

NOTRS

(NOT R) AND S

XOR

R XOR S

XNOR

REX-NOR S

7.25.4
AS Field
The AS field, ALU source, selects two of the five possible sources for the ALU. Table 7-13 shows the
combination of the three bits in the AS field. The R, S, A, 0, B, 0, and Q are the inputs and outputs of
the ALU Data Source Selector in the ALU (Figure 7-4).

7-40

PORT PROCESSOR MODULE

Table 7-13

Decoding of Bits in the AS Field

Decode

NOTE:
A and B are the contents of the internal registers selected by fields RA and RB, respectively
D is the data input to the ALU from outside the 2901

Q is the contents of the internal Q Register

o is all zeros for that input.
AB Field
7.25.5
The AB field, ALU to BUS, determines if the D OUT lines will be driven by the 2901 ALU or if the D
IN contents will be transferred to the D OUT lines, bypassing the ALU. It also enables or disables the
BS field decoders. Table 7-14 describes the decoding of the bit in the AB Field.

Table 7-14

Decode of the Bit in the AB Field

Decode

Description

D IN Bus source to D OUT

ALU to D OUT

7.25.6
+ Field
The + field, EXEC IF COND TRUE, is one bit long. This bit is combined with the following signals to
generate INHIBIT EXEC (inhibit execute).
•

TST COND TR (test condition true)

•

COND EXC (conditional execute) ($ field)

7-41

PORT PROCESSOR MODULE

INHIBIT EXEC prevents:
•

Any ALU operation of each instruction for which it is active

•

The IOC Latches from being enabled

•

The destination decoders from being enabled

Table 7-15 describes the decoding of the bit in the + field along with EXEC IF COND TRUE and TST
COND TR to generate INHIBIT EXEC.

Table 7-15

Decode of the Bit in the + Field

COND
EXC

EXEC IF
COND TRUE

TST COND
TR

INHIBIT
EXEC

Condition

Execute all operations

Stop ALU, IOC, destination operations

Execute all operations

X means the state of the signal does not matter

7.25.7
RB Field
The RB field, B Port Register, selects one of the sixteen internal 2901 registers to be read and/or written
by the 2901 ALU. If a value of 58 or 78 is in the the AS field, the A Port Register field (RA field) is forced
to the same value as the RB field.
7.25.8
TEST Field
The TEST field, TEST CONDITION < 03:00 >, selects one of sixteen signals for the conditional operations of the sequencers. The hardware includes two separate selectors, one for each of the two
sequencers. Table 7-16 shows the test conditions for the four bits of the TEST field.

7-42

PORT PROCESSOR MODULE

Table 7-16

Decode of the Bits in the TEST Field

Decode

Control Sequencer

Data Sequencer

1 (True) always

Last Control Sequencer
ALU result = 0

Last Data Sequencer
ALU result = 0

Last Control Sequencer
ALU carry out

Last Last Data Sequencer
ALU carry out

Last Control Sequencer
ALU MSB

Last Last Data Sequencer
ALU MSB

Last Control Sequencer

Last Last Data Sequencer

o OUT LSB

Data Sequencer flag

Control Sequencer flag, inverted

Common Sequencer Flag 6

Common Sequencer Flag 7

Control Bus Error *

Data Bus Error *

Not Used

PLI Test 0 **

PLI Test 1 **

Rcvr Buffer A Full

Rcvr Buffer B Full

Xmtr Attention

Control Bus Request Active

Data Bus Request Active

* Inclusive OR summation. Refer to Sections 7.17 and 7.16.
** Refer to Section 7.18.2.

7.25.9
BD Field
The BD field, bus destination, selects the register that will be written with the data that has been placed
on the 0 OUT lines. Table 7-17 shows the decode of the three bits.

7-43

PORT PROCESSOR MODULE

Table 7-17

Decode of the Bits in the BD Field

Decode

Control Sequencer

Data Sequencer

Nap

Control Bus Data Xcvrs

Data Bus Data Xcvrs

Control Bus Address Xcvrs

Data Bus Address Xcvrs and Counter

Scratch pad Data

Scratchpad Data

PLI Bus Register

Program Address Register

Control Register

lac 3 SET; Scratch pad Adrs

Scratch pad Adrs

lac 3 CLR; Status Bus Register

Scratchpad Adrs

7.25.10
@ Field
The @ field, lac ENABLE, permits the IOC field to modify the lac Latches when set. This bit is not
set when using the LITERAL field.
The lac field has dual functions: it can be gated to the lac Latches when the @ field is set or the
field can be the literal input to the ALU.
7.25.11
IOC Field
The lac field, input/output control, if enabled by lac ENABLE(@), modifies the IOC Latches. Bits
< 22:20 > select the desired latch, and bit 23 sets or clears that latch. Table 7-18 describes the decoding
of the bits in the lac field.

Table 7-18

Decode of the Bits in the IOC field

Decode

Control Sequencer

Data Sequencer·

CNTL PROC FLAG

DATA PROC FLAG

LTS GRN

PLI RVRS

ROLL

Not Used

EN STATUS

RD MODE

Not Used

ONE BYTE

COMMON lac 6

COMMON lac 7

7-44

PORT PROCESSOR MODULE

7.25.12
RU\ Field
The RA field, A Port Register, selects one of the sixteen internal 2901 registers to be operated on by the
A,LU. The RA field is a shared field and is only enabled if the AS field does not equal 5 or 7 and bit AB
does not specify the LITERAL field.
7.25.13
BS Field
The BS field, bus source, selects one of the eight K.pli registers which are external to the ALU. The
contents of the selected register are enabled onto the D IN lines, routed through the input multiplexer,
and presented to the D inputs of the 2901 ALU. Table 7-19 describes the decoding of the bits in the BS
field.
The BS field is a shared field and is only enabled if the AS field does not equal 5 or 7 and bit AB does
not specify the LITERAL field.

Table 7-19

Decode of the Bits in the BS field

Decode

Control Sequencer

Data Sequencer

NOP

Control Bus Data Xcvrs

Data Bus Data Xcvrs

Control Bus Address Xcvrs

Data Bus Address Xcvrs

Scratchpad Data

Scratch pad Data

PLI Bus Register

Control Bus Errors

Data Bus Errors

Not Used

7.25.14
S Field
The S field, test sense, is XORed with the output of the Control and Data Test Select multiplexer to
generate TST COND TR (test condition true). TST COND TR is then combined with branch address
equal to 77778 and JUMP CNTL 1 to determine whether the sequencer will output the Program Counter,
the Stack, or the Branch Address. Table 7-20 describes what operation is perforined in the sequencer
depending on the selected test condition and the TST COND TR signal.

7-45

PORT PROCESSOR MODULE

Table 7-20

Decode of the Selected Test Condition and TST COND TR

Select Test
Condition

TEST FOR
TRUE

TST COND
TR

Operation

Branch, Call, or Return

Increment Program Counter

Branch, Call, or Return

7.25.15
$ Field
The $ field, conditional execute, enables all instructions when clear. When set, this bit enables the
conditional execution of the IOC, bus destination, and ALU instructions. Refer to Section 7.25.6 for a
description of how this bit and TST COND TR and EXEC IF COND TRUE work together.
7.25.16
K Field
The K field, jump control, is logically combined with TST COND TR and BR ADR < 11:00 > equal to
all ones (77778) to control the next operation of the 2911 Sequencers. (Refer to Section 7.25.14.) This
combination controls the operation of the internal stack, and it determines whether the sequencer will
output the:
•

Program Counter

•

Stack contents

•

Branch address field

Table 7-21 describes the decode of the input signals for the sequencer operation.

Table 7-21

Decode of Input Signals for Sequencer Operation

Branch Address

JUMP
CNT 1

TST COND
TR

STACK

Operation

***

HOLD

Increment

***

HOLD

Increment

77778

HOLD

Increment

77778

HOLD

Increment

***

HOLD

Branch

***

PUSH

Call

77778

HOLD

Branch

77778

POP

STK

Return

* * * can be anything except 77778

7-46

PORT PROCESSOR MODULE

7.25.17
P Field
The P field, instruction parity, is the single parity bit for the 48-bit microinstruction word. This bit is
calculated odd parity for the other 47 bits. If the number of 1 bits in the other 47 bits is even, then this
bit is a I, making the 48-bit microinstruction word odd parity. If the number of I bits in the other 47
bits is odd, then this bit is a 0 making the 48-bit microinstruction word odd parity
BA Field
7.25.18
The BA field, branch address, provides the instnlction address for conditiOI1ilI and unconditional
branches and subroutine calls. Also, during the execution of certain instruction~;, this field provides
supplemental data and control information. Refer to Section 7.25.19.
Destination and Branch Field Combinations
7.25.19
The BA field is not always a branch address. This field is also used for data and control for certain
instructions. When the BD field equals two, these lines are used as data and control lines. These BA
and BD field combinations are described in the following two sections.
7.25.19.1
Writing Control Bus Address Transceivers
Writing the Control Bus Address Transceivers is done with D OUT and the BR ADR lines. Bus lines D
OUT < 15:00> are latched and then gated onto CADR lines < 16:01 >, respectively, during the Control
Memory Cycle. BR ADR 11 is latched and gated onto CADR 00 (LSB). BR ADR < 10:08> are latched
and gated onto CCYCLE < 0:2 >, respectively. BR ADR 07 is latched. It then determines, during the
Control Memory Cycle, whether the K.pli Control Bus Data Transceivers will be gated onto the CDATA
lines. In order to write the register, the BD field lllUSt equal two and the Control Sequencer must be
active.
Table 7-22 shows what Control Memory Cycles are generated from BR ADR < 1007>.

Table 7-22

Control Memory Cycles Initiated from Decode of the BA Field

Control Memory Cycle

Initiate Control Memory Read Cycle

Initiate Control Memory Write Cycle

Initiate Interrupt Cycle

Initiate Lock Cycle

Initiate NMA Cycle

7.25.19.2
Writing Data Bus Address Transceivers and Counter
When the microcode writes the Data Bus Address, part of the address is written ftom the D OUT lines,
and branch address bits BR ADR < 10:09> are logically ANDed, latched, and then used to drive DNMA
during the Data Bus Cycle (Figure 7-12).
Table 7-23 shows the decoding of BR ADR < 10:09 > to generate DNMA.

7-47

PORT PROCESSOR MODULE

Table 7-23

Decoding of BR ADR < 10:09 > to Generate DNMA

BR ADR 10

BR ADR 09

DNMA

o
o

7.26 HARDWARE DETECTED ERRORS
Table 7-24 describes the K.pli hardware detected errors.

Table 7-24

Hardware Detected Errors

Error

Description

Control Bus Error

This error is generated when an illegal cycle code is specified
during a Control Bus Cycle. This error is part of the CNTL ERR
SUM test condition and is cleared by a P.ioc dear command or
a Control Sequencer clear.

Control Bus Parity Error

This error is generated when a value from Control Memory
is received with bad parity (sensed when read from the data
transceivers). This error is part of the CNTL ERR SUM test condition and is cleared by a P .ioc clear command or a Control Sequencer clear.

Control Bus NXM

This error is generated when a Control Bus Cycle did not assert
CACK. This error is part of the CNTL ERR SUM test condition,
and is cleared by a P .ioc clear command or a Control Sequencer
clear.

Instruction Parity Error

This error is generated when a parity error is detected during an
instruction fetch. This error is meaningful only when the Data
Sequencer has been put into roll mode. This error is part of the
CNTL ERR SUM test condition and is cleared by a P.ioc clear
command or a Control Sequencer clear.

Scratchpad Parity Error

This error is generated when a parity error is detected during a
read from Scratchpad. This error is part of the CNTL ERR SUM
and DATA ERR SUM test conditions and is cleared by a P.ioc
clear command or a Control Sequencer clear.

PLI Parity Error

This error is generated when one or more bytes read from the
PLI Data Bus is received with bad parity. This error is part of the
DATA ERR SUM test condition and is cleared by a P.ioc clear
command or a Data Sequencer clear.

7-48

PORT PROCESSOR MODULE

Table 7-24 (Cont.)

Hardware Detected Errors

Error

Description

Data Bus Overrun

This error is generated when a Data Bus Cycle is initiated before
completion of the preceding cycle. This error is part of the DATA
ERR SUM test condition and is cleared by a P joe clear command
or a Data Sequencer clear.

Data Bus Parity Error

This error is generated when one or more words with bad parity
are read from Data Memory. This error is part of the D AT A ERR
SUM test condition and is cleared by a P joe clear command or
a Data Sequencer clear.

Data Memory NXM

This error is generated when a Data Bus Cycle does not assert
DACK. This error is part of the DATA ERR SUM test condition
and is cleared by a P joe clear command or a Data Sequencer
clear.

LINK Errors

The K.pli detects two errors generated in the LINK. Abort Transmission and Transmit Buffer Parity errors assert XMTR ATTENTION. The Control Sequencer tests XMTR ATTENTION at the
Control Test Select multiplexer. The Control Sequencer must
then issue a read transmitter status command to the LINK and
check the bits of the returned status to see what caused XMTR
ATTENTION.

7-49

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

CHAPTER 8
HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

8.1 INTRODUCTION
The HSC50 Input/Output Control Processor Module (F-11 P.ioc) is an extended hex module which
contains:
•

Four LEDs for status indications

•

An F-11 processor and memory management

•

Timing and interrupt logic for the F-11

•

An interface to Program Memory

•

A bootstrap PROM

•

110 page windows into Control Memory

•

Control, timing, and arbitration for the HSC50 Data Bus and Control Bus

•

Interface for two TU58 cassette drives

•

Pio Control and Status Register

•

An interface to the HSC50 Operator Control Panel (Switch/Display Regiskr)

•

K Init and Status Registers

•

Error Address Register

•

Serial Number Register

•

Control Memory and Data Memory interfaces

8.2 LED INDICATORS
The P.ioc contains four LED indicators: one red, one green, and two yellow (Figure 8-1). These are
described in the following sections.

8-1

HSCS'O INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 8-1

P joe LEOs

6)>-VELLOW

STATE

RUN

RED

GREEN

STATUS

eX-1066A

8-2

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

8.2.1
P.ioc Diagnostic OK LEOs
The red and green LEOs are used to indicate whether the P .ioc successfully completed all of its initialization diagnostics. The module powers up with the red LED on and the green LED off. Upon successful
completion of the power up diagnostics, the red LED is turned off and the green LED is turned on.
These LEOs are controlled by a bit in the Switch/Display Register. (Refer to Section 8.13.)
8.2.2
RUN LED
The RUN LED, a yellow LED adjacent to the red Diagnostic OK LED, blinks once for each PDP-II
instruction fetch cycle. This is analogous to the RUN light on standard LSI-II processor systems. When
the F-II is running, this LED is illuminated at about half-brilliance (compared to the other LEOs on the
module).
8.2.3
State LED
The yellow State LED is controlled by bit < 03 > of the Pio Control and Status Register (PIOCSR) and is
connected in parallel with the State indicator on the Operator Control Panel.
8.3 HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE BLOCK DIAGRAM
Figure 8-2 is a block diagram of the P.ioc showing the principal hardware elements and data paths. Each
of these elements will be described in the following sections.
8.4 F-11 BLOCK
The F-II Block contains the F-II processor and associated logic. The F-II block is located on the
upper-left side of Figure 8-2. The F-II is implemented using three chips. Two MOS/LSI chips, data
and control, implement the basic processor (Figure 8-3). The third chip, the memory management unit
(MMU), provides a PDP-11134 software-compatible memory management scheme .

8-3

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 8-2

HSCSO Input/Output Control Processor Module Block Diagram

CLK
TIMING
CLK CTL

2,3

INTERRUPT
LOGIC

F-11

XCVRS
DAL

BDAL

3,16

LOAD STROBES

;t
y-

ADDRESS
DECODE

READ STROBES (

BUS
DRIVERS

Vt
N

OUT BUS

I
BOOTSTRAP
PROM

TU58
INTERFACES

12,13

SERIAL
NUMBER
REGISTER
11,13

--~

CONSOLE
TERMINAL
INTERFACE

ERROR
ADDRESS
REGISTERS

SWITCH
DISPLAY
REGISTER

IN BUS

TU58 -1

CONSOLE
TERMINAL

TU 58-2

OPERATOR
CONTROL
PANEL

CX-l067A
Sheet 1 of 2

(Continued on next page)

8-4

. HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 8-2 (Cont.)

HSC50 Input/Output Control Processor Module Block Diagram

DREO
PROGRAM
MEMORY
BUS

DATA BUS
ARBITRATOR
AND TIMING

DNMA

I )GRANT

!)TIMING

BUS
DRIVERS

OUT BUS

[:ATA BUS
I,HERFACE
8,!l

PIO
CONTROL!
STATUS
REGISTER

K INIT
AND
STATUS
REGISTER

CONTROL
MEMORY
WINDOWS

CONTROL
BUS
INTERFACE

CONTROL BUS

6,7

IN BUS

~STATUS ~

. ~----___
--

CLEARS
CREO

NOTE:
NUMBERS IN LOWER LEFT HAND
CORNER OF BOXES REFER TO
PAGE NUMBERS IN THE MODULE
SCHEMATIC.

CGRANT
CONTROL BUS 1 - - - - - - - - .
ARBITRATOR
~----- ~ CTIMING
AND TIMING

CCYCLE

~--- .....

CACK

~----- . .

CERR

.17
CX-l067A

Sheet 2 of 2

8-5

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 8-3

F-11 Processor Functional Block Diagram

MIB BUS

< 15:00 >

MEMORY
MANAGEMENT
CHIP

OAL BUS

BUS
CONTROL
LOGIC

21 :00 >

BOAL CONTROL

o
A
L

CX-l068A

The data chip (DC302) performs the following functions:
•

Performs all arithmetic and logical functions

•

Handles data and address transfers with the external world

•

Coordinates most interchip communication

The control chip (DC303) does microprogram sequencing for PDP-1I instruction decoding and contains
the control store ROM. The data and control chips are both contained in one 40-pin package. The MMU
chip (DC304) contains the registers for 22-bit memory addressing.
8.4.1
Memory Management Unit Chip
The Memory Management Unit (MMU) chip provides the memory management function. This chip
provides dual mode (user and Kernel) address relocation of 22 bits. Sixteen-bit virtual addresses are
received from the data chip via the Data Address Lines (DAL), relocated to the appropriate 22-bit
physical address and then sent on the DAL to replace the original virtual address for transmission to the
Program Memory Bus. The MMU chip contains the status registers and active page registers (P AR/PDR
register pairs), as well as access protection and error detection capability.
The MMU chip is controlled by information received on the Microinstruction Bus (MIB) from both the
data chip and the control chip, and by several discrete control inputs.

8-6

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Aborts generated by protection hardware are vectored through kernel address 250R• The software uses
status regi.sters to determine why the abort occurred. Note that an abort to a location which is itself
an invalid address will cause another abort. Thus, the kernel program must ensure the kernel virtual
address 2508 is mapped into a valid physical address. Otherwise, an infinite loop- occurs.
The Memory Management chip contains four status registers:
•

Memory Management Register 0

•

Memory Management Register 1

•

Memory Management Register 2

•

Memory Management Register 3

The following sections describe these four memory management registers.
8.4.1.1
Memory Management Status Register 0
Memory Management Status Register 0 (SRO) contains abort error flags, memory Inanagement enable,
and other essential information required to recover from an abort. The register is located at 177775728 ,
The format of SRO is shown in Figure 8-4. Table 8-1 describes the bits in the SRG.

Figure 8-4

Memory Management Status Register 0

ABT ABTIABTI o-r;r~ PRoe

~~~ MODE.

EN~

I 0 I. NUMBER
PAGE

NRS PLE ROE

MA~

CXO-1129A

Table 8-1

Memory Management Status Register 0 Bit Description

Bits

Description

ABORT NON-RESIDENT - This bit is set by attempting to access a page with an Access
Control Field key equal to 0 or 4.

ABORT PAGE LENGTH ERROR - This bit is set by attempting to access a location in a
page with a block number (virtual address bits < 12:06» outside the area authorized by
the Page Length Field of the Page Descriptor Register for that page.

ABORT READ-ONLY ERROR - This bit is set by attempting to write in a read-only page.
Read-only pages have access keys of 2.

12:07,04

These bits are read-only and are always O.

06:05

PROCESSOR MODE - These bits indicate the processor mode (kernel =00, user = 11)
associated with the page causing the abort.

8-7

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Table 8-1 (Cont.)

Memory Management Status Register 0 Bit Description

Bits

Description

03:01

PAGE NUMBER - These bits indicate the virtual page number referenced. Pages, like
blocks, are numbered from 0 upwards. The page number field is used by the error
recovery routine to identify the page being accessed if an abort occurs.

ENABLE MANAGEMENT - When set, all addresses are relocated and protected by the
Memory Management Unit. When reset, the Memory Management Unit is disabled and
addresses are not relocated or protected.

8.4.1.2
Memory Management Status Register 1
The Memory Management Status Register 1 (SRI) is implemented on some PDP-II computers to provide
additional capability. The HSC50 does not implement this register but does respond to its bus address,
177775748 , and reads it as all Os. This information is provided for clarity only.
Memory Management Status Register 2
8.4.1.3
Memory Management Status Register 2 (SR2) is loaded with the 16-bit virtual address (VA) at the beginning of instruction fetch, but is not updated if the instruction fails. SR2 is the virtual address program
counter. Upon abort, the result of SRO bits 15, 14, or 13 being set freezes SR2 until the SRO abort flags
are cleared. The SR2 register is located at 177775768 and is a read-only register.
Memory Management Register 3
8.4.1.4
Memory Management Register 3 (MMR3) enables or disables 22-bit mapping. MMR3 is located at
177725168 and is cleared at power up, by a console start, and by a RESET instruction. Figure 8-5 shows
the format of the MMR3. Table 8-2 describes the bits in this register.

Figure 8-5

Memory Management Register 3

CX03-1130A

8-8

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Table 8-2

Memory Management Register 3 Bit Description

Bits

Description

15:06
04:00

These bits are read-only and are always O.

ENABLE 22-BIT MAPPING - When set, this bit selects 22-bit relocation when MMRO < 00 >
is set. When cleared, 18-bit relocation is selected when MMRO < 00 > is set.

8.4.2
Bus Control Logic
The Bus Control Logic generates the necessary clock, strobe, and enables for the DAL transceivers.
8.4.3
Data-Address Lines
The Data-Address Lines (DAL) Bus is routed between all the MOS chips and the Program Memory Bus
Transceivers. The 22-bit DAL Bus is time multiplexed. During clock-high time, the DAL bus transfers
data from the data chip to the other MOS chips or between the rest of the module and the MOS chips.
During clock-low time, the DAL Bus transfers service data (external and internal interrupt requests) from
the module to the control chip.
8.4.4
Microinstruction Bus
The 16-bit Microinstruction Bus (MIB) is common to all data and control chips. A subset of the MIB is
routed to the MMU because it does not need access to all MIB control signals.
The MIB is time-multiplexed and is used for different functions during clock high and low times. During
clock-high time, the MIB transfers control information from the data chip to all control chips, the MMU,
and the rest of the logic. During clock-low time, the MIB transfers microinstructions from the control
chip to the data chip.
NOTE
For more detail on the F-ll, refer to the Microcomputer Processor Handbook 1979-1980.
8.5 MICRO-ODT
Micro-ODT, as currently implemented in the F-l1 microcode, accepts either 16· or 18-bit addresses,
but not 22-bit addresses. Since the HSC50 utilizes the full 22-bit addressing capability of the MMU,
and since special hardware is required to implement 18-bit ,uODT addressing, the P joe only allows
16-bit addressing in ,uODT. This provides access to the first 28 Kwords of Program Memory and the I/O
page. However, since the 110 page is accessible, all available Control Memory is accessible using the
Control Memory Windows. Data Memory cannot be accessed using ,uODT. Note that even if the MMU
is enabled, the ,uODT microcode disables relocation.

8-9

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

8.6 INTERRUPT LOGIC
The Interrupt Logic generates the interrupt and vector address to the F-ll (shown on the left side of
Figure 8-2). Table 8-3 shows the interrupt and trap vectors that are assigned in the F-ll P.ioc. Notice
that the Control Bus can software interrupt on Level 7 through 4 (Section 8.16.4 and Chapter 3).

Table 8-3

Interrupt and Trap Vectors for F-l1 P.ioc

Trap
Vector
Address

Interrupt
Level

Function
(reserved)

000
004

Non-maskable

Bus error (non-existent memory)

010

None

Control error (non-existent F-ll Control Chip)

014

Non-maskable

BPT, breakpoint trap used for HSC OOT

020

Non-maskable

lOT, Input/Output Trap, used for HSC software inconsistency

024

Non-maskable

Power fail

030

Non-maskable

EMT, emulator trap, used for system service call

034

Non-maskable

TRAP instruction

060

4 (3)

Console terminal, keyboard

064

4 (4)

Console terminal, printer

100

6 [1]

Line clock

114

Non-maskable

Parity error on read-from-memory

120

4 (5)

Control Bus Interrupt, level 4

124

Control Bus Interrupt, level 5

130

Control Bus Interrupt, level 6

134

Control Bus Interrupt, level 7

250

Non-maskable

MMU abort

300

6 [2]

TU58 1, receiver

304

6 [3]

TU58 I, transmitter

310

4 (1)

TU58 2, receiver

314

4 (2)

TU58 2, transmitter

Note that the numbers in parentheses 0 indicate the order of priority of level 4 interrupts. The numbers
in brackets [] indicate the order of priority of level 6 interrupts.

8-10

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

8.7 ADDRESS DECODE
The Address Decode logic decodes addresses and provides the load strobes and read strobes for the
110 page registers located on the P.ioc module. The decode is shown on the left of Figure 8-2.
8.8 BOOTSTRAP PROM
The bootstrap PROM contains 1 Kwords starting at location 177730008 (shown on the left side of Figure 8-2). This code is executed after:

•

A power-up

•

A subsystem INIT (from either the host or the Operator Control Panel)

•

A software-initiated INIT

Two starting addresses are provided: the cold boot starts at 177730008 and the warm boot starts at
177730108 , A cold boot happens when the HSC powers up or when the INIT switch is pushed. A warm
boot happens when the system crashes or the set show utility requests that the HSC reboot. During a
warnl boot the software checks to see what caused the boot (for example, an NXM or parity error).
The F-11 is hard-wired for Power Up Mode 2. This mode causes automatic execution of the bootstrap
at address 177730008 whenever the F-11 is initialized.
8.9 TUS8 INTERFACE
The TU58 Interface logic provides a parallel interface to the P .ioc and a serial interface with the TU58.
8.9.1
Parallel P.ioc Interface
The P.ioc has two separate TU58 interfaces. However, the HSC50 is shipped with only one TU58
Controller and two drives. This section describes only one of the interfaces. The interface has the same
characteristics as a DL-11D. It contains the following four registers:
•

Receiver Status Register (RCSR) 1775208

•

Receiver Data Buffer Register (RBUF) 1775228

•

Transmitter Status Register (XCSR) 1775248

•

Transmitter Data Buffer Register (XBUF) 1775268

Figures 8-6, 8-7, 8-8, and 8-9 show the format of these four registers. Tables 8-4, 8-5, 8-6, and 8-7
describe the bits in the registers.

Figure 8-6

Receiver Status Register

CXO-1131A

8-11

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Table 8-4

Receiver Status Register Bit Description

~it

Description

DEVICE PRESENT - This read-only bit indicates a TU58 (or terminal) is plugged into this
interface. This line is RS232C/RS423 compatible.

RECEIVER READY - This read-only bit indicates that there is a character in RBUF to be read.

RECEIVER INTERRUPT ENABLE - This read/write bit, when set, causes an interrupt to be
generated on the assertion of RCV ROY. Note that setting this bit when ReV ROY is already
asserted will cause an interrupt.

Figure 8-7

Receiver Data Buffer Register

[Toll------------.-------

IERRIOVR
FRM ~o
ERR ERR
15

RECEIVED

DATA

CXO-1132A

Table 8-5

Read Data Buffer Register Bit Description

Bits

Description

ERROR - This read-only bit is the inclusive-OR of OVERRUN ERROR and FRAMING ERROR.

OVERRUN ERROR - This read-only bit indicates that the receiver attempted to set bit 07 in
RCSR when it was already set. In other words, a new character was received and the preceding
character had not yet been read.

FRAMING ERROR - This read-only bit indicates no stop bit was received .

07:00

RECEIVED DATA - These are the 8-bit characters just received. This byte is read-only.

Note that there is no parity error bit implemented in this register. Parity is not checked or generated on
any of the serial interfaces.

8-12

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 8-8 Transmitter Status Register

CX01133A

Table 8-6 Transmitter Status Register Bit Description
Bit

Description

TRANSMITTER READY character for transmission.

TRANSMITTER INTERRUPT ENABLE - This read/write bit, when set, causes an interrupt to
be generated on the assertion of XMT ROY. Note that setting this bit when XMT ROY is already
set will cause an interrupt to be generated.

MAINTENANCE - This read/write bit, when set, causes the serial output of the transmitter
section to be connected to the input of the receiver section. Thus, a charader loaded into XBUF
can then be read back in RBUF.

BREAK - This read/write bit, when set, causes the transmitter to send a continuous SPACE
which will be detected by the receiver as a framing error.

This read-only bit, when set, indicates that XBUF can accept a

Figure 8-9 Transmitter Data Buffer Register

---]
00

CXO-1134A

Table 8-7 Transmitter Data Buffer Register Bit Description
Bits

Description

07:00

TRANSMITTED DATA - These write-only bits are loaded with the character to be transmitted.

8-13

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Data format for all three serial interfaces is 8 data bits, no parity, and 1 stop bit.
The first TU58 interface occupies addresses 177775208 -177775268 and uses 3008 (Rcvr) and 3048 (Xmtr)
for its vectors. The second TU58 interface (not used) occupies addresses 177775308-177775368 and uses
3108 (Revr) and 3148 (Xmtr) for its vectors. The first TU58 interface interrupts at level 6 and the second
TU58 interface interrupts at level 4.
8.9.2
Serial Interface
The serial interface is an RS232C/RS423 compatible asynchronous full duplex serial line. Control commands are distinguished from binary data via the radial-serial bus protocol. Transmit and receive baud
rates are the same and are jumper-selectable for 38.4, 19.2, or 9.6 Kbaud. Table 8-8 shows the configuration for baud rate selection jumpers. The baud rate is jumper-selectable according to the following
table:

Table 8-8 TUS8 Serial Interface Baud Rate Selection
Jumper W4

Jumper WS

TUS8 Baud Rate

38.4K

OUT

9.6K

OUT

19.2K

OUT

38.4K

8.10 CONSOLE TERMINAL INTERFACE
The Console Terminal Interface is a EIA RS232C/RS423 serial interface. This interfa~e is connected to
the console terminal. The console terminal is the communications link between the processor and you.
The hardware interface for this terminal is also a DL-11D interface. The register set is the same as for
the TU58, above, and occupies the addresses 177775608-177775668 . Vectors for this interface are 608
(Rcvr) and 648 (Xmtr). It interrupts at level 4. Available baud rates are 300 and 9600 baud. The baud
rate is selected by Jumper W3: in for 9600 baud, out for 300 baud.
Reception of a break character (that is, detection of a framing error by the UART) on this interface will
assert the processor's HALT line, if the Secure/Enable switch is in the ENABLE position, causing the
F-11 to enter .uODT.
Note that the UART remembers a break character until a subsequent valid character is received. Therefore, if a break is received while the Secure/Enable switch is in the SECURE position, and no other
valid character is subsequently received, the break will be remembered and subsequently switching the
Secure/Enable switch to ENABLE will cause the F-ll to enter .uODT immediately. This may be caused
by powering the console terminal on or off while leaving the HSC50 powered on.
An additional maintenance feature is included in this interface. If the INIT pushbutton on the Operator
Control Panel is held depressed, any character received from the console keyboard is immediately
echoed back to the terminal, thus providing a simple test of the serial line driver and receiver while
bypassing the UART and associated hardware.
This terminal interface is also used to communicate with the F-ll .uODT.

8-14

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

8.11 SERIAL NUMBER REGISTER
The 16-bit Serial Number Register (shown just left of the middle in Figure 8-2) provides a unique
identifiable number for each P.ioc module. The serial number is encoded by adding or removing
jumpers on the module. The address of this register is 177700568 ,
8.12 ERROR ADDRESS REGISTER
The Error Address Register consists of two locations: Low Error Address and High Error Address (shown
in the middle of Figure 8-2). These two registers catch the full 22-bit physical address on the OUT BUS
at the time a NXM or a parity trap occurs. These registers are frozen by the occurrence of the error
and each, independent of the other, remains frozen until it is read. After being read, each register
will resume catching the corresponding portion of the address. Following are the addresses of the two
registers:
Low Error Register - 177700248
High Error Register - 177700268
Figures 8-·10 and 8-11 show the format of these two registers.

Figure 8-10

Low Error Address Register

C.__

P_h.YSiCal _Ad_d_r_e_S_S__
<_15_:_0_0_>. _ _ _

~
00

CXO-1135A

Figure 8-11

High Error Address Register

E_o,S ___L: <21:16~
15

08 07 06 05

00
CXO-1136A

8.13 SWITCH/DISPLAY REGISTER
The Switch/Display Register (shown in the lower middle of Figure 8-2) is the interface between the
software and the Operator Control Panel. This read/write register is located at 177700428 ,
Figure 8-12 shows the arrangement of the five switches and indicators on the Operator Control Panel.
Response to operation of these switches is handled entirely by software; no interrupts to the F-11 are
generated by changes in state of the switches (except, of course, for INIT).

8-15

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 8-12

Indicators and Switches on the Operator Control Panel

INIT SW
IND 4

~J
~

SW 3 TST
LAMP
IND 3

~J
~

~w 0

rNO 0 ]
CXO-1137A

The functions of the five panel switches and indicators are defined by software, except as follows:
•

INIT-a momentary push button which, when pushed and released, causes the F-11 to execute
its bootstrap routine.

•

SW 3-a momentary push button which, when pushed, provides a hardware lamp test.

In addition, there is a two-position rocker switch, SECURE/ENABLE. This switch provides three functions:
•

Whenever the switch is in the ENABLE position, a break received from the terminal causes the
F-11 to enter .uODT.

•

If the F-11 is in Kernel mode and HALT instruction is decoded, the state of this switch is
sampled. If the switch is in the ENABLE position, the F-11 enters .uODT. If the switch is in
the SECURE position, the F-11 executes a trap to location 108. If the F-11 is in user mode, a

HALT instruction causes a trap to location 1°8 ,
•

In addition, if this switch is in the SECURE position, the IN IT switch is disabled.

Figure 8-13 shows the format of the Switch/Display Register. Table 8-9 describes each bit of the register.
The software must poll this register to detect changes in the state of the switches.

Figure 8-13 Switch/Display Register

~ERVEO TwT~lsw
lOlA C/O INHILMPILMPILMPILMPILMP]
~~ 0
OK NXM PAR 4
3
2
1 0

~
15

CXO-1138A

8-16

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Table 8-9

Switch/Display Register Bit Description

Bits

Description

15:12

These bits are read-only and always zero.

11:08

SWITCHES < 3:0 > - These bits reflect the state of the corresponding switches on the Operator Control Panel. These bits are read-only. Note that no hardware debounce logic is
provided; debouncing is done by software.

DIAGNOSTIC OK - This bit lights the Diagnostic OK LEDs. A zero lights the red LED and a
one lights the green LED. This bit is zero on power up and is set to a one'upon completion of
the PROM bootstrap diagnostics. The intent of this bit is a simple visual GO/NO-GO indicator
for the P.ioc.

CONTROL/DATA NON-EXISTENT MEMORY - This bit, when set, forces a NXM trap on
any Control or Data Memory Bus access.

INHIBIT PARITY TRAP - This bit, when set, inhibits all parity traps, thus enabling examination of any memory location which has a hard parity error.

04:00

LAMPS < 4:0 > - These bits, when set, light the corresponding indicators on the Operator
Control Panel. These bits are read/write.

The last 8 writable bits are cleared by Host Clear, Bus Init, and 110 Clear.

8.14 PIO CONTROL AND STATUS REGISTER
The Pia Control and Status Register (PIOCSR) co~tains bits that control functions and provide status
information on the P joe.
Figure 8-14 shows the format of the PIOCSR. Table 8-10 describes each bit of the register. Except as
noted in Table 8-10, all bits are read/write and are cleared by either Bus Init or 10 Clear. This register
is located at 177700408 .
Figure 8-14 Pio Control and Status Register

I~~I
15

I ] I::I::I~E
13

~:~rCKl
08

CXQ-1139A

8-17

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Table 8-10

Pio Control and Status Register Bit Description

Bits

Description

TERMINAL ENABLE - This bit corresponds to the position of the Operator Control Panel
SECURE/ENABLE switch. A 1 indicates the ENABLE position of the switch (read-only).

This bit is always zero.

This spare read/write bit is not used.

Spare

SWAP BOARD - This bit, when set, causes the first two memory boards in the system to
swap the base address for the Program Memory on each board (not used).

SWAP BANK - This bit, when set, causes the first memory board in the system to swap
the addressing ranges between Program Memory banks on that board. These two bits are
provided to maximize the probability that working memory is available starting at address
000000 for interrupt vectors.

09:08

SELECT P < 1:0 > - These bits provide a code which identifies which Control Bus interrupt
field this P will respond to. These two bits are always zero in the HSC50.

ENABLE CONTROL BUS ARBITRATOR - This bit, when set, turns on the Control Bus
Arbitrator for the seven other Control Bus requesters. When clear, only the P.ioc may access
Control Memory.

10 CLEAR - This write-only bit is used to clear lIO page device registers.

HIGH-BYTE PARITY TEST - This bit, when set, causes the high byte parity tree to generate
even parity on the next write-cycle to memory, therefore writing incorrect high-byte parity at
that address. The bit is automatically cleared following that write cycle. This function applies
to all three areas of men10ry (Program, Control, and Data). This bit is also cleared by BUS
INIT, but not by lIO CLEAR.

LOW -BYTE PARITY TEST - This bit performs the same function as bit < 05 > except for the
low byte.

LED - This bit lights a yellow LED, D6, located near the handle of the P.ioc and also drives
the STATE lamp located on the Operator Control Panel.

NON-MEMORY-ACCESS - This bit when set, causes the P.ioc to execute an NMA cycle on
the very next Control Memory or Data Memory access it makes. This bit is cleared automatically at the conclusion of that Control or Data Memory access. This bit has no effect on and
is not cleared by Program Memory accesses.

CONTROL MEMORY INTERRUPT ENABLE - This bit, when set, causes the P.ioc to execute
an interrupt cycle on the very next Control Memory access it makes. This bit is cleared
automatically at the conclusion of that Control Memory access. Note that if the P.ioc accesses
Data Memory with this bit set, the bit will be cleared after that access with no interrupt
generated.

8-18

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Table 8-10 (Cont.)

Pio Control and Status Register Bit Description

Bits

Description

CONTROL MEMORY LOCK - This bit, when set, causes the P .ioc to execute a lock cycle on
the next Control Memory access it makes. This bit is cleared automatically at the conclusion
of that memory access. Note that if the P.ioc accesses Data Memory with this bit set, the bit
will be cleared after that access with no lock cycle generated.

The last three bits (NMA, CNT IE, and LCK) have been prioritized such that, if mure than one bit is set
at a time, the highest priority bit will determine which type of cycle will occur. Following that cycle, all
set bits will be cleared. The priority of these bits is:
1. NMA
2. CNT IE
3. LCK

8.15 K INIT AND STATUS REGISTERS
The K INIT and Status Registers initialize and hold the eight bit status of the:
Host Interface (K.pli)
Disk Data Channel (K.sdi)
Tape Data Channel (K.sti)
Figure 8-15 shows the format of the K INIT Register located at 177700448 . Table 8- 11 describes the bits
in the K INIT Register.

Figure 8-1.5

K INIT Register

K
INI;----=c SPAR:=I
<7:0>
-----

KST

<3:0>
,---03 02 01

--]
00

CXQ-1140A

Table 8-11

K INIT Register Bit Description

Bits

Description

15:08

K INITIALIZE < 7:0 > - These bits are backplane slot-specific clear signals. A zero in
any bit position clears the module in the corresponding backplane slot. A one in any bit
position negates the clear to that module and enables it to run. These bits are cleared to
zero on power-up only. Note that since the P.ioc is considered Requester 0 in the HSC50,
K INIT < 0 > has no significance.

8-19

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Table 8-11 (Cont.)

K INIT Register Bit Description

Bits

Description

07:04

These bits are spare bits.

03:00

SELECT K STATUS - These four bits are decoded to select the status of a requester.
The codes refer to specific backplane slots. These bits are written first and then the Status
Register is read to obtain the status. The HSC50 provides for only eight requesters (codes
008 through 078). Any code greater than 078 generates a STATUS byte of 3778 or all ones
in the Status Register.

Figure 8-16 shows the format of the Status Register located at 177700468 . Table 8-12 describes the bits
in the Status Register.

Figure 8-16 Status Register

___

[:ITIT~ITEEL ~!__~_~_~_S
15

CXO-1141A

Table 8-12

Status Register Bit Description

Bits

Description

STATUS PARITY - This bit is Status Parity. The Ks supply the parity bit from software (even
or odd). The P.ioc checks the parity with software.

06:00

STATUS - These bits are the 7-bit status code returned from each K. Note that if a backplane
slot is not occupied, reading the status for that slot returns a status byte of 3778 or all ones.
NOTE
Both the K INIT Register and Status Register are
read/write. However, byte-writes to K INIT Register write all 16 bits of this register.

8.16 THE INTERFACE TO CONTROL MEMORY
The interface to Control Memory consists of three blocks:
•

Control Memory Windows

•

Control Bus Interface

•

Control Bus Arbitrator and Timing

The following sections describe these three blocks which are shown at the right side of Figure 8-2.

8-20

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

8.16.1
Control Memory Windows
The P joe software has very little need to access Data Memory because the Ks load and unload data
buffers. But the software needs to access many different control blocks scattered all over Control Memory. In addition to the standard MMU, there is a need for a separate address relocation feature for
Control Memory. A large number of page address relocation registers is needed, but page descriptor
registers are not necessary.
The Control Window feature provides 1024 Window Address Registers (WADRs) They are used whenever there is a virtual address in the range 16xxxx8.
NOTE

Throughout this discussion of Control Window Logic,
a 16-bit address is used for ease of explanation.
However, the MMU translates this 16-bit address to
a 22-bit address, then gates it onto the BOAL Bus.
Whenever an address is in the 16xxxx8 range:
•

The hardware activates the Control Memory Window logic

•

The appropriate Window Address Register is gated (along with part of the virtual address) to
the Control Memory Address (CADR) lines

•

The Control Bus is requested

•

Control Memory is accessed

The software can still use the MMU to access Control memory, but this is rarely done.
The software can access the W ADRs to load and read them by using 110 page addresses.
All of the hardware for this feature resides on the P.ioc module and consists of the following:
•

1024 WADRs contained in a lK x 16 RAM

•

WINDR 1700208 - Window Index Register

•

WBUSR 1700228 - High Order Address History Register

•

LOCADR 1700548 - Low Order Address History Register

The WADRs are the actual page address registers. The WINDR is an index register used as part of the
WADR l-of-l024 selection. The WBUSR and LOCADR are history registers that hold the CADR of the
last Control Memory access for error recovery and diagnostic purposes.
8.16.1.1
Control Memory Window Address Selection
The software uses the Control Memory window logic to change a 16-bit PDP-II address into a 17-bit
Control Memory address. This 17-bit address then points to a control block in Control Memory. Control
blocks start on a double-word boundary and the address represents an offset frOIn the start of Control
Memory measured in increments of double words.
To change the 16-bit address to a 17-bit address the software performs the following four steps:
•

Selects a window set

•

Writes a double-word offset address into a WADR

•

Reads back a virtual address

•

Uses the virtual address to address Control Memory

8-21

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 8-17 is a sample PDP-II macro program that shows the steps involved in changing the 16-bit
address to a 17-bit address using the WINDR and WADR. The following describes the steps:

Figure 8-17 WADR Addressing
012767 000005 170020

MOV D #5.$WINDR

016767 100000 170006
016700 170006

MOV ~
MOV ~

DBPTR.$WADR3 ;MOV the double word offset to WADR3
$WADR3.RO
;get the virtual address in RO

011002

MOV ~

eRO) .R2

;select window set #5 using the
;window index register

;get the contents of Control Memory
;and put it in R2

CXO-1142A

The first MOV writes a 5 in the WINDR which selects window set number 5 out of a possible
128 sets. Figure 8-18 shows how the 1 Kword by 16-bit RAM is divided into 128 window sets
of eight WADRs.
The WINDR is loaded once prior to using a window set.

The second MOV writes the double-word offset address from the Control Memory virtual
address of 0 to WADR3. The source is gated directly into the WADR without shifting the bits,
as shown in the upper portion of Figure 8-19.

The third MOV reads back a sort of virtual address from WADR3. The low order seven bits
of the WADR3 are shifted left two places and gated onto the IN BUS as show in the middle
portion of Figure 8-19. The I/O page address is 1700068 . Table 8-13 shows the register address
of each WADR and the virtual 110 page address range each covers.

The fourth MOV uses the sort of virtual address obtained from step 3 above to actually address
Control Memory. When the Control Window Logic is activated (by a virtual address in the
16Zxxx8 range), the high order nine bits of the WADR are shifted left one place and gated onto
the CADR lines as shown in the bottom portion of Figure 8-19.
NOTE
The Z in the virtual address 16Zxxxs is the
WADR register.

8-22

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 8-18 Window Address Register Selection
WINDOW SET 5 WADR 3

10 a a W W W I WINllR
10F128
~
----~

WADRl

x x

V I R 1 U A LAD DR E SS

aaY Y

I/O PAGE ADDRESS

1 6 Z X

WADR 2
WADR 3
1 OF 8
WADR4
WADR5
WADR6
WADR 7

1 7
~------~y~-----~

1KW X 16-BIT RAM

CX-423B

Table 8-13 1/0 Page Address of Window Address Registers
Register

1/0 Page Address

WADRO

170000

160000-160777

WADR1

170002

161000-161777

WADR2

170004

162000-162777

WADR3

170006

163000-163777

WADR4

170010

164000-164777

WADR5

170012

165000-165777

WADR6

170014

166000-166777

WADR7

170016

167000-167777

Only 16-bit virtual addresses are shown here. However, the MMU would add bits to make 22-bit
addressing.
Note that the third most significant digit of the 110 page address corresponds to the associated WADR.

8-23

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 8-19 WADR Gating

SOURCE
WADR INPUT
LOADING WADR BY
INSTRUCTION VIA
I/O PAGE ADDRESS
1700XX
WADR

WADR
WADR OUTPUT
ACCESSING WADR BY
INSTRUCTION VIA
I/O PAGE ADDRESS
1700XX
DEST

WADR
WADR OUTPUT
USED BY CM LOGIC
CAUSED BY VA
16ZXXX
CADR

CX-422B

8.16.1.2
Control Window Example
The following example selVes to illustrate the use of a Control Window. This explanation refers to
Figure 8-20.
1.

A control block is set aside in Control Memory by the P joe. The starting address of this control
block is designated by a 16-bit pointer that represents the offset (in increments of double words)
from the start of control memory.
In this example, the pointer is 0004108 or an offset of 4108 double words from the start of
Control Memory. Such an offset corresponds to Control Memory address 0010208, assuming
word addressing started at 0000008 , (An MMU access of the same address would use the
physical 22-bit, byte-oriented address 160020408 ,)
The software selects one of the WADRs to use. To illustrate, in this case it chose window set
5, WADR3.

For selection of window set 5, the software deposits a 58 in WINDR.

The software then deposits the pointer 0004108 into WADR3.

WADR3 contains a pointer 0004108.
The software retrieves the contents of WADR3 with a standard PDP-l1 instruction.
WADR contents are gated as follows:
8-24

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

-----------11

Figure 8-20 Control Window Example

BYTE DESIGNATOR
WORD DESIGNATOR

DOUBLE WORD DESIGNATOR

17 16 15 14 13 12 11 10 9
WADR

oJ
,---.A...--.,

ell
11 1 1 0 0 1 1 0
'----y-----J '---..r----J

iii
WADR

°2~

01~

(

~) +

,, , ,

r ,

•

1
-

em
WBUSR

.2~

em
CADR

) IJ

~~
1 1 0 0 1

IN BUS

0: 1]

-',

1---

I. , ,

)

-'~0-2~

LOCADR

CX-424B

8-25

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Zeroes are gated onto IN BUS < 01:00 >, forcing a double word boundary.

Bits < 06:00 > of the WADR are gated onto IN BUS < 08:02 >. These bits shift left two
places, aligning the low-order bit of the pointer with a double-word designation.

011 2 is gated onto IN BUS <11:09> because this is WADR3.

11102 is gated onto IN BUS <15:12> because a WADR was addressed and creates
16xxxxxs·

The result is 163040s . This will be used by the software as a 16-bit virtual address.
Virtual address 1630408 corresponds to the start of the control block in this example.
If the software requires only the first control block of this word or byte, it would add

nothing to this base address. Suppose the software wants to examine some information deeper in the control block.
[4

For instance, to examine the third byte (low-order byte of the second word) software
adds two to the virtual address.
The virtual address then contains 1630422 , used by the software as the virtual address
in a PDP-11 instruction. Because the hardware sees the virtual address in the 16xxxxs
range, the window logic is activated which forces use of the Control Bus. As a result,
the hardware:

Sees 16xxxx8 and activates the Control Window.

Sees xx3xxx8 and selects WADR3. (WINDR still selects window set 5.)

m Gates WADR3 <15:07> onto CADR <16:08>.

m Gates virtual address < 08:01 > onto CADR < 07:00 >.
iE

Uses virtual address < 00 > as a byte designator, if a byte instruction is being executed.
CADR < 16:00 > (001021 s ) on the Control Bus accesses a word in Control Memory.
This is the second word of the control block.
Finally, the hardware captures CADR < 16:00> and saves it in the history registers.

CADR < 16:01 > is captured in WBUSR < 15:00 >.

CADR < 00 > is captured in LOCADR < 01 > .

Control Window Limitation
8.16.1.3
One limitation is placed on the Control Window feature. If the software is sequentially accessing information from a control block, and it crosses a 1000s byte address boundary, the new address would
have incremented the Z in virtual address 16Zxxxs. This would result in selecting a different WADR. So
there is a 1000s byte address boundary limitation. This limits the maximum size of a control block to
512 bytes assuming it starts at a 1000s byte boundary; less if it starts at other than a 1000s boundary.
8.16.2
Control Bus Interface
The Control Bus Interface block contains the Control Bus Data Transceivers and Control Bus Address
Transceivers for the P.ioc (shown on the right side of Figure 8-2).

8-26

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

8.16.2.1
Control Bus Data Transceivers
The Control Bus Data Transmitter is 20 bits long:

•

< 15:00> is data

•

Bit 16 is low byte parity

•

Bit 17 is high byte parity

•

Write low byte (CWRTL)

•

Write high byte (CWRTH)

The translnitters are written from the OUT BUS at DOUT time if the address is between 1600008 and
1677778 ,
The Control Bus Data Receiver is 18 bits long:
•

< 15:00> is data

•

Bit 16 is low byte parity

•

Bit 17 is high byte parity

The receivers are enabled onto the IN BUS < 15:00> at DIN time if the address is between 1600008
and 1677778 ,
8.16.2.2
Control Memory Address Transceivers
The Control Memory Address Transceiver (CADR) address inputs are controlled by the Control Memory
Window logic (Section 8.16.1).
'
The Control Memory Address Receivers are two read-only registers:
•

Window Bus Register (WBUSR) - 1700228

•

Low Control Memory Address Register (LOCADR) - 1700548

These two registers provide access to the address asserted on the Control Bus on each P joc cycle. They
are updated after each Control Bus cycle by the pjoc.
The Window Bus Register contains the high-order 16 bits of the 17-bit word address.
Figure 8-21 shows the format of the Low Control Memory Address Register. Bit < 00 > of this register
is bit < 00 > of the 17-bit word address.

Figure 8-21

Low Control Memory Address Register

ITEErrt I I I I I I Ig~D[l
0

CXQ-1143A

8-27

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

8.16.3
Control Bus Arbitrator and Timing
The P.ioc module contains the timing and arbitration logic for the Control Bus (shown in the lower right
of Figure 8-2). For signal polarities and information about this bus, refer to Chapter 3.
The Control Memory consists of dynamic RAMs (DRAMs) which must be refreshed. To do this, the
P.ioc generates an internal 66.7 KHz (15 .usecond period) clock to indicate when a refresh cycle is to be
performed. This signal is input to the Control Bus Arbitrator as the highest priority Control Bus request.
The arbitrator acknowledges the refresh cycle by the assertion of CREFR GRANT on the next available
Control Bus cycle, with the same timing as any of the CGRANT n signals. The Control Memory logic
thus uses the assertion of CREFR GRANT to initiate an internal refresh cycle.
NOTE
Refreshing is independent of the ENACBS bit in the
PIOCSR.
8.16.4
Interrupt Cycle
To execute a Control Bus Interrupt cycle, it is only necessary to set the CN IE bit in PIOCSR and then
MOV the Interrupt Mask to ANY Control Memory address, using either the Control Memory Windows
or Memory Management. A 1 in any bit position will queue an interrupt at that level to the P .ioc.
Interrupts on more than one level may be generated by one Control Bus Interrupt cycle. The CNT IE bit
will be cleared at the completion of the Interrupt cycle. Figure 8-22 shows the format of the Interrupt
Mask.

Figure 8-22

P joe Control Bus Interrupt Mask

ITJJIITIIIITI I ~T±J
7

CXO-1144A

8.16.5
Lock Cycle
To execute a Control Bus Lock cycle, it is only necessary to set the LCK ENA bit in PIOCSR and then
MOV the desired Lock Address to any destination where it may be examined to determine if the location
is already locked. At the completion of the Lock cycle, the LCK ENA bit in PIOCSR is automatically
cleared.
8.17 DATA MEMORY INTERFACE
The Data Memory Interface consists of two blocks of logic shown on the lower right of Figure 8-2:
•

Data Bus Interface

•

Data Bus Arbitrator and Timing

The P.ioc module contains the timing and arbitration logic for the Data Bus. In addition, the P.ioc is the
lowest priority requester. The followings sections describe the Data Memory interface logic.

8-28

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

8.17.1
Data Bus Interface
The Data Bus Interface block contains the Data Bus Data Transceivers and the Data Bus Address
Transceivers for the P .ioc. The following sections describe these two transceivers
8.17.1.1

Data Bus Transceivers

The Data Bus Data Transmitter is 20 bits long:

•

< 15:00 > is data

•

Bit 16 is low byte parity

•

Bit 17 is high byte parity

•

Write low byte (DWRTL)

•

Write high byte (DWRTH)

The transmitters are written from the OUT BUS at DOUT time if the address is bt'lween 140000008 and
157777778 ,
The Data. Bus Data Receiver is 18 bits long:

•

< 15:00 > is data

•

Bit 16 is low byte parity

•

Bit 17 is high byte parity

The receivers are written onto the IN BUS < 15:00 > at DIN time if the address lS between 140000008
and 157777778 ,
8.17.1.2
Data Bus Address Transceivers
The Data Bus deals with word addresses and has 18 significant address bits. This 18 bit address is
handled differently in the Data Bus Address Transmitters than in the Data Bus Address Receivers.
8.17.1.2.1
Data Bus Address Transmitters
The address on the OUT BUS < 18:01 > is clocked into the Data Bus Address Transmitters < 17:00 >
when the address is between 140000008 and 157777778 , Notice the shift of one bit to the right to make
the address a word reference.
8.17.1.2.2
Data Bus Address Receivers
The Data Bus Address Receivers are two read-only registers. These registers are:
•

High Data Bus Address Register (HIDADR) located at 177700528

•

Low Data Bus Address Register (LODADR) located at 177700508

After each Data Bus cycle by the P.ioc, the registers are updated with the 18-bit wor i address. Figure 8-23
shows the format of the two receiver registers.

8-29

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 8-23

Data Bus Address Receivers

HIDADR

0._S_~_ _ _ >IA<17:1~

[ _______

08 07

03 02 01 00

LODADR
[ ______.___D_a_t_a. __
Bu_s__A_d_d._r_e_ss__<_1._4_:_00_>__
08 07

~
01 00
CXO-1145A

8.17.2
Data Bus Arbitrator and Timing
The P .ioc module contains the timing and arbitration logic for the Data Bus. For signal polarities and
information about this bus, refer to Chapter 3.
The P .ioc has the lowest priority Data Bus requester.
8.18 I/O PAGE ADDRESS UTILIZATION
Table 8-14 is a list of the I/O page addresses assigned in the P.ioc.

Table 8-14 1/0 Page Address Utilization
Physical Address

Function

17777776

Processor Status Word

17777656
17777654
17777652
17777650
17777646
17777644
17777642
17777640

User PAR 7
User PAR 6
User PAR 5
User PAR 4
User PAR 3
User PAR 2
User PAR 1
User PAR 0

8-30

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Table 8-14 (Cant.)

110 Page Address Utilization

Physical Address

Function

17777616
17777614
17777612
17777610
17777606
17777604
17777602
17777600

User PDR 7
User PDR 6
User PDR 5
User PDR 4
User PDR 3
User PDR 2
User PDR 1
User PDR 0

17777576
17777574
17777572

Memory Management Status Register 2
Memory Management Status Register 1
Memory Management Status Register 0

17777566
17777564
17777562
17777560

Console Xmtr Data Buffer Register
Console Xmtr Status Register
Console Rcvr Data Buffer Register
Console Rcvr Status Register

17777536
17777534
17777532
17777530

TU58 2 Xmtr Data Buffer Register
TU582 Xmtr Status Register
TU58 2 Rcvr Data Buffer Register
TU58 2 Rcvr Status Register

17777526
17777524
17777522
17777520

TU58 1 Xmtr Data Buffer Register
TU58 1 Xmtr Status Register
TU58 1 Rcvr Data Buffer Register
TU58 1 Rcvr Status Register

17776776

17773000

}

BootStrap PROM

17772516

Memory Management Status Register 3

17772356
17772354
17772352
17772350
17772346
17772344
17772342
17772340

Kernel PAR 7
Kernel PAR 6
Kernel PAR 5
Kernel PAR 4
Kernel PAR 3
Kernel PAR 2
Kernel PAR 1
Kernel PAR 0

8-31

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Table 8-14 (Cont.)

110 Page Address Utilization

Physical Address

Function

17772316
17772314
17772312
17772310
17772306
17772304
17772302
17772300

Kernel PDR 7
Kernel PDR 6
Kernel PDR 5
Kernel PDR 4
Kernel PDR 3
Kernel PDR 2
Kernel PDR 1
Kernel PDR 0

17770056

Serial Number Register

17770054

Control Memory Low Address Register

17770052
17770050

Data Memory High Address Register
Data Memory Low Address Register

17770046
17770044

K Status Register
K Init Register

17770042

Switch/Display Register

17770040

Pio Control and Status Register

17770026
17770024

High Error Address Register
Low Error Address Register

17770022
17770020
17770016
17770014
17770012
17770010
17770006
17770004
17770002
17770000

Window Bus Register
Window Index Register
Window Address Register 7
Window Address Register 6
Window Address Register 5
Window Address Register 4
Window Address Register 3
Window Address Register 2
Window Address Register 1
Window Address Register 0

17767776 }
Control Memory Windows
17760000

1/0 PAGE REGISTER FORMAT SUMMARY
Figure 8-24 is a summary of the 110 page registers on the P.ioc.

8.19

8-32

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 8-24 110 Page Register Format Summary
WADR n

(17 770 000 - 016)

(WRITE)
DOUBLE-WORD POINTER
(HIGH 16 BITS OF 17-BIT WORD ADDRESS)
15

(READ)
1

512 BYTE OFFSET = ADDRES ~-~;--j
LOW-ORDER WORD OF DOUBLE we

~~-~

(0 - 7)
15
WINDR

(17 770 020)

I~_O~I_O_~I_O~I_O~I_O~I_O~I_O~I_O~I__O~1~____(~_~_~_DO__W_1__~~:~~~~
15
WBUSR

(17 770 022)
DOUBLE-WORD POINTER OF
LAST CONTROL MEMORY REFERENCE

LOEADR (17 770 024)

~----.~-~PHYSICAL ADDRESS
<15:00>

CX:O-1146A
SHEET 1 OF 4

(Continued on next page)

8-33

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 8-24 (Cont.)

1/0 Page Register Format Summary

HIEADR

(17 770 026)

0 I 0 I 0 I 0 I 0

PIOCSR

0 I 0

PHYS!~~~l!~ORESS~

(17 770 040)

TRM
ENA

SWP SWP SEL SEL ENA 10 HIP LOP LED NMA CNT LCK
BRD BNK P1 PO CBS CLR TST TST
IE

SW
3

SW
2

SW
1

SW
0

DIA C/olINH LMP LMP LMP LMP
OK NXM PAR 4
3
2
1

IL~pl

SWDR

(17 770 042)
RESERVED

15
KINR

(17 770 044)
K INIT
<7:0>

KSTR

(17 770 046)

SPARE

KST
<3:0>

CXO-1146A
SHEET 2 OF 4

(Continued on next page)
8-34

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 8-24 (Cont.)

110 Page Register Format Summary

LODADR

(17 770 050)
D_A_T_A__
BU_S__A_D_D_RE_S_S________________
<14:00>

-~~
_U

__________________
L..

HIDADR

(17 770 052)

I I I I I I I I I I I I I I D!i~-~~
0

LOCADR

T~G
15

(17 770 054)

I0 I0 I0 I0 I 0 I0 I0 I 0 I0 I 0 I 0 I 0 I0 I 0
16

I~~~

(17 770 056)
16 BIT
SERIAL NUMBER
14

(17 777 620)
TU58-1 RCSR
(17 777 530)
TU58-2 RCSR
(17 777 560)
TERM RCSR

I~~~I

l:g~I~~vl

I0 I 0 I 0 I

o~
00

CXO-1146A
SHEET 3 OF 4

(Continued on next page)

8-35

HSC50 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 8-24 (Cant.) 110 Page Register Format Summary
(17 777 522)
TU58-1 RBUF
(17 777 532)
TU58-2 RBUF
(17 777 562)
TERM RBUF

~IE_R_R~I~_~_:~I~_:_:~I_o~I o~l_o~l_o~I_O~I~
___

R_E_g_~i_~_E_D

________

______

(17 777 524)
TU58-1 XCSR
(17 777 534)
TU58-2 XCSR
(17 777 564)
TERM XCSR
I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0
15

I~~~I~:TI 0 I

I
04

IMNTI
03

IBRKI

(17 777 526)
TU58-1 XBUF
TU58-2 XBUF
(17 777 536)
(17 777 566)
TERM XBUF
TRANSMITTED
DATA

I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I
15

CXO-1146A
SHEET 4 OF 4

8-36

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

CHAPTER 9
HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

9.1 INTRODUCTION
The HSC70 Input/Output Control Processor Module (J -11 P joj) is an extended hex module that contains
the following logic:
•

Eight LEDs for status indications

•

A DCl11 (J-11) processor (with integral memory management)

•

Timing and interrupt logic for the J-11

•

A 4-Kword instruction cache

•

An interface to Program Memory, with integral direct memory access (DMA) and interrupt
capability

•

A bootstrap PROM

•

110 page windows into Control Memory

•

Control, timing, and arbitration for the HSC70 Data Bus and Control Bw·;

•

An RS-423 / DL-11 compatible interface for a console terminal for the J- J 1

•

Pio Control and Status Register

•

An interface to the HSC70 Operator Control Panel (Switch/Display Register)

•

K Init and Status Registers

•

Error Address Register

•

Serial Number Register

•

Control Memory and Data Memory interfaces

9.2 LED INDICATORS
The P.ioj contains eight LED indicators (Figure 9-1): one red, one green, and six yellow. These LEDs
are described in the following sections.
9.2.1
P.ioj Diagnostic OK LEOs
The red LED (D7) and green LED (D8) are used to indicate whether the Pjoj successfully completed
all of its initialization diagnostics. The module powers up with the red LED on and the green LED off.
Upon successful completion of the power up diagnostics, the red LED is turned off and the green LED
is turned on. This LED is controlled by a. bit in the Switch/Display Register (Section 9.11).

9-1

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 9-1

P.ioj LEOs

(i)
}.lODT

SLU
MEM

SEQ
STATE
RUN

~
~

RED
GREEN

STATUS

CX-1069A

9-2

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

9.2.2
RUN LED
A yellow LED, D6 (adjacent to the red Diagnostic OK LED), blinks once for each PDP-II instruction
fetch cycle" This is analogous to the RUN light on standard LSI-II processor systems. When the J-ll
is running, this LED will be illuminated at about half-brilliance (compared to the other LEDs on the
module).
9.2.3
State LED
This yellow LED (DS) is controlled by bit < 03 > of the Pio Control and Status Register (PIOCSR) and is
connected in parallel with the State indicator on the Operator Control Panel.
9.2.4
Status LEOs
The four yellow Status LEDs (DI-D4) are controlled by the J-ll internal microcode. All four LEDs are
initially on. As soon as the J-ll starts operating, it turns off the micro-ODT LED (Dl). After going through
several microcode steps, LED D4 is turned of( indicating that the J-11 is sequencing and has reached
this point in the microcode. It then performs several memory operations and, if successfut turns off
the MEMORY OK LED, D3. Finally, the J-ll tests whether the console terminal port is functional and,
if so, turns off LED D2. The J-l1 then proceeds to the bootstrap.

In addition, any time the J-ll is executing ,uODT, LED Dl is on.
9.3 HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE BLOCK DIAGRAM
Figure 9-2 is a block diagram of the P.ioj showing the principal hardware elements and data paths. Each
of these elements will be described in the following sections.

9-3

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 9-2
TIMING

HSC70 Input/Output Control Processor Module Block Diagram

-- CLK A/B
-- CLK CTL

1-3

tV
J-11

fL-

\r-

J-11
OUTPUT
REGISTER
(74F373)

B < 21:00

> H

MDAL
< 21 :00 > H

~7
4K WORD
INSTR CACHE
AND CONTROL

DMA
REGISTER

1, 4

~ PROGRAM
MEMORY

BUS
XCVRS
(2908)

INTERRUPT
LOGIC

Vii'r

~~
16
J-ll
INPUT
REGISTER
(74F373)
2

TO
PROGRAM
MEMORY
BUS

A <

21:00 > H

OUTBUS
DRIVERS
OUTBUS <

(74LS248)

21:00 > H

6
10 PAGE
ADDRESS
DECODES

LOAD

PIOCSR

STROBES

SWITCH/DISPLAY
REGISTER

(17 770040)
READ
STROBES

(17 770042)
19,8

INBUS
RCVRS
INBUS < 15:00 > H

(74L248)

TO
OPERATOR
CONTROL
PANEL
NOTES:
1. * THESE BLOCKS HAVE INPUTS TO
THE INTERRUPT LOGIC
2. NUMBERS IN LOWER LEFT HAND
CORNER OF BOXS REFER TO PAGE
NUMBERS IN THE MODULE SCHEMATIC
CX-1070A

Sheet 1 of 2

(Continued on next page)

9-4

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 9-2 (Cont.)

HSC70 Input/Output Control Processor Module Block Diagram

PROGRAM
MEMORY
BUS

BIBUS
XCVRS
BIBUS

(DC021)

15:00

13
BOOTSTRAP
PROM
(17 773000
TO
17 776 776)
13

CONSOLE
TERMINAL
INTERFACE
(DC319)
(17 777 56X)
12

AUX1,AUX2
INTERFACES
(DC319)
(17 777 52X)
(17 777 53X)
12

TO
CONSOLE
TERMINAL

OUTBUS

21 :00 > H

~
K INIT AND
STATUS
REGISTERS
(17 770044)
(17 770046)
14

INBUS

CLEARS
TO Ks

CREO

CCYCLE

ERROR
ADDRESS
REGISTER
(17 77024,
17 770026)

SERIAL
NUMBER
REGISTER
(17 770056)

CONTROL
MEMORY
WINDOWS

CONTROL
BUS
INTERfACE

DATA BUS
INTERFACE

7, 8

9, 10

15:00 > H

STATUS
BUS
< 7:0 >

CONTROL
[iUS

CGRANT
CONTROL BUS
ARBITRATOR
AND TIMING ~--t... CTIMING
~---I'" CACK
CERR
11

DREO

DATA BUS
ARBITRATOR
AND TIMING

DNMA ---II'" 11

DATA
BUS

DGRANT

~--I" DTIMING

CX-l070A
Sheet 2 of 2

9-5

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

9.4 P.ioj CONTROL LOGIC
The P.ioj control logic controls the operation of the P.ioj. The control logic is located in the upper-Iefthand corner of Figure 9-2. Figure 9-3 shows a detailed block of this logic. The block contains:
•

DC}ll Microprocessor

•

Cache Data Path and Cache Memory

•

State Sequencer

•

Input/Output Control Logic

•

Program Memory Input/Output Transceivers

Each of these blocks is described in the following sections.
NOTE
For a detailed explanation of this logic, refer to the
KD/1l-A CPU Module User's Guide (EK-KDJ1A-UG).
9.4.1
DCJ11 Microprocessor
The DC}11 Microprocessor has the complete PDP-II/70 instruction set plus PDP-I1I44-11I70 memory
management for addressing up to two-million words of memory. The complete processor is implemented in one 60-pin hybrid package. Figure 9-4 is a block diagram of the DC}11 Microprocessor. It
performs the following functions:
•

Executes the PDP-II instruction set

•

Controls the memory n1anagement

•

Supports the console micro-ODT

•

Initiates all the data transfers and operations
NOTE
For a detailed explanation of the DCJ11 Microprocessor, refer to the DCIll Microprocessor User's Guide
(EK-DCJ11-UG).

Besides the standard PDP-II registers, the DClil contains special registers. The way they are implemented in the P .ioj is described in the following sections.
9.4.1.1
Cache Control Register
The Cache Control Register (CCR) contains information which is used to control the operation of Cache
Memory. It is located at 177777468. Figure 9-5 shows the format of the register, and Table 9-1 describes
the bits. Unless otherwise noted, bits in this register are read/write.

9-6

Figure 9-3

P .ioj Control Logic Functional Block Diagram

~ DMA

A BUS

RSYNC

1\
11

B BUS

DMA REG OE __
P3
ALE

GP WRITE ..

OUTPUT
REGISTER

BUFCTL ..

~
RLE

I---

PROGRAM
MEMORY
BUS
RECEIVERS

A BUS

MBUFCTL

MDAL BUS

TAG BUS

P2
MPARITY

RLOE ..

EVNT EN
P5

STRB

V1--sBU~
i'f
vi

MABORT

GP WRITE

B BUS

CACHE
DATA PATH
INPUT
REGISTER

""'--

ILOE

STATUS
LEDS

...

MMISS
CACHE
MEMORY

COMP

•

Vt-

~
P4

i'r

..
.

en
o....,

PROGRAM
MEMORY
BUS
TRANSMITTERS

Z
"U

c:
-I
(3
c:

-I

CACHE CONTROL

c:
-I

RPOK
~

MAINTENANCE
REGISTER

MDAL BUS

r-!---

DCJ11-AA
MICROPROCESSOR

MMISS

PROCESSOR

MPARITY

CONTROL

MEVENT

MALE

I---

RLE

TERM ENA

GP DATA OE

RLOE

I MDV

MBUFCTL

--'"'

MCONT__

MSTRB

STATE

-'"

SEO!JF.~.'CI=Q

-..

-I

:u
o
r-

DMA REG OE

GP DATA Of.,

......

PMEM BUS OE

ILOE
MDV

COMP

CONT

ABORT ..

DRCP
P1

...

r--

en
en
o
:u

s:
o

o
c:
r-

CX-1071A

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 9-4

DC}ll Block Diagram

- - - - - - - - r
I

PARITY ___
DMR ___

I
I
I

MISS ___
ABORT ___

r----

I/O
STATE
SEQUENCER

~------------------~V

ALE

......... BUFCTL

~1~6~B~IT~----------------_,;; PAGE

I
I

......... PRDC

~BSO

ADDER

~BS1

L.f\
~
1I~___~122-BIT

16-BIT

~US3~

LENGTH

IV)JL-______~~

t-~VA~(1~26~)_ _

....J

PAR/PDR REGISTER
FILE (INCLUDES
FLOATING POINT
REGISTERS AND CPU
ERROR REGISTERS)

~6-BIT

22-BIT

M BUS

MULTIPLEX

v
'\

INPUT/
OUTPUT
LATCHES

SPECIAL REGISTERS

MMRO
MMR1
MMR3
MEMORY
MANAGEMENT

r--

t - - - - - .I\.'\ COMPARATOR ~

-;;'ATZ'7HIP'

ABORT

~~~---------------~~,...------..,CARRY

STRB

- . scn:

CONT ___

- - - - - - - - - -,..._----..,-

I ,...----------------------~~

CACHE CONTROL
HIT/MISS
PIRO

- -l\r---1-----'\J\
--------------~

B BUS 32-BIT /

MAIN REGISTER
FILE (CONTAINS
GENERAL PURPOSE
REGISTERS)

A
. ; BUS

S BUS 32-BIT

)

V !%16

ARITHMETIC

TER

t\ ,...---..,

F BUS 32-BIT,)

~ SWAPPER

LOGIC

32IBI~T

INPUT/
OUTPUT

DATA 22 BIT

~ MULIPLEXER "

____

f\-

v'------~

--V

SHIFT

21-00

I-C CONTROL

EXECUTION
CONTROL
CONDITION A
CODE
V'---

h
I

LOGIC

L.:.XE~ION_

A BUS 32-BIT

~_---_----_---_---_----_----_----'_

-- -- -- -- -- -- -- -- -- -- J

r
FPE - .

I\r- ,,....-I

PWRF ....
HALT ....
PARITY ..... ~~~~~~~PT

,.....

IL..:::-

PLA

IRQ

~~~~TER

~ggl~ESS

° -.

::~ ~

IRQ3....

L..:.0N"~~L

I I

IDAL
LATCH

~
~

ABORT
SERVICE
LOGIC

EVENT .... LOGIC

~.7r----.....

'00::

IDAL BUS 16BIT

N-

I I N,

___ A100

~~gE

rMICROSTORE
(PLA/ROM)

_______

- - . . A 101
GENERATOR ----- A102
'----'\-------

t---

:BU~

...

11__ ~

:"03 _ _ _

I
I
I

CO~ROLCHIP J

CX-1072A

9-8

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 9-5

Cache Control Register

/oT~~IWRWIBypIFL IPARIWRWI ~ FORCE DIA~~
~~l~ TPR
15

ABT DPR

~ MISS

MDE1~~J

CXD-1159A

Table 9-1

Cache Control Register Bit Description

Bits

Description

15:11

These read-only bits are always O.

When set, WRITE WRONG TAG PARITY, this bit causes incorrect tag parity to be written on
cache writes. A cache tag parity error will occur on the next access to that location.

When set, UNCONDITIONAL CACHE BYPASS, this bit forces all references to memory by
the J-ll to go to Program Memory. Read or write hits will result in invalidation of those
locations in the cache; misses will not change the contents.

When set, FLUSH CACHE, this bit causes the entire contents of the cache to become invalid.
This will take approximately 1.7 milliseconds. Note that while the flush is taking place, DMA
is not serviced. Resetting this bit causes no action. This write-only bit rt'ads as O.

If this bit, PARITY ERROR ABORT, is set and a cache parity error oCCUI'S, the cache reference

aborts through vector 1148 , The cache is updated.
06

When set, WRITE WRONG DATA PARITY, this bit causes incorrect data parity on both data
bytes to be written on cache writes. A cache data parity error will occur on the next access to
that location.

05:04

These read/write bits are not used.

03:02

When set, FORCE CACHE MISS, either bit reports the J-II memory references as cache
misses and disables cache parity checking. The cache is essentially removed from the system.

When set, DIAGNOSTIC MODE causes all non-bypass and non-forced-n1iss word writes to
allocate the cache, regardless of nonexistent memory errors.

This bit, DISABLE CACHE PARITY INTERRUPT, is used in conjunction with CCR<07>.
If CCR < 07 > is cleared, this bit determines what action is taken when a cache parity error
occurs. If this bit is cleared and a cache parity error occurs, the cache is updated and an
interrupt through vector 1148 is generated. If this bit is set and a cache parity error occurs,

the cache is updated but no abort or interrupt is generated.
This register is cleared on power up or by a console start. It is not affected by a RESET instruction.
A cache parity interrupt or abort will only occur if a previous cache parity abnrt has been cleared.
Specifically, MSER < 07: 05> must be cleared before new cache parity errors are recognized.

9-9

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

9.4.1.2
Cache Hit/Miss Register
The Cache Hit/Miss Register (CHMR) indicates whether the six most recent CPU memory references
resulted in cache hits or cache misses. Bits enter from the bit < 00 > position and shift left. A one
indicates a cache hit, a zero a cache miss. Figure 9-6 shows the format of the register. The register is
located at 177777528 and is read-only.
Figure 9-6

Cache Hit/Miss Register

ITEIIITEITI_"_<=-F._LOW],
15

CXO-1165A

The value of this register at power up is undefined. The register is not affected by console start or a
RESET instruction.
9.4.1.3
CPU Error Register
The CPU Error Register identifies the reason for any abort or trap through location 0048 , It is located at
177777668 and is read-only. Figure 9-7 shows the format, and Table 9-2 describes the bits.

Table 9-2

CPU Error Register

Bits

Description

15:08

These bits are always O.

When set, ILLEGAL HALT, this bit indicates that execution of a HALT instruction was attempted while in user mode, supervisor mode, or in kernel mode while the Operator Control
Panel SECURE/ENABLE switch was in the SECURE position.

When set, ADDRESS ERROR, this bit indicates that word access to an odd byte or an instruction fetch from an internal register was attempted.

When set, NON-EXISTENT MEMORY, this bit indicates that a reference to Program, Control,
or Data memory timed out.

When set, 110 PAGE TIMEOUT, this bit indicates that a reference to the 110 page timed out.
Note that a timeout to Control Memory while using the Control Memory Windows will set
this bit instead of nonexistent memory (NXM).

When set, YELLOW STACK VIOLATION, this bit indicates a yellow zone stack overflow trap
occurred.

When set, RED STACK VIOLATION, this bit indicates a push to the kernel stack aborted
while servicing an abort, interrupt, or TRAP instruction.

01:00

These bits are always O.

9-10

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 9-7

CPU Error Register

ILL ADR N
I/o YEL
RED
HLT ERR XM. TO
STK STK

I~_ 0 ]

I I

CXO-1166A

This register is cleared by power up, console start, and when it is written. It is not affected by a RESET
instruction.
9.4.1.4
Programmable Interrupt Request Register
The Programmable Interrupt Request (PIRQ) Register provides seven levels of software interrupt capability. The software queues an interrupt request by setting one of the PIR bits « 15:9 » in the register
which correspond to interrupt priority levels 7 through 1, respectively. Bits < 7:5> and < 3:1> are set
by the DeJ11 to the encoded value of the highest pending request. When the program interrupt request
is granted, the processor traps through a vector at virtual location 2408 . It is the responsibility of the
interrupt service routine to clear the appropriate bit in the PIRQ before exiting. The format of PIRQ is
shown in Figure 9-S. Table 9-3 describes the bits in the PIRQ.
This register is cleared by power up, by console start, and by RESET instructions. The PIRQ is located
at 177777728 .
Figure 9-8

Programmable Interrupt Request Register

IPIRIPIRlpljPIRlpI~IPIRlpIITO
PRIORITY=t} PRIORITY [~]
7
6
5
4
3
2
1
15:09
15:09
-

---~~--

-00

CXO-1167A

Table 9-3

Program Interrupt Request Register Bit Description

Bits

Description

15:09

When set, PROGRAM INTERRUPT REQUEST < 7:1> these read/write bits queue a program
interrupt request at levels 7 through 1.

This read-only bit is always O.

07:05

These read-only bits are set by hardware to the encoded value of the highest pending request.

This read-only bit is always O.

03:01

These read-only bits are set by hardware to the encoded value of the highest pending request.

This read-only bit is always O.

9-11

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

9.4.1.5
Memory Management Status Registers
Aborts generated by the Memory Managen1ent Unit (MMU) are vectored through kernel virtual location
2508 . Memory management registers 0, I, 2, and 3 are used to determine why the abort occurred and
to allow for easy program restarting. Note that an abort to a location which is in itself an invalid address
will cause another abort. The following sections describe these four memory management registers.
9.4.1.5.1
Memory Management Register 0
Memory Management Register 0 (MMRO) contains error flags, the page number whose reference caused
the abort, and various other flags. The register is located at 177775728 . The format of MMRO is shown
in Figure 9-9. Table 9-4 describes the bits in the MMRO.

Table 9-4

Memory Management Register 0 Bit Description

Bits

Description

This bit, ABORT NON-RESIDENT, is set by attempting to access a page with an Access
Control Field key equal to 0 or 2. It it also set by attempting to use memory relocation with a
processor mode of 2.

This bit, ABORT PAGE LENGTH ERROR, is set by attempting to access a location in a page
with a block number (virtual address bits < 12:06» that is outside the area authorized by the
Page Length Field of the Page Descriptor Register for that page.

This bit, ABORT READ-ONLY ERROR, is set by attempting to write in a read-only page.
Read-only pages have access keys of 1.

12:07

These read-only bits are always O.

06:05

These bits, PROCESSOR MODE, indicate the processor mode (kernel = 00, supervisor = 01,
user = II, illegal = 10) associated with the page causing the abort. If the illegal mode is specified, an abort is generated and MMRO < 15 > is set.

This bit, PAGE SPACE, indicates the address space associated with the page causing the abort
(I space = 0, D space = 1).

03:01

These bits, PAGE NUMBER, indicate the page number of the page causing the abort.

When set, ENABLE RELOCATION, this bit causes all addresses to be relocated. When
cleared, memory management is inoperative and addresses are not relocated.

Note: MMRO < 15:13 > can be set by an explicit write; however, such an action does not cause an abort.
Whether set explicitly or by an abort, MMRO < 15:13> cause the memory nlanagement logic to freeze
the contents of MMRO < 06:01 > Memory Management Register 1 and Memory Management Register 2.
These registers remain frozen until MMRO < 15:13> are cleared by an explicit write or an initialization
sequence.
MMRO < 15:13,00> are cleared by power up, by a console start, and by a RESET instruction. MMRO
< 06:01> are undefined at power up and reflect the last unfrozen relocation operation after a console
start or RESET instruction.

9-12

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 9-9

Memory Management Register 0

A~T
ABil~O-rr:IT~];ROC~G
~GE--~EN~J
MODE
SPC
NUMBER
REL

BT
NRS PLE ROE
e
15 14 13

CXO' 1168A

9.4.1.5.2
Memory Management Register 1
Memory Management Register 1 (MMRl) records any autoincrement/autodecrement of the general purpose registers. This register supplies information needed to recover from a Memory Management abort
by allowing programmed register back up.
MMRI is located at 177775748 and is read-only. Its state at power up is undefined. Figure 9-10 shows
the format of the MMR 1.

Figure 9-10

Memory Management Register 1
MOUNT CHANGED UEGISITER AMOUNT CHANGE~REG~S~'ER-J
(2'S COMPLEMENT)
NUMBER
(2'S COMPLEMENT)
NUMBER

[l
15

---._--

CXO-1169A
If MMRO < 15:13 > are non-zero, the contents of MMRI are frozen. If MMRO < 15:13> are zero, then

receipt of the signal MPRDC-L (start of macroinstruction) or an RDF microinstruction clears the register.
Thereafter, selection of the half (bits < 7:0 > versus bits < 15:8» of MMRI which is updated, when it
is not frozen, toggles between the two halves, starting with the low half (bits < 7:0.». Therefore, source
operand register changes will always be recorded in bits < 7:0 >; however, destination operand register
changes may be recorded in either half of MMR 1 (depending on the mode of the source operand and
the instruction type).
MMRI is undefined at power up.
9.4.1.5.3
Memory Management Register 2
Memory Management Register 2 (MMR2) is loaded with the current 16-bit virtual address at the beginning of instruction fetch. MMR2, located at 177775768 , is a read-only register. Its state at power up is
undefined.

9-13

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

9.4.1.5.4
Memory Management Register 3
Memory Management Register 3 (MMR3) performs the following functions:
•

Enables or disables the use of D space page address registers' and page descriptor registers

•

Enables or disables the use of 22-bit mapping

•

Controls data on the time-multiplexed input MAP (pin 19 of the DCJll)

MMR3, located at 177725168 , is cleared at power up, by a console start, and by a RESET instruction.
Figure 9-11 shows the format of the MMR3. Table 9-5 describes the bits in this register.

Figure 9-11

Memory Management Register 3

1oT~~IoToToToToT~ENA ENA ENA ENA]

~~~~~~~CSM KDS SDS UDS
15

CXO-1170A

Table 9-5

Memory Management Register 3 Bit Description

Bits

Description

15:06

These read-only bits are always O.

This read-write bit is not used.

When set, ENABLE 22-BIT MAPPING, this bit selects 22-bit relocation when MMRO < 00 > is
set. When cleared, 18-bit relocation is selected when MMRO < 00 > is set.

When set, ENABLE CSM INSTRUCTION, this bit allows recognition of the Call Supervisor
Mode instruction.

02:00

When set, ENABLE (KERNEL, SUPERVISOR, USER) DATA SPACE, this bit enables Data
Space mapping for the corresponding mode.

9.4.1.6
Micro-ODT
Micro-ODT, as currently implemented in the J-ll microcode, accepts 22-bit physical addresses. Therefore, all HSC70 memory is accessible using micro-ODT. Note that all I/O page references 177600008
through 177777778 require that all 22 bits be specified. However, leading Os for either address or data
are not necessary.
Input Register and Output Register
9.4.2
The Input Register and Output Register interface the A BUS and B BUS to the MDAL BUS. These
registers allow the DCJ11 to transmit addressing and data information on the B BUS to the Program
Memory Bus and receive data on the A BUS from the Program Memory Bus.

9-14

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

9.4.3
State Sequencer
The State Sequencer gate array generates most of the control and timing signals for the P .ioj control
logic. Data transfers over the A BUS and B BUS are controlled by the array. Furthermore, the Program
Memory Bus interface is sequenced by the array.
The State Sequencer runs only during external bus access. When the State Sequencer is inactive, the
data paths are set up to do a high speed cache read operation. If the J-ll makes an external bus cycle,
the State Sequencer runs and manipulates the P.ioj control logic and Program Memory Bus in order to
perform external bus cycles:
•

Memory input/output

•

Interrupt vector reads

•

General purpose input/output

•

Direct Memory Access arbitration

9.4.4
Cache Data Path
The Cache Data Path is a multifunction gate array that controls the 8 Kbyte direct rnap Cache Memory.
It generates B BUS bits <21:13> as TAG data for the cache write transaction. Parity for the TAG data
is generated, predicted, and checked by the gate array. The gate array also contains the flush address
counter used to clear or flush the cache memory.
The Cache Data Path contains a Cache Control Register which is a shadow copy of the one in the DeJll
(Section 9.4.1.1). It also contains the Clock Register and the Memory System Error Register which are
described in the following sections.
9.4.4.1
Clock Register
The Clock Register, CLKREG, allows software to enable the.50 Hz clock interrupt. The register, located
at 177775468 , has the format as shown in Figure 9-12. Bit <06>, CLOCK ENABLE, is a read/write bit
which, when set, enables the 50 Hz line clock interrupt. This bit is clear on power-up. All other bits are
read-only and are zero.

Figure 9-12

Clock Register

CXO-1171A

9.4.4.2
Memory System Error Register
The Memory System Error Register (MSER) is located at 177777448 , Figure 9-13 shows the format of
the register, and Table 9-6 describes the bits. The entire regis~er is read-only.
This register is cleared by any MSER write reference. It is also cleared on power up or by a console
start (for example, by using Micro-ODT). It is unaffected by a RESET instruction.

9-15

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 9-13

Memory System Error Register

~H~!;IOIOlol~
15

CXQ-1172A

Table 9-6

Memory System Error Register Bit Description

Bits

Description

This bit, PARITY ABORT, is set if a cache or memory parity error aborts an instruction.

14:08

These bits are always O.

This bit, HIGH BYTE PARITY ERROR, is set if Cache Control Register (CCR) bit < 07> is set
and a cache parity error occurs in the high data byte.

This bit, LOW BYTE PARITY ERROR, is set if CCR < 07 > is set and a cache parity error occurs
in the low data byte.

This bit, TAG PARITY ERROR, is set if CCR < 07 > is set and a cache parity error occurs in
the tag field.

07:05

These bits are all set if CCR < 07 > is cleared and any type of cache parity error occurs.

04:00

These bits are always O.

9.4.5
Cache Memory
The Cache Memory is an 8-Kbyte, block size one, direct map (set size one) instruction cache. The
Cache Data Path chip contains the control logic to support the Cache Memory. The Cache Men10ry
is transparent to all programs and is designed with high-speed RAM memory. The memory locations
currently being accessed from Program Memory are automatically stored in the Cache Memory. The
next time these locations are accessed, the data is retrieved from the Cache Memory. This eliminates
the time-consuming Program Memory Bus transaction. Full parity protection is provided for the, Cache
Memory and much of the parity calculations are done by the Cache Data Path chip.
The Cache Memory asserts COMP when an address scores a cache memory hit. NIMISS is asserted
when the address scores a cache memory miss. The memory read/write functions are controlled by the
TAG BUS from the Cache Data Path chip. The data is written into the memory from the A BUS and
read on the B BUS.
Figure 9-14 shows the logical subdivision of the 22-bit physical address.

9-16

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 9-14

Logical Subdivision of a 22-bit Physical Address

[

LABEL

"----- .--..--g

INDEX

~--

21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
II'XO-1173A

Figure 9-15 shows the organization of each 29-bit cache entry.

Figure 9-15

Organization of each 29-bit Cache Entry

_____TA__G
_____________
28

~
18

~______.____:y_Ii__~_____~_~~I____________~_~_~_E
16

CXO-1174A

PO is the odd parity bit for the low data byte; PI is the odd parity bit for the high data byte. P2 stores
even parity for the tag and valid (V) bits.
In operation, the 12 bit index field fronl the physical address is used to access one of the 4-Kword
locations in the cache. Then the 9-bit label field of the physical address is compared with the 9-bit tag
field stored in the cache. If the two fields compare, then the valid bit is checked to contain a one and
the P2 parity bit is checked for correct parity. If these conditions are met, a cache hit is declared and
the data contents of that cache entry are used by the J-l1. If any of these conditions is not met, then a
cache miss is declared and the J-l1 must then access Program Memory.
The response of the cache to various conditions is shown Table 9-7.

9-17

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Table 9-7

Response of the Cache to Various Conditions
CPU Hit

CPU Miss

DMA Hit

DMA Miss

READ

Read cached
data

Read memory
- allocate
cache

Read memory
- no cache
change

WRITE
WORD

Write through
cache to
memory

Write memory
- allocate
cache

Invalidate
cache - update
memory

Update memory
- no cache
change

WRITE
BYTE

Write through
cache to
n1emory

Write memory
- no cache
change

Invalidate
cache - update
memory

Update memory
- no cache
change

READ
BYPASS

Read memory
no cache
change

Read memory
- no cache
change

WRITE
BYPASS

Write memory
- invalidate
cache

Write memory
- no cache
change

READ
FORCE
MISS

Read memory
- no cache
change

WRITE
FORCE
MISS

Write memory
- no cache
change

9.4.6
Direct Memory Access Register
The Direct Memory Access (DMA) Register is written with the address of each DMA write cycle. This
address is n10nitored by the State Sequencer to ensure that the cache data does not become stale. If the
DMA write address is in cache, then that cache entry is invalidated.
The DMA register receives an address from the Program Memory Bus via the A BUS and latches it into
the register when RSYNC is asserted. The address is driven onto the B BUS to check it against the
addresses in the cache memory when DMA REG OE is asserted.
Program Memory Bus Receivers
9.4.7
The P.ioj control logic receives address and data from the Program Memory Bus via six 2908 bus
transceivers as shown in Figure 9-16. The State Sequencer provides the control signals RLE and RL
OE that transfer bus data to the A BUS. The data is latched when RLE is asserted. The output drivers
are then enabled by RL OE, which enables the bus data to the A BUS.
9.4.8
Program Memory Bus Transmitters
The P .ioj control logic transmits address and data to the Program Memory Bus via six 2908 bus
transceivers as shown in Figure 9-17. The address and data inputs are controlled by the LATCH input.
The address is clocked into the transceiver when the STRB input from the DCl11 is asserted. Write data
is clocked into the transceiver when the DCRP input from the State Sequencer is asserted.

9-18

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 9-16

Program Memory Bus Receivers

BDAL

PROGRAM MEMORY
BUS TRANSCEIVER
A BUS

RL E

RX/LCH/EN

RL OE

RXEN
P5

BPOK

BUS INPUT
TRANSCEIVER

RPOK

BSACK

RSACK

BDMR

RDMR

BIRO

RIRO

BDCOK

MINIT

BDOUT

RDOUl

BSYNC

RSYNC

BRPLY

RRPLY
CX-1073J\

The Program Memory control signals are transmitted by the Bus Output Transceivers. The State Sequencer provides most of the handshake protocol with the Program Memory Bus.
9.4.9
Maintenance Register
The Maintenance Register is configured for the J-11 to power up to the bootstrap address of 177730008 ,
This register also causes a trap through vector 0048 after a kernel mode HALT if the Secure/Enable
switch is in the SECURE position. If the switch is in the ENABLE position, a kernel mode HALT causes
the J-11 to enter micro-OOT. The register is located at 177777508 and is read-only. Figure 9-18 shows
the format of the register, and Table 9-8 describes the bits.

9-19

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 9-17

Program Memory Bus Transmitters

PROGRAM MEMORY
BUS TRANSCEIVER

BDAL

B BUS

DRCP

TXCLK

STRB

PMEM BUS OE

RXEN
P5

BUS INPUT
TRANSCEIVER

TDMG

BDGMO

TIAKO

BIAK

TINIT

BINIT

DCOK

BDCOK

TDIN

BDIN

TDOUT

BDOUT

TSYNC

BSYNC

PIOC RE P L Y -

BRPLY

CX-l074A

Figure 9-18

Maintenance Register

CXO-1175A

9-20

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Table 9-8

Maintenance Register Bit Description

Bits

Description

15:08

These bits are always O.

07:04

These bits are always 1. This configuration indicates a J-l1 module design unknown to standard PDP-II operating systems.

This bit, TERMINAL ENABLE, is the inverse of Pio Control and Status Register bit < 15>_
This bit defines the action taken by the J-11 when a HALT instruction is encountered while
in kernel mode. If the bit is a I, a kernel HALT instruction will trap through vector 0048 - If
the bit is a 0, micro-ODT will be entered.

This bit is always 1.

This bit is always O.

When set, POWER OK, this bit indicates that the power supplies hav£> detected that the ac
input power is satisfactory.

9.5 INTERRUPT LOGIC
The Interrupt Logic generates the interrupt and vector address to the DCJll (located on the left side of
Figure 9-2). Table 9-9 shows the interrupt and trap vectors that are assigned in the J-ll pjoj. Notice
that the Control Bus can software interrupt on level 7 through 4 (Section 9.15.4 and Chapter 3).

Table 9-9

Interrupt and Trap Vectors for 1-11 P.ioj

Trap
Vector
Address

Interrupt
Level

Function
(reserved)

000
004

Non-maskable

Bus error (non-existent memory)

010

None

Illegal and reserved instruction

014

Non-maskable

BPT, breakpoint trap used for HSC ODT

020

Non-maskable

lOT, input/output trap used for HSC software inconsistency

024

Non-maskable

Power fail

030

Non-maskable

EMT, emulator trap used for system service calls

034

Non-rnaskable

TRAP instruction

060

4 (1)

Console Terminal Receiver

064

4 (2)

Console Terminal Transmitter

100

Line Clock

9-21

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Table 9-9 (Cont.)

Interrupt and Trap Vectors for J-ll P.ioj

Trap
Vector
Address

Interrupt
Level

Function

114

Non-maskable

Parity error on read-from-memory

120

4 (7)

Control Bus interrupt, level 4

124

Control Bus interrupt, levelS

130

Control Bus interrupt, level 6

134

Control Bus interrupt, level 7

230

4 *

K.rx interrupt

240

7 to 1

Programmable interrupt request

250

Non-maskable

MMU abort

300

4 (3)

Auxiliary Serial Port 1 Receiver

304

4 (4)

Auxiliary Serial Port 1 Transmitter

310

4 (5)

Auxiliary Serial Port 2 Receiver

314

4 (6)

Auxiliary Serial Port 2 Transmitter

Note that the numbers in parentheses 0 indicate the order of priority of level 4 interrupts.
* The level 4 interrupt generated on the Program Bus is the lowest priority level 4 interrupt. All level 4
interrupts generated within the P.ioj module have higher priority than any off the module.

9.6 BOOTSTRAP PROM
The bootstrap PROM contains two Kwords in two lK pages (shown in the upper-right corner of Figure 9-2.) Each page starts at location 177730008 and extends through 177767768 . The BOOT PAGE 2
bit in the Pio Control and Status Register determines which page is active. (Refer to Section 9.10.) The
code contained in this PROM is executed after power-up, a subsystem INIT (from either the host or the
Operator Control Panel), or a software-initiated INIT.
The J-l1 Power Up Mode 2 is hard-wired. This mode causes automatic execution of the bootstrap at
address 177730008 and automatic loading of the Program Status Word with the value 3408 .
9.7 CONSOLE TERMINAL INTERFACE
The Console Terminal Interface provides an interface to the Console Terminal (shown in the upper-right
corner of Figure 9-2.) This interface uses an EIA RS-423 signal-level serial interface. The terminal is used
to perform console functions. Conlmunications between the processor and the operator or field engineer
is via a sequence of ASCII characters which are interpreted by the processor as console commands.
The Console Terminal Interface uses a DL-l1 compatible asynchronous receiver/transmitter DC319 chip.
This interface is a superset of the DL-IID interface. That is, there are four registers, as follows, but with
some additional bits defined:
•

Receiver Status Register (RCSR) 177775608

•

Receiver Data Buffer Register (RB UF) 177775628

9-22

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

•

Transmitter Status Register (XCSR) 177775648

•

Transmitter Data Buffer Register (XBUF) 177775668

Figure 9-19, 9-20, 9-21, and 9-22 shows the format of each register. Table 9-10, 9-11, 9-12, and 9-14
describe the bits for each register.

Figure 9-1.9

Receiver Status Register

1oTo~~1oTo~~~~-~-1."-0-]

Lf~l~LL~T:.l~~
15

cxo- 176A

Table 9-10

Receiver Status Register Bit Description

Bit

Description

When set, this bit indicates a terminal is connected to this interface. This bit, DEVICE PRESENT,
is a read-only bit. This line is RS-232-C/RS-423 compatible.

When set, this bit indicates that a character is currently being received. This bit, RECEIVER
ACTIVE, is a read-only bit.

When set, this bit indicates that there is a character in RBUF to be read. This bit, RECEIVER
READY, isa read-only bit.

When set, this bit causes an interrupt to be generated on the assertion of RCV RDY. This bit,
RECEIVER INTERRUPT ENABLE, is a read/write bit. Note that setting this bit when RCV RDY
is already asserted will cause an interrupt.

Figure 9-20

Receiver Data Buffer Register

I:;~I I I I
~.....L'~~

IERRIOVR FRM

ERR ERR

RECEIVED
DATA

_ _ _ _ _ _ _

--]

00
CXO-1177A

9-23

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Table 9-11

Receiver Data Buffer Register Bit Description

Bits

Description

This bit is the inclusive-OR of OVERRUN ERROR and FRAMING ERROR. This bit, ERROR,
is a read-only bit.

When set, this bit indicates that the receiver attempted to set bit 07 in RCSR when it was
already set. In other words, a new character was received and the preceding character had
not yet been read by the J-11.

When set, this bit indicates no stop bit was received. This bit, FRAMING ERROR, is a readonly bit.

When set, this bit indicates the serial-in signal went from a mark to a space condition for 11
bit times after serial reception started. This bit, RECEIVED BREAK, is a read-only bit.

07:00

These eight bits are the character just received. These bits, RECEIVED DATA, are read-only
bits.

Note that there is no Parity Error bit implemented in this register. Parity is not checked or generated on
any of the serial interfaces.

Figure 9-21 Transmitter Status Register

1oT~~I010~~;-r;;;r~;;r;;;]
~~~~~~~~~
15

CXQ-1178A

Table 9-12 Transmitter Status Register Bit Description
Bits

Description

When set, this bit indicates that XBUF can accept a character for transmission. This bit,
TRANSMITTER READY, is a read-only bit.

When set, this bit causes an interrupt to be generated on the assertion of XMT RDY. Note that
setting this bit when XMT RDY is already set will cause an interrupt to be generated. This bit,
TRANSMITTER INTERRUPT ENABLE, is a read/write bit.

05:03

When enabled by PBR ENA, bit < 01> in this register, these bits select the baud rate for the
serial port as shown in Table 9-13.

9-24

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Table 9-12 (Cont.)

Transmitter Status Register Bit Description

Bits

Description

When set, this bit causes the serial output of the transmitter section tel be connected to the
input of the receiver section. Thus, a character loaded into XBUF can then be read back in
RBUF. This bit, MAINTENANCE, is a read/write bit.

When set, this bit overrides the default (hardware determined) baud rate of the serial port
and allows the Programmable Baud Rate Select bits to determine the baud rate. This bit,
PROGRAMMABLE BAUD RATE ENABLE, is a read/write bit.

When set, this bit causes the transmitter to send a continuous SPACE, which will be detected
by the receiver as a framing error. This bit, BREAK, is a read/write bit.

Table 9-13

Baud Rate Select for a DC319

PBR 2

PBR 1

PBR 0

Baud Rate

300

600

1200

2400

4800

9600

19.2K

38.4K

Figure 9-22 Transmitter Data Buffer Register

---]
15

CXO 1179A

9-25

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Table 9-14 Transmitter Data Buffer Register Bit Description
Bits

Description

07:00

These eight bits are the characters to be transmitted. These bits, TRANSMITTED DATA, are
write-only bits.

Data format for this interface is 8 data bits, no parity, and 1 stop bit.
Vectors for this interface are 0608 for the receiver and 0648 for the transmitter. It interrupts at level 4.
The default baud rate for this port is 9600 baud.
A maintenance feature is included in this interface. If the IN IT button on the Operator Control Panel is
held depressed, any character received from the console keyboard is immediately echoed back to the
terminal. This provides a simple test of the serial line driver and receiver, while bypassing the UART
and associated hardware.
9.8 AUXILIARY SERIAL INTERFACES
There are two additional serial ports provided to the J-11 P .ioj (shown in the upper-right corner of
Figure 9-2). These interfaces are also a superset of the DL-IID. The register set is the same as for the
console terminal. (Refer to Section 9.7.)

The first Auxiliary Serial Port (AUXl) occupies addresses 177775208 - 177775268 and uses 3008 and
3048 for its Receiver and Transmitter vectors, respectively. The second Auxiliary Serial Port (AUX2)
occupies addresses 177775308 - 177775368 and uses 3108 and 3148 for its Receiver and Transmitter
vectors, respectively. Both interfaces interrupt at level 4.
The serial interface is electrically compatible with EIA RS-423 signal levels. It provides for asynchronous,
full duplex communication. Transmit and receive baud rates are the same.
The default baud rate for both Auxiliary Serial Ports is 9600 baud.
1/0 PAGE ADDRESS DECODES
The I/O Page Address Decodes decode the OUT BUS and provide the load strobes and read strobes
for the I/O page addresses. The decode is shown in the left of Figure 9-2.

9.9

9.10 PIO CONTROL AND STATUS REGISTER
The Pia Control and Status Register (PIOCSR) contains bits that control functions on the P .ioj. It also
provides status information.
Figure 9-23 shows the format of the PIOCSR. Table 9-15 describes each bit of the register. Except as
noted in Table 9-15, all bits are read/write and are cleared by TINIT. This register is located at 177700408 .
Figure 9-23

Pio Control and Status Register

~~~fs;Io

EN~ IP LOP LED NMA CNT LCK

~~~~ PG2 CB~ ST TST
15

ENA IE

ENA

CXO-1180A

9-26

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Table 9-15

Pio Control and Status Register Bit Description

Bits

Description

This bit corresponds to the position of the Operator Control Panel Secure/Enable switch. A
one indicates the ENABLE position of the switch (read-only).

This read-only bit is always zero.

13:12

These read/write bits are not used.

This bit allows the software to swap Control Memory banks. When set, it causes the HSC70
Memory Module to select the upper half of the Control Memory DRAMs as the active bank.

This bit allows the software to swap Program Memory banks. When set, it causes the HSC70
Memory Module to swap the addressing ranges between Progranl Memory banks on that module. This bit maximizes the probability that working memory is available starting at address
0000008 for interrupt vectors.

This read/write bit is not used.

This bit determines which page of the Bootstrap PROM is selected. When reset, the first 1
Kwords of the Bootstrap PROM are accessible in the range 177730008 through 177767768 ,
When set, it causes the second 1 Kwords of the Bootstrap PROM to be accessible in the range
177730008 through 177767768 ,

This bit enables the Control Bus Arbitrator. When set, the Control Bus· Arbitrator is enabled
for the nine other Control Bus requesters. When clear, only the P.ioj may access Control
Memory.

This read-only bit is always zero.

This bit is the high-byte parity test. When set, it causes the high byte parity tree to generate
even parity on the next write-cycle to memory, therefore writing incorrect high-byte parity at
that address. The bit is automatically cleared following that write cycle. This function applies
to all three areas of memory (Program, Control, and Data). This bit is abo cleared by TINIT.

This bit is the low-byte parity test. It performs the same function as bit < 05 > for the low
byte.

This bit lights the yellow LED, 05, located near the handle of the P.ioj. It also drives the
STATE indicator located on the Operator Control Panel.

This bit is the non-memory-access enable. When set, it causes the P.ioj to execute a NonMemory Access (NMA) cycle on the next Control Memory or Data Metnory access. This bit
is cleared automatically at the conclusion of that Control or Data Memory access. This bit has
no effect on and is not cleared by Program Memory accesses.

9-27

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Table 9-15 (Cont.)

Pio Control and Status Register Bit Description

Bits

Description

This bit is the Control Memory interrupt enable. When set, it causes the P.ioj to execute an
interrupt cycle on the next Control Memory access. This bit is cleared automatically at the
conclusion of that Control Memory access. Note that if the P.ioj accesses Data Memory with
this bit set, the bit will be cleared after that access with no interrupt generated.

This bit is the Control Memory lock enable. When set, it causes the P.ioj to execute a lock
cycle on the next Control Memory access. This bit is cleared automatically at the conclusion
of that memory access. Note that if the P.ioj accesses Data Memory with this bit set, the bit
will be cleared after that access with no lock cycle generated.

NOTE: A different priority scheme from the F-ll P.ioc implementation has been used for these last
three bits (NMA ENA, CNT IE, and LCK ENA). In this design, setting NMA ENA will cause an NMA
cycle to occur, regardless of the state of the other two bits. However, setting both CNT IE and LCK
ENA simultaneously will generate an illegal cycle code on the Control Bus, providing a mechanism for
diagnostics to check this logic. Under normal circumstances, only one of these three bits should be set
at a time.

9.11 SWITCH/DISPLAY REGISTER
The Switch/Display Register (shown in the lower middle of Figure 9-2) is the interface between the
software and the Operator Control Panel. This read/write is register located at 177700428 ,
Figure 9-24 shows the arrangement of the five switches and indicators on the Operator Control Panel.
Response to operation of these switches is handled entirely by software; no interrupts to the J-11 are
generated by changes of state of the switches (except, of course, for INIT).

Figure 9-24 Indicators and Switches on the Operator Control Panel

INIT SW
IND4

SW 3
a
LAMP
TST
IND 3

~J
~J
~J
~
~
l~
CXO-1181A

The functions of the five panel switches and indicators are defined by software, except as follows:
•

INIT-a momentary push button which, when pushed and released, causes the J-11 to execute
its bootstrap routine.

•

SW 3-a momentary push button which, when pushed, provides a hardware lamp test.

9-28

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

In addition, there is a two-position rocker switch, SECURE/ENABLE. This switch provides three functions:
•

When the switch is in the ENABLE position, a break received from the terminal causes the J-11
to enter ,uODT.

•

If the J-11 is in Kernel mode and HALT instruction is decoded, the state of this switch is
sampled. If the switch is in the ENABLE position, the J-11 enters ,uODT. If the switch is in the
SECURE position, the J-11 executes a trap to location lOs. If the J-11 is in user mode, a HALT

instruction causes a trap to location lOs.
•

In addition, if this switch is in the SECURE position, the IN IT switch is disabled.

Figure 9-25 shows the format of the Switch/Display Register. Table 9-16 describes each bit of the
register. This register must be polled by software to detect changes in the state of the switches.

Figure 9-25 Switch/Display Register

~SERVED
15

NH LMQ
LMP
LMj
LM;
t~MPj
4
3
2
1
0

sw sw sw

DIA C/D I
OK NXM PAR

-,01

CXO-L182A

Table 9-16 Switch/Display Register Bit Description
Bits

Description

15:12

These read-only bits are always zero.

11:08

These read-only bits reflect the state of the corresponding switches on the Operator Control
Panel. Note that no hardware debounce logic is provided; debouncing is done by software.

This bit lights the DIAGNOSTICS TESTING/FAILED LED or the DIAGNOSTICS PASSED
LED. A zero lights the DIAGNOSTICS TESTING/FAILED LED (red) . and a one lights the
DIAGNOSTICS PASSED LED (green). This bit powers up as zero and is set to a one by the
successful completion of the PROM bootstrap diagnostics. The intent of this bit is a simple
visual GO/NO-GO indicator for the P.ioj.

This bit, when set, forces a NXM trap on any Control or Data Memory Hus access.

This bit, when set, inhibits all parity traps, thus enabling examination of any memory location
which has a hard parity error.

04:00

These read/write bits, when set, light the corresponding indicators on the Operator Control
Panel.

Note that the eight writable bits are cleared by TINIT.

9-29

HSC7Q INPUT/OUTPUT CONTROL PROCESSOR MODULE

9.12 K INIT AND STATUS REGISTERS
The K INIT and Status Registers initialize and hold the eight bit status of the:
Host Interface (K.pli)
Disk Data Channel (K.sdi)
Tape Data Channel (K.sti)
Figure 9-26 shows the format of the K INIT Register located at 177700448 , Table 9-17 describes the bits
in the K INIT Register.
Figure 9-26

K INIT Register

IKINIKINIKINIKINIKINIKINIKITIO
KlffiKIN: r : J 0
765432198

K SELECT
<3:0>

]

----

CXQ-1183A

Table 9-17

K INIT Register Bit Description

Bits

Description

15:09
07:06

These bits are backplane slot-specific clear signals. A zero in any bit position clears the
module in the corresponding backplane slot. A one in any bit position negates the clear
to that module and enables it to run. These bits are cleared to zero on power-up or after
a subsystem INIT from the Operator Control Panel, but not on a subsystem INIT from a
host processor. Note that since the P .ioj is considered Requester 0 in the HSC70, there
is no KIN <0>.

08,05,04

These are spare bits.

03:00

These four bits are decoded to select the status of a requester. The codes refer to specific
backplane slots. These bits are written first, and then the Status Register is read to obtain
the status. This implementation provides for 10 requester codes (codes 008 through 118 );
codes 128 through 178 generate a K STATUS byte of 3778 or all ones.

Figure 9-27 shows the format of the Status Register located at 177700468 , Table 9-18 describes the bits
in the Status Register.

Figure 9-27 Status Register

CTEI 111I I~!L__ ~_~!_U_S
0

K<_:__

_____ ]

CXQ-1184A

9-30

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Table 9-18

Status Register Bit Description

Bits

Description

STATUS PARITY - This bit is Status Parity. The Ks supply the parity bit from software (even
or odd). The P.ioj checks the parity with software.

06:00

These bits, K STATUS, are the 7-bit status code returned from each Bus Requester. Note that
if a backplane slot is not occupied, reading the status for that slot will return a status byte of

3778 or all ones.
NOTE
Both the K INIT Register and Status Register are
read/write. However, byte-writes to K INIT Register write all 16 bits of this register.
9.13 ERROR ADDRESS REGISTERS
The Error Address Registers (shown in the middle of Figure 9-2) consist of the Low Error Address and
High Error Address. These two registers catch the full 22-bit physical address on the OUT BUS at the
time a NXM or parity trap occurs. The J-ll could have been addressing the:
Progranl Memory
Control Memory
Data Memory
These registers are frozen by the occurrence of the error and each, independent of the other, remains
frozen until it is read. After being read, each register will resume catching the corresponding portion of
the address. The following are the addresses of the two registers:
Low Error Register - 177700248
High Error Register - 177700268
Figures 9·-28 and 9-29 show the format of these two registers.
9.14 SERIAL NUMBER REGISTER
The 16-bit Serial Number Register provides a unique identifying number for each P.ioj module. (The
Serial Number Register is shown just right of the middle of Figure 9-2.) The serial number is encoded
by adding or removing jumpers on the module. The address of this register is 177700568 ,
Figure 9-28

Low Error Address Register

PhYS_iC_a_l__A_d_d._r_e_ss__<_1__5_:_0_0_>__.________

~J
00

CXQ-1185A.

9-31

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 9-29

High Address Register

E~~o_.S_ _ _

<21:16>J

08 07 06 05

00
CXO-1186A

9.15 CONTROL MEMORY INTERFACE
The Control Memory interface consists of three blocks on:
•

Control Memory Windows

•

Control Bus Interface

•

Control Bus Arbitrator and Timing

The following sections describe these three blocks which are shown at the right side of Figure 9-2.
9.15.1
Control Memory Windows
The software has very little need to access Data Memory because the Ks load and unload data buffers.
But the software needs to access many different control blocks scattered through Control Memory. In
addition to the standard MMU, there is a need for a separate address relocation feature for Control
Memory. A large number of page address relocation registers are needed, but page descriptor registers
are not necessary.
The Control Window feature provides 1024 Window Address Registers (WADRs). They are used whenever there is a virtual address in the range 16xxxx8'
NOTE
Throughout the discussion of Control Window Logic,
a 16-bit address is used for ease in explanation.
However, the MMU in the DC}11 translates this 16bit address to a 22-bit address before gating it to
the B BUS.
Whenever an address is in the 16xxxx8 range:
•

The hardware activates the Control Window logic

•

The appropriate Window Address Register is gated (along with part of the virtual address) to
the Control Memory Address (CADR) lines

•

The Control Bus is requested

•

Control Memory is accessed

The software can still use the MMU to access Control memory, but this is rarely done.
The software can load and unload the WADRs by using I/O Page addresses.
All of the hardware for this feature resides on the P .ioj module and consists of the following:
•

1024 W ADRs contained in a 1K x 16 RAM

•

WINDR 1700208 - Window Index Register

9-32

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

•

WBUSR 1700228 - Hi Order Address History Register

•

LOCADR 1700548 - Lo Order Address History Register

The WADRs are the actual page address registers. The WINDR is a index register used as part of the
WADR 1--of-l024 selection. The WBUSR and LOCADR are history registers that h~)ld the address of the
last Control Memory access for error recovery and diagnostic purposes.
9.15.1.1
Control Memory Window Address Selection
The software uses the Control Memory window logic to change a 16-bit PDP-II address into a 17-bit
Control Memory address. This 17-bit address then points to a control block in Control Memory. Control
blocks start on a double-word boundary and the address represents an offset frOlt1 the start of Control
Memory measured in increments of double words.
To change the 16-bit address to a 17-bit address the software performs the following four steps:
•

Selects a window set

•

Writes a double-word offset address into a WADR

•

Reads back a virtual address

•

Uses the virtual address to address Control Memory

Figure 9-30 is a sample PDP-II macro program that shows the steps involved in changing the 16-bit
address to a 17-bit address using the WINDR and WADR. The following describes the steps:

Figure 9-30 WAD R Addressing
012767 000005 170020

MOV 0

#5,$WINDR

016767 100000 170006
016700 170006

MOV ~
MOV ~

DBPTR,$WADR3 ;MOV the double word offset to WADR3
$WADR3,RO
;get the virtual address in RO

011002

MOV ~

(RO),R2

;select window set #5 using the
;window index register

;get the contents of Control Memory
; and put it in R2

CXQ-1269A

9-33

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

The first MOV writes a 5 in the WINDR which selects window set number 5 out of a possible
128 sets. Figure 9-31 shows how the 1 Kword by 16-bit RAM is divided into 128 window sets
of eight WADRs.
The WINDR is loaded once prior to using a window set.

The third MOV reads back a sort of virtual address frOIn WADR3. The low order seven bits
of the WADR3 are shifted left two places and gated onto the IN BUS as shown in the middle
portion of Figure 9-32. The lIO page address is 1700068 , Table 9-19 shows the register address
of each WADR and the virtual 110 page address range each covers.

The fourth MOV uses the sort of virtual address obtained from step 3 above to actually address
Control Memory. When the Control Window Logic is activated (by a virtual address in the
16Zxxx8 range), the high order nine bits of the WADR are shifted left one place and gated onto
the CADR lines as shown in the bottom portion of Figure 9-32.
NOTE
The Z in the virtual address 16Zxxx8 is the
WADR register.

Table 9-19

110 Page Address of Window Address Registers

1/0 Page Address

WADRO

170000

160000-160777

WADR1

170002

161000-161777

WADR2

170004

162000-162777

WADR3

170006

163000-163777

WADR4

170010

164000-164777

WADR5

170012

165000-165777

WADR6

170014

166000-166777

WADR7

170016

167000-167777

9-34

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 9-31 Window Address Register Selection

WINDOW SET 5 WADR 3

0 0 0 W W W

I WINDP

~
----------~
10F128

WADR1
16ZXXX

VI RTUAL ADDRESS

1700YY

I/O PACJE ADDRESS

WADR2
WADR 3
WADR 4

... 1 OF 8

WADR 5
WADR6
WADR 7

~---------y~-------~
1KW X 16-BIT RAM

CX-423B

9-35

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 9-32

WADR Gating

SOURCE
WADR INPUT
LOADING WADR BY
INSTRUCTION VIA
I/O PAGE ADDRESS
1700XX
WADR

WADR
WADR OUTPUT
ACCESSING WADR BY
INSTRUCTION VIA
I/O PAGE ADDRESS
1700XX
DEST

WADR
WADR OUTPUT
USED BY CWLOGIC
CAUSED BY VA
16ZXXX
CADR
CX-422A

9.15.1.2
Control Window Example
The following example selVes to illustrate the use of a Control Window. Refer to Figure 9-33.
1.

A control block is set aside in Control Memory by the P.ioj. The starting address of this control
block is designated by a 16-bit pointer that represents the offset (in increments of double words)
from the start of control memory.
In this example, the pointer is 0004108 or an offset of 4108 double words from the start of
Control Memory. Such an offset corresponds to Control Memory address 0010208 , assuming
word addressing starts at 0000008 . (An MMU access of the same address would use the physical
22-bit, byte-oriented address 160020408 .)

The software selects one of the WADRs to use. In this case, it chose window set 5, WADR3.

9-36

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 9-33

Control Window Example

BYTE DESIGNATOR
WORD DESIGNATOR

------------"l

WADR

DOUBLE WORD DESIGNATOR

17 16 15 14 13 12 11 10 9

o 0

I"__ ~

000

.r •
I

•

IN BUS

'---y-----/ '-y------J

Ii)
WADR

10 0 0

1!1

~,---~~--------

m
A

r
CADR

-1-

, . ,tpi

em
WBUSR

r • ,r r ,r •r

r .r

•

r r ,

ID
LOCADR

o 0

CX-1075A

9-37

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

For selection of window set 5, the software deposits a 58 in WINDR.

The software then deposits the pointer 0004108 into WADR3.

WADR3 contains a pointer 000410s .
The software retrieves the contents of WADR3 with a standard PDP-II instruction.
WADR contents are gated as follows:

Zeros are gated onto IN BUS < 01:00 >, forcing a double word boundary.

Bits < 06:00 > of the WADR are gated onto IN BUS < 08:02 >. These bits shift left two
places, aligning the low-order bit of the pointer with a double-word designation.

011 2 is gated onto IN BUS <11:09> because this is WADR3.

11102 is gated onto IN BUS <15:12> because a WADR was addressed and creates
16xxxxx8'

to this base address. For instance, to examine the third byte (low-order byte of the
second word), software adds two to the virtual address.
The virtual address then contains 1630422 , used by the software as the virtual address
in a PDP-II instruction. Because the hardware sees the virtual address in the 16xxxxs
range, the window logic is activated which forces use of the Control Bus. As a result,
the hardware:
~

Sees 16xxxxs and activates the Control Window.

Sees xx3xxxs and selects WADR3. (WINDR still selects window set 5.)

Gates WADR3 < 15:07> onto CADR < 16:08>.

iD]

Gates virtual address < 08:01> onto CADR < 07:00 >.

CADR <16:01> is captured in WBUSR <15:00>.

m CADR < 00 > is captured in LOCADR < 00 >.
9.15.1.3
Control Window Limitation
One limitation is placed on the Control Window feature. If the software is sequentially accessing information from a control block and it crosses a 1000s byte address boundary, the new address would
have incremented the Z in virtual address 16Zxxxs. This would result in selecting a different WADR. So
there is a 1000s byte address boundary limitation. This limits the maximum size of a control block to
512 bytes assuming it starts at a 1000s boundary; less if it starts at other than a 1000s boundary.

9-38

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

9.15.2
Control Bus Interface
The Control Bus Interface block (located on the right side of Figure 9-2) contains the Control Bus Data
Transceivers and Control Bus Address Transceivers for the P .ioj.
9.15.2.1
Control Bus Data Transceivers
The Control Bus Data Transmitter is 20 bits long:

•

< 15:00> is data

•

Bit 16 is low byte parity

•

Bit 17 is high byte parity

•

Low byte write enable (CWRTL)

•

High byte write enable (CWRTH)

The transmitters are written from the OUT BUS at TDOUT time if the address is between 1600008 and
1677778 .
The Control Bus Data Receiver is 18 bits long:

•

< 15:00 > is data

•

Bit 16 is low byte parity

•

Bit 17 is high byte parity

The receivers are written onto the IN BUS < 15:00 > at TDIN time if the addres'; is between 1600008
and 1677778 .
9.15.2.2
Control Memory Address Transceivers
The Control Memory Address Transceiver (CADR) address inputs are controlled by the Control Memory
Window logic (Section 9.15.1).
The Control Memory Address Receivers are two read-only registers:
•

Window Bus Register (WBUSR) - 1700228

•

Low Control Memory Address Register (LOCADR) - 1700548

These two registers provide access to the address asserted on the Control Bus on each P joj cycle. They
are updated after each Control Bus cycle by the pjoj.
The Window Bus Register contains the high-order 16 bits of the 17-bit word addrt,ss.
Figure 9-34 shows the fonnat of the Low Control Memory Address Register. Table 9-20 describes the
bits in this register.

Figure 9-34

Low Control Memory Address Register

CXQ-1187A

9-39

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Table 9-20 Low Control Memory Address Register Bit Description
Bits

Description

15:04

These bits are always O.

03:01

These bits, CCYCLE < 2:0 >, are the cycle code bits corresponding to the last P.ioj Control
Memory cycle.

This bit, CONTROL BUS ADDRESS < 00 >, is the least significant word address bit of the
last P.ioj Control Memory cycle.

9.15.3
Control Bus Arbitrator and Timing
The P.ioj module contains the timing and arbitration logic for the Control Bus (located in the lower
middle of Figure 9-2). For signal polarities and information about this bus, refer to Chapter 3.
The J-ll P.ioj does not use any backplane pins to generate and receive the CREQUEST and CGRANT
signals, as in the F-ll implementation. Instead, the J-ll P.ioj CREQUEST andCGRANT signals are
contained entirely within the module and the extra backplane fingers are redefined to add two additional
Control Bus Requesters. The new requesters are 8 and 9, which are higher priority than the original
eight. The P .ioj is the lowest priority Control Bus requester.
The Control Memory consists of dynamic RAMs (DRAMs) which must be refreshed. To do this, the
P.ioj generates an internal 66.7 KHz (15 ,usecond period) clock to indicate when a refresh cycle is to be
performed. This signal is input to the Control Bus Arbitrator as the highest priority Control Bus request.
The arbitrator acknowledges the refresh cycle by the asserting CREFR GRANT on the next available
Control Bus cycle, with the same timing as any of the CGRANT n signals. The Control Memory logic
thus uses the assertion of CREFR GRANT to initiate an internal refresh cycle.
NOTE
Refreshing is independent of the ENACBS bit in the
PIOCSR.
9.15.4
Interrupt Cycle
To execute a Control Bus Interrupt cycle, it is only necessary to set the CNT IE bit in PIOCSR and then
MOV the Interrupt Mask to ANY Control Memory address, using either the Control Menl0ry Windows
or Memory Management. A one in any bit position will queue an interrupt at that level to the P.ioj.
Interrupts on more than one level may be generated by one Control Bus Interrupt cycle. The CNT IE bit
will be cleared at the completion of the Interrupt cycle. Figure 9-35 shows the format of the Interrupt
Mask.

Figure 9-35

P .ioj Control Bus Interrupt Mask

CXO-1188A

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

9.15.5
Lock Cycle
To execute a Control Bus Lock cycle, it is only necessary to set the LCK ENA bit in PIOCSR and then
MOV the desired Lock Address to any destination where it may be examined to determine if the location
is already locked. At the completion of the Lock cycle, the LCK ENA bit in PIOCSR is automatically
cleared.
9.16 DATA MEMORY INTERFACE
The Data Memory Interface consists of two blocks of logic shown in the lower right of Figure 9-2:
•

Data Bus Interface

•

Data Bus Arbitrator and Timing

The P.ioj module contains the timing and arbitration logic for the Data Bus. In addition, the P.ioj is the
lowest priority requester. The following sections describe the Data Memory intertace logic.
9.16.1
Data Bus Interface
The Data Bus Interface block contains the Data Bus Data Transceivers and the Data Bus Address
Transceivers for the P.ioj. The following sections describe these two transceivers.
9.16.1.1

Data Bus Transceivers

The Data Bus Data Transmitter is 20 bits long:

•

< 15:00 > is data

•

Bit 16 is low byte parity

•

Bit 17 is high byte parity

•

Low byte write enable (DWRTL)

•

High byte write enable (DWRTH)

The transmitters are written from the OUT BUS at TDOUT time if the address is between 140000008
and 157777778 ,
The Data Bus Data Receiver is 18 bits long:

•

< 15:00 > is data

•

Bit 16 is low byte parity

•

Bit 17 is high byte parity

The receivers are written onto the IN BUS < 15:00> at TDIN time if the address is between 140000008
and 157777778 .
9.16.1.2
Data Bus Address Transceivers
The Data Bus deals with word addresses and has 18 address bits. This 18-bit address is handled
differently in the Data Bus Address Transmitters than in the Data Bus Address Receivers.
9.16.1.2.1
Data Bus Address Transmitters
The address on the OUT BUS < 18:01 > is clocked into the Data Bus Address Transmitters < 17:00 >
when the address is between 140000008 and 157777778 , Notice the shift of one bit to the right to make
the address a word reference.

9-41

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

9.16.1.2.2
Data Bus Address Receivers
The Data Bus Address Receivers are two read-only registers:
•

High Data Bus Address Register (HIDADR) located at 177700528

•

Low Data Bus Address Register (LODADR) located at 177700508

After each Data Bus cycle by the P.ioj, the registers are updated with the 18-bit word address. Figure 9-36
shows the format of the two receiver registers.

Figure 9-36

Data Bus Address Transceivers

HIDADR

0,_S_~_ _ _ t<17:1~

[ _______
15

08 07

03 02 01 00

LODADR

o_o_>_~

[ ______
Da_t_a__B_u_S_Ad_d_.r_e_s_s_<_1_4_:

08 07

01 00

CXO-1189A

9.16.2
Data Bus Arbitrator and Timing
The P.ioj module contains the timing and arbitration logic for the Data Bus. For signal polarities and
information about this bus, refer to Chapter 3.
The J-ll P.ioj does not use backplane pins to generate and receive the DREQUEST and DGRANT
signals, as in the F-ll implementation. Instead, the J-ll P.ioj DREQUEST and DGRANT signals are
contained entirely within the module, and the extra backplane fingers are redefined to add two additional
Data Bus Requesters. The new requesters are 8 and 9 (higher priority than the original eight). The P.ioj
has the lowest priority Data Bus requester.
9.17 I/O PAGE ADDRESS UTILIZATION
Table 9-21 is a list of the I/O page addresses assigned in the P.ioj.

9-42

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

1/0 PAGE REGISTER FORMAT SUMMARY
Figure 9-37 is a summary of the 110 page registers on the P.ioj.

9.18

Table 9-21

110 Page Address Utilization

Physical Address

Function

17777776

Processor Status Word

17777772

Program Interrupt Request Register

17777766

CPU Error Register

17777752
17777750
17777746
17777744

Cache Hit/Miss Register
Maintenance Register
Cache Control Register
Memory System Error Register

17777676
17777674
17777672
17777670
17777666
17777664
17777662
17777660

User Data PAR 7
User Data PAR 6
User Data PAR 5
User Data PAR 4
User Data PAR 3
User Data PAR 2
User Data PAR 1
User Data PAR 0

17777656
17777654
17777652
17777650
17777646
17777644
17777642
17777640

User Instruction PAR 7
User Instruction PAR 6
User Instruction PAR 5
User Instruction PAR 4
User Instruction PAR 3
User Instruction PAR 2
User Instruction PAR 1
User Instruction PAR 0

17777636
17777634
17777632
17777630
17777626
17777624
17777622
17777620

User Data PDR 7
User Data PDR 6
User Data PDR 5
User Data PDR 4
User Data PDR 3
User Data PDR 2
User Data PDR 1
User Data PDR 0

17777616
17777614
17777612
17777610
17777606
17777604
17777602
17777600

User Instruction PDR 7
User Instruction PDR 6
User Instruction PDR 5
User Instruction PDR 4
User Instruction PDR 3
User Instruction PDR 2
User Instruction PDR 1
User Instruction PDR 0

9-43

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Table 9-21 (Cont.)

110 Page Address Utilization

Physical Address

Function

17777576
17777574
17777572

Memory Management Status Register 2
Memory Management Status Register 2
Memory Management Status Register 0

17777566
17777564
17777562
17777560

Console Xmtr Data Buffer Register
Console Xmtr Status Register
Console Rcvr Data Buffer Register
Console Rcvr Status Register

17777546

Clock Register

17777536
17777534
17777532
17777530

Aux Serial Port 2 Xmtr Data Buffer Register
Aux Serial Port 2 Xmtr Status Register
Aux Serial Port 2 Rcvr Data Buffer Register
Aux Serial Port 2 Rcvr Status Register

17777526
17777524
17777522
17777520

Aux Serial Port 1 Rcvr Status Register
Aux Serial Port '1 Xmtr Data Buffer Register
Aux Serial Port 1 Xmtr Status Register
Aux Serial Port 1 Rcvr Data Buffer Register
Aux Serial Port 1 Rcvr Status Register

17777400
17777402
17777404
17777406

Command/Status Register
Memory Address Register 0
Memory Address Register 1
Memory Address Register 2
Memory Address Register 3

17776776 }
Bootstrap PROM (both pages)

17773000
17772516

Memory Management Status Register 3

17772376
17772374
17772372
17772370
17772366
17772364
17772362
17772360

Kernel Data PAR 7
Kernel Data PAR 6
Kernel Data PAR 5
Kernel Data PAR 4
Kernel Data PAR 3
Kernel Data PAR 2
Kernel Data PAR 1
Kernel Data PAR 0

9-44

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Table 9-21 (Cont.)

110 Page Address Utilizati0!l_ _ _ _ _ _ _ _ _ __

Physical Address

Function

17772356
17772354
17772352
17772350
17772346
17772344
17772342
17772340

Kernel Instruction PAR 7
Kernel Instruction PAR
Kernel Instruction PAR
Kernel Instruction PAR
Kernel Instruction PAR
Kernel Instruction PAR
Kernel Instruction PAR
Kernel Instruction PAR

17772336
17772334
17772332
17772330
17772326
17772324
17772322
17772320

Kernel Data PDR 7
Kernel Data PDR 6
Kernel Data PDR 5
Kernel Data PDR 4
Kernel Data PDR 3
Kernel Data PDR 2
Kernel Data PDR 1
Kernel Data PDR 0

17772316
17772314
17772312
17772310
17772306
17772304
17772302
17772300

Kernel Instruction PDR 7
Kernel Instruction PDR 6
Kernel Instruction PDR 5
Kernel Instruction PDR 4
Kernel Instruction PDR 3
Kernel Instruction PDR 2
Kernel Instruction PDR 1
Kernel Instruction PDR 0

17772276
17772274
17772272
17772270
17772266
17772264
17772262
17772260

Supervisor Data PAR 7
Supervisor Data PAR 6
Supervisor Data PAR 5
Supervisor Data PAR 4
Supervisor Data PAR 3
Supervisor Data PAR 2
Supervisor Data PAR 1
Supervisor Data PAR 0

17772256
17772254
17772252
17772250
17772246
17772244
17772242
17772240

Supervisor Instruction PAR 7
Supervisor Instruction PAR 6
Supervisor Instruction PAR 5
Supervisor Instruction PAR 4
Supervisor Instruction PAR 3
Supervisor Instruction PAR 2
Supervisor Instruction PAR 1
Supervisor Instruction PAR 0

9-45

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Table 9-21 (Cont.)

1/0 Page Address Utilization

Physical Address

Function

17772236
17772234
17772232
17772230
17772226
17772224
17772222
17772220

Supervisor Data PDR 7
Supervisor Data PDR 6
Supervisor Data PDR 5
Supervisor Data PDR 4
Supervisor Data PDR 3
Supervisor Data PDR 2
Supervisor Data PDR 1
Supervisor Data PDR 0

17772216
17772214
17772212
17772210
17772206
17772204
17772202
17772200

Supervisor Instruction PDR 7
Supervisor Instruction PDR 6
Supervisor Instruction PDR 5
Supervisor Instruction PDR 4
Supervisor Instruction PDR 3
Supervisor Instruction PDR 2
Supervisor Instruction PDR 1
Supervisor Instruction PDR 0

17770056

Serial Number Register

17770054

Control Memory Low Address Register

17770052
17770050

Data Memory High Address Register
Data Memory Low Address Register

17770046
17770044

K Status Register
K Init Register

17770042

Switch/Display Register

17770040

Pia Control and Status Register

17770026
17770024

High Error Address Register
Low Error Address Register

17770022
17770020
17770016
17770014
17770012
17770010
17770006
17770004
17770002
17770000

17767776
17760000

}

Control Memory Windows

9-46

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 9-37 110 Page Register Format Summary
WADR n

(17 770 000 - 016)

(Write)

C
15

DOUBLE-WORD POINTER
(HIGH 16 BITS OF 17-BIT WORD ADDRESS)

,---------

(READ)
512 BYTE OFFSET = ADDRESS ~~
LOW-ORDER WORD OF DOUBLE WO~D ~

(0 - 7)

15
WINDR

WBUSR

---J

(17 770 020)

I I I I~ I IO~

WINDOW INDEX
(000 - 177 (8»_.
06

(17 770 022)
DOUBLE-WORD POINTER OF
LAST CONTROL MEMORY REFERENCE

LOEADR

(17 770 024)
PHYSICAL ADDRESS
<15:00>

_ _ _ _ _ _ _ _
I...---

---J
01

CXQ-1190A
SHEET 1 OF 7

(Continued on next page)
9-47

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 9-37 (Cont.)

110 Page Register Format Summary

HIEADR

(17 770 026)

~YS;;~~l!~DRES~~

I 0 I 0 I 0 I 0 I 0 I 0
15

PIOCSR

SWP SWP
BRD BNK ~~

(17 770 042)
RESERVED

rili
I~

L - -_ _ _ _ _...... ,

KINR

~o HIP
LoplLEDINMA CNTILCKI
TST TST
ENA IE ENA

(17 770 040)

TRM
ENA

SWDR

w3 SW2

w SW]1IAC/D INH LMPILMPILMPILMPILMPI
lOOK

NXM PAR

(17 770 044)

KIN KIN KIN KIN KINIKIN~~ SELECTI
7 6 5 4 3
2 L-=--L~~~ <3:0> ~
15

I 0 I 0 I 0 I 0 I I I T N_ _ _
S _

KSTR

(17 770 046)

K<~~~;U

CXO-1190A
SHEET 2 OF 7

(Continued on next page)

9-48

HSC70 INPUT/OUTPUT CONTROL P·ROCESSOR MODULE

Figure 9-37 (Cont.)

110 Page Register Format Summary

LODADR

(17 770 050)

~
B_U_S._A_D_D_R_E_S.S__________________ -T~
_ ____~____________DA_T_A__
<14:00>
U
15

HIDADR

(17 770 052)

LOCADR

(17 770 054)

I I I I lor] I°HTIo~~;__
;~;E 1~
0

T~G
15

(17 770 056)
16 BIT
SERIAL NUMBER
14

551e541~531 e;2 51 1e501

INTR DIS PAR BUSY MOTR DRV CS7 CS6 C
ENB REQ TST LED ENB SEL

NXM
ERR

15
READ
ONLY

14
13
READ I
ONLY

Command/Status Register (CSR) (17777400)
PAR
ERR

09
08 07
READ/WRI TE

I
CXO-1190A
SHEET 3 OF 7

(Continued on next page)
9-49

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 9-37 (Cont.)

1/0 Page Register Format Summary

MEMORY ADDRESS REGISTER 0 (MARO) ~RACK REGISTER (TREG) (17777402)
IA07 IA06 lAOS IA041A031A02
15

IA01~

09
08 07
READ/WRITE

ADDR~

CURRENT TRACK
06

00
1

MEMORY ADDRESS REGISTER 1 (MARl) ~ECTOR REGISTER (SREG) (17777404)
A15

A14

A13

A12 All A10

IA09~

09
08 07
READ/WRITE

DESIRED SECTOR ADDRESS
06

00
1

(17777406)
MEMORY ADDRESS REGISTER 2 (MAR2)rlATA/TRACK REGISTER (DREG)
GRN
LED

DMA
TST

A21

(17 777 520)
(17 777 530)
(17 777 560)

I~~~I

I
12

DISK DATA OR

DESIRED TRACK ADDRESS

I~~~I

08 07
09
READ/WRITE

IT I~g*n°
09

---------------------1

I
03

r:J
00

(17 777 522)
(17 777 532)
(17 777 562)

ERR OVR FRM
ERR ERR

A16

----

AUXl RCSR
AUX2 RCSR
TERM RCSR

AUXl RBUF
AUX2 RBUF
TERM RBUF

A2 °IA191A18 IA17

:;~
11

I ITL____ g_!_~_~E_D J
0

R_E__

_____

CXO-1190A
SHEET 4 OF 7

(Continued on next page)

9-50

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 9-37 (Cont.)

1/0 Page Register Format Summary
(17 777 524)
(17 777 534)
(17 777 564)

AUX1 XCSR
AUX2 XCSR
TERM XCSR

(17 777 526)
(17 777 536)
(17 777 566)

AUX1 XBUF
AUX2 XBUF
TERM XBUF

I I I I I I I IOL
0

CLKREG

----]

TRANSMITTED
DATA

(17 777 546)

I ° I° I° I° I~ITflfi:E[~ ~I~
15

MSER

(17 777 744)

I~~I ° I° I° I° I°IT I~!RI~~R ~!; ill ~I:J
15

CACHE CONTROL REG

(17 777 746)

I~ I° I° I° I IWRW~~~~;-rD;A-g
0

.TPR~~~~~MDE~
10

CXQ-1190A
SHEET 5 OF 7

(Continued on next page)

9-51

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 9-37 (Cont.)

1/0 Page Register Format Summary

MAINT REG

(17 777 750)

HIT/MISS REG

CPU ERR

(17 777 752)

(17 777 766)

I I I I I~ I~~il:~: i~ol~*~~1 IJ
0

PIRQ REG

NXM

PDR

(17 777 772)

PIR PIR PIR PIR PIR PIR
6
5
4
3
2
7
15

~~~~ORITY

~~~~:091
09

Iol
.U
01

(GENERAL)

BYP
CCH

~~---------------------

p~o
0 IEXPIACC CT~EJ
WRT
DIR FIELD

PAGE LENGTH FIELD

CXO-1190A
SHEET 6 OF 7

(Continued on next page)

9-52

HSC70 INPUT/OUTPUT CONTROL PROCESSOR MODULE

Figure 9-37 (Cant.)

PAR

110 Page Register Format Summary

(GENERAL)
PAGE ADDRESS FIELD
16

CXO-1190A

SHEET 7 OF 7

9-53

HSC50 MEMORY MODULE

CHAPTER 10
HSC50 MEMORY MODULE

10.1 INTRODUCTION
The HSC50 Memory Module (M.std) is an extended-hex size module residing in slot two of the HSC50,
adjacent to the F-11 I/O Control Processor Module (P.ioc). The module number, LOI06, is stamped on
the handle. The M.std contains three separate and independent memories, each on its own bus. The
three memories are:
•

Control Memory or M.ctl (residing on the Control Bus)

•

Data Memory or M.data (residing on the Data Bus)

•

Program Memory or M. prog (residing on the Program Bus)

Each of the memory arrays includes byte parity.
Refer to Figure 10-1 for a block diagram of the M.std olodule and its three basic components.
The three memories each use different RAM types and quantities as shown in Table 10-1.

Table 10-1

Size of Memor,Y and TYEe of RAMs

Memory

Size

M.ctl

Number
Of Chips

Type Of Chips

Access Time

128 Kbytes
64 Kwords

64KX1 Dynamic RAMs

150 nanoseconds

M.data

128 Kbytes
64 Kwords

16KX1 Static RAMs

70 nanoseconds

M.prog

256 Kbytes
128 Kwords

64KX1 Dynamic RAMs

150 nanoseconds

NOTE
The HSC50 was originally designed to accept more
than one memory module and the memory module
was designed to permit different configurations of
memory size. However, at present,the HSC50 uses
only a single memory module with the configurations shown in Table 10-1.

10-1

HSC50 MEMORY MODULE

Figure 10-1

HSCSO Memory Module Block Diagram

CONTROL BUS

~
~~
MEMORY MODULE (L0106)

~/
M.ctl

M.prog

I
\

\
/

PROGRAM MEMORY
256 KBYTES

CONTROL MEMORY
128 KBYTES

en
co

::)

0::

(!)

0
0::
a..

M.data

DATA MEMORY
128 KBYTES

""
A~.7

t>..

DATA BUS

CX-954A

10.2 STATUS LED
The yellow LED on the Memory Module indicates memory activity. It lights on every memory cycle to
Control, Data, or Program Memory. The LED becomes brighter with increased memory activity.
10.3 CONTROL MEMORY
Control Memory, which resides on the Control Bus, performs a read or write cycle as determined
by the requestor that has been granted the Control Bus for that cycle. To ensure data retention of the
dynamic RAMs, Control Memory also performs refresh cycles once every 15 microseconds. It is logically
organized as one bank that is 18-bits wide (16 data bits and 2 parity bits) and 64 Kwords deep.
Figure 10-2 is a block diagram of Control Memory. The following sections describe each block in the
diagram.

10-2

HSC50 MEMORY MODULE

Figure 10-2

CADR <15:00>

Control Memory Block Diagram

-l\

CMT1 5""!
CM REF CYC

RAS/CAS
MUX

CM AMUX <7:0>

-P02

.....
CMT5 0 -

8-BIT
REFRESH
ADDRESS
COUNTER

128 KBYTES

r---

CONTROL
MEMORY
ARRAY

P02

CADR <16:> -

SELECT
LOGIC

EIGHTEEN
64KXl
DYNAMIC RAMS

f-- CM SEL

P03
CTIMIN GCWRT H CWRT L CREFR GRAN TCM SE L-

TIMING
LOGIC

I--f---f---I---

RAM
DRIVER

RAS
CAS
WREN

-vvv
.AAA

POl
I-- CM T15

r--- CM REF CYC

I-- CM T50

P01 I - CM RD CYC

CDATA <15:00

>~
--V DATA

CM <15:00>, LP, HP IN

..'\
I
v

CM <15:00>
LP, HP OUT
DIN

DOUT

'"'\
I

CDATA HP - RECEIVERS
CDATA LP -

P04 CM RD CYC-

P02

DATA
DRIVERS

CDATA <15:00>

I--C DATA HP
f--C DATA LP

P02
CX-955A

10-3

HSC50 MEMORY MODULE

10.3.1
RAS/CAS Multiplexor
The RAS/CAS Multiplexor supplies row and column addresses to the RAMs during read and write cycles.
It receives the desired Control Memory address from the active requestor on the CADR < 15:00> signal
lines. The outputs of the RAS/CAS Multiplexor go to the RAMs themselves and supply the RAMs with
the desired address.
NOTE
The 16 bits of CADR < 15:00> address all 128
Kbytes, or 64 Kwords. The 16-bit address is on
word boundaries. Each read from Control Memory
reads a 16-bit word. Therefore, the 16 bits select
a word. The P.ioc shifts its address right one bit
before it puts the address on the CADR. The Ks always do a word write. The P .ioc can do a byte write
using the CWRTH and CWRTL signals.

During a refresh cycle, the signal CM REF CYC disables the output of this multiplexor. The row and
column address signals are supplied by the 8-Bit Refresh Address Counter located below the multiplexor.

10.3.2
8-Bit Refresh Address Counter
The 8-Bit Refresh Address Counter supplies refresh row addresses to the RAMs during refresh cycles.
The signal CM REF CYC increments the counter and also enables the counter outputs. The outputs of
the counter are connected to the RAS/CAS Multiplexor output lines. The outputs of the multiplexor are
disabled during refresh cycles.
10.3.3
Select Logic
The Select Logic monitors CADR < 16> and generates CM SEL if CADR < 16> is zero.
NOTE
The Select Logic contains other logic for the implementation of more than one Memory Module and
more than one bank of memory.

10.3.4
Timing Logic and RAM Drivers
The Timing Logic circuitry generates the required RAM timing and bus interface timing for Control
Memory. CTIMING is the clock from the P.ioc that starts the timing circuitry for Control Memory. The
timing is provided by a tapped delay line. The signals CWRTH and CWRTL, fro"m the active requestor,
determine if the cycle is to be a read or a write. Also CWRTH (high byte) and CWRTL (low byte)
determine which byte is written for a write cycle. The signal CREFR GRANT determines if the cycle is
to be a refresh cycle. CM SEL is asserted if the address is for the Control Memory.
The RAM Drivers supply the RAMs the row address strobe (CM RAS 0 and CM RAS 1), column address
strobe (CM CAS 0), and the two write enables (CM WRT HB and CM WRT LB). The write enables allow
either byte or word writes.
NOTE
The design allows for two banks of Control Memory, so there are signals that control both banks.
However, with this configuration of 128 Kbytes,
only Bank 0 is used.

10-4

HSC50 MEMORY MODULE

10.3.5
Data Receivers
The Data Receivers supply data to the RAMs on a write cycle. The receivers are always enabled. The
data to be written, as well as the high and low parity bits, are present on the CDATA lines. The receiver
output lines (CM < 15:00> ,HP,LP IN) drive the Data-In lines (DIN) of the RAMs.
10.3.6
Data Drivers
The Data Drivers supply data to the Control Bus out of RAM on a read cycle. They are enabled by
the signal CM RD CYC. When enabled, the data to be read is taken from the RAM outputs (CM
< 15:00 > ,HP,LP OUT), through the drivers to their outputs, and out on the backplane to the active
requestor.
10.3.7
Control Memory Cycles
During a Control Bus cycle, the Control Memory is executing one of four cycles:
Idle
W'rite
Read
Refresh
The P.ioc decodes the CCYCLE lines on the Control Bus and determines if the cycle is a write or read.
The P.ioc initiates the refresh cycle. The following sections explain each cycle type Refer to the timing
diagrams supplied for read, write, and refresh.
10.3.7.1
Control Memory Idle Cycle
An idle cycle occurs when there is no active requestor or when a Non-Memory Access (NMA) cycle or
an Interrupt (INTR) cycle occurs. The Control Memory remains idle because the P.ioc does not generate
CTIMING. Therefore Control Memory does not generate CM SEL or the acknowledge (CACK) for any
NMA, INTR, or idle Control Bus cycle.
10.3.7.2
Control Memory Write Cycle
The Control Memory Write Cycle cannot begin until a requestor has been granted bus control with
CGRANT. The P .ioc Control Bus Arbitration Logic acknowledges the request with CGRANT and the
requestor becomes active for that cycle.
Refer to Figure 10-3 for a timing diagram of the Control Memory Write Cycle.
The following list describes the Control Memory Write Cycle:
1.

When CGRANT is asserted, the active requestor asserts:
•

The address to be written on the CADR lines 'which are inputs to the CAS/RAS Multiplexor and the Select Logic

•

The data to be written on the CDATA lines which are inFuts to the Data Receivers
asserting CM xx IN

•

The comnland to write, CWRTH and/or CWRTL, generates the vVREN for the RAMs

When the Control Memory receives the assertion of CTIMING from the P.ioc, the memory
begins its cycle

The acknowledge signal, CACK, is asserted to tell the active requestor the selected address is
an existing address in Control Memory

The output of the RAS/CAS Multiplexor (CM AMUX xx) enables the row address to the RAMs

The signal CM RAS is asserted
10-5

HSC50 MEMORY MODULE

NOTE:

The address or data lines can be in the high state or low state at
any given time. The lines here are shown in the high state.
CX-1151A

The RAS/CAS Multiplexor output enables the column address to the RAMs 15 nanoseconds
later

The signal CM CAS is then asserted to strobe the data and parity into the RAM from the active
requestor on the CD ATA lines of the data receivers

10-6

HSCSO MEMORY MODULE

10.3.7.3
Control Memory Read Cycle
The Control Memory Read Cycle cannot begin until a requestor has been granted bus control with
CGRANT. The P.ioc Control Bus Arbitration Logic acknowledges the request with CGRANT, and the
requestor becomes active for that cycle.
Refer to Figure 10-4 for a tinling diagram of the Control Memory Read Cycle.
The following list describes the Control Memory Read Cycle:
1.

When CGRANT is asserted, the active requestor asserts the address to be read on the CADR
lines which are inputs to the RAS/CAS Multiplexor

When the Control Memory receives the assertion of CTIMING from tht., P.ioc, the memory
cycle begins

Neither CWRTH or CWRTL being asserted indicates a read cycle

The CADR lines are gated through the RAS/CAS Multiplexor and generate CM AMUX xx H
for the row address

CTIMING generates:
•

CM RD CYC

•

CM RAS

The column address is generated from the CADR lines 15 nanoseconds lilter

CM CAS is then generated

The data is read out of the RAM and is enabled onto the Control Bus by eM RD CYC

10.3.7.4
Control Memory Refresh Cycle
The dynamic RAMs used in Control Memory require that all rows within the RAM be refreshed every
4 milliseconds to ensure data retention. A refresh timer circuit on the P.ioc provides a signal called
CREFRESH CLK approximately every 15 microseconds to ensure that all 128 rows are refreshed within
the required 2-millisecond period.
Refresh requests are given the highest priority in the arbitration logic on the P.ioc. No data is transferred
across the Control Bus during a refresh cycle, nor does Control Memory generate CACK or drive the
CDATA lines.
The arbitrator asserts CREFR GRANT, notifying the Control Memory that a refresh cycle is to be performed. The refresh cycle begins when CTIMING is asserted. The 8-Bit Refresh Address Counter
supplies the address of the row to be refreshed. The counter is enabled by CM REF CYC and is incremented by the negation of the CM REF CYC signal. (CM REF CYC is the coinplement of CREFR
GRANT from the Timing Logic.)
Refer to Figure 10-5 for a timing diagram of the Control Memory Refresh Cycle.
10.4 DATA MEMORY
Data Memory is 128 Kbytes of memory and resides on the Data Bus. Data Memory uses 16Kxl static
RAMs because of the high speed requirements of the Data Bus. It is organized as 4 banks of 18 RAMs
apiece designated as banks zero, one, two, and three. Each bank is 18 bits wide (16 data bits plus 2
parity bits) and 16 Kwords deep. Either data byte within a word may be written separately using the
signals DWRTH and DWRTL.
Data Memory is used by both the P.ioc and the Ks to perform data transfers. All data which flows
through the HSC50 subsystem goes through the Data Memory.

10-7

HSC50 MEMORY MODULE

Figure 10-4

Control Memory Read Cycle Timing
300 ns
CGRANT L
CADR n L
CM SEL L

l
l

--,

CTIMING H
CACK L
CWRTH/L L
CM WRT HB/LB L
CM WRT CYC L
CM AMUX xx H

X
ROW

X
COLUMN

CM RD CYC L
CM RAS x L

CM CAS x L
CDATA n L
CM xx OUT H
NOTE:

--.J
/

'L-

The address or data lines can be in the high state or low state at
any given time. The lines here are shown in the high state.
CX-1149A

The Data Memory block diagram (Figure 10-6) shows the components of Data Memory. The following
sections describe each of those components.

10-8

HSC50 MEMORY MODULE

Figure 10-5 Control Memory Refresh Cycle Timing
- - - - - 300 ns - - - - -

CREFR GRANT L
CM REF CYC L

IL..___________--'
l~

________________

~r___

CM SEL L
CTIMING H
CACK L
CWRTH/L L
CM WRT HB/LB L
CM AMUX xx H
CM RD CYC L
CM RAS x L

\ . . . . _--------1/

CM CAS x L
NOTE:

The address or data lines can be in the high state or low state at
any given time. The lines here are shown in the high state.
CX-1150A

10-9

%
Ul

Figure 10-6 Data Memory Block Diagram

DADR

<13:00> ~ ADDRESS

o
3:
m
3:

P07

CLKA DWRTH DWRTL DMSEL -

......

oI
......
o

RAM
DRIVER
P05
t--

SELECT
LOGIC

DATA
MEMORY
ARRAY
BANK 0 AND 1
WREN

DATA r-OUT

THIRTY-SIX
16KX1
STATIC RAMS

DM RD CYC

r- DM SEL
r- DACK

rvvv-

P05 I-- DM WRT CYC

DNMA DADR <16> DADR <17>-

64 KBYTES

DM A <13:00>A

RECEIVERS/
DRIVERS

CLKB -

o
l:J
<

DM BANK SEL 0

ENM

DM BANK SEL 1

1A.

r-n/

P05

ENM
DATA IN

POS

t..

)

64 KBYTES

t..

DADR <13:00>

ll..

ADDRESS
RECEIVERS/
DRIVERS

DM A<13:00>B

WREN

.........

BANK
SELECT

DM NMA -

P06

.\
J

.!.

DDATA HP
DDATA LP DMOE -

AAA

DADR 15 DADR 14 -

DD ATA<15:00>

[

P07

DATA
RECEIVERS
EN

P06

DM
<15:00>
HP, LP
OUT

DATA
MEMORY
ARRAY
BANK 2 AND 3

DATA
DRIVERS

DATA
OUT

DDATA <15:00>

r- DDATA HP

r- DDATA LP
P06

DM RD CYC

.A.AA

"' ...

A.AA

,., '"

AAA

DM BANK SEL 2
DM BANK SEL 3

"'''''''

DM <15:00>, HP, LP IN

ENM
I--- ENM

I---

~
r

THIRTY-SIX
16KX1
STATIC RAMS
DATA
IN
P09
CX-957A

HSC50 MEMORY MODULE

10.4.1
Address Receiver/Driver
The Data Memory Address Receiver/Drivers supply addresses to the RAMs for read and write cycles.
The inputs to the receivers are DADR < 13:00>. The drivers in the upper left of Figure 10-6 provide
DM A < 13:00> A to Banks zero and one. The drivers in the middle of the figure provide DM A < 13:00 >
B to Banks two and three. The receivers/drivers are always enabled.
NOTE
DADR < 15:14> are inputs to the Bank Select logic.

10.4.2
Timing Logic and RAM Drivers
The Data Memory Timing Logic generates the required RAM timing and bus interface timing for Data
Memory. The Timing Logic has delay lines that provide discrete timing signals; ClK A and CLK B from
the P joc are inputs to these delay lines. The Data Bus cycles are synchronized by the requestor having
been granted control of the bus with the signal eLK A or CLK B which have 150 nanoseconds periods.
The Ram Driver drives the write signals DWRTH and DWRTL to the RAMs for writing either or both
bytes.
10.4.3
Select Logic
The Select Logic compares the address on the DADR lines and generates DM SEL and DACK if the
address is in the range of the installed memory. DNMA H disables the select logic because Data
Memory is not selected for a non-memory access cycle. (The requestors use the non-memory access
cycle to check the operation of the DADR and DDATA lines.)
10.4.4
Bank Select
The Bank Select logic selects one of four banks of RAM available to Data Memory. It is enabled by the
negation of DM NMA (a non-memory access cycle is not in progress). Signals DADR 15 and DADR 14
select one of the four banks as shown in Table 10-2.

Table 10-2

Data Memory Bank Selection

DADR 15

DADR 14

Bank Selected

10.4.5
Data Receivers
The Data Receivers supply data to the RAMs on a write cycle. They are always enabled by the signal
DM OE. The data and parity bits to be written are driven onto the DDATA < 15:0G>,HP,LP lines by the
active requestor and passed through the driver to the RAM inputs DM < 15:00> ,HP,LP IN.

10-11

HSC50 MEMORY MODULE

10.4.6
Data Drivers
The Data Drivers supply data to the Data Bus out of RAM on a read cycle. The drivers are enabled only
on a read cycle by the signal OM RD CYC. When the drivers are enabled, the data as well as the parity
bits are driven onto the Data Bus lines, DDATA < 15:00> ,HP,LP.
10.4.7
Data Memory Cycles
During any given Data Bus cycle, Data Menlory is executing one of three cycles:
Idle
Write
Read
The static RAMs used in Data Memory do not require refresh cycles. Each of the three cycles is covered
in the following sections. Refer to the timing diagrams supplied for the read and write cycles.
10.4.7.1
Idle Cycle
An idle cycle occurs when there is no active requestor or when an NMA (non-memory access) cycle
occurs. During these cycles the signal DNMA H forces the Data Memory select logic not to select Data
Memory and forces the bank select logic not to select any bank of Data Memory.
10.4.7.2
Write Cycle
To write to Data Memory, a requestor must first acquire the Data Bus by asserting its request to the
bus arbitrator on the P.ioc. Once the requestor receives the assertion of DGRANT from the P.ioc, it has
possession of the Data Bus for that cycle.
Refer to Figure 10-7 for a timing diagram of the Data Memory write cycle.
The following list describes the Data Memory write cycle:
•

After the P.ioc asserts DGRANT, the high to low transition of the CLK B H signal clocks the
active requestor's DGRANT flip-flop asserting the address to be written on the DADR lines

•

With the assertion of the DADR lines:
•
•
OM BANK SEL x is asserted from the Bank Select logic
•

OM Axx A/B is asserted from the Address Receivers/Drivers

•

OM SEL is asserted from the Select Logic

•

DACK is asserted from the Select Logic

•

The requestor then asserts the DO ATA lines and DWRTH/L lines

•

The Data Receivers assert DM xx IN to the RAMs

•

The Timing Logic asserts OM WRT CYC from DWRTH/L

•

The RAM Driver asserts OM WRT HB/LB

•

The data is written into the RAMs

10-12

HSC50 MEMORY MODULE

Figure 10-7 Data Memory Write Cycle Timing
- - - - 150 ns - - - - -

CLK B H
OAOR n L

I~----~------~
~~

__________________

~r---

OM BANK SEL x L -----.~_ _ _ _ _ _ _ _ _ _ ___'r_
OM Axx AlB H
OM SEL L
OACK L

______________________r-____________________

~r-

OOATA n L
OWRTH/L L
OM xx IN H
OM WRT CYC L

______________~r_

OM WRT HB/LB L

NOTE:

The address or data lines can be in the high state or low state at
any given time. The lines here are shown in the high state.
CX-1153A

10-13

HSC50 MEMORY MODULE

10.4.7.3
Data Memory Read Cycle
To read from Data Memory, a requestor must first become active by asserting its request to the P.ioc
arbitration logic and receiving the asserted DGRANT signal.
Refer to Figure 10-8 for a timing diagram of the Data Memory read cycle.

Figure 10-8

Data Memory Read Cycle Timing
- - - - - 150 ns

CLK B H
OAOR n L

IL_______--'
~L_

____________________~

OM BANK SEL x L - - - - - .
OM Axx AlB L
OM SEL L

r--

OACK L
OM RO CYC L

OM xx OUT H

I
I

r--

ODATA n L
NOTE:

The address or data lines can be in the high state or low state at
any given time. The lines here are shown in the high state.
CX-1152A

The following list describes the Data Memory read cycle:
•

After the P.ioc asserts DGRANT, the high to low transition of the eLK B H signal clocks the
active requestor's OGRANT flip-flop asserting the address to be written on the DAOR lines

•

With the assertion of the DADR lines:
•

OM BANK SEL x is asserted from the Bank Select logic

10-14

HSC50MEMORY MODULE

•

OM Axx A/B is asserted from the Address Receivers/Drivers

•

OM SEL is asserted from the Select Logic

•

DACK is asserted from the Select Logic

•

The OM RD CYC signal is asserted from the Timing Logic

•

The outputs from the RAMs are enabled through the Data Drivers by OM RD CYC

•

When CLK B goes HI, the data is strobed into the receivers on the requestor

10.5 PROGRAM MEMORY
The P joc loads the operational and diagnostic software into Program Memory via the TU58 tape unit.
The P .ioc is the only module that uses Program Memory.
Program M:emory uses 36 dynanlic 64Kxl RAMs logically organized as two banks (bank 0 and bank
1). Each bank is 18 bits wide (1 parity bit per byte) and 64 Kwords deep. The I'joc can assign the
starting address of 000000008 to either bank 0 or bank 1. This capability allows the P.ioc to operate
even if one bank fails (only 128 Kbytes). Remember that the F-11 processor on the P.ioc requires the
standard PDP-II trap and interrupt vectors to start at address 000000008 , However, the P.ioc does not
dynamically swap banks when the HSC50 is online.
The Program Memory block diagram (Figure 10-9) shows the components of the memory. The following
sections describe each of these components.
10.5.1
BDAL Buffer
The BDAL Buffer receives the address or data on the BDAL lines. PM SYNC clo.cks the address into
the CAS and RAS Address Driver. After PM SYNC latches the address into the CAS and RAS Address
Driver, the BDAL Buffer receives the data for the RAMs if a write cycle is to be performed to memory.
The data is then available at the DIN input of the memory array.
10.5.2
CAS and RAS Address Drivers
The CAS and RAS Address Drivers supply row and column addresses to the RAM Address Driver. The
input signals are:
PM < 15:00 > IN-address from BDAL Buffer
PIVl SYNC-clock
PM COL ADR EN -enable for CAS Address Driver
PM ROW ADR EN -enable for RAS Address Driver
10.5.3
RAM Address Driver
The RAM Address Driver supplies the addresses to RAM for read, write, and refresh cycles. The CAS
and RAS Address Drivers supply the saved address during a write or read cycle. The 8-Bit Refresh
Address Counter supplies the address during a refresh cycle.
10.5.4
8-Bit Refresh Address Counter
The 8-Bit Refresh Address Counter supplies the refresh row address to the RAMs ouring refresh cycles.
A refresh cycle disables the outputs of the CAS and RAS Address Drivers. The signal PM REF IN PROG
enables the refresh counter output and increments the counter at the end of the refresh cycle.

10-15

Figure 10-9

Program Memory Block Diagram

::z:
en

(')

..
BDAl<17:00>

-.II.

PM<15:00>IN

r
PM SYNC-

r'""

CAS
ADDRESS
DRIVER

r--

RAM
ADDRESS
DRIVER

PM AMUX<7:0>

ADR

128 KBYTES

t- ClK
~

BDAl
BUFFER

P12

WRT HI BYTE
RAS
ADDRESS
DRIVER

P12

WRT lO BYTE

m
==

0==

PROGRAM
MEMORY
ARRAY

P12

,....

~
PM SYNC
ClK
PM COL ADR ENEN
PM ROW ADR EN -

PMOE-

t-PM lCAS

r-v

I--

ttI-

:lJ

DOUT

BANKO

DIN

0==

C
rm

r--

EIGHTEEN
64KX1
DYNAMIC RAMS

r-r-r--

P13

P12

..
BDAl<21: 18>

)

~
PM A<17:16>j

ADDRESS
DECODE
lOGIC

BBS7 ~

"""'I
"""'

P11

~PM SEl

PM REF IN PROG-

8-BIT
REFRESH
ADDRESS t - COUNTER

~ ADR

PM<OO>IN PM SYNC-

P12

P11

BSYNC -

PM SEl -

PM RD REO

SW AP PM BANK-

PM UCAS

>
>
-

PM ROW ADR EN

PM COL ADR EN

PM RD REOPMWR REORAM
DRIVERS
BDINBDOUTBRPlYBINIT-

P10

DATA
DRIVER
CONTROL
AND
BRPlY
lOGIC

: ) 80 Al<21:00>

"
PM lATCH
DATA
PM ENB D
DRVRS

DATA
DRIVERS

Pll

P1 1 -BRPlY

BANK
SELECT
lOGIC
BDCOK Pl0

P13

PM <15:00>, HP, lP OUT

RAM
TIMING
lOGIC

P10

PM ClR RD/WRT REO

r-r--

EIGHTEEN
64KX1
DYNAMIC RAMS

PM WRT REO

PM REF IN PROG

PMClR REF~

PM RAS 0
PM RAS 1

Pll

PM REF REO
MEMORY
REOUEST
lOGIC

PMWRT REGPM REF IN PROG -

BWTBT PREFR ClK-

J\.AA

RAM
DRIVERS

DOUT

BANK 1

Jl.AA
...... ,.

WRITE
BYTE
DECODE
lOGIC

PM WTBT-

PROGRAM
MEMORY
ARRAY

DIN

Q"\

128 KBYTES

P10
CX-958A

HSC50 MEMORY MODULE

10.5.5
Address Decode Logic
The Address Decode Logic selects program memory for address combinations that do not assert BBS7
and BDAL <21:18>. The output is PM SEL.
10.5.6
Write Byte Decode and RAM Drivers
The Write Byte Decoder supplies the inputs to the RAM Drivers depending on the state of PM 00 IN
and PM WTBT. If the P.ioc does not assert PM WTBT (write byte), both bytes of the word are written
into Program Memory. If the P joc asserts PM WTBT, the PM 00 IN (bit 00 of the .lddress) signal selects
which byte (HI or La) is written into Program Memory.
The RAM Driver provides the write enable to the RAMs. If a refresh cycle is not in progress (PM REF
IN PROG), PM WRT REQ enables the output of the RAM Driver.
Memory Request Logic
10.5.7
The Memory Request Logic consists of several flip flops servicing the types of requests to which Program
Memory can respond. The valid requests for Program Memory are:
Read
·Write
Read -modify -write
Refresh
10.5.8
RAM Timing Logic
The RAM Timing Logic provides the timing for the Program Memory via a delay line.
10.5.9
Bank Select Logic and Program Memory RAM Driver
The Bank Select Logic selects which of the two banks of Program Memory has a starting address of
000000008 , The signal SWAP PM BANK from the P joc selects that bank.
The RAM Drivers supply the CAS and RAS signals to the RAMs. The output frOln the RAM Timing
Logic generates PM RAS 0 (low byte) and PM RAS 1 (high byte). Depending on the output from the
Bank Select Logic, the RAM driver asserts PM LCAS (bank 0) or PM UCAS (bank 1).
10.5.10
Data Driver Control and BRPLY Logic
The Data Driver Control and BRPL Y Logic control the reading and writing of data through the Program
Memory data drivers. The following are the input signals:
PM RD REQ-read request
PM WR REQ-write request
BDIN-read control
BDOUT-write control
The output signal PM LATCH DATA clocks the data from the RAMs into the Data Drivers. The signal
PM ENB D DRVRS enables the output of the Data Drivers onto the BDAL lines.
The BRPLY Logic asserts the signal BRPLY at the completion of a memory cycle. The signal BDIN gates
BRPLY for a read cycle. The signal BDOUT gates BRPLY for a write cycle.
10.5.11
Data Drivers
The Data Drivers supply data to the Program Bus during a a read cycle. The signal PM LATCH DATA
clocks the data from the RAMs into the Data Drivers. The signal PM ENB D DRVRS enables the output
of the Data Drivers onto the BDAL lines. On a read cycle, the BDAL < 17:00 > L lines receive the data
plus the parity bits, PM < 15:00> ,HP,LP OUT, from the RAMs.

10-17

HSC50 MEMORY MODULE

10.5.12
Program Memory Cycles
As stated earlier, Program Memory performs the following four cycles:
Write
Read
Read-modify-write
Refresh
The following sections describe these cycles.
10.5.12.1
Program Memory Write Cycle
Refer to Figure 10-10 for a timing diagram of the Program Memory write cycle.
The following list describes the Prograln Memory Write Cycle:
1.

The P.ioc asserts the address on the BDAL lines while asserting BWTBT (write cycle).

The signal BSYNC latches the address into the CAS and RAS Address Drivers (PM SYNC).

The RAM Timing Logic asserts PM ROW ADR EN to enable the output of the RAS Address
Driver.

The P.ioc asserts the write data on the BDAL lines.

The P.ioc asserts or negates BWTBT, depending on the type of cycle (word or byte).

The signal BDOUT initiates the Program Memory write cycle by generating PM WRT REQ.

The RAM Timing Logic generates the timing for the RAM Drivers that assert PM RAS 0 and
PM RAS 1.

The RAM Timing Logic negates PM ROW ADR EN, disabling the output of the RAS Address
Driver.

The RAM Timing Logic asserts PM COL ADR EN, enabling the output of the CAS Address
Driver.

10. The RAM Timing Logic generates the timing for the RAM Drivers asserting PM CAS.
11. The Write Byte Decode Logic, through the RAM Drivers, generates the write enable (WRT HI
BYTE and WRT La BYTE) for the RAMs.
12. The Data Driver Control and BRPLY Logic negate BRPLY, finishing the write cycle.
10.5.12.2
Program Memory Read Cycle
Refer to Figure 10-11 for a timing diagram of the program memory read cycle.
The following list describes the Program Memory Read Cycle:
1.

The P.ioc asserts the read address on the BDAL lines while negating BWTBT (read cycle).

The signal BSYNC latches the address into the CAS and RAS Address Drivers (PM SYNC).

The Memory Request Logic asserts PM RD REQ when the P.ioc asserts BSYNC.

The RAM Timing Logic asserts PM ROW ADR EN, enabling the output of the RAS Address
Driver.

The RAM Timing Logic generates the timing necessary for the RAM Drivers to assert PM RAS
o and PM RAS 1.

The RAM Timing Logic negates PM ROW ADR EN, disabling the output of the RAS Address
Driver.
10-18

HSC50 MEMORY MODULE

Figure 10-10 Program Memory Write Cycle Timing

BSYNC L
BDAL xx L

IL-___
=x~

,------------------------~

____ ______________________________ ____
~x~

ADDRESS

~~~

DATA

PM SEL H

BWTBT L

____41______________________________ -==x~
HI

Word

La = Byte

L-l______.....II'

BDOUT L
PM WRT REQ L

L....-_ _ _ _ _ _ _ _

PM ROW ADR EN L
PM RAS L

________ _J

PM COL ADR EN L - - - - - - - - - - - - - - - - - - - ,L - -_ _ _ _ _ _ _ J...----PM CAS L
PM AMUX xx H

_---Jr

\~--

_________________ ______
~x~

~==x~

___

PM WRT CYC H
PM WRT HI/La BT L - - - - - - - - - - - - - - - : . -________ ~
BRPLY L

NOTE:

.....II'

L - -_ _ _ _ _ _ _

The address or data lines can be in the high state or low state at
any given time. The lines here are shown in the high state.
CX-1156A

10-19

HSC50 MEMORY MODULE

Figure 10-11 Program Memory Read Cycle Timing

BSYNC L
BDAL xx L

X
ADDRESS

PM SEL H

PM RD REQ H

BWTBT L

----.-r==-x==
DATA

PM ROW ADR EN L
PM RAS L
PM COL ADR EN L ---....,
PM CAS L
PM AMUX xx H

_____

~x~

_____--JI

__________

~x~

_____________________________

PM RD CYC H
PM xx OUT L

----------------~I

\~-----------------------

----Jr--

PM LATCH DATA L ----------------------:________________
BDrN L

~-----------~

PM ENB D DRVRS L --------------------------,L...-_ _ _ _ _ ----1r - - BRPLY L

NOTE:

The address or data lines can be in the high state or low state at
any given time. The lines here are shown in the high state.
CX-1154A

10-20

HSC50 MEMORY MODULE

The RAM Timing Logic asserts PM COL ADR EN, enabling the output of the CAS Address
Driver.

The RAM Timing Logic generates the timing necessary for the RAM Drivers to assert PM CAS.

PM LATCH DATA latches the data output of Program Memory (PM xx OUT) into the Data
Drivers.

10. The signal BDIN asserts PM ENB D DRVRS, enabling the data from the Data Drivers onto the
BDAL lines.
11. The Data Driver Control and BRPLY Logic negate BRPLY, finishing the read cycle.
10.5.12.3
Program Memory Read-Modify-Write Cycle
Program ~v1emory is capable of performing a read-modify-write cycle to the same address. The readmodify-write cycle is a single bus cycle that generates two memory cycles. This cycle is similar to a
read cycle followed by a write cycle. However, in a read-modify-write cycle, the address is sent to the
memory only once (during the read cycle). During the write cycle, the memory uses the address it
latched into the CAS and RAS Address Drivers.
The P.ioc asserts BSYNC L during the entire cycle.
Although this cycle is a continuous cycle on the Program Bus, a refresh cycle can occur between the
read and the write cycles. The refresh cycle will delay the write cycle.
10.5.12.4
Program Menlory Refresh Cycle
Program Memory RAMs require refresh cycles to ensure data retention in the dynamic RAMs. The
overflow of the counter on the P.ioc asserts PREFR CLK every 15 microseconds to the Program Memory.
If a read or write cycle is in progress when the P joc asserts PREFR CLK, the Program Memory does
not initiate the refresh cycle until the read or write cycle finishes. Also, the program memory will not
initiate a read or write cycle until any refresh cycle in progress is complete.
The 8-bit Refresh Address Counter provides the refresh row address. The end of the refresh cycle
increments the counter. A refresh cycle does not use the column address strobe (CAS).
Refer to Figure 10-12 for a timing diagram of the Program Memory refresh cycle.

10-21

HSC50 MEMORY MODULE

Figure 10-12

Program Memory Refresh Cycle Timing
- - - - - - - 15 microseconds - - - - - - - - - -

PREFR CLK H

PM REF REQ H

______________~r_

____________________

PM REF IN PROG H ~
PM REF T75 H
PM SEL H
BRPLY L

PM ROW ADR EN L
PM RAS L
PM CLR RAS L
PM COL ADR EN L - - - - - - - - - - - - - - - - - - - - - - - - - - PM CAS L
PM AMUX xx H

____--'I

\~---------------------

PM TO H
NOTE:

The address or data lines can be in the high state or low state at
any given time. The lines here are shown in the high state.
CX-1155A

10-22

HSC50 MEMORY MODULE

10.6 JUMPER AND DIPSHUNT CONFIGURATION
There are various jumpers and dips hunts on the HSC50 Memory Module. TablE:~ 10-3 describes the
purpose and normal configuration of each jumper and dipshunt for the HSC50 Memory Module.

Table 10-3

HSC50 Memory Module Jumper and Dipshunt Configuration

Jumpers
or
Dipshunts

Normal
Configuration

Description

Out

Install for 16K RAMs in Control Memory

Out

Install for 16K RAMs in Control Memory

Install for 1 bank of 64K RAMs in Control Memory

Out

Install for 2 banks of 64K RAMs in Control lMemory

Install for 64K RAMs in Control Memory

Out

Install for 16K RAMs in Control Memory

Out

Install for 16K RAMs in Control Memory

Install for 1 or 2 banks of 16K RAMs or 1 bank of 64K RAMs in
Control Memory

Install for 64K RAMs in Control Memory

WlO

Install for 64K RAMs in Control Memory

Install 8-position dipshunt for 64KW in Data Memory

Out

Install 8-position dipshunt for 16KW in Data Memory

E33

Out

Install 8-position dipshunt for 32KW in Data Memory

El12

Out

Install 5-position dips hunt for 16KW in Control Memory

El13

Install 5-position dips hunt for 32KW, 64KW, or 128KW in Control
Memory

E223

Out

Install 5-position dipshunt for 64KW in Program Memory

E229

Out

Install 8-position dipshunt for 32KW in Program Memory

E239

Install 8-position dipshunt for 64KW or l28KvV in Program Memory

E242

Install 5-position dipshunt for 32KW or 128KVV in Program Memory

10-23

HSC70 MEMORY MODULE

CHAPTER 11
HSC70 MEMORY MODULE

11.1 INTRODUCTION
The HSC70 memory module, M.std2 (Memory Standard 2), is an extended-hex size module residing in
slot two of the HSC70, adjacent to the J-ll I/O Control Processor Module (P.ioj). The module number
LOl17 is stamped on the handle. The M.std2 contains three separate and independent memories, each
on its own bus, as well as a controller for the RX33 floppy disk drives. The three memories and the
floppy disk controller are :
•

Control Memory or M.ctl (residing on the Control Bus)

•

Data Memory or M.data (residing on the Data Bus)

•

Program Memory or M.prog (residing on the Program Bus)

•

Floppy Disk Controller or K.rx (residing on the Program Bus)

Each of the memory arrays includes byte parity.
Refer to Figure 11-1 for a block diagram of the M.std2 module and its four components.
The three memories each use different RAM types and quantities as follows:
•

M.ctl = 256 Kbytes (128 Kwords) uses 18 256Kxl dynamic RAMs

•

M.data = 512 Kbytes (256 Kwords) uses 72 64Kxl static RAMs

•

M.prog = 1 Mbyte (512 Kwords) uses 36 256Kxl dynamic RAMs

11.2 STATUS LEOs
There are three LEDs on the Memory Module. They display the status of the M.std2.
The yellow LED is the memory active LED. It lights on every memory cycle to Control, Data, or Program
Memory. The the yellow LED becomes brighter with increased memory activity.
The red and green LEDs are controlled by the Module OK bit in the MAR2 (Memury Address Register
2) of the floppy controller. Setting the bit will turn on the green LED (module OK) and turn off the
red LED (module BAD). Following power up, the bit will be cleared and the red LED will be on. After
passing diagnostics, the green LED comes on (module OK bit). The memory address register will be
discussed in Section 11. 7.1. 4.

11-1

HSC70 MEMORY MODULE

Figure 11-1

M.std2 Block Diagram

CONTROL BUS

MEMORY MODULE (L0117)

M.ctl

M.prog

PROGRAM MEMORY
1024 KBYTES

CONTROL MEMORY
256 KBYTES + 256 KBYTES

::>
co
~

«
a:

(!)

oa:

0..

M.data

K.rx

DATA MEMORY
512 KBYTES

FLOPPY DISK
CONTROLLER

CX-959A

11-2

Figure 11-2 Control Memory Block Diagram

J\.

CADR (16:00»

CM AMUX<8:0>

SWAP CM BANK- ADDRESS
MUX
T25- SEL

P02

CM REF CYC-r-

8-BIT
REFRESH
ADDRESS
COUNTER

I-

512 KBYTES

!---

P02

CONTROL
MEMORY
ARRAY
EIGHTEEN
256Kx1
DYNAMIC RAMS

CM TIMINGCM WRT H/LCREFR GRANTSLOW CYCLECM CLR RAS_

t--~

TIMING
LOGIC

RAM
DRIVER

-./\IV\,
.AAA

-.. " " v

-..AAA
.... v

RAS
CAS
WR EN

P01
!-T25
~CIV1 REF CYC
~CM SEL

P01,P02 -CM RD CYC
CM(15:00>"""'---'"
-\

"nllTI\ ,....'t:;.nn'>'
1~.'"'-..;r".1
:'M7A
..... !....If.-..\ !

;--..

......

CDATA HP:'" RECEIVERS
CDATA LP-

~-c-~-.~-_'-,5-:-~-.~-.,-LP-.-U-p-I-.~-!~ ~I_~_O_T_~_I_~_I

LP,HP OUT "-

:_'_~_7_~_:_:_:~·1I~C-M~~-~~g-~~~~E_~_A:_~_E_:_:_2_~~~'~"">

____

P02
CX-960A

HSC70 MEMORY MODULE

Control Memory, residing on the Control Bus, performs a read or a write cycle as determined by the
requestor that has been granted the Control Bus for that cycle. To ensure data retention of the dynamic
RAMs, control Memory also performs refresh cycles once every 15 microseconds. Control Memory is
logically organized as one bank 18 bits wide and 128 Kwords deep. Since there are eighteen 256Kxl
dynamic RAMs in this design, there is a second bank of 128 Kwords contained within the same RAMs.
This second bank may only be accessed by the P .ioj asserting the signal SWAP CM BANK H.
In use, the M.std2 stores 16 data bits and 2 parity bits which have identical paths for both data and
timing. In addition, either data byte may be written independently.
The following sections describe each of the components shown in the Control Memory block diagram.
11.3.1
Address Multiplexer
The Control Memory Address Multiplexer supplies row and column addresses to the RAMs during
read and write cycles. The address multiplexer is actually three 74F258 quad multiplexers. It receives
the desired Control Memory address from the active requestor on the CADR < 16:00> L signal lines.
The outputs of the address· multiplexer go to the RAMs themselves and supply the RAMs with the
desired address. The signal SWAP CM BANK H, if asserted by the P.ioj, is also an input to the address
multiplexer and is used to access the second bank of RAM in Control Memory.
11.3.2
Control Memory Eight Bit Refresh Address Counter
The Eight Bit Refresh Address Counter supplies refresh row addresses to the RAMs during refresh
cycles. The counter is a 74LS590. The signal POI CM REF CYC L enables the counter outputs. The
counter outputs are connected to the address multiplexer output lines because the address multiplexer
is not enabled during refresh cycles. The Refresh Address Counter is incremented at the end of each
refresh cycle.
11.3.3
Control Memory Timing Logic and RAM Drivers
The timing logic circuitry generates required RAM timing and bus interface timing for Control Memory.
The timing logic uses a 74F158 multiplexer to select taps of a delay line to provide timing. The multiplexer
is steered by the signal SLOW MODE H. CTIMING H is the clock from the P.ioj that starts the timing
circuitry for Control Memory. The signals CWRTH Land CWRTL L, from the active requestor, determine
if the cycle is to be a read or a write. The signal CREFR GRANT L determines if the cycle is to be a
refresh cycle.
Two 74FOOs supply the RAMs with the row address strobe (CM RAS L), column address strobe (CM
CAS L), and the two write enables (CM WRT HB Land CM WRT LB L). The write enables allow either
byte or word writes.
11.3.4
Control Memory Data Receivers
The Control Memory Data Receivers, consisting of three 74F240 buffered line drivers, supply dat~ to
the RAMs on a write cycle. The receivers are always enabled. The data to be written, as well as the high
and low parity bits, are present on the CDATA lines. The receiver output lines (CM < 15:00,HP,LP>
IN H) drive the Data-In lines (D IN) of the RAMs.
11.3.5
Control Memory Data Drivers
The Control Memory Data Drivers, consisting of three 74F240 buffered line drivers, supply data to the
Control Bus out of RAM on a read cycle. They are enabled by the signal CM RD CYC L. When enabled,
the data to be read is taken from the RAM outputs (CM < 15:00,HP,LP> OUT H), through the drivers
to their outputs, and out on the backplane to the active requestor.
One of the data drivers also drives the acknowledge (CACK L) signal, which indicates that the Control
Memory recognizes and is responding to the address received from the active requestor.

11-4

HSC70 MEMORY MODULE

11.4 CONTROL MEMORY CYCLES
During a Control Bus cycle, the Control Memory executes one of the following four cycles:
Idle
Write
Read
Refresh
The P.ioj decodes the CCYCLE lines on the Control Bus and determines if the cycle is a write or read.
The P.ioj initiates the refresh ·cycle. Each cycle is covered in the following sections. Refer to the timing
diagrams supplied for read, write, and refresh cycles.
11.4.1
Control Memory Idle Cycle
An Idle Cycle occurs when there is no active requestor or when a Non-Memory Access (NMA) cycle
or an Intenupt (INTR) cycle occurs. The Control Memory remains idle during th,~se types of cycles
because the P.ioj does not generate CTIMING H. Therefore, Control Memory does not generate CM
SEL L or the acknowledge (CACK L) for any idle, NMA, or INTR, Control Bus cycle.
11.4.2
Control Memory Write Cycle
In order to write to Control Memory, a requestor must first have been granted bus control by sending
its request to the Control Bus arbitrator on the P.ioj module. The P.ioj acknowledge's the request with
the assertion of CGRANT L, and the requestor becomes active for that cycle.
At this point refer to Figure 11-3 for a timing diagram of the Control Memory write cycle.
With the assertion of CGRANT L, the active requestor asserts the address to be written on the CADR
< 16:00 > L lines of the address multiplexer. CTIMING H is then asserted. The PJiiJj asserts the write
enables, CWRTH L or CWRTHL L, depending upon which byte(s) are to be written. The signal C CAS
L is then asserted to strobe the data and parity into the RAM from the active requestor on the CDA TA
< 15:00,HP,LP> L lines of the data receivers. The acknowledge signal CACK L is asserted to tell the
active requestor the selected address exists in Control Memory.
When the Control Memory receives the assertion of CTIMING H from the P.ioj, it begins a write cycle
to the address received on the CADR lines. The signal CTIMING H is asserted by the P.ioj and is gated
through the Control Memory to become CM SEL L. The data on the CDATA lines prus parity is gated
through the data receivers onto the D IN lines of the RAMs and written in the selected address.
11.4.3
Control Memory Read Cycle
To read from Control Memory, a requestor must have been granted the Control Bus for that cycle
by sending a request to the control bus arbitrator on the P.ioj and receiving back t'le assertion of the
CGRANT L signal. The requestor is then active.
At this point refer to Figure 11-4 for a timing diagram of the Control Memory read cycle.
With the assertion of CGRANT L, the requestor asserts the desired address with the signals CADR
< 16:00 > L. Both write enable lines, CWRTH Land CWRTL L, are negated. The Control Bus Arbitrator
on the P joj decodes the cycle as normal and asserts the signal CTIMING H.
When Control Memory receives the assertion of the CTIMING H signal with the write enable lines
negated, it starts a read cycle. The row address is selected with CM RAS L. The column address is
valid, but not strobed onto the address lines until CM CAS L is asserted. CACK L b generated, telling
the active requestor this is a valid Control Memory address. The data read from RAl'v1 is output onto the
COAT A lines and sent to the active requestor. CM RAS L is negated and then CM CAS L and the data
are negated. The CACK L signal is then negated to signal the end of the Control Mt.~mory read cycle.

11-5

HSC70 MEMOR'y MODULE

Figure 11-3 Control Memory Write Cycle Timing
300 ns
CGRANT L
CADR n L

CTIMING H

CM SEL H

CACK L

CWRTH/L L

CM WRT HB/LB H

(CM WRT GATE H)

CM WRT HB/LB L

CDATA n L

CM xx IN H

CM RAS L

--,
~

CM CLR RAS H

CM CAS L
CM AMUX xx H

L
ROW

-==x=

COLUMN

CM T25 L

NOTE:

(E121-12)

The address or data lines can be in the high state or low state
at any give time. The lines here are shown in the high state.
CXO-1225A

11-6

HSC70 MEMORY MODULE

Figure 11-4 Control Memory Read Cycle Timing
- - - 300 ns - - - - - - CGRANT L
CADR n L
CTIMING H
CM SEL H

---------------,~
~--

--,~

L ___

_ _ _ ,J

CACK L
CWRTH/L L
(CM WRT GATE H) _____J

~~------.---

(E121-12)

CM WRT HB/LB L
CM RAS L
CM CLR RAS H

---1L..-_ _ _ ~

_______.____J

CM CAS L

L-.._ _ _ _ _ _

~-,---,J

CM AMUX xx H
ROW

COLUMN

CM T25 L
CM RD CYC L
CM xx OUT H

~--------I

-------.----.~

\----------- - - - - - -

CDATA n L

NOTE:

The address or data lines can be in the high state or low state
at any give tim.e. The lines here are shown in the high state.
CXO-1226A

11-7

HSC70 MEMORY MODULE

11.4.4
Control Memory Refresh Cycle
The dynamic RAMs used in Control Memory require that all rows within the RAM be refreshed every
four milliseconds to ensure data retention. A refresh timer circuit on the P.ioj provides a signal called
CREFRESH CLK H approximately every 15 microseconds to ensure that all 128 rows are refreshed
within the required 2-millisecond period.
Refresh requests are given the highest priority in the arbitration logic on the P .ioj . No data is transferred
across the Control Bus during a refresh cycle, nor does Control Memory generate CACK L or drive the
CDATA lines.
The arbitrator asserts CREFR GRANT L, notifying the Control Memory that a refresh cycle is to be
performed. The refresh cycle begins when CTIMING H is asserted. An eight-bit refresh address counter
on the Control Memory supplies the address of the row to be refreshed. The counter is enabled by
CREFR GRANT L and is incremented by the negation of the CREFR GRANT L signal.
Refer to Figure 11-5 for a timing diagram of the Control Memory refresh cycle.
11.5 DATA MEMORY
Data Memory resides on the Data Bus. Refer to Figure 11-6 and the print set.
Data Memory supports 256 Kwords of memory. It uses 64Kxl static RAMs because of the high speed
requirements of the Data Bus. It is organized as 4 banks of 18 RAMs each designated as banks zero,
one, two, and three.
Each bank is 18 bits wide (16 data bits plus 2 parity bits) and 64 Kwords deep. Either data byte may be
written separately using the signals DWRTH Land DWRTL L.
The following sections describe each of the components shown in the Data Memory block diagram.
11.5.1
Data Memory Address Receiver/Driver
The Data Memory Address Receiver/Drivers, consisting of four 74F240 buffered line drivers, supply
addresses to the RAMs for read and write cycles. Two supply addresses to banks zero and one, and
two supply addresses to banks two and three. They are always enabled. The address lines on the Data
Bus are labeled DADR < 15:00 > L.
11.5.2
Data Memory Timing Logic and RAM Drivers
The Data Memory Timing Logic generates required RAM timing and bus interface timing for Data
Memory. Data Memory timing depends on a 74F158 multiplexer, steered by the SLOW CYCLE L
signal, to select taps of a delay line for discrete tinling modes. The Data Bus cycles are synchronized
by the requestor which has been granted control of the bus with the signal CLK B H. Both are 150
nanoseconds long.
A 74FOO is used to drive the write signals DWRTH Land DWRTL L to the RAMs for writing either or
both bytes.
11.5.3
Data Memory Select Logic
The select logic compares the address on the DADR lines and generates DM SEL and DACK if the
address is in the range of the installed memory. DNMA H disables the select logic because Data
Memory is not selected for a non-memory access cycle. (The requestors use the non-memory access
cycle for diagnostic purposes in checking the operation of the DADR and DDATA lines.)

11-8

HSC70 MEMORY MODULE

Figure 11-5 Control Memory Refresh Cycle Timing

1 - - - - - 300 ns
CREFR GRANT L
CM REF CYC L

11-___._________---'
I~

_____________r__

CM SEL L
CTIMING H

__r

CACK L
CWRTH/L L
CM WRT HB/LB L
CM RAS x L

--1

CM CLR RAS H

CM CAS x L
CM AMUX xx H
CM RD CYC L
NOTE:

The address or data lines can be in the high state or low state
at any give time. The lines here are shown in the high state.

GXO-1227A

11-9

Figure 11-6 Data Memory Block Diagram

n
.....
o

256 KBYTES

...
DDATA< 15:00>
y

m
==
==
o

II.

ADDRESS
RI:CEIVERS/
DRIVERS

OM A< 15:00> A

DATA
MEMORY
ARRAY
BANK 0 AND 1

-I

==
o
c

P06

CLK B DWRTHDWRTL +5

~
=-

DNMADADR(17)-

,..

c:
RAM
DRIVER

TIMING
LOGIC

P04

-vvv- WREN

DATA
OUT

Ivvv-

OM RD CYC
P04 - OM WRT CYC
-DMSEL
OM BANK SEL 0
-DACK
OM BANK SEL 1
SELECT
LOGIC

THIRTY·SIX
64KX1
STATIC RAMS
CSO
CSl

r..

~rI

P04

DATA IN

P07
I\.

\
I
v

OM
<15:00)
HP,
LP OUT

256 KBYTES
t..

DADR <15:00>

ADDRESS
RECEIVERS/
DRIVERS

DM NMA-

r..
DDATA( 15:00>

DATA
MEMORY
ARRAY
BANK 2 AND 3

...A

OM A <15:00>B

[

P06
DADR<16>_
DADR <17>-

WREN

I-vvv-BANK
SELECT

hvvv
h

......
vvv

P06 ~vv

DATA
RECEIVERS

DDATA HPDDATA LP P05

r--

OM BANK SEL 2
DM BANK SEL 3

OM <15:00> ,HP,LP IN

f-f--

CS2
CS3

DATA
OUT ~

DATA
DRIVERS

DDATA < 15:00>

t - DDATA HP

l - DDATA LP

ENB

P06

OM RD CYC

THIRTY·SIX
64KX1
STATIC RAMS

~ DATA
)

IN
POB
CX-962A

HSC70 MEMORY MODULE

11.5.4
Data Memory Bank Select Logic
The Data Memory bank select logic selects one of four banks of RAM available" to Data Memory. The
bank select logic consists of one 74F139 one~of~four decoder. It is enabled by the negation of DNMA H
(a non~memory access cycle is not in progress). Signals DADR 16 Land DADR 17 L select one of the
four banks as shown in Table 11-1.

Table 11-1 Memory Bank Selection
DADR 17

DADR 16

Bank Selected

000
011
102
113

11.5.5
Data Memory Data Receivers
The Data Memory data receivers, consisting of three 74F240 buffered line drivers, supply data to the
RAMs on a write cycle. They are always enabled by the signal DM OE L. The data and parity bits to be
written are driven onto the DDATA < 15:00,HP,LP> L lines by the active requestor and passed through
the driver to the RAM inputs DM <15:00,HP,LP> IN H.
11.5.6
Data Memory Data Drivers
The Data Memory data drivers supply data to the Data Bus out of RAM on a read cycle. The Data
Memory data drivers, three 74F240 buffered line drivers, are enabled only on a read cycle by the signal
DM RD CYC L. When the drivers are enabled, the data as well as the parity bits are driven onto the
Data Bus lines, DDATA <15:00,HP,LP> L.
DATA MEMORY CYCLES
11.5.7
During a Data Bus cycle, the Data Memory executes one of the following three cycles:
Idle
Write
Read
The static RAMs used in Data Memory do not require refresh cycles. Each of the three cycles are covered
in the following sections. Refer to the timing diagrams supplied for write and read cycles.
11.5.7.1
Data Memory Idle Cycle
An idle cycle occurs when there is no active requestor or when an NMA (non"memory access) cycle
occurs. During these cycles, the signal DNMA H forces the Data Memory select logic not to select Data
Memory and forces the bank select logic not to select any bank of Data Memory.

11-11

HSC70 MEMORY MODULE

11.5.7.2
Data Memory Write Cycle
To write to Data Memory, a requestor must first acquire the Data Bus by asserting its request to the bus
arbitrator on the P.ioj. Once the requestor receives the assertion of DGRANT L from the pjoj, it has
possession of the Data Bus for that cycle.
At this point refer to Figure 11-7 for a timing diagram of the Data Memory write cycle.
With the assertion of DGRANT L, the active requestor asserts the address to be written on the DADR
< 17:00 > L inputs of the address receiver/drivers which supply the address to the RAM address input lines. The data and parity bits to be written are put on the data receiver input lines (DDAT A
< 15:00,HP,LP> L) and the write enables (DWRTH Land DWRTL L) are asserted.
When the RAMs receive the address and one or both of the write enable lines are asserted, the cycle
begins writing to the address received on the DADR lines.
Data Memory generates write enable pulses for one or both bytes as needed. eLK B H is used with a
delay line to generate the DM WRT PULSE H signal.
11.5.7.3
Data Memory Read Cycle
To read from Data Memory, a requestor must first become active by asserting its request to the P.ioj
arbitration logic and receiving the asserted DGRANT L signal.
At this point refer to Figure 11-8 for a timing diagram of the Data Memory read cycle.
With the assertion of DGRANT L, the requestor asserts the address to be read on the DADR < 17:00 > L
lines of the Data Memory Address Receiver/Drivers. The output of the receiver/drivers are to the RAM
address input lines (DM A < 15:00> H). The write enables, DWRTH Land DWRTL L, are negated as
is the DNMA signal.
When Data Memory receives the address with the write enable lines negated, it begins the read cycle
from the address on the DADR lines. The memory drives the data read, plus parity, onto the DDATA
lines as long as both write enables and the DNMA signals remain negated and the address remains
valid.
11.6 PROGRAM MEMORY
Program Memory, residing on the Program Bus, performs a read or a write cycle as directed by the pjoj
or the K.rx, whi<;hever has been granted control of the Program Bus. Refer to Figure 11-9 and the print
set. Program memory also performs refresh cycles every 15 microseconds as directed by the P .ioj signal
PREFR eLK H.
Program Memory is logically organized as two banks, each 18 bits wide (16 data bits and 2 parity bits)
and 256 Kwords deep. Either data byte may be written to separately with the signals BWTBT Land
BDAL 00 L. The signals BDAL 19 (which becomes PM 19 IN L) and SWAP PM BANK are used to select
one of the two banks as shown in Table 11-2.

11-12

HSC70 MEMORY MODULE

Figure 11-7 Data Memory Write Cycle Timing

150 ns
CLK B H
OAOR n L

.---.1

---.I
~

--.S

OM SEL L
OACK L

OWRTH/L L

OM WRT CYC L

OM WRT GATE L

OM WRT HB/LB L

---.I

~.--~-

~
~

OOATA n L

---.I

OM xx IN H

OM BANK SEL x L -~______________--'
OM AOOR xx H

L,_ __

OM RO CYC L
NOTE:

The address or data lines can be in the high state or low state
at any give time. The lines here are shown in the high state.
CXO-1228A

11-13

HSC70 MEMORY MODULE

Figure 11-8 Data Memory Read Cycle Timing
150 ns

-.r

CLK B H

DADR n L

-.r

DM SEL L

DACK L

DWRTH/L L

DM WRT CYC L

_----.r-

DM RD CYC L

DM WRT GATE L

--.r--

DM WRT HB/LB L
DM BANK SEL x L

DM ADDR xx H

_----.r-

DM xx OUT H
DDATA n L
NOTE:

""-r-

The address or data lines can be in the high state or low state
at any give time. The lines here are shown in the high state.
CXO-1229A

11-14

Figure 11-9

Program Memory Block Diagram

I-------.....J~'\I
PM<15:00> IN

BDAL< 17:00>

PM SYNC -

ii-

BDAL
BUFFER

COLUMN
ADDRESS
LATCH
~
LE
OE

..
--,I

Pll

l ~g~RESS

RAM
ADDRESS
DRIVER

PM AMUX< 8:0>

ADR

Pl1

WRT HI BYTE
WRT LO BYTE

L - I LATCH
I---,
PM SYNC - I - - - - LE
PM COL ADR ENPM ROW ADR EN
OE
P11
P11

PM LCAS

rr~
r~

f-'\ DIN

512 KBYTES
PROGRAM
MEMORY
ARRAY
BANKO
EIGHTEEN
256 KXl
DYNAMIC RAMS

i--

r-~
r--

P12

f\.

BDAL< 21 :20»
V

ADDRESS
DECODE
LOGIC

BBS7-

P10

~
~

PM SEL

8-BIT
REFRESH
I-ADDRESS
COUNTER
Pl1

PM SELPREFR CLKPM DOUT-

RAM
DRIVERS

PM WRT REG
PM REF IN PROG-

PM RAS 1

PM WRT REO
PM RD REO
PM REF IN PROG

I J

~ <

}

P12

I--PM COL ADR EN

PM 15:00,HP,LP OUT

RAM
TIMING
LOGIC

PM RD REOPMWR REORAM
DRIVERS

P09

BDIN_
P09

BDOUTBRPLY-

BANK
SELECT
LOGIC
P09

I--

BINITPM 191NPM SYNCSW APPM BANK-

I--

EIGHTEEN
256KXl
DYNAMIC RAMS

PM UCAS
Pl0

PM REF REO

PM CLR REF ---I .
PM CLR RD/WRT REO

DOUT

BANK1

PM RASO

I--PM ROW ADR EN

MEMORY
REOUEST
LOGIC

PROGRAM
MEMORY
ARRAY

---

r-I"AA

)

BSYNCBWTBT _

DIN

.",,,,, ....

WRITE
BYTE
DECODE
LOGIC
Pl0

512 KBYTES

PM<OO>INPM SYNCPMWTBT-

ADR

..J\

PM REF IN PROG-

(J1

~
~

DATA
DRIVER
CONTROL
AND
BRPLY
LOGIC

PM LATCH
DATA

BDAL <17:00>

....0(")

DATA
DRIVERS

==
m
==
0

PM ENB D
DRVRS

Pl0

Pl0 -BRPLY

==
0
0

BOCOK -

,..m

c:
P09
CX-963A

HSC70 MEMORY MODULE

Table 11-2

Program Memory Bank Select

BDAL 19

SWAP PM BANK

Logical Bank
Selected

Physical Bank
Selected

The following sections describe each of the components shown in the Program Memory block diagram.
11.6.1
Program Memory BDAL Buffer
The BDAL buffer is three 74L5244 octal buffers. They receive an address from the P.ioj or K.rx,
whichever is in control of the Program Bus. The buffers are always enabled by the signal PM OE
L. The outputs of the BDAL buffers (PM < 15:00> IN L) are applied to the row and column address
latches. After the address has been latched into the row and column address latches, the BDAL lines
receive data from the P.ioj or K.rx to be written to the RAMs.
Program Memory Rowand Column Address Latches
11.6.2
The Program Memory Rowand Column Address Latches supply row and column addresses to the RAM
Address Driver. The row and column address selection is done with four 745373 eight-bit latches. The
signals PM < 15:00> IN L are the inputs of the latches. The enable is the signal PM ROW ADR EN L for
the row address latch and PM COL AOR EN L for the column address latch. The clock for both latches
is PM SYNC L. The enables and clock for the row and column address selection come from the timing
and Program Memory selection logic.
11.6.3
Program Memory RAM Address Driver
The RAM Address Driver supplies the addresses to RAM for read, write, and refresh cycles. The
Program Memory RAM Address Driver is a series of 74537 drivers. The outputs of the row and column
address latches are applied to the RAM address inputs as signals called PM AMUX < 8:0 > H.
11.6.4
Program Memory Data Driver Control and Reply Logic
The Data Driver Control Logic controls the reading and writing of data through the Program Memory
data drivers. The read request and write request signals, as well as the read and write control signals,
are inputs to the logic. The outputs of the logic control the clock and enable of the data drivers.
The reply logic signal BRPLY L is dependent on a P.ioj or K.rx signal BDIN for a read cycle or BOOUT
for a write cycle. This logic contains a flip flop for the read path and a flip flop for the write path.
11.6.5
Program Memory Data Drivers
The Program Memory Data Drivers supply data out of RAM to the Program Bus on a read cycle. The
data driver logic consists of three 745373 eight-bit latches. They are enabled by the signal PM ENB 0
ORVRS L and clocked by the signal PM LATCH DATA L. On a read cycle, data plus parity is taken
from the RAM outputs, PM < 15:00,HP,LP > OUT L, and clocked out on the BOAL < 17:00 > L lines to
the P.ioj or K.rx.

11-16

HSC70 MEMORY MODULE

11.6.6
Program Memory Eight Bit Refresh Address Counter
The Program Memory Refresh Address Counter supplies refresh row addresses to the RAMs during
refresh cycles.

The refresh counter is a 74LS590 eight-bit counter. The outputs of the row and column address drivers
are disabled for a refresh cycle. The signal PM REF IN PROG L enables the refresh counter output and
causes the row and column address drivers to supply a refresh address rather than a memory address
to the RArvls. This refresh address is incremented at the end of every refresh cycle.
11.6.7
Program Memory Address Decode Logic
Program Memory is selected for all address combinations· that do not assert BBS7 L, BDAL20 L, or
BDAL21 L.
11.6.8
Program Memory Write Byte Decode and RAM Driver Logic
The Write Byte Decoder (byte select logic) is a 74LS74 flip flop and two 74S00 NAND gates. During a
word write, the flip flop is ignored and both bytes are written. During a byte write, the flip flop captures
the state of address bit zero (bit zero selects which of the two bytes is written).

Logic consisting of a 74S37 NAND gate applies the outputs of the byte select flip flop plus the signal
PM WRT ENB H to the selected RAMs for writing the high or low bytes.
11.6.9
Program Memory Request Logic
The Program Memory Request Logic consists of several flip flops servicing the types of requests Program
.Memory can respond to. The requests valid for Program Memory are:

Read
Write
Refresh
11.6.10
Program Memory RAM Timing Logic
The RAM Timing Logic consists of a 74S64 AND-OR-INVERT gate and delay lines. The types of requests
available from the request logic are monitored by the gate, and the applicable timing is generated
depending on the gate input that is true.
11.6.11
Program Memory Bank Select Logic and Program Memory RAM Driver
The Bank Select Logic selects one of the two banks of Program Memory available. The state of the signal
PM 19 IN L determines which bank is selected. The bank select flip flop captures the state of PM 19 IN
L and applies it to two NAND gates for the selection of the upper or lower bank. If the signal SWAP
PM BANK H is asserted, the signal PM 19 IN L is inverted and the other bank of RAM is selected.

The Program Memory RAM Driver logic performs two functions. The output of the Bank Select Logic
selects the lower or upper banks of Program Memory, and the output of the RAS flip flop strobes the
desired row address. The row address strobe signals are PM RAS 0 L and PM RAS 1 L. The output
signals for bank selection are PM LCAS L and PM UCAS L. Once the row has been selected, the bank
select signals are supplied to select either the lower or the upper bank of RAMs.
11.6.12
PROGRAM MEMORY CYCLES
As stated earlier, Program Memory performs a write, read, or refresh cycle. The write and read cycles
are initiated by either the P.ioj or the K.rx. The refresh cycle is initiated by the P.ioj.' Refer to the timing
diagrams supplied for write and read cycles.

11-17

HSC70 MEMORY MODULE

11.6.12.1
Program Memory Write Cycle
Refer to Figure 11-10 for a timing diagram of the Program Memory write cycle.
To initiate a write cycle, the bus master for that cycle (P.ioj or K.rx) asserts an address to be written to
on the BDAL lines while asserting BWTBT L. The bus master then asserts BSYNC L. The address on
the BDAL lines is latched into the address latches. The bus master then asserts the data and parity bits
to be written on the BDAL lines. The signal BDOUT L is asserted and the Program Memory write cycle
begins. The signal BRPLY L is asserted at this time.
If a refresh is not in progress, the write cycle begins as soon as BOOUT L is received. If a refresh cycle

is in progress, the write cycle is delayed as much as 330 nanoseconds, one internal memory cycle, until
the refresh is completed. Byte writes are accomplished by asserting BWTBT L before issuing BOOUT
L. The BDAL 00 L signal determines which byte is to be written.
When the write cycle is finished, BOOUT L is negated. Program memory then negates BRPLY L.
11.6.12.2
Program Memory Read Cycle
Refer to Figure 11-11 for a timing diagram of the program memory read cycle.
To initiate a read cycle, the bus master asserts an address on the BOAL lines to read from. BWTBT L is
negated to indicate a read cycle and BSYNC L is asserted. This starts the internal timing sequence for
a read cycle.
If a refresh is not in progress, the data is read from RAM and latched in the data drivers. The data is

held in the data driver latch until receiving BOIN L, at which time the data is driven out onto the BOAL
lines. The reply signal, BRPLY L, is then asserted.
If a refresh was in progress, the read cycle is delayed as much as 330 nanoseconds, or one complete

memory cycle, until the refresh cycle is completed.
When the data has been gated onto the BDAL lines, BOIN L is negated and BRPLY L is negated. The
data is removed from the BDAL lines.
Program Memory Refresh Cycle
11.6.12.3
Program Memory RAMs require refresh cycles to ensure data retention in the dynamic RAMs. A refresh
circuit on the P.ioj supplies refresh requests to the Program Memory every 15 microseconds. If a refresh
request is supplied while a read or write cycle is in process, the request is queued until the present cycle
is finished. Similarly, if a read or write cycle is received while a refresh is in process, the read or write
request is queued until the refresh cycle is complete.
An Eight Bit Refresh Address Counter in the Program Memory provides the row address to be refreshed.
This address is incremented at the end of every refresh cycle. The column address strobe (CAS) is not
needed for refresh.
Refer to Figure 11-12 for a timing diagram of the Program Memory refresh cycle.
11.7 FLOPPY DISK CONTROLLER
The Floppy Disk Controller, or K.rx, residing on the Program Bus, performs direct memory access
(DMA) word transfers when reading or writing. The minimum data transfer size in one comnland is
512 bytes (one sector). The maximum data transfer size in one command is one track (512 bytes x 15
sectors). At the end of a data transfer an interrupt is generated.
The main controlling chip for the K.rx is the 2797. It is also known as the Floppy Disk Controller
(FDC) and will be referred to as the FDC in this document. It controls the software-to-hardware and
hardware-to-software conversions between the RX33 floppy disk drives and the K.rx.
Pre-programmed PALs are used to control the steering and timing of the K.rx internal data path.
11-18

HSC70 MEMORY MODULE

Figure 11-10 Program Memory Write Cycle Timing

BSYNC L
BDAL xx L

~===x

ADDRESS
PM SEL H
BWTBT L

____.____.______________ ___x===
DATA

l _ L____________ · ___~=
HI = Word

BDOUT L

La = Byte

L-,__

BRPLY L
PM WRT REQ L

~,--

PM ROW ADR EN L

__J
11-._-

PM RAS L

~--

-~-

___J

PM COL ADR EN L
PM CAS L
PM AMUX xx H
PM WRT CYC H

,_______==x

"_~-

---------------~~

PM WRT HI/La BT L - - - - - - - - - - - - - - - - ,
NOTE:

.---~

The address or data lines can be in the high state or low state
at any give time. The lines here are shown in the high state.
CXO-1230A

11-19

HSC70 MEMORY MODULE

Figure 11-11

Program Memory Read Cycle Timing

BSYNC L
BDAL xx L

r--

=x=DATA

~=---x.
ADDRESS

PM SEL H

PM RD REQ H

_r-

BWTBT L

==x==

~-------y

PM ROW ADR EN L
PM RAS L

~------------------------~,----~

PM COL ADR EN L -----,' - -_ _ _ _ _,---1r - PM CAS L

PM AMUX xx H

----~

PM RD CYC H

---~

PM xx OUT L

~----------------------~-

------------~

PM LATCH DATA L

\~-------------------~.

_________________

~r_-

BDIN L

L -_____J

BRPLY L

L-.___________-.J

PM ENB D DRVRS L -------'-------L-,______ ~NOTE:

The address or data lines can be in the high state or low state
at any give time. The lines here are shown in the high state.
CXO-1231A ,

11-20

HSC70' MEMORY MODULE

Figure 11-12

Program Memory Refresh Timing
15 micro sec/CYCLE

_ _J

PREFR CLK H

PM REF REQ H

__S -

__I

PM REF IN PROG H .~
PM REF T75 H

--~

PM SEL H
BRPLY L

PM ROW ADR EN L __~
PM RAS L

_____

-L-___-----'r

PM CLR RAS L
PM COL ADR EN L
PM CAS L
PM AMUX xx H
PM TO H
NOTE:

"----

-.~

__r-

~------

The address or data lines can be in the high state or low state
at any give time. The lines here are shown in the high state.
CXO-1232A

11-21

HSC70 MEMORY MODULE

The starting memory word address for any data transfer is loaded into a 22-bit Memory Address Register
(MAR). It is a physical memory address as opposed to a virtual memory address. The MAR will autoincrement by two at the end of each word transfer.
Byte parity is checked or generated for all data transfers to and from memory. Odd parity is used.
A non-existent memory error (NXM) will be detected if a memory reply is not received in response to
each word transferred.
Lost data errors will be detected if the data transfer rate of the K.rx is not maintained by the Program
Bus during a data transfer.
11.7.1
Floppy Controller Registers
The K.rx uses four 16-bit registers to control the floppy disk drives. The low byte of each register is
implemented within the FDC chip while the high byte of each register is implemented external to the
FDC chip. All four registers are word addressable only. These registers are:

•

Command and Status Register, High Byte (CSR HIGH BYTE)

•

Command and Status Register, Low Byte (CSR LOW BYTE *)

•

Current Track Register (TRK REG *)

•

Sector Register (SEC REG *)

•

Data Register, Track Address Register (DAT/TRK REG *)

•

Memory Address Register, Low Byte (MAR 0)

•

Memory Address Register, Middle Byte (MAR 1)

•

Memory Address Register, High Byte (MAR 2)
NOTE
The asterisk (*) denotes the registers implemented
in the FDC chip.

The registers and their bit assignments and addresses are shown in Figure 11-13. Notice the division
between bytes designating actual registers.
A description of each register follows.

11.7.1.1
Command and Status Register (CSR)
The CSR register is the most frequently used. The low byte of the CSR is part of the FDC chip. The
high byte is implemented with an AM2952 eight-bit bi-directional register.

The Command and Status Register high byte is described in Table 11-3.

11-22

HSC70 MEMORY MODULE

Figure 11-13

Floppy Register Bit Assignments
Command/Status Register (CSR)
PAR
ERR

NXM
ERR

INTR DI S IPAR IBUSY MOTR IDRV ICS71 CS61 CS51 CS41 CS31 CS.-2' ICS11 CSo]
ENB RE Q TST LED ENB SEL

11 10
15
14
13 12
Read Read 1 - - - , - - Only Only
I/O Address 17777400

09
08 07
Read/Write

00
1

Memory Address Register 0 (MARO) ~raCk Register (TREG)
IA07 IA06 IA05
15

IAO~IA03IA02 IA01~
12

1-------------------------

09
08 07
Read/Write

CURRENT TRACK ADD_R_E_S_S______]
06

00
1

I/O Address 17777402
Sector Register (SREG)

Memory Address Register 1 (MARl)

IA15 IA14 IA13
15

IA12IA11IA-10~~A-0-9~A-0-8+-'---D-E-S-IR-E-D-S-EC-T-0-R--A-DD--RE_S_S____]
12

09
08 07
Read/Wri te

00
1

I/O Address 17777404
Memory Address Register 2 (MAR2)
GRN
LED

DMA
TST

A21

A2 0IA191A18

A17

Data/Track Register (DREG)

A16

DISK DATA OR

-----]

DESIRED TRACK ADDRESS
12

1--------------------

09
08 07
Read/Write

00
1

I/O Address 17777406
CXO-1233A

11-23

HSC70 MEMORY MODULE

Table 11-3 Command and Status Register Bit Assignments (High Byte)
Bit

Name

Read/Write

Description

Parity Error

Read Only

Sets when bad parity is received in one or both
bytes during a DMA read from memory. Clears
on power-up, when a new command is loaded
into the CSR, when B INIT L is asserted or when
the motor enable bit, bit 9, is cleared.

NXM Error

Read Only

Sets when a reply is not received from memory within ten microseconds of the assertion of
BSYNC L by K.rx during a DMA read or write.
Clears by power-up, when a new command is
loaded into the CSR, when B INIT L is asserted
or when the motor enable bit is cleared.

Interrupt Enable

Re,ad/Write

Prevents unwanted interrupts from K.rx. Must
be set before the interrupt condition occurs or
no interrupt will be generated.

Disable DMA Request

Read/Write

Used by diagnostics to inhibit DMA requests.
Not set in normal application.

Parity Test

Read/Write

U sed by diagnostics to force bad parity for both
bytes when doing DMA writes to memory. Also
detects parity when doing DMA reads from locations that have good parity.

Drive Busy LED

Read/Write

Controls the LED on front of floppy disk drive.

Motor Enable

Read/Write

When clear, keeps K.rx in initialized state by
generating an internal reset similar to the assertion of B INIT L from the P joc. When set, both
drives are spun up and a seek to track zero is
performed.

Drive Select 011

Read/Write

Selects one of the two floppy disk drives. Clear
selects drive zero, set selects drive one.

The CSR Registers low byte, CSR BITS < 7:0 >, when written to, represent the Command Register.
When read back they represent the Status Register. The Status Register bits are dynamically defined;
they change context depending on the type of 'command last issued. Commands will be discussed in
more detail in Section 1l. 7.4.
11.7.1.2
Memory Address Register O/Track Register (MARO/TREG)
MARO and the Track Register are byte-wide registers paired as a single, word-wide register, jointly
accessible as a word. MARO is the high byte of the word.

11-24

HSC70 MEMORY MODULE

11.7.1.2.1
MARO <15:8>, Read/Write
MARO is loaded with the lowest eight bits of the desired memory transfer address, A < 07:00 >, prior
to issuing a DMA read or write command. It auto-increments by two at the end of each DMA word
transfer. The carry out of MARO is the carry in to MARL
This register is cleared on power up or when BINIT L is received.
11.7.1.2.2
Track Register <07:00>, Read/Write
The Track Register is read to determine the head location on a selected drive. It increinents by one every
time the head is stepped in (away from track zero) and decrenlents by one when the head is stepped
out (toward track zero).
This register is not directly initialized by power up, BINIT L, or clearing the motor enable bit, but the
seek resulting from the power up or BINIT L loads the track register with zeros.
Memory Address Register l/Sector Register (MARlISREG)
11.7.1.3
MARl and the Sector Register are byte-wide registers paired as a single, word-wide register, jointly
accessible as a word. MARl is the high byte of the word.
MARl < 15:08 >, Read/Write
11.7.1.3.1
MARl is loaded with the middle eight bits of the desired memory transfer address, A < 15:08>, prior
to issuing a DMA word transfer. It auto-increments by one at the end of a DMA word transfer if the
carry-out bit of MARO is asserted. The carry out of MARl is the carry in of MAR2.
This register is cleared on power up or when BINIT L is received.
11.7.1.3.2
Sector Register <07:00>, Read/Write
This register is loaded with the desired sector position. The register contents are compared with the
recorded sector number in the 10 field of the media during floppy read or write operations. The Sector
Register will auto-increment during multi-sector transfers until it contains a sector humber that is one
greater than the number of sectors per track (for example: 208) causing a record-not:fdund error.
This register is initialized to 0018 on a power up, when BINIT L is asserted, or when the Motor Enable
bit goes frorn clear to set.
Memory Address Register 2/Data Register (MAR2/DREG)
11.7.1.4
MAR2 and the Data Register are byte-wide registers paired as a single word-wide register and are only
accessible jointly as a word. MAR2 is the high byte of the word.
11.7.1.4.1
MAR2 <21:16>
MAR2 is loaded with the highest six bits of the desired memory transfer address, A <21:16>, prior to
issuing a DMA read or write command. It auto-increments by one at the end of a DMA word transfer
if the carry-out bit of MAR 1 is asserted.
11.7.1.4.2
MAR2, Bit 15, Module OK LED
Bit 15 is the module OK bit. It is set to light the green LED (module OK) on the M.std2 module. Bit 15
is cleared to light"the red LED (module BAD). It is not an address bit.

11-25

HSC70 MEMORY MODULE

11.7.1.4.3
MAR2, Bit 14, Enable DMA Test
Bit 14 is the Enable DMA Test bit. It is set to test DMA transfers without having a floppy disk drive
connected to the FDC. When set, the FDC does not drive the floppy interface signals. This guarantees
that a DMA test doing a write sector operation cannot inadvertently write on the floppy media. Although
the motor enable bit may be set, DMA Test will spin down the motors. Bit 14 is not an address bit.
All bits of the MAR2 register are cleared on power up or when BINIT L is asserted.
11.7.2
Data Register
The Data Register is loaded with the address of the desired track position on a seek command. The
contents of this register are compared with the current track number in the Track Register to determine
in which direction and how far to step the head.
During the read or write operations, the Data Register is used as a holding register and serves as the
port for data byte loading and unloading to the Memory Data Register (MDR). The MDR, sometimes
known as the XBUF/RBUF, is discussed in Section 11.7.3.4.
11.7.3
K.rx Floppy Controller Block Diagram
The following paragraphs describe the K.rx components. Refer to Figure 11-14 and the print set.
Program Bus Register Selector, Synchronizer, Register Control PAL
11.7.3.1
The Program Bus Register Selector is a DC004 which receives the BDAL < 02:00 > L lines and the bus
control signals, BSYNC L, BWRTBT L, BDIN L, and BDOUT L. These signals are used for reading and
writing the K.rx registers. The Register Selector is enabled by the signal RX MATCH H. The outputs of
the DC004 are the inputs to a bank of D flip flops contained in a 74F374 labeled the Synchronizer on
the block diagram. The outputs of the Synchronizer are fed into two 16R8 PALs, the Register Control
PAL (REGCTL), and the RX Control PAL (RX CTL). The Synchronizer, the Register Control PAL, and
the RX Control PAL are clocked by the signal PAL CLK H and are always enabled by the signal TS
OE L. The Register Control PAL takes the REG SEL x L signals from the Synchronizer and outputs the
signals needed to read and write the Floppy Disk Controller Memory Address Registers (MARs). The
RX Control PAL uses the same signals from the Synchronizer for reading and writing the Control and
Status Register (CSR.)
11.7.3.2
Program Bus Transceivers and Vector Control, High Address Driver
The Program Bus transceivers consist of four DC005 bi-directional chips. When receiving, the transceivers
receive the BDAL < 15:00 > L signals from the Program Bus and turn them into RX D < 15:00> H signals
that the K.rx can use as data lines. When transmitting the RX D < 15:00> H signals are driven onto the
Program Bus BDAL lines. The DC005s are labeled BUS INTERFACE. The high address driver (74LS240)
takes the RX D<21:16> H signals plus a write command and converts them back to BDAL signals and
a BWTBT L signal for transmission on the Program Bus.
11.7.3.3
Parity Generator/Checker
The K.rx parity generator/checker consists of two 74LS280 parity generators. They take the RX D < 15:00 >
H signals from the Program Bus transceiver:s and generate the odd parity bits BDAL 17 Land BDAL
16 L. The checking is done by routing the parity bits, now called RDAL<17:16>, back to the 74LS280s
through exclusive OR gates. The signal PAR TST H, a bit from the Control and Status Register, is used
during diagnostics to force reading or writing with bad parity. This is a check for the 74LS280s.

11-26

HSC70 MEMORY MODULE

11.7.3.4
Interrupt Control and Vector Timing
Interrupt: control and vector timing is done with a DC003 labeled on the print S"I,~t as UNIBUS INTERRUPT. The signal INTR REQ H from the FDC chip initiates an interrupt if INTR ENB H is set in the
CSR. The P.ioj responds with BIAKI L (interrupt acknowledge) and BDIN L. The ~.. rx sends the interrupt
vector of 230 (octal) to the P.ioj along with BRPLY L. Interrupts are generated at the end of a command
if the INTER ENB H bit is set in the CSR. The interrupt may indicate successful completion or an error.
The CSR must be examined to determine the results.
11.7.3.5
DMA Control
DMA control is done with a DC010 and is labeled DIRECT MEM ACCESS on the print set. The signal
DMA REQ H, originally from the Disk Read and Disk Write PALs, initiates the DMA cycle by asserting
BDMR 1.. After asserting BDMGI L, the signals MASTER H, TSYNC H, TDIN H, TDOUT H, ADR EN
H, and DATA EN H are generated appropriately. These signals are applied to .l bus driver (74LS240)
to generate the bus control signals, BSYNC L, BDIN L, BDOUT L, and BSACK ,.
11.7.3.6
Disk Read PAL, Disk Write PAL
The disk read and disk write logic is contained in two separate 16R8 PALs labeled respectively DISKRO
and DISKWR on the print set. They are clocked by the PAL CLK H signal and always enabled by TS
OE L. The Disk Read PAL receives key timing events applicable to reads and outputs read data path
control signals. The Disk Write PAL receives key timing events applicable to writes and outputs write
data path control signals.
Memory Address Register (MAR)
11.7.3.7
The three memory address registers are 20X8 PALs. Each is individually loaded by the register control
PAL with the signals LO MAR x L. They are clocked by PAL CLK H and always enabled by TS OE L.
The inputs are the RX data lines RX 0 < 15:8> H. These inputs are used to load the starting memory
address for the data transfer about to begin. After a word is transferred, the MA R is auto-incremented
by two.
11.7.3.8
Non-existent Memory Detection
The non-existent memory (NXM) detection logic consists of a 74LS123 one-shot tlnd a 74LS74 flip-flop.
The flip-.flop detects the timeout of the one-shot. A timeout occurs when K.rx transfers a word to or
from memory and a memory reply is not received within 10 microseconds. Wher: a timeout is detected,
the signal NXM ERR L is generated.
11.7.3.9
Floppy Disk Controller 2797 (FDC)
The 2797 Floppy Disk Controller is the main controlling chip for the K.rx. The 2797 is an LSI chip
designed to be a one chip floppy interface controller. This chip provides the hardware/software interface
by converting software commands loaded into the data/track register, sector regi~,ter, track register, and
CSR into signals which are sent to the floppy drive to cause it to seek, read, or write. Hardware signals
from th~~ floppy drive are converted into data and status which are read by softh/-are. The RX D< 7:0 >
H signals provide the software/hardware interface signals.

11-27

HSC70 MEMORY MODULE

Figure 11-14 K.rx Controller Block Diagram

BSYNC
BWTBT
BDIN
BDOUT

PROGRAM
BUS
REGISTER
SELECTOR

SYNCHRONIZER

BADL<2:0>
P13

P13

HI ADDR
DRIVER

BDAL<21: 16>

P13

BADL<15:00>

PROGRAM
BUS
TRANSCEIVERS
AND
VECTOR
GENERATOR

RX
CONTROL
PAL

2797
R/W
CONTROL

RX D <15:0>
P14

P13
A

KEY TIMING EVENTS

BDAL<17>
BDAL<16>

PARITY
GENERATOR/
CHECKER
P13
PARITY
TEST

BIRO 4BIAKi -

DISK
READ
PAL

~ READ

DATA PATH
CONTROLS

P13
PAR ERR

KEY TIMING EVENTS

INTERRUPT
CONTROL
AND
VECTOR
TIMING
P13

DISK
WRITE
PAL

WRITE
DATA PATH
CONTROLS

P13

RX D<O>
BDMR
BDMGI

BDIN
BDOUT
BSACK

RX D <15:8>

DMA
CONTROL

BSYNC
BUS
DRIVER
P13

MASTER

22 BIT
MEMORY
ADDRESS
REGISTER/
COUNTER

RX D<21:17>

RX D< 16:9)

RX D<8:1>

P13

DMA
REO

INCREMENT
CX-964A

Sheet 1 of 2

(Continued on next page)
11-28

HSC70 MEMORY MODULE

Figure 11-14 (Cont.)

K.rx Controller Block Diagram

BSYNC?OUS NXM ERROR
PAL
CLK

P14

...--_ _ _.....,

CABLE TO
FLOPPY
DRIVES
CABLE
RCVR

CLR NXM

CABLE
DRIVER
OSC
4MHz

DIVIDE
BY2
RX 0<7:0>

RLS

WD2797
FLOPPY
DISK
CONTROLLER

P15

CONTROL
INPUTS
RAW READ
DATA IN

P15

CONTROL
OUTPUTS
DATA
SEPARATOR
WRITE
PRECOMP P14

WRITE
DATA OUT

RX 0 <15:8>
16-BIT
RBUF/XBUF
MDR
REGISTER

RX 0<7:0>

RX 0<7:0>
P14

DISK
COMMAND
REGISTER

DISK
FUNCTION

P15

RX 0<13:8>

COMMAND
AND
STATUS
REGISTER

MODE
CONTROL

P15
NXM ERROR
PAR ERROR

ERROR
REGISTER
BUFFER

RX 0<15:12>

P14
RD CSR

CX-964A
Sheet 2 of 2

11-29

HSC70 MEMORY MODULE

The FDC also generates and checks cyclic redundancy checks (CRC) for all data transfers. An on-chip
data separator receives encoded read data and generates separate data and clock on a read cycle. A
write precompensation circuit compensates for predictable magnetic shifting effects when writing to the
floppy drive.
A 4 MHz crystal oscillator with a divide-by-two flip-flop provides the timing for the FDC.
NOTE
The 4 MHz oscillator also provides the PAL CLK.
The Floppy Disk Controller has two potentiometers and a switch that are set at the factory and are not
to be adjusted in the field. The potentiometer connected to WPW (pin 33) adjusts the write precompensation. The potentiometer connected to RPW (pin 18) adjusts the data separator. The switch connected
to VCO (pin 26) adjusts the data separator.
11.7.3.10
RBUF/XBUF Register (MDR)
The 16-bit RBUF/XBUF register consists of two 8-bit 2952 registers. It is also known as the Memory Data
Register or MDR. It is used to latch receive or transmit data onto the K.rx data lines (RX D < 15:00 > H).
11.7.3.11
Disk Command Register
The Disk Command Register is a 16R8 PAL. It is labeled in the print set as the FUNDEC, or function
decoder. The Disk Command Register takes as inputs the RX D<7:4> H signals and provides disk
functions as outputs. These disk functions are:
DISK RIW L
LD CSR DLY L
DISK READ L
DISK WRITE L
The PAL is clocked with PAL CLK H and is always enabled with TS OE L.
11.7.3.12
Command and Status Register (CSR)
The command and status register is an 8-bit 2952 read/write register. It is not labeled in the print set but
can be identified by the enable inputs, LD CSR Land RD CSR L. The CSR is clocked by PAL CLK H.
It takes as inputs the RX D < 13:8> H lines, and outputs the first six bits of the high byte of the CSR.
On a read, the high byte of the CSR is read and output on the RX D < 13:8> H lines.
11.7.3.13
Error Register Buffer
The error register buffer is a 74LS240 eight-line driver. Its output control is enabled by RD CSR L. It
passes the NXM ERR L and PAR ERR L signals and loads them into the two most significant bits of the
CSR. These bits are read only.

11-30

HSC70 MEMORY MODULE

11.7.3.14
Cable Driver and Cable Receiver
The cable driver is a DC02l bus transceiver that takes applicable floppy drive signals from the FDC and
drives them over a cable to the floppy disk, drives. It is enabled as long as ENH DMA TEST H is not
asserted. Signals to the floppy disk drives are:
WR DATA L
WR GATE L

DRV SEL 0 L
DRV SEL 1 L
SIDE SEL L
MOTOR ENB L
DIR SEL L
STEP L
IN USE L
The cable receiver, a 74LS244 buffer, receives signals from the floppy disk drives over the cable and
delivers them to the FDC. The receiver is always enabled by the signal TS OE 1. Signals from the floppy
disk drives are:
INDEX L
TRACK 0 L
WR PROT L
RD DATA L
READY L

11.7.4
Floppy Disk Controller Commands
The 2797 Floppy Disk Controller accepts eleven commands. They should be loaded into the CSR only
when the busy status bit, bit 0, is clear. The one exception to this is the force interrupt command which
will be discussed in Section 11.7.4.4. Commands are divided into four types, they are:

•

Seek Commands (type I commands)

•

Read/Write Sector Commands (type II commands)

•

Read Address and Read/Write Track Commands (type III commands)

•

Force Interrupt Command (type IV commands)

Commands and types are summarized in Table 11-4. The bit assignments for each type of command
are discussed in the following sections. The variables in columns 0 through 4 will also be explained.
11.7.4.1
Floppy Disk Controller Disk Seeks (Type I Commands)
Five commands are recognized by the floppy controller as seek or head positioning commands. These
commands are loaded into the command and status register (CSR) when the busy status bit, bit 0, is
clear. These head positioning commands are shown in Table 11-5.

11-31

HSC70 MEMORY MODULE

Table 11-4

Floppy Disk Controller Command Summary
2797 Bit Assignments

Type

Command

Restore

Seek

Step

Step In

Step Out

Read Sector

Write Sector

Read Address

Read Track

Write Track

Force Interrupt

Table 11-5

Head Positioning Commands

Command

Description

If Success

If Failure

Restore

Seek Track 0

Track Reg = 0

Seek Error Set

Seek

Seek Track n

Track Reg = n

Seek Error Set

Step

One Step, Same Oir

Track Reg = n+ 1/-1

Seek Error Set

Step In

One Step In

Track Reg = n+ 1

Seek Error Set

Step Out

One Step Out

Track Reg = n-l

Seek Error Set

The head positioning commands accept four arguments as valid in the low byte of the CSR. Table 11-6
describes these four arguments.

11-32

HSC70 MEMORY MODULE

Table 11-6 Head Positioning Command Arguments
Bits

Action

Location

rlrO

Selects stepping rate of motor

Bits 0 and 1 of CSR

Perform track number verify

Bit 2 of CSR

Head load flag

Bit 3 of CSR

Track update bit

Bit 4 of CSR

11.7.4.1.1
Restore Command
A Restore command is actually a seek to track zero. It is executed following power-up, the assertion of
BINIT L, or when bit 9 of the CSR (motor enable) goes from clear to set. Upon receipt of this command,
the TRACK 0 L signal to the FDC is sampled. If the signal is low, indicating the head is positioned over
track zero, the track register is loaded with zeros and an interrupt is generated. If the signal is not low
(head not over track zero), stepping pulses at the rate specified by the rIrO field are issued from the
FDC until the track zero input is activated. The track register is then loaded with zeros and the interrupt
is generated. If the TRACK 0 L signal is not asserted within 255 stepping pulses, the FDC terminates
the operation, interrupts, and sets the seek error status bit. If the V bit is set in the CSR, a verification
will take place. The h bit allows the head to be loaded at the start of the command.
11.7.4.1.2
Seek Command
A Seek cOInmand requires that the desired track number be loaded into the Data Register before the
Seek command is initiated. A seek error will be generated if a non-existent track number is used. The
track register keeps the number of the current track position. Track zero is the outermost track. The FDC
will update the track register and issue stepping pulses in the appropriate direction until the contents
of the track register are equal to the data register (the desired track location). A verification takes place
if the V bit is set. The h bit allows the head to be loaded at the start of the command. An interrupt is
generated at the completion of the command.
11.7.4.1.3
Step Command
Upon receipt of the Step I:ommand, the FDC issues a one-step pulse to the disk drive. The step motor
direction is the same as the previous step command. A verification takes place if the V bit is set. The
track register is updated if the T bit is set. The h bit allows the head to be loaded on the start of the
command. An interrupt is generated at the completion of the command.
11.7.4.1.4
Step In Command
Upon receipt of the Step In Command, the FDC issues a one-step pulse in the direction of the innermost
track. If the T bit is set, the track register is incremented by one. A verification takes place if the V bit
is set. The h bit allows the head to be loaded on the start of the command. An intenupt is generated at
the completion of the command.

11-33

HSC70 MEMORY MODULE

11.7.4.1.5
Step Out Command
Upon receipt of the Step Out command, the FDC issues a one-step pulse in the direction of the outermost
track (track zero). If the T bit is set, the track register is decremented by one. A verification is done if
the V bit is set. The h bit allows the heads to be loaded at the start of the command. An interrupt is
generated at the completion of the command.
11.7.4.2
Floppy Disk Controller Disk Reads and Disk Writes (Type II Commands)
The type two commands are:
Read Sector
Write Sector
Each will be discussed separately.
11.7.4.2.1
Read Sector Command
The Read Sector command accepts four arguments as valid in the low byte of the CSR. Table 11-7
describes these four arguments.

Table 11-7 Read Sector Command Arguments
Bit

Location

Action

Bit 4 of CSR

o = single sector
1 = multi-sector transfer

Bit 3 of CSR

o = 1024 bytes/sector
1 = 512 bytes/sector

Bit 2 of CSR

o = sample head load timing, no delay
1 = sample head load timing, 15ms delay

Bit 1 of CSR

o = select side zero
1 = select side one

Note: The L bit of the CSR should always have a 1 in that bit position.
Once the head has been positioned over the desired track (cylinder), data may be transferred from
the floppy disk to memory with the Read Sector command. The three bytes of the Memory Address
Register (MAR) must be loaded with the 22-bit starting memory address, and the desired sector address
must be loaded into the Sector Register.
Multiple sector transfers are accomplished by setting the m bit in the command word of the CSR.
Multiple sector transfers are of the form sector x through end of track, x being the value contained in the
Sector Register. Spiraled transfers or transfers crossing track boundaries require nlultiple read sector
commands.
As each bit arrives serially from the disk, it is shifted through a data shift register until eight bits have
arrived. The eight bits are then transferred to the Data Register (DR), and Data Request (DRQ) is set.
The first byte is read from the the DR and loaded into the low byte of the MDR (Memory Data Register)
that acts as a staging register. The second byte is read and loaded into the MDR high byte and a DMA
request is issued.

11-34

HSC70 MEMORY MODULE

Once the K.rx receives the assertion of BDMG I L from the P.ioj, it transfers the assembled word to memory along with correct parity for each byte. Upon completion of the transfer, the MAR is incremented
by two. This sequence continues until all 512 bytes of the sector have been transferred to memory.
The busy bit of the CSR will be set while the read sector command is in progress. A two-byte CRC is
computed as the data is read from the floppy and compared to the CRC read at the end of the data
field. A CRC error will set if the computed CRC and the data field CRC do not match. An interrupt is
generated at the completion of the read sector command. The low order bits of the CSR are redefined
upon completion of the read sector command and must be examined for any errors. They are then reset
when rewritten. These bits are shown in Table 11-8.

Table 11-8 Status for Type II and Type III Commands
Bit

Name

Meaning

Not Ready

This bit, when set, indicates the drive is not ready. \Nhen reset, it indicates
that the drive is ready. The type II and III commands will not execute unless
the drive is ready.

Write
Protect

On Read Sector: not used. On Read Track: not used. On any write: indicates
a write protect. This bit is reset when updated.

Record Type

On Read Sector: indicates the sector type code from data field address mark.
1 = deleted data mark. 0 = data mark. On any write: forced to a zero.

Record Not
Found (RNF)

When set, indicates the desired track, sector, or side was not found. This
bit is reset when rewritten.

eRC Error

If S4 is set, an error was detected in the ID field; otherwise, the error was

in the data field. This bit is reset when rewritten.
S2

Lost Data

When set, indicates no response to the data request output (DRQ). This bit
is reset to zero when rewritten.

Data Request

A copy of the DRQ output. When set, it indicates the data register (DR) is
full on a read or empty on a write. This bit is reset to zero when rewritten.

Busy

When set, a command is being executed. When not set, a command is not
being executed.

11.7.4.2.2 Write Sector Command
The Write Sector command accepts five arguments as valid in the low byte of the CSR. Table 11-9
describes these four arguments.
Once the head has been positioned over the desired track (cylinder), data may be transferred to the
floppy disk from memory with the Write Sector command. The three bytes of the Memory Address
Register (MAR) must be loaded with the 22-bit starting memory address, and the desired sector address
must be loaded into the Sector Register.
Multiple sector transfers are accomplished by setting the m bit in the command word of the CSR.
Multiple sector transfers are of the fornl sector x through end of track, x being the value contained in the
Sector Register. Spiraled transfers or transfers crOSSing track boundaries require multiple write sector
commands.

11-35

HSC70 MEMORY MODULE

Table 11-9 Write Sector Command Arguments
Bit

Location

Action

Bit 4 of CSR

o = single sector
1 = multi-sector transfer

Bit 3 of CSR

o = 1024 bytes/sector
1 = 512 bytes/sector

Bit 2 of CSR

o = sample head load timing, no delay
1 = sample head load timing, ISms delay

Bit 1 of CSR

o = select side zero
1 = select side one

Bit 0 of CSR

o = write data address mark
1 = write deleted data address mark

When the Write Sector command is loaded, the DRQ bit of the FDC sets and the K.rx issues a DMA
request. Once K.rx receives the assertion of BDMG I L from the P.ioj, it transfers one word from memory.
That word is loaded into the Memory Data Register (MDR). Both bytes of the word are checked for correct
parity.
The data in the lower byte of the MDR is loaded into the Data Register (DR) of the FDC which clears
the Data Request bit (DRQ) of the FDC. The FDC moves the byte into the data shift register which shifts
each bit serially onto the floppy disk. The second byte of data is fetched from the high byte MDR and
loaded directly into the DR.
When the third byte is requested, the DMA sequence is repeated and another word is fetched from
memory. At the conlpletion of each DMA word transfer, the MAR is incremented by two. This sequence
continues until all 512 bytes of the sector have been transferred from memory to the floppy. A two-byte
CRC is computed as the data is written to the floppy and appended to the data field.
If the data has not been loaded by the required time, a byte of zeros is written to the floppy and the
Lost Data bit will be set.

The busy bit of the CSR is set while the Write Sector command is in progress. Again the low order bits
of the CSR are redefined for a Write Sector command upon completion of the comnland (Table 11-8).
Partial writing of sectors is accomplished by writing the data and filling the balance with zeros.
Write precompensation is enabled whenever the track number is greater than 43 10 .
An interrupt is generated at the completion of the Write Sector command.
NOTE
If the floppy disk drive is write protected, an in-

terrupt is automatically generated if a Write Sector
command is received.

11-36

HSC70 MEMORY MODULE

11.7.4.3
Type III Commands
The type III commands are:
Read Address
Read Track
Write Track (Format)
Each will be covered separately.
11.7.4.3.1
Read Address Command
Upon receipt of the Read Address command, the head is loaded and the busy status bit is set. The next
encountered 10 field is read from the disk into the DR, and a DRQ is generated. The FDC checks for
validity, and the CRC status bit is set if there is an error. The track address of the ID field is written into
the Sector Register for comparison. Upon completion of the command, an interrupt is generated and
the busy status bit is cleared.
11. 7 .4.3.2
Read Track Command
Upon receipt of the Read Track command, the head is loaded and the busy status bit is set in the CSR.
Reading starts when an index pulse is detected and continues until the next index pulse is detected.
All gap, header, and data bytes are assembled and transferred to the DR, and DRQs are generated for
each byte. The accumulation of bytes is synchronized to each address mark detech.'d. An interrupt is
generated at: the completion of the command.
11.7.4.3.3
Write Track Command (Formatting)
Formatting the disk is accomplished by positioning the head over the desired track and issuing the Write
Track commland.
Upon receipt of the Write Track command, the head is loaded and the busy status bit is set in the CSR.
Data Request is set immediately, and a word is fetched from memory and loaded into the DR. Writing
starts when the first index pulse is detected and ends when the next index pulse is detected, at which
time the interrupt is generated. If the DR has not been loaded by the time the index pulse has been
detected, the operation is terminated making the device not busy. The Lost Data status bit is set and an
interrupt is generated. This sequence continues from index pulse to index pulse.
Status Register Summary
11.7.4.3.4
Table 11-10 is a summary of the Status Register bits for all commands discussed so far.

Table 11-10 Status Register Summar~
Bit

All Type I
Commands

Read
Address

Read
Sector

Read
Track

Write
Sector

Write
Track

Not Ready

Not ready

Not Ready

Write
Protect

Head Loaded

Record Type

11-37

HSC70 MEMORY MODULE

Table 11-10 (Cont.)

Status Register Summary

Bit

All Type I
Commands

Read
Address

Read
Sector

Read
Track

Write
Sector

Write
Track

Seek Error

RNF

CRC Error

Track 0

Lost Data

Index Pulse

DRQ

Busy

11.7.4.4
Type IV Commands
The Force Interrupt command is the only type IV command. It is used to terminate a multiple sector
read or write or to ensure type I status in the Status Register. This command can be loaded into the
Command Register at any time. If a command is being executed (busy status bit set), that command is
terminated and the busy status bit is reset.
The lower four bits of the command determine the conditional interrupt as follows:

•

10 = Not-Ready to Ready Transition

•

11 = Ready to Not-Ready Transition

•

12 = Every Index Pulse

•

13 = Immediate Interrupt

The conditional interrupt is enabled when the corresponding bit positions of the command (10-13) are set
to a one. When the condition for interrupt is met, the INTR REQ H line of the FDC is set, indicating that
the condition specified has occurred. If 10-13 are all set to zero, no interrupt occurs but the command
presently being executed will be terminated immediately.
When using the immediate interrupt command (13 = 1), an interrupt will be immediately generated and
the current command terminated. Reading the status or writing to the CSR will not clear this command.
Setting 10-13 to zeros is the only way to clear the immediate interrupt command.
More than one condition may be set at a time. If for example, 11 = 1 and 12 = 1, an OR function is
performed so that the interrupt is generated on either a ready to not-ready transition or on the next
index pulse.
11.8 JUMPER CONFIGURATION
There are five jumpers on the HSC70 Memory Module. Table 11-11 describes the purpose and normal
configuration of each jumper for this module.
NOTE
The purpose of the factory set potentiometers and
switch is described in Section 11.7.3.9.

11-38

HSC70 MEMORY MODULE

Table 11-11

HSC70 Memory Module Jumper Description

Jumper

Normal
Configuration

Out

Installed for two banks of Data Memory
Removed for four banks of Data Memory

Installed for normal operation
Removed when using external clock input

Installed for 2 MHz clock (500 Kbytes/second)
Removed for 1 MHz clock

Out

Installed for 1 MHz clock (250 Kbytes/second)
Removed for 2 MHz clock

Out

Installed for 250 Kbytes/second transfer rate
Removed for 500 Kbytes/second transfer rate

Description

11-39

DATA CHANNEL MODULE

CHAPTER 12
DATA CHANNEL MODULE

12.1 INTRODUCTION
This chapter contains the logical and functional description of the Data Channel Module. There are two
kinds of Data Channel Modules:
•

Disk Data Channel-LOI08-YA-HSC5X-BA-K.sdi

•

Tape Data Channel-LOI08-YB-HSC5X-CA-K.sti

The differences between the two modules are the microcode in the PROM and a jmnper.
NOTE
When talking about the Data Channel Module in
general, the mnemonic K.sdi/K.sti will be used.
When talking about a specific data channel, the
mnemonics K.sdi or K.sti will be used.
The K.sdi/K.sti is an L series extended-hex module which is the interface between the HSC and the Standard Disk/Tape Interconnect Bus (SDIISTI). It uses several of the 2900-family bit-slice devices, supported
by medium/small scale integration transistor/transistor logic. The architecture of K.sdi/K.sti consists of
2900-family components organized as dual sequencers alternately accessing a common control store and
supporting a single 16-bit data path.
The K.sdi supports up to four disk drives, each connected radially via the SDI Bus. The maximum serial
data rate from any drive is 25 Mbit/second. Different drive types with different serial data rates may be
simultaneously connected to one K.sdi. However, all disks must adhere to the sector formats for 16-bit
and IS-bit data.
The K.sti supports up to four tape formatters, each connected radially via the STI Bus.
The K.sdi/K.sti does not use control registers to communicate with the P.ioc and other controllers in
the HSC. Communications between the K.sdi/K.sti and the P.ioc and other controllers of the HSC are
performed using memory resident control structures.
Go/No-Go diagnostics for K.sdi/K.sti are nlicrocoded and are entirely resident in PR.OM along with the
functional microcode.

12-1

DATA CHANNEL MODULE

12.2 STATUS LEOS
The red and green LEDs indicate the status of the K.sdi/K.sti module. The module powers up with the
red LED on and the green LED off. Upon successful completion of the power up diagnostics, the red
LED is turned off and the green LED is turned on.
12.3 MICROINSTRUCTION WORD
The microinstruction word from Control Store controls the operation of the K.sdi/K.sti. The microinstruction word is 48 bits wide. Each word is divided into sixteen fields, and each field controls different
portions of the K.sdi/K.sti hardware. Figure 12-1 shows the fields and their position within the microinstruction word. Table 12-1 contains a brief description of each field. Section 12.7 has a detailed
description of each field.

Figure 12-1

Microinstruction Word

I c I
47

41 40

44 43

IABI + I
38 37 36 35

IOC

RA/BS

TEST

28 27

I@ I

LITERAL

25 24 23

20 19

BRANCH ADDRESS (BA)

14 13

00
CX-1224A

12-2

DATA CHANNEL MODULE

Table 12-1 Microinstruction Word Field Description
Field

Description

The C field is the carry-in into the ALU for the current microinstruction.
It steers the literal to the most significant byte for AI~ fields 3 through 7.

The AD field, ALU destination, determines the routing of the ALU output
data internal to the 2901.

The AF field, ALU Function, determines the oper,ltion to be performed
by the ALU.

The AS field, ALU source, selects two of the five possible sources for
the ALU.

The AB field, ALU to BUS, determines whether ALU or the bus source
decoder is the source for the data on the BUS.

The + field, EXEC IF COND TRUE, is one bit long. This bit is combined
with the following signals to generate INHIBIT EXEC (inhibit execute).
•

TST COND TR (test condition true)

•

COND EXC (conditional execute)

INHIBIT EXEC prevents:
•

Any ALU operation of each instruction for which it is active

•

The IOC Control latches from being enalJled

•

The destination decoders from being enabled

The RB field, B Port Register, selects one of the sbcteen internal registers
to be read and/or written by the 2901 ALU. If a value of 58 or 78 is in the
AS field" the A Port Register field (RA field) is forced to the same value
as the RB field.

TEST

The TEST field, TEST CONDITION < 03:00 >, selects one of 16 signals
for the conditional operations of the sequencers. The hardware includes
two separate selectors, one for each of the two sequencers.

The BD field, bus destination, selects the register to be loaded with the
data on the BUS lines.

The @ field, IOC enable, when set, permits the IOC field to modify the
IOC latches. This bit is not set when using the LrrERAL field.

IOC

The IOC field, input/output control, if enabled b}' IOC ENABLE, modifies the IOC Latches. Bits < 22:20 > select the desired latch, and bit 23
sets or clears that latch.

12-3

DATA CHANNEL MODULE

Table 12-1 (Cont.)

Microinstruction Word Field Description

Field

Description

The RA field, A Port Register, selects one of the sixteen internal 2901
registers to be operated on by the ALU. The RA field is a shared field
and is only enabled if the AS field does not equal 58 or 78 and bit AB
does not specify the LITERAL field.

The BS field, bus source, selects one of the K.sdi/K.sti registers which
are external to the ALU. The contents of the selected register are enabled
onto the BUS lines, routed through the input multiplexer, and presented
to the D inputs of the 2901 ALU.

The S field, test sense, is XORed with the output of the Test Multiplexer
to generate TST COND TR (test condition true). TST COND TR is then
combined with branch address equal to 77778 and JUMP CNTL 1 to
determine whether the sequencer will output the Program Counter, the
Stack, or the Branch Address.

The $ field, conditional execute, enables all instructions when clear.
When set, this bit enables the conditional execution of the laC, bus
destination, and ALU instructions.

The K field, jump control, is logically combined with TST COND TR and
BR ADR < 11:00> equal to all ones (77778) to control the next operation
of the 2911 Sequencers. This combination controls the operation of the
internal Stack, and it determines whether the sequencer will output the:
•

Program counter

•

Stack contents

•

Branch address field

The P field, instruction parity, is the single parity bit for the 48-bit microinstruction word. This bit is calculated odd parity for the other 47
bits. If the number of 1 bits in the other 47 bits is even, then this bit is
a 1 making the 48-bit microinstruction word odd parity. If the number
of 1 bits in the other 47 bits is odd, then this bit is a 0 making the 48-bit
microinstruction word odd parity.

12.4 DATA CHANNEL MODULE BLOCK DIAGRAM
Figure 12-2 is a block diagram of the K.sdi/K.sti showing the principal hardware elements and data
paths. Each of these elements are described in the following sections. These sections describe the block
diagram as if it were made up of two different components. The left side of the block diagram is control
and interface to the rest of the HSC. The right side of the block diagram is input and output to the
Standard Disk/Tape Interconnect.

12-4

DATA CHANNEL MODULE

NOTE
Notice on Figure 12-2 the bus labeled K.SDI BUS
(BF BUS, KL BUS, INV BUS) D15:00. The names
represent the same bus with different buffers because of dc loading, ac loading, and the way the
Scratchpad RAM inverts the bus. This chapter will
consistently refer to this bus as BUS D < 15:00>.
To differentiate the various serializer/deserializers,
encoder/decoders, receiver/drivers, and multiplexers on the right side of the block diagram, a name,
a coordinate, and a page number appears in each
block. For example, the block containing SER DESER,
07, P12 will be referred to as the Upper Real-Time
Controller State Serializer (07 P14).
12.5 CONTROL AND INTERFACE THE TO REST OF THE HSC
The control and interface to the rest of the HSC of the K.sdi/K.sti has almost all the same components
as the K.pli. If you look at the left side of Figure 12-2 you will see some of the same blocks that are in
the K.pli block diagram. In the following sections we will cover the control portion of the K.sdi/K.sti:
•

Sequencers

•

Test Multiplexer

•

Program Address Counter

•

Control Store and Instruction Register

•

Arithmetic and Logic Unit (ALU)

•

Scratchpad RAM

•

Upper and Lower Sequencer Control Registers

•

Control and Data Error Registers

•

PALs

The PALS will be discussed along with the SDIISTI interface.
The interfaces to the rest of the HSC are on the left side of the block diagram. These elements are:
•

Data Bus Interface

•

Control Bus Interface

•

Status Bus Interface

12-5

DATA CHANNEL MODULE

Figure 12-2

Data Channel Module Block Diagram

ALU SRC 2:0
ALU DEST 2:0
ALU FUNCT 2:0
A REG 3:0 _ _ _....
B REG 3:0 _ _-....;........

~~; ;ERLC2~~0 ==~6
P07

SET IOC

DIAGNOSTIC REGISTER
PALS

ALU
2901

16 ADDRESSES
16 BITS

P07
'--..-_...A

SELLTRL

DBUS
DATA

DBUS
ADR
P02

CDATA PAR _
ERR

TEST
COND UPPER
s~1 ......... TRUE SEQUENCER
CO~ TEST f-~
2911
P04
STATUS MUX

CBUS
DATA

LOWER
STATUS

P01

DRV
STATUS
BITS

CBUS
ADR

LOWER
SEQUENCER
2911
P04

__ DDATA PAR
ERR

INSTR PAR

CHECKER
P06.

INST PAR
ERR

2K x 48
r---- ~
~ ALU
AND
.... CNTL
INSTR
~
REGISTER

1 1 - - - - ' 11

L...L.

rr- D

Q
PADR
REG

rr- ADRS

_iUS~
_ SRC
CNTL

=~:j
DEST
CNTL
P03

P04

~~~

~ CNTL-v'

SEQ ADR
11:00

----P03

LOWER ENAJ,

F==

ROLL-.J

P051

JUMP CNTL 1

MSNG
- D BUSOVRN

~~~__~

P01

STATUS 7:0 STATUS
REG

L- DATA PLS

_ C BUS ERR

CONTROL
STORE

UPPER ENA ...J
-

i~ ~~~AR

- - RESP PLS MSNG

P03

CADR 16:00,
CCYCLE 2:0

-RT PAR ERR

l1'

UPPER!'....

D SERDES OVRN-

~')c:=:::::;1

LD PADR REG

1
po~1

IDATA ERR REG

a D NXM
ECC ERR ---J

C NXM

. . SEND UPR RTCS

CDATA
15:00,
LP, HP

CNTL ERR REG I

MISC
. . LWR MUX EN
... LWR DRV SEL
CLK PRESINST PAR_
ERR

- MISC
.... DRV INIT
..... UPR DRV SEL

DBUSADR _
4COUNTER
P02 -

~~~rr~P~08~

P13
-r---

+,.....---------.1 t

LWR CNTL REG
P08

UPR CNTL REG
P08

P02

""---

1.1

DADR
17:00,
_DNMA
~

~SECTOR 3:0

P06

K.SDI BUS(BF BUS, KL BUS, INV BUS) D15:00

DDATA
15:00,

cLP'l

~ INDEX3:0

SCRATCHPAD
RAM

BR ADR 11:00
~

TEST FOR TRUE

S ENABLE

TEST COND 3:0

P08

4,
I

D GRANT
D TIMING

DBUS
TIMING
P02

DREG

C GRANT
C TIMING

CBUS
TIMING
P01

C REG
RCVR CLK

NOTE: PAGE NUMBERS AND CO-ORDINATES
INSIDE BOXES REFER TO ETCH REV E
LOCATIONS. FUNCTIONALITY APPLIES
TO ALL PREVIOUS ETCH REVS.
CX-120lA

Sheet 1 of 2

(Continued on next page)
12-6

DATA CHANNEL MODULE

Figure 12:-2 (Cont.)

Data Channel Module Block Diagram
TTL - . ECl

DC026

DC027

CONTROL
SERDES
DC018

____

DRVORrDS
DRV 0 DATA
MUX

OUT
______-L~
__________~

ClK~-L
DATAIN~

DRV 0 DATA
DRV 1 DATA
DRV 2 DATA
DRV 3 DATA

P09

RTDS
RIR
DATA
RTCS
W/C
DATA

RTC DA-l A 0
WRTDArAO

P14

DC026

ECC OUT 09:00 . . . .

16 BIT
TTL OUT I----I~
ClK
DATA IN
OUT P09

I---~

ECC
SERDES
DC018
10 BIT

D4
P14

WRT DATA 0
I--IM---I~ WRT DATA 1
1-1-.............. WRT DATA 2
I--II-I-......~ WRT DATA 3

DRV 1 RTDS
DRV 1 DJUA

RTDS
RIR
DATA

RTC DA fA 1

RTCS
W/C
DATA

WRT DA fA 1

DC026

C4
lWR MUX EN
lWR DRV SEl
DC027

P14

DRV2RrDS
DRV 2 DATA

RTDS
___~ ~~.-' RIR

RTC DA lA 2
WRTDATA2

RTCS

DATA

W/C
DATA

DRV 0 ClK
DRV 1 ClK
DRV 2 ClK
DRV 3 ClK

RTCS
W/C
DATA

RTC DA-r A 0
RTC DAfA 1
RTC DATA 2
RTC DAIA 3

P14
DC027
ENCODER
DRV 1
RTDS

Pll

lWR MUX
EN
lWR DRV
SEl

TTl~Cl

g DRV 2 RTDS

P14

Pll

DC704

DC027

* DRV STATUS BITS

DESER

* DRV STATUS BITS

DESER

- B3
- DRV 3 RTDS

P12

*
**

-----~--' DATA

RTC DATA 3
WRTDATA3

DRV STATUS BITS

RTDS
RIR

DRV 3 R fDS
DRV 3 DATA

P14

DRV OClK
DRV 1 ClK
DRV 2 ClK
DRV 3 ClK

DC026

Pll

DRV STATUS BITS: AVAI l, R/W RDY, ATTN, RDY TO REC, INDEX, SECTOR
RTCS BITS: DRV INIT, RCVR RDY, RD GATE, WRT GATE
CX-120lA

Sheet 2 of 2

12-7

DATA CHANNEL MODULE

12.5.1
Sequencers
In the lower-left corner of Figure 12-2 you will see the two sequencers. The use of these two sequencers
which alternately and independently access a common Control Store is the heart of the architecture of
the K.sdi/Ksti. The two sequencers, in conjunction with the Control Store and Arithmetic and Logic Unit
(ALU), are designated Upper Sequencer and Lower Sequencer. The two sequencers control different
portions of the external interfaces, and they have separate and independent functions.
NOTE

In the K. pH, the sequencers are named Control Sequencer and Data Sequencer. The two sequencers
in the K.sdilK.sti have the same function as those
in the K.pli; however, they are named Upper and
Lower. The Upper Sequencer has the same function
as the Control Sequencer and the Lower Sequencer
has the same function as the Data Sequencer.
The Upper Sequencer is responsible for initiating the work that the K.sdi/K.sti does in response to
commands for the P .ioclP .ioj. This includes examining queues for work to do, acquiring and retiring
buffers, and so on. The activity level of this sequencer is fairly high and fairly constant.
The Lower Sequencer handles all aspects of a data transfer between Data Memory and the disk/tape
drive. During a data transfer, the Lower Sequencer is busy; at all other times it is idle.
One sequencer does not help out or share the work assigned to the other sequencer. Each sequencer
has its own job to do.
With a basic clock period of 150 nanoseconds, each sequencer has an apparent micro-cycle time of 300
nanoseconds. One advantage of this technique is that no effective time is lost by either sequencer when
executing a branch, since the Control Store is accessed by the branching sequencer while the other
sequencer is executing.
The sequencers are the control section of the K.sdi/K.sti. Each sequencer consists of three 2911 bit-slice
devices connected to form a 12-bit address. Figure 12-3 is a block diagram of one 2911. Each bit-slice
is 4 bits wide and consists of the following logic:
•

Program Counter Register

•

Incrementer

•

Four Register Stack

•

Stack Pointer

•

Next Address Multiplexer

•

Internal logic to control these functions

The sequencers in the K.sdi/K.sti connect three 2911s for a 12-bit wide address. This 12-bit address
allows the sequencer to address 4 Kwords of Control Store. This address always points to the next
instruction by automatically incrementing after the instruction fetch. The stack is 12-bits wide and four
words deep and is used along with the stack pointer during branch operations.
The internal multiplexer within the sequencers is capable of choosing one of the following for output to
the program address register:
•

The Stack

•

The Program Counter Register

•

The branch address supplied from the Control Store

12-8

DATA CHANNEL MODULE

Figure 12-3 2911 Sequencer Block Diagram

1~~p
\

STACK POINTER

FOUR REGISTER STACK

4'
BR ADR

~.7

~so
-

~ S1

t
i

"".7 "".7 ""
RNEXT ADDRESS
F

~
REGISTEn

MULTIPLEXER

~, ZERO

INCREMENTER

~J
SEQUENCE ADDRESS
CX-1235A

As connected on the K.sdi/K.sti, the sequencers perform the following operations:
•

CONTINUE-Increments the Program Counter Register and places the new address on the
SEQ ADR <11:00> lines.

•

RETURN FROM SUBROUTINE (pop stack)-Loads the Program Counter Register with the
current value on the top of the stack and gates this value to the SEQ ADR <: 11 :00> lines. The
Stack Pointer is then decremented.

•

JUMP TO BRANCH ADDRESS-Loads the Program Counter Register with the current value
of the branch address and gates this address to the SEQ ADR < 11 :00>. The Stack and Stack
Pointer are not affected.

•

SUBROUTINE CALL (push stack)-Increments the Stack Pointer and pushes the current value
of the Program Counter Register onto the Stack. Loads the Program Counter Register with the
current value of BR ADR <11:00> and gates this address to SEQ ADR <ll:00>.

12-9

DATA CHANNEL MODULE

12.5.2
Test Multiplexer
The sequencers must have the ability to test different conditions on the K.sdi/K.sti. Figure 12-2 shows
a test multiplexer to the left of the two sequencers. This test multiplexer contains two separate 16-input
multiplexers to select test conditions for the two sequencers. Bits 31 through 28 of the Control Store
generate TEST COND < 3:0 > that select one of the 16 inputs. Either the true or the comple~ent of the
selected test condition may be selected. This is accomplished by the TEST FOR TRUE (bit 15 from the
Control Store). A synchronization circuit is included to prevent incorrect testing of asynchronous test
conditions. Available test conditions include:
•

Drive status

•

ALU status

•

lac Latches

•

Error indicators

Section 12.7.8 contains a description of each input to the test multiplexers.
Program Address Register
12.5.3
The sequencers must address the Control Store through the Program Address Register (P ADR REG)
shown in Figure 12-2. This register accepts the sequencer outputs on each clock and presents the
instruction address to the Control Store for the fetch operation.
The sequencer outputs may be disabled and the Program Address Register forcibly loaded from the
ALU by LD PADR REG. For example, the ALU may execute a calculated jump by calculating the jump
address from a table and writing the data to the Program Address Register from BUS D < 11 :00>. During
this time, the outputs of the sequencers are disabled.
The Upper Sequencer microcode can force the Lower Sequencer to trap to address 37778 , The Upper
Sequencer microcode may do this if it failed to communicate with the Lower Sequencer through the
Scratchpad RAM. The Lower Sequencer may be stuck in a loop. The logic in Figure 12-4 shows that the
decoder that loads the Program Address Register is disabled when a FORCE LWR TRAP is asserted.
When the Lower Sequencer tries to load the Program Address Register, the decoder is disabled and the
outputs from the 2911 are pulled high and a 37778 is loaded into the Program Address Register.
12.5.4
Control Store and Associated Logic
Figure 12-2 shows the Control Store and Instruction Register located to the lower left of center. The
Instruction Register consists of latches on the output of the Control Store. These latches drive the
following control logic:
•

ALU Control

•

Bus Source Control

•

Bus Destination Control

•

lac Control

Along with the Instruction Register and control logic, we will look at the Instruction Parity Checker logic
in this section.

12-10

Figure 12-4 Force Lower Sequencer to Vector 37778 Logic

UPPER
SEQUENCER

+5V +5V +5v +5V

PROGRAM
ADDRESS
REGISTER

2911
OUTPUTS
YO
Y1
Y2
Y3

OF
1F
2 F
3F
lD PADR REG l

----------12

UPR PROC I H - - - - - - - - - - 1 1
DEADBAND l

--~

DO
01
02
03

RO
R1
R2
R3

PADROO
PADR01
PADR02
PADR03

1
I

OUT EN

I
I
1_ _ _
P4_ _ _ ..JI

SEl

P4 ...l
L ___

EN P4

UPPER
CONTROL
REGISTER

o
SQNCR ClK l--+--iC

0
P4

FORCE lWR TRAP H
SF BUS 004

UPR PRoe I H

-4

z)z

9L....--_ _ _ _ _

--I

CX-1202A

o
c

c::

DATA CHANNEL MODULE

12.5.4.1
Control Store and Instruction Register
Figure 12-2 shows the PROM Control Store to the right of the sequencers. All microcode instructions
are contained in the Control Store. This Control Store is 48 bits wide (including parity). The Control
Store consists of twelve 2K by 4 PROMs. One microinstruction is fetched from the Control Store during
each 150 nanosecond clock cycle. At the end of the clock cycle, the microinstruction is loaded into a
latch (Instruction Register) where it is held for the following execution cycle.
The Upper Sequencer has the ability, in diagnostic mode, to command the Lower Sequencer to consecutively fetch and test parity in all Control Store locations. This is accomplished with the ROLL signal
on the output of the IOC Control latches. (Refer to Section 12.5.4.6.)
A detailed description of each bit of the microinstruction word is contained in Section 12.7.
Instruction Parity Checker
12.5.4.2
The Instruction Parity Checker checks for odd parity over the 48 bits of the instruction from the Control
Store. This parity bit is gated to the test select multiplexer. Bit 12 is the odd parity bit for the 48 bits
of the instruction word. The Instruction Parity Checker is located at the top of the Control Store in
Figure 12-2.
If a Control Store parity error is detected when K.sdi/K.sti is in normal mode, the sequencers are

stopped, resulting in a complete halt of all K.sdi/K.sti operations. Recovery occurs only after the P.ioc
initializes the module.
12.5.4.3
ALU Control
The ALU Control (ALU CNTL) logic latches the bits from the Control Store to control the ALU by:
•

Determining the routing of the ALU output internal to the 2901

•

Determining the operation to be performed by the ALU

•

Selecting two of the possible five inputs to the ALU

•

Controlling the output of the ALU to the BUS D < 15:00 >

Figure 12-5 shows which Control Store bits generate which ALU control. Each bit is described in
Section 12.7.
12.5.4.4
Bus Source Control
The Bus Source Control (BUS SRC CNTL) logic decodes Control Store bits < 18: 16 > to enable the
different sources to BUS D < 15:00> for each sequencer. The Bus Source Control logic is located on the
output of the Control Store in Figure 12-2. Figure 12-6 is a block diagram of the Bus Source Control
logic.
ALU TO BUS disables the two decoders. ALU TO BUS is generated by the ALU Control logic. (Refer
to Section 12.5.4.3.)
Each sequencer reads from its own sources. The signals UPR PROC 0 and UPR PROC 1 determine
which decoder is enabled. Notice that the Scratchpad RAM is the only source that can be read by both
sequencers (RD SCRATCH REG).

12-12

DATA CHANNEL MODULE

Figure 12-5 ALU Control Logic
CONTROL
STORE

INSTRUCTION
REGISTER
CARRY IN

PROM 47

ALU DEST 2:0

PROM 44:46
v

ALU FUNC 2:0

PROM 41:43
v

PROM 38:40

ALU SOURCE 2:0

PROM 37

A LU TO BUS
CX-1203A

12.5.4.5
Bus Destination Control
The Bus Destination Control (BUS DEST CNTL) logic decodes Control Store bits < 27:25 > from Control
Store to load registers (for example, LD STATUS REG) and start timing (for exampl,,~, SET C REQ). Signals UPR PROC 0 and UPR PROC 1 control which destination decoder is selected. The Bus Destination
Control logic is located on the output of the Control Store in Figure 12-2. Figure 12-7 is a block diagram
of the Bus Destination Control logic.
Each sequencer writes to its own destinations. The signals UPR PROC 0 and UPR PROC 1 determine
which decoder is enabled. Notice that there is a common destination decoder which allows either
sequencer to write to Scratchpad RAM, load the Diagnostic Register, or load the Program Address
Register.
Another enabling signal to the Bus Destination Control logic is destination clock (DEST CLK). Notice
that a qualifier to DEST CLK is INHIBIT EXEC. The test multiplexers assert INHIBfr EXEC when a test
is false. The microcode uses this feature to inhibit loading a register if the test is not met. An example
would be the microcode moving data from the Scratch pad RAM to the Control Bus Data Register but
first testing to see if the bus is busy. (This operation can be coded in one instruction.) If the bus is busy
when the sequencer executes this instruction, the Scratch pad RAM data would be gated onto the bus
but would not be clocked into the Control Bus Data Register. The signal INHIBIT EXEC would disable
DEST CLK.

12-13

DATA CHANNEL MODULE

Figure 12-6

Bus Source Control Logic
CONTROL
STORE

INSTRUCTION
REGISTER
BUS SRC 0

PROM 16

RD
RD
RD
RD
RD
RD

BUS SRC 1

PROM 17

BUS SRC 2

PROM 18
P05

UPPER SEQUENCER
BUS SOURCE

P05

CNTL DATA
CNTL ADDR
CNTL SRDS
SEC/IND REG
CNTL SRDS
CNTL ERR BITS

ALU TO BUS
UPR PROC 0

P03
LOWER
SEQUENCER
BUS
SOURCE

ALU TO BUS
UPR PROC 1
P03

RD
RD
RD
RD
RD
RD

~--RD

SCRATCH

REG

DATA BUS
MUNG RSDU
DATA SRDS
D ADR REG
DATA ERR BITS
EGC RSDU

CX-1204A

12-14

DATA CHANNEL MODULE

Figure 12-7 Bus Destination Control Logic
CONTROL
STORE
PROM 25

INSTRUCTION
REGISTER
BUS DEST 0

LD CNTL DATA
LD CNTL ADDR
LD CNTL SRDS
LD UPR CNTL Fl EG
LD STATUS REG
SET C REQ

BUS DEST 1

PROM 26

BUS DEST 2

PROM 27
P05

UPPER SEQUENCER
BUS DESTINATION

P05
ALU TO BUS - + - H H
UPR PROC 0
P03

COMMON DESTINATION
INHIBIT EXEC
CLKA----I

DEST CLK

P03

LD DIAG REG
WRT SCRATCH BEG
LD PADR REG

LOWER SEQUENCER
BUS DESTINATION

UPR PROC 1
ALU TO BUS
P03

LD DATA BUS
LD 0 ADR REG
LD DATA SRDS
LD LWR CNTL F! EG
LD LWR STATE
RD DATA ERR BITS
RD ECC RSDU
CX-1205A

12.5.4.6
IOC Control
The term lac stands for Input/Output Control. The lac Control (laC CNTL) logic, shown to the right
of the Control Store in Figure 12-2, decodes Control Store bits < 22:20 > from the Control Store and
sets or clears the lac Control latches. These latches may not be set or cleared if the LITERAL field, to
the ALU, is being used. Modification of these latches is specified if lac ENABLE is set. Figure 12-8 is
a block diagram of the lac Control logic. Table 12-2 describes each bit in the IOC Control latches.

12-15

DATA CHANNEL MODULE

Figure 12-8

IOC Control Logic
CONTROL
STORE

UPPER IOC's

INSTRUCTION
REGISTER
IOC SEl 0

PROM 20 I PROM 21 I--

IOC SEl 2

PROM 22 I--

SETIOC

PROM 24 I PROM 23 I-P05

f--UPR PROC FLAG
f--INIT/FUN FLAG
f--RCVR ROY
-ROll
-CNTl SRDS ENA
-RCV MODEO
-UPR SER MUX EN
-ENA OESER

IOC SEl 1

P03

P05
lOWER IOC's

ENABlEIOC

f-- lWR PROC FLAG
f--ECC BYPASS
f--SERDES ENABLE
-RD MODE
-ECC IOC ENABLE
-ECCTIMING

ClK UPR IOC
r--

UPR PROC 0 DEST ClK -

ClK lWR IOC ' - P06
'----

P03
CX-1206A

Table 12-2

IOC Control Bit Description

Bit

Definition

UPR PROC FLAG

This bit is set or cleared by the Upper Sequencer and is an input to the Lower
Test Multiplexer. This bit is used for microcode communication from the Upper Sequencer to the Lower Sequencer.

INIT IFUN FLAG

This bit is set or cleared by the Upper Sequencer. This bit controls the two
LEDs. When set, the green LED is on and the red LED is off. When clear, the
red LED is on and the green LED is off. This bit is available for the Upper
Sequencer to test through the test multiplexer.

RCVR RDY

This bit is set or cleared by the Upper Sequencer. When set, this bit indicates that the K.sdi/K.sti is ready to receive a level 2 response from the disk
unit or tape unit. (Refer to Section 12.6 for definition of)evel 2 response.)
When cleared, it indicates that the K.sdi/K.sti is not ready to receive a level 2
response.

12-16

DATA CHANNEL MODULE

Table 12-2 (Cont.)

IOC Control Bit Description

Bit

Definition

ROLL

This bit is set or cleared by the Upper Sequencer. When set, it prevents the
Lower Sequencer from executing all ALU, 110, and branch operations. The
Lower Sequencer is forced to increment its address through Control Store
in order to fetch and check instruction parity. When cle.)r both sequencers
operate normally.
f

CNTL SRDS ENA

This bit is set or cleared by the Upper Sequencer. When set, this bit enables
the Control SERDES. When reset, this bit resets all the internal registers and
counters of the Control SERDES.

RCV MODE

This bit is set or cleared by the Upper Sequencer. This bit switches the Control
SERDES between receive mode and transmit mode. When set, the Control
SERDES is in receive mode; when clear, the Control SERDES is in transmit
mode.

UPR SER MUX EN

This bit is set or cleared by the Upper Sequencer. When set, this bit enables
WRT DATA <3:0> and RTC DATA <3:0> multiplexers. WRT DATA <3:0>
and RTC DATA < 3:0 > are wired ORed for information from either the Upper
Sequencer or Lower Sequencer. When cleared, the output of the multiplexer
is disabled.

ENA DESER

This bit is set or cleared by the Upper Sequencer only. When set, this bit
enables the output of the real-time drive state from the Real-Time State Deserializer for a selected port. When cleared, this bit disables the output of the
Real-Time State Deserializer.

DATA PROC FLAG

This bit is set or cleared by the Lower Sequencer and is an input to the Upper
Test Multiplexer. This bit is used for microcode communication from the Lower
Sequencer to the Upper Sequencer.

ECC BYPASS

This bit is set or cleared by the Lower Sequencer. When set, this bit disables
the output of the Data SERDES to the encoders and enables the output of the
ECC SERDES to the encoders. When clear, this bit enables the output of the
Data SERDES to the encoders and disables the output of the ECC SERDES to
the encoders.

SERDES ENABLE

This bit is set or cleared by the Lower Sequencer. When set this bit enables the
Data SERDES. When reset, this bit resets all the internal registers and counters
of the SERDES.

12-17

DATA CHANNEL MODULE

Table 12-2 (Cont.)

IOC Control Bit Description

Bit

Definition

RD MODE

This bit is set or cleared by the Lower Sequencer. When set, this bit is an
enabling signal to Data Bus Transceiver and configures the Data SERDES and
ECC SERDES to receive data from the disk or tape unit. When clear, this bit
configures the Data SERDES and ECC SERDES to receive data from the Data
Bus Transceivers.

ECC IOC ENABLE

This bit is set or cleared by the Lower Sequencer. When set, this bit enables
the ECC logic and ECC SERDES. When clear, this bit disables the ECC logic
and resets all the internal registers and counters of the SERDES.

ECC TIMING

This bit is set or cleared by the Lower Sequencer. When set, this bit enables
the ECC logic. When cleared, this bit disables the ECC logic.

12.5.5
Arithmetic and Logic Unit
Figure 12-2 shows the Arithmetic and Logic Unit (ALU) in the upper-left corner. The ALU is implemented with four 2901 bit-slice devices, providing a 16-bit data path. The 2901 bit-slice ALU chip can
perform addition, subtraction and logic operations. Its internal data paths and registers are four bits
wide (Figure 12-9). Nine control signals and eight register-select lines detennine the ALU function,
operand source, and destination. The ALU has the following characteristics:
•

A 2-port RAM comprised of 16 registers. The RAM registers are read via their A or B Data Out
ports.

•

A 4-bit shift register on the RAM data input. The output of this register is connected in ring
counter fashion to the input.

•

A 4-bit Q register for assisting with multiplication and division algorithms.

•

A 4-bit shift register on the Q register input.

•

A multiplexer that selects the output of the Q register shifter or the ALU output for input to
the Q Register.

•

Two multiplexers that select the ALU inputs. These inputs may be the direct input, the A or B
RAM, logic zero, or the Q Register.

•

An output multiplexer that selects the ALU output or port A of the RAM and gates it to BUS.

•

A 2-input ALU capable of performing the operations shown in Table 12-3.

12-18

DATA CHANNEL MODULE

Figure 1.2-9

2901 ALU Block Diagram

A REG 3:0

A ADDRESS
RAM
16 ADDRESSABLE
REGISTERS

B REG 3:0
A
DATA
OUT

B
DATA
OUT

LOGIC 0
DIRECT INPUT

ALU SOURCE
OPERAND DECODE

R
ALU SOURCE 2:0

ALU FUNCTION
DECODE

C IN
8-FUNCTION ALU

G
p
C N+4
F S (SIGN)

OVERFLOW
F=OOOO

AL.U FUNC 2:0
A
F
OUTPUT DATA SELECTOR

I\LU DESTINATION
DECODE

DOUT
ALU DEST 2:0
CX-1236A

12-19

DATA CHANNEL MODULE

Table 12-3 ALU Operations
Operation

Operands Used

Addition

R + S

R+ S+ 1
Subtraction

R-S
S-R
R-S-l
S-R-l

Logical OR

R OR S

Logical AND

RANDS

Logical NOTRS

(NOT R) AND S

Logical XOR

R XOR S

Logical XNOR

R XNOR S

Organization of the 2901 is such that shift operations are separate from, and independent of, the arithmetic and logical operations, and are effective only on the inputs to the internal Q and RAM registers.
The results of ALU operations are not shifted at the Y outputs. The ALU state flags reflect the ALU
results before any shift.
Shifts may be performed at the RAM register inputs, or at the inputs of both the RAM and Q registers
in one instruction. All are 16-bit shifts, and the ALU carry is never affected by any shift operation. Shifts
performed on the Q register are end off. That is, on a left shift the contents of bit 15 are lost and 0 is
shifted into bit 00. On a right shift the contents of bit 00 are lost and a 0 is shifted into bit 15. Shifts
performed on the RAM registers are circular. That is, on a left shift the contents of bit 15 appear in bit
00, and on a right shift the contents of bit 00 appear in bit 15.
Pipelining Concepts
12.5.6
Now that you have read about the elements that make up the computing power on the K.sdi/K.sti, let's
look at how the sequencers, Program Address Register, Control Store, and Instruction Register form a
pipeline. Pipelined designs decrease instruction cycle time by performing fetch and execute operations
in parallel (Figure 12-10). The Instruction Register holds the current microinstruction that controls the
processing section and helps the control sections select the next address. Thus, the processing section is
operating on the current microinstruction while the control section is fetching the next microinstruction
from the Control Store.
12.5.7
K.sdilK.sti Pipeline
The K.sdi/K.sti uses a form of microinstruction/address/status pipelining (double pipelining). Registers
are provided for the current microinstruction (Instruction Register), the sequencer address (Program
Address Register), and the ALU/real-time status (test multiplexers). Due to these three registers, the
double pipelining design has three parallel paths. These paths simultaneously perform the following
operations:

12-20

Figure 12-10 K.sdi/K.sti Double Pipelining

PROGRAM
ADDRESS
REGISTER

CONTROL
STORE

INSTRUCTION
REGISTER

SR ADR 11:00
TEST FOR TRUE
TEST COND 3:0

CX-1207A

-I

....
o

:r:
)t

Z
m

o
C

c:
rm

DATA CHANNEL MODULE

•

The current microinstruction is clocked into the Instruction Register. It controls the ALU along
with the branch address of the Upper and Lower Sequencers.

•

The sequencers generate a new value for the Program Address Register.

•

The current value in the Program Address Register fetches the next microinstruction for the
Control Store. Control Store bits < 31:28 > select the test conditions for the test multiplexers.

12.5.8
Pipeline Timing
Figure 12-11 shows the timing for an instruction fetch-execute sequence. The SQNCR CLK supplies the
timing for all the control timing. UPR PROC 1 is high when the Upper Sequencer is active. UPR PROC
1 is low when the Lower Sequencer is active. The timing in Figure 12-11 starts with the Upper Processor
gating the address on SEQ ADR < 11 :00>. Then the following steps occur:

Figure 12-11

Pipeline Timing for an Instruction Fetch-Execute Sequence

SONCR ClK l

LJ--10-0~~
UPR PROC 0 H

100

LJ
I

I~------~I

2911

~PC

CONTENTS

________I

I_________,

1 ,,------'"""'\

(UPR PROC)

ADDRESS C 1
I
2911 /-LPC CONTENTS (lWR PROC)
I
I

CLOCK INTO PADR REGISTER - - - - - 1....
~1

I~--------~

1 ADDRESS C+l
1
1

,r-------:."
ADDRESS D I
.... 1

1 ADDRESS C+2
1
1
1 ,----------.,
I
1

ADDRESS D+l

1 ADDRESS D+2

I
I

-----,,------...\1
I

FETCH C I
FETCH D I
CLOCK INTO INSTRUCTION REGISTER-------I........I-- - - - - I....
~I

FETCH C+1 I

PADR REGISTER CONTENTS

1
1
~--~\I

INSTRUCTION REGISTER CONTENTS

EXECUTE C I
CLOCK INTO TARGET REGISTER - - - - - - - - - - - 1..
-.11
I
I
TARGET REGISTER CONTENTS (UPR PROC)

FETCH D+1 I
I

1
1

FETCH C+2

EXECUTE DI EXECUTE C+l EXECUTE C+2
.... 1
1
I

I
RESULT C+1

RESUlTC:

.....

TARGET REGISTER CONTENTS (lWR PROC)
RESULT D

CX-1234A

12-22

DATA CHANNEL MODULE

•

On the high-to-Iow transition of the UPR PROC 0 signal:
•

The address fronl the Upper Sequencer is gated into the Program Address Register

•

The Control Store starts selecting the microinstruction for the tJ pper Sequencer

•

The Lower Sequencer gates its program address onto SEQ ADR < 11:00 >

On the next high-to-Iow transition of the UPR PROC 0 signal:
•

The microinstruction word is clocked into the Instruction Register to be used by the
Upper Sequencer

•

The Upper Sequencer gates its program address onto SEQ ADH. < 11: 00 >

•

The program address of the Lower Sequencer is gated into the Program Address
Register

The steps listed above tend to indicate an order of operation. However, SQNCR CLK occurs at the
same time on the sequencers, Program Address Register, and Instruction Register.
12.5.9
Scratchpad RAM
The K.sdilK.sti has a Scratchpad RAM that has 16 memory locations of 16 bit:·;. There is no parity
protection. The two sequencers use the Scratchpad RAM:
•

As a storage for variables

•

As a communications mechanism between each other

Since there are only 16 words in Scratchpad RAM we only need to decode 4 bits. These 4 bits come
from the Instruction Register and are:
10C SEL 0
IOC SEL 1
10C SEL 2
SET 10C
The signal to read from memory, RD SCRATCH REG, comes from the Bus Source Control logic. The
signal to write to memory, WRT SCRATCH REG, comes from the Bus Destination Control logic.
12.5.10
Upper Control Register
The Upper Control Register (UPR CNTL REG) is shown just below the ALU in Figure 12-2. It is controlled
by the Upper Sequencer. Figure 12-12 shows the bits of the register. Table 12-4 describes the bits in
this register.

12-23

DATA CHANNEL MODULE

Figure 12-12

Upper Control Register

BF BUS 000 H

BF BUS 001 H

BF BUS 002 H

BF BUS D03 H

BF BUS 004 H

BF BUS 005 H

BF BUS 006 H

INV BUS 007 L

CLEAR IN L

CLR

LO UPR CNTL REG L

CLK

UPR ORV SEL 0 H

UPR ORV SEL 1 H

SENO UPR RTCS H

CLR RT PAR ERR H

FORCE LWR TRAP H

ORIVE INIT H

UPR STOP H

OIAG MOOE L

P08
CX-120SA

12-24

DATA CHANNEL MODULE

Table 12-4

Upper Control Register Bit Description

Bit

Definition

UPR DRV SEL < 1:0>

These two bits select the destination drive for the Control SERDES and real-time
controller state for the Upper Sequencer.

SEND UPR RTCS

When set, this bit provides the sync bit for the Upper Real-Tirne Controller State
Serializer (P12 D7).

CLR RT PAR ERR

When set, this bit dears the real-time drive state error in the Real-Time Drive
State Deserializers. The UPR DRV SEL 011 bits select which drive deserializer is
cleared.

FORCE LWR TRAP

When set, this bit forces the Lower Sequencer to address 37778 (Section 12.5.3).

DRIVE IN IT

When set, this bit asserts DRIVE INIT to the Real-Time Controller State Serializer. This bit initializes the drive presently selected by the the UPR DRV SEL
OIl.

UPR STOP

When set, this bit halts the K.sdi/K.sti immediately. This bit gives the microcode
the ability to halt program execution due to the detection of a catastrophic error
(an error which could possibly cause the K.sdi/K.sti to write bad data on the
disk or tape).

DIAG MODE

When clear, this bit puts the K.sdi/K.sti in diagnostic mode. When in diagnostic mode the following K.sdi/K.sti hardware changes occur: The hardware has
control of the real-time drive status bits and the bits capable of forcing errors
on the Control and Data buses. It is capable of doing loop-back testing of the
Control and Data SERDES. The Control Real-Time Control Serializer is capable
of writing into the Real-Time Drive Deserializers. Control of the real-time drive
status bits and the Control and Data bus error forcing ability is via the Diagnostic
Register. (Refer to Section 12.5.12.)

Notice in Figure 12-12 that the input to bit 7 (DIAG MODE L) is INV BUS D07 L. The INV BUS
inverts the signal on BUS D07. Therefore, when the Control Sequencer writes a 1 on BUS D07, it is
inverted and clears bit 7 of the Upper Control Register which puts the K.sdi/K.sti in diagnostic mode.
Also, when the K.sdi/K.sti is initialized from the P.ioc, the register is cleared by CLEAR IN L which
puts the K.sdi/K.sti in diagnostic mode.

12.5.11
Lower Control Register
The Lower Control Register (LWR CNTL REG) is shown just below the ALU in Figure 12-2. It is
controlled by the Lower Sequencer. Figure 12-13 shows the bits of the register. Table 12-5 describes
the bits in this register.

12-25

DATA CHANNEL MODULE

Figure 12-13 Lower Control Register

BF BUS 000 H

BF BUS 001 H

BF BUS 002 H

BF BUS 003 H

BF BUS 004 H

BF BUS 005 H

LWR ORV SEL 0 H

LWR ORV SEL 1 H

LWR SER MUX EN H

6R
BF BUS 006 H

BF BUS 007 H

LWR STOP H

CLEAR IN L
LO LWR CNTL REG L

CLR P08
CLK
CX-1209A

12-26

DATA CHANNEL MODULE

Table 12-5

Lower Control Register Bit Description

Bit

Definition

LWR DRV SEL < 1:0> These two bits select the destination drive for the Data SERDES and real-time
controller state for the Lower Sequencer. These two bits also select which drive
is selected for input to the Data SERDES.
LWR SER MUX EN

This bit is set or cleared by the Lower Sequencer. When set, this bit enables
WRT DATA <3:0> and RTC DATA <3:0> multiplexers. WRT DATA <3:0>
and RTC DATA <3:0> are wired ORed for information from either the Upper
Sequencer or Lower Sequencer. When cleared, the output of the multiplexer is
disabled.

LWR STOP

12.5.12
Diagnostic Register
The diagnostic register is an 8-bit register that allows the microcode to generate signals to test the parity
check circuits during diagnostic mode. The Diagnostic Register is shown just above the Scratchpad RAM
in Figure 12-2 and is writable by the Upper and Lower Sequencers. Figure 12-14 shows the bits in this
register. Table 12-6 describes the bits in this register.

Table 12-6 Diagnostic Register Bit Description
Bit

Description

La PAR TEST

C, D, E-rev etch
Forces bad parity to be written into Data or Control Memory, depending on
which is being written. This bit forces bad parity into tht> low byte only. When
the system receives an initialize, the bit comes up asserted low forcing parity
errors on the bus. To access the bus with no parity errors, this bit is set 1. This
applies to diagnostic mode only.
F-revetch
Any time this bit is a I, bad parity is generated.

HI PAR TEST

Same as LO PAR TEST, only this bit controls the high byte.

PARITY FORCE

Forces bad parity to be generated across the output of the Control Store instruction word.

12-27

DATA CHANNEL MODULE

Figure 12-14

Diagnostic Register

lO PAR TEST

BF BUS 008
HI PAR TEST
BF BUS 009
PARITY FORCE
BF BUS 010
3R
BFBUS011

BF BUS 012

BF BUS 013

BF BUS 014

BF BUS 015

OIAG MODE
lO OIAG REG

EN P08
ClK
CX-1210A

12-28

DATA CHANNEL MODULE

12.5.13
Control Error Register
Once the Upper Sequencer checks the Upper Test Multiplexer signal CNTL ERRSUM and finds it
asserted, it then can read the Control Error Register and determine which error generated the CNTL
ERRSUM. The following errors can assert CNTL ERRSUM:

CNTLNXM
C DATA PAR ERR
C BUS ERROR
RESP PLS MSNG
INSTR PAR ERR
The error register also includes some Control Bus status signals as shown in Figure 12-15. Table 12-7
describes the bits in this register. The Control Error Register is shown just above the Control Store in
Figure 12-2.
Figure 12-15

Control Error Register

CAOR 00

KL BUS 000

CCYCLE 0

KL BUS 001

CCYCLE 1

KL BUS 002

CCYCLE 2

KL BUS 003
P01

C BUS ERROR

KL BUS 004

CNTL NXM

KL BUS 005

C DATA PAR ERR

KL BUS 006

INSTR PAR ERR
RESP PLS MSNG

KL BUS 007

LJPR CLK PRES

KL BUS 014

SYNC RT PAR ERR

KL BUS 015

KLBUS013

POB
CX-1211A

12-29

DATA CHANNEL MODULE

Table 12-7 Control Error Register Bit Description
Bit

Description

CADR 00

This bit is the least significant bit of the Control Bus Address used on the last
Control Bus Cycle by this module.

CCYCLE <2:0>

These three bits define what type of cycle was performed on the last Control
Bus Cycle by this module.

C BUS ERROR

This bit is the state of the CERR signal from the last Control Bus Cycle by this
module. Once set, this bit remains set until cleared by reading this register.

CNTL NXM

This bit is the state of the CACK signal from the last Control Bus Cycle by this
module. Once set, this bit remains set until cleared by reading this register.

C DATA PAR ERR

This bit indicates that there was a parity error on the Control Bus. Once set,
this bit remains set until cleared by reading this register.

INSTR PAR ERR

This bit indicates that there was a parity error in the instruction word coming
from the Control Store.

RESP PLS MSNG

This bit indicates that a transmission error from the drive occurred. This
could be an extra pulse or a missing pulse over the SDIISTI connection.

UPR CLK PRES

This bit is not actually an error, but it is used to determine if a drive is in the
off or offline state. In the offline state, clock transitions are present on the
Real-Time Drive State line. In the off state or during drive initialization, clock
transitions are not present.

SYNC RT PAR ERR

This bit indicates that a parity error or a transmission error occurred in the
real-time state serializer/deserializers.

12.5.14
Data Error Register
The Lower Sequencer reads the Data Error Register to determine if any errors occurred in the logic it
controls. There is no ORing of data errors like the CNTL ERRSUM for the Upper Sequencer. The error
register also includes some Data Bus status signals as shown in Figure 12-16. Table 12-8 describes the
bits in this register. The Data Error Register is shown just above the Control Store in Figure 12-2.

12-30

DATA CHANNEL MODULE

Figure 12-16 Data Error Register

DADR16

KL BUS DOO

DADR 17

KL BUS D01

DNMA

KL BUS D02
P02

DATA NXM

KL BUS D05

DATA PAR ERR

KL BUS D06

D BUS OVRRN

KL BUS D07

SYNC RT PAR ERR

KL BUS DOa

DATA PLS MSNG

KL BUS D13

DSERDES OVRN

KL BUS D14

ECC ERROR

KL BUS D15
poa

CX-1212A

Table 12-8

Data Error Register Bit Description

Bit

Description

DADR < 17:16 >

These two bits contain the two MSBs of the Data Bus Address used on the last
Data Bus Cycle by this module.

DNMA

This bit reflects the state of the DNMA signal from the last Data Bus Cycle by
this module.

DATA NXM

This bit is the state of the DACK signal from the last Data Bus Cycle by this
module. Once set, this bit remains set until cleared by reading this register.

DATA PAR ERR

This bit indicates that there was a parity error on apr. 'vious Data Bus cycle
by this module. Once set, this bit remains set until cleared by reading this
register.

D BUS OVRRN

This bit indicates that a Data Bus Cycle was requested when the previously
requested cycle had not yet completed. Once set, thi~ bit remains set until
cleared by reading this register.

12-31

DATA CHANNEL MODULE

Table 12-8 (Cont.)

Data Error Register Bit Description

Bit

Description

SYNC RT PAR ERR

This bit indicates that a parity error or a transmission error occurred in the
real-time state serializer/deserializers.

DATA PLS MSNG

This bit indicates that a data transmission error from the drive occurred. This
could be an extra pulse or a missing pulse over the SDIISTI connection.

DSERDES OVRN

This bit indicates that there was a Data SERDES overrun. The Lower Sequencer
did not transfer the data to or from the Data SERDES fast enough.

ECC ERROR

This bit indicates that there was an Error Correction Code (ECC) error on a
data read operation.

12.5.15
Status Register
The Status Register is gated onto the backplane by the P.ioc to check the status of the K.sdi/K.sti. The
Status Register is shown in the lower-left-hand corner of Figure 12-2. The Status Bus Register is loaded
by microcode from BF BUS 0< 15:08> (Figure 12-17).
Figure 12-17 Status Register

BF BUS 009 -

BF BUS 010 -

BF BUS 008

BF BUS 011

AOY

f--

STATUS 00

A1Y

r-- STATUS 01

A2Y

f--

STATUS 02

A3Y

f--

STATUS 03
TO P.ioc/P.ioj

r--O EN
BF BUS 012

BF BUS 013

BF BUS 014

BF BUS 015

B3
- - 0 EN

CLEAR IN -0 ClR
lO STATUS REG
ClK P8

BOY

STATUS 04

B1Y

STATUS 05

B2Y

STATUS 06

B3Y I-- STATUS 07
P8

S ENABLE l _
(FROM P.ioc/P.ioj)
CX-1213A

12-32

DATA CHANNEL MODULE

12.5.16
Control Bus Interface
The Control Bus Interface is associated with the Upper Sequencer. The Upper ~;equencer uses this
bus to access the HSC Control Memory which contains the control structures defining the work to
be performed by K.sdi/K.sti. The Upper Sequencer scans predefined areas of Control Memory for
work and nlanipulates the control structures. The K.sdi is capable of maintaining data rates up to 2.22
megabytes per second on this bus. For Control Bus timing information, refer to Chapter 3. The Control
Bus Interface is shown in the lower-left-hand corner of Figure 12-2.
The interface is implemented with 2917 A-type latched bus transceivers plus a separate byte parity generator which is shared with the Data Bus.
The Control Bus Address Transceivers are read or written by microcode. When a Control Memory
write is performed, the hardware provides an automatic wrap around so that the contents may be
read and verified. These transceivers are latches only. The Control Bus Address must be incremented
by microcode and reloaded for each Control Memory access. The value obtained from reading the
transceivers is the address used in the last completed bus cycle.
Notice in Figure 12-18 that the result obtained from reading the Control Bus Address does not have the
same organization as required when loading it. The signals BUS D < 15:00> go to CADR < 16:01 >.
The signals BR ADR < 11:08> go to CADR 00 and CCYCLE < 2:0 >. When the Upper sequencer reads
the register, CADR 00 and CCYCLE <2:0> go to KL BUS <03:00>.
The Control Bus Data Transceivers may be read or written by microcode. When a Control Memory
write is performed, the hardware provides automatic wrap around so that the contents may be read and
verified. This read is organized exactly the same as the word that was gated to the data transceivers
(including parity). The value obtained does not represent what is actually in memory as a result of the
bus write (although this would be the typical result), but only what the K.sdi/K.sti transceivers placed
on the backplane bus lines during the bus cycle.
Control Memory cycles are initiated when SET C REQ is specified in Control Store BUS DEST < 2:0 >.
During execution of this instruction BR ADR < 10:8> determine the type of bus .:-:ycle which will be
performed, and BR ADR 11 controls the least significant address bit (Figure 12-18).
12.5.17
Data Bus Interface
This interface is similar to the Control Bus interface, except that it is associated with the Lower Sequencer.
It is used to access the HSC Data Memory during data transfers. Data to be sent to the disk/tape is read
from Data Memory, while data obtained from the disk/tape is written into Data Melnory prior to being
routed to the next process associated with the data transfer. The K.sdi/K.sti is capable of maintaining
data rates up to 6.66 megabytes per second on this bus. For Data Bus timing information, refer to
Chapter 3. The Data Bus Transceivers and Address Register are shown on the left ~ide of Figure 12-2.

12-33

-t

~
(')

::E:

Figure 12-18 Control Memory Address Register

Z
Z

m
r-

Kl BUS D15 H

KlBUSDll H

Kl BUS D07 H

Kl BUS D03 H

Kl BUS DOO H

C
Kl BUS Dl0 H

Kl BUS D14 H
REC

REC

3
RD CNTl ADDR l
C ADR ClK l

CADR 16 l

""""
I

Kl BUS D06 H
REC

Kl BUS D13 H

Kl BUS D09 H

Kl BUS D12 H

Kl BUS 008 H

REC

Kl BUS D04 H

lATCH

CADR 12 l

CADR 08 l

REC

Kl BUS D05 H
3

CADR 04 l

Kl BUS DOl H

Kl BUS D02 H

Kl BUS DOl H

Kl BUS D02 H

Kl BUS 000 H

Kl BUS D03 H

RD CNTl ERR BITS l

EN
lATCH

CADR 00 l

CADR 15 l

CADR 11 l

CADR 14 l

CADR 13 l

CADR 10 l

BUSDllH

BUS 007 H

CGRANT l

CCYClE 1 l

CADR 01 l

CCYClE 2 l

BR ADR 11 H

BUS 002 H

XMIT

BUS

CADR 02 l

BUS 003 H

BUS 006 H

BUS 010 H
XMIT
2

CADR 05 l

CCYClE 0 l
BUS

BUS
CADR 06 l

CADR 09 l

CADR 03 l

CADR 07 l
BUS

SUS

BR ADR 10 H

XMIT

BUS 009 H

BUS 005 H

BUS 001 H

BR ADR 09 H

BUS D08 H

BUS 004 H

BUS 000 H

BR ADR 08 H

ClK

CX-1214A

DATA CHANNEL MODULE

12.5.17.1
Data Bus Data Transceivers
The Data Bus Data Transceivers are read or written by microcode, and the value obtained when reading
the Data Transceivers has exactly the same format as required to write them. When a Data Memory write
is performed, the hardware provides an automatic wrap around so that the data and address contents
may be read and verified. The value obtained does not represent what is actually in memory as a result
of the bus write (although this would be the typical result), but only what the transceivers placed on the
backplane bus lines during the bus cycle.
Data Bus cycles are initiated by either writing (which initiates a write cycle) or re.1ding (which initiates a
read cycle) the Data Bus Data Transceivers.
The Data Bus Data Transceiver Drivers are controlled by the RD MODE signal from Lower IOC Control
Latch bit 5. If RD MODE is clear, these drivers will not drive the bus. If RD MODE is set, these drivers
will be gated onto the bus during each Data Bus cycle. This is true regardless wh(·ther a cycle is initiated
by a load or a read of the data transceivers.
NOTE
The term read is in reference to the disk/tape, not
to Data Memory.
Data Bus Address
12.5.17.2
This interface consists of 2917 A-type latched bus transceivers, but includes an up/down counter for the
address. The Data Bus Address Transceivers and counter are loaded by microcode, and the transceivers
may be read by microcode. Note that the result obtained from reading the Data Bus Address Transceivers
does not have the same organization as required when loading it (Figure 12-20). The value obtained
from reading the transceivers is the address used in the last completed bus cycll'.
The Data Bus address is 18-bits wide. The 12 least significant address bits are derived from a counter
which is automatically incremented (or decremented) at the end of each Data Bus cycle. Normally, the
address is written prior to beginning a block transfer, and it is not rewritten while the block transfer is
in progress. However, this counter will not cross 4 Kword boundaries.
Figure 12-19 shows a simplified diagram of how the Data Bus address is encoded. The microcode must
assert the signal LD D ADR twice to generate the Data Bus address. On the first LD D ADR, BF BUS
< 4:0> is clocked into the 5 bit latch. On the second LD D ADR, the following registers bits are clocked:
•

The 5-bit latch is clocked into counter bits < 04:00 >

•

The BF BUS D<06:00> are clocked into the counter bits <11:05>

•

The BF BUS D < 12:07> are clocked into Data Bus Address Transceivers

12-35

DATA CHANNEL MODULE

Figure 12-19

Data Bus Address Transceivers and Counter
QUAD
XCVR
2917A
E54

REC
RD D ADR REG l - - C EN
DGR l -rC lATCH

DADR07L~
DADR 06 l
A34
DADR 05 l
DADR 04 l

A32
A31

UP/DOWN
COUNTER
7415191
E55
BF BUS D02 H -

BF BUS DOl H -

BF BUS DOO H -

b- HI ADR ClK H

.....

- DO

BF BUS D03 H

BF BUS D02 H

BF BUS DOO H

CLEAR IN l
lD D ADR REG l

D4
D5

---c ClR

CLI<

R4
R2
Rl

RIP ClK
ClK
DGRl r - UP/DRN
CNTR GND l

DADR03L

DADR 02 l
DADR 01 l
DADR 00 l

R4
R5

RD D ADR REG l
DGR l

UP/DOWN
COUNTER
7415191
E64

BF BUS D04 H

Kl BUS D03 H
Kl BUS D02 H
2 I-- Kl BUS DOl H
3 ~ Kl BUS DOO H

0
1

REC

6 D FF
7415174
E47

QUAD
XCVR
2917A
E29

ClK
UP /DRN

DREQFF H - CLI<

,..,
...... EN
,.., lOAD

CNTR GND l
lD D ADR REG l

BF BUS DOl H

-C

0
1
XMIT
2
3
EN

BUS

RIP ClK

r--

~
~

0
1
2
3

lO ADR ClK H

0 ~ Kl BUS D07 H
1 ~ Kl BUS D06 H
2 - Kl BUS D05 H
3 I-- Kl BUS D04 H

- - 0 EN

BUS

f-o 3

hl
l...c

P- lO ADR ClK H

-rO lATCH

f-o 0
~
A29
f-O 1
A28
f-o 2
A27

f--

DREQ FF H -

0
1
XMIT
2
3
EN
ClK

- ~ EN
r
'-

lOAD

-'-

CX-1215A

Sheet 1 of 2

(Continued on next page)
12-36

DATA CHANNEL MODULE

Figure 12-19 (Cont.)

Data Bus Address Transceivers and Counter

OUAD
XCVR
2917A
[38

"I'

[c ~
I

RD D ADR REG l
DGR l
DADR 11 l
DADR 10 l
DADR 09 l
DADR 08 l

UP/DOWN
COUNTER
7415191
E107
BF BUS D06 H

BF BUS D05 H

BF BUS D04 H

BF BUS D03 H

----dEN

LATCH
0

3
0
1

2
3
DREQ FF H

BUS

Kl BUS Dl1 H
Kl BUS Dl0 H
KL BUS D09 H
Kl BUS D08 H

XMIT

EN
eLK

RIP ClK
HI ADR ClK H

ClK
UP/DRN

CNTR GND l
lD DADR REG l

----r-<
----~n

EN
lOAD

QUAD
XCVR
2917A
E62

+5.0V

REC
RD DATA ERR BITS l
DGR l

EN
lATCH

0
1
2
3

QUAD
XCVR
2917A
E46

Kl BUS D03 H
Kl BUS D02 H
Kl BUS D01 H
Kl BUS DOO H

0
I~EC

RD D ADR REG l
DNMA H
DADR 17 l
DADR 16 l

0
1
2
3

DADR 15 l
DADR 14 l
DADR 13 l
DADR 12 l

BUS

FN
LArCH
0
1

2
3

Kl BUS D15 H
Kl BUS D14 H
Kl BUS D13 H
Kl BUS D12 H

BUS

0
NON MEM ACC l
BF BUS D12 H
BF BUS D11 H

2
3

lD D ADR REG l

EN
ClK

XMIT

BF BUS D10 H
BF BUS D09 H
BF BUS D08 H
BF BUS D07 H

1
.J

XMIT

!.N

lDDADRREGl

ClK
CX-1215A

Sheet 2 of 2

12-37

DATA CHANNEL MODULE

Figure 12-20 Generating the Data Bus Address
MSB

BF BUS

LSB

I~
'---y---'
NOT USED

I I I I I716 I

COUNTER

MSB

DATA BUS ADDRESS TRANSCEIVERS

LSB

CX-1216A

12-38

DATA CHANNEL MODULE

Note that counter bits < 04:00 > are derived from the latch, not directly from the BF BUS lines. In order
to correctly write the entire address, LD D ADR REG must be executed twice. The first write places
the desired contents of address < 04:00 > on BF BUS < 04:00 >. The second write places the desired
contents of address < 17:05 > on BF BUS < 12:00>.
The procedure to start a data transfer is:
1.

Write the least significant five address bits

Write the remainder of the address

Perform one dummy data read (if it is a memory read operation)

Move a data word, conditioned on completion of previous word

Repeat the above step until the transfer is complete

12-39

DATA CHANNEL MODULE

12.5.18
Sector/Index PALs
The Sector/Index PALs latch the occurrence of the sector and index pulses so that microcode can deal
with them via polling. The PALs are shown to the right of the Scratchpad RAM in Figure 12-2. The
index < 3:0 > and sector < 3:0> come from the real-time drive state deserializers shown in the lowerright hand corner of the block diagram. The PALs have 16 outputs which are 4 groups of 4. Figure 12-21
shows the SectorlIndex Register, and Table 12-9 describes the bits in the register.
One input to the PALs is from two jumpers (WI and W2). These two jumpers configure the Data Channel
Module as an K.sdi or an K.sti.

Figure 12-21 Sector/Index Register

~~~~~~~~--;;-r;'~M

~~~~~~~~~~~

CXO-1274A

Table 12-9 Sector/Index Register Bit Description
Bits

Description

ISD<3:0>

Index or Sector pulse detected from the corresponding disk drive. The Control Sequencer
uses these bits to keep track of the rotational position of each drive. When the Control
Sequencer reads this register, any set bits are cleared. The PAL logic will not attempt to
clear the sector or index bits if the bits are not set.
Not used for K.sti.

ID<3:0>

Index pulse detected from the corresponding disk drive. Similar to ISO<3:0>.
This bit is not used for an on-line Tape Formatter.
This bit is the latched low order bit of the event counter from an off-line Tape Formatter. The Upper Sequencer tests this bit and the SI bit for a state change in the Tape
Formatter.

IV<3:0>

Index valid from the corresponding drive. These bits are set by the assertion of Index
pulse and remain set until either sequencer issues a clear or until a Sector pulse is received and that drive's ISO bit is still set. For example, the sector counter for that drive
is no longer valid because of a previously unrecognized Sector pulse.
Not used for K.sti.

12-40

DATA CHANNEL MODULE

Table 12-9 (Cont.)

Sector/Index Register Bit Description

Bits

Description

515<3:0>

Synchronized Index or Sector pulse from the corresponding drive. the Data Sequencer
uses these bits to detect sector boundaries.
This bit has the following two meanings in an K.sti:
Tape Formatter on line: A latch copy of the Acknowledge bit from the Tape Formatter. The Acknowledge bit indicates whether a data transfer completed successfully.
Tape Formatter off line: This bit is the latched second least significant low order bit
of the event counter from an off-line Tape Formatter. The Upper Sequencer tests this bit
and the ID bit for a state change in the Tape Formatter.

12.6 INPUT AND OUTPUT TO THE STANDARD DISK/TAPE INTERCONNECt
The right side of Figure 12-2 shows the logic that the K.sdi/K.sti uses to communicate with the drive
over the Standard Disk Interconnect (SDI) or the Standard Tape Interconnect (51'1). The SDIISTI is
shown on the upper-right of the block diagram. The K.sdi/K.sti has four ports and there are four hybrid
receiver/driver circuits that drive the SDIISTI ports.
The K.sdi/K.sti performs seven different functions over the SDIISTI:
•

Sends level 2 commands to a drive. (A level 2 command requires two or more bursts of
information to transfer the command to a disk drive or a tape formatter. It also requires a
response. An example of a level 2 command would be a seek command to a disk drive or a
position tape command for a tape formatter.)

•

Receives level 2 responses from a drive. (A level 2 response from a disk drive or tape formatter
is two or more bursts of information in response to a level 2 command frOIn the controller.)

•

Sends level 1 comrnands to a drive. (A level 1 command is one burst of information to a disk
drive or tape formatter. This command does not require a response. Examples of a level 1
command are select group for a disk drive and read for a tape formatter.)

•

Sends data to to be written on a drive.

•

Receives data read from a drive.

•

Sends real-time controller state to a drive.

•

Receives real-time drive state from a drive.

Instead of describing the individual blocks on the right-hand side of Figure 12-2, the following sections
and figures describe the blocks as functions. The descriptions start with the top block and work toward
the bottom.
NOTE
Any special chip used on the K.sdi/K.sti is described in detail in HSC50170 Chip Descriptions Technical Manual (EK-HSS74-TM).

12-41

DATA CHANNEL MODULE

12.6.1
Send Level 2 Commands to a Drive
The Upper Sequencer can send a level 2 SDIISTI comnland to a drive. The Upper Sequencer gets the
level 2 commands (INITIATE SEEK, GET STATUS, ... ) from Control Memory and controls the logic
that passes them from the Control Memory Transceivers to the Write/Command Data line on the SDI
/STI. You have already read how the Upper Sequencer gets data from the Control Memory Transceivers.
In this section, you will read how the Upper Sequencer controls the logic that turns the parallel data
BUS D < 15:00> into pulse-encoded information on the SDIISTI. The level 2 commands go from the
Control SERDES to the Write/Command Data Line through the logic shown in Figure 12-22.

Figure 12-22 Send Level 2 Commands to a Drive Block Diagram
TTl~ECl

DC026

DC027

CONTROL
SERDES
DC018
OUT

o
o
U'i

DRV 1 DATA
DRV 2 DATA
DRV 3 DATA

ClK t4-..&..---""'""'"'I
DATA IN ........- - - - - - 1
P09

DRV 0 RTDS

RTDS
R/R
DATA

RTC DATA 0

RTCS

W/C
DATA

Cl
CJ)

co
UPR MUX EN
UPR DRV SEl

'--...,...-J
DATA
SERDES
DEMULTIPLEXER

CX-1217A

Each word of the command goes from BUS D < 15:00> to the SDIISTI through the following logic:
1.

The Control SERDES serializes the parallel information from BUS D< 15:00 >. The clock for
the SERDES chip is derived from the Read/Response Data line on the SDIISTI.

The serial output of the SERDES is synchronized by a flip/flop to produce NRZ information.

This NRZ information is then converted from TTL to ECL before being sent to the encoder (06
Pll).

The encoder then encodes the NRZ information to the pulse encoding for the SDI/STI.

The output of the encoder is then sent to the demultiplexer (04 P14).

The UPR DRV SEL signals, from the Upper Control Register, select which SDIISTI Driver the
information is going to. The output of the demultiplexer is wire ORed with the output of the
Data SERDES Demultiplexer. The signal UPR MUX EN, from the Upper IOC latch, selects this
demultiplexer.

The output of the denlultiplexer is sent to the SDIISTI Driver where it is then sent over the
Write/Command Data line. In this block diagram the driver selected was (B8 P14) for port O.

12-42

DA r A CHANNEL MODULE

12.6.2
Receive Level 2 Responses from a Drive
The Upper Sequencer controls receiving the serial level 2 responses from the drive, converts it to
parallel, and then transfers it to Control Memory. You have already read how the Upper Sequencer
loads the address and data for Control Memory. In this section, you will read how the Upper Sequencer
controls the logic that receives the serial data and turns it into parallel information for BUS D < 15:00>.
A level 2 response from the drive goes from the Read/Response line to BUSD < 15:00> through the
logic shown in Figure 12-23.

Figure 12-23

Receive Level 2 Responses from a Drive Block Diagram
DC026

DC027
ENCODER

CONTROL
SERDES
DC018

OUT

+
0
0

t!i

ClK
DATA IN
P09

DRV 1 DATA
DRV 2 DATA
DRV 3 DATA
D5
Pll

DRV 0 RTDS

RTDS
R/R
DATA

RTC DATA 0
WRT DAT,\ 0

RTCS

D6 -

WIC
P14

DATA

UPR DRV SEl

Cl
(f)

::J
CD

CX-1218A

Each word of the response comes from the SDIISTI (right side of block diagranl) to BUS D < 15:00 >
through the following logic:
1.

The response information comes into the SDIISTI Receiver (A8 P14) from the Read/Response
Data (R/R DATA) line (port 0 in this block diagram).

The information from the SDIISTI Receiver (DRV x DATA) is one of four inputs to the multiplexer (C1 PI4). The UPR DRV SEL signals from the Upper Control Register select which input
to gate through the multiplexer.

The output from the multiplexer is an input to the decoder (D6 Pll). The decoder decodes
the pulse information and generates clock and data. This information is changed from ECL to
TTL. The Control SERDES changes it from serial to parallel.

When the information is ready, the Upper Sequencer is signaled, and it then moves the information from the Control SERDES over BUS D < 15:00> to the Control Bus.

12.6.3
Send Level 1 Commands to a Drive
The Lower Sequencer can send a level 1 SDIISTI command to a drive. The cOlnponents of the path
are the same type as those described in Section 12.6.1. The Lower Sequencer gets the level 1 SDIISTI
command from Scratchpad RAM and controls the logic that passes it to the Write/Command Data line
on the SDIISTI. In this section, you will read how the Lower Sequencer controls the logic that turns the
parallel data BUS D < 15:00> into pulse-encoded information on the SDIISTI. A level 1 command goes
to the Write/Command Data line on the SDIISTI through the logic shown in Figure 12-24.

12-43

DATA CHANNEL MODULE

Figure 12-24 Send Level 1 Commands to a Drive Block Diagram
DC026
DRV 0 RTDS

RTDS
R/R
DATA

RTC DATA 0

RTCS

W/C
DATA

------t

BUSD15:00 .........

DATA
SERDES
DC018
16 BIT
TTL OUT
ClK
DATA IN
OUT P09

[
CONTROL
SERDES
DEMULTIPLEXER

WRT DATA 1

-+-it-r-l~ WRT DATA 2
-+-i1+Ti~ WRT DATA 3

lWR MUX EN
lWR DRV SEL
DC027

DRV 1 ClK
DRV 2 ClK
DRV 3 ClK

ClK
C5
Pll

CX-1219A

The level 1 SDIISTI command goes from BUS 0 < 15:00> to the SDIISTI through the following logic:
1.

The Data SERDES serializes the parallel information from BUS D<15:00>. The clock for the
SERDES chip is derived from the Read/Response Data line on the SDIISTI.

The output of the SERDES is synchronized by a flip/flop.

This NRZ information is then converted from TTL to ECL before being sent to the encoder (C6
P11).

The encoder encodes the NRZ information to the pulse encoding for the SDIISTI.

The output of the encoder is sent to the demultiplexer (C4 P14).

The LWR DRV SEL signals, from the Lower Control Register, select which SDIISTI Driver the
information is going to. The output of the denlultiplexer is wire ORed with the output of the
Control SERDES Demultiplexer. The signal LWR MUX EN, from the Lower Control Register,
selects this demultiplexer.

The output of the demultiplexer is sent to the SDIISTI Driver where it is then sent out over the
Write/Command Data line. In this block diagram the driver selected was (B8 P14) for port O.

12-44

DATA CHANNEL MODULE

Send Data to a Drive
12.6.4
The Lower Sequencer is the only sequencer that can send data to a drive. It uses the Data SERDES.
However, the data must also pass through the ECC SERDES (Figure 12-25). The Lower Sequencer gets
the data from Data Memory and moves it from the Data Bus Transceivers to the Data SERDES over BUS
D<15:00>.
Figure 12-25 Send Data to a Drive Block Diagram
DC026
DRV 1 RTDS

RTDS
R/R
DATA

RTC DATi\ 1

RTCS

W/C
DATA

ECC OUT 09:00 . . . .

' - - - - - - 4 SERDES

BUSD15:00 .......

DC018
16 BIT
TTL OUT 1 - - -....
ClK
DATA IN
OUT P09

WRT DATA 0

ECC
SERDES
DC018
10 BIT

WRT DATA 2
WRT DATA 3

lWR MUX EN
lWR DRV SEl
DC027

DRV 0 ClK
DRV 2 ClK
DRV 3 ClK

ClK

CX-1220A

The data goes from BUS D < 15:00 > to the SDIISTI through the following logic:
•

The Data SERDES serializes the parallel data from BUS D< 15:00>. The clock for the SERDES
chips is derived from the Read/Response Data line on the SDIISTI. This time the data goes out
the TTL OUT line to the ECC SERDES.

•

The ECC SERDES does two things:
•

Converts the serial data to 10-bit parallel data and writes it to the Reed Solomon ECC
Generator (R-S Gen)

•

Synchronizes the serial data with a flip/flop

•

This NRZ data is converted from TTL to ECL before being sent to the encoder (C6 Pll).

•

The encoder encodes the NRZ data to the pulse encoding for the SDIISTI.

•

The output of the encoder is sent to the demultiplexer (C4 PI4).
12-45

DATA CHANNEL MODULE

•

The LWR DRV SEL signals, from the Lower Control Register, select which SDIISTI Driver the
information is going to. The output of the demultiplexer is wire ORed with the output of the
Control SERDES Demultiplexer. The signal LWR MUX EN, from the Lower Control Register,
selects this demultiplexer.

•

The output of the demultiplexer is sent to the SDIISTI Driver where it is then sent out over the
Write/Command Data line. In this block diagram the driver selected was (B6 P14) for port 1.

•

The above sequence is repeated until the end of the sector or record. Then the Lower Sequencer
puts the ECC SERDES in parallel to serial mode. It then starts the R-S Generator sending its
170 bit ECC calculation to the ECC SERDES. The R-S Generator sends 10-bit symbols, one at
a time, to the ECC SERDES. The ECe SERDES converts the parallel 10-bit ECC symbols to
serial and sends them right behind the data to the drive.

12.6.5
Receive Data from a Drive
The Lower Sequencer controls receiving the serial read data from the drive, converts it to parallel, and
then transfers it to Data Memory. You have already read how the Lower Sequencer loads the address
and data for Data Memory. In this section, you will read how the Lower Sequencer controls the logic
that receives the serial data and turns it into parallel data for BUS D < 15:00 >. Figure 12-26 shows the
logic that receives the data, decodes it, and converts it to parallel.
Figure 12-26

Receive Data from a Drive Block Diagram

ECC OUT 09:00'"

BUS D15:00 .......
16 BIT
TTL OUT
ClK
DATA IN
OUT P09

ECC
SERDES
DC018
10 BIT
TTL IN
ClK
DATA IN
OUT P09

DC027
ENCODER

DRV 0 ClK
DRV 1 ClK
DRV 2 ClK

DATA

DC026

ClK

RTDS

RIR

DATA

RTC DATA 3
WRT DATA 3

L._.----~

RTCS
W/C
DATA

CX-1221A

12-46

DAfA CHANNEL MODULE

The data goes from the SDIISTI (right side of block diagram) to BUS D < 15:00> through thefollowing
logic:
1.

The read data comes into the SDIISTI Receiver (A3 P14) from the Read/Response Data (R/R
DATA) line (port 3 in this block diagram).

The data from the SDIISTI Receiver (DRV x DATA) is one of four inputs to the multiplexer
(AliBI P14). The LWR DRV SEL signals from the Lower Control Register select which input to
gate through the multiplexer.

The output from the multiplexer is an input to the decoder (C6 P11). The decoder decodes the
pulse information and generates clock and serial data. This infornlation is changed from ECL
to TTL.

The serial data is then clocked into the Data SERDES and ECC SERDES at the same time.

The Data SERDES converts the serial data to 16-bit parallel data and ~:;ignals the Lower Sequencer that a word of data is ready. The Lower Sequencer moves the data to the Data Bus
Transceivers.

As the Data SERDES is converting, the ECC SERDES is converting the serial data to 10-bit
parallel symbols for the R-S Generator.

At the completion of the transfer, the R-S Generator checks to see if it has a zero ECC. If the
ECC is zero, it is correct. If the ECC is not zero, the ECC ERROR bit is set in the Data Error
Register.

12.6.6
Send Real-Time Controller State to a Drive
The lower-right side of Figure 12-2 is where the logic converts the real-time controller state to serial
information and sends it over the SDIISTI. The Upper Sequencer or Lower Sequencer sends real-time
controller state to the drive. They cannot both send the state at the same time. FiguTes 12-27 and 12-28
show the inputs to the Real-Time State Serializers for the K.sdi and K.sti and the Real-Time Controller
State line for the given input.

12-47

DATA CHANNEL MODULE

Figure 12-27 K.sdi Real-Time Controller State

SEND]
UPR
RTCS
UPPER SEQUENCER REAL-TIME STATE SERIALIZER

ERmI =r==lli~~E I I

I:~~R I~i~Cr_~_:_EA_z~:_~_~_)
__

__]

REAL-TIME CONTROLLER STATE FROM UPPER SEQUENCER

LOWER SEQUENCER REAL-TIME STATE SERIALIZER

EA~I"~~~U~WI~E~~Cr P~~B~
GATE

GATE

(1)

(8 ZEROS)

-------

REAL-TIME CONTROLLER STATE FROM LOWER SEQUENCER
CXO-1272A

12-48

]

DATA CHANNEL MODULE

Figure 12-28

K.sti Real-Time Controller State

UPPER SEQUENCER REAL-TIME STATE SERIALIZER

REAL-TIME CONTROLLER STATE FROM UPPER SEQUENCER

LOWER SEQUENCER REAL-TIME STATE SERIALIZER

A:IITY=r=r=-rillLOCK
SLOW
-

KEE~JiitYNCI
(1)

GOING

PREAMBLE
(8 ZEROS)

---,--------'

REAL-TIME CONTROLLER STATE FROM LOWER SEQUENCER
CXO-1273A

The Upper Sequencer sends two signals to the drive:
•

RCVR RDY lets the drive know when it can send a response or attention n1essage

•

DRIVE INIT initializes the drive

The Lower Sequencer sends two signals to a disk drive:
•

WRITE GATE asserts logic in the drive to do a write data operation

•

READ GATE asserts logic in the drive to read data back to the K.sdi/K.sti

The Lower Sequencer sends two signals to a tape drive:
•

KEEP GOING optimizes the performance of streaming tape drives.

•

CLOCK SLOW indicates to the formatter that the K.sti is temporarily unable to support an
effective clock rate in excess of 8.8 MHz.

12-49

DATA CHANNEL MODULE

Figure 12-29 shows the logic to send real-time controller status to a drive. There is an Upper Sequencer
Real-Time Controller State Serializer (D7 P12) and a Lower Sequencer Real-Time Controller State Serializer (D4 P12).
NOTE
The Real-Time Controller State serializers send the
state when the least significant bit is set as an input
to the serializers. This bit is also the SYNC bit on
the Real-Time Controller State line.
Figure 12-29 Send Real-Time Controller State to a Drive Block Diagram
DC026
RTDS

DRV 0 ClK

DRV 1 DATA

DRV 2 ClK
DRV 3-ClK

RIR

DATA
RTCS

WRT DATA 1

W/C
DATA

STATUS BITS
SEND UPR RTCS
~-.....

RTCDATAO

H+-+-r..... RTC DATA 2
I-++-++~

DRV 0 ClK

RTC DATA 3

DRV 2 ClK
DRV 3 ClK
lWR MUX
EN
......_P_ll... lWR DRV
SEl

P14

CX-1222A

The real-time controller state for the Upper Sequencer goes through the following logic:
•
•

The clock for the serializer (D7 P12) comes from the Real-Time Drive State line on the SDIISTI.
TheUPR PROC STATUS BITS to the serializer (D7 P12) come from laC Control logic (RCVR
ROY) and Upper Control Register (DRIVE INIT).

12-50

DAfA CHANNEL MODULE

•

When the Upper Sequencer sets the SEND UPR RTCS bit in the Upper Control Register, the
serializer starts sending the real-time controller state until the bit is cleared. This bit is the least
significant bit of the serializer input.

•

The output of the serializer is changed from TTL to ECL and then pulse encoded (B6 Pll).

•

The multiplexer (07 P14) is selected by UPR MUX EN from the roc Control Logic. The port
driver is selected by UPR DRV SEL bits from the Upper Control Register (for this example,
port 1). Notice that the output of the multiplexer is wire ORed with the output from the Lower
Sequencer's multiplexer (C7 PI4). Only one multiplexer can be enabled at a time.

•

The selected drive (B6 P14) then sends the status over the Real-Time Controller Status (RTCS)
line on the SOIlSTI.

The Lower Sequencer does not set bits in a register to enable the Lower Real-Time Controller State
. Serializer (04 PI2). The status bits along with SYNC are generated through the ALU by the LITERAL
field and then written into the serializer.
12.6.7
Receiving Real-Time Drive State from a Drive
The drives send their real-time drive state over the Real-Time Drive State (RTOS) line to the port receivers
shown on the right side of Figure 12-2. The output of the receivers is DRV x RTOS. Figure 12-30 shows
the logic for the four ports receiving real-time drive state:
•

The real-time drive state comes into the receivers (not shown) whose output it DRV x RTDS.

•

The decoders (B6,A6,C3, and B3 Pll) change the pulse encoded SDIISTl state into NRZ. Then
the signal level is changed from ECL to TTL.

•

The state is then deserialized. There are two types of deserializers. The deserializers for port
o and 1 are also serializers for real-time controller state which you saw in Section 12.6.6. Ports
2 and 3 are in one chip (C2 PI2).

•

The Upper Sequencer or Lower Sequencer can read the DRV STATUS BITS for a particular
port by asserting ENA DESER x.

•

Some of the DRV STATUS BITS are inputs to the test multiplexer.

12-51

DATA CHANNEL MODULE

Figure 12-30 Rec;:eiving Real-Time Drive State from a Drive Block Diagram

ORV 0
RTOS

ORV STATUS BITS
ENA OESER 0

ORV 1
RTOS
OC027
ENCODER
DRV STATUS BITS
ENA OESER 1

TTL.-.ECL

- 9 ORV 2 RTOS

ORV STATUS BITS
ENA OESER 2
ORV STATUS BITS
ENA OESER 3

ORV 3 RTOS

CX-1223A

12.7

MICROINSTRUCTION
This section describes the organization and purposes of the fields within the microinstruction word.
The microinstruction is 48-bits wide. The microinstruction word is divided into 16 fields, each of which
controls different portions of the K.sdi/K.sti hardware. Figure 12-31 shows the fields and their position
within the microinstruction word. The following sections describe each of these fields.

12.7.1

C Field
The C field is the carry-in into the ALU for the current microinstruction. It steers the literal to the most
significant byte for AF fields 3 through 7.

12-52

DATA CHANNEL MODULE

Figure 12-31

Microinstruction Word Description

44 43

41 40

38 37 36 35

IOC
TEST

RA/BS

LITERAL

28 27

25 24 23

20 19

BRANCH ADDRESS (BA)

15 14 13

00
CX-1224A

12.7.2
AD Field
The AD field, ALU destination, determines the routing of the ALU output data internal to the 2901.
Table 12-10 describes the decoding of the three bits in the AD field.

Table 12-10

Decoding Bits in the AD Field

Decode

Description

ALU to Q Register

No write

ALU to RB, output RA (RB if AS = 5 or 7)

ALU to RB

ALU/2 to RB, Q/2 to Q (right shift)

ALU 12 to RB (right shift)

ALU*2 to RB, Q*2 to Q (left shift)

ALU *2 to RB (left shift)

12-53

DATA CHANNEL MODULE

AF Field
12.7.3
The AF field, ALU Function, determines the operation to be performed by the ALU. Table 12-11
describes the decoding of the three bits in the AF field. The Rand S are the inputs to the ALU
(Figure 12-9).

Table 12-11

Decoding Bits in the AF Field

Decode

Mnemonic

ALU Function

ADD

R plus S

SUBR

S minus R

SUBS

R minus S

R OR S

AND

RANDS

NOTRS

(NOT R) AND S

XOR

RXOR S

XNOR

REX-NOR S

12.7.4
AS Field
The AS field, ALU source, selects two of the five possible sources for the ALU. Table 12-12 shows the
combination of the three bits in the AS field. The R, S, A, 0, B, 0, and Q are the inputs and outputs of
the ALU Data Source Selector in the ALU (Figure 12-9).

Table 12-12

Decoding Bits in the AS Field

Decode

12-54

DATA CHANNEL MODULE

AB Field
12.7.5
The AB field, ALU to BUS, determines whether ALU or the bus source decoder is the source for the
BUS. Table 12-13 describes the decoding of the bit in the AB Field.

Table 12-13 Decode the Bit in the AB Field
Decode

Description

Bus source to BUS D < 15:00>, D input to ALU is BUS D < 15:00 >

ALU to BUS D < 15:00>, 0 input to ALU is the LITERAL field

12.7.6
+ Field
The + field, EXEC IF COND TRUE, is one bit long. This bit is combined with the following signals to
generate INHIBIT EXEC (inhibit execute).
•

TST COND TR (test condition true)

•

COND EXC (conditional execute (Refer to Section 12.7.15»

INHIBIT EXEC prevents:
•

Any ALU operation of each instruction for which it is active

•

The lac Control latches from being enabled

•

The destination decoders from being enabled

Table 12-14 describes the decoding of the bit in the + field along with EXEC IF COND TRUE and TST
COND TR to generate INHIBIT EXEC.

Table 12-14 Decode the Bit in the + Field
COND
EXC

EXEC IF
CONDTRUE

TST COND
TR

INHIBIT
EXEC

CONDITION

Execute all operations

Stop ALU, laC, destination operations

Execute all operations

X = the state of the signal does not matter

RB Field
12.7.7
The RB field, B Port Register, selects one of the sixteen internal registers to be read and/or written by
the 2901 ALU. If a value of 58 or 78 is in the AS field, the A Port Register field (RA field) is forced to
the same value as the RB field.

12-55

DATA CHANNEL MODULE

TEST Field
12.7.8
The TEST field, TEST CONDITION < 03:00 >, selects one of 16 signals for the conditional operations
of the sequencers. The hardware includes two separate selectors, one for each of the two sequencers.
Table 12-15 shows the test conditions for the four bits of the TEST field. Tables 12-16 and 12-17 describe
what each bit is.

Table 12-15

Decode the Bits in the TEST Field

Decode

Upper Sequencer

Lower Sequencer

1 (True) always

Last Upper Sequencer
ALU result = 0

Last Lower Sequencer
AL U result = 0

Last Upper Sequencer
ALU carry out

Last Lower Sequencer
AL U carry out

Last Upper Sequencer
ALU MSB

Last Lower Sequencer
ALU MSB

Upper Sequencer
internal bus LSB

Lower Sequencer internal Bus LSB

Lower Sequencer flag

Upper Sequencer flag

Not used

Real-Time sector or index

Init/Fun Flag

Delayed zero test

Control Bus Error *

Data word clock

Control SERDES ready

Data SERDES ready

Drive attention

ECC symbol ready

Drive ready to receive

Drive available

R/T transmit ready

Drive Rd/Wrt ready

Not used

Zero ready

Control Bus Request Active

Data Bus Request active

* Inclusive or summation. Refer to Sections 12.5.17 and 12.5.16.

12-56

DATA CHANNEL MODULE

Table 12-16 Description of the Bits to the Upper Test Multiplexer
Bit

Description

Always a logical 1

Output of ALU equals a zero

Carry out of ALU from last Upper Sequencer operation

Most significant bit of the output from the ALU from last Upper Sequencer operation

Least significant bit of the BUS from last Upper Sequencer operation

This bit is writable by the Lower Sequencer and readable by the Upper Sequencer. Used by the
microcode to synchronize software operations between the Upper and Low£'r Sequencers.

Not used

This bit indicates whether the microcode is running diagnostics or functional code. The system
comes up with this bit cleared. This indicates that the K.sdi/K.sti is running diagnostic code.
When the diagnostic code is completed, this bit is set. This bit is set or cleared by the microcode
through the IOC Control logic on the output of the Control Store.

This bit is a summary of the following hardware detected error conditions:
Control Non Existent Memory
Control Data Parity Error
Control Bus Error
Drive Response Error
Instruction Parity Error
Refer to Section 12.5.13 for a description of the above errors.

This bit indicates that the Control SERDES is ready for a parallel 110 transfer depending on the
mode (read or write).

This bit is the drive attention bit from the selected port.

This bit is the the ready to receive bit from the selected port.

This bit is the port available bit from the selected port.

This bit is the read/write ready bit from the selected port. When this bit is asserted, it indicates
the drive may be written to or read from. If during a data transfer the drive detects an error, the
data transfer is aborted and the read/write ready bit is negated.

Not used

This bit indicates that a Control Bus Cycle is in progress. This bit is set when the request is
initiated and cleared at the completion of the data transfer.

12-57

DATA CHANNEL MODULE

Table 12-17

Description of the Bits to the Lower Test Multiplexer

Bit

Description

Always a logical 1

Output of ALU equals a zero from the last Lower Sequencer operation

Carry out of ALU from the last Lower Sequencer operation

Most significant bit of the output from the ALU from the last Lower Sequencer operation

Least significant bit of the BUS from the last Lower Sequencer operation

This bit is writable by the Upper Sequencer and readable by the Lower Sequencer. Used by the
microcode to synchronize software operations between the Upper and Lower Sequencers.

This bit is the real-time sector/index pulse for the drive selected by the Lower Sequencer.

This bit is the zero test bit from the ALU delayed one Lower Sequencer cycle.

This bit is data word clock (DATA WORD CLK) ORed with ALU carry (CI6). This bit is used at
the beginning of a data transfer to prevent the K.sdi/K.sti microcode from hanging. Data word
clock negates soon after the detection of the sync pattern. The microcode then monitors the
SERDES signal DATA WD RDY. If the drive fails and does not send a word to the SERDES, the
microcode hangs. If the data word clock is not detected within an allotted time, the ALU carry is
generated from a software timer that the microcode is looping on waiting for the data from the
drive. The ALU carry signal then allows the microcode to get out of the loop.

This bit indicates that the Data SERDES is ready for a parallel I/O transfer depending on the
mode (read or write).

This bit indicates that the RS Generator Chip has an ECC symbol ready to read.

This bit is the ready to receive bit from the selected port.

This bit indicates that another word can be parallel loaded into the Lower Real-Time Controller
State Serializer.

C, Of E-rev etch
This bit is zero test delayed (ZERO TST DL Y) (Bit 7) ANDed with the sector pulse (SECTOR H)
from the selected drive. This bit allows the software to set a counter and then loop looking for a
Sector pulse while decrementing the counter. If the drive is not working correctly and does not
send a Sector pulse, the counter goes to zero and the software exits the loop.
F-revetch
This bit is the AND of DATA WD RDY from the Data SERDES and DREQ FREE (the data bus is
not in use).

This bit indicates that a Data Bus Cycle is in progress. This bit is set when the request is initiated
and cleared at the completion of the data transfer.

12-58

DATA CHANNEL MODULE

DO Field
12.7.9
The BD field, bus destination, selects the register that will be loaded with the data that has been placed
on the BUS lines. Table 12-18 shows the decode of three bits.

Table 12-18

Decode the bits in the DO Field

Decode

Upper Sequencer

Lower Sequencer

NOP

Control Bus Data Xcvrs

Data Bus Data Xcvrs

Control Bus Address Xcvrs

Data Bus Address Xcvrs and Counter

Control SERDES

Data SERDES

Upper Control Register *

Lower Control Register *

Program Address Register

Status Bus Register

Lower Real-Time Control State

Scratchpad RAM

-----------------

* Also the Diagnostic Register

12.7.10
@ Field
The @ field, IOC enable, when set, permits the IOC field to modify the IOC latches. This bit is not set
when using the LITERAL field.
NOTE
The IOC field has dual functions: it can be gated to
the IOC Control latches when the @ field is set, or
the field can be the literal input to the ALU.
12.7.11
IOC Field
The IOC field, input/output control, if enabled by IOC ENABLE, modifies the IOC Latches. Bits
<22:20> select the desired latch, and bit 23 sets or clears that latch. Table 12-19 describes the decoding of the bits in the IOC field.

12-59

DATA CHANNEL MODULE

Table 12-19

Decode the Bits in the IOC Field

Decode

Upper's IOC

Lower's IOC

UPR PROC FLAG

LWR PROC FLAG

INIT/FUN FLAG

Not Used

RCVR RDY

Not Used

ROLL

ECC BYPASS

CNTL SERDES ENA

DATA SERDES ENABLE

RCV MODE

RD MODE

UPR SER MUX EN

ECC lac ENABLE

ENA DESER

ECC TIMING

RA Field
12.7.12
The RA field, A Port Register, selects one of the sixteen internal 2901 registers to be operated on by the
ALU. The RA field is a shared field and is only enabled if the AS field does not equal 58 or 78 and bit
AB does not specify the LITERAL field.
12.7.13
BS Field
The BS field, bus source, selects one of the K.sdi/K.sti registers which are external to the ALU. The
contents of the selected register are enabled onto the BUS lines, routed through the input multiplexer,
and presented to the D inputs of the 2901 ALU. Table 12-20 describes the decoding of the bits in the
BS field. The BS field is a shared field and is only enabled if the AS field equals 5 or 7 and AB equals

O.
Table 12-20 Decode the Bits in the BS Field
Decode

Upper Sequencer

Lower Sequencer

Nap

NOP

Control Bus Data Xcvrs

Data Bus Data Xcvrs

Control Bus Address Xcvrs

Low Order ECC Residue

Control SERDES

Data SERDES

SectorlIndex Register

Data Bus Address Xcvrs

Control Error Register

Data Error Register

Not Used

High Order ECC Residue

Scratchpad RAM

12-60

DATA CHANNEL MODULE

12.7.14
S Field
The S field, test sense, is XORed with the output of the Test Multiplexer to generate TST COND TR
(test condition true). TST COND TR is then combined with the branch address equal to 77778 and
JUMP CNTL 1 to determine whether the sequencer will output the Program Countt'r, the Stack, or the
Branch Address. Table 12-21 describes what operation is performed in the sequencer, depending on
the selected test condition and the TST COND TR signal.

Table 12-21

Decode the Selected Test Condition and TST COND TR

Select Test
Condition

TEST FOR
TRUE

TST COND
TR

Operation

Branch, Calt or Return

Increment

Branch, Calt or Return

12.7.15
$ Field
The $ field, conditional execute, enables all instructions when clear. When set, this bit enables the
conditional execution of the lOCi bus destination, and ALU instructions. Refer to Section 12.7.6 for a
description of how this bit and TST COND TR and EXEC IF COND TRUE work together.
12.7.16
K Field
The K field, jump controt is logically combined with TST COND TR and BR ADR < 11 :00> equal to all
ones (77778) to control the next operation of the 2911 Sequencers (Section 12.7.14). This combination
controls the operation of the internal Stack, and it determines whether the sequencer will output the:
•

Program counter

•

Stack contents

•

Branch address field

Table 12-22 describes the decode of the input signals for the sequencer operation.

12-61

DATA CHANNEL MODULE

Table 12-22

Decode Input Signals for Sequencer Operation
JUMP

TSTCOND
STACK

Operation

HOLD

Increment

HOLD

Increment

77778

HOLD

Increment

77778

HOLD

Increment

***

HOLD

Branch

***

PUSH

Call

77778

HOLD

Branch

77778

POP

STK

Return

Branch Address

CNT1 TR

***

* * * can be anything except 77778

P Field
12.7.17
The P field, instruction parity, is the single parity bit for the 48-bit microinstruction word. This bit is
calculated odd parity for the other 47 bits. If the number of 1 bits in the other 47 bits is even, then this
bit is a 1 making the 48-bit microinstruction word odd parity. If the number of 1 bits in the other 47 bits
is odd, then this bit is a 0 making the 48-bit microinstruction word odd parity.
BA Field
12.7.18
The BA field, branch address, provides the instruction address for conditional and unconditional
branches and subroutine calls. Also, during the execution of certain instructions, this field provides
supplemental data and control information (Section 12.7.19).
12.7.19
Destination and Branch Field Combinations
The BA field is not always a branch address. This field is also used for data and control for certain
instructions. When the BD field equals 2, these lines are used as data and control lines. These BA and
BD field combinations are described in the following two sections.
12.7.19.1
Write Control Bus Address Transceivers
Loading of the Control Bus Address Transceivers is done with BUS and the BR ADR lines. Bus lines
BUS D < 15:00> are latched and then gated onto CADR lines < 16:01 >, respectively, during the Control
Memory Cycle. BR ADR 11 is latched and gated onto CADR 00 (LSB). BR ADR < 10:08> are latched
and gated onto CCYCLE < 0:2 >, respectively. BR ADR 07 is latched and then determines, during the
Control Memory Cycle, whether the K.sdi/K.sti Control Bus Data Transceivers will be gated onto the
CDATA lines. In order to load the register, the BD field must equal two and the Upper Sequencer must
be active.

12-62

DATA CHANNEL MODULE

Table 12-23 shows what Control Memory cycles are generated from BR ADR < 10:07>.

Table 12-23 Control Memory Cycles Initiated from Decode the DA Field
10

Control Memory Cycle

Initiate Control Memory Read Cycle

Initiate Control Memory Write Cycle

Initiate Interrupt Cycle

Initiate Lock Cycle (Read and Force)

Initiate NMA Cycle

12.7.19.2
Write Data Bus Address Transceivers and Counter
When the microcode loads the Data Bus Address, part of the address is loaded from the BUS lines, and
branch address bits BR ADR < 10:09 > are logically ANDed, latched, and then used to drive DNMA
during the Data Bus Cycle (Figure 12 -19).
Table 12-24 shows the decoding of BR ADR < 10:09> to generate DNMA.

Table 12-24 Decoding DR ADR < 10:09 > To Generate DNMA
DR ADR 10

DR ADR 09

DNMA

12-63

POWER SYSTEM

CHAPTER 13
POWER SYSTEM

13.1 INTRODUCTION
The HSC power system consists of an ac power controller, an airflow sensor, dc power supplies, and
power switches and indicators.
The HSC50 has an ac power controller and one or two power supplies depending on the number of data
channels installed. The HSC70 has a different power controller and always has both power supplies
installed. The following sections describe the HSC power system.
13.2 AC POWER CONTROLLER
The HSC has four ac power controllers. The HSC50 uses the following two:
HSC50-AA-70-19122-01 for 120/208 Vac
HSC50-AB-70-20613-01 for 380-415 Vac
The HSC70 uses the following ac power controllers:
HSC70-AA-881A for 120/208 Vac
HSC70-AB-881B for 380-415 Vac
The ac power controller provides ac power to the power supplies and blower nlotor. Figures 13-1
and 13-2 show the location of the ac power controllers in the cabinets. Figures 13-3 to 13-8 show
various views of the power controllers. Each controller is described in the service nlanual.
Each power supply and the blower motor should be plugged into a different input phase. On the rear of
the HSC50 ac power controller, you will see the phase outlets marked by Ll, L2, and L3 (Figures 13-4
and 13-6). On the HSC70 ac power controller, you will see the phase outlets marked by 01, 02, and
03 (Figure 13-8).
13~3
AIRFLOW SENSOR
The airflow sensor is mounted in the exhaust duct of the cabinet and monitors the velocity of the
exhausted air through the exhaust duct (Figures 13-1 and 13-2).

The airflow sensor switch is self heating and requires moving air to keep the switch open. Power to
heat the sensor comes from the -5.2 volts on the backplane and + 12 volts on the main power supply
(Figure 13-9). If the blower fails, the sensor energizes the airflow sensor relay (Kl) through the same
source and interrupts the ac power through the total off circuit in the ac power controller.

13-1

POWER SYSTEM

Figure 13-1

HSCSO Inside Rear
. View
.

AC POWER
CONTROLLER

CX-l093A

13-2

POWER SYSTEM

Figure 13-2

HSC70 Inside Rear View

AC POWER
CONTROLLER
CX-1094r,\

13-3

POWER SYSTEM

Figure 13-3

HSCSO AC Power Controller (120/208 Vac)-Front View
DELAYED OUTPUT
CONNECTOR

LINE POWER
CI RCUIT BREAKERS

CB2-4 (SWITCHED)

CB5 (UNSWITCHED)

-'''- ........

.."

~"""""

(l,)'

CX-013B

13-4

POWER SYSTEM

Figure 13-4

HSC50 AC Power Controller (120/208 Vac)-Rear View

UNUSED

BLOWER OUTLET

MAIN POWER
SUPPLY OUTLET

AUXI LlARY POWER
SUPPLY OUTLET

UNSWITCHED

CX-411A

13-5

POWER SYSTEM

Figure 13-5

HSC50 AC Power Controller (380-415 Vac)-Front View
DELAYED OUTPUT
CONNECTOR

REMOTE/OFF
LOCAL ON SWITCH

A.C. Input

LINE PHASE
INDICATORS

LINE POWER
CIRCUIT
BREAKER

CB1

CX-013C

13-6

POWER SYSTEM

Figure 13-6 HSC50 AC Power Controller (380-415 Vac)-Rear View

J3
Total

Off

BLOWER OUTLET

MAIN POWER
SUPPLY OUTLET

AUXI L1ARY POWER
SUPPLY OUTLET

CX-411B

13-7

POWER SYSTEM

Figure 13-7 HSC70 AC Power Controller-Front View

GROMMETED
CORD
OPENING
POWER CONTROL
BUS CONNECTORS

f.\ SECONDARY
~ON

O•
I' I
,

SECONDARY
OFF

REMOTE BUS
CONTROL

INTERNATIONAL SYMBOLS

SERIAL LOGO
LABEL

CX-893A

13-8

POWER SYSTEM

Figure 13-8

HSC70 AC Power Contro 11er-Top View

MAIN

POWER
SUPPLY
OUTLET
AUXILIARY

POWER
SUPPLY
OUTLET
CX-l095A

13-9

POWER SYSTEM

Figure 13-9 Airflow Sensor Cabling
MAIN
PS

J/P35
+12V
AC POWER
CONTROLLER

SENSOR*

J/P70

BLOWER
AC

N.O.

-5.2V ........---'

BACKPLANE
TOTAL OFF

*NOTE: SCHEMATIC REPRESENTATION OF SOLID STATE COMPONENT
CX-1096A

The total off circuits are different in the HSC50 and HSC70. The total off circuit in the HSC50 trips the
main circuit breaker in the ac power controller to remove ac power. The total off circuit in the HSC70
deenergizes a relay in the ac power controller to remove ac power.
NOTE
The ac must be turned off and then back on to reset
this circuit.

When the total off circuit removes ac power, the power supplies sense the loss and assert the power
fail circuit to the P.ioc or P.ioj. Asserting power fail allows for an orderly shutdown of the HSC.

13-10

POWER SYSTEM

13.4 POWER SUPPLIES
The HSC has two power supplies: the main power supply and the auxiliary power supply. Figures 13-10
and 13-·11 show the location of the power supplies. These two power supplies are the switching regulator
type. The output voltage is maintained through sense line feedback from the backplane. Figures 13-12
and 13--13 show the connections between the power supplies and backplane.
The need for an auxiliary power supply in the HSC50 depends on the number of data channel modules
installed. If the HSC50 has more than three data channels, the auxiliary power supply is installed.
However, the HSC70 always contains both power supplies.
NOTE
These power supplies are not field adjustable.
The following sections describe the two power supplies.
13.4.1
Main Power Supply
The main power supply is rated at 750 watts and provides the following voltag£·s to the backplane:
+5.0 volts
-5.2 volts
+ 12 volts
The output current depends on how the power supplies are configured. If the auxiliary power supply is
not installed on an HSC50, the main power supply operates in mode 1. If the auxiliary power supply is
installed, the main power supply operates in mode 2.
13.4.1.1
Main Power Supply-Mode 1
Mode 1 is when the main power supply supplies all of the power for the HSC50 (no auxiliary power
supply). Table 13-1 shows the current outputs of the main power supply in mode 1.

Table 13-1 Main Power Supply Outputs-Mode 1
Voltage

Current

+5.0 volts

100 amperes

-5.2 volts

35 amperes

+ 12 volts

2 amperes (70-20033-01 and 70-20033-02)
4 amperes (70-20033-03 and 70-20033-04)
CAUTION
Never install a 70-20033-01 or 70-20033-02 main power
supply in an HSC70 because it does not supply
enough current. Use a 70-20033-03 or 70-20033-04
main power supply with a 4 ampere rating for the
+ 12 volts. However, any of the main power supplies may be used in an HSC50.

13-11

POWER SYSTEM

Figure 13-10 HSC50-Inside Front View

CX-l097A

13-12

POWER SYSTEM

Figure 13-11 HSC70-Inside Front View

HSC70
DC POWER SWITCH

AUXILIARY
POWER SUPPLY
CX-1098A

13-13

POWER SYSTEM

Figure 13-12 HSC50 Internal Cabling

7019686-01

o.q 02

7019679-01

~=-----"=7020206'OI OR -02
DELAYED
OUTPuT

CX-051A

13-14

POWER SYSTEM

Figure 13-13 HSC70 Internal Cabling
r.=====i[]

---------DRIVE 0

FLOPPY SIGNAL CABLE
11701167-011

DRIVE I

~~--.~

DC ON/OFF
SWITCH
DC ON/OFF CABLE
11701231-021

17020203-011
SECURE
ENABLE
SWITCH

OCP CABLE
11701203-(: 1

17019680-011

17020197-011
OCP/BACKPLANE CABLE
11701215-011
17019681-011

BACKPLANE IREAR VIEWI

1226092-01

A I R FLOW SENSOR 1PART
OF OUTLET DUCT ASSY
7020191-021

'-'l'I-_ _ _~.""5v'-- _ _ _ _

BLOWER
11218828-001

--]

--=:1

GNO

~~~~~~~~
~~~~~~~

17020198-011

FED

17019683-011

C B

-~il_

TA
RB

A
RA

CI CABLES
11700717-011
4X

_~7_1

51 CABLE 8X
11700958-011

POWER SUPPLY
AC LINE CORD
11701276-011

BLOWER AC LINE CORD
11701276-02 OR --031

',-

BP TO P5 1NTERCONNECT
11701266-011

REAR SH I ELO/C I CABLE
A5SY 17023140-011

NOT U5EO

POWER CONTROLLER
ASSEMBLY
13024374-01 DR -021

~~l

[

---TOP I/O BULKHEAD
ASSY 17023134-011

-----~
BOTTOM I /0 BULKHEAD
ASSY 17023135-011

--==-=-

3 PHASE/NEUTRAL/GNO
AC POWER CORD

--~~=PC A/; SEN ,0:'

" ' - - - RELA Y
11701231-01 J

13-15

CX-944A

POWER SYSTEM

13.4.1.2
Main Power Supply-Mode 2
The main power supply automatically operates in mode 2 when there is an auxiliary power supply
present in the HSC. In mode 2 the auxiliary power supply supplies up to 135 amperes for the + 5.0
voltage. After 135 amperes, the main power supply also starts supplying current for the + 5.0 volts.
Refer to Section 13.5 for the interaction between the two power supplies. Table 13-2 shows the current
outputs of the main power supply in mode 2.

Table 13-2

Main Power Supply Outputs-Mode 2

Voltage

Current

+ 5.0 volts

65 amperes

-5.2 volts

70 amperes

+ 12 volts

2 amperes (70-20033-01 and 70-20033-02)
4 amperes (70-20033-03 and 70-20033-04)

Notice that the current capacity in mode 2 is increased for the -5.2 volts and decreased for the + 5.0
volts. This is automatic. The power supply is still rated at 750 watts.
NOTE
The + 12 volt power supply is a slave of the -5.2
volt power supply. Therefore, the -5.2 volt power
supply must be gel}erating current for the + 12 volts
power supply to work. This means that you must
have at least one module installed with ECl logic
on it (LINK, K.sdi, or K.sti).
13.4.2
Auxiliary Power Supply
The auxiliary power supply has a single + 5.0 volt output. In the HSC50, the auxiliary power supply is
added if there are more than three data channels present. The HSC70 always has an auxiliary power
supply.
The auxiliary power supply is rated at + 5.0 volts and 135 amperes. Section 13.5 describes how the two
power supplies interact to supply the current for the HSC.
13.5 INTERACTION BETWEEN MAIN AND AUXILIARY POWER SUPPLIES
The main and auxiliary power supplies interact to supply the needed current for the HSC. The configuration of the power supplies make this interaction automatic. In brief, the outputs of the + 5.0 volts
are connected in parallel and the auxiliary power supply is adjusted to + 5.1 volts. The auxiliary power
supply supplies all of the needed current for the + 5.0 volts until the demand from the HSC exceeds
its rated output of 135 amperes. The main power supply is adjusted for' + 5.0 volts; therefore, it does
not supply any current when the output from the auxiliary power supply is above + 5.0 volts. When the
demand exceeds 135 amperes, the voltage output of the auxiliary power supply starts to drop. When the
output voltage drops to + 5.0 volts, the main power supply starts to supply current for the + 5.0 voltage.
If you measure + 5.1 volts at the backplane, the auxiliary power supply is supplying all of the + 5.0 volts.

13-16

POWER SYSTEM

13.6 PROTECTION CIRCUITS
Each HSC power supply has the following three protection circuits:
•

Over voltage protection

•

Over current protection

•

Over temperature protection

These three protection circuits are explained in the following sections.
13.6.1
Over Voltage Protection
The over voltage protection circuits in each power supply provide protection for the modules. When
the voltage rises above the values stated in Table 13-3, an SCR shorts the output to ground. You must
remove the ac power and restore it before the power supply will work again.

Table 13-3 Over Voltage Specifications
Voltage

Over Voltage Protection Limit

+5.0 volts

+ 6.50 volts

-5.2 volts

-6.76 volts

+ 12 volts

+ 15.0 volts
NOTE
If a remote sense wire becomes open-circuited, the

voltage increases and triggers the over voltage protection circuit.
13.6.2
Over Current Protection
The over current protection circuits keep the HSC power supplies from destroying themselves. When
the output current exceeds the rated output, the output voltage starts to drop (foldback). Table 13-4
shows what current the power supplies supply with a dead short.
WARNING
You should remove all rings and metal watches
when working around the the backplane or power
supplies in the HSC. The power supplies have a
high output current capacity. A metal object could
become red hot if shorted between ground and a
voltage.

13-17

POWER SYSTEM

Table 13-4

Dead Short Current of the Power Supplies

Voltage

Maximum Dead Short Current

+ 5.0 volts
Main
Auxiliary

50 amperes
65 amperes

-5.2 volts

35 amperes

+ 12 volts

2 amperes

13.6.3
Over Temperature Protection
Each power supply has an over temperature protection circuit. When the internal temperature is exceeded, the power supply disables the output and a power fail is detected by the P .ioc or P .ioj.
13.6.4
Ripple and Noise
Figure 13-14 shows the ripple and noise present on the dc outputs of the power supplies. Ripple is the
low frequency component in the waveform. The regulators switch at 100 KHz. Noise is the high frequency
component of the waveform. The transistors turning on and off at the minimum and maximum points
of the ripple cause noise. The maximum allowable ripple is 50 millivolts peak to peak. The maximum
allowable noise is 50 millivolts peak to peak.
Figure 13-14 Power Supply Ripple and Noise Specifications

RIPPLE
50 MI LLiVOLTS

NOISE
50 MI LLiVOLTS

5 MICROSEC

e_----I-..!

10 MICROSEC

CX-l099A

13-18

POWER SYSTEM

NOTE
You should not attempt to measure the ripple of
either power supply with an ordinary scope. You
need special equipment to measure ripple of these
power supplies accurately.
13.7 POWER FAIL
Each power supply (main or auxiliary) has a POWER FAIL signal output. This signal indicates the
imminent loss of dc voltage due to loss of ac input or internal thermal shutdown. The POWER FAIL
signal can be generated by either the main or auxiliary supply. This POWER FAIL signal from each
power supply is wire ORed together on the HSC backplane. Figure 13-15 shows where you can check
the POWER FAIL signal on the power supplies.
The Fll or Jll detects the POWER FAIL signal and executes a standard PDP-II Trap to 24 power fail
interrupt. You should note following POWER FAIL signal troubleshooting aids:
1.

The POWER FAIL signal output from one supply is not an input to the other supply. For
example, the main power supply does not know when the auxiliary supply is generating a
POWER FAIL. Therefore one supply can be generating a POWER FAIL while the other is
supplying voltages. If you suspect a problem with the power system, check the POWER FAIL
signal for a low (ground).

The POWER FAIL signal affects the HSC50 and HSC70 differently as described below:
•

On the HSC50, the POWER FAIL signal is not an input to the Voltage Monitor Circuit
on the P.ioc. Therefore, if the auxiliary power supply is generating POWER FAIL, it is
quite likely that the POWER indicator will still be on.

•

On the HSC70, the POWER FAIL signal is an input to the Voltage Monitor Circuit on
the P.ioj. Therefore, if a power supply asserts the POWER FAIL signal, the POWER
indicator on the OCP will be off.

13.8 DC POWER SWITCH
You can manually turn the power supplies off and on using dc power switch on the front bulkhead
(Figures 13-16 and 13-11). This switch disables the switching regulators in the power supplies. It also
allows you to turn dc off without turning off the blower.
NOTE
Turning off the dc power switch does not activate
the POWER FAIL to give any advanced warning that
dc is going away. The dc power switch is intended
for service purposes only, and you should only use
the switch if the HSC is offline to the host. Otherwise, you may lose data.

13-19

POWER SYSTEM

13.9 POWER INDICATOR
The POWER indicator on the Operator Control Panel is driven from a dc comparator circuit on the P.ioc
or pjoj. This circuit is different for the HSC50 and HSC70:
•

On the HSC50, the circuit only nlonitors the + 5.0, -5.2, and + 12.0 volts. If the circuit detects
that any of these voltages have dropped approximately one third, the indicator goes off.

•

On the HSC70, the circuit monitors the + 5.0 volts, -5.2 volts, + 12.0 volts, and the POWER
FAIL signal. If the circuit detects that any of the voltages have dropped approximately one
third, or if the power supplies assert POWER FAIL, the indicator goes off.

It is important to note that this indicator being on does not mean the voltages are within specifications.

13-20

POWER SYSTEM

Figure 13-15

Power Fail Test Points

STANDARD POWER
SUPPLY ASSEMBLY

POWER FAIL
TEST POINT

OPTIONAL POWER
SUPPLY ASSEMBLY

POWER FAIL
TEST POINT
TB1

CX-l100A

13-21

POWER SYSTEM

Figure 13-16 HSC50 DC Power Switch Location

o OFF POSITION

CX-014C

13-22

Index
----------.------------------~------------

Backplane
functional description, 2·25
BASIC SLOT signal, 5-30
BBS7 L signal, 3-7, 11-17
BBS7 signal, 3-6, 10-17
BDAL 00 L signal, 11-12, 11-18
BDAL 02:00 L signal, 11-26
BDAL 08:02 signal, 3-12
BDAL 15:00 L signal, 3-7, 11-26
BDAL 15:00 signal, 3-6, 3-7
BDAL 15:08 signal, 3-8
BDAL 16 L signal, 11-26
BDAL 17:00 L signal, 11-16
BDAL 17:00 signal, 3-7, 10-17
BDAL 17:16 signal, 3-6, 3-8
BDAL 17 L signal, 11-26
BDAL 17 signal, 3-8
BDAL 19 IN L signal, 11-12
BDAL20 L signal, 11-17
BDAL 21:18 signal, 3-6, 3-7, 10-17
BDAL21 L signal, 11-17
BDAL lines, 10-15, 11-18
BDCOK H.signal, 3-8
BDCOK signal, 3-6
BDIN L signal, 3-7, 11-18, 11-26, 11-27
BDIN signal, 3-6, 10-17, 11-16
BDMG I L signal, 11-35
BDMG L signal, 3-13
BDMGO L signal, 3-2, 3-8
BDMGO signal, 3-6
BDMR L signal, 3-2, 3-7, 3.. 13
BDMR signal, 3-6, 3-14
BDOUT L signal, 3-7, 3-21, Ll-18, 11-26, 11-27
BDOUT signal, 10-17, 11-16
B DRIVER ENABLE signal, 5..24
B DRIVER ENA signal, 5-41
BlACK L signal, 3-7
BIAKI L signal, 11-27
BIAK L signal, 3-2, 3-7
BIAK signal, 3-6
BINIT L signal, 3-7, 11-25, 11-33
BINIT signal, 3-6
BIRQ 4 L signal, 3-2, 3-7
BIRQ 4 signal, 3-6
Bit synchronization bytes, 518
Blower

ABORT + INIT FCN signal, 5··47
ABORT XMIT FCN command, 5-33
ABORT XMIT FCN signal, 5-39, 5-44
ACK/NACK Packet Reception, 5-5
ACK/NACK Packet Transmission, 5-3
ACK/NACK transmission, 5-21
ACK DONE signal, 5-49
ACK ENA signal, 5-47
ACK packet inserts, 5-21
ACK RCV]) signal, 5-39
ACK Receive PAL states, 5-44
ACK Receive State Logic, 5-44
ACK Source Compare Logic, 5-18
ACK Transmit State Logic, 5-49
A DRIVER ENABLE signal, 5-24
A DRIVER ENA signal, 5-41
Airflow Sensor
cabling, 13-2
functional description, 2-3, 13-1
ALT PATH BUSY signal, 5-30,5-32,5-33
ARBC = 0 signal, 5-32
ARB CMP ADD 3:0 signal, 5-32
ARB OK signal, 5-32, 5-35
ARB signal, 5-32
AR STATE D signal, 5-39
AR STATE M signal, 5-39
AUX1 PRESENT + signal, 3-3
AUX1 RCV + signal, 3-3
AUX1 RCV - signal, 3-3
AUX1 XMT + signal, 3-3
AUX1 XMT - signal, 3-3
AUX2 PRESENT + signal, 3-3
AUX2 RCV + signal, 3-3
AUX2 RCV - signal, 3-3
AUX2 XMT + signal, 3-3
AUX2 XMT - signal, 3-3
Auxiliary power supply
description, 13-16
AX STATE A signal, 5-49
AX STATE H signal, 5-49

B
Backplane buses
introduction, 3-1

Index-l

Blower (cont'd.)
functional description, 2-3
BPOK signal, 3-6
BRPlY l signal, 3-7, 3-21, 11-16, 11-18, 11-27
BRPlY signal, 3-6, 10-17
BSACK l signal, 3-2, 3-8, 11-27
BSACK signal, 3-6, 3-14
BSYNC l signal, 3-7, 3-8, 10-21, 11-18, 11-26
BSYNC signal, 3-6, 3-7
BSYSNC l signal, 11-27
Bus requestors
backplane slot number, 3-21
definition of, 3-21
BUSY Signal, 5-21
BWRTBT l signal, 11-26
BWTBT l signal, 3-7, 11-12, 11-18, 11-26
BWTBT signal, 3-6, 3-15
BYSNC l signal, 3-21
Byte Framer, 5-11

CI Bus arbitration inhibited, 5-33
CI Bus arbitration process, 5-28
CIB XMIT signal, 5-24
CLEAR RCVR signal, 5-49
CLEAR x H signal, 3-38
ClK A/B signal, 3-28
ClK ACK DST REG signal, 5-21
ClK A H signal, 3-38
ClK A signal, 10-11
ClK B H signal, 3-38, 11-8, 11-12
ClK B signal, 10-11
ClK CTl H signal, 3-38
ClK DST ADR REG signal, 5-21
Clocks
MDECODER, 5-10
CM 15:00,HP,lP IN H signal, 11-4
CM 15:00,HP,lP IN signal, 10-5
CM 15:00,HP,lP OUT H signal, 11-4
CM 15:00,HP,lP OUT Signal, 10-5
CM CAS l signal, 11-5
CM RAS 0 signal, 10-4
CM RAS 1 signal, 10-4
CM RAS l signal, 11-4, 11-5
CM RD CYC L Signal, 11-4
CM RD CYC signal, 10-5
CM REF CYC signal, 10-4, 10-7
CM SEl l signal, 11-5
CM SEl signal, 10-4, 10-5
CM WRT HB l signal, 11-4
CM WRT lB l signal, 11-4
CNODE ADDRESS signal, 5-21
Command
ABORT XMIT FCN, 5-33
RESET XMIT STATUS, 5-33
XMIT FCN, 5-33
Complement destination address checking, 5-44
Computer Interconnect Bus, 1-1
Console terminal
functional description, 2-3
Control Bus
cycle encoding, 3-25
cycles, 3-25
description, 3-23
differences between HSC50 and HSC70, 3-1
interrupt cycle, 3-29
interrupt cycle timing, 3-30
interrupt mask, 3-29
lock cycle, 3-31
lock cycle timing, 3-32
non-memory access cycle, 3-31
read cycle, 3-25
read cycle timing, 3-26
refresh cycle, 3-31
signals, 3-24
termination, 3-24
write cycle, 3-28
write cycle timing, 3-28

c
CACK l signal, 3-29, 3-30, 3-31, 11-4, 11-5, 11-8
CACK signal, 10-5, 10-7
CADR 15:00 signal, 10-4
CADR 16:00 l signal, 3-29, 11-4, 11-5
CADR 16 signal, 10-4
CAD R signal, 3-29
CARRIER DET A signal, 5-10, 5-32, 5-47
CARRIER DET B signal, 5-10, 5-32, 5-47
Carrier detection (CI), 5-8
Carrier Detection logic, 5-8
CBASE IN signal, 3-39
CBASE OUT Signal, 3-39
C CAS l Signal, 11-5
CCYClE 2:0 l Signal, 3-29
CCYClE lines, 11-5
CCYClE signal, 3-25
CDATA 03:00 signal, 3-30
CDATA 07:00 signal, 3-28
CDATA 15:00,HP,lP l signal, 3-29, 11-5
CDATA 15:00 Signal, 3-25, 3-30
CDATA 15:08 l signal, 3-28
CDATA lines, 10-5, 10-7, 11-4, 11-5, 11-8
CGRAN 0 l signal, 3-2
CGRAN l signal, 3-2
CGRANT 8 l signal, 3-2
CGRANT 9 l signal, 3-2
CGRANT l signal, 11-5
CGRANT n l signal, 3-31
CGRANT signal, 3-25, 10-5, 10-7
CGRANT x l Signal, 3-25, 3-29, 3-30
CHAR SYNC signal, 5-44, 5-47, 5-49
2797 Chip
See Floppy Disk Controller
CIA XMIT signal, 5-24
CI Bus arbitration, 5-28
CI Bus arbitration counters, 5-30

Index-2

Control Memory
Address Multiplexer, 11-4
8-Bit Refresh Address Counter, 10-4
block diagram, 10-2, 11-3
cycles, 10··5 to 10-7
Data Drivers, 10-5, 11-4
Data Receivers, 10-5, 11-4
Eight Bit Refresh Address Counter, 11-4
functional description, 10-2, 11-3
Idle Cycle, 10-5, 11-5
memory cycles, 11-5 to 11-8
RAS/CAS Multiplexor, 10-4
Read Cycle, 10-7, 11-5
Read Cycle timing diagram, 10-7, 11-5
Refresh Cycle, 10-7, 11-8
Refresh Cycle timing diagram, 10-7, 11-8
Select Logic, 10-4
Timing Logic and RAM Drivers, 10-4, 11-4
types of memory cycles, 10-5
Write Cycle, 10-5, 11-5
Write Cycle timing diagram, 10-5, 11-5
CRe checker, 5-24
CRC checker enabled, 5-47
CRC CLOCK as XMIT ClK, 5-28
CRC CLOCK signal, 5-26
CRC generation, 5-21
CRC generator, 5-26
CRC longword, 5-26
CRC lookup table functions, 5-26
CRC OK signal, 5-49
CRC STATUS signal, 5-16, 5-28
CREFR CLK L signal, 3-2, 3-31
CREFRESH CLK H signal, 3-31, 11-8
CREFRESH CLK signal, 10-7
CREFR GRANT L signal, 3-31, 11-4, 11-8
CREFR GRANT signal, 10-4, 10-7
CREFR REQ L signal, 3-2, 3-31
CREQ 0 l signal, 3-2
CREQ 8 l signal, 3-2
CREQ 9 l signal, 3-2
CREQ L signal, 3-25
CREQUEST L signal, 3-2
CREQ x L signal, 3-28
CRY signal, 5-32
CSR
See Floppy Disk Controller Command and
Status Register
CTIMING H signal, 3-29, 3-31, 11-4, 11-5, 11-8
CTIMING signal, 3-29, 10-4, 10-5
CWRTHL L signal, 11-5
CWRTH l signal, 3-25, 3-28, 3-29, 11-4, 11-5
CWRTH signal, 10-4
CWRTl L signal, 3-25, 3-28, 3-29, 11-4, 11-5
CWRTL signal, 10-4
CYCLE 2:0 L signal, 3-30
Cyclic Redundancy Check, 5-3
Cyclic Redundancy Check (CRC)' 5-16

D 7:0 H signal, 11-30
DACK L signal, 3-34, 3-36
DACK signal, 10-11, 11-8
DADR 13:00 signal, 10-11
DADR 15:00 L signal, 11-8
DADR 15:14 signal, 10-11
DADR 16 L signal, 11-11
DADR 17:00 L signal, 11-12
DADR 17:00 signal, 3-34, 3-36
DADR 17 L signal, 11-11
DADR lines, 10-11, 11-8
Data Bus
cycles, 3-34
description of, 3-32
differences between HSC50 ,md HSC70, 3-1
NMA cycle, 3-37
read cycle, 3-34
read timing, 3-35
signals, 3-33
termination, 3-33
write cycle, 3-36
write timing, 3-36
Data Channel Module
ALU Control, 12-12
Arithmetic and logic Unit, 12-18
block diagram description, 12.4
board deSignation, 12-1
Bus Destination Control, 12-13
Bus Source Control, 12-12
control and interface, 12-5
Control Bus Interface, 12-33
Control Error Register, 12-29
Control Store, 12-10
Control Store and Instruction Register, 12-12
Data Bus Address, 12-35
Data Bus Data Transceivers, 12-35
Data Bus Interface, 12-33
Data Error Register, 12-30
destination and branch field combination, 12-62
Diagnostic Register, 12-27
functional description, 2-17, 12-1
input and output to SDI/STL 12-41
Instruction Parity Checker, 12-12
lac Control, 12-15
K.sdi/K.sti pipeline, 12-20
Lower Control Register, 12··25
microinstruction word, 12-2, 12-52
AB field, 12-55
AD field, 12-53
AF field, 12-54
AS field, 12-54
BA field, 12-62
BD field, 12-59
BS field, 12-60
C field, 12-52
$ field, 12-61

Index-3

Data Channel Module
microinstruction word (cont'd.)
@ field, 12-59
IOC field, 12-59
K field, 12-61
P field, 12-62
+ field, 12-55
RA field, 12-60
RB field, 12-55
S field, 12-61
TEST field, 12-56
pipeline timing, 12-22
pipelining concepts, 12-20
Program Address Register, 12-10
receive data from a drive, 12-46
receive level responses from a drive, 12-43
receiving Real-Time Drive State from a drive,
12-51
Scratchpad RAM, 12-23
SectorlIndex PALs, 12-40
send data to a drive, 12-45
send level 1 commands to a drive, 12-43
send level 2 commands to a drive, 12-42
send Real-Time Controller State to a drive,
12-47
sequencers, 12-8
status LEDs, 12-2
Status Register, 12-32
test multiplexer, 12-10
Upper Control Register, 12-23
write Control Bus Address Transceivers, 12-62
write Data Bus Address Transceivers and
Counter, 12-63
Data Memory
Address Receiver/Driver, 10-11, 11-8
Bank Select, 10-11
Bank Select logic, 11-11
block diagram, 10-8, 11-8
Data Drivers, 10-12, 11-11
Data Receivers, 10-11, 11-11
functional description, 10-7, 11-8
Idle Cycle, 10-12, 11-11
memory bank selection, 11-11
memory cycles, 10-12 to 10-15, 11-11 to 11-12
Read Cycle, 10-14, 11-12
Read Cycle timing diagram, 10-14, 11-12
Select Logic, 10-11, 11-8
Timing Logic and RAM Drivers, 10-11, 11-8
Write Cycle, 10-12, 11-12
Write Cycle timing diagram, 11-12
Write cycle timing diagram, 10-12
Data packets
definition, 5-1
DBASE IN signal, 3-39
DBASE OUT signal, 3-39
DC power switch purpose, 13-19
DDATA 07:00,LP Signal, 3-36
DDATA 15:00,HP,LP lines, 10-11

DDATA 15:00,HP,LP L signal, 11-11, 11-12
DDATA 15:00,HP,LP signal, 3-34, 3-36, 10-12
DDATA 15:00 Signal, 3-36
DDATA lines, 10-11
DDATA lines signat 11-8
Destination address register, 5-21
Destination bytes, 5-21
Destination compare (ACKL 5-16
DGRANT 0 L signat 3-2
DC RANT 8 L signat 3-2
DCRANT 9 L signal, 3-2
DGRANT L signal, 3-2, 11-12
DGRANT Signal, 10-12, 10-14
DC RANT x L signal, 3-34, 3-36
D IN lines, 11-5
D IN sign at 11-4
DIN signat 10-5, 10-15
DIR SEL L signat 3-3, 11-31
D LYD HD R TO signal, 5-33
DM 15:00,HP,LP IN H signat 11-11
DM 15:00,HP,LP IN signal, 10-11
DM A13:00 A signat 10-11
DM A13:00 B signat 10-11
DM A 15:00 H signat 11-12
DMA REQ H signat 11-27
DM NMA signat 10-11
DM OE L signat 11-11
DM OE signal, 10-11
DM RD CYC L signat 11-11
DM RD CYC signat 10-12
DM SEL signat 10-lL 11-8
DM WRT PULSE H signat 11-12
DNMA H signat 3-34, 10-12, 11-8, 11-11
DNMA signat 11-12
DREQ 0 L signat 3-2
DREQ 8 L signat 3-2
DREQ 9 L signal, 3-2
DREQUEST L sign at 3-2
DREQ x L signal, 3-34
DRV SEL 0 L signal, 3-3, 11-31
DRV SEL 1 L signal, 3-3, 11-31
DRV SEL 2 L signat 3-3
DRV SEL 3 L signat 3-3
DST CMP Signal, 5-16, 5-44, 5-47
DTIMING L signat 3-36
Dual count round robin arbitration algorithm, 5-28
DWRTH L signat 3-34, 3-36, 11-8, 11-12
DWRTH signal, 10-7, 10-11
DWRTL L signal, 3-34, 3-36, 11-8, 11-12
DWRTL signat 10-7, 10-11

E
E151-1 signat 5-24
E151-2 signat 5-24
E183-11 signat 5-24
E197-R2 signat 5-11
E198-3 signat 5-11

Index-4

Floppy Disk Con troller (can t' d .)

ECL
emitter-coupled logic, 5-8
ECL logic.. 5-8
ENA ACK CDST signal, 5-21
ENA ACK SRC signal, 5-21
ENA ACK TDST signal, 5-21
ENA IN signal, 3-39
ENA OUT signal, 3-39
ENA SYNClTR CNT signal, 5-18, 5-41
ENA SYNC/TR signal, 5-18, 5-41
ENA SYNC DET signal, 5-10, 5-46, 5-47
ENA XMIT DATA PARITY signal, 5-21, 5-41
ENA XMIT DATA REG signal, 5-41
ENA XMIT LATCH signal, 5-18
ENB DMA TEST H signal, 11-31
EXT MLOOP defined, 5-33

Disk Write PAL, 11-27
DMA Control, 11-27
Error Register Buffer, 11-30
2797 Floppy Disk Controller Chip, 11-27
functional description, 11 .. 18
Interrupt Control and V,dor Timing, 11-27
Memory Address Register, l1-22, 11-27
Memory Address Register, High Byte (MAR 2),
11-22
Memory Address Registe!, Low Byte (MAR 0),
11-22
Memory Address Register, Middle Byte (MAR 1),
11-22
Memory Address Register O/Track Register, 11-24
Memory Address Registel lISector Register,
11-25
Memory Address RegisteJ 2/Data Register, 11-25
Non-existent Memory Df.'tection, 11-27
Parity Generator/Checker, l1-26
Program Bus Register Control PAL, 11-26
Program Bus Register Selection, 11-26
Program Bus Synchronizer, 11-26
Program Bus TransceivelSand Vector Control,
High Address Driver, 11-26
RBUF/XBUF Register, 11-30
register bit assignments, 11-22
registers, 11-22 to 11-26
Sector Register, 11-22
Status Register summary 11-37
FORCE ARB defined, 5-33
FORCE CARRIER defined, .:-1-33
FORCE PATH A signal, 5-10
FORCE PATH B signal, 5-10
FORCE PATH signals, 5-41

F
FDC Chip

See Floppy Disk Controller
Floppy Disk Controller
block diagram, 11-28
Cable Driver and Cable Receiver, 11-31
Command and Status Register, 11-22, 11-30
Command and Status Register, High Byte, 11-22
Command and Status Register, Low Byte, 11-22
Command and Status Register bit assignment
(high byte), 11-22
commands, 11-31 to 11-38
disk reads, 11-34
disk writes, 11-34
head positioning, 11-32
head positioning command arguments,
11-32
Read Address, 11-37
Read Sector, 11-34
Read Sector command arguments, 11-34
Read Track, 11-37
Restore, 11-33
Seek, 11-31, 11-33
status for Type II and Type II, 11-35
Step, 11-33
Step In, 11-33
Step Out, 11-34
Type I, 11-31
Type II, 11-34
Type III, 11-37
Type IV, 11-38
Write Sector, 11-35
Write Sector command arguments, 11-35
Write Track (Formatting), 11-37
command summary, 11-31
Current Track Register, 11-22
Data Register, 11-22, 11-26
Disk Command Register, 11-30
Disk Re'ad PAL, 11-27

H
HEADER ABORT RCVR signal, 5-39
HEADER TIME OUT signal. 5-39, 5-49
HOST CLR H signal, 3-39
Host Interface
functional description, 2 ·22, 4-4
HSC50
as a node on a cluster, 1-5
backplane
functional description, 2-25
block diagram, 2-5
Data Channel Module
functional description, 2-17
features, 1-1
Input/Output Control Processor
functional descriptinn, 2-10
load device, 2-3
Memory Module
functional descripti'on, 2-15
physical characteristics, 2-1
HSC70

Index-5

HSC70 (cont'd.)
as a node on a cluster, 1-5
backplane
functional description, 2-25
block diagram, 2-5
Data Channel Module
functional description, 2-17
features, 1-1
Input/Output Control Processor
functional description, 2-12
load device, 2-3
Memory Module
functional deSCription, 2-17
physical characteristics, 2-1

Input/Output Control Processor
HSC50 (cont'd.)
diagnostic OK LEDs, 8-3
Error Address Registers, 8-15
F-11 block diagram, 8-6
functional description, 2-10, 8-1
High Error Address Register, 8-15
II 0 page address of Window Address
Registers, 8-22
110 page address utilization, 8-30
interface to Control Memory, 8-20
interrupt and trap vectors, 8-10
interrupt cycle, 8-28
Interrupt Logic, 8-10
K INIT and Status Register, 8-19
K INIT Register bit deSCription, 8-19
lock cycle, 8-28
Low Control Memory Address Register,
8-27
Low Error Address Register, 8-15
Memory Management Register 0, 8-7
Memory Management Register 0 bit
description, 8-7
Memory Management Register 1, 8-8
Memory Management Register 2, 8-8
Memory Management Register 3, 8-8
Memory Management Register 3 bit
description, 8-8
Memory Management Unit Chip, 8-6
MIB, 8-9
Microinstruction Bus, 8-9
Micro-ODT, 8-9
Operator Control Panel, 8-16
parallel P.ioc interface, 8-11
Pio Control and Status Register, 8-17
Pio Control and Status Register bit
description, 8-17
Receiver Data Buffer Register, 8-12
Receiver Data Buffer Register bit
description, 8-12
Receiver Status Register, 8-11
Receiver Status Register bit description,
8-11
RUN LED, 8-3
serial interface, 8-14
Serial Number Register, 8-15
State LED, 8-3
Status LEOs, 8-1
Status Register bit deSCription, 8-20
Switch/Display Register, 8-15
Switch/Display Register bit description,
8-16
Transmitter Data Buffer Register, 8-13
Transmitter Data Buffer Register bit
deSCription, 8-13
Transmitter Status Register, 8-13
Transmitter Status Register bit description,
8-13

ICCS PATH SELECTED signal, 5-49
ILl
See Interprocessor Link Interface
INDEX L signal, 3-3, 11-31
Information packet
bit synchronization, 4-1
body, 4-3
character synchronization, 4-3
cyclic redundancy check, 4-4
destination, 4-3
packet length, 4-3
packet type/length, 4-3
source, 4-3
trailer, 4-4
Information Packet Reception (LINK), 5-3
INITIALIZE signal, 5-39, 5-44, 5-47
Input/Output Control Processor
HSC50
Address Decode, 8-11
block diagram, 8-4
block diagram description, 8-3
Bootstrap PROM, 8-11
Bus Control Logic, 8-9
console terminal interface, 8-14
Control Bus Arbitrator and timing, 8-28
Control Bus Data Transceivers, 8-27
Control Bus Interface, 8-26
Control Memory Address Transceivers,
8-27
Control Memory windows, 8-21
Control Window address selection, 8-21
Control Window limitation, 8-26
Data-Address Lines, 8-9
Data Bus Address Receivers, 8-29
Data Bus Address Transceivers, 8-29
Data Bus Address Transmitters, 8-29
Data Bus Arbitrator and timing, 8-30
Data Bus interface, 8-29
Data Bus Transceivers, 8-29
Data Memory Interface, 8-28
description of F-11 block diagram, 8-3

Index-6

Input/Output Control Processor
HSC50 (cont'd.)
TU58 Interface, 8-11
TU58 serial interface baud rate selection,
8-14
HSC70
Auxiliary Serial Interfaces, 9-26
block diagrann, 9-4
block diagrann description, 9-3
Bootstrap PROM, 9-22
Cache Control Register, 9-6
Cache Control Register bit description, 9-9
Cache Data Path, 9-15
Cache Hit/ Miss Register, 9-10
Cache Mennory, 9-16
Clock Register, 9-15
Console Ternninal Interface, 9-22
Control Bus Arbitrator and Tinning, 9-40
Control Bus Data Transceivers, 9-39
Control Bus Interface, 9-39
Control Logic, 9-6
Control Mennory Address Transceivers,
9-39
Control Mennory Interface, 9-32
Control Mennory windows, 9-32
Control Window address selection, 9-33
Control Window Exannple, 9-36
Control Window linnitation, 9-38
CPU Error Register, 9-10
CPU Error Register bit description, 9-10
Data Bus Address Receivers, 9-42
Data Bus Address Transceivers, 9-41
Data Bus Address Transnnitters, 9-41
Data Bus Arbitrator and tinning, 9-42
Data Bus interface, 9-41
Data Bus Transceivers, 9-41
Data Mennory interface, 9-41
DC]ll nnicroprocessor functional
description, 9-6
diagnostic OK LEDs, 9-1
Direct Mennory Access Register, 9-18
Error Address Register, 9-31
functional description, 2-12
110 Page Address Decodes, 9-26
110 page address of Window Address
Registers, 9-34
110 Page address utilization table, 9-43
Input Register and Output Register, 9-14
Interrupt and Trap Vectors, 9-21
Interrupt Cycle, 9-40
Interrupt Logic, 9-21
introduction, 9-1
K INIT and Status Registers, 9-30
K INIT Register bit description, 9-30
lock cycle, 9-41
Low Control Mennory Address Register bit
deSCription, 9-39

Input! Output Control Processor
HSC70 (cont'd.)
Maintenance Register. 9-19
Maintenance Register bit description, 9-20
Mennory Managennent Register 0, 9-12
Mennory Managennent Register 0 bit
description, 9-12
Mennory Managennent Register 1, 9-13
Mennory Managennent Register 2, 9-13
Mennory Managennent Register 3, 9-14
Mennory Managennent Register 3 bit
description, 9-14
Mennory Systenn Error Register, 9-15
Mennory Systenn Error Register bit
description, 9-16
nnicro-ODT, 9-14
Pio Control and Status Register bit
description, 9-21
Pio Control and Statu:-, Registers, 9-26
Progrann Interrupt Request Register bit
description, 9-1 r
Progrannnnable Interrupt Request Register,
9-11
Progrann Mennory Bus Receivers, 9-18
Progrann Mennory Bus Transnnitters, 9-18
Receiver Data Buffer Register, 9-23
Receiver Data Buffer Register bit
description, 9-23
Receiver Status Registpr, 9-23
Receiver Status Register bit description,
9-23
RUN LED, 9-3
Serial Nunnber Register, 9-31
State LED, 9-3
State Sequencer, 9-15
Status LEOs, 9-1, 9-3
Status Register bit desniption, 9-31
Switch/Display Register, 9-28
Switch/Display Register bit deSCription,
9-29
Transnnitter Buffer Data Register, 9-25
Transnnitter Buffer Data Register bit
description, 9-25
Transnnitter Status Register, 9-24
Interprocessor Link Interface
function, 4-4
INT MLOOP defined, 5-33
INT MLOOP signal, 5-8, 5-24, 5-44, 5-47
INTR ENB H signal, 11-27
INTR REQ H signal, 11-38
IN USE L signal, 3-3, 11-31

K
K.ci

See Host Interface
K.pli

See Port Processor Module

Index-7

MAR

Krx

See Floppy Disk Controller Memory Address

See Floppy Disk Controller

Ksdi

See Data Channel Module

See Memory Address Register

Ksti

MARO/TREG
See Floppy Disk Controller Memory Address
Register O/Track Register
MAR1ISREG
See Floppy Disk Controller Memory Address
Register 1ISector Register
MAR2/DREG
See Floppy Disk Controller Memory Address
Register 2/Data Register
Mass Storage Control Protocol, 1-1
MASTER signal, 11-27
MAX CRC 3 signal, 5-39, 5-50
MDECODER CLOCK, 5-10
MDECODER Clock, 5-10
MDECODER signal, 5-11, 5-16
MDR
See Floppy Disk Controller Data Register

See Data Channel Module

L
L0100

See Port Link Module
L0105

See Input/Output Control Processor (HSC50)
L0106

See Memory Module
L0107

See Port Processor Module
L0108-YA
See Data Channel Module
L0108-YB
See Data Channel Module
L0109
See Port Buffer Module
L0111
See Input/Output Control Processor (HSC70)
L0117
See Memory Module
LAST SYNC signal, 5-18
LD CSR L signal, 11-30
LD MAR x L Signal, 11-27
LINK
See Port Link Module
LINK interface signals, 5-35
LOAD ARB COUNT, 5-30
LOAD ARB COUNT signal, 5-32
Load device, 2-3
LOAD signal, 5-49
Longword (CRC), 5-21
Loopback path functions, 5-35
LOOP Signal, ·5-39
LT (I PLUS 1) signal, 5-32

See Floppy Disk Controller RBUF/XBUF Register
ME DATA signal, 5-24
Memory Module
HSC50
block diagram, 10-1
functional description, 2-15, 10-1
jumper and dipshunt configuration, 10-23
size and type, 10-1
status LED, 10-2
HSC70
block diagram, 11-1
functional description, 2-17, 11-1
jumper configuration, 11-38
size and type, 11-1
status LED, 11-1
Message Receive State Logic (LINK), 5-47
Message Transmit State Logic (LINK), 5-39
Module
Kpli
See Port Processor Module
Ksdi
See Data Channel Module
Ksti
See Data Channel Module
LINK
See Port Link Module
M.std
See Memory Module
M.std2
See Memory Module
P.ioc
See Input/Output Control Processor
(HSC50)
P.ioj

M
M.std

See Memory Module
M.std2

See Memory Module
Main power supply
description, 13-11
Maintenance testing
compare logic polarity reversal, 5-16
Manchester
decoder, 5-8
decoder timing, 5-10
Manchester Decoder, 5-3
Manchester Decoder Logic, 5-9
Manchester Encoder, 5-3, 5-24

See Input/Output Control Processor
(HSC70)

Index-8

Module (cont'd.)
PILA
See Port Buffer Module
MOTOR ENB L signal, 3-3, 11-31
MR CRC 3 signal, 5-49
MR STATE E signal, 5-49
MR STATE G signal, 5-47
MR STATE I signal, 5-33, 5-49
MSCP
See Mass Storage Control Protocol
MSG END + HTO signal, 5-49
MSG XMIT State PALs (LINK) 1 and 2, 5-39
MX STATE A, 5-30,5-39
MX STATE B, 5-30
MX STATE C, 5-32
MX STATE L Signal, 5-41

Parity
channel output, 5-18
receive data, 5-18
Parity error checker functions, 5-21
Path selection (CI), 5-8
PBASE IN 0 L signal, 3-2
PBASE IN 1 L signal, 3-2
PBASE IN 2 L signal, 3-2
PBASE IN 3 L signal, 3-2
PBASE IN 4 L signal, 3-2
PBASE IN 5:0 signal, 3-6, 3-9
PBASE IN 5 L signal, 3-2
PBASE IN signal, 3-5
PBASE OUT 0 L signal, 3.,2
PBASE OUT 1 L signal, 3-2
PBASE OUT 2 L signal, 3·2
PBASE OUT 3 L signal, 3.. 2
PBASE OUT 4 L signal, 3':'2
PBASE OUT 5:0 signal, 3",3-9
PBASE OUT 5 L signal, 3·2
PBASE OUT signal, 3-5
PENA OUT signal, 3-6
PENA L signal, 3-2
PENA OUT signal, 3-9
PE Signal, 5-39
Phase encoding
definition, 5-9
PILA
See Port Buffer Module
PLI
See PORT LINK Interface
See Port Link Interface
PLI link control
abort transmission, 6-12
disable link control, 6-14
enable link control, 6-13
read buffer, 6-18
read node address, 6-19
read receiver status, 6-14
read switches, 6-19
read transmitter status, 6-16
select buffer, 6-22
set mode, 6-20
sync, 6-22
PM 00 IN signal, 10-17
PM 15:00,HP,LP OUT L signal, 11-16
PM 15:00,HP,LP OUT signal, 10-17
PM 15:00 IN L signal, 11-16
PM 15:00 IN signal, 10-15
PM 19 IN L signal, 11-17
PM AMUX 8:0 H signal, 11-16
PM COL ADR EN L signal, 11-16
PM COL ADR EN signal, to-IS
PM ENB D DRVRS L signal, 11-16
PM ENB D DRVRS signal, 10-17
PM LATCH DATA L signal, 11-16
PM LATCH DATA signal, 10-17

N
NEW DATA 7:0 signal, 5-26, 5-28
N load multiplexor selection, 5-30
NODE ADDRESS < 3:0
signal, 5-30
Node address complement, 5-16
Node address true, 5-16
NXM ERR L signal, 11-27, 11-30

o
OCP

See Operator Control Panel
Operating states (LINK), 5-35
Operator Control Panel
functional description, 2-3, 2-30
indicators and switch (HSC50), 8-16
indictors and switches (HSC70), 9-28

p
P.ioc

See Input/Output Control Processor (HSC50)
P.ioj

See Input/Q.,utput Control Processor (HSC70)
POI CM REF CYC L signal, 11-4
Packet Formats
acknowledge/negative acknowledge packet, 4-4
information packet, 4-1
PACKET LENGTH signal, 5-47
Packet type byte, 5-21
PAL, 5-8, 5-11
sync character detect enable, 5-10
PAL (LINK mode control), 5-33
PAL, Programmable Array Logic, 5-5
PAL CLK H signal, 11-27, 11-30
PAL CLK signal, 11-30
PAls (MSC RCVR state) function, 5-47
PAL state logic, 5-21
Parallel to serial data conversion, 5-24
PAR ERR L signal, 11-30

Index-9

Port Link Module (cont'd.)
functional overview, 5-1
functions, 5-1, 5-33
MX STATE A (idle), 5-30
overview, 4-7
states, 5-5, 5-32, 5-39
transmit/receive functions, 5-3
Port Processor Module
arithmetic and logic unit, 7-9
block diagram, 7-4
Control Bus Interface, 7-19
Control Register, 7-35
Control Register bit definition, 7-35
Control Store, 7-9
Data Bus Address, 7-21
Data Bus Data Transceivers, 7-21
Data Bus Interface, 7-21
Data Parity Generation and Check Logic, 7-36
Destination Decoder, 7-36
functional description, 2-23, 7-1
hardware detect errors, 7-48
Instruction Parity Checker, 7-36
IOC Latch bit description, 7-36
IOC Latches, 7-36
K.pli Pipeline, 7-13
microinstruction word
AB field, 7-41
AD field, 7-39
AF field, 7-40
AS field, 7-40
BA field, 7-47
BD field, 7-43
BS field, 7-45
C field, 7-39
destination and branch field combinations,
7-47
$ field, 7-46
@ field, 7-44
IOC field, 7-44
K field, 7-46
P field, 7-47
+ field, 7-41
RA field, 7-45
RB field, 7-42
S field, 7-45
TEST field, 7-42
microinstruction word description, 7-1, 7-37
overview, 4-10
pipeline timing, 7-13
pipelining concepts, 7-11
PLI Data Bus And PLI Control, 7-24
PLI interface, 7-24
PLI Interface control, 7-34
PLI Interface control signals, 7-34
PLI Status, 7-27
program address register, 7-9
revision level switches, 7-17

PM LCAS L signal, 11-17
PM LCAS signal, 10-17
PM OE L signal, 11-16
PM RAS 0 L signal, 11-17
PM RAS 0 signal, 10-17
PM RAS 1 L signal, 11-17
PM RAS 1 signal, 10-17
PM RD REQ signal, 10-17
PM REF IN PROG L signal, 11-17
PM REF IN PROG signal, 10-15
PM REF INPROG signal, 10-17
PM ROW ADR EN L signal, 11-16
PM ROW ADR signal, 10-15
PM SEL signal, 10-17
PM SYNC L signal, 11-16
PM SYNC signal, 10-15
PM U CAS L signal, 11-17
PM UCAS signal, 10-17
PM WR REQ signal, 10-17
PM WRT ENB H signal, 11-17
PM WRT REQ signal, 10-17
PM WTBT signal, 10-17
Port Buffer Module
block diagram, 6-2
description, 6-1
functional description, 2-23
operation, 6-6
PLI link control, 6-10
load transmit buffer, 6-10
reset transmit status, 6-12
transmit, 6-10
receive, 6-6
transmit, 6-8
overview, 4-10
status LEOs, 6-23
PORT DATA 7:0, 5-33
PORT LINK Interface
function, 4-4
Port Link Interface, 6-1
description of signals, 6-4
PLI CLOCK, 6-6
PLI DATA 7:0, 6-5
PLI INITIALIZE, 6-6
PLI LINK CONTROL 3:0, 6-5
PLI RCVR BUFFER A FULL, 6-5
PLI RCVR BUFFER B FULL, 6-5
PLI RECEIVE DATA PAR, 6-5
PLI SELECT, 6-5
PLI TRANSMIT DATA PAR, 6-5
PLI XMTR ATTENTION, 6-5
Port Link Module
arbitration comparator functions, 5-32
arbitration countdown, 5-32
block diagram, 5-1
CONTROL 3:0 signal, 5-33
definition, 5-1
functional description, 2-24

Index-lO

Program Bus (cont'd.)

Port Processor Module (cont'd.)
Scratchpad Memory, 7-13
sequencers, 7-4
Source Decoder, 7-37
Status Bus Register, 7-18
Status lEDs, 7-1
Status Registers, 7-14
Status Registers bit assignment, 7-15
test multiplexer, 7-9
Power Controller
functional description, 2-1
Power controller
designations, 13-1
purpose, 13-1
views of. 13-1
Power indicator
description, 13-20
Power Supply
auxiliary power supply
description, 13-16
cabling (HSC50), 13-11
cabling (HSC70), 13-11
dc power switch purpose, 13··19
description, 13-11
functional description,' 2-2
interaction, 13-16
main power supply
description, 13-11
power fail, 13-19
power fail test points, 13-20
protection circuits, 13-17
over current, 13-17
over current specifications, 13-17
over temperature, 13-18
over voltage, 13-17
over voltage specifications, 13-17
ripple and noise, 13-18
ripple and noise specifications, 13-18
voltages, 2-2
voltages a.nd currents, 13-11, 11-16
Power system
introduction, 13-1
PREFR ClK H signal, 11-12
PREFR ClK l signal, 3-8
PREFR ClK signal, 3-6, 10-21
Program Bus
addressing, how accomplished, 3-15
data transfers, 3-15
data transfer types, 3-15
data word length, 3-15
DATI Cycle, 3-16
DATI cycle timing, 3-17
DATIO and DATIOB cycles, 3-21
DATO and DATOB cycle, 3-18
DATO or DATOB cycle timing, 3-20
description of, 3-4
differences between HSC50 and HSC70, 3-1

DMA request/grant sequelcing, 3-13
DMA transaction phases, 3.,.13
HSC50/70 differences, 3":
identical to Q-Bus signals, 3-6
interrupt proctocal timing, 3-12
interrupt protocol (HSC7('), 3-10
interrupt request/acknowUege sequence, 3-10
mastership protocol, 3-13
master-slave relationship, 3-5
purpose, 3-4
request/grant bus cycle tiDiing, 3-14
signals, 3-6
signal which differ from the Q-Bus signals, 3-8
transactions, 3-9
Program Memory
Address Decode logic, 10·17, 11-17
bank selection, 11-12
Bank Select logic and Pro:;ram Memory RAM
Driver, 10-17
Bank Select logic and RAM Driver, 11-17
BDAl Buffer, 10-15, 11-16
8-Bit Refresh Address Cou:lter, 10-15
block diagram, 10-15, 11-12
CAS and RAS Address Drivers, 10-15
Data Driver Control and BRPlY logic, 10-17
Data Driver Control and Reply logic, 11-16
Data Drivers, 10-17, 11-16
Eight Bit Refresh Address Counter, 11-17
functional description, lo. 15, 11-12
memory cycles, 10-18 to W-21, 11-17 to 11-18
Memory Request logic, 10 -17
RAM Address Driver, 10-1'>, 11-16
RAM Timing Logic, 10-17, 11-17
Read Cycle, 10-18, 11-18
Read Cycle timing diagram, 10-18, 11-18
Read-Modify-Write Cycle, 10-21
Refresh Cycle, 10-21, 11-U:
Refresh Cycle timing diagrlm, 10-21, 11-18
Request Logic, 11-17
Rowand Column Address Latches, 11-16
Write Byte Decode and RAvl Driver logic, 11-17
Write Byte Decode and RAM Drivers, 10-17
Write Cycle, 10-18, 11-18
Write Cycle timing diagram, 10-18, 11-18
PROM
LINK Sync/Trailer, 5-18
PROM addressing, 5-18

R
RO signal, 5-24
RO through R3 signals, 5-26
RBS7 signal, 3-15
RCAR DROP signal, 5-49
RCVR ACTIVE Signal, 5-33
RCVR A ENABLE defined, 5-;\3
RCVR B ENABLE defined, 5-;,3

Index-11

RCVR BUFFERS FULL signal, 5-21
RCVR CLK generator, 5-11, 5-22
RCVR CLK signal, 5-11, 5-16
RCVR PACKET END signal, 5-47
RCVR PATH SEL A signal, 5-8
RCVR PATH SEL B signal, 5-8
RCVR SERIAL DATA signal, 5-11
RDAL 17:16 signal, 11-26
RDAL 21:13 signal, 3-15
RDAT 7:00 signal, 5-3
RDATA signal, 3-18
RDAT REG 7:0 signal, 5-21, 5-28
RDAT REG 7 = 1, 5-44
RD CSR L signal, 11-30
RD DATA L signal, 3-4, 11-31
RDIN signal, 3-12
RDOUT signal, 3-21
READY L signal, 3-4, 11-31
Receive channel busy (arbitration condition), 5-33
REG SEL x L signal, 11-26
Related Documentation, table, 1-5
Requestor number backplane slots, 3-21
RESET XMIT STATUS command, 5-33
RIAKO signal, 3-12
RINIT signal, 5-47
RRPLY signal, 3-12, 3-21
RX D 13:8 H signal, 11-30
RX D 15:00 H signal, 11-26, 11-30
RX D 15:8 H signal, 11-27
RX D 21:16 H signal, 11-26
RX D 7:0 H signal, 11-27
RX MATCH H signal, 11-26
RXMIT signal, 5-47

STATUS 7: 00 signal, 3-38
Status LED
Data Channel Module, 12-2
HSC50 Input/Output Control Processor, 8-1
HSC50 Memory Module, 10-2
HSC70 Input/Output Control Processor, 9-1
HSC70 Memory Module, 11-1
Port Buffer Module, 6-23
Port Processor Module, 7-1
STEP L signal, 3-3, 11-31
SWAP CM BANK H signal, 11-4
SWAP CMEM BANK H signal, 3-3,3-8
SWAP CMEM BANK signal, 3-6
SWAP MEM BANK H signal, 3-3, 3-9
SWAP MEM BANK signal, 3-6
SWAP MEM BOARD H signal, 3-3, 3-9
SWAP MEM BOARD signal, 3-6
SWAP PM BANK H signal, 11-17
SWAP PM BANK signal, 10-17, 11-12
SWAP PMEM BANK H signal, 3-3, 3-8
SWAP PMEM BANK signal, 3-6
SWAP TRUE/COMP ADR defined, 5-35
SYNClTR GONE signal, 5-18, 5-39, 5-41, 5-49, 5-50
Sync character (LINK), 5-10
Sync character bytes, 5-18
Sync character detect enable PAL, 5-10, 5-46
Sync character detector enabled, 5-46
Sync detector, 5-11
SYNC signal, 5-11, 5-16
functions, 5-16
System Communications Architecture, 1-1
System Communications Services, 1-1

T
Tl PARESENT + signal, 3-3
T1 RCV + signal, 3-3
T1 RCV - signal, 3-3
T1 XMTR OUT + signal, 3-3
Tl XMTR OUT - signal, 3-3
T2 PRESENT + signal, 3-3
T2 RCV + signal, 3-3
T2 RCV - signal, 3-3
T2 XMTR OUT + signal, 3-3
T2 XMTR OUT - signal, 3-3
TABORT signal, 5-39
TACK signal, 5-49
TBS7 signal, 3-15
TDAL 08:02 signal, 3-12
TDAL 15:00 signal, 3-21
TDAL 21 :00 signal, 3-15
TDAL signal, 3-21
TDATA PARITY ERROR signal, 5-21
TDATA PARITY LATCH signal, 5-21
TDATA PARITY signal, 5-21
TDATA signal, 3-18
TDIN H signal, 11-27
TDIN signal, 3-18

SECURE/ENABLE switch
function (HSC70), 9-29
SELECT signal, 5-33
SEL PATH CARRIER signal, 5-32
SEL TPATH signal, 5-32, 5-41
SEL TRAILER signal, 5-41
S ENABLE 0 L signal, 3-2
S ENABLE 8 L signal, 3-2
S ENABLE 9 L signal, 3-2
S ENABLE i L lines, 3-38
S ENABLE i L signal, 3-2
Serial shift register timing, 5-24
SHIFT IN (E29-5) signal, 5-26
Shift register cycles, 5-16
SIDE SEL L signal, 3-4, 11-31
Signal
CARRIER DET B, 5-10
FORCE PATH A, 5-10
SINGLE STEP L signal, 3-2
SLOW CYCLE L signal, 3-2, 3-39, 11-8
SLOW MODE H signal, 11-4
Source byte, ACK, 5-21

Index-12

TDMG signal, 3-14
TDOUT H signal, 11-27
TDOUT signal, 3-21
TEST BOOTSRAP L signal, 3-2
TINIT signal, 5-39, 5-41, 5-49
TIRQ4 L signal, 3-12
TRACK 0 L signal, 3-3, 11-31, 11-33
Trailer bytes, 5-18
Transmit channel, 5-18
Transmit data input, 5-18
Transmit data parity check, 5-21
Transmit driver enable signals, 5-41
Transmit status (LINK) bits, 5-41
TR DLY signal, 5-47
TRPLY signal, 3-18, 3-21
True/complement destination bytes, 5-16
True destination address checking, 5-44
TSACK signal, 3-14
TS OE L signal, 11-26, 11-27, 11-30, 11-31
TSYNC H Signal, 11-27
TSYNC signal, 3-14, 3-15, 3-18, 3-21
TTL
transistor-transistor logic, 5-8
TWTBT signal, 3-15, 3-21

XMIT STATUS bits defined, 5-44
XMIT TEST CLK signal, 5-22
Xmtr Framer Shift Register (UNK), 5-22

v
VALID RCVR DATA signal, 5-47
VALID RCVR PARITY defined, 5-35

w
WACK Signal, 5-39, 5-44, 5-47
WR DATA L signal, 11-31
WRD AT A L signal, 3-3
WR GATE L signal, 3-3, 11-31
WR PROT L signal, 3-4, 11-31

x
XMIT ATTENTION signal, 5-39, 5-44
XMIT ATTENTION signal conditions, 5-41
XMIT BUFFE R EMPTY signal, 5-39
XMIT CLK generator, 5-22
XMIT CLK signal" 5-18, 5-22
XMIT CLK timing, 5-22
XMIT clock, 5-15
XMIT CRe ENA signal, 5-28
XMIT DATA BUS 7:0 signal, 5-26
XMIT data input latch, 5-18
XMIT DATA PARITY signal, 5-21
XMIT DATA signal, 5-18, 5-21
XMIT ECL Drivers, 5-24
XMIT FCN command, 5-33
XMIT PATH B SEL defined, 5-33
XMIT SERIAL DATA signal, 5-24
XMIT STATUS 4 signal, 5-39
XMIT STATUS 7:0 signal, 5-41

Index-13

INSTALLING AND RUNNING

TH~

CI EXERCISER

saFTW~RE

CAV-T637B-TE)

INSTALLING

A~O

RUNNING THg eI EXERCISER

SOFT~ARE

CONTENTS

--------

1.0
2.0

2.1
2.2

2.3
2.4
2.5
3.0
4.0
5.0

Page 2

PAGl:£

ABSTRACT • • • • • • • • • • • • • • • • • • • • • •
PREPARING TO RUN THE eI ~XERCISER •• • • • • • • •
Process Quotas And Privileges • • • • • • • • • •
System Resources • • • • • • • • • • • • • • • • •
~od1fylnq The System Parameters
•••••••••
SCS system 10 • • • • • • • • • • • • • • • • • •
pollIng Interval • • • • • • • • • • • • • • • • •
IN5TALLI~G THE eI EXERCISER SOFTWARE • • • • • • • •
LaAOI~G THE eI EXERCISER SOFTwARE
•••• • • • • •
RUNNING THE CI EXERCISER • • • • • • • • • • • • • •

APPENDIX A

SYSGEN PARAMETERS

APPENDIX 8

PROCESS QUOTAS AND PRIVILEGES

3
3
3
3

4
4
4
5
6

INSTALLING AND RUNNING THE eI EXERCISER SOFTwARE
1.0

Paqe l

ABSTRACT

The CI Exerciser 15 an onllne tool used to detect errors wlthin a CI
cluster and Isolate a oroblem to a speclfic node. The software cackage
consists of a user mode dlagnostlc that runs under the
dlagnostic
su~ervlsor, a controller class driver, and a responder class ~rlver.
When running the exerclser In a cluster, at least one nOde must be a
controller;
any or all of the nodes can be responders, The controller
sendS commands to the responder, the responder takes the soecified action
a"d returns responses to the controller, In thls manner, the controller ca"
syste~at1callY Check out the cluster and isolate any croblems to a
speciflc
node.
All error orintouts are made at the controlllnq nOdeCs);
user lnterface to the responder.

there

TO RUN THg CI EXERCISER

2.0

P~gPARING

2.1

Process Quotas And Privileges

When runninq the eI Exe~ciser, the user mu~t have speclfic priv1leges an~
quotas.
The reauired values can be qiven to an account by running the
authorize crogram. The privileges and quotas must at least meet the minlmum
Shown in apcend1x B.

2.2

system Resources

The SYSGEN utl11ty can be used to modlfy the parameters spee1fled below.
Since most are non-dynamic,
the system must be REBOOTED before the new
parameters values take effect.
IT IS STRONGLY RECOMMENDED THAT THE SYSTEM MANAGER BE
MODIFYING THE SYSGEN PARAMETERS ANO REBOOTING THE SYSTEM.

2.3

NOTIFIEn

BEFORE

ModlfylnQ The System Parameters

'rhe CI Exerciser (and assoclated drivers) reou1re a certain amount of system
resources.
Specifically, the values for nonpaqed poOl, IRP count, SRP
count, LRP count, scsconncnt and scsbuffcnt should be Increased before
loading and running the exerciser. Aopend1x A shows how to calculate tne
- requlred values. The CIEPARA~S command flle wlll modify tnese v~lues for
YOU.
DO ~IOT RUN THIS COMMAND FILE WITHOUT FIRST NOTIFYING THE SYSTEM
~ANAGER.
There is a second command flle that can be run to put these sysgen
values back to the values prior to running the CIEPARA~S command file, it 15
called CIEP~RRST.
If CIEPARA~S is run more than once, CIEPARRST w1ll only
return the values to the last set. Remember that once the sysgen oarameters
are Changed, rebooting will not restore them to there oriqinal values.
If
CIEPARA~S
is run tw1ce without runnino CIEPARST, the values must be chanaed
manually. Refer to aooendlx A to calculate the a~ount by which CIEPARAM~
will Change the sysqen parameters and for instructions to execute th@

INSTALLING AND RUNNING THE eI EXERCISER SOFTWARE

Page 4

command files. CIEPARAMS and CIEPARST command files are put
sysmalr,t area by the Installatlon proceedure explained belOw.

into

the

The cluster conflguratlon Is important in mod1fy1ng tnese parameters.
ControJLler/Responder nodes reQu1re qreattr increases to the parametera than
R.sponder nodes, and larqer clusters requ1re qreater increases to the
parameters than small clusters.
R~~fer to appendix A for a table t~at shows the add1tions that should be
made to the. system parameters as a function of node type and cluster
conf1guration.

2.4

SCS System 10

Each node 1n the CI cluster must have a unique, NON-ZERO SCS system
1dentl1!ication. This parameter Is strictly I software entity used by the eI
softwaz"e to distinguish between nodes in the cluster, and should not be
confused with the system conflquration reglster.
The SCS System 10 Is
modifie~d by the sysgen parameter SCSSYSTEMIO.
It more than one node 1n a
clustel~ has the same SCS system 10, the diaqnostic wlll NOT run correctly.

2.5

PollinQ Interval

The interval at whlcn the eI port driver polls should be kept at 15 seconds
or less.
This restriction helcs avoid excessivelY lonQ timeout Intervals
which can occur it an error is detected by the exerciser.
The polllnq
intervell is controlled by the sysqen parameter PAPOLLINTERVAL.

3.0

INSTALLING THE CI EXERCISER SOFTWARE

The CI Exercis~r software resides on floppy disk (AS-T637A-TE) for a
or on TUSS (BE-T64SA-OE) tor a CI750. Installinq the software simply
1nvolve~s executing a
command procedure on the media -h1ch coples the
aooropriate files into the SYSSMAINTENANCE area.
To install the CI
exerelser sOttware on a VAX do the followings
CI780

Log into the field service or system manaq@r account
Remove the console media from the console device
Insert the CI Exerciser media into the console device
-

Mount the CI Exerciser medla by typinq

"~OUNT

CS1 eIE"

Note:
If the attempt to mount the CIE media falls due to no device, then
the console must be connected using sysqen. Type the following and
then continue the installation:
S MCR SYSGEN
SYSGEN> CONNECT CONSOLE

INSTALLING AND

RUNNI~G

Page 5

THE CI EXERCISER SOFTWARE

SYSGEN) EXIT

Perform the installation

tyoinq

"~CS1:[CIE]CIEINSTAL"

Dismount the CI Exerciser med1a by tye1ng "DISMOUNT CS1"
Remove the eI Exerciser media from the console device
Reclace the console media in the console device
The latest version of the Diagnostic Supervisor should also be put into the
sysmaint area and used to run EVXCI.
OiaqnostiC supervisor media is
included in the installation kit.

4.0

LOADING THE CI EXERCISER SOFTWARE

Before runnlnq the CI exe~ciser, a second command procedure must be
executed to load the appropriate class driverCs) into nonpaaed pool. This
procedure, CIELOAD.CO~, prompts the user as to whether the node 1s to be a
controller or just a responder, and loads the driver(s) appropriately.
Running the controller in a node will cause moderate degradation of sYltem
performance, while runnlnq just th~ responder will have less of a degradinq
~ttect.

The drivers must be loaded each time the system is rebooted.
the drivers, oerform tne tollowinq steps:

load

Establish CMKRNL orivilege by typing "SET PROC/PPIV=C~KR"
necessary 1f the system ~anaqer account is beinq used)

(Not

Loq into the field service or system

Load the software

typing

~anager

account

"~SYSS~AINTEnANCE:CIELQAO"

I~STALLING

5.0

ANO

RU~NING

THE eI EXERCISER SOFTWARE

PeQe 6

RUNNING THE eI EXERCISER

()nce the CI class drivers have been loaded on the system, the responder
1s rceady to participate 1n cluster test activ1ty. The follow1nq addItional
commands must be Issued to run the controller software. Note that an ATTACH
and SI~LgCT command must be issued for each port that is to be tested.
For a CI780 •••
S RUN ESSAA
OS> LOAD EVXCI
OS> ATT CI780 S81 PAAO tr br port_number
OS> ATT CI_NODE PAAO node_name VAX780 port_number
OS> attach additional ports •••
OS> SELECT PAAO
DS> select additional ports •••
OS> 5T
For a CI7S0 •••
s RUN ECS~A
OS> LOAD EVXCI
OS> ATT CI750 ~UB PAAO slot br port_number
OS> ATT CI_NODE PAAO node_name VAX750 port_number
05> attach additional ports •••
OS> SELECT PAAO
OS> select additional ports •••
OS> 5T
~ote:

If runninQ the qenerate activity test, test 20, control C may take up to 30
secondS to respond.
when the DS promot 15 returned, the desired aetion may
be taken.
Note:
OnlY one controller Should run either th~ Qener~te activity test (test 20'
or the monitor performance counters test (test 21) in a cluster at one time.
A helc facility is also available with the CI Exerciser.
Type "HELP
gVXCI" to find the topics for which help information 1s ~va11abl~, and "HELP
EVXCI topic" for information about a particular topiC.

APPENDIX A
SYSGEN PARAMETERS

Below are two table, the first for nodes that are to be controllers
responders and the other for nodes that are to be only responders.
A controller node must be ~ responder.
The values are calculated by
first deter~lnlnq the maximum number of controllers and responders
that will be running in the system.
Then plug 1n the values and
determ1ne the amount to increase tne parameter.
~nd

C = maximum numoer ot controllers 1n the cluster.
R

= max1mum number of resoonders 1n the cluster.

+ add

* multioly

SYSGEN PARAMETERS

Page A-2

Parameter

V~lue

to add to exlstlnq parameter

-----------+---------------------------------------NPAGEDYN

29k

( 2.5k

* r

hytes

-----------+-----------------.. _-------------------SF/peOUNT

( 2

( S * C

--.--------+---------------------------------------IRPCQUNT

C 8

(

8 •

C )

-----------+---------------------------------------7 * R

LRPCQUtIlT

( 2 • C ,

._._--------.---------------------------------_._---2 * R

SCSCC'lNNCNT

-----------+---------------------------------------SCSBUF'F"CNT

2 • C

------_._--+---------------------------------------Table 1

Controller I R@sponder Node

C = maximum number of controllers 1n the cluster.
R = maximum number of resconders in the cluster.
+ add

* multioly

SYSGEN PARAMETERS

Value to add to existing parameter

Parameter

-----------+---------------------------------------NPAGEDYN

51<

2.51<

* C ) bytes

-----------.-----------------_._-----------._.-----SRPCOUNT

C 5 • C

-----------+---------------------------------_._-_.tRPCOUNT

-----------+----------------------------------~-.2 • R

LRPCOUNT

2 * C

-----_ ... _-+---------------------------_._._-------SCSCOP-JMCNT

-----------+------------_._._----------------------SCSBUF'FC~IT

.----------+--------------~-----------.---~--------Table 2

C = maximum

num~er

~es~onder

Only Node

of controllers in the cluster.

R = maximum number of responders 1n the cluster.
+ add

* multiply

SYSGEN

PARA~ETERS

Suppc,se one eontroller node is beinq run in a three node cluster, with
all three nodes bein; selected for test.
Then, the followin~
increases should be made to the sysqen p~ra~eters:
C
~

= 'L
= :2

In the controller/responder node:
NPAGEDYN
SRPCOUNT
IRPCOUNT
LRPCCHJ"IT
SCSCONNCNT
SCSBUFF'CNT

1)
31.51( bytes
29k + (2.-;
1 ) ::I 75
66 + (2
2) + (5
(8
1)
2) + (9
24
(7
1 ) = 16
2) + (2
(2
2) + 1
5
2 + (2 • 1 )
4

•

*
=

The 1~ollowlnq increases Should be made to the sysqen parameters in the
two resoonder nodes:
51(

IRPCOUNT
LRPCOUNT
SCSCONNCNT
SCSBUFFCNT

1)
7.51( bytes
+ (2.5
1)
2 ) + (5
7
(4
2) + ( 8
1)
16
1) = 6
(2
2) + (2
2 + 1 ::I 3
(2
1)
2

NPAGEDYN
SRPCOU~T

•
•*
*

•

•*

APPENDIX B
PROCESS QUOTAS AND PRIVILEGES

The followl~o is ~ table of minimum and tycical process quotas and
crivileqes needed to run the eI exercIser.
These values can be
modified by running the Authorize program.
Authorize has a help
facility to aid in ~aK1nq any necessary Changes.
PRIO:
PRCLM:
ASTLM:
FNQLM:
TQELM:

PrivIleGes

4
2
10
20
100

BYTLM:
65000
P8YTLM:
0
.a1SDEFAULTa 150
~SQUOTA:
1024
'I4SEXTENT: 1024

~IOLM:
D!OL~:

1000
1000
20
0

FILLM:
SHRFILLM:
cpu.
no lImIt

Digital Equipment Corporation. Colorado Springs, CO 80919