HSC50/70 Hardware Technical Manual

This document is the HSC50/70 Hardware Technical Manual, published by Digital Equipment Corporation in July 1986. It is a technical reference primarily intended for support-level field service representatives to understand the architecture and operation of the HSC50 and HSC70 mass storage server subsystems.

The manual provides a comprehensive technical description of the hardware, assuming prior knowledge of Digital Storage Architecture (DSA), Mass Storage Control Protocol (MSCP), Standard Disk/Tape Interconnects (SDI/STI), Computer Interconnect (CI), and basic HSC operation.

Key areas covered in the document include:

1. System Overview: An introduction to the HSC mass storage server, its role as a stand-alone controller and passive node in a CI cluster, its communication protocols (MSCP, TMSCP, DUP), I/O management, data integrity features (CRC, EDC, ECC, parity), self-diagnostics, and physical/electrical isolation.
2. Physical and Functional Characteristics: Detailed descriptions of the HSC's physical components (AC power controller, power supplies, blower/airflow sensor, console terminal, load device, operator control panel) and its functional modules. It highlights the differences between the HSC50 (F-11 CPU, TU58 load device, up to 6 data channels) and HSC70 (J-11 CPU, floppy disk load device, up to 8 data channels).
3. Internal Bus Architecture: A thorough explanation of the backplane buses:
   • Program Bus: Used by the CPU (P.ioc/P.ioj) and floppy disk controller (K.rx) to access Program Memory. Includes details on signals, transactions (DATI, DATO, DATOB, DATIO, DATIOB), interrupt protocols, and DMA mastership.
   • Control Bus: A synchronous bus used by various modules to access Control Memory, with details on signals, cycles (read, write, interrupt, lock, refresh, NMA), and arbitration.
   • Data Bus: A synchronous bus for high-speed data transfers between modules and Data Memory, covering signals, cycles, and arbitration.
   • Differences in bus implementation and signal names between HSC50 and HSC70 are noted.
4. Module-Specific Hardware Details: Each major module has dedicated chapters explaining its intricate components, interfaces, microinstruction words, and operational logic:
   • Host Interface (K.ci): Comprising the Port Link Module (LINK), Port Buffer Module (PILA), and Port Processor Module (K.pli), it details packet formats (information, ACK/NACK), CI arbitration, and data buffering.
   • I/O Control Processor (P.ioc/P.ioj): The central processing unit, covering its CPU chip set, memory management unit (MMU), internal registers, cache (HSC70), interrupt logic, and interfaces to the console, load devices, and internal buses.
   • Memory Modules (M.std/M.std2): Descriptions of Program, Data, and Control Memory organization, timing cycles (idle, read, write, refresh), and the Floppy Disk Controller (HSC70 only).
   • Data Channel Modules (K.sdi/K.sti): Interfaces with SDI/STI drives, data transfer functions, real-time controller state management, and detailed microinstruction fields.
5. Power System: A dedicated chapter on the AC power controllers, main and auxiliary power supplies, airflow sensor, and protection circuits (over voltage, over current, over temperature, power fail) for both HSC50 and HSC70.

The document focuses solely on the hardware's technical specifications and functional theory, excluding user information, general diagnostic utilities, installation procedures, and specific software details not directly tied to hardware operation.