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EK-DRV1J-UG-002

May 1980

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Document:	DRV11-J Parallel Line Interface User's Guide
Order Number:	EK-DRV1J-UG
Revision:	002
Pages:	62
Original Filename:	http://bitsavers.org/pdf/dec/qbus/EK-DRV1J-UG_002_DRV11J_UG.pdf

OCR Text

DRV11-J
parallel line interface
user's guide

EK-DRV1J-UG-002

digital equipment corporation • marlboro, massachusetts

1st Edition, December, 1979
2nd Edition, November; 1980

The material in this manual is for informational purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in this manual.

Printed in U.S.A.

This document was set on DIGITAL's DECset-8000 computerized
typesetting system.

The foHowing are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DIGITAL
DEC
PDP
DECUS
UNIBUS
DECLAB

DECsystem-lO
DECSYSTEM-20
DIBOL
EduSystem
VAX
VMS

MASSBUS
OMNIBUS
OSj8
RSTS
RSX
lAS
~1INC-ll

'1"80·1'5

CONTENTS
Page
CHAPTER 1

INTRODUCfION

1.1

1.4
1.5
1.5.1
1.5.2
1.5.3
1.5.3.1
1.5.3.2
1.5.3.3
1.5.3.4
1.6

GENERAL DESCRIPTION ................................................................................
FEATURES ..................................... ~.....................................................................
DOCUMENTATION............................................................................................
DIAGNOSTIC SOFTWARE ...............................................................................
SPECIFICATIONS...............................................................................................
Physical Specifications ............................. ............ ....... .......... ....... ..................
Electrical Specifications...................................................... ...... .................. ...
Environmental Specifications .............................................. ...... ... ..... ............
Operating and Storage Temperature Ranges ........................................
Relative Humidity............................................................... ... ..... ...........
Airflow during Operation.......................................................................
Altitude ................... 00.............................................................................
INSTALLATION..................................................................................................

CHAPTER 2

FUNCfIONAL DESCRIPTION

2.1
2.2

GENERAL DESCRIPTION ................................................................................ 2-1
CONTROL/STATUS REGISTERS ................................................................... 2-1
DATA BUFFER REGISTERS............................................................................. 2-1
INTERRUPT CONTROL .................................................................................... 2-1
Functional Description ... ......... ....................................................................... 2-7
Interrupt Controller Interface........................................................................ 2-7
Interrupt Controller Operating Description................................................... 2-9
Interrupt Control Reset ...... .................. .................. ...... ............... .... .... ........... 2-12
Interrupt Control Register Description............................. ....... ...................... 2-13
Status Register..... ............ .............. ........................................................ 2-13
Command Register ............................................................................. ,... 2-14
Mode Register........................................................................................ 2-14
Interrupt Request Register (lRR) ............. ............................. ............... 2-14
Interrupt Service Register (ISR) ........................................................... 2-15
Interrupt Mask Register (IMR) ............................................................ 2-16
Auto-Clear Register (ACR) .................. ........... ..... .... ........ ..................... 2-16
Vector Address Memory........................................................................ 2-16
OPERATING OPTIONS ...................................................................................... 2-17
Interrupt Priority Mode Selection......................... ......... .......... ..... .......... ....... 2-17
Individual Vector or Common Vector Mode .................................................. 2-19
Interrupt or Polled (Flag) Mode........................... ..... ..................................... 2-19
Mode Register Bit 3 ..... ................ ............ ...................................................... 2-19
IRQ Polarity Option ....................................................................................... 2-19
Register Preselection Option.......................................................................... 2-19
Master Mask Option ...................................................................................... 2-20
SYSTEM OPERATING SEQUENCE ............................ .......... .......................... 2-20
COMMAND DESCRIPTIONS ........................................................................... 2-21
Reset ................................................................................................................ 2-21
Clear IRR and IMR ....................................................................................... 2-21
Clear Single IMR and IRR Bit ...................................................................... 2-21
Clear IMR ........... ...... ...... .......... ........ ........... .................................................. 2-21

1.2
1.3

2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.5.1
2.4.5.2
2.4.5.3
2.4.5.4
2.4.5.5
2.4.5.6
2.4.5.7
2.4.5.8
2.5
2.5.1
2.5.2
2.5.3
2.5.4
2.5.5
2.5.6
2.5.7
2.6
2.7
2.7.1
2.7.2
2.7.3
2.7.4

lit

1-1
1-1
1~2

1-2
1-2
1-2
1-2
1-3
1-3
1-3
1-3
1-3
1-3

CONTENTS (Coot)
Page
2.7.5
2.7.6
2.7.7
2.7.8
2.7.9
2.7.10
2.7.11
2.7.12
2.7.13
2.7.14
2.7.15
2.7.16
2.7.17
2.7.18
2.7.19
2.7.20

Clear Single IMR Bit ..................................................................................... 2-22
Set IMR........ ....... ............. ..... ............................. ............ ................................ 2-22
Set Single IMR Bit ................................................................................... ,. .... 2-22
Clear IRR ....................................................................................................... 2·22
Clear Single IRR Bit... ......... ............. ....... ....................... ................. .............. 2-22
Set IRR ......... ....... ..... .......... ... ........................................................................ 2-22
Set Single IRR Bit ......................................................................................... 2-23
Clear Highest Priority ISR Bit .......................... ............................................ 2-23
Clear ISR ....................................................................... ................... .......... ... 2-23
Clear Single ISR Bit ...................................................................................... 2-23
Load Mode Bits MO through M4 ................................................................... 2-23
Control Mode Bits M5, M6 and M7 ...... .................................................. ...... 2-23
Preselect IMR for Writing ............................................................................. 2-24
Preselect ACR for Writing............................................................................. 2-24
Preselect Vector Address Memory for Writing ............................................. 2-24
Coding B2, B 1, BO Field Commands ......... .... .......................................... ...... 2-25

CHAPTER 3

CONFIGURATION

.3.1
3.2
3.3
3.4
3.5

GENERAL DESCRIPTION ................................................................................
FACTORY CONFIGURATION .........................................................................
DEVICE ADDRESSES ........................................................................................
DEVICE ADDRESS JUMPERS..........................................................................
INTERRUPT VECTOR ADDRESSES...............................................................

CHAPTER 4

INTERFACING

4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9

INTERFACE CONNECTORS............................................................................
INPUT jOUTPUT SIGNAL FUNCTIONS ........................................................
INPUT jOUTPUT SIGNAL ASSERTION LEVELS ........................................
INPUT jOUTPUT SIGNAL LOOPBACK CONNECTIONS ...........................
INTERFACE CABLE.. ............................................................... .... ........... ...... .....
INPUT/OUTPUT FUNCTION TIMING ..........................................................
INPUT DATA OPERATION...............................................................................
OUTPUT DATA OPERATION ...........................................................................
INTERRUPT OPERATION ................................................................................

CHAPTERS

PROGRAMMING EXAMPLES

5.1
5.2
5.3
5.4

GENERAL DESCRIPTION ................................................................................
PROGRAMMED DATA TRANSFER WITHOUT HANDSHAKING ...........
PROGRAMMED DATA TRANSFER WITH HANDSHAKING....................
INTERRUPT-DRIVEN TRANSFER .................................................................

CHAPTER 6

OPTIC ISOLATOR INTERFACE EXAMPLE

3-1
3-1
3-1
3-5
3-5

4-1
4-1
4-1
4-5
4-5
4-5
4-9
4-9
4-9

5-1
5-1
5-1
5-3

FIGURES
Figure No.
2-1
2-2

2-3
2-4
....

L.-J

2-6
2-7

2-8
2-9
2-10
2-11
2-12

2-13
3-1
3-2
4-1
4-2
4-3
4-4
4-5
4-6
5-1
5-2
5-3
5-4
6-1

Tide

Page

DRV!l-J Block Diagram........................................................................................ 2-2
CSRA Bit Assignments '" ....... ............. ...................................................... ......... ..... 2-3
CSRB Bit Assignments............ .................................. ................. ....... ......... ........ .... 2-4
CSRC Bit Assignments ............................................................... ........ .... ........... .... 2-5
CSRD Bit Assignments. ................. ....... ......................................................... ........ 2=6
Data Buffer Register Bit Assignments................................. .................................. 2-7
Group 1 and Group 2 Interrupt Controller
Interconnections.................. .......... ................................................................. 2-8
Intergroup Priority Resolution Timing ................................................................... 2-10
Interrupt Controller Block Diagram............................................ ....... .................... 2-11
CSRA and CSRC Status Registers' Bit Assignments ........................................... 2-14
Mode Register Bit Assignments ..................... .......... ......... ....................... .......... .... 2-15
DRVl1~J Vector Address Format .......................................................................... 2-17
Rotating Priority Mode.... ............................. ......................................................... 2-18
DRYlI-J Jumper Locations ................................................................................... 3-2
DRVII-J Device Address Format.......................................................................... 3-5
DRYll-J I/O Connector Pin Locations................................................................. 4-2
I/O Bus Interface, Simplified Schematic .............................................................. 4-4
DRVll-J I/O Function Timing ............................................................................. 4-7
Input Data Transfer Sequence ......................... ..... ....................... ... ... ............ ........ 4-10
Output Data Transfer Sequence ............................................................................ 4-1 i
Interrupt Sequence................................................................................................. 4-12
Example of a Programmed Data Transfer
without Handshaking ..................................................................................... 5-2
Example of a Programmed Data Transfer
with Handshaking... ....... ........................ ...... ..... ... ...... .... ................ ........ ... ...... 5-3
Example of an Interrupt-Driven Output Program ..................... ............................ 5-4
Example of an Interrupt-Driven Input Program ...................... .............................. 5-5
Example of an Optic Isolator Interface.................................................................. 6-2

TABLFS
Table No.
1-1
2-1
2-2

2-3
2-4
2-5
2-6
2-7
2-8
2-9

Title

Page

DRVII-J Module Pin Assignment ......................................................................... 1-4
CSRA Bit Functions and Descriptions..... .... ................... ....................................... 2-3
CSRB Bit Functions and Descriptions .. ....................................................... .......... 2-4
CSRC Bit Functions and Descriptions................................................................... 2-5
CSRD Bit Functions and Descriptions................................................................... 2=6
Summary of Data Bus Transfers ............................................................................ 2-12
Interrupt Control Register and Memory Summary ............................................... 2-13
Fixed Priority Mode ...... ..... ...... ...................... ............. ........................................... 2-17
Vector Address Memory Field Coding ................................................................... 2-25
Command Register B2, BI. 80 Field Coding ......................................................... 2-25
v

TABLES (Coot)
Table No.
2-10

3-1
3-2
3-3
4-1
4-2
4-3
4-4

Title

Page

DRV11-J Command Code Summary ..................................................................... 2-26
DRVII-J Factory Jumper Configuration................................................................ 3-3
DRV11-J Jumper Functions................................................................................... 3-4
DRVII-J Registers................................................................................................. 3-4
I/O Connector Pin Assignments ............................................................................ 4-2
I/O Signal Functions.............................................................................................. 4-5
DRVII-J Loopback Signal Connections................................................................ 4-6
I/O Function Timing Tolerance............................................................................. 4-8

CHAPTER 1
INTRODUCTION
1.1 GE~ERAL DESCRIPTIO~
The DR V II-J is a double-height parallel line interface module designed for use in LSI-II microcomputer systems. It contains four programmable ports designated A. B. C and D. Each port contains
16 I/O lines and is capable of transferring a 16-bit word between the LSI-II bus and the user device(s}.
Data word transfers in or out of the DR V II-J are accomplished by the assertion of two control signals
at each port of the 0 R V II-J and two control signals asserted by the user device to its respective port.
These control signals must be asserted in a protocol sequence while observing timing constraints to
ensure an orderly data transfer. The protocol sequence is described in Chapter 2.
The DR V II-J will also accept ir.terrupt requests from up to 16 1/0 lines to generate up to 16 individual vector addresses. This interrupt capability for real-time response makes it useful for sensor I/O
applications. The DR V II-J may also be used as a general-purpose interface to custom devices. or two
DR V II-Js may be connected together as a link between two LSI-II buses.
The DRVII-J contains two programmable mode registers that provide a number of operating modes
to customize the moduie configuration for different system applications. The module may be programmed for use in vectored-interrupt-driven systems or software-polled systems. When used in vectored
interrupt systems. the module may be programmed to operate in either a fixed priority or a rotating
priority resolution mode. In addition. the module may be programmed to generate either a common
vector address or individual vector addresses in response to user device(s} interrupt requests. Additional operating options available under program control include the selection of an active high or
active low interrupt request polarity. preselection of internal registers, and the selection of a master
mask bit to arm or disarm the interrupt capability of the DR V I1-J. All of the operating modes and
options are described in detail in Chapter 2.
The DR V I1-J also contains two RA Ms that are used to store programmed interrupt vector addresses.
One 8-bit RA M location is used to store each interrupt vector address. One vector address may be
programmed for each of the 16 interrupt request inputs.

1.2 FEATLRES
The DR V 11-J contains the following features.
•
•
•
•
•
•

Four 3-state 16-bit parallel I/O ports
User-assigned device addresses
Acceptance of up to 16 external interrupt requests
Programmable interrupt vector addresses
Program-controlled input/ output operations
Programmable operating modes:
Interrupt Controller Mode - Interrupt-driven
Priority Modes - Fixed or Rotating
Vector Address Selection - Individual or common vector

I-I

1.3 DOCUMENTATION
I n addition to this user's guide, refer to the Field Maintenance Print Set, M POO866, for information on
the DRVII-J module.
1.4 DIAGNOSTIC SOFTWARE
Diagnostic software is available for troubleshooting, fault isolation, and verification at both the module level and system level. Two diagnostics are required for testing at the module level and these must
be run in sequence. A DECX II module diagnostic is required to test the module at the system level.
Turnaround cable BC05W-02 must be installed with a half twist to J I and J2 when running the module- and system-level diagnostics. The diagnostic software is designated as follows.

•
•
•

CVDRCAO Part I
CVDRDAO Part 2
DECX 11 Module CXDRJAO

1.5 SPECIFICATIONS
The following defines the physical, electrical and environmental specifications for the DRV II-J
module.
1.5.1

1.5.2

Physical Specifications

Identification

M8049

Size

Double-height
22.8 cm X 13.2 cm
(8.9 in X 5.2 in)

Electrical Specifications

Power

+5 Vdc ± 5% @ 1.8 A (maximum),
1.6 A (typical)

Bus loads

ac 2
dc I

I/O Signal Electrical Parameters:

Data Buffer 3-State Outputs

Data Buffer Inputs

V(OL) = 0.5 V @ I(OL) = 8 rnA
V(Ol) = 0.4 V @ I(OL) = 4 rnA
V(OH) = 2.4 V @ I(OH) = ...:2.6 rnA

I(lL) = -0.2 rnA @ V(IL) = 0.4 V
V(IH) = 20 ~A @ V(lH) = 2.7 V

Protocol Signal Inputs

Protocol Signal 3-State Outputs
V(OL) = 0.55 V @ I(Ol) = 64 rnA
V(OH) = 2.4 V @ I(OH) = -15 rnA

1-2

Termination = 120 n
I(IL) = -27 rnA @ V(IL) = 0.5 V
I(lH) = 80 ~A @ V(IH) = 2.7 V

1.5.3 Enfironmental Specifications
The DRVII-J module may be operated or stored in the following environmental conditions.
1.5.3.1

Operating and Storage Temperature Ranges

Operating range:

50 to 60 0 C (41 0 to 140 0 F)

Storage range:

-40 0 to 66 0 C (-40 0 to 150 0 F)

If the module is not within its operating temperature range, move it to an area within the range and
allow it to stabilize for a minimum of five minutes before operating. Also, derate the maximum operating temperature by 10 C (1.8 0 F) for each 305 m (1000 ft) of altitude above 2440 m (8000 ft).
1.5.3.2

Relatbe Humidity

Storage:

10% to 90%, noncondensing

Operating:

10% to 90%, noncondensing

1.5.3.3 Airflow during Operation - Provide adequate airflow to limit the inlet-to-outlet temperature
rise across the module to 50 C (9 0 F) when the inlet temperature is 60° C (140° F). For operation
below 55 0 C (131 ° F), limit that rise to 10° C (18° F) maximum.
1.5.3.4

Altitude

Storage:

The module will not be mechanically or electrically damaged at altitudes up
to 15,240 m (50,000 ft), 90 mm mercury.

Operating:

Up to 15,240 m (50,000 ft), 90 mm mercury. Note: Derate the maximum
operating temperature by 10 C (1.8 0 F) for each 305 m (1000 ft) of altitude
above 2440 m (8000 ft).

1.6 INSTALLA TION
The DR V I1-J is a bus request level 4 module and must be installed in an LSI-! I backplane dual-option
slot foHowing the rules for position-dependent interrupt priority configurations. In position-dependent
configurations, peripheral devices with the highest priority must be installed closest to the processor
and the remaining devices placed in the backplane in decreasing order of priority, with the lowest
priority module farthest from the processor.

Before installing the module(s) in the backplane, check that the proper device address jumpers are
installed. Three standard LSI-II bus addresses are reserved for the DRVII-Js. If the application requires more than three DR V 11-1s, the additional modules must be assigned addresses located in the
user-reserved address space. Chapter 3 describes the address configuration procedure. The standard
factory jumper configuration is described in Table 3-1, and Figure 3-2 shows the device address format.
CAUTION
DC power must not be applied to the backplane when
installing or remofing modules.
The DRVl!~'s functionality must be proved after
installation by performing an acceptance test. The
acceptance test consists first of running the basic system diagnostics and then running the DR V Il-J module-level diagnostics listed in Paragraph 1.4.

1-3

Module Pin Assignments
The DRV11-J module pin assignments are described in Table I-I.

Table I-I

DRVII-J Module Pin Assignment
Connector B

Connector A
Side J
Signal

Side I
Signal

+5V
NC
GND
NC
BDOUTL
BRPLY L

NC
NC
NC
NC
NC
NC

A
B
C
D
F

+5V
NC
GND
NC
BDAL2L
BDAL3L

NC
NC
NC
NC
NC
NC

H
J
K
L
M
N

BDAL4L
BDAL5L
BDAL6L
BDAL7L
BDAL8L
BDAL9L

BIRQ 7 L
NC
NC
GND
NC
NC

P
R
S

BDAL 10 L
BDAL II L
BDALI2L
BDAL 13 L
BDAL 14 L
BDALI5L

BIRQ 5 L
BIRQ 6 L
NC
NC
NC
NC

A
B
C
D

NC
NC
NC
NC
NC
NC

H
J
K

L
M
N

BDIN L
BSYNC L
BWTBT L
BIRQ4
BIAKI L
BIAKO L

NC
NC
NC
GND
NC
NC

P
R
S
T
U
V

BBS 7 L
BDMGI L
BDMGOL
BINITL
BDALO L
BDALI L

E
F

Side 2
Signal

Side 1
Signal

NOTE:
1. Connector A, pin A, side 1 corresponds to bus pin AA I.
2. NC = no connection.

1-4

U
V

CHAPTER 2
FUNCTIONAL DESCRIPTION
2.1 GE:\IERAL DESCRIPTION
The DRVII-J contains the logic necessary to provide communication between the LSI-II bus and up
to four user devices in 16-bit word lengths via four I/O ports. Four control lines associated with each
of the four ports ensure orderly information transfers. Word transfers are executed by programmed
I/O operations or interrupt-driven routines. Write data is output by the DRVII-J to the I/O bus
through 3-state data latches, and read data is input through unlatched bus buffers. Figure 2-1 shows
the main logic functions performed by the 0 R V I1-J module.

All control/status and I/O data transfers take place over a bidirectional internal bus (TSD < 15:00»
on the DRVII-J. The module contains four I/O buses, one for each port (A, B. C and D). Each port
has an associated control/status register (CSRA, CSRB. CSRC or CSRD) that contains status information when read and command words when written. All ports have 16 bidirectional 3-state lines and
perform controlled input/output operations. Note that port A is the only port that will perform bit
interrupt functions in addition to input/ output data transfers. The 16 external interrupt requests are
functionally divided into two groups of eight lines, referred to as group 1 and group 2.
2.2 CONTROL/STATUS REGISTERS
The control/status registers (CSRA, CSRB, CSRC and CSRD) are read/write byte-addressable registers with bit assignments as shown in Figures 2-2, 2-3, 2-4 and 2-5. The function and description of the
control/status register bits are described in Tables 2-1, 2-2, 2-3 and 2-4.

2.3 DATA BUFFER REGISTERS
The four data buffer registers (DBRA, DBRB, DBRC and DBRD) are 16-bit word-addressable registers. They are used as latched output data buffers when the DRV Il-J is in output mode (write) and as
unlatched bus buffers in input mode (read). The contents of the output data buffers may be examined
while the DR V 11-J is in an output mode by performing a read operation of the input data buffers. This
ability to examine the output data buffers in the output mode provides software access to the internal
conditions of the 0 R V 11-J.

The latched output data buffer registers DRBA through DBRD are not cleared by BINIT. The bit
assignment is the same for all registers and is shown in Figure 2-6.
2.4 INTERRUPT CONTROL
The DRY11-J is capable of monitoring 16 lines to generate 16 vectored interrupts. The interrupt control is performed by a DeOO3 interrupt logic chip and interrupt controller chips. A functional description of the signals required to initiate interrupts and the DRY 11-J registers used for programming,
reading and writing the internal registers of the interrupt controllers is given in Paragraph 2.4.1. An
operating description of the interrupt controllers is given in Paragraph 2.4.2, and the internal registers
of the interrupt controllers are described in Paragraph 2.5

2-1

r--INTERRUPT CONTROL ~
E1~

IR07~----------.---,-r----------~~---------------------,

GROUP 2

IRO 6 .....- - - - - , - - . - + i
IRO 5 '-,----.-.--~

IRO
BUFFER

INTERRUPT IR04~----------ri-t-t1-________~~~------------------~

~r--~

~~~C8~~~O

r-::)

BIAKI L

BINIT L

~~~

r-________~6~

__ ~: ~

I--

DC003

GINT
RIP El

' - - - A15
'--_ _ _~r-

AI/O<'11'B>

IRQ <"70>

I~<--~_~_~A_T._RcO_sL_R~_E_R...;;;.r-,~.i
-

IRO

"A''---A-I/-O-''-'-O->---'

~
..r:' ""--g-~-~-~-" "

BUFFER

TSD<7,O,»

USER RPL Y C
USER RPLY 0

"
- - - - - - "A'--_
_ _ _ _ _~

'----------~ ~
A.t-_____________~--~~----_,

GROUP 1
INTERRUPT

LOW BYTE

KV ___A_"_O_<"_'_5_'_2>_.,

BUFFER

' - -_ _ _ _ _ _ _ _---l....
~

.--________

A IIO·~150>

IAK
XMIT A
WRT A

N
N

(AR2)

BDMGI L

(AS'})

BOMGO L

•

VECTOR
ADDRESS
BUffER

(

K:'r__
TRANS
CEIVERS

....
y

...

---.1 f

BBS7 L V'

Wl-W9

~
V
o

MATICH H
•

III
t-

XMIT 0

(AE,})

BoOUT L

(AH2)

BDIN L

(AJ2)

BSYNC L

(AF2)

BRPLY L

110 CONTROL
AND
READIWRITE
REGISTER
SELECT

0110<150>
(PORT 0 DBRD)

) ____

WRTO~

....
USER ROY A
.R_O_D_-=-=-=-=-=-=~~~r--------r_----~~~~~~---~----

TSo<10>

)

~ WRT CSRA

...

Ro A. B. C. 0

WRT A. B. C. 0

_
_

XMIT A. B. C. 0
OUT HB

_
~

)

---.J t

______________________
L.
TSDB

VEC

'_
BWTBT L

(PORT C DBRC)

CSRO
DBRD
L....,.--....-.,...--' ...

)

,...-__---lL.-__......, "A,L-_____________""'....

(AK2)

'----

__--------J.,. ____

C 110<15:0>

-----1
....

(AP,})

)

XMIT C
WRT C
ROC - - - - - '

ADDRESS
JUMPERS

ADDRESS
DECODER

-----1

CSRC
oBRC

BDAL<I,}:4> )

B 1/0<15 0>
(PORT B DBRB)

'--...-...-..,...._' ~

-.--J t

...J

CSR15
DIR(VB)

....

<t:

r---

)

-----1

~_ _R_D_B_....~~====~rA~----~~

T_S_D_<_15_:0_>_ _, / ) ~

R_D_A~,~====~rA~-------------------J
. ,.
g~~~

_____

XMIT B
WRT B

TSD<150>

(PORT A oBRA)

---.1 f

V9·V2

USER RPlY B

"A,......_ _ _ _ _ _ _- ,

I RO

A14

SELO _
WRTCSRA _

USER RPl Y A

~-=-

.......,._....-;.,RI;;-P_E;;,O::.-r· "

1--(-A-N-2)----B-IA-K-O-L---tOf
(AT2)

....

~_(A--L2-)---_B-IR-Q-4_L~
(AMI)

~ •.Wll

CONTROLLER

CSRA

DRVllJ ROY A
DRV l1J RPL Y A

r-------....._U_S_E_R_R_o_Y_B_ _--I
CSRB
REGISTER
.....

PORT

SELECT

~~L._~o_NN_DT_PR_Oo_RL_T..rl
•
LATCH

..
"

SEL 0

....

DRV11J RPLY B

CONTROL

lDAL<3:'}»
CSR 15 ~

----'--_________~'-,,,~-----------------L-DA--Lr--3-:-L->-------------------'

Figure 2·1

DRVllJ ROY C
DRV1'J RPL Y C

-~...:.U...:S..::.E~R-R...:D...:.Y-O=-----f

SELO_
OUTHB_L-______

DRVII·J Block Diagram

r-------14-...:U...:S..::.E~R...:.R...:D...:.Y_C=____-1r:::::---_,
CSRC

01 R (VB) _

.iI

oRV11J ROY B

CSRD

DRV11J ROY 0

-L____~r_-D_R-V-'-1J-R-P-L-Y-D-~____

15
ROY
A

UNUSED
I

DIR
A

CIS

MR-431g

Figure 2-2

Table 2-1

CSRA Bit Assignments

CSRA Bit Functions and Descriptions

Bit

Name

Function

Description

07:00

C/S7-C/SO

Read/Write

These bits are used in conjunction with CSRB bits<07:00> to program
interrupt control group I. They contain status information when read and
command words when written. Unaffected by BINIT. (See Paragraphs
2.4.5.1 and 2.4.5.2 for status and command definitions.)

DIR A

Read/Write

DIRECTION A. Used for controlling DBRA. This bit. in conjunction
with the USER RDY signal. controls the direction of data transfer. When
the DIR bit is cleared. the DRV IIJ RDY output signal is asserted and the
DRVII-J is the input device. When this bit is set and the USER RDY
signal is asserted. the D RV II-J is the output device. The negation of either
DIR or USER RDY causes the DRV II-J outputs to remain in their highimpedance state. Cleared by BINIT.

Read/Write

INTERRUPT ENABLE. Enables the DRV II-J to generate processor interrupts when set. Used to enable both group I and group 2 interrupts.
Cleared by BINIT.
Unused. Read as Os.

14:\0
15

ROY A

Read Only

USER READY A. Used for controlling DBRA. When read. this bit yields
the state of the USER ROY signal. A 0 means negated- and a I means
asserted. This bit is used in conjunction with the DIR bit to enable DRV 11J output operations. The user device asserts this signal when it desires the
DRV II-J to output data. Unaffected by BIN IT.

2-3

15
ROY
B

UNUSED

·1

OIR
8

MR·4312

Figure 2-3

Table 2-2

CSR B Bit Assignments

CSRB Bit Functions and Descriptions

Bit

~ame

Function

Description

07:00

D7-DO

Read/Write

These bits are used in conjunction with CSRA bits <07:00> to program
interrupt control group I. They contain information selected by the command word loaded through CSRA. The registers available are the IRR,
ISR, ACR, IMR and the vector address memory. Unaffected by BINIT.
(See Paragraphs 2.4.5.4 through 2.4.5.8 for a detailed description of the
registers and their functions.)

DIR B

Read/Write

DIRECTION B. Used for controlling DBRB. This bit, in conjunction with
the USER RDY signaL controls the direction of data transfer. When the
DIR bit is cleared, the DRY IIJ RDY output signal is asserted and the
DRYII-J is the input device. When this bit is set and the USER RDY
signal is asserted. the DRY II-J is the output device. The negation of either
DIR or USER RDY causes the DRYII-J outputs to remain in their highimpedance state. Cleared by BINIT.
Unused. Read as Os.

14:09
15

RDY B

Read Only

USER READY B. Used for controlling DBRB. When read, this bit yields
the state of the USER RDY signal. A 0 means negated and a 1 means
asserted. This bit is used in conjunction with the DI R bit to enable DRV 11J output operations. The user device asserts this signal when it desires the
DRYII-J to output data. Unaffected by BINIT.

2-4

15
ROY

UNUSED

.....I

OIR

CIS
7

CIS

CIS
5

CIS
4

CIS

0
l\r1R·4313

Figure 2-4

Table 2-3

CSRC Bit Assignments

CSRC Bit Functions and Descriptions

Bit

Name

Function

Description

07:00

CjS7-CjSO

Read/Write

These bits are used in conjunction with CSRD bits <07:00> to program
interrupt control group 2. They contain status information when read and
command words when written. Unaffected by BIN IT. (See Paragraphs
2.4.5.1 and 2.4.5.2 fOi status and command definitions.)

DIR C

Read/Write

DIRECTION C. Used for controlling DBRC. This bit, in conjunction with
the USER RDY signal, controls the direction of data transfer. When the
DIR bit is cleared, the DR V IIJ R DY output signal is asserted and the
DRVII-J is the input device. When this bit is set and the USER RDY
signal is asserted, the DR V II-J is the output device.The negation of either
DIR or USER RDY causes the DRV II-J outputs to remain in their highimpedance state. Cleared by BIN IT.
Unused. Read as Os.

14:09

ROYC

Read Only

USER READY C. Used for controlling DBRC. When read. this bit yields
the state of the USER RDY signal. A 0 means negated and a I means
asserted. This bit is used in conjunction with the DIR bit to enable DRVIIJ output operations. The user device asserts this signal when it desires the
DRVII-J to output data. Unaffected by BINIT.

2-5

15
ROY

I-

·1

UNUSED

DIR

DO
MR-4314

Figure 2-5

Table 2-4

CSRD Bit Assignments

CSRD Bit Functions and Descriptions

Bit

;\lame

Function

Description

07:00

D7-DO

Read/Write

These bits are used in conjunction with CSRC bits <07:00> to program
inter rupt control group 2. They contain information selected by the command word loaded through CSRC. The registers available are the IRR,
ISR. ACR, IMR and the vector address memory. (See Paragraphs 2.4.5.4
through 2.4.5.8 for a detailed description of the registers and their functions.)

DIR D

Read/Write

DIRECTION D. Used for controlling DBRD. This bit. in conjunction
with the USER RDY signal, controls the direction of data transfer. When
the DIR bit is cleared, the DRVl tJ RDY output signal is asserted and the
DRVII-J is the input device. When this bit is set and the USER RDY
signal is asserted, the DRV II-J is the output device. The negation of either
DIR or USER RDY causes the DRVII-J outputs to remain in their highimpedance state. Cleared by BINIT.
Unused. Read as Os.

14:09

RDY D

Read Only

USER READY D. Used for controlling DBRD. When read. this bit yields
the state of the USER RDY signal. A 0 means negated and a I means
asserted. This bit is used in conjunction with the DI R bit to enable DRV I 1J output operations. The user device asserts this signal when it desires the
DRVII-J to output data. Unaffected by BINIT.

2-6

1oIII~"'------1/0 BUS <15: 8 > - - - - - -......14..------1/0 BUS <7 :O>--------4.~1

MR-4315

Figure 2-6

Data Buffer Register Bit Assignments

2.4.1 Functional Description
The interrupt control logic shown in Figure 2-1 consists primarily of a De003 interrupt logic chip and
two interrupt controller chips. Five LSI-II bus control signals (BIRQ 4 L, BIAKI L, BIAKO L, BDIN
Land BINIT L) are used by the interrupt control logic for initialization, sending interrupt requests to
the processor, receiving the interrupt acknowledge signal from the processor, and sending the vector
address to the processor.

Each interrupt controller chip is responsible for monitoring a group of eight interrupt request inputs.
Each group of eight interrupt requests is applied via I RQ buffers to an 8-bit interrupt request register
(lRR) in the interrupt controller.
The two interrupt controllers (group I and group 2) are programmed independently. The group I
interrupt controller is programmed through the low bytes of eSRA and eSRB while the group 2
interrupt controller is programmed through the low bytes of eSRC and CSRD. The oniy commonalities of the two groups are priority resolution and the interrupt enable (IE) eSRA bit 9. Both
interrupt controllers must operate in the same mode, either interrupt or polled. Each interrupt controller contains an 8-bit interrupt mask register (lMR) that may be used to disable the processing of
any undesired interrupt requests.
The group 1 interrupt controller has the higher priority and its enable output is connected to the enable
input of group 2. Group I must be armed to accept interrupts with the master mask bit set in the mode
register. When group 1 is armed, its enable output goes high. thus enabling group 2 interrupts. Therefore, whenever the interrupt mode is selected, group 1 must be armed, even if none of the group 1
interrupt requests are being used in order to pass the enable signal along to group 2.
Group I and group 2 may be programmed to respond to either an active high or an active low transition on the interrupt request lines. A bit in the interrupt request register (IRR) is set whenever the
corresponding interrupt request line makes an inactive-to-active transition and meets rhe active pulse
width requirements. Active pulse widths 270 os or greater wi!! set the corresponding IRR bit, while
pulse widths 30 ns or less are ignored. Active pulse widths between 30 ns and 270 ns mayor may not set
the IRR bit.
2.4.2 I nterrupt Controller Interface
The interconnections between the group I and group 2 interrupt controllers. their relation to the
DR V II-J A I/O bus and the LSI-II bus are shown in Figure 2-7. Latched data address line LDAL 3 L
or H, along with the SEL 0 L signal. is used to select group 1 for subsequent reading/writing through
the low byte of CSRA or CSRB. or group 2 for reading/writing through eSRC or CSRD. Intergroup
priority management is controlled by the enable-in (EI). enable-out (EO) and the response-in-progress
(RIP) signals. Note that the IAK L. GINT. RIP. and PAUSE lines are respectively tied together.
Group I is always enabled because its enable-in (EI) pin is floating high. The enable-out (EO) signal of
group I is connected to the enable-in (EI) pin of group 2.

2-7

VECTOR·
ADDRESS
BUFFER

GROUP 1
INTERRUPT CONTROLLER
CSRA, CSRD LOW BYTE

TSD <7:0> " )
y

y---

..,.

()

(~<;~

PAUSE

SELOL -

R 0 EN )>---t--t---i

LDAL3H

-A12

YJ4

-----

.J;: Wll

CS WRT RD

IAK GINT E1

RIP PAUSE I A
IRO<3:0>K. -

..,-

V:!-'-----~
~ 1/0 <15:12>

r - - - A13

--~-(~~-~()~(-)--()--(-~----~()~(~~--

)

.-----1 A 14

csa

TSD <7:0>

(11/0 <11 :8>

1-----r-----1A15

IAK L )>---+--+--t--+---i
GINT

IRO
BUF

IRO <3:0>

OUT LB)
LDAL2L)>--4-~-+---i

tv
I
00

I---+----II&I/V\,..-- +5 ....

)

LDAL 3 L

V1--

Cs WRT AD CD iAK Gi'NT EO RiP P'AliSE
CSI

TRANSCEIVERS

~A 1/0 <7:0>

IRO
BUF

~~r____
IR_O_<_7_:_0>
____~

GROUP2
INTERRUPT CONTROLLER
CSRC, CSRD LOW BYTE

USER RPLY A
USER RPLY B

I RO 7 ......---~-+--+---'~ A
I RO 6 .....----+-+----1...---1 B

I RO 5 ......-----t--"'---~ C
EO

- 6'
IRO
BUF

IRO 4 ....- - - - - ' - - - - - - 1 0

USER RPLY C
USER RPLY 0

MR 4734

Figure 2-7

Group I and Group 2 Interrupt Controller Interconnections

Each interrupt controller group accepts eight 1RQ inputs through the I RQ buffers. The timing relationship of the signals involved in intergroup priority resolution is shown in Figure 2-8. For purposes
of this discussion, suppose that an active interrupt (I RQ 7) arrives at group l. When IRQ 7 is applied
to group L a group interrupt (G INT) will be generated if the request is not masked or the master mask
bit has not disarmed the interrupt controller. The G INT signal will generate BI RQ 4 L. if the processor
has enabled interrupts. by setting the interrupt enable bit. The processor wiii accept Bi RQ 4 L after
executing the current instruction, issue BIA K L, and disable its internal interrupt structure. When the
processor returns the BIAK L signal, EO of group 1 goes low. PA USE goes low to indicate that a data
bus transfer operation is presently under way. The risi ng edge of PA US E extends the I A K L pulse and
is also ANDed with the RPL Y signal of the I/O control logic to delay the assertion of BRPL Y until
the CUiient data transfer is completed.
After the fall of BIAK L, group I and group 2 wait until a brief internal delay elapses and then
examine EI. If EI is low, internal activity is suspended until EI goes high. If EI is high, the internal
circuitry is checked to see if an unmasked interrupt request is pending. In this example. EI of group I is
always high and EO stays low after the brief internal delay because of IRQ 7. The low EO signal of
group I therefore disables group 2. The group 1 RIP signal is brought low, and PAUSE is brought
high, causing the IAK signal to go high. When the IAK signal goes high, the vector address programmed for IRQ 7 is output through the vector address buffers and transceivers to the LSI-II bus. Note
that the PAUSE output automatically adjusts the position of its rising edge to accommodate the
particular intergroup and intragroup priority resolution conditions that occur for each IAK cycle.
The RIP output serves two basic functions within the interrupt system. First, its falling edge informs
the other interrupt controller that an interrupt request has been selected and PAUSE may therefore be
released. Second, as long as RIP is low, only the interrupt controller ,that is causing RIP to go 10\\' is
allowed to respond to IAK L inputs. RIP stays low until the vector address for the selected interrupt
has been transferred. Suppose that a new interrupt request arrives at IRQ 0 of the group 2 interrupt
controller during the time the vector address of group I is being transferred. Without the RIP signal
there would be confusion when IRQ 0 arrives at the group 2 interrupt controller. The group 2 interrupt
controller treats RIP as an input, and therefore, will not respond to IRQ 0 until RIP goes high.
2.4.3 I nterrupt Controller Operating Description
The block diagram Figure 2-9 shows the registers. interface signals and basic information flow of an
interrupt controller chip. The interrupt controller chips for group I and group 2 are identical and the
following description applies to both. Interrupt requests (IRQ <7:0» are captured and latched in the
interrupt request register ORR). Any requests not masked by the interrupt mask register (11\1 R) will
cause a group interrupt (G INT) output to the processor if the interrupt controller is enabled, armed,
and IE (CSRA) bit 9 is set. \Vhen the processor is ready to accept the interrupt, it issues an IAK L
pulse that initiates two operations. First, the priority of pending interrupts is resolved, and second, the
vector address associated with the highest priority interrupt is transferred from the vector address
memory to the data bus (TSD <7:0».

Other interrupt management functions are controlled by the auto-clear register (ACR), the interrupt
service register (lSR), and the mode register (M R). The command register is used by the processor to
exercise control over the many functions provided by the DR V II-J. while the status register reports on
the internal condition of the DR V II-J.
The interrupt controller is addressed by the processor as either a control port or a data port through
use of the LDAL 2 bit. The control port provides direct access to the command register and the status
register. The data port is used to communicate with all other internal locations.

2-9

GROUP 1 IRQ 7

\------"',

GINT

IAK L

PAUSE

ENABLED
EO GROUP 1
EI GROUP 2

DISABLED

RIP

BRPLY L

NOTE:
EI OF GROUP 1 IS OPEN AND ALWAYS ENABLED.
MFI-47315

Figure 2-8 Intergroup Priority Resolution Timing

2-10

CSl lGROUP 1)
CSO (GROUP 0)

RD EN

OUT LB

LDAL2

,. PAUSE

r------,.---------CS

Ro
WRT

VECTOR
ADDRESS
MEMORY
8 X 32
A/W RAM

BYTE
COUNT
MEMORY
BX2
R/W RAM

BUS
CONTROL

PAUSE

COMMAND]
REGISTER

MODE
REGISTER

STATUS
REGISTER

IISR)
INTERRUPT
SERVICE
REGISTER

IIMR)
INTERRUPT
MASK
REGISTER

BUS
BUFFER
N
I

IAK L
ENABLE IN
ENABLE OUT

iA'i<
EI
EO

(IRR)

INTERfWPT
REQUEST

IRQ 7--:---"0>
~._._ _

INTERRUPT
CONTROL

RESPONSE IN
PROGRESS

RIP

PRIORITY CONTROL LOGIC
GINT

~,.~G-R_O-U-P-I-N-T-E-R-R~U-PT---------.------------------~------MR-4355

Figure 2-9

I nterrupt Controller Block Diagram

Information is transferred through the interrupt controllers, the DRVII-J I/O bus, and the LSI-II bus
hy the eight 3-state bidirectional data bus lines (TSD <7:0». Control signal configurations for all
information transfer operations are described in Table 2-5. The following conventions are assumed:
RD EN and OUT LB are mutually exclusive~ RD EN, OUT LB, and LDAL 2 have no meaning unless
CS I or CSO is low: active IA K L pulses occur only when CS I or CSO is high.
Table 2-5

Summary of Data Bus Transfers

Control Input
TSD <7:0> Data Bus Operation
CSO

CSI

LDAL2

RD E;\l

OllT LB

IAK L

Transfer contents of preselected data register to data bus
(read).

Transfer contents of data bus to preselected data register
(write).

Transfer contents of status register to data bus (read).

Transfer contents of data bus to command register (write).

Transfer contents of selected vector address memory location to data bus (read).

No information transferred.

'OTE:

X = "don't care" condition: LDAL = I = control port: 0 = data port.

The status register is selected directly for reading by the LDA L control input. Other internal registers
are read by preselecting the desired register with mode bits 5 and 6, and then executing a data read. The
vector address memory can be read on Iy with IA K L pulses.
The command register is selected directly for writing by the LDAL 2 control input. The mask and
auto-clear registers are loaded following specific commands to that effect. To load each level (IRQ
<7:0» of the vector address memory. the vector address memory preselect command is issued to
select the desired level. A data-write operation is then executed to load that level.
2.4.4 Interrupt Control Reset
The DR V II-J does not include an external hardware reset input for the interrupt control. The reset
function is accomplished by software command, or automatically during power-up. The processor
may initiate a reset at any time by writing all Os into the command register of each interrupt controller.
Power-up reset circuitry on each interrupt controller integrated circuit is internally triggered by the
rising Vee voltage (IC supply voltage. 5 V) to generate a brief reset pulse when the predetermined
threshold is reached. The interrupt controllers are unaffected by a BIN IT on the LSI-II bus.

The vector address memory and byte count register contents are not affected by a software reset, but
their contents are unpredictable after a power-up reset. Therefore. if the vector address memory and
byte count register are to be used, they must be initialized by the processor after power-up.
The interrupt mask register is set to all Is by either a software reset or a power-up reset. thus disabling
recognition of interrupts by the DRVII-J. The status registers continue to reflect the internal condit;,.....,
..... ",f n- ... ".I....- 1I
LIVII VI e l V U p

"II""' ' ' ,... ... 1""11.11"1"'11. ,

UIIY

el VUp

n ..... .r1

allY

n,"A

a l '"

.... .1""\. ..

IIV~

".....thO ..... I./;t:"'1III2o I"'lffAr"'tOrl ..... '1

V~II"'I

I.:)",

UII"''''~'''U

2-12

V..,

rAC"At

I",.,,,, ••

The mode registers are cleared to all Os to provide the DR V 11-J with a reasonable operating environment after a power-up or software reset. The mode registers after reset are assigned the following
operating options.
Interrupt mode
I ndividual vectoring
Fixed interrupt priority
IRQ polarity active low
ISR preselected for reading
I- nterrunt
controllers
disarmed bv., master mask bit
r
2.4.5 Interrupt Control Register Description
The 0 R V I1-J uses the control and operation registers, plus the vector address memories of the interrupt controllers, to perform and manage its many functions. Table 2-6 lists these elements and summarizes their size and number.
Table 2-6

Interrupt Control Register and Memory Summary

Description

I nterrupt request register
1nterrupt service register
Interrupt mask register
-\uto-clear register
StJtus n:,gister
\1 nde register
Command register
Byte count
Vector address memory

IRR
ISR
IMR

I
I

Bit Size
Per
Register

8
8
8
8
8
8
8
2
8 X 32*

ACR

Quantity
Per
DRVII-J

2
2
2

2
2
2
16
16

*Although each interrupt controller contains 32 vector address memory locations of 8 bits each. the DRVII-J uses only 8 of

2.4.5.1 Status Register - Each status register is eight bits wide and contains information describing
the internal state of the DR V II-J. The s~atus register is read directly by executing a read operation at
CSRA for group 1 or CSRC for group 2. Figure 2-10 shows the status register bit assignments.

The high-order status bit S7 reflects the information state of the group interrupt (G INT) signal. Bit S7
remains valid when interrupts are disabled by the polled mode option, thus permitting the processor to
check for interrupts by reading the status register.
Status bit S6 reflects the state of the enable-in (EI) input signal and indicates if group 2 is enabled or
disabled. When S6 is high, group 2 can generate an interrupt request. When S6 is low. group 2 inter- ·
rupt requests are disabled. Group 1 is always enabled.
Status bit S5 reflects the state of the priority mode option as specified by mode register bit MO. When
S5 is high, rotating prioriiY is seiecied. When S5 is iow, fixed priority is selected.
Status bit S4 reflects the state of the interrupt mode option as specified by mode register bit 2. When S4
is high. the polled mode is selected and interrupt requests are disabled. When S4 is low, the interrupt
mode is selected.
2-13

ENABLE INPUT
o DISABLED
1 ENABLED
(GROUP 2 ON LY)
GROUP INTE R RUPT
1 NO UNMASKED
IRRBITSET
o AT LEAST ONE
UNMASKED IRR
BIT SET

INTERRUPT MODE
o INTERRUPT
1 POLLED

FOR INTERNAL USE ONLY.
MAY READ AS ZEROS OR
ONES.

PRIORITY MODE MASTER MASK BIT
o FIXED
0 DISARMED
1 ROTATING
1 ARMED

MR·4356

Figure 2-10

CSRA and CSRC Status Registers' Bit Assignments

Status bit S3 reflects the state of the master mask bit as specified by mode register bit M7. When S3 is
low, the group is disarmed and IRR bits that are set will not generate interrupt requests. When S3 is
high, the group is armed and interrupts can occur.
Status bits S2, S 1 and SO are for internal use by the DRVll-J. These bits may read as zeros or ones and
should not be correlated with external events or operational states of the module.

2.4.5.2

Command Register - Each command register is eight bits wide and is used to store the most
recently entered command. The register is loaded directly from the data bus by executing a write
operation at CSRA for group I or CSRC for group 2. Depending on the specific command opcode
that is entered, an immediate internal activity may be initiated, or CSRB and CSRD may be preconditioned for subsequent register transfers. The opcodes for each command operation are described
in Paragraph 2.7. (The commands are summarized in Table 2-10.)

2.4.5.3

Mode Register - Each mode register is eight bits wide and is used to establish the operating
modes and conditions for the many functional features of the DRYll-J. The mode register allows the
processor to customize the interrupt system for a particular application. Figure 2-11 shows the mode
register bit assignments. No single command or interface operation will load all bits of the mode
register in parallel. The five low-order bits (MO through M4) are loaded in parallel directly from the
command register. Mode bits M5, M6 and M7 are controlled by separate commands. The mode
register contents cannot be read out on the data bus. However, the conditions of mode bits MO, M2
and M7, which reflect the priority, interrupt and master mask bit modes, are available as part of the
status register. The mode register is cleared by a software reset or a power-up reset.

2.4.5.4 Interrupt Request Register (IRR) - Each IRR is eight bits wide and is used to recognize and
store active transitions on the ei~ht interrupt request lines. A bit in the IRR is set whenever the
corresponding IRQ input line ma-kes an inactive-t'o-active transition and meets the minimum active

2-14

pulse width requirements. Also, the processor (under program control) may set the I R R bits by using
two types of commands. This capability permits software-initiated interrupts and is a useful tool for
system testing.
All IRR bits are cleared by a reset. IndividuallRR bits are cleared automatically when their interrupts
are acknowledged by the processor. Four types of commands, in addition to reset, allow the processor
to clear I R R bits.
The IRR may be read onto the data bus by preselecting it in mode register bits M5 and M6 with a load
mode register command, followed by a read ofCRSB <7:0> for group 1 or CSRD <7:0> for group 2.

REGISTER
PRESE LECTION
00 INTERRUPT
SERVICE
REGISTER
01 INTERRUPT
MASK
REr,ISTER
10 INTERRUPT
REQUEST
REGISTER
11 AUTO CLEAR
REGISTER

MASTER MASK BIT
o DISARMED
1 ARMED

PRIORITY MO DE
o FIXED
1 ROTATIN G

UNUSED
MUST BE 0
INTERRUPT MODE
o INTERRUPT
1 POLLED

VECTOR SELECTION
INDIVIDUAL
VECTOR
1 COMMON VECTOR

I REQ POLARITY
ACTIVE LOW
ACTIVE HIGH

MR-4357

Figure 2-11

Mode Register Bit Assignments

2.4.5.5 Interrupt Service Register (ISR) - Each ISR is eight bits wide and is used to store the acknowledge status of individual interrupts. When the processor acknowledges an interrupt request, the
DRVll-J selects the highest priority request that is pending, clears the associated IRR bit, and sets the
associated ISR bit. When the ISR bit is programmed for automatic clearing, it is reset by the internal
hardware before the end of the acknowledge sequence. When the ISR bit is not programmed for
automatic clearing, it must be reset by command from the processor.
The DR V 11-J uses the ISR internally to erect a "masking fence:' When an ISR bit is set and fixed
priority mode is selected. only requests of higher priority will cause a new group interrupt (G INT)
output. Thus, requests from lower priority interrupts (and from new requests associated with the set
ISR bit) win be "fenced out" and ignored until the ISR bit is cleared. In the rotating priority mode. all
requests are fenced out by an ISR bit that is set and no new interrupts will be generated until the ISR
bit is cleared. When automatic clearing is specified, no masking fence is erected since the ISR bit is
cleared.

2-15

If an unmasked interrupt arrives from a device of higher priority than the current ISR, the processor
will be interrupted if its interrupt input is enabled. When the new interrupt is acknowledged, the
associated higher priority ISR bit is set and the fence moves up to the new priority level. When the new
ISR bit is cleared. the fence will then fall back to the previous ISR level. The ISR may be read onto the
data bus by preselecting· it in mode register bits M5 and M6 with a load mode register command,
followed by a read of CSRB <7:0> for group 1 or CSRD <7:0> for group 2.
Interrupt Mask Register (lMR) - Each 1M R is eight bits wide and is used to enable/disable
the processing of individual interrupts. Only unmasked IRR bits can generate an interrupt. The IMR
does not otherwise affect the operation of the IRR. An IRR bit that is set while masked will cause an
interrupt when its 1M R bit is cleared.

2.4.5.6

All eight IMR bits for each group may be set, cleared, read or loaded in parallel by the processor. In
addition, individual 1M R bits may be set or cleared by command. This allows a control routine to
enable or disable directly an individual interrupt without disturbing the other mask bits and without
knowledge of their state or context.
The 1M R polarity is active high for masking~ a 0 enables the interrupt and a I disables it. The poweron reset and the software reset cause all IMR bits to be set, thus disabling all interrupt requests. The
1M R may be read onto the data bus by preselecting it in mode register bits M5 and M6 with a load
mode register command. followed by a read ofCSRB <7:0> for group I or CSRD <7:0> for group 2.
2.4.5.7 Auto-Clear Register (ACR) - Each ACR is eight bits wide and specifies the automatic clearing
option for each of the ISR bits. When an auto-clear bit is set, the corresponding ISR bit set in an
interrupt acknowledge (lAK) cycle is cleared by the internal hardware before the end of the IAK
sequence. When an auto-clear bit is not set, the corresponding ISR bit that has been set in an IAK
cycle is cleared by a command from the processor.

\Vhen selected, the auto-clear option provides two related functional effects. First. it eliminates the
need for the associated interrupt service routine to issue a command to clear the ISR bit. Second, it
eliminates the masking fence that would otherwise have been erected, allowing lower priority interrupts to cause a new interrupt request.
The ACR is loaded in parallel from the data bus by issuing the ACR load preselect command. followed by a write into the data port. The ACR is read onto the data bus by preselecting it in mode
register bits M5 and M6 with a load m.ode register command, followed by a read of CRSB <7:0> for
group 1 or CSRD <7:0> for group 2.
2.4.5.8 Vector Address Memory - The vector addresses are programmed by the vector address memory preselect command, followed by a data-write operation to load the vector address required for
each interrupt request level. The vector address memory preselect command is entered directly into the
low byte <7:0> of CSRA for group 1 or the low byte <7:0> of CSRC for group 2. Preselect commands entered through CSRA select CSRB for subsequent loading of the vector addresses in group I.
Preselect commands entered through CSRC select CSRD to load the addresses for group 2.
N ormaily, one vector address is loaded after each preselection command. (Figure 2-12 shows the
vector bit positions relative to the loaded byte.) This in turn causes one interrupt to occur for each
valid transition on the corresponding I RQ input. Vector addresses are placed on the LSI-II bus during
IA K operation.

Loading the vector address into each new interrupt request level must be preceded by a new vector
address memory preselect command. Therefore. 16 preselect commands. each followed by a data-write
operation. are required to load 16 vector addresses into the vector address memory.
2-16

Note that while the DRVlI-J only uses one vector address per interrupt, the interrupt controller chips
are capable of handling four vector addresses per interrupt level. To ensure proper operation, the user
must always use a byte count of one (BYO = 0, BY 1 = 0) and load oniy one data byte after each
preselect command.
15

I
I

CSRB (GROUP 1)
OR
CSRO (GROUP 2)
MR4309

Figure 2-12

DRVII-J Vector Address Format

2.5 OPERATING OPTIONS
The mode register bits are program-controlled to establish the combination of interrupt operating
options desired for a particular DRV II-J system application. Refer to Figure 2-11 for the mode register bit assignments. A detailed description of the various options available follows. The master mask
bit will affect both group 1 and group 2; all other mode bits affect only their corresponding groups.
2.5.1 Interrupt Priority Mode Selection
\fode register bit MO specifies either a fixed or rotating priority resolution mode for the DR V II-J.
When MO is low, fixed priority is selected and the eight IRQ inputs for both group I and group 2 are
assigned a priority based on their physical location at the interface. Group 1 IRQ 0 has the highest
priority and group 2 IRQ 7 has the lowest. Table 2-7 lists the priorities assigned to the A I/O < 15:0>
lines and the USER RPL Y lines.
Table 2-7
i

Fixed Priority Mode

Group

Connection

Level

IRR, ISR, IMR, ACR
Bit Assignments

1
1
1
1
1

A 1/00
A I/O 1
A I/O 2
A I/O 3
A 1/04
A I/O 5

0
1
2
3
4
5

DO
01
02
03
04
05

A 1/06

A 1/07

2
2
2
2
2
2

A 1/08
A 1/09
A I/O 10
A I/O 11
USER RPLY A
USER RPLY B
USER RPLYC
USER RPLY0

0
1
2
3
4-

DO
01
02
03
04
05
06
07

2
2

567*

Highest

>-CSRB

"""
>-CSRO
I

II
)

-Jumper (WIl) selects either USER RPLY (A:D) or A I/O <15:12> signals.

2-17

Priority

Lowest

Interrupt acknowledge operations are initiated by the processor in response to a group interrupt
(GINT) output by the interrupt controllers.
Interrupt priority is resolved after the processor initiates the interrupt acknowledge sequence. When
the DR V I1-J receives an IA K signal, the interrupt controllers perform priority arbitration to select the
highest unmasked pending interrupt, and then output a vector address associated with the selected
interrupt request. In the fixed priority mode, therefore, devices with a high priority may be serviced
many times before a lower priority device is serviced once. In many systems, this is an appropriate
method of servicing the interrupting devices. In those systems where this is not an appropriate method,
the. interrupt masking capability of the DRVII-J may be used to modify the effective priority structure. This may be accomplished by masking out recently serviced high priority devices, thus permitting
recognition of lower priority inputs.
Alternatively, the rotating priority mode may be selected for use in systems where the eight interrupts
of each group have similar priority and bandwidth requirements. Mode register bit MO = 1 selects the
rotating priority mode. As shown in Figure 2-13, the relative priorities remain the same as in the fixed
mode. I n the rotating priority mode, however, the lowest priority position in the circular chain is
assigned by the hardware to the most recently serviced interrupt. Priority rotation occurs only within a
given group and priority between group 1 and group 2 remains fixed, with group I having the higher
priority.

HIGHEST
PRIORITY

(NEW HIGHEST PRIORITY)

(LAST INTERRUPT SERVICED)

Figure 2-13

Rotating Priority Mode

The example shown in Figure 2-13 assumes IRQ 5 has been serviced and is assigned the lowest priority
(7). IRQ 6 now occupies the new highest priority position, IRQ 7 next to the highest. etc. If two new
interrupts simultaneously arrive at IRQ I and IRQ 4, IRQ I is selected and becomes the lowest
priority. IRQ 4 will then be acknowledged unless an active input of IRQ 2 or IRQ 3 arrives in the
meantime.

2-18

This rotating scheme prevents anyone interrupt request from dominating the system. An interrupt
request will not have to wait for more than seven more service cycles before being acknowledged.
Priority is resolved when the ISR bit of the presently selected interrupt is cleared.
in the rotating priority mode. jnputs other than the one currently serviced are fenced out and will not
cause interrupts until the ISR bit is cleared. Thus, only one bit at a time is set in the ISR. Use care
when selecting the rotating mode to keep from doing so again when -more than one ISR is set.
2.5.2 Individual Vector or Common Vector Mode
Bit M! of the mode register specifies the vectoring option. When M 1 = 0, the individual vector mode is
selected and each interrupt request line is associated with its own location in the vector address memory. Each location contains the vector address that was loaded by the program after system power-up.
When M I = I, the common vector mode is selected and all vector information is supplied from the
vector address memory location associated with interrupt request line 0 (I RQ 0), regardless of which
interrupt request line is acknowledged. The common vector mode is useful in systems where several
similar devices share a common service routine and direct individual device identification is not important. This may be true because of the nature of the peripheral-system interaction or in the case of a
transient system condition that uses the common vector temporarily to save the additional programming overhead required to load the vector address memory twice per group.
2.5.3 Interrupt or Polled (Flag) Mode
Bit 2 of the mode register allows the system to enable or disable interrupt requests. When M2 = 0, the
interrupt mode is selected and interrupts are enabled. The interrupt mode may be considered the
"normal" mode because it permits full use of the interrupt control and management capabilities of the

DRY! I-J.
When M2 = I, the polled mode is selected, which forces the group interrupt (GINT) output of the
interrupt controllers to the inactive state and thus prevents the DRVII-J from issuing a bus interrupt
request (BIRQ 4 L). Since no bus interrupt requests are supplied, the processor cannot initiate the
interrupt acknowledge sequence. Consequently, ISR bits are not set, masking fences are not erected,
and IRR bits are not automatically cleared. Polled-mode operation requires the processor to read the
status register to determine if requests are pending. Software routines must then be used to determine
which input iine requested the interrupt. IRR bits may be cieared by the software. The polled mode of
operation effectively bypasses the hardware interrupt, vectoring, and fencing functions of the DRVIIJ. What remains is the interrupt request latching and masking functions.
2.5.4 !\'lode Register Bit 3
Bit 3 of the mode register is not used and must be programmed to a O.
2.5.5 IRQ Polarity Option
Bit 4 of the mode register specifies the polarity of interrupt request inputs to which the DRY II-J will
respond. When M4 = 0, the interrupt request inputs are selected as active low and a negative-going
transition is required to set the associated IRR bits. When M4 = 1, the interrupt request inputs are
selected as active high and a positive-going transition is required to set the associated I RR bits. This
polarity option may be used to simplify the design of the DRY I1-J interface to the interruptIng
devices.

2.5.6

Bits 5 and 6 of the mode register specify the internal data register contents that will be output by the
DR V II-J during a read operation at the data port. These bits do not affect destinations for write
operations. The four registers that may be read are the IRR, ISR, IMR and AeR. Preselect coding for
each register is shown in Figure 2-11. The preselection remains in effect for all data transfers until the
contents of M 5 and M6 are changed.

2-19

The ability to examine these operating registers in conjunction with the status register contents provides important information regarding the current internal conditions of the DR V II-J. The processor's access to these registers permits dynamic operating flexibility and provides important diagnostic.
testing. and debugging information.

2.5.7

Master Mask Option

Bit 7 of the mode register specifies the armed status of the DR V II-J by' way of the master mask control
bit. When M7 = 0, the group is disarmed as if all eight bits in the 1M R had been set. I RQ inputs will be
accepted and latched but will not be sent to the processor. When M7 = I, the group is armed and any
active unmasked interrupt inputs may cause interrupt requests to the processor.
The master mask option permits the system to disarm a group and prevent the processing of interrupts
without disturbing the contents of the I MR. Thus, when the group is re-armed, the old 1M R conditions are stil1 valid and need not be reloaded. Note that a single command to the master mask bit of the
highest priority interrupt group shuts down the entire interrupt system. This is the only mode bit that
affects both groups.

2.6

SYSTEM OPERATING SEQUENCE

The management of interrupts by the DRV II-J requires interaction between the processor, the
DR V II-J, and the user device. The operations performed by the system are described in the following
typical sequence of events. The DR V II-J is initialized, enabled, and ready to run in the interrupt
mode. The processor has enabled its internal interrupt structure to accept DR V II-J interrupt requests.
l.

One (or more) of the IRQ inputs becomes active, indicating that service is desired.

The requests are captured and latched in the IRR asynchronously. The latching action of the
I R R cannot be disabled and active requests will always be stored un less a previous request at
the same IRR bit has not been cleared.

If the active IRR bit is masked by the corresponding bit in the IMR, no further action takes
place. When the IRR bit is not masked, an interrupt request will be generated.

When the processor recognizes an interrupt request, it will complete the execution of its
current instruction and then execute an interrupt acknowledge cycle.

When BIAKI L is received, the DRVII-J begins selection of the highest priority unmasked
IRR bit. All interrupts that have become active before the falling edge of BIAK are considered. When selection is complete, the contents of the vector address memory location associ·
ated with the selected request are accessed.

The processor accepts the vector address on the LSI-II bus and negates IAK.

In parallel with the transfer of the vector address, the DRV II-J automatically clears the
selected I R R bit and sets the selected ISR bit. I f the auto-clear function is not in force for the
selected interrupt. the ISR bit will cause the erection of a masking fence, and interrupts will
be disabled until a higher priority interrupt arrives or until the ISR bit is cieared. The
interrupt service routine must clear the ISR bit near the end of the routine if the auto-clear
function is not used.

If a higher priority request arrives while the current request is being serviced, and if the fixed
priority mode is in effect, the DRVII-J will output another interrupt request (nested interrupt). The processor will recognize the interrupt signal only if it has enabled its internal
interrupt logic. If this new request is acknowledged. the DRV II-J will clear the corresponding i R R bit and set the corresponding ISR bit.

2-20

When the processor has completed all service associated with the interrupt, it will clear the
remaining ISR bit (if the auto-clear capability is not used), enable its internal interrupt
system (if it has not already done so), and return to the main ·program.

2.7 COMMAND DESCRIPTIONS
The DR V I1-J command set allows the processor to customize the interrupt operating modes and
options for a particular application. Commands are also used to initialize and update the vector address memory iocations and to manipulate the internal controlling bits set during interrupt servicing.
Commands are entered directly into the command register by writing into the low byte of CSRA for
group I or CSRC for group 2. Preselection commands entered through CSRA select CSRB for subsequent group I register transfers. Preselection commands entered through CSRC select CSRD for
subsequent group 2 register transfers. All the available commands are described below and are summarized in Table 2-10. An ··X" in any bit position of the command code indicates a "don't care" condition. Any commands that alter the state of the IMR, IRR or master mask bit should be executed with
the processor status word at a priority level equal to the DRY I1-J to prevent undefined interrupts
from occurring.

2.7.1

Reset

I ~7 I ~6 I ~5 I ~4 I ~3 I ~2 I ~I I ~o I
The reset command allows the processor to estabiish a known internal condition. The vector address
memory and byte count registers are not affected by the software reset. The 1M R is set to all 1s. The
ISR, IRR, ACR and mode registers are cleared to all Os.
2.7.2

Clear IRR and IMR

I ~7 I ~6 I ~5 I
I

All bits in the IMR and IRR are cleared at the same time. Thus, all interrupts pre enabled and the
previous history of all IRQ transitions is forgotten. If the interrupt request was active when the command was entered, it becomes inactive.
2.7.3

Clear Single IMR and IRR Bit

I ~7 I ~6 I ~5 I ~4 I

C2
B2

Cl
Bl

co
BO

The same single bit is cleared in both the IMR and IRR. Other bits are not changed. If the specified
I R R bit is generating an active interrupt output. the interrupt request may become inactive upon entry
of the command. The bit position cleared is specified by the 82, B I, 80 field as shown in Table 2-9.
2.7.4

Clear IMR

I ~7 I ~6 I

C5 I

~4 I ~3 I ~2 I ~I I ~o I

All bits in the IMR are cleared. All IRR bits will therefore be unmasked and any IRR bits that were set
will be able to cause an active interrupt request after the command is entered.
2-21

2.7.5

Clear Single IMR Bit

I ~7 I ~6 I I ~4 I ~3 I ~~ I ~: I ~~ I
C5

A single bit in the 1M R is cleared. Other bits are not changed. If the corresponding bit in the IRR is
set. it will be unmasked and will be able to cause an active interrupt request after entry of the command. The 1M R bit cleared is specified by the B2, B I; BO field as shown in Table 2-9.

I I ~3 I ~2 I ~ I ~o
I

All bits in the IMR are set to I. All IRR bits will therefore be masked and unable to generate an
interrupt request. If the interrupt request is active, it will become inactive after the command is entered.

2.7.7

Set Single Il\tR Bit

I ~7 I ~6 I I I ~3 I ~~ I ~: I ~~ I
C5

A single bit in the IMR is set. Other bits are not changed. If the corresponding bit in the IRR is active
and generating an interrupt, the interrupt request will become inactive after the command is entered.
The 1M R bit set is specified by the B2, B I, BO field as shown in Table 2-9.

2.7.8

Clear IRR

I ~71 I ~5 I ~4 I ~3 I ~2 I ~l I ~o
C6

All bits in the IRR are cleared. The interrupt request will become inactive. New transitions on the IRQ
inputs will be necessary to cause an interrupt.

2.7.9

Clear Single IRR Bit

I ~71

I ~5 I ~4 I I ~~ I ~: I ~~
C3

A single bit in the IRR is c1eared~ it will not cause an interrupt until it is set. The IRR bit cleared is
specified by the B2, B1, 80 field as shown in Table 2-9.

2.7.10

Set IRR

I ~7 I ~6 I ~5 I I ~3 I ~2 I ~l I ~O
C4

All bits in the IRR are set to I. Any that are unmasked will be able to cause an interrupt request. This
command allows the processor to initiate eight interrupts in parallel.

2-22

C4
I

A single bit in the IRR is set to 1; if unmasked, it will be able to generate an interrupt request. This
command allows the processor to simulate with software the arrival of a hardware interrupt request. It
also gives the software access to the hardware priority resolution, masking, and control features of the
DR V 11-1. The bit set is specified by the 82, 81, 80 field as shown in Table 2-9.

2.7.12

Clear Highest Priority ISR Bit

I ~7 I ~6 I I ~4 I ~3 I ~2 I ~I I ~o
C5

A single bit in the ISR is cleared. If only one bit was set, the set bit is cleared. If more than one bit was
set, this command clears the bit with the highest priority. This command is useful in software contexts
where the service routine does not know which device is being serviced. It should be used with caution
since the highest priority ISR bit may not really be the bit intended. When using the auto-clear option
on some interrupts, and/or when a subroutine nesting hierarchy is not priority-driven. the highest
priority ISR bit may not correspond to the bit being serviced.
2.7.13

Clear ISR

I ~7 I I I I ~3 I ~2 I ~I I ~o
C6

All bits in the ISR are cleared. Mask fencing is eliminated.
2.7.14

Clear Single ISR Bit

I ~7 I ~6 I ~5 I
I -

I -

C2
82

CI
Bl

co
BO

A single bit in the ISR is cleared. If the bit was already cleared, no effective operation takes place. The
bit cleared is specified by the 82, BI, 80 field as shown in Table 2-9. This command is most useful to
service routines in managing the ISR without the help of the auto-clear option.
2.7.15

Load Mode Bits MO through M4

I ~7 ~6 I ~5 I ~: I ~3
I

The five low-order bits of the command register are transferred into the five low-order bits of the mode
register. This command controls all of the mode options except the master mask and the register
preselection.
2.7.16

Control Mode Bits MS, M6 and M7

I ~7 I ~6 I

~4
2-23

The M6. M5 field in the command is loaded into the M6, M5 locations in the mode register. This field
controls the register preselection bits in the mode register. The N). NO field in the command controls
mode bit M7 (master mask) and is decoded as follows.

o
1
o

o
1
1

No change to M7
Set M7
Clear M7
( Illegal)

)

Thus. this command may be considered as three distinct commands, depending on the coding of N 1
and NO.
I.

2.
3.

Load M5. M6 only
Load M5. M6, and set M7
Load M5. M6, and clear M7

The command summary in Table 2-10 lists these three versions.
2.7.17

Preselect IMR for Writing

I I ~6 I I
C7

The 1M R is targeted for loading from the data bus when the next write operation occurs at the data
port. All subsequent data-write operations will also load the 1M R until a different command is entered. Read operations may be successfully inserted between the entry of this command and the subsequent writing of data into the 1M R. The mode register is not affected by this command.
2.7.18

Preselect ACR for Writing

I ~7 I ~6 I ~5 I ~4
The ACR is targeted for loading from the data bus when the next write operation occurs at the data
port. All subsequent data-write operations will also load the ACR until a different command is entered. Read operations may be successfully inserted between the entry of this command and the subsequent writing of data into the ACR. The mode register is not affected by this command .
. 2.7.19

Preselect Vector Address Memory for Writing

C5
1

C4
BYl

C3
BYO

C2
L2

Cl
Ll

CO
LO

One level in the vector address memory is targeted for loading from the data bus by subsequent datawrite operations. The byte count register for that level is loaded from the BY I, BYO field in the
command. The L2. L I. LO field specifies which of the eight request levels is being selected. Table 2-8
describes the byte count register field and IRQ-level field coding. This command should be followed by
one data-write operation at CSRB group I or CSRD group 2 to load the desired vector address. See
Figure 2-12 for vector address bit assignments, The byte count should be I since the LSI-J' requires
only one vector for an interrupt.
2-24

Table 2-8

Vector Address Memory Field Coding

IRQ Le,eI

Byte Count Register
BYI

BYO

0
0

I
"

Count

II 21
I 43
I

0
0
0
0

Level

0
1

2
3

0
0

6
7

The byte count value does not control the number of bytes written into the vector address memory.
However, it does control the number of bytes read from the memory by IAK sequences and the
num ber of interrupts generated by the selected request level. Vector address locations are output by the
DR V 11-1 in the same order they were entered. The number of addresses written must equal the byte
count: otherwise, erroneous data may remain in the memory and cause an invalid address to be output
as a vector.
2.7.20

Coding B2, BI, BO Field Commands

Table 2-9 describes the coding of the B2, B 1, BO field of the command register that is used to set or
clear a specified bit in the IRR, IMR or ISR. Refer to Table 2-10 for a summary of the B2, BI. BO field
coding.

Table 2-9

Command Register B2, B I. BO Field Coding

Command Register Field
B2

Bit
Specified

0
0
0

0
0

1
i

0
i

I
2
3

I
I
I
I

0
0

I
I

6
7

2-25

Table 2-10
Command Code

DRVII-J Command Code Summary
Command Description

Reset.

Clear all IRR and IMR bits.

Clear the IRR and IMR bits specified by the B2. BI. BO field.

Clear alllMR bits.

Clear the IMR bit specified by the B2. Bl. BO field.

Set all 1M R bits.

Set the IMR bit specified by the B2. B I. BO field.

Clear alllRR bits.

Clear the IRR bit specified by the B2. B I. BO field.

Set alii R R bits.

Set the IRR bit specified by the B2, BI. 80 field.

Clear the highest priority ISR bit.

Clear all ISR bits.

Clear the ISR bit specified by the B2. B I. BO field.

0
0

Load mode register bits 00:04 with the specified pattern.

Load mode register bits 5 and 6 with the specified pattern.

Load mode register bits 5 and 6 and clear mode bit 7

Preselect the IMR for subsequent writing through CSRB or CSRD.

Preselect the ACR for subsequent writing through CSRB or CSRD.

BYI BYO L2

Load BY 1 and BYO into the byte count register and preselect the vector
address memory request level specified by the L2. L I. LO field for subsequent writing through CSRB or CSRD.

0
0

NOTE:

Load mode register bits 5 and 6 and set mode bit 7.

X = "don't care" condition.

2-26

CHAPTER 3
CONFIGURA TION
3.1 GENERAL DESCRIPTION
This chapter describes how users may configure the DRVII~J module to function with their systems.
Eleven wire-wrap jumpers or jumper clips may be installed or removed in various combinations to
select the desired configuration. Nine of the jumpers (W I through W9) are used to select the device
starting address. Jumper WI 0 is reserved for future use. Jumper W 11 is used to select the combination
of high-byte port A signals used to generate the interrupt requests. The location of these jumpers is
shown in Figure 3-1.
3.2 FACTORY CONFIGURATION
Users may reconfigure any of the jumpers (except W10) so that the module will function in their
particular systems. The factory configuration as shipped is described in Table 3-1 to help users determine the jumper changes required. Table 3-2 lists the jumpers and describes their functions.
3.3 DEVICE ADDRESSES
The DR V II-J contains eight device registers that can be individually addressed by the computer program. The eight device registers are divided into four controijstatus registers (CSRA, CSRB, CSRC
and CSRD) and four data buffer registers (DRBA, DRBB, DRBC and DRBD). Each of the I/O ports
(A, B, C and D) is accessed by a control/status register and a data buffer register associated with that
port. Table 3-3 lists the eight addressable device registers.
The DRVII-J jumper arrangement provides the capability to configure any address from 7600008 to
7776008. But the only addresses that may be used must fall within the block of addresses that are
assigned to the area of the address map reserved for users. This area is the range of addresses from
7640008 to 7677768.
Three standard device addresses have been assigned for use with DR V II-Js: 764160, 764140 and
764120. The module is configured at the factory for an address of 764160. I f two additional modules
are used in a system, the second DRVt 1-J would normalfy be configured for 764t40 and the third for
764120.

If the system application requires more than three DR V II-Js, addresses for the additional modules
must be selected from the user-reserved area of the address map and assigned in descending order in a
modulus of 20 (octal). When selecting addresses other than the three standard addresses, refer to the
current issue of the Microcomputer Interfaces Handbook to avoid possible I/O device address conflicts.

3-1

Wll

E9J4c:::J

eJ3c:::::J
Wl0

Figure J-l

DR\ ll-J J u m pc r L. ocalions
. !!

•

3-2

Table 3-1

Jumper

Jumper
State-

W2
W3

DRVII-J Factory Jumper Configuration

Function Implemented

This arrangement of jumpers WI through W9 assigns the device address 7641608 to the first of
eight addressable bus registers. With a starting address of 7641608 . the remaining bus registers are automatically assigned the following contiguous addresses.
CSRA
DBRA
CSRB
DBRB
CSRC

DBRC
CSRD
DBRD

764160
764162
764164
764166
764170
764172
764174
764176

W7
W8
W9
WIO

Reserved for future use.

WII

DRV II-J monitors group 2 vectored interrupts using port A I/O bits < 11:08> and USER
RPL Y (A through D) signals (default configuration).

• R = removed = O.
I = installed = I.

3-3

Table 3-2

DRVII-J Jumper Functions

Jumper

Function

Description

AI2

All

AIO

Jumpers W I through W9 correspond to address bits A 12 through A4, respectively. The
jumpers implement an octal base device address in the 760000 through 777760 range. A
jumper installed connects the address bit to ground and permits a match with the corresponding BDAL L = I (low) bit. Removing a jumper permits an address bit match with
the corresponding BDAL L = 0 (high) bit.

W 10
WII

Reserved for future use.
Group 2
vectored
interrupts

W II selects the port A high-byte (group 2) signals to be used for generating vectored
interrupts. When W II is installed (factory configuration), port A I/O bits < II :08> and
the USER RPL Y (A through D) signals are used for generating vectored interrupts.
Connecting W II to J4 permits the port A 1;0 bits < 15:08> to cause interrupts and
disables the USER R PL Y (A through D) interrupt inputs.

Table 3-3 DRVII-J Registers

Address (octal)·

CSRA
DBRA
CSRB
DBRB
CSRC
DBRC
CSRD
DBRD

Control status register A
Data buffer register A
Control status register B
Data buffer register B
Control status register C
Data buffer register C
Control status register 0
Data buffer register 0

7XXXXO
7XXXX2
7XXXX4
7XXXX6
7XXXIO
7XXXl2

7XXXi4
7XXX16

·XXXX is jumper-selectable between 6000 8 and 77768 to configure the
module for a group of addresses in a moduius of 20 (octai); factory set to
6416 8 (CSRA = 7641608. DBRD = 7641768).

3-4

3.4 DEVICE ADDRESS JUMPERS
Nine address jumpers (WI through W9) are installed or removed to establish a base device register
address. Figure 3-2 shows the format of a DRY II-J device address. Note that address bits A 13
through A 15 are neither configured nor decoded by the module. These bits are decoded by the bus
master module as the bank 7 select (BBS 7 L) bus signal. Address bit a is used by the program to select
a high-byte or low-byte operation. Address bits 1 through 3 are used t.o select one of the eight device
registers in the addressed module.
3.5 INTERRUPT VECTOR ADDRESSES
The DR Vii -j may be programmed to operate in systems that are either interrupt-driven or softwarepolled. If the DRYII-J is used in an interrupt-driven system, the interrupt vector addresses must be
programmed into a RAM (vector address memory) contained in the two interrupt controller chips E2
and E 10.

A total of 16 vector addresses may be stored in the vector address memory. Although the vector
address bits 07: DO (see Figure 2-12) provide the capability to program addresses in the 0000 through
1774 (octal) range, the vector addresses actually assigned must conform to the floating vector conventions established for the LSI-II bus. The floating vector convention used for communications devices
(and other devices that interface with the PDP-II series of products) assigns vectors in order, starting
at 300 and ending at 776 (octal). To avoid device conflicts, refer to the current issue of the .Wicrocomputer Interfaces Handbook when assigning vector addresses.

A15

A14

13
A13
I

A12

Al1

10
Al0

07
A7

A4
I

A1
I

'---v------'

BBS7 L = 1 (L)

ADDRESS JUMPERS

BYTE
SELECT
1 = HI BYTE

0= LO BYTE
INSTALLED = ALLOWS MATCH TO OCCUR WITH A 1 (LOW) ON THE CORRESPONDING BUS LINE.
REMOVED = ALLOWS MATCH TO OCCUR WITH A 0 (HIGH) ON THE CORRESPONDING BUS LINE.
MR-4308

Figure 3-2

DR-V 11-J Device Address Format

3-5

CHAPTER 4
INTERFACING
4.1

I:\TERFACE CO~~ECTORS

Tv. 0 hoard-mounted 50-pin male connectors (J 1 and J2) interface the DR V II-J to the user device.
Con nector J I is used to interface the port A and port B signals, wh ile J2 is used for the port C and port
D signals. Figure 4-1 shows the location of the J2 connector and the pin numbering scheme. The
numhering of pins on connector JI (not shown) is similar to that on J2. The interface signal names and
their respective connector pins are described in Table 4-1.
4.2 I~PlTT /OCTPUT SIGNAL FUNCTIONS
Programmed input/output data transfers between the ORVII-J and the user device may be accomrlished by the assertion of four control signals associated with each DRY II-J port. The control signals
must he asserted in a handshaking sequence (protocol) to synchronize the DR V II-J and the user
device. thus ensuring that no data is lost. The simplified schematic Figure 4-2 shows the relation of the
I 0 signals to the internal interface logic. Table 4-2 lists the I/O signals and describes their functions.
4.3 I~PLT/OLTPLT SIGNAL ASSERTION LEVELS
The DR V II-J I/O signal assertion levels at the J 1 and J2 connectors are defined separately for the I/O
hus signals. protocol signals and USER RPL Y signals. All I/O bus signals (I/O < 15:0» are defined
as heing asserted ( 1) high (+ 3 V) and negated (0) low (ground). W ri te data is output by the DRY I1-J
to the 1,0 bus through latched drivers, while input data is received through unlatched Schmitt trigger
hufTers.
CAUTION
In order for group 1 IRR bits <7:0> and group 2
!RR bits <3:0> to be valid, the A I/O < 11 :0> lines
must be connected to the user device and have active
signals present. If the A I/O < 11 :0> lines are open,
the I R R bits must be masked in the corresponding
1M R register.

The protocol signals (DRYllJ ROY, ORVllJ RPLY and USER ROY) are defined as being asserted
(I) low (ground) and negated (0) high (+ 3 V). Active transition of the USER RPL Y signals is defined
hy seHing mode register bit Nt4 in the group 2 interrupt controiler when the \V i i jumper is instaiied.

4-1

MA-4311

Figure 4-1

DR V 11-J I/O Connector Pin Locations

Table 4-1

I/O Connector Pin Assignments

Jl
Signal Name

Connector
Pin

Signal Name

J2
Connector
Pin

DRVllJ RDY A
DRVIIJ RPLY A
USER RDY A
USER RPLY A
A LO IS

JI-29
J 1-33
J 1-31
JI-27
J 1-45

DRVIIJ RDY 0
DRVIIJ RPL Y D
USER ROY 0
USER RPLY 0
D I/O 15

J2-29
12-33
J2-31
J2-27
J2-45

A I/O 14
A 110 13
A I/O 12
A I/O 11
A I/O 10

JI-46
J 1-43
JI-49
JI-48
JI-44

01/014
D I/O 13
D I/O 12
01/0 11
D I/O \0

J2-46
12-43
12-49
J2-48
J2-44

A 1/09
A 1/08
A 1/07
A 1/06
A 1/05

J I-50
J 1-47
J 1-41
J 1-36
JI-42

01/09
D 1/08
D 1/07
D 1/06
01/05

12-50
J2-47
J2-41
J2-36
12-42

A 1/04
A I/O 3
A 1/02
A I/O l
A 1/00

J 1-35
JI-4O
J 1-38
Jl·39
J 1-37

01/04
D 1/03
01/02
o ~/O I
01/00

J2-35
12-40
12-38
12-39
J2-37

GND
GNO
GND
GNO
GND

J 1-26
J 1-28
j i-30
J 1-32
J 1-34

GNO
GNO
GND
GNO
GNO

J2-26
J2-28
J2-30
J2-32
J2-34

4-2

Table 4-1

I/O Connector Pin Assignments (Cont)

Signal Name

J2
Connector
Pin

DRVIIJ ROY C
DRVIIJ RPLY C
USER ROY C
USER RPLY C

J2-20
J2-24
J2-22
J2-18

C I/O 15

12-6

C I/O 14
C I/O 13
C I/O 12
C I/O 1\
C I/O 10

J2-5
12-8
J2-2
J2-3
J2-7

C 1/09
C 1/08
C 1/07
C 1/06
C I/O 5

J2-\
J2-4
12-\0
J2- i 5
J2-9

11-12
11-14

C 1/04
C I/O 3
C I/O 2
C i/O i
C liOO

J2-16
12-11
J2-13
n- i 2

JI-\7
J 1-\9
J 1-21
J \-23
J 1-25

GND
GND
GND
GND
GND

J2-17
J2-19
J2-21
12-23
J2-25

Signal "lame

JI
Connector
Pin

DRVIIJ ROY B
DRVIIJRPLYB
USER ROY B
USER RPLY B

J 1-20
J 1-24
11-22
JI-18

B I/O 15

JI-6

B 1,'014
B 1'013
B I/O 12
B I/O II
B I/O 10

JI-5
J 1-8
JI-2
J\-3
JI-7

B 1/09
B I/O 8
B I/O 7
B 1/06
B I/O 5

J 1-\
J 1-4
J 1-\0
JI-\5
1 \-9

B 1/04
B I/O 3
B 1/02
B i/O 1
BIiOO

J 1-16
11-\ I

GND
GND
GND
G:"-lD
G:"-lD

[ I
I I

JI-13

II
II
! ,

II
"I

II
11

IIi!

4-3

J2-14

Jl AND J2

9519

74 LS244

EIO IRO <7:0> t--....---c

A 1/0<11:0>

E2 IRO <3:0>
74 LS244

(X) I/O <15:0>

WRITE (X)
DIR
74S241
XRPL Y (X)

DRV11-J RPL Y (X)

DIR
READ (X)
NOTE:
(X) = A, S, C, OR 0

Figure 4-2

I/O Bus Interface. Simplified Schematic

4-4

Table 4-2

I/O Signal Functions

Signal ~ ame*

Function

DRVl11 RDY (X)

The DRV II-J asserts this signal during an input operation (read) to inform the user device that it
is ready to accept data. The signal is asserted when the corresponding DRV IlJ DI R bit is
cleared.

DRVllJ RPLY (X)

This pulse is generated by the DRVII-J to notify the user device that data has been accepted
(read) or that data is available (write). When the DRVII-J is the input device (read). the pulse is
generated by reading the corresponding data buffer with the associated DI R bit cll!orl!d. When
the DRV II-J is the output device (write), the pulse is generated by writing the corresponding data
buffer with the associated DI R bit seT.

(X) I/O < 15:0>

These are the 16 3-state I/O bus inputs and outputs.

uSER RDY (X)

The user device asserts this signal during a DRVII-J output operation to inform the DRVII-J
that it desires data. This signal. in conjunction with the associated DI R bit. enables the DRV II-J
3-state outputs. It appears as bit 15 in CSR (X) and must be asserted by the user device to enable
the DR V II-J to output data.

USER RPL Y (X)

This signal is asserted by the user device to inform the DRV II-J that data is available M that data
has been accepted. When the DRVII-J is the input device, the signal is asserted to indicate that
data is available. When the DRVII-J is the output device. the signal is asserted when the user
device accepts the data. This signal will generate an interrupt request if W II is installed.

*(X) = A. B, C or D.

4.4 INPUT / OUTPUT SIGNAL LOOPBACK CONNECfIONS
The DRVII-J signal pin assignments are arranged to permit loopback operation when a BC05W-XX
cable is installed with a half twist connecting J I-I to J2-50. Cable BC05W -xx must be installed to run
the CVDRCA, CVDRDA and DECX II module diagnostics. With the cable installed in this manner,
the proper connections are made to loopback the DRVII-J protocol signals. Communication with this
tjlpe of connection is made bet\veen ports £d.. and C and between ports Band D. This arrangement also
permits interconnecting two DRVII-Js by the same method, with communication between either J I
and J I or J I and J2. Table 4-3 describes the loopback signal connections between ports A and C and
between ports Band D.
4.5 INTERFACE CABLE
The BC05W-XX cable may be used to connect the DRVII-J to user devices or to link two LSI-II
buses together through two DRVII-Js. The BC05W-XX is a flat shielded cable with 50-pin connectors
at both ends, and is available in 0.6 m (2 ft), 3.0 m (10ft) and 7.6 m (25 ft) lengths. The cable length
(XX) is specified in feet. For example, a 2-foot BC05W cable is ordered as BC05W-02.

The maximum cable length of 25 feet is specified for the distance between two DR V 11-Js or from a
DRVII-J to a user device with an ac load equivalent to the DRVII-J. The maximum cable length may
have to be shortened if the ac load of the user device is greater than the ac load of the DRVII-J.
4.6 INPUT jOUTPUT FUNCTION TIMING
The time relationships between the DRV II-J signals and the user device signals required to perform
input/output data transfers are shown in Figure 4-3. The timing tolerances between the various signals
are described in Table 4-4.

4-5

Table 4-3

JI Pin No.

DRVII-J Loopback Signal Connections

Signal

J2 Pin No.

D 1/09
D I/O 12
D I/O II
D Ij08

50
49
48
47

DI/O 14
D I/O 15
D I/O 10
D I/O 13

46
45
44
43

D 1/05
D I/O 7
D 1/03
DI/O I

42 Port D
41
40
39

4
5
6
7
8

B 1/014
B I/O 15
B I/O 10
B 1.'0 13

9
10
II
12

B I/O 5
B 1/07
B I/O 3
B I/O I

.....
.....
.....

13
14
15
16

B I/O 2
B 1/00
B 1/06
B 1/04

.....

18
20
22
24

USER RPLY B
DRVllJ RDY B
USER ROY B
DRVIIJ RPLY B

27
29
31
33

USER RPLY A
DRV11J ROY A
USER ROY A
DRVIIJ RPL Y A

35
36
37
38

A 1/04
A 1/06
A 1/00
A I/O 2

2
.3

Port B

Pert A

NOTE:

.....

B 1/09
B I/O 12
B I/O II
B 1/08

+-+

.....
.....
+-+

.....
.....
.....

+-+

.....
.....

D 1/02
DI/OO
D 1/06
D 1/04

rr
36
35

DRVllJ RPLY D
USER RDY 0
DRVIIJ RDY D
USER RPLY D

33
31
29

DRVIIJ RPLY C
USER ROY C
DRV11J RDY C
USER RPLY C

.....

CI/04
C 1/06
C 1/00
C 1/02

16
15
14
13
i2 Port C

+-+

.....
+-+

......

22
20
18

A!fO I

40
41
42

A I/O 3
A I/O 7
A I/O 5

.....
.....
.....
.....

Ci;O i
C I/O 3
C I/O 7
C I/O 5

10
9

43
44
45
46

A I/O 13
A I/O 10
A I/O 15
A 1/0 14

.....
.....
.....
.....

C I/O 13
C I/O 10
C I/O 15
CI/Ol4

8
7
6
5

47
48
49
50

A 1/08
A 1/0 II
A I/O 12
A 1/09

.....
.....

C 1/08
CliO II
C I/O 12
CI/09

......
......

3
2
I

•

Connector pins 17. 19. 21. 23, 25, 26, 28. 30. 32 and 34 on J 1 and J2 are grounds.

4-6

\4-- T2 ---.j
I

DRV11J ROY

-------~~:~--~.--~:==========================~======~~/
-+i ~
T3

USER ROY

--..,.1

i/O <15:0>

14--

=
_=----l~r<\...__.._ _ _ _ _>-C
--+I

USER RPL Y

----.J T8

j.-Tl1-1

'ICI------I---------I---

\:1~

1IIII_~--T7

'+-T6-.4

I _--------------------

oRV11J RPLY

DRV11J INPUT TIMING

IDRV11J ROY

USER ROY

I/O <15:0>

~Tl0~

I
I

Jo4-T9~
I
I

--+i T8 r-

~ T3 J.-

)

·1

I
J.(

)
;

~T14~

oRVllJ RPLY

J.--- T 12 -.t

USER RPL Y

f.-- T 11 --+I

DRV11J OUTPUT TIMING
NOTE
REFER TO TABLE 4·4 I/O FUNCTION TIMING TOLERANCE FOR
DESCRIPTION OF T1 THROUGH T14.
MA·4353

Figure 4-3

DRVII-J I/O Function Timing

4-7

Table 4-4

1/0 Function Timing Tolerance
T oIerance*·

'\;ame*

Description

Min,

Max,

DRVIIJ RDY to ORVII-J
3-state outputs disabled

()

DR V IIJ ROY to user device
3-state outputs enabled

USER ROY to user device
3-state output enabled

User device _~-state data
set up to USER R PL Y

()

Tfl

DR V IIJ RPL Y pulse width
(input mode)

410

2000

User device 3-state data
hold time after DRV IIJ R PL Y

DRV IIJ R DY to user device
3-s1ate output disabled

User 3-state outputs
disabled to USER R DY
assertion

TIO

USER RDY to DRVII-J
3-state outputs enabled

Til

USER RPLY
pulse width

TI2

DRVII RPLY
pulse width (output)

410

2000

TI3

USER RPL Y hold time
after DRVII RPL Y

TI4

DR V I I-J 3-state data to
DR V IIJ RPL Y assertion

300

·Refer to Figure 4-3 for illustration of TI through T14.
**Tolerances are in nanoseconds.

4-8

4.7 I;\/PliT DATA OPERATION
An input data operation is a transferral of a 16-bit data word from a user device to any DR V II-J input
port. Three control signals and the I/O < 15:0> bus lines are used to perform an input data transfer.
The transfer sequence is initiated when the DRVI1-J asserts DRVllJ ROY to inform the user device
that data may be piaced on the I/O bus associated with the ROY signaL The user device then places
the data on the bus and asserts US ER R PLY to inform the DR V II-J that data is available. The
DR V II-J reads the input data buffer and then asserts DR V IlJ RPL Y to notify the user device that the
data has been accepted.

The sequence of operations performed by the DR V I1-J and the user device during an input data
transfer is shown in Figure 4-4. (The timing between the control signals is shown in Figure 4-3.)
4.8 OlJTPUT DATA OPERATION
An output data operation is a transferral of a 16-bit data word from any DR V II-J port to a user
device. Three control signals and the I/O < 15:0> bus lines are used to perform an output data transfer. The output data transfer is initiated when the user device asserts USER ROY to inform the
DR V 11-J to send data. The DRY II-J outputs the data on the I/O < 15:0> bus lines and asserts
DRV II] RPL Y to inform the user device that data is available" The user device accepts the data and
then asserts USER RPL Y to notify the DR V j j -J that the data has been accepted.

The sequence of operations performed by the user device and the DR V II-J during an output data
transfer is shown in Figure 4-5. (The timing between the control signals is shown in Figure 4-3.)
4.9 I~TERRllPT OPERATIO~
The user device can input up to 16 individual interrupt requests to the DR V II-J. either through the
port A I/O < 15:0> lines or through the 4 USER RPL Y signals and the A I/O < I! :0> lines. The
DR V 11-J cannot process interrupt requests until its interrupt control logic is enabled by the processor.
The processor enables the DRY Il-J by setting the interrupt enable bit 9 of CS RA. The sequence of
DRY I1-J and user device signals during an interrupt operation is shown in Figure 4-6.

4-9

DRV11-J

USER DEVICE

*REQUEST DATA
• ASSERTS DRV11J ROY
• DISABLES TRISTATE DATA
BUFFER OUTPUTS

----~ --.... SEND DATA

.--

ACCEPTS DATA

• SETS IRR BIT AND GROUP
INTERRUPT
• AN IRQ IS GENERATED
IF IE IS SET
• ASSERTS DRV11J RPL Y
WHEN INPUT DATA BUFFER
IS READ (DATA ACCEPTED) ~

• PLACES DATA ON I/O
BUS <15:0>
____ • ASSERTS USER RPL Y
___ --(DATA AVAILABLE)

-- --- --

--.... DATA ACCEPTED

INPUT COMPLETE
• NEGATES DRVllJ RPL Y
* NEGATES DRV11J ROY

----.. --..

• DEVICE RECEIVES
DRV11J RPLY
___ • NEGATES USER RPL Y

- - . . * INPUT COMPLETE
• REMOVES DATA FROM
I/O BUS <15:0>

NOTES
IF THE USER DEVICE IS INCAPABLE OF EXECUTING THE INPUT FUNCTION
PROTOCOL, DATA TRANSFER IS DEPENDENT UPON PERIODIC READING OF
THE INPUT BUFFER, WITH THE DRV11-J IN AN INPUT MODE. (DIR BIT
CLEARED)
* THESE STEPS ARE ON L Y REQUI RED WHEN I/O MODES ARE SWITCHED FROM
INPUT TO OUTPUT OR OUTPUT TO INPUT. IF MODES ARE NOT SWITCHED,
THE USER DEVICE SENDS DATA AND THE DRVll-J ACCEPTS THE DATA TO
COMPLETE THE DATA TRANSFER.
MR-43151

Figure 4-4

Jnpui Data Transfer SC4uence

4-10

DRVll·J

USER DEVICE

·OUTPUT DATA REQUEST

-- -- --- --

·OUTPUT DATA

• OUTPUTS DATA ON I/O
BUS <15:0>
• ASSERTS DRV11J RPL Y
(DATA AVAILABLE)

• DEVIC;::E ASSERTS
USER ROY

ACCEPT DATA
• DEVICE ASSERTS USER RPLY
(DATA ACCEPTED)

DATA ACCEPTED
• SETS IRR BIT AND
GROUP INTERRUPT
• AN IRQ IS GENERATED
IF IE IS SET.
• NEGATES DRVl 1J RPL Y

___ __

OUTPUT COMPLETE
• NEGATES USER RPL Y
• NEGATES USER ROY

• OUTPUT COMPLETE
• REMOVES DATA FROM
I/O BUS <15:0>

NOTES
IF THE USER DEVICE IS INCAPABLE OF PERFORMING THE OUTPUT FUNCTION
PROTOCOL, THEN DATA TRANSFERS ARE DEPENDENT ON PERIODICALLY
WRITING THE OUTPUT DATA BUFFER WHILE THE USER ROY SIGNAL IS
HELD ASSERTED (GND) WITH THE DRV11·J IN AN OUTPUT MODE. (D!R B!T SET)
• THESE STEPS ARE ONLY REQUIRED IF MODES ARE SWITCHED BETWEEN INPUT
AND OUTPUT OR OUTPUT AND INPUT. IF MODES ARE NOT SWITCHED, THE
DRVll-J SENDS THE DATA AND THE USER DEVICE ACCEPTS THE DATA TO
COMPLETE THE DATA TRANSFER.
MR...:J52

Figure 4-5

Output Data Transfer Sequence

4-11

DRV11-J

USER DEVICE

ENABLE INPUT
·ASSERT DRVllJ ROY

---- ---

-........ ·ENABLE DATA

__ • PLACE DATA ON A I/O'
BUS <0:11>

ENABLE INTERRUPT
• ENABLE INTERRUPT
CONTROL

"""'"-

"""'"-........ REQUEST INTERRUPT

____ ---~

INTERRUPT
• ASSERT GROUP INTERRUPT
AND IRQ IF IE IS SET
• ASSERT DRV11J RPL Y WHEN
INPUT BUFFER IS READ
___

---

"""'"-

.-- • CREATE AN INACTIVE
TO ACTIVE TRANSITION
ON A I/O <11:0>OR
USER RPLY <A:D>

-........ INTERRUPT DONE
• RECEIVES DRV11J RPL Y

NOTE
• THESE STEPS ARE NOT REQUIRED IF MODES ARE NOT CHANGING FROM
OUTPUT TO INPUT.
MR·4354

Figure 4-6

Interrupt Sequence

4-12

CHAPTER 5
PROGRAMl\tlING EXAl\;lPLES
5.1

GENERAL DESCRIPTION

The DR V II-J may be used in systems where the data is transferred to or from the user device under
program control, or in those using interrupt-driven service routines. Programmed data transfers may
be performed with or without the protocol control signals (handshaking), depending on the system's
complexity. The simplest of system applications may not require the handshaking signals, whereas
more complicated system applications require handshaking signals to synchronize the processor with
the user device. The following three programming examples illustrate how the DR V II-J may be programmed to operate in program-controlled data transfer systems without handshaking and with, and
in interrupt-driven systems.
5.2

PROGRA\1\1ED DATA TRANSFER WITHOUT HANDSHAKING

In the simplest system applications. input and output data transfers may be performed under program
control by reading and writing the data buffer registers (DBRA, DBRB, DBRC and DBRD). Data
can be transferred on a bit-by-bit basis. the method used when the DRV II-J is connected to a simple
user device that does not generate or interpret handshaking signals. For example. I port could monitor
i 6 independent switches. if. in actuai operation. input to the DR V i i -j is aiiowed to change whiie the
software is reading the buffer, erroneous data may be read. In such a case, the software can "'debounce" the line by reading the line until it gives reproducible results. The routines shown in Figure 5I illustrate the software interface to the DR V) )-J. The first routine initializes the DR V I1-J for operation. The second returns the status of 1 of 32 independent input lines that are connected to the A and
B I/O pins.
5.3

PROGRAMMED DATA TRANSFER WITH HANDSHAKING

In more complicated system applications, handshaking (DR V II-J polled mode) must be used between
the DR V 11-J and the user device to indicate the availability of data and to synchronize the sender and
receiver so that data is not lost. For example. when the DR V II-J sends a 16-bit command to a user
device. it must wait until the command is executed before it can send another. Another example is
where the user device assembles 16 signals and then informs the DR V II-J that data is available. I n the
programming example in Figure 5-2, the first routine initializes the DRV II-J for operation. An input
routine reads data from the port A I/O lines after detecting the USER RPL Y signal with the group
interrupt bit in CSRA. The output routine waits for the USER RDY signal from the user device
(available in CSRB) before it outputs data on the port B I/O lines.

5-1

; Routine to initialize the DRVII-J for input without handshaking.
Uses ports A and B for 32 lines of input.

1
2
3

4 000000
5 000000
6 000004
7 000010

INITDR: :
005037
005037
000207

CLR
CLR
RTS

164160
164164

B
9

10
11

12
13 000012
14 000012
15 000014
16 000020
17 000022
IB 000024
19 000026
20 000032
21 000034
22 000036
23 000040
24
25 000042
26 000046
27 000050
2B
29
30

@tCSRA
@tCSRB

initialize for input
initialize for input
return to caller

Routine to check the status of one of the 32 input lines:
The routine expects a line number ,from a to 31 in RD.
It returns the state of the li~e (0 or 1) in RO.

RDLINE::
010046
0427000 177757
040016
006200
006200
016000 164162
005316
100402
006200
000774
042700
005726
000207

5$:

177776

10$:

000001

MOV
BIC
BIC
ASR
ASR
MOV
DEC
BMI
ASR
BR

RO, -(SP)
1177757, RO
RO, (SP)
RO
RO
DBRA(RO), RO
(SP)
10$
RO
5$

save the line number
clear all but port flag
clear all but -line in port- bits
form offset from DBRA

BIC
TST
RTS

1177776, RO
(SP) +

remove the other bits
pop the saved !ine number
and return to the caller

read the appropriate buffer register
shift the bits
in RO
until the right one is in bit

.END

SYMBOL Ti\B LE
BASE
CSRA
CSRB

164160
164160
• 164164

CSRC
CSRD

164170
'" 164174

Figure 5-1

DBRA
DBRB

164162
164166

DBRC
DBRD

164172
164176

INITDR
RDLINE

Example of a Programmed Data Transfer without Handshaking

5-2

OOOOOORG
000012RG

Initialize the DRVII-J for programmed rio with handshaking.
Set up to read from port A, write to port B.

4 000000
5 000000
6 000002
7 000006
8 000014
9 000020
10 000022
11 000026
12 000032
13 000036
14 000040
15
16
17
18
19 000042
20 000042
21 000046
22 000050
23
24 000056
25 000062
26
27
28
29
30 000064
31 000064
32 000070
33 000074
34 000076
35 000104
36
37
38

NITDR: :
010046
005037
012737
012700
105010
112710
112710
112710
012600
000207

164160
000400
164170

MOV
CLR
164164

MOV

MOV
CLRB
MOVB
MOVB
MOVB
MOV
RTS

000054
000055
000204

RO. - (SP)
@,CSRA
1400. @t CSR8
'CSRC, RO
(RO)
154, (RO)
'55, (RO)
'204, (RO)
(SP)+, RoPC

Routine to wait for
caller in RO.

105737
100775
112737

164170

013700
000207

164162

000114

164170

RDPORT: :
10$:
TSTB
BMI
MOVR
MOV
RTS

dat~

save RO
clear DIR,
~~~

available

@,CSRC
10$
1114, @,CSRC
@,DBRA, RO
PC

reset group 1 interrupt control

CSRB DrR for output

RO points to CSRC
reset group 2 interrupt control
clear g(OUP 2 IMR bit 4 (user reply A)
clear group 2 IMR bit 5 (user reply B)
set group 2 polled m0de
restore saved RO
return to caller
VI'

pert A and

r~turn

the data .... ..., the

wait for group 2 -interruptclear group 2 IRR bit 4
so we can detect user reply A again
G get DBRA
; and return to caller

Routine to send data passed by the caller in RO to port B and wait for
it to be accepted by the user device.
WTPORT::
010037
105737
100775
112737
000207

164166
164170
000 ll5

10$:
164170

MOV
TSTB
8MI
MOVB
RTS

RO, @JDBRB
@lCSRC
10$
'115, @,CSRC
PC

put data into DBRB
wait for group 2 event (data accepted)
clear group 1 IRR bit 5
return to the caller

.END

000001

SAMPLE TABLE
BASE
CSRA
CSRB

164160
164160
= 164164

CSRC
CSRD
DBRA

164170
164174
164162

Figure 5-2

DBRB
DBRC

164166
164172

OBRO
INITOR

= 164176
OOOOOORG

ROPORT
WTPORT

000042RG
000064RG

Example of a Programmed Data Transfer with Handshaking

5.4 INTERRLPT-DRIVEN TRANSFER
I n systems where the number of devices and/or the complexity of service increases. the DR V II-J may
be used to enhance processor throughput and response time by eliminating the need for a polling
program. In such applications, the DRVII-J can be initialized to interrupt the processor when the user
device has accepted data (output) or when it has data available (input). The following two programs
output data from port A (see Figure 5-3) and input data from port C (see Figure 5-4) under interrupt
control. The program in Figure 5-3 initializes the DR V II-J to interrupt on USER R PLY A (output)
and the program in Figure 5-4 initializes the DRV II-J to interrupt on USER R PLY C (input). The
DR V II-J vector address memory is loaded with the vector address and the appropriate group 2 interrupt line enabled. The output program will then force an interrupt to occur by setting the group 2 port
.\ I R R bit 4. This starts the interrupt service routine. which runs in parallel w'ith the main program.
The programs perform unrelated functions while input/output is proceeding asynchronously. The
programs then wait for a done flag. which is set by the interrupt service routines to indicate that the
input loutput transfer is completed.

5-3

Program to send 256 words of data to DRVI1-J port A under interrupt
control.

1
2
3

Set up DRVll-J vector at an unused location (location 400)

4
5

.ASECT

6 000000
7

8
9

000400

10 000400
11 000402
12
13 000000

001110'
000340

= 400
interrupt is vectored to location WTINT
at priority level 7 (interrupts disabled)

WTINT
340
• PSECT

15 000000
16
17
18
19
20
21
22 001000
23 001002
24
25 001004
26 001004
27
28 001012
29 001016
30 001020
31 001024
32 001032

this is the 256 word output buffer
fill buffer with ascending numbers for test

OBUS:
CaNT = 0
.REPT
256.
.WORD
CaNT
CaNT = CONT+1
.ENDR

000000
000400

OPNTR:
OFLAG:

next word pointer
output done flag

.BLKW
.BLKW

START:
MOV

114 0 0, @'CSRA

164170

MOV

000344
000100
000241

164174
164160

MOVB
MOVB
MOVB

'CSRC, RO
CLRB (RO)
'344, (RO)
1100, @,CSRD
1241, @ICSRA

000241
000300
000020 164174
000000' 177714
177712
000054
000134

MOVB
MOVB
MOVB
MOV
CLR
MOVB
MOVB

1241, (RO)
1300, (RO)
120, @ICSRD
'OBUF, OPNTR
OF LAG
154, (RO)
1134, (RO)

012737

001400

012700
105010
112710
112737
112737
112710
112710
112737
012767
005067
112710
112710

164160

33
34 001040
35 001044
36 001050
37 001056
38 001064
39 001070
40 001074
41
42
43
44
45
46
47 001100
48 001:04
49 001106
50
51
52
53 001110
54 0011Jo
55 001116
56 001124
57 001126
58 001134
59 001142
60
61 001144
62 001150
63
64
65

set port A four output, enable interrupts,
and reset group 1 interrupt controller
RO points to CSRC
reset group 2 interrupt controller
preselect vector address memory (line 4)
load vector of 400
arm group 1 with master maks bit
this will enable group 2
arm group 2 with master mask bit
preselect ACR for writing
set ACR to clear line 4 (user reply A)
initialize output pointer
and done fl ag
clear group 2 IMR bit 4 (user reply A)
set group 2 IRR bit 4 (cause an interrupt)
to get things started)

NOW, the CPU can be used for other things while the data is being sent.
Some time later ..•
005767
001775
000000

177676

10$:

TST
BEQ
HALT

OF LAG
10$

; The following

wait for output complete

is the interrupt service routine.

WTINT:
112737
026727
001407
017737
062767
000002

000114
177656

164170
001000'

177646
000002

164162
177636

005267
000002

177632

001004'

MOVB
CMP
BEQ
MOV
ADD
RTI

1114, @ICSRC
OPNTR, ,OBUF+5l2.
10$
@OPNTR, @'DBRA
'2, OPNTR

clear group 2 IRR bit 4 (REPLY A)
; sent all words in buffer?
if so, we're done
else send out next word
point to following word
return from interrupt

10$:
RTI

INC

OFLAG

signal output complete
return from interrupt

.END

START

SYMBOL TABLE
BASE
CONT
CSRA

164160
000400
164160

CSRB
CSRC
CSRD

= 164164

= 164170
.. 164174

DBRA
DBRB
DBRC

164162

DBRD
OBUF
OF LAG

= 164166

,. 164172

164176
OOOOOOR
001002R

OPNTR
START
WTINT

OOlOOOR
001004R
OOlllOR
"''' .. 739

Figtlre 5-)

Example of an !nterrupt-Dr!ven Output Program

5-4

Program to read 256 words of data from ORVI1-J port C under interrupt
control.

2
3
4
5
6 000000
7

Set up DRVII-J vector at an unused location (location 400).
.ASECT
= 400

000400

9
~O

11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

000400
000402

.PSECT

000000
rBUS:
I PNTR:
IFLAG;

000000
001000
001002
012737

001000

001012
001016

012700
005010

164170

001020
001024
001032

112710
112737
112737

000346
000100
000241

001040
001044
001050
001056
33 001064
34 001070
35
36
37
38
39
40
41
42 001074

112710
112710
112737
012767
005067
112710

44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59

001102

. BLKW
. B LKW

256.

256 word input buffer
next empty word pointer

input done flag

START:

001004
001004

43 001100

interrupt is vectored ~o location HDINT
at pri?rity level 7 (interrupts disabled)

HOINT
340

001104'
000340

MOV

ilOOO, @'CSRA

MOV
CLR

ICSRC, RO
(RO)

164174
164160

MOVB
MOVB
MOVB

'346, (RO)
tl 00, @'CSRO
1241, @'CSRA

000241
000300
164174
000100
000000' 177714
177712
000056

MOVB
MOVB
MOVB
MOV
CLR
MOVB

1241, (RO)
'300, (RO)
1100, @ICSRD
iIBUF, IPNTR
IFLAG
'56, (RO)

164160

Now,

reset group 1 interrupt controller,
enable DRVll-J interrupts
RO points to CSRC
set port C for input, reset group 2
interrupt controller
preselect vector address memory (line 6)
load vector of 400
arm group 1 with master mask bit
this will enable group 2
arm group 2 with master mask bit
preselect ACR for writing
set ACR to clear line 6 (user reply C)
initialize input pointer
and done flag
clear group 2 IMR bit 6 (user reply C)
interrupts will now be generated on data
received from port C

the CPU can be used for other things while the data is being received.

Some time later ...

005767
001775
000000

177702

TST

.Lv;;>

IFLAG
10$

BEQ

.ait for input finished

HALT
i

The following

001104
001112
001120
001126
001134
001136

112737
013777
062767
026727
001005
112737

000116
164172
000002
177646

164170 RDINT:
177660
177652
001000'

000036

164170

001144
001150

005267
000002

177632

is the interrupt service routine.

MOVB
MOV
ADD
CMP
BNE
MOVB

1116, @ICSRC
@IDBRC, @rPNTR
12, IPNTR
IPNTR, IlBUF+512.
10$
136, @ICSRC

INC

IFLAG

10$:

001004'

clear group 2 IRR bit 6 (REPLY C)
get the word just received
bump buffer pointer
; buffer full?
branch if buffer not full
we're done.
Set group 2 IMR bit 6
inter rupt)
signal input complete

return from interrupt
. END

STAR'!'

SYMBOL TABLE
BASE
CSRA
CSRB

164160
164160
164164

CSHC
CSRO
DBRA

164170
164174
164162

DBRB
DBRC
DBRD

Figure 5-4

Exampie of an interrupt-Drtven Input Program

164166
164172
164176

IBUF
IFLAG
IPNTR

5-5

DOOOOOR
001002R
OOlOOOR

RDrNT
START

aCll04R
OOl004R

(disable

CHAPTER 6
OPTIC ISOLATOR INTERFACE EXAl\1PLE
GENERAL DESCRIPTION
The DR V II-J can be used for industrial machine control. process control, monitoring applications.
etc. When the module is used in industrial applications, the computer system must often operate in a
hostile electrical environment. The DR V II-J may have to control or monitor components such as
lamps. motors. relays and switches. all of which generate electrical noise. In such an environment.
interfacing the DRVII-J to the user device(s) through optically coupled isolators may be necessary.
Optic isolators are used to isolate electrically and/ or convert signal levels between the user device(s)
and the DRV! I-J latched output drivers in output mode, or the unlatched Schmitt trigger buffers in
input mode. The simplified schematic Figure 6-1 shows how the optic isolators may be connected to
the DRV) I-J for data input and output transfers. The choice of an appropriate optic isolator or optic
isolator module depends upon the requirements of the specific application.

6-1

ORV11J INPUT MODE ONLY

ORV11 J
ORV11·J
CONN
INPUTS
(X) 110 <150>

(X) 10· 15:0>

USER
CONN.
USER
INPUT

(X) I/O <150>

OPTIC ISOLATOR

•
•

ORVllJ ROY (XI-+-++---\
+5 V

ORVllJ RPLY IXI-t+-+--"""

tV
OPTIONAL
RESISTOR

USER ROY (Xl
\---+~4--..L.-.----- (ALWAYS HIGH)

+5 V

\ - - + . - t - - - - - - - - USER RPL Y (X)
CABLE
(BCOSWI
ORVll·J OUTPUT MODE ONL Y

TSO' 150>

ORV11J
OUTPUTS
(X)IIO <15:0>

ORV11-J
CONN

USER
CONN
r0-

USER
(X) 110 <15:0>

LS374
WRT DB IXI

>CK

OIR IX)

+5 V

(
I

'5V~

USER ROY (XI

(
I

"'~
OPTIC ISOLATOR

-b

(

ORV11J ROY (X)

ORV11J RPLY (X)

l
I

USER RPLY (X)

(

USER RPLY (X)

CAB LE
(BCOSWI

~WTE

IXI -~ A. B, C, OR 0

MA OJ59

Figure 6-1

Example of an Optic Isolator Interface

6-2

Reader's Comments

DRVII-J Parallel Line Interface
User's Guide

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