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EK-DHV11-TM-002

September 1985

189 pages

Original

8.3MB

Document:	DHV11 Technical Manual
Order Number:	EK-DHV11-TM
Revision:	002
Pages:	189
Original Filename:	http://bitsavers.org/pdf/dec/qbus/EK-DHV11-TM-002.pdf

OCR Text

EK-DHV11-TM-002

DHV11
Technical Manual

EK-DHV11-TM-002

DHV11
Technical Manual

Prepared by Educational Services
of
Digital Equipment Corporation

First Edition, September 1983
Second Edition, November 1985

The information in this document is subject to change without
notice. Digital Equipment Corporation assumes no responsibility
for any errors herein.
Notice: This equipment generates, uses, and may emit radio
frequency energy. The equipment has been tested and found to
comply with the limits for a Class A computing device pursuant
to Part 15 of FCC rules, which are designed to provide
reasonable protection against such radio frequency interference
when operated in a commercial environment. Operation of this
equipment in a residential area may cause interference in which
case the user at his own expense may be required to take
measures to correct the interference.
Printed in U.S.A

The following are trademarks of Digital Equipment Corporation.

momoDmo™
DEC
DECmate
DECUS
DECwriter
DIBOL
MASSBUS

PDP
P/OS
Professional
Rainbow
RSTS
RSX

RT
UNIBUS
VAX
VMS
VT
Work Processor

CONTENTS
CHAPTER 1

INTRODUCTION

1.1
1.2
1.2.1
1.2.2
1.2.3
1.2.4
1.2.5
1.3
1.3.1
1.3.2
1.3.3
1.3.3.1
1.3.3.2
1.4
1.4.1
1.4.2
1.4.2.1
1.4.2.2
1.4.2.3
1.4.2.4
1.4.2.5
1.5
1.5.1
1.5.2
1.5.3

SCOPE ............................................................. 1-1
OVERVIEW ....................................................... , 1-1
General Description ............................................ , 1-1
Physical Description ............................................ , 1-2
Versions of DHV11 ............................................. , 1-4
Configurations .................................................. , 1-4
Connections .................................................... 1-6
SPECIFICATION ................................................... 1-6
Environment Conditions ......................................... , 1-6
Electrical Requirements ......................................... , 1-7
Performance ................................................... , 1-7
Data Rates ................................................ , 1-7
Throughput ................................................ , 1-8
INTERFACES ...................................................... 1-8
System Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-8
Serial Interfaces ................................................ , 1-8
Interface Standards ......................................... , 1-8
Serial Data Format ......................................... , 1-10
Line Receivers ............................................. , 1-11
Line Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-11
Speed/Distance Considerations .............................. , 1-11
FUNCTIONAL DESCRIPTION ..................................... 1-12
Control Function ............................................... , 1-12
Q-Bus Interface ................................................ , 1-12
Serial Interfaces ................................................ , 1-12

CHAPTER 2

INSTALLATION

2.1
2.2
2.3
2.3.1
2.3.2
2.3.3
2.3.3.1
2.3.3.2
2.4
2.4.1
2.4.2
2.5
2.6
2.6.1
2.6.2
2.6.3
2.6.4
2.6.5
2.6.6
2.7
2.7.1

SCOPE ............................................................. 2-1
UNPACKING AND INSPECTION ................................. , 2-1
INSTALLATION CHECKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .. 2-2
Address Switches ............................................... , 2-2
Vector Switches ................................................ , 2-3
Backplane .' .................................................... , 2-4
Connection to the Q- Bus .................................... , 2-4
Bus Grant Continuity Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-5
PRIORITY SELECTION ........................................... , 2-6
DMA Request ................................................. , 2-7
Interrupt Request ............................................... , 2-7
MODULE INSTALLATION ......................................... 2-8
CABLES AND CONNECTORS ..................................... 2-9
Distribution Panel .............................................. , 2-9
Staggered Loopback Test Connector H3277 ....................... , 2-12
Line Loopback Test Connector H325 ............................. , 2-13
Null Modem Cables ............................................ , 2-13
Full Modem Cables ............................................. , 2-15
Data Rate to Cable Length Relationships .......................... , 2-16
MULTIPLE COMMUNICATIONS OPTIONS ....................... , 2-16
Floating Device Addresses ....................................... , 2-16

Page

iii

2.7.2
2.8
2.8.1
2.8.2
2.8.3

Floating Vectors .................................................
INSTALLATION TESTING .........................................
Testing in PDP-11 Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Testing in MicroVAX I Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Testing in MicroVAX II Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

CHAPTER 3

PROGRAMMING

3.1
3.2
3.2.1
3.2.2
3.2.2.1
3.2.2.2
3.2.2.3
3.2.2.4
3.2.2.5
3.2.2.6
3.2.2.7
3.2.2.8
3.2.2.9
3.3
3.3.1
3.3.2
3.3.3
3.3.3.1
3.3.3.2
3.3.3.3
3.3.4
3.3.5
3.3.6
3.3.7
3.3.8
3.3.9
3.3.10

SCOPE ............................................................. 3-1
REGISTERS ....................................................... 3-1
Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-1
Register Bit Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-3
Control and Status Register (CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-4
Receive Buffer (RBUF) . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .. 3-6
Transmit Character Register (TXCHAR) . . . . . . . . . . . . . . . . . . . . .. 3-8
Line Parameter Register (LPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-8
Line Status Register (STAT) ................................. 3-11
Line Control Register (LNCTRL) ............................. 3-12
Transmit Buffer Address Register Number 1 (TBUFFAD1) ...... 3-15
Transmit Buffer Address Register Number 2 (TBUFFAD2) ...... 3-15
Transmit DMA Buffer Counter (TBUFFCT) ................... 3-16
PROGRAMMING FEATURES ...................................... 3-17
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-17
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-17
Transmitting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-18--DMA Transfers ............................................ 3-18
Single Character Programmed Transfers .......... . . . . . . . . . . . .. 3-18
Methods of Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-19
Receiving. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-19
Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-19
Auto X-ON and X-OFF ......................................... 3-19
Error Indication. . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-21
Modem Control ................................................. 3-21
Maintenance Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-22
Diagnostic Codes ............................................... '. 3-22
Self-Test Diagnostic Codes .................................. 3-22
Interpretation of Self-Test Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-22
Skipping Self-Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. 3-23
Background Monitor Program (BMP). . . . . . . . . . . . . . . . . . . . . . . . .. 3-24
PROGRAMMING EXAMPLES .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-24
Resetting the DHV11 ............................................ 3-24
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-25
Transmitting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-26
Single Character Programmed Transfer ........................ 3-26
DMA Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-27
Aborting a DMA Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-28
Receiving. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-28
Auto X-ON and X-OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-29
Checking Diagnostic Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-30
Modem Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-31

3.3.10.2
3.3.10.3
3.3.10.4
3.4
3.4.1
3.4.2
3.4.3
3.4.3.1
3.4.3.2
3.4.3.3
3.4.4
3.4.5
3.4.6
3.4.7

2-20
2-22
2-22
2-23
2-24

CHAPTER 4

TECHNICAL DESCRIPTION

4.1
4.2
4.3
4.3.1
4.3.2.
4.4
4.4.1
4.4.2
4.4.2.1
4.4.2.2
4.4.2.3
4.4.3
4.4.4
4.4.5
4.4.6
4.4.7
4.4.8
4.5
4.5.1
4.5.2
4.6
4.6.1
4.6.2
4.6.3
4.6.4
4.6.4.1
4.6.4.2
4.6.4.3
4.6.4.4
4.6.5
4.7
4.7.1
4.7.1.1
4.7.1.2
4.7.1.3
4.7.1.4
4.7.2
4.7.3
4.7.4
4.7.4.1
4.7.4.2
4.7.5
4.7.6
4.8
4.8.1
4.8.1.1
4.8.1.2
4.8.2

SCOPE ............................................................. 4-1
Q-BUS INTERFACE ................................................ 4-1
SERIAL INTERFACES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-6
Modem Control and Status Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-6
EINTTL Level Conversion .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-6
CONTROL SECTION ............................................... 4-6
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-6
Common RAM .................................................. 4-7
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-7
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-8
FIFO ...................................................... 4-8
RAM Access ................................................... 4-9
Store Arbitrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-10
Microcomputers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-10
Address and Data Latches ........... , . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-10
FIFO Addresses ., .................. , ............. , . . . . . . . . . . . .. 4-11
FIFO Control ............. , , .. , , , , . , . , , . , , , , , . , . , , . . . . . . . . . . . . .. 4-11
OTHER CIRCUITS, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-11
Voltage Converter , . , . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-11
Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-11
DATA FLOW ...................................................... 4-11
Host Read from a Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-12
Writing to a Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-13
Single-Character Transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-14
DMA Transmissions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-15
DMA Block Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-17
DMA Data Management. .................................... 4-17
DMA Error Detection and Timeout ........................... 4-17
DMA Abort ................................................ 4-18
Receiving. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-18
TECHNICAL DETAIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-20
DHVll Internal I/O Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-20
PROCI Memory-Mapped I/O ................................ 4-20
PROCI Integral I/O Port Functions ........................... 4-22
PROC2 Memory-Mapped I/O ................................ 4-23
PROC2 Integral I/O Port Functions ........................... 4-25
Q-Bus Interrupts .. '.............................................. 4-26
Common RAM Arbitration ....................................... 4-26
FIFO Counter Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-30
Host Read from the FIFO ................................... 4-31
PROC2 Write to the FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-31
Control/Status Register (CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-31
Voltage Converter (SMPS) ....................................... 4-33
ROM-BASED DIAGNOSTICS ...................................... 4-35
Self-Test .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-35
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-35
Location and Interpretation of Diagnostic Codes. . . . . . . . . . . . . . .. 4-35
Background Monitor Program (BMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-36

CHAPTER 5

MAINTENANCE

5.1
5.2
5.2.1
5.2.2
5.3
5.3.1
5.3.2
5.4
5.4.1
5.4.1.1
5.4.1.2
5.4.1.3
5.4.2
5.5
5.5.1
5.5.2
5.5.3
5.5.3.1
5.5.4
5.5.5
5.6
5.6.1
5.6.1.1
5.6.1.2
5.6.1.3
5.6.2
5.6.2.1
5.6.2.2
5.7
5.7.1
5.7.2
5.7.3
5.8
5.9
5.10

SCOPE ............................................................. 5-1
MAINTENANCE STRATEGY ........................... " ....... " 5-1
Preventive Maintenance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
Corrective Maintenance ........................................ " 5-1
INTERNAL DIAGNOSTICS ...................................... " 5-2
Self-Test .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-2
Background Monitor Program (BMP) .............................. 5-2
XXDP+ DIAGNOSTICS ........................................... 5-2
CVDHA?, CVDHB?, and CVDHC? ..... , ................ " ...... 5-2
Functions of CVDHA? .................................... " 5-3
Functions of CVDHB? .................................... " 5-3
Functions of CVDHC? .................................... " 5-3
DECX/ll Exerciser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-3
DIAGNOSTIC SUPERVISOR SUMMARY ......................... " 5-3
Loading the Supervisor Diagnostic ............................... " 5-4
Four Steps to Run a Supervisor Diagnostic ....................... " 5-4
Supervisor Commands ........................................... 5-5
Command Switches ....................................... " 5-6
Control/Escape Characters Supported ............................ " 5-6
Example Printouts ............................................. " 5-7
CORRECTIVE MAINTENANCE ON MICROVAX I SYSTEMS .... " 5-8
The Macroverify Diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-8
Setting Up Procedures ..................................... " 5-9
Bootstrapping Procedure ................................... " 5-9
Macroverify Operation .................................... " 5-9
DHVII Diagnostic EHXDH..................................... 5-9
Setting Up Procedures ..................................... " 5-10
Bootstrapping Procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-10
RUNNING MICROVAX II DIAGNOSTICS ......................... 5-18
Overview of the MicroVAX II Maintenance System. . . . . . . . . . . . . . ... 5-18
Running the Customer Version of the Micro VAX II Diagnostic. . . . . .. 5-19
Running the Maintenance Version of the Micro VAX II Diagnostic .. " 5-19
FIELD REPLACEABLE UNITS (FRUs). . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-25
TROUBLESHOOTING FLOWCHART ............................ " 5-25
COMPONENT REPLACEMENT ................................. " 5-25

APPENDIX A IC DESCRIPTIONS
Al
A2
A2.1
A2.2
A2.3
A3
A3.1
A3.2
A4
AS
A6
A7

SCOPE ............................................................ A-I
8051 MICROPROCESSOR/MICROCOMPUTER ................... " A-I
8051 Block Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-I
Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-2
Read/Write Timing............................................ " A-4
SC2681 DUAL UART (DUART) .................................. " A-5
Block Description ............................................. " A-5
Pin-Out Information ................................... : . . . . . . . .. A-7
DC003 INTERRUPT IC .......................................... " A-9
DC004 PROTOCOL IC ............................................. A-13
DC005 BUS TRANSCEIVER IC .................................... A-17
DCOlO DIRECT MEMORY ACCESS LOGIC ...................... " A-21

APPENDIX B MODEM CONTROL
B.1

B.2
B.2.1

SCOPE ............................................................ B-1
MODEM CONTROL ............................................... B-1
Example of Auto-Answer Modem Control for the PSTN. . . . . . . . . . . .. B-2

APPENDIX C GLOSSARY OF TERMS
C.1
C.2

SCOPE ............................................................ C-1
GLOSSARY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. C-2

APPENDIX D AUTOMATIC FLOW CONTROL
D.1
D.2
D.3
D.3.1
D.3.2
D.3.3

OVERVIEW ....................................................... D-1
CONTROL OF TRANSMITTED DATA ............................. D-1
CONTROL OF RECEIVED DATA .................................. D-2
Flow Control by the Level of the Received Character FIFO .......... D-2
Flow Control by Program Initiation ............................... D-3
Mixing the Two Types of Received Data Flow Control .............. D-4

APPENDIX E INSTALLATION GUIDE FOR THE DHV11 REMOTE
DISTRIBUTION PANEL CABINET KIT
E.1
E.2
E.2.1
E.2.2
E.2.3
E.2A
E.3
EA
EA.1
EA.1.1
EA.1.2
EA.2

GENERAL DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
FUNCTIONAL DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
H3176 Bulkhead Panel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
H31 75 Remote Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
BC22H-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
BC051.rXX ....................................................
INSTALLATION ...................................................
DIAGNOSTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MicroPDP-11 Diagnostics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
CVDHBE Test. ............................................
CVDHC?O Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Micro VAX II Diagnostics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

vii

E-1
E-4
E-4
E-4
E-4
E-4
E-4
E-5
E-5
E-5
E-6
E-6

FIGURES
Figure No.

Title

1-1
1-2
1-3
1-4
1-5
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
3-1
3-2
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
5-1
5:..2
A-I
A-2
A-3
A-4
A-5
A-6
A-7
A-8

M3104 Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-3
Example of DHV11 Configuration................. . . . . . . . . . . . . . . . . . . .. 1-5
DHVII Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .. 1-6
Serial Character Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-10
DHV11 Functional Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. 1-11
Location of Switchpacks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-2
Setting the Device Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-3
Setting the Vector Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-4
Bus Grant Continuity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-6
DHVll Installation.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-8
H3173-A Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-9
H3173-A Circuit Diagram............................................ 2-10
Staggered Loopback Test Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-12
Line Loopback Test Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-13
Null Modem Cable Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-15·
Register Coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-3
Diagnostic/Status Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-22
DHV11 Block Diagram ............................................... 4-2
DATI Bus Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-4
DATO or DATOB Bus Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-4
Interrupt Request/Acknowledge Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-5
DMA Request/Grant Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-5
Common RAM - Memory Map ........................................ 4-7
Common RAM Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-9
Reading from a Register ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-13
Writing to a Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-14
Single-Character Transmit ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-15
DMA Data Transfer ................................................. 4-16
DMA Character Handling ............................................ 4-17
DMNMemory Error Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-18
Receiving a Character ........................... ~ . . . . . . . . . . . . . . . . . . .. 4-19
PROCI I/O Decoding ................................................ 4-21
PROC2 I/O Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-24
Interrupt Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-27
RAM Arbitration and Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-28
Store Access Timing Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-29
CSR and Register Address Circuits .................................... 4-32
DHVII Voltage Converter ............................................ 4-34
Register Contents After Self-Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-35
Troubleshooting Connection Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
Troubleshooting Flowchart ............................................ 5-26
8051 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-I
8051 Symbol and Pin-Out Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-2
Program Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-4
Data Memory Read Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-5
Data Memory Write Cycle ........................................... A-5
SC2681 Dual Universal Asynchronous Receiver Transmitter (DUART) ... A-6
SC2681 Pin-Out Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-7
DC003 Logic Symbol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-9

Page

Vlll

A-9
A-I0
A-II
A-12

A-13
A-14
A-15
A-16
A-17
A-18
A-19
D-l
D-2
D-3
E-l
E-2

DC003 A Section Timing ............................................ A-lO
DC003 A and B Section Timing ...................................... A-II
DC004 Simplified Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-14
DC004 Timing Diagram .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-15
DC005 Simplified Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-19
DC005 Timing Diagram ............................................. A-20
DCOlO Simplified Logic Diagram ..................................... A-21
DCOlO Logic Symbol/Truth Table .................................... A-23
DCO 10 Voltage Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-23
DCOlO Timing Diagram, DMA Request/Grant ......................... A-24
DCOlO Timing Diagram ............................................. A-25
Transmitted Data Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. D-l
Received Character FIFO-Level Flow Control .......................... D-3
Program-Initiated Flow Control ....................................... D-4
DHVII Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. E-2
DHVII Remote Distribution Panel Cabinet Kit. . . . . . . . . . . . . . . . . . . . . . . .. E-3

TABLES
Page

Table No.

Title

1-1
1-2
2-1
2-2
2-3
2-4
2-5
3-1
3-2
3-3
4-1
4-2
4-3
4-4
A-I
A-2
A-3
A-4
A-5
A-6
B-1
E-l

DHVII Data Rates .................................................. 1-7
EIA/CCITT Signal Relationships. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-9
DHVII Bus Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-5
H3173-A Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-11
Data-Rate/Cable-Length Relationships. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-16
Floating Device Address Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-17
Floating Vector Address Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-20
DHVII Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-2
Data Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-10
DHVII Self-Test Error Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-23
PROCI Memory-Mapped I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-20
PROCI Integral I/O Port Functions .................................... 4-22
PROC2 Memory-Mapped I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-23
PROC2 Integral I/O Port Functions .................................... 4-25
8051 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-3
SC2681 Pin Designation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-8
DC003 Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-12
DC004 Pin/Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-16
DC005 Pin/Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-17
DCOI0 Pin/Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-21
Modem Control Leads ................................................ B-2
Cabinet Kit Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. E-l

PREFACE
This document describes the installation requirements and servicing procedures for the DHVII
asynchronous multiplexer. It contains information for first-line service, field service support, and for
customer engineers. A substantial programming chapter is included. Appendix C contains a glossary of
terms used in this manual.
The manual is organized into five chapters plus appendices.
Chapter 1
Chapter 2
Chapter 3
Chapter 4
Chapter 5
Appendix A
Appendix B
Appendix C
Appendix D
Appendix E

Introduction
Installation
Programming
Technical Description
Maintenance
Integrated Circuit Descriptions
Modem Control
Glossary of Terms
Automatic Flow Control
Installation Guide for the DHVll Remote Distribution Panel Cabinet Kit

The following is a list of related titles and document numbers.
Document

Number

LSI-II Microcomputer Interfaces Handbook
LSI-II Systems Service Manual
Communications Mini-Reference Guide
Terminals and Communications Handbook
Microcomputers and Memories
DHVll Print Set
DHVII Maintenance Card

EB-20I75-20
EK-LSIFS-SV
EK-CMINI-RM
EB-20752-20
EB-209I2-20
MPOI793
EK-DHVI1-MC

ORDERING THIS MANUAL
DIGITAL Personnel Ordering
Additional copies of this document and printed copies of the documents listed may be obtained from:
Digital Equipment Corporation
444 Whitney Street
Northboro, Massachusetts 01532
ATTN: Printing and Circulation Services (NR2/MI5)
Customer Services Section
Customer Ordering Information
Purchase orders for supplies and accessories should be sent to:
Digital Equipment Corporation
Accessories and Supplies Group
Cotton Road
Nashua, New Hampshire 03060
Contact your local sales office or call DIGITAL Direct Catalog Sales toll-free 800-258-1710 from 8.30
a.m. to 5.00 p.m. eastern standard time (US customers only). New Hampshire, Alaska, and Hawaii
customers should dial (603)-884-6660. Terms and conditions include net 30 days andF.O.B. DIGITAL
factory. Freight charges will be prepaid by DIGITAL and added to the invoice. Minimum order is
$35,00. Minimum does not apply when full payment is sent in with an order. Checks and money orders
should be made out to Digital Equipment Corporation.
European Customers
European customers should order the manual from their local Accessories and Supplies Group (A and
SG).

xii

CHAPTER 1
INTRODUCTION
1.1 SCOPE
Chapter 1 provides general information and specifications. It describes how the module can be configured,
and how it interfaces with the system bus and the serial data lines. Physical and functional descriptions are
also included.
1.2 OVERVIEW
The DHVl1 is an LSI-l1/Q-bus option. All future references to the bus will be by the global term Q-bus.
The specific terms Q 16, Q 18, or Q22 will be used where needed to identify versions with 16-, 18-, or 22bit addresses.
1.2.1 General Description
The DHVll option is an asynchronous multiplexer which provides eight full-duplex asynchronous serial
data channels on Q-bus systems. The option can be used in many applications. These include data
concentration, terminal interfacing, and cluster controlling.
The main features of the DHVl1 are as follows:
•

Eight full-duplex asynchronous data channels

•

Direct Memory Access (DMA) or single-character programmed transfers on transmit

•

Large 256-entry First-In-First-Out (FIFO) buffer for received characters, dataset status
changes, and diagnostic information

•

RS-423-A/V.I0/X.26 and RS-232-C/V.28 compatible

•

Full-duplex point-to-point 'or auto-answer dial-up operation

•

Programmable split speed per line

•

Total module throughput of 15000 characters per second

•

Q16, Q18, and Q22 bus compatible

•

Automatic flow control of transmitted and received data

•

Self-test and background monitor diagnostics

•

Programmable test facilities

•

Single quad-height module (M31 04)

•

All functions are programmable, except for device address and vector selection which are done
by hardware switches on the module.
1-1

Enough modem control is provided on all eight channels to allow auto-answer dial-up operation over the
Public Switched Telephone Network (PSTN). Suitable modems to use this facility are the Bell models
103, 113, 212, or equivalent. The DHV 11 can also be used for point-to-point operation over private lines.
Modem control is' implemented by software in the host.
The module provides DMA or single-character transfers from the host system to the serial lines. A 256character FIFO buffer is provided for data received from the serial lines.
By using microcomputers (referred to as PROC 1 and PROC 2 in this manual), the DHVII releases the
host system from m3ny of the data handling tasks.
One 8051 microcomputer controls DMA and single-character transmissions from the host system to the
DHVl1. A second 8051 controls four SC2681 Dual Universal Asynchronous Receiver Transmitters
(DUARTs) which carry out the serial/parallel and parallel/serial conversion of data.
The DHVII carries ROM-based diagnostics which are executed independently of the host. A fuB range of
diagnostic programs is also available.
A green LED gives the GO/NO-GO status of the module. More detailed diagnostic information is also
made available to the host system via the FIFO buffer. Loopback test connectors are available for use with
the system-based diagnostics.
I/O addresses and interrupt vectors for the module are selected on two Dual-In-Line (DIL) switchpacks.
All other DHVII functions and configurations are programmable.
To prevent data loss at high throughput levels, the DHVII can be programmed for automatic X-ON and
X-OFF operation.
1.2.2 Physical Description
The option is based on a standard quad-height module (M31 04). The layout of this module is shown in
Figure 1-1. The dimensions are 21.6 cm x 26.5 cm (8.51 inches x 10.44 inches).
The, module is connected to the Q-bus via connectors A and B. 11 and J2 are connected to the
communications lines via BC05 L- xx cables and H31 73-A distribution panels.
On some backplanes, jumpers WI (BIAK) and W2 (BDMG) extend the bus grant signals to the next
module slot via connectors C and D.
DIL switchpacks E58 and E43 select the device address and vector address of the module.

1-2

LOW CHANNELS (0-3)

HIGH CHANNELS (4-7)

BERG CONNECTOR

DUART SC2681
(CHANNELS 2/3)

DUART SC2681
(CHANNELS 011)

DUART SC2681
(CHANNELS 617)

PROC 2
8051

24MHz
OSC

PROC 1
8051

ADDRESS
SELECT

DUART SC2681
(CHANNELS 4/5)

E58

ADDRESS AND
VECTOR SELECT
E43

BACKPLANE CONNECTORS
Wl - INTERRUPT ACK GRANT
W2 - DMA GRANT

}

IN FOR H9270 AND H9275 BACKPLANES
OUT FOR H9273 AND H9276 BACKPLANES
RD1141

Figure 1-1

M3104 Module

1-3

1.2.3 Versions of DHVll
To facilitate installation in different system packages, and to allow installation in non-specified cabinets,
the DHVll module (DHVII-M) can be supplied with one of three cabinet kits. Except for the length of
the flat ribbon cables, the cabinet kits are the same.
DHVII-M is made up of the following:
•
•
•

M3104
EK-DHVlI-TM

The module
This technical manual
Packaging.

The three cabinet kits are:
•
•
•

CK-DHVII-AA (21-inch cables); example of use, PDP-l1/23S
CK-DHVlI-AB (12-inch cables); example of use, Micro/PDP-lI
CK-DHVlI-AC (30-inch cables); example of use, PDP-1I!23 PLUS

Each kit is made up of:
•
•
•
•
•
•

Two BC05L-xx cables (see NOTES)
H325 line loopback connector
H3277 staggered loopback connector
Two H3173-A distribution panels (see NOTES)
Mounting bolts and washers for H3173-A.
Adapter plate (contained in CK-DHVII-AC)
NOTES
The H3173-A distribution panels provide noise
filtering and static discharge protection on the
communications lines.
BC05L-xx cables are supplied in different lengths
for each kit. The kits are specified in Section 2.2.
DIGITAL does not supply a cabinet kit for
installing the DHVll in non-FCC-compliant
cabinets.

The hardware is connected as in Section 1.2.5.
1.2.4 Configurations
Figure 1-2 shows some possible DHVll configurations. The position of the module on the bus
(backplane) determines its DMA and interrupt priorities. A guide to positioning is given in Section 2.4.
Any or aU of the data channels can be connected to a terminal or to a data communications line.

1-4

HOST
}
PROCESSOR~~SY_S_T_EM~B_U_S_(_Q2~2~O_R_LS_I_l_l)________________________~

"'>-

r----------

DEVICE

----

,.-.-~'-----.....

I
I
I

M3104 MODULE

I
I

I
\

, 8 DATA CHANNELS

LOCAL
EQUIPMENT

LD~12..O~I~ _

REMOTE
EQUIPMENT

I
MODEM

TELEPH~NE OR_MODEM
..

DATACOMMS
'----~ LINE

REMOTE

r----- TERMINAL

LOCAL
L-----Ir-~ TERMINAL

I
I

TELEPHONE OR

-------- I
I
L
REMOTE
PROCESSOR

__ _

MODEM
4'--_ _~ DATA COMMS
LINE
I

MODEM _

REMOTE
DHVll

_ _ _ _ _ _ _ .J

~__________________
Q2_2_0_R
__
LS_I_l_l_B_US
______________________________

R01142

Figure 1-2

Example of DHVII Configuration

1-5

1.2.5 Connections
Figure 1-3 shows the connections for the DHV11. These include normal operating connections and test
connections. More detail is shown in Figure 2-3 in Section 2.

}

CHANNELS
0-3

.........

H3277

" "U'\
\

STAGGERED
LOOPBACK
TEST
CONNECTOR

,~~~~~

.......

_--

~;_~

n
--

.,/

25 PIN D TYPE
CONNECTORS
CHANNELS
4-7

~ = NORMAL CONNECTION
...,. = TEST CONNECTION

NOTE:

H325
LINE
LOOPBACK TEST
CONNECTOR

=
=

BC05L~01
30.48 CM (12 INCHES)
BC05L-1 K = 53.34 CM (21 INCHES)
BC05L-2F 76.2 CM (30 INCHES)
R01143

Figure 1-3 DHV11 Connections
1.3

SPECIFICATION

1.3.1

Environment Conditions
•
•
•

Storage temperature: O°C to 66°C (32°F to 151°F)
Operating temperature: 5°C to 60°C (41°F to 140°F)
Relative humidity: 10% to 95% non-condensing

1-6

1.3.2

Electrical Requirements
+5 V dc + or - 5% at 4.25 A (typical)
+12 V dc + or - 20% at 520 rnA (typical)

Negative 12 V dc is generated by a Switched Mode Power Supply (SMPS) circuit on the DHV11.1t has
the following specification:
-11.85 V dc + or - 7.25% at 400 rnA (maximum)
Output ripple is 200 mV peak to peak at 36.7 kHz
Loads applied to the Q-bus are as follows:
Q-bus ac loads
Q-bus dc loads
1.3.3

2.9 ac loads
1.0 dc loads

Performance

1.3.3.1 Data Rates - Each channel can be programmed to operate at one of a number of speeds. If
needed, th~ transmission and reception rates can be different (split speed). Table 1-1 shows the data rates
which are'possible. The maximum rate per channel is 38400 bits per second (bits/s).
The eight serial channels are implemented with four DUART ICs (Integrated Circuits). Channels are
paired as follows: 0/1, 2/3, 4/5, 6/7. Because of the method of data rate generation, all transmit and
receive rates for a DUART channel-pair must be in the same group (A or B).
Table 1·1

DHV11 Data Rates

Speed (Bits/s)

Groups

50
75
110
134.5

150
300
600
1200

B
AandB
AandB
AandB

1800
2000
2400
4800

B
B
AandB
AandB

7200
9600
19200
38400

A
AandB
B
A

R
AandB
AandB

Data rate selection is covered in Chapter 3 (Programming).

1-7

1.3.3.2 Throughput - Each channel is capable of full-duplex operation at data rates of up to 38400
bits/so The DRVll, however, cannot handle eight channels operating at this rate at the same time. Total
maximum throughput is also dependent on the application and configuration.
Maximum throughput:
Per channel (send)

1000 characters per second in single-character transfer mode
2000 characters per second in DMA mode

(receive)

4000 characters per second.

On any channel, the DRVII can send at one of the above transmit rates and receive at 4000 characters
per second at the same time.
Total (8 channels)

15000 characters per second
NOTES
The DMA firmware cannot handle transmit data
faster than 2000 characters per second (19200
bits/s). If the transmit data rate is increased to
38400 bits/s, the duration of each character will
be halved but there will be gaps in transmission.
15000 characters per second is the sum of both
transmitted and received characters on all
channels. This throughput could support all
channels transmitting or receiving at 19200 bits/ s,
or all channels transmitting and receiving at 9600
bits/ s. The above figures are based on a 7- bit
character with start bit, parity bit, and one stop
bit.

1.4

INTERFACES

1.4.1 System Bus Interface
The M3104 module will connect directly to the Q-bus via connectors A and B. To make the module
compatible with backplanes which have Q-bus on C and D also, two jumpers (W 1 and W2) are provided.
The use of these jumpers is described in Section 2.3. Backplane signals, together with pin details, are listed
in Table 2-3.
1.4.2

Serial Interfaces

1.4.2.1 Interface Standards - The DRVII provides interface signals which conform to a subset of
the EIA/CCITT standard RS-232-C/V.24. The electrical characteristics conform to EIA/CCITT
standards RS-232-C/V.24 and RS-423-A/V.28 (unbalanced interface). The interface is compatible with
X.26/V.I0 standards but does not comply with the slew rate requirements.
Conriections to the external equipment are via 25-pin male subminiature D-type connectors, as specified
for RS-234-C.

1-8

By means of suitable cables and connectors (not supplied or supported by DIGITAL) the channels can be
made compatible with the following:
1.
2.

Subset of EIA interchange standard RS-449
EIA electrical standard RS-422 (balanced).
NOTE
Even when RS-422 is implemented; RS-423-A
cable length/data rate recommendations should
be followed.
The distribution panel does not support split
grounds.

Table 1-2 shows RS-232-C/V.24/RS-449 signal relationships, and pin connections for the male
subminiature D-type connectors.
Table 1-2

EINCCITT Signal Relationships

Signal
Name

D-Type RS-232-C
Circuit
Pin
CCITIV.24

Protective Ground

Circuit
RS-449

(GND)

(SIG GND)

102

Transmitted Data

(TXD)

103

Received Data

(RXD)

104

Request to Send

(RTS)

105

Clear to Send

(CTS)

106

Data Set Ready

(DSR)

107

Data Terminal Ready

(DTR)

108/2

(RI)

125

(DCD)

109

NOTE

Signal Ground

Ring Indicator
Data Carrier Detect

The backward channels listed below are not
supported. However, by using another channel
for this function, and by connecting a suitable
cable (H1200 or H1201 for example), backward
channel operation is possible.

1-9

Circuit No.

Function
Transmitted backward channel data
Transmit backward channel line signal
Received backward channel data
Backward channel ready
Backward channel received line signal detector

118

120
119

121
122

1.4.2.2 Serial Data Format - Serial characters are made up of a coded sequence of bits which are
enclosed between a start and a stop signal. The start signal is always 1 bit long but the stop signal is
programmable to 1, 1.5, or 2 bits. The duration of a bit is dependent on the selected data rate.
Character codes may be 5, 6, 7, or 8 bits long, optionally followed by a parity bit. Parity can be
programmed as even, odd, or no parity.
Ori serial data channels controlled via the D HV 11, the data line is held marking when inactive. Transfer of
each character begins with a start bit (space) and ends with one or more stop bits (mark).

Figure 1-4 shows the reception of an 8-bit character with parity. The Least-Significant Bit (LSB) of the
character code is transmitted first. If another character is not ready for transmission, the line will stay
marking. The figure shows 1, 1.5, and 2 stop bits.

NOTE
This description applies to signals at the DUART
pins. Signals measured on the interchange circuits
will have the opposite polarity to those shown.
The data rate clock which times the serial data, is 16 times the programmed data rate. Arrows show when
the bits are tested for polarity.
8 DATA BITS

______________

-JA~

______________

)

! ! ! ! ! ! ! ! ! ! !
MARK + l--+-~

SPACE -

PARITY BIT

START BIT

R01144

Figure 1-4

S~rial Character Format

The DHV11 allows the following serial character formats:
•
•
•

Characters of 5, 6, 7, or 8 bits with or without parity and with 1 stop bit
Characters of 6, 7, or 8 bits with or without parity and with 2 stop bits
Characters of 5 bits with or without parity and with 1.5 stop bits.

1-10

1.4.2.3 Line Receivers - The serial line receivers used in this module are 9637 AC or equivalent.
They convert the EIA input signals to TTL levels suitable for the DUARTs.
Signals are· inverted by the receivers.
1.4.2.4 Line Transmitters - The serial line transmitters used in this module are 9636AC or
equivalent. They convert TTL level signals from the DUARTs to EIA levels on the data lines.
Signals are inverted by the transmitters.
1.4.2.5 Speed/Distance Considerations - The maximum data rate which can be used on a line
depends upon a number of factors. These are:
1.
2.
3.
4.

The characteristics of the line transmitters and receivers
The characteristics of the serial cable (or link)
The length of the cable
Noise (interference) which affects the line.

A 'speed against distance' table for typical conditions is provided in Section 2.6.6.
SERIAL INTERFACES
CONTROL SECTION

022/LSI11 BUS
INTERFACE

DMA REOUEST

DMA ADDRESSES AND DATA

DMA
INTERRUPT
AND
PROTOCOL
LOGIC

1--DATA AND CON FIG

--I

RAM

REGISTERS
AND
BUFFERS

1
1

1------ 1
1

BUS
DRIVERS
AND
RECEIVERS

FIFO
CONTROL ~~_...,

1
FIFO
1
(256 CHARS) 1

.~
w
Z

Z
<I:

W
...J

Il.

::J

__ J1

0...-_ _...

110
ADDRESS
RECOG /o:R~EA~D:-A~D:-::D:::'RE=::S:::::S~E~NA~B~LE
NITION
1

I
1
I
~ 1

WRITE ADDRESS
ENABLE
RD 761

Figure 1-5

DHVll Functional Block

1-11

1.5

FUNCTIONAL DESCRIPTION

1.5.1 Control Function
In the DHVII module (Figure 1-5), data is transferred by three methods:
1.

By DMA. Blocks of data are transferred from system memory to the serial interface. DMA data
is routed via the bus receivers, PROC1, the RAM, and PROC2.

In the non-DMA mode, single characters can be transferred from the host system to the serial
interface. The route for single characters is via the bus receivers, the RAM, PROC 1, the RAM,
and PROC2.

Single characters can be transferred from the serial interface to the host system. The route for
received characters is via PROC2, the FIFO buffer, and the bus drivers.

At the center of the control section is a 1K-word RAM. By writing control words to registers in the RAM,
the host can indirectly configure and command the module. The host can also write data bytes to registers
in the RAM.
Two microcomputers (PROC 1 and PROC 2), which contain their own programs in internal ROM, scan
the RAM in order to detect a new configuration, or data to be transferred. They also write status
information to the RAM, which can then be read by the host.
PROC 2 configures the DUARTs as instructed, and transfers transmit and receive data between the
RAM and the DUARTs. Received characters are writteri to FIFO addresses provided by FIFO control.
Among other functions, PROC 1 controls DMA actions. Using DMA information provided by the host, it
starts DMA circuits which control each DMA transfer. PROC 1 keeps track of DMA addresses and
character count, and reports to the host when the block has been transferred.
Both microcomputers execute· background diagnostics when not busy with other tasks.
1.5.2 Q-Bus Interface
The DHVII module is considered by the host system as a number of I/O ports. The bus drivers and
receivers recognize DHVII addresses and allow the host to access the FIFO buffer and the registers.
When the FIFO buffer is being read, FIFO control provides the read addresses.
Standard DIGITAL LSI protocol, interrupt, and DMA integrated circuits (ICs) control the interface.
Module address switches are connected to comparators in the bus driver/receiver ICs. When an I/O
address from the host is the same as the address on the switches, the DHV11 responds to the host. On
receiving the response, the host proceeds with the transaction.
Vector address switches are also connected to the bus drivers. These allow the DHVll to supply two
interrupt vectors (transmit and receive) to the host during an interrupt acknowledge sequence.
1.5.3 Serial Interfaces
Eight full-duplex serial interfaces are provided by four DUARTs. These ICs, controlled by PROC 2, are
configured as needed by the host system. They carry out the serial/parallel and parallel/ serial conversion.
When a received character is assembled PROC 2 is interrupted.
The status of modem control lines for each channel is polled by PROC 2. If programmed to do so, the
DHVII will report changes of modem status to the host. Such reports are made via the FIFO buffer and
the device registers.

1-12

CHAPTER 2
INSTALLATION
2.1 SCOPE
This chapter contains information on how to prepare and install the DHVII option. It contains sections
on the following:
•
•
•
•
•
•

Device and vector address selection
Rules for backplane positioning
Recommended cables
Test connectors
Floating address and vector assignment
Testing after installation.

2.2 UNPACKING AND INSPECTION
There are a number of versions of the DHVll, all of which are based on the module kitDHVII-M. This
may be ordered with one of the three cabinet kits listed below. Examine all parts for physical damage.
Report damaged or missing items to the shipper and the DIGITAL representative.
DHVII-M

M3104 + EK-DHVII-TM,
(field upgrade base option)

DHVll"AP

System integrated DHVII
(DHVII-M + appropriate cabinet kit)

Field Upgrade Cabinet Kits
CK-DHVI1-AA
CK-DHVII-AB
CK-DHVII-AC

PDP-l1/23S systems
MicroPDP-ll and MicroVAX systems
PDP-ll/23+ systems

Contents
H325
H3277
H3173A
BC05L-IK
BC05L-O1
BC05L-2F
74-28684-01
90-06021-01
90-06633-00

Single line loopback
Staggered loopback
4-line 25-way distribution panel
40-way ribbon cable, 21 inch
40-way ribbon cable, 12 inch
40-way ribbon cable, 30 inch
Adapter plate
Bolt
Washer

2-1

11
1
1

1
1
2

1
1
2
2

2
2
2
8
8

8
8

2.3

INSTALLATION CHECKS

2.3.1 Address Switches
The device address for the DHVII is set on switchpacks E58 and E43. The location of these switchpacks
is shown in Figure 2-1. Figure 2-2 shows the method of setting the device address on the switchpacks. The
example shown is for a Q22-bus address of 177604408.
From the information contained in Figure 2-2 it can be seen that switches 5 and 8 on switchpack E5 8 must
be set to ON for the example shown.

~==:::::I L.-I_---..II
I~;:::::=::::::.I~I_---'
1..------11
DD
1
JUMPERS Wl AND W2 ARE REMOVED FOR TYPE H9276
AND H9273 BACKPLANES AND INSTALLED FOR TYPE
H9275 AND H9270 BACKPLANES

E58 c:::x:::J E43

R02342

Figure 2-1

Location of Switchpacks

Use the following method to set the device address.
1.

Define the octal address. This mayor may not be the factory default, and will depend upon what
other devices are contained within this system configuration. Refer to Table 2-4 for information
on floating device address assignments.

Convert the octal address to a binary bit pattern. You can write this pattern on Figure 2-2, in the
blank character line left for this purpose.

Relate the binary address to the switches on the switchpacks, and set switches to ON where
they relate to binary 1.

2-2

LEGEND

= SWITCH OFF (binary 0)

123456781

000010010

SWITCH ON (binary 1)

Q-BUS ONLY
AS ALL ONES
NOT ON UNIBUS
..
•

BIT No.

EXAMPLE
SETTING
17760440

INTERPRETED _ _ _---I..~I-T-ii-ii--r-I-JI'-~

SEE NOTE

PART OF
SWITCHPACK E43

SWITCH PACK E58

I .

I
I
I

DECODED
BY DEVICE

1'-.
I

~~~~

~/~~ ~~ 17
~f~~ vC/O"
2 }, I/}
9.1
~J-

'---' L--...------J ~ ~ ~ "-----..".--.~ '---...----.J
DEVICE
ADDRESS

I
I

....

I
I

.... ,

I
I
~--~~-~,

I 01 = 6

I2J = 7

USE THE BLANK ROW TO
PENCIL-IN THE ADDRESS
PATTERN YOU NEED

EACH GROUP IDENTICAL

I
I

NOTE:

/
/

I
/
' .... 1//
~-~

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

=0
= 1
= 2
= 3
= 4
= 5
= 6
= 7

RD2254

Figure 2-2

Setting the Device Address

2.3.2 Vector Switches
During an interrupt acknowledge sequence, the DHVII returns a 7-bit interrupt vector to the host The six
high-order bits of this vector are derived from the settings of the last six switches of switchpack E43. The
location of this switchpack is shown in Figure 2-1. Figure 2-3 provides an example of these switches set to
an address of 3008. From the information in Figure 2-3 it can be seen that switches 4 and 5 must be set to
ON for the example shown.

2-3

You can use t4e following method to set up the vector address.
1.

Define the octal address. This mayor may not be the factory default Refer to'Table 2-5 for
information on floating vector address assignments.

Convert the octal address to a binary bit pattern. You can write this pattern on Figure 2-3 in the
blank line left for this purpose.

Relate the binary address to the switches on the switchpack, and set switches to ON where they
relate to binary 1.

PART OF
SWITCHPACK E43

LEGEND

D=
I
=

SWITCH OFF (binary 0)

011000

SWITCH ON (binary 1 )

..._ _ INTERPRETED
AS ALL ZEROES

EXAMPLE
SETTING

=300

I
I

DECODED
BY DEVICE

SEE NOTE
BIT No.

VECTOR
ADDRESS:

\
\

BOTH GROUPS IDENTICAL

\/
~

NOTE:
USE THE BLANK ROW TO
PENCIL-IN THE ADDRESS
PATTERN YOU NEED

0
0
0
0
1

. ON SWITCH PACK E43
SWITCH 2 IS NOT USED

1
1

0
0
1
1
0
0
1

0
1
0
1
0
1
0
1

= 0
= 1
= 2
= 3

== 4
= 5
= 6
= 7
R02255

Figure 2-3
2.3.3

Setting the Vector Address

Backplane

2.3.3.1 Connection to the Q Bus - The DHV11 interfaces with the system via the Q-bus. The physical
connection is made via the A, B, C, and D edge connectors on the module.
Bus signals, their categories, functions, and pin designation are listed in Table 2-1.

2-4

Table 2-1

DHVII Bus Connections

Category

Signal

Function

Pin Number

DatalAddress

BDALO.L - 1.L
BDALl.L - l5.L
BDAL16.L - l7.L
BDAL18.L - 21.L

DatalAddress Lines

AU2-AV2
BE2 - BV2
ACl- ADI
BCl - BFl

Data Control

BDOUT.L
BRPLY.L
BDIN.L
BSYNC.L
BWTBT.L
BBS7.L

Data Output Strobe
Reply Handshake
Data Input Strobe
Synchronize Strobe
Write Byte Control
I/O Page Select

AE2
AF2
AH2
AJ2
AK2
AP2

Interrupt Control

BIRQ.L
BIAKI.L
BIAKO.L

Int. Req. Level 4
Int. Ack. Input
Int. Ack. Output

AL2
AM2
AN2
>::11!',

DMA Control

BDMR.L
BDMGI.L
BDMGO.L
BSACK.L

DMA Request
DMA Grant Input
DMA Grant Output
Bus Grant Acknowledge

ANI
AR2
AS2
BNl

System Control

BINIT.L

Initialization Strobe

AT2

Power Supplies

+5 V
+12 V

DC Volts
DC Volts

AA2-DA2
BD2

Grounds

GND
GND
GND
GND

Ground Connections
Ground Connections
Ground Connections
Ground Connections

AC2-DC2
ATI - DTI
AJl - BJ1
AMl-BMl

2.3.3.2 Bus Grant Continuity Jumpers - Backplanes suitable for DHVII fall into two groups:

Q/CD Q/Q -

Q-bus on A and B connectors, user-defined signals on C and D
Q-bus on A and B, and C and D connectors.

In Q/CD backplanes, bus grant signals pass through each installed module via the A and B connectors of
each bus slot.

Q/Q backplanes are designed so that two dual-height options can be installed in a quad-height bus slot.
The Q-bus lines are routed as follows:
AB,
CD,
CD,
AB,

first slot
first slot
second slot
second slot

and so on.

2-5

Lihes AM2, AN2, CM2, and CN2 (BIAK) and AR2, AS2, CR2, and CS2 (BDMG) carry the bus grant
signals .. Figure 2-4 uses BIAK as an example of bus grant routing. The same method is used for continuity
ofBDMG.
Q/CD BACKPLANE

Q/Q BACKPLANE

r----...,
I

MODULE
CN2

I
CID

I
1
1

INTERRUPT
CONTROL

L __

1---

CM2

---I

1
1
1 INTERRUPT 1

AlB 1

BIAK

I
I

CONTROL

AM2
DUAL

- - - - --I

CN2

1 AN2 [

CM2

1
1

I AM2

AlB

I
I

INTERRUPT
CONTROL

L _ M...9D~L!. _ J

QUAD
I
L_~~LI. _I

SLOT

CM2

AN2

INTERRUPT
CONTROL

lSHORT'CIRCUIT

1----,

I
1

I
I

~ 1 IF INSTALLED

C/D

CM2

CN2

__-.J

AN2

Wl EXTENDS
BIAK

~.
AM2

BIAK

AN2

INTERRUPT
CONTROL

1
1

lAM2
DUAL

L_M.ED~~ J
SLOT

1
1

1
IAM2
QUAD
_M.2P~E_ _I

"---;:?M2

SLOT

-~o-- BACKPLANE

•

MODULE WIRING
AD1S39

Figure 2-4

Bus Grant Continuity

Each dual-height module will extend the continuity of bus grant signals BIAK and BDMG to the next
module. .
If a quad-height option is installed,jumpers perform the grant continuity function of a dual option installed
on C and D.
Therefore, with a Q/Q backplane, WI and W2 should be installed. H9275 and.H9270 are examples of
this type of backplane.
In a Q/CD backplane, pins CM2, CN2, CR2, and CS2 are available for user-defined signals. Therefore
WI and W2 must be removed. H9276 and H9273 are examples of this type of backplane.
2.4 PRIORITY SELECTION
The DHVII uses the BIRQ4line to request interrupt service. It does not monitor any of the higher-level
interrupt request lines. Because of this, both the interrupt request and DMA (non-processor request)
priorities of the DHVll, are selected by the position of the DHVll on the bus.
The bus (backplane) position may be a compromise between DMA and interrupt priority requirements.
As a general rule, DMA request priorities should be considered first, and then interrupt (bus) requests.

2-6

2.4.1 D MA Request
DMA request priority is usually selected on a basis of throughput. The faster devices (higher throughput)
will usually have priority over slower DMA devices; for example, disk, tape, and then communications
devices. This is because a fast device will usually reach an overrunlunderrun condition sooner than a
.
.
slower device.
The simple approach can be further complicated by hardware buffering in the device. For example, a disk
controller may read a full sector of information into a hardware buffer. It may then raise a DMA request to
. move the data to system memory. If the request is not serviced immediately, there is no danger of data loss.
However, a magnetic tape unit or a communications device without buffering may need to be serviced
quickly. In this case the slower unit might be serviced first. This method of priority selection could, of
course, reduce disk throughput.
The system designer should consider the following four factors in determining DMA priorities:
1.
2.
3.
4.

Device average service time
Maximum wait time to be allowed (before loss of data)
Average time between DMA requests
Slack time.

Using the above parameters, the system designer should assume that all DMA requests are made at the
same time. He should then check that his selected priority sequence does not violate the parameters of any
DMA device.
If there is only one DMA device in the system there is no DMA contention. The device's position on the
bus will be determined by its interrupt (BIRQ) priority.

NOTE
If the system memory needs refresh cycles via the
bus, these should be considered as DMA requests.

2.4.2 Interrupt Request
Interrupt requests have four levels of priority. The lowest is Level 4 and the highest is Level 7. Requests·
are made on bus interrupt request lines BIRQ4 to BIRQ7. To avoid,contention, lower-priority devices
usually monitor the higher request lines.
Within any priority group, priority is decided by backplane position. The most time-critical interrupts
must be nearer the CPU.
There are two common types of configuration for devices which need interrupt service:
1.
2.

The position-independent configuration
The position-dependent configuration.

In the position-independent configuration, devices of different priority groups can be placed anywhere in
the backplane.
In the position-dependent configuration, devices of different priority groups are positioned in descending
order of priority from the CPU.
Because the DHVll is a Level 4 device which does not monitor higher request lines, it must be positioned
after all devices that do. Therefore DHVll priority is position dependent in either configuration.

2-7

By assuming that all interrupts are raised at the same time, the system designer can check his priority
sequence as for DMA requests.
2.5 MODULE INSTALLATION
Once the backplane position of the DHVII has been defined, the module can be installed and the
backplane checked with a testmeter.
CAUTION
Switch off power before inserting or removing
modules. Be careful not to snag module components
on the card guides or adjacent modules.

LL.

L.LJ

PIN A

CHANNELS
0-3

A. PRINTED

RED LINE
TOA

"
H3277

STAGGERED
LOOPBACK
TEST
CONNECTOR
.......

RED LINE
TOA

---

RED LINE
TO A

OR--~~J1

ON PCB

ri
\

H3
3-A
DISTRIBUTION
PANEL

/
. / RED LINE
A

CHANNELS
4-7

~ =
~ =

NOTE:

NORMAL CONNECTION
TEST CONNECTION

H325
LINE
LOOPBACK TEST
CONNECTOR

BC05L-01 = 30.48 CM (12 INCHES)
BC05L-1 K= 53.34 CM (21 INCHES)
BC05L-2F = 76.2 CM (30 INCHES)
RD1540

Figure 2-5

DHVII Installation

2-8

2.6

Connect the BC05L cables to J1 and 12. Figure 2-5 shows how the parts ofthe option connect
together.

Install the module in its correct backplane position as defined in Section 2.4.

Check that +5 V is present between AA2 and ground.

Check that + 12 V is present between BD2 and ground.

CABLES AND CONNECTORS

2.6.1 Distribution Panel
Each H3173-A distribution panel adapts one of the DHVll 's berg connectors to four subminiature Dtype RS-232-C connectors. Noise filtering is provided on each pin of the RS-232-C connectors. This
reduces electromagnetic radiation from the cables. It also provides the logic with some protection against
static discharge.
Figure 2-6 shows the layout and Figure 2-7 shows the circuit. There is no CCITT equivalent of EIA
circuit AA (protective ground). The O-ohm link WI can be removed to disconnect this circuit as needed.
Table 2-2 is for two distribution panels. Information in parentheses applies to channels 4 to 7.
METAL PLATE
FILTERED D-TYPE (x4)
SCREWLOCK (x8)

~
~

"
2-

O~===I==~

E
u

00
M

a:i

-E
u

L!)

THREADED
INSERT (x4)

1-~-------LI----

co
M

~PCB

----- -

_J,h___- U - - - - FOR 6-32
BOLT

90-06021-01

P~9

J3
_ _ BERG (J5)

----~------~~--

- - - - - - -----

2.62em
(1.031in)
5.24em (2.062in)
NOT DRAWN TO SCALE

6.60em (2.60in)
RD1146

Figure 2-6

H3173-A Layout
2-9

The following is an example of the use of Table 2-2.
Signal TXDO is the Transmitted Data line for channel O. Its CCITT circuit number is 103. It is connected
to J5 pin B on the H3173-A for channels 0 to 3.
Signal TXD4 is the Transmitted Data line for channel 4. Its CCITT circuit number is 103.1t is connected
to J5 pin B on the H3173-A for channels 4 to 7.
J1

.---

rr"-/

r--

SIGNAL GROUND

TRANSMIT DATA 0/4

..
2

..
Y

DATA CARRIER DETECT 2/6

RECEIVE DATA 0/4

DATA SET READY 2/6

-8

6
".

.!2

DATA TERMINAL READY 0/4

2_0

RING INDICATOR 0/4

REQUEST TO SEND 2/6

CLEAR TO SEND 0/4

CLEAR TO SEND 2/6

REQUEST TO SEND 0/4

,..

RING INDICATOR 2/6

DATA TERMINAL READY 2/6

20
3

•

•~

DATA SET READY 0/4

RECEIVE DATA 2/6

DATA CARRIER DETECT 0/4

TRANSMIT DATA 2/6

2
".

-!j

SIGNAL GROUND

!;!
M

r
R

"---

SIGNAL GROUND

TRANSMIT DATA 1/5

DATA CARRIER DETECT 3/7

RECEIVE DATA 115

DATA SET READY 3/7

DATA TERMINAL READY 115

•

RING INDICATOR 115

,..

N..N

REQUEST TO SEND 3/7

CLEAR TO SEND 1/5

..
5

CLEAR TO SEND 3/7

REOUEST TO SEND 1/5

RING INDICATOR 3/7

DATA TERMINAL READY 3/7

2_0

•
W

DATA SET READY 1/5

RECEIVE DATA 3/7

DATA CARRIER DETECT 115

TRANSMIT DATA 3/7

V_V

SIGNAL GROUND

'----

L.--

W1
~
-=- PROTECTIVE GROUND
R01147

Figure 2-7

H3173-A Circuit Diagram

2-10

Table 2-2

H3173-A Connections
Circuit No.

J5 Pin No.

102
103
104
108/2
125
106
105
107
109

I-A (2-A)
I-B (2-B)
l-C (2-C)
I-D (2-D)
l-E (2-E)
I-F (2-F)
I-H (2-H)
l-K (2-K)
l-L (2-L)

SIGGND 1(5)
TXDl(5)
RXDl(5)
DTRl(5)
RIl(5)
CTSl(5)
RTSl(5)
DSRl(5)
DCDl(5)

102
103
104
108/2
125
106
105
107
109

I-M (2-M)
I-N (2-N)
I-P (2-P)
l-R (2-R)
I-S (2-S)
I-T (2-T)
l-U (2-U)
l-W (2-W)
I-X (2-X)

DCD2(6)
DSR2(6)
RTS2(6)
CTS2(6)
RI2(6)
DTR2(6)
RXD2(6)
TXD2(6)
SIG GND 2(6)

109
107
105
106
125
108/2
104
103
102

l-Y (2-Y)
l-Z (2-Z)
I-BB (2-BB)
l-CC (2-CC)
I-DD (2-DD)
l-EE (2-EE)
I-FF (2-FF)
I-HH (2-HH)
I-JJ (2-JJ)

DCD3(7)
DSR3(7)
RTS3(7)
CTS3(7)
RI3(7)
DTR3(7)
RXD3(7)
TXD3(7)
SIG GND 3(7)

109
107
105
106
125
108/2
104
103
102

l-KK (2-KK)
l-LL (2-LL)
I-NN (2-NN)
I-PP (2-PP)
l-RR (2-RR)
I-SS (2-SS)
I-TT (2-TT)
l-UU (2-UU)
I-VV (2-VV)

Signal
SIG GND 0(4)
TXDO(4)
RXDO(4)
DTRO(4)
RIO(4)
CTSO(4)
RTSO(4)
DSRO(4)
DCDO(4)

Name
Transmitted Data
Received Data
Data Terminal Ready
Ringing Indicator
Clear to Send
Request to Send
Data Set Ready
Data Carrier Detected

2-11

2.6.2 Staggered Loopback Test Connector H3277
(See Figure 2-8.) The H3277 test connector is used during diagnostic tests. It allows all channels to be
tested. Using this connector, you can trace a channel fault to one of two channels.
J2

S
FF

HH
C

TXDO

TXD4

RXD2

t t RXD6

TXD2

TXD6

RXDO

t f RXD4

DSR2

B
FF

DSR6

DTR2

DTR6

DSRO

DSR4

'=::3 ~,

"=:B E"

cc
y

SS
F
L

N
TT

UU
P

DCD2

DCD6

RTS2

RTS6

=:B E
DCDO

DCD4

TXDl

TXD5

RXD3

t t RXD7

TXD3

TXD7

RXDl

t f RXD5

RR
LL

DSR3

DTR3

0::

f-U

z
z

u
t9

0::
LU

f-LU

u
t9

0::
LU

ii:

0
'<t

E2='
DTR7

...............

DSR7

.--

---- ---

PHYSICAL ARRANGEMENT

s~ ~s

DSRl

DCD3

ED
DSR5

DCD7

T=:g ET

RTS3

RTS7

DCDl

DCD5

X
R01148

Figure 2-8

Staggered Loopback Test Connector

2-12

2.6.3 Line Loopback Test Connector H325
This connector is shown in Figure 2-9. It can be used during diagnostic tests to trace a fault to a single
channel.
CCITT No.

NAME

24
NOT USED ~
15
NOT USED
NOT USED
NOT USED
NOT USED
103

TXD

104

RXD

105

RTS

106

CTS

109

DCD
NOT USED

107

DSR

108.2

DTR

125

17
11
12

W1
(~

\(··············u

O \\ • • • • • • • • • • • • J o J

H325

PHYSICAL ARRANGEMENT

6
20

W1 IS PERMANENTLY IN
FOR DHV11 TESTING

CONNECTIONS
RD1149

Figure 2-9

Line Loopback Test Connector

2.6.4 Null Modem Cables
Null modem cables are used for local RS-232-C connection. Because of Federal Communications
Commission (FCC) regulations, the cable specifications for the United States and Canada are different
from those for non-FCC countries. Other countries may also have similar ElectroMagnetic Interference
(EMI) control regulations. EMC/RFI shielded cabinets (see glossary) are now available for systems
which conform to FCC requirements.

2-13

Recommended null modem cables are as follows:
1.

BC22D (for EMC/RFI shielded cabinets)
•
•
•

Round 6-conductor fully shielded cable to FCC specification
Subminiature 25-pin D-type female connector moulded on each end
Lengths available:
BC22D-I0
BC22D-25
BC22D-35
BC22D-50
BC22D-75
BC22D-AO
BC22D-B5

3.1 m (10 ft)
7.62 m (25 ft)
10.72 m (35 ft)
15.24 m (50 ft)
22.9 m (75 ft)
30.48 m (100 ft)
76.2 m (250 ft).

BC03M
•

Round 6-conductor (three twisted pairs), each pair shielded

•

Cables over 30.48 m (100 ft) have a 25-pin subminiature D-type female connector at one
end. The other end is unterminated for passing through conduit.

•

Cables 30.48 m (100 ft) and less have a similar connector at each end.

•

Lengths available:
BC03M-25
BC03M-AO
BC03M-B5
BC03M-EO
BC03M-LO

7.62 m (25 ft)
30.48 m (100 ft)
76.2 m (250 ft)
152.4 m (500 ft)
304.8 m (1000 ft).

BC22A

•
•
•

Round 6-conductor cable
Subminiature 25-pin D-type female connector moulded at each end
Lengths available:
BC22A-1O
BC22A-25

3.1 m (10 ft)
7.62 m (25 ft).

Cables of groups 1,2, and 3 are all connected as in Figure 2-10. The cables are not polarized and can
therefore be connected either way.

2-14

PIN
NUMBERS

10
20
3 0
7 0

60
20 0

PROTECTIVE GROUND

TRANSMITIED DATA

RECEIVED DATA

TRANSMITIED DATA

SIGNAL GROUND

DATA SET READY

DATA TERMINAL READY

DATA SET READY

01
03
02

o 7
020

06
RU1150

Figure 2-10

Null Modem Cable Connections

2.6.5 Full Modem Cables
Recommended full modem cables are as follows:
1.

BC22F (for EMC/RFI shielded cabinets)
•
•
•

Round 25-conductor fully shielded cable
Subminiature 25-pin D-type female connector on one end, male connector on the other
Lengths available:
BC22F-1O
BC22F-25
BC22F-35
BC22F-50
BC22F-75

- 3.1 m (10 ft)
- 7.62 m (25 ft)
- 10.72 m (35 ft)
- 15.24 m (50 ft)
- 22.9 m (75 ft)

BC05D

•
•
•

Round 25-conductor cable
Subminiature 25-pin D-type female connector on one end, male connector on the other
Lengths available:
BC05D-1O
BC05D-25
BC05D-50
BC05D-60
BC05D-AO

- 3.1 m (10 ft)
- 7.62 m (25 ft)
- 15.24 m (50 ft)
- 18.6 m (60 ft)
- 30.48 m (l00 ft).
CAUTION

In some countries, protective hardware may be
needed when connecting to certain lines. Refer to
the national regulations before making a connection.

2-15

2.6.6 Data Rate to Cable Length Relationships
All the recommended cables have data rate/cable length characteristics as in Table 2-3. Cables oflengths
different from those quoted in Sections 2.6.4 and 2.6.5 will have to be specially made. A suitable nonFCC cable for this purpose is Belden type 8777.
Table 2-3

Data-Rate/Cable-Length Relationships

Data Rate
(Bits/s)

Cable Length
(Meters)

Cable Length
(Feet)

110
300
1200
2400
4800
9600

914
914
152
152
76
76

3000
3000
500
500
250
250

NOTE
Cables longer than 15.24 m (50 ft) or with a total
capacitance greater than 2.5 nanofarads violate
RS-232-C and V.28 specifications.
CAUTION
RS-232-C is meant for local communication.
Communication devices can be damaged by induced
high voltages. You can usually minimize these
voltages by limiting the total cable length to 100 m
(300 feet), or by installing surge-limiting devices.
Do not run the cable outdoors. Keep low-voltage
data wiring away from ac power wiring, as required
by electrical codes of practice.
2.7

MULTIPLE COMMUNICATIONS OPTIONS

2.7.1 Floating Device Addresses
On UNIBUS and Q-bus systems, a band of addresses (xxx6001Os to xxx63776s) in the top 4K words is
assigned as floating address space (xxx means all top address bits = 1).
Options which can be assigned floating device addresses are listed in Table 2-4. This table gives the
sequence of addresses for both UNIBUS and Q-bus options.
Having one list allows us to use one set of configuration rules and one configuration program.

2-16

Table 2-4
Rank
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

Floating Device Address Assignments

Device
D111
DHII
DQll
DUll, DUVll
DUPII
LKIIA
DMCl1/DMRII
DZll/DZVll,
DZSll, DZ32
KMCll
LPPII
VMV21
VMV31
DWR70
RLll, RLVll
LPAII-K
KWII-C
Reserved
RXll/RX2ll,
RXV11/RXV21
DRII-W
DRll-B
DMPll
DPVll
ISBll
DMVII
DEUNA
UDASO/RQDX DMF32
KMSll
VSI00
TU81
KMVII
DHVl1/DHUll -

Size
(Decimal)

Modulus
(Octal)

4
8
4
4
4
4
4

10
20
10
10
10
10
10 CDMC before DMR)

4
4
4
4
8
4
4
8
4
4
4

10 (DZll before DZ32)
10
10
10
20
10
10 *
20 *
10
10
10*
(RXII before RX211)
10
10 **
10
10
10
20
10*
4 *
40
20
20
4
20
20

4
4
4
4
4
8
4
2
16
6
8
2
8
8

* The first device of this type has a fixed address. Any extra devices have a floating address.
** The first two devices of this type have a fixed address. Any extra devices have a floating address.
NOTE
DZII-E and DZI1-F are treated as two DZII s.
When there are no previous floating address
space options in a system, the address of the first
DHVII installed will be 7604408.

2-17

Devices of the same type are given addresses in sequence, so all DZVll s have addresses higher than
DUVII s and lower than RLVII s.
The column Size (Decimal), in Table 2-4, shows how many words of address space are needed for each
device. The column Modulus (Octal) is the modulus used for starting addresses. For example, devices
with an octal modulus of 10 must start at an address which is a multiple of 108. The same rule is used to
select a gap address after an option, or for a nonexistent device.
The address assignment rules are as follows.

Addresses, starting at 177600108, are assigned according to the sequence of Table 2-4.

Option and gap addresses are assigned according to the octal modulus as follows:
a.

Devices with an octal modulus of 4 are assigned an address on a 48 boundary (the two
lowest-order address bits = 0)

Devices with an octal modulus of 10 are assigned an address on a 108 boundary (the three
lowest-order address bits = 0)

Devices with an octal modulus of20 are assigned an address on a 208 boundary (the four
lowest-order address bits = 0)

Devices with an octal modulus of 40 are assigned an address on a 408 boundary (the five
lowest-order address bits = 0)

Address space equal to the device's modulus must be allowed for each device which is
connected to the bus

A I-word gap, assigned according to rule 2, must be allowed after the last device of each type.
This gap could be bigger when rule 2 is applied to the following rank

A I-word gap, assigned according to rule 2, must be allowed for each unused rank on the list if a
device with a higher address is used. This gap could be bigger when rule 2 is applied to the
following rank.

If extra devices are added.to a system, the floating addresses may have to be reassigned in agreement with
these rules.
In the following example, a brief description of address assignment is given. Note that the list includes
floating vector addresses. These are explained in Section 2.7.2.
Example: One DUVll, one RLVll, and two DHVlls
Vector

Address (Octal)
xxx60010
xxx60020
xxx60030
xxx60040
xxx60050

D111 gap
Hll gap
DQll gap
nUVl1
nUVl1 gap

2-18

300

Vector

Address (Octal)
xxx60060
xxx60070
xxx60100
xxx60110
xxx60120

DUPll gap
LK11A gap
DMCll gap
DZV11 gap
KMCll gap

xxx60130
xxx60140
xxx60160
xxx60170
xxx60200

LPPll gap
VMV21 gap
VMV31 gap
DWR70gap
RLVll

xxx60210
xxx60220
xxx60230
xxx60240
xxx60250

RLVll gap
LPA11-K gap
KWll-C gap
reserved gap
RXV11 gap

xxx60260
xxx60270
xxx60300
xxx60310
xxx60320

DRll-W gap
DRll-B gap
DMP11 gap
DPV11 gap
ISBll gap

xxx60340
xxx60350
xxx60354
xxx60400
xxx60420

DMV11 gap
DEUNAgap
UDA50 gap
DMF32 gap
KMS11 gap

xxx60440
xxx60444
xxx60460
( xxx60500
-. xxx60520

VSlOO gap
reserved
KMV11 gap
1st DHV11
2nd DHV11

xxx60540

DHV11 gap

..:0;-

310

320
330

The first floating address is xxx60010. As the DJ11 has a modulus of 109, its gap can be assigned to
xxx6001O. The next available location becomes xxx60012.
As the DH11 has a modulus of 20g, it cannot be assigned to xx600l2. The next modulo 20 boundary is
xxx60020, so the DHll gap is assigned to this address. The next available location is therefore
xxx60022.
A DQll has a modulus of 109. It cannot be assigned to xxx60022. Its gap is therefore assigned to
xxx60030. The next available location is xxx60032.
ADUV11 has a modulus of 109. It cannot be assigned to xxx60032. Itis therefore assigned to xxx60040.
As the 'size' of DUV11 is four words, the next available address is xxx60050.

2-19

There is no second DUVll, so a gap must be left to indicate that there are no more DUVlls. As
xxx600S0 is on a 108 boundary, the DUVll gap can be assigned to this address. The next available
address is xxx600S 2.
And so on.
2.7.2 Floating Vectors
Addresses between 3008 and 7748 are designated as the floating vector space. These addresses are
assigned in sequence as in Table 2-S.
Each device needs two 16-bit locations for each vector. For example, a device with one receive and one
transmit vector needs four words of vector space.
The vector assignment rules are as follows:
1.

Each device occupies vector address space equal to 'Size' words. For example, the DLV11-J
occupies 16 words of vector space. Ifits vector was 3008, the next available vector would be at
3408.

There are no gaps, except those needed to align an octal modulus.

An example of floating vector address assignment is given in Section 2.7.1.

Table 2-5

Floating Vector Address Assignments

Rank

Device

Size
(Decimal)

Modulus
(Octal)

1
1
2
2
2

DC11
TUS8
KL11
DL11-A
DLll-B

4
4
4
4
4

10
10
10
10
10

2
2
3
4
S

DLV11-J
DLVll, DLVll-F
DP11
DM11-A
DN11

16
4
4
4
2

10
10
10
10
4

6
7
8
9
10

DM11-BB/BA
DR11 modem control
DR11-A, DRV11-B
DR11-C, DRV11
PA611 (reader + punch)

2
2
4
4
8

4
4
10
10
10

11
12
13
14
IS

LPD11
DI07
DX11
DL11-C to DLV11-F
DJ11

4
4
4
4
4

10
10
10
10
10

2-20

Table 2-5

Floating Vector Address Assignments (Cont)

Rank

Device

Size
(Decimal)

Modulus
(Octal)

16
17
17
18
19

DHll
VT40
VSVll
LPSll
DQll

4
8
8
12
4

10
10
10
10
10

20
21
22
23
24

KWll-W, KWVll
DUll, DUVll
DUPll
DVll + modem control
LKII-A

4
4
4
6
4

10
10
10
10
10

25
26
27

4
4

10
10

DWUN
DMCll/DMRll
DZll/DZSll/DZVll,
DZ32
KMCll

4
4

10
10

29
30
31
32
33

LPPll
VMV21
VMV31
VTVOI
DWR70

4
4
4
4
4

10
10
10
10
10

34
35
36
37
38

RLl1/RLVll
TSll, TU80
LPAII-K
IPll/IP300
KWII-C

2
2
4
2
4

4
4
10
4
10

*
*
*

*(RXll before RX2ll)

40
41
42

RXll/RX211
RXVll/RXV21
DRII-W
DRII-B
DMPll

2
2
4

4
4
10

43
44
45
46
47

DPVll
MLll
ISBll
DMVll
DEUNA

4
2
4
4
2

10
4
10
10
4

48
49
50
51
52

UDA50/RQDXl
DMF32
KMSll
PCLII-B
VS100

2
16
6
4
2

4
4
10
10
4

(DMC before DMR)
(DZll before DZ32)

*
(MASSBUS device)

*
*

* The first device of this type has a fixed vector. Any extra devices have a floating vector.
2-21

Table 2-5

Floating Vector Address Assignments (Cont)

Rank

Device

53
54
55
56
57

TU81
KMVII
KCT32
lEX
DHVII/DHUll

Size
(Decimal)

Modulus
(Octal)

2
4
4
4
4

4
10
10
10
10

NOTE
A KL11 or DLII used as the console has a fixed
vector.
MLII is a MASSBUS device which can connect
to UNIBUS via a bus adapter.
2.8 INSTALLATION TESTING
All individual device diagnostics should be run without error before DECX!11 is used.
2.8.1 Testing in PDP-ll Systems
The following tests should be run after installation:
1.
2.
3.
4.
5.

Internal loopback
Staggered loop back
Line loopback
Modem loopback.
Keyboard echo (CVDHC only)

The self-test runs automatically when the bus or DHVII is reset. If no fault is found, the diagnostic LED
will flash OFF/ON/OFF and then come ON permanently. The first off state is very short and may not be
seen. However, ifthe LED goes off before coming on permanently the diagnostic has found no faults. This
does not prove that the option is serviceable.
During the self-test diagnostic operation, bytes are written to the FIFO. By reading these bytes, the
engineer can receive more detailed information about the state of the D HV 11. Diagnostic bytes and their
interpretation are described in Section 3 of this document. The self-test can take up to 2.5 seconds.
CVDHB? and CVDHC? have four modes of operation:
1.
2.
3.
4.

Internalloopback
Staggered loopback
Line loopback
Modem loopback.

2-22

The mode can be selected by answering a prompt from the diagnostic program. A summary of the use of
the diagnostic supervisor is provided in Chapter 5.
Test the module in the following sequence. There is a test flowchart in Section 5.9 of this manual.
1.

Switch on power, or reset the system. Check the diagnostic LED sequence.

Run the CVDH?? diagnostics for one error-free pass (CVDHB? and CVDHC? in the internal
loopback mode). Any fault message indicates a defective module.

Connect the H3277 staggered loopback connector and run CVDHB? and CVDHC? for one
error-free pass in the staggered loopback mode. Any fault message indicates a defective
DHVII or cable. Swap cables (as in Figure 5-2, configuration C) and repeat the test in order to
find the defective component.

Connect the BC05L-xx cables as for normal operation. Install an H325 line loopback
connector at line number 0 of the distribution panel. Run CVDHB? and CVDHC? in line
loopback mode on line number 0 for one error-free pass. Repeat for all lines.

Run the DECX/II exerciser to verify that the DHVII will run with other options of the
system.
NOTES
The DHVII should now be ready for connection
to external equipment See Section 2.6 if necessary,
for recommended modem and null-modem cables.
The CVDH?? diagnostics can be used, in modem
loopback mode, to check the communications
link. The modem must be set up manually. The
diagnostic will test to the point where the line is
looped back.

2.8.2 Testing in MicroVAX I Systems
The following diagnostic tests are available for testing a DHVII in MicroVAX I systems.
EHXDH
EHKMZ

DHVII Test
Macroverify-MicroVAX System Test

Macroverify is a standalone diagnostic which contains a DHVII test module. Further information is
contained in Chapter 5. Chapter 5 also contains information on testing in MicroVAX II systems.
Test the option as follows:
1.

Boot from the MicroVAX system diskette (number 2 of 2). Attach and select the DHVll
which you want to test.

Run EHXDH for three error-free passes of the internal (default) test.

Install the H3277 staggered loopback connector on the M3104 ribbon cables (see Figure 2-5).
Run EHXDH for three error-free passes of the staggered test.

Remove the H3277 and configure the DHVII for normal operation.

2-23

If you want to test the operation of a terminal link, connect the terminal line to the distribution
panel. Run the EHXDH echo test on that line until the link is proven. Depending on the type of
terminal, you may need a null modem for this test. Press CTRL/Z to exit from the echo test.

Remove all external cables and connectors from the distribution panel. Boot the CPU tests
diskette (number 1 of2). The Macroverify diagnostic runs automatically when the boot process
is complete. When the test completes, the status of all options is displayed.

Ifno device has a TEST FAILED status, the DHV11 is now ready for connection to external
equipment. If the connection is to a local terminal, you must use a null modem cable assembly.
Use the BC22A, BC22D, or BC03 P null modem cables for connection between the option and
the terminal. You can also use the H312-A null modem unit in place of null modem cables.

Use a BC22E or BC05D cable to connect the option and a modem.
Because they are not components of a DHV11 option, all of the referenced cables must be ordered
separately.
2.8.3 Testing in MicroVAX II Systems
Refer to Section 5.7 of Chapter 5, and run the maintenance version of the diagnostic as described in
Section 5.7.3. Run the DHVll test for three error-free passes.
If you want to test the operation of a terminal link, you can select the appropriate echo test from the menus.
When the echo test has completed, run the first part of the MicroVAX II diagnostic; this is option 1 on the
main menu. When this test has completed, refer to step 7 of Section 2.8.2.

2-24

CHAPTER 3
PROGRAMMING
3.1 . SCOPE
This chapter describes the CSR and control registers, and how they are used to control and monitor the
DHVII. The chapter covers:
~

•

The bit functions and format of each register
Programming features available to the host.

Some programming examples are also included.
Chapter 4, Sections 4.1 to 4.6, is recommended reading for anyone programming this device.
3.2 REGISTERS
_
The host system controls and monitors the DHVII module via several registers which are implemented in
RAM.
Command words or bytes written to the registers are interpreted and executed by the firmware. Status
reports and data are also transferred via the registers.
One of the functions of the microcomputers is to scan the registers for new instructions or data.
3.2.1 Register Access
DHVll registers occupy eight words (16 bytes) of Q-bus, memory-mapped I/O space. However, by
indexing, this is expanded on the DHVII to 114 words.
The position of the eight words within the top 4K words of memory, is switch-selected on the D HV 11. In
order to access the module, bits <12:4> of an I/O address must match the address switch coding.
Table 3-1 lists the DHVII registers and their addresses. The suffix (M) means that there are eight of these
registers; one for each channel. When an (M) register is accessed, the address (Table 3-1) is indexed by
the contents of CSR<3:0>.
NOTE
CSR <3:0> allows 16 registers to be addressed.
However, only the bottom eight registers of each
block are used. Therefore CSR bit 3 must always
be O.
The term 'Base' means the lowest I/O address on the module. That is to say, when the four low-order
address bits = O.

3-1

Table 3-1

DHVll Registers

Register
Control/Status Register
Receive Buffer
Transmit Character
Line Parameter Register
Line Status
Line Control
Transmit Buffer Address 1
Transmit Buffer Address 2
Transmit Buffer Count

(CSR)
(RBUF)
(TXCHAR)
(LPR)
(STAT)
(LNCTRL)
(TBUFFADl)
(TBUFFAD2)
(TBUFFCT)

Address (Octal)

Type

Base
Base + 2
Base + 2 (M)
Base + 4 (M)
Base + 6 (M)
Base + 10 (M)
Base + 12 (M)
Base + 14 (M)
Base + 16 (M)

Read/Write
Read Only
Write Only
Read/Write
Read Only
Read/Write
Read/Write
Read/Write
Read/Write

NOTE
It is physically possible to write to the line status
register. However, this register must not be written
by the host.
Registers are accessed by instructions which use 'base + n' as a source or destination. However, before
mUltiple (M) registers are accessed, the channel number must be written to the CSR. The following
example explains this.
To read the line status register of channel 3, the following I/O commands would be executed:
MOVB #CHAN,@#BASE
MOV @#BASE+6,RO

;WRITE CHANNEL NUMBER (SEE BELOW) TO CSR
;READ THE LINE STATUS REGISTER

In the above example:
CHAN = OerOOO 112

Where e - the RXIE bit
and r
- the MRST bit (would be 0)
and 00112 = channel number 3

'Base + 6' will address a block of 16 line status registers, only eight of which are used. The DHVll
hardware will index this address by three, thereby selecting line status register number 3.
NOTE

Not all register bits are specified. In a write
action, aU unspecified bits must be written as
Os. In a read action, unspecified bits are
undefined.

The exception to the above rule is that a bit
may be written as logical 1 or 0 if it is read as
logical 1. That is to say, read-modify-write
instructions work correctly.

3-2

3.2.2 Register Bit Definitions
Register formats which precede the definitions of register bits, are coded as follows:
•

Bits marked lie may hold data set status, or special information from the diagnostic programs.
These are covered in Section 3.3.10.

•

Registers which are modified by reset sequences are coded as shown in Figure 3-1.

CLEARED BY MASTER RESET

SET BY MASTER RESET

CLEARED BY BINIT
BUT NOT BY MASTER RESET
RD2249

Figure 3-1

3-3

3.2.2.1

Control and Status Register (CSR) -

CSR (BASE)

TX
ACTION

DIAGNOSTICS
FAILURE

TRANSMIT
INT. ENABLE

RCVE
INT.
ENABLE
(RXIE)

TRANSMIT
LINE NUMBER

RCVE DATA
AVAILABLE

TRANSMIT
DMA ERROR

INDIRECT ADDRESS REG POINTER
(CHANNEL No.)

MASTER
RESET

Bit

Name

Description

<3:0>

IND.ADDRREG
(Indirect Address
Register) (RlW)

These bits are used to select the wanted channel register when
accessing a block of indexed (M) registers. They form the binary
number of the channel which is to be accessed.

MASTERRESET
(Master Reset)
(RlW)

Set by the host, in order to reset DHV11. Stays set while DHVl1
runs a self-test diagnostic, and then performs an initialization
sequence. The bit is then cleared to tell the host that the process is
complete.
This bit is set by BINIT (bus initialization signal), or by the host
processor setting CSR<5>.
The host should not write to this bit when it is already set.

RXIE
(Receiver
Interrupt
Enable)
(RlW)

When set, this bit allows the DHVll to interrupt the host when
RX.DATA.AV AIL is set. An interrupt is generated under the
following conditions:
1.
2.

RXIE is set and a character is placed into an empty FIFO
The FIFO is not empty and RXIE is changed from 0 to 1.

Cleared by BINIT but not by MASTER.RESET.

RX.DATA.
AVAIL
(Received Data
Available) (RD)

When set, indicates that a received character is available. This bit is
clear when the FIFO is empty. It is used to request an RX interrupt.
Set after MASTER.RESET because the FIFO contains diagnostic
information.

3-4

Bit

Name

Description

<11:8>

TX.LINE
(Transmit Line
Number) (RD)

If TX.ACTION is set, these bits hold the binary number of the
channel which has just:
1.
2.
3.

Completed a DMA block transfer
Accepted a single character for transmission
Aborted a DMA block transfer.

If TX. DMA. ERR is also set, these bits contain the binary number of
the channel which has failed during a DMA transfer.
12

TX.DMA.
ERROR
(Transmit DMA
Error) (RD)

If set with TX.ACTION also set, means that the channel indicated
by CSR<II:8> has failed to transfer DMA data within 10.7
microseconds of the bus request being acknowledged, or that there is
'
a memory parity error.
TBUFF AD 1 and TBUFF AD2 registers will contain the address of
the memory location which could not be accessed. TBUFFCT will
be cleared.

DIAG.FAIL
(Diagnostic Fail)
(RD)

When set, indicates that DHVII internal diagnostics have detected
an error. The error may have been detected by the self-test diagnostic
or by the BMP.
This bit is associated with the diagnostic-passed LED. When it is set,
the LED will be off. When it is cleared, the LED will be on.
The bit is set by MASTERRESET. It is cleared after the internal
diagnostic programs have been run successfully.
It is only valid after the MASTERRESET bit CSR<5> has beencleared.

TXIE
(Transmit Interrupt
Enable) (RlW)

When set, allows the DHVII to interrupt the host when CSR<15>
(TX.ACTION) becomes set.
Cleared by BINIT but not by MASTER RESET.

TX.ACTION
(Transmitter
Action) (RD)

This bit is set by DHVll when:

The last character of a DMA buffer has left the DUART

A DMA transfer has been aborted

A DMA transfer has been terminated by the DHVII because
of nonexistent memory being addressed, or because of a
memory parity error

3-5

-Name

Bit

Description
4.

When a single-character programmed output has been
accepted. That is to say, the character has been taken from
TX.BUFF.

This bit is cleared when the CSR is read by the host.
Also cleared by MASTER.RESET.
NOTE
CSR contents should only be accessed by a MOV or MOVB
instruction. Other instructions may lose the state of the TX
ACTION bit (CSR<lS».

3.2.2.2 Receive Buffer (RBUF) - This register has the same address as the Transmit Character
register (TXCHAR). However, a READ from 'base + 2' is interpreted by the DHVl1 hardware as a
READ from the FIFO. Therefore, RBUF is a 256-character register with a single-word address. The
Least Significant Bit (LSB) of the character is in bit O.
RBUF (READ BASE + 2)

11
R

DATA
VALID

IR IR IR IR IR

IR IR IR IR

*
0
R

I
RECEIVED
CHARACTER

RECEIVE
LINE NUMBER

FRAMING
ERROR

OVERRUN
ERROR

*
7

R
9
DATA SET

(FROM HIGH BYTE
STATUS FLAGS OF STAT)

PARITY
ERROR

DIAGNOSTIC INFO

Bit

Name

Description

<7:0>

RX.CHAR
(Received
Character)

If RBUF<14:12> = 000, these eight bits contain the oldest
character in the FIFO. The character is good.

(RD)

IfRBUF<14:12> = 001,010, or 011, these eight bits contain the
oldest character in the FIFO. The character is bad.

3-6

Bit

Name

Description
If RBUF<14:12> = 111, these eight bits contain diagnostic or
modem status information. In this case, RBUF<O> has the
following meanings:
0= Modem status in RBUF<7:1> (see Section 3.2.2.5)
1 = DiagnosticinformationinRBUF<7:1> (see Section 3.3. 10).
If there is an overrun condition, the UART data buffer for that
channel will be cleared. A null character, with RBUF<14> set, will
be placed in the receive character FIFO. The cleared data will be
lost.
The DHVII does not have a break detect bit. A line break is
indicated to the program as a null character with the FRAME.ERR
set.

<11:8>

RX.LINE
(Receive
Line Number)

These bits hold the binary number of the channel on which the
character of RBUF<7:0> was received or on which a data set
change was reported.

(RD)
12

PARITY. ERR
(Parity Error)

Set if this character has a parity error and parity is enabled for the
channel indicated by bits <11:8> (also see RX.CHAR).

(RD)
13

FRAME.ERR
(Framing Error)

Set if the first stop bit of the received character was not detected (also
see RX.CHAR).

(RD)
14

OVERRUN.ERR
( Overrun Error)

(RD)

Set if one or more previous characters of the channel indicated by bits
< 11 :8> were lost because of a full FIFO or failure to service the
UARTs (also see RX.CHAR).
NOTE
The 'aliI s' code for bits <14:12> is reserved. This code indicates
that modem status or diagnostic information is held in
RBUF<7~>.
.

DATA. VALID
(Data Valid)

Set if the FIFO is not empty. Cleared by MASTER.RESET or by
the FIFO becoming empty.

(RD)
After self-test, diagnostic information is loaded into the FIFO.
Therefore this bit is always set after a successful master reset
sequence.

3-7

3.2.2.3 Transmit Character Register (TXCHAR) - Single-character programmed transfers are
made via the transmit character register. Bit function is as follows:
TXCHAR (WRITE BASE + 2)

TRANSMIT
DATA VALID

TRANSMIT
CHARACTER
AD1177

Bit

Name

Description

<7:0>

TX.CHAR
(Transmit
Character)
(WR)

Character to be transmitted. The LSB is bit O. For 7-, 6-, or 5-bit
characters, unused bits must be '0'.

TX.DATA.
VALID
(Transmit Data
Valid) (WR)

When set, instructs the DHVII to transmit the character held in bits
<7:0>. The bit is sensed by the DHVll which then transfers the
character, clears the bit, and sets TX.ACTION.
TX.DAT A. VALID and the character can be written together, or by
separate MOVB instructions.

3.2.2.4 Line Parameter Register (LPR) - This register is used to configure its associated channel.
Bit function is as follows:
LPR (BASE + 4)

rrII
15

rI I I JJI rI JJ
10

RIW RIW RIW RIW [RIW RIW RIW RIW

RIW RIW RIW RIW RIW RIW RIW

I I I I
TRANSMIT
SPEED

STOP
CODE

PARITY
ENABLE
EVEN
PARITY

RECEIVE
SPEED

3-8

CHARACTER
LENGTH

DIAGNOSTIC
CODE

Bit

Name

Description

<2:1>

DIAO
(Diagnostic
Code)
(R/W)

Diagnostic control codes. Used by the host as follows:

CHAR LOTH
(Character
Length)
(R/W)

Defines the length of characters. Does not include start, stop, and
parity bits.

<4:3>

00 = Normal operation
01 = Causes the Background Monitor Program (BMP) to report
the DHVII status via the FIFO. BMP reports are covered in
Section 3.3.10.

00 = 5 bits
01 = 6 bits
10 = 7 bits
11 = 8 bits
Set to 11 by MASTERRESET.

PARITY.ENAB
(Parity Enable)
(R/W)

Parity enable. Causes a parity bit to be generated on transmit, and
checked and stripped on receive.
1 = Parity enabled

o = Parity disabled
Cleared by MASTER RESET.
6

EVEN. PARITY
(Even Parity)
(R/W)

If LPR<5> is set, this bit defines the type of parity.
1 = Even parity

o = Odd parity

Cleared by MASTERRESET.
7

STOP. CODE
(Stop Code)
(R/W)

Defines the length of the transmitted stop bit.

o = 1 stop bit for 5-, 6-, 7-, or 8-bit characters
1 = 2 stop bits for 6-, 7-, or 8-bit characters, or 1.5 stop bits for
5-bit characters
Cleared by MASTER RESET.

<11:8>

<15:12>

RX.SPEED
(Received Data
Rate) (R/W)
TX.SPEED
(Transmitted
Data Rate)
(R/W)

Set to 1101 by MASTERRESET (9600 bits/s).
Defines the receive data rate (Table 3-2).
Set to 1101 by MASTERRESET.
Defines the transmit data rate (Table 3-2).

3-9

Table 3-2

Data Rates

Maximum
Error (%)

Groups

50
75
110
134.5

0.01
0.01
0.08
0.07

A
B
AandB
AandB

0100
0101
0110
0111

150
300
600
1200

0.01
0.01
0.01
0.01

B
AandB
AandB
AandB

1000
1001
1010
1011

1800
2000
2400
4800

0.01
0.19
0.01
0.01

B
B
AandB
AandB

1100
1101
1110
1111

7200
9600
19200
38400

0.01
0.01
0.01
0.01

A
AandB
B
A

Code

Data Rate
(Bits/s)

0000
0001
0010
0011

NOTE
The 8-channel interface uses four dual-channel
ICs. Channels 0 and 1,2 and 3,4 and S, and 6 and
7 are- paired. It is the responsibility of the user to
select transmit and receive data rates of the same
group (A or B) for any pair of channels.
Group B contains most of the commonly used
rates, therefore Imost software could use this
group only and thus avoid the problem of interaction
between adjacent"channels.
If the transmitter and receiver of a channel are configured in different groups, the group of the receiver is
selected.
If a 'pair' of channels are configured in different groups, the group of the most recently configured channel
is selected. This changes the data rate of a channel when its paired channel is reconfigured to the other
group.

3-10

3.2.2.5 Line Status Register (STAT) - The high byte of this register holds modem status information.
The low byte is undefined.
STAT (BASE + 6)

DCD

DSR

RI
(RING
INDICATOR)

ALWAYS 0

CTS

Bit

Name

Description

STAT<8>
(Status
Register, bit 8)
(RD)

Permits the software to distinguish between DHVll and DHU11.

CTS
(Clear to Send)
(RD)

Gives the present status of the Clear To Send (CTS) signal from the
modem.

0= DHVll
1 = DHUll

1 = ON
O=OFF
12

DCD
(Data Carrier
Detected) (RD)

Gives the present status of the Data Carrier Detected (DCD) signal
from the modem.
1 =ON
O=OFF

3-11

Bit

Name

Description

RI (Ring
Indicator)

Gives the present status of the Ring Indicator (RI) signal from the
modem.

(RD)
1 = ON
O=OFF

Gives the present status of the Data Set Ready (DSR) signal from the
modem.

DSR(Data
Set Ready)

(RD)
1 = ON
O=OFF

NOTE
In order to report a change of modem status, the DHVII writes
the high byte of STAT into the low byte of RBVF.
RBVF<14:12> = III to tell the host that RBVF<7:0> do not
hold a received character (see modem control, Section 3.3.8).
3.2.2.6 Line Control Register (LNCTRL) - The main function of this register is to control the line
interface.
LNCTRL (BASE + 10)
15

IRlWJ
RTS

IRIWJ RIWJRIWJ RlWJ RlWJ RlWJ RIWJ RIWJ RIWJ RIWJ

MAINTENANCE
MODE

DTR
LINK

OAUTO

FORCE.
XOFF

TYPE

DMA
ABORT

RX
ENABLE

BREAK

IAUTO
RD2248

Name

Description

TX.DMAABORT
(Transmit D~A
Abort) (RlW)

Set by the driver program to halt the transfer of a DMA buffer. The
transfer can be continued by clearing TX.DMAABORT and then
setting TX.DMASTART. No characters will be lost.
The program must make sure that TX.DMA.ABORT is clear before
setting TX.DMASTART. Otherwise the transfer will be aborted
before any characters are transmitted.
See Section 3.3.3.1,
TX.DMA.ABORT.

DMA

Cleared by MASTER RESET.

3-12

Transfers,

for

the

use

Bit

Name

Description

!AUTO
(Incoming Auto
Flow) (R/W)

This is the auto-flow control bit for incoming characters. If it is set,
the DHV11 will control incoming characters by transmitting X-ON
and X-OFF codes.
If the FIFO becomes congested, the DHV11 will send an X-OFF
code to channels with this bit set. An X-ON will be sent when the
congestion is reduced. See Auto X-ON and X-OFF, Section 3.3.6.
NOTE
An X-ON code = 218 = DCl = CTRL/Q.
An X-OFF code = 238 = DC3 = CTRL/S.
No other codes are specified for the interface.

RX.ENA
(Receiver Enable)
(R/W)

If set, this receiver channel is enabled.
If reset when this DUART channel is assembling a character, that
. character is lost.
Cleared by MASTERRESET.

BREAK
(Break Control)
(R/W)

If set, this bit forces the transmitter of this channel to the spacing
state.
Transmission is restarted when the bit is cleared.
NOTE
There is a short delay between writing the bit and the channel
changing state. The delay is dependent on throughput. Because
of the normal length of a BREAK signal, this should not cause
problems.

OAUTO
(Outgoing Auto
Flow) (R/W)

This bit is the auto-flow control bit for outgoing characters. When
set, ifRX.ENA is also set, the DHV11 will automatically respond to
X-ON and X-OFF codes received from a channel. The DHV11
uses the TX.ENA bit in TBUFF AD2 to stop and start the flow. See
Auto X-ON and X-OFF, Section 3.3.6.

FORCE.XOFF
(Force X-OFF)
(R/W)

This bit can be set by the program to indicate that this channel is
congested at the host system (for example, ifthe typeahead buffer is
full). When it sees this bit set, the DHV11 will send an X-OFF code.
Until the bit is reset, X-OFFs will be sent after every alternate
character received on that channel. When the bit is reset, an X-ON
will be sent unless. IAUTO is set and the FIFO is critical. See Auto
X-ON and X-OFF, Section 3.3.6.

3-13

Bit

Name

Description

<7:6>

MAINT
(Maintenance Mode)
(R/W)

These bits can be written by the driver or test programs, in ore
test the channel.
The coding is as follows:
00 = Normal operation
01 = Automatic echo mode - Received data is retransmitted
(regardless of the state of TX.ENA) at the data rate
. selected for the receiver. The received characters are
processed normally and placed in the received character
FIFO. In this mode, the DHVII will not transmit any
characters (this includes internally generated flow-control
characters). The RX.ENA bit must be set when operating
in this mode.
10 = Localloopback - The D U ART channel output is internally
connected to the input. Normal received data is ignored
and the transmit data line is held marking. In this mode,
flow-control characters will be looped back instead of
being transmitted. The data rate selected for the transmitter
is used for both transmission and reception. The TX.ENA
bit still controls transmission in this mode. The RX.ENA
bit is ignored.
11 = Remote loopback - In this mode, received data is retransmitted at a clock rate equal to the received clock rate. The
data is not placed in the receiver FIFO. The state of
TX.ENA is ignored. The RX.ENA bit must be set on the
respective channel.

LINK.TYPE
(Link Type)
(R/W) ,

This bit must be set if the channel is to be connected to a modem.
When the bit is set, any change in modem status will be reported via
the FIFO as well as the STAT register.
If this bit is reset, this channel becomes a 'data leads only' channel.
Modem status information is loaded in the high byte of STAT but is
not placed in the FIFO.

DTR
(Data Terminal
Ready) (R/W)

This bit controls the Data Terminal Ready (DTR) signal.
1 = ON

0= OFF
12

RTS
(Request To Send)
(R/W)

This bit controls the Request To Send (RTS) signal.
1 = ON

0= OFF

3-14

3.2.2.7 Transmit Buffer Address Register Number 1 (TBUFFADl) TBUFFAD1 (BASE + 1 2)

I I I I II

I I

IRIWJRIWJ RIWJ RlWJRIWJ RIWJ RIWJ RIWJ RIWJRlWJ RIWJRlWJ RIWJ RIWJ RIWJ RIWJ
I I I I I I I I

TXMIT DMA ADDRESS
(BITS 0 - 15)
A01178

Bit

N arne

Description

<15:0>

TBUFFAD<15:0>
(Transmit Buffer
Address [Low))

Bits <15:0> of the DMA address (see Section 3.2.2.8).

(RlW)

3.2.2.8 Transmit Buffer Address Register Number 2 (TBUFFAD2) TBUFFAD2 (BASE + 14)

I I I I I I
TXMIT
ENABLE

DMA
START

TXMIT DMA ADDRESS
(BITS 16 - 21)

Bit

Name

Description

<5:0>

TBUFFAD<21:16>
(Transmit Buffer
Address [High))

Bits <21:16> of the DMA address.

(RlW)

Before a DMA transfer, TBUFFADI and the low byte of
TBUFF AD2 are loaded with the start address of the DMA buffer.
This address is not valid during a DMA transfer. When TX.ACTION
is returned, the address will be valid.

\\
!

3-15

Bit

Name

Description

TX.DMA.START
(Transmit DMA
Start) (RlW)

Set by the host to start a DMA transfer. The DHVII will reset the bit
before returning TX.ACTION.
Cleared by MASTERRESET.
NOTE
After setting this bit, the host must not write to TBUFFCT,
TBUFFADl, or TBUFFAD2 <7:0> until the TX.ACTION
report has been returned.

TX.ENA
(Transmitter Enable)
(RlW)

When set, the DRVl1 will transmit all characters.
When cleared, the DHVll will only transmit internally generated
flow-control characters.
Set by MASTER RESET.
In the OAUTO mode, this bit is used by the DHVll to control
outgoing characters. See Auto X-ON and X-OFF, Section 3.3.6.

3.2.2.9 Transmit DMA Buffer Counter (TBUFFCT) TBUFFCT (BASE + 16)
15

DMA CHARACTER COUNT
(WHEN VALID, HOLDS No. OF CHARS. STILL TO BE SENT)

Bit

N arne

Description

<15:0>

TX.CHARCT
(Transmit Character
Count) (RlW)

Loaded with the number of characters to be transferred by DMA.
The number of characters is specified as a 16-bit unsigned integer.
After a DMA transfer has been aborted, this location will hold the
number of characters still to be transferred.
See also the previous NOTE.

3-16

3.3

PROGRAMMING FEATURES

3.3.1 Initialization
The DHVll is initialized by its on-board firmware.
Initialization takes place after a bus reset sequence, or when the host sets CSR<5> (MASTER.RESET).
Before starting initialization, the on-board diagnostics run a self-test program. The results ofthis test are
reported by eight diagnostic bytes in the FIFO.
NOTE
This self-test diagnostic can be skipped on
command from the program. This is covered in
Section 3.3.10.3.
The DHVll state, after a successful self-test, is as follows:
1.
2.
3.

Eight diagnostic codes are placed in the FIFO
The diagnostic fail bit (CSR<13» is reset
All channels set for:
a.
b.
c.
d.
e.
f.
g.
h.
i.
j.
k.

1.
m.
n.
o.
p.

Send and receive 9600 bits/ s
Eight data bits
One stop bit
No parity
Parity odd
Auto-flow off
RX disabled
TX enabled
No break on line
No loopback
No modem control
DTR and RTS off
DMA character counters zero
DMA start addresses zero
TX.DMA.START cleared
TX.DMA.ABORT cleared.

The DHV11 clears the MASTER.RESET bit (CSR<5 » when initialization and self-test are complete.
3.3.2 Configuration
After DHV11 self-initialization, the driver program can configure the DHVll as needed. This is done via
the LPR and LNCTRL registers.
By writing to the associated LPR and LN CTRL the program can select data rate, character length, parity,
and stop bit length for each channel. Individual receivers and transmitters can be enabled and auto-flow
selected.

3-17

For operation with any device which uses modem-type signals, LINK. TYPE of the associated LNCTRL
register should be set.
NOTE
If RX.ENA is reset while a receive character is
being assembled, that character will be lost

Writing to the LPR or LNCTRL registers of any
line impacts transmission performance on every
line.
3.3.3 Transmitting
Each channel of the DHVII can be programmed to transmit blocks of characters by DMA, or single
characters only. Such transfers are covered in the following three subsections. For data flow and timing
considerations see Chapter 4, Section 4.6.
3.3.3.1 DMA Transfers - Before setting up the transfer of a DMA buffer, the program should make
sure that TX.DMA.START is not set. TBUFFCT, TBUFFAD1, and TBUFFAD2 should not be
written unless TX.DMASTART is clear.
Transmission will start when the program sets TX.DMASTART.
The size of the DMA butTer, and its start address, can be written to TBUFFCT, TBUFFAD1, an,\
TBUFFAD2 in any order. However, TBUFFAD2 contains TX.ENA and TX.DMASTART, so it is
probably simpler to write TBUFF AD2 last. By using byte operations on this register, TX.ENA and
TX.DMA.START can be separated.
The DHVII will perform the transfer and set TX.ACTION when it is complete. If TXIE is set, the
program will be interrupted at the transmit vector. Otherwise, TX.ACTION must be polled.
TX.ACTION is not returned until the UART has completely transmitted the last character of the DMA
buffer.
To abort a DMA transfer, the program must set TX.DMA.ABORT. The DHVII will stop transmission,
and update TBUFFCT, TBUFFAD1, and TBUFFAD2<7:0> to reflect the number of characters
which have been transmitted. TX.DMA.START will be cleared. If the interrupt is enabled, TX.ACTION
will interrupt the program at the transmit vector. After the TX.ACTION has been returned, if the program
clears TX.DMA.ABORT and sets TX.DMA.START, the transfer can be continued without loss of
characters.
If a DMA transfer fails because of a memory error, the transmission will be terminated. TBUFF AD 1 and
TBUFF AD2 will point to the failing location. TBUFFCT will be cleared.
3.3.3.2 Single Character Programmed Transfers - Single characters are transferred via a channel's
TX. CHAR register. The character and the DATA VALID bit must be written as defined in Section
3.2.2.3. Note that the character and the DATA VALID bit can be written by separate MOVB
instructions.
The DHVII returns TX.ACTION when it reads the character from TX.CHAR. As with DMA
transfers, this bit can be sensed via interrupt or by polling the CSR.

3-18

In single-character mode, TX.ACTION is returned when the DHV11 accepts the character, not when it
has been transmitted. Each channel has a 3-character buffer. Therefore, if modem status bits or line
parameters are changed immediately after the last TX.ACTION of a message, the end of the message
could be lost. The program can prevent loss by adding three null characters to the end of each singlecharacter programmed transfer message.
3.3.3.3 Methods of Control - Examples of control by polling or by the use of interrupts are given in
Section 3.4, Programming Examples.
3.3.4 Receiving
Received characters, tagged with the channel number and DATA VALID, are placed in the FIFO buffer
(RBUF). If a character is put in an empty RBUF, the DHV11 sets RX.DAT AAVAIL. It stays set while
there is valid data in there. If RXIE is set, the program will be interrupted at the receive vector. The
program's interrupt routine sh,ould read RBUF until DATA. VALID is reset.
NOTE
The interrupt is dynamic. It is raised as
RX.DATA.AVAIL is set after RXIE, or as RXIE
is set after RX.DATAAVAIL. If the interrupt
routine does not empty the FIFO, RXIE must be
toggled to raise another interrupt.
If RXIE is not set the program must poll RBUF often enough to prevent data loss.
3.3.5 Interrupt Control
During an interrupt request sequence, assuming that interrupts are enabled, the DHV11 can provide two
vectors:
1.
2.

The 'base' vector set on the interrupt vector switches
'Base' vector +" 4.

The base vector is supplied each time da,ta is put into an empty FIFO.
The 'base + 4' vector is supplied when:
1.
2.
3.

A DMA block has been transferred.
A DMA transfer has been aborted, or terminated because of a memory error.
A single-character programmed transfer is complete.

At the two vectors, the host must provide the addresses of suitable routines to deal with the above
conditions.
3.3.6 Auto X-ON and X-OFF
X-ON and X-OFF codes are commonly used to control data flow on communications channels. To use
.
this facility, interfaces must have suitable decoding hardware or software.
A channel which receives an X-OFF stops sending characters until it receives an X-ON. A channel which
is becoming overrun by received data sends an X-OFF. It sends an X-ON when the congestion is relieved.

3-19

If the DHVII is programmed for automatic flow control (auto-flow), it can automatically control the flow
of characters. Three bits control this function:

1.
2.
3.

IAUTO
FORCE.XOFF
OAUTO

LNCTRL<I>
LNCTRL<S>
LNCTRL<4>

IAUTO and FORCE.XOFF both control incoming characters. IAUTO is an enable bit which allows the
state ofthe FIFO counters to control the generation ofXOFF and XON codes. The FORCE.XOFF bit
is a direct command from the program.
1.

The DHVII hardware recognizes when the FIFO is three-quarters full and half full. The
firmware uses these states for auto-flow control.
If the program sets a channel's IAUTO bit, the DHVII will send that channel an X-OFF ifit
receives a character after the FIFO becomes three-quarters full. Ifthe channel does not respond
to X-OFF, the DHVII will send an X-OFF in response to every alternate character received.
An X-ON will be sent when the FIFO becomes less than half full, unless FORCE.XOFF for
that channel is set. X-ONs are only sent to channels to which an X-OFF has been sent.
By inserting X-ON and X-OFF characters into the data stream, the program can perform flow
control directly. However, if the DHVII is in the IAUTO mode, the results will be
unpredictable.
InIAUTO mode, ifRX.ENAis set, X-ONs andX-OFFs will be transmitted even ifTX.ENA
is cleared.

When FORCE.XOFF is set, the DHVII sends an X-OFF and then acts as ifIAUTO is set
and the FIFO is critical (was three-quarters full, and is not yet less than half full). When
FORCE.XOFF is reset, an X-ON will be sent unless the FIFO is critical and IAUTO is set.

If the program sets OAUTO, the DHVII will automatically respond to X-ON and X-OFF
characters from the channel. It does this by clearing and setting the TX.ENA bit.
The program may also control the TX.ENA bit, so in this case it is important to keep track of
received X-ON AND X-OFF characters.
Received X-ON and X-OFF characters will always be reported via the FIFO. It is possible
during read/modify/write operations by the program, for the DHVII to change the TX.ENA
bit between the read and the write action. For this reason, ifDMA transfers are started while
OAUTO is set, it is advisable to write to the low byte of TBUFF AD2 only.
NOTES
I.

The DHVII may change the state ofTX.ENA
for up to 20 microseconds after OAUTO is
cleared by the program.

When checking for flow-control characters,
the D HV II only checks characters which do
not contain transmission errors. The parity
bit is stripped and the remaining bits are
checked for X-ON (21 8 ) and X-OFF (23 8)
codes.
3-20

Further information on automatic flow control for the DHVII is contained in Appendix D.
3.3.7 Error Indication
The program is informed of transmission and reception errors by means of four bits:
1.
2.
3.
4.

TX.DMA.ERR
PARITY. ERR
FRAME.ERR
OVERRUN. ERR

CSR<12>. See Section 3.2.2.1
RBUF<12>. See Section 3.2.2.2
RBUF <13>. See Section 3.2.2.2
RBUF <14>. See Section 3.2.2.2.

RBUF<14:12> are also used to identify a diagnostic or modem status code.
3.3.8 Modem Control
Each channel of the module provides modem control bits for R TS and DTR. Also on each channel are
modem status inputs CTS, DSR, RI, and DCD. These bits can be used for modem control or as general
purpose outputs and inputs (see STAT register, Section 3.2.2.5).
CTS, DSR, and DCD are sampled by PROC2 every 10 ms. Therefore, for a change to be detected, these
bits must stay steady for at least 10 ms after a change. RI is also sampled every 10 ms, but a change is not
reported unless the new state is held for three consecutive samples. There are no hardware controls
between the modem control logic and the receiver and transmitter logic. Any coordination should be done
under program control. Modem status change reports are placed in the received character FIFO at the
correct position relative to the received characters.
By setting LINK. TYPE (LNCTRL<8> ), a channel can be selected for modem operation. Any change of
the modem status inputs will be reported to the program via the received character FIFO. Modem control
bits must be driven by the program's communication routines. Control bits are written to LNCTRL.
Appendix B gives more detail of modem control.
By clearing LINK. TYPE 'the channel is selected as a 'data lines only' channel. Modem control and status
bits can still be managed by the program but status bits must be polled at the line status register. Changes of
modem status will not be reported to the program.
NOTE
When transmitting by the single-character
programmed transfer method, up to three
characters can be buffered in DHV11 hardware.
If modem control bits are to be changed at the end
of a transmission, three null characters should be
added. When TX.ACTION is set after the third
null character, the last true character has left the
UART.
Status change reporting is done via the FIFO as follows:
•

When OVERRUN. ERR, FRAME,ERR, and PARITY. ERR are all set, the eight low-order
bits contain either status change or diagnostic information. In this case:
•

IfRBUF<O> = 0, RBUF<7:1> holds STAT<15:9> (see Section 3.2.2.5).

•

IfRBUF<O> = 1, RBUF<7:1> holds diagnostic information (see Section 3.3.10).

3-21

3.3.9 Maintenance Programming
As well as using on-board and external diagnostic programs, the host can also test each channel directly.
Bits 7 and 6 of LN CTRL allow each channel to be configured in normal, automatic echo, localloopback,
and remote loopback modes (see LNCTRL Section 3;2.2.6).
The host must provide suitable software to test these configurations.
3.3.10

Diagnostic Codes

3.3.10.1 Self-Test Diagnostic Codes - After bus reset or master reset, the DHV1I executes a self-test
and initialization sequence. At the end of the sequence, eight diagnostic codes are put in the FIFO.
RX.DATA.AVAIL is set and MASTER.RESET is cleared.
After an error-free test, DIAG.F AIL will be reset. The 'diagnostic passed' LED will be on. If an error is
detected, DIAG.FAIL will be set and the LED will be off.
An example program whic~ reads and checks the diagnostic codes from RBUF, is included in Section 3.4.
3.3.10.2 Interpretation of Self-Test Codes - The high byte of diagnostic codes in RBUF can be
interpreted as in Section 3.2.2.2, except that bits <11:8> are not the line number. They indicate the
sequence of the diagnostic byte. That is to say, 0 = first byte, 1 = second byte, and so on.
Figure 3-2 shows how the diagnostic code in the low byte ofRBUF, should be interpreted. Table 3-3 gives
the meaning of each implemented diagnostic byte.
D7

DIAGNOSTIC STATUS BYTE

1- 0 = MODEM STATUS CODE

c: =
1

DIAGNOSTIC CODE

IF D7 = 1, THEN:
0= PROC1 SPECIFIC ERRORS IN D4- D2
1 = PROC2 SPECIFIC ERRORS IN D4- D2

IF 07 = 1, THEN:
1----- 0 ::= SELF-TEST CODE IN 05- D1
L - - -___

1 = BMP CODE IN 05-D1

= ROM VERSION IN 06-02, D1 IS THE PROC No.
1 = DIAGNOSTIC CODE IN 06-01

1 - - -...... 0
L . . . - _......

RDt 163

Figure 3-2 Diagnostic/Status Byte

3-22

Table 3-3
Code
(Octal)
201
203
211
213
217
225
227
231
233
235
237

DHVII Self-Test Error Codes

Test
Self-test null code (used as a filler)
Self-test skipped
Basic data path error from PROC2
Undefined UART error
Received character FIFO, logic error
PROC 1 to common RAM error
PROC2 to common RAM error
PROCI internal RAM error
PROC2 internal RAM error
PROCI ROM error
PROC2 ROM error

If D7 = 0 and DO = 1, ROM version number is in D6 - D2.
Dl = PROC number (0 = PROCl)
NOTE
Codes not shown in this table indicate undefined
errors.
After self-test, the eight codes in the FIFO will consist of six diagnostic codes and two ROM version
codes. If there are less than six errors to report, null codes (201 8) fill the unused places.
After an error-free test, six null codes and two ROM version codes will be returned.
If self-test is skipped (see next section), six 203 8 codes and two ROM version codes will be returned.
3.3.10.3 Skipping Self-Test - Self-test takes up to 2.5 seconds to complete. Depending on system
software, this may cause a 2.5-second hangup. The Skip Self-Test facility allows the program to bypass
the self-test diagnostic.
Skipping self-test is done as follows:
1.

The program resets the DHV11

The diagnostic firmware writes 125252 8 throughout the common RAM within eight
milliseconds (ms) of reset

The program waits 10 ms ( + or - 1 ms) after issuing reset. It then writes 052525 8throughout the
control registers (not the CSR), within the next 4 ms

3-23

The diagnostic firmware waits until 16 ms after reset. It then checks for a 052525 8 code in
common RAM.
If it finds the code, self-test is skipped. The DIAG.F AIL bit is cleared and control is passed to
the communications firmware which starts initialization.

If the code is not found, self-test starts.
NOTE
The program must not write to the CSR or the
control registers during the period starting 15 ms
after reset and ending when the MASTER.RESET
bit is cleared. This could cause a diagnostic fail
condition.
3.3.10.4 Background Monitor Program(BMP) - When not busy with other tasks, the DHVII 's
microcomputers perform background tests on the option. This is done by checking the timer-generated
interrupts used by the firmware (one interrupt in PROCI and two in PROC2). One of two codes is
returned to the FIFO:
3058 3078 -

DHVll running
DHVl1 defective.

A single diagnostic word is returned via the FIFO. The low byte contains the diagnostic code. In the high
byte, OVERRUN. ERR, FRAME.ERR, and PARITY. ERR are all set to indicate that bits<7:0> do not
hold a normal character. The line number (RBUF< 11 :8» = O.
IfPROC2 stops running, PROCI will set DIAG.FAIL and will tum off the LED. The LED will stay off,
even if the fault clears. If PROCI stops running, PROC2 will load a 307 code into the FIFO.
Normally, the BMP will only report when it finds an error. However, if the program suspects that the
DHVII is not working it can get a BMP report at any time. This is done by setting DIAG (LPR <2: 1» of
any channel to 0 1. The line number returned is that of the LPR used to request the report.
On completion of the, check, the BMP will clear the 01 code in DIAG. The host should not write to the
LPR of that channel until DIAG has been cleared.
3.4 PROGRAMMING EXAMPLES
This section contains programming examples. They are not given as the only method of driving the option.
These programs are not guaranteed or supported.
3.4.1 Resetting the DHVll
In the following example:
•

DIAG is a routine to check the diagnostic codes. It returns with CARRY set if it detects an
error code (see Section 3.3.10).

•

The loop at 1$ can take up to 2.5 seconds, so the programmer could poll via a timer or poll at
interrupt level zero.

3-24

A ROUTINE TO RESET THE DHVll AND CHECK THAT IT IS FUNCTIONING
CORRECTLY.
NOTE: A SOPHIS'rrCATED PROGRAM WOULD TIME OUT AFTER 3 SECONDS
IF THE RESET DID NOT COMPLETE.
DHVRES: :
1$:

2$:

MOV

#40,@#DHVCSR

BIT
BNE
BIT
BNE

#40,@#DHVCSR
1$
#20000,@#DHVCSR
DIAGER

MOV

18. , R5

MOV
J'SR
BCS

@#RBUFF,R0
·PC,DIAG
DIAGER

SOB

R5,2$

SET MASTER. RESET AND
CLEAR INTERRUPT ENABLES.
WAIT FOR MASTER. RESET TO
CLEAR.
CHECK THE DIAGNOSTICS FAIL
BIT.
NOTE: TEST INSTRUCTION IS
OK BECAUSE THERE ARE
NO TX.ACTS PENDING.
PROCESS THE EIGHT SELF
TEST CODES.
GET NEXT DIAGNOSTIC CODE.
PROCESS rf.
CARRY SET - MUST HAVE BEEN
AN ERROR.
GO BACK FOR NEXT CODE.

RTS

RETURN - CARD IS RESET.

DHVll HAS FAILED TO RESET PROPERLY, SO HALT AND WAIT FOR
THE FIELD SERVICE ENGINEER.
DIAGER: HALT
BR

DIAGER

3.4.2 Configuration
This routine sets the characteristics of channel 1 as follows:
1.
2.
3.
4.
5.

Transmit and receive at 300 bits/s
Seven data bits with even parity and one stop bit
Transmitters and receivers enabled
No modem control
No automatic flow control.
SET CHARACTERISTICS OF CHANNEL 1 TO THE FOLLOWING STATE:1)

TRANSMIT AND RECEIVE AT 300 B.P.S.

7 DATA BITS WITH EVEN PARI'fY AND ONE STOP BIT.

TRANSMITTERS AND RECEIVERS ENABLED.

NO MODEM CONTROL.

NO AUTOMATIC FLOW CONTROL.

3-25

SETUP:
:
/

3.4.3

MOV

#1,@#DHVCSR

MOV

#IIl5256~, @iLPR

MOV
MOVB

#4 , @tLNCTRL
*2~~,@iTBFAD2+1

SELECT THE LINE WE'RE
IN'rERESTED IN.
DATA RATE, STOP BITS,
PARITY AND LENGTH
ENABLE THE RECEIVER.
ENABLE THE TRANSMITTER.

RTS

RETURN - CHANNEL 1 DONE.

Transmitting

3.4.3.1 Single Character Programmed Transfer - This is a program to send a message on channell.
The message (MESS) is an ASCII string with a null character as terminator.
Polling is used but a TX.ACTION interrupt could also be used.
This program would function on a DHVll with only this channel active. Otherwise it would lose
TX.ACTION reports of other channels. However, a program to control all channels would be too big to
use as an example.
A ROUTINE TO WRITE A MESSAGE TO CHANNEL 1 USING SINGLE CHARACTER
MOI?E.
SINGOT: :
POINT TO CHANNEL WE WISH
TO TALK TO.
POINT TO MESSAGE.

MOV

U,@#DHVCSR

MOV

*MESS,R~

MOVB
BEQ
MOVB

MOV
BPL

@#DHVCSR,Rl
2$

WAIT FOR TX.ACT

BIC
CMP
BNE

U7~377,Rl

ISOLATE CHANNEL NUMBER.

IGNORE THE TX.ACT IF ITS
NOT OURS (SHOULDN'T HAPPEN)
GO BACK FOR NEXT CHARACTER.

RTS

MESSAGE SENT.

.ASCIZ
.EVEN

/A SINGLE CHARACTER MESSAGE FOR CHANNEL 1/

1$:
(R~) +, @ltTXCHAR

MOVE CHARACTER TO TRANSMIT BUFFER
GO RETURN IF ALL CHARACTERS GONE.
SET DATA VALID BIT TO START.

*2~~,@ltTXCHAR+l

2$:

#IIl~~4~0,Rl

3$:

MESS:

3-26

3.4.3.2 DMA TransferTHIS PROGRAM SENDS A~SAGE OUT ON EACH LINE OF THE DHVll AND
HALTS THE MACHINE WHEN ALL TRANSMISSIONS HAVE COMPLETED.
THE MESSAGES ARE TRANSMITTED USING DMA MODE, AND INTERRUPTS ARE
USED TO SIGNAL TRANSMISSION COMPLETION.
DMAINT: :
MOV
MOV

tTXINT, @fI:TXVEc'r
t2f3f3,@#TXPSW

SET UP THE INTERRUPT VECTORS.
INTERRUPT PRIORITY FOUR.

MOV
CLR

#8. , Rf3
Rl

EIGHT LINES TO START.
START AT LINE ZERO.

MOVB
MOV
MOV
MOV

Rl,@#DHVCSR
#DMASIZ,@tTBFCNT
tDMAMES,@#TBFADl
#lf3f32f3f3,@tTBFAD2

INC
SOB

Rl
Rf3,l$

SELECT THE REGISTER BANK.
SET LENGTH OF MESSAGE.
SET LOWER 16 ADDRESS BITS.
START DMA WITH TRANSMITTER
ENABLED (ASSUME UPPER ADDRESS
BITS ARE ZERO).
POINT TO NEXT CHANNEL.
REPEAT FOR ALL LINES.

CLR
MOVB

R5
It 10f3,@ltDHVCSR+l

R5 IS USED BY INTERRUPT ROUTINE.
ENABLE TRANSMITTER INTERRUPTS.

CMP
BNE

#8. , R5
2$

WAIT FOR ALL LINES TO FINISH.

HALT
BR

1$:

2$:
3$:

ALL DONE, SO STOP.

TRANSMITTER INTERRUPT ROUTINE.
R5 IS INCREMENTED AS EACH LINE COMPLETES.
TXINT: :
MOV
BIT
BNE

@fI:DHVCSR,RI3
4$

GET LINE NUMBER OF FINISHED LINE.
CHECK FOR DMA FAILURE.
GO HALT - MEMORY PROBLEM.

INC
RTI

FLAG THAT ANOTHER LINE HAS FINISHED.

HALT
BR

#10f3fi,,~,R0

4$:

DMAMES: .ASCII
DMASIZ =
.EVEN

MEMORY PROBLEM
<15><12><7><7><7>/SYSTEM CLOSING DOWN NOW/
.-DMAMES

3-27

3.4.3.3 Aborting a DMA TransferTHIS ROUTINE IS CALLED TO ABORT A DMA TRANSFER IN PROGRESS ON A
SPECIFIED LINE.
THIS ROUTINE MAKES THE (RATHER RASH) ASSUMPTION
THAT THERE ARE NO OTHER TRANSFERS IN PROGRESS.
ON ENTRY, R0 CONTAINS THE NUMBER OF THE LINE TO BE ABORTED.
DMABRT: :

3.4.4

MOV
BIS

R0,@tDHVCSR
U,@tLNCTRL

POINT TO THE CHANNEL TO BE ABORTED.
SET THE DMA ABORT BIT.

MOV
BPL
SWAB
BIC
CMP
BNE

@fDHVCSR,Rl
1$
Rl
U 77760, Rl
R0,Rl
1$

WAIT FOR THE TX.ACT

BIC

U ,@tLNCTRL

CLEAR DOWN THE ABORT FLAG
FOR NEXT TIME.

RTS

BUFFER COMPLETELY ABORTED,
THE DMA REGISTERS REFLECT
WHERE THE DHVll GOT TO.

CHECK ITS OUR LINE.
IGNORE IT IF ITS NOT (OUR
ASSUMPTION WAS WRONG!)

Receiving

THIS ROUTINE PROCESSES RECEIVED CHARACTERS UNDER INTERRUPT CONTROL.
IF AN XOFF IS RECEIVED, TH~ TRANSMITTER FOR THAT CHANNEL IS TURNED
OFF. IF AN XON IS RECEIVED, THE TRANSMITTER IS TURNED BACK ON. ALL
OTHER CHARACTERS ARE IGNORED.
THIS IS JUST AN EXAMPLE, A BETTER WAY TO PERFORM FLOW CONTROL IS TO
USE THE AUTOMATIC CAPABILITIES OF THE DHVll.
RXAUTO: :
MOV
MOV

tRXINT,@tRXVECT
t200,@fI:RXPSW

SET UP THE INTERRUPT VECTORS.
PRIORITY LEVEL FOUR.

MOV
CLR

t8. ,R0
Rl

ENABLE ALL THE RECEIVERS,
STARTING AT CHANNEL ZERO,

MOVB
BIS
INC
SOB

Rl,@tDHVCSR
t4,@#LNCTRL
Rl
R0,1$

SELECT THE CINE.
ENABLE THIS RECEIVER.
SET POINTER TO NEXT CHANNEL.

MOVB

U00,@fI:DHVCSR

ENABLE THE RECEIVER INTERRUPTS.

RTS

RETURN - INTERRUPTS DO THE RESET.

1$:

INTERRUPT ROUTINE TO DO THE MAIN TASK.

3-28

RXINT: :
MOV

RI2I,-(SP)

SAVE CALLERS REGISTERS.

MOV
BPL
MOV
BIC
BNE

@#RBUFF,RI2I
RXIEND
RI2I,-(SP)
#11217777, (SF) +
RXNXTC

GET THE CHARACTER.
IF NO DATA VALID, WE'VE FINISHED.
CHECK FOR ERRORS, MODEM AND
DIAGNOSTICS CODES.
- JUST IGNORE THEM.

BIC
SWAB
BIS
MOVB
SWAB
CMPB
BNE

U 71212121121, RI2I
RI2I
UI2lI2l,Rr2I
RI2I,@fDHVCSR
Rr2I
f21,RI2I
1$

REMOVE UNNECESSARY BITS.
POINT TO THIS CHARACTERS LINE.
(ADD THE INTERRUPT ENABLE BIT.)

BISB
BR

f2r21r21,@iTBFAD2+1
RXNXTC

ENABLE THE TRANSMITTER.
GO CHECK FOR MORE CHARACTERS.

CMPB
BNE

f23,Rr2I
RXNXTC

WAS IT, AN "XOFF"?
NO - GO CHECK FOR MORE CHARACTERS.

BICB
BR

f2121121,@iTBFAD2+1
RXNXTC

DISABLE THE TRANSMITTER.
GO CHECK FOR MORE CHARACTERS.

MOV
RTI

(SP)+,Rr2I

RESTORE THE DESTROYED REGISTER.

RXNXTC:

PUT CHARACTER BACK IN LOWER BYTE.
WAS IT AN "XON"?
NO - GO CHECK FOR AN "XOFF"

1$:

RXIEND:

3.4.5 Auto X-ON and X-OFF
THIS PROGRAM SENDS A MESSAGE OUT ON EACH LINE OF THE DHV11 AND
HALTS THE MACHINE WHEN ALL TRANSMISSIONS HAVE COMPLETED.
THE MESSAGES ARE TRANSMITTED USING DMA MODE, AND INTERRUPTS ARE
USED TO SIGNAL TRANSM-ISSION COMPLETION.
AUTOMATIC FLOW CONTROL IS ENABLED ON THE OUTGOING DATA.
TXAUTO: :

1$:

MOV
MOV

fATOINT,@iTXVECT
i2121r21,UTXPSW

SET UP THE INTERRUPT VECTORS.
INTERRUPT PRIORITY FOUR.

MOV
CLR

f8. , RI2I
Rl

EIGHT LINES TO START.
START AT LINE ZERO.

MOVB
BIS

R1,@#DHVCSR
f24,@#LNCTRL

MOV
MOV
MOV

fAUTOSZ,@#TBFCNT
#AUTOMS,@#TBFAD1
#11211212121r21,@#TBFAD2

INC
SOB

Rl
RI2I,1$

SELECT THE REGISTER BANK.
ENABLE AUTOMATIC FLOW CONTROL
ON THE TRANSMITTED DATA.
SET LENGTH OF MESSAGE.
SET LOWER 16 ADDRESS BITS.
START DMA WITH TRANSMITTER
ENABLED (ASSUME UPPER ADDRESS
BITS ARE ZERO).
POINT TO NEXT CHANNEL.
REPEAT FOR ALL LINES.

CLR
MOVB

R5
Ur2Ir2I,@#DHVCSR+1

R5 IS USED BY INTERRUPT ROUTINE.
ENABLE TRANSMITTER INTERRUPTS.

3-29

2$:
CMP
BNE

i8. , R5
2$

HALT
BR

WAIT FOR ALL LINES TO FINISH.

3$:
ALL DONE, SO STOP.

;'
~

TRANSMITTER INTERRUPT ROUTINE.
R5 IS INCREMENTED AS EACH LINE COMPLETES.

ATOINT: :
MOV
BIT
BNE

@#DHVCSR, R~
4$

GET LINE NUMBER OF FINISHED LINE.
CHECK FOR DMA FAILURE.
GO HALT - MEMORY PROBLEM.

INC
RTI

FLAG THAT ANOTHER LINE HAS FINISHED.

U~~~~, R~

4$:
HALT
BR
AUTOMS: .ASCII
AUTOSZ =
.EVEN

MEMORY PROBLEM
4$
<15><12><7><7><7>/SYSTEM CLOSING DOWN NOW/
.-AUTOMS

3.4.6 Checking Diagnostic Codes
THIS ROUTINE CHECKS THE DIAGNOSTICS CODES RETURNED FROM THE DHVII.
ON ENTRY, R0 CONTAINS THE CHARACTER RECEIVED FROM THE DHVII.
ON EXIT, THE CARRY BIT WILL SE'CLEAR FOR SUCCESS, SET FOR FAILURE.
DIAG: :
SAVE THE CODE FOR LATER.

MOV

R~, -

SIC
CMP
BNE

U07776,R~
U70~~1,R~

CHECK THAT IT'S A DIAG. CODE.

DIAGEX

IF NOT, JUST EXIT NORMALLY.

MOV

(SP) , R~

GET THE CODE

i2~~,R~

CHECK FOR ROM VERSION NUMBER.

BITB
BEQ
CMPB
BEQ
CMPB
BEQ
CMPB
BEQ

(SP)

S~C~.

DIAGEX
i2~1,R~

SELF TEST NULL CODE.

DIAGEX
i2~3,R~

SELF TEST SKIPPED CODE.

DIAGEX
i3~5,R~

DHV RUNNING CODE.

DIAGEX
ALL THE REST ARE ERROR CODES.

SEC
BR

AN ERROR CODE WAS RECEIVED, SO
SET THE CARRY FLAG.

DIAGXX

3-30

DIAGEX:
EVERYTHING OK, SO CLEAR CARRY.

CLC
DIAGXX:
MOV
RTS

3.4.7

RESTORE THE CHARACTER/INF~.

(SP)+,R"
PC

Modem Control

THIS ROUTINE WILL ANSWER A MODEM CALL, PRINT OUT A MESSAGE AND
HANG UP THE PHONE.
DMA MODE IS USED. IF SINGLED CHARACTER MODE WERE USED, THEN
THE MESSAGE WOULD NEED TO BE PADDED OUT WITH THREE NULLS DUE
TO INTERNAL BUFFERING OF THE DHVll.
MODEM: :
MOV
CLR

#8. ,R"
Rl

SET UP ALL CHANNELS FOR MODEMS.

MOVB
MOVB
MOV
INC
SOB

Rl, @#DHVCSR
#125,@#LPR+l
#4 1313, @#LNCTRL
Rl
R",l$

POINT TO CHANNEL TO BE SET UP.
3"" BPS DATA RATE.
SET MODEM DISABLE RECEIVER.
POINT TO NEXT CHANNEL.
SET UP ALL CHANNELS.

MOV
MOV
MOV
MOV
MOV

#MRXINT,@#RXVECT
#213", @#RXPSW
#MTXINT,@#TXVECT
#21313, @#TXPSW
#4" 1 "", @#DHVCSR

SET UP INTERRUPT VECTORS.
(INTERRUPT LEVEL FOUR)

LET INTERRUPT ROUTINES DO EVERYTHING

ENABLE THE INTERRUPTS.

TRANSMITTER INTERRUPT ROUTINE.
MTXINT:
MOV
MOV
SWAB
BIC
BIS
MOVB
MOV
MOV
RTI

SAVE THE REGISTER WE USE.
GET INTERRUPTING LINE NUMBER.
SELECT THIS CHANNELS REGISTERS.

RO,-(SP)
@l/DHVCSR,RO
RO
#177760,RO
IllOO,RO
RO,@#DHVCSR
#400, @/ILNCTRL
(SP)+,RO

(RETAIN INTERRUPT ENABLE)
DROP DTR, RTS AND CLEAR ABORT.
RESTORE THE REGISTER WE USED.

3-31

RECEIVER INTERRUPT ROUTINE.
MRXINT: :
MOV

RO,-(SP)

SAVE THE REGISTER WE USE.

MOV
BPL
MOV
BIC
CMP
BNE
MOV
SWAB
B1:C
BIS
MOVB

@IIRBUFF,RO
MRXEND
RO,-(SP)

GET INTERRUPTING LINE.
EXIT IF ALL DONE •.
SAVE FOR LATER USE.
TEST FOR MODEM INFO.

MRXNXT
(SP),RO
RO
1I177760,RO
IIlOO,RO
RO,@IIDHVCSR

SKIP IF NOT.
SELECT REGISTERS FOR THIS LINE.

MOV
BIC
CMP
BNE
BIC

(SP),RO
11177547,RO
11230, RO
1$
III , @IILNCTRL

CHECK FOR READY FOR TRANSMISSION.

MOVB

1123,@IILNCTRL+l

MOV
MOV
MOV
BR

IINOSYSZ,@IITBFCNT
IINOSYS,@IITBFAD1
IIl00200,@IITBFAD2
MRXNXT

BIT
BEQ
MOVB
BR

11200, RO

MRXLOP:

11107776,RO
11070000, RO

(RETAIN INTERRUPT ENABLE)

DSR, DCD & CTS NOT SET, TRY START.
CLEAR DOWN ABORT BIT (IN CASE WE
SET IT WITHOUT A DMA IN PROGRESS).
ASSERT RTS IN CASE CTS AND DSR
WERE ASSERTED AT THE SAME TIME.
OUTPUT MESSAGE.
(TRANSMITTER INTERRUPT ROUTINE
CLEARS DOWN THE CALL.)
GO LOOK FOR MORE.

1 $:

CHECK FOR DSR.
NO - GO CHECK FOR NEW CALL.
ASSERT RTS.
GO LOOK FOR MORE.

2$
1123,@IILNCTRL+l
MRXNXT

2$:
BIT
BEQ
MOVB
BR

3$
113,@IILNCTRL+l
MRXNXT

CHECK FOR RING INDICATOR.
NO - GO CLOSEDOWN CALL.
ASSERT DTR.
GO LOOK FOR MORE.

BISB
MOVB

Ill, @IILNCTRL
Ill,@IILNCTRL+l

ABORT ANY CURRENT DMA TRANSFERS.
DROP MODEM SIGNALS.

TST
BR

(SP)+
MRXLOP

REMOVE SIGNALS FROM THE STACK.
GO ROUND AGAIN.

MOV
RTI

(SP)+,RO

RESTORE THE REGISTER WE USED.

.ASCII

<15><12><7><7><7>/SYSTEM UNAVAILABLE, PLEASE TRY LATER/
.-NOSYS

1140,(SP)

3$:
MRXNXT:
MRXEND:

NOSYS:
NOSYSZ

.EVEN

3-32

CHAPTER 4
TECHNICAL DESCRIPTION
4.1 SCOPE
This chapter describes:

•
•
•
•
•
•

Operation of the main hardware blocks
Data flow
Control of address and data
Operation of the microcomputers
Use and control of the RAM
Internal diagnostics.

The chapter starts with a description at block diagram level. This is followed by a section on data flow, and
then specific areas are described in more detail. A basic description of the DHVII 's ROM-based
diagnostics completes the chapter.
It is a~sumed that the reader has read Chapter 3, Sections I, 2, and 3 of this document.
I

Refer to Figure 4-1 throughout this description.
4.2 Q- BUS INTERFACE
The simplified block ofthe Q-bus interface in Figure 1-5 is expanded in Figure 4-1. The interface is made
up of all the components between the external and internal buses.
DC005 bus transceivers control the address and data lines BDAL<17:0> and BAL<21:18>. Bus
transceivers also:
I.
2.

Recognize device addresses
Provide vectors during interrupt sequences.

When (I) the DHVll is bus slave, access to the DHVll is allowed when BBS7 is asserted (I/O
operation) and BDAL< 12:4> 'matches' the address on the module address switches. By this means, the
DHVII recognizes a valid device register address. Transceiver direction is controlled by BDIN and
BDOUT, which indirectly generate XMIT.H and REC.H. The 'match' condition generates the signal
MATCH.
In an interrupt acknowledge cycle (2), the DC003 interruptIC responds to BIAKI. The signal VECTOR
enables the vector switches onto the BDAL lines via the DC005 s. VECT.2.H is the low bit ofthe vector
address. It identifies a receive (0) or transmit (I) interrupt vector. VECTOR also generates BRPLY via
DC004 protocol logic.

4-1

~RE~Q~---------------------~I DMAREQ I~_ _ REQ

r--

BDMGI
BDMGO
BINIT

I - - - DATIN
I---DATIO
r--MASTER
r--ADREN
r--DATEN
r--DIN
r - - DOUT

DC010
DMA
CONTROL

BDMR
BRPlY
BSYNC

ClK

I
r---,
r-- I
~ a ~-----------~~~~~~~~--lATCH

AD<7:

I~_ -

P1AD<7:0> & P1A<15:8>

I ~ 'I I - I
A~<7:0> I I
~

r-r

T.! II

I--

I/'-~B~DA:;::l~" BUS

1'--_ _--..I'Ir-RANSCEIVER~

::;-

...

BDAl

Llv'j," ~

r I-=--JT rT
~

DC005

AD<3:1>

INPUT

L_~_~

,--

A.P<,7:0> ;

D<7:0>

LATO

'v--~ (") IV/////////////////

I
~
r--------~--:--.Il ~
I I
A~1D5:8> ~
~

L0T~E~

"""="

g§
a:

1-_.:..:A::.D1.:..:6::.-_-.I

<C <12,11 & 10-; I __
DC_0_0_5_1;-."-,...----..J...Jl..l

.....

1ADDRESS
DMA
1

1 ffi
~
I

~I,~N~D~<3~:~0>~~I_~~

~______..J.I_~~~ ~ ~

I ...::.. I

1;-1-

DC005
<9,8,7 & 1-:; t------LL:J_~JI
BDAl

;11

L'-- J
__-_-----'

r---r- &l

~---~I.:-I~rT
,rT"1
~

<6,5,4 & 0>
BDAl

r--_ _ _ _

AD<21 r I .: 1. 6>
1/......

t--

ADDRESS ......
BITS
~
9'& 8=00

II §if'I

I
v-:".

•

D<15:8>
Lo::;.::;;..::l~~I.....!.I
......... ~ ~
2

I\!ECTOF

BBS7L

1I i

r---

AD<15 ~
IDMA DATAl
~ ~ I~~~LA
__
TC_H_E_S~~

MODULE
ADDRESS
SWITCHES

VECTOR
SWITCHES

(FROM PROe1)

AD17

'"""'--

A<7:0>

I""

MEM

D<15:8>

~:2 ~OR

2:.E.

(J)

AD<15:0>

...:

~ I<#////////.o'////"

-=- I

v--r----I

A<15:8>1

w <15,14 & 13> 1----~1'v-----.""'1.../1
1----------y--r-T"'1r----.---::-:-:==-----~1I ~
~
BAl
~N
<c
1 OUTPUT
u

-'~~

£ <21,20,17 &' 1----~rv---rTv'I ~
-

BAl 16>

1ii

~ <19,18,3&2>

: :J

lj:!

DC005

XMIT.H
L - - - - + - REC.H

BDOUT
BDIN
BRPlY

AD<3:0>T"

-oUTHB

v~~iJ~
_I

SElO _ _

AD15

I
I
1

TX
ACTION
lATCH

r--

L-~L...L-'" ~

(")

_~ <13 :8>

~ r--_
~) ~
I

BIAKI

DC003
INTERRUPT
lOGIC

BIAKO

I:=}
t:=}

,H
1

,L--

PORT B
INITO

TXIE
RXII:

Figure 4-1
4-2

DRV11 Block Diagram

TX ACTION (P1108.l)

FIFO
CONTROL

~
~
SDAT::%~

aE:15

SDAT14
r"'L--- & <6:0>
I RX.DATA. A~All

:2 u.

I-

(FIFO NOT EMPTY)

~ ~I

MREm

_I-----L§JSDAT 15

I
I

MASTER
RESET
lATCH

----t
I
I
-

~ ~

,..--- _

PORTA

~ ~ ~...0'§/0

VECTOR
VEC

~...:A::::D~5~_ _ _ _ _ _ _ _ _ _ _ 1 _

BINIT

~
~

SDAT
i"///

L _ I - - _ _ ~~ _ _
BIRQ

STROBE
__

-.....

AD<2:0>, _1_

IZ II

CSR

ADDRESS .......-.--.--......
REGISTER

I ~-~
I
~
~
I

W////////////.o'/h

--l

SEl 0

EN -INWD
DC004
PROTOCOL
lOGIC

8 L-_.!....
I_.L...II'I INDIRECT ~---L...L.......J

BWTBT
BSYNC

ICSR

MATCH

1:j

U:::J

I__ ~

LiA~ES

DMA COMPLETE -L"'7"""-~--P2 CHANGE
FLAG

r-----'

~~ ~ I
, 9&8~ f::
~ r;;"1 J;;["\ i I
r-

BITS

c=: :~; ~"'\'-'~~~J
-"

<t
~

SAO<90>

,'1
"l'"
l"\
l"

~C~

I I
II
~
~
I, , T ~~ I
-

INTO
PROC1
(DMAIINTERRUPT)
S051

DMAIMEMERROR-

<15:S>

--I

CSR STROBE

PROC1)

0< : >

INPUT DATA
LATCHES

A<7:0J -

D<15:S>

["\.

l"
["\
["\

r, , '\.

RAM
ADDRESS
l!;TCHES
I
PROCl ........J

["\.

. . . '"l"
L '

i~~~

'OAHS,O>

~ I ~I

....,

I ~

CONVERTER

1
'//LZq~
BUS

SDAT<15:0>

SAD<S:O>

- -l

"'"

t'-

~ ...-

'"wo'o

\... "

COMMON RAM

SAO<9,0>

f%: '\ '\. '- '-

(BUS)

RDIWR

..,...,

~
["~
~~
"":::"_"~~~
,~'-~~ ,~
~"'. ~'~
'"

(S,M.P.S.)

GRANT r
I ----1-..1R!EE~O_ PROC1
PROC1 - GRANT STORE
REO _ PROC2
PROC2
GRANT ARBITRATOR
REO
HOST

["\

~~~~~~~~~~~:LL~~~~
~~
-

+12V

~N~RT~ _ _ _

~~~
["\ ~
i'
~""/h

.!----. ...

I'NCWO"

REGISTERS

AND FIFO)

J .1

-l

~ I
I ~
I 7] ~ ~~ T~ ;-;
1 'ffi'
1 ~
,
~ """'I I_ _ _ _ ___I
t~~ ~~ I"''':::'~
I " ' "~ ~~,
I l"\ ~
~ ~
I l"~ ~~~~
~ I
I
r-Iht~ I
,~
I ~",~l'
I
R
I~
''
, '~
~
~~ sc,,"
I
I
'ffi' '7' 1"
- ') -; ,,~~ W h"l' ~I':
';.',";;0;, ~
I ~~~;;;""'-- ~,,"'
I ~ I
~ I J A"""
~
I
I
~
5
~
J
I
~
'~I
~
~W
~L
I
I
~I~hl
I ",TC"'. I
'.
• I
1 t'["\.
-.J
~
I :~"SS ..~
I
~ I
--7----1~~ ~
L - ."
1
I
r-~ - 1• - :~~~!
g~ 8'
- -- -_I
a?

r(O""S =
FIFO

FIFO

r----l
I
I ~VOLTAGE

~~"~~?a

~ I
, "\.J::; F"'"
~
I v:
'-"-

BAUD RATE CLOCK
~CI~TO.!!- _ _ _

~f%: ITXCEIVER~I ~
~
~ __
PROCl
DATA

LJ I

13.6S64~

'<t

r------

~ 1""1 ~~f"'~

""'--

r-:;"I

=-,

r - -I
r
I
~
I
1 r::=;
s~ ~
;2; II"'" .1 """
~ ~ l,"''' «r~ ~ ~ I
~~ I ~_ 1
I 1 - ~ I~
i'
,r.:;~ I ~~ 11/~~ V#~
Is~ 9 1_
~
~ ~ 1_
- ) ~ ~I~ l"
t;01 .... 1 _ ~
I ~
l"
~ "- I
I L'- ~ 1

~~I
'I
I
A<15:S>

["\
["\

I/;:

iPROC2

I DATA

['-

TXCEIVERSI

HI BYTE

LO BYTE

ENABLE

..''

CONTROL

,:::E 0

-I

TXD<7:0>

--..J

I .. 1

""'--

"'0<>,0>

•

DTR<7:0>
DSR<7:0>

J.-.,L.

DCD<7:0>

I-

OUA""

...!::..

RAM

ADDRESS

l '

, -

- , /

L!,RO£

II:

SANDS

..."

INTO/1

LL:::==~~l'l----""IN_T_1:-;- ru-R~-~-;". sE R-;vl"I~T~E)on~ =
'P2AD<7:0> & P2A<15:S>

CHANGE "Q

'NT'lLR_UPT
_ _.L...._ _ _
FULL
ALARM

....

...

S051

],_

"""

RIO, 7

--t--o INT 6/7

:::E Z

<t-l

I
I
I

~8
~~

LINE
INTERFACE

Z -~
:::i

: {~ -~.d
L

RD819

When the bus transceivers recognize a valid device register address, the DC004 is enabled. MATCH
allows BDIN or BDOUT to generate BRPLY. The external bus signals are decoded by the DC004 which
generates the following as necessary:
INWD
OUTLB
OUTHB

Word transfer, DHVll to the bus master
Low byte (AD<7:0» transfer, bus master to DHVl1
High byte (AD<15:8» transfer, bus master to DHVl1.

Both OUTHB and OUTLB are generated to transfer a word to DHVII.
The DC004 also decodes the low address lines to generate a number of register select (SEL) signals.
SELO is the signal which selects the CSR.
If a condition which needs interrupt service occurs, the DC003 interrupt logic interrupts the host (BIRQ).
When the acknowledge signal (BIAKI) is returned, VECTOR and VECT.2 are generated as previously
described. BIAKO provides bus grant continuity.
BINIT is the bus initialize signal. It resets the DHVII to a known state.
The DCOlO is a DMA controller used by the DHVII to perform a DMA transfer. A hardware DMA
request enables the IC, which then makes a request via BDMR (bus DMA request) for control ofthe bus.
The DCO 10 provides the appropriate bus-control signals to transfer a word of data to DHVII. After each
transfer the bus is released. Another DMA request is needed for the transfer ofthe next word. DMA data
does not pass through the DCO 1O.
Figures 4-2 and 4-3 show the DATI (INWD), DATOB (OUTLB or OUTHB), and DATO (OUTLB
and OUTHB) handshake sequences. In each case the DHVII is bus slave.
Figure 4-4 shows an interrupt request/ acknowledge sequence which requests the host processor to read an
interrupt vector from the DHVl1. This sequence is followed by a DATI operation which transfers the
vector.
In Figure 4-5, a DMA request/grant sequence is shown. Note that when bus grant (BDMGO) is received,
the DCO 10 becomes bus master. It generates the signals for an INWD transfer from system memory to the
DMA data latches.
NOTE
A DATIO or DATIOB sequence is made up of a
DATI followed by DATO or DATOB.
NOTE
On Q-bus systems, BDAL<17:16> are used to
provide data parity information to the bus master.
To prevent the DHVl1 from generating false
parity information, AD<17:16> are only enabled
onto the BDALs when the DHVII is bus master.
ADREN from the DMA controller performs the
enable function.
A description of DC003, DC004, DC005, and DCOlO is included in Appendix A.

4-3

BUS MASTER
(PROCESSOR OR DEVICE)

SLAVE
(MEMORY OR DEVICE)

ADDRESS DEVICE MEMORY
"ASSERTBDAl<f7,OO> lWITH
ADDRESS AND
" ASSERT BBS7 IF THE ADDRESS
IS IN THE 10 PAGE

--- ---------..

• ASSERT BSYNC l

---------

DECODE ADDHtSS
STORE"DEVICE SELECTED"
OPERATION

REQUEST DATA
REMDVE THE ADDRESS FROM
BDAl < \7,00> l AND NEGATE BBS7

--- ------- --- ----

ASSERT 8DIN l

TERMINATE INPUT TRANSFER
ACCEPT DATA AND RESPOND
BY NEGATING BDIN l

TERMINATE BUS CYCLE
• NEGATE BSYNC l

---

INPUT DATA
PLACE DATA ON BDAl < 15,00> l
_ _ " ASSERT BRPlY l
" PLACE PARITY INFO ON BDAl < 17' 16> l

---- - ----

OPERATION COMPLETED
- - - - - - - - " NEGATE BRPlY l

Figure 4-2

DATI Bus Cycle

BUS MASTER
(PROCESSOR OR DEVICE)

SLAVE
(MEMORY OR DEVICE)

ADDRESS DEVICE/MEMORY
" ASSERT BDAl <17,00> l WITH
ADDRESS AND
ASSERT BBS7 l IF ADDRESS IS
IN THE 10 PAGE
" ASSERT BWTBT l (WRITE
CYCLE)
" ASSERT BSYNC L

--- - ---- ---------

----- ----

OUTPUT DATA
" REMOVE THE ADDRESS FROM
BDAL < 17,00> l AND NEGATE BBS7 l
AND BWTBT l
" PLACE DATA ON BDAl < 16:00> L
" ASSERT BDOUT L
__ _

DECODE ADDRESS
STORE"DEVICE SELECTED"
OPERATION

----- -----"

- --

TAKE DATA
RECEIVE DATA FROM BDAl
LINES
ASSERT SRPlY l

-"
----- - ....
-- ---- --

TERMINATE OUTPUT TRANSFER " NEGATE SDOUT L (AND BWTST L
IF A DATOB SUS CYCLE!
" REMOVE DATA FROM SDAL < 16:00> L _

OPERATION COMPLETED

TERMINATE BUS CYCLE
NEGATE BSYNC l

Figure 4-3

NEGATE BRPLY L

DATU or DATOB Bus Cycle

4-4

DEVICE

----- ----------..

INITIATE REOUEST
_ . ASSERT BIRO L

STROBE INTERRUPTS
ASSEAT BDIN L

I
I

RECEIVE BDIN L

STORE "INTERRUPT SENDING
IN DEVICE

•

GRANT REOUEST
• PAUSE AND ASSERT BIAKO L

RECEIVE VECTOR & TERMINATE

REQUEST

INPUT VECTOR ADDRESS
• NEGATE BD1N LAND BIAKO L

-------....
------ --

RECEIVE 81AKI L
RECEIVE BIAKI L AND INHIBIT

BIAKO L
PLACE VECTOR ON BOAl < 15:00 > L
ASSERT eRPlY L
_ . NEGATE BIRO L

--------

COMPLETE VECTOR TRANSFER
REMOVE VECTOR FROM BDAL BUS
NEGATE BRPLY L

PROCESS THE INTERRUPT
SAVE INTERRUPTED PROGRAM

PC AND PS ON STACK
LOAD NEW PC AND PS FRO~:
VECTOR ADDRESSED LOCATION
EXECUTE INTERRUPT SERVICE
ROUTINE FOR THE DEVICE

Figure 4-4

Interrupt Request/Acknowledge Sequence

CPU

DEVICE
REQUEST BUS
_

• ASSERT SOMR L

GRANT BUS CONTROL
• NEAR THE END OF THE
CURRENT BUS CYCLE
(BRPLY L IS NEGATED)

ASSERT BOMGO LAND
INHIBIT NEW PROCESSOR
GENERATED BYSNC L FOR
THE DURATION OF THE

ACKNOWLEDGE BUS
MASTERSHIP
• RECEIVE BOMG
• WAIT FOR NEGATION OF
BSYNC LAND BRPlY l

DMA OPERATION

• ASSERT BSACK l
• NEGATE BOMR L

TERMINATE GRANT
SEQUENCE
• NEGATE BDMGO LAND
WAIT FOR DMA OPERATION - TO BE COMPLETED

EXECUTE A DMA DATA
TRANSFER

....---

INa SOONER THAN
NEGATION OF LAST BRPLY
L) AND BSYNC L

RESUME PROCESSOR
OPERATION
• ENABLE PROCESSOR·
GENERATED BSYNC L
(pROCESSOR IS BUS
MASTER) OR ISSUE
ANOTHER GRANT IF BDMR
L IS ASSERTED

Figure 4-5

• ADDRESS MEMORY AND
TRANSFER UP TO 4 WORDS
OF DATA A~ DESCRIBED
FOR DATI OR DATO BUS
CYCLES
• RELEASE THE BUS BY
TERMINATING BSACK L

WAIT 4 p.s OR UNTIL
ANOTHER FIFO TRANSFER
IS PENDING BEFORE
REQUESTING BUS AGAIN

DMA Request/Grant Sequence
4-5

4.3 SERIAL INTERFACES
The serial interfaces shown in Figure 1-5 are made up offour DUARTs and a number ofline drivers and
receivers. These are shown in the bottom right-hand corner of Figure 4-1.
The four DUARTs are controlled and serviced by PROC2. All parallel data into and out of the DUARTs
is transferred via PROC2.
A common interrupt tells PROC2 when one ofthe DUARTs has assembled a received character. In order
to find the interrupting channel, PROC2 checks each DUART status in turn. It then constructs a status
byte, transfers it to the FIFO, reads the character from the DUART, and transfers that to the FIFO.
All other DUART status information, such as:
•
•

Ready to accept a character for transmission
Status change on a modem control line

is polled by PROC2.
4.3.1 Modem Control and Status Lines
Each DUART has output lines for the modem control signals Request To Send (RTS) and Data Terminal
Ready (DTR). There are also inputs for the modem status signals Clear To Send (CTS), Data Set Ready
(DSR), and Data Carrier Detected (DCD). The status of the input lines is visible to the host through the
ST AT register. Output lines can be controlled via the LN CTRL register.
Ring Indicator (Rl) signals are input directly to PROC2 from the line receivers.
There is no 'break detect' bit in the status registers. A break condition is reported via the FIFO as a null
character with the framing error bit set.
4.3.2. EIA/TTL Level Conversion
Interface to the serial lines is provided by 9636AC line drivers and 9637 AC receivers. These inverting
amplifiers convert between EIA levels on the serial lines, and TTL levels at the DUARTs.
NOTE
More detail of the SC2681 DUARTs used in the
DHV11 is provided in Appendix A3.
4.4

CONTROL SECTION

4.4.1 General
The control section (Figure 1-5) is made up of everything except the two interfaces which have just been
described. This section contains:
•

The common RAM - via which almost all commands and data are routed

•

The store arbitrator-which regulates all RAM access requests from the host and the DHVII 's
two microcomputers

•

The microcomputers - PROCI and PROC2

•

Data and address latches and drivers

4-6

•

FIFO control and address circuits - which supply the appropriate FIFO addresses

•

The CSR - which is the main control register.

The CSR is a separate set of latches and is not part of common RAM.
4.4.2

Common RAM

4.4.2.1 Memory Map - The common RAM (common to both microcomputers) IS mapped to
microcomputer addresses 800016 to 87FF16 as shown in Figure 4-6.
PHYSICAL
(WORD)
ADDRESSES
(HEXADECIMAL)

DIAGNOSTIC
BYTES

MICROCOMPUTER
(BYTE)
ADDRESSES
(HEXADECIMAL)

03FF

87FE

0248

8490

0200

8400

0100

8200

0080
0070
0060
0050
0040
0030
0020
0010
0000

8100
80EO
80CO
80AO
8080
8060
8040
8020
8000

SCRATCH
AREA

SINGLE CHAR BUFFER

INTERPROCESSOR
BUFFERS

DMA OUTPUT BUFFERS
8 x 8 WORDS
HI BYTE = FLAG
LO BYTE = CHAR

8 x 1 WORD
CHAN I
7
CHAN I
6
CHAN I
5
CHAN I
4
CHAN I
3
CHAN I
2
CHAN I
1
CHAN I
0
I
I

ADDRESS OF FIFO
= READ BASE+2
= RBUF

256 WORD
(512 BYTES)
FIFO

I
I

16 x TBUFFCT
16 x TBUFFAD2
16 x TBUFFAD1
16 x LNCTRL
16 x STAT
16 x LPR
16 x TXCHAR (WRITE)
NOT USED

OBUS
LOGICAL
ADDRESSES
(OCTAL)

I
UNUSED
AREA

I
I

BASE+16
BASE+14
BASE+12
BASE+10
BASE+6
BASE+4
BASE+2
BASE

HIGH
BYTE

LOW
BYTE

R01152

Figure 4-6

Common RAM - Memory Map

The top lK bytes (above the FIFO) are used by PROCI and PROC2 for interprocessor buffers and a
scratch area.
Each channel has an 8-word buffer for DMA characters. There are also eight I-word buffers (one for each
channel) for single-character programmed transfers. By using buffers, the DHVll is able to transmit more
efficiently. Buffers are filled by PROCI and emptied by PROC2.

4-7

Each word of a buffer has a flag byte (D<15:8» and a character byte (D<7:0». When PROC1
transfers a character to a buffer, it sets the flag byte to a non-zero condition. When PROC2 transfers a
character to a UART, it clears the flag byte to zero. In this way, the flag byte is used as a handshake
between PROC 1 and PROC2.
The top eight words are reserved for self-test diagnostic bytes.
4.4.2.2 Registers - The DHV11 is controlled via registers. There are seven for each channel, plus the
FIFO (RBUF) and a common CSR. The functions of registers are as follows:
CSR

- Main control register for channel selection, important flags, and control bits

RBUF

- FIFO for received characters, and status and diagnostic information

TXCHAR

- Any character written to a channel's TXCHAR is transmitted on that channel

LPR

- Command codes written by the host to this register configure the channel

STAT

- Indicates the current modem status

LNCTRL

- Command register via which the host controls the channels

TBUFF AD 1 - Loaded by the host, while setting up a DMA transfer with the 16 low-order bits of
a DMA address
TBUFF AD2 - Holds the six high-order bits of a DMA address, plus control bits
TBUFFCT

- Loaded by the host, while setting up a DMA transfer, with the number ofDMA
characters to be transferred.

Register functions are described in Chapter 3 (Programming).
Figure 4-6 shows the location of registers and their physical addresses. Each block allocated to a register
contains 16 word locations, only 8 of which are used. These locations are indexed by an address
previously written to CSR<3:0>. For example, in order to write to the TXCHARregister for channel 7 ,
the host must first write 7 to CSR<3:0>. When the host then writes to TXCHAR (BASE + 2), the
address is indexed by 7. This accesses the appropriate TXCHAR register from the block of 16.
The host can also write bytes to the registers. In that case, even addresses (BASE + 2, BASE + 4, and so
on) will access the low byte (D<7:0». Odd addresses (BASE + 3, BASE + 5, and soon) will access the
high byte (D<15:8».
Transfers to the master, from the registers and the FIFO, are routed via the output data latches. Transfers
from the master to the registers pass through the input data latches.
4.4.2.3 FIFO - This 256-word RAM area usually contains received characters and status information.
When the host reads from BASE + 2(RBUF), the oldest word in the FIFO is transferred.
There is only one received character buffer (RBUF). The index bits (CSR<3:0» are ignored during a
read action from RBUF.

4-8

4.4.3 RAM Access
(See Figure 4-7.) The common RAM can be accessed by the host, or by each of the DHVll
microcomputers. Therefore, it is a 3-port memory.
FROM
HOST

FROM
PROC2

I
I

- - --,

FROM
PROC1

I
I
I
I

FIFO
COUNTERS

HOST
EN

RAM
ADDRESS
LATCH

PROC2
EN

I
I

RAM
ADDRESS
LATCH

PROC1
EN

L __

____________________ J

DATA
LATCHES

HOST
EN

TO/FROM
HOST

DATA
TRANSCEIVERS

PROC2
EN

TO/FROM
PROC2

DATA
TRANSCEIVERS

PROC1
EN

TO/FROM
PROC1
R01l53

Figure 4-7

Common RAM Access

Addresses (Figure 4-7) come from four sources:

•

•
•
•

PROCI
PROC2
The host processor (via translation logic)
The FIFO Fill and Empty counters.

During a write to FIFO (by PROC2) or a read from FIFO (by the host), the RAM address is given by one
of the FIFO counters. Dotted lines in Figure 4-7 indicate that this area is oversimplified.
Figure 4-1 shows more detail of the same circuit.

4-9

4.4.4 Store Arbitrator
When one of the microcomputers or the host needs to access the RAM, it will generate a request for store
access. The store arbitrator (Figures 4-7 and 4-1) sequentially scans the request lines. When it detects a
request, that request is granted and the other two requests are locked out. The arbitrator issues enable
signals for the appropriate address and data sources, and starts memory timing and control logic.
Signals produced by the timing and control logic perform the read or write action and then terminate the
access.
4.4.5 Microcomputers
Using the RAM as a common reference point, PROC1 and PROC2 manage the functions of the DHV11.
Under control of firmware, contained in internal ROM in each microcomputer, the RAM is scanned for
commands or data. The main functions of each microcomputer are as follows:
PROC1
1.
2.
3.
4.

Single-character transfers from the TXCHAR register to the output buffers in common RAM.
Control of DMA transfers from system memory to the output buffers in common RAM.
Reporting back to the host via the TX.ACTION bit in the CSR.
Executing the Background Monitor Program (BMP) when not busy with other tasks.

PROC2
1.

Transfer of characters (DMA and single character) from the output buffers to the appropriate
DUART channel.

Transfer ofreceived characters and error status from the DUARTs to the FIFO. Recognition
of automatic flow control (auto-flow) characters X-ON and X-OFF. Auto-flow is described in
Chapter 3, Programming.

Servicing internal interrupts which are raised when the host writes to the LPR or LNCTRL
registers.

Scanning the modem status lines for a change of state. Reporting back to the host via the STAT
register and FIFO.

Executing BMP when not busy with other tasks.

4.4.6 Address and Data Latches
To meet the interface timing demands, latches are used for all transfers between the host and the DHV11.
For example, to transmit a single character, the host writes the character to the TXCHAR register.
During this action the TXCHAR address is latched into the register address latch. The data is latched into
the input data latches. The arbitration and timing and control circuits complete the transfer to TXCHAR.
Characters transferred by DMA are not routed through the TXCHAR register. Special DMA latches are
provided for this purpose.
At the beginning of a DMA cycle the next DMA address is written to the DMA address latches (Figure 4-1).
This generates a DMA request to the DMA control IC, DCO 10, which transfers the next word from host
memory to the DMA data latches. PROC1 will transfer the word (two characters) from the latches to the
DMA buffer area in common RAM, except at the beginning or end of an odd length buffer.

4-10

4.4.7 FIFO Addresses
The FIFO is implemented in common RAM. It is filled by PROC2 and emptied by the host. It is made to
act like a FIFO by the action of two counters.
The Fill counter provides addresses during PROC2 FIFO WRITE actions. It points to the next available
location. The counter is incremented after each word (two separate bytes) is written.
The Empty counter provides addresses during a FIFO READ action by the host. It addresses the oldest
word in the FIFO. It is incremented after each word is read.
4.4.8 FIFO Control
Received characters are transferred from the DUARTs to the FIFO in order to be read by the host.
PROC2 loads the status (high) byte and then the character (low) byte. The host reads this information as a
full word. A FIFO control circuit manages these actions by monitoring GRANT signals from the store
arbitrator and READ or WRITE signals from the host or PROC2.
The functions of the FIFO control circuit are as follows:
•
•
•
•
4.5

Gating the appropriate FIFO counter onto the store address (SAD<9:0» bus
Incrementing the appropriate counter after access
Disabling both FIFO addresses when the FIFO is not being accessed
Reporting the state of the FIFO (FULL, ALARM, EMPTY) to PROC2 and the CSR.

OTHER CIRCUITS

4.5.1 Voltage Converter
Line drivers and receivers need both + 12 V and -12 V in order to generate line signals at EIA levels. The
voltage converter, which is a small Switched-Mode Power Supply (SMPS), produces -12 V from the +12
V supply.
4.5.2 Oscillators
Also on the module are the following circuits:
•
•

Oscillator to provide 24 MHz, 12 MHz and 6 MHz clock signals for the timing circuits
Oscillator of 3.6864 MHz to provide the basic clock for DUART data rates.

4.6 DATA FLOW
DHVll firmware uses interrupt timers in PROCI and PROC2 to enter certain routines which handle
data and check the control registers. Therefore a delay, dependent on the timer interval, can be introduced
into some data paths. When referring to Figures 4-8 to 4-14, these delays must be considered.
The delays are as follows:
1.

TXCHAR to single-character transmit buffers:
Every 780 microseconds PROCI checks for characters in each TXCHAR register. If
available, one character will be transferred to the buffers from each register. It is this timer
which limits single character transmission to 1000 characters per second.

4-11

DMA data latch to DMA buffer area:
Each time PROC 1 services the single-character buffers it also checks, and services if needed,
one pair of channels for D MA. The channels are serviced in rotation. This means that a specific
channel is serviced every 4 X 780 microseconds = 3.12 milliseconds. PROC 1 will transfer up
to eight characters to each of the two DMA output buffers in common RAM (Figure 4-6).

Single-character or DMA output buffer to DUART:
Every 480 microseconds PROC2 checks the interprocessor buffers for valid data. If there is
data waiting, a character will be transferred to each DUART channel which is ready to take a
character. It is this timer which limits DMA transmission per channel to 2000 characters per
second.

DUART to FIFO:
Received characters are not handled by timer-driven interrupts, but by direct interrupt from the
DUART. Therefore, in comparison with transmitted characters, the delay is not significant.

The DMA start bit is sampled every 3.12 milliseconds. There is also a delay of up to 480
microseconds in PROC2. This gives an average delay of 1.8 milliseconds before a DMA
transfer is started.

Timer dependent tasks of PROC2 may be delayed by:
1.

The receive interrupt

The parameter change interrupt which is raised (by hardware) when the host writes to the LPR
or LNCTRLregisters. (It may have to change the DUARTconfiguration or the state of modem
control lines )

The need to monitor modem status lines. These are sampled every 10 milliseconds.

From the foregoing it should be clear that PROC2 delays are to a great extent dependent on application
and on throughput.
In the following descriptions of data flow, the basic timer delays are noted against the appropriate data
paths on the diagrams.
4.6.1 Host Read from a Register
(See Figure 4-8.) Except for RBUF or the CSR, the channel number must first be written to CSR<3:0>.
This is followed by a READ from BASE + n (see Figure 4-6).

4-12

INDIRECT
ADDRESS
REGISTER
CSR<3:0>

CHANNEL NUMBER

ADDRESS

INDEXED ADDRESS

ADDRESS

DATA

RAM
BUS
TRANSCEIVERS

DATA

OUTPUT
DATA
lATCHES

DATA

ClK

BUS
GRANT

CONTROL

DC004
PROTOCOL

BUS REQ

ARBITRATOR

READ
ENABLE

BUS GRANT

TIMING
AND
CONTROL

RD1339

Figure 4-8

Reading from a Register

The register address is latched into the register address latches, to be applied to the RAM when bus access
is granted.
The READ action from the host generates a BUS REQUEST to the store arbitrator, which generates
BUS GRANT. This starts the timing signals which read a word from the addressed register. When BUS
GRANT is deasserted, the data is latched into the output data latches.
BRPLY (Figure 4-2) is inhibited until data transfer to the output latches is complete. BRPLY is then
asserted. READ signals on the Q-bus transfer the word to the host.
4.6.2 Writing to a Register
(See Figure 4-9.) In order to write to a register the channel number is first written to CSRbits <3:0>. This
is followed by a WRITE to BASE + n (see Figure 4-6).

4-13

INDIRECT
ADDRESS
REGISTER
(CSR<3:0»

CHANNEL NUMBER

ADDRESS

INDEXED ADDRESS

ADDRESS

DATA

RAM
BUS
TRANSCEIVERS

DATA

INPUT
DATA
LATCHES

DATA

BUS
GRANT

CONTROL

DC004
PROTOCOL

BUS REQ

ARBITRATOR

WRITE
ENABLE

BUS GRANT

TIMING
AND
CONTROL

RD1340

Figure 4-9

Writing to a Register

The register address is latched into the register address latches and is applied to the RAM when the bus
access is granted. The data to be written is latched into the input data latches.
The WRITE action from the host generates a BUS REQUEST to the store arbitrator. BUS GRANT
enables the data from the input data latches and provides RAM timing signals. Data will be written to the
addressed register.
For a WRITE BYTE action, address line 0 will select the high or low byte of a word.
4.6.3 Single-Character Transmit
(See Figure 4-10.) To transmit a character by use of the single-character transmit facility, the character
and the DATA.VALID bit can be written to the TXCHAR register. This would be done exactly as in
Section 4.6.2. To transmit subsequent characters, the TX.ACTION bit for this channel must be checked
by polling or via interrupts.

4-14

RAM

WRITE
PROC1
DATA

SINGLE CHAR
TRANSMIT BUFFER

READ

WRITE
PROC2

DATA

TRANSMIT
DUART

DATA

TX CHAR

DATA

~
DELAY UP TO 780 ~s
(390 ~s TYPICAL)

DELAY NORMALLY UP TO 480 ~s
(MAY BE EXTENDED BY LINE PARAMETER
CHANGES OR BY RECEIVED CHARACTERS)

Figure 4-10

RD1341

Single-Character Transmit

PROC 1, which scans the TX CHAR register, detects from the data valid bit that a new character has been
written. It reads the character and then transfers it to the single-character buffer area in the common RAM
(Figure 4-6). PROC1 writes the channel number and the TX.ACTION bit to report acceptance of the
character.
PROC2, which scans the buffer area, reads the character from the buffer area and writes it to the
appropriate DUART. The DUART then transmits the character serially on the appropriate channel.
4.6.4 DMA Transmissions
Section 3 (Programming) describes how a DMA block transfer is set up. The host writes a DMA buffer
start address, the number of characters to be transferred, and a TX.DMA.START bit to TBUFFAD1,
TBUFFAD2, and TBUFFCT.

4-15

ADDRESS
ADDRESS

DMA
ADDRESS
lATCHES

STRDBE 1,
2 AND 3.

RAM

ADDRESS

DATA

BUS
RANSCEIVER!O

DATA

DMA
DATA
lATCHES

READ

WRITE

PROC1

DATA

READ

DMA BUFFER
AREA

DATA

PROC2

WRITE
DATA

DUART

TRANSMIT
DATA

I
..-

STROBE 3

0'\
ClK

CONTROL

DC010
DMA
CONTROL

DMA REO

DMA
REO
lATCH

DELAY UP TO 3,12 ms
(1,56 ms TYPICAL)

Figure 4-11

DELAY NORMAllY UP TO 480)Js
(MAY BE EXTENDED BY LINE PARAMETER
CHANGES OR BY RECEIVED CHARACTERS)

DMA Data Transfer

RD1342

4.6.4.1

DMA Block Transmit - Figure 4-11 shows the data flow for a DMA transfer.

When the host sets TX.DMA.START, PROC1 writes the DMA address (in three bytes) to the DMA
address latches. Writing the most significant address byte sets the DMA request latch, which starts a
DMA transfer.
The DCOIO performs a READ from memory, using the DMA address held in the address latches.
The DMA cycle always transfers a word from system memory to the DMA data latches. PROC1 reads
the word (two characters) one byte at a time, and transfers them, via its data transceivers, to a buffer area in
RAM. Note that PROC1 can only write to the buffer area if there is space for at least two characters.
PROC2, which scans the buffer area, reads the character from the buffer area and writes it to the
appropriate DUART.
The DUART transmits the character serially on the appropriate channel.
4.6.4.2 DMA Data Management- When a DMA block starts with an odd address, or ends with an
even address, PROC1 will transfer the addressed character only, to the output buffer.
Figure 4-12 shows how DHV11 manages a 9-byte DMA transfer. The start address is 10618 and the end
address is 10728.
PROC2 transfers characters from the buffer area, exactly as in Section 4.6.4.1.
START OF
DMA BLOCK

END OF
DMA BLOCK

LaC

1060

1061

1062

1072

1073

1074

'---_-..

___________

FIRST WORD
READ FROM
MEMORY TO
DMA DATA
LATCHES

'--_~

_ _ - - ' J l ' -_ _ _ _ _ _ _~ ___-~

---...------J

_____J ' - -

FIRST BYTE
TRANSFERRED
TO COMMON
RAM

l,-_~

_ _ _~

BYTE
BYTE
LAST BYTE
TRANSFERRED TRANSFERRED TRANSFERRED
TO COMMON TO COMMON
TO COMMON
MM
MM
MM

LAST WORD
READ FROM
MEMORY
TO DMA
DATA LATCHES
RD1160

Figure 4-12

DMA Character Handling

4.6.4.3 D MA Error Detection and Timeout - Q-bus protocol demands that, during a bus transaction,
a bus master which does not receive BRPLY within 10 microseconds of sending BSYNC should terminate
the transaction. For a DMA transfer the DHV11 becomes bus master; therefore it must obey the timeout
rule. The DHVll also checks parity bits BDAL 17 and 16.
At the beginning of each DMA cycle the DMA controller uses ADREN (address enable) to gate the
DMA address onto the Q-bus. The trailing edge of this signal starts a hardware counter (Figure 4-13)
which will time out after 10.7 microseconds if there is no reply from the bus. The counter is cleared by its
own timeout or by a bus reply.

4-17

The D MA error status is cleared by aD MA request. It will generate aD MA error signal (D MA ERROR)
if the timer times out or if a memory parity error (BDAL 17 and 16 asserted) is detected. The parity error is
latched when the bus reply goes false at the end of the transaction.
At the end of the DMA cycle, when the DCOIO deasserts BDIN, aDMA COMPLETE signal (Section
4.7.1.2) is generated. When PROCI detects DMA COMPLETE it checks the state ofDMA ERROR. If
an error is detected, the DRVII will read the same location once more before reporting an error to the
host.
REPLY (HIGH)
P1102.L (DMA REO)

MEMORY PARITY ERROR
(LOW)

LOW IF REPLY
OR TIMEOUT

D SET Q

HIGH
TO CLEAR

REPLY (LOW)

D SET
DMA
ERROR
LATCH
P1109.H
(DMA ERROR)

10.7 }Js
COUNTER
CLEAR

E62
ADREN.L

12MHz
CLK
R01161

Figure 4-13

DMA/Memory Error Generation

4.6.4.4 DMA Abort - PROCI transfers DMA data from the host, in blocks of up to eight characters
(four words). The data is held temporarily in the DMA output buffer area in common RAM. PROC2
scans the buffer for data, and transfers it byte by byte to the DUARTs. Separate buffer areas are reserved
for each channel.
A DMA sequence can be terminated by a DMA abort command from the host. When this happens,
PROC2 stops the transfer of characters to the DUART channel. PROCI stops transferring data, counts
the characters in the buffer, corrects TBUFFCT, TBUFFADl, and TBUFFAD2, and then clears the
DMA buffer area for this block. It then sets TX.ACTION to report that the transmission has been
aborted. To continue transfer of the aborted block, the host need only clear TX.D MA.ABO R T and set the
TX.DMA.START bit. The transfer will continue without losing characters.
4.6.5 Receiving
(See Figure 4-14.) When a serial channel has assembled a character, it will raise an interrupt. PROC2 will
respond by reading status from each D U ART in turn. When it finds the interrupting channel, PROC2 will
transfer an error/line-number status byte and the character byte to the FIFO.
PROC2 writes all receive information to a I-word address in the RAM; C040 = low byte, C041 = high
byte. These addresses are decoded and ANDed with 'PROC2 grant' to enable the FIFO Fill counter.
This counter provides the actual FIFO address. The counter is incremented after each character byte is
transferred. Therefore the character (low byte of RBUF) is transferred last.

4-18

RAM
INT

ADDRESS
DATA

BUS
TRANSCEIVERS

LOW
ADDRESS
BITS

+:0-

I
.......

1.0

DATA
OUTPUT
LATCHES

STATUS & DATA

FIFO

READ ADDRESS

EMPTY
COUNTER

DC004
PROTOCOL

PROC
2

WRITE ADDRESS

READ
ENABLE

INCi tEN

w"'~
ENABLE

FIFO
CONTROL

BUS GRANT

CONTROL

STATUS AND DATA

BUS REO

I
STATUS

DUART

DATA

AND DATA

FILL
COUNTER

INC
ADDRESS C04X

PROC2 GRANT

ARBITRATOR

PROC2 STORE REO

.. -

RD1296

Figure 4-14

Receiving a Character

To read the FIFO, the host performs a 'read from register' sequence as described in Section 4.6.1. In this
case, however, the DC004 recognizes that the FIFO (Base + 2) is being read. This causes the Empty
counter and the FIFO to be enabled.
The data is transferred via the data output latches as for a 'read from register' operation.
If characters are received faster than they are removed by the host, the FIFO will eventually become full.
PROC2 will stop taking characters from the DUARTs. A further four characters can be buffered in any
DUART channel before the overrun condition is reached. When this happens, any overrun channel will
be flushed.
When space is available, a null character (one for each overrun channel) with the overrun error bit set will
be placed in the FIFO.
4.7 TECHNICAL DETAIL
This section provides a more detailed description of specific areas of DHVII logic and electronics.
4.7.1 DHVll Internal I/O Control
PROCI and PROC2 firmware defines the functions of the DHVII. The functions managed by the
microcomputers are controlled and monitored via I/O ports associated with each microcomputer. These
are memory-mapped I/O ports, and integral ports PI and P3. (See Appendix A2, 8051 Microcomputer.)
Memory-mapped I/O used internally on the DHVII is very similar to PDP-II memory-mapped I/O
architecture. I/O addresses start at C00016 on each microcomputer.
4.7.1.1 PROCI Memory Mapped I/O - Table 4-1 lists the addresses and functions of PROCI
memory-mapped I/O. Figure 4-15 shows how the addresses are decoded.
Table 4-1

PROCI Memory-Mapped I/O

I/O Type

Signal Name

Function

CODa

Write

PIIOO.L

Load low-order eight bits of DMA
address into DMA address latch.

COOl

Write

PlI01.L

Load middle eight bits ofDMA address
into DMA address latch.

C002

Write

PlI02.L

Load high-order six bits ofDMA address
into DMA address latch. Set DMA
request latch.

Address
(H exad ecimal)

Not used.

C003
C004

Read

PlI04.L

Read low byte of DMA data from
DMA data latch.

COOS

Read

PlI05.L

Read high byte of DMA data from
DMA data latch.
Not used.

C006

4-20

Table 4-1
I/O Type

Signal Name

Function

Write

PlI07.L

PROCI CSR write. Also starts a dummy
store-access sequence. This is to prevent
access conflicts to this register.

Address
(Hexadecimal)
C007

PROCI Memory-Mapped I/O (Cont)

+VE

"
-P-1A-D-<-2-·0-.J>""
........... SELECT
- - - '""1.v' / / 0 - 7

rDM~DR~sl
LATCHES
I
-::-:-=---::-+'"
P1AD<7:0»
I

DMA
REO
F-LATCH

DMAREQTO
DMA CONTROLLER
0 o-:P-'l..:..::IO=O.:..::.L~_;--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _-+--a
P1101.L
I

',v

I
I

1~~~---7-------------------~

2o-:P~1~IO~2~.L_~~_ _ _ _ _ _ _ _ _ _~

P1 AD<7:0>
,

30
4~P~1~IO~4~.L~_ _ _ _ _ _ _ _ _ _ _ _,

6 0

70-

~--~r-

ENABLE IS:
P1 AD15 HIGH)
P1AD14 HIGH

rREQUEST SYNCHRONIZER 1

-.JI

+VlE - ; ; - -

COOx

PlRDDRWRST::::

7~1

i
: r-.-l=
1

CL Qr-

I
I

,---->

P1AD<5:0> )

MID
BYTE

I
AD<15:8>
v

HIGH
6 BITS

I
AD<21 :16>
v

L _____I

I
I

DMADATA-'
LATCHES
I

P1AD<7:0>
...."

LOW
BYTE

L -_ _ _ _ _ _ _ _+_~

' - - - - + - P1 SRQH

<" Pl AD<,7:0>

P1 CLK

VLCI-,--..."..--..,.~ I AD<7:0>
I

_ _ _ _1
/1

CSRFC.L

I
I

'---___---'I_q

D E9 Q

r - - P1 SLOW.L

- r- -

D E7 Q

AD<'7:0>

5~P~1~IO~5~.L~_ _ _ _ _ _ _ _ _~

- - - - - - I ENABLE

LBOYTW
E

HIGH
BYTE

AD<15:8>

L ____ ,

RD2250

Figure 4-15

PROCI I/O Decoding

4-21

4.7.1.2 PROCI Integral I/O Port Functions - Table 4-2 lists the functions of the integral ports used
by PROCI.
Table 4-2

PROCI Integral I/O Port Functions

Port

Direction

Signal Name
(Explanatory
Title)

Function

PLO

Input

PlI08.L
(TX ACTION)

1= DHVII has completed or terminated
a transmit action. Waiting for read by
host.

o= C SR has been read by host. This bit
is cleared when host reads CSR.
PLI

Pl.2

Input

PlI09.H
(DMA ERROR)
PlIOIO.H
(DMA COMPLETE)

I = Error during last DMA transfer.

o = No DMA error.
I = Last DMA request has been
completed.

o = Not completed.
Pl.3

Output

PlIOIl.H
(DIAG ERROR)

I = Error found during self-test diagnostic
or BMP.

o = No error was detected during selftest diagnostic or BMP.
This bit drives the' diagnostics passed'
LED and the' diagnostics fail' bit in
theCSR.
PI.4

Not used.

Pl.5

Not used.

Pl.6

Output

PlIOI4.L
(MRCLEAR)

0= Clear and hold master reset latch.
I = Release hold.

Pl.7

Not used.

P3.0

Input

IPSLO

Serial input line to PROCI internal
UART.

P3.I

Output

IPSLI

Serial output line from PROCI internal
UART.
The above two serial lines connect to
PROC2 internal UART for direct
reporting during diagnostics.

P3.2

Not used.

4-22

Table 4-2
Direction

Port

PROCI Integral I/O Port Functions (Cont)
Signal Name
(Explanatory
Title)

Function

P3.3

Not used.

P3.4

P2INT1.L

Input

PROC2 interrupt monitor
0= Pending change to LPR or LNCTRL
registers.
1 = No pending change.
Not used.

P3.5
P3.6

Output

PIWRL

Write strobe for common RAM and
the DUARTs.

P3.7

Output

PIRD.L

Read strobe for common RAM and
the DUARTs.

4.7.1.3 PROC2 Memory-Mapped I/O - Table 4-3 shows the addresses and functions of PROC2
memory-mapped I/O. Figure 4-16 shows how the addresses are decoded. The low address lines are used
to select one of 16 registers in each DUART.
Table 4-3

PROC2 Memory-Mapped I/O

Address
(Hexadecimal)

I/O Type

Signal Name

Function

COOO
to
COOF

Read/Write

UARTO.L

Chip select DUART O.
Internal registers addressed by ADO to AD3.

CO 10
to
COIF

Read/Write

UARTI.L

Chip select DUART 1.
As above.

C020
to
C02F

Read/Write

UART2.L

Chip select DUART 2.
As above.

C030
to
C03F

Read/Write

UART3.L

Chip select DUART 3.
As above.

C040

Write

FIWRL

Writes the low byte of the FIFO word
(usually the received character) to the FIFO.
The trailing edge increments the FIFO
address pointer (so it is written after the
status byte). ADO = O.

4-23

Table 4-3
Address
(Hexadecimal)

PROC2 Memory-Mapped I/O (Cont)

I/O Type

Signal Name

Function

C041

Write

FIWRH

Writes the high byte (status) to the FIFO.
Written before the low byte. ADO = 1.

COSO

Write

FICL.L

Clears the FIFO address counters at bus or
DHVII reset. (In effect empties the FIFO.)
Not used.

C060

Clear interrupt request PROC2. When the
LPR and LNCTRL registers are written, a
hardware interrupt request is raised to alert
PROC2. During the interrupt routine,
PROC2 clears the interrupt request via
INTCL.L.

INTCL.L

Write

C070

I
I
1-..

INTERNAL REGISTER SELECT

P2AD<3:0>

P2AD<6:4>

SELECT

i
SEL

UARTO.L

DUARTS
0-3

UART1.L

1
2

UART2.L
UART3.L

3
4

)

FIWR.L

5
60--ENABLE
ENABLE IS:
AD15 HIGH)
AD14 HIGH = COxx
P2 RD OR WR STROBE

7
FIFO
COUNTER
FICL.L

ADDRES0

....

ADDRESS
LATCHES

SAD<7:0~

RAM

P2INT1.L
Q

INTCL.L

R01156

Figure 4-16

PROC2 I/O Decoding

4-24

4.7.1.4 PROC2 Integral I/O Port Functions- Table 4-4 shows the function of the integral ports used by
PROC2.
Table 4·4

PROC2 Integral I/O Port Functions

Port

Direction

Signal Name

Function

PLO
to
Pl.7

Inputs

RIBO.L
to
RIB7.L

o to 7 from modems.
0= ON, 1 = OFF.

P3.0

Input

IPSLI

Serial input line to internal U ART, PROC2.

P3.1

Output

IPSLO

Serial output line from internal UART,
PROC2.

Indicates the state ofthe Ring Indicator lines

The above two serial lines connect to the
PROCI internal UART for direct reporting
during diagnostics.
P3.2

Input

P2INTO.L

0= DUART service interrupt request active.
1 = Interrupt inactive.

P3.3

Input

o = CHANGE interrupt request active.

P2INTl.L

Becomes active each time the host writes to
LPR or LNCTRL.
1 = Interrupt inactive.

P3.4

Input

o = FIFO is full

FULL.L

1 = FIF 0 is not full
P3.5

Input

o = FIFO has reached three-quarters full

ALARM.L

condition and has not yet been emptied
below half full.
1 = FIFO not in the above state.
P3.6

Output

P2WRL

Write strobe for common RAM and the
DUARTs.

P3.7

Output

P2RD.L

Read strobe for common RAM and the
DUARTs.

4-25

4.7.2 Q- Bus Interrupts
(See Figure 4-17.) The function of the DC003 interrupt logic is to make interrupt requests and to supply a
vector to the host. Signal sequences for interrupt request and acknowledge are given in Figure 4-4.
If interrupts are enabled, they are generated under the following conditions:

When a received character is loaded into a previously empty FIFO (EMPTY.L is asserted to
indicate this state)

When, with data in the FIFO, RXIE is changed to the enable state

When, during a single-character programmed transfer, a character IS removed from a
TXCHAR register

When a DMA block transfer is completed, or has been aborted, or has failed because of a DMA
error.

For conditions 3 and 4, the signal TX.ACTION.H is generated.
EMPTY.L, when it goes false, causes a receive interrupt request (RQA) and TX.ACTION.H causes a
transmit interrupt request (RQB).
Interrupts are enabled by writing a 1 to CSR bit 6 and/or CSR bit 14. This action generates receive
interrupt enable (RXIE) and transmit interrupt enable (TXIE) respectively. The host can read the status
of these lines by a CSR read action.
The enable signals are ANDed with the appropriate request, and latched to generate RQA or RQB. If
both are true, priority is given to RQA.
For both RX and TX interrupts, bus interrupt request (BIRQ.L) is generated. The request is cleared again
by RDIN.L at the start of an interrupt acknowledge cycle.
NOTE
Both RX and TX interrupt requests are latched by
a rising edge. Therefore in order to raise another
interrupt request, one of the inputs to AND gates
A or B must be deasserted and then asserted.
In an interrupt acknowledge cycle, the DC003 interrupt IC responds to BIAKI.L. The signal
VECTOR.H enables the vector switches onto BDAL<3:8>. VECT.2.H provides the low bit ofthe
vector address on BDAL<2>. It identifies a receive (0) or transmit (1) interrupt vector. VECTOR.H
also generates BRPLY via DC004 protocol logic. The vector is transferred to the host by a DATI
sequence which follows the interrupt request/grant sequence.
4.7.3 Common RAM Arbitration
(See Figure 4-18.) To allow the common RAM to be accessed by the microcomputers and by the host, the
DHVII provides arbitration circuitry. However, arbitration introduces a delay into a memory access
sequence. To account for this delay, the store access cycle of the requesting device must be extended.
Data addresses and control signals from the external bus are extended by delaying BRPLY.L. This signal
is disabled until the store access is complete. The 8051 microcomputers, however, cannot be controlled in
this way. They have no handshake signal such as WAIT, and because they are dynamic it is not possible to
stop the clock.

4-26

CSR
DRIVERS
RXIE

BIT 6
BIT 14
EN
CSR
READ

AD06.H
CSR WRITE
LOW BYTE
(CWR.LB.H)

15
14

RX
REO
LATCH

RXIE
LATCH

PORT A

-----1
CLR REO A

RQA

I
1

RDIN.L~P~-===--

BIRO.L

17
INHIBIT B PRIORITY
EM PTY.L--+:..:.....------;.--'
CONTROL
BIAKI.L .7
-------1----+1

112

PORT B

01-----'
AD14.H
D
CSR WRITE
13
TXIE
HIGH BYTE -"'-:-"----1> LATCH
(CWR.HB.H)
01--_----1

TX
REO
LATCH

CLR REO B

VECTOR.H
VECT.2.H

I
I
1

TX.ACTION.H
(P1108.L)

PART OF OC003 INTERRUPT LOGIC _ I
L ______________
R01151

Figure 4-17

Interrupt Logic

The DHV11 solves the problem by slowing down the related microcomputer clock every time PROC1 or
PROC2 tries to access the RAM. The normal clock frequency is 12 MHz. This is reduced to 1.5 MHz
during RAM access. Approximately 330 nanoseconds after a store request has been granted, the normal
clock frequency is enabled.
Figure 4-18 provides more information on the RAM arbitration and timing blocks. A description of the
operation follows.
A 4-state scan counter (0 to 3) is driven by the 12 MHz clock. The output is used as a synchronized count
for a request multiplexer and two accept decoders.
On each positive edge of the clock one of the latched store request lines (SRQDs) from PROC1, PROC2
or the bus is connected to the request latch. On each negative edge the input to the latch is sampled. A valid
store request will set the latch. The scan counter will be stopped and the RAM state counter will be
enabled.
With the scan counter stopped, the MUX and the decoders will also stop. One ofthe grant signals, ACP1,
ACP2, or ACB (accept PROC1, PROC2, or BUS), will be true. The equivalent SCS (store chip select)
signal will be selected but not enabled.
Now that the RAM state counter is enabled, it is incremented by the 12 MHz clock from 000 to 101. The
counter is then held in the 101 state by END.L.

4-27

COUNT

12 MHz ClK

SCAN COUNT ENABLE

SCAN
COUNTER
0·3
E76

I r
COUNT

P1SRQD- 0
P2SRQD-- 1

.J:>.
I
tv

BUSRQD-- 2
NOT USED - - 3

!~
4·1
MUX

E69

COUNT
ENABLE

F
J \/

Q GRANT

lDREQ

P2WR.L

INWD.H

~02
P1WR.L

RAM STATE
COUNTER 0·7
A
B
C E27

TS4

E28
12MHz_>
eLK

ACP1

TO TX.ACTION
lATCH

P1SCS

CHIP
P2SCS
SELECT
DECODER ~CS

~
V

Q-

END.L

WRTS

E77

~ j Jj

CLEAR

GRANT
DECODER

I> LATCH

REMOVES All
SROs AND
CANCELS
SLOW
CLOCK

.........
ACP2 }
ACB

---4

OUT
HB

p....... NOT USED

ENABLE ADDRESS
& DATA PATHS

F:::
SWR.L

WRITE
ENABLE

INfO

I--

ADDRESS

""'

COMMON
RAM

OUT
LB

CHIP
SELECT
LOGIC

DATA
CS (HI BYTE)
CS (LOW BYTE)

I t .....

(CSR
ADDRESSED)
RD1154

Figure 4-18

RAM Arbitration and Timing

Figure 4-19 gives timing details for a store access cycle.

12MHz ClK

SRQD

MUX

GRANT
SCAN CT ENABLE - - - - - - - - - \ - ,

B (WRTS)

C (TS4)
END.l

STOPS RAM TIMING COUNTER
RD1343

Figure 4-19

Store Access Timing Cycle

In Figure 4-19:
•

Write Time State (WRTS) is inverted to enable the selected Store Chip Select (SCS) signal via
the decoder. This action performs two functions:
1.

It enables the appropriate Chip Select (CS) signals via the chip select logic

It enables the appropriate write enable line. SWRL will be true when one of the gates

E83, E84, or E102 is enabled and its input is low. That is to say, whenPROCI, PROC2,
or the host are writing to the RAM.

4-29

•

SWR.L, and CS signals for the high and/or low byte, perform the RAM access. If SWR.L is
false, a read action is performed.

•

In a PROC1 write to the CSR, WRTS is used to set the TX.ACTION bit.

•

Time State 4 (TS4) - If a PROC 1 or PROC2 request is valid, the related microcomputer clock
will be running slow at 1.5 MHz. TS4 switches the clock back to 12 MHz. TS4 also de asserts
any active store request. SRQD will be deasserted on the next negative-going 12 MHz clock.

•

END.L holds the RAM timing counter at 101 as previously described.

•

Chip select logic uses ADO, 0 UTHB, and OUTLB to select a byte or word. Ifthe CSR is being
addressed, both chip select lines will be inhibited.

•

At the endofthe memory cycle, SRQD is de asserted. On the next negative 12 MHz clock, the
request latch and the RAM state counter will be reset, and the arbitrator will continue to scan
for requests.
NOTE
Store request signals (SRQDs) to E69 are
supplied by a 74S374 octal latch (E70), part
number 19-13671-51. This IC has special timing/
stability characteristics and must only be replaced
by an IC of the same type.

4.7.4 FIFO Counter Control
(See Figure 4-1.) It is the action of FIFO counters which makes a section of common RAM act as a FIFO.
During initialization, the counters are cleared. As characters and status are written to the FIFO, the Fill
counter steps ahead of the Empty counter which is still addressing the bottom of the FIFO. As the host
reads each word the Empty counter is stepped to address the next word. The difference between the
counters is the number of characters in the FIFO. Both counters will roll over after a count of 255.
Comparator circuits check the two counters. The conditions, empty, halffull, three-quarters full, and full
can be detected.
When EMPTY is deasserted, a hardware request is generated for receive interrupt service. This can be
disabled by software.
FULL is a signal which stops PROC2 from putting more characters into the FIFO.
ALARM is asserted when the FIFO becomes three-quarters full. It stays asserted until the FIFO
becomes less than half full. These signals are used when the DHV11 is programmed for auto-flow on
incoming characters. X-OFF characters are generated when the FIFO is more than three-quarters full.
X-ON characters are generated when it becomes less than half full.

To address the appropriate FIFO location, address bits SAD9 and SADS must be set to and 1
respectively and the appropriate address counter must be enabled. The correct SAD<9:S> code is
generated for any FIFO access, that is to say:
1.

When the FIFO (READ from base + 2) is addressed and ACB (Figure 4-1S) is asserted

4-30

When PROC2 generates a FIFO WRITE signal (FIWRL) and ACP2 (Figure 4-18) is
asserted.

4.7.4.1 Host Read from the FIFO - During a host READ from the FIFO the contents of the Empty
counter are latched onto SAD<7:0> by a decode of:
1.
2.
3.

INWD from the DC004 protocol IC
The RBUF address (base + 2)
ACB from the RAM arbitrator.

By the same signals, a strobe is generated to increment the counter ready for the next action. If the FIFO is
empty (EMPTY.L asserted), the strobe is inhibited.
Chip select logic decodes BSCS and INWD to generate CS signals for both bytes ofthe addressed word.
4.7.4.2 PROC2 Write to the FIFO - When PROC2 writes to the FIFO (FIWRL asserted), the
contents of the Fill counter are latched onto SAD<7:0> by an AND of:
1.
2.

FIWRL from PROC2 (see Table 4-3)
PROC2 accept signal (ACP2).

By the same signals, a strobe is generated to increment the counter ready for the next action. However,
because PROC2 can only write bytes, the strobe is only enabled when the low byte is written. For this
reason the low byte is always written last.
The high or low byte is selected by ADO from PROC2 (see Table 4-3). Chip select logic decodes the state
of ADO in order to generate the correct CS signal. The ADO = o state is used to enable the strobe which
increments the Fill counter.
4.7.5 Control/Status Register (CSR)
This is the main control register ofthe module. PROCI updates the high byte as necessary. The host can
poll the CSR to find the DRVl1 status.
Associated with the CSR (see Figure 4-20) are the following:
•

Indirect Address Register- a 4-bit latch (ADO to AD3) which holds the number of the channel
which is to be accessed. The contents ofthis register are used to index the addresses supplied by
the host. Figure 4-20 shows how indexing is performed.
NOTE
The indirect address register holds the channel
number. Therefore, to configure a channel, the
register has only to be loaded once. The control
registers for that channel can then be loaded in
sequence. Only when the host needs to access
another channel must the indirect address register
be reloaded.

•

Master Reset Latch - set by BINIT or by writing a 1 to bit 5 of the CSR Cleared by PlIO 14.L
from PROCI.
PlIOI4.L and MRST.L are ORed at E29 to make sure that MRST does not go false until the
end of PlI014.L strobe.

4-31

----

AD<15:0> INTERNAL BUS

r:: - - - --,

I CSR

J
+3vT- 0

MRST.L

SDAT51

RXIE

SDAT61

RX DATA AVAIL

SDATl

Qr----

Cf)
Cf)

Pl10l4.L

MRST

]

FIFO
CONTROL

I
I
I
1 ..

r-- -

0<{

z
z0<{

WRT
CSR
LOW BYTE

DIAGNOSTIC FAld
PROCl

TX DMA ERROR
~CTION

TXIE

....
AD<3:0> )

-... CHANNEL
SAD<3:0> (LINE)
... No.

•

DC003
INTERRUPT
CONTROLLER

SAD<7-4;:; REGISTER
.
BLOCK

OV ---+-

....

CSR tEAD

SET

I~ TX ACTION
LATCH
I r+ CLEAR

I
ADf4

SDAT12
SDAT14

?- SDAT<15:0>

* SDAT<11:8>

•

*
SDAT13
*

GRT

I
I

HOST (BUS)
ACCESS

~
-....

DATA
LATCHES

I
I

LATCHES
AND
DRIVERS

>
I

TX LINE No.

::r:
u

•

AD~
a::
0
0

E29

...,
SDAT<3:0>

CHANNEL ADDRESS):
INIT.L

--'
UJ

...

INDIRECT *
ADDRESS IND<3:0>
LATCH

REtT
CSR
READ

r---

I Yo
1 LS125

.....

1--- SDAT15
~iL

BITS MARKED •
ARE LATCHED

L ____ ---1

R01157

Figure 4-20

CSR and Register Address Circuits

•

DC003 interrupt controller- provides interrupt enable status to the CSR. If bit 6 is set, receive
interrupt is enabled. If bit 14 is set, transmit interrupt is enabled.

•
•

FIFO Control - indicates that there is valid data in the FIFO.

•

TX ACTION Latch - indicates when a transmit action has been completed. It is cleared when
the CSR is read.
PROCI - provides the following information:
On SDAT<II:8> On SDAT12
On SDAT13
On SDAT15
-

The related transmit channel number
Diagnostic fail bit
TX.DMA.ERROR bit
TX.ACTION bit.

4.7.6 Voltage Converter (SMPS)
TheDHVll'slinedrivers andteceiversneedboth +12 Vand-12 V supplies. The + 12 Vis supplied from
the backplane, but -12 V is derived from + 12 V by a voltage converter. This device uses switched-mode
power supply techniques to generate the negative voltage.
The circuit is built around a TIA94 switching regulator which uses pulse-width modulation to regulate the
-12 V output. The maximum current supplied is approximately 400 mAo
Switched-mode power supplies of the typeused by DHVll operate according to the following principles
(refer to the simplified circuit diagram of figure 4-21).
Switching pulses from a pulse width modulator/regulator switch a transistor (Q 1) to convert a dc input (V
IN) to a pulsed dc current in an inductor (L).
When Q1 is switched on, point X becomes positive causing current to flow through L. This generates a
magnetic field around L.
When Q1 is switched off, the current stops and the field collapses. This drives point X negative, and puts a
forward bias on diode D. Current generated by the collapsing field is transferred via the forward-biased
diode to the smoothing capacitors. In this way a negative voltage (V OUT) is generated.
As current is transferred to the output, the voltage at X rises until the diode is cut off again. The circuit wilt
stay in this state until the next switching pulse opens Q 1.
The inset of Figure 4-21 shows waveforms of the current through L, as seen by an oscilloscope across
R14. When Q1 is switched on, current rises linearly until Q1 is switched off again. The collapsing field
generates current, which reduces linearly as it is transferred to the output. With wider switching pulses,
more current is transferred to the output. Therefore, the power transferred (shaded in the inset) is
proportional to the width of switching pulses.
Feedback (VAR) from V OUT to the pulse width modulator is compared with a reference voltage (REF).
If VAR is too negative (V OUT is too high), the width of switching pulses is reduced. If VAR is too
positive, the width is increased. This action maintains V OUT at the correct level.
The same method of comparison is used to detect an over-current condition. When the voltage
(proportional to output current) across R14 'gets too high, the switching pulse width is reduced. This
reduces the current.

4-33

The switching frequency, selected by R12 and C9, does not change. In DHV11 this frequency is 36.7
kHz. If the oscillator is working, a sawtoothed 36.7 kHz waveform can be detected on pin 5 or 6.

+12V SUPPLY
VIN

FUSE

-12V

~----~----~~

VOUT

n:,I

k-------~I

~~+_~~O~F~F~~I

,
I

~II----"

;"'--____~:", __ j~ib
I
:-='-....;:;;...;.-'-~:

= POWER TRANSFERRED TO OIP

RD1158

Figure 4-21

DHV11 Voltage Converter
4-34

4.8

ROM-BASED DIAGNOSTICS

4.8.1

Self-Test
1

4.8.1: 1 General- WhenDHVll or the Q-bus is reset, theDHV11's master reset latch is set. This causes
the microcomputers to execute a DHVll self-test sequence.
During self-test, diagnostic codes are stored in the top six words of the common RAM, and also in the top
two bytes of PROC2's internal RAM.
At the end of self-test, control is passed to the communications firmware, which starts the initialization
routine. During initialization the diagnostic codes are transferred to the FIFO.
At the end of the initialization process, the master reset latch is reset, thereby clearing CSR bit 5 (MRST).
This bit is polled by the host. When MRST is cleared the host can read and interpret the diagnostic codes.
The 'diagnostic fail' bit in the CSR indicates whether the diagnostic program detected an error condition.
The green 'diagnostic passed' LED is on when the bit is cleared and vice-versa.
When a serviceable DHVll is reset, the LED follows this sequence:
1.
2.
3.
4.

Off for about 0.03 seconds
On for about 0.2 seconds
Off for 1 to 2.5 seconds
On permanently.

If the LED does not follow this sequence, the DHVll is defective.

4.8.1.2 Location and Interpretation of Diagnostic Codes - Figure 4.22 shows where diagnostic
information is loaded immediately after self-test. DIAG 0 to DIAG 7 are the diagnostic bytes stored
during self-test. Diag 0 to Diag 7 are the same bytes which are transferred during initialization.
HEX
ADDRESS

PROC2
INTERNAL RAM

DIAG 1

DIAGO

ADDRESS = BASE+ 2
(FIFO)

EXTERNAL RAM
MSB

LSB
DIAG 7
DIAG 6
DIAG 5
DIAG4
DIAG 3
DIAG 2

1111
1111
1111
1111
1111
1111
1111
1111

I
0111
0110
0101
0100
0011
0010
0001
0000

I
I
I
I

PHYSICAL (WORD)
ADDRESSES (HEX)

03FF
03FE
03FD
03FC
03FB
03FA

TOPDF
EXTERNAL
RAM
(SCRATCH
AREA)

Diag 7
Diag 6
Diag 5
Diag 4
Diag 3
Diag 2
Diag 1
Diag 0

RD1162

Figure 4-22

The high byte ofRBUF can be interpreted as in Chapter 3, Section 3.2.2.2, except that bits 11 to 8 are not
the line number. They indicate the sequence of the diagnostic byte. That is to say, 0 = first diagnostic byte,
1 = second diagnostic byte, and so on.
Chapter 3, Programming, explains how to interpret diagnostic codes.
4.8.2 Background Monitor Program (BMP)
Many of the regular operations by PROC 1 and PROC2 are controlled by internal timers. The timers
generate internal interrupts which vector the microcomputers to the appropriate routine.
When they are not busy with other tasks, PROCI and PROC2 check their timer-generated interrupts. If
there is an error, a NOGO report is passed to the host via the FIFO.
BMP can also be activated by command from the host. In this case a GO/NOGO report is passed to the
host.
Any time the BMP finds an error, DIAG.F AIL is set in the CSR and the diagnostic LED is switched off.
The LED will stay off, even if the fault clears.

4-36

CHAPTER 5
MAINTENANCE
5.1 SCOPE
This chapter explains the maintenance strategy and how the diagnostic programs are used to find a
defective Field Replaceable Unit (FRU). The description is supplemented by a troubleshooting
flowchart.
5.2

MAINTENANCE STRATEGY

5.2.1 Preventive Maintenance
No preventive maintenance is planned for this option. However, if the host system is being serviced, a
visual check should be made for loose connectors and damaged cables.
5.2.2 Corrective Maintenance
The M3104 module, BC05L-xx cables, and H3173-A distribution panels are all FRUs. Corrective
maintenance is therefore based on finding and replacing the defective FRD. However, if the fault is not in
the option, it may be possible to perform tests of external equipment. Figure 5-1 can be used as a basis for
troubleshooting.

M3104

DISTRIBUTION
PANELS
H3173-A

BC05L-xx
CABLES

MODEM

-1--1

MODEM

TERMINAL
ETC.
RD1164

Figure 5-1

Troubleshooting Connection Diagram
5-1

5.3 INTERNAL DIAGNOSTICS
Internal diagnostics run without intervention from the operator. There are two tests, called self-test and
background monitor test.
5.3.1 Self-Test
This test starts immediately after bus or device reset. It is a limited test, which checks the internally
accessible parts of the DHVII and gives a GO/NOGO indication via the DIAG.F AIL bit and the
'diagnostics passed' LED. Self-test also reports error or status information to the host via the FIFO. This
information is used by system-based diagnostics such as CVDH??
During a successful (no defects) self-test, the LED flashes OFF/ON/OFF before coming ON
permanently. The first OFF period is very short and may not be seen. However, if the LED goes off and
then comes on permanently, the diagnostic has found no faults. If self-test is skipped (see Chapter 3,
Section 3.3.10.3), the LED will just go on.
Because ofthe limitations of self-test, a correct sequence does not guarantee that all sections of the module
are good.
5.3.2 Background Monitor Program (BMP)
The BMP carries out tests on the DHVII when the option is not engaged in other tasks. If it detects an
error, the BMP reports to the host via the FIFO. It also switches off the 'diagnostics passed' LED.
By writing codes to the LPR, the host can cause the BMP to report the DHVII status even if an error has
not been detected. It is used if the host suspects that the DHVll is dead.
NOTE
More detail of the self-test and BMP diagnostics
is given in the technical description and programming sections of this manual.
5.4. XXDP+ DIAGNOSTICS
In order to run these diagnostics, the host system must have at least the minimum configuration specified.
Loopback connectors will be needed for some of the tests. For more information, refer to the program
documentation at the beginning of the CVDH?? listings.
5.4.1 CVDHA?, CVDHB?, and CVDHC?
These programs form a Functional Verification Test (FVT) which runs on Q-bus members of the PDP-II
processor family. This test runs under the PDP-II Diagnostic Supervisor. It will run standalone using the
XXDP+ monitor, or it can be run automatically under the Automatic Product Test (APT) system.
The minimum system requirements are:
•
•
•
•
•

Q-bus CPU
32K bytes memory
Console terminal
XXDP+ load device with Diagnostic Runtime Services (DRS) supervisor
DHVII option.

5-2

In order to test the full DMA address capability of the DHVll, the diagnostic uses the following address
patterns. If the high address lines are to be tested, the host must have memory at the following locations as
well as the 32K bytes defined in the previous paragraph:
Address bits

Memory address
(High bank)

Memory address
(Low bank)

Ifmemory is not available at these locations, some high DMA address bits will not be tested. This will not
be considered as an error. The operator, by answering a prompt, can display information specifying the
bits which were tested.
5.4.1.1 Functions ofCVDHA? - This program checks the reset and the register access functions, and
verifies that the handshake between the DHVl1 and the host is operating correctly. It also checks reports
from the self-test and BMP.
Loopback connectors are not used in this test.
5.4.1.2 Functions of CVDHB? - This program checks the major communication functions of the
DHV11. It verifies the correct operation of modem control signals and the register bits which control and
report them. CVDHB? does not perform extensive data transmission and reception tests.
Loopback connectors can be used in this test.
5.4.1.3 Functions of CVDHC? - This program checks the major communication functions which
use the D U ARTs. It checks split-speed operation, and verifies that D U ART errors are reported correctly.
Extensive data transfer tests are performed in both DMA and single-character modes. CVDHC? also
includes a keyboard test.
Loopback connectors can be used in this test.
5.4.2 DECX/11 Exerciser
When a DHV11 or other option is installed or replaced, it is necessary to run the DECX/II exerciser
CXD HV xx. The exerciser must first be configured to match the host system. For more information, refer
! to the DECX/ll User Manual (AC-F035B-MC) andDECX/ll Cross-Reference (AC-F05SC-MC).
DECX/I1 should not be run until all modules have passed their own diagnostic tests. Therefore, before
running the exerciser, the DHVll must pass all phases of CVDH??
5.5 DIAGNOSTIC SUPERVISOR SUMMARY
The CVDH?? diagnostics have been written for use with the Diagnostic Runtime Services (DRS)
supervisor. DRS, which provides the interface between the operator and the diagnostic programs, can be
used with load systems such as ACT, APT, SLIDE, XXDP+, and ABS loader. By answering prompt
questions supplied by the supervisor the operator can define the following:
1.

2.
3.

The hardware configuration of the DHVll s being tested
The type of test information to be reported
The conditions under which the test should be terminated or continued.

5-3

5.5.1 Loading the Supervisor Diagnostic
The diagnostic program may be loaded and started in the normal way, using any of the supported load
systems. For example, using XXDP+, the program CVDHBABIN is loaded and started by typing
R CVDHBA
The diagnostic and the supervisor will be loaded and the program started. The program types the following
message:
CVDHBABIN
DRSC7
CVDHB-A-O
DHV-l1 FUNCT TEST PART2
UNIT IS DHV-ll
RESTART ADDR: xxxxxx
DR>
DR> is the prompt for the diagnostic supervisor routine. At this point a supervisor command must be
entered (supervisor commands are listed in Section 5.5.3).
AO on the end of CVDHB indicates the revision level (A) and the patch level (0).
5.5.2

Four Steps to Run a Supervisor Diagnostic
1.

Enter the start command.
When the prompt DR> is issued, type:
STA/PASS:1/FLAGS:HOE<CR>
The switches and flags are optional.

Answer the hardware parameter questions.
The program prompts with:
CHANGE HW?
You must answer Y to this query if you want to change the hardware parameter tables. The
program will then ask a number of hardware parameter questions in sequence. For example,
the first question is:
# UNITS?

At this point, enter the number of units to be tested.
NOTE
Some versions of the diagnostic supervisor do not
ask the CHANGE HW? question at the first start
command. Instead they go straight into the hardware parameter question sequence.
The answers to the questions are used to build hardware parameter tables (P-tables) in memory. A series
of questions is posed for each device to be tested. A hardware Potable is built for each device.

5-4

Answer the software parameter questions.
When all the hardware P-tables are built the program responds with:
CHANGE SW?
If other than default parameters are wanted for the software, type Y. If the default parameters
are wanted, type N.
If you type Y, a series of software questions will be asked and the answers to these will be
entered into the software P-table in memory. The software questions will be asked only once,
regardless of the number of units to be tested.

Diagnostic execution
Mter the software questions have been answered, the diagnostic starts to run.
What happens next is determined by the switch options selected with the start command, or
errors occurring during execution of the diagnostic.

5.5.3 Supervisor Commands
The supervisor commands that may be issued in response to the DR> prompt are as follows:

•
•
•
•
•
•
•
•
•
•
•

START

Starts a diagnostic program

RESTART

When a diagnostic has stopped and control is given back to the supervisor,
this command restarts the program from the beginning

CONTINUE

Allows a diagnostic to continue running from where it was stopped

PROCEED

Causes the diagnostic to resume with the next test after the one in which it
halted

EXIT

Transfers control to the XXDP+ monitor

DROP

Drops units specified until an ADD or START command is given

ADD

Adds units specified. These units must have previously been dropped

Prints out statistics if available

DISPLAY

Displays P-Tables

FLAGS

U sed to change flags

ZFLAGS

Clears flags.

All of the supervisor commands except EXIT, PRINT, FLAGS, and ZFLAGS can be used with switch
options.

5-5

5.5.3.1 Command Switches
Switch options may be used with most supervisor commands. The available switches and their functions
are as follows:
•

/TESTS:

Used to specify the tests to be run (the default is all tests). An example of the
tests switch used with the start command to run tests 1 to 5, 19, and 34 to 38
would be:
DR> START/TESTS:I-5:19:34-38<CR>

•

/PASS:

U sed to specify the number of passes for the diagnostic to run. For example:
DR> START/PASS: 1<CR>
In this example, the diagnostic would complete one pass and give control
back to the supervisor.

•

/EOP:

Used to specify how many passes of the diagnostic will occur before the end
of pass message is printed (the default is one).

•

/UNITS:

U sed to specify the units to be run. This switch is valid only if N was entered
in response to the CHANGE HW? question.

•

/FLAGS:

U sed to check for conditions and modify program execution accordingly.
The conditions checked for are as follows:
:HOE
:LOE
:IER
:IBE
:IXE
:PRI
:PNT
:BOE
:UAM
:ISR
:IOU

Halt on error (transfers control back to the supervisor)
Loop on error
Inhibit error reports
Inhibit basic error information
Inhibit extended error information
Print errors on line printer
Print the number of the test being executed before execution
Ring bell on error
Run in unattended mode, bypass manual intervention tests
Inqibit statistical reports
Inhibit dropping of units by program.

5.5.4 Control/Escape Characters Supported
The keyboard functions supported by the diagnostic supervisor are as follows:
•

CTRL/C (/\C)

Returns control to the supervisor. The DR> prompt would be typed in
response to CTRL/C. This function can be typed at any time.

•

CTRL/Z ("Z)

Used during hardware or software dialogue to terminate the dialogue and
select default values.

•

CTRL/O (/\0)

Disables all printouts. This is valid only during a printout.

•

CTRL/S ("S)

Used during a printout to temporarily freeze the printout.

•

CTRL/Q (/\Q)

Resumes a printout after a CTRL/S.

5-6

5.5.5 Example Printouts
Two examples of diagnostic printouts follow. The first is error-free. In the second test, the device address
is incorrect.
Entries by the operator are underlined. An underline without an entry shows that the operator has pressed
the RETURN key to select the default parameter.
1.

Error-free pass
R CVDHBA
CVDHBA.BIN
DRSC7
CVDHB-A-O
DHV-11 FUNCT TEST PART2
UNIT 1 IS DHV-ll
RESTART ADDR: 147670
DR)START
CHANGE HW (L)

? ~

*' UNITS (D) ? 1..
UNIT 0
CSR ADDRESS: (0) 160460 ? 160500
INTERRUPT VECTOR ADDRESS: (0) 300 ?
ACTIVE LINE BIT MAP: (0) 377?__
TYPE OF LOOPBACK (l=INTERNAL, 2=STAGGERED,
3=25 PIN CONNECTOR, 4=MODEM):
INTERRUPT BR LEVEL:

(0)

2 ?

4 ?

CHANGE SW (L) ? Y
REPORT UNIT NUMBER AS EACH UNIT IS TESTED: (L) Y ?
NUMBER OF INDIVIDUAL DATA ERROR TO REPORT ON A LINE:
CVDHB EOP 1
o CUMULATIVE ERRORS
DR)EXIT

5-7

(D) 0 ?

Test with wrong device address selected
R CVDHBA
CVDHBA.BIN
DRSC7
CVDHB-A-O
DHV-ll FUNCT TEST PART2
UNIT IS DHV-ll
RESTART ADDR: 147670
DR>START
CHANGE HW (L) ? Y
:11= UNITS

(D)

? 1

UNIT 0
CSR ADDRESS: (0) 160460 ? 160500
INTERRUPT VECTOR ADDRESS: (0) 377 ?
ACTIVE LINE BIT MAP: (0) 377 ? __
TYPE OF LOOPBACK (l=INTERNAL, S=STAGGERED,
3=25PIN CONNECTOR, 4=MODEM):
INTERRUPT BR LEVEL: (0) 4 ?
CHANGE SW (L)

(0)

2 ?

?:i.

REPORT UNIT NUMBER AS EACH UNIT IS TESTED: (L) Y ? __
NUMBER OF INDIVIDUAL DATA ERRORS TO REPORT ON A LINE (D)

0 ?

CVDHB DVC FTL ERROR 00101 ON UNIT 00 TST 001 SUB 000 PC: 021354
DEVICE REGISTER ACCESS ERRORS
BUS TIME-OUT TRAP CAUSED BY READ ATTEMPT
BUS TIME-OUT TRAP CAUSED BY WRITE ATTEMPT
DHV MAY BE AT THE WRONG Q-BUS ADDRESS.
UNIT

0 DROPPED FROM FURTHER TESTING

PASS ABORTED FOR THIS UNIT
CVDHB EOP 1
1 CUMULATIVE ERRORS
DR>

5.6 CORRECTIVE MAINTENANCE ON MICROVAX I SYSTEMS
Corrective maintenance is performed when operational failures or diagnostic tests indicate that the
DHV11 is defective. Diagnostic test programs for DHV11 s installed in MicroVAX I systems are listed
below.
EHKMV
EHXDH

Macroverify-MicroVAX Systems Test
DHV11 Tests

5.6.1 The Macroverify Diagnostic
Macroverify is a system test which is quick to run, and is used:
•
•
•

As a first-line check before using device diagnostics
As a confidence check
To verify the complete system after installation or maintenance.

5-8

The Macroverify diagnostic runs on a standalone basis and operates when the CPU Tests diskette is
booted from one of the RX50 drives. The program takes up to four minutes to run and needs 30K bytes of
memory.
The tests performed by Macroverify do not destroy information recorded on the disks.
5.6.1.1

Setting Up Procedures - Power up all devices in the configuration. Set all the disk drives for

VO. Place a diskette in each RX50 drive. Disconnect any external cables or test connectors from the
DLVJ1 and DHVl1 distribution panels. If the system is not set up correctly, Macroverify will output a
TEST FAILED message.
5.6.1.2 Bootstrapping Procedure - To boot the Macroverify diagnostic, mount the CPU Tests
diskette in one of the RX50 drives and type:
BDUAI

(boot from drive 1)

BDUA2

(boot from drive 2)

or:
5.6.1.3 Macroverify Operation - Macroverify runs as soon as the boot operation is completed
successfully. The program contains routines which check for all possible system configurations.
For each possible device, a test is made to see ifthe device responds to its assigned Q-bus address. If the
device does not respond, the following status message is displayed on the console.
DEVICE xxxxx WITH CSR yyyyyy, VECTOR zzz NOT FOUND.
NO TESTING PERFORMED.
NOTES
1.

The vector number will not be displayed for
devices with floating vectors.

The standard address and vector are 7604408
and 3008 respectively, but early versions of
Macroverify expect the address to be 7605008.
The status message will be displayed even if
the DHV11 is configured correctly. Later
versions of Macroverify test the DHVll at
the standard address of 760440 vector 300.
Note that, if other floating address devices
are installed, the D HVll address will be
moved within the floating address space, and
will not be recognised by Macroverify.

For each device that responds to its assigned address, a sequence of user-level tests is performed. A 'test
succeeded' or 'test failed' message is displayed, together with the time taken for a successful test
5.6.2 DHVll Diagnostic EHXDH
The EHXDH diagnostic is resident on the MicroVAX system tests diskette number 3. This diagnostic
runs under VDS, and should be run if an operational failure or the Macroverify program indicates a
defective DHVII.

5-9

5.6.2.1 Setting Up Procedures - Before running the diagnostic, make sure that the address and
vector are correctly set up, as described in Chapter 2, Sections 2.3.1 and 2.3.2.
Disconnect all external cables from the distribution panel.
I

5.6.2.~

Bootstrapping Procedures - To boot from the MicroVAX system test diskette, mount
diskette 2 on drive 0 of the RX50 drive, and diskette 3 on drive 1 of the RX50.
NOTE
The DHVII diagnostic is contained on the third
diagnostic diskette. This diskette does NOT contain
a bootable diagnostic monitor. Therefore, the
user must boot diskette 2 on drive 0, and load the
diagnostic from diskette 3 on drive 1.

The diagnostic can now be booted in the manner described in the first example of the test format.
Examples of the test format are shown in the following pages. Operator inputs are underlined in the
examples.
»> B/IO DUAl
ATTEMPTING BOOTSTRAP
VAX DIAGNOSTIC SOFTWARE
PROPERTY OF
DIGITAL EQUIPMENT CORPORATION

** CONFIDENTIAL AND PROPRIETARY **
Use Authorized Only Pursuant To A Valid Right-to-use License
DIAGNOSTIC SUPERVISOR.
DS> ATTACH RXSO
Device Link? DUA
Device Name? DUA2
DS> SET LOAD DUA2:

ZZ-EHSAA-V6.13-001

I-JAN-1983 00:00:03

The above sequence enables diskette 3 mounted in drive 1 (logical device DUA2)
How to Call Up the Directory for This Diagnostic
DS> DIR
Directory _DUA2:[SYSO.SYSMAINT]
EHXDH.EXE;l
EVRMA.EXE;l
EVRMC.EXE;l

EHXDH.HLP;l
EVRMA.HLP;l
EVRMC.HLP;l

EHXVS.EXE;l
EVRMB.EXE;l

Total of 10 files

5-10

EHXVS.HLP;l
EVRMB.HLP;l

Several test options are available to the user. Details of these options may be obtained by running the
diagnostic HELP file.
Example of Running a HELP File

DS> HELP EHXDH
HELP
The DHVll is an asynchronous multiplexer that provides an
interface between eight asynchronous serial data communications
channels and any processor that supports Q 22 bus devices.
EHXDH is the name of the MICRO VAX Standalone Diagnostic.
It is
to be used to verify that a DHVll connected via Q 22 bus to a MICRO VAX
system is functioning correctly.
Additional information available:
'HELP
OPTIONS
SECTIONS

RUN TIME
EVENT FLAGS
Errors

REQUIREMENTS
SUMMARY
TEST DESC

PREREQUISITES
DEVICE

ATTACH DHVll
QUICK

How to Attach, Load, and Start a DHV Diagnostic at Standard Address and Vector

DS> LOAD EHXDH
DS> ATT DHVll
Device Link? HUB
Device Name? TXA
Device Address? 760440
Vector Address? 300
BR Level? .!.
DS> SEL TXA:

5-11

Example of Running an Internal Test
os> START
.• Program: OHV11 - VAX Functional Verification Test, revision 1.0, 29 tests,
at 00:02:30.28.
Testing: TXA
lines to test [(ALL) or 0,1,2, •.. 7] <RET>
Line Speed [(4800), 50, 75, 110, 134.5, 150, 300, 600, 1200, 1800, 2000, 2400,
7200, 9600, 19200, 38400] 9600
lOOp type [(INTERNAL), EXTERNAL, STAGGERED] <RET>
Micro Processor number 1 ROM version is 2
Micro Processor number 2 ROM version is 2
Frame error bit not tested; wrong looptype.
End of run, 0 errors detected, pass count is 1,
time is l-JAN 1983 00:06:28.40

(This is not an error)
(Successful pass)

Example Showing Sections Available for the EHXDH Diagnostic
OS> HELP EHXDH SEC
SECTIONS
There two sections supplied with this diagnostic;
• MODEM
•

ECHO

The modem section runs a modem loopback test and is
by using the vds command ST/SE=MOOEM.

invoked

The ECHO section allOW a user to select a line with a
terminal attached. All characters typed on the terminal will be
checked for errors, then echoed back to the terminal.

Example Showing the Options That Are Available
OS> HELP EHXDH OPT
OPTIONS

Additional information available:
LINES TO TEST

BAUO RATE

LOOP TYPE

5-12

Example Showing the Tests Available for the EHXDH Diagnostic
os> HELP EHXDH TEST

TEST OESC
Additional information available:
Test
No.

Test Description

Device Register Address Test. This test verifies that the UUT will respond to the proper
Q-bus handshaking when accessed. Line 0 only is tested.

Master Reset/Self-Test Test. This test verifies that the self-test is operational.

Master Reset/Skip Self-Test Test. This test verifies that the master reset bit clears within a
short time after it is set, if the Skip Self-Test sequence is used. The test verifies that the Skip
Self-Test return codes are normal.

Diag Field (BMP) Test. This test verifies that a request for BMP code reporting is answered
by the UUT within the specified time.

Self-Test Forced Failure Test. This test verifies that the self-test will report errors correctly
when it is forced to fail. The test verifies that the diagnostic fail bit will go to the active and
inactive states.

ROM Version Printout Test. This test reports the versions of numbers of the 8051 ROMS.

ID Bit Test. This test verifies that the identity bit which determines whether the device is a
DHUll or a DHVII is either set (DHUll) or clear (DHVll).

Tx Enable/Action. This test verifies that if a data word is written without the Tx data bit set, no
Tx action is generated.

10.

Rx Data Available/Rx Data Valid/Rx Enable Test This test verifies the following.
•

That all relevant bits are initialized correctly

•

That Rx DATA AVAILABLE and Rx DATA VALID remain clear if a character is
transmitted with Rx ENABLE clear

•

That Rx ENABLE sets and clears data and on the current line only

•

That Rx receives data and on the current line only

•

That Rx DATA AVAILABLE is cleared when the buffer is read, but that Rx DATA
VALID remains set until the FIFO is empty

•

That transmitted data is correct and that no errors have occurred

5-13

11.

Maintenance Mode Test This test verifies that the maintenance modes are working correctly.
The test will operate only if staggered loopback is selected.

12.

Rx FIFO Test This test verifies that the FIFO locations can be uniquely addressed from the
Q22 bus. The FIFO is filled with 256 unique bytes of data, and is then checked for data
integrity.

13.

Interrupts Test This test verifies that the Tx and Rx interrupts are operating correctly.

14.

DMA Start/DMAAbort Test This test verifies that each DMA start bit will initiate aDMA
Tx on a line, that it can be aborted and resumed, and that DMA aborts and that completions
cause interrupts.

15.

Byte Count Register Test This test verifies that the byte count registers function correctly, by
checking that the number of bytes received is the same as the number of bytes transmitted.

16.

DMA Address/Data Test This test verifies the ability of the device to correctly increment
addresses and byte counts.

17.

Speed Test This test transmits characters at all speeds on all lines in internalloopback mode,
using the Tx FIFO to transmit characters.

18.

XON/XOFF Test This test verifies that X-ON/X-OFF control is functioning correctly.

19.

Data Format Test This test verifies that all sizes and formats function correctly. Ten
characters are used and each line is verified.

20.

Modem Signal Test This test verifies that changing the UUT line control DTR bit affects the
state of the DTR control line and looped signals, and verifies that no unexpected bits are set.
The test also verifies that changing the UUT line control RTS bit affects the state of the RTS
control line. Provision is made for testing the ability of the modem to connect to another
modem.

21.

Framing Error/Break Bit Test. This test verifies that forced framing errors are reported
correctly.

22.

Parity Generation/Detection Test This test verifies that parity works correctly and that
parity errors are reported. The test functions only in staggered loop back.

23.

Overrun Detection Test This test verifies that the UUT will receive the maximum number of
characters without causing an overrun error, and that the receipt of one more character will
cause an overrun error.

24.

Exerciser Test. This test causes an lines to transmit simultaneously. 1024 byte buffers are used
for transmission and reception. The format is 8 bit, no parity, and 1 stop bit.

5-14

25.

Modem Loop Test. This test is run on a modem in loopback mode, or is run on a remote modem
that is in remote loopback mode.

26.

Terminal Echo Test. This test loops back all characters that are received on a line. The
operator is asked to which line the characters are to be echoed; this will permit isolation of the
direction of a failing line.

27.

I.AUTO Test. This test verifies that the I.AUTO bit is functioning correctly.

28.

Split Speed Test Part A This test verifies the correct functioning of split speed operation. The
test operates only in staggered loopback mode.

29.

Split Speed Test Part B. This is a continuation of the previous test.

Running Two Passes of the Diagnostic Staggered Loopback Test
Remove the ribbon cables from the distribution panel and connect them to the H3277 test connector, as
shown in Figure 2-5.

DS> START/PASS=2
.. Program: DHV11
VAX Functional Verification Test, revision 1.0, 29 tests,
at 00:09:30.42.
Testing: TXA
lines to test [(ALL) or 0,1,2, ... 7] <RET>
Line Speed [(4800), 50, 75, 110, 134.5, 150, 300, 600, 1200, 1800, 2000, 2400,
7200, 9600, 19200, 38400] 9600
loop type [(INTERNAL), EXTERNAL, STAGGERED] STAGGERED
Micro Processor number 1 ROM version is 2
Micro Processor number 2 ROM version is 2
•• First pass done, 0 errors detected, time is

1-JAN-1983 00:14:38.06

Micro Processor number 1 ROM version is 2
Micro Processor number 2 ROM version is 2
•. End of run, 0 errors detected, pass count is 2,
time is I-JAN-1983 00:19:05.14
Restore the ribbon cables to their original positions in the distribution panel. See Figure 2-5.

5-15

The following example is the single loopback test with the H3277 loop back connector on line 0 of
the distribution panel (see Figure 2-5)
DS> START
•• Program: DHVl1 - VAX Functional Verification Test, revision 1.0, 29 tests,
at 00:30:19.98.
Testing: TXA
lines to test [(ALL) or 0,1,2, .•. 7] 0
Line Speed [(4800), 50, 75, 110, 1:34.5, 150, 300, 600, 1200, 1800, 2000, 2400,
7200, 9600, 19200, 38400] <RET>
loop type [(INTERNAL), EXTERNAL, STAGGERED] EXTERNAL
Install all H325 turnaround connectors, type RETURN key when done [(No), Yes]
<RET>
Micro Processor number 1 ROM version is 2
Micro Processor number 2 ROM version is 2
Frame error bit not tested; wrong looptype.
•. End of run, 0 errors detected, pass count is 1,
time is I-JAN 1983 00:33:02.17

(This is not an error)

Remove all the test connectors, and reconnect the terminals ifthey have been removed for test purposes.
The following example is of the terminal echo test line O. Any character typed on the terminal will be
echoed.
This test can only be effective if an additional VDU and cable are available.
DS> START/SEC=ECHO
•. Program: DHVl1 - VAX Functional Verification Test, revision 1.0, 29 tests,
at 00:33:38.60.
Testing: TXA
lines to test [(ALL), or 0,1,2, ... 7] JL
Line Speed [(4800), 50, 75, 110, 134.5, 150, 300, 600, 1200, 1800, 2000, 2400,
7200, 9600, 19200, 38400] 9600
"C

5-16

The following test example shows errors
> START

•• Program DHVII - VAX Functional Verification Test, revision 1.0, 29 tests,
at 00:22:17.95.
Testing: TXA
lines to test [(ALL) or 0,1,2, ... 7] JL
Line Speed [(4800), 50, 75, 110, 134.5, 150, 300, 600, 1200, 1800, 2000, 2400,
7200, 9600, 19200, 38400] 9600
loop type [(INTERNAL), EXTERNAL, STAGGERED] EXTERNAL
Install all H3277 turnaround connectors, type RETURN key when done [(NO), Yes]
YES
Micro Processor number 1 ROM version is 2
Micro Processor number 2 ROM version is 2
DHV11 - VAX Functional Verification Test - 1.0 ********
Pass 1, test 18, subtest 1, error 15, 1-JAN-1983 00:24:56.18
Hard error while testing TXA: XON/XOFF Test failed

********

Current line number = 0
********

End of Hard error number 15 ********

DHV11 - Vax Functional Verification Test - 1.0 ********
Pass 1, test 20, subtest 1, error 16, l-JAN 1983 00:25:06.66
Hard error while testing TXA: Modem Signal Test failed

********

Current line number = 0
********

End of Hard error number 16 ********

DHVll - VAX Functional Verification Test - 1.0 ********
Pass 1, test 20, subtest 1, error 22, 1-JAN-1983 00:25:15.74
Hard error while testing TXA: Modem Signal Test failed

********

Current line number = 0
********

End of hard error number 22 ********

DHVll - VAX Functional Verification Test - 1.0 ********
Pass 1, test 20, subtest 1, error 35, l-JAN-1983 00:25:24.87
Hard error while testing TXA: Modem Signal Test failed

********

Current line number = 0
********

End of Hard error number 35 ********

5-17

Frame error bit not tested; wrong looptype.
******** DHVll - VAX Functional Verification Test - 1.0 ********
Pass 1, test 21, subtest 1, error 3, I-JAN-1983 00:25:36.46
Hard error while testing TXA: Framing Error/Break Bit Test failed
Current line number = 0
********

End of Hard error number 3 ********

DHVll - VAX Functional Verification Test - 1.0 ********
Pass 1, test 24, subtest 1, error 8, I-JAN-1983 00:25:54.65
Hard error while testing TXA: Exerciser Test Failed

********

Current line number = 0
********

End of Hard error number 8 ********

DHVll - VAX Functional Verification Test - 1.0 ********
Pass 1, test 27, subtest 1, error 9, l-JAN-1983 00:26:04.10
Hard error while testing TXA: I.auto test failed

********

Current line number = 0
********

End of Hard error number 9 ********

.. End of run, 7 errors detected, pass count is 1,
time is l-JAN-1983 00:26:12.89
DS>

5.7 RUNNING MICROVAX II DIAGNOSTICS
These diagnostics are entirely different from MicroVAX I diagnostics in that they are based on
VAXELN, and not on the VAX diagnostic supervisor as in MicroVAX I.
5.7.1 Overview of the MicroVAX II Maintenance System
The MicroVAX II Maintenance System (MMS) is a menu-driven maintenance and diagnostic system
which uses the Micro VAX Diagnostic Monitor (MDM). MMS is booted from an RX50 diskette drive, or
from a TK50 tape drive. MMS is available in two versions.

•

The customer version packed with each system
The service version which is available to the customer under license

5-18

The two versions share the same main menu, but only the maintenance version contains full
troubleshooting and maintenance capabilities.
The loading procedure is the same for both versions. After the power-on preliminaries have completed,
there is a countdown sequence before the main menu is displayed.
5.7.2. Running the Customer Version of the Micro VAX II Diagnostic
The customer will proceed as described in Section 5.7.3 for the service version, but selection from the
main menu is limited, and options 3 and 4 are not available. Normally the customer will select option 1 to
test the system.
If there is a failure during the customer version of the diagnostics, an error message is output to the
terminal. The user may then want to consider whether help is needed from DEC trained staff.
5.7.3 Running the Maintenance Version of the MicroVAX II Diagnostic
When booting from the TK50, make sure that all fixed disk drives are off-line, and that the doors to all
diskette drives are open. Booting the TK50 takes about three minutes.
If the halts are disabled before the system is powered ON, MMS will automatically boot.
If the halts are enabled on the MicroVAX II system, the prompt will appear when the system is powered
on. To boot the MMS under these conditions, enter the commands after the prompt as follows.

»> bDUAx
(where x is the number of the disk drive containing the MMS)

»> bMUAx
(where x is the number of the tape drive containing the MMS)
~ter booting, a disclaimer message appears on the screen, together with copyright and license
mformation, and the revision level of MMS. The revision level is important because the newer levels
include testing for additional options.

An example of the format now follows. Operator inputs are underlined.

5-19

»> B DUA2
KA630-A. V1.0
Performing normal system tests.
7 •• 6 •• 5 •• 4 •• 3 ••

Tests completed.
Loading system software.
2 •• 1 •. 0 ••

VAXELN V2.0-00
MicroVAX

Maintenance

System

MDM Version 1.02

CONFIDENTIAL DIAGNOSTIC SOFTWARE
PROPERTY OF
DIGITAL EQUIPMENT CORPORATION
Use Authorized Only Pursuant to a Valid Right-to-use License
Copyright (c) 1985
Digital Equipment Corporation
Current date and time is: 17-NOV-1985 15:30:11.64
Press the RETURN key to continue,
OR enter new date and time, then press the RETURN key.
[DD-MMM-YYYY HH:MM]: <RET>
MAIN MENU
1 -

Test the system

2 -

Show system configuration and devices

3 -

Display the Utilities Menu

4 -

Display the Service Menu

5 -

Exit MicroVAX Maintenance System

Type the number, then press the RETURN key. > 2

5-20

SYSTEM CONFIGURATION AND DEVICES
SYSTEM CONFIGURATION
CPUA ••. MicroVAX CPU
KA630-AA 1MB, FPU MOO HOO
MEMA •.• MicroVAX memory system
3 megabytes. 6144 Pages.
KA630 ••• CPU module, 1MB on-board memory.
MS630-BA ••• Quad height memory module, 2MB.
RQDXA ••• Winchester/floppy disk controller.
Revisions =94 and 6
RX50 .•• Floppy disk drive.
Cannot identify drive, Offline.
TK50A .•• Cartridge Tape Controller
DEQNAA ... Ethernet controller.
08-00-2B-02-08-9D
DHVllA ... 8 line asynchronous multiplexer
ROM Rev 11 9
Press the RETURN key to return to the previous menu. > <RET>
>

MAIN MENU
1 - Test the system
2 - Show system configuration and devices
3 - Display the Utilities Menu
4 - Display the Service Menu
5 - Exit MicroVAX Maintenance System
Type the number, then press the RETURN key. > 4

5-21

SERVICE MENU
CAUTION: This menu is intended for use by qualified service
personnel only. Misuse of the commands could destroy data.
1 - Set test message and parameters
2 - Exercise system continuously
3 - Display the device menu
4 - Enter system commands
Type the number, then press the RETURN key,
OR type 0 and Press the RETURN key to return to the main menu. > 4
SERVICE MENU
ENTER SYSTEM COMMANDS

CAUTION: You are entering the MicroVAX Diagnostic Monitor (MOM)
via the command line processor. There are no menus once you
enter the monitor. Refer to the MDM User's Guide for detailed
instructions.
To return to the Main Menu from the MicroVAX Diagnostic Monitor
type "RESTART" and press the RETURN key, or reboot the system.

Press the RETURN key to enter the MicroVAX Diagnostic Monitor,
OR type 0 and Press the RETURN key to return to the Main Menu. > <RET>

5-22

MDM»

HELP

Currant Commands Are:
CONFIGURE
SELECT Diag_Name
ENABLE Diag_Name
DISABLE Diag_Name
SET DETAILED MESSAGE ON
DETAILED MESSAGE OFF
MODE VERIFY
SERVICE
PROGRESS OFF
PROGRESS BRIEF
PROGRESS FULL
SECTION FUNCTIONAL
UTILITY
EXERCISER
TEST
ALL
Number
PASSES Number
START
START ALL
SHOW CONFIGURATION
SHOW DEFAULT
SHOW DEVICE UTILITIES
SHOW ERRORS
MDM» CONFIG
MDM»

- Configure System
- Select diagnostic (all units) to run
- Allow a diagnostic to run
- Prevent a diagnostic from running
- Display detailed messages
- DO NOT display detailed message
- Set verify mode tests
- Set service mode tests
- Print no progress messages
- Controller progress messages
- Controller and test progress messages
- Set functional test section
- Set utility test section
- Set exerciser test section
- Run all tests
- Run only test number xx
- Run tests for xx passes
- Start selected tests running
- Start all tests running
- Show configuration information
- Show default settings
- Show utility titles
- Show reported errors

SHOW CONFIG
1
2
3
4
5
6

CPUA

MDM»

Enabled KA630-AA 1MB, FPU MOO HOO
Enabled 3 megabytes. 6144 Pages.
RQDXA Enabled Revisions =94 and 6
TK50A Enabled
DEQNAA Enabled 08-00-2B-02-08-9D
DHVllA Enabled ROM Rev 11 9
SEL DHV11A

MDM»

ENA DHV11A

MDM»

SHOW DEV UT

MEMA

DHV11A 8 line asynchronous multiplexer
1 - Transmit Pattern Test
2 - Terminal Echo Test
3 - Bulkhead Loopback Test

5-23

MDM»

SHOW DEF

Salected Device:
6
DHVllA Enabled ROM Rev 11 9
Mode is SERVICE
Section is FUNCTIONAL
Number of passes is: 1
No time limi t
Tests to be run:
ALL
Continue on error
Detailed message is Off
Progress message is Off
MOM» START
Please ao the following things:
Open the Backpanel of the MicroVax.
Disconnect the bulkhead from the DHVll flat ribbon cables.
Place the H3277 loopback connector between the
two flat ribbon cables. See DHV11 Technical Manual for
illustration PG. 1-6.
Hit return when finished •..
Thank you for attaching the loopback H3277 connector.
MOM»

SET DET ON

MOM»

SET PROG FULL

MOM» START
DHVllA started by MOM
DHVllA DSL Pass number 1
Test number 1
DHVllA DSL Pass number 1
Test number 2
DHVllA DSL Pass number 1
Test number 3
DHVllA DSL Pass number 1
Test number 4
DHVllA DSL Pass number 1
Test number 5
Cables A and B passed Functional test 5.
DHVllA ended with no errors
MOM»

5-24

When all tests have been completed
On completing the test sequence with zero errors:
•
•

Remove the diagnostic media and store it in a safe place
Restore the system configuration.

5.8 FIELD REPLACEABLE UNITS (FRUs)
The FRUs are:
Reference No.

Item

M3104
BC05L-xx
H3173-A
H3277
H325

Quad-height module
Flat cable, 40 conductor
Distribution panel
Staggered loopback test connector
Line loopback test connector

The last two items do not affect the operation of the system.
Depending on local maintenance strategy, modems and! or external cables may also be FRUs. See Figure
5-1.
5.9 TROUBLESHOOTING FLOWCHART
When troubleshooting is necessary, the flowchart sequence of Figure 5-2 should be used as a guide.
The flowchart is based on the CVDH?? diagnostics. Note that CVDHA? has no loopback mode.
5.10 COMPONENT REPLACEMENT
The M31 04 module is a multilayer fine-line-etch PCB. Only the microcomputers, which are on sockets,
can be replaced in the field. This should only happen if the firmware is updated.

5-25

YES

NOTE:
CVDHA? HAS
NO LOOPBACK
MODE

WORKING CON FIG
RUN TEST
(INTERNAL LOOP)

YES

REPLACE
DHV11

CONFIG A
RUN TEST
(STAGGERED)

YES

CONFIG C
RUN TEST
(STAGGERED)

CONFIG B
RUN LINE LOOPBACK
TEST FOR EACH
LINE

YES

REPLACE

H325

EXTERNAL
LINE CHECKS
USING MODEM
LOOPBACK TEST

WORKING CON FIG.
RUN SYSTEM
EXERCISER

NOTE:
THIS FLOWCHART ASSUMES THAT THE SYSTEM IS INITIALLY
IN THE NORMAL WORKING CONFIGURATION
AD2343

Figure 5-2

Troubleshooting Flowchart
5-26

REPLACE
DHV11

REPLACE
CABLE Y

REPLACE
CABLE X

YES

REPLACE

H3277

LOW
CHANS
0-3

3173-A

0
1
2
3

X
X

H3277
4
HIGH
CHANS
4-7

5
6
7

J2
CONFIGURATION A

CONFIGURATION B

CONFIGURATION C
RD1562

Figure 5-2

Troubleshooting Flowchart (Cont)

5-27

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

APPENDIX A
IC DESCRIPTIONS
Al SCOPE
This appendix contains data on the 8051 microcomputers and other LSI chips used in the DRVII. The
smaller common ICs, which are well described in standard reference books, are not included. For
information not included in this document, read the appropriate manufacturer's data sheets.
A2

8051 MICROPROCESSOR/MICROCOMPUTER

A2.1 8051 Block Description
The 8051 is a microcomputer based on the Intel 8048. Its configuration is programmable. The block
diagram is shown in Figure A-I.
FREQUENCY
REFERENCE

r-=--=-~-

I
I
I

I
I

OSCILLATOR
ATINMDING

--------4096 BYTES

~EO~~~~

6;~:~~~ORY

ROM

RAM

~--L--....L--...,-l

I
I
I

TWO 16-BIT
TIOMERIEVENT
C UNTERS

I
I

8051
CPU

I
I
I
I

COUNTERS

64K-BYTE BUS
EXPANSION
CONTROL

PROGRAMMABLE I/O

INTERRUPTS

L
INTERRUPTS

II
I

PROGRAMMABLE
SERIAL PORT
• FULL DUPLEX
UART
• SYNCHRONOUS
SHIFTER

CONTROL

PARALLEL PORTS,
ADDRESS/DATA BUS,
AND I/O PINS

SERIAL
IN

SERIAL
OUT
R01166

Figure A-I

8051 Block Diagram

A-I

As well as having 128 bytes of RAM for register space, stack, and data memory, the IC contains:
•
•
•
•

4K bytes of program memory ROM
Two 16-bit programmable timer/counters
A full-duplex programmable serial UART capable of data rates up to 1 M bits/s
32 programmable I/O lines arranged as four 8-bit ports.

Other features not indicated in the diagram are:
•

Single +5 V supply

•

64K bytes program memory and 64K bytes data memory addressing capability

•

Up to 128 bytes stack

•

Four 8-byte register banks

•

Two-level interrupt system with programmable priority. Interrupts may also be triggered by the
counter/timers.

•

Byte or bit addressing capability.

A.2.2 Configuration
Figure A-2 provides more information on how the 8051 can be configured. It also gives pinout details.
RSTIVPD

0
f--

cr:

XTAL2

£l.

EAlVDD

........
....
....
....
............

P1.0

8051

i=
u

::J

f--

)0-

cr:

«0
z

ifJ

TO---'"
T1---"
WR.RD'-

£l.

--.
--.

--.

ADO
AD1

PO.2

AD2

P1.4

PO.3

AD3

ifJ
ifJ

P1.5

PO.4

AD4

cr:

P1.6

PO.5

AD5

P1.7

PO.6

AD6

RSTIVPD

PO.7

AD7

w
0
0

cr:

--.
--.
cr:

PO.O

P1.3

vee

P1.2

f--

--.
--.

RXD---..
TXD.INTO---..
INT1 ---...

PO.1

£l.

ifJ

P1.1

«f-«0

PSEN
ALE/PROG

ifJ

::J

ifJ

::J
CD
ifJ
ifJ

10 8051 31

EAlVDD

RXD

P3.0

TXD

P3.1

ALE/PROG

INTO

P3.2

PSEN

INT1

P3.3

P2.7

A15

P3.4

P2.6

A14

P3.5

P2.5

A13

P3.6

P2.4

A12

P3.7

P2.3

A11

P2.2

A10

XTAL2

0
0

XTAL1

P2.1

VSS

P2.0

cr:

--.

R[}1169

ROl167

Figure A-2

8051 Symbol and Pinout Diagrams
A-2

When external memory is addressed, port 0 becomes a multiplexed 8-bit data bus / low-order (~7 to A?)
address bus. If the external address is higher than 255, port 2 provides A15 to A8. When not bemg used m
combination with port 0, port 2 returns to its programmed condition.
The 8051 signals are briefly described in Table A-I.
Table A-I

8051 Pin Description

Vss
Circuit ground potential.
Vcc
+5 V power supply during operation, programming, and verification.
PORTO
Port 0 is an 8-bit open-drain bidirectional II 0 port. It is also the mUltiplexed low-order address and data
bus when using external memory. It is used for data input and output during programming and verification.
Port 0 can sink/source LSTTL loads.
PORT 1
Port 1 is an 8-bit quasi-bidirectional I/O port. It is used for the low-order address byte during
programming and verification. Port 1 can sink/source four LSTTL loads.
PORT 2
Port 2 is an 8-bit quasi-bidirectional I/O port. It also issues the high-order address byte when accessing
external memory. It is used for the high-order address and the control signals during programming and
verification. Port 2 can sink/source four LSTTL loads.
PORT 3
Port 3 is an 8-bit quasi-bidirectional I/O port. It also contains the interrupt, timer, serial port, and RD and
WR pins that are used by a number of options. The output latch corresponding to a secondary function
must be programmed to a 1 for that function to operate. Port 3 can sink/source four LSTTL loads. The
secondary functions are assigned to the pins of port 3, as follows:
•

RXD/data (P3.0). Serial port receiver data input (asynchronous) or data input/output
(synchronous)

•

TXD/clock (P3.l). Serial port transmitter data output (asynchronous) or clock output
(synchronous)

•

INTO (P3.2). Interrupt 0 input or gate control input for counter 0

•

INTl (P3.3). Interrupt 1 input or gate control input for counter 1

•

TO (P3.4). Input to counter 0

•

Tl (P3.5). Input to counter 1

•

WR (P3.6). The write control signal latches the data byte from port 0 into the external data
memory

•

RD (P3.7). The read control signal enables external data memory to port O.

A-3

Table A-I

8051 Pin Description (Cont)

RST/VPD
A change oflevel from low to high on this pin (at approximately 3 V) resets the 8051. IfVPD is held within
its specification (approximately +5 V) while Vcc drops below specification, VPD will provide standby
power to the RAM. When VPD is low, the RAM's current flows from Vcc. A small internal resistor
permits power-on reset using only a capacitor connected to Vcc.
PSEN L
The Program Store Enable output is a control signal that enables the external program memory to the bus
during normal fetch operations. Not connected on DRVIl.
ENL/VDD
When held at a TTL high level, the 8051 executes instructions from the internal ROM/EPROM when the
PC is less than 4096. When held at a TTL low level, the 8051 fetches all instructions from external
program memory.
XTALI
Input to the oscillator's high-gain amplifier. Grounded on the DRVIl.
XTAL2
Output from the oscillator's amplifier. Driven by a 12 MRz clock on the DRV11.
A.2.3 Read/Write Timing
Read/write timing cycles are shown in Figures A-3, A-4, and A-5.

T12

Tl0

T11

OSC

ALE

PSEN

RD, WR

PORT 2

FLOAT

PORTO

Figure A-3

Program Memory Read Cycle

A-4

ALE

PSEN

ADDRESS A1S-AS

PORT 2

PORT a

DATA IN

FLOAT

Figure A-4

Data Memory Read Cycle

ALE

PSEN

ADDRESS A1S-AS

PORT 2

PORT a

INSTR

iFLOAT

DATA OUT

A7- A O

Figure A-5

ADD RESS OR
SFR P2

ADDR ESS
OR F LOAT

Data Memory Write Cycle

In each cycle, ALE (Address Latch Enable) is issued as a latching signal for A 7 to AO. Latching occurs on
the negative-going edge of ALE. Once the low address bits are latched, port 0 can be used to transfer data.
Ifprogram memory is being read, Program Store Enable (PSEN L) must be asserted before the instruction
is read in. RD Land WR L will both be invalid.
When data memory is being accessed PSEN L is false and RD L or WR L are asserted.
Note that with a 12 MHz clock (OSC), a program memory cycle takes 500 nanoseconds. A data memory
cycle takes one microsecond.
A.3

SC2681 DUAL UART (DUART)

A.3.1 Block Description
Block diagram Figure A-6 shows the functional blocks of the D U ART. Except for the bus buffer, which is
a parallel holding register, there are control registers in every block. It is via these registers that the
DUART is programmed and monitored.

A-5

When the chip enable line (CEN) is low, the registers can be accessed by read or write actions of the host.
Address lines A3 to AO provide the address. RDN or WRN provides the timing and control. Commands,
status, or data are transferred on the data lines D7 to DO. The operational control block manages these
parallel operations.
r--..
8/

00-0 7<
/

CHANNEL A

BUS BUFFER

TRANSMIT
HOLDING REG

TxDA

TRANSMIT
SHIFT REGISTER
w

RON

WRN

<J)

a::
w

•

CEN
4,::

AO-A 3

RESET

•
•

OPERATION
CONTROL

ADDRESS
DECODE

R/W CONTROL

I -'

RECEIVE
HOLDING REG

(3)

RECEIVE
SHIFT REG

RxDA

MRA1,2
CRA
SRA

BE]
INTERRUPT
CONTROL

INTRN

(fJ

CHANNELS
(AS ABOVE)

ISR

hOB

a::

RxDB

...J

'"
w

(fJ

C/)
::;)

INPUT PORT

III

TIMING

I
I

BAUD RATE
GENERATOR

CLOCK
SELfCTORS

a:
....
z

1- «....

«
c
~

«
z

w
....

CHANGE OF
STATE
DETECTORS (4)

I PO-IP6

~
ACR

OUTPUT PORT
'---

I
X1/CLK

•

COUNTERI
TIMER

XTAL OSC

FUNCTION
SELECT
LOGIC

v--

OPO-OP7

~
OPR

CSRA
CSRB
ACR
CTUR
CTLR

VCC

GND
R01170

Figure A-6

SC2681 Dual Universal Asynchronous Receiver Transmitter (DUART)

A-6

Two serial data channels (A and B) perform the parallel/serial and serial/parallel conversion. Each
TRANSMIT channel has a 2-byte buffer. This allows the next character to be loaded while the previous
one is being transmitted. Each RECEIVE channel has a 4-byte buffer to allow for delays in interrupt
response.
Also related to the serial interface are a 7-bit input port and an 8-bit output port. These lines can be used as
individual, sense, and flag lines. Each line has a secondary function which may be used to provide modem
control for the serial data lines.
A 3.6864 MHz crystal provides the basic timing for the timing block. This section contains a
programmable counter/timer which can be programmed for many RECEIVE and TRANSMIT baud
rates. The counter/timer can also be clocked by input port 2.
Interrupts are generated when at least one of eight maskable interrupt conditions occurs. INTRN will
inform the controlling processor of changes in the DUART status. The interrupt routine should read status
and then take the appropriate action. INTRN is commonly used to indicate that a received character has
been assembled or that the DUART can accept a new character for transmission.
The DUART can also be operated in the polled mode.
Characters to be transmitted must be written to the appropriate transmit holding register.
Received characters must be read from the appropriate receive holding register.
A.3.2

Pin-Out Information

RD1171

Figure A-7

SC2681 Pin-Out Diagram

A pin-out diagram is provided in Figure A-7. The related pin functions are listed in Table A-2. This
information applies to the 40-pin DIL version of SC2681 only.

A-7

Table A-2

SC2681 Pin Designation

Mnemonic

Direction

Pin Name and Function

DO to D7

I/O

Data Bus - Bidirectional 3-state data bus used to transfer
commands, data, and status between the DUART and the CPU.
DO is the least significant bit.

CEN

Chip Enable - Active-low input signal. When low, data transfers
between the CPU and the DUART are enabled on DO to D7 as
controlled by the WRN, RDN, and AO to A3 inputs. When high,
places the DO to D7 lines in the 3-state condition.

WRN

Write Strobe - When low, and CEN is also low, the contents of
the data bus are loaded into the addressed register. The transfer
occurs on the positive-going edge of the signal.

RDN

Read Strobe - When low and CEN is also low, causes the
contents of the addressed register to be placed on the data bus. The
read cycle starts on the negative-going edge of RN.

AO to A3

Address Inputs - Select the DUART internal registers and ports
for read/write operations.

RESET

Reset - A high level clears the internal registers (SRA, SRB,
IMR, ISR, OPR, OPCR), puts OPO to OP7 in the high state, stops
the counter/timer, and puts channels A and B in the inactive state
with the TxDA and TxDB outputs in the mark (high) state.

INTRN

Interrupt Request - Active-low open-drain output which signals
to the CPU that one or more of the eight mask able interrupting
conditions are true.

Xl/CLK

Crystal 1 - Crystal or external clock input. Grounded on the
DHVII.

Crystal 2 - Connection for the other side ofthe crystal. Connected
to a 3.6864 MHz crystal on the DHVII.

RxDA

Channel A Receiver Serial Data Input - The least significant bit
is received first. Mark is high, space is low.

RxDB

Channel B Receiver Serial Data Input- The least significant bit
is received first. Mark is high, space is low.

TxDA

Channel A Transmitter Serial Data Output - The least
significant bit is transmitted first. This output is held in the mark
condition when the transmitter is disabled, idle, or when operating
in localloopback mode. Mark is high, space is low.

OPO to OP7

General Purpose Outputs - Used by the DHVll for modem
control.

A-8

Table A-2

SC2681 Pin Designation (Cont)

Mnemonic

Direction

IPO to IP6

General Purpose Inputs - Used by the DHVll to monitor
modem status.

Vcc

Power Supply

GND

Ground

Pin Name and Function

+5 V supply input

A.4 DC003 INTERRUPT IC
The interrupt controller is an 18-pin DIL device that provides the circuits to perform an interrupt
transaction in a computer system that uses a 'pass-the-pulse' type arbitration. The device provides two
interrupt channels, A and B, with the A section at a higher priority than the B section. Bus signals use highimpedance input circuits or open-collector outputs, which allow the device to be attached directly to the
computer system bus. Maximum current taken from the Vcc supply is 140 rnA.

Figure A-8 is a simplified logic diagram of the DC003 IC. Timing for the interrupt section is shown in
Figure A-9, while Figure A-I 0 shows the timing for both A and B interrupt sections. Table A-3 describes
the signals and pins of the DC003 by pin and signal name.

DC003
17
ROSTA H
15

16
ENA DATA H

ENA ST H

ENA ClK H

BIRO l

07
05
03

... BIAKI l

BIAKO l

....

BINIT l

INITO l

BDIN l

VECTOR H

Ifo..

~ 06
~ 04

02
ENB ClK H

VEC ROSTB H

12
ENB DATA H
10

11
ROSTB H

ENB ST H

MK 0164

Figure A-8

DC003 Logic Symbol

A-9

300

MIN\

(MIN

BINITL ~

7-35:
lri:------------------------------------~--------------

INITO L ~
~

c..J

1
1

ENA DATA H

~------

ENA CLK H

30 MI.\I--i

______

_ __ L_ _ _ _ _ _ _ _ _ _ _ _

Fl~--------------------~n ~--------------------I
I

ENA ST H

ROSTA H

7-30

--l F
I
I
1

BIRO L

15--65 --:

r--

.....JF 20-90

L...___
--,;.:

BDIN L
I

BIAKI L

35 MIN

--l I:::..J
I

I
I

35 MIN-:

l:=J

I
I

I
1

c--T-L_

V ECTO R H ______________'_0_-_4_5_--'--:..1...J1 -:

-i:r-_____________

1L.
__'_0_-_4_5________;..-__

I
I

'2--55-:I W='2-55

BIAKO L
NOTE:
TIMES ARE IN NANOSECONDS.

Figure A-9

De003 A Section Timing

A-IO

MK 0173

300==~____________________- - - - - - - - - - - - - - - - - - - BINIT l IM-'NI300:
PMIN:
1
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _
_~'

--rR.J:I'~-50

INITO l

7--35
ENB DATA H

~'--~--------------------------I

ENB ClK H

30 MIN-i

FlL_______________________
I

I
I

ENB ST H

BIRO l

7---30-1

'5-65-:I L-___________________________________________
I

ROSTB H

ENA DATA H

--------~l
I

-i FlL_____________________________
I

ENA ClK H

30 MIN

ENA ST H

ROSTA H

------------------~

B DIN l

I
I

BIAKI l

35 MIN-i

I:J
I
I
I

LJ
U

35 MIN-i

I
I
I

V ECTO R H _______________________'_0_-_4_5..:..rfR....I
: .....~_0_-_4_5____'_0_-_4_5;-rrH-'
: ' 0-45

;r+--,
VECROSTB H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _'_5_-_6_5!...;---j---.J :---, '5-65
NOTE:
TIMES ARE IN NANOSECONDS.

Figure A-lO

MI< 0175

DC003 A and B Section Timing

A-11

Table A-3

DC003 Signals

Pin
No.

I/O Name

Symbol

Function

Interrupt
Vector Gating
Signal

VECTORH

This signal gates the appropriate vector address to
the bus and forms the bus signal BRPLY L.

Vector
Request B
Signal

VEC RQSTB H

When asserted, this signal indicates RQ ST B service
vector address is wanted. When not asserted it
indicates RQST A service vector address is wanted.
VECTOR H is the gating signal for the complete
vector address; VEC RQSTB H is normally bit 2 of
the address.

Bus Data In

BDINL

The BDIN signal always precedes a BIAK signal.

Initialize Out

INITO L

This is the buffered BINIT L signal used in the
device interface for general initialization.

Bus Initialize

BINIT L

When asserted, this signal brings all drive lines to
their non-asserted state (except INITO L).

Bus Interrupt
Acknowledge
(Out)

BIAKO L

This signal is the daisy-chained signal that is passed
by all devices not requesting interrupt service (see
BIAKI L). Once passed by a device, it must continue
to be passed until a new BIAKI L is generated.

Bus Interrupt
Acknowledge
(In)

BIAKI L

This signal is the processor's response to BIRQ L
true. This signal is daisy-chained so that the first
requesting device blocks the signal, while nonrequesting devices pass the signal on as BIAKO L to
the next device in the chain. The leading edge of
BIAKI L causes BIRQ L to be deasserted by the
requesting device.

Asynchronous
Bus Interrupt
Request

BIRQL

This request is generated when a RQST signal and
the appropriate Interrupt Enable signal become
valid. The request is removed after the acceptance of
the BDIN L signal and on the leading edge of the
BIAKI L signal, or the removal of the appropriate
interrupt enable, or by the removal of the appropriate
request signal.

17
10

Device
Interrupt
Request
Signal

RQSTAH
RQSTB H

When asserted with the enable NB flip-flop asserted,
this signal causes BIRQ L to be asserted on the bus.
This signal line normally stays asserted until the
request is serviced.

16
11

Interrupt
Enable Status

ENA STH
ENB ST H

This signal indicates the state ofthe interrupt enable

NB internal flip-flop which is controlled by the
signal line ENA/B DATA H and the ENA/B CLK
H clock line.

A-12

Table A-3

DC003 Signals (Cont)

Pin
No.

I/O Name

Symbol

Function

15
12

Interrupt
Enable Data

ENA DATA H
ENB DATA H

The level on this line, in conjunction with the
ENA/B CLK H signal, determines the state of the
internal interrupt enable A flip-flop. The output of
this flip-flop is monitored by the ENA/B ST H
signal.

14
13

Interrupt
Enable clock

ENACLKH
ENB CLKH

When asserted (on the positive edge), interrupt
enable AlB flip-flop assumes the state ofthe ENNB
DATA H signal line.

A.S

DC004 PROTOCOL IC
The protocol chip is a 20-pin OIL device that functions as a register selector, providing the signals
necessary to control data flow to and from up to four word registers (8 bytes). Bus signals can be directly
attached to the device because receivers and drivers are provided on the chip. An RC delay circuit is
provided to slow the response of the peripheral interface to data transfer requests. The circuit is designed
so that if close tolerance is not wanted, only an external 1 kilohm ( + or - 20%) resistor is needed. External
RCs can be added to change the delay. Maximum current taken from the Vcc supply is 120 rnA.
Figure A-II is a simplified logic diagram of the DC004 IC. Signal timing in relation to different loads is
shown in Figure A-12. Signal and pin definitions for the DC004 are shown in Table A-4.

A-13

VECTOR H

BDAL 2
BDAL1
BDAL 0

VCC
ENB H

DC004

RXCX H
SEL6 L

BWTBT L

BSYNC L

SEL2 L

BDIN L

SELO L

BRPL Y L

OUTHB L

BDOUT L

OUTLB L

GND

INWD L

SEL4 L

- +VCC
D
ENB
LATCH
G

ENB

§}--VCC

SYNC
BDAL2 L 02

BDALl L 03

~GND

D
02
LATCH
0

DAL2

DECODER

17 SEL 6 L

D
01
LATCH
G

DAL1

14 SEL 0 L

13 OUTHB L
BDALO L 04

D
00
LATCH

12 OUTLB L

18 RXCX H

L-________________________________

BDOUT L

BDIN L

~01

VECTOR H

~--------------------------------~11 INWDL
MK 0171

Figure A-II

DC004 Simplified Logic Diagram

A-I4

BSYNC L

SE L (0, 2, 4, 6) L

-.,i

t:=
~___

15__tO__
4_0___________~~:~f=5t030

BWBTL~

~~??0

BDOUT L

15MIN.~b:
~___1_5_M_I_N_·_:1~~~14=~~====~--=~_\_\----.IL----__________________

OUTHB L
OUTLB L
BDIN L

~'~

5 to 30-':

I--

--: I- 5 to 30

'_
- _ _ _ _---'-'......J

5t030=1L-+~
______~~I.--------~\ f~i--~.I,,
,

____

-i F5 to 30

IWD L

'--------'---',

BRPL Y L

20 to 430 ----.:

\::

: - -{ - 2.4 V

~------+,---J 1

;-.-------i

:--10 to 45

VECTOR H

RX Cx H

--------------------~~

*TIME REQUIRED TO DISCHARGE RX Cx FROM ANY CONDITION ASSERTED =

150ns

NOTE:
TIMES ARE IN NANOSECONDS.
RD1346

Figure A-I2

DC004 Timing Diagram

A-I5

Table A-4

DC004 Pin/Signal Descriptions

Signal

Description

VECTORH

Vector - This input causes BRPLY L to be generated through the delay
circuit. It is independent of BSYNC Land ENB H.

2
3
4

BDAL2 L
BDALIL
BDALO L

Bus Data Address Lines - These signals are latched at the assert edge of
BSYNC L. Lines 2 and 1 are decoded for the select outputs; line 0 is used
for byte selection.

BWTBTL

Bus Write Byte - While the BDOUT L input is asserted, this signal
indicates a byte or word operation: asserted = byte, not asserted = word.
Decoded with BDOUT L and latched BDALO L to form OUTLB Land
OUTHB L.

BSYNC L

Bus Synchronize - At the assert edge of this signal address information is
trapped in four latches. When not asserted, disables all outputs except the
vector term of BRPLY L.

BDINL

Bus Data In - This is a strobe signal to effect a data input transaction.
Generates BRPLY L through the delay circuit and INWD L.

BRPLY L

Bus Reply - This signal is generated through an RC delay by VECTOR
H, and strobed by BDIN L or BDOUT L, and BSYNC L and latched
ENBH.

BDOUTL

Bus Data Out - This is a strobe signal to effect a data output transaction.
Decoded with BWTBT Land BDALO to form OUTLB Land OUTHB
L. Generates BRPLY L through the delay circuit.

INWDL

In Word - Used to gate (read) data from a selected register onto the data.
bus. Enabled by BSYNC L and strobed by BDIN L.

12
13

OUTLB L
OUTHB L

Out Low Byte, Out High Byte- Used to load (write) data into the lower,
higher, or both bytes of a selected register. Enabled by BSYNC Land
decode ofBWTBT L and latched BDALO L, and strobed by BDOUT L.

14
15
16
17

SELO L
SEL2 L
SEL4 L
SEL6 L

Select Lines - One ofthese four signals is true as a function ofBDAL2 L
ifENB H is asserted at the assert edge ofBSYNC L. They indicate that a
word register has been selected for a data transaction. These signals never
become asserted except at the assertion of B SYN C L (then only if ENB H
is asserted at that time) and, once asserted, are not deasserted until
BSYNC L is deasserted.

RXCX

External Resistor Capacitor Node - This node is provided to vary the
delay between the BDIN L, BDOUT L, and VECTOR H inputs and
BRPLY L output. The external resistor should be tied to Vcc and the
capacitor to ground. As an output, it is the logical inversion of BRPLY L.

ENBH

Enable - This signal is latched at the asserted edge of BSYNC L and is
used to enable the select outputs and the address term of BRPLY L.

A-16

A6 DC005 BUS TRANSCEIVER IC
!he 4-bit transceiver is a 20-pin DIL low-power Schottky device for primary use in peripheral device
Interfaces. It functions as a bidirectional buffer between a data bus and peripheral device logic. In addition
to the isolation function, the device also provides a comparison circuit for address selection, and a
?onstant generator, useful for interrupt vector addresses. The bus I/O port provides high-impedance
Inputs and open-collector outputs to allow direct connection to a computer's data bus. On the peripheral
device side, a bidirectional port is also provided, with standard TTL inputs and 20 rnA tri-state drivers.
Data on this port has the opposite polarity to the data on the bus side.
Three address jumper inputs are used to compare against three bus inputs and to generate the signal
MATCH. The MATCH output is open-collector, which allows the output of more than one transceiver to
be wire-ANDed to form a combined address match signal. The address jumpers can also be put into a third
logical state that disconnects that jumper from the address match, allowing for' don't care' address bits. In
addition to the three address jumper inputs, a fourth high-impedance input line is used to enable/disable
the MATCH output.
Three vector jumper inputs are used to generate a constant, that can be passed to the computer bus. The
three inputs directly drive three of the bus lines, overriding the action of the control lines.
Two control signals are decoded to give three operation states: receive data, transmit data, and disable.
Figure A-13 is a simplified logic diagram of the DCOO5 IC. Timing for the functions is shown in Figure A-14.
Signal and pin definitions for the DC005 are given in Table A-S.
Table A-5

DC005 Pin/Signal Descriptions

Name

Function

12
11
9
8

BUSOL
BUSI L
BUS2L
BUS3 L

Bus Data - This set of four lines constitutes the bus side of the transceiver.
Open-collector outputs; high-impedance inputs. Low = 1.

18
17
7
6

DATOH
DATIH
DAT2H
DAT3H

Peripheral Device Data - These four tri-state lines carry the inverted
received data from BUS (3:0) when the transceiver is in the receive mode.
When in transmit data mode, the data carried on these lines is passed
inverted to BUS (3:0). When in the disabled mode, these lines go open (high
impedance). High = 1.

14
15
16

JVl H
JV2 H
JV3 H

Vector Jumpers - These inputs, with internal pull-down resistors, directly
drive BUS (3: 1). A low or open on the jumper pin causes an open condition
on the corresponding BUS pin ifXMIT H is low. A high causes a 1 (low) to
be transmitted on the BUS pin. Note that BUSO L is not controlled by any
jumper input.

MENBL

Match Enable - A low on this line enables the MATCH output. A high
forces MATCH low, overriding the match circuit.

MATCHH

Address Match - When BUS (3:1) matches the state of JA (3:1) and
MENB L is low, this output is open; otherwise, it is low.

A-17

Table A-5

DC005 Pin/Signal Descriptions (Cont)

Name'

Function

1
2
19

JAI L
JA2L
JA3 L

Address Jumpers - A connection to ground on these inputs allows a match
to occur with a 1 (low) on the corresponding BUS line. An open allows a
match with a 0 (high). A connection to Vee disconnects the corresponding
address bit from the comparison.

XMITH
RECH

Control Inputs - These lines control the operation of the transceiver as
follows.

REC XMIT

o
1
1

0
1

DISABLE: BUS and OAT open
XMIT DATA: OAT to BUS
RECEIVE: BUS to OAT
RECEIVE: BUS to OAT

To avoid tri-state overlap conditions an internal circuit delays the change of
modes between XMIT OATA and RECEIVE mode, and delays the
enabling oftri-state drivers on the OAT lines. This action is independent of
the DISABLE mode.

A-18

DC005 TRANSCEIVER
JA1 L
JA2 L 2
MATCH H 3
REC H 4
XMIT H 5
DAT3 H 6
DAT2 H 7
BUS3 L B
BUS2 L 9
GND
10

20VCC
19 JA3 L
1BDATOH
17 DAn H
16 JV3 H
15 JV2 H
14 JV1 H
13 MENB L
12BUSOL
11 BUS1 L

DATO

JA1
H

BUS2

JA2

JA3

MENB

XMIT

JV3

DAT3

>-______-===::j.....Jr-+-------+--{~03 MATCH H

REC

[2Q}- Vce

Figure A-13

ITID- GND
DeDD5 Simplified Logic Diagram

A-19

TRANSMIT DATA TO BUS
XMIT H -

-JI

___

-I

REC H (GROUND)
BUS L - OUTPUT

I- 5 TO 30 ns
1

I
I-

5 TO 25 ns -J

OAT H - INPUT -

_ _- - - . J I IL.._ _

I- 5 TO 30 ns

-I

-I
I- 5 TO 25 ns
----'1-1-!........::-':""=--=":' ' :' ::' ' T'""I- -

RECEIVEDATA FROM BUS (BUS INITIALLY HIGH)
XMITH(GROUNO) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

-II

""""""'=--=-"_

REC H _ _ _ _
OAT H - OUTPUT
BUS L - INPUT

1 - 1_ _

~
I- 0 TO 30 ns
--,
1

-----.-------1....,

-I

I- 0 TO 30 ns

I- 8 TO 30 ns

IL..._ _ _ _ _ _ _ _..1....-_ _

RECEIVE DATA FROM BUS (BUS INITIALLY LOW)
XMIT H (GROUND)
REC H
OAT H - OUTPUT

------------------------------I

-----I""'"

1
I- 0 TO 30 ns

-IL-""""""1--0-T-O-3-0 ns

-I

I- 8 TO 30 ns

--I!

BUS L -INPUT _ _ _ _ _L -_ _

VECTOR TRANSFER TO BUS

JV H _ _ _ _ _~I
______
-I.L...-....,I- 20 ns MAX
-I
I- 20 ns MAX
BUSL-OUTPUT
L...I_ _ _ _ _ _ _ _ _~I

ADDRESS DECODING
BUS L - INPUT ____________~X\....._~--------10 TO 40 ns
MATCH H _______---;_-+I--=-=-:-:-_~X'_
-!
1-5T040ns
-.j
I-l0T040ns
MENB L
1
1

,. . ----__-1--'---____,1-

___.,___+I___

RECEIVE MODE LOGIC DELAY
XMIT H
RECH _ _ _ _~I

-J

I- 40 TO 90 ns

-LI______________

OAT (3:0) H (OUTPUT) ___________

MK 0174

Figure A-14

DeOOS Timing Diagram

A-20

A.7 DCOIO DIRECT MEMORY ACCESS LOGIC
.
This DMA controller provides the logic to perform the handshaking operations needed to request land to
gain control of the system bus. Once the DCO 10 becomes bus master it generates the signals needed to
perform aD IN, DO UT, or DATIO transfer as specified by control lines to the chip. The DCO 10 I <r has a
control line that will allow multiple transfers or only four transfers to take place before giving up the bus.
Figure A-IS is a simplified logic diagram of the DCO 10 IC. The logic symbols and truth table are shown in
Figure A-16, and the DCOIO voltage waveforms are shown in Figure A-17. Table A-6 describ~s the
signals and pins of the DCOIO by pin and signal name. Figures A-18 and A-19 show the timing.
MA~HA S 0

(MASTER

====D--SDMR L

r-----~IMA"'STEERRLl=LI

H.-----<:r---'\

ENAJ=1~h--~~~~i=D~==~

ENA1'-=f:~~====!:~D

{MASTER
RSYNCH~

Figure A-IS

DCO 10 Simplified Logic Diagram

Table A-6

DCOI0 Pin/Signal Descriptions

Signal

Description

REQH

Request (TTL Inputs) - A high on this signal initiates the bus request
transaction. A low allows the termination of bus mastership to take
place.

BDMGI L

DMA Grant Input (High Impedance) - A low on this signal allows
bus mastership to be established if a bus request was pending (REQ =
high); otherwise this signal is delayed and output as BDMGO.

CNT 4 H

Count Four (TTL Output) - A high on this signal allows a maximum
of four transfers to take place before giving up bus mastership. A low
disables this feature and an unlimited transfer will take place as long as
REQ is high. If left open this pin will assume a high state.

A-21

Table A-6

DCOI0 Pin/Signal Descriptions (Cont)

Signal

Description

TMOUTH

Time-Out (TIL Input/Open Collector Output) - This I/O pin is low
while SACK H is high. It goes into high impedance when SACK H is
low. When driven low it prevents the assertion ofBDMR; when driven
high it allows the assertion ofBDMR to take place ifBDMR has been
deasserted because of the 4-maximum transfer condition. An RC
network may be used on this pin to delay the assertion of BDMR.

DATIN L

Data In (TIL Input) - This signal allows the selection of the type of
transfers to take place according to the truth table (Figure A-16).

DATIO L

Data In/Out (TIL Input) - This signal allows the selection ofthe type
of transfer to take place according to the truth table (Figure A-16).
During a DATIO transfer, this signal must be toggled in order to allow
the completion of the output cycle of the I/O transfer.

RSYNC L

Receive Synchronize (TIL Input) - This signal allows the device to
become master according to the following relationship:
RSYNC L . RPLY L . SACK H = MASTER

CLKL

Clock (TTL Input) - This clock signal is used to generate all transfer
timing sequences.

REPLY L

Reply (TTL Input) - This signal is used to enable or disable the free
clock signal.
This signal also allows the device to become master according to the
following relationship:
RSYNC L' RPLY L . SACK H = MASTER

INIT L

Initialize (TTL Input) - This signal is used to initialize the chip to the
state where REQ is needed to start a bus request transaction. When
INIT is low, the following signals are deasserted: BDMRL, MASTER
H, DATEN L, ADREN L, SYNC H, DIN H, DOUT H.

BDMRL

DMA Request (Open Collector Output) - A low on this signal
indicates that the device is requesting bus mastership. This output may
be tied directly to the bus.

MASTERH

Master (TTL Output) - A high on this signal indicates that the device
has bus mastership and a transfer sequence is in progress.

BDMGO L

DMA Grant Output (Open Collector Output) - This signal is the
delayed version ofBDMGI ifno request is pending; otherwise it is not
asserted. This output may be tied directly to the bus.

A-22

Table A-6

DCOI0 Pin/Signal Descriptions (Cont)

Signal

Description

TSYNC H

Transmit Synchronize (TTL Output) - This signal is asserted by the
device to indicate that a transfer is in progress.

DATENL

Data Enable (TTL Output) - This signal is asserted to indicate that
data may be placed on the bus.

ADRENH

Address Enable (TTL Output) - This signal is asserted to indicate
that an address may be placed on the bus.

DINH

Data In (TTL Output) - This signal is asserted to indicate that the bus
master device is ready to accept data.

DOUTH

Data Out (TTL Output) - This signal is asserted to indicate that the
bus master device has output valid data.

TRUTH TABLE
WHERE

L '" TTL LOW
H
TTL HIGH

X = DON T CARE

INPUTS
DAllN

Figure A-16

DAllO

TRANSFER
TYPE

DAIIO
DIN
DOUT

DCOIO Logic Symbol/Truth Table.

INPUT

OUTPUT IN
1 5V

PHASE

I l·H

OUTPUT OUT
OF PHASE

15V

PULSE CONDITIONS FOR DELAY MEASUREMENTS

Figure A-1?

DeOIO Voltage Waveforms

A-23

I~III
I
I~
I

ClK

~rs--~----.:.-------~-3-5-.:1~51
REO H
TMOUT H

~_-t---+----+--.....JIL...fl
I
_Ii-- 20'-65

ADREN H
DATEN l

I
I~---~--~.
_ _ _-t--...!......._----I..I!--15-60
1
I
I

TSYNC H

RPlY H

I I

13~J I.- __I

30
90_ __
;.-1.1_
_-_

I J ~f--,If-----...-I---J

I S~;-+----+-I- - - - - -

I fl
18-~1_ I I

I II
I

'--

I
I

1"-,I 130
r-

Il~I

-:Or

18-60 II

-Jr-IL_ _ _ __

18-60 I

---11j+-

: rl~1- - - - i

I I!~-;-I----l~5rJ____:---_+lI'

d18=60 I

I
DIN H

-: I

I YI
I

I
1

~~f~------~-----------

51 I

-:301-

ENDCYClE----~I------~----------~I~I--------~f~I--I--------~Ir--l~---DATI N l

--l 60
----+-t---.
I
I
I I~~I------------~S~I--------~H~--------~I------------I

DATIO l

MASTER H

- I

I~~I--------~Srl----~5ir-------71----------

I
I
-I
I

I
I

-l

FlO-58

TIMES IN
NANOSECONDS

j:!§-66

SINGLE NUMBERS
ARE MINIMUM
TIMES
RD1345

Figure A-19

DCO 10 Timing Diagram

A-25

APPENDIX B
MODEM CONTROL
B.1 SCOPE
This appendix contains information useful to both the programmer and the engineer. It defines control
signals, describes typical modem control methods, and warns against likely network faults. A detailed
example of auto-answer operation is included.
B.2 MODEM CONTROL
The DRV11 supports sufficient modem control to permit full-duplex operation over the public switched
telephone network (PSTN) and over private telephone lines. Table B-1 lists the control leads supported by
the DRV11 together with an explanation of their use and purpose. In this appendix, the terms MODEM
and DATASET have the same meaning. They refer to the device which is used to modulate and
demodulate the signals transmitted over the communications circuits.
The DRV11 modem control interface can be used in many applications. These include control of serial
line printers, terminal cluster controllers, and industrial 110 equipment, in addition to the more usual
applications in telephone networks. Use of the control leads described in Table B-1 is therefore
completely application dependent, although there are international standards which telephone network
applications should obey. There are no hardware interlocks between the modem control logic and the
transmitter and receiver logic. Program control manages these actions as necessary.
A subset of the leads listed in Table B-1 could be used to establish a communications link using modems
connected to the switched telephone network. Ring Indicator (RI), Data Terminal Ready (DTR), and
Data Carrier Detected (DCD) are the absolute minimum requirements. In some countries Dataset Ready
(DSR) is also needed. It is usually desirable, however, to implement modem control protocols which will
operate over most telephone systems in the world. Also, some protection should be included to guard
against network faults, particularly in applications such as dial-up time-sharing systems. Such faults
include:
•

Making a channel permanently busy (hung) because of a misdialed connection from a non-data
station

•

Connecting a new incoming call on an in-use channel. This fault might occur, for example, after
a temporary carrier loss, if the host system assumed that the carrier was reasserted by the
original caller.

Modem control with some protection against common faults, and which is compatible with the telephone
networks in most geographic areas, can be implemented by using all the signals listed in Table B-1, in the
way described by the CCITT V.24 recommendations. Section B.2.1 describes a method of implementing
a full-duplex auto-answer communications link via modems over the PSTN. It is provided here only to
show the operation and interaction of DHV11 modem control leads in a typical application.

B-1

Table B-1
Name

RS-232-C

GND

TXD

V.24

25-Pin

Modem Control Leads
Definition

Protective ground. This provides a path between the
modem and D HV 11 for discharge of potentials such as
static electricity.

102

Signal Ground. This is a reference level for the data and
control signals used at the EIA interface.

103

From DHV11 to modem. This signal contains the
serial bit stream to be transmitted to the remote station.

RXD

104

From modem to DHVII. This signal is the serial bit
stream received by the modem from the remote station.

RTS

105

From DHV11 to modem. Causes the modem's carrier
to be placed on the line.

CTS

106

From modem to DHVII. Indicates that the modem has
successfully placed its carrier on the line and that data
presented on circuit BA will be transmitted to the
communication channel.

DSR

107

From modem to DHV11. Indicates that the modem has
completed all call establishment functions and is
successfully connected to a communications channel.

DTR

108/2

From DHVII to modem. Indicates to the modem that
the DHVll is powered up and ready to answer an
incoming call.

DCD

109

From modem to DHVII. Indicates to the DHV11 that
the remote station's carrier signal has been detected and
is within appropriate limits.

125

From modem to DHVl1. Indicates that a new incoming
call is being received by the modem.

B.2.1 Example of Auto-Answer Modem Control for the PSTN
The system operator determines which DHVl1 channels should be configured for either local or remote
operation. Local operation implies control of data-leads only, while remote operation implies that modem
control will be supported. The host software will assert DTR and RTS together with the Link Type bit in
the LNCTRL register for all DHVII channels configured for remote operation. DTR informs the modem
that the D HV 11 is powered up and ready to acknowledge control signals from the modem. RTS is asserted
for the full-duplex mode of operation and causes the modem to place its carrier on the telephone line when
the modem answers a call. Link Type (LNCTRL<8» enables modem status information to be placed in
the receive character FIFO where it will be handled by an interrupt service routine. Modem status
changes are always reported in the STAT register regardless of the state ofLNCTRL< 8> . The modem is
now prepared to auto-answer an incoming call.

B-2

Dialing the modem's number causes RI to be asserted at the EIA interface. This informs the DRVll that
a new call is being received. RI has to be in a stable state for at least 30 ms or else the change will not be
reported by the DRVll. Since DTR is already asserted, the modem will auto-answer the incoming call
and start its handshaking sequence with the calling station. The time needed to complete the handshaking
sequence can be in the order of tens of seconds if fallback mode speed selection and satellite links are
involved. The modem will assert DSR to indicate to the DRVll that the call has been successfully
answered and a connection established.
NOTE
On some older types of modem used on the PSTN,
the opposite effect is also true. The RI signal may
be very short, or it may not even occur if DTR is
previously asserted. When this type of modem
answers an incoming call it asserts DSR almost
immediately and deasserts RI at the EIA interface.
Programs must therefore expect RI or DSR or
DCD as the first dataset status change received
from the modem when establishing a connection.
As RTS was previously asserted, the modem's carrier will be placed on the line when DSR is asserted.
When the modem has successfully placed its carrier on the line it will assert CTS which indicates to the
DRVII that it may start to transmit data. Should the incoming call be the result of a misdialed number
then it is possible that a carrier signal would never be received. To guard against this, the host starts a timer
when it detects RI or DSR. This is usually in the range of 15 to 40 seconds, within which time the carrier
must be detected. When the modem detects the remote modem's carrier signal on the line, it will assert
DCD which indicates to the DRVII that data is valid on the RXD line.
The modem may now exchange data between the DRV11 and the calling station for as long as DCD,
DSR, and CTS stay asserted. If any of these three signals disappear, or if RI should be detected during
normal transmission, it would indicate a fault condition. A change of state of any of these signals would
cause an interrupt via the receive FIFO.
The handling of the fault conditions now becomes country-specific as some telephone systems tolerate a
transient carrier loss while others do not. In the USA it is usual to proceed with a call if carrier resumes
within two seconds. In non-USA areas it is possible for telephone supervisory signals, such as dial-tone, to
be misinterpreted by the modem as a resumption of carrier. In this case the host program would assume
that the connection had been reestablished to the original caller and would cause a 'hung' channel. To
prevent this, DTR should be deasserted immediately after the loss of DCD, CTS, or DSR to abort the
connection. DTR should stay deasserted for at least two seconds, after which time a new call could be
answered.

B-3

APPENDIX C
GLOSSARY OF TERMS
C.I SCOPE
This appendix contains a glossary of terms used in this manual. The terms are in alphabetical order for
easy reference.
C.2

GLOSSARY

asynchronous A method of serial transmission in which data is preceded by a start bit and followed by a
stop bit. The receiver provides the intermediate timing to identify the data bits.
auto-answer A facility of a modem or terminal to automatically answer a call.
auto-flow Automatic flow control. A method by which the DHVII controls the flow of data by means
of special characters within the data stream.
backward channel A channel which transmits in the opposite direction to the usual data flow.
Normally used for supervisory or control signals.
BAL Bus Address Line.
BDAL Bus Data and Address Line.
base address
BMP

The address of the CSR.

Background Monitor Program.

CCITT Comite ConsultatifInternational de Telephonie et de Telegraphie. An international standards
committee for telephone, telegraph, and data communications networks.
dataset

See modem

DIL Dual-In-Line. The term describes ICs and components with two parallel rows of pins.
D MA Direct Memory Access. A method which allows a bus master to transfer data to and from system
memory without using the host CPU.
DUART Dual Universal Asynchronous Receiver Transmitter. An IC used for transmission and
reception of serial asynchronous data on two channels.
duplex A method of transmitting and receiving on the same channel at the same time.
EIA Electrical Industries of America. An American organisation with the same function as the CCITT.
EMC

Electro-Magnetic Compatibility. The term denotes compliance with field-strength, susceptibility,

and static discharge standards.

C-I

FCC Federal Communications Commission. An American organisation which regulates and licenses
communications equipment.
FIFO
first.

First In First Out. The term describes a register or memory from which the oldest data is removed

floating address A CSR address assigned to an option which does not have a fixed address allocated.
The address is dependent on other floating address devices connected to the bus.
floating vector An interrupt vector assigned to an option which does not have a fixed vector allocated.
The vector is dependent on other floating vector devices connected to the bus.
FRU

Field Replaceable Unit.

GO/NOGO

A test or indicator which defines only an 'error' or 'no error' condition.

Integrated Circuit.

I/O

Input/Output.

LSB

Least Significant Bit.

LSI-ll bus

Another name for the Q-bus.

microcomputer An IC which contains a microprocessor and peripheral circuitry such as memory, I/O
ports, timers, and UARTs.
modem The word is a contraction of MOdulator DEModulator. A modem interfaces a terminal to a
transmission line. A modem is sometimes called a dataset.
MSB

Most Significant Bit.

multiplexer A circuit which connects a number of lines to one line.
null modem A cable which allows two terminals which use modem control signals to be connected
together directly. Only possible over short distances.
PCB

Printed Circuit Board.

protocol

A set of rules which define the control and flow of data in a communications system.

PSTN Public Switched Telephone Network.
Q-bus

A global term for a specific DIGITAL bus on which the address and data are multiplexed.

Q22,

Q18 and Q16

RAM

Random Access Memory.

RFI

Radio Frequency Interference.

ROM

Read Only Memory.

SMPS

Switch Mode Power Supply.

Terms used to define 22-, 18-, and 16-bit address versions of Q-bus.

C-2

split-speed A facility of a data communications channel which can transmit and receive at different data
rates at the same time.
UART Universal Asynchronous Receiver Transmitter. An IC used for transmission and reception of
serial asynchronous data on a channel.
X-OFF A control code (238) used to disable a transmitter. Special hardware or software is needed for
this function.
X-ON

A control code (218) used to enable a transmitter which has been disabled by an X-OFF code.

C-3

APPENDIX D
AUTOMATIC FLOW CONTROL
D.1 OVERVIEW
Flow control is the control of data flow along a communications line, to prevent an overspill of queues or
buffers, or to prevent loss of data when the receiver is unable to accept it.
The method of flow control adopted for the DHVII is datastream-embedded ASCII control characters. The
control characters used are X-OFF (0238) and X-ON (0218). X-OFF stops transmission and X-ON starts
transmission. The codes are transmitted in the opposite direction to the data which they control.
The DRV11 has one mode of operation for transmitted data (received flow-control characters) and two
modes of operation for received data (transmitted flow-control characters). Each mode can be enabled on
a 'per-channel' basis. Each direction of flow is discussed separately within this appendix.
D.2 CONTROL OF TRANSMITTED DATA
The mode of flow control for transmitted data is the simplest of the three flow-control modes of the
DRV11.
When the DRV11 receives an X-OFF character for a particular channel, the TX.ENA bit for that
channel is cleared. When this bit is clear the D RVII will not transmit any data on that channel; however,
internally generated flow-control characters will still be transmitted. When an X-ON character is
received, the TX.ENA bit for that channel is set. Figure 0.1 illustrates the operation ofthe transmitted
data flow control.

OAUTO=1
OAUTO=O

RD2251

Figure 0.1

Transmitted Data Flow Control
D-l

Only characters without transmission errors are checked for X-ON and X-OFF codes. The characters
have their parity bit stripped before comparison.
NOTE
For the automatic flow control to operate correctly,
the DHVll and the connected equipment must
have the same line configuration.
The transmitted data mode of flow control is enabled by setting OAUTO (bit 4 of the line control register),
and is disabled by clearing OAUTO. The default for this mode is 'disabled'. The DHYll may alter the
state of the TX.ENA bit up to 20 microseconds after the program clears the OAUTO bit.
The DHY11 always passes flow-control characters back to the program via the received character FIFO,
whether or not this mode is enabled.
D.3 CONTROL OF RECEIVED DATA
The flow control of received data is slightly more complicated than that of transmitted data; therefore, for
descriptive purposes, the two modes of received data flow control are first treated separately.
D.3.1 Flow Control by the Level of the Received Character FIFO
Occasionally, the program may not be able to empty the received character FIFO as fast as the received
data is filling it. Since the program is unaware of how full the FIFO is, it is unable to take appropriate
action to prevent data loss. To overcome this problem, the DHY11 can be programmed on a 'per-channel'
basis, so that an X-OFF is sent before the FIFO reaches a critical condition. In these circumstances,
when the FIFO becomes three-quarters full, the X-OFF is sent to the channels from which data is
received, and thereafter an X-OFF character is sent in response to every second received character.
When the FIFO level drops below half full, an X-ON character is transmitted. The operation of the
FIFO-level flow control is shown in Figure D-2.
The FIFO-level flow-control mode is enabled by setting IAUTO (bit 1 of the line control register). The
mode is disabled by clearing IA UTO. The default for this mode is 'disabled'. IfIAUTO is cleared after an
X-OFF is sent but before an X-ON would normally be sent, an X-ON is sent anyway.

D-2

IAUTO=l

FIFO.CRIT=T

FIFO.CRIT=F

RD2252

NOTE

FIFO.CRIT is set true
when the FIFO level
rises to three-quarters full, and is again set false
(F) when the FIFO level falls below half full.
Figure D-2

Received Character FIFO-Level Flow Control

0.3.2 Flow Control by Program Initiation
Sometimes there may be a requirement for the program to invoke flow control automatically; for example,
when internal buffers become full. Under these circumstances, the DRV!! provides a FORCE.XOFF
bit; this is bit 5 of the line control register. When the FORCE.XOFF bit is set, the DRV!! transmits an
X-OFF character for that channel, and a further X-OFF bit is transmitted for every second character
received on the channel. An X-ON is sent when the FORCE.XOFF bit is cleared. Figure D-3 illustrates
the operation of program-initiated flow control.

0-3

CHAR RCVD

FORCE.XOFF=1

CHAR RCVD
FORCE.XOFF=O

R02253

Figure D-3

Program-Initiated Flow Control
NOTE

The X-ON and X-OFF codes are not transmitted
instantly, because of firmware delays in seeing
and acting on the program requests; therefore, if
the FORCE.XOFF bit is set and then immediately
cleared, this does not cause an X-OFF/X-ON
sequence to be transmitted.
The FORCE.XOFF bit is set to zero by a DHVII reset sequence.
0.3.3 Mixing the Two Types of Received Data Flow Control
To calculate the effect of using the two modes, they should be logically ORed together; an X-ON will not
be sent until both sources are inactive. IfFORCE.XOFF is set while the FIFO-critical mode is active, the
SEND XOFF is immediately entered even if an X-OFF has just been transmitted. If the FIFO-critical
mode becomes active while FORCE.XOFF is set, an X-OFF is sent in response to the next received
character.

0-4

APPENDIX E
INSTALLATION GUIDE FOR THE DHVII REMOTE
DISTRIBUTION PANEL CABINET KIT
E.l GENERAL DESCRIPTION
The D HV11 remote distribution panel cabinet kit (Figure E-2) allows eight RS-232 data-only serial lines
to be distributed from one type-B (6.60 cm X 8.38 cm) (2.60 in X 3.20 in) bulkhead panel.
This arrangement overcomes limitations of space in the host system by doubling the number ofDHV11
serial lines that can be installed in the host's I/O panel.
Four variations of the cabinet kit are available. The cabinet kit contains the following components.

•
•

H3176

Bulkhead panel - fits into one type-B I/O panel cutout in the host system.

H3175

Remote distribution panel - contains eight 25-pin D-type subminiature
connectors.

•

BC22H-10

25-conductor external 3-metre (lO-foot) cable - connects the H3175 remote
distribution panel to the bulkhead panel.

•

BC05L-xx *

40-conductor internal ribbon cables ( two) - connect the D HV11 module to the
inside of the H31 76 bulkhead panel.

•

H315-B

Loopback connector ( one).

•

Screws

6-32 screws (four) used to attach the H3176 bulkhead panel to a system I/O
panel.

•

74-28684-01 Adapter plate (-VC cabinet kit only). Adapts the H3176 bulkhead panel to the
PDP-11/23+ H349 distribution panel.

The cabinet kits are listed in Table E-l. The difference is the length of the internal cables.
Table E-l

Cabinet Kit Details

Cabinet Kit

Internal Cables (Two)

Where Used

CK-DHVll-VA

BC05L-1K (53.34 cm, 21 in)

BA123 enclosure

CK-DHVll-VB

BC05L-01 (30.48 cm, 12 in)

BA23 enclosure

CK-DHVll-VC

BC05L-2F (76.20 cm, 30 in)

PDP-11/23+ H349 distribution panel

CK-DHVll-VF

BC05L-03 (91.44 cm, 36 in)

H95 42 cabinet systems

* Cable length varies - see Table E-l
E-1

LOW CHANNELS (0-3)

HIGH CHANNELS (4-7)
DIAGNOSTIC LED

BERG CONNECTOR

,...---- J 1-----,

BERG CONNECTOR

r - - - - - J2 - - . . . ,

ADDRESS ADDRESS AND
SELECT
VECTOR SELECT

~~
D

BACKPLANE CONNECTORS
MR·14074

Figure E-I

DHVll Module

E-2

~
~~7
H31 5-B LOOPBACK
CONNECTOR

6
5

BC05L-XX CABLES

3
TO DHV11 J1

m
r
W

RED STRIPE
TO PIN A

TO DHV11 J2

RD2348

Figure E-2

DHVll Remote Distribution Panel Cabinet Kit

E.2

FUNCTIONAL DESCRIPTION

E.2.1 H3176 Bulkhead Panel
The H31 76 bulkhead panel consists of two 40-pin vertical headers ·and a fully filtered female 25-pin
D-type subminiature connector. The H3176 is connected to aDHVl1 by two BC05lrXX cables which
bring eight pairs of data signals (transmit/receive), plus signal ground for each pair, to the H3176. There is
also a connection to chassis ground, using a O-ohmjumper. This jumper can be cut if chassis ground is not
desired.
Overall dimensions: 8.38 cm X 6.60 cm (3.3 in X 2.6 in)
E.2.2 H3175 Remote Distribution Panel
The H3175 remote distribution panel distributes the eight pairs of data signals (transmit/receive), plus
signal ground for each pair, to eight male 25-pin D-type subminiature connectors. The connection to the
H3176 bulkhead panel is made by the BC22H-1O cable.
Overall dimensions: 27.94 cm X 8.37 cm X 1.78 cm (11 in X 3.4 in X 0.70 in)
E.2.3 BC22H-I0
The BC22H-1O is a 3-metre (lO-foot) male-to-male 25-conductor D-type subminiature fully shielded
EIA cable.
E.2.4 BC05L-XX
The BC05lrXX cables are 40-conductor flat ribbon cables. The length of the cables depends on the
system in which they are installed.
E.3 INSTALLATION
The DHVII remote distribution panel cabinet kit is installed in a system in the same way as an ordinary
cabinet kit.
1.

Slide the DHV11 module (Figure E-l) partially out of the system backplane.

Insert the two BC05lr XX cables into the two Berg connectors on the DHVII module. The red
striped edge of the cables should be installed onto Pin A of the DHVII module Berg
connectors.

Reinstall the D HV 11 module.

If you are installing this cabinet kit into a PDP-ll/23+ system, install the adapter plate (part
number: 74-28684-01) into one of the 4X4 openings in the H349 distribution panel.

Install the H3176 bulkhead panel into the system I/O panel using the four 6-32 screws.

Insert the BC05lr XX cables into the rear connectors of the H31 76 bulkhead panel. Attach the
cable from DHV11 connector 11 to the top connector of the H3176, and the cable from
DHVII connector J2 to the bottom connector. There are small arrows on one edge of the
H31 76 internal connectors. The red striped edge of the cables should be attached to the arrow
side of the H31 76 connectors.
This procedure ensures that there is a one-to-one correspondence between the labeling of the
H31 75 and the actual physical line numbers of the D HVII. If this procedure is not followed,
the physical line numbers will not correspond to the H3175 labeling (0 to 7).

Insert the BC22H-I0 cable into the external connector of the H3176 bulkhead panel.
E-4

Insert the BC22H-1O cable into the bottom 'Input' connector of the H317 5 remote distribution
panel.

Place the H31 75 remote distribution panel in a location that is accessible, but where it will not
be disturbed. The H31 75 has three tear-drop cutouts at both the top and bottom so that it can be
mounted on a wall three different ways, or on the floor.

E.4 DIAGNOSTICS
Diagnostic testing for the DHV11 remote distribution panel cabinet it is available for MicroPDP-11 and
MicroVAX II systems. Contact your local DIGITAL sales office for the order numbers of the diagnostic
kits.
E.4.1 MicroPDP-11 Diagnostics
The following MicroPDP-11 diagnostic tests are used for the DHVII remote distribution panel cabinet
kit.

•
•

CVDHBE (revision level E)
CVDHC? (? = revision level D or E)

CVDHCD (test C, revision level D) will be available in November of 1985. CVCHBE andCVDHCE
will be available in February of 1986, in release 126 of the MicroPDP-ll field service kit.
E.4.1.1 CVDHBE Test - CVDHBE tests the ability of the device to transmit and receive characters
correctly. It tests features such as automatic X-ON/X-OFF, correct operation of modem bits, and
whether there are any bad interactions between modem signals, data signals, or other lines.
From the XXDP+ prompt (.), run the test and reply to the set-up questions as follows (the replies are
either underlined, or explained in parentheses) .

• R VDHBEO
DR> START
CHANGE HW ( L) ?.!..
# UNITS (D) ? 1

UNIT 0
CSR ADDRESS: (0) 160460 ? (Enter the CSR address of the DHV11, or just press
RETURN if the CSR address is 160460)
INTERRUPT VECTOR ADDRESS: (0) 300 ? (Enter the interrupt vector of the DHV11,
or just press RETURN if the vector is 300)
ACTIVE LINE BIT MAP: (0) 377 ? (Press RETURN)
TYPE OF LOOPBACK (l=INTERNAL, 2=H3277, 3=H325, 4=H3101, 5=H3103, 6=70-22629,
7=H315-B): (0) 2 ? :L
INTERRUPT BR LEVEL: (0) 4? (Press RETURN)
CHANGE SW (L) ? N

E-5

E.4.1.2 CVD H C?O Test - (? = revisions D and E.) CVDHC tests DMA and split speed. It also tests
modems and terminals, and verifies that data integrity checks (such as framing and parity checking) are
working.
From the XXDP+ prompt, run the test and reply to the set-up questions as follows (the replies are either
underlined, or explained in parentheses) .

•R VDHC?O
DR>START
CHANGE HW (L ) ?..!..
# UNITS (D) ? 1

UNIT 0
CSR ADDRESS: (0) 160460 ? (Enter the CSR address of the DHV11, or just press
RETURN if the CSR addre'ss is 160460)
INTERRUPT VECTOR ADDRESS: (0) 300 ? (enter the int~rrupt vector of the DHVll,
or just press RETURN if the vector is 300)
ACTIVE LINE BIT MAP: (0) 377 ? (Press RETURN)

NOTE
The choice of loopback connectors dift'ers between
revision D and E of this test, as follows.
Revision D (CVDHCDO):

TYPE OF LOOPBACK (1=INTERNAL, 2=H3277, 3=H325, 4=MODEM, 5=KEYBOARD ECHO):
(0) 2 ? (Select 3, but use the H315-B)
Revision E (CVDHCEO):

TYPE OF LOOPBACK (1=INTERNAL, 2=H3277, 3=H325, 4=MODEM, 5=KEYBOARD ECHO,
6=H3101, 7=H3103, 10=70-22629, 1l=H3l5-B): (0) 2 ? .ll
When you have chosen the appropriate loopback connector, continue as follows:

INTERRUPT BR LEVEL: (0) 4 ? (Press RETURN)
CHANGE SW (L) ? N
E.4.2 MicroVAX II Diagnostics
MicroVAX II diagnostic tests for the DHVll remote distribution panel cabinet kit are in the MicroVAX
maintenance kit. The MicroVAX maintenance kit is available on RX50 diskettes or a TKSO cartridge.

E-6

These kits contain the MicroVAX Maintenance System (MMS). The MicroVAX Diagnostic Monitor
(MDM) in MMS is used in conjunction with the R3!5-B loopback connector to test a suspected bad serial
line on the device. Load the media according to the instructions in the maintenance guide included with the
kit.
When you reach the main menu, select:
4 - Display the Service Menu
From the service menu, select
4 - Enter System Commands
Two modes of testing are available in MD M - verify and service. Tests in service mode require the use of
loopback connectors, and may destroy customer data. Use service mode to test the DRVll remote
distribution panel cabinet kit. Write-protect all mass-storage devices before running the test.
Each mode is divided into three sections - functional, exerciser, and utility. Tests in the utility section are
typically interactive. Use the utility sections to test the DRV!! remote distribution panel cabinet kit.
To get a list of the MDM commands, enter 'help' at the MDM prompt. Refer to the MicroVAX
Maintenance Guide for a detailed explanation of MDM.
After selecting '4 - Enter System Commands', press the RETURN key to start MDM. From the MDM
prompt, 'MDM> > >', enter the following sequence.
Prompt

User Response

Meaning

MDM»>

set p f

Set progress full

MDM»>

set det on

Set detailed messages on

MDM»>

set mod serv

Set MDM to service mode

MDM»>

set sec util

Set section to utility

MDM»>

conf

Configure the system

MDM»>

sho conf

Show the configuration

MDM»>

sel4

Select the number of the DRV!! you want to test from the displayed
configuration (4 here is an example only)

MDM»>

set test!

Select the staged loopback test

MDM»>

Start the staged loopback test

E-7

At this point a series of set-up questions appear. The default responses appear in brackets. Press the
RETURN key ( <RET> ), if you want to enter the default response. The default responses are valid for the
DHV11 remote distribution panelloopback test, with the following exception.
•

The default response [y] of the first question (test modem control lines?) will not correctly test
the remote distribution panel, since it is a data-only device. Answer NO to this question.

The set-up questions appear as follows (the replies which you should give are either underlined, or
explained in parentheses).

Do you wish to test modem control lines? [y]

Which port would you like to test (0-7)? [all connections] <RET>
Which baud rate would you like to test? (O-IS)? [13] (Press RETURN to test at
9600 baud, or enter ? to
list the baud-rates)
How many data bits (5, 6, 7 or 8)? [8] ~
Parity enabled (Yes = 1, No = O)? [0] <RET>
Parity sense (1 = even, 0 = odd)? [0] <RET>
Number of stop bits (1 or 2)? [1] <RET>
Attach the H315 -B loopback connector to the port to be tested and press the RETURN key. The test will
run and the results of the test will be displayed.
If you want to test another port, or restart the diagnostic program for any reason, you must reconfigure the
system. To do so, begin again at the 'conf' command:
MDM»>

conf

and continue with the remainder of the sequence listed above.

E-8