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XX-AD55D-9E
2000
43 pages
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pdp9mc
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XX-AD55D-9E
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Pages:
43
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http://bitsavers.org/pdf/dec/pdp9/pdp9mc.pdf
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(In Reverse End Zone) Tape Traveling in Forward Direction .., W 1 W 2 W 3 W 4 W 5 W 6 W 7 w 8 W 9 .}.~ .IT' "V' 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 . 0 0 0 0 0 0 1 0 1 0. 0 0 0 0 0 1 0 1 1 0 0 0 0 'I 0 1 1 0 0 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 1 0 1 0 1 1 0 1 1 0 1 0 1 1 0 1 1 0 1 1 1 1 0 1 1 0 1 1 1 1 0 1 1 0 1 1 0 1 0 1 1 0 1 1 0 1 1 1 1 0 1 1 0 1 0 1 1 0 1 1 0 1 0 1 1 0 1 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 55 ::c CD <: ~ ~ fjJ 55 ::c CD ~:: ~fjJ 0. 25 ~ c1" s: tI.l CD ~~& ~()f-I 0 ST mLE (1) Assume up to speed Mark Track is now entering window Counter Advances at TP ¢ = C-Sync 100 () ~ = C-Sync 101 100 25 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 c1" S:tI.lCD S» <4 Ij 1 1 0 1 0 1 0 1 0 ~ () 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ~ Ij ::s f-I 0' 0 = C-Sync = C-Sync 100 101 100 () ~ 101 19 8 (10) More Interb10ck Marks To Go Assume Block Mark Next = C-Sync 101 100 -2- W 1 W 2 W 3 W 4 W5 W 6 W 7 W 8 W 9 100 1 26 tx:J~ ~I-'i III 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 1 0 1 0. 32 O~ ~s=< III CD 101 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 1 0 1 0 1 a 1 1 a CD 1= 100 a a a 1 1 1 1 0 1 1 0 1 1 0 1 0 1 1 0 1 a 1 1 1 a 1 a 1 1 1 1 a 1 1 a a a 1 a 1 1 a 0 1 1 1 0 0 1 1 0 0 1 ~~~ ~0.(Jl 101 100 ~(')Ill ~~~ C-Sync = 1= Mk Blk Mk Reset ST :IDLE Set ST Blk Mk 101 000 001 1 010 all 100 101 000 10' ~S Ii(') ~~ 1 0 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 1 1 10' ::u ~I-d~ Ii 0 CD 1 1 1 0 0 1 0 0 1 0 1 0 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 001 010 all 100 == Mk Blk Start Reset ST Blk Mk Set ST Rev CK CD 1 0 0 0 0 1 0 0 0 oa 001 010 all ~O~ (Jl 101 100 = Mk Blk Start Reset ST Rev Ck Set Data 101 000 -3W1 W2 W3 W4 W5 W 6 W7 W8 W9 1ft fJ;I~ ~!j~ '11»'1 ~l-'rIl (1) 1 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 001 010 ( 1st Data) ( Word Here) 011 100 101 = Mk B1k Start 000 1ft I-1j '1 (1) ::0 I (1) fJ;I< !j~ I» rIl 1-'(1) 7f1 ~t:1 1»1» '1c1' ~I» 1 0 0 0 1 0 0 0 0 001 ( 2nd Data) ( Word Here) 1 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 = Mk Blk Start 0 0 1 1 0 1 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 1 1 1 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0 0 0 0 010 011 100 101 000 001 010 ( 3rd Data) ( Word Here) 011 100 101 000 7f1 !3::t:1 '1c1' 1»1» 1 0 1 1 1 0 0 9 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 1 0 0 0 1 0 001 010 011 ~I» 0 1 1 1 1 1 1 0 100 0 0 101 0 1 1 1 0 0 0 000 -4- W 1 W 2 W -: W 4 W 5 W 6 w 7 W 8 W 9 7~ 1 0 1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0 0 000 001 010 ~t:1 ll'll' 'ieT ~l» 011 100 101 000 Enough Data - Now Proceeding To Block End, And Entering Next Block! 73 t-cI 'i ~<D ll'l 'il:l;j ~E; ll' I-' 73 I:I;j bfE; 'ill' 1 0 1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 1 1 0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 0 1 0 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 000 001 (Next to last) ) (Data Word 011 100 101 - Mk Blk End Reset Data Set ST Final 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 0 1 0 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 ~t-cI ll'O 'iO ~ 000 001 010 (Last Data Word) ~I-' 73 010 011 100 = Mk Blk End Reset ST Final Set ST CK Reset ST CK Set ST IDLE 101 000 001 010 all 100 = Mk Blk End 101 000 -5W 1 W 2 W 3 W 4 W 5 W 6 W7 W 8 W 9 73 1 1 1 1 1 0 ::0 1 1 1 1 0 ~S~ IjQIj 1 1 1 0 1 1 0 1 0 1 co ~~1'Jl co 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 000 001 010 011 100 101 = Mk Blk End 000 51 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 1 0 1 0 0 1 001 :s:~ 1»1» Ijlj 010 011 ~o.. 100 101 000 45 1 1 1 0 1 0 0 1 1 tJj~ 1 1 0 1 0 0 1 1 0 OCO 'i()'i 1 0 1 0 0 1 1 0 0 co 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 1 0 0 1 0 1 001 ~j-J< ~~rJl 010 011 100 101 000 25 1 1 1 0 0 1 0 1 0 ~ 1 1 0 0 1 0 1 0 1 ~tIlCO 1 0 0 1 0 1 0 1 0 ~()j-J 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 C"t C<l'i 'i::Sc' 0 () ~ 001 010 = C-Sync 011 100 = C-Sync 101 000 -6W 1 W 2 W 3 W 4 W 5 W 6 W7 W8 W9 25 ~ cT f CllC'O 1 1 0 1 0 1 0 1 000 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 0 ~~ 6- 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 = C-Sync 010 = C-Sync ;:s;' 1 0 1 0 1 0 1 0 1 575(10) More Blocks To Go • (Assume EOT Next, 198 More Interblock Syncs). 011 100 ;:s;'()1-' () 001 = Mk Blk Mk Reset ST IDLE Set ST Blk Mk 101 000 Entering FWD End Zones 22 ~~~ W1 W2 W3 W4 W5 W6 W7 W8 W9 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 0 001 010 011 ;:s;'o. 100 101 000 22 ~~~ 1 1 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 1 0 0 1 0 1 0 0 1 a 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 a a 1 0 a 1 a 001 010 011 100 101 = Mk End 000 H) ) ) ) • -15V -3V • • 1")1 .. , lei R7 02 -3V -15V • • ~ 017 I 06 01 -15V 82PF ~ -l 019 82~ 018 R1 12K R2 12K 04 016 l~ I 044 R2 12K 045 T -7V H J -15V H J . ~015 03 043 -7V (J • ...., ...., -7V -15V R 129K ~046 6 -7V o F ~ ~ M '-"'-- K E L THE 5202 F. F. (2 PER CARD) )THE 8213 F.F. ) ) R +10V 010 04 03 R5 R11 1.5K 1.5K R9 pe. • (2 PER CARD) s +10V R6 _I • • 01 -3V eN 012 -4.2VO • _I v. , 07 -15V • _I U. . 1_. • o-+.2V -15V 08 • I I. -3V 0 -2.2v ':""5\1 N P N P o C2 R7 'V\I'tv • 27MMF • T 7.5K xxx s R 1.5K T R12 'V\I'tv 0 -3.5V • l I U v S-131 ADDER Carry Insert D V SUM OUT L Carry In "A" K S liS II -~ CARRY OUT To Pin L of next Adder T 1. An odd number of inputs true produce a sum out. 2. Two or more inputs true produce a carry out. B - SUMMING NETWORK: 131 If an odd number of inputs to the summ ing network is true, the sum output w ill be true. The inputs to the summing network are A (Pin S), B (Pin T), Carry In (Pin l) and Carry Insert (Pin D). Transistors Q1, Q3, Q7, Q9, Q10, Q11, Q2, Q4, Q5, Q6 and Qa affect the sum output. The output (Pin V) directly reflects the state of Q4 through Emitter Follower Qa. A -3 level equals a "One" output, a ground equals a "Zero" output. Thus, if Q4 is off, a "One" output will be reflected through Q8 and conversely, if Q4 is on, a "Zero" output will be felt at Pin V. Q4 1s state of conduction is cortrolled by the voltage potential felt on the bases of Q2 and Q5. The potential is developed across resistor R4, thus, the potential is directly controlled by the amount of current allowed to flow through R4. The. amount of current that flows through R4 is directly proportional to the number of inputs that are true. If no input is true, minimum current is flowing and if all inputs are true, maximum current will flow. Investigating this curr0nt flow further, note that transistors Q1, Q3 and Q9 are all in this current path, therefore, the conduction of these transistors will affect the amount of current that flows through R4. When the transistors are all off, minimum current will flow and when the transistors are all on, maximum curtent flows. For the sake of discussion, let us assume that when all transistors (Q1, Q3 and Q9) are off, ~ un its of current are flow ing through R4. When 1 trans istor turns on, 1 unit of current flows, 2 trar,';istors on will cause 2 units of current to flow and 3 transistors on will cause 3 units of current to flow. Q1 will turn on when "A" is true. Q3 will turn on.when "B" is true. Q9 will turn on if Carry Insert is true or if Carry In is true. Investigating Q9 further you will note that its emitter potential (thus its state of conduction) is controlled by transistor Q7 or Q11. If Carry Insert is true, Q7 turns on, which causes Q9 to turn on. I·f Carry In is true, the left hand sides of Q10 and Q11 turn on, causing Q9 to turn on. Thus, Carry Insert and Carry In are ORled together at transistor Q9. Summing up, there are four units of current possible which flow through R4. These units of current reflect how many inputs are true. It has been stated that there will be a sum output whenever an odd number of inputs is true, therefore, it is possible to conclude that since the number of inputs true will be directly reflected by the units of current present through R4, there will be a sum output whenever odd units of current flow through R4. When there are no inputs true, ~ units of current flow through R4. The potential developed across R4 is such that it will cause Q5 to turn on. Q5 turning on causes Q6 to turn off. The potential on the base of Q4 is controlled by the conduction state of Q6. Q4 attempts to cut off. However, the base potential on Q2 is more pos itive than Q4 1s base potential, which forces Q4 into the on state and Q2 off. Thus, Q4 is conducting, producing a "0" sum out through Q8 to Pin V. -2- When one input is true, 1 unit of current flows through R4. With the increased current flow the voltage felt on the bases of Q2 and Q5 goes more negative. The change of voltage is not enough to change the conduction state of Q5, therefore, Q5 will remain on and Q6 off. The base of Q2, however, is now more negative than the base of Q4. This causes Q2 to turn on and subsequently Q4 to turn off. Q4 turning off produces a negative level to Pin V through Q8. The sum is now a "1". When two inputs are true 2 units of current flow through R4, causing the voltage at the base of Q2 and Q5 to go even more negative. It would seem that this would cause Q2 to conduct harder causing Q4 to be cutoff "Harder" than before, still causing a "One" output. However, remember that Q6 was also control ing the conduction factor of Q4. The base potential on Q6 is now more positive than that of Q5, causing these transistors to change states. Q5 is now off and Q6 is now on. Q6 turning on causes the base of Q4 to go sharply negative. In fact the base of Q4 is once again more negative than the base of Q2. This causes Q2 to cut off and Q4 to turn on, producing a "0" output for the sum at Pin V. When three inputs are true, 3 units of current flow through R4, causing the most negative voltage possible to be felt by the bases of Q2 and Q5. Needless to say, a more negative potential on the base of Q5 reaffirms that Q5 is off and Q6 is on. You guessed itl Once again the voltage on the base of Q2 is more negative than the voltage of Q4 1s base, causing Q2 to turn on and Q4 to turn off, subsequently producing a "1" on the sum output Pin V. R4 Current A 8 0 0 0 0 0 C Insert CI v 0 Unit Q2 Q4 Q5 Q6 SUM 0 off on on off 0 on off on off on off on off off on off on on off on off 2 off on off on 0 2 off on off on 0 3 on off off on 0 2 0 0 0 0 0 SUMMING NETWORK 0 B - 131 CARRY NETWOR K: If two or more of the three inputs to the Carry Network are true, the Carry Output will be true. The three inputs are "All (Pin S), IIBII (Pin T) and Carry In (Pin L). The Pin K (Carry Out) voltage is a direct analog representation of the inputs to the carry circuit. There are four distinct states at which the inputs can exist. They are: all off (i .e. not true), one true, two true and all three true. It is possible to conclude that since the inputs can be in four possible conditions, the voltage measured at Pin K (Carry Out) will be indicative of the number of inputs that are true at any given time. There are four possible voltage levels at Pin K. When two or more inputs are true the voltage level at Pin K is an assertive value. Pin K is connected to the next most significant Adder Stage (Pin L) Carry Input through a 100 ohm resistor, thus the assertive level of a carry out, becomes an assertive carry in level for the next most significant Adder stage. Briefly, this is how the carry circuit operates. First of all, transistors Q1, Q3, Q12, Q11 (L) and Q11 (R), Q10 (L) and Q10 (R) are associated with the Carry Network. Once again, there are four possible voltages at Pin K. With no inputs true, the voltage at Pin K will be at its most negative level, and with all inputs true, the voltage at Pin K will be most positive. The Pin K voltage is directly dependent on the base voltage of Emitter Follower Q 11 (R). The base voltage of Q 11 (R) is dependent on the amount of current flowing through R-36 and the voltage at the emitter of Emitter Follower Q12. The current flow through R36 is controlled by the state of conduction of Current Sw itch Q 10 (L) and Q 10 (R). The state of Q 10 (L) and Q 10 (R) is dependent on the Carry Input Level at Pin L. The voltage at the emitter of Emitter Follower Q12 is dependent on the voltage at the base of Q12. This base potential is controlled by the conduction states of Q1 and Q3, which are monitoring the "A" and IIBII Inputs at Pins Sand T. There are three possible voltages developed at the base of Q12. The most negative potential will be present when both A and B are not true. The most positive potential will be present when both A and B are true. A middle voltage potential (Halfway between most negative and most positive) wiJl be present when either one of the inputs (A or B) is true. Thus Emitter Follower Q12 is capable of supplying three different voltage potentials to the base of Q 11 (R). However, there has to be four voltage potentials at the base of Q11 (R). Q12 supplies three of them. Let us investigate how the fourth voltage is supplied. The fourth potential is supplied via the voltage drop across R36. Need Iess to say, current must flow throuqh R36. It will be shown that if Carry In is not true, current will flow through R36 developing a voltage. Thus, with no inputs true, the voltage supplied by Q12 will be at its most negative level, delivering 3 negative voltage units to the Q11 (R) stage, and current is flowing through R36, delivering 1 negative voltage un it to the Q 11 (R) stage. This causes Pin K (Carry Out) to be at its most negative potential. -2- Carry In (Pin L) controls QlO (L) and QlO (R) in this manner. When Carry In is not true, the base of Q 10 (R) will be more pos it ive than the base of Q 10 (L). The more positive base level of QlO (R) is felt on the emitter of QlO (L). These voltages cause Q 10 (R) to turn on and Q 10 (L) to turn off. When Q 10 (R) turns on current will flow through R 36, which causes one negative voltage unit to be felt on the base of Ql1 (R). This signifies that Carry In is not true. When the Carry In voltage (Pin L) reaches an assertive level, the base of QlO (L) will be more positive than the base of QlO (R). The more positive level at the base of QlO (L) is felt on the emitter of QlO (R). These voltages cause Q 10 (L) to turn on and Q 10 (R) to cut off. Current ceases to flow through R36. Since current is not flowing through R36 one less, negative voltage unit will be felt on the base of Q11 (R). (i.e. The base voltage of Q11 (R) will raise 1 unit positive.) This signifies Carry In is true. IIA" and IIB" (Pins Sand T) control the base potential of Q12 in this manner. When "A" and "B" are not true Ql and Q3 are cut off. This causes 02 and 03 to forward bias. 02 and 03, when forward biased, cause a negative voltage to be fed to the base circuit of Q12, causing the base of Q12 to go negative. The base of Q12 is most negative when both D2 and 03 are forward biased, signifying that both IIA" and "B" are not true. Of course this most negative voltage is fed to the base of Q11 (R) conveying the condition of "A" and liB II • When either "A" is true or IIBII is true (but not both), one of the diodes (02 and 03) will be forward biased and the other will be reverse biased. This causes the negative voltage on the base of Q12 to be cut in half, which now conveys the fact to Q11 (R) that one of the inputs (either "A" or IIB") is true. When both IIAII and IIB" are true, Q1 and Q3 are turned on, causing diodes 02 and 03 to be reverse biased. This action causes the base of Q12 to go to its least negative voltage, signifying to Q11 (R) that both inputs ("AII and "BII) are true. The Carry Out voltage (Pin K) will be assertive for four combinations of Inputs. Remember if two or more inputs are true, a Carry Out will be generated. Also, remember there is a maximum of four negative voltage units at the base of Ql1 (R). Three units are developed at Q 12 and one unit is developed at R36. When four or three negative units are present at Q 11 (R) Ca rv <)ut (Pin K) will be negated. When two or one negative units are presel"t at Q11 (R) the Carry Out (Pin K) will be assertive. When "AII and IIB" are both true, both diodes 02 and 03 are reverse biased, causing the base of Q12 to go to the least negative potential. This causes the base of Ql1 (R) to go two units positive producing a Carry Out. R36. When "AII and Carry In are true, 02 is reverse biased and current does not flow through This causes the base of Q11 (R) to go two units positive producing a Carry Out. R36. When "B" and Carr'! In are true, 03 is reverse biased and current does not flow through This causes the base of Q11 (R) to go two units positive producing a Carry Out. -3- When "A" and "8" and Carry In are true, 02 and 03 are reverse biased and current does not flow through R36. This causes the base of Qll (R) to go three units positive produc ing a Carry Out. The four above conditions are the only combination of inputs that will cause a Carry Out. All other cond it ions would not cause the voltage on the base of Q 11 (R) to go positive enough to produce a Carry Out. ** Q12 Voltage QlO QlO L R Qll (R) *** Voltage * Carry Out A B CI Potent. 0 0 0 0 Off On 0 0 0 On Off 0 Off On 0 On Off Off On On Off 2 2 Off On 2 2 On Off 3 0 0 0 0 0 0 0 Potent. 0 2 0 * A one equals a Carry Out I however I it is an analog voltage and does not represent normal DEC logic levels. ** o = Most Negative. 2 == Least Negat ive . *** 0= Least Positive. 3 = Most Positive. 0 A B 0 0 0 0 CI v Cry Insert 0 0 0 0 0 0 0 0 A B 0 0 0 0 CI 0 0 0 CO 0 0 0 ADDER R4 Current 02 BE 1.37 rna +5.643 8.97 rna +3.659 I +2.909 8.97 rna f 05 BE 06 BE II +4.893 +2.1 Surn Out +4.885 0 +4.885 +3.659 I +2.909 +2.1 +4.885 15.2 rna +2.033 + 1.283 +2.1 +1.46 8.97 rna +3.659 +2.909 +2.1 +4.885 15.2 rna +2.033 + 1 .283 +2.1 + 1.46 0 15.2 rna +2.033 . + 1.283 +2.1 + 1 . .16 0 22 rna + .258 - .492 +2. 1 +1.46 011 (R) E E Next Stage 010 (L) B E -5.0 -6.7 0 -3.7 -5.7 0 -3.7 -5.7 -2.4 -4.6 -3.7 -5.7 -2.4 -4.6 -2.4 -4.6 -1.1 -3.5 0 04 BE +2.1 0 0 0 B - 131 0 """~,,, AR~66 BY DIGITAL '"" ""'"' ,"'''".., PYRIGHT! rooe • R4 261 MF I ro - ~ • V ..1..lZ:~.~ '" ~R12 7,500 _ ~j DeE~ 05 DEC 3009B DEC 3009B ... f f (AI ~ ~R13 _ -___ I r-' ,01 MHl ~R36'" _. , 470 03 DEC 10% 30098 R22 1,500 C3 ----=-~- -1-' -( , 10% DO:C f'" 3009B 09 DEC __.---1 - 3009B -,-- ._f~_~·G UNLESS OTHERWISE IIOCATED; RESISTORS ARE 114W; 5 'Yo MF RESISTORS ARE METAL FIL.M 1/8W DIODES ARE 0662 D668 2 (TWO) IN3606 IN SERIES 1;33 261 MF MF .J!- ~ 1f~i; ~t? MODULE 8Y A 100""- i!4W: 5%, CARBON RESISTOR FROM PIN K TO PIN L T;);;7[-~, -oC,U GNO t r:':~'::' --- -- -- -- -- _-L_~·\Jg- MFD - R27 237 * CO IS CO~NECTED YO CION n:E NF XT 1'Yo 100 PPM C2 I - . 01 I -J' _ ._ ,.... c~ 0 I0 SDA-8 6660666 I -.6V 017 ~:I)r,~~-;$t4~ 1'f.64 ',21 MFD €ib: 011 SOA-8 cr--..Mr-H -J 470 ~ .D3 0668' *D19 -LC5 'T'.OI 018 (CARRY I"S<:R Tl /-- ;--.. 0 oll4 I" '. RI L;::' 1'" ;.09 ! 0668 RI6 4640 ~,OOO I ___ _ +_ i D668 RIO 1,500 t::j~ •• • IOV III " C8 R:g}R41 " r./ _. "" ,,,.. h " , ' , / ) 30( 94 '~--'T 06 ff , T 2 1. 0,. _. _." "" - ' ..... r "'~-1."i~ I, - , D~ I '. ~J% " I Dot>· $15,000 -_c·_ '.,; 'HF""" 562 '" I ~R6 -'n . ------~. .OIMFD 04 • ..::...iI:!_ .-.. e- __ __ - , . . . : 220 DEC~ 3639 01 ~.---~-.~--.,,,, -'-~. _ h_ _ __ f" R7 220 ~ , ____ ..___ _.. ____ -----r-------I-o---=JfISp3[Sj· f--~ L".J;~~ _. _ H38~mN3aO:l 3ZIS I f I=E_ R~~ 5. rNANCE PU GLY TIC 15 FURNIS HED NATURE AND TORATION AND MAIN < EO ACCORDIN THE ONLY FOR TE;HOULD BE TREAT ----' CIRCUITS " \ \ . . • . . ·-·II: . · . . . ~:. -.IV f~l6 f 11 0 'B -151t L5V I -----,-----::::::-::--:-:-:--:------- ~~~;LETT~ ,~~:,_~,: __ uT,~A:{ OR ,tU':O~DECONVE,RS!Sl1~HAR1---~"1I--"-D-.-D·-D--~-D"'lT-'T-Cl--' ORr-. ~~~'LVERMAN ~~~/~j ~~J~~:I! --W30~~ _-=- rD66:0E~~_-~~E~-;;~~ ~ i l l · ADDE R B 131 ~~363~ ~f,~~~:±;~±±::!:;::!:;::!:;::!:;::!:;;;;!;:::!:;::!:;::!:;::!:;::!:;::!:;=====::!:;::!:;=;;;!;:d:~=~ ~ ~- ,------1 E~ OIZlJ' _~~.J.B~~-I com-r--~ _____ :____ J ~~:~-==~~~:~::±.~==--:r= __-- '~<~~P~~'~:,A,:I>~.?~R. ::-;OGGE 2-9.&61' 10ATE -- 1 SDA. S --- f0NE _ DIGITAL EQUIPMENT CORPORATION ~ MAYNARD, Q LJ ! PM E NT: LPR,NTt[, ,'HI =wn rr I IIR~.I I NelMS" . - - - - - ... I REI MASSACHUSETTS ,- -15V +6V -15V -2.1V THE 131 ADDER V 1.5K 250 550 +10V +2.1 V ••- - - - - + - - - i 220 +IOV 470 .~i -15V 1.5K f i -15V -- ......L- - 1":":\ "-~I P /7 ~ ~3K I • -15V -5V -\,~~ 1 SUM OUT fv 250 CARRY~ ADR OUT CMPL 0 L CARRY IN ~~ I S T
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