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Document:	FPF11 Floating-Point Processor Technical Manual
Order Number:	EK-FPF11-TM
Revision:	001
Pages:	75
Original Filename:

OCR Text

K-FPF11-TM-OO1

FPFI]

- Floating-Point
Processor
Technical Manudl

FPF]

Floating-Point
Processor

Technical Manual

Prepared by Educational Services
of
Digital Equipment Corporation

1st Edition, July 1981

The material in this manual is for informational purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in this manual.

Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000 computerized
typesetting system.

The following are trademarks of Digital Equipment
Corporation.

DIGITAL
DEC
PDP
DECUS

DECsystem-10
DECSYSTEM-20
DIBOL
EduSysiem

DECLAB

VMS

UNIBUS

VAX

MASSBUS
OMNIBUS
0S/8
"RSTS

RSX
IAS

MINC-11

9/83-15

CONTENTS

CHAPTER 1

INTRODUCTION

GENERAL ..o e
FEATURES OF THE FPF11 .cooooiiiiiioieeeeeeeeeeeeeeeeeooo
ARCHITECTURE ...ttt

SPECIFICATIONS ...
RELATED DOCUMENTS ...ttt

1-1
1-4
1-4

1-4
1-5

REVIEW OF FLOATING-POINT NUMBERS
INTRODUCTION. ...ttt
INTEGERS ...

O
—

o
L

Lok oW

FLOATING-POINT NUMBERS .........cooooioiiiioer oo
NORMALIZATION ...ooiieeeeeeeeeeeeeeeeeeeeeeeeeeee

2-4

INTRODUCTION ..ottt
FPF11 INTEGER FORMATS: SHORT AND LONG ..o

3-1

Floating-Point EXponent..............ccooooovimooeoooeeeeeeeeeeeeoeo

3-6

Floating-Point Fraction...................c..........e

FPF11 PROGRAM STATUS REGISTER ....c.oovoooioirmeoeeeeoeoeooo
PROCESSING OF FLOATING-POINT EXCEPTIONS.....ooovooooooos

FLOATING-POINT ACCUMULATORS .....ooroeeeeoeeeeoeoeeoeeeoo
INSTRUCTION FORMATS ......ooviimieieaooe e

4.3.2

4.3.3
4.3.4
4.3.5

4.3.6
4.3.7
4.3.8

4.3.9
4.3.10

4.3.11

4.3.12
4.3.13

4.3.14

3-1

3-3

4.1

4.3.1

2-3

FPF11 FLOATING-POINT FORMATS:
SINGLE-AND DOUBLE-PRECISION ..o
FPF11 Floating-Point Data Word..............ccooooooomoeeeeoeoooo

FLOATING-POINT INSTRUCTIONS

4.3

2-1
2-2

FLOATING-POINT ADDITION AND SUBTRACTION ..o
FLOATING-POINT MULTIPLICATION AND DIVISION ..o

CHAPTER 4

4.2

2-1

INSTRUCTION SET ...ttt

3-1
3-5
3-6

3-8

4-1

4-4
o 4-11
Floating Modulo INStruction.............o.c.ooioeoeeoeeeooooooeoee 4-11
Load INStIUCHION ...ovouiiiitieiicet
e 4-11
StOre INSTIUCHION ...cvoveeeietee e
o 4-11
Load Convert Double-to-Floating, Floating-to-Double
INSTrUCHIONS .e.eeoiieiiic
e et 4-11
Arithmetic INStIUCHIONS ..........c.ooiioeiiieeeeoeeeeeeee

Store Convert Double-to-Floating, Floating-to-Double
Instructions .............coooovooiioiooiee et
et e e et tt
e e 4-12
Clear INSTrUCHION. ......c.ooviiitiiiee e 4-12
Test INSTrUCION. ....o.oeiiiiii e 4-12
ADSOIULE INSEIUCTION .ovvoeiieiieec e 4-12
Negate INSTruCtion......cocooiiiiiiiii
e 4-13
Load Exponent INStruction .............c.ooeooe oo 4-13

Load Convert Integer-to-Floating Instruction ... 4-14
Store Exponent InStruction................cooocomvooooeooooeeo 4-15

Store Convert Floating-to-Integer InStruction ...........o.ocoov oo 4-17

CONTENTS (Cont)

4.3.22
4.4

Load FPF11’s Program Status (LDFPS) Instruction.........cccoccoocoiiiniinnnnn 4-20
Store FPF11’s Program Status (STFPS) Instruction ..........cocooniniinn 4-20
Store FPF11’s Status (STST) INStruction ........cccoociviiiiiiiiiiiiiiininneee 4-20
Copy Floating Condition Codes (CFCC) Instruction .........cocooeiiiiiniiinens 4-21
Set Floating Mode (SETF) Instruction ... 4-21
e 4-21
Set Double Mode (SETD) INStruction ......cccccoocuiiiviimniriiiiiiiieiiieie
nien 4-21
iininininiini
.......oooove
Set Integer Mode (SETI) Instruction..
4-21
o
..
InStruction
Set Long-Integer Mode (SETL)
4-21
.
.
.
FPF11 PROGRAMMING EXAMPLES

CHAPTER 5

FUNCTIONAL DESCRIPTION

4.3.15
4.3.16

4.3.17

43.18
4.3.19

=—t

t
s eare e e eab s e e s e e st
e et e et
R AL oot
GENE
t
e aaa e e st e sttt
s et
OVERVIEW oot
FPF11 CONTROL AND DATA FLOW DESCRIPTION ...
Microcontroller: Sequencer and Control Store........ooooieiiiiiiin
MIB TNt ACE oo e eeieeeeeeeeee e e eeeieeee e e e e e e et eseebtee e s srnne e e e s bss e e e st e e e snieeneeeans

Wb
-

L0 L9 19 Lo Lo L L W 1D L0 LD LI L LW W W L L W W Wb —

4.3.20
4.3.21

CHAPTER 6

5-1
5-1
5-2
5-2
5-5

Receiving Logic (from the CPU) ... 5-5
Transmitting Logic (to the CPU) ..o 5-5
s 5-5
Interface Control and Clock LOZIC .....oviiirrioiiiiiiii
Interface Control LOZIC .......ooovreieiriiiiiiiiiieie e 5-9
CLOCK LOZIC oot 5-9
e e e eenree e e e et s e e s e e nrrae e e s st e e e s 5-10
DAL INEEITACE cneeeeeeeeeee e
s 5-10
TBUS RESOUICES ..veeeeeeeeieieiiiiieeeeeeeeeeeeeaesaeeseeieeieesetrreneeeeaaeaaaaeeesresasanan
5-10
.
Floating-Point Instruction Register (FPIR) ..
5-12
t
FD/FL REISTET ....eeieienieieiiiiiiiiieeene s
5-12
ii
cooonini
Floating-Point Status (FPS) Register.......c
5-12
i
s
iiiiiiii
eviiiiii
Status Flags RegiSter.....coo
5-12
s
t
e
e
e
sse
o
e
et
e
CONSLANT ROMS ..
5-12
s
st
s
e
e
e
e
e
absbe
s
a
e
e
s
s
e
msebeeeeeenabbbabaas
s
T oot ee e e e ee e e e e e e eeeasaeeeeee
COUIIE
5-12
iiiii
..ocovni
Microprocessor Data Path LOIC....
5-12
e
iiiiieiiee
Address MUltIPIEXETS ...vevveeveeiii
5-13
t
i
Shift Linkage LOZIC....ooeeieiiiiiiii
5-13
eieee
eiiiii
ereiii
Fast Carry LOZIC. . ovevei
5-13
s
irsieenceiee
enieniriienits
.....cueeuieir
OT
AM?2901 Bipolar MICTOPIOCESS

INSPECTION AND INSTALLATION

GENERAL .ottt ettt
t
tt
e e
ot
INSPECTION ..ettt
INSTALLATION PROCEDURE .....oooiiiiiiiiiei i

6-1
6-1
6-1

MAINTENANCE

MAINDEC CIFPAA (FPF11, NG 1)
MAINDEC CJFPBA (FPF11, NO. 2) it

7-1
7-1

Figure No.
1-1

1-2

2-1
3-1

3-2
3-3
3-4

3-5
3-6
3-7
4-1

4-2
4-3
4-4

4-5
4-6
4-7

4-8
4-9
5-1
5-2

5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
6-1
6-2
6-3

Titie

Page

FPFTT Module (M8188) ......cuiieiiiieeeoeeeee
eeeeeeeeeeoo
1-2
FPF11 Floating-Point Processor, Functional Block DIagram .coooevee
eieireeeeea
-3
NOrmMaliZaAtioN ..o
2-3
Integer Formats.............coccoviiii
ioeeeeee
3-2
Floating-Point Data Formats in Memory........cooooo
ooevooo 3-2
Floating-Point Data Words in Memory...........cccoovo
veveeooo
3-3
Interpretation of Floating-Point Numbers .......ccocooovooe
ovooo 3-4
Unnormalized Floating-Point Fraction ...........cccc
ooooveoi
3-5
Floating-Point Exponent NOtations..............cocoovv
voeecooo
3-6
FPF11 Status Register FOrmat ...........cocoooooovevm
omoeoooooo
3-6
Floating-Point Accumulators .........oocooooovoiooei
oooeoo
4-1
FPFIT Instruction FOrmats........o.ooovoviiivioioieoe
eoeeoeooo
4-2
Double-to-Single-Precision Rounding ..........ccoco
ovevveee 4-11
Single-to-Double-Precision Appending ...........occoooo
ooeoooo 4-12
Shifting an Integer Left Eight Places ...........cocoooo
meeeooooo 4-15
Example of a Normalized Integer..............cccoooovo
evoeomo 4-15
Store Exponent (Example 1)..........oocoovoiooio
omoooooo 4-16
Store Exponent (EXample 2)...........ocovoovovomoooooo
ooooooo 4-16
Example of a Store Convert Integer ...........cococev
oevevooooo 4-17
FPF11/CPU INterface.........coooiueuimiiieiiioooeeeoeeeoee
eooeooo
5-1
FPF11 Floating-Point Processor, Functional Block Diagram ....c..c.c
cooooviiveeii 5-3
Microcontroller (Sequencer and Control Store),
Functional Block Diagram ..........c.c.co.ooooovoooiiom
oooeooo
5-4
FPFT1 Control Word ........cccooenimiiiiieoeeeeee
eeoeoo
5-6
MIB Interface, Functional Diagram...........cococoo
vooeoo
5-8
Interface Control and Clock Logic, Functional Diagram......cc.oc
coovviiioveeinen 5-9
DAL Interface, Functional Diagram ...........cccocoo
ovooeoooo 5-10
TBus Resources, Functional Diagram ..........oooco
oovooo 5-11
Microprocessor Data Path, Functional Diagram ......ooo.oc
ooovoooio 5-13
AM?2901 Bipolar MiCrOPIOCESSOT . ............c.oweveeeeeeeeoo
ooooooo 5-14
RAM Register File Layout ...............ccooomommoeoeoo
ooooo 5-15
FPF11 Module in Various Configurations ..........cocoooov
voooo 6-2
FPF11 Cable Layout...........cccocoooioiiiiiiooo
eoeeooooo
6-3
FPFI1 Jumper Locations ............oo.oououoeioooooee
ooooo
6-4

TABLES
Table No.
3-1
3-2
4-1
4-2

4-3
5-1
6-1

Title

Page

FPF11 Status Register Bit DeSCTiptions .........cocoovevevovooooooooooooo
FPET1 EXCePtion COodes. .......oovuvuiuiiveviioeeeeeeeeeeeeeeeeeeoeeoeeeee
eee
Format of FPF11 INStructions..............ococooooooooooooo o

4-3

I'and L Formats and Their Floating-Point EQUivalents ...

4-18

FPFT1 Jumper Configurations...............c.ooooouoerooeooooooeoeooeeeeo

6-4

FPF11 INStruction Set...........oooooovivoioioooooooeeeoeee

Control Word Bit DeSCriptions ..............cocoooooooeoooeooeooeoeoeoeooo

3-7
3-8
4-6

5-7

PREFACE

The FPF11 floating-point processor is an option designed to operate with a PDP-11/23 central processing unit (or other compatible CPU) in executing floating-point arithmetic operations. This manual provides a detailed technical description of the FPF11 and service information.

Chapter 1 describes the features of the FPF11 and its architecture.
Chapter 2 outlines the fundamentals of floating-point arithmetic.
Chapter 3 describes the three data formats the FPF11 recognizes.
Chapter 4 describes the floating-point instructions the FPF11 uses.

Chapter 5 gives a functional description of the FPF11.
Chapter 6 contains the information necessary to inspect, install, and check out an FPF11 ina
PDP-11/23 or other compatible system.

Chapter 7 describes the diagnostics used to verify the FPF11 is operating properly.

vii

AA/RAR

A Ay

INTRODUCTION

1.1

GENERAL

The FPF11 floating-point processor is a hardware option for use with the PDP-11/23 or other FPF11compatible central processing unit (CPU). Its function is to execute the entire PDP-11 floating-point

instruction set.

The FPF11

is contained in one quad-height module, M8188 (see Figure 1-1), which becomes an integral
part of the CPU when installed. The module is installed in the backplane slot adjacent to the CPU (for

systems using the PDP-11/23). It connects to the CPU by a ribbon cable that plugs into the socket
designated for the optional floating-point processor chip. The FPF11 does not connect to the system
bus, and therefore, has no affect on bus loading. Figure 1-2 shows the FPF11 signal interface with the

CPU. These signals are discussed in Chapter 5.

The FPFI1’s dedicated high-speed data path increases the execution speed of floating-point instructions. The 64-bit-wide data path avoids the use of complex arithmetic coding routines that would be
required if a 16-bit CPU were to operate on the 32-bit or 64-bit operands. The FPF11 uses its own
internal clock to speed up the execution of floating-point instructions. This clock is controlled by the

FPF11 microcode and generates variable-length microcycles so that each microword is executed in a
minimum amount of time. In addition, the FPF11’s operation does not depend on the memory management unit (MMU) for its scratch-pad registers, as the KEF11-A floating-point option does.

The FPF11 features both single- and double-precision (32- or 64-bit) capability. It uses the same addressing modes and memory management (when present) as the CPU. Floating-point processor instructions can reference the floating-point accumulators, the CPU’s general registers, or any location in
memory.

1-1

gza 3 013

_¢m:|_._”_lu108m16o3llum__O||683m_nnm__18LY339.3mn_;_O_81093(05h933_“fin_n_m_vsd]6—3n_]e(Byo9v3_n_m”I‘€3n_n__n:623Lv3ea_m_mn____v8i1d3913n____m93___

=Lg__HHh013t8oS3nELe_fo_fiLl__lnn___2a-€33=8I.3l—_nn__—R9509333=i__fml3=wn=__o_vA3mo)_A5v3E(J_=-__HH““B,OE!In_m_0Nz39-238:E=_f“_lg-HZ.3¢f—[iv

3k d= [ w3 =3 A
1

0/3

[aI-n3]i]

][oim

MAIN MEMORY

(

SYSTEM BUS

=)
N

ceu

TCPU CLK

RESET H
CSEL L

FPF11

=
MR-4286

Figure 1-2

FPF11 Floating-Point Processor, Functional Block Diagram

1-3

1.2

FEATURES OF THE FPF11

Performs medium-speed, floating-point operations

17;¢-digit accuracy

Microprogrammed control store

Six 64-bit floating-point accumulators

Error recovery aids

No affect on system bus loading

32-bit (single-precision) and 64-bit (double-precision) data modes

Addressing modes compatible with existing PDP-11 addressing modes

Special instructions that improve input/output routines and mathematical subroutines

Allows execution of in-line code*

Converts 32- or 64-bit floating-point numbers to 16- or 32-bit integers during store
instructions

1.3

Converts 32-bit floating-point numbers to 64-bit floating-point numbers, and vice versa, during load and store instructions

ARCHITECTURE

The FPF11 contains scratch-pad registers, a floating exception address (FEA) pointer, status and error
registers, and six general-purpose accumulators (AC0-ACS).
Each accumulator is interpreted to be either 32 or 64 bits long, depending on the instruction and the
status of the floating-point processor. For 32-bit instructions, only the leftmost bits are used. The remaining bits are unaffected.
The six general-purpose accumulators are used in numeric calculations and interaccumulator data
transfers. The first four registers (ACO-AC3) are also used for all data transfers between the FPF11
and the central processor’s general registers or memory.
1.4

SPECIFICATIONS

Identification

M8188

Type

Quad-size

Height

26.5 cm (10.5 in)

Length

22.8 cm (8.9 in)

Width

1.27 cm {0.5 in)

* That is, floating-point instructions and other instructions can appear in any sequence desired.

Bus Loads

None

Environment

Operating Temperature

_—

Power Consumption

(o)

59 Cto 50° C (41°

Humidity

nar~ant

+5.0 Vdec, 5.5 A

1.5
RELATED DOCUMENTS
The following documents supplement the information contained in this manual.
Document

Number

Microcomputer Interfaces
Microcomputer Processor Handbook

EB-158

AWLNJwWwNIL

EB-1

These documents can be ordered from:
Digital Equipment Corporation
444 Whitney Street

Northboro, MA 01532
Attention:

Printing and Circulating Services (NR2/M15)
Customer Services Section

1-5

CHAPTER 2
REVIEW OF FLOATING-POINT NUMBERS

2.1
INTRODUCTION
This chapter briefly outlines the fundamentals of floating-point arithmetic, providing useful
backgrouna for more advanced topics in later chapters. if you are aiready familiar with floating-poin
t arithmetic, go directly to Chapter 3 for a discussion of FPF11 data formats.

2.2

INTEGERS

In many cases, data in a computer system is represented by integers. For example, the numbers

could be represented in a 16-bit machine would range from 0000005 to 1777778 (019 to 65,5361¢).

that

How-

ever, there are problems with integer representation. A number between 1 and 2, for example,
could not
be represented. Thus, integer representation imposes an accuracy limitation. Furthermore,
numbers
greater than 65,536,¢ also could not be represented. This imposes a range limitation.

These limitations are caused by the stationary position of the radix point (for example, the

decimal
point in base 10 notation, the binary point in base 2 notation). An integer’s radix point is omitted
in
integer representation since only whole numbers are used. (A defined radix point implies the possibility
of fractions in the numbering scheme.) For this reason, an integer is sometimes called
a fixed-point
number.
Integer notation, however, can be modified to overcome the range and accuracy limitations imposed
by
a fixed radix point. This is done through the use of floating-point notation.
2.3
FLOATING-POINT NUMBERS
Floating-point numbers, unlike integers, have no position restrictions on their radix points. A

popular
type of floating-point representation is called scientific notation. In scientific notation a floating-poin
t
number is represented by some basic value multiplied by the radix raised to some power.

basic
value

//exponent
1,000,000,¢9 = 1. X 109
\

2-1

There are many ways to represent a number in scientific notation, as shown below.
5120

X 1072

= 51200.
=
=
=
=
=

% 107!
5120.
% 100
512
x 10!
51.2
5.12 X 102
512 % 103

The convention chosen for representing floating-point numbers with scientific notation in the FPF11
requires the radix point to be always to the left of the most significant digit in the basic value (for
instance, .512 X 103 above). In this way fractions are represented. More examples of scientific notation are shown below.

Decimal | Scientific Notation
Number

64
33
1/2
1/16

0.64
0.33
0.5
0.625

Binary

Octal

Decimal

X 102
X 102
X 100
x 1071

0.1
041
0.4
0.

X 83
x 82
x8Y
X 81

0.1
0.100001
0.1
0.1

x 27
X 26
x 20
X 273

Note that in each of the examples above, only significant digits are retained in the final result and the
radix point is always to the left of the most significant digit. Establishing the radix point in a number
whose basic value is greater than (or equal to) 1 is accomplished by shifting the number to the right
until the most significant digit is to the right of the radix point. Each right shift causes the exponent to
be incremented by 1. Similarly, establishing the radix point in a number whose basic value is between 1|
and O (that is, a fraction) is accomplished by shifting the number to the left until all leading Os are
eliminated. Each left shift causes the exponent to be decremented by 1.

To summarize, the value of a number remains constant if its exponent is incremented for each right
shift of the basic value and decremented for each left shift. The representation for floating-point fractions is one in which all nonsignificant leading Os have been removed. The process used to obtain this
representation is called normalization and is explained in more detail in Paragraph 2.4.

2.4

NORMALIZATION

In digital computers the number of bits in a fraction is limited. Retention of nonsignificant leading Os
decreases accuracy by taking places that could be filled by significant digits. For this reason, the process called normalization is used in the FPF11. Normalization consists of testing a fraction for leading
0s and shifting it left until it is in the form 0.1... . The exponent is accordingly decremented by the
number of places of the fraction is shifted left. This ensures that the normalized number retains equivalence with the original number. Since digits to the right of the binary point are weighted with inverse
powers of 2 (thatis, 1/2, 1/4, 1/8...), the smallest normalized fraction is 0.10000... (1/2), and the largest normalized fraction is 0.11111... . Figure 2-1 shows an unnormalized fraction that must be leftshifted six places to be normalized. The exponent is decremented by six to maintain equivalence with
the original number.

2-2

EXPONENT

FRACTION

NORMALIZED

100

011

000

111

001

NORMALIZED

011

101

111

001

000

DECREASE EXPONENT BY SiX

LEFT-SHIFT FRACTION SIX PLACES
MR-5895

Figure 2-1

Normalization

Problem A — Represent the number 751 as a binary normalized floating-point number.
1.

Integer conversion.
7510 = 1001011,

Convert to floating-point form.

1001011.0 x 20 = 0.1001011 x 27
Fraction = 0.1001011
Exponent = 111

Problem B - Represent the number 0.25;¢ as a binary normalized floating-point number.
1.

Integer conversion.

0.2519 = 0.01,
2.

Convert to floating-point form.

0.01 x 20 = 0.1 x 2
Fraction = 0.1
Exponent = —1

2.5

FLOATING-POINT ADDITION AND SUBTRACTION
In order to perform floating-point addition and subtraction, the exponents of the two floating-point
numbers involved must be aligned or equal. If they are not aligned, the fraction with the smaller expo-

nent is shifted right until they are. Each shift to the right is accompanied by an incrementation of the
exponent. When the exponents are aligned or equal, the fractions can then be added or subtracted. The

exponent value indicates the number of places the binary point is to be moved to obtain the integer

representation of the number.

2-3

point representation.
In the example below, the number 7;g is added to the number 40,0 using floatingvalue dictates
exponent
the
added;
are
fractions
the
then
and
Note that the exponents are first aligned
the final location of the binary points.

0.101 000 000 000 000 X 26 = 505 = 40
0.111 000 000 000 000 X 23 = 73 = 70

To align exponents, shift the smaller fraction three places to the right and increment its exponent by
three, then add the two fractions.

0.101 000 000 000 000 X 26 = 503 = 40;o
+0.000 111 000 000 000 X 26 = 73 = Tip
0.101 111 000 000 000 X 26 = 57y = 47y

To find the integer value of the answer, move the binary point six places to the right.
5

0 101 111.000 000 000 = 57g = 4710
A

2.6

FLOATING-POINT MULTIPLICATION AND DIVISION

added. In
In floating-point multiplication, a fraction is multiplied by another and their exponents are
need
You
d.
subtracte
are
s
exponent
their
and
another
floating-point division, a fraction is divided by
not align the binary points in floating-point multiplication or division.
Example: Multiply 710 by 40j0.

X 23 0= 7g= Tyo
0.111000

X0.1010000 X 26 = 505 = 40;0
1110000

0000
11100

(Result already in normalized form.)

Move the binary point nine places to the right.
4

700011000.00000 = 4305 = 280;0

l})

110001100000000 X 29

1111000
X 24
1010000 X 23

1.01000‘) 1111000 =
1.100000

1010000) 1111000.000000
1010000

101000
101000

Exponent: 4 — 3 =1

Result: 1.100000 X 2

Normalized result: .1100000 x 22
normalized fraction

normalized exponent

Move the binary point two places to the right.
11.00000 = 35 = 30

C HAPT
ALAN

) §

ER 3

DATA FORMATS

3.1
INTRODUCTION
The FPF11 requires its input data (operands) to be formatted in one of
four ways: short-integer format
(I), long-integer format (L), single-precision format (F), and double-precision
format (D).
Data output from the FPF11 is also formatted, taking the form of:
e

FPFI1 status information and FPF11 exception information required
by the CPU, or

Data sent to memory (via the CPU) in I, L, F, or D format.

This chapter describes the FPF11 data formats mentioned above. (It
1s assumed you are familiar with
2’s complement notation.)

3.2
FPF11 INTEGER FORMATS: SHORT AND LONG
The short-integer format (I) is 16 bits long, the long-integer format (L)

32 bits long. Data words (operands) in integer format are represented in 2’s complement notation. In
the I and L formats the most
significant bit of the data word is the sign bit. Figure 3-1 shows the integers
5 and —5 in the [ and L
formats. Figure 3-2 illustrates the formats in which integers are arranged
in memory. Integers sent to
memory must be in one of the formats shown.

Integers received by the FPF11 are arranged and manipulated according
to the type of instruction
being executed. Refer to Chapter 4, Paragraphs 4.3.11 and 4.3.12 for descriptio
ns of the ways in which
incoming integers are manipulated during the load exponent and
load convert integer-to-floating instructions, respectively.

3.3
FPF11 FLOATING-POINT FORMATS: SINGLE- AND DOUBLE
-PRECISION
The single-precision format (F) is 32 bits long, the double-precision
format (D) 64 bits long. Figure 3-2
shows that the most significant bit is the sign of the fraction (and
the floating-point number being represented). The next 8 bits contain the value of the exponent, expresse
d in excess 200 notation (see Paragraph 3.3.1.2). The remaining bits (23 for single-precision, 55 for
double-precision) contain the fraction.
The fraction and its associated sign bit are expressed in sign and
magnitude notation (see Paragraph
3.3.1.1).

3-1

INTEGER =5

.
SHORT

INTEGER (1)

WORD 1

SIGN BIT

LONG

INTEGER (L)

—

WORD 2

WORD 1

((

(

| R

(¢

— ——— ———— — —— — =

—— SIGNBIT —— —— ——

INTEGER =-b

WORD 1

[
15

SHORT

INTEGER (1)

SIGN BIT

WORD 2

WORD 1

—
LONG
INTEGER (L)

{(

(

{ (

(

IR
SIGN BIT

MR-4273

Figure 3-1

[

SINGLE-PRECISION

MEMORY
WORD 1
A

31
S

FLOATING-POINT (F)

FORMAT

l
I

63 62

(D} | S
FLOATING-POINT
0
FORMAT

EXP

22 ({

“

EXP

|1 \ | S

]

L {(

IRE

—A

LR DL
S

))4

48 47

L R
L

\
1 L

32 31

MEMORY
WORD 3

((

ot
1 T\

—

)

—

——

2
MEMORY WORD

55 54

({

FRACTION

MEMORY
WORD 2

G O

i
MEMORY
WORD 1

‘e

DOUBLE-PRECISION

Integer Formats

MEMORY
WORD 4
_AL

16 15

((

T
]

|S€|

]
_J

FRACTION

S =SIGN

EXP = EXPONENT IN EXCESS 200 NOTATION (REFER TO PARAGRAPH 3.3.1.2)
FRACTION = 23- OR 55-BiT FRACTION iN SIGN AND MAGN!TUDE FORMAT

Floating-Point Data Formats in Memory

Figure 3-2

MR 4270

3.3.1

FPF1

Figure 3-3 illustrates the formats in which floating-point numbers are arranged in memory. Floatingpoint numbers sent to memory must be in one of the formats shown. Floating-point numbers received by

the FPF11 are arranged as illustrated in Figure 3-4.

The sign bit, exponent bits, and fraction bits in an FPF11 data word have the same values as their
corresponding data word in memory. Note, however, that the FPF11 data word has more bits than its
counterpart in memory. This is so because the FPF11 has provision for generating an overflow bit, a
“hidden” bit.

SINGLE PRECISION

15 14
MEMORY | |

INITIALLY LOADED

INTO FPF11

]

EXP

6362

—
—

/ — —

56 55_—~"

——
P

4039

FRAC[TION

FRACTION
15
0
]

o
]

/\ —_

—— —

= — —_

zEROES

— ~ — 8.

|s]

EXP

—

J,
)

FPF11 WORD

IN WORKING AREA

63 62\61

| |

39|38

FRACTION

]
0

ZEROES

]

OVERFLOW BIT

(EXP=0, Bi

HIDDEN BIT ——

MR-4267

a. Single-Precision Format

1514

mewory [s] exe | | ¢

L 7‘\ — \/ 4 ~
7\<— — ~L

637 62

INITIALLY LOADED [T~
INTO FPF11

FRACTION

56 , 56

s|
]

FPF11 WORD

63 e2ler

N woRKING AREA L ||

}

_ 7

40397 " 24237 §T.65~— __0

FRACTION

Exp

/1]

F EXP |

Sl ZEROJ

OVERFLOW BIT

—
HIDDEN BIT

(EXP=0, BIT 62=1)
MR-4268

b. Double-Precision Format

Figure 3-3

Floating-Point Data Words in Memory

3-3

SIGN j

EXPONENT

MEMORY

FRACTION

0|0

NUMBER 32 REPRESENTED
IN SIGN AND MAGNITUDE

FORMAT (NUMBER ASSUMED

NORMALIZED)

SIGN
FPF11 | o
S

1]o0|olo]lo|l1|1]o0
7

3|2

o|1|/ofolo|o|o]|o]o

EXPONENT

ADDITIONAL

OPERANDS

210

FRACTION

HIDDEN

EXPONENT = 206 — 200 = 6 = 2°

BIT

FRACTION = 1/2 (INSERTION OF HIDDEN BIT)

FLOATING POINT NUMBER =2° X 1/2=32

SIGN _i

EXPONENT

FRACTION

—

MEMORY

NUMBER 7/16 REPRESENTED
IN SIGN AND MAGNITUDE

6|5

3|2

‘

63 62 61 60 59 58 57 56 55
J

——

FORMAT (NUMBER ASSUMED

NORMALIZED)

————
) ——

AgF'?E';fNNS‘SL

== =
J

EXPONENT

FRACTION
HIDDEN

EXPONENT= 177
— 200 = - 1= 2"

BIT

FRACTION = 1/2+ 1/4+ 1/8
= 7/8 (INSERTION OF HIDDEN BIT)

FLOATING POINT NUMBER =2" X 7/8=7/16
MR-4276

Figure 3-4

Interpretation of Floating-Point Numbers

7
_

ol1]1]1]lo]lolo]lo]o

HERIEEEEEEERERE

FPF11

SIGN

A fraction, with its associated sign bit, hidden bit, and overflow bit.

An exponent.

3.3.i.1 Fioating-Point Fraction — The fraction is expressed in sign and magnitude notation. The following simple example illustrates the idea behind this method of notation.
Integer

2’s Complement

Notation

Sign and Magnitude Notation

OoRuto

sign bit

HIHO

000010

\ magnitude

100010

sign bit

\magnitude

Only a change of sign bit is required to change the sign of a number in sign and magnitude notation.
Note that a positive number is the same in both notations.
Unnormalized floating-point fractions have a range of approximately 0 through 2, as shown in Figure 35. The FPF11, however, normalizes all unnormalized fractions. That is, the fractions are adjusted so
that there is a 0 to the left of the binary point (bit 63) and a | to the right of the binary noint (bit 62),
Thus, normalized fractions range in magnitude from 0.1000 to 0.1111 (1/2 to approximately 1).
dian

~aAis

)

]

iiiv

SMALLEST

NONZERONUMBER |

63
LARGEST

NONZERO NUMBER |

{
}

{

|APPROXIMATELY
0

1
.{

| 1

| APPROXIMATELY
2

{

|
MR-4277

Figure 3-5

Unnormalized Floating-Point Fraction

The fraction overflow bit (bit 63) is set during certain arithmetic operations. For example, during addition certain sums will produce an overflow such as 0.1000... 4+ 0.100... , which yields 1.000... . This
result must be normalized, so the FPF11 right-shifts the fraction one place and increases the exponent
by one.

Bit 62 is called the hidden bit. Recall that since fractions are normalized by the FPF11, the bit immediately to the right of the binary point (bit 62) is always a 1. This bit is dropped when a fraction is sent to
memory and appended when a fraction is received from memory. This procedure allows one extra bit of
significance in floating-point fraction representation.

3-5

3.3.1.2 Floating-Point Exponent — The 8-bit floating-point exponent is expressed in excess 200 notation. Figure 3-6 illustrates the relationship between exponents in 2’s complement notation and exponents in excess 200 notation. It shows the range of floating-point numbers that can be handled by the
FPF11. For simplicity, a fraction length of only three bits is shown.
2’s Complement

Excess 200

( 1‘77 Most positive exponent

[ 377 Most positive exponent

Positive

Exponents )

Exponents

| 0 Least positive exponent

| 200 Least positive exponent

i 3;77 Least negative exponent

[ 177 Least negative exponent

Negative

Exponents )

Exponents

| 200 Most negative exponent
Figure 3-6

| O Most negative exponent

Floating-Point Exponent Notations

Note that an exponent in excess 200 notation is obtained by simply adding 200 to the exponent in 2’s
complement notation. Thus, 8-bit exponents in excess 200 notation range from 0 to 377 (—200 to
+177). A number with an exponent in excess of —200 is treated by the FPF11 as 0.

The number 0.1, is actually 0.1 X 29, and the exponent is represented as 10,000,000 because 200g
represents an exponent of zero.

3.4 FPF11 PROGRAM STATUS REGISTER
The FPF11 contains a resident program status register that contains the floating-point condition codes
(carry, overflow, zero, and negative) that can be copied into the central processing unit. In other words,
FN, FZ, FV, and FC can be copied into the CPU’s N, Z, V, and C condition codes, respectively. The
program status register also contains three mode bits and additional bits to enable various interrupt
conditions. Figure 3-7 shows the layout of the program status register. Each bit shown in the figure is
described in Table 3-1.

MODE BITS

INTERRUPT ENABLES
14

FER | FID

NOT | NOT

usep | USED

Fluv|

FIU | FIV | FIC

CCNDITION CODES
A

04
NOT

|usep

MR.4278

Figure 3-7

FPF11 Status Register Format

J=U

Bit

Name

This bit indicates an error condition of the FPF11.
!

Function

Pt
et

disabled; normally clear. Primarily a maintenance feature.
13

Not used.

FIUV

Floating interrupt on undefined variable — When this bit is set and a —0 is obtained from memory, an interrupt occurs. If the bit is not set, —0 can be loaded and

Floating interrupt on underflow — When this bit is set, an underfiow condition
causes a floating underflow interrupt. The result of the operation causing the interrupt is correct except for the exponent, which is off by 400g. If this bit is not set
and underflow occurs, the result is set to O.

FIV

Floating interrupt on overflow — When this bit is set, floating overflow causes an
interrupt. The result of the operation causing the interrupt is correct except for
the exponent, which is off by 400g. If this bit is not set, the result of the operation

stored; however, all arithmetic operations treat it as if it were a +0.

is the same; however, no interrupt occurs.
FIC

Floating interrupt on integer conversion error — When this bit is set and the store
convert floating-to-integer instruction causes FC to be set (indicating a conversion
error), an interrupt occurs. When a conversion occurs, the destination register is
cleared and the source register is untouched. When this bit is reset, the result of
the operation is the same; however, no interrupt occurs.

Double-precision mode bit — When set, this bit specifies double-precision format;
when reset, it specifies single-precision format.

Long precision integer mode bit — This bit is employed during conversion between
integer and floating-point format. If set, double-precision 2’s complement integer
format of 32 bits is specified; if reset, single-precision 2’s complement integer format of 16 bits is specified.

Truncate bit — When set, this bit causes the result of any floating-point operation
to be truncated rather than rounded.

FN, FZ,

These bits are the four floating-point condition codes, which can be loaded in the
CPU’s C, V, Z, and N condition codes, respectively. This is accomplished by the
copy floating condition codes (CFCC) instruction. To determine how each instruction affects the condition codes, refer to Chapter 4, Table 4-1.

FV, FC

3.5

PROCESSING OF FLOATING-POINT EXCEPTIONS

Location 244g is the interrupt vector used to handle all floating-point interrupts. A total of six possible
interrupt exceptions can occur; these are encoded in the FPF11 exception code (FEC) register. The
interrupt exception codes represent an offset into a dispatch table, which routes the program to the
correct error handling routine. (The dispatch table is a function of the software.) The FEC for each
exception is briefly described in Table 3-2.

In addition to the FEC register, the CPU contains a 16-bit floating exception address (FEA) register,
which stores the address of the last floating-point instruction that caused a floating-point exception.

Table 3-2

FPF11 Exception Codes

Exception

Code

Definition

Floating op code error — The FPF11 causes an interrupt for an erroneous op code.

Floating divide by zero — Division by zero causes an interrupt if FID is not set.

Floating (or double) integer conversion error.

Floating overflow.

Floating underflow.

Floating undefined variable.

NOTE
The traps for exception codes 6, 10, 12, and 14 can
be enabled in the FPF11 program status register. All
traps are disabled if FID is set.

3-8

CHAPTER 4
FLOATING-POINT INSTRUCTIONS

4.1

FLOATING-POINT ACCUMULATORS

The FPF11 contains six accumulators (ACO-ACS). These accumulators are 64-bit read /write scratchpad memaories
u/}fh
nandagctruntivae
roadouf
LIVO
Vwilll
1IUIIIUd LI uUVLIY
L
IO
L.
.

Eanl—\ arrtirnlatae
Tos

o~
madle
o
ch accumulator is inter pr eted as beiflg
cither 32 or 64
1t

armenta

bits long, depending upon the instruction and the FPF11 status (refer to Chapter 3). If an accumulator
is interpreted as being 64 bits long, 64 bits of data occupy the entire accumulator. If an accumulator is
interpreted as being 32 bits long, 32 bits of data occupy only the leftmost 32 bits of an accumulator, as

shown in Figure 4-1. The remaining bits are irrelevant.

64-BIT ACCUMULATOR

" 32.8IT ACCUMULATOR
Id

0
1

ACCUMULATORS (

MSB

LSB
MR-.4279

Figure 4-1

Floating-Point Accumulators

The floating-point accumulators are used in numeric calculations and interaccumulator data transfers.
Accumulators ACO-AC3 are used for all data transfers between the

FPF11 and the CPU or memory.

4.2
INSTRUCTION FORMATS
An FPF11 instruction must be in one of five formats. These formats are summarized in Figure 4-2. The

2-bit AC field (bits 6 and 7) allows selection of scratch-pad accumulators ACO-AC3 only.

If address mode 0 is specified with formats F1 or F2, bits <2:0> are used to select a floating-point
accumulator. Only accumulators AC5-ACO can be specified in mode 0. If AC6 or AC7 is specified in

bits <2:0> in mode 0, the FPF11 traps when floating-point interrupts are enabled (FID = 0). The
FEC will indicate an illegal op code error (exception code 2). Table 4-1 lists the formats of the FPF11
instructions.

4-1

1
0C=17g

[

1
0OC=17g

i
]

T
AC

]

FOC

]

{
]

T
FOC

}

T
SRC/DST

]

)

SRC/DST

FDST

FOC

FOC
!

T
T
FSRC/FDST

]

ocC = 17g

1
FOC

OC=17g

0C =17g

MR-4269

Figure 4-2

FPF11 Instruction Formats

The fields of the various instruction formats listed in Table 4-1 are interpreted as follows.
Mnemonic

Description

Operation code — All floating-point instructions are designated by a 4-bit op code of 17g.

FOC

Floating operation code — The number of bits in this field varies with the format; the code

is used to specify the actual floating-point operation.

SRC

Source — A 6-bit source field identical to that in PDP-11/23-11/24 instructions.

DST

Destination — A 6-bit destination field identical to that in PDP-11/23-11/24 instructions.

FSRC

Floating source — A 6-bit field used only in format F1. This field is identical to SRC
except in mode 0, when it references a floating-point accumulator rather than a CPU
general-purpose register.

FDST

Floating destination — A 6-bit field used in formats F1 and F2. This field is identical to
DST except in mode 0, when it references a floating-point accumulator instead of 2 CPU

generai-purpose register.
AC

Accumulator — A 2-bit field used in formats F1 and F3 to specify FPF11 scratch-pad

accumulators ACO-AC3.

Table 4-1

Format of

FPFi1 Instructions

Instruction

Format

Instruction

Mnemonics

ABSOLUTE

ABSF FDST
ABSD FDST

Fl1

ADD

ADDF FSRC, AC
ADDD FSRC, AC

CLEAR

CLRF FDST
CLRD FDST

COMPARE

CMPF FSRC, AC
CMPD FSRC, AC

COPY FLOATING CONDITION CODES

CFCC

DIVIDE

DIVF FSRC, AC
DIVD FSRC, AC

LOAD

LDF FSRC, AC

LDD FSRC, AC
F1

LOAD CONVERT

LDCFD FSRC, AC
FDCDF FSRC, AC

LOAD CONVERT INTEGER-TO-FLOATING

LDCIF SRC, AC
LDCID SRC, AC

LDCLF SRC, AC
LDCLD SRC, AC
F3

LOAD EXPONENT

LDEXP SRC, AC

LOAD FPF11’'S PROGRAM STATUS

LDFPS SRC

Fli

MODULO

MODF FSRC, AC
MODD FSRC, AC

MULTIPLY

MULF FSRC, AC

MULD FSRC, AC
F2

NEGATE

NEGF FDST

NEGD FDST
F5

SET DOUBLE MODE

SETD

SET FLOATING MODE

SETF

SET INTEGER MODE

SETI

SET LONG-INTEGER MODE

SETL

4-3

Table 4-1
Instruction

Format

Instruction

Mnemonics

STORE

STF AC, FDST

STORE CONVERT

STCFD AC, FDST

STORE CONVERT

STCFI AC, DST

4.3

Format of FPF11 Instructions (Cont)

STD AC, FDST

STCDF AC, FDST

FLOATING-TO-INTEGER

STCFL AC, DST

STCDI AC, DST
STCDL AC, DST

STORE EXPONENT

STEXP AC, DST

STORE FPF11’S PROGRAM STATUS

STFPS DST

STORE FPF11°’S STATUS

STST DST

SUBTRACT

SUBF FSRC, AC

TEST

TSTF FDST

SUBD FSRC, AC

TSTD FDST

INSTRUCTION SET

Table 4-2 contains the instruction set of the FPF11. Since some of the symbology may not be familiar, a
brief explanation if it follows. The information in Table 4-2 is expressed in symbolic notation to provide
you with a quick reference to the function of each instruction. The paragraphs following the table supplement its information.

A floating-point flip-flop, designated FD, determines whether single- or double-precision
floating-point format is specified. If the flip-flop is cleared, single-precision is specified and
designated by F. If the flip-flop is set, double-precision is specified and designated by D. Examples are NEGF, NEGD, and SUBD.

NOTE

!\)

Only the assembler or compiler differentiates between NEGF and NEGD or LDCID and LDCLD instructions. The floating-point does not differentiate
between the instructions but depends upon the value
of FD and FL as usually controlled by SETD,
SETF, SETC, and SETI instructions (that is,
LDCID — SETI — SETD — LDCLD).

An integer flip-flop, designated FL, determines whether short-integer or long-integer format
is specified. If the flip-flop is cleared, short-integer format is specified and designated by 1. If
the flip-flop is set, long-integer format is specified and designated by L. Examples are SETI
and SETL.

Several convert instructions use the symbology defined below.

Cirp — Convert long-integer to double-precision floating.
Cpp.iL — Convert double-precision floating to long-integer.

1g or double-floating to single-floating.

Of D,F—
C F.D Ar
-

UPLIM is defined as the largest possible number that can be represented in floating-point
format. This number has an exponent of 377 (in excess 200 notation) and a fraction of all 1s.
Note that the UPLIM depends on the format specified. LOLIM is defined as the smallest
possible number that is not equal to 0. This number has an exponent of 001 and a fraction of
all Os, besides the hidden bit.

The following conventions are used when referring to address locations.
the contents of the location specified by xxxx
(XXXX)
ABS (address) absolute value of (address)
EXP (address) exponent of (address) in excess 200 notation

Some of the octal codes listed are in the form of mathematical expressions. These octal codes
can be calculated as shown in the following examples.
Example 1: LDFPS Instruction

Mode 3, register 7 specified (F4 instruction format).
170100 4+ SRC
SRC field is equal to 37.
Basic op code is 170100.

SRC and basic op code are added to yield 170137,
Example 2: LDF Instruction

AC2, mode 2, register 6 specified (F1 instruction format).
172400 + AC * 100 + FSRC
AC =2

2 *100 = 200
172400 + 200 = 172600

FSRC is equal to 26.

172600 + 26 + 172626

AC v 1 means that the accumulator field (bits 6 and 7 in formats F1 and F3) is logically

ORed with O1.
Example:

Accumulator field = bits 6 and 7 = AC2 = 105, AC v 1 = 11.

4-5

Table 4-2

FPF11 Instruction Set

Mnemonics

Instruction Description

Octal Code

ABSF FDST
ABSD FDST

Absolute
FDST « minus (FDST) if FDST < 0; otherwise FDST « (FDST)
FC «0
FV <0
FZ « 1 if exp (FDST) = 0; otherwise FZ « 0
FN <0

1706004+ FDST
F2 Format

ADDF FSRC, AC
ADDD FSRC, AC

Floating Add
AC « (AC) + (FSRC) if[AC| + (FSRQ)
< LOLIM; otherwise AC « 0
FC«0

172000+ AC*100+FSRC
F1 Format

FV «1if| AC|> UPLIM,; otherwise FV «0

FZ « if (AC) = 0; otherwise FZ « 0
FN « 1 if (AC) < 0; otherwise FN « 0
CLRF FDST
CLRD FDST

Clear

170400+ FDST
F2 Format

FDST « 0

FC <0
FV <0

FZ « 1
FN <0
CMPF FSRC, AC
CMPD FSRC, AC

Floating Compare
FC«<~0
FV <0
FZ « 1 if (FSRC) - (AC) = 0; otherwise

173400+ AC*100+FSRC
F1 Format

FZ «0
FN « 1 if (FSRC) - (AC) < 0; otherwise
FN «0

CFCC

Copy Floating Condition Codes
C «FC
V«FV
Z ~ FZ
N « FN

170000
F5 Format

DIVF FSRC, AC
DIVD FSRC, AC

Floating Divide
AC « (AC)/(FSRC) if | (AC)/(FSRC)|
2 LOLIM; otherwise AC « 0
FC«~0

174400+ AC*100+FSRC
F1 Format

FV
< 1if|AC|> UPLIM; otherwise FV « 0

FZ « 1 if EXP (AC) = 0; otherwise FZ « 0
FN « 1 if (AC) < 0; otherwise FN
0

4-6

Table 4-2

Mnemonics

LDF FSRC, AC

LDD FSRC, AC

LDCDF FSRC, AC
LDCFD FSRC, AC

FPF11 Instruction Set (Cont)

Instruction Description

Octal Code

172400+AC*100+FSRC

Floating Load

F1 Format

AC « (FSRC)
FC«0

FV «0
FZ « 1 if (AC) = 0; otherwise FZ « 0
FN < 1 if (AC) < 0; otherwise FN « 0

Load Convert Double-to-Floating or
Floating-to-Double

AC « Cgp or Cp,r (FSRC)

FC~0

FV < 1if|AC| > UPLIM; otherwise
FV <0
_
FZ ~ 1 if (AC) = 0; otherwise FZ « 0
FN « 1 if (AC) < 0; otherwise FN « 0

177400+AC*100+FSRC

F1 Format

F, D-single-precision to
double-precision floating

D, F-double-precision to
single-precision floating

If the current format is single-precision floating-point (FD = 0), the source is assumed to
be a double-precision number and is converted to single-precision. If the floating-truncate bit is set, the number is truncated;
otherwise, it is rounded. If the current format
is double-precision (FD = 1), the source is assumed to be a single-precision number and
loaded left-justified in the AC. The lower half
of the AC is cleared.
LDCIF SRC, AC
LDCID SRC, AC
LDCLF SRC, AD
LDCLD SRC, AC
LDCIF = Single Integer
to Single Float
LDCID = Single Integer
to Double Float
LDCLF = Long Integer
to Single Float
LDCLD = Long Integer
to Double Float

Load and Convert from Integer to Floating

rp (SRC)
AC « CiL
FC«0
FV <0

FZ « 1 if (AC) = 0; otherwise FZ « 0
FN « 1 if (AC) < 0; otherwise FN « 0
CiL
Fp specifies conversion from a 2’s complement integer with precision I or L to a
floating-point number of precision F or D. If
integer flip-flop IL = 0, a 16-bit integer (I) is
double specified, and if IL = 1, a 32-bit in-

teger (L) is specified. If floating-point flip-flop
FD = 0, a 32-bit floating-point number (F) is
specified, and if FD = 1, a 64-bit floatingpoint number (D) is specified. If a 32-bit integer is specified and addressing mode O or
immediate mode is used, the 16 bits of the
source register are left justified, and the remaining 16 bits are zeroed before the conversion.

4-7

177000+ AC*100+SRC
F3 Format

Table 4-2

FPF11 Instruction Set (Cont)

Mnemonics

Instruction Description

Octal Code

LDEXP SRC, AC

Load Exponent
AC SIGN « (AC SIGN)
AC EXP « (SRC) + 200 only if ABS (SRC)
<177
AC FRACTION « (AC FRACTION)
FC«0
FV « 1 if (SRC) > 177; otherwise FV « 0
FZ « 1 if EXP (AC) = 0; otherwise FZ « 0
FN « 1 if (AC) < 0; otherwise FN « 0

176400+ AC*100+SRC
F3 Format

LDFPS SRC

Load FPF11’s Program Status Word
FPS « (SRC)

170100+SRC
F4 Format

MODF FSRC, AC
MODD FSRC, AC

Floating Modulo
AC v 1 « integer part of (AC)*(FSRC)
AC « fractional part of (AC)*(FSRC)

1714004+AC*100+FSRC
F1 Format

- (AC v 1) if | (AC)*(FSRC)|

2 LOLIM or FIU = 1; otherwise AC « 0
FC «0

FV «1if| AC|> UPLIM; otherwise FV «0

FZ « 1 if (AC) = 0; otherwise FZ « 0
FN « 1 if (AC) < 0; otherwise FN « 0
The product of AC and FSRC is 48 bits in
single-precision floating-point format or 59
bits in double-precision floating-point format.
The integer part of the product
[(AC)*(FSRC)] is found and stored in AC v 1.
The fractional part is then obtained and
stored in AC. Note that multiplication by 10
can be done with zero error, allowing decimal
digits to be stripped off with no loss in precision.

MULF FSRC, AC
MULD FSRC, AC

Floating Multiply
AC «~ (AC)*(FSRC) if | (AC)*(FSRCO) |
2 LOLIM; otherwise AC « 0

171000+ AC*100+FSRC
F1 Format

FC ~0

FV «1if| AC|> UPLIM,; otherwise FV «0

FZ « 1 if (AC) = 0; otherwise FZ « 0
FN « 1 if (AC) < 0; otherwise FN « 0
Negate

FDST « minus (FDST) if EXP (FDST) # 0;

otherwise FDST « 0
FC«0
FV <0
FZ « 1 if if EXP (FDST) = 0; otherwise
FZ <0

FN « 1 if (FDST) < 0; otherwise FN « 0

NEGF FDST
NEGD FDST

170700+ FDST
F2 Format

ahla
auvic

A
=4

LI
1T Y
Frril

Tawcdenzndd
HISUULCLUH

C b
ODOCL

(44
LUl

Mnemonics

Instruction Description

Octal Code

SETD

Set Floating Double Mode
FD « 1

170011
F5 Format

Set Floating Mode
FD <0

F5 Format

Set Integer Mode
FL «0

F5 Format

SETF

SETI

SETL

170001

170002

Set Long-Integer Mode

170012

FL « 1

F5 Format

STF AC, FDST
STD AC, FDST

Floating Store
FDST « (AC)
FC « FC
FV « FV
FZ « FZ
FN « FN

174000+ AC*100+FDST
F1 Format

STCFD AC, FDST
STCDF AC, FDST

Store Convert from Floating-to-Double or
Double-to-Floating

176000+ AC*100+FDST
F1 Format
F, D-single-precision to

FDST « Cg p or Cp g (AC)
FC
0

FV «1if| AC|> UPLIM; otherwise FV « 0
FZ « 1 if (AC) = 0, otherwise FZ « 0
FN « 1 if (AC) < 0; otherwise FN « 0

dnnh]n._.nrnrwa1
nn nn')f._.
VHUIVT
I VWIDIVil
livar

ing
D, F-double-precision to
single-precision floating

The STCFD instruction is the opposite of the
LDCDF instruction; thus, if the current format is single-precision floating-point (FD =
0), the source is assumed to be a single-precision number and is converted to double-precision. If the floating truncate bit is set, the
number is truncated; otherwise, it is rounded.
If the current format is double-precision (FD
= 1), the source is assumed to be double-precision number and loaded left-justified in the
AC. The lower half of the AC is cleared.
STCFI AC, DST
STCFL AC, DST
STCDI AC, DST
STCDL AC, DST

Store Convert from Floating-to-Integer
Destination receives converted AC if the resulting integer number can be represented in
16 bits (short integer) or 32 bits (long integer).
Otherwise, destination is zeroed and C-bit is
set.

4-9

175400+ AC*100+DST
F3 Format

Table 4-2

FPF11 Instruction Set (Cont)

Mnemonics

Instruction Description

STCFI = Single Float to
Single Integer
STCFL = Single Float to
Long Integer
STCDI = Double Float
to Single Integer
STCDL = Double Float
to Long Integer

FV <0
FZ « 1 if (DST) = 0; otherwise FZ « 0
FN « 1 if (DST) < 0; otherwise FN « 0
C<FC
V « FV
Z«~FZ
N « FN

Octal Code

When the conversion is to long integer (32
bits) and address mode 0 or immediate mode
is specified, only the most significant 16 bits
are stored in the destination register.

STEXP AC, DST

Store Exponent
DST «~ AC EXPONENT - 200g

175000+ C*100+DST
F3 Format

FC«0
FV <0
FZ « 1 if (DST) = 0; otherwise FZ « 0
FN « 1 if (DST) < 0; otherwise FN « 0
C «FC
V «FV
Z~FZ
N « FN

STFPS DST

Store FPF11’s Program Status Word
DST « (FPS)

170200+DST
F4 Format

STST DST

Store FPF11’s Status
DST « (FEC)
DST + 2 « (FEA) if not mode 0 or not immediate mode

170300+ DST
F4 Format

Floating Subtract

173000+AC#*100+FSRC
F1 Format

SUBF FSRC, AC
SUBD FSRC, AC

AC « (AC) - (FSRC) if | (AC) - (FSRC)|
2 LOLIM; otherwise AC « 0
FC«0
FV « 1 if AC UPLIM; otherwise FV « 0
FZ « 1 if (AC) = 0; otherwise FZ « 0
FN « 1 if (AC) < 0; otherwise FN « 0

TSTF FDST
TSTD FDST

Test
Floating

FC <0
FV <0

FZ « 1 if EXP (FDST) = 0; otherwise FZ « 0
FN « 1 if (FDST) < 0; otherwise FN « 0

170500+ FDST
F2 Format

4.3.1
Arithmetic Instructions
_
The arithmetic instructions (add, subtract, multiply, divide) require one operand in a source (a floatingpoint accumulator in mode 0, a memory location otherwise) and one operand in a destination accumulator. The instruction is executed by the FPF11 and the result is stored in the destination accumulator.

The compare instruction also requires one operand in a source and one operand in a destination accumulator. However, the two operands remain in their respective locations after the instruction is executed by the FPF11, and there is no transfer of the result.
4.3.2

Floating Modulo Instruction

The floating modulo (MOD) instruction causes the FPF11 to multiply two floating-point operands, separate the product into integer and fractional parts, and store one or both parts as floating-point num-

bers. The integer portion goes into an odd-numbered accumulator and the fraction goes into an evennumbered accumulator.

The integer portion of the number, when expressed as a floating-point number, contains an exponent
greater than 201 in excess 200 notation. This means the integer has a decimal value of some number
greater than 1 and less than UPLIM, where UPLIM is the greatest possible number that can be represented by the FPF11.

The fractional portion of the number, when expressed as a floating-point number, contains an exponent
less than or equal to 201 in excess 200 notation. This means the fraction has a value less than | and
greater than LOLIM, where LOLIM is the smallest possible number that can be represented by the
FPF11.
4.3.3

Load Instruction

The load instruction causes the FPF11 (and the CPU, if not in mode 0) to take an operand from a
source and copy it into a destination accumulator. The source is a floating-point accumulator in mode 0,
a memory location otherwise.

4.3.4 Store Instruction
The store instruction causes the FPF11 (and the CPU, if not in mode 0) to take an operand from a
source accumulator and transfer it to a destination. The destination is a floating-point accumulator in
mode 0, a memory location otherwise.
4.3.5

Load Convert Double-to-Floating, Floating-to-Double Instructions

The load convert double-to-floating (LDCDF) instruction causes the FPF11 to assume that the source
specifies a double-precision floating-point number. The FPF11 then converts that number to single-pre-

cision, and places this result in the destination accumulator. If the floating truncate (FT) status bit is
set, the number is truncated. If the FT bit is not set, the number is rounded by adding a 1 to the singleprecision segment. The MSB of the double-precision segment is a 1 depending on the prior conditions
set up the the FD bit (see Figure 4-3). If the MSB of the double-precision segment is 0, the singleprecision word remains unchanged after rounding.

63 62

33 32

SINGLE-PYRECISION

DOUBLE-PRECISION

SEGMENT

SEGMENT
MR-4280

FPS

[S—

Double-to-Single-Precision Rounding

——

Figure 4-3

The load convert floating-to-double (LDCFD) instruction causes the FPF11 to assume that the source
specifies a single-precmon number The FPF11 then converts that number to double-precision by ap-

Note that for both load convert instructions, the number to be converted is originally in the source (a
floating-point accumulator in mode 0, a memory location otherwise) and is transferred to the destination accumuiator after conversion.

4.3.6

Store Convert Double-to-Floating, Floating-to-Double Instructions

The store convert double-to-floating (STCDF) instruction causes the FPF11 to convert a double-precision number located in the source accumulator into a single-precision number. The FPF11 then transfers this result to the specified destination. If the floating truncate bit (FT) is set, the floating-point
number is truncated; if the FT bit is not set, the number is rounded. If the MSB (bit 31) of the doubleprecision segment of the word is a 1, a 1 is added to the single-precision segment of the word. This
depends on the prior conditions set up by the FD bit (see Figure 4-3); otherwise, the single-precision
segment remains unchanged.
The store convert floating-to-double (STCFD) instruction causes the FPF11 to convert a single-precision number located in the source accumulator into a double-precision number. The FPF11 then transfers this result to the specified destination. The single-to-double precision is obtained by appending the
number of Os equivalent to the double-precision segment of the word (see Figure 4-4).
63

((

]

L {1
3}

]

{(

{4
)i

ALL Os

(1
1}
A

LIS

00
B

ALL Os
L
(1
BER

SINGLE-PRECISION

DOUBLE-PRECISION

SEGMENT

MR 4270

Figure 4-4

Single-to-Double-Precision Appending

Note that for both store convert instructions, the number to be converted is originally in the source
accumulator and is transferred to the destination (a floating-point accumulator in mode 0, a memory
location otherwise) after conversion.
4.3.7 Clear Instruction
The clear instruction causes the FPF11 (in mode 0) to clear a floating-point number by setting all bits
to 0.

4.3.8

Test Instruction

The test instruction causes the FPFI1 (in mode 0) to test the sign and exponent of a floating-point
number and update the FPF11 status accordingly. The number tested is obtained from the destination
(a floating-point accumulator in mode 0,

a memory location otherwise). The FC and FV bits are

cleared; the FN bit is set only if the destination is negative. The FZ bit is set only if the exponent ofthe
destination is 0. If the FIUV status bit is set, a trap occurs (after the test instruction is executed) when

a —O0 is encountered.
4.3.9 Absolute Instruction
The absolute instruction causes the FPF11 (in mode 0) to take the absolute value of a floating-point
number by forcing its sign bit to 0. If mode O is specified, the sign of the number in the floating-point

destination accumulator is forced to 0. The exponent of the number is tested, and if it is 0, Os are written into the accumulator. If the exponent is not 0, the accumulator is unaffected.

4-12

If mode O is not specified, the sign bit of the specified data word in memory is zeroed. This word is then
transferred from memory to a floating-point accumulator. The exponent of this word is tested, and if it

is 0, the entire data word is zeroed and transferred back to memory. If the exponent is not 0, the original fraction and exponent are restored to memory.

Absolute and negate instructions are the only instructions that can read and write a memory location.

4.3.10 Negate Instruction
The negate instruction causes the FPF11 (in mode 0) to complement the sign of an operand. If mode 0
is specified, the sign of the number in the floating-point destination accumulator is complemented. The
exponent of the number is tested, and if it is 0, Os are written into the accumulator. If the exponent is
not 0, the accumulator is unaffected.

If mode 0 is not specified, the sign bit of the specified data word in memory is complemented. This
word is then transferred from memory to a floating-point accumulator. The exponent of this word is
tested, and if it is O, the entire data word is zeroed and transferred back to memory. If the exponent is
not 0, the original fraction and exponent are restored to memory.
4.3.11

Load Exponent Instruction

The load exponent instruction causes the FPF11 to load an exponent from the source (a floating-point
accumulator in mode 0, a memory location otherwise) into the exponent field of the destination accumulator. In order to do this the 16-bit, 2’s complement exponent from the source must be converted (by

the FPF11) to an 8-bit number in excess 200 notation. This process is further described below.
Assume that the 16-bit, 2°’s complement exponent is coming from memory. The possible legal range of

16-bit numbers in memory is 000000g to 177777g. On the other hand, there are two possible legal
ranges of exponents in the FPF11.
1.

Positive exponents (0g—177g) — When 200g is added to any of these numbers, the sum stays

within the legal 8-bit exponent range (that is, from 200g to 377g).
2.

Negative exponents (177601g—1777773) — When 200g is added to any of these numbers, the
sum stays within the legal 8-bit exponent range (that is, from 1g to 177g).

Any number from memory outside these ranges is illegal and will result in either an overflow or an

underflow trap condition.
Notice that all legal positive exponents coming from memory have something in common: their nine
high-order bits are Os. Similarly, all legal negative exponents from memory have their nine high-order
bits equal to 1. Therefore, to detect a legal exponent, only the nine high-order bits need be examined for
all 1s or all Os.
Example 1: LDEXP 000034
0
Exponent of 34
200

00000000

00011100
10000000

10011100
2

Each of the nine high-order bits is 0, so this is a legal positive exponent. The number 234 is sent to
the 8-bit exponent field of the specified accumulator.

Example 2: LDEXP 201
)

Exponent of 201
200

00000000

10000001

00000001

10000000

overflow

This is an illegal positive exponent. Notice that an overflow occurs when 200 is added to the
exponent.

Example 3: LDEXP 100200
2

Exponent of 100200
200

10000000

00000000

10000000

underflow

This is an illegal negative exponent. Notice that when 200 is added to the exponent, a result is
produced that is more negative than can be expressed by the 8-bit exponent field. Thus, an underflow occurs.

Example 4: Special Case — Exponent of 0: LDEXP 177600

Exponent of 177600
+

11111111

10000000

00000000

This is the one case where the nine high-order bits are all equal, but the exponent is illegal. This is
so because 177600 represents an exponent of 0. This exponent causes an underflow condition to
exist; that is, it is treated as an illegal negative exponent.

4.3.12 Load Convert Integer-to-Floating Instruction
The load convert integer instruction takes a 2’s complement integer from memory and converts it to a
floating-point number in sign and magnitude format. If short-integer mode is specified, the number
from memory is 16 bits and is converted to a 24-bit fraction (single-precision) or a 56-bit fraction
(double-precision), depending on whether floating- or double-precision mode is specified. If long-integer
mode is specified, the number from memory is 32 bits and is converted to a single- or double-precision
number, depending on whether floating- or double-precision mode is specified. The integer is loaded
into bits <<55:40> if short-integer mode is specified or into bits <<55:24> if long-integer mode is specified. It is then left-shifted eight places so that bit 55 is transferred to bit 63 (see Figure 4-5).

The integer is then assigned an exponent of 217g in short-integer mode. This is the result of adding 200g

to 17g (since the exponent is expressed in excess 200 notation), which represents 15;¢ shifts. This num-

ber of shifts is the maximum number required to normalize a number. If long-integer mode is specified,
the integer is assigned an exponent of 237g, which represents 311¢ shifts.

4-14

63 62 61

60 59 58 57 56 55 54 53 52 51

50 49 48 47 46 45 44 43 42 41

0fo0lojojojofojojr|1j1]1|1jojof1|1}1]1]1]lo]|o0|0]1

MR-4271

Figure 4-5

Shifting an Integer Left Eight Places

The FPF11 tests the 2’s complement integer by examining if bit 63 is a positive or negative number. If
it is positive, the number is normalized by left-shifting until bit 63 becomes a 1. If bit 63 is 1 (negative
number), the integer is negative, the sign bit is set, the number is 2’s complemented, and then normal-

ized.

To normalize a number, bit 63 (MSB) of the fraction must be equal to 0 and bit 62 must be made equal

to 1. To do this, the integer is shifted the required number of places to the left and the exponent value is
decreased by the number of places shifted (see Figure 4-6).

63 62

60 59 58

57 56

55 54 53 52

50 49 48 47 46 45 44 43 42 41

0.]0jofjojojolofo|o|o|loflojo]ojo]1|ofjo

f{o]lololo

0|C

|
MR.4272

Figure 4-6

EXP =

2lg

Example of a Normalized Integer

—17g8

Shift integer 15 places to the left to normalize it.
Bit 59 = 0, bit 58
= 1.

200g

Decrease the exponent by 15;¢, which equals 17g.

Loading a long integer with an FED = 0 and more than 24 significant digits causes the less significant
digits to be truncated (with some loss of accuracy).

4.3.13 Store Exponent Instruction
The store exponent (STEXP) instruction causes the CPU to access a floating-point number in the
FPFI1, extract the 8-bit exponent field from this number, and subtract a constant of 200 (since the

exponent is expressed in excess 200 notation). The exponent is then stored in the destination as a 16-bit,
2’s complement, right-justified number with the sign of the exponent (bit 07) extended through the

eight high-order bits.

The legal range of exponents is 0 to 377g, expressed in excess 200 notation. This means that the number

FAN

stored ranges from —200 to 177 after the constant of 200 has been subtracted. The subtraction of 200
is accomplished by taking the 2’s complement of 200 and adding it to the exponent field.

Two examples that illustrate the process follow. One uses an exponent greater than 200, the other an
exponent less than 200.

Example 1: Exponent = 207

(See Figure 4-7.)

Exponent of 207
2’s complement of 200

10000111
+10000000

Result = 7¢

00000111

sign bit /

EXPONENT (8 BITS)

NUMBER IN FPF11
FLOATING-POINT

— A

o | o

olofo

F?ACT'OI

]

SIGN EXTENSION

EXPONENT

TRANSFERRED

o | o

TO MEMORY

(OR ACCUMULATOR)

\ BIT 7 ISEXTENDED TO

THE 8 HIGH-ORDER BITS.
MR.4281

(See Figure 4-8.)

Example 2: Exponent = 42

00100010

Exponent of 42

+10000000

2’s complement of 200

10100010

Result = -42

sign bit

EXPONENT (8 BITS}

FLOATING-POINT

NUMBER IN FPF11

FIRACTICIN\J

SIGN EXTENSION

EXPONENT

TRANSFERRED

TO MEMORY

(OR ACCUMULATOR)

BIT 7 ISEXTENDED TO

THE 8 HIGH-ORDER BITS.
MR 4282

Figure 4-8

Store Exponent (Example 2)

4-16

4.3.14

Store Convert Floating-to-Integer Instruction

The store convert floating-to-integer instruction causes the CPU to take a floating-point number and
convert it into an integer for transfer to a destination. The four classes of this instruction are as follows.

STCFI - Convert a single-precision, 24-bit fraction to a 16-bit integer (short-integer mode).

STCFL - Convert a single-precision, 24-bit fraction to a 32-bit integer (long-integer mode).

STCDI - Convert a double-precision, 56-bit fraction to a 16-bit integer (short-integer mode).

STCDL - Convert a double-precision, 56-bit fraction to a 32-bit integer (long-integer mode).

The (normalized) floating-point number to be converted is transferred to the floating-point processor
(FPP). The FPP works with the sign bit and either of the following.

The 15 MSBs of the fraction for floating-to-integer and double-to-floating conversion.

The 31 MSBs of the fraction for double-to-long conversion.

The entire fraction for floating-to-long conversion.

The FPP subtracts 201 from the exponent to determine if the floating-point number is a fraction. If the
result of the subtraction is negative, the exponent is less than 201, and the absolute value of the floating-point number is less than 1. When converted to an integer, the value of this number is 0; a conversion error occurs, the FZ bit is set, and Os are sent to the destination. If the result of the subtraction
is positive (or 0), the exponent is greater than (or equal to) 201, and the floating-point number can be
converted to a nonzero integer (see Figure 4-9).

+ ' sl

BEFOREl

SHIFTING

AFTER

smrrinel
13 PLACES

olo|lololololo]ololojo]o|o]o

lolololololojololojofolo]1|ol]o

;

MSB
MR-4283

Figure 4-9

Example of a Store Convert Integer

The FPP makes a second test to determine if the floating-point number to be converted is within the
range of numbers that can be represented by a 16-bit integer (1 format) or 32-bit integer (L format).
Consider the range of integers that can be represented in I and L formats and their floating-point equivalents. Refer to Table 4-3.

Table 4-3

Most Positive

1 and 1. Formats and Their Floating-Point Equivalents

I Format
(16 bits)

Floating-point
Equivalent

L Format
(32 bits)

077777

+.1111... x 213

17777777777 | +.1111... x 231

000001

+.100... x 2!

00000000001

177777

—. 1111 x 216 | 37777777777

100000

—.1000... X 216 | 20000000000 | —.100... x 232

Integer

Least Positive

Integer

Least Negative
Integer

Most Negative
Integer

Floating-point
Equivalent

| 4.100... x 2!

| —.1111... X 232

NOTE: MSB of integer = sign of integer.

Thus, the exponent of a positive floating-point number to be converted must be less than 169 (220 in
excess 200 notation) to convert to I format, or 32, (240 in excess 200 notation) to convert to L format.

The exponent of a negative number to be converted must be less than or equal to 16 or 329 to convert
to I or L format, respectively.
The FPP tests whether the floating-point number to be converted is within the range of integers that
can be represented in I or L format by subtracting a constant of 20g (for short integers) or 40g (for long
integers) from the result of the first test. (Result of first test = biased exponent — 2013 — unbiased
exponent — 1.} If the result of the subtraction is positive or 0, the floating-point number is too large to

be represented as an integer; a conversion error occurs and Os are sent to the destination. If the result of
the subtraction is a negative number other than — 1, the floating-point number can be represented as an
integer without causing an overflow condition. If the result of the subtraction is — 1, the exponent of the
iy

floating-point number is either 220 (for short integers) or 240 (for long integers), and conversion proceeds. However, the floating-point number is within range only if it is negative and its fraction is .100...
(that 1s, if it is the most negative integer; see Table 4-3 above). If, in this case, the number is not the
most negative integer, it will be detected by a third conversion error test after conversion (see below).

To convert the fraction to an integer, the FPP shifts it right a number of places as specified by the
following algorithms.

Short integer:
Number of right shifts = 20g 4+ 201g — biased exponent — 1
Long integer:
Number of right shifts = 40g + 201g — biased exponent — 1

Regardless of the condition of the FT bit, the fractional part of the number is always truncated during
this shifting process.
If the floating-point number is positive, the integer conversion is complete after shifting, and the number is transferred to the appropriate destination. However, if the floating-point number is negative, the
number must be 2’s complemented before it is sent to its destination.

4-18

After conversion, the FPP performs a third test for a conversion error by comparing the MSB of the
(converted) integer with the sign bit of the original (unconverted) number. If the signs are not the same,
a conversion error has occurred and the FPP traps if the FIC bit is set. This test is performed to detect a
floating-point number with an exponent of 220 (for short integer) or 240 (for long integer) that has not
been converted to the most negative integer.

Example 1: Store Convert Floating-to-Integer (STCFI)
Exponent = 203
Sign=10

Fraction (24 bits) = .100000000000000000000000
15 MSBs of fraction = .100000000000000
203 (excess 200) = 2

Integer to be stored = 1/2 X 2 =4

Fraction=1/2

Test 1: Is the number to be converted a fraction?
Exponent:

2033
-201

Since this result is positive, the given floating-point

number is not a fraction and conversion may proceed without error.

Test 2: Is the floating-point number to be converted within range? (We are working with a
positive short integer.)
Result of Test 1:

2
=20

Indicates that the number to be converted is within

-16

Yes

range and can be represented as a 16-bit integer.
No conversion error occurs.

How many right shifts? Use algorithm:

20g + 201g- 203g- 1 = 205 - 33 = 153 = 13y
= 13 right shifts

This example involves a positive number, so conversion is complete after 13 right shifts. If
the number had been negative, the integer would have been 2’s complemented.
Test 3: The MSB of the converted integer and the sign bit of the original floating-point

number are compared. Since they are equal, no conversion error occurs.

Exponent = 240g

Sign=10
31 MSBs of fraction = .1000000000000000000000000000000
Test i: Is the number to be converted a fraction?

Exponent:

240g
-201

373

Since this result is positive, the given floating-point
number is not a fraction, and conversion may pro-

ceed (i.e., no conversion error occurs).

Test 2: Is the floating-point number to be converted within range? (We are working with a
positive iong integer.)
Resuit of Test i:

37
-40
-1

We know the number is out of range by examining

the sign bit (in fact, this number is one greater than
the most positive integer that can be represented).
However, the FPP does not know this yet, and conversion proceeds without error at this point.

How many right shifts? Use algorithm:

40g + 201g-2403-1 =10
= No right shifts

Converted 32-bit integer = 20000000000
Since the number is positive, conversion is now complete (i.e., no need for 2’s complementing).
Test 3: The most significant bit of the converted integer (which is 1) and the sign bit of the

original floating-point number (which is 0) are compared. Since they are not equal, a conversion error occurs, which we predicted in Step 2.

4.3.15
Load FPF11’s Program Status (LDFPS) Instruction
The load FPF11’s program status (LDFPS) instruction causes the FPP to transfer 16 bits from the
location specified by the source to the floating-point status (FPS) register. These 16 bits contain status

information the FPF11 uses to enable and disable interrupts, set and clear mode bits, and set condition
codes. (See Paragraph 3.4.)
4.3.16 Store FPF11’s Program Status (STFPS) Instruction
The store FPF11’s program status (STFPS) instruction causes the FPP to transfer the 16 bits of the
FPS register to the specified destination.
4.3.17 Store FPF11’s Status (STST) Instruction
The store FPF11°s status (STST) instruction causes the FPP to read the contents of the floating exception code (FEC) and floating exception address (FEA) registers when a floating-point exception (error)
occCurs.

4-20

If mode 0 addressing is enabled, only the FEC is sent to the destination accumulator. If mode 0 addressing is not enabled, the FEC is stored in memory, followed by the FEA. In memory, the FEC data
occupies all 16 bits of its memory location, while the FEA data occupies only the lower 4 bits of its

location.

When an error occurs and the interrupt trap in the CPU is enabled, the CPU traps to interrupt vector
244¢. The user should issue the STST instruction to determine the type of error that has occurred.
NOTE
The STST instruction should be used only after an
error has occurred, since in all other cases the instruction contains either irrelevant data or the con-

ditions that occurred after the last error.
4.3.18 Copy Floating Condition Codes (CFCC) Instruction
The copy floating condition codes (CFCC) instruction causes the CPU to copy the four floating condition codes (FC, FZ, FV, FN) into the CPU condition codes (C, Z, V, N).

4.3.19

Set Floating Mode (SETF) Instruction

The set floating mode (SETF) instruction causes the FPP to clear the FD bit (bit 07 of the FPS regis-

ter) and indicate single-precision operation.
4.3.20 Set Double Mode (SETD) Instruction
The set double mode (SETD) instruction causes the FPP to set the FD bit (bit 07 of the FPS register)
and indicate double-precision operation.
4.3.21

Set Integer Mode (SETI) Instruction

The set integer mode (SETI) instruction causes the FPP to clear the IL bit (bit 06 of the FPS) and

indicate that short-integer mode (16 bits) is specified.
4.3.22

Set Long-Integer Mode (SETL) Instruction

The set long-integer mode (SETL) instruction causes the FPP to set the IL bit (bit 06 of the FPS) and
indicate that long-integer mode (32 bits) is specified.
4.4

FPF11 PROGRAMMING EXAMPLES

What follows are two programming examples that use the FPF11 instruction set. In Example 1, A is

added to B, D is subtracted from C, the quantity (A + B) is multiplied by (C — D), the product of this

multiplication is divided by X, and the result is stored. Example 2 calculates DX3? + CX?2 + BX + A,
which involves a 3-pass loop.

Example 1: [(A + B) *(C — D)] * X
SET F
LDF
ADDF
LDF
SUBF
MULF
DIVF
STF

A,ACO

:.LOAD ACO FROM A

B,ACO

:ACO HAS (A + B)

C,ACI

:.LOAD AC1 FROM C

D,ACI
ACI1,ACO
X,ACO
ACO.Y

:ACI HAS (C — D)
:ACO HAS (A + D) * (C — D)
:ACO HAS (A + D) * (C — D)/X
.STORE (A + D) *(C — D)/XINY

4-21

)

()

loop 3

ACO=[DX2+CX +B]*X + A
ACO=DX3+CX2+BX
+ A
F
SET
MOV #3,%0

MOV #D+4,%1

LOOP;

LDF (6)+,ACl
CLRF ACO
ADDF -(4),ACO
MULF AC1,ACO
SOB %0,LOOP
ADDF —(4),ACO
STF ACO.~(6)

4-22

;SET UP LOOP COUNTER
;SET UP POINTER TO COEFFICIENTS
;POP X FROM STACK
;CLEAR OUT ACO
;ADD NEXT COEFFICIENT
;TOPARTIAL RESULT
;:MULTIPLY PARTIAL RESULT BY X
;DO LOOP 3 TIMES
;ADD X TO GET RESULT
:PUSH RESULT ON STACK

CHAPTER 35
FUNCTIONAL DESCRIPTION

5.1

GENERAL

The functions of the FPF11 floating-point processor are presented in this chapter. First examined, in an
overview, is the passing of controls at the interface between the CPU and FPF11. Later a discussion on
the control and data functions within the FPF11 provides a basic understanding of how the FPF11
works.
5.2 OVERVIEW
The CPU contains two internal buses, the microinstruction bus (MIB) and the data/address lines
(DALs) as illustrated in Figure 5-1. The MIB <15:00> is the control bus, which is used to carry the
16-bit CPU microinstructions. The DAL <<15:00> is the data bus, which is used to carry data, addresses and PDP-11 instructions. The FPF11 is connected to these buses by a ribbon cable.

MAIN MEMORY

(

SYSTEM BUS

MIB

TCPU CLK

CPU

RESET H

FPF11

CSEL L

<'r

DAL

>
MR-4286

| P

Figure 5-1

TN 11

MMYIT

FPF11/CPU lInterface

Tha (D] avarntee

PR
B AR NO

~nade hy anc
UAU\.«uL\/O PNP_11
1 171 711 VUUW
U Iwi

t}
LULER lllvlllUl_y
n r) frr\
nnnn
It accomphshes this by executing CPU microinstructions. While the CPUis thus mvolved the FPFII monitors the CPU microinstruction flow at its

MIB interface (see Paragraph 5.3.2). When the FPF11 decodes the microinstructions to be an instruction fetch (IFETCH), it knows the next piece of information on the DAL is a PDP-11 instruction and it
inputs this instruction into its floating-point instruction register (FPIR) in parallel with the CPU. The
CPU uses the next two microcycles to examine the instruction. During this interval, the FPF11 sets up
to process the instruction in case it turns out to be in the floating-point class (contains an op code of
17XXXX).

At the end of the two microcycles, the CPU microinstruction on the MIB tells the FPF11 whether or
not it is in the floating-point class. If it is not, the FPF11 goes back to monitoring the CPU and awaits
the next IFETCH. If it is a floating-point instruction, the CPU passes control to the FPF11, which then
becomes the microinstruction source on the MIB. At this point the FPF11 has control over the CPU.
The FPF11 issues CPU microinstructions to move operands between main memory and the FPF11 as
dictated by the PDP-11 floating-point instruction in the FPIR. The operands are passed on the DAL
data bus.
During those times when no CPU actions are required, the CPU receives a no operation (NOP) microinstruction. This occurs while the FPF11 operates on floating-point data. The FPF11 may run at its own
clock rate while the CPU receives NOPs at the CPU’s clock rate. Resynchronization occurs prior to the
returning of control to the CPU, that is, upon successful completion of a PDP-11 floating-point instruction. Control is passed back to the CPU by entering the CPU’s SERVICE routine. This causes the
FPF11 to return to its monitoring of CPU microinstructions.
If the completion of a floating-point instruction is unsuccessful, control is passed back to the CPU by
entering the CPU’s TRAP HANDLER microroutine. The trap vector associated with floating-point
processor errors (244g) is sent to the CPU on the MIB. The FPF11 then returns to monitoring CPU
microinstructions. The CPU handles the trap as directed by the interrupt service routine at 244g. The
FPF11 stores the error code and address associated with the failing PDP-11 floating-point instruction in
its floating error code (FEC) and floating error address (FEA) registers, respectively. Software may use
this information to recover from the error.
5.3 FPF11 CONTROL AND DATA FLOW DESCRIPTION
Figure 5-2 is a functional diagram of the FPF11. Similar to the CPU, the FPF11 has both a control path
and a data path. The control store outputs form the control path. (The control word is 104 bits wide.)
Data, addresses, and PDP-11 floating-point instructions are passed on the TBus <15:00>, which is the
FPF11 internal bus.
Control functions are performed by the sequencer, the control store, the MIB interface, and the interface control and clock logic. Data handling functions are performed by the DAL interface, TBus resources, and the microprocessor data path.
5.3.1

Microcontroller: Sequencer and Control Store

The sequencer and the control store together form the FPF11 microcontroller, shown in Figure 5-3. The
microcontroller directs all FPF11 activity by conditionally sequencing through the microcode in the
control store.

The sequencer makes the decisions that control microprogram execution. It consists of branch and IR
decode programmable logic arrays (PLAs) and the microprogram counter (MPC) logic. Information
received from the TBus resources, MIB interface, microprocessor data path, interface control and clock

5-2

MICROCONTROLLER
|

FPP I

MIB<15:00>

CLK

MIB

INTERFACE

CONTROL

I >

STORE

MICROPROG 104, |
CONTROLS

2 3
’

MIB INTERFACEl

CONTROL

*mpc<o08:00> 9,

DECODED

{"MiCROINSTRUCTION
4

CPU

AND

|cLock LogGic

SECTOR CLKS 4/

JAM MPC ZERO H

I
44

MPC<08:00>

SEQUENCER

MICROPROCESSOR

DATA PATH

29,

FPP CLK

TCPU CLK _JINTERFACE CONTROL
cseL L

13,

RESET H

TO/FROM

10, DATA PATH BUT CONDITIONS
7/

TBUS RESOURCE
DAL INTERFACE
CONTROL

46 VPATA
Epp

CLK

16,
7

TBUS RESOURCES

FPIR<07:06>,<02:00> 5,
7

DAL<15:00>
DAL

TCPU CLK

INTERFACE

—

TBUS<15:00>

MR-4293

Figure 5-2

FPFI11 Floating-Point Processor, Functional Block Diagram

T
T T T T T T T T T SEQUENCER
SEQUENCER ]

IMICRO»

FROM CONTROL STORE Zgfififié“fs 2/

FROM TBUS RESOURCES

TBUS RESOURCE

v-S

DATA PATH

FROM INTERFACE }

CONTROL AND
CLOCK LOGIC

24, |

SEE

FROM MICROPROCESSOR | | BUT CONDITIONS
FROM TBUS RESOURCES

BRANCH

AND

IRDECODE

#»

I
NAB<07:00>>

plas

NOTE 2

I
FROM MIB INTERFACE

MPC<08:00>

STORE

(CONTROL

WORD)

TO TBUS RESOURCES

104/, TO MICROPROCESSOR

DATA PATH

TO INTERFACE CONTROL

AND CLOCK LOGIC

CSNA<08:00>

SEE NOTE 1

14,

MPC

LOGIC

Jé

L TO MIB INTERFACE

| JAM MPC ZERO H

|
|
|

| 77

TO SEQUENCER

MICROPROGRAM

19,| CONTROL|CONTROLS

I
I

NOTES:

1. BUT CONDITIONS ARE COMPOSED OF

DECODED MICROINSTRUCTIONS, DATA

PATH BUT CONDITIONS, AND OUTPUTS
FROM THE FD/FL REGISTER AND

COUNTER IN THE TBUS RESOURCES.

2. TBUS RESOURCE DATA IS COMPOSED CF

OUTPUTS FROM THE FLOATING-POINT

INSTRUCTION REGISTER, FD/FL REGISTER,

— e

————_—

——

— — -

FLOATING-POINT STATUS REGISTER, THE
STATUS FLAGS REGISTER AND COUNTER.
MR-4287

Figure 5-3

Microcontroller (Sequencer and Control Store), Functional Block Diagram

logic, and bits of the previous control word cause the sequencer to output microaddresses on MPC
<08:00>. These microaddresses are sent to the control store to select microinstructions for FPF11
control and to the MIB interface to select CPU microinstructions.

The sequencer uses four types of data:

Control store next address (CSNA), from the control store. This address gives the sequencer

Branch micro test (BUT) conditions, from the microprocessor data path (see Paragraph
5.3.6), counter (see Paragraph 5.3.5.6), FD/FL register (see Paragraph 5.3.5.2), and MIB
interface (see Paragraph 5.3.2). These signals allow the sequencer to modify the CSNA, this
giving the microcontroller its ability to make decisions based on these BUT conditions. The
BUT conditions are individually controlled by the BUT field of the control word so that vari-

its base microaddress for the next microword.

ous combinations of conditions can be tested.

Next address bits (NABs), from the branch and IR decode PLAs. These bits are similar to
the BUT conditions except that the branch and IR decode PLAs are used to test for classes
of conditions; for example, op code type. Further, they provide more flexibility in modifying
the microaddress to the control store.

JAM MPC ZERO, from the interface control and clock logic. This signal resets the microcode to the CPU monitoring sequence in the event of a CPU RESET or a failure to detect
the presence of a PDP-11 floating-point instruction decode.

word (see
The control store logic is made up of 13 512 X 8-bit ROMs, which make up the control
Figure 5-4 and Table 5-1). In addition, two more ROMs are used to hold the CPU microinstruction.
Thus, the microcontroller directs the execution of the current PDP-11 floating-point instruction.
5.3.2

MIB Interface

The FPF11 uses the MIB interface to either monitor or control the CPU, as shown in Figure 5-5.
ns, this logic
5.3.2.1 Receiving Logic (from the CPU) - While the CPU is executing PDP-11 instructioThis
decoded
IFETCH.
monitors the MIB, waiting to decode the CPU microinstruction associated with
inwhich
ruction,
microinst
microinstruction is sent to the sequencer. This logic also decodes the CPU
dicates the start of a PDP-11 floating-point instruction.

point in5.3.2.2 Transmitting Logic (to the CPU) — While the FPFI11 is executing PDP-11 floatingsequenthe
from
<08:00>
structions, the microinstruction ROMs located here are addressed by MPC
<15:00>
MIB
the
cer. This causes the microinstruction ROMs to output CPU microinstructions on
and makes the CPU available to the FPF11 for use in accessing main memory.

The direction of information flow out of the MIB interface is controlled by the microcontroller (see
Figure 5-3) and timed by the interface control and clock logic (see Figure 5-6).
e Controi and Clock Logic

5.3.3 Interfac
the FPF11
The interface control and clock logic is responsible for maintaining proper timing between
the CPU
provides
logic
This
5-6.)
Figure
and the CPU, for both data (DAL) and control (MIB). (See
(MIB),
line
CSEL
the
on
source
ruction
with the signal that allows the FPF11 to be the CPU microinst
here.
timed
is
g
processin
FPF11
internal
and also receives the RESET line from the CPU. In addition,
5-5

119| 118 l 117 |116l115 I114 l 113 ‘112 111 l 110I109 I108 |107 |106 |105 104
XMIB

XMIB XMIB

CPU CONTROL

XMIB

STORE

CPUCTL FIELD

( ROM E NO

ROM 13

ASSERTEDPOLARITY

|—1

MICRO BIT NO.

103[102

FPF11 CONTROL STORE <

{1011100

(99 | 98 | 97

% [ &

|con

§i

=13

ROM

sv|

o | g

FIELD NAME

ROM 12

{1111

= =

BIT NAME

CON
ROM

CON

ROM

“1a
e

vfr

| 96 ] 95 [ 94

CON

ROM

ROM 9

|92

HOT

RATE | RATE

{90

{89

FPS1

FPS2

RATE

CONROM

|91

1lo]lololoiololololo

|[DALD |

HOT

=HOT
o0

|88

87|85

|85|84]|83

FPIR | CNTR|CON

FDFL

ROM

FLAGS

8218180

CNT

DAL

FPS1

FPS2

CLK

FIELD

ROM 10

|93

HOT

ROM 11

111101

TDST

FIELD

-l

() ’L

FIELD

ROM 8

ROM 7

ROM 6

0jojojojojojofojrjtrflojojojof—ftofjr|lvprvfvlalalalapa

falaiapafalriatalalal
T T717Tq

791787717675

|74

73|72

BS5

|71

|70

{69

68|67

|CIN|JLSH

{SNG

ROT

DBL

)66

1-0

INSRT

9-¢

6564|6362

]

ROT|

SEL

1381371363534

B
SEL

)33

SECT
SECT

SEL

gttt

EX
0]l2

_
glg

|32(31)30{29]28|27

SECT

BR2

BRO

SECT

BR3

SEL

BR1

I
BR2

ALU

DST

EX
ALU

ALU
1

EX | FR

SRC

SRC|

DST

SRC
2

DST
o2

|24|23}22{21j20

ILDPC Q|

ENA

CLR

oH
IO

T1 FAST|
cout|

FPS

FR
ALU

ALU

EXCTL———— la— FR

FR
SRC

ALU
1

DST

19181716165

>foN

2
I

[

ADRS
ol2

B
FRCTL——————lg—

ADRS

ADRS
ol2

—le— A

ADRS

——

ROM 1

bl ol

AT AT

[1afl3]12]11|1w0je]|s]7[e6lslalala]i1]o

Z | o

E{s-40
=z

SRC{ADRS | ADRS|ADRS | ADRS

SRC

ROM 2

{2626

BR1

’

DST

ROM 3

SEL

DST

ROM 4

|61[{60|59]|58|57|56|55]54)563]|52|51|50]|a0]a8a7a6]a5]|aal43]|a2|a1]ao0

DST

f———SHIFT LINKAGE————mla——EX

FIELD

DST

ROM 5

TSRC

————‘,

[N63

|NA8 NA7 NA6 NA5 NA4 NA3 NA2 NA1 NAO

CNTRO

o}l1

0|3

»le-A

qn—-SECTOR—-—.n—-————BUM——chUTs’

le-B
PORT

PORT

[—BUT2 —»

FIELD

le—— BUT 1—

le—————BUTO

NEXT ADRSFIELD—————

BUT

FIELD
NOTE:

(ON TBUS BUT CONDITIONS)
TO=Y8

T1=Y9
T5 = Y61
T6 = Y62
MR-4289

Figure 5-4

FPFI11 Control Word

Table 5-1

Control Word Bit Descriptions

Bits

Field

Description

00:08

Next Address

Provides the base address for the next control word.

09:14

BUTO

Enables for branch micro test conditions.

Instruction Hold

Controls the latching of MPC <08:00> into microinstruction

16:18

BUT1

Enables for branch micro test conditions.

Test JENTRY

20:22

BUT2

Enables for branch micro test conditions.

Hold CSEL

Controls the assertion of FPF11 “CSEL” (chip select) to indicate