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· Digital Equipment Corporation
Maynard, Massachusetts

PDP-9
Instruction Manual

KF09A
Automatic Priority Interrupt

DEC-09-ISAA-D

KF09A
AUTOMATIC PRIORITY INTERRUPT
INSTRUCTION MANUAL

digital equipment corporation • maynard. massachusetts

1st Printing June 1968

2 nd Pri nti ng May 1969
3rd Pri nti ng Apri I 1972

The material in this manual is for informational purposes and is subject to change
without notice.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

FLIP CHIP

PDP
FOCAL

DIGITAL

COMPUTER LAB

CONTENTS

CHAPTER 1
INTRODUCTION

Page

1.1

Scope

1-1

1.2

Purpose

1-1

1.3

Related Documents

1-2

2-1

Standard API Channel/Priority Assignments

2-5

2-2

Controls and Indi cators

2-6

2-3

API lOT Instructions

2-6

2-4

SPI Control Word Format

2-8

2-5

ISA Control Word Format

2-9

2-6

Mai ntenance Instructi on Status Word

2-10

4-1

API Module Complement

4-1

CHAPTER 1
INTRODUCTION

1 .1

SCOPE
This manual contains operation and maintenance information for the KF09A Automatic

Priority Interrupt (API) option of the Programmed Data Processor PDP-9, manufactured by Digital Equipment Corporation, Maynard, Massachusetts.

For a complete understanding of the option and its relation-

ship to the basic PDP-9 system, the user should be thoroughly familiar with the contents of the PDP-9
Maintenance Manual, F-97.

1 .2

PURPOSE
The API option extends the PDP-9s capabil ities by providing priority servicing for as many as

28 I/O devices with minimum programming and maximum efficiency. Its priority structure permits high
data rate devices to interrupt the service routines of slower devices with a minimum of system "overhead. II
The option permits the device service routines to enter directly from hardware-generated entry points,
eliminating the need for time-consuming flag searches to identify the device that is causing the interrupt.
The option provides 32 unique channels, or entry points, for the device service routines, and
8 levels of priority. The four higher levels are for fast access to service routines in response to deviceinitiated service requests.

Each of these levels can be multiplexed to handle up to eight devices

assigned an equal priority. The four lower levels are assigned to program-initiated software routines
for transferring control to programs or subroutines on a priority basis. Four of the 32 channels are reserved
for these software levels.
Each device interfaced to the API option specifies (sends) its "trap address II or unique service
routine entry point to the processor when granted an API break by the processor. Core memory locations
408 through 778 are assigned as these entry points. JMS or JMS I instructions contained in these locations
provide linkage to the actual service routines.
Of the 28 hardware channels, 3 are assigned internally to the paper tape reader, real-time
clock, and optional power failure detection system. The API interface logic for these devices is wholly
contained within the I/O wing of the PDP-9.
Each API priority takes precedence over lower API priorities, program interrupts (PI fac i I ity,
basic PDP-9), and the main program. The program segment of highest priority interrupts lower priority
program segments when activated. Above all of these in priority, of course, are the DMA, DCH, and
RTC.
The entire API system may be enabled or disabled by a single lOT instruction. With the
exception of the paper tape reader channel, it is not possible to enable or disable a single channel.

1-1

The more sophisticated I/O devices connected to the API system have the abil ity to enable or disable
themselves.

Simple devices such as the tape reader, tape punch, etc., must be programmed with lOT

clear instructions to clear their flags and thus disconnect, just as they disconnect from the PI facility.

1.3

RELATED DOCUMENTS
In addition to certain documents I isted in Chapter 1 of the PDP-9 Maintenance Manual, the

API is supported by the test tapes and program documents indicated in Table 1-1. Refer to Chapter 4
of this manual for test conditions.

Table 1-1
Related Documents

1 .4

Number

Title

Form

MAINDEC-9A-DOIA-PH

I/O Test (API)

Hardware Read-In (HRI) paper
tape

MAINDEC-9A-DOIA-D

I/O Test (API)

Program description

POWER REQUIREMENTS
The API option needs no source of primary or dc power other than that already supplied with

the basic PDP-9 system. All necessary power is prewired to the option module locations.

1.5

ENGINEERING DRAWING REFERENCES
Throughout this manual all references to API drawings and basic PDP-9 drawings are abbreviated.

Refer to Chapter 5 of the PDP-9 Maintenance Manual for a description of drawing number codes.
Chapter 5 of this option manual contains a set of API drawings and circuit schematics for all
the API modules.

1.6

SPECIFICATIONS
Heat Dissipation

61 BTU/hr

Power Dissipation

0.018 kW

1-2

CHAPTER 2
INSTALLATION AND OPERATION

2.1

INSTALLATION
The API option requires no special installation instructions. Complete installation merely

involves inserting the modules into their assigned module locations in the I/O wing of the PDP-9
(drawing KD14) and ascertaining that the following jumpers are removed from the CP and I/O wings:
API BK RQ from F22C to F22R (drawing KC27)
PRE API SYNC from J10C to J10S (drawing KD16)

2. 1 . 1

Interface Cabling
Communication between the PDP-9 central processor and any external device connected to

an API channel is made through the primary and secondary I/O bus as defined in Section 3.8 of the
PDP-9 Maintenance Manual. The same cabl ing considerations apply. The devices themselves contain
essentially the same interface control logic as that for the DCH devices, including W103 Device
Selectors and W104 Multiplexers.

Each external device interfaced to the API must use a W104 Multiplexer

module or equivalent logic between the device and the I/O bus.
The secondary I/O bus has 12 line connections which are un ique to the API/W104 interface.
These are the API RQ, API GR, and API EN I ines shown on drawing KD2(2) for each of the four hardware priority levels.

Since these control I ines pass through all W104 modules, it is relatively easy to

change a device's assigned priority by disconnecting it from one set of lines and connecting it to another.
Because of cable length restrictions and the time delay encountered in propagating signals through the
multiplexer modules, no more than eight devices should be interfaced to one priority level.
The W104 module establ ishes priority among devices assigned to the same priority level. It
is also used to gate the channel trap address onto the I/O bus (10 ADDR) I ines at the appropriate time.
Devices that do not clear their flags must have the flags cleared by program control (lOT) after API
breaks, i.e., the device flag is cleared in the API routine and not with the W104 1s C LR FLG signal as
might be assumed.
Figure 2-1 is an example of four devices tied to the API. Only the unique API I ines are
shown. In this example, the following relationship exists between device and priority level.
Device

Priority Level

2-1

If all four devices request service simultaneously, they are serviced in the following order:
C, B, D, A. Although Band D are on the same priority level, device B is serviced before device D
because it is closer to the computer on the I/O bus.

DEVICE' A

DEVICE

6 10 ADDR LINES
(AND OTHER
CONTROL SIGNALS)

DEVICE

CONNECT AS
4-

~~:~~E T~RAP
ADDRESS

APIO RO ::::
APIO GR(!)

..J

...J

APIO EN

W104

..-

~M
6
DEV CE

API 1 RQ ::::
API 1 GR(1)
APII

--.

...

API2 RO I'"
API2 GR(!1

-.I

API 2 EN

WI04

6:J'
DE~CE

API3 RO ~
API 3 GR(11
API 3 EN

J
..J

WI04

I
I

.J
J

Wl04

I
I

....
~

~AG
DE~CE

....
~

E1'
DE~ICE

Figure 2-1 Devices on the Automatic Priority Interrupt System

Each W104 module contains six address selection lines (pins AJ, AK, AL, AN, AS, AU).
These lines are normally connected to the 10 ADDR lines of the I/O bus to form the trap address.
For standard API devices, pin AJ is connected to line 12 (40 ) and pins AK-AU form the channel
8
number. In some cases, trap addresses above 778 may be used, although standard PDP-9 peripherals
should be restricted to 408 through 77 . Figure 2-2 shows the possible connections for trap addresses
8
between 10°8 and 137 .
8

2-2

II
Q
I
I

?, 9 9,

CONNECTED'

'~
I

AS' REO,'

6 b 6 6'
I

Wl04

Figure 2-2 Connections for Trap Addresses Between 100 and 137
8
8

If a single device is required to generate a number of different addresses on the basis of a
single flag, the W104 can be used to gate the address from a fl ip-flop register onto the 10 ADDR
lines.

Figure 2-3 is an example of this situation.

10 ADDR

~--------------~v~----------------~
R200 SERIES

FLIP - FLOPS

Figure 2-3 Gating FI ip-Flop Register onto I/O Address Lines

Figure 2-4 is a case of a single device with multiple flags, anyone of which can cause a
trap to a unique address. In this case, the different flags are all tied to the same request line. They
must be individually tested by lOT instructions (I/O SKIP), and therefore must also be tied to the I/O
SKIP line. They are also individually cleared as shown. The flags are also connected to the REQ(l)
line to assure that the REQ flip-flop wi" clear when a" flags are cleared, regardless of whether or
not the API break request is granted. The flag handl ing routi nes must assure that the flags are treated
properly. That is, each flag must be honored, then cleared only after appropriate device servic ing
has been completed.

2-3

FLAG

I---------.---~.

REQ(1)

..J---_ - - - - - - t - - - - - - t > r~~/G~~Dl
BO

I.....-_ _

lOT CLEAR A - - - { ) I - - - - - - - '

Figure 2-4 Single Device with Multiple Flags

Alternatively, a separate W104 module may be used for each flag using the API facility. This
method presents no special problems. The additional flags are treated as separate devices and no special
programming is required in the flag handling routine.

2. 1 .2

Program Interrupt Connections
Each device that interfaces to the API facility mayor may not also connect to the PDP-9s

PI facility. When a device flag is interfaced to both facilHies, the API will have priority over the
PI {no program interrupt will occur after the API has serviced the device}. If the API facility is disabled
by program control, the PI operates normally.

See Figure 3-1 for special PROG INT RQ gating at the

W104 module.

2.1.3

Standard C ha n ne I/Pri ori ty Ass i gnments
Each device interfaced to the API option specifies its "trap address" or the unique entry point

to its service routine. The addresses are tapped from the W104 Multiplexer and are cabled to the I/O
bus connections labeled 10 ADDR 12 through 10 ADDR 17. Core memory locations 40a through 77a
are reserved as the service routine entry points, where trap addresses and channel numbers are related
as follows:
{trap address}a = {channel number)a +40a
Locations 40a through 77 a should contain JMS or JMS 1 instructions to provide linkage to
the actual service routines. JMS I is useful for reaching a routine located in a memory bank other than
the bank currently accessed in extended memory systems.

2-4

Table 2-1 shows the relationship between channel number and trap address, the channel
assignments for standard PDP-9 devices, and the suggested priority levels. The channel number
assignments should remain fixed for software compatibi I ity, but priority levels may be changed at the
user's discretion.

Table 2-1
Standard API Channel/Priority Assignments
Octal
Channel
Number

Device

Software priority

---

DECtape

Option
Number

Priority

Address

TC02

MAGtape

TC59

Drum

RM09

Disk

Paper Tape Reader*

RTC {overflow}*

Power fail

KP09

Parity

MP09

Display {L. P. flag}

34H,339

Card readers

CR01E, CR02A

Line Printer

647

A/D

AF01B

DB99A/DB98A

DB09A

360 Data Li nk

DX34B**
DX35B***

637 Data Phone

DP09A

23-37

Unassigned

*Furnished with basic PDP-9 system
**Local
***Remote

2-5

2.2

OPERATING CONTROLS AND INDICATORS
The API option contains no manual controls or indicators other than those already wired into

the operator's console of the PDP-9. Table 2-2 I ists these controls and indicators.

Table 2-2
Controls and Indicators
Contro 1/1 ndi cator

Function

10 ADDR position displays trap address from I/O bus in 15
least-significant indicator lamps.
binary 1s.

Lighted lamps indicate

API position displays the status of API ENABLE, API 0 RQ
through API 7 RQ, PLO through PL7 from left to right with
indicator lamp 01 unused. Lighted lamps indicate active
status.
PS ACTIVE indicators

2.3

Upper bank indicates status of hardware priority levels 0
through 3 from left to right. Lower bank indicates status of
software priority levels 4 through 7 from left to right. Lighted
lamps indicate active status.

API INSTRUCTIONS
The API logic adds five lOT instructions to the basic PDP-9 repertoire and makes use of the

DBR instruction extant in PI-initiated service routines. Table 2-3 briefly describes these instructions,
and programming considerations for their use follow.

Table 2-3
API lOT Instructions
Octal
Code

Mnemonic

703304

DBK

Debreak. Releases the highest currently active priority level.

703344

DBR

Debreak and restore. Releases the highest currently active priority
level and provides for restoration of the LIN K, EPC, memory extend
mode, and memory protect mode status to the interrupted program.

705501

SPI

Skip on priorities inactive. Tests for the successful raising of an ISAinitiated priority level.

Description

2-6

Table 2-3 (Cont)
API lOT Instructions

Octal
Code

Mnemonic

705512

RPL

Reads API status bits from API logic into the AC.

705504

ISA

Initiate sel ected activity. Requests service at a software priority
level or raises the currently active priority to a higher level. Also
enables or disables the API system.

Descri pti on

2.4

PROGRAMMING CONSIDERATIONS

2.4.1

DB K Instruction
This instruction is used within a currently active API service routine to return the routine to

its normally assigned priority level after the need for its temporary raising (by ISA or CAL) has been
satisfied.

DBK is not normally used to terminate an API service routine because it does not provide for

the restoration of the LIN K, EPC, memory extend mode, and memory protect mode status to the interrupted
program.

2.4.2

DBR Instruction
Like DBK, this instruction returns the currently active API routine to its normally assigned

priority level. Additionally, it primes the PDP-9 system to restore the LIN K, EPC, memory extend mode,
and memory protect mode to the status they occupied at the time of interrupt. The status is stored in core
memory by JMS along with the interrupted program count when the API service routine is entered.

Normally

the next to the last instruction in the service routine, DBR is followed by a JMP I to the interrupted program,
which performs the actual restoration of the program count and the status information. As for all lOT
instructions, another interrupt cannot occur until execution of the subsequent instruction, i. e., JMP I,
is completed.

2.4.3

(DBR used in a PI-initiated service routine has no effect on API status.)

SPI Instruction
This instruction tests for the successful ISA-initiated raising of a priority. The instruction

uses a control word previously placed in the AC (by LAC) to test the priority level of the currently active
API service routine.

In the API logic the control bits are compared with corresponding API status conditions.

The program will skip the next instruction if the corresponding API conditions for the set control bit in
Table 2-4 are true.

2-7

Table 2-4
SPI Control Word Format
AC Bit

2.4.4

API Condition Tested

API ENABLE {1}

01-09

Not used

Priority level 0 inactive {highest}

Priority levelland higher inactive

Priority level 2 and higher inactive

Priority level 3 and higher inactive

Priority level 4 and higher inactive {software}

Priority level 5 and higher inactive {software}

Priority level 6 and higher inactive {software}

Priority level 7 and higher inactive {software}

ISA Instruction
This instruction controls the status of API priorities. It in itiates the activity spec ified by

a control word placed in the AC by a previous LAC instruction. Table 2-5 shows the control word format.
Within lower priority service routines it may become desirable to raise the routine's priority
level so that it can continue without interruption by any higher priority API request.

For example, this

may be necessary because of some calculation within the routine. By issuing the I SA instruction with the
proper bit set into the AC the priority of the service routine is raised.

No instruction in a channel address

is executed. The routine merely continues at the higher priority level. Thus the two priority levels are
currently active to restore the routine to its original priority level, a DBK releases the highest currently
active priority level.
Normally, SPI and ISA are combined {microcoded} as one instruction {705505}. If the SPI
function finds that the currently active API routine is already at the requested level or higher, the ISA
function is ineffective and the next instruction is executed. The program must be written so that no DBK
follows in this case, and so that the routine terminates in a DBR later. If the SPI function finds that the
API routine is not at the requested level or higher, the ISA function raises it to that level, and the next
instruction is skipped.

Here the program is written for a DBK at some intermediate point where the

higher priority level is no longer necessary, and a DBR terminates the routine later. ISA cannot be used
t6 lower the priority of a currently active routine because the logic wi II not recognize the request.

2-8

Table 2-5
ISA Control Word Format
AC Bit

Activity Specified

Enable API (disable if 0)

Maintenance only (paper tape reader priority)

03-05

Not used

Request service at priority level 4 (software)

Request service at priority level 5 (software)

Request service at priority level 6 (software)

Request service at priority level 7 (software)

Raise priority to level 0

Raise priority to level 1

Raise priority to level 2

Raise priority to level 3

Raise priority to level 4

Raise priority to level 5

Raise priority to level 6

Raise priority to level 7

In addition to its normal function, ISA is also used in the API test program to raise the paper
tape reader1s priority to anyone of the levels below.
ISA with AC bits 01, 02
set to:

Raise PTR priority
level to:

Remove PTR from
API system

None of the basic I/O devices furnished with the PDP-9 (reader, punch, teletype, RTC)
are assigned to API priority levels 0 or 1. By issuing an ISA instruction with AC bits 01 and 02 set as
above, the PTR priority level can be raised to 0 or 1 thereby providing a means of checking the API
interface structure for these levels. This function should only be used for checkout and maintenance
purposes. The paper tape reader is permanently assigned to priority level 2 in normal API operations.
When I SA is programmed, note that AC bits 01, 02 at simultaneously asserted levels present an inval id

2-9

and unrecognized condition to the API logic. Therefore, ISA is not normally issued with both bits asserted,
and the LAW instruction should not be used to load the AC with the control word.

(LAW, 76XXXX,

followed by ISA yields this invalid condition.) Actually, the invalid condition has the effect of removing
the paper tape reader from the API system and may be programmed intentionally to allow the reader to
operate with the PI rather than the API fac i I ity.

2.4.5

RPL Instruction
The RPL instruction (705512) is used to read API status bits (Table 2-6) from the API logic into

the AC through the Input Mixer. The status bits can then be viewed in the console REGISTER indicator
by selecting the AC position of the REGISTER DISPLAY switch when the computer is in a stop condition.

Table 2-6
Maintenance Instruction Status Word
Status Bit

2.4.6

Status of

Status Bit

Status of

API ENABLE

API 7 RQ

Not used

PLO

API 0 RQ

PL1

API 1 RQ

PL2

API 2 RQ

PL3

API3 RQ

PL4

API 4 RQ

PL5

API 5 RQ

PL6

API6 RQ

PL7

CAL Instruction with API
The CAL instruction may be used within a currently active API routine to call for a stored

subroutine. In a real-time program environment it is necessary to maintain data input/output flow,
where it is not possible to perform long, complex calculations at priority levels which shut out these
data transfers.

In this case a high-priority hardware input/output routine which recognizes the need

for the complex calculation can call for it with CAL. CAL branches the program segment to core location
00020, where it stores the current program count/status and performs the calculation at location 00021 •
Whenever CAL is used in this manner, it also automatically activates software priority level 4. Thus,
the two priority levels are currently active (the higher priority level of the data transfer routine, and

2-10

the software priority level}.

The higher priority has control, indirectly raising the software level and

shutting out all lower priority API requests. The subroutine continues at the higher priority level.
A DBR at the end of the CAL subroutine releases the highest currently active priority level,
i.e., the hardware level, debreaking back to level 4.
In the case where CAL is used within a lower priority software routine, priority level 4 becomes
the .!2.ighest currently active priority, in which case DBR releases this level and debreaks to the lower
level.
JMP I following DBR in either case should return to the JMS-entered program count rather
than the CAL-entered count.

2.4.7

Dynamic Priority Reallocation
In order to most efficiently service the I/O devices, the hardware provides three distinct methods

for dynam ic priority reallocation.

2.4.7. 1

Device-Dependent - Since channel number and priority level are independent, a device may

be designed to interrupt at anyone of several priority levels without grossly affecting programming. In
a control application the device could raise its priority under program control when the data rate increases,
for example. In this case the device would make use of more than one priority level.

2.4.7.2

Program-Genera~ed Service Requests - The program may generate interrupt requests on any

of the four software priority levels. If the level is below the currently active priority level, the request
will be honored when the higher priority levpls are released. If the level is higher than the currently
active level, the request will be honored immediately. The instruction (JMS) in the software priority
channel will be executed, storing the current program count and entering the new program segment.

2.4.7.3

Programmed Priority Changes - In order for an interruptable program to change parameters

in an interrupt service subroutine, the priority interrupt system is normally turned off while the changes
are effected. Unfortunately, all interrupts are shut out during this time including those that indicate
mach ine errors or are vital to control real time processes. Thus, the API has been designed so that a
program segment may raise its priority only high enough to shut out those devices whose service routines
require changes. The method of raising priority and lowering it requires minimum possible time. By
issuing the ISA instruction with the proper bits set in the accumulator the priority of the currently active
program segment is raised. No instruction in a channel is executed. The program merely continues on
at its higher priority level. To restore the program segment to its original priority level, a DBK instruction is issued.

2-11

For example: a priority 2 routine is entering data in memory locations A though A + 10; but,
based on a calculation made by a priority 6 routine, it becomes necessary to move the data to memory
locations B through B + 20. The changes in the routine at level 2 must be completed, without interruption, once they are started. This is possible by the level 6 program raising itself to level 2 (devices on
the same or lower priority may not interrupt), completing the change, and debreaking back to level 6.
2.5

PROGRAMMING EXAMPLES

2.5. 1

Input Ten Words from A/D Converter
A service routine INAD inputs 10 words to a FORTRAN array for later processing. The core

location of the A/D channel contains a JMS INAD. The basic components of INAD are:
INAD

o
DAC SAVAC

lOT

lOT
LAC SAVAC

lOT
DBR
JMP* INAD

/ENTRY POINT
/SAVE AC
/READ A/D BUFFER
/STORE IN ARRAY
/TEST FOR LAST WORD - IF YES, INITIATE
/SOFTWARE INTERRUPT TO ACCESS DATA
/FORMATTING ROUTINE
/ELSE, START NEXT CONVERSION
/RESTORE AC
/CLEAR DEVICE FLAG
/DEBREAK AND RESTORE
/RETURN

The program segment to start the conversion would look as follows:

lOT

/INITIALIZE INAD
/SELECT CONVERTER FOR FIRST CONVERSION
/CONTINUE WITH PROGRAM

If INAD were active, one could instruct it to input an additional 10 words with the following segment:

LAC (
ISA

DBK

2.5.2

/CONTROL WORD
/RAISE PRIORITY TO
/LOC K OUT INAD
/CHANGE INAD PARAMETERS
/RESTORE PRIORITY TO ORIGINAL LEVEL

Simulation of Hardware Interrupt
A hardware interrupt may be simulated by:
LAC ( )
ISA
JMS INAD

/CONTROL WORD
/RAISE TO HARDWARE PRIORITY
/ENTER IN AD

2-12

2.5.3

Use of Software Leve Is
An organizational example of a program using five levels may be as follows:

2.5.4

Interrupt level 0

Highest priority alarm conditions, computer or
processor malfunctions.

Interrupt level 1

Control process A/D - D/A, sense and control
input/output routines.

Interrupt level 3

Teletype I/O routines for operator interface,
operator can query or demand changes as required.

Interrupt level 4
{software}

FORTRAN subroutines to calculate process control
input/output data. Direct digital control routines.

Main Program

Lowest priority, operator interface programming,
requested readout, etc.

Queueing
High priority/high data rate/short access routines cannot perform complex calculations based

on unusual conditions without holding off further data inputs. To perform the calculations, the high
priority program segment must initiate a lower priority {interruptable} segment to perform the calculation.
Since, in general, many data handling routines wi" be requesting calculations, there will be a queue
of calculation jobs waiting to be performed at the software level.

Each data handling routine must add

its job to the appropriate queue and issue an interrupt request {ISA instruction} at the corresponding
software priority level.

2-13

CHAPTER 3
PRINCIPLES OF OPERATION

This chapter describes the API option in terms of its instruction repertoire and the logic
necessary to implement those instructions. The discussions include references to the logic drawings in
Chapter 5 and to pertinent drawings in the PDP-9 Maintenance Manual.

3. 1

SYSTEM DESCRIPTION
The heart of the API system is the W104 Multiplexer, Figure 3-1. External device and I/O

bus interfacing can be correlated with the simple installation diagram shown in Figure 2-1. As with
DCH/RTC program breaks the initiation of an API break depends first on the issuance of 10 SYNC pulses
in the I/O control logic of the PDP-9. 10 SYNC pulses occur on computer ClK POS pulses only when
no AM SYNC (DMA) signal or lOT instruction is currently in progress and the API SYNC flip-flop is set.
Assuming that an lOT instruction (ISA) has initially enabled the system, and that other lOT
instructions have later enabled specific, fixed-priority devices as required, the currently active program
segment continues. When the API is initially enabled, PRE API SYNC or Pl7EN (some API priority
level set) sends a PI DISABLE signal to the I/O control logic, deferring all interrupt requests from the
PI facility while the API is handling a request.
When a device II ready II flag sets, it conditions the DCD input gate to the API REQ flip-flop,
Figure 3-1. The next permissible 10 SYNC pulse from the I/O control logic sets the API REQ flip-flop
if allowed by API X EN IN. In Figure 3-1, the negative API X EN IN level from the API logic (API 0,
1,2,3 EN, Figure 2-1) goes to the first of eight possible W104s on the same priority level. This level
remains negative at API X EN OUT and goes to API X EN IN of the next W104 if the API REQ flip-flop
is in the reset state. If the API REQ fl ip-flop becomes set, its API X EN OUT leve I goes to ground and
appears as API X EN IN at the next W104, holding its API REQ flip-flop and all others in the reset state.
Thus the W104 closest to the I/O bus establishes priority among devices issuing requests on the same
priority level.
A set API REQ flip-flop issues an API X RQ to the API logic via the I/O bus, Figure 2-1,
where X denotes the 0, 1, 2, 3 priority level. The API logic determines if the API X RQ is of a higher
priority than that of any simultaneous and/or already waiting requests from devices on other priority
levels. If so, API X RQ activates the API synchronization logic. The synchronization logic examines
the qua I ity and conditions of the currently active program segment, and eventually sets an API SYNC
fl ip-flop and issues an API BK RQ/BK SYNC signal to the centra I processor as soon as conditions permit.
Such conditions as a current DCH/RTC program segment or an lOT instruction in any program segment
delay the API BK RQ/BK SYNC until the 10 ClK POS following the last cycle of the last consecutive
DCH/RTC program segment or lOT instruction.
3-1

PROG
INT - - - - - - - - - ,
RQ

LDGIC NOT

INCWDED

r-C

.. WlO4

CONNECT AS NEEDED

__- - - FLAG ( 1)

0 0 - - - 0 1 0 ADOR 12
~H
0

.:>

10 AOIlO IT

~-----.....~ ENA(1l

~---~6------~}
BV

. . - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 API X RQ (TO AP I LOG I C I

..--------t----------------------------------. ENA(O)
8M

~~~-4-------------_+------_+-----+_------------------------------~API

X EN OUT

I----~---I

API X EN IN
API REQ (0)

BU
API REQ (1)

W
I

10
PWR CLR

SELECT

I
I
I

API X EN IN

ENB(O

ENB(O)

ONLY USED WITH DATA
CHANIEL. NOT NECESSARY
WITH API

BF
FLAG CLR
(NOT USED FOR API)

10 POWER CLEAR

L__

10 SYNC ----------~

ENA (0)

I
I
I
I
I
I
I

~A_(_Il_ _ _ _ _ _ _ _ _ _ _ J

~--~-----------------------------_i> CLEAR

FLAG
(NOT USED FOR API)

BS
FLAG (1) --------------------------------------~

BE
API X GR --------------------------------------------~--_M
API REQ (1)

Figure 3-1 Multiplexer W1 04, Block Diagram

When API BK RQ/BK SYNC does occur, an API X GR (1) goes to the W104 from the API
logic, setting the ENA flip-flop and conditioning its DCD reset gate. ENA (1) allows the W104 to
put the device's 10 ADDR on the I/O bus. API BK RQ also goes to the extended memory control option
to clear the EPC when the processor acknowledges the API break.
If API BK RQ/BK SYNC occurs following the last cycle of a DCH/RTC program segment or
lOT instruction as noted, the computer returns to the main program to execute one instruction; BK SYNC
must wait for the DONE (1) level in the instruction execution, when this occurs it causes the BK ENTRY
process word (11) to replace the BGN process word (10) of the normal computer execute cycle. (An
EAE instruction can cause a wait of up to 18 l-'s before DONE.)
BK entry substitutes the device's 10 ADDR for the current address in the PC, and the computer
enters the XCT cycle. The XCT cycle fetches the instruction addressed by 10 ADDR (trap address) for
execution.
On the next processor word (33), the transition of EXT (0) causes the API logic to reset
API X GR, API SYNC, API BK RQ/BK SYNC, and sets a PLX flip-flop indicative of the priority level
of the API break just entered. API X GR (0) and 10 SYNC reset the W104's ENA flip-flop.
All computer logic circuits are now initialized for subsequent break requests from any source
above the currently active priority level.

Lower API levels, the PI faci I ity, and the main program are

all blocked by the I/O control logic and API logic. These lowl'dr priority requests are deferred until the
current program segment relinquishes control, while higher priority requests can interrupt the current
program segment upon completion of its current instruction (or the instruction following a current lOT).
Note in Figure 3-1 that the API REO flip-flop can be gated externally to the PI facility's
PROG INT RQ line at the I/O bus if it is desired to connect an API device to the PI facility also.
Such is the case of the paper tape reader, rea I-time clock, and optional power failure detection system,
which are connected to both facilities. In this situation a"device flag issues a PROG INT RO at the same
time the W104 issues an API X RO, but if the API is enabled, the PROG INT RO is blocked by the PI
DISABLE generated in the API. The API break service routine clears the flag before exiting the routine,
so that no repeated API break occurs. The device flag must also be connected to clear the API REO
fl ip-flop (See Figure 3-1).
The foregoing discussion briefly describes the system operation for the four device-oriented,
fixed-priority levels. The API instructions also provide for program-initiated interrupts on the four fixed
software priority levels, and for raising all levels to higher priorities as necessary. Each of these functions
is described in detai I be low.

3-3

3.2

LOGIC DISCUSSION

3.2. 1

ISA Instruction
The ISA instruction (705504) performs four distinct functions.
a.

Enables or disables the API in conjunction with the state of ACOO.

Raises the priority level of the paper tape reader to 0, 1, 2 in conjunction with AC01-02

for maintenance purposes.
c.

Requests service of software priority level 4, 5, 6, 7 in conjunction with AC06 through 09.

Raises the priority level of the current program segment to anyone of the eight levels

in conjunction with AC1 0 through 17.
To perform any of the last three functions, ISA must necessarily be programmed with ACOO
in the 1 state.

Otherwise the API disables.

ISA fetch and decoding logic is identical to all other lOT instructions as explained in the
PDP-9 Maintenance Manual. In brief, during the fetch cycle the ISA instruction is placed in the MB,
the op code portion in the IR, and the AC contents are placed in the AR. MB14 (0) in the instruction
generates lOT OR ARO, drawing KC12, so that the ARO and 10 BUS ON sense fl ip-flops become set
on the (third) CM STROBE that extracts the lOT execute process word (76) from control memory. ARO
(1) and 10 BUS ON (1) gate the contents of the AR onto the I/O bus via the A bus and ADR.
lOT (B) derived from lOT (1) decodes the device select bits MB06 through 11 for appropriate
DSOO-05 levels on drawing KD3 (1). These levels go to the API logic, drawing KF1 (3), where they
generate the API SEL level. The MB15 through 17 command bits are decoded and synchronized with
the 10 CLOCK 100, 101 on drawing KD3 to issue an IOP4 pulse at the start of the fourth lOT cycle.
IOP4 (1) triggers pulse amplifier S602-J28U on drawing KFl (3), producing the IOT5504 pulse. The
IOT5504 pulse in turn generates CLR API GR at S603-F30T, drawing KF1 (1). CLR API GR resets API
BK RQ and API 0, 1, 2, 3 GR, and generates API 10 CLR, all on KF1 (3). API 10 CLR resets PRE
API SYNC and API SYNC on KF1 (1).
IOT5504 proceeds to execute any function called for by the other AC bits now on the I/O
bus as follows.

3.2.1.1

API Enable - IOT5504 strobes the DCD gates at the API ENABLE flip-flop, drawing KFl (3).

If 10 BUSOO is 1, it conditions the set gate, and IOT5504 sets the flip-flop. If 10 BUSOO is 0, it conditions
the reset gate via 10 BUSOO (B) at the input mixer, drawing KD7. IOT5504 resets the flip-flop in this
instance.

3-4

3.2.1 .2

Request Service on Software Priority Level - I SA can request service on any software priority

level. To obtain such service once the request has been made, all higher priority levels must be currently
inactive. Otherwise, the request waits unti I all higher priority requests have been honored and released.
To request service on priority level 4, for example, 10 BUS06 (1) conditions the DCD set gate
to the API4 RQ flip-flop, drawing KFl (1), so that IOT5504sets the flip-flop. API4 RQ (1) generates
API 4 RQ (1) B on drawing KFl (2). This level genera!'es a RQ SYNC 4 on KFl (1) only if the associated
PL4 EN level is asserted. PL4 EN is an indicator of the currently active priority level and comes from
the DC carry chain S181-E27.

Here the status of all priority levels PLO through PL7 are so connected

that an active priority level turns off all lower PLX EN levels (see Logic Handbook, C-l05). PL3 (1)
at the carry chain, for example, makes PL3 EN through PL7 EN go to ground, inhibiting the RQ SYNC
3 through RQ SYNC 7 gates. In this case, the API 4 RQ fl ip-flop remains set and waits until PL3 (1)
is released by a DBK or DBR instruction before it can cause a RQ SYNC 4 level.
Moreover, a second DC carry chain, S181-H30 on drawing KF1 (2), looks for simultaneous
API requests on other priority levels. If an API 2 RQ is present, for example, then API 2 RQ at H30F
is CIt ground, causing the API 3, 4, 5, 6, 7 RQ (1) B levels to go to ground at the carry chain output.
API4 RQ (1) B thus grounds itself at the RQ SYNC 4 gate even though the API 4 RQ flip-flop is set.
On drawing KF1 (1), API 2 RQ genera'tes API 2 RQ (1) B for application to its RQ SYNC 2 gate, thus
gaining priority control. The RQ SYNC 0 through 7 levels start the break synchronization as explained
in Section 3.2.2.

3.2. 1 .3

Raise Priority Level - The I SA instruction uses AC bits 10 through 17 to raise the currently

active priority level to the level indicated in the bits. A currently active priority level PL3 can be
raised to PL2 by AC12 (1). AC12 (1) appears as 10 BUS12 (B) from the input mixer to the RPL EN gate,
drawing KF1 (1).

Here PL2 EN is negative because PL3 (1) at the DC carry chain disables all PLX EN

levels but PL2 EN, PL1 EN, PLO EN.
RPL2 EN conditions the DCD set gate to the PL2 flip-flop, and IOT5504 sets the flip-flop.
PL2 and PL3 are now both currently active, and the currently active service routine or program segment
continues at the higher level.

3.2.1.4

Raise PTR Priority Level - The paper tape reader is assigned to priority level 2, which may be

raised to 1 or 0 for maintenance purposes. The reader's W104 Multiplexer is installed within the API
logic as shown on drawing KF1 (4).
To raise the reader's priority to level 0, AC01 (1) and AC02 (0) appear as 10 BUSOl (ground)
and 10 BUS02 (negative) at the PLS CONTROL 0,1 flip-flops, drawing KF1 (4). IOT5504 sets PLS
CONTROL 0 and resets PLS CONTROL 1 under these conditions. This combination results in the SEL 0

Ieve I at Sl 07 -B04D.
3-5

SEL 0 now waits for the RDR FLG (1), indicating that the reader has assembled a data word

in its reader buffer (RB) and is ready to transfer it into memory. RDR FLG (1) conditions the set DCD
gate to the API REQ flip-flop in the W104. The API REQ flip-flop sets on the next available 10 SYNC
SP (B) pulse. 10 SYNC SP (B) derives from 10 SYNC SP at S 107-B05, drawing KF 1 (4). 10 SYNC SP
occurs on the next 10 CLK POS pulse, drawing KD3(1).
Note that a PF API RQ (1) from the W104 of the optional power failure detection option holds
the reader's API REQ flip-flop in the reset state via terminal BH, since this option is assigned highest
priority •
When the API REQ flip-flop in the reader's W104 does set, it issues a PTR API RQ (1) level
from terminal BU. SEL 0 and PTR API RQ (1) produce API 0 RQ at R123-C02N, and also ground the
API 0 EN level at R111-B06H. This level goes to the first W104 on the priority level 0 line at the I/O
bus, disabling all other requests from devices on this priority.
API 0 RQ goes to KF1 (1) where it generates API 0 RQ (B). This level produces RQ 0 EN on
KFl (2), and removes the ground API 0 RQ (B) from the input inverter Sl07-F31N at the DC carry chain
S181-H30. This puts RQ 1 EN and all outputs from the carry chain at ground, deferring the requests
from all other priority levels.
RQ 0 EN is NANDed with PLO EN for RQ SYNC 0 on drawing KF1 (1). The PLO EN level
is asserted by virtue of the CAF EN (B) and PLO (0) signals at inverter Sl07-E28T. CAF EN(B) is always
present in the absence of an IOT33XX instruction (CAF, DBK, DBR).
RQ SYNC 0 starts the API break synchronization as explained in Section 3.2.2. The API
SYNC and API BK RQ flip-flops become set upon synchronization, and API 0 GR follows thereafter.
API 0 GR (1) from KF1 (3) produces PTR GR on KF1 (4) in conjunction with SEL O. PTR GR sets the ENA
flip-flop in the reader's W104, and conditions the DCD reset input gate. ENA (1) puts the reader's

10 ADDR on the I/O bus, the break entry process word 11 enters the 10 ADDR in the MB, and the API
break starts. As the break starts, the PLO flip-flop sets and the API 0 GR flip-flop resets. Upon resetting
API 0 GR resets ENA and makes PTR GR go to ground. PTR GR then resets the API REQ flip-flop. However, because the RDR FLAG is set, the next 10 SYNC pulse will again initiate PTR API RQ and API 0
RQ. This will not cause a subsequent API break because PLO is now set. Before exiting the service
routine, an RRB instruction must be issued to obtain the information from the reader buffer. This causes
the RDR F LG to reset. RDR F LG (0) puts -3V on pin K of the S 107- B05 on drawing KF 1 (4). The output therefore goes to ground and the collector resets PTR API RQ. The service routine may now be
exited without a repeated API break.
The reader's program segment thus operates at priority level O. The RDR FLG sets on each
occasion that the reader has assembled a new word in its buffer, and resets on an lOT instruction which
reads the buffer contents into the AC. Note that PTR API RQ produces a PROG INT RQ in the reader

3-6

control logic in conjunction with RDR FLG (1). If both systems are enabled, the next 10 SYNC POS
pulse to occur will simultaneously set the PROG SY flip-flop on drawing KD3 (2) and the PRE API SYNC
fl ip-flop. However, PRE API SYNC (1) and API ENABLE (1) wi II produce PI DISABLE on drawing KF 1 (3);
this will immediately collect or reset PROG SY and the interrupt will be controlled by the API logic;

3.2.2

Break Synchronization
A RQ SYNC X leve I occurs on drawing KF 1 (1) as a resu It of the ISA functions of Sections

3.2.1.2,3.2.1.4, or simply as a result of enabling the API system as in 3.2.1.1 and letting a device
request service on its fixed priority level.
RQ SYNC 0-7 conditions the DeD set gate to PLO-7 in all three cases; RQ SYNC 0-3
appears at the API 0 GR - API 3 GR jam input gate in case of a device-oriented request; RQ SYNC 4-7
conditions the DCD reset gate to the API 4 RQ - API 7 RQ flip-flop and appears at the 10 ADDR bus
gating (KD5) in the case of a software-generated request.
In a II cases RQ SYNC 0-7 generates on API SYNC RQ on drawing KF 1 (1). PRE API SYNC
wi II set on the next permissible 10 SYNC POS pulse. On drawing KD3 (2) an 10 SYNC POS pulse
occurs at 10 CLK (b) time only if:
a.

No lOT instruction (lOT (0) ) is currently in progress.

No RTC break (C LK SYNC (0) ) has been initiated.

No PI break (PROG SY (0) ) has been initiated.

No API or DCH break (PRE API SYNC (0) ) has been initiated.

If a DCH break has been initiated, the API must wait until the start of the second or third
DCH cycle, at which time DCH SYNC resets, removing INC V DCH and consequently a PRE API SYNC
(0) reset-holding level from the collector of the PRE API SYNC flip-flop, drawing KFl (1). Refer to
Figure 3-2 and to the DCH discussion in the PDP-9 Maintenance Manual.
I-------wc-~~~

o _DCH
SYNC

I---wc ---4~~I..___-

~f4

DATA IN

O-ENA
1 _PRE API
SYNC

NEXT FETCH CYCLE--+I

CA ---".I~"-DATA OUT ~-DATA OUT

i i i
O-DCH
SYNC

Figure 3-2

1 _SK SYNC

O-ENS
1 - A P I SYNC

O-ENA
1PRE API
SYNC

~f4

NEXT FETCH CYCLE --.j

0 - ENS
1 - API SYNC

API Break Timing Following a DCH Break

3-7

I_SK SYNC

This delay gives the DCH time to reset ENB in its Wl 04, removing the force select level from
its device before the API break begins. Because of this delay, the computer returns to the main program
and executes at least one instruction before BK SYNC initiates an API break at instruction DONE time.
Since an RTC break also gen~rates INC V DCH, it too delays the setting of PRE API SYNC,
in this case permitting the main program to execute at least two instructions before BK SYNC initiates an
API break, Figure 3-3.

\4---WC

-1~TI4-_-:XET

::= i

~,.

EXECUTE

"!-I

NEXT FETCH

"!-I
EXECUTE ----=----iIBK

t_BK SYNC

SYNC

BGN
ENTRY

O-CLK SYNC

Figure 3-3 API Break Timing following an RTC Break

PRE API SYNC (1) conditions the API SYNC fl ip-flop, drawing KFl (1), and produces PI
DI SABLE in conjunction with API ENABLE (1), drawing KFl (3). Note that PI DI SABLE can also result
with API ENABLE (1) if the Pl7 EN level is present. Pl7 EN means that a priority level is still active
as evidenced by a PlX (0) input to the DC carry chain. For example, a DBK or DBR releases the highest
currently active priority level, a lower level remaining active. Since API ENABLE remains set unless
reset by I SA, API ENABLE (1) and Pl7 EN keeps the PI DI SABLE level at its asserted ground level.
This level goes to drawing KD3 (2) where it prevents PROG I NT RQs from initiating PI breaks until the
API system is disabled or until no further API requests are present.
The next 10 ClK POS pulse sets API SYNC. API SYNC (1) conditions the ACT API GR, ACT
Pl, and ClR API GR gates, all on drawing KF1 (1), and the API BK RQ set gate, drawing KF1 (3).
On the next 10 ClK POS pulse, 10 ClK (B) from KD3 (3) generates an API STROBE on KF1 (3),
which sets API BK RQ and generates ACT API GR. ACT API GR strobes the jam input gates of the API
0, 1, 2, 3 GR fl ip-flops to set any fl ip-flop conditioned by an appropriate RQ SYNC level. API BK RQ (1)
produces BK SYNC on KD3 (2) and API BK RQ (l)B on KF1 (1). At the 10 ADDR bus, drawing KD5, API
BK RQ {l)B turns on the appropriate 10 ADDR 12, 16, 17 signals if an ISA-initiated RQ SYNC 4-7 level
is present (software request).
Conversely, an API 0, 1, 2, 3 GR (1) level sets the ENA fI ip-flop of the W104 which issued
an API 0, 1, 2, 3 RQ and conditions the reset gate.

3-8

ENA (1) puts the device's 10 ADDR on the I/O bus.

BK SYNC waits for the DONE (1) level of the current execute cycle, at which time ODD ADDR,
on drawing KC17, changes the address of the next process word from 10 (BGN) to 11 (BK entry). Whereas
the BGN process word sets up the MB for the next computer fetch cycle, the BK entry word enters the 10
ADDR in the MB for the start of the API break. The BK entry word contains the processes EXT, IRI, SM,
and CMA30. EXT (1) sets the BK flip-flop on KD3 (2), produces LIO on KC13, and 10 ADDR ON BUS
on drawing KD7 (1). IRI (1) puts Os in the IR. 10 ADDR ON BUS gates the 10 ADDR bits from the I/O
bus into the input mixer, where they appear at I/O bus (B). LIO gates the contents of I/O bus (B) onto
the 0 bus. EXT (1) on drawing KC19 (2) produces 1 ..... MBI in conjunction with MEM DONE, SM (1),
and RUN (1). 1 ..... MBI sets the MBI flip-flop, and MBI (1) gates the 0 bus contents into the MB.
At the CM address gates on drawing KC17, EXT (1) and API BK RQ (1) B boost the next CM
address from 30 to 33 (EXT entry). SM (1) of the BK entry word and the next CM ClK pulse extract the
XCT entry word from control memory as ClK and SM (1) start the core memory cycle. Thus, the XCT
cycle starts, retrieving the instruction contained in the addressed core memory location (trap address)
for execution, going from process word 33 to 24 to 30 (execute).
Upon extracting the XCT entry word 33, EXT (1) is no longer present; EXT (1) B generates
ACT Pl and ClR API GR on KF1 (1). ACT Pl sets the appropriate PlO-7 flip-flop and resets the appropriate
API 4 RQ - 7 RQ fl ip-flop if set by an ISA-initiated request. ClR API GR resets the API 0, 1, 2, 3 GR
flip-flop if set by an ISA or device-initiated request, resets API BK RQ, and generates API 10 ClR. API
10 ClR resets PRE API SYNC and API SYNC.

The next 10 ClK POS pulse produces 10 SYNC, which resets ENA in the W104, now conditioned
by reset API X GR. All API circuits are now initialized for other API requests. The currently active
API break continues until released or until interrupted by a higher priority API request, DCH/RTC
request, or DMA request.

3.2.3

SPI Instruction
The SPI instruction (705501) tests the status of the API ENABLE flip-flop and/or a Pl X EN

level as commanded by a control word in the AC. If the API ENABLE fI ip-flop is in the reset state or
the Pl X EN level is true (negative), the program skips the next instruction. A true Pl X EN level
indicates that the priority level and all others above that level are inactive.
The SPI instruction is decoded as usual to produce the API SEl level on KF1 (3) and the IOP1 (1)
level in the I/O control logic. The control word in the AC gets to the I/O bus (B) via the AR, ADR and
I/O bus as for ISA. On drawing KF1 (3) the control word bits are gated with the corresponding API ENABLE
and PL X EN status levels at R141-E24. If the corresponding status for the command control word bit
is true, API SEl and the output of R141-E24 place a negative input at the INT SKP RQ BUS gate Rl11-

3-9

F29H. IOP1 (1) arrives from the I/O control logic to enable the gate. INT SKP RQ BUS goes to KD3 (3)
to cause the skip, as explained in the PDP-9 Maintenance Manual.
The PL X EN levels come from the DC carry chain S181-E27, drawing KF1 (1).

For a negative

PL X EN level out, the corresponding PLX flip-flop and all others of higher priority are reset (inactive).
3.2.4

CAL Instruction
The CAL instruction (op code 00) automatically activates software priority level 4 regardless

of the currently active priority level.

During process word 12 of the computer fetch cycle, IRI (1) places

the CAL op code in the IR, where it is decoded to set the CAL fl ip-flop, drawing KC12. On the next
process word (24), IRI (1) resets. CAL (1), IRI (0), and API ENABLE (1) produce PL4 (1) and CLR API GR I
drawing KFl (3). PL4 (1) sets the PL4 flip-flop, drawing KF1 (1), by collector-pulling the negation side
to ground.
CLR API GR resets the API 0, 1, 2, 3 GR and API BK RQ flip-flops, and generates API 10 CLR,
drawing KF1 (3). API 10 CLR resets PRE API SYNC and API SYNC, drawing KF1 (1).
The currently active priority level remains active. The subroutine reached by CAL operates
at the currently active priority level if higher than PL4, or operates at PL4 if lower. A DB K at the end
of the CAL subroutine releases the highest priority level. The lower level remains active.
3.2.5

DBK, DBR Instructions
Both the DBK (703304) and DBR (703344) instructions release the highest active priority level.

Both instructions are decoded to generate the CAF EN and CAF EN (B) levels, drawing KD3 (1).
On drawing KFl (1), CAF EN conditions the DCD gate to the ACT PL signal and the DCD
reset gate to the PLO fl ip-flop. CAF EN (B) disables the PLX EN carry chain. On drawing KFl (2)
CAF EN enables the DBK carry chain, and on KFl (3), CAF EN disables API STROBE pulses.
At the DBK chain the highest active priority level produces a corresponding ground DBK X
level and makes all lower priority outputs go negative. The active DBK X level conditions the reset
gate of its corresponding PLX flip-flop. ACT PL occurs on the IOP4 (1) level to reset the flip-flop.
In addition, the DBR instruction produces an IOT3344 level on KD3 to set the DB RESTORE
flip-flop.

DB RESTORE (1) waits for the following JMP I instruction, at which time the interrupted status

of the LIN K, memory extend mode, memory protect mode, and extended program counter are restored to
the main program along with the contents of the PC.

3.2.6

See Section 3.8.1 .7, PDP-9 Maintenance Manual.

Maintenance Instruction
The maintenance instruction (705512) reads certain API status conditions (Table 2-6) into the

AC via the input mixer, drawing KD7. The instruction is decoded as usual to produce API SEL on drawing
KFl (3) as for ISA. At IOP2 time the IOP2P pulse from the I/O control logic sets the IOT5502 flip-flop.
3-10

IOT5502 (1) is gated onto the INT RD RQ BUS, drawing KD3 (3), and produces API ON BUS, drawing
KD7 (1). API ON BUS gates the status bits onto I/O bus (B). INT RD RQ BUS produces RD RQ (B) which
is gated with 101 (1) and ClK DlY'D for AC RD. AC RD goes to the CM sense flip-flops, drawing KC19
(2) where it becomes AC RD (B) and produces the 1 ..... ACI pulse.
AC RD (B) goes to drawing KC13 to produce LIO.

1 ..... ACI sets the ACI flip-flop.

LIO gates the contents of I/O bus{B} onto

the 0 bus, drawing KC20. ACI (1) gates the 0 bus contents into the AC.

See Section 3.8.1.4 of the

PDP-9 Maintenance Manual for more details on input transfers.

3.2.7

Power Failure Detection Option
When the Power Failure Detection option KP09A is installed in the I/O wing along with the

API system, it is assigned priority level 0 and its W104 is installed internally as shown on drawing KFl (4).
When the option detects the start of a power failure, its PWR DN output to the W104 causes
an API break which is used to save the contents of certain PDP-9 registers before the power turns off
completely.
API break synchronization is simi lar to that explained for PTR breaks, except that the priority
level is fixed.

Separate API 0 EN and API 0 RQ levels are taken from the W104 directly rather than

going through the SEl 0, 1 gating. PWR DN causes a PROG INT RQ if the API system is disabled, as
similarly noted in the PTR discussion, 3.2.1.4.

3.2.8

Clock Overflow Breaks
The real-time clock {RTC} of the basic PDP-9 system is assigned priority level 3. Its Wl 04

module is installed internally, drawing KFl (4). When the RTC break causes the RTC's WC register to
overflow, its ClK FlG sets, drawing KD3 (2), to cause an API break.
API break synchronization is similar to that explained for PTR breaks, except that the priority
level is fixed.

Separate API 3 EN and API 3 RQ levels are taken directly from the Wl 04 rather than

going through the SEl gating as for PTR breaks.
ClK FlG (1) causes a PROG I NT RQ if the API system is disabled, as similarly noted in the
PTR discussion, 3.2.1 .4.

3.3

INDICATOR WIRING
The REG ISTER indicator wiring for the API and I/O ADDR positions of the REGI STER DI SPLAY

switch is discussed in Section 3.7.5 of the PDP-9 Maintenance Manual.
The PS ACTIVE indicators are direct-wired to the indicator drivers, drawing CS-9-0-4, via
the IO/console interface connector W037-A10, drawing KD6, from the PlO-7 flip-flops in the API option.

3-11

CHAPTER 4
MAINTENANCE
4. 1

GENERAL MAINTENANCE
The general maintenance practices described in the PDP-9 Maintenance Manual also apply

to the API option.
4.2

TEST PROGRAM
The API option can be tested using I/O Test (API) MAINDEC-9A-DOIA-PH under normal

operating conditions and under voltage margins as specified on the margin sheet suppl ied with the system.

4.3

MODULE REPLACEMENT
Table 4-1 lists the full complement of logic module comprising the API option. The spare

modules kit SP09A offered by DEC as a replacement stock level for the entire PDP-9 system provides
at least one spare of all module types used in the API. It is recommended that the user maintain this
minimum stock level to avoid equipment down-time due to repair of faulty modules.

Table 4-1
API Module Complement
DEC Type

Module Type

Quantity

B213

Dual Flip-Flop

R002

Diode Network

R1ll

NAND/NOR Gate

R123

Input Bus Gate

R141

AND/OR Gate

5107

Inverter

5181

DC Carry Chain

5202

Dual Flip-Flop

5203

Triple Flip-Flop

5205

Dual Flip-Flop

5602

Pulse Amplifier

5603

Pulse Amplifier

W005

Clamped Load

W104

Multiplexer

*Total quantity of four when Power Fai lure Detection KP09A is installed.
4-1

CHAPTER 5
ENGINEERING DRAWINGS

This chapter contains a complete set of engineering drawings pertaining to the API option
along with circuit schematics of all logic modules. DEC engineering drawings are encoded as to drawing
type, major assembly and series. These drawing number codes are explained in Chapter 5 of the PDP-9
Maintenance Manual.

5.1

SIGNAL MNEMONIC INDEX
All signals originating on the API logic drawings are listed below in alphanumeric order. The

Origin column locates the source of the signals to the specific logic drawing, using the abbreviated
drawing number system.

Signal

Origin

Description

ACT API GR

KFl (1)

Activate API grant

ACT PL

KFl (1)

Activate priority level

API BK RQ

KFl (3)

API break request

API BK RQ 1 (B)

KFl (3)

API ENABLE

KFl (3)

API 10 CLR

KFl (3)

API SEL

KFl (3)

API SYNC

KFl (1)

API SYNC RQ

KFl (1 )

API SYNC (1) B

KF1 (1)

API 0 EN

KF1 (4)

API 0 EN - API 2 EN

KF1 (4)

API 0 GR - API 3 GR

KF1 (3)

API 0 RQ

KF1 (4)

API 0 RQ - API 2 RQ

KF1 (4)

API 0 RQ (B) - API 3 RQ (B)

KF1 (1 )

API 0 RQ NEG - API 3 RQ NEG

KFl (I)

API 2 RQ (B) - API 7 RQ (B)

KF1 (2)

API3 EN

KFl (4)

API 3 RQ

KF1 (4)

API 4 RQ - API 7 RQ

KFl (I)

5-1

API select

Signal

Origin

API 4 RQ (1) B - API 7 RQ (1) B

KF1 (2)

CLR API GR

KF1 (1)
KF1 (3)

COY API RQ (1)

KF1 (4)

Real-time clock overflow API reguest

DBK 1 - 7

KF1 (2)

Debreak highest priority

INT SKP RQ BUS

KFl (3)

Interva I sk ip req uest bus

lOA DDR 12, 14, 16

KF1 (4)

Power failure detection trap address (52)

lOA DDR 12, 14

KF1 (4)

Paper tape reader trap address (50)

lOA DDR 12, 14, 17

KF1 (4)

Real-time clock overflow trap address (51)

10 CLR (B)

KFl (3)

10 PWR CLR NEG

KF1 (4)

10 SYNC SP (B)

KF1 (4)

IOT5502

KF1 (3)

IOT5502 (0)

KF1 (3)

IOT5504

KF1 (3)

PF API RQ (1)

KF1 (4)

PF API RQ (1)

KF1 (4)

PI DISABLE

KF1 (3)

PLS CONTROL 0 -PLS CONTROL 1

KF1 (4)

Paper tape reader priority select control

PL 0 - PL 7

KF1 (1)

Priority level

PL 0 EN - PL 6 EN

KF1 (1)

PL4 (1)

KF1 (3)

PL 6 EN P

KF1 (1)

PL 7 EN

KF1 (1)

PL 7 EN (B)

KF1 (1)

PRE API SYNC

KF1 (1)

PRE API SYNC EN

KF1 (1)

PRE API SYNC (0)

KF1 (1)

PTR API RQ (1)

KFl (4)

PTR API RQ (1)

KFl (4)

PTR GR

KFl (4)

RPL 1 EN - RPL 7 EN

KFl (1)

RQ SYNC 0 - RQ SYNC 7

KFl (1)

RQ 0 EN - RQ 1 EN

KFl (2)

SEL 0 - SEL 2

KFl (4)
5-2

Description

Special 10 SYNC pulse

Power failure API request

Paper tape reader API request

Raise priority level enable

Paper tape reader priority select level

5.2

DRAWING LIST
Below is a list of all drawings included in this chapter. Other refated API logic is included

in the Chapter 5 drawings of the PDP-9 Maintenance Manual as part of the prewired, basic system.

Drawing Number

Title

Revision

Page

B-C S-B213-0-1

Dual FI ip-Flop B213, Circuit Schematic

5-4

B-C S-R002-0-1

Diode Network R002, Circuit Schematic

5-4

B-C S-R 111 -0-1

NAND/NOR Gate R111, Circuit Schematic

5-5

B-C S-R 123-0-1

Input Bus Gate R123, Circuit Schematic

5-5

B-CS-R 141-0-1

AND/OR Gate R141, Circuit Schematic

5-6

B-C S-Sl 07-0-1

Inverter S107, Circuit Schematic

5-6

B-C S-S181-0-1

DC Carry Chain S181, Circuit Schematic

5-7

B-C S-S202-0-1

Dual FI ip-Flop S202, Circuit Schematic

5-7

B-C S-S203-0-1

Triple Flip-Flop S203, Circuit Schematic

5-8

B-C S- S205-0-1

Dual FI ip-Flop S205, Circuit Schematic

5-8

B-C S- S603 -0-1

Pulse Amplifier S603, Circuit Schematic

5-9

B-C S-W005-0-1

Clamped Load W005, Circuit Schematic

5-9

D-C S-W1 04-0-1

Multiplexer W104, Circuit Schematic

5-11

D-BS- KF09-A-1

Automatic Priority Interrupt, Block Schematic (Sheet 1)

5-13

D-B S- KF09-A-1

Automatic Priority Interrupt, Block Schematic (Sheet 2)

5-15

D-BS- KF09-A-1

Automatic Priority Interrupt, Block Schematic (Sheet 3)

5-17

D-BS- KF09-A-1

Automatic Priority Interrupt, Block Schematic (Sheet 4)

5-19

A-PL- KF09-A-2

Automatic Priority Interrupt, Module Parts List

5-3

5-21

r-----------------~--------------------------------~----------------_1~--------------------~A
+IOV
M GND

.~ 022

RII

R211

1,000

r-~.

CIO

-3V

....JL

"1i

4 ~2(p MFO

\ hi.
~'D24
'-=' QI4
RIB
100
10"1.

R20
6,800

R23
6,800

...

R24
100
10%

-3,5V

r-------~~------_.----------+4_T--4_--~~--~----__------_4--4_------_.--------~+_~-2~.~~~ I ~'g~~2

IMIj[

DO~.I f+__I~.51_ 'r-ID6H~" ~H."l
......

......

...

R8
470
100;.

RI
1,500

R2
750

~~H~J ~~; ~ 1'O"~~, L,J~..1

~f1l39B ~

R3
7,500

RI3
100

...

DEC
3639B

7,5oo?

R22

R27

470
10%

1\
27

100

~
RI4
1,500

~----~----_+--------;_~

Rill
1,500

RI6
750

}i'/

~~639B ()1---J

4 MMFORI~OO;'l

~
R7
1,500

/I
27

M~b ~~D

RI7
7,500

R21
1,500

MMFO R::%l

~~~
3639B

7,500 ~

R2B
I,!IOO

R29
750

R3
750

~---+----_r----~--------+_~

~--~~---4~--------------------------~~--------~----e---~~----------------------------~----~--~~IB

-1!lV

UNLESS OTHERWISE INDICATED;
RESISTORS ARE 114W; 5'"
DIODE S ARE 06114TRANSISTORS ARE DEC 3009B

B-CS-B213-0-1

Dual Flip-Flop B213, Circuit Schematic

010

0664

0664
09

::
::
::

...1
0664

0664
DB

I!lJI

0664

0664
07

...1
0664

0664
08

I!lJI

0664

...1

0664

! ::::::::;;i!;:::::!

B-CS-R002-0-1

Diode Network R002, Circuit Schematic

5-4

r-------------......--------------....

-------------~OA.IOV(AI

GND

2 I
Df64:
DI I
0664 I 5

DII

D-e!I4

I
I

---,

~.\OO:
R
I

2 I

B- IIIV

:L.. _____________
EXAMPLE DGL2 .J:

UNLESS OTHERWISE INDICATED:
RESISTORS ARE 1/4W; 5%
PRINTED CIRCUIT REV. FOR
DGL BOARD IS SIB

B-CS-R 111-0-1

NAN D/NOR Gate R111, Ci rcuit Schemati c

r-___________....____________~------------~~------------t-------------~----------oA.,OV(A)
R5
IOD,OOO

R 2
100,000

RB
100,000

R II

100,000

RI4
100,000

R 17

IDqOOO

~------_+----._------~~--~--------+_--~~------_r----.-------_1----~-----oC OND

R4
15,000

RI
15,000

R7
15,000

RIO
15,000

RI3
15,000

Ria
15,000

L-____________~------------~------------~~------------~------------~----------oB-15V

UNLESS OTHERWISE INDICATED:
TRANSISTORS ARE DEC 3639
RESISTORS ARE 114W,5°4
DIODES ARE 0-664

USE THE ETCH BOARD OF W 101

1;:::--;:--;;----;;1

B-CS-R123-0-1

Input Bus Gate R123, Circuit Schematic

5-5

DI4

..,

D,!,a
~

.
....

D!2

D~
~

...
D.!J
...

~
...

CI
.01

~'D2~

DEcaoon

~~D

D!
RII

"g~:2

f"'I

D',!

0112

III~OOO

~.'

®~I

....

Din

C GND

DECant

024

....

......

-lite

RII
1,1100

7,1100

111,000

....

DII

!1
T

DI
~

D~2

...
....

D20

11,000

R7
111;000

DII

A +IOV(A)

RIO
100,000

RI
27,000
10%

.......

D21

DI7

........

R3
111,000

~,
~2

D!,.I

....

111,000

....

Dill

UNLESS OTHERWISE INDICATED:
RESISTORS ARE 114W, 11%
DIODES ARE DIS4

........

B -IIIV

111,000

B-CS-R141-0-1

AND/OR Gate R141, Circuit Schematic

r---- ----,
:

EX~~tiE

r - - - - - - t - - - - - - - + - - - - - -.......- - - - - - . - - - - - - + - - - - - - + . + - - - ; - - - - - -, - O A . I O V ( A )
RI

100,000

I~~~~~_J

r-------,

.......--~---~~--~-~r--_+~r_~~-~~_T~2---~,-oCGNO

r---+---.---~--+---_r--

08
:
0-682

0-6621
I
DID
I

0-662 :
011

0-662 1
~~--~-~-~-~r_~-+_--r_~-~--~-~-~-~-~~++-_+-~~-~6
:

RI5

1,500

~--4---~--~--~--_+--~--_4--~~--~-~~-~_+-~~-~,-_+~I--~-oB-15V
r5~JOO:I

____ J

UNLESS OTHERWISE INDICATE 0:
RESISTORS ARE 114W;II%
DIODES ARE 0 - 664
TRANSISTORS ARE DEC 3639B
PRINTED CIRCUIT REV. FOR
DGL BOARD IS SIA

USE THE ETCH BOARD OF THE R 107

1::::::::::::::::::1

B-CS -S 107-0- 1

Inverter S 107, Circuit Schematic

5-6

i ST~!~E

L ______ J

A +IOV
RI

~O2

r-(QOI

R9
11

'~053
RI6

"018

012

4~2: ~294 ~30 ..

HQ05

...
~31" . ~034
~

032 033

RI4
rf06

~~ 016

~~08

RI3
n,5

~~015

~ ~09

nO':

~'017

~010

::: I"'CI

~oll
RI5

B -15V

~R19

o21~ ,

RI2
rl04

" C GNO

~O7

HQ06

~'014

~R18

RII

013

020' ,

tJRI7

·~2~ ~027

~o2!3

RIO
12

R!3

-E9 -E9

t
.
"
fo40fo4~

o2.2~'

4
fo35

~, 023

R20

~3~ 037~ 038 "039

R22

R21' '024

"04~ .044 ~4: ~45.4

~46t47fo48~ ~ ~5~ ~ .. "
4

049

051

052

,.. FK
r. H

M
~

B-CS-S181-0-1

~~043

DC Carry Chain S181, Circuit Schematic

~~46" ~049

~,,047

.,,044

~",045

r-o p

r080.o00~ '016

~'D25

~"'D50

... 048

...-0 V
A.IOV(A)

R4
100,000

UD4

...

~g~ r
~ h ' ~E
- 62
05

08
R3

, ,pI4....
0-662

--.. , '8~~62

'91 O~

l~bO.~O

R2
12,000
10%

fD?

R5
3,000

Dc.!:

....

N~ fD.fo
...

~~
1\

....

J~~, r
023

R6
3,000 ~,,012

R9
12,000
10°/.

D}.I

12r8~~

RII
12,000
10°/.

RI2

121g~?

~D26

B-CS-S202-0-1

051

RI5
3,000

....

DJIl

....

030

RI7

RI6
3.000 ~~D31

RI9

12'1%~/?

0'52

Dual Flip-Flop S202, Circuit Schematic

5-7

C GND

l'rg~ll62

?J7

M~6 ;;

I
UNLESS OTHERWISE INDICATED:
TRANSISTORS ARE DEC 3639C
RESISTORS ARE 15,000
RESISTORS ARE 1/4W,5%
CAPACITORS ARE MMFD
DIODES ARE 0, 664

0.,!4

, r D33
0-662
3
... ' r8_ l62

027
r?1
RI3

...

RIO

rols,ooo' '035

A .. ' rg~~62

Oil

...

R 14
100,000

R20
12,000

g~~2

"~~~62

" ~ , g:~62

10%

~
1500

B-15V

A.IOV(Al

C GNO
046
0-662
0411
0-1162
044
0-662
043
0-862
B-IIIV

R25
1,500

UNLESS OTHERWISE INDICATED:
RESISTO RS ARE 114 W; 5%
CAPACITORS ARE MMFO
DIODES ARE 0-664
USE THE ETCH BOARD Of' THE R203

TRANSISTORS ARE DEC 3639C

1::::::::::::::::::1

8-C5-5203-0-1

Triple Flip-Flop 5203, Circuit Schematic

No-__~.~_10_57_~Al_10_II_9___________________________~+~_10_61-,

~U RI6
"~027'~D30 100,000

RB
100,000

R4
100POO

R20
100,000

CI
100
1\

...
R6
R7
3,000 1:1,000

RI3
RI4
RIS
RI7
111,000 15,000 15,000 3,000

RIO
RI2
111.000 I!!,OOO

RIB
3,000

049
0-662

R22
R24
15,000 111,000

RI9
15,000

...... B-15V

UNLESS

RII
R9
15,000 15,000

OTHERWISE INDICATED:

RESISTORS ARE 1/4W; II %
CAPACITORS ARE MMFD
DIODES ARE 0- 664
TRANSISTORS ARE DEC 3639C

P..I.

I .....

H......

0111
...

to;;

OJ3

"'"

022

I.oiII

R21
111,000

p.,:0

p":2

"'"

M
tD58

toro

.....

leo

1:::::::::::::::: :::-:- 1USE THE ETCH BOARD OF THE R205

PARTS LIST A-PL-S201l-0-0

8-C5-5205-0-1

Dual Flip-Flop 5205, Circuit Schematic

5-8

'" I

R25
1,500

15,000

?o:7
.....

....

D46
..

V
j062

":' A-IOVlAI

R3
IOODO
15".

"~Oll

~~g?662

...

DEC
2884-21

....

F
)

A2
lepeo
15%

Ae ~
I,eeo
15'1'.

....

~010

~ ~O12

A7
a,ooo
15%

"0;4

"'"

,
~

~~oo ~~oo

0
)

OJ,

O~!I

'0415

~.O~

:~4

RI2
1,1500
15'1'.

...

~024

'1.:.3

~~~oo

Rli ~
1,1500
15".

Ale

)

r047

o~e

~rO;8

MFO ~ ,OS8
0-88

~
~

~O 34

~036

R21 ~
S,OOO
eo;.

~,g~:8

R22
1,1500
eo;.

~~200

I-lev

'033
R

8~,

0!,.2

....

'~i:o

b2~00

OjO

:,11

15".

'021
K

V
AI4 ~
3,000
15%

0-611

7r ,,g~:11
2gi~-21
~f i,f:.C~

~'B~2

" i:o
~022

~.040

~ 'B-~62

C,H,N,U
GNO

10,000

--<

DEC
2894-21

~ ~03e

015

'liI

.~
...
100,000
15 %

10,000

--<

All

bz.:,~oo b~200
E

,'8~~82
,~)'82
Ai
le,ooo
eo;.

'011

~ ~023

o~e

Ojl

~~}82 .....-- ,i~o
~
~

~l
10,000

.~
...
100
15%

'049

UN~ESS

OTHERWISE INDICATED:
RESISTORS ARE 1/4WI 10%
CAPACITORS AAE MMFO
DIODES ARE 0-664
TRANSISTORS ARE DEC 3639-C

USE THE ETCH BOARD OF THE R603

I ~::::;::::ii;:::::1

B-CS-S603-0-1

Pulse Ampli fi er S603, Circuit Schematic

~________~~______- .________~________._------~~------__~------~~------~---------,rj,-~---------i'----~.B-ISV

C2
.01
MFD

.-----9~--,......_---oC

C3
.01
MFD

RI6

I,we>

II
:

I :::::::::::::::::: I

B-CS-W005-0-1

-3V

II...STRATE
_____ .JI

UNLESS OTHERWISE INDICATED,
RESISTORS ARE V4W·, 8 ..
DlODE8 ARE 0-664

Clamped Load W005, Circuit Schematic

5-9

GND

AK
YIO AODR 13

Y'0 AOOR 12

AL.

AN
flO AODR IS

AOOR 14

AU
910 ADOR 17

AS
910 AODR 16

AA
.~

R2
10,000
10"'"

R9
100,000

liS
100,000

RI3
100,000

DI7

... ...

CI
.001
MFO

,g~62
"
"g:12

d!,,~1
OEC21194-28

...

C~A.
F~G.

F
RI
3,000

RI
1,1500

RII

....

016

RI
7,500

023

CI
100

0"i4

6Rl
BE

...

D21' ,. 022

J1.3

IIIIIIFO

041 042
D812 0112

~."
os-, 0112
0;0
....

.....

RIIII
100,000,

v.i51
"

~ioo,ooo

D71

.~~

~J...t.

Dr. DeO
08120612

0162

RIO
100,000

...; IrD95

(? QI7

,~g=2
... rg~~2

024

029

...
~

ENA"I"
AP

RII
7,!l00

RI2

RI4

RIS

RI7
7,1100

...

RII
1,000

050.

064

DiM

.~, T· ~ 1

....

~
ENS"O·

R21

Rill
7,1500

RZI

RIO

R32

RIS

~,s00

"~r'
"

D,!'7

0,?2

rl
RII
3,000

"089
0612

Af;ij....:....

C5
100

~g:~z

r¥Q19

"D811
D862

g~06~

'~g~06~

r- 0105
0662

~AH

SE~EC

10
SYNC.

r ol04
0662

0100

OIl
R44

R41
1,000

C6
.01
MFO

0101

AC .8C
ONO

0107 [
0662

,0103
0662

~, D94

~
....

LoL

~21
lC7
OI
MFO
-.7Y

D7i

"g::2

AE
ENB "I"

IIIIIIFO

R20
3,000

~14

QI2

"~~2
,,0112
0112

~t100

~.~~ D!7

rIo

~ D..47

0411

~g::2
033 : r~:2
...

[JOII
RIO
3,000

044'

RI4
100,000

094 095
0662 0662

....

-d~
100

~02

... ...

R411
100,000

RS9
100,000

012
DlI2

I" g~~2

~
....

030 031
0812 06112

R33
~ 'DM
100,000

R27
100,000

~
....

1:....

R22
' ~ D40
100,000

Rle
100,000

,,. D27

...

«(Q4

o'IB ole
0812 DlI2
• !to OS

RII
100,000

+IOV

R41

R4.
7,500

RII2

RII4
10,000
10"'"

Rill
7,500

R62
3,000

-3V
R65
1,500

R6I
7,500

·15V

"01

R24
100,000

R2.
100,000

~,"

~QIO

,~g=2
031

"~612

RQ
BY

R37
100,000

R43
100,000

Gr,, W

,,046
0112

"g:~2

R411
100,000

, ,gHz

rg~:z

0611
, 'tis82

O~:, rDIG2
IF'"

C~II.FL8. 075

.~~

8111
EN.OUT ~

10 PWR.CLR. 041

R211
7,1100

R31
3,000

R34
1,500

R3I
7,1500

098'

092

097

, ,091
0662
1 '090
0662

C6
100

....

r-;:r-

~~~" ~~~

.....

~099

096

........

r~G.

D73

...

D61"~

~04' ~OSl
R2I
7,1500

Btt

EN.IN

074

c..o

UNL.ESS OTHERWISE INDICATED:
DIODES ARE 0864
TRANSISTORS ARE OEC36598
RESISTORS ARE 111,000
RESISTORS ARE 114W, II ..

~"
...
...

07?, r

rg~2

034

R57
100,000

019
R40
1,1100

R42
7,500

R47

[l085
RliO
3,000

R5S
5,000

R1I6

R59

D-CS-W 104-0-1

R61

Multiplexer W104/ Circuit Schematic
5-11

P _ 0(')

TO
Pl 71!)
fL A "1.( 1

TJ
rl ; W_(I

IS CLR(J-3-2)

lie

10 PilR Cl R FOS
(0-3-1 )
(K"DS-A-I-2 )

TO
S9~

(~F09 .. A- 1-2)

I"'

(G~n

lOBUS 17
(G~4 )
RO e EN

I KFE9_A-I-2 )

~";F"-'

"I J ROI a)

A"T AP I GR
AP I SYNc( t)
ACT PL
PL 7 EN! _"

\J~

'::>
l'tPI. 3 EN

1-\

RPL I EN

RPL. 2. EN

'--

IO B'V<;:; 6

RPL 7 EN

~PI..

A AL( j)
ia

~Q ~y ~c."7:

RO 1 EN
(KFII9-A-I-2 )
AP I
Re
(J-2-2 )
TO
AP I 5 kG
(0-L-2)
loF 4P
(0-3-3 )

Y: _ B

~'I~C

t~~~%--~~~7-~~'-~--~r-~--'-~~~~~~~--~~r-~=-~--~~~:;~~--~~~~='~--~~~~~~--~-r~~-'~--------~~~~~~--~~~:~~~--~~~~~~~~~~~~~ tO~ ~~~~~~

.10 8U;; ~6

liP:

OBK I

IO 81j~ 7

.. - .. -

'I.O 'i:;,\l~ 9

CAF EN
( U-·3-1'

<"Q ':'>'<\-)c ¢
1<:Q ~ 'i:.N

BK( 1 )
(O--3-Z1
API S~ Re(l)
(KFBI-A-I-3)
CAF E~(B)(Oe3-1)

eLK SY"C( 1)
(003-2)
OCH SYNC( I )
(033-2 )
lOT 5594

CO-KF9S-A-I-3)

?L 'E \-)

rw~~o:.l

1E.e.g

I·
A PI ¢ <:'Q _ _ l_4-........______=<~

ID '"

ce-y

'CQ ,:>Y\JC,

IN 1\

-e. tl

MC.)

~G< ."Y\.lC ~ E
'CCl ":lY,H_ 4- \-I
'CQ -:''''I.Jc. 'S ~

0,- 4- (~)

'leGl, ,::>Y\-.J<!. G; '-

or'

i CKT

T!.Qo;:,Y\,)C.7~~

Ir'J-i¢a>~
I
t:.~q I

L !. __ .J
API 2 Ro. NEG

",C! 1 C1------~0I
T
e

t-:-:----<> PRE ;'."':L- ~,YNC(r;v

I
<:;:'?

"(~) ~

<:;:j-1..:.."-l=--_____K:.:.....

API STROBE
1'1 PI 3 RQ NEG_

APT SYNC(J)
3hR~(:)F1:

API
CLR API GR
H

REf NJ

o 21-1

R PL 3 EN
IO Sus /3(8)
PL 3 EN

~~ ~
-

PL 4 £ N

EU514(B)~O
BuS
~R/lil

PL 4 ~N

15(B)

RPL
7 EN

PL SEN

D-BS-KF09-A-1

Automatic Priority Interrupt, Block
Schemati c (Sheet 1)

5-13

RO a EN
RD t EN
AP I 2 RaId)

Pl 4 ~Q( 9)
i KF~~-A- I- t)
?l 1 ~B( A)

AP, 3 RCe,)

(KFn2·· A-J-1)

API 4T~G(I)8

AFI td I)
I ~F~9···A· t·;)

API

API : R~( I)~

OSK 7
TO
DBK t

Ie 3 r<)

(KH9·A·'I-I)
API R: 0 :~)

(KF)S-A·I-ll
AP: 1 HO
(U~2· ~)

AP I
Rq
(0-2-2 )

CAF EN (D93-11
Pl9(y) (KFOS-A-l-l)
TO
Pl7( ~)( ~F99-A-1-1)

~?r "'7 ~Q(\~ e.

A'?I: CD ~Q(¢)

C'i2'<
CI<T

i::'Q ¢e~

APrEN/iE3LE(1)

I ":;,ISI
\-\~¢

\-\
NI\

A'Pl: '=> ~Q(¢)~

A'?I. ¢~Q('6)~
\-\~9

l>.'?'I" 6 ~Q(I) l!.

?\_::,(¢) -J

I
~'?~.4 "i<!Q,(¢)

pC4C1

/:>"'P"t .... ~Q.0)'e:>

1:.

'D'O\'\. (0

o'O\'\. "::>

CBK4

l:'Q\E..\..I

A'?"! Ar'RQ(I)'5
.~

?C'~I

\.f\

A'?J.
p
¢'CQ ('5

~?"L c: ~Q

1~~V1

1:)'01< 3

,",,,,,,,U 1

I>..'?J: ~ 'RQ (S")

'?I...\ C<t)

\-\

L _---.l

'?\...z:.(¢)~

A-I

I>- '?I =. ~Q (~)

-.<..

....

I
I

~DBI< C.

DBK'

p..?"!. \ 'CQ
CAr;: "-IV \...

H REF NO
0-21-2

D-BS-KF09-A-1

Automatic Priority Interrupt I Block
Schemati c (Sheet 2)

5-15

This drawing anc! specifications, herein, art. the PO.
erty o~ Driltal EQuilXTlent Cotpol'8tion and Shall nat bI-

rel'rOoduced or copleQ or used, in wnoleorlnp.trtn.
the 1)a!>IS for the mlnuf.ac:t\n or satl ofit.n\awithoLlt
written permilsiOl'1.

£ (1)
l AP101I ENA8l
5522 (1)

AP I
6R (1)
AP I 1 GR (1).
AP I 2 GR (1)
AP I 3 GP (1)

0, ~~~_ ~~S

I NT SKP RQ SUS
PIG I SABl E

P~R CLR pes
(D- 3-1 )
: Q ClR (33-2)

I JP2P

AP I

(0- 3- 3)

I C BUS B~
(D- 2)
RG SYNC PTO
RQ SYNC 1
(KF09-A-l-l)

lOP 1( 1)
(D - 3- S)

C'_L'i':

r:1".:~~]

_..

Pl 7 EI-:
TO

lOT 5504

:0::: Lk/i;
CAr £N

IO CLR (8)

LAP:
l'\f

Pl S E~
( 0-2)

AP I BK RQ (1)

fP: SYNC(lJ

TD (394)
10 BUS 16(8)(D04)

lOP

AP I 3 EN
API BK RO 1(8)

: 0 BUS DB(S)

(OKFa9-A-I-I )
I D BUS 17

API 2 EN

~~:- r-.::,~'J
'

10 CLR

rOT 5502 (0)

STReBE

rv 1\1

Rill I

LJ~~J

(U- 3- 3)

OS 5 (0-3-1)
OS4P (0-3-1)
OS 3 (0-3-1)
8S 2 (0-3-1)
OSIP (0-3-1)
OS
(0-3-1)

PRE P>.'?l: ~"n..lC (\)
1='1-1 Eo\.,)

API EN/l13LE(I) u

ACT API GR
(KF09-A-I-I)

.,.\-CoEN

rvV
"-I<\-I

AP I SYNC( I)
(KF09-A-l-1 )

1<:c,4

I: 0 'el..l 5

\0('0)

l>,'?I. 'E.\.lA'OI...E (I)

AP IDEN
(002-2 )
TO
~PI3£N

a EN

AAI 1 EN

1:0

(002-2)

"'-'---OPL4(J)

l:0 'O\)':, ¢ (<:OJ
1='L¢'e\.l

IO'O\)":>I¢('O)
'17cN( B)
'D~,FB9-A-l-1 )

IO PiYR C'l.RPrJ.

'?I-~ ~\,l

A PI ~NflBLt(I) H

IO 'O\J"3 I 1 ('OJ
PL~"-I..l

I061)"::,lc(S)
'?L :;'iO.~)

?I-7iO\l
('OJ

r:O?4(1) ?

:1:0 'O\,)"::, \ " (S')
l:O '0-';':> 14('0)
?L'=>c\l

IO 'O\)':;, \"O{'B')

CAL (I)

+ - " - - - - - - - - - - - - - - - -......--~o l>-.'?'I. o;:,~\...
1\
Io 'O'J'S I,

--------<:;. CL R API GR

0'5':0

D"'::>4'?
T

-;,
0':;3
O""~

DS\?

O"::,¢

D-BS-KF09-A-l

Automatic Priority Interrupt 1 Block
Schematic (Sheet 3)

5-17

W'l~5

IlPI(4EI'I

,A 23
~--*''------'fiP.!

SEL .0
'PiR API RQ (I)

+=--_..... saL. fD

/ EN

SEt. I

SEL2

PTR,APt RClO

PTR /iPI RQ(I)

DPY FlPI RQ (I)

ro BOS J

---+--

SE.L 1

sus e.

API

liPI

rlJ RQ

j RQ

2 RQ

IO PWR CLR NE.&

IO PWRCLR.
P05.

SEt. PJ

PF IiPI RQ(lJ

PTR API RQ(I)

RDR F"LG(I)

CLI'( FLG.(I)

cov /lPT RGl (I)

fi'I

PTR API RGI (/J
~"""",-,'--_. PTR GR

!O SYNC. 51"'(6)
IO SYNC. sp_U-",---..~

- - - - - - Sl£L

API
RQ

liP!

3 EN

PF II PI
RQ (J)

RQ/J)

, - - - L - - - ' - - - - L . . , IIJ

IO pwR (LR NEG,

prR IIPI

IO SYNC. 5 P (8)

,ilL

WI¢4

PWR DN(IJ

IO 5 YNC SP (8)

IO ADDR /4

IO IlDDR

RDR F'LG (/J

AL.

WI!Z'4
1i8f}7

BV
IO /ll:>OR

ICYSYNC SpeS)

AI.

IO I'1DDR 14

:::1..K Ft.G(I)

Ie.

IO rlDDR 14

IIPI 3 GR(I)

It,

IO ADDR

I BLl

'I.O IIDDR 12.

/l8¢13

IIPI ~ GR (I)

COY I1PI
RQ (I)

IOADDR ,2.

API
3 RQ

w~f55
1123

VV~VJ5

Ac3

SF"

SF
L
VVGJ1}5

AZS

SE'LIli

PF -"IPI Rq 0)

API \Z GR(Iil) R

API 3 GR(9) K

SEL 2-

DPY liP! Rq(l)

PTR GR

-I;

ONLY NEEDED WHEN
OPTION

D-BS-KF09-A-1

KPi2I9-f/

INSTJ"ILLE"P

Automatic Priority Interrupt 1 Block
Schemati c (Sheet 4)
5-19

Digital Equipment Corporation
Maynard, Massachusetts

printed in U.S.A.