KF09A Automatic Priority Interrupt Instruction Manual

This document describes the KF09A Automatic Priority Interrupt (API) option for the PDP-9 Programmed Data Processor, designed to enhance its interrupt handling capabilities. The API system provides priority servicing for up to 28 I/O devices through 32 unique channels and 8 distinct priority levels. Four higher priority levels are dedicated to fast access for device-initiated service requests, while four lower levels are for program-initiated software routines.

A core feature is the use of hardware-generated entry points, or "trap addresses" (locations 40 to 77 octal in core memory), which allow device service routines to be entered directly, thereby reducing system overhead by eliminating the need for flag searches. The W104 Multiplexer module is crucial for assigning priorities among devices on the same level and routing trap addresses. API priorities supersede standard Program Interrupts (PI) and the main program, though higher-level operations like DMA, DCH, and RTC maintain precedence.

The manual details installation, operation, and the underlying logic of the API. It introduces several new IOT (Input/Output Transfer) instructions: ISA (Initiate Selected Activity) for enabling/disabling the API, requesting software level service, or raising priority; DBK (Debreak) for releasing the highest active priority level; DBR (Debreak and Restore) which also restores the system state after an interrupt; SPI (Skip on Priorities Inactive) for testing priority level changes; and RPL (Read Priority Level) for accessing API status bits.

Key programming considerations, such as dynamic priority reallocation and the strategic use of software priority levels for managing complex calculations without hindering high-priority data transfers, are also discussed. The API integrates internal devices like the paper tape reader, real-time clock, and power failure detection system into its priority structure, allowing for efficient, interrupt-driven operation.