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DEC-09-I3CA-D-68

March 1968

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Document:	TC02 DECTape Transport Control
Order Number:	DEC-09-I3CA-D-68
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Pages:	124
Original Filename:	http://bitsavers.org/pdf/dec/pdp9/DEC-09-I3CA-D-68.pdf

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INSTRUCTION MANUAL
TC02
DECTAPE TRANSPORT
CONTROL

DIGITAL EQUIPMENT CORPORATION. MAYNARD, MASSACHUSETTS

DEC-09-I3CA-D

TC02
DECTAPE TRANSPORT CONTROL
INSTRUCTION MANUAL
March 1968

DIGITAL EQUIPMENT CORPORATION. MAYNARD, MASSACHUSETTS

TABLE OF CONTENTS
CHAPTER 1
INTRODUCTION AND DESCRIPTION
1.1

PURPOSE AND SCOPE

1-1

1.2

EQUIPMENT DESCRIPTION

1-2

1 .2.1

Physical Characteristics

1-2

1.3

SYSTEM DESCRIPTION

1-3

1.4

REFERENCED DOCUMENTS

1-4

CHAPTER 2
OPERATION AND PROGRAMMING
2.1

DECTAPE SYSTEM

2-1

2.2

DECTAPE CONTROL TC02

2-2

2.3

DECTAPE FORMAT

2-2

2.3.1

Mark - Track Format

2-4

2.4

DECTAPE INSTRUCTIONS

2-7

2.5

STATUS A AND B REGI STERS

2-8

2.5.1

Status A Register Functions

2-8

2.5.2

Status B Register Functions

2-10

2.6

CONTROL MODES AND FUNCTIONS

2-11

2.7

CONTROL FUNCTIONS

2-11

2.7.1

Move

2-12

2.7.2

2-12

2.7.3

Read Data

2-13

2.7.4

Read All

2-13

2.7.5

Write Data

2-14

2.7.6

Write All

2-14

2.7.7

Write Timing and Mark Tracks

2-14

2.7.8

Enable and Interrupt Feature

2-15

2.7.9

Error Conditions

2-15

2.8

PROGRAMMED OPERATION

2-15

iii

CONTENTS (cont.)

CHAPTER 3
PRINCIPLES OF OPERATION

3.1

FUNCTIONAL DESCRIPTION

3-1

3.1.1

Information Flow

3-1

3.1.2

Command Flow Registers

3-5

3.2

SYMBOLS AND ABBREVIATIONS

3-6

3.3

DETAI LED DESCRI PTI ONS

3-11

3.3.1

Basic Read/Write Logic

3-11

3.3.2

Initial ization Operations

3-13

3.3.2.1

I/O Bus Interface

3-13

3.3.2.2

Timing Pulse Generation

3-14

3.3.2.3

Tape Unit Selection

3-14

3.3.2.4

Tape Motion Selection

3-15

3.3.3

Device Selection Logic

3-15

3.3.4

Status B Register and Skip Instructions

3-16

3.3.5

Interrupt Enable

3-16

3.3.6

New Unit/Motion Select

3-16

3.3.7

Counter Register

3-17

3.3.8

Window Register

3-18

3.3.8.1

Counter Sync level (C-SYNC)

3-18

3.3.8.2

Start Block Mark (MK BlK MK)

3-19

3.3.8.3

Data Marks

3-21

3.3.9

State Register

3-22

3.3.10

Function Selection

3-22

3.3.10.1 Move Tape (000)

3-23

3.3.10.2 Search (001)

3-23

3.3.10.3 Read Data (010)

3-24

3.3.10.4 Read All Functions (011)

3-24

3.3.10.5 Write Data Function (100)

3-25

3.3.10.6 Write All Function (101)

3-26

3.3.10.7 Write Timing and Mark Track (110)

3-26

3.3.11

Read and Write Sequences

3-27

3.3.12

Longitudinal Parity Buffer Operation

3-32
iv

CONTENTS (cont.)

3.3.13

Power Clear and Error Stop Logic

3-33

3.3.14

Increment CA Inhibit (+l-CA I NH)

3-33

3.3.15

Interrupt Request

3-33

3.3.16

Error Flags (EF)

3-33

3.3.16.1 Mark - Track Error (MK TRK)

3-34

3.3.16.2 Select Error (SEL)

3-34

3.3.16.3 Parity Error (PAR)

3-36

3.3.16.4 Timing Error (TIM)

3-36

3.3.16.5 End Error (END)

3-37

3.3.17

3-37

DEC tape Flag (DTF)
CHAPTER 4
INSTALLATION

4.1

INSTALLATION PROCEDURES

4-1

4.1. 1

Site Preparation

4-1

4.1 .2

Environmental Conditions

4-2

4.1 .3

Power and Cable Requirements

4-2

4.1.4

DECtape Signal Connectors

4-2
CHAPTER 5
MAl NTENANCE

5.1

MAINTENANCE EQUIPMENT

5-1

5.2

MAINTENANCE CONTROL PANEL

5-1

5.3

DEC MODULES

5-4

5.3.1

Module Locations and Complement

5-4

5.3.2

Circuit Description

5-5

5.3.3

Module Replacement Procedure

5-5

5.4

POWER SUPPLY 779

5-21

5.4.1

Mechanical Characteristics

5-22

5.4.2

. Power Supply Checks

5-22

5.4.3

Marginal Checks

5-22

5.5

POWER CONTROL PANEL (Type 832F)

5-23

5.6

PREVENTIVE MAl NTENANCE

5-24

5.6.1

Mechanical Checks

5-24

CONTENTS (cont.)

CHAPTER 6
ENGINEERING DRAWINGS

6.1

SYMBOLS AND DESIGNATIONS

6-1

6.2

DRAWING LIST

6-1

TABLES

1-1

DEC Documents

1-4

2-1

Mark Track Coding

2-6

2-2

TC02 DECtape Instruction List

2-8

2-3

Status A Bit Assignments

2-9

2-4

Status B, Bit Assignment

2-10

3-1

Engineering Drawing Identification

3-6

3-2

Symbols and Abbreviations

3-7

3-3

Counter Register Sequence

3-17

3-4

Sequence of Block Marks and Control States

3-19

3-5

Sequence of Events During Read Operation

3-28

3-6

Sequence of Events During Write Operation

3-30

5-1

Maintenance Equipment

5-1

5-2

Maintenance Control Panels (Switch and Indicators)

5-2

5-3

TC02 Module Complement

5-4

6-1

Engineering Drawing List

6-1
I LLUSTRA TlONS

1-1

System Configuration

1-1

2-1

Basic Six Line Tape Unit

2-1

2-2

Track Allocation Showing Redundantly Paired Tracks

2-3

Control and Data Word Assignments

2-4

Mark - Track Format

2-5

Status A Register, Format

2-9

2-6

Status B Register, Format

2-10

3-1

Information and Command Flow

3-1

3-2

Type TCOl DECtape Control Functional Block Diagram

3-3

ILLUSTRATIONS (cont.)

3-3

Read/Write Logic and Waveforms

3-12

3-4

Mark - Track Decoding (C-SYNC)

3-1S

3-5

Mark - Track Decoding (MK BLK MK)

3-20

3-6

Mark - Track Decoding (MK BLK START -210)

3-20

3-7

Mark - Track Decoding (MK BLK START -010)

3-21

3-S

Mark - Track Decoding (MK DATA 070)

3-21

3-9

Mark - Track Decoding (MK BLK END)

3-21

3-10

Error Check Flow Diagram

3-35

4-1

TC02 Unit Single Cabinet Installation Dimensions

4-1

4-2

TC02 Control, Cable Diagram

4-3

5-1

Maintenance Control Panels (Switch and Indicators)

5-2

GS53 Speed and Unit Circuit

5-6

5-3

GSS2 Manchester Read/Write Amplifier

5-7

5-4

R002 Diode Network

5-S

5-5

Rl13 Diode Gate

5-S

5-6

R201 Flip-Flop

5-9

5-7

R302 Delay (One-Shot)

5-9

5-S

R303 Integrating One-Shot

5-10

5-9

R401 Variable Clock

5-10

5107 Inverter

5-11

5111 Diode Gate

5-11

5-12

5123 Diode Gate

5-12

5-13

5151 Binary-to-Octal Decoder

5-12

5-14

5202 Dual Flip-Flop

5-13

5-15

S203 Triple FI ip-Flop

5-13

5-16

5205 Dual Flip-Flop

5-14

5-17

5602 Pulse Amplifier

5-14

5-1S

5603 Pulse Amplifier

5-15

5-19

W01S Connector Board

5-15

5-20

Wl03 PDP-9 Device Selector

5-16

5-21

Wl04 PDP-9 I/o Bus Module

5-17

vii

ILLUSTRATIONS {cont.}

5-22

W107 High Impedance Follower

5-19

5-23

W520 Comparator

5-19

5-24

W850 I/O Cable Connectors

5-20

5-25

Power Supply Type 779, Schematic Diagram

5-21

5-26

Power Control Panel Type 832F

5-24

viii

CHAPTER 1
INTRODUCTION AND DESCRIPTION

The Type TC02 DECtape Control, manufactured by Digital Equipment Corporation, is a
synchronizing and controlling unit used for transfer of information between Programmed Data Processor
PDP-9* and the TU55 DECtape Transport.
The DECtape system, consisting of the TC02 control and up to eight TU55 transports, is a
magnetic tape storage facility that stores information at fixed positions on magnetic tape, as in magnetic disc or drum storage devices; rather than at unknown or variable positions, as in conventional
magnetic tape systems. This feature allows the replacement of blocks of data on tape in an ordered
fashion without disturbing previously recorded information.

In particular, during the writing of infor-

mation on tape, the system reads format (mark) and timing information from the tape and uses this information to determine the exact position atwhich to record the information to be written.

Similarly, in

reading, the same mark and timing information is used to locate data to be played back from the tape.
A typical system (Figure 1-1) consists of a PDP-9, one TC02, and up to eight TU55 transports (only one transport can be selected at a time).
The levels of discussion in this manual assumes that the reader has previous knowledge of both
the PDP-9 processor and the TU55 DECtape Transport.

This manual includes references to the support-

ing documents listed in Table 1-1.

STATUS____

~TATUS

PDP-9

110

BUS

CONTROL
DATA

TC02
CONTROL

CONTRO,=_

TU55
NO.1

DATA

~-- ~

Figure 1-1
1.1

System Configuration

PURPOSE AND SCOPE
This manual describes the DECtape Transport Control TC02, includes maintenance information

in a form for easy use and quick reference, and is the major reference covering the TC02 control. Detailed explanations of standard products, such as modules, PDP-9 processor, and TU55 are contained in
the standard documents for these products.

+. PDP is the

registered trade mark for the programmed data processors manufactured by Digital Equipment
Corporation, J'vAIaynard, Massachusetts.

1-1

1.2

EQUIPMENT DESCRIPTION
The Te02 DECtape control logic occupies three Flip-Chip mounting panels. A maintenance

control panel (Figure 5-1) occupies the right-hand half of the upper mounting panel. This panel is
covered during normal programmed operations.
The Te02 is mounted one mounting panel space up from the bottom of the cabinet, and a
maximum of four TU55 transport units can be mounted above the TC02 in the same cabinet. (Additional
units must be mounted in another cabinet.)
The standard DEC computer has double doors on front and rear. Power supplies and power
controls are mounted inside the rear double doors on a full-width plenum door latched by a spring
loaded pin at the top. Module mounting panels are mounted behind the double door in front with the
wiring side facing outward. Fans at the bottom of the cabinet provide filtered cooling air. The rear
plenum door has blank panels in space not occupied by components. The TC02 and associated DECtape
TU55 Transports ~eceive power from the Type 779 Power Supply and the Type 832F Power Control.
1 .2. 1

Physical Characteri stics
Dimensions
TC02 Control:

15-3/4 in. high, 19 in. wide

TU55 Transport:

10-1/2 in. high, 19-1/2 in. wide, 9-3/4 in. deep

Cabinet:

69-1/8 in. high, 22-1/4 in. wide, 27-1/6 in. deep

Weight
TC02:

30 Ib

TU55:

65 Ib (rack mounted)

Cabinet:

620 Ib (with maximum equipment mounted)

Power Requirement
TC02:

115V, 60 cps, 4A. A Type 832F Power Control and a
Type n9 Power Supply are included with the TC02
Control (N9M transformer used for 50 cps).

TU55 Transport:

115V ± 10%, 60 cps, 2A maximum, 1.5A idle

Cabinet:

115V, 60 cps cource capable of delivering 20A

Tape Characteristics
Reel capacity:

260 ft of 0.75 in., 1 mil thick Mylar tape (empty reel:
2-3/4 in. diameter; loaded reel: 3-3/4 in. diameter)

Density:

350 ±55lines per in.

Motion:

Bidirectional

Addressable blocks per reel:

11008 (576 10 ) 18-bitwordsinblocksof256 1O words

1-2

Word Transfer Rate
One tape line is read or written every 33-1/3

'"'S.

An 18-bit word is read and assembled or disassembled and written in 200

'"'S.

In reverse direction, the transfer rate varies by 30% as the effective reel diameter changes.
Addressing
Mark and timing tracks allow searching for a particular block.
Start time:

375 ms approximate

Stop time:

375 ms approximate

Turn around time:

375 ms

Input Signals to Transport from Control
Commands:

FORWARD, REVERSE, GO, STOP, ALL HALT

Unit select:

Select unit 1 through 8

Information:

Analog write signals to the recording head

Output Signal from Transport to Control
Control:

WRITE ENABLE

Information:

Analog read signals from recording head

Environmental Conditions

1.3

Thermal Dissipation:

2000W

Operati ng Temperature:

500 to 900 F ambient

Humidity:

10% - 90% relative humidity*

SYSTEM DESCRIPTION
The TC02 consists of tape control logic, which under direction of the PDP-9, controls the

operation of up to eight TU55 DECtape Transports. The TC02 transfers data between the PDP-9 core
memory and the selected tape transport.

To transfer data, the TC02 uses the data channel facility of

the PDP-9; the WC (word count) register specifies the record length, the CA (current address) register
spec ifi es the core memory address of the data tran sfer •
During both input and output operations, the TC02 receives data and control information from
the processor and generates the appropriate signals for the selected transport to execute the programmed
commands. Binary information is transferred between the tape transport and the computer as one 18-bit

* Tape manufacturer recommends 600 F - 800 F and 40% - 60% relative humidity for best tape performance.
1-3

computer word every 200 !-IS.

In writing the TC02 disassembles the 18-bit computer word into six suc-

cessive 3 -bit words to be written on tape. During reading, the TC02 assembles six successive 3 -bit
words into an 18-bit computer word.

Transfer of an 18-bit word always occurs in parallel. As the

start and end of ec)ch block are detected, the TC02 generates a DECtape control flag signal (DTCF) to
cause a program interrupt in the computer.
The program interrupt is used by the computer program to determine the block number. When
it determines that the next block is the one selected for transfer, it selects the read or write control
function.

Each time a word is assembled, or DECtape is ready to receive a word from the computer, the

control produces CI data flag (DF) to request a data break. Therefore, when each 18-bit computer word
is assembled the data break initiates a transfer.

By using the mark-track decoding circuits and the data

break faci lity, the main computer program can continue during tape operation.
1 .4

REFERENCED DOCUMENTS
The DEC documents listed in Table 1-1 contain material which supplements the information in

this manual. These documents may be obtained from DEC field offices or from the main office in
Maynard, Massachusetts.
Table 1-1
DEC Documents
Document
No.

Title

Description

C105

Digital Logic Handbook

Specifications and descriptions of the FLlPCHIP modules.

C100

System Modules

Specifications and descriptions of basic
system modules and power supplies.

F95

PDP-9 Users Handbook

Programming and operating information for
the computer including brief instructions on
TC02 control.

F97

PDP-9 Maintenance Manual

Complete information on the internal operation of PDP-9 logic, memory, basic in/out,
and options.

H- TU55

TU55 Maintenance Manual

Transport drive logic and internal operations.

In addition to the documents listed in Table 1-1, a complete set of library programs are
available.

1-4

CHAPTER 2
OPERATION AND PROGRAMMING

This chapter contains information required for operation and programming of the TC02. Included are a description of the format of information on the DECtape magnetic tape, and the modes of
operation used in programming TC02 operations.

General operating information for TU55 transport is

contained in the TU55 Maintenance Manual.
2.1

DECTAPE SYSTEM
DECtape uses a lO-track read/write head. Tracks are arranged in five nonadjacent redun-

dant channels:

a timing channel, a mark channel, and three information channels. Redundant record-

ing of each character bit on nonadjacent tracks materially reduces bit dropout and minimizes the effect
of skew.

Series connection of corresponding track heads within a channel and the use of i\A,anchester

phase recording techniques, rather than amplitude sensing techniques, virtually eliminate dropouts.
The timing and mark channels control the timing of operations within the TC02 control unit
and establish the format of data contained on the information channels. The timing and mark channels
are recorded prior to all normal data reading and writing on the information channels. The timing of
operations performed by the tape drive and some control functions are determined by the information on
the timing channel. Therefore, wide variations in the speed of tape motion do not affect system performance.

Information read from the mark channel is used during reading and writing data, to indicate

the beginning and end of data blocks and to determine the functions performed by the system in each
control function.
During normal data reading, the TC02 control assembles 18-bit computer length words from
six successive lines read from the information channels of the tape (Figure 2-1). During normal data
writing, the control disassembles la-bit words and distributes the bits so they are recorded on six successive lines on the information channels. A mark channel error check circuit assures that one of the
permissible marks is read in every six lines on the tape.

, •
:...r-....s+....... .... I .... ....
, , 0 I"'ARK TRACK CODE I , , 0 0 0 , , I
MARt<. TRAC K )
, I , 0 , 01 " 61 '1 "I " , 0 , 0 , , 0
"I '6
, , , , , ,
'NFOR-{z< , , , ,II 4 CONTROL
0
1
WORD
.. I
zl ,
,
, , 0 0 ,
,
,
0
"
"
~
,

LiM LIne Lint LIM Line
Z
4

TIMING TRAC KLJ.

Ln•

I .......... : ....

DATA OR

MATtON
TRACKS

RfDUNDENT
TRACKS

NOT
SHOWN

f4--- •L,_ -----Figure 2-1

Basic Six Line Tape Unit

A tape contains a series of data blocks that can be of any length wh ich is an even number of
18-bit words. Block length is determined by information on the mark channel.

2-1

Usually a uniform block

length (256 10 for the PDP-9) is established over the entire length of a reel of tape by a program which
writes mark and timing information at specific locations. The ability to write variable -length blocks
is useful for certaiin data formats. For example, small blocks containing index or tag information can be
alternated with large blocks of data. The maximum number of blocks addressable is 4096.
Between the blocks of data are areas called interblock zones. The interblock zones consist
of 30 lines on tap1e before and after a block of data. Each of these 30 lines is divided into five 6-line
control words.
Block numbers normally occur in sequence from 1 to N. There is one block numbered 0 and
one block N + 1. The total length of the tape is equivalent to 849,036 lines which can be divided into
any number of blocks up to 4096 by prerecording of the mark track.

Normally, 57610 blocks of 256 10

words each are prerecorded for PDP-9 DECtape.
2.2

DECTAPE CONTROL TC02
A maximum of eight TU55 transports can be connected to a TC02. Of the PDP-9 data chan-

nels available, DECtape is assigned to channel 0 (core memory locations 30 and 31).
C(30) = Word Count (in 2s complement form) -WC
C(31) = Current Address Register - CA
Data transfers can take place to or from only one transport at a time at a rate of one word
every 200 fJS (1 block of 256 10 words every 53 ms), after the desired block has been found.

Since the

CA is incremented before the data transfer (except in search where the CA is not incremented), the
initial contents should be set to the desired initial address minus one. The WC is also incremented before each transfer and must be set to the 2s complement of the desired number of data transfers. In this
way, the word trclnsfer which causes the word count overflow is the last transfer to take place.
The number of lOTs (input/output transfer commands) required for the TC02 is minimized by
transferring all required control data (unit, function, mode, direction, etc.) from the accumulator (AC)
to the control using one set of lOTs, and similarly, transferring all status information (the above plus
status bits, error flags, etc.) into the AC from the control by a second set of lOTs.
To provide for automatic parity checking during the READ DATA function, a 6-bit parity
check character is computed and recorded by the DECtape control for every block recorded during the
Write Data function. The 6-bit parity check character is computed by the complement of the exclusive
OR (logical equivalence) of the reverse parity check character and every six bits of every data word.
2.3

DECTAPE FORMAT
The format of the DECtape is shown in Figure 2 -2 and provides 10 tracks, 5 tracks redun-

danty recorded;

i.e., three pair of tracks for data and two pair for timing and mark information. A

lO--track recording head reads and writes the five duplexed channels.
The prerecorded timing track synchronizes read/write operations. The location of the timing
tracks along the edges of the tape permits strobing on the analog sum of the timing track signals

2-2

(minimizing tape skew effect) and thus reading the data tracks when they are in the most favorable
position. The location of the data tracks in the middle of the tape also minimizes skew effect.

10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0I

TIMING TRACK I

MARK TRACK I

INFORMATION TRACK I

(11010111000'01111

INFORMATION TRACK 2

INFORMATION TRACK 3

)1010'

0110

INFORMATION TRACK lA

(

(SomegslTl)

INFORMATION TRACK 2A

010

1010

00'
1

)1
~

3/4 "

10101011010100011101110

(Same Ot IT 2\

REOUNDANT

:~:~Ro~~'~ TRACK 3
MARK TRACK IA
(50_01 MTI)

~:~ i~~CK I>

Figure 2-2

TRACKS

00011100011'00011100011

00 00000 00 0 00000000000 00
Track Allocation Showing Redundantly Paired Tracks

Data is recorded by the Manchester method in which a prerecorded timing track synchronizes
read/write operations. When writing on the tape, the write amplifiers supply the maximum current in
either one direction or the other (non -return to zero, NRZ). To write a pulse, the polarity of the write
current is reversed, and the polarity of the pulse that is produced depends on whether the write current
underwent a positive or negative transition.

The timing track is prerecorded wi th al ternate positive

and negative transitions at fixed time intervals. The negative transition is used only during writing and
is a signal to load the write buffer. The positive transition is used during both reading and writing.
During writing, this transition is a signal to switch the polarity of the write current in all write heads.
If a ZERO is being written, the current, which starts out positive for writing ZEROs, is switched to
negative resulting in a negative transition.

If a ONE is being written, the current starts out negative

and generates a positive transition when switched to positive. During reading, the positive transition
of the timing track is a signal to strobe the data and mark track read -amplifier outputs into the read
buffer.

If a positive transition is sensed at strobe time, a ONE is placed in the buffer; otherwise a

ZERO is strobed in.
Because the strobe is a relatively narrow pulse, the system is not affected by noise outside
the strobe time. At strobe time, all data signals are negative pulses representing ZEROs or positive
pulses representing ONEs. These pulses are all at their peaks. To have any effect, a noise pulse must
be large enough to reverse the polarity of a data pulse.

Data can be written immediately adjacent to

previously written data because the timing is controlled by the timing track that is written on the tape.
Information is stored on the tape in block form (Figure 2-3). Block length is flexible and
determined by information on the mark-track. A complete reel of tape (849,036 lines) can be divided
into any number of blocks up to 4096. As stated earlier, a uniform block length is established over
the entire length of a reel of tape by a program which writes mark and timing information at specific
locations. The ability to write variable-length blocks, however, is useful for certain formats, for example, where small blocks containing index or tag information need to be alternated with the large
blocks of data.
2-3

...j

ONE COMPLETE REEL-260 FT 4096 BLOCKS (MAX,)

~~,~~=t~I~"P!fj

ry-

1 4 - - - - - ONE BLOCK 26610 18 BIT WORD LOCATIONS ---~

TIMING TRACK
MARK TRACK

DATA I
DATA 2
DATA :3

'"
cr

''li" 'li '"z '" '"z '"z
0

if
0

:il0

'"
'" '" '"
'"
'"0z '"z '"0z '"0z '"z '"z '"0z '"z '"0z
0

10 DATA WORDS

Figure 2 -3

REDUNDANT
TRACKS

NOT
SHOWN

C~~~~~L _____

Control and Data Word Assignments

Each block contains data and control words as shown in Figure 2 -3. These of course are
assembled by the TC02. Control words separate the data portions of adjacent blocks and record address
and checking information. Each con trol or data word occupies six Iines on tape, i.e., 18 bits (see
Fi gure 2 -1) .
2.3.1

Mark - Track Format
One of the five DECtape channels is reserved for control information exclusively. The con-

trol codes are stored serially, six bits per code. The mark track contains these 6-bit codes (see
Figure 2-1), which initiate controls to raise flags in the program, request data breaks, detect block
mark numbering and block ends, and protect control portions of tape (see Figure 2 -4). The TC02
automatically identifies these codes to control transmission of data. The mark track also provides for
automatic bidirectional compatibility, variable block formatting, and end -of-tape sensing.
During all tape processing functions except recording of the timing and mark track, a single
mark-track bit is read from each line of tape, regardless of whether the information is being read from
or written onto the data tracks; and each tape line in both the information and mark tracks is positioned
at the center of the right polarization in the timing track, as shown in Figure 2-1. The six lines on the
tape that contain the mark code in the mark track are designated as a mark frame.
A given change of polarization on tape read in one direction produces a pulse opposite in
polarity to that produced by the same change when tape is read in the opposite direction. Consequently,
a mark code read in reverse of the direction in which it was recorded has the order of bits reversed and
the bits complemented.

For example, a mark code read forward as 100101 is read as 010110 in reverse.

This correspondence is termed the complement obverse or the complement image. Every 6-bit code has
one and only one complement obverse which is constructed by complementing all bits and reversing their
order. Therefore, the complement obverse of the complement obverse is the original code itself.

octal notation, the complement obverse of any pair of digits is constructed by reversing the order of
digits, then performing the following transformation on each:

0-7

1 - 3

2 - 5

3 - 1

4 - 6

5 - 2

6 - 4

7 - 0

2-4

MOTION OF TAPE

ONE BLOCK

,.
2
MARt< TRACK

01001~010010

N
I
til

P
C
C

lNTERBLOCK SYNC. MARK

010101 010110 011010 00 I OOC 0010 ~COOIOOO 001000 1 11 000 111000

CH.l
CH.2
CH.3
REVERSE
END MARKS

NEXT
I BLOCK
I MARK

DATA
7

1 1 1011 1 1 10" 11 1 0 1 1 111011 101001 1 00 1 0 1 ~ I 0 I 0 I 0101 10

\~1I011101l01

P
C
C

t t

FORWARD
END MARKS

INTERBLOCK SYNC. MARK
REVERSE BLOCK MARK IN 1)

FORWARD BLOCK MARK (Nl)
REVERSE GUARD MARK

GUARD MARK

LOCK MARK

REVERSE LOCK MARK

REVERSE PCC MARK

PCC MARK

REVERSE FINAL MARK

FINAL MARK
PRE-FINAL MARK

REVERSE PRE-FINAL MARK
DATA MARK SHOWING BIT ORIENTATION OF lB BIT WORD ON TAPE

ADDITIONAL DATA MARKS

PCC·6 BIT PARITY CHECK CHARACTER IHARDWARE COMPUTED)

Figure 2-4

Mark - Track Format

The transformations indicate that there are eight octal codes which are their own complement
obverses:

07,13,25,31,46,52,64, and 70. All other possible combinations of two octal digits

(there are 56) are different from their complement obverses. As shown in Table 2 -1, the complement
obverse of any mark is designated by the minus sign (e.g., mark G = 51 has the complement obverse

-G = 32).
Since the DECtape system allows reading and writing in both directions of tape motion, the
mark track must be coded to present the same information when entering a block from either direction.
The marks at the end of a block are the complement obverses of the marks at the beginning, in reverse
order.

For example, if the control reads the marks E, M, -G as the first three marks beginning a

block in forward motion, then it will read G, -M, -E, in that order, as the last three marks of the same
block.

In reverse motion, however, the control sees the complement obverse of the contents of the

mark track; thus the first information, when reading the block in reverse, is -(-E), -(-M), -(G),
which is identical to E, M, -G.
All marks used in the standard DECtape format are listed in Table 2-1. Only 10 valid codes
exist even though a given code may have different designations. Some of these marks are not required
for the operation of the Type TC02 DECtape control.
Table 2-1
Mark Track Coding
Octal Code

Function

C (Check)

Signifies the end of a mark frame whose first two lines
were the forward parity check group.

-C (Reverse Check)

Signifies that the 6-bit reverse longitudinal parity
check group is contained in the control unit read/
write buffer and that the beginning of the data portion of a block is in the forward direction.

E, -D (Data)

In both forward and reverse tape motion, the data
mark occupies all mark frames in the data portion of
the block except for the final and prefinal marks.
The number of data marks is limited only by the
Iength of tape.

E, (Interblock)

The first and last mark of every block (no-op mark).

End (Forward End)

Indicates the end zone of tape in forward direction.
The forward end mark is positioned approximately
10ft from actual tape end.

-END (Reverse End)

Indicates the end zone of tape in reverse direction.
The reverse end mark is positioned approximately
10ft from end of tape.

F (Final)

Signifies that the last word read from the data portion
of the block is in the read/write buffer and data
buffer. Signals that the next frame begins with the
6-bit forward longitudinal parity check group.

-F (Reverse Final)

Signifies that the last word read from the block, in
the reverse direction, is in the read/write buffer
and data buffer.

Mark

2-6

Table 2 -1 (Cont)
Mark Track Coding
Mark

Function

Octal Code

G (Guard)

- G (Reverse Guard)

L (Lock)

Indicates the first of four octal 10 marks.

- L (Reverse Lock)

Protects subsequent records in the event of mark -track
errors.

M (Forward Block)

Signifies the start of a block and indicates that the
block number is contained in the TC02 control.

-M (Reverse Block)

P (Prefinal)

In the forward tape direction, the prefinal mark is the
next to last mark in the data portion of a block. It
is the first of four marks using octal code 73.

- P (Reverse Prefinal)

In the reverse tape direction, signifies the next to last
mark in the data portion of a block.

Performs same function as -L (reverse lock).

The standard mark track uses the serial code of 6-bit characters to divide the tape into
words. Codes are written on the mark track opposite word locations to identify the type of information
stored at that location on tape.

Block addresses are written for both forward and reverse directions

and identified by two types of mark codes (the second is the complement obverse of the first). A
checksum is written at each end of the block. The hardware computed checksum is the 6-bit logical
equivalent (i .e., the complement of the exclusive OR) of each six bits written on tape plus the reverse
checksum previously recorded.

By including the reverse checksum in the computation, the block may

be read in either direction at a later time without an error. The control uses the final marks to establish synchronism and raise block-end flags. Data marks locate data words.
2.4

DECTAPE INSTRUCTIONS
The seven basic lOT instructions used in the programming of the PDP-9 for TC02 operations

are listed in Table 2-2, with octal code assignments and a description of the instruction operation.
These instructions apply to two functional groups within the TC02, designated as status A and status B,
and are used to cI ear, read, and load the status A and B regi sters. These two regi sters are used to
govern tape operations and provide status information to the computer programs.

2-7

Table 2-2
TC02 DECtape Instruction List
Mnemonic

Octal Code

DTCA

707541

CI ear status A regi ster. The 0 ECtape con trol and error fl ags
are undisturbed (DTF and EF).

DTRA

707552

Read status A register. The AC is cleared and the content of
status A register is ORed into the accumulator.

DTXA

707544

XOR status A register. The exclusive OR of the content of
bits 0 through 9 of the accumulator and status A is loaded
into status A register, and bits 10 and 11 of the accumulator
are sampled to control clearing of the error and DECtape
flags, respectively. Any time this command is given with
AC bits 0 through 4 set to 1, the select delay of 120 ms will
be incurred, while the new mechanical motion begins.

DTLA

707545

Load status A regi ster. Combines action of DTCA and DTXA
to load ACO through 9 into status A register. Bits 10 and 11
control clearing of error and DECtape flags, respectively.

DTEF

707561

Skip on error flag. The state of the error flag (EF) is sampled.
If it is set to 1 the content of the PC is incremented by one
to skip the next sequential instruction.

DTRB

707512

Read status B. The AC is cleared and the content of status B
is ORed into the accumulator.

DTDF

707601

Skip on DECtape flag. The state of the DECtape flag (DTF)
is sampled. If it is set to a 1, the content of the PC is
incremented by one to skip the next sequential instruction.

2.5

Description

STATUS A AND B REGISTERS
All 10 command bits (0 through 9) of status A register may be sensed, set, or changed via

lOTs.

Bits 10 and 11 of the AC are not retained by status A but enable or disable the clearing of the

DECtape and ERROR flags. The bits in status B register may be sensed and cleared by lOTs.
To issue a DECtape command, the command bits 0 through 9 of status A register are set as
desired by bits 0 through 9 of the AC with bits 10 and 11 set to O. Bit 11 of B register is set when a
DTF occurs and must be cleared before the next DTF to avoid a timing error. When any error occurs,
bit 0 of B register and the corresponding 'bits 1 through 5 will be set depending on the error. This bit
must be cleared to avoid further interrupts on the same condition. All error flags (status B register) are
cleared by issuing a DTXA instruction with AC bit 10 set to O.
2.5.1

Status A Register Functions
Figure 2-5 is the format for the status A register. This register contains three unit select

bits, two motion bits, one mode bit, three function bits and three bits which control the flags. The
bit assignments for the status A register are provided in Table 2 -3.

2-8

o I 1 I 2 I 3
TRANSPORT
UNIT SELECT

I4 I5 I6

I8 I9

MOTION
MODE

OECTAPE FLAG
ERROR FLAG
ENABLE
INTERRUPT FLAG
FUNCTION

Figure 2-5

Status A Register, Format

Table 2-3
Status A Bit Assignments
Function

AC Bit

Transport Unit Select

0-2

Conditions
Octal Code
000
001
010
011
100
101
110
111

Motion

Mode

Unit
--

1
2
3

4
5
6
7

0= Forward (FWD)
1 = Reverse (REV)

0= Stop motion (STOP)
1 = Start motion (GO)

o = Normal mode (NM)
1 = Continuous mode (CM)

Function

6,7,8

Octal Code

Operation

000
001
010
011
100
101
110
111

Move
Search
Read data
Read all
Write data
Write all
Write timing and mark track
Unused (causes select error)

Enable the interrupt

1 = Enable DECtape control flag DTF and
EF to cause program interrupt

Error flag

o = Clear all error flags
1 = Error flags undisturbed

DECtape flag

0= Clear DECtape flag
1 = DECtape flag undisturbed

2-9

2.5.2

Status B Register Functions
Figure 2-6 shows the format of the information in the status B register. This register contains

6 bits of error status information, and the DECtape flag bit. Table 2-4 lists the function of the bit
assignments.

o I 1 I2

ERROR FLAG
MARK-TRACK ERROR

110 111

~~
I

~-----

END OF
TAPE ERROR

DECTAPE FLAG
UNUSED

' - - - - - - - - - - - - - TIMING ERROR

SELECT ERROR - - - - - - - - - '
PARITY ERROR - - - - - - - - - - "

Fi gure 2 -6

Status B Regi ster, Format

Table 2-4
Status B, Bit Assignment
Function

AC Bit

Conditions

Error FI ag (EF)

1 = Detection of any nonoperative condition by the
control as listed in the error functions described in AC
bits 1 through 5 of this table. These conditions stop
transport motion except for parity errors.

Mark - Track Error
(MKTRK)

1 = Information read from mark track is erroneously
decoded.

End of Tape Error
(END)

1 = the end zone on either end of tape is over the read
head.

Select Error (SE)

This error occurs 5 fJS after loading status A register to
indicate one or more of the following conditions.
(a) The unit select code specified does not correspond
to any transport select number or is set to more than
one transport.
(b) Specifies a write function when the WRITE ENABLE/
WRITE LOCK switch is in the WRITE LOCK position.
(c) Specifies an unused function code (111) bits 6 through
8 of the status A register.
(d) Specifies any function except Read All with the
maintenance control panel RDMK/WRTfv\/NORMAL
switch in the RDMK position.
(e) Specifies any function except Write TIming and
Mark Track with the RDMK/WRTfv\/NORMAL switch
in the WRTM position.

(f) Specifies the Write Timing and Mark - Track function
with the RDMK/WRTfv\/NORMAL switch in a position
other than WRTM.

2-10

Table 2-4 (Cont)
Status B, Bit Assignment
Function

Conditions

AC Bit

Parity Error (PAR)

1 = Error occurs during a Read Data function if the
longitudinal parity over entire data block including
reverse checksum and checksum, is not equal to 1.
If a parity error is to be set at the end of a block,
it will be set at the same time the DTF is set. During
CM if a word count overflow does not occur at the
end of a block, the harity error is set at the end of
the block in which t e parity error occurs. The parity
error cannot be set after the DTF is set.

Timing Error (TIM)

1 = Program fault caused by one of the following conditions:
(a) A data break request is not answered within 66 !-IS
±30% of the data break request.
(b) The DTF was not cleared by the program before the
control attempted to set it.
(c) The read data or write data function was specified
after the current data block has been entered to
prevent incomplete data block transfers.

DECtape Flag (DTF)

2.6

6,7,8,9,
10

Unused

1 = DECtape operation complete

CONTROL MODES AND FUNCTIONS
The TC02 control unit operates in either the normal mode (NM) or continuous mode (CM) as

determined by the mode bit (5) in the status A register. In the normal mode, the data transfer and flag
indications are controlled by the format of the information on tape. In the continuous mode, data transfer and flag indications are controlled by a word count (WC) read from core memory and by the tape
format.
The normal mode differs from the continuous mode primarily in the time at which the DECtape
flag (DTF) is set. The DECtape flags which occur in the normal mode are inhibited in the continuous
mode until a word count overflow has occurred. In both modes, data break requests occur only when a
word count overflow has not occurred during the currently specified function.
2.7

CONTROL FUNCTIONS
The seven functions available with the TC02 and their octal numbers, as specified by the

bits 6 through 8 of the AC are as follows.

2-11

Function

Octal No.

Nbve
Search
Read Data
Read All
Write Data
Write All
Write Timing and Mark Track
Unused at present (select error if given)

0
1
2
3
4
5
6
7

All functions take place in either direction and in either normal mode (NM) or continuous
mode (CM). NM differs from CM only in the fact that the DECtape flag (DTF) occurs at more frequent
intervals in NM. The DTF settings which occur in NM are eliminated in the CM until word count
overflow (WC) has occurred.

2.7.1

Move
The Nbve function simply sets the selected unit in motion (forward/reverse). NM and CM

have no meaning and are ignored in this function alone. When the tape enters either end zone* (i .e.,
beginning of tape (BOT) and end of tape (EaT)), and the unit in question is selected:
a. The error flag (EF) is set.
b. The EaT bit (bit 2 of status B register) is set.
c. An interrupt occurs. **
A program check on the forward/reverse motion bit (AC bit 3) of the status register wi II determine whether EaT or BOT occurred. If the unit is deselected, however, the tape runs off the reel
with no flags raised and no interrupt. In order to stop a selected unit at any time, the GO bit (AC
bit 4) must be set to O. * Once a unit is deselected, status information pertaining to that unit is no
longer accessible unless it was saved by the program prior to deselection.

2.7.2

Search
The Search function provides the capability of random access of data blocks on DECtape.

This function is used to locate the number of the block to or from which data transfer will occur. In
normal mode at each block mark until EaT occurs, the DTF is raised and an interrupt occurs. The
block number is automatically transferred by the hardware into the memory location specified by the

* If either end zone is entered during turn around or during stopping of tape, the EaT bit is not set and
no interrupt occurs.
**AII references to the occurrence of interrupts assume both that the program interrupt is on, and
the DTF and EF have been enabled to the program interrupt or API (i .e., bit 9 of status A register
is set to a 1). If either of these is not true, flags are raised and status bits are set (and may be sensed
and/or cleared), but no interrupt occurs.

2-12

CA {current address}. The CA must have been set previously by the program, but the contents are not
incremented. The WC is incremented at each DTF, and the program must clear the DTF bit in the status
register and check the block number until the desired one is found.
In continuous mode, the WC is set to the 2s complement of the number of blocks to skip. At
each block mark, the block number is read into the memory location specified by the CA which is not
incremented. The DTF is raised only at the block mark atwhich the WC overflows. At that time, an
interrupt occurs. Continuous mode provides a virtually automatic DECtape search.
2.7.3

Read Data
The Read Data function is used to transfer blocks of data into core memory with the transfer

controlled by the standard tape format. The standard block length is 256 18 -bit words. For this and
all following functions, the CA register initially must be set to the transfer memory location - 1 because the CA register is incremented just before each word transfer. The WC register is also incremented prior to each word transfer so must be set to the 2s complement of the number of words to be
transferred prior to the transfer. Data may be transferred in forward or reverse but it is transferred into
(from) ascending addresses in memory.
Any number of words equal to or less than 1 block may be transferred in NM. The DTF is
raised and an interrupt occurs at the end of each block. The DTF must be cleared before the beginning
of the next block (i .e., 1.7 ms) to avoid an erroneous timing error. When partial blocks are transferred, data transmission ends with WC overflow {i.e., the word which causes the WC overflow is the
last one transferred}.

The remainder of the block is read and parity checked, however, before the DTF

and interrupt occur.

Tape motion continues until the GO bit is reset to 0 by the program. If the GO

bit is not reset to a 0 or a new function specified before the end of the next block, a timing error will
occur. READ DATA in NM is intended primarily for single, 256-word, block transfers. If any other
number of words is to be transferred, it is advantageous to use CM. If the programmer chooses to use
NM for any other number of words, however, the program must check for WC overflow of each interrupt
since there is no other way to determine when to stop the tape or change to another function. When
the WC overflow occurs, it is essential that the function be changed or the GO bit set to O. Otherwise
transfer begins again {the lOT to clear the DTF implicitly specifies the same function again} at the next
block {or next word for the ALL BITS functions} since WC = 0000008 is valid.
Any number of words may be transferred in CM. However, the DTF and an interrupt occur
only once after a WC overflow and an end of block.

The comments concerning tape continuation apply

in CM as well as NM.
2.7.4

Read All
The Read All function allows information to be read from an unusually formatted tape

essentially reading all data channels recorded on DECtape regardless of the mark -track value. DUTing
the Read All function the DECtape control does not distinguish between different marks recorded on the
mark track-- except to check for mark-track errors (MKTK) and end of tape (END).

2-13

In normal mode (NM), the DTF is raised and causes an interrupt at the end of each 18 -bit
word transfer. Data transfer stops after WC overflow, but tape motion continues until the GO bit is set
to 0 or a new function is specified (in both NM and CM). If the DTF is not cleared after each word
transfer, a timing error occurs at the end of the next word (i .e., 200 fJS later).
For continuous mode, the DTF is raised and causes an interrupt at WC overflow only. If this
interrupt is ignored no more data transfers occur but tape motion continues to EOT.

2.7.5

Write Data
The WRITE ENABLE switch on the TU55 must be in WRITE ENABLE position for all Write

functions. All the details of the Read Data function description apply with the following exceptions.
In normal mode, the DTF is set to a 1 at the end of each block. If WCO did not occur in the
block just ended and a new function is specified, the next block will be written {provided the DTF has
been cleared}. If WC overflow did occur in the block just ended and no new function is specified, the
tape continues to move but the writers are disabled. In both CM and NM, when partial blocks are
written, data transfer from core to DECtape stops at WC overflow. The 0000005 are written in the remaining data words of the block and the parity check character is computed over the entire block and
recorded.
In continuous mode, the DTF is set at the end of the block in which WC overflow occurred.
Therefore, if no new function is specified, the tape continues to move but the writers are disabled.
2.7.6

Write All
All the details of the Read All function description apply. The Write All function is used to

write an unusual format {such as block numbers on DECtape after timing and mark tracks have been recorded}.

The word which causes WC overflow is the last one written in NM or CM.

The tape con-

tinues to move but the writers are disabled.
NOTE
Change of function must be delayed for 90 fJS to insure
recording of last word. AI ternative method: set WC
to 1 greater than desired number of word transfers and
change function with in 40 fJS after WCO.

2.7.7

Write Timing and Mark Tracks
This function and only this function may be performed with the selector switch on write tim-

ing and mark track (WRTM) on the maintenance control panel. Whereas the timing track is actually
hardware recorded during execution of this function, the mark track is generated and recorded by program. The value written in the mark track is determined by bits 0, 3,6,9, 12, and 15 of the l8-bit
word being written (i .e., the same bits assigned to channell).
CM may be conveniently used for this function since the hardware WC provides an automatic
counter and interrupt at WC overflow only; in NM, the DTF and interrupt occur at every word until

2-14

WC overflow. In NM, after WC overflow, if the GO bit or DECtape flag are not cleared, a timing
error occurs and no more data is recorded. After WC overflow in CM, if the GO bit is not set to 0,
zeros are written on down tape.
2.7.8

Enable and Interrupt Feature
The enable-to-the-interrupt feature allows the program to remove DECtape from the pro-

gram interrupt line (even if the interrupt is ON). This is primarily of value in the automatic priority
interrupt system.
When command bit 9 in the status register is set to a 1, the TC02 is connected to the interrupt system.

If this bit is 0, the DTF in the TC02 cannot cause an interrupt even if the interrupt faci-

1ity in the PDP-9 is ON.

Similarly, any of the five error conditions will cause an interrupt if bit 9 is

set to 1 in the status register, but cannot cause a program interrupt if bit 9 is a 0.
Whether th i s bi tis set or not does not infl uence the setting of status bi ts
status B register upon receipt of an error flag (EF) or DTF.

°through 5 of the

Similarly, the result of the I/O skip in-

struction is independent of the condition of this bit.
2.7.9

Error Conditions
Five types of errors can be detected in using DECtape:

timing, parity, selection, end -of-

tape, and mark - track errors.
For all errors the EF is raised, a bit is set in the status register, and an interrupt occurs (if the
enable-to-interrupt bit has been set). The DTEF instruction skips on the inclusive OR of those error
bits; hence, each status bit must be checked to determine the kind of error. For all but the parity
error, the selected transport is stopped and the EF is raised at the time of error detection. No DTF
occurs. For a parity error, the GO bit remains 1 (i.e., motion continues) and the EF is raised simultaneously with the DTF in NM. Only 1 interrupt occurs, hence the program must check the EF.
A parity error in CM rai ses the EF at the end of the block in wh i ch the pari ty occurs, causing
an interrupt (if enabled). If no program action is taken, for example, stop transport or reverse and reread, data transfer continues and the DTF is raised and causes an interrupt at WC overflow and end of
final block read.
2.8

PROGRAMMED OPERATION
Before using DECtape tape for data storage, the reel of tape is prerecorded in two passes.

In the first pass, the timing and mark tracks are placed on the tape. During the second pass, the forward and reverse block numbers are written. Prerecording uses the WRTM control function and the
manual switch on the maintenance control panel of the type TC02 control to (1) write on the timing
and mark tracks, (2) to activate a clock which produces the timing track recording pattern, and (3) to
enable flags for program control.

2-15

Unless the WRTM control function and the switch are used simultaneously, writing on the
mark and timing channels is inhibited. A red indicator lights on the maintenance control panel when
the manual switch is in the WRTM position.
The seven basic lOT instructions are generated, as required, by the PDP-9 program to clear,
read, and load the Status A and Status B elements. The lOT skip instruction is available to test the
status of the TC02 control. Since all data transfers between the TC02 and the PDP-9 memory are controlled from the computer, the program sets the word count (WC) and current address (CA) registers
using the memory reference instruction in the process of initializing a block transfer. Before and after
a DECtape operation, the program can check for error conditions.
The DECtape system is started wi;h the search function to locate the block number selected
for transfer.

When the correct block is fv.md, the transfer is accomplished by setting the WC, CA,

and the status A and status B registers. Wh.::m searching, the DECtape control reads only block numbers.
These are used by the operating program to locate the correct block number. In NM, the DTF is raised
at each block number. In CM, the DTF is raised only after the WC reaches zero. The CA is not incremented during searching, and the block number is placed in core memory at the location specified
by the contents of the CA. Data is transferred to or from PDP-9 memory from locations specified by
the CA wh ich is incremented before each transfer.
When the start of the data position of the block is detected, DF is raised to initiate a data
break request to the computer each time the DECtape system is ready to transfer an 18-bit word.
Transfers occur between the DECtape and successive core memory locations specified by the CA. The
initial transfer address-l is stored in the CA by an initializing routine. The number of words that are
transferred is determined by the tape format in NM or by the tape format and WC in CM. At the concusion of the data block transfer,

the DTF is raised and a program interrupt occurs. The interrupt sub-

routine checks the DECtape error bits to determine the validity of the transfer and either initiates a
search for the next information to be transferred or returns to the main program.
During all normal writing transfers, a checksum (the 6-bit logical equivalent of the words in
data block) is computed automatically by the control and is automatically recorded as one of the contro words immediately following

the data portion of the block. The same checksum is used during

reading to determine that the data playback and recognition takes place without error.
Anyone of the eight tape transports may be selected for use by the program. After using a
particular transport, the program can stop the drive currently being used and select a new drive, or can
select another transport while permitting the original selection to continue running. This allows rapid
searching, since several transports may be used simultaneously. Caution must be exercised because,
although the original transport continues to run, no tape-end detection or other sensing take place.
All functions provide for automatic and sensing, but this feature stops tape in the selected tape drive
only.
For programming examples that illustrate possible ways to code DECtape functions on the
PDP-9, see the PDP-9 Users Handbook, Chapter 5, page 5-13.

2-16

CHAPTER 3
PRINCIPLES OF OPERATION

This chapter provides a description of the basic functional elements of the DECtape Control
Type TC02, descriptions of data and control information transfers, and detailed descriptions of TC02
control operations. For information on the PDP-9 and TU55 transport, refer to the documents listed in
Table 1-1.
3.1

FUNCTIONAL DESCRIPTION
The I/O bus interface shown in Figure 3-1 is completely described in paragraph 3.3.2.1.

When operations are initiated, and the device number, to which the command in the I/O bus is addressed, is sent, the major registers are cleared. Information then is transferred into the TC02 registers
from the computer or read from the DECtape into the TC02 registers for assembly of a computer word.

1/0

PDP-9
CONTROL

TU55

TC02

DATA
CHANNEL

lIO BUS

INFORMATION
FLOW
SYNCRONIZATION

INFORMATION

BUS

READIWRITE
HEADS

PGM
TRANSFERS
INTERRUPTS

lIO BUS

CONTROL
OPERATIONS

COMMAND

BUS

MOTION AND
SELECTION

Figure 3 -1

Information and Command Flow

Once the tape unit is selected, the read or write operation is established, and proper motion is
determined.
The basic functional elements of the PDP-9 processor, TC02 control, and TU55 transport
interface blocks are shown in Figure 3-2. Numerals in the lower right-hand corner of the blocks indicate the bit capacity of the element. Numerical subscripts on the signal flow lines indicate the bit
assignments of the signals. Numerals in the lower left-hand corner indicate the engineering drawing
that shows the detailed elements of the function. Blocks that represent the Status A and Status B
functions are indicated by A and B, respectively, at the top right-hand corner of the block.

3. 1 .1

Information Flow
Information flow for write operation, indicated on Figure 3-2, involves transfer from the

I/O bus through gating, a data buffer, read/write buffer, and write amplifiers to the write heads. For
reading, data is transferred through the read amplifiers and back through the same elements. The following list defines the characteristics and functions of each of these elements.

3-1

~ PDP 9 -------..::~-------------

TC9}2

------------------------~~--TUS5 ~

'NF'ORM~,T10N

FLOW

DEVICE
SELECTION

CONTROL

LINES
lOT PULSES

rio BUS
B
COMMAHb
FLOW

SKIP REQUE'ST

rA:P.f:I_ _
1E!'.£/y'T~

r--,

- - --.A.P.I. I
I GoATINGj4-..,

IA.RI.L ________ ..-1

I
.~- _..J

L£9lfTB9~

PROGRAM INTE.RROPT I REG/VEST

D[CfORM NO
ORO 102

Figure 3-2 Type TCOl DECtape Control
Functional Block Diagram
3-3

Data Buffer (DB). - The data buffer is an l8-bit register used as a storage buffer to

synchronize data transfers as a function of tape timing between the memory buffer register of the computer and the read/write buffer.
b.

Read/Write Buffer (RWB). - The read/write buffer is a 6-bit register consisting of two

3-bit registers which transmit data between the data control and the read/write heads. During read
operations, one bit from each of the three data channels on tape is read into the read/write buffer and
sh i fted left.
c.

Write Amplifiers. - The five write amplifiers receive timing signals, mark-track, and

data information from the read/write buffer and provide the necessary current to the tape heads to write
the data on tape.
d.

Read Amplifiers. - The five read amplifiers transfer information from the tape heads to

the read/write buffer, and mark track to the window register, and timing signals to control.
3.1.2

Command Flow Registers
The registers and signals which control the transport operations and the data flow are de-

scribed as follows.
a.

Longitudinal Parity Buffer (LPB). - The longitudinal parity buffer is a 6-bit register

used to perform a parity check on the three information channels. The operation is performed by setting
the 6-bits of information read from two consecutive lines on tape into the RWB and complementing each
stage of the LPB if the corresponding bit of the RvVB contains a zero.
b.

Window (W). - The window is a 9-bit shift register through which mark-track informa-

tion is serially shifted to generate control signals for the DECtape system. Because the mark-track
window is three bits longer than is required to contain one mark, additional redundance is provided to
check that marks follow one another in the proper order. The bits of the mark -track window are continuousy decoded to detect when any of the legal marks appear.

Data Flag (DF). - The data flag flip-flop through DCH gating, requests a data break

from the processor when a word is ready to be transferred to or from the TC02.
d.

Control. - The control logic generates the timing and synchronizing pulses to perform

the functions specified in the function register and to coordinate the operations between the PDP-9
processor and TU55 transport.
e.

Device Selector. - The device selector decodes the lOT instructions for the DECtape

and generates the necessary pulses to load status registers, and generate SKIP pulses.
f.

Unit Select Register. - The unit select register is a 3-bit register which is loaded under

program control from the accumulator bits 0 through 2, and specifies a particular TU55 transport.
g.

Motion Register. - The motion register is a 2-bit register loaded from the accumulator

bjts 3 and 4, with the appropriate command of GO or STOP (bit 4), FORWARD or REVERSE (bit 3).
h.

Mode Register. - The mode register is a l-bit register that selects either normal or

continuous mode.

3-5

Function Register. - This is a 3-bit register that specifies one of seven possible opera-

tions to be performed by the DECtape.
j.

Function Decoder. - This decodes the content of the function register bits 1 through 3,

and transfers the decoded information to the control.
k.

Enable to the Interrupt. - This 1-bit register is loaded from the accumulator, bit 9, to

enable or disable the DECtape from the program interrupt.
I.

Error Register. - A 5-bit register in which any section can be set by the TC02 control

to indicate one of five error conditions.
m.

Error Flag (EF). - The error flag is set by one or more errors indicated by the error

DECtape Flag (DTF). - The DECtape flag is set at the completion of the currently

regi ster.
specified operation.
o.

Skip Gating. - Skip gating logic generates a pulse from the DTF flag and SKIP lOT to

request a skip from the PDP-9. This gating is not affected by the enable to the interrupt.
p.

Interrupt Gating. - This requests the program interrupt from the PDP-9 when the EF or

DTF is set and the DECtape is enabled to the interrupt.
3.2

SYMBOLS AND ABBREVIATIONS
The listings of Table 3-1 and 3-2 identify the engineering drawing set and the major sym-

bols and abbreviations used and referenced in this chapter.
Table 3-1
Engineering Drawing Identification
Dwg No.

Mnemonic

Description

TC02-0-1

R/W AMPS, SP GEN,

Read/write amplifiers, special generator and
test connector

TEST CONN
TC02-0-2

LPB & RWB

Longitudinal parity and read/write buffer
registers

TC02-0-3

I/O Bus Gating

Input/output bus gating

TC02-0-4

I/O Bus, lOTs

Input/output bus and lOT (input/output transfer)
instructions

TC02-0-5

ERRORS, MCP SWITCH

Error flip-flops (status B register) and manual
control panel switch

TC02-0-6

CONTROL

Control circuits including DTF and OF flip-flops
counter circuits, and major system control signals

TC02-0-7

STATUS A, COMMAND
BUS

Status A register (unit selection, motion, functions,
and ENI)

TC02-0-8

WINDOW, MK TK, STATE

Window register, mark-track logic

TC02-0-9

MCP & CABLES

Maintenance control panel and cables

3-6

Table 3-1 (Cont)
Engineering Drawing Identification
Mnemonic

Dwg No.

Description

TC02-0-10

TP GEN

Timing pulse generator

TC02-0-11

DTB

Data buffer regi ster

TC02-0-15

Timing

Four drawings

TC02-0-16

DCH, API

Data channel, automatic priority interrupt
Table 3-2
Symbols and Abbreviations

Symbol/
Abbreviation

Description

Source
Dwg.

Destination
Dwg.

0- DTB

Reset the D TB (buffer)

0- DTF

Reset the DTF flip-flop (DECtape
flag)

0- EF

Reset the EF flip-flop (error flag)

0- LPB

Reset the LPB (longitudinal parity
buffer)

0- STATUS A

Reset status A register flip-flops
(USR, MR, FR, ENI)

0- WINDOW

Reset the window register

+1 - CA INHIBIT

Inhibit incrementing the CA
(current address register)

1 - DTF

Set the DEC tape flag fl ip -flop

(100) - CO2

Set CO, Clear Cl and C2

BMRl

Buffer motion register

7,10

BXSA DY

Control flip-flop signal

CO-2(101 )MK BLK MK

With SEARCH to produce 1 - DF

CO, Cl and C2

Control clock flip-flops

5,6,8,9

CKO

Clock counter bit 1

CKl

Clock counter bit 2

CLR DF

Clear data flag flip-flop

COMP RWB 0-2

Complement read/write buffer
register 0-2

C STA

From the processor, produces reset
to status A register, initiates
XSA DY and BXSA DY delay

5,7

C SYNC

Level used to sync counter CO-2

DATA SYNC

Counter sync-ed with data

6,8,9

DCH EN IN

Data channel enabled in

DCH EN OUT

Data channel enabled out

DCH GRANT

Data channel granted

3-7

Table 3-2 (Cont)
Symbols and Abbreviations
Symbol/
Abbreviation

Descri pti on

Source
Dwg.

Destination
Dwg.

DCH RQ

Request for data channel

to processor

DS 0-5

Device selector lines

...

DTB 0-5,6-11, DTB 12-17

D ECtape buffer regi ster

2,3,9

DTB -+ I/O BUS 0-9
DTB-+ I/O BUS 10-17

Enables transfer of assembled
computer word onto the I/O bus

DTENA

Used to sync data channel breaks

DTENB

Used to sync data channel breaks

5,6,7

DT RQ

Used to sync data channel breaks

Data flag signal

DTF

DECtape flag

3,4,5,9,16

Error flag

3,4, 16

EF + DTF

Error flag or DECtape flag

END

End of tape

3,9

ENI

Enable the interrupt

3, 16

FWD

Forward motion

TU55

FRO

Function register bit 1

3,6,9

FR1

Function register bit 2

3,5,6,9,16

FR2

Function register bi t 3

3,9

FR3

Function register bit 4

3,6,8,9

Go command

TU55

INT

Generates interrupt request

I/O ADDR

Address for DCH or API break

I/O BUS 0-9

Inputs to status A register

I/O BUS 0-17

Data inputs to DTB

I/O BUS 10

To control clear to status B
register

I/O BUS 1-4

Generates signal NEW U+M

lOP 1-4

lOPs from the computer

10 OFLO

Word count overflow indication

10 P'vVR CLR

10 power clear

10 SYNC

I/O sync signal

4, 16

lOTB

Buffer signal

LPB 0-5

Longitudinal parity buffer
bits 0 through 5

9, 11

LPB -+ DTB

Load LPB bits into data buffer

LPB 11

LPB bits not equal to 1

3-8

Table 3-2 (Cont)
Symbols and Abbreviations
Symbol/
Abbreviation

Description

Source
Dwg.

Destination
Dwg.

LPB DTB 0- 5

LPB bits to DTB bit locations 0
through 5

MK BLK END

Flag signal marking end of data
block

3,6

MK BLK START

Flag signal marking start of data
block

MK END

Flag signal indicating that the
end zone is entered

MK DATA

Mark data

MK TK

Mark-track error flip-flop
signal

3
3,9

Motion register 0 bit
Motion register 1 bit

7
7

3,9
3,9, 10

Parity error signal

3,9

PROG INT RQ

Program in terrupt request

PWR CLR

Power clear signal

5,6, 10, 16

PWR CLR + ES

Power clear or error stop

7, 10

RATE DY

READ ALL

5,6

5,6,8

MOVE
MRO
MRl
PAR

RD STATUS

Control pulse initiated by lOP

READ DATA
REV

Reverse di recti on command to
the transport

TU55

READ DO

Read ampl ifier output track 0

READ D1

Read ampl ifier output track 1

READ D2

Read amplifier output track 2

RD MK

Read mark level output from MCP
switch

RD MK TRK
RD RQ

Read mark track

Read request

RD T TRK

Read timing track

RD +WD

Read or write data signal

ROTATE DTB 00-11

Rotate contents of data buffer
bits 0 through 11

ROTATE DTB 12-17/RWB

Rotate data buffer 12 through 17
and RWB

2,5, 11

RUN
RWB 0

Read/write buffer bit 0

3-9

Table 3-2 (Cont)
Symbols and Abbreviations
Symbol/
Abbreviation

Descr~tion

Source
Dwg.

Destination
Dwg.

RWB 0-5

Read/write buffer bit 0 through 5

RWB 1

Read/write buffer bit 1

RWB2

Read/wri te buffer bi t 2

RWB 3 IN

Read/write buffer 3 in

RWB¥ LPB

Computes parity check in LPB

RWB SHIFT LEFT

Shift contents of RWB left and
read next line of tape

Select error enable

5,7

6,8, 16

3,9

TU55

5,7

SEARCH
SEL

Select error flip-flop

SINGLE UNIT
SKP RQ

Skip request

Speed of DECtape

STA 10 BUS

Write content status A register
onto bus

3, 16

STB 10 BUS

Write content status B register
onto bus

3, 16

ST BLK MK

State in wh ich control senses
block numbers

5,9

ST CK

State in wh ich automatic error
detection occurs

5,6,9

ST FINAL

Final data word of block state

6,9

ST IDLE

State in which DECtape transport
not up to speed, is stopped, or
between blocks

4,5,6

STOP

Stop command to transport

TU55

ST REV CK

State in which reverse checksum
is overhead

6,9

SW TM

Switch timing and mark level output
of MC P swi tch

TIM

Timing error

3,9

T/M ENABLE

Timing mark enable

TPO

Timing generator signal 0

5,6

TP1

Timing generator signal 1

6,8

TU55

UNIT SELECT
UP TO SPEED

Indicates transport is up to operating
speed

6,8,9

USR 0,1,2

Unit select register bits

3,9

Word count flip-flop

6,9

3-10

Table 3-2 (Cont)
Symbols and Abbreviations
Symbol(
Abbreviation

DescriEJ'ion

Source

Dw-.a.

Destination
Dwg.

WCO

Word count overflow pulse

WREN

Write enable

7,9,10

WRITE ALL

WRITE DATA

WRITE OK

Write enable/write lock sensing
from TU55

TU55

5,6,7

WR RQ

Write request

WRTM

Write timing and mark

5,6,7,8, 10

XSAD

Amplified XSTA pulse

XSA DY

Status A register delayed pulse

XSTA

Load status A register pulse

5,6,7

3.3

DETAILED DESCRIPTIONS

3.3.1

Basic Read/Write Logic
The basic read/write logic for the Type TC02 DECtape control is shown on the left of

Figure 3-3. Each channel of the read/write circuit contains a flip-flop and input gates, a write amplifier governed by the flip-flop outputs and a read amplifier. Read inputs are paralleled with the write
amplifier outputs across the head allowing the read amplifier to respond to signals from both the read
and write amplifier.
The read amplifier is a high-gain differential amplifier augmented by a transient positive
feedback. When a signal of either polarity is sensed by the head, the read amplifier outputs switch
immediately and are asserted unambiguously, regardless of noise, which prevents head cross talk resulting from simultaneously writing in the data channels and reading in the timing and mark channels.

The

read amplifier outputs U and V are standard DEC logic levels of -3V and ground. When input E is more
positive than D, V is asserted at ground and U is negative; when D is more positive, the output levels
reverse. Because of positive feedback, the read amplifier oscillates in the absence of input signals.
The read amplifier output waveforms therefore are rectangular whenever the differential input signal
is indetermi nate.
The write amplifier is a saturated grounded -emitter push -pull amplifier with its output collectors connected through resistances to pins J and K. If the enable level is asserted negative, the
write amplifier is governed entirely by the state of the flip-flop. When the flip-flop is 1, K floats
and J is returned through the resistance and the saturated output collection to -13V. When the flipflop is 0, J floats and K is negative.

3-11

WRITING

(21

ROTATE DTB/RWB OR
RWB SHIFT LEFT (TP-01
COMP RWB 0-2 ITP-11

(31

DATA (GND-n

(41

RWBO

(51

WRITE CURRENT

(61

READ AMP OUTPUTS

(Il

t
{:

- - - - - - - - T~;E- - - - - - - - - - - - - (71

~6~~~~~:TI~.

~ -TAPE- MOTION - - ';-E~~ -M~~E; - L~;;-~O--~I~~ -;E~A~;V; ~~ ~~P~ - - - -

IR I L IR I L I R I L I R I L IR I L I R I L IR I L I R I L

THIS CHANNE L

-----------------------------------REArnNG-------------------------

(81

HEAD VOLTAGES

( 91

READ AMP OUTPUTS

(101

RWB SHIFT LEFT

1111

RWB3 - GND I

(TP-01

Figure 3-3

Read/Write logic and Waveforms

In the two tracks corresponding to each channel on tape, information is recorded in a manner
that makes read signals from the two head inductors reinforce on playback. The two inductors can be
considered as a single head inductor whose winding is center tapped to ground, reading and writing in a
single track.
When a write flip-flop contains 0, current flows from ground through the head inductor into
K, and the polarization of the head core is oriented clockwise. The tape polarization, as the tape
moves across the head, is oriented toward the left regardless of the direction of tape motion. Similarly,
when the flip-flop contains a 1, tape polarization is oriented toward the right regardless of the direction of tape motion. When reading, the current induced in the head by a change in polarization flows
opposite to the current required to cause the same change. Consequently, the current induced by a
left-to-right tape polarization change is a current flowing out of the head toward pin E. The head is
a source, and when a terminal is a current source, it is positive. Thus a left-to-right polarization
change causes the read amplifier input E to be positive.

Consequently~ V is ground and U is negative.

By the same reasoning, the left-to-right polarization change induces a positive signal at D and results
in V being negative and U ground.
The Manchester recording system used in the control requires two pulses to write each bit in
a channel. The first pulse, ROTATE DTB/RWB or RWB SHIFT LEFT, loads the write flip-flop with the
value of the bit to be written. (See the timing diagrams, Dwg. No. D-TC02-0-15, (sheets 1 and 2)
and Dwg. No. D- TC02-0-2. The second pulse, COMP RWB 0 through 2, complements the flip-flop.
Depending on the state of the flip -flop, the ROTATE DTB/RWB pulse mayor may not cause a polarization change on the tape. The RWB 0 through 2 pulse, however causes a tape polarization change
3-12

because as a complement input it changes flip-flop state. When reading, the value of a recorded bit is
detected at the head inductor output as the polarization change passes over the head. The RWB 0-2
pulse produces a right-to-Ieft polarization change when the flip-flop is loaded with 1, and produces
left-to-right change when loaded with O.
In Figure 3-3 the ROTATE DTB/RWB or RWB SHIFT LEFT and RWB 0-2 pulses alternate.
The first pulse sets the flip-flop to the 1 level, the second complements. This relationship is shown in
lines 1 and 2. line 3 shows bits to be written, and line 4 shows flip-flop receipt of each bit.

line 9

shows direction of tape polarization. If the tape is read in the same direction as it is written, the tape
positions corresponding to the time that the write flip-flop was complemented will show a right-to-Ieft
change on a 1, a left-to-right change on O. The head voltages at read amplifier inputs E and 0 are
shown in line 10, the read amplifier outputs on line 11. In reading, the shift pulses in line 12 for RWB
coincide with those of line 2 (which complemented the write flip-flop in writing). The right-to-Ieft
polarization change representing a 1 results in ground at U at the time of the shift pulse. Consequently,
line 13 shows a 1 shifted into the shift register as the first bit that is read.
If tape is read in the opposite direction to which it was written, the polarizations reach the

head gap in reverse order; that is, the head senses a left-to-right change where a 1 was written, etc.
The contents of the mark channel are selected to take advantage of this condition. Data written in one
direction and read in the opposite direction will be complemented.
The read and write amplifiers are shown on Dwg. No. 0 - TC02-0-1. The READ T TRK and
READ MK TRK read amplifiers produce timing and mark-track outputs. The associated write amplifiers
are used only to format tape. The READ T TRK read amplifier also provides a SP input for generation
of the UP TO SPEED signal (Dwg. No. D-TC02 -0-10). The READ DO, READ 01 and READ 02 read
amplifiers and corresponding write amplifiers on Dwg. No. D-TC02-0-1 produce the outputs necessary
for transfer of data between associated RWB 0, 1, 2 bits and the DECtape.
3.3.2

Initialization Operations
Operations of the TC02 usually begin with a CNT n, FWD, GO, NM, SEARCH command.

In addition to the operations involved in filling the command register (status A), certain other operations,
such as initial time delay, are common to all DECtape functions.
3.3.2.1

I/O Bus Interface - The I/O bus interface for the TC02 is shown on Dwg. No. D-TC02-0-4.

The logic by wh ich lOPs from the computer are decoded to produce control and command signals are
shown here, as well as the bus connections. lOPs are shown entering the control and being applied to
W103 circuits for decoding and generation of command signals for TC02 logic.
Initially, two pulses are issued on the I/O bus, to provide CSTA to clear the status A register and I/O Power Clear to clear the status B register. I/O power clear is used to clear the registers
when power is turned on or the program is restarted. CSTA is used to clear the register under program
control.

3-13

3.3.2.2

Timing Pulse Generation (Dwg. No. 0- TC02-0-10 and 15) - Timing pulses are required for

both formatting the tape and for reading information from tape. During WRTM function, the T/M
ENABLE level activates the clock and thus allows timing pulses TPO and TP1 to be generated if the MCP
switch is in the WRTM position. This position causes the WRTM/RDMK indicator (Dwg. No. 0- TC02-09) to light and generates the SNTM level. This level is ANDed with MR1 (l) and the WRTM level to
produce TM/ENABLE, which starts the 120 kc clock.
On the positive transition of the clock pulse, the CK1 flip-flop is complemented. The
positive transitions of the CK1 flip-flop complement the CKO flip-flop. The outputs of CKl and CKO
at location 028, result in generation of the 100 ns timing pulses TPO and TPl which occur alternately
every 16.6I-'s. The CKO(l) output also is applied to the timing track write amplifier at location C23
(Dwg. No. 0- TC02-0 -1) to produce the ti ming track pattern wri tten on tape.
Timing pulse outputs also require the SWTM output from the MCP switch and the WREN level
at location F15 and F19 to be true.
During the write function when the C2 flip-flop (Dwg. No. 0- TC02-0-6) goes to zero,' the
negative transition sets the WREN flip-flop and generates WREN (1) output. The WREN flip-flop is
reset again at C2(O) when anyone of the ANDed inputs that is associated with the write functions is
removed. This flip-flop allows a full data word to be written, even though one of the enabling level
inputs have been removed before the end of a word has been reached.
Timing pulses TPO and TP1 are generated during read operations when the UP TO SPEED (1)
flip-flop is set at location 027, Dwg. No. D-TC02-0-10. The inverted output is gated with SWTM
level, which is present when the MCP switch is in any position other than WRTM (Dwg. No. 0- TC020-5). to provide a ground conditioning level to the DCD gates associated with the TPO and TPl power
amplifiers. When the timing track 'signals READ TRK are received at location 022, the positive going
pulses to the DCD gate, generates the timing signals.
The TPO and TPl outputs are applied as feedback to PA, location ClO. The outputs of this
power amplifier trigger a 10 I-'s delay during reading and writing data, producing a -3V output to
inhibit any extraneous timing signals which may be generated as a result of cross talk between data and
timing channels.
3.3.2.3

Tape Unit Selection (Dwg. No. 0- TC02-0-7) - The unit select information USR 0-2 in

status A register is decoded by the binary-to-octal decoder R151. A ground level on one of the eight
outputs enables a SELECT level within the specified TU55 transport. The transport that is enabled by
the grounded line responds to the transport control signals and connects its read/write heads to the head
signal lines.
The USR 0, 1, and 2 stages of the status A register are set or held reset by the condition 1 or
0, respectively, from I/O bus 00, 01, and 02. The outputs of USR 0, 1, and 2 are displayed on the
indicator panel via connector A-ll pins A, B, and C (Dwg. No. 0- TC02-0-9). These outputs can
also be sent back to the computer over the I/O bus under control of STA" 10 bus pulse, which controls
transfer of status A register content to the AC.

3-14

The binary -to -octal decoder S151 accepts the inputs from the three stages and provides the
single grounded output on one of eight lines directly to W023, C32, which is the cable connector for
the TU55 transports. (Refer to Logic Handbook, page 66 for complete circuit description and truth table
analysis. )
3.3.2.4

Tape Motion Selection (Dwg. No. D- TC02-0-7) - Motion control information from the

processor via the I/O bus is set into the status A register stages MTO and MR1. The outputs of these two
stages determine when the selected transport wi" be activated and the direction of tape travel. The
outputs of MRO produces either FWD (MRO(O», or REV (MRO(L». The logic is mutually exclusive so that
only one direction signal can possibly be active at a given time.
Both direction signals can be inhibited by several conditions as shown on the logic. The
X STA CLEAR STATUS A pulses at A-l 0 insure that no spurious direction signal wi" occur when the
status A register is cleared. The MR1(0) and B XSA DY (delay) levels at the A-l0 OR circuit insure
that no direction signal changes occur during a stop operation or before the delay circuit output. The 0
output of BMRl flip-flop also inhibits motion signals.
The BMRl flip-flop controls STOP and GO generation by the condition of MR1. MR1(1)
provides GO. MRl (0) resets BMRl and produces STOP at A-09-N. The FWD, REV, STOP, GO signals are sent to the selected transport through C32 (Dwg. No. D- TC02-0-9).
3.3.3

Device Selection Logic
The device selector logic decodes the output of the memory buffer, bits 3 through 8, and

generates lOT pulses (Dwg. No. D- TC02-0-4) used to initiate the status A and status B operations
(X STA). Status A register is shown on Dwg. No. D- TC02-0-5.
The control operations, wh ich are initiated by computer instructions and which involve
status A register are shown on Dwg. No. D- TC02-0-4. These instructions are RSTA (read status A
register), CSTA (clear status A register), and XSTA (load status A register). The status A instructions
contain an octal 76 in bits 3 through 8 of the memory buffer register and are decoded by device selector
Wl03, location EFll on Dwg. No. D-TC02-0-4. RSTA at event time 2 (l0P2) is gated with the device selector to produce the 400 ns READ STATUS A pulse. The information on status A register (Dwg.
No. D- TC02-0-7) consisting of unit select USR 0-2, motion control MRO and 1, function register
FRO-3, and ENI, enable interrupt, is gates with STA" I/O bus pulse (Dwg. No. D-TC02-0-3) locations DOl and D02 to produce I/O bus 00 through 99, which are loaded into the PDP-9 AC through
connector EF01 or EF05.
Instruction Clear Status A is also decoded by the device selector Wl03 on D-TC02-0-4 and
during event time 1. Pulse 10Pl is produced and gated with the decoded output to generate the 400 ns
CLEAR STATUS A signal (CSTA). CSTA output produces the 0" STATUS A at D15 to clear the status A
register functions on Dwg. No. D-TC02-0-7, and the CXA pulse at location C18 Dwg. No.
D- TC02-0-5. The positive going CXA pulse triggers the 5 (..Is delay at R302 providing a -3V XSA DY
output for the QtlTation of the delay. Clearing status A register selects tape unit 8 by the 000 configuration of the unit select register. The negative XSA DY level at location D23, Dwg. No. D-TC02-0-5,
3-15

holds both the STOP and GO levels ground (Owg. No. 0- TC02-0-7) to prevent a change of motion to
tape unit previously specified. The positive going end of the XSA OY pulse jams the contents of MR1
into the BRM1 motion flip-flop (Owg. No. 0-TC02-0-7). Either the BRM1(0) output or MR1(0) pulse
wi II provide a ground level at both the FWD and REV outputs of S107, preventing a direction change
from occurring to insure that only the newly selected unit receives the new command.
lOT load status A register is decoded at the device selector. and gated with the IOP4 pulse
at event time 3 to generate the 400 ns XSTA pulse (Owg. No. 0- TC02-0-4). The ground XSTA pulse
output performs an exclusive OR function with the buffered accumulator outputs shown at locations 007
and 008 (Owg. No. 0- TC02-0-3) complementing the data in status A register when the buffered input
level goes to ground at least 400 J-IS before the XSTA pulse is received. This permits specific information in the status register to be changed without affecting the remaining information.
The negative XSTA pulse is amplified by PA 5603 (upper left of Owg. No. S- TC02-0-7) to
produce a negative XSAO pulse at Sl07 and a positive XSAO pulse at the amplifier output.
3.3.4

Status B Register and Skip Instructions
The status B regi ster, Skip Error Flag, and Skip on OTF instructions are decoded by W103s

shown on Owg. No. 0-TC02-0-4. These instructions are SEF (Skip on Error Flag), RSTB (Read status B),
and SOTF (Skip on OECtape Flag). The SEF and SOTF occur at IOP1 time and the RSTB at 10P2 time.
The Skip pulse causes the program counter in the POP-9 to be incremented by one and skip
to the next sequential instruction.
When a programmed 10P2 pulse appears at event time 2, the RSTB 400 ns produces STB'" I/O
bus pulse which is a common pulse input to the NAND gates associated with modules shown on Owg. No.
0- TC02-0-3 that have inputs from status B register.

A -3V level on any of the gate inputs indicates

that an error exists, the OECtape flag is set, etc., and will result in ground outputs for loading into the
POP-9 AC or an OR transfer.
LOTB is generated during a OCH break to load the OECtape buffer (OTB) from memory. ROTB
is generated during a OCH break to read the OECtape buffer (OTB) into the memory.
3.3.5

Interrupt Enable
Bit 9 of the AC determines the status of the ENI flip-flop (Owg. No. 0- TC02-0-7). This

flip-flop enables (ENI(1)) or disables (ENI(O)) a program interrupt. The output of ENI(1) causes an
interrupt request to be sent to the POP-9 (Owg. No. 0- TC02-0- 16).
3.3.6

New Unit/tv\otion Select
The buffered accumulator outputs (Owg. No. 0- TC02-0-10) I/O bus 00(1) through -04(1),

the unit selection and motion control bits, are sampled by the OR gate locations F17 and F16, to determine whether a new unit or motion has been specified. A ground level on any BACO-4 input or at
buffered memory bit BMB9(0), which indicates a change on bits 0 through 4, will result in a ground level
NEW U+ M output. This level allows the negative going CXA pulse {produced by XSTA, see

3-16

Dwg. No. D-TC02-0-5) to trigger the 120 ms U+M delay. The U+M(O) output from the delay sets
the 70 flS RATE DY, which in tum sets the Up-to-Speed flip-flop, location D27. The output of the
Up-to-Speed flip-flop, when reset, resets DATA SYNC. UP TO SPEED (1) enables TP ENABLE to
aI/ow the READ T TRK (0) inputs at location D22 to generate the timing pulse outputs TPO and TP1.
When the U+ M delay is set (l), the negative output prevents the timing track pulses (SP) read from
tape during the up-to-speed operation from triggering the RATE DY flip-flop. The SP signals (Dwg.
No. D-TC02-0-1) are produced by the READ T TRK amplifier.
When the U+M delay is reset, the ground level output conditions the DCD gate to allow the
first SP pulse to set the rate delay flip-flop. The ground level output of the rate delay conditions the
DCD gate associated with the Up-to-Speed flip-flop, and thus aI/ow the next SP pulse which occurs
within a 70 flS interval (rate delay) to set the Up-to-Speed flip-flop and start the TC02 operations.
The Up-to-Speed flip-flop is reset by the positive transition of the BRM1(0) level which indicates a
stop motion, and by the ground output of the timing mark enable level (T/M ENABLE) generated at
S107 location D22. Resetting this flip-flop produces a 0'" WINDOW pulse which clears the window
register (Dwg. No. D-TC02-0-8) while the tape is not up to speed.
3.3.7

Counter Register
The Counter Register (location E15 Dwg. No. D-TC02-0-6) consists of three flip-flops used

to control the blocks of information on the tape as shown on the timing diagrams of Dwg. No.
D-TC02-0-15, Sheets 1 through 4. The outputs of the CO, Cl and C2 flip-flops provide a count of six
for formatting a data word on tape and for the mark-track information. Initially the counter register is
set to 100 by the (100)'" CO-2 pulse (Dwg. No. D-TC02-0-15, Sheet 1) produced by the C-SYNC
ground signal and the positive transition of TPO. This count presets the counter in synchronization with
the tape and starts the first count of six. The count sequence is shown on Table 3-3 and Dwg. No.
D- TC02-0-15.
Table 3-3
Counter Register Sequence
Cl

TPO Pulse

1 (C-SYNC- TPO)

0
0

3-17

Table 3-3 (Cont)
Counter Register Sequence

TPO Pulse

0
0
3.3.8

Window Register
The window register W1 -9, shown on Dwg. No. D- TC02-0-8, location E29, F29, F30, F31,

F32, provides temporary storage for the mark-track information read from tape during all tape functions
except WRTM. At the start of the loading operations all flip-flops are cleared by the 0 ..... WINDOW
pulse generated by resetting the Up-to-Speed flip-flop. When the tape is up to speed, the READ MK
TRK information from the read heads conditions the DCD gates associated with W9 flip-flop, and the
TP1 timing pulses then shift the mark-track information into the window register. The next TP1 pulse
which appears after the W2 flip-flop is set, will set the W1 flip-flop which will remain set until
cleared by the 0 ..... WI NDOW pulse. The outputs of the window regi ster are appl ied as inputs to six
separate AND gates which decode "the inputs and generate specific mark -track level outputs.
3.3.8.1

Counter Sync Level (C-SYNC) (Dwg. No. D-TC02-0-8) - Initially, when reading mark-

track information either in forward or reverse, the first code to be recognized and used for synchronization is a result of the bit information formed by octal 525 or 725. This information appears after the
reverse -end -mark codes sequence through the W-regi ster. The bit configuration (Figure 3 -4) are decoded by the C-SYNC gating logic (location F22), to produce a series of C-SYNC level outputs which
condition the control register.
MARK

oCTAL

REV BLOCK
4
I 5

525

I 0 011 0

TAPE MOTION
EXTENSION
2

EXTENSION
2
I 5

FWD BLOCK
2
j 6

0 I

o I 011 0 , o , 011

o I 0 II

J I
®

0
®
®
7

Figure 3-4

tv\ark-Track Decoding (C-SYNC)

3-18

The first code recognized by the C- SYNC gating appears at 1. These nine bits are decoded
with the -3V output of Slll, location F22, and generate the C-SYNC levels for all operations except
write timing mark.
With fwo extension marks (E) inserted in the mark-track information, the C-SYNC signal
will appear six times at the input to the AND gate and produce the C-SYNC level to reset the control
clock. Only at the last decoding six, however, will the control clock initiate a count and synchronize
the counter with the mark -track information.
3.3.8.2

Start Block Mark (MK BLK MK) (Dwg. No. D-TC02-0-8) - The next bit configuration in the

W-register, which is recognized,is the forward or reverse block mark. This information appears during
the next TP1 pulse after the C-SYNC level is generated, as shown on Table 3-4 and on timing diagram
(Dwg. No. D- TC02-0-15, Sheet 1). The positive transition of the TPO pulse which preceded the TP1
pulse sets the counter register to 101. The W-register information is gated with the WRTM level and
the counter register outputs, CO(1), C1(0), and C2(1) to generate the CO-2(101) MK BLK MK outputs,
as shown on Figure 3-5.
Table 3-4
Sequence of Block Marks and Control States
Block Mark Code
(Octal)

Event No.

Block Mark or State

Tape stopped (ST IDlE(l))

Start tape

UP TO SPEED (1)

C SYNC

DATA SYNC (1)

C(101) • MK BLK MK

SHIFT STATE

ST BLK MK (1)

MK BLK START

SHIFT STATE

ST REV CK (1)

MK BLK START

SHIFT STATE

DATA (1)

MK DATA

070

MK BLK END

073

SHIFT STATE

ST FINAL (1)

MK BLK END

SHIFT STATE

725 or 525
126

210

010

373

3-19

Table 3-4 (Cont)
Sequence of Block Marks and Control States

Event No.

Block Mark Code
(Octal)

Block Mark or State

ST CK (1)

C1(1)

SHIFT STATE

ST IDLE (l)

Start at event number 6

M ARK

EXTENSION

oCTAL

526 0

Figure 3-5

1 01,

126

TAPE MOTION

FWD BLOCK

REV GUARD

1 01,

1 0

Mark - Track Decoding (MK BLK MK)

The octal 2 position of the reverse guard mark, in the forward tape direction, or octal 5
portion of the guard mark in the reverse tape direction is recognized together with the lock marks to
generate the next mark-track signal MK BLK START as shown in Figure 3-6, and timing diagram
(Dwg. No. D-TC02-0-15, Sheet 1).

MARK

REV GUARD

oCTAL

210

Figure 3-6

TAPE MOTION
LOCK 1

LOCK 2

o 1 110 1 0 0011000

- I

0
ETC

Mark-Track Decoding (MK BLK START -210)

The outputs from the W register, except for W2, are ANDed and inverted resulting in the
MK BLK START outputs at location F15, Dwg. No. D-TC02-0-8. This occurs at the next 100 count of
the control register as shown on the timing diagram. This lock mark is the first of four that are programmed on tape. Each will generate the MK BLK START levels. The bit configuration required for
the next three lock marks are shown in Figure 3-7.

3-20

TAPE MOTION
LOCK 2

LOCK'

oCTAL

, I 30

, I 0

M ARK

LOCK

, I 0
LOCK 4

0'0 00 ,100000,100000,100000,1000
CD --oJ.--,1-®---

~0-3=.c--,+--I~_--'

-,+--I

Figure 3-7

Mark - Track Decoding (MK BLK START -010)

The same AND gate which decoded 2108 W-register configuration will decode the 0108 and
product the additional MK BLK 5TART level.
3.3.8.3

Data Marks - The data mark follows the last lock mark and is decoded by AND gates R002

and 5111, locations F20 and F24. The W-register configuration is shown in Figure 3-8 •
...- TAPE MOTION

M ARK

LOCK 4

OATA ,

OATA 2

OATA

0 7 I 0 7 I 0
070 o 0 0 , , ,10 0 0 , , ,10 0 0 ETC.

oCTAL

_ __

CD __J_-®-=-~,+-I~_Fi gure 3-8

Mark - Track Decoding (MK DATA 070)

The -3V inputs are inverted and generate the MK DATA output levels as shown on timing diagram (Dwg. No. D- TC02-0-15, Sheets 1 and 2). After the last data mark has been decoded, AND
gate (Dwg. No. D- TC02-0-9, locations E30 and E31) decodes an octal U73, and three octal 373s
from the W-register to generate a series of four mark block end signals (MK BLK END), as shown on
Figure 3-9 and timing diagram (Dwg. No. D-TC02-0-15, Sheet 2). This is accomplished by not decoding inputs from the W2 and W3 flip-flops.

_
MARK

DATA

TAPE MOTION

PRE FINAL

FINAL

CHECK SUM

LOCK

0 7 3 7 I 3 7 I 3 7 .1 3
073
373 000 , , ,10 , 0 , , , \0 , o , , , \0 , 0 , , ,10 , 0

oCTAL
or

CD-,.c--I-®-2=.c--,~1~0-3=.c--,~1~0_4=_,~I~_I__~
Figure 3-9

Mark-Track Decoding (MK BLK END)

3-21

The next two mark-track codes, guard mark (51) and block mark (45), which follow the
lock mark, are not decoded and the decoding continues through the same sequence, as previously specified' until the end marks (222) are decoded by AND gate (location F19, 20 and 21, Dwg. No.
D- TC02-0-8), which generates the MK END level.
3.3.9

State Regi ster
The state register (Dwg. No. D-TC02-0-8, locations F26, 27, and 28) is a ring counter

which indicates the control states of the TC02 as determined by the mark-track decoding sequence.
The state register is cleared (forced to the ST IDLE (1)) each time the Up-to-Speed flip-flop is reset.
The control states are sequenced through the state register by the positive transition of the SHIFT STATE
pulses produced by monitoring both the decoded outputs of the mark-track and by the outputs of the state
register at locations E21, F14, and F15. The outputs of the state register are connected to the MCP to
provide a visual indication during DECtape operations. Table 3-4 lists in sequence the various block
marks and control states that are generated.

The first five events occur prior to the generation of the

first SHIFT STATE pulse.
At event 6, the first block mark is decoded. The ground MK BLK MK level is inverted by
S107 at location F15, and applied to another circuit of F15 to generate SH ST EN. This signal results
in the first SHIFT STATE pulse at event time 7, which sets the ST BLK MK flip-flop. At event time 10,
the mark-track decoded output MK BL START is gated with the -3V ST BLK MK (1) output and generates
the second SHIFT STATE pulse. This pulse sets the ST REV CK flip-flop and resets the ST BLK MK flipflop. The second MK BL START level produced by the mark-track decoding network is gated with the
-3Voutput of ST REV CK flip-flop at location F14 to produce the third SHIFT STATE pulse at event
time 13, which sets the Data flip-flop. The Data flip-flop remains set for all data words and until the
MK BLK END level is decoded which allows the SHIFT STATE pulse at event time 17 to set the ST
FINAL flip-flop. The second MK BLK END pulse is ANDed with the ST FINAL (1) output producing a
SHIFT STATE pulse at event time 20, and sets the ST CK flip-flop. The ST CK (1) -3V output AND
gated with the counter register output Cl (1) sets the ST IDLE flip-flop at event time 23, which allows
the sequence of events starting at event time 6, to repeat for the next block.
3.3.10

Function Selection (Dwg. No. D- TC02-0-7)
The function command for the selected TU55 transport arrives over I/O bus 06 through 08,

which are applied to the FRl-3 flip-flops of status A register. Stages FRl-3 constitute the function
register.
The outputs of the function register are decoded by the binary-to-octal decoded S151 at
location A-07 to provide one of the seven function levels used to select tape unit operations. This
circuit produces a single ground level output on one of the selectable function lines shown on Dwg.
No. D-TC02-0-7. The condition of the function register is displayed on the indicator panel via A-ll
pins F, H, J, and K (Dwg. No. D-TC02-0-9). The outputs are also gated back over the I/O bus
(Dwg. No. D-TC02-0-3) under control of STA .... 1/0 bus pulse.

3-22

A description of the logical operations within the TC02 control for each function is described in the following paragraphs.
3.3.10.1

Move Tape (000) - The Move Tape function (MOVE), used to reposition or rewind tape, is

implemented by a Load Status Register instruction, which specifies all zeros (0 .... STATUS A) in the
function register FRl-3. The Move function allows the tape unit selected to move in the direction
specified by the motion register (MRO) until the tape end zone is detected, without allowing data
transfers to occur.
The MRl (1) level from the motion register allows the BRMl flip-flop (location C16) to be set
at the end of the XSA DY delay and starts the tape motion in the direction specified by MRO. When
up-to-speed is reached, the mark-track information is read from the tape. If no select error is detected, the tape motion continues and the mark-track information is read without effect on the operation until the end zone is detected. The decoded end zone generates a MK END level (Dwg. No.
0- TC02-0-8), which allows the END flip-flop (Dwg. No. 0- TC02-0-5) to be set by the TPO timing.
3.3.10.2

Search (001) - The Search function is used to locate block numbers on tape. During this

function, all information is read from the tape; however, only block numbers are transferred to the
PDP-9 where the program performs a comparison of the information received with a specified block
number to determine whether the two are the same.
The Search function is initiated by an octal 1 in the function register. When the transport
comes up to speed, the timing track pulses READ TRK generate the TPO and TPl pulses (Dwg. No.
D-TC02-0-10). The control operations performed are similar to the Read function. As shown on control drawing (0- TC02-0-6) the WREN(O) output allows the TPl pulses to generate RWB SHIFT LEFT
pul ses, which assemble the information from tape in the RWB. The decoded mark -track information
(Dwg. No. 0- TC02-0-8) produces a series of C-SYNC levels, the last of which generates the first
ROTATE DTB 00-11 and ROTATE DTB 12-17/RWB pulses and rotates the first bits of the block number
into the DTB. Wore shift pulses are then generated at TPl times to assemble the rest of the block number into the RWB, and the MK BLK MK siglal is decoded to shift the state to ST BLK MK. At the
C2(0) transition, another ROTATE DTB 00-11 and ROTATE DTB 12-17/RWB pulse load the DTB with the
block mark information. Then a 1 ... OF pulse (Dwg. No. D-TC02-0-6) is generated to set the data
flag (generating a break request) by SEARCH, CO-2(101), and MK BLK MK. In the normal mode, the
DTF flip -flop is alsa set to request a program interrupt to determine whether the block number transferred is the block number desired. In the continuous mode, the DTF is set only if a word count overflow (WCO) pulse is received.
Unless another function is specified, the control continues in the Search function, the marktrack decoding is performed and the data is assembled and shifted in the DTB and RWB. The 1 ... OF
pulse, which sets the data flag, will not be generated, however, until the next MK BLK is decoded.
During the ST REV CK state, the 0'" LPB and RWB ¥

LPB are generated for the parity com-

putation. The parity has no significance, however, during search.

3-23

3.3.10.3

Read Data (010) - The Read Data function is normally performed after the program has

searched and located the desired block number. Read data is specified by an octal 2 in the function
register. After the Search function is completed, the control is normally in the ST BlK MK state.
When mark-track information is decoded as a MK BlK START, the SHIFT STATE pulse (Owg. No.
D- TC02-0-8) changes the state to ST REV CK. During the previous states of the Search function, the
ROTATE DTB to RWB and RWB SHIFT LEFT pulses were generated. No read data, however, was allowed
to be transferred. The ST REV CK level enables the TPl pulses to generate the 0 ~ lPB pulses (Dwg.
No. D- TC02-0-6) to clear the lPB. The RWB ¥ LPB pulses, which exclusive ORs the 6-bit RWB information into the LPB (Dwg. No. D- TC02-0-2), are also produced during ST REV CK (l). This permits the reverse check word (the last 6 bits read) to be included in the parity computation. The state
DATA is entered and the data is assembled and shifted by the RWB SHIFT LEFT and ROTATE DTB 00-11
and ROTATE DTB 12-17/RWB pulses as described in the read and write sequence. Each time ROTATE
DTB 00-11 and ROTATE DTB 12-17/RWB pulses are generated, a RWB ¥ LPB pulse allows the parity
computation to be performed.
If the WC register (Dwg. No. D-TC02-0-7, location 12) is set, indicating that a word
count overflow has not occurred, the 1 ~ DF pulse at the C2(0) transition will set the data flag (DF)
requesting the interrupt request to transfer the word in the DTB to the PDP-9. When the request is
granted the DCH GRANT pulse produces CLR DF to clear the DF.
This sequence continues until the end of the data portion of a block occurs, which is signified by the ST CK state. When the ST CK flip -flop is reset, the contents of the LPB should contain all
ONEs or the parity error will be indicated by the lPBlt

(Owg. No. D-TC02-0-2) input which sets

the PAR flip-flop. At this time, in the normal mode (FRO(O», the ST CK (0) pulse will generate
1-+ DTF pulse to set the DTF flip-flop.

In the continuous mode (FRO(l), the DTF flip-flop will be set

if a word count overflow had been issued during the previous data block. If the DTF flip-flop is set,
the programs must specify a new operation. If it is not set, and the continuous mode is specified, the
operation will continue as previously described. When a word count overflow occurs during the middle
of a data block, the data transfers will stop.
3.3.10.4

Read All Functions (01l) - The Read -All function, specified by an octal 5 in the function

register, allows all information to be written in the data tracks on tape, including reverse check, block
numbers, etc., to be read and transferred to the PDP-9 processor. Real all can be programmed initially
or after a Search function that locates a specific block on tape before reading begins. When the tape
has reached speed, only one C-SYNC level is required to set the DATA SYNC flip-flop, and the information on tape is read even though it may not be synchronized. This can occur in the. middle of a
data word on tape.
The operations within the DTB/RWB during the Read All function are similar to the operations
which occur during the Read Data function.

The RWB SHIFT LEFT pulses are produced at time TPl

enabled by the WREN (0) output to assemble the information into the RWB. The ROTATE DTB 00-11 and
ROTATE DTB 12-17/RWB pulses then occur as C2(0) transition, causing the information in the RWB to be

3-24

transferred to the DTB. The same pulse transition also generates an RWB ¥ LPB pulse which allows the
parity computation. TP1 pulses again produce RWB SHIFT LEFT pulses followed by another RWB V LPB
pulse. At this time, the CO (0) input wi II generate 1'" DF pulse which sets the DF flip-flop, requesting
a data break.
In the normal mode, with the FRO(O) 1\ RD +WD input applied, the 1'" DTF pulse will also
set the DTF flip-flop requesting the program to specify a new operation. Although the next word is not
transferred, the setting of the data flag may result in a timing error requiring a new function to be
specified or a similar operation to be performed. In the continuous mode with FRO(1), the DTF flip -flop
is set when the WCO pulse occurs from the PDP-9. The tape motion will continue, but no additional
data transfers wi II occur.
During the Read-All function, although parity is computed, mark-track information is decoded, and the state register changes, these operations have no effect on data transfer.
3.3.10.5

Write Data Function (100) - The Write Data function is used to write data on tape in the

data areas assigned by the mark-track coding. The Write Data function is normally initiated following
a search operation which determines the block position on tape where the data will be written. The
initialization process allows the tape to reach speed, the DATA SYNC flip-flop to be set, and the
counter to be synchronized with the mark -track information. Specifying write data before the DATA
SYNC f/ ip -flop has been set wi II result in no operation.
When the Write Data function is specified after a Search function, the control is normally
in the START BLOCK MARK state (Dwg. No. D-TC02-0-15, Sheet 1). The START BLOCK MK (1)
level is gated with the decoded window register output MK BLK START level (Dwg. No. D- TC02-0-8,
location F14) to generate a SHIFT STATE pulse which sets the ST REV CK flip-flop, changing the state
of the control. Pulses 0'" LPB and RWB ¥ LPB, a sequence of pulses will load and clear the LPB during
the reverse check state.

The reverse checksum which occurs one 6-bit word before the data state,

however, will be included in the parity computation. Pulse 0-+ DTB, generated during ST REV CK(1)
by CO(1) (Dwg. No. D- TC02-0-6) clears the DTB and generates 1-+ DF pulse at location C15, which
sets the DF flip -flop and requests a data break. The ST REV CK(1) level is gated with the 5T DA TA
(Dwg. No. D-TC02-0-6) to generate tbe WD EN level. This level allows the WREN flip-flop to be
set and enable the data to be written. The WREN (1) output, gated with TP1 produces the first CaMP
RWB 0-2 pulse (Dwg. No. D- TC02-0-6, location D16), which is required for the write sequence
(Dwg. No. D-TC02-0-15, Sheets 1 and 2). With the WREN(l) flip-flop set, the RWB SHIFT LEFT
pulses are produced at the C2(1) transition (Dwg. No. D- TC02-0-6).
The sequence for the write operation is described in Paragraph 3.3.11. If a word count
overflow has not occurred during the previous word, the data flag DF will be set each time the O"'DTB
pulse is produced. If a word count overflow is issued during a previous word, the write sequence continues, but the DF flip-flop is not set with the result that all ZEROs are written in the remaining
block on tape. (See DF flip-flop DCD gating input to set side shown (Dwg. No. D-TC02-0-6.)

3-25

At the end of a data block, the parity check character is loaded into the DTB by the LPB
DTBO-5 pulse produced by the positive transition of the second MK BLK END (Dwg. No. D- TC02-0-15,
Sheet 2), LPB DTBO-5 is produced by MK BLK END pulse enabled by ST FINAL(l), and WRITE DATA
as shown on Dwg. No. D- TC02-0-6. The LPB information is written on tape in the checksum slot the
same as a data word.
In the normal mode at the end of a data block, the positive transition of the ST CK (0) level
will set the DTF flip-flop and, in the continuous mode, the same transition will also set the DTF flipflop provided that a word count overflow WC(O) has occurred during the previous data block (see DTF
gating, (Dwg. No. D- TC02-0-6). The writers are disabled after the parity is written by the WREN
flip-flop, which is reset by the ground WD EN level that is produced when the data state is changed.
The control continues to change states if DTF is not set and begins writing again in the block; the
operations repeat in the same sequence.
3.3.10.6

Write All Function (101) - The Write All function specified by octal 5 in the function

register, allows nonstandard formats to be written on tape, such as the insertion of block numbers or
codes at unusual locations on tape.
This function can be preceded by the Search function, which determines the position on tape
where the information wi II be written and can be implemented at any time after the tape has come up to
speed (after only one C-SYNC level has been generated) which may cause the writing to be displaced
by a half word.
The positive transition of the WRITE ALL level sets the W INH flip-flop as shown on Dwg.
No. D- TC02-0-15, Sheets 3 and 4" and the logic of Dwg. No. D- TC02-0-6. This prevents the WREN
ftip-flop from being set and inhibits writing at this time. The timing sequence for the Write All function
is shown on the timing diagram. The positive transition, when counter flip-flop CO is set, will reset W
INH flip-flop provided that the WC flip-flop was previously set. The 0- DTB pulse is also generated
at this time resulting in a 1 ..... DF pulse requesting a data break to write the first word.
If the Write All function is specified before the middle of the area assigned on tape for a
data word, the first word will be written in the next data area which follows. If the function is specified after the middle of the current data word position, the next data word position will be skipped before the data word is written. The write sequence then continues. Parity is computed during thi s function' but the LPB ..... DBO-5 pulse which is required to write parity is not produced. The state register
continues to shift but has no effect on the operation.
In the normal mode, the DTF (l) wi II generate an interrupt request when enabled by ENI (1)
(see INT logic, Dwg. No. D- TC02-0-11). During the continuous mode, when a word count overflow
occurs, the WC(O) level will set the DTF flip-flop. The WC(O) level, at this time, will alsa set the
W INH flip-flop inhibiting the writing of future words on tape, but the tape motion will continue.
3.3.10.7

Write Timing and Mark Track (110) - The Write Timing and Mark-Track function is used to

format a new tape by recording the timing and mark tracks prior to the recording of data.

3-26

This function is enabled only with the WRTIv\IRDMK/NORMAL switch on the TC02 control
panel in the WRTM position and with the WRITE ENABLE/WRITE LOCK switch of the TU55 transport in
the WRITE ENABLE position. The control panel switch generates a SWTM level which is gated with
MRl (1) and the WRTM level to produce the TM ENABLE levels (Dwg. No. D- TC02-0-10). The
TM ENABLE level activates the 120 kc clock, producing the CKl and CKO outputs which generate the
TPO and TPl timing pulses. The CKO and CKl and TM ENABLE outputs are applied to the T TRK write
amplifier (Dwg. No. D-TC02-0-10) to generate the pattern to be written on the timing track. The
TM ENABLE level (Dwg. No. D-TC02-0-10) resets the Up-to-Speed flip-flop resulting in a 0
WINDOW level, which prevents mark-track information from being decoded (Dwg. No. D-TC02-0-8).
It also resets the DATA SYNC flip -flop preventing synchronization of the control operations.
The WRTM and SWTM levels are gated with associated outputs to produce the WRITE SET
level (Dwg. No. D- TC02-0-6). At the CO(O) transition, the WREN flip-flop is set and enables the
data track amplifiers (Dwg. No. D- TC02-0-l) to write the information contained in the RWB. The
first word that is written on tape, however, will be within the 10 ft of tape designated for the reverse
end code and will not be read during the Read Tape function.
The WREN(l) level allows the RWS SHIFT LEFT pulse, the ROTATE DTS 00-11 and ROTATE
DTS 12-17/RWS pulses, and the COMP RWB 0-2 pulses to perform the write operation as described in
Paragraph 3.3.11. The WREN(l) at CO(l) transition (Dwg. No. D-TC02-0-15, Sheet l) generates the
0-+ DTS pulse, which clears the DTB and sets the DF flip -flop requesting the first word.
The programming format for the mark track requires that the mark-track information appear
in bits 0, 3, 6, 9, 12 and 15 of the data word. The information received by the mark-track write
amplifiers (Dwg. No. D- TC02-0-1) is from RWBO (Dwg. No. D- TC02-0-2). Therefore, the only data
bits which appear in this buffer are bits 0, 3, 6, 9, 12 and 15. This information also appears in data
track 1 on tape, which also receives information from RWBO.
When the WRTM function is completed, the TM ENABLE levels are held active by the SWTM
and WREN (1) inputs.

Enough TPO pulses are produced to cause the CO(O) transition necessary to reset

the WREN flip-flop and turn off the write amplifiers.
3.3.11

Read and Write Sequences
The sequence of events that occur during the Read and Write functions are summarized in

Tables 3-5 and 3-6, respectively. The times of each event are specified in terms of control clock
pulses and timing pulses TP1.

Illustrations of the bit contents of the RWB and DTB section after each

event has occurred are shown in the diagrams in the last column of the tables. The DTB and RWB registers are shown on Dwg. No. D- TC02-0-2 and D- TC02-0-11, respectively.
The events for the read operation in Table 3-5 are programmed to assemble an 18 -bit data
word in the DTB for subsequent transfer to the PDP-9 during a data break. At the start of the assembly,
the first three bits 0 through 2 of the data word are strobed from the read amplifiers into the right half of
the RWB. Bits 0 through 2 are then shifted left into the left half of RWB and the second three bits (3
through 5) of the data word are strobed into R'NB3-5.

3-27

Next, the first 6 bits of the 18-bit data word is

(1)
Table 3-5
Sequence of Events During Read Operation
Event
No.

3
(.oJ

Event
Begin assembly of first
3 bits of data word

Complete assembly of
next 3 bits of data word

Perform barity check of
first 6 its of data word.
Rotate 6 bits of data
word from RWB to DTB

Time of Event
TP1· C2(1)

TP1· C2(1)

C2(0) (i.e., transition from 1 to 0)

ex>

Begin assembly of next
3 bits of data word

Complete assembly of
next 3 bits of data
word

TP1' C2(1)

TP1· C2 (1)

Initiating Input(2)

Resulting Operation (3)

RWB SHIFT LEFT (6C15)

First three bits from R/W amplifier outputs
strobed into RWB 3-5.

RWB SHIFT LEFT (6C15)

RWB:

4 5

Word Bits:

Bits 0 through 2 shifted left to RWBO-2 and
bi ts 3 th rough 5 from R/'N ampl ifi er outputs
strobed into RWB3-5.
RWB:

Word Bits:

4 5
3 4 5

RWB ¥ LPB (6C13)

Compute parity of RWB contents (i .e., bits 0
through 5).

ROTATE DTB 00-11
ROTATE DTB 12-17/
RWB (6C10)

Rotate RWB 0-5 into DTB 12 -17

RWB SHIFT LEFT (6C15)

DTBO-5:

DTB6-11 :

DTB12-17:

4 5

RWBO- 5:

Word bits 6 through 8 from R/W amplifier outputs strobed into RWB3-5. Contents of DTB
same as in event 3.
RWB:

4 5

Word Bits:

Bits 6 through 8 shifted left into RWBO-2 and
word bits 9 through 11 from R/W ampl ifier
outputs strobed into RWB 3 -5. Contents of
DTB same as in event 3.

4 5

RWB:

Word Bits:

9 10 11

-----------

~-.--.---.---

_ ..

Table 3-5 (Cont)
(1)
Sequence of Events During Read Operation
Event
No.
6

Event

Time of Event

Perform parity check of
next 6 bits of data word

C2(0) transition from
1 to 0 COMP RWB

Rotate contents of RWB
and DTB

In itiating Input (2)
RWB ¥ LPB (6CI3)

Compute parity of RWB c:ontents (i.e., bits 6
through 11 in event 5).

ROTA TE DTB 00-11
ROTATE DTB 12-17/
RWB (6CI0)

Rotate DTB 12 -17 into DTB 6-11, and RWB 0-5
into DTB 12-17.

(Repeat for last 6 bit
segment of data word)
7

Transfer complete assembled word in DTB to
PDP-9

Begin assembly of next
3 bits of data word

TPl· C2(I)

RWB SHIFT LEFT (6CI5)

Complete assembly of
next 3 bits of data
word.

TPl· C2(1)

RWB SHIFT LEFT (6CI5)

-0

Perform parity check of
next 6 bits of data word
Rotate contents of RWB
and DTB plus 1'" DTF

C2(0) transition from
1 to 0 COMP RWB

DTBO-5:

DTB6-11 :
DTB 12 -17:
RWBO-5:

0
6
x

1
7
x

2
8
x

3 4 5
9 10 11
x x x

W
I
N

Resulting Operation (3)

Word bits 6 through 8 from R/W amplifier outputs strobed into RWB 3-5. Contents of DTB
same as in event 3.
0 1 2 3 4 5
RWB:
Word Bits:
x x x 6 7 8
Bits 6 through 8 shifted left into RWBO-2 and
word bits 9 through 11 from R/W amplifier
outputs strobed into RWB 3-5. Contents of
DTB same as in event 3.
RWB:

Word Bits:

2
8

3 4 5
9 10 11

RWB ¥ LPB (6CI3)

Compute parity of RWB contents (i.e., bits 6
through 11 in event 5). Request DCH transfer.

ROTATE DTBOO-11
ROTATE DTB12-17/
RWB (6CI0)

Rotate DTB12-17 into DTB6-11, and RWBO-5
into DTB 12 -17
DTBO-5:

DTB6-11 :

9 10 11

DTB 12 -17:

12 13 14 15 16 17

RWBO-5:

Table 3-6
(l)
Sequence of Events During Write Operation
Event
No.
1

W
I
W

Event
Request data word

Data word "n" transferred from PDP-9
to DTB

Time of Event
CO(l)· WREN(l)

Asynchronous with
TC02

Rotate contents of RWB
and DTB and wri te bi ts
o through 2 of word "n"

Initiation Input(2)
0" DTB (6D7)
1" DF (6C2)

lTDB

ROTATE DTBOO-11
ROTATE DTB12-17/
RWB

Resul ting Operation (3)
Clear data buffer and set DF flip-flop to request data word "n" from PD P-9 •
DTBO-5:

DTB6-11 :
DTB 12 -17:

0
0

RWBO-5:

last 6 bits of word "n-l"

la-bit data word "n" transferred to DTB.
DTBO-5:

DTB6-11 :
DTB 12 -17:
RWBO-5:

6 7 a 9 10 11
12 13 14 15 16 17
last 6 bits of word "n-1"

Complement bits 0
through 2 and write
complemented bits

Computes parity of bits 0
through 5 of word "n"

TP1· WREN(l)

COMP RWB 0-2(6D5)

RWB ¥ lPB (6B3)

DTBO-5 rotated into RWBO-5, DTB6-11 into
DTBO-5, and DTB 12-17 into DTB6-11
RWBO-2 provides bits 0,1,2 as inputs to
write amplifiers.
DTBO-5:
DTB6-11 :
DTB 12 -17:
RWBO-5:

6 7 a 9 10 11
12 13 14 15 16 17
x x x x x x
0 1 2 3 4 5

Complement contents of. RWB 0-2 to provide
complement bits 'O,T,2 as inputs to write
amplifiers. Contents of DTB remain same as
in event 3.
RWBO-5:
0 T '2 3 4 5
Compute parity of RWB contents (i.e., bits 0
through 5) at end of event 3.

Table 3-6 (Cont)
(1)
Sequence of Events During Write Operation
Event
No.

Time of Event

Initiating Input(2)

Resulting Operation(3)

Shift contents of RWB to I C2(1)· WREN(1)
Ieft and wri te RWB bi ts
3-5

RWB SHIFT LEFT (6B7)

Contents of RWBO-5 shifted left and bits 3,4,5
provided as inputs to write amplifiers. Contents of OTB remain same as in event 3.

Event

RWBO-5:

Complement bits 3
through 5 and write
complemented bits.

I TP1· WREN(1)

COMP RWB 0-2 (605)

(Repeat from event 3
to write next 2 groups
of 6 bits for a complete
data word)

Request next data word

O-'OTB (508)
1" OF (502)

Data word lin +1 11 transferred from POP-9 to
OTB

Asynchronous with
TC02

LTOB

'3 "4 5

Clear data buffer and set OF flip-flop to request data word lin +111 from POP-9.
OTBO-5:
OTB6-11:
OTB 12-17:
RWBO-5:

VJ
I
W

Complement contents of RWBO-2 to provide
complement bits 3,4,5 as inputs to write amplifier. Contents of OTB remain same as
event 3.
RWBO-5:

CO(1)· WREN(1)

345

0
0

0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
12 13 14 15 16 17

18-bit data word IIn+ll1 transferred to OTB.

IIn+ll1 bits
OTBO-5:

o 1 2 3 4 5

OTB6-11 :
OTB 12-17:

6 7 8 9 10 11
12 13 14 15 16 17
lin" bits
12 13 14 15 16 17

RWBO-5:

accumulated in the LPB.

At the same event time the first 6 bits of the data word from the RWB rotate

into the OTB 12-17. The same sequence is followed to strobe two more groups of six bits through the
RWB and to perform a parity check on them. The 18-bit word is completely assembled in the OTB and
is ready for transfer to the POP-9.
The read sequence in the following table is assumed to start at the reading of a word in the
middle of a data block. The numeral-letter -numeral designations indicate the location of an initiating
input on an engineering drawing contained in Chapter 6.
The events for the write operation in Table 3-6 are programmed to request an 18-bit data
word from the POP-9, store it temporarily in the OTB, and transfer it in 3-bit segments to the write
amplifiers. The first six bits of the 18-bit data word are stored in one section of the OTB(OTBO-5),
and the next six bits in OTB6-11, and the final six bits in OTB 12-17. A rotation transfers six bits at a
time into the RWB and makes the first three bits (0-2) available to the write amplifiers. Each 6-bit
group of the data word is included in the accumulated parity check to be written at the end of the
block. In addition, bits 0 through 2 are complemented and supplied to the write amplifiers. Then the
contents of RWB are shifted left so that bits 3 through 5 replace bit 0 through 2 in RWBO-2. Bits 3
through 5 are now available to the write amplifiers in normal and complement form in the same manner
as bits 0 through 2.
3.3.12

Longitudinal Parity Buffer Operation
The longitudinal parity buffer (LPB) (Dwg. No. 0- TC02-0-2) performs the parity check of

information in the data tracks. Essentially the parity check reads the number of binary ZEROs in each
6-bit group of data word bits and forms a parity bit, which is recorded in the checksum control word at
the end of the data block.

The checksum is computed by complementing the bits of the LPB when the

respective bit of the RWB is a O. The LPB register outputs are gated as shown on Owg. No.0-TC02-0-3
to produce the LPB= 1 and LPB/l levels. If all LPB register flip-flops are not set during a read data
operation, the LPB /1 level will set the parity flip-flop PAR '(Dwg. No. 0- TC02-0-5) indicating that
a parity error has occurred.
At the end of a write data operation, the contents of the LPB is gated into OTBO-5 to be
written after the last data word.
The signals that control the LPB operations are defined in the following paragraphs and are
produced by the logic shown on Owg. No. D- TC02-0-6. The timing sequence for these signals are
shown on Dwg. No. 0-TC02-0-15, Sheets 1 and 2. The 0 .... LPB pulse clears the LPB at the beginning
of each block. Six pulses are generated by TPl during the reverse check state, ST REV CK(1) to initiaize the LPB register for computation of the parity character.

However, only the last pulse is required

for the operation. Note that one RWB ¥ LPB pul se is generated after the last 0 .... LPB i ust as the data
portion of the block is entered (in Read Oata or Write Oata). This is done to include the reverse checksum in the computation of the checksum for the entire block. This allows the tape to be read in the
opposite direction from which it was written yet have the proper checksum.

3-32

The RWB¥ LPB pulse is used to perform the parity computation from the RWB to the LPB.
The parity is computed at the same time ROTATE DTB 00-11 and ROTATE DTB 12 -17/RWB pulses are
generated during a read operation, and at the same time that the COMP RWB 0-2 pulse is produced
during the write operation.
A LPB-+ DTB 0-5 pulse is required at the end of the ST FINAL block to initiate the formation
of a parity bit for recording the checksum control word at the end of the data block.
The enabling conditions used for the generation of the LPB-+ DTB 0-5 pulse are a WRITE DATA
level from the function decoder, and ST FINAL (1) level from the state counter. When a ground MK
BLK END pulse from the mark-track decoding network appears at the gate $603, LPB-+ DTB 0-5 pulse is
produced. This pulse is transferred to the RWB register (Dwg. No. D- TC02-0-2) and DTB register
bits 12-17 (Dwg. No. D-TC02-0-1) to gate information received from LPT 0(1) through LPB 5(1) into
DTB.
3.3.13

Power Clear and Error Stop logic
The power clear pulses (I/O PWR CLR) generated by the PDP-9 processor (Dwg. No.

D-TC02-0-4) are inverted and applied to the PA (Dwg. No. D-TC02-0-5, location C2), with the EF
signal to generate the PWR CLR + ES pulses. The EF signal is produced by monitoring the outputs of the
error flip-flops MK TK (1), SEL(1), TIM (1), and END (1).

When a (1) condition exists on any input

to the NOR gate, as a result of an error, the EF level will be produced. The ground PWR CLR pulses
are used to reset the DATA SYNC flip-flop, WREN flip-flop, DTF flip-flop, and the DF flip-flop
when power is initially applied or removed from the PDP-9. In addition the ground PWR CLR + ES signal will continually set the U+M delay (Dwg. No. D-TC02-0-10) to prevent Up-to-Speed flip-flop
from being set during the detection of an error or when the PWR CLR pulses are received.
3.3.14

Increment CA Inhibit (+1-+ CA INH)
The +l-+CA INH signal (Dwg. No. D-TC02-0-16) is generated during the search function

to prevent the incrementing of the current address. When the current address (CA) is not incremented,
the block number is placed in core memory at the same location for each block number transferred.
3.3.15

Interrupt Request
The INT level (Dwg. No. D-TC02-0-16) from the control is used to initiate a program in-

terrupt in the PDP-9 processor. The interrupt enable is determined by the status of the ENI flip-flop
(Dwg. No. D-TC02-0-7). When ENI is set, either an error flag EF(1) input or DECtape flag DTF(1)
wi" resul t in the request for an interrupt on the API or PI.
3;3.16

Error Flags (EF)
Five flip-flops (Dwg. No. D-TC02-0-5) produce error signals at the occurrence of any of

the errors listed under the Status B functions. When a specific type of error occurs, the error detection
circuits set the appropriate flip-flops to a 1 state.

3-33

The error input conditions that initiate a specific type of error signal are as shown on
Figure 3-10. All error flip-flops are cleared by a ground pulse as shown on Dwg. No. D-·TC02-0-5.
These pulses are produced either by I/O PWR CLR or when an I/O BUS 10(0) level from th4:! PDP-9 and
a XOR STATUS (XSTA) pulse from the device selector appear simultaneously at the gate input.
When any error signal except PAR appears at one of the inputs to the NOR gate (Dwg. No.
D- TC02-0-5, location D2), the gate produces an EF (1) output level. This output is used in forming
the PWR CLR + ES signal. The same output is also passed through an inverter to produce an error flag
EF (1) or EF (0) level. EF (1) and EF (0) levels are also provided when a PAR error signal appears at the
input of an inverter.
The EF (1) level resulting from any of the error signals is passed through another inverter to
produce a corresponding complementary EF (1) level. Ground level EF (1) serves as an input to the BEF
flip-flop (Dwg. No. D-TC02-0-16) for generating an INT (Interrupt) level while the -3V EF(1) level
is used as an input to a gate (Dwg. No. D- TC02-0-4) to generate SKIP RQ.
EF (1) and the set outputs from the error flip-flops enable inputs to the I/O BUS 00-05, and
are pulsed onto the bus by STB I/O BUS, which is generated from the command RSTB (read status B
register).
3.3.16.1

Mark-Track Error (MK TRK) - A MK TRK error signal is produced by MK TRK flip-flop

(Dwg. No. D- TC02-0-5) when information read from the mark channel is in error. When MK TRK
errors are detected by the input gating, the gating output enables the DCD input gate of the flip -flop.
The ground CO(O) pulse from the control clock indicates that a 6-bit character has been read from the
mark track and is in the window register. This CO(O) pulse sets the MK TRK flip-flop under certain
enabling conditions.
One input to the MK TRK gating circuit represents one of four mark-track codes - MK BLK
START, MK DATA, MK BLK END, MK END. These codes appear at times throughout reading of DECtape.
Other inputs to the gating circuit prevent MK TK error indications during a MOVE function
and during the ST IDLE and ST BLK MK intervals. These intervals are indicated by -3V ST IDLE (0) and
ST BLK MK (0) levels. The MK TK decodings are not valid during the ST IDLE and ST BLK MK intervals
because the control may not be synchronized with the DECtape at these times.
3.3.16.2

Select Error (SEL) - A select error signal is produced by the SEL flip-flop (Dwg. No.

D- TC02-0-5) when any of the select errors are detected. After the input gate is enabled by a select
error condition, the flip-flop is set by a ground XSA DY pulse at the gate input.
The following conditions wi II result in setting the SEL flip -flop.
1. WRTMA' SWTM:

MCP switch is not set on WRTM while PDP-9 program is attempting to

write timing and mark data on new tape.
2. WRTM A SWTM:

MCP switch is set on WRTM while the PDP-9 program has specified

another function.

3. FRl (l) A WRITE OK: DECtape transport control switch is set on WRITE LOCK while
PDP-9 program is attempting to write.

3-34

MK TK (I)
(MARK TRACK
ERROR)

END (I)
(END ZONE
ENTERED)

SEL (1)
(SELECT
ERROR)

PAR (I)
(PARITY
ERROR)

TIM (1)
(TIMING
ERROR)

NOTES:
1. MK TK iI)-

SEL (1).

XSA DY II [(WRTM'" SW'mlll (FRICI)
II{WRITE OK)OV(WRTMIISWTM)V
(RDMK II REA ALL)]

PAR (1l -

STCK(O) II READ DATA II LPB "I< 1

TIM (0-

(1-DTFIIDTF(I))V(ST BLKMK(O)II
ST Il'LE(OllV(RD +WDIIXSAD)V
ROTAIT DTB 12-17 RWB II (DF(1) V
DTENA (11 II DTENB(ll)

Figure 3-10

Error Check Flow Diagram

3-35

NO
PROG. INT
REQUEST

4. RD MKA READ ALL: MCP switch is set on RD MK but Real All function is not specified
by the PDP-9.
In addition to the conditions listed, the single unit comparator circuits shown on Dwg. No.

0- TC02-0-5 monitor the single unit line from the TU55 transports and generates a select error (SE)
output if the line indicates either no units or more than one unit have been selected. This is effectively
accomplished by noting the resistance of the Single Unit line and generating a ground select error level
(SE) if the resistance is not within the specified limits.
With no units connected, the voltage at pins E and K of comparator W520 is -9V. The
voltage at pin 0 and pin L is held constant at -7.5V and -5V, respectively, by the resistance network
consisting of R1, R2, and R3. When this condition exists, pin 0 being more positive than pin E will
cause a ground level SE output at pin H indicating a select error. When one unit is selected, the resistance of the line which is effectively in parallel with resistor R5, results in a voltage at pin K which
is between the constant voltage at pin 0 of -7 .5V and pin E of -5V. This voltage condition prevents
the difference amplifiers from conducting, and the output at pin Hand N will be -3V indicating a noerror condition. If more than one unit is selected on the line, the resistance in parallel with R5 will be
decreased resulting in a voltage at pin K more positive than the -5V at pin L and the difference amplifier will conduct, resulting in a ground SE output at pin N.
3.3.16.3

Parity Error (PAR) - A PAR error signal is produced by PAR flip-flop during a Read Data

function if the LPB check at the end of the data block does not equal 1. This condition enables the
DCD gate to the flip-flop. Then a ground ST CK (0) pulse at the gate input sets the flip-flop. A
ST CK (0) pulse occurs at the end of a data block.
3.3.16.4

Timing Error (TIM) - A timing error (TIM) is produced by the TIM flip-flop (Dwg. No.

0- TC02-0-5) when any of the TIM error conditions listed in Table 2 -4 are detected.
One operation that produces a timing error is to ROTATE DTB 12 -17/RWB when a OF (1)
exists as shown on Dwg. No. D-TC02-0-5. An error occurs because the data in DTB is no longer the
same as it was at the instant the OF was set. The illegal operation is indicated to the TIM flip-flop
when a ROTATE DTB 12 -17/RWB ground pulse appears at the DCD input gate at a time when the gate
is enabled by a OF (1) ground level. The error is also indicated in this way whenever DTENA (1) or
DTENB (1) exists, when the ROTATE pulse arrives.
Another TIM occurs when a 1 .... DTF ground pulse appears at the input to the DCD gate of
PA 5603 at a time when this gate is enabled by a DTF (1) ground level. This illegal condition indicates
that the TC02 is attempting to set the DTF at the end of a current operation, but that the program did
not clear the DTF at the end of the last operation. The error is indicated to the TIM flip-flop by
collector triggering the TIM(1) output with the ground level generated by the amplifier.
A third TIM occurs when -3V levels appear simultaneously at each input to the 4-input
NAND gate (Dwg. No. 0- TC02-0-5, location C3). This condition is illegal because it indicates that
an attempt is being made to read data or write data (RD+WD) while passing over the data position on

3-36

the tape. The -3V ST BLK MK (0) and ST IDLE (0) input levels indicate that the head is not passing over
the ST BLK MARK and ST rOLE blocks and therefore is passing over the data position. The -3V XSAD
input is a standard 100 ns pulse which is generated 400 ns after receipt of an XOR STATUS A pulse.
When all inputs to the NAND gate are -3V, the resulting ground level is used for collector triggering
the 1 output of the TIM flip -flop.
3.3.16.5

End Error (END) - In normal operation the window register contains an end zone code (222)

when the end zone of the DECtape is reached. At this time, the ground level at the window decoder
output serves to enable the DCD input gate to the END flip -flop. When the next TPO appears at the
gate input, the flip-flop is set. A ground level at the 0 output of the END flip-flop indicates an error
that is not expected by the program but is legitimate if used to indicate the end of a normal operation
(e.g., rewind).
3.3.17

DECtape Flag (DTF)
The DECtape flag (DTF) network in the top center of Dwg. No. D-TC02-0-6 provides ap-

propriate DTF output control levels which indicate the completion of specific operation.
DTF flip-flop is cleared by either collector triggering its 0 output with a ground level from
NAND gate S123 (Dwg. No. D-TC02-0-4) or by the appearance of a PWR CLR ground pulse at the
direct clear input. A ground level for clearing through the 0 output is provided when a -3V I/O BUS 11
(0) level from the PDP-9 and a -3V XSTA pulse appear simultaneously at the input to the NAND gate.
When cleared, a ground 1- DTF pulse from one of three input gating circuits wi" set the flip-flop to a
1 state.
The inputs to gating circuit location C6 indicate the conditions listed below.
a.

FR3 (l):

selection of anyone of the SEARCH, READ ALL or WRITE ALL functions by

the function register.
b.

WRTM:

selection of WRTM function by function register.

FRO(l): selection of CM of operation.

When a FR3 (1) or WRTM ground level and a -3V FRO (l) level appear at the gating circuit
input, with the DT ENB(l) and the I/O ()fLO pulse, the resulting ground level provides the 1- DTF.
This sets the DTF during CM and Search, Real A", Write A" or WRTM.
One of the DCD input gates to PA S603 is enabled when a -3V WRTM + FR3 (l) and a -3V
FRO (O)(indicating NM) appear simultaneously at the inputs to the NAND gate. Then when a ground
CLR OF pulse is applied to the DCD gate, the PA generates the desired 1- DTF pulse. This sets the DTF
during NM and Search Read A", Write All or WR TM.
Another input gating network controls the generation of a 1- DTF pulse at the start of the
parity check in the NM or CM. In the NM, either a ground level Read Data or Write Data input from
the function decoder plus a FRO (0) level input enables DCD gate 6C4. Then the appearance of a
ground ST CK (0) from the state register at the start of the parity check causes the desired 1- DTF pulse
to be generated. In the CM, an enabling input is applied to the DCD input gate when the RD+WD,

3-37

FRO (1), and we (0) inputs are at -3V. This sets the DTF at the end of the Data Block in Read Data or
Write Data taking into account the NM or eM and weo to produce the DTF settings as defined earl ier.

3-38

CHAPTER 4
INSTALLATION

This section contains general information on the installation and maintenance of the TC02
DECtape control. The installation procedures refer to a single cabinet installation of both TC02 control
and two TU55 D ECtape transports. Installation information for mounting additional TU55 transports or
TC02 control in an existing cabinet is available upon request.
4.1

INSTALLATION PROCEDURES
The TC02 DECtape control and associated TU55 transports are shipped with the cabinet at-

tached to the PDP-9, as a single unit cabinet mounted and crated, or as individual units to be installed
in an existing cabinet. The installation information in this chapter refers primarily to cabinet mounted
units as the requirements for separate units vary according to the needs of the specific system.
Upon receipt of the unit, an initial visual inspection should be performed to insure that no
obvious physical damage has been incurred during shipment.
4. 1 .1

Site Preparation
No special site preparation is required for the installation of the TC02 unit. Adequate

clearance must be provided for proper installation and for servicing. Figure 4-1 shows the installation
dimensions required by the unit.
SWINGING
PLENUM ~
DOOR

SWINGING
DOORS 121

50!!.·
TC02
TAPE UNIT

L__ r

~ JL

22.L
4 ~

27i'
8

SWINGING
DOORS 121

CABINET FRONT

Figure 4-1

TC02 Unit Single Cabinet Installation Dimensions

4-1

When the cabinet is not physically attached to the PDP-9 console, both the power and signal
cables enter through holes provided in the base of the cabinet. Casters are mounted on the cabinet base
to enable the unit to be easily positioned and to allow sufficient clearance for the cables. No subflooring is normally required.
4.1.2

Environmental Conditions
The environmental conditions for the proper operation of the TC02 control unit are limited by

the magnetic tape used with DECtape. The acceptable environmental conditions for the magnetic tape
are an ambient air temperature between +60o F and +80o F with a relative humidity level between 40%
and 60%. The TC02 DECtape control operating environment is the same as that required by the PDP-9
processor.
The installation site must also be as free as possible from excess dirt and dust, corrosive fumes
and vapors, and strong magnetic fields.
4.1.3

Power and Cable Requirements
The TC02 control and associated TU55 transports operate from single phase line voltage of

105V to 125V, 60 cps. The maximum current requirement is dependent on the number of TU55 transports
included in the system. The maximum current requirement for the TC02 control is 4A, and each transport requires approximately 2A maximum. A Hubble, 3-terminal, 220V twist-lock flush receptical
rated at 30A with ground neutral should be installed near the site of the cabinet to allow connection to
the power cable supplied.
Figure 4-2 shows the internal and external cable interconnections as viewed from the rear of
the cabinet. All other interconnections between TC02 panel assemblies are facilitated by the panel
wiring which is exposed to the front of the cabinet.
Panel locations EF01 through EF04 are connected by panel wiring to panel locations EF05
through EF08. This allows the interconnecting cables to the PDP-9 processor to be attached to the bottom of the TC02 unit and the cables to additional peripheral units to be connected next to these.
4.1.4

DECtape Signal Connectors
A description of the cable connectors are listed in the Digital Logic Handbook, Doc. No.

C-105 by the identification number shown on the system drawings of Chapter 6.

4-2

TO ADDITIONAL
TU 5 5 TRANSPORTS

1
U
6

TU55

3 2

AC POWER CAB LE

I
3 2

111111

0
A

TU55

2
AC POWER CAB LE

I
3
COMMAND
CABLE

111111

INFO CABLE

r=ll

CONTROL PANEL

DTA

I--

-1 r-D
j----

SW ITCH CABLE

DTB

12 1110

I
DTC

DTD

IIO BUS

'-----..------I

TO PDP-9 PROCESSOR

FIXED

PWRSUPPLY _

DTE

1110 9

8 7 6 5 4

3 2 I

BLOWER

Figure 4-2

TC02 Control, Cable Diagram

4-3

DTF

--- I--

FROM
110 V. 60 CYCLES

CHAPTER 5
MAINTENANCE

The information contained in the following paragraphs is required for servicing the TC02
DECtape control.

Information pertaining to the TU55 transport is contained in the TU55 DECtape

Instruction Manual listed in Paragraph 1.4.
The maintenance procedures contain a description of the switches and indicators on the
maintenance control panel and general preventive maintenance instructions. When used in conjunction
with the PDP-9 operating program and the TC02 maintenance programs, the control panel provides a
visual indication of the operating state and content of the TC02 control.
5.1

MAINTENANCE EQUIPMENT
Table 5-1 is a list of the equipment recommended for servicing the TC02 control in addition

to the standard hand tool s normally requi red.
Table 5-1
Maintenance Equipment
Equipment

Manufacturer

Model

Multimeter

Triplett or Simpson

630 - MA or 260

o sci Iloscope

Tektronix

Series 540 or 580, with
Type CA differential
amplifier or equivalent

Head Cleaner kit (8705)

Potter

PIN A 425 484

Variable Power supply

DEC

(from PDP-9)

Module extender*

DEC

W980

* Furnished with the PDP-9 Processor
5.2

MAINTENANCE CONTROL PANEL
The maintenance control panel is located at the cabinet front, behind the access doors. The

panel contains a switch used in the operation of the TC02 and indicators which display the status and
information in the control.
Table 5-2 lists the function and panel designation of the switch and indicators shown on
Figure 5-1. The number of indicators for each designation is enclosed in parenthesis.

5-1

ST~TUS

WC ROY US

OS OCH API OTF OF

f-~i-k4IR441"IR)~~~CCCCCCCCC
uS~

ENI

DATA BUFFER

11.1 ]( x x)( I I )( I I )( I I ]( I X,:~

•

STATE

•

LPB

RWB

"cccccel 1)( X 1](1 'l'" I 1
8MRC

COUNTER

WRTM NORM ROMK
LA,

k"s,Sr,m!!n'&bP4la lT4'4li4~lhL1IJ4
Figure 5-1

ERRORS

END

PAR

TIM

Maintenance Control Panels (Switch and Indicators)
Table 5-2
Swi tch and Indi cators
(Maintenance Control Panel)

Designation

Function

STATUS (Indicators)
USR (3)

Indicates the contents of the unit select register.

MR(2)

Indicates the status of the motion control registers
which selects; stop, go, forward, reverse.

FR (4)

Indicates the contents of the function register.
FR (0) Normal/Continuous Mode.
FR (1 -3) Octal code of the selected function.

ENI (1)

Lights to indicate that the TC02 is enabled to the
PD P - 9 program interrupt.

US (1)

Lights to indicate that the selected TU55 transport has
reached the required speed for reading or writing.

ERRORS (Indicators)
MR {Indicator)
(1)

Lights to indicate that a mark -track error has been
detected.

END (Indicator)
(1)

Li ghts to indi cate that the end of tape has been

detected.

5-2

Table 5-2 (Cont)
Swi tch and Indicators
(Maintenance Control Panel)
Designation

Function

SE (Indicator)
(1)

Lights to indicate that a function select error, or no
transport selected, or more than one transport
selected.

PAR (Indicator)

(1)

Lights to indicate that a parity error has been
detected.

TIM (Indicator)
(1)

Lights to indicate a program timing fault.

STA TE (Indicators)
BM(1)

Lights to indicate that the Block Mark state is
activated.

RC (1)

Lights to indicate that the Reverse Check state is
activated.

D (1)

Lights to indicate that the Data State is activated.

F (1)

Lights to indicate that the Final State is activated.

C (1)

Lights to indicate that the Check State is activated.

1(1)

Lights to indicate that the Idle State is activated.

DATA BUFFER (Indicators)
(0-2)(3-5)(6-8)(9-11 )
(12-14)(15-17)

Indicates the content of the data buffer register.

RWB (Indicators)
(0-2)(3-5)

Indicates the content of the read/write buffer register.

DTF (Indicator)
(1)

Lights to indicate that the DECtape flag is set.

DF (Indicator)

(1)

Lights to indicate that a data flag is set requesting a
data break.

W (Indicator)
(1)

Lights to indicate that the write enable level is
activated.

LPB (Indicators)
(0-2)(3-5)

Indicates the content of the longitudinal parity buffer.

COUNTER (Indicators)
CO, C1, C2
DCH (Indicator)
API (Indicators)
US
DS

Provides indication of the count function of the counter
register used for mark -track decoding,..
Li ghts during DCH request.
Lights during API request.
Up-to-Speed flip-flop
Data Sync flip -flop

5-3

5.3

DEC MODULES
The standard DEC modules used on the TC02 control are described in Digital Logic Handbook

Doc. No. C-l05 except for modules described in the following paragraphs. One spare module of each
type is generally recommended to facilitate maintenance of the TC02 control.
5.3.1

Module Locations and Complement
The position of the modules within the mounting panels, as viewed from the wiring side, is

shown on the Module List Drawings of Chapter 6. Each module is represented by a rectangle with the
module type designation at the top. Each rectangle in turn is subdivided to show the circuits that are
contained on the module. In general, the circuits are identified by the logic signal(s) available at the
circuit outputs.
Table 5-3 lists the type and quantity of modules used in the TC02.
Table 5-3
TC02 Module Complement
Number
Required

!lE:.

Description

G853

Speed and Unit Circuit

G882

Manchester Read/Write Amplifier

R002

Diode Network

R113

Diode Gate

R201

Flip-Flop

R302

Delay (One-Shot)

R303

Integrating One-Shot

R401

Variable Clock

S107

Inverter

S111

Diode Gate

S123

Diode Gate

S151

Binary-to-Octal Decoder

S202

Dual Flip-Flop

S203

Triple Flip-Flop

S205

Dual Flip-Flop

S602

Pulse Amplifier

S603

Pulse Amplifier

W018

Connector Board

W103

PDP-9 Device Selector

5-4

Revision

Table 5-3 (cont)
TC02 Module Comp,lement
Number
Required

Type

Description

Wl04

PDP-9 I/o Bus Module

Wl07

High Impedance Follower

W520

Comparator

W850

I/o Cable Connectors

5.3.2

Revision

Circuit Description
The following circuit description is provided to supplement the information in the Digital

Logic Handbook C-l05, and the circuit diagrams of the modules of the system follow.
MANCHESTER READER/WRITER G882 (Figure 5-3)
The Manchester Reader/Writer G882 is a standard size FLIP CHIP module for use in reading
and writing one channel of Type TU55 DECtape. Each module contains two write amplifiers and one
high-gain differential read amplifier. The read amplifier saturates with a 1 mV input.
Module Characteristics
The terminals for the module are shown in Figure 5-3. The input and output characteristics
are as follows.
Reader Inputs E, D - are differential signa Is centered at ground. The input impedance is
approximately 400 ohms to ground. A nominal input signal is a sine wave between 5 kc and 30 kc.
Reader Outputs U, V - are standard DEC levels of -3V and ground. The outputs can drive
10 mA of load at ground.
Writer Inputs - N, R, and P are standard DEC levels of -3V and ground. The input load of
2 mA is shared by the inputs at ground level.
Writer Outputs - J and K, are nominal 180-mA current pulses from ground to -15V. The
power requirements of the module are +10(A)/18 mA and -15(B)/235 mAo The marginal check limits
in both cases are ±20%.
Both the reader and the writer circuits are returned to a common C, F ground.
5.3.3

Module Replacement Procedure
When necessary to remove modules, the procedure is as follows.
a.

Turn off all power to the Type TC02 DECtape Control.

5-5

Gently pull the module from the mounting panel. Use a straight even pull to avoid

damage to plug connections and the printed-wiring board.
Access to adjustment controls on the module or access to signal tracing points can be gained
by removing the module, connecting a Type W980 Module Extender into the mounting panel, and inserting the module into the extender.

R7
',000
B

-15V

01
0664

R3
I,!SOO

R5
120
2W

~ g~64

1,000

R2
470
R4
180
1/2W

C2
2.2 MFD
20V

R'
100

Po----::-1~E

RI
1,000

CI
2.2 MFO

2QV

C
GNO

R8
100

o-------1i----------Wv-F
- +

UNLESS OTHERWISE INDICATEO:
RESISTORS ARE 1/4 w. 5%

Figure 5-2 G853 Speed and Unit Circuit

5-6

"
A +IOV
K

~. ~ U
06

D4
R

R20

R22

R24

R37

R35

~
""

+
-

R28

R26

.---

dfc-~
~d~ ~13 fell
K~:
IT
~~
(i/
~010 (~
R12' tl5tl~ Q6 ~
,[
013

R39

R40L .. 023

RI4

012
, 02

RI8

~cD14

DID

R34

RI5

, 03

R3I

011

f'\..

012

CIO

RI3

~fRI7

RI9

R21

R23

R25

R27

•

DI7 019
R30

e,F GNO

~~D21

V
R33

, D27

, D26

f--RI

....

RIO

~.
RI6

*C4

R29

R32

'D25

'D24

R36

R38

~~ 022

4B -ISV

08 09 012 QI3
06, Q7, QIO,QII
05
Q2,04
R39
R36, R38

1503099
1300241
1:300318

R30, R33

RES.

1/4W

1300432

Q 1,03

R 17 THRU A21,R23,R25 THRU R2B,
R12, Rl3
R6, R 14, R35, R37

31<

RES. 220

1/4W 5% CC
RES. 560 1/4W 5% CC
RES. 68
2W 5% CC
~R4,RII
RES. 750
1/4W 5% CC
R3,R7,RIO,RI6 ,R22 ,R24,R29 R31,R32,R34 RES. 1.5K il4W 5% CC
RES. lOOK 114W 5% CC
~RES. 7.5K 1/4W 5% CC
~--DIODE 114M 6.SAc
~-3.9V
DIODE IN748
DIODE IN756A B.2V
DIODE 0670
THAU 027
DIODE 0662
01,04,07 THAll ~D, 015 THAU 020
OIODE 0664
CIO,CII
CAP. I 200MMF 100V 5% D,M.
C5
CAP. 2.2 MFD 20V 10%
CAP. 3.9MFD 10V 10% S, TANT
C4 C6 C7 C8 C9
CAP. . 47MFO 20V 10% S. TANT
C3
CI,C2
CAP. 680MMF 100V 5% O.M.
PARTS LIST
REFERENCE DESIGNATION
DESCRIPTION
-PARTS LIST

4#---~3L14

~~1<:,,1)24

I
,

------ -- -"lOS'. l;z~

Figure 5-3

1502979

TRANS ISTaR DEC363BB
TRANSISTOR DEC3009B-S
TRANSISTOR DEC3009A-S
TRANSISTOR DEC350D 5
TRANSISTOR DEC2894-3B-S
RES. 120 1/4W 5% CC
RES. 470 1/2W 10% CC

G882 Manchester Read;Write Amplifier

I", I""

1503100
1501999
1503209

1300271
1301890

1302308
1301401
130039 t
1302466
1301422
1100102
1100121
1103441
1102162
1100113
1100114
1002430
1002627
1000064
1005965
1000026
A PL-G8B2-0-0
PART NO.

DID

~
0"4

01'4
DI

0664

0664
D8

0664
ON

0664
D7

p.:

0lS4

D664

0664
DI

0664

Figure 5-4

R002 Diode Network

a-Isv

.,.

15.000

D20
0684

027 028

D2.
0664

A+ lOY

II --1

I
1

15,000
DI2
0114

v
DIS 017

1
1
I

03
DECS8SI1 1

DII
0664

1
II

"" II
~.oo

D 2.1

D23 1

D221

MFD

D21 I

-av,nAn

UNLESS OTHERWISE INDICATED;
RESISTORS ARE V4 W, 5%
DIODES ARE 0662

Figure 5-5

Rl13 Diode Gate

5-8

.co

1
C IIIID

Ql+KM AI
C GND

.S
100,000

4~'0
;>£
~2

0.,

•

DII

3ge

100

DI2

~22

D-"Z

D2I

DII
D-112

e: 1I.

DII

D....

•

~24
"

D25

CI
100

04"!i

D ••

39C

•

L Ii

•z

IS,DOD

••

.1
ISjlOO

IS,DOD

DII

~
"

D35

""-

CS
IOD

D-_

oal

~?D

fun'tn

18,000

D49~

0<8

1~52

~ DIC

'?P

D21

1 f21

"1"·0"

D••

~12

II!,OOO

100,000

DIll
D-112

DIO

4~0'3

0.2

RIO

'~12
DI1
p.az

cal

O-. .Z

4,100

4,700

R'
I!!,OOO

.11

IS,ooo

.15
IS,DOO

.'2
IS,DDO

.14

.11

.'S
IS,DOO

15,000

ISPOO

R"
IjlDO

a-ISY

UNLESS OTHERWISE INDICATED'

~=='-::EI=:~g%

DIODD ARE 0-11.

Figure 5-6

R201 Flip-Flop

r-------------------------------------------------------------_.-------------------------------~~o_----------~O +~ov
r-_1~--~--------_1~----._------------_1~----~~~--._----_.--~----~--------~----_1~------------~~~~-.~D~3~2~~-oCGND

018
0662
015
0882
01'
0882

0862
030
0662

013
0682

RIO

09
R2
1,500

R23
100

012
0682
011
0662

1.. 500

RI
1,500

+CIO
.....,='-"'!.-"'--------+------..... 0862
031
39

+C5
39
-liFO

RI2
7,500

RI'
1,500

R2'
1,500

.--.-+.....

025
RI5
1,500

-liFO
10%

029
0682
028
0662
027
0882

1128
7,500

L-----~----~~--~~-t~~~------------~~--~~~----~~--~~--_1~~--~~~~~~------------~~---t-R~2~7-------oB-15V

RI3
1,000

1,000

Ko-"'\A/V'-+----o L

R25

RII
20,000
112W
BOURNS Oil
DAYSTROII

011

UNLESS OTHERWISE INDICATED:
RESISTORS ARE II.W; 5 ...
CAPACITORS ARE MIIFD
DIODES ARE 088.
TRANSISTORS AilE DECaln

Figure 5-7

R302 Delay (One-Shot)

5-9

021

023

20,000
112W
BOURNS Oil
DAYSTROM

....
0'

100,000

·11

15,000

05
0 ..5

0-664

01'

0-664

UC>-<

, D.

0-664

~€64 O~J4

D~l~4

r([,

'f.;1!, ~

0--66

Oil

. .05

.... lij~

017
4,700

2N3eos

'l?

012

....
o.

1,000

022

.o.

3,000

~C~OO~

017
0-664

01'

RI.

,ok

I,oao

~~1Io
100
3,0

CO NO

...

~~9

0664

15,000; 5'11

....'0
CII
.01

0215

~"C?

•

@IO V

020
0-664

0,.

~
.31

3POO

02'
02.
022
021

...

~500

02.

025

09
20,000

IOV( AI

027

1,500; 5%

15,000

9.4

010

012
5.0

Df*

FC~22

••

1,500

-664

015

4.700

0-664

013
•2

~r....

ROO

ftl.
4,700

....

C2
.001

'F g27 ' f.';7.

WElTON

021
7,eoO

- C9
~ ~~8
a9 + 3.

I-

02.
1,500

...

025
7,500
5'"

02.
1,500
5'"

02.
•• 0

O. o
•• o
8-15

V
UNLESS OTHERWISE INDICATED:
RESISTCRS ARE V4W,IO%

s p

DIOOES ARE 0-662,
... II A 27SP
TRANSISTORS ARE DEC 3131. CAPACITORS ARE "'D

Figure 5-8

R303 I ntegrating One-Shot

, - - - - - -.....------_OA+IOVIAI
,---~-------------------~R-5----~~R-1--------.-R9----------------S=----.-R-I-2---.----.....-----r~--5-----1~~rR-I-1--------~Jlc GNo
1,000

15,000

1,000

ENABLE

016

1,000

100,000

',8:200

019

C6
82
R

p1~200
N~
030
0662
031

R6
3,000

0.15

RB
1,000

Moj F

015

2.2

0662

o1IflI---i

RI4

10%

15,000

RI6
3,000

R20

3,000

RIB

7.500

L-----~--------------------------------------------------------------------------------4-------4-------r_------~_oB_15V

UNLESS OTHERWISE INDICATED'

~~~SA~E'',t:~g."
DIODES ARE 0-664

TRANSISTORS ARE DEC 36311-0
RII IS A _215P

Figure 5-9

R401 Variable Clock

5-10

r--------,

: EX;::iE I

r - - - - - - . - - - - - - -....- - - - -.....-----___<~-----.....-----l;_<I>---+_------oA.,OV(A)
1
R7
1
RI
R2
R.
R5
R.
R3
100,000

100,000

.-------..,

r-----J

r---+_--.---~--....--_+--.....---~--._--_+--._.--r1~-~--~-~~-~,-oCGND
08

0-662 I

D9
I
0-6621
I
DID
I
0-662 ~

L--+--~~~~--~~~4_--+_~-~--~~~_+--t_--4_+~~~==~~-~.
R9
3,000

011
I
0-662 '

RIO

RI,

3,000

1,&00

t---~--~---+---t--~~-~>---+---~--~--~·--+-+--~-~~I--+-*_~3~V--r,-OB-Iav
DI.
0-662

RI7

I!SPOO

020
0-662

~~~oo 1

RIS
15,000

L:T_R~~:_J

____ J 1
D2.

D27

D2.

UNLESS OTHERWISE INDICATE 0:
RESISTORS ARE 1/4W;5%
DIODES ARE 0-664
TRANSISTORS ARE DEC 36398
PRINTED CIRCUIT REV. FOR
DGL BOARD IS SIA

Figure 5-10

S107 Inverter

,--------------._--------------.-----------------0 A + 10V(A)
r ,--'
I
I
I
I

~b,oool

I
I

0~6'!

I RI
15,000

0-664

,--,

01.

Oil

06
0-66'

010

0-664

F I

012

0-684

017

013

D_O~64 ~

DI.

I
I

019

I
I

r - - - - - - - - - + - - - - . - - - - - - - - - - - 1 - - -.....------.-~.....---~-oC GND

0-8&4

0-664

'POOl
5% 21

R,
15,000

R7
1&,000

3,000

5"4

I L----~-~---------___<~--~-----------*_--~-------_r~-~~~.-I.V
1_ ~X~M~~ ...EC!!:.5.J

:~!Z.!~J

UNLESS OTHERWISE INDICATED
TRANSISTORS ARE DEC 3639
RESISTORS ARE 114W;10%
DIODES ARE 0-662
PRINTED CIRCUIT REV. FOR DGL BOARD IS SIA

Figure 5-11

5111 Diode Gate

5-11

.,.

r-------------~--------------t_------------~--------------._------------_.-----------oA+IOV

••

100,000

.,7

100,000

IAI

100,000

r--------+----t--------+----~------_1----~------~r_--~--------t_--_t-----oC GNO

RIO

7,500

RI6

7.500

1,'00

1.'00

L-------------~--------------~------------~--------------~------------~~--------_oB-I&V

UNLESS OTHERWISE INDICATED:

TRANSISTORS ARE OEC3839
RESISTORS ARE 114W, 5"
DIODES ARE 0664

Figure 5-12

S123 Diode C7ate

A.IO"~)

RI
100,000

RO
100.000

••

.3
100,000

••

100,000

••

•7
100,000

.6
100,000

100,000

~" ~.. ~.. ~.. KO" k)" KO" (>'"

>----:9
N '

~2
p

'~oa

•• ,

.'0
1It,000
D33
D-81"

la ,DOD

~~I
t' FF~ ~

' 112' ~.

11>0'

RI3
11,000
DM
1)..662

RI2
D•• J8,DOO
D~62

, . '117

~O.

~'O ~II

" D37

laZ~o

12 ' ~. ~I.'

D-882

>--

031

.0.
3,000

3,DOO

RI6
~,
18,000
D3.
D-662

II '

~~:.

r
CI

MFO

D-6ii

~.. 4~oo '~21 ' ~OO'

~9
r~o

,~:O

~" 8,6 ' ~17

~,~o

f8'::'
j~32

.23

~~~

RIa
D3. 11,000

>-----9v 7

UO
3,000

'~:O
~662

0-182

I--

jo.o

.01
',000

~~::..

D....

D34 ,a,ooo
0-862

. ~.

I).M!

RII

'~28

3,DOO

0.7

.20

•

'~07

• 006

'1re~6
D-Ill

'~:"
0.._

CGND

B-Iev

~~2

~24
UNLESS OTHERWISE INOI CATED:

2' FF~ ~

RESISTORS ARE 1/4Wi'%
TRANSISTORS ARE DEC 313••

.. OF:~

DIODES ARE D-_

Figure 5-13

S151 Binary-to-Octal Decoder

5-12

~D43

~~D45

~l
R4
100,000

rD4

~
0

D~~

014'
0-662
013
0-662

O-S

£.i

08
R3

19' o~

AlD47

048

O--OP

>--OV

Fo'l,p001 POlS

@
---*- ~~~62
CI
82

C3
82

019

~
r

A .. IOV{Al

025

'029

022
r

D-662

023

R 14
100poe

028
1P 6-662

Oil
R7

A~D50

027
RI3

--""

?''1

RI8
100,000

035

D.!4

033
0-662
032
0-662

Dj7

C GNO
C4

"
,

042
0-662

12,000
lOY.

OTHERWISE

~07

R5
3,000

RS
3,000

~012

12,000
10%

RIO

12f~~

RII

12,'1:'-2

RI2

051

INDICATED

02"

'lg~~

RI5

3,000

RI7

RIS
3POQ

052

TRANSISTORS ARE DEC 3639C
RESISTORS ARE 15,000
RESISTORS ARE 1/4W,5"0
CAPACITORS ARE MMFD
DIODES ARE 0- 664

~~031

RIO

12,000
10'"1.

030

C5
.01
MFO

RI
12,000
10%

UNLESS

~4"~ ~D4'

~D44

R20

,,041
0-662

040
0-662
039
0-662

121'8~

B-15V

~
1,500

USE THE ETCH BOARD OF THE R202

1;::::::7::;;::::::1

Figure 5-14

5202 Dual Flip-Flop

A.t(Jl(A)

C GND

D4S

0-662

04"

0-112
04"
0-662
043
0-882

-!O.
R2"

1,500

UNLESS OTHERWISE
REslSTO RS

ARE

INDICATED'

114 Wi 5%

CAPACITORS ARE MMFO
DIODES ARE 0-664
TRANSISTORS

ARE DEC 3639C

Figure 5-15

5203 Triple Flip-Flop

5-13

~056

054

_'053

r---o

>-()L

R8
100,000

R'
D6

1'03
CI
100

IOOPOD

'~662

'8~662

,g~62

D24

l ' D 27 ~

D30

C4
100

029

C3
100

"'"R2
RI
15,000 IS,ooo

F!S31XXl:

~
D
0-662

D32

0-662

~ 045

048
C GND

C6
100

D41

~?8
-662
'8~l62

DI.

R7
R6
3,000 10,000

:',!5

RIO
RI2
10,000 10,000

j'!4

DOl

036

RI3
RIS
RI7
RI'
15,000 15,000 15,000 3,000

3,000

R22

R"
15.000

15,{XX)

052
0-662

~~~D

'g~62

".:3

RI8

D51
0-662
C7
.01
MFD1

I 0

D28

DII

;t.&0

R20
100,000

100,000

DI2

... .

DK)

>--OT
RI6

I 0

061
Af.IDV{A

'8.'~

05.

>-()U

021 1

017

~~057 ~

D4.
0- 662

R24
15,000
B-15V

UNLESS

OTHERWISE

RII
R.
15,000 15,000

INDICATED

016

RESISTORS ARE 1/4Wj 5 %
CAPACITORS ARE MMFD
DIODES ARE 0-664
TRANSISTORS ARE DEC 3639C

C2
100

D15
H

R 21

15,000 R23
15,000

D23

01.

...

D22

*D""

D42

040

C5
100

D'"

M
D,,"

Figure 5-16

R25

1,500

'----

D":'"
V

D60

062

5205 Dual Flip-Flop

A .. IOV(A)

R4
100,000
D3

D37

R2
15,000

RI
R3
12,000 12pJO

,,~,

DEC '3639-C

R20
C2
270

47
10%

R5
1,500

D3~

~5
04

D4.

®"

:!'POO

~OIS

I~k>'

014

"013 ; ~C3
82

Hf--o

019
M

C8
.001
MFD

•

0-662

023

D~2

ISPOD

R.
12,000

R21
C5 47
270 10%
RI4
1,500

040

RI2
12,000 12,000 1'024

0'17

'i.~ 1 'D21

020
~

RIO

DEC 3639-C

~~2S

RII

RI7
:g.$.OO

«J~3

D~2

DID

>---<>F
1'D43

RI3
100,000

\g~o
01

0-662 D-S-S2 ~

d~tJ!f
.01

1~~001 'D30
C6
82

D32

02."

028
028

>--OR

>--<)T

D48

04.

UNLESS OTHERWISE INDICATED"
RESISTORS ARE 114W; 5".
CAPACITORS ARE MMFO
DIODES ARE 0-664
TRANSISTORS ARE DEC 2894-28

5602 Pulse Amplifier

5-14

,
,

g~';;62
034
0-662
g:U2

Ej
1,500

DI8

Figure 5-17

~D41 C7 ;
.01
MFD

RI8
12,000

D 12

'D46 1 047

CoN GND

, D36
0-662

'D42

:h~~ ~031

>---<>J
D45

FD
04

050

B-I!5 V

'3
1000
5%

.
.. "~ .--

~
~o,oOO

011

-----<

,g~

R 23
'7

~D23

DIS

DEC
2894-28

0-662

02
J

"8..6662
Pl

,,,i~o
~
010
'5
l,roO •
5%

R2
ISpOO
.%

:,4

~~~.2
~

...

027

022

R7
3poO•
5%

R"
I5DOD
5%

RI2 •
1,500
5%

RII
~2~OO

RI'
3,ODO
5'Y.

~D2'

10.000

~,p,O
0-66

.-R2li
'7

0-662

>--

012

"B ~
~D3'

, O~
,~

DEC

2894-28

D,j,2

,f<i:o

10,000

A ... IO\l{A)

C,H,N,U
GND

31" ~03.

03'

~~~OD
5%

RI5

RI8

.01

C6
270

RI"
1,500
.%

DEC
2894-28

0":'3

R21
3,000
.%

MFD,

R~6,

"g~:.

MFD ~

----

r D38
0-66

037
0-66

R22
1,500
5%

B-15V

~ DO

~2~O

~2af~OO ~2f."0
E
01

.2CI

'.D~'

D..!

013

lf~OO

DO.

C3
82

020

,..

04.

UNLESS OTHERWISE

021

C.
82

rD.8

INDICATED:

RESISTORS ARE 1/4Wj 10%
CAPACITORS ARE MMFO
010 DES ARE 0 - 664
TRANSISTORS ARE DEC 3639-C

PARTS LIST A-PL-S603-0-0

Figure 5-18

AO
BO
cO
00

EO
FO
HO
JO

01 • •1011.
01.~0 •••
01.~0•••

01. ~Ol ••
013",,~1••

012.1 0 • 8 •
Oil ~D •• 4

010.1 0 •••

-0

LO
MO
NO
PO
"0

SO
TO
uO
VO

5603 Pulse Amplifier

017~0.84

O.~O".

o BlK

o BRN
o RED
o ORN
o YEL
o G".

o BLU
o VIO
o GRY

o WHT
08~ 0804

07~0.8.

0!~01 ••
O'~ 0.8.
0.~018.

O'~O •••

O'~ 0.10

01 ~01.4

o BL_

RIBBON CABLE

o BRN
o flED
o OR.N
o YEL
o GRN

o BLU
o via

Figure 5-19 W018 Connector Board

5-15

R
032

~'7

02.

033

049

..
AA+ r0\1 (A)
AS - r

RI
15,000

R2
100pOO

R5
R'
3,000 15,000

R8
R.
100,000 I,"""

RII

RI3

K.\OOO

~OOO

10",.
02.

rD.

330
01.

021
-662
023
0-662

rP
\!!, Q2

027

~...

BE~
BF~

....

BH~

BJ~
8K~
Bl~
8M

.. 012

8N~
BP~
BR~

BS~
BT~

••

15,000

012
15,000

~ooo

--<
020

0-~2 ...

018
3,000 15,000

01.
021
100,000 ,500

D••
0-662
0.7
0-662

030
0-661:..

AD
032
0-662

g~P

.2.
.7
10%

0;:

R36

QI'

027

031

rD ••

O!.

1,1500

050

D5.
0-862
058
0-662

~~
AE

-0
.....
I

I----

>--

057
0-662

'--

.~
1,500 011

03.

3POO

~OOO

056
0-662

R29

QI~

1,500

.37
3poe
~ 0.0

Des

•• 2
47
10'4

, .~'o
~QIO
A~

...

0 ••

O~.

02.
IOPOO
10%
D4'

D., ~

O~"

«?"

'040
0-662

r--

0;2

0-662

.M
.poe

'---< I---05.

03 •

.oa
O~L.oO.
~

D••

0'7
0-<162
048
0-662

.,.
~

02.

.33
10,000
10%
DOl

C8
3~p

IO~~

D51 ~

0 ••

07
100,000

.28
100poe ~30
,500

0---

1,1500

.2.
.2.
3,000 15poe

~'2

~~
.15

«?'

03
0-662

I~,~~

.20

115,000

028

LP'

.'0
47
10%

CI
.80

~3'

~ D31

It)

; ~~'O
.01
MFO

8U~

BV~

AC.Be

UNLESS

OTHERWISE

TRANSISTORS ARE

RESISTORS

INDICATED:
DEC 3639

ARE 1/4 W, 5%

·CAPACITORS

ARE

DIODES

0-664

ARE

MMFO

t
Figure 5-20

W103 PDP-9 Device Selector

G~O

AI(

10 ADOR 12

All
) 10 ADDR 15

AL
10 ADDa 14

.0 ADINt "

AU
10 AGDR 17

.0 AGOIt II

r-------------~------------~~~----------------~----~~--~~--------------~----+__.----------~----+_
______-.____________~~--_;--~------------------~----~~~----------~----+__.------------------_.----~A~ ~OV
,1t2

ItS

10,000
10 ..

100,000

...

It'S
100.000

~, DI1

100.000

I.0oI

Dil

«(..

I.0oI

De.

It ..
lO0,O0O

.....

...

f.!.1

~t"
.00

.......

~.l [JDII
...

Itl

'.100

It"

It'

It1

1,100

IUD
1.000

It II
T.SOD

....

...4

....

~-,

E ... 1

...1
1'.100

IGOPOO
041

oea .....

I.GOO

a.ooo

100.000

...

1t.1

7'/100

D••

DII

...

IE. . -,-

....

U'·O·
Af'o-----.

?,HO

/yGIe

~'O"
01. .

. ~'DI'

0Ie1

017'

DIOI
~AH

~LEC1

r~IO'

IYNC.

072

.... .F
" .... .,000

RSO

...,r

DIll

rfoa

It.

"01.

4:5
IDO

~ ,DI7'

I.0oI

M ....

D104 ..

017'

~'=~a

......

DeS

.....

oTi

~,:::.

~,g=t

~t-"
100

~GI"

fiW' GI.

~
...

0. .

ItIO

It.4

D•• ' , 047'

"OIl
DMI

l
:, n
DIll

EIIA-r

ItI7

~ 04.
~ ~

". +f1"

1'0.,.,.

lIE

Itl
S.OOO

1GO.ooo

D,!

ID~'

~, DolO

R.a

~D~..

IHg~a

R..
100,000

Dill DH.

DHlDH.

cut.

~'DI7

It ••

It4 ..

It. .

....

Itl.

1.100

SpOD

.... . ..

10.000
10..

-SV

. .2

a,ooo

T.100

... 1
7',500

It.5
',.00
AI

"D.

....

ICM)POO

114.
100.000

It41

It 17'

It••

IOOPOO

.oopoo

100.000

~.~

~".:,,;
":::'
~,D"

,....

DI ••

034
UNLESS OTHEIt.1SI IIIIDICATED:
0100£1 AltE OM4

TRANSIITORS A..IE HU.S.I
.1I1IT0..1 Aft 11,000
ItEIIITO.I AitE 114. . . . .

E"OUT

...

7.100

It..

7.100

It ..

1.000

IE... III):I

....

0114 ..

It ...

'.100

It'l

1.100

DM
It_

••aoo

.....

7.500

071

F
1t4T

lfDes
It aD

1.000

III

1,000

.5. ... ..

Figure 5-21

W104 PDP-9 I/O Bus Module
5-17

-laV

R6
470,000

'g~84

'g~~4

100
C5
... .... .... ~ MMFO

.... ... ...

016 017 018

RI4
470.000

{EJ

R22
470,000

'g~i4
028027 028

...

MMFO

08
DEC
3639B

)m9B

MFO

-, -~
\J::::,)

C7
100

...

R8
4,700

R9
1,500

RII
68,000

RI6
4,700

012
DEC
36398
CI

"038
C2

RI9
68,000

R24
4,700

-i" .01

"037

'~1~

*P31
0684
RI7
1,500

C,V

"031

MMFD

021
0684
1*1

+IOV

GNO

C9
100

011
*1OB84
R3
68,000

C3
.01

R25
1,500

MFO

'036
R28
1,500
B

-15V
L

02 03 04

....... ... ...

«J

C4
100

..... ~

012 013 014

""'""... ...

MMFD

02
DEC
3639B

.....

,*P9
0664
RI
68,000

RIO
470,000

"g~4

470,000

"g~64

C6
100

.. ..... \t::

022 023 024

MMFO

...

OS
DEC
3639B

.....

R5
1,500

R7
68,000

RI2
4,700

,.....

R26
470,000

'm4

'E6~1

...

032033 034

100

MMFO

,.....

1"'1

....
.....

010
DEC
3639B

RI5
68,000

R20
4,700

014
DEC
3639B

i*,029
0664
RI3
1,500

CIO
100
MMFD

......

l*pl9

0684

R4
4,700

RI8
470,000

,g:g4

035
*10664
R21
1,500

R23
68,000

R27
4,700

R29
1,500

UNLESS OTHERWISE INDICATED:
RESISTORS AR E 114 w; 5 'II.
DIODES ARE 0662
TRANSISTORS ARE DEC'3639C

Figure 5-22 W107 High Impedance Follower

r---_1~----~------------_,~--~----~~------------t_--_1~----~--------------------t_--------~A+IOv

025
0-662
02'
0-66Z
023
0-662

.,
c aND
022

D-862

021

0-662

020

0-662

011
0-662

R2
4,700

R4
15,000

R6
4,100

10%

RI
4,700
10%

RIO
15POO

RIZ
4,700
10%

.,.

4,700
10'11.

-3V

'-- .!!."~~J
RI6

RII

R21

I!!,OOO

••700

I,SOO

10%
8-15V

UNLESS OTHERWISE INDICATED:
RESISTORS ARE 1/4W; 15%
DIODES ARE 0-664
TRANSISTORS ARE DEC 3009B

Figure 5-23

W520 Comparator

5-19

..
C4

GND
AC

0662

g~62l

g~62

D5
0662

AF~

R2
270
10%
2W

>--jl

DI6

DIO

>----()

D2~

010

AC
GNO

0662
D3

AL~

D22...w.

AM~

~D13

",.D12

0662

011

YEL

WHT

02Qw.

WHT

--0 BE

().

--0 BF

...w D33

VIO

WHT

0--

ORN

B/W

VIO

RED

GRN

O/W

VIO

RED

<>-

BRN

G/W

<>-

VIO

RED

-0

SLATE

B/W

-<>

S/W

0.-

AT~

WHT

RED

O/W

B/W

l'l.-

WHT

BLK

(').

,...-

-"'" D34

,.. 032

...w.D3I

DO~

D4~

041

-<JBH

...w.D3O

03.

J.oO.D2.

D3S

-<J BJ

OBK

D4a----o SL

-0 BM

D37

...w.D27

D36

"1 3

0662 I C6

I
I
I

051
0662 I
050 I

1
•
I
16

Do'

--n0

06621
;

13~g::2IC5

-<JBN

='~BP

,046

, -{) BR

06621

RO ~
270
10%
( 2W
BB,-ISV

L.-

- 3V STRAiE
Be", r 2
....,
GND

Ir 045 1 ;

06621

R3-.=1"

(

-<.> BT

047
0662 1

0662 1

I
1

-u os
-W D2 •

I
I
I

052

-oBD

S/W

DIBw.

YEL

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L.oI D.

D4~

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...w.

035

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~ B/W

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I 2
I

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-<J BC

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SLATE

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AB,-15V

D2!..w.

AS
RI
270
10%
2W

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~D17

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- ~.V STRATE

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GND
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1\

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07
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017

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026

!::!.
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05
0662

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ORN

AE
AF

DIS

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SLATE

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270
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AB ,-[5V

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044

D34

043

D33

042

...... 32

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12
1

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BC

I
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3
1

I
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BF
B"

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052
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051

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050 I
0662 I _
049 I ..

,=D~':J
R4
270
10%

BB,-15V

-3 V STRATE

0662
03

0662
02

0662
UNLESS OTHERWISE INDICATED:
DIODES ARE 0664
CAPACITORS ARE .01 MFO

01
el

0662

AC
GND

AL
AM
AN

013

022

!::!.

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02.

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BS

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Figure 5-24

[2- - - ,

SLATE

W850 I/O Cable Connectors

. ",.D27

036 ....

Be
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D4B
D662,c?

gi~2il

046 I
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045 I :::

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5.4

POWER SUPPLY 779
Power Supply 779 is a dual power supply unit designed for installation on a plenum door.

One of the supplies fllrnished +10V and -15V suitable for logic power; the other is a lightly filtered t
center-tapped 30V floating supply suitable for furnishing power to solenoids, etc. The -5V outputs of
the power supply are connected in parallel to supply logic power to both the TC02 and TU55 transports.
The schematic diagram of this power supply is shown in Figure 5-25 I.and the electrical characteristics
are listed in DEC System Module Handbook, C-100.
Input voltages:

115 Vac, 60 cps (10SV to 12SV)

Output vol tages:

+10Vi -15Vi center-tapped 30V(+1SV-15V)

Maximum output current:

8A {limited by curve)

Line load regulation:
(under all line and load
condi tions)

+lOV regulated to 9-11Vi all +1SV supplies
regulated tQ 14 -16V

Ripple:

1V at +10Vi 500 mV at -15Vi 2.SV at 30V

Size frequency regulation:

±3%

Maximum voltage between
output and chassis:

300V

r - - -OMI
-----,

DEC

1016

I
I

BROWN

1~14qo_--~~ IE~~~~~~--_+~!------~-------===~--~------~~--O
I
I

I NPlH
IISV AC

60'"
2

L ______ ...l
OMI
r------l

REO-WHT
TWISTED

BROWN I

IL _ _ _ _ _ _ _ J
UNLESS OTHERWISE INDICATED
It HEYMAN MFG CO TABTERMINAL IN PLASTIC BUSHING

c=J CINCH JONES TERMINAL STRI~
Figure'15-25 Power Supply Type 779, Schematic Diagram

5-21

5.4.1

Mechanical Characteristics
Pertinent mechanical characteristics of Power Supply 779 are as follows.

5.4.2

Panel width:

16-5/8 in.

Finish:

Chromate conversion, coating

Power input plug:

Jones No. 141 strip

Power output plug:

Heyman tab terminals

Power Supply Checks
The use of a multimeter permits output voltage measurements to be made on the Type 779

power supply without disconnecting the power supply. An oscilloscope should be used to measure the
peak-to-peak ripple content of each dc output voltage. Because the power supply is not adjustable, a
unit that does not meet the following tolerances should be considered defective and steps should be
taken to correct the deficiency!
Nominal
Voltage
Outputs
(vol ts)

Output
Voltage
Range
(vol ts)

+10

9-11

-15

14-16

Maximum Peak-to-Peak
Output Ripple Voltage
(vol ts)

0.5

± 15 (for center tapped 30V circuit)

5.4.3

Marginal Checks
Marginal checks are performed to aggravate borderline circuit conditions within the control

logic and thus produce observable faults.

By recording the bias voltage levels at which circuits fail,

progressive deterioration can be plotted and expected failure dates can be predicted. This procedure
provides a means for planned replacement. Marginal checks are also useful as a troubleshooting aid to
locate marginal or intermittent components (e. g., deteriorating transistors).
Marginal checks are performed by operating the logic circuits from an adjustable external
power supply located in the PDP-9 or DEC Type 734B Dual Variable Power Supply. Raising the bias
level above +10V increases the transistor cutoff required to be overcome by the preceding transistor,
thus causing a below-par transistor to fail.

Lowering the bias level below +lOV reduces the transistor

base bias and noise rejection. This procedure provides detection of high-leakage transistors and simulates high-temperature conditions for checking thermal runaway. Raising and lowering the -15V supply
has little effect on the logic circuits because the collector load voltage of most modules is clamped at
-3V. It does, however, increase and decrease the output pulse amplitude of the pulse amplifier circuits
(e.g., the delay circuits) and then provides a sensitivity check of the circuits which follow.
CAUTION
Increasing the -15V power to a val ue more negative than
-18V wi" cause damage within the logic circuits.

5-22

The panel for conducting marginal checks of the Type TC02 DECtape Control is located at the
left-hand side of the wired panel assembly. When switched on (up), switches 1A through 1F apply power
from the marginal check bus; when switched off (down), normal power is applied. The "Up" position of
the top switch on each panel selects the marginal check voltage of+10V. The "down" position selects
the fixed voltage of +1 OV. The lower switch of each panel performs the same function with the -15V.
A color-coded connector on the right side of each panel connects the normal and marginal
operating voltages to the marginal check panel. The normal and marginal power buses are common to all
panels. The normal power bus is connected to the Type 779 Power Supply, the marginal power bus to the
marginal check power supply on the PDP-9.
A marginal check if performed as follows.
a.

Set selector switch on marginal-check power supply to +10 mc and adjust the power sup-

ply output for +1 OV.
b.

Set the top normal/marginal check switch on the panel to be tested to its "up" position.

Start DECtape operation in a normal program or in a routine which fully utilizes the cir-

cuits in the rack to be tested. If no suitable program is avai lable in the normal system application, se1ect an appropriate maintenance routine. The maintenance programs provide basic exercises of specific
functions and scope loops for these functions as well as a routine which redundantly exercises all
functions.
d.

Decrease the marginal -check power supply output vol tage unti I normal system operation

is interrupted. Record the marginal-check vol tage. If desired, locate and replace the marginal transistors at this time.
e.

Restart DECtape operation and increase the marginal-check power supply output voltage

until normal operation is interrupted.

Record the marginal-check voltage. If desired, locate and re-

place the marginal transistors at this time.

Set the top normal/marginal check switch in step c to its "down" position.

g.
h.

Repeat steps a through f for the center normal/marginal switch on the panel being tested.
Set selector switch on the marginal-check power supply to -15mc and adjust the power

supply output for -15V.
i.

Repeat step c.

Set the bottom normal/marginal switch on the panel being tested to its "up" position.

Repeat steps d and e and then return the bottom norma I/marginal swi tch to its "down"

Adjust the output of the marginal-check power supply to OV and set the selector switch

position.
to its "off" position.
5.5

POWER CONTROL PANEL (Type 832F)
The Power Control Panel is mounted on the plenum door at the rear of the cabinet and is used

in conjunction with Type 779 Power Supply. The schematic diagram of the panel is shown on
Figure 5-26 •

5-23

",,4 BlK

~--------------------------------------~~~----------------------------,-~-oGND

fit 10 RED

}

~+--+-+----tr'''-------+---~--+---_ _-~~
~....----.,.--

oI'lOWHT

UTE. RNAl{-----EXTERNAl
JU'~~RS
JUMPER
REMOTE
FOR
OPE~ATlON
SLOW ON

FAST ON

NOTES·
01.02,03.04 THYRECTOR G.E. 20SP484, J 15V
CI CAPACITOR 2 X.I MFD IPOO VDC
"YAT 10011-1
CORN ELL DUBLIER.
C2 II C 3 CAPACITOR BATHTUB- DEC PURCH. SPEC.". CAF- 0001
2 X.I MFD 600 vac CORNELL DUBLIER.
SI TOGGLE SWITCH DPOT 7583K& 3POS CENTER OFF
52 TOGGLE SWITCH DPST 7590K9
KI RELAY *'O~-8-687 NORMAllY OPEN 115VAC COil 3-5 SEC DELAY
QUICk OPERATE. SLOW RELEASE.
K2 RELAY ""'040-8-58 NORMALLY OPEN 115 VAG COIL 3-5 SEC DELAY
SLOW OPERATE,QUICK RELEASE.
K 3 RELAy .... EM-I 115 VAt EBERT ELECTRONI Cs.
CB I CIRCUIT BREAKER
190-230-101 30 AMPS. 250V, 60 eye-CURVE 4
TM HOBBS TIME METER TYPE MII906 120V 60 eYe-CURVE 4

Figure 5-26
5.6

Power Control Panel Type 832F

PREVENTIVE MAINTENANCE
Preventive maintenance consists of procedures performed prior to the initial operation of the

equipment and periodically during its operating life. These procedures include visual inspections,
cleaning, mechanical checks, and circuit element checks. Marginal checks are also conducted when
considered necessary to aggravate border-line conditions or intermittent failures so that they can be
detected and corrected. A log book should be available for recording specific data which indicates
the rate of performance deteriation and provides information for determining when components should be
replaced.
Except for marginal checks all preventive maintenance procedures should be performed once
a month or every 200 operating hours, whichever occurs first.
NOTE
The heads on each TU55 should be cleaned dai Iy using
the head cleaner listed in Table 5-1.
5.6.1

Mechanical Checks
The following mechanical checks should reveal any substandard conditions in the mechanical

operation of the control unit.
a.

Clean the exterior and the interior of the control by means of a vacuum cleaner or by

using clean cloths moistened in a nonflammable solvent.

Clean the air filter at the bottom of each cabinet. Remove the filter by removing the

fan and housing which are held in place by two knurled and slotted screws. Wash the filter in soapy
5-24

water, dry in an oven or by spraying with compressed gas, and spray with Filter-kote (Research
Products Corp., 1015 E. Washington Ave., Wisconsin, 53703).
c.

Clean all rotary switches with a spray cleaner such as Contactene.

Lubricate door hinges and casters with a light machine oil. Wipe off excess oil.

Visually inspect the TC02 for completeness and general condition.

Inspect all wiring and cables for cuts, breaks, fraying, deterioration, kinks, strain, and

mechanical security.
g.

Repair or replace any defective wiring.

Inspect switches, controls, knobs, jacks, connectors, transformers, fans, capacitors,

lamp assemblies, etc. Tighten or replace as required.
h.

Inspect switches for binding, scraping, misalignment, and positive action. Adjust,

align, or replace as necessary.
i.

Inspect all racks of logic to assure that each module is securely seated in its connector.

Inspect power supply capacitors for leaks, bulges, or discoloration.

citors exhibiting these signs of malfunction.

5-25

Replace any capa-

CHAPTER 6
ENGINEERING DRAWINGS

This chapter contains the logic block diagrams and module location diagrams of the TC02
DECtape Control. The equivalent drawings for the TU55 DECtape transport are contained within the
TU55 Instruction Manual.
6.1

SYMBOLS AND DESIGNATIONS
The block and signal symbols used on the logic diagrams are defined in the Digital Logic

Handbook, C-105 together with a description of standard DEC logic levels. The signal designations
assigned are defined in Table 3-2 of this manual.
6.2

DRAWING LIST
Table 6-1 lists the pertinent engineering drawings referenced in this manual. These drawings

relate to the discussions in this manual and do not necessarily reflect the latest revisions incorporated in
the equipment. When discrepancies exist between the drawings contained in this manual and the drawings shipped with the device, the latter should be assumed to be the correct drawing set.
Table 6-1
Engineering Drawing List
Title

Revision

Page

D-TC02-0-1

R/W AMPS, SP GEN, TEST CONN

6-3

D-TC02-0-2

LPB and RWB Registers

D-TC02-0-3

6-7

D-TC02-0-4

I/o Bus Gating
I/o Bus, lOTs

6-9

D-TC02-0-5

Errors, MCP Switch

6-11

D-TC02-0-6

Control

6-13

D-TC02-0-7

Status A, Command Bus

6-15

D-TC02-0-8

WINDOW, MK TRK, STATE

6-17

D-TC02-0-9

MCP and Cables

D-TC02-0-1 0

TP GEN

6-21

D-TC02-0- 11

DTB Register

6-23

D- TC02-0-13 (Sheet 1)

Module List Panels A-F

6-25

D-TC02-0-13 (Sheet 2)

Module List Panels A-F

6-27

D-TC02-0-15 (Sheet 1)

Timing

6-29

D- TC02-0-15 (Sheet 2)

Timing

6-31

Number

6-5

6-19

6-1

Table 6-1 {cont}
Engineering Drawing List
Title

Number

Revision

Page

0-TC02-0-15 {Sheet 3}

Timing

6-33

0-TC02-0-15 {Sheet 4}

Timing

6-35

0-TC02-0-16

OCH, API

6-37

0-TC02-0-17

Test Connectors

6-39

0-7007236-0-0

TC02 Bussed Wiring Assembly

6-41

6-2

1"Gsez I C2!
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6-5

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D-BS-TC02-0-6
6-13

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D-BS-TC02-0-7

STATUS A, Command Bus
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O-BS-TC02-0-7

STATUS A, Command Bus
6-15

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DEC fORM NO.
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MCP and Cables

6-19

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A
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52.115 15ZJ5

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15l.J15

27 28 29

30 31

32 33 34 35

40 41

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ENABLE

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20 21

24 25

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27 28
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35 36 37 38

43 44

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32 33 34

11521

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29 30 31
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6-25

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I/O BUS 16 tt)
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'I/O B.US 17 (t)
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¢-5 -----~..

D£C fORM NO.
DftO 102

O-BS-TC02-0-11

6-23

OTB Register

7
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all

MARK {

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0
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0

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TO P.

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O-CL-TC02-0-17

Test Connectors for TC02

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33 34

40 41

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111.12
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29 30 31

32 33 34

35 36 37 38

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D-MU-TC02-0-13 Module list Panels A-F
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6-27

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0- TO-TC02-0-15
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6-29

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(Sheet 3)

6-33

Timing

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#" 12-3594-03'2.

=_110.. 8

D-AD-7005236-0-0 TC02 Bussed Wiring Assembly

6-41

momoomo

DIGITAL EQUIPMENT CORPORATION. MAYNARD. MASSACHUSETTS
Printed in U.S.A.