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DEC-09-I1BA-D
February 1969
46 pages
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KX09A
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DEC-09-I1BA-D
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46
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http://bitsavers.org/pdf/dec/pdp9/DEC-09-I1BA-D_KX09A_Feb69.pdf
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INSTRUCTION MANUAL KXOSA MEMORY PROTECTION OPTION P-9 DIGITAL EQUIPMENT CORPORATION. MAYNARD, MASSACHUSETTS DEC-09-Il BA-D KXOBA MEMORY PROTECTION OPTION DIGITAL EQUIPMENT CORPORATION. MAYNARD, MASSACHUSETTS 1st Printing September 1968 2nd Pr i nt i ng February 1969 Copyright © J968 by Digital Equipment Corporation 1969 Instruction times, operating speeds and the like are included in this manual for reference only; they are not to be taken as specifications. The following are registered trademarks of Digital Equipment Corporation, Maynard, Massachusetts: PDP FOCAL COMPUTER LAB DEC FLIP CHIP DIGITAL ii CONTENTS Page CHAPTER 1 INTRODUCTION 1• 1 . Related Documentation 1-1 1.2 System Description 1-2 CHAPTER 2 INSTALLATION 2. 1 Interconnections 2-1 2.2 Power Requirements 2-1 2.3 Environment 2-1 2.4 On-Site Checkout 2-1 CHAPTER 3 OPERATION AND PROGRAMMING 3. 1 3.1.1 3.2 3.2. 1 3-1 Operation KX09A Indicators 3-1 Programming 3-2 Stored Data Word Format 3-2 CHAPTER 4 THEORY OF OPERATION 4. 1 Block Diagram Discussion 4-1 4.2 Device Selection 4-3 4.3 Instruction Descriptions 4-3 4.3. 1 Skip on Nonexistent Memory Flag (MPSNE): 701741 4.3.2 Skip on Violation Flag (MPSK): 701701 4.3.3 Enter User Mode (MPEU): 701742 4.3.4 Clear Violation Flag (MPCV): 701702 4.3.5 Clear Nonexistent Memory Flag (MPCNE): 701744 4.3.6 Load the Boundary Register (MPLD): 701704 4.4 4.4. 1 Detai led Descriptions 8 4-3 4-4 8 4-4 8 4-4 8 8 8 4-4 4-5 4-5 Comparator Circuit 4-5 4.4.2 User Mode Enable Circuit 4-6 4.4.3 Mon itor Ci rcuit 4-6 4.4.4 Trap Circuit 4-7 iii CONTENTS (Cont) Page CHAPTER 5 MAINTENANCE 5. 1 Diagnostic Program 5-1 5.2 Recommended Spares 5-1 CHAPTER 6 ENGINEERING DRAWINGS ILLUSTRATIONS 1-1 Memory Protection System 1-2 3-1 KX09A Indicator Panel 3-1 3-2 Stored Data Word Format 3-2 4-1 Block Diagram 4-2 TABLES 1-1 Reference Documents 1-1 3-1 KX09A Indicators 3-1 3-2 KX09A lOT Instructions 3-2 5-1 KX09A Modules 5-1 iv CHAPTER 1 INTRODUCTION The KX09A Memory Protection Option is a PDP-9 computer option manufactured by Digital Equi pment Corporation. It is used to trap certain i nstructi ons, references to protected areas of the core memory and references to nonexistent memory banks. This document and the referenced documents provide information necessary for installation, operation and maintenance of the KX09A Memory Protection Option. The level of discussion assumes that ,the reader is familiar with the core memory system of the PDP-9 centra I processor. 1 .1 RELATED DOCUMENTATION The documents listed in Table 1-1 contain material which supplements information in this document. Table 1-1 Reference Documents Title Document Number Digital Logic Handbook C-105 Specifications and descriptions of most FLIP CHIP * modules, plus simplified explanation of the selection and use of these modules in numerous applications. PDP-9 User Handbook F-95 Operation and programming information for the PDP-9. PDP-9 Maintenance Manual Volumes I and II F-97 Operation and maintenance information for the PDP-9, including engineering drawings. DM09A Instruction Manual DEC-09-19AB-D Operation and maintenance information for the PDP-9 DMA Multiplexer option. KX09A Memory Protect Test MAINDEC-9AD 1EB-D Operating instructions and program listing for the KX09A diagnosti c program. Contents *FLIP CHIP is a trademark of Di gi tal Equi pment Corporation 1-1 1 .2 SYSTEM DESCRIPTION The KX09A Memory Protection Option is connected to the PDP-9 central processor and control memory system (Figure 1-1). It establishes a foreground/background environment for PDP-9 time-sharing processing activity by specifying the boundary between the protected (lower) and unprotected (upper) regions of core memory. Memory locations are assigned to the protected region in increments of 2000 a locations and the protected region is variable by a programmed instruction. All instructions are monitored before they are executed. The logic within this equipment traps instructions that reference locations below the boundary or instructions that are in the illegal category. This trapping causes the execution of an effective JMS instruction after the machine cyc Ie in which the attempted violation occurred. The address referenced by the effective JMS instruction will be location absolute 20 if the program interrupt facility is disabled, or location absolute 0 if the program interrupt faci lity is enabled. If a nonexistent memory bank is referenced by an instruction I a trap occurs to prevent a hang-up condition in the central processor. PDP-9 CENTRAL PROCESSOR (KC09Al ~ PDP-9 CONTROL MEMORY SYSTEM (MC70Bl r-----o Figure 1-1 KX09A MEMORY PROTECTION OPTION (PART OF ME09Bl Memory Protection System 1-2 CHAPTER 2 INSTALLATION The KX09A Memory Protection Option consists of 47 FLIP CHIP modules of the B-, R-, Sand W-series mounted in two Type 1943D module mounting panels. Wiring for the KG09A, MP09A and MP09B options is also installed on the two module mounting panels. The complete assembly, Type ME09B, is mounted in two spaces immediately above the paper tape reader/punch unit in the PDP-9 central processor cabinet. There are no special installation requirements other than those required for the PDP-9 central processor if the equipment is installed in the plant. If a field installation is performed, insert the modu Ie complement per drawing D-MU-KX09-A-l. Remove jumpers and install external components using drawing A-CP-ME09-B-3 as a reference. 2.1 INTERCONNECTIONS Standard PDP-9 I/O bus cables and three flexiprint cables connect the KX09A to the PDP-9 central processor, and three flexiprint cables complete the connections to the control memory system. The I/O bus cables are shown on drawing D-IC-KX09-A-4 and the six flexiprint cables are shown on drawi ng D-IC-KX09-A-5, sheet 1. Drawi ng D-IC-KX09-A-5, sheet 2, shows a schemati c vi ew of the installed cables and identifies the cable lengths and the terminating module types. 2.2 POWER REQUIREMENTS The KX09A draws the necessary dc power from the PDP-9 centra I processor power buses. It requires 10V at O.2A and -15V at 3.2A. 2.3 ENVIRONMENT The environmental specifications for the KX09A are identical to the PDP-9 central processor envi ronmenta I speci fi cati ons • 2.4 ON-SITE CHECKOUT Check wiring for shorts and correct any shorts that are found. Check that the jumpers for the KX09A are removed from W18-D25 and that all unused pins on W18-D25 are jumpered per drawing A-CP-ME09-B-3. Check that the external components are installed. Check a" cables using drawing D-KX09-A-5 (sheet 2) as a reference. Check that the jumper between H35C and H35F (USER MODE (1)B to ground) in the PDP-9 central processor is removed. 2-1 Turn on power and run a few small programs to check the operation of the boundary register and the PRTCT switch. A sample program is shown below: LAS LBR JMP.-2 The boundary register should follow the state of the appropriate bits in the data switches. If the results are incorrect, check the 10TIs and the logic for missing signals, etc. Run a JMP. program. Press the START key with the PRTCT switch in the UP position and ob- serve that both the USMD indicator and the indicator above the PRTCT switch illuminate. Check that the PRTCT switch has no further effect once the program is running. Check that the 10 RESET key clears the boundary register and the USMD lights. Run the diagnostic program MAINDEC-9A-D1EB-D and run margins on racks A, B, C, and D of the ME09B using margins of 10 ± 4V and -15 ± 3V. 2-2 CHAPTER 3 OPERATION AND PROGRAMMING 3.1 OPERATION The user mode (memory protect) of the KX09A is enabled by either a MPEU instruction I or by placing the PRTCT switch on the PDP-9 operator console in the UP position and pressing the START key. Once the program has started I the KX09A is in user mode and the PRTCT switch has no further effect. The indicator above the PRTCT switch lights when the user mode is enabled. 3.1 .1 KX09A Indi cators The indicators shown in Figure 3-1 are mounted above the PDP-9 marginal check panel. Indicator functions are listed in Table 3-1. 00000000 PRVN NEXM USMD Figure 3-1 BR3 BR4 BR5 BR6 BR7 KX09A Indicator Panel Table 3-1 KX09A Indi cators Name Function PRVN Li ghts when protect vi 0 lati on flag is ra i sed. NEXM Lights when nonexistent memory flag is raised. USMD Lights to indicate that the user mode is enabled. BR3 through BR7 Indicate the upper limit (in 2000 increments) of the protected 8 regi on of core memory. 3-1 3.2 PROGRAMMING The KX09A memory protection option adds the lOT instructions listed in Table 3-2. Table 3-2 KX09A lOT Instructions Mnemonic Octal Code MPSNE 701741 Skip on nonexistent memory flag. The nonexistent memory flag is set whenever the processor attempts to reference a nonexi stent area of core. For a 32K machine, the flag would never get set. MPSK 701701 Skip on violation flag. The memory protect violation flag wi II be set whenever the execution of an instruction has violated the provision of memory protection. MPEU 701742 Enter user (protect) mode. Memory protect mode wi II be entered at the end of the next i nstructi on that is not an lOT. MPCV 701702 Clear violation flag. MPCNE 701744 Clear nonexistent memory flag. MPLD 701704 Load the memory protection boundary register with the contents of AC3 through 7. The boundary register wi II store the number of 2000 word blocks to be pro8 tected. 3.2.1 Function Stored Data Word Format Figure 3-2 shows the data format of the word deposited in location 20 or 0 when a violation is trapped. o 1 2 17 345 IIIIIII Uk '-v--"', I _v- L PROGRAM COUNTER EXTENDED PROGRAM COUNTER - - - - - STATE OF KX09A (1 WHEN IN USER MODEl - - - - - - STATE OF EXTEND MODE (1 WHEN IN EXTEND MODE STATE OF LINK L - -_ _ _ _ _ _ _ _ _ _ _ _ Figure 3-2 Stored Data Word Format 3-2 CHAPTER 4 THEORY OF OPERATION 4.1 BLOCK DIAGRAM DISCUSSION The KX09A Memory Protection Option (Figure 4-1) establishes a foreground/background environment for PDP-9 time-sharing processing activity by specifying the boundary between protected (lower) and unprotected (upper) regions of the core memory. Memory locations are a Ilocated to the protected region in word blocks of 2000 locations. A number that represents the upper limit of the 8 protected region is transferred from the PDP-9 AC register and to the boundary register via the 10 BUS 03 through 07 lines. This number is jammed into the boundary register by an MPLD instruction. The KX09A can be placed in the user (protect) mode by an MPEU instruction or by placing the PRTCT switch in the UP position and pressing the START key on the PDP-9 operator console. With the user mode enabled, the KX09A monitors the instruction to be performed for illegal instructions (instructions that should not be used by time-sharing users; e.g., lOT, OAS, HLT, a chain of XCT), references to memory locations within the protected region, and reference to nonexistent memory banks. If one of these conditions is detected, control is transferred to a monitor program before the instruction is exec uted • These functions are performed in the following manner. A comparator circuit compares the number stored in the boundary register with bits 3 through 7 of the instruction address. The KMA < BR signal is generated and the monitor circuit is enabled if the number in bits 3 through 7 is less than the number in the boundary register. ,The operation code of the instruction is decoded in the monitor circuit and the monitor circuit is enabled if the instruction is in the illegal category. To check for references to nonexistent memory banks, the MEM START pulse sets the MEM OK flip-flops and the MEM STROBE pulse clears the flip-flop. If a nonexistent memory bank is referenced, the MEM STROBE pulse is not generated and the MEM OK flip-flop remains set. Then, the next CLKD pulse sets the NON-EX MEM flip-flop. Outputs from the MEM OK and NON-EX MEM flip-flops are ANDed enabling the monitor circ uit • When the monitor circuit is enabled, the 1 ->- FOUND 1 signa I is sent to the trap circuit causing the 13 -. CMA and FOUND 1 SAVE (B) signa Is to be generated. The FOUND 1 SAVE (B) signa I from the trap circuit is sent to the central processor and causes the execution of an effective JMS instruction after the machine cycle that attempts to violate. The address referenced by the effective JMS instruction is location absolute 20, if the PI faci lity is disabled, or location absolute 0, if the PI faci lity is enabled. The 13 ->- CMA signa I sets the PROTECT VIOLA nON flip-flop, disables the user mode enable circuit, and sets the CMA register to 33. 4-1 The state of the KX09A (a 1 for the user mode) is stored in bit 2 of the storage word by those operations that save the state of the machine (CAL, JMS, PI). The stored program count (PC) wi II contai n one more than the location of the vi olati ng i nstructi on, except for JMP to a protected area. In thi s case, the stored PC wi II contai n the protected address • . - - - - - - - - - - - - . SKIP RQ SD0 IOPI-3 DS0-5 ~---.L...-------+-------__a__. ""START FOUND 1 SAVE (8) OPERATION CODES OF INSTRUCTION USER MODE (0 8 BITS 3-7 OF ADDRESS 1/0 BUS 110 BUS L..-_ _ 0_3_ _ 0_7_ _ _ _ _ _ _ _ _ "_" _______ """ _ _ _ _ _ _ _ _ _(_MP_E_U_)_ .... DEBREAK AND RESTORE (lOT 70 3344) (UP) -15V ~ .., (DOWN) PRTCT PDP-9 CONSOLE Figure 4-1 Block Diagram If the user mode is enabled when an API break starts and the API channel address contains a H LT, OAS, or lOT instruction rather than the normal JMS instruction, the instruction is inhibited, the user mode is disabled and no violation is detected. A debreak and restore (DBR) instruction (703344 ) is performed to return the KX09A to the user mode. 8 4-2 A CAL instruction disables the user mode and never causes a violation. If the user mode is disabled when reference to a nonexistent memory bank is made, the NONEX MEM flip-flop is set but no trap occurs. Since the MEM STROBE pulse is not generated, the program will hang-up. To prevent this, the output from the MEM OK flip-flop is inverted and sent to the PDP-9 as a RESTART signa I (drawing KC-16). The input to B104-F31 T is conditioned and the next CM ClK pulse enab les the strobe logi c. The program conti nues after a 1 ~s pause. There are six lOT instructions added for the KX09A. The functions of the MPlD and MPEU instructions have been briefly explained in this discussion. Refer to Section 4.3 for complete details on a" KX09A lOT instructions. 4.2 DEVICE SELECTION Signals on the device selection lines (DSO through DS5) and one subdevice select line (SDO) of the PDP-9 I/O bus are used to select the KX09A Memory Protection Option and generate the required control signals. A description of device selection using drawing D-BS-KX09-A-2 (sheet 1) as a reference follows. Device select lines DSO and DS1 are inverted generating buffered signals. These signals and the signa Is on DS2 through DS5 are sent to a Wl 03 module that has been coded for a 178 code. The signal on the SDO line is inverted generating complementary SDO signals. When an KX09A lOT instruction is placed on the I/O bus, the 178 code is decoded by the W103 module and enables the lOP pulse. The resultant lOT pulse is ANDed with the appropriate SDO signal to generate the control signal. 4.3 INSTRUCTION DESCRIPTIONS There are six lOT instructions which initiate action in the KX09A Memory Protection Option. The functions performed by these lOT instructions are described below using drawing D-BS-KX09-A-2 (sheets 1 and 2) as a reference. 4.3.1 Skip on Nonexistent Memory Flag (MPSNE): 701741 8 This instruction checks the condition of the NON-EX MEM flip-flop. A -3V level is applied to R111-A27E if a nonexistent memory bank has been referenced. The signal on the SDO line (-3V during this instruction) is inverted twice and applied to R111-C28E. The signals on the device selection lines and the IOP1 line are decoded by the W1 03 decoder module and the resultant pulse is applied to R111-C28D. The AND gate is enabled and its output signal is applied to W640-C29D generating the MPSNE pulse. The MPSNE pulse is applied to R111-A27D generating a skip request (SKIP RQ) that is sent to the PDP-9 via the I/O bus. 4-3 4.3.2 Skip on Violation Flag (MPSK): 701701 8 The condition of the PROTECT VIOLATION flag flip-flop is checked with this instruction. A -3V level is applied to R111-A28E if a violation is detected (i .e., a reference to locations below the boundary, an illegal instruction, etc.) and the PROTECT VIOLATION flip-flop is set. The signal on the SDO line (OV during this instruction) is inverted and applied to Rl11-D28E. Signals on the device select lines and the 10Pl pulse are decoded by the W103 module and the resultant pulse is applied to Rll1-D28D. The AND gate is enabled and its output pulse is applied to W640-C29K generating the MPSK pulse which is applied to Rl11-A28D generating a SKIP RQ. 4.3.3 Enter User Mode (MPEU): 701742 8 This instruction is performed to place the KX09A in the protect (user) mode. The signal on the SDO line (-3V during this instruction) is inverted and applied to S202-C32V conditioning the DCD gate at the set side of the PRE-USER MODE flip-flop. The signals on the device select lines and the IOP2 pulse are decoded by the W1 03 module generating the lOT 1702 pulse. The lOT 1702 pulse is applied to S202-C32U setting the PRE-USER MODE flip-flop and applying -3V to Rl11-D32E. During this instruction and all lOT instructions, the lOT flip-flop in the PDP-9 (drawing KC12) is set. Therefore, OV is applied to R111-D32D, disabling the DCD gate at the set side of the USER MODE flip-flop. The DCD gate remains disabled unti I an instruction other than an lOT instruction is performed. Then, the lOT flip-flop is cleared, R111-D32D goes to -3V, the DCD gate is enabled and the USER MODE flip-flop is set by the DONE (1) pulse at the end of the instruction. A OV level from the USER MODE flip-flop is inverted generating the USER MODE (l)B signa I that is sent to the centra I processor as UM (1) via the memory extensi on/parity interface (drawi ng KC-28) • 4.3.4 Clear Violation Flag (MPCV): 701702 8 The PROTECT VIOLATION flip-flop (violation flag) is cleared by this instruction. The signal on the SDO line (OV during this instruction) is inverted twice and the resulting signal is applied to S202-B29L conditioning the DCD gate at the clear side of the flip-flop. Signal lOT 1702 is generated by the W103 decoder module and applied to S202-B29K clearing the flip-flop. 4.3.5 Clear Nonexistent Memory Flag (MPCNE): This instruction is performed to clear the NON-EX MEM (nonexistent memory flag) flip-flop. The signal on the SDO line (-3V during this instruction) is inverted and applied to the DCD gate at the 4-4 clear side of the NON-EX MEM flip-flop. The W103 decoder module generates the lOT 1704 pulse that is also applied to the DCD gate. The DCD gate is enabled and the flip-flop is cleared. 4.3.6 Load the Boundary Regi ster (MPLD): 701704 8 The protected area of core memory is established during the performance of this instruction. A number that represents the number of 2000 word b locks to be protected is sent from the AC to the 8 jam inputs of the boundary register flip-flops via I/O bus 03 through 07. The signal on the SDO line (OV during this instruction) is inverted and applied to Rl11-D28S. The signals on the device selection lines and IOP4 are decoded by the W1 03 decoder module and the resultant signa lis app Ii ed to R111D28R. The AND gate is enabled and its output signal is applied to a pulse amplifier generating the MPLD (lOT 1704) pulse which enables the jam inputs of the boundary register jamming the number into the register. The output signals from the boundary register are sent to a comparator circuit at the top of drawi ng D-BS -KX09-A-2 (sheet 1). Bits 3 through 7 of the referenced address (bits 3 and 4 speci fy the memory bank number) are a Iso sent to the comparator circuit and compared with the contents of the boundary register. Any reference to a memory location with an address lower than the number contained in the boundary register causes the KMA < BR signal to be generated. Any reference to a locati on whi ch is equa I to or greater than the contents of the boundary regi ster has no effect • 4.4 DETAILED DESCRIPTIONS The logic contained in the four circuit blocks (Figure 4-1) is described using drawing D-BS-KX09-A-2 (sheet 1 and 2) as a reference. The PDP-9 Mai ntenance Manua I drawi ng reference conventions are used in this manual to reference PDP-9 engineering drawings. 4.4.1 Comparator Circuit The comparator circuit consists of nine AND gates which compare bits 3 through 7 of the referenced memory address with the number stored in the boundary register. The number in the boundary register represents the upper limit of the core memory protected region. If BR7 and BR6 equal 1 the first 6000 locations are protected I etc. Complementary signa Is (BR3 (0) through BR6 (1) and BR7 (1)) 8 are sent to the comparator and connected to the AND gates. Bits 5 through 7 of the referenced address are jammed into KMA5 through KMA7 during the fetch cyc Ie as the instruction is being read into the MB and the complementary outputs from the flip-flops are connected to the AND gates. Complementary signa Is of EMA3 and EMA4 (bits 3 and 4) of the address are a Iso sent to the AN D gates if the memory extension control is in use. This ANDing of signals causes the KMA < BR signal to be generated if the referenced address is within the protected region of core memory. 4-5 4.4.2 User Mode Enable Circuit The user mode enable circuit (sheet 2) consists of the PRE-USER MODE flip-flop, the USER MODE fli p-flop, and a number of control gates which enable and disable the KX09A user mode. The USER MODE fli p-flop is set or cleared by the DONE (1) signa I from the centra I processor depending on the condition of the PRE-USER MODE flip-flop. The lOT (0) signal from the lOT flip-flop in the PDP-9 central processor prevents the generation of the USER MODE (l)B signal unti I the lOT flip-flop is cleared. Therefore, an lOT instruction that set the PRE-USER MODE fli p-flop does not cause a violation. The PRE-USER MODE flip-flop can be set in any of the following ways: the DCD gate at the set side of the flip-flop is enabled by an MPEU instruction; the direct set input (S202-C32M) is enabled when the START key is pressed, if the PRTCT switch is in the UP position; or the direct set input is enabled by a DBR instruction, if MB02 (1) is 1 (bit 2 of the word deposited in location 20 or 0 when a violation is trapped) • The PRE-USER MODE flip-flop can be cleared in any of the following ways: the EXT (1) and PROG SYNC (l)B signals are ANDed together during a JMS 0; the EXT (1) and API BK RQ (l)B signals are ANDed together during a JMS X; CAL (1) and IRI (0) signals are ANDed together during a JMS 20; the 0 .... EPC signa I generated during an I/O RESET: or the 13 -+ CMA signa I generated when a violation is detected. When the USER MODE flip-flop is set, the USER MODE (1)B signal goes to -3V. It is sent to the PDP-9 I/O control (drawi ng KD-3 (3)) where it is appli ed to S 107-H 18S as UM (1). The UM (O)B signa I at the output of the inverter goes to OV and performs the following functions: disables the output from R111- J12H (drawing KD-3 (3)) preventing the lOP pulses from being generated and inhibiting the lOT instruction; prevents data from being loaded into the AC during an input transfer by inhibiting the generationof the OR ACI signal (drawing KC-12); prevents an output transfer from the AR by inhibiting the generation of the lOT OR ARO signal (drawing KC-12); during operate instruction, disables the output from Rll1-J28H (drawing KC-10 (1)) preventing the RUN (0) signal from going to OV (the HLT instruction is disabled); and inhibits the generation of the LIO and DASO signals (drawing KC-13) required for an OAS instruction by disabling the output from Rlll-D07U. 4.4.3 Monitor Circuit The monitor circuit decodes conditions that cause violations and generates the 1 .... FOUND 1 signal. The conditions that cause a violation are the second XCT instructions in a chain of XCT instructions (the first XCT instruction is allowed), a H LT instruction, an OAS instruction, an lOT instruction, a reference to a nonexistent memory bank, or a reference to a memory location within the protected 4-6 region. The HLT, OAS, and lOT instructions are totally inhibited when the user mode is enabled. If a H LT or OAS instruction is combined with any other operate group instructions (microprogramming), the other parts of the operate group instruction are performed. An instruction in the illegal category is detected by decoding the operation code (MBOO through MB04) of the instructions. Then, the EXT (0) conditions a DCD gate at the set side of the JAM VIOLATION flip-flop during a fetch entry and the IRI (0) B pulse sets the flip-flop. The JAM VIOLATION pulse is sent to the instruction decoders and generates the 1 .... FOUND 1 signal if an operation code for an illegal instruction is present. A reference to a nonexistent memory bank is detected by ANDing the MEM OK (1) and NON-EX MEM (1) signals. If both flip-flops are set, the 1 .... FOUND 1 signal is generated. If a memory location within the protected region is addressed, the KMA < BR signal is generated and inverted conditioning a pair of AND gates. One of the AND gates generates the 1 .... FOUND 1 signal, if the instruction is a JMP to an address within the protected region (the PCI (l)B signal is -3V) , and if the program was not just started by depressing the START key (ADSO (0) signal is -3V). This logic allows a reference to an address within the protected region when the program is started with the START key. The second AND gate generates the 1 .... FOUND 1 signa I if an address within the protected region is addressed directly (IR4 (0) signal OV) and if the instruction is not a CAL instruction (CAL (0) signal is OV). This logic allows an indirect reference within the protected region and the execution of a CAL instruction. 4.4.4 Trap Ci rcui t The trap circuit consists of the FOUND 1 and FOUND 1 SAVE fli p-flops and their associated gates. It is enabled and the 13 .... CMA and FOUND 1 SAVE (B) signals are generated if a violation is detected and the user mode is enabled. The USER MODE (1) and PRE-USER MODE (1) signals are ANDed together; the resulting signal conditions a DCD gate at the set side of the FOUND 1 flip-flop. Then the 1 - FOUND 1 pulse sets the FOUND 1 flip-flop when a violation is detected. The leading edge of the FOUND 1 (1) signal sets the FOUND 1 SAVE flip-flop generating the FOUND 1 SAVE signal that is applied to the level input of the PV flip-flop (drawing KC-12). The SM flip-flop is set (CMA 24) and the SM1 signal is ANDed with a -3V signal from the FOUND 1 flip-flop generating the 13 .... CMA pulse. The 13 .... CMA pulse is sent to the direct set input of the CMA 2,4 and 5 flip-flop (drawing KC-19 (1)) setting the CMA register to 33. The PRE-USER MODE flip-flop is cleared and the PROTECT VIOLATION flip-flop is set by the 13 .... CMA pulse. To prevent a second 13 .... CMA pulse from being generated, the SM (1) signal is delayed and ANDed with the CLKD pulse generating the MEM START pulse that clears the FOUND 1 flip-flop. 4-7 When location 33 is addressed, the IRI flip-flop is set and the IRI (1) signal is applied to the jam input of the PV, CAL and IR flip-flops. With FOUND 1 SAVE present, the PV flip-flop is set and the PV (1) signal disables the SA inputs to the IR clearing the IR. The PV (1) signal is also ANDed with the PIE (1) signa I. If the PIE (1) signa I is -3V (PI enabled), the level input of the CAL flip-flop is disabled and an effective JMS 0 is performed. If the PIE (1) signal is a OV (PI disabled), the contents of the IR are decoded (all 0 at this time) and an effective JMS 20 is performed. Since the FOUND 1 flip-flop was cleared by a MEM START pulse generated during a preceding cycle, the DCD gate at the clear side of the FOUND 1 SAVE flip-flop is conditioned by the FOUND 1 (0) signa I. The MEM START pulse generated during this cyc Ie enab les the DCD gate and clears the FOUND 1 SAVE flip-flop. With both flip-flops cleared, the trap circuit is ready to check the next instruction. 4-8 CHAPTER 5 MAl NTENANCE The maintenance procedures contained in the PDP-9 Maintenance Manual apply to the KX09A Memory Protection Option. 5.1 DIAGNOSTIC PROGRAM The diagnostic program MAINDEC-9A-Dl EB-D checks the KX09A Memory Protection Option for norma I operati on. All lOT i nstructi ons associated with the option are tested and the logic's abi lity to trap instructions, which can interface with the protected area of memory, is checked. The instructions tested include HLT, OAS, any lOT, and an XCT followed by an XCT. Operation of the boundary register is then checked by a lIocating protected areas of core memory in segments of 2000 locations. 8 During the boundary register tests, the program checks that a protect violation does not occur when the referenced address is equa I to the contents of the boundary regi ster. Additi ona I tests are provi ded in the diagnostic program to check KX09A operation when the PDP-9 is equipped with the KG09A Memory Extension Control option and/or the KF09A Automatic Priority Interrupt option. 5.2 RECOMMENDED SPARES Table 5-1 lists the modules used in the KX09A. All of these modules with the exception of the W640 module, are used elsewhere in the PDP-9 system. Since it is unnecessary to carry duplicate spare modules, one W640 module is the only recommended spare. Table 5-1 KX09A Modules Quantity Type Function 1 B104 Inverter 1 B105 Inverter 4 B213 Jam Flip-Flop 1 B310 Delay 5 R002 Diode Network 22 Rll1 NAND/NOR Gate 5 S202 Dual Flip-Flop 5-1 Table 5-1 (Cont) KX09A Modules Quantity Type Function 3 WOO5 Clamped Load 1 W103 Device Selector 3 W612 Pulse Amplifier 1 W640 Pulse Output Converter 5-2 CHAPTER 6 ENGINEERING DRAWINGS This chapter contains the standard bloc.k schematics, circuit schematics, and engineering drawings necessary for understanding and maintaining the KX09A Memory Protection Option. The drawings are listed in the same order as they appear in this manual. Engineering Drawings Drawing Number Title Revision D-MU-KX09-A-1 Module Utilization List A 6-3 D-BS-KX09-A-2 Control (Sheet 1) A 6-5 D-BS-KX09-A-2 Control (Sheet 2) A 6-7 D-TD-KX09-A-3 Memory Protect (Sheet 1) 6-9 D-TD-KX09-A-3 Memory Protect (Sheet 2) 6-11 D-TD-KX09-A-3 Memory Protec't (Sheet 3) 6-13 D-IC-KX09-A-4 I/O Interface 6-15 D-IC-KX09-A-5 Cable Connection Type B 6-17 Module Schematics B-CS-B 104-0-1 Inverter C 6-19 B-CS-B105-0-1 Inverter E 6-19 B-CS-B213-0-1 Jam Flip-Flop F 6-20 B-CS-B310-0-1 Delay B 6-20 B-CS-R002-0-1 Diode Network A 6-21 B-CS-R 111-0-1 NAND/NOR Gate F 6-21 B-CS-S202-0-1 Dual Flip-Flop D 6-22 B-CS-WOO5-0-1 C Iam ped Load B 6-22 C-CS-W103-0-1 Device Selector D 6-23 B-CS-W612-0-1 Pu Ise Ampl i fi er C 6-24 B-CS-W640-0-1 Pulse Output Converter L 6-24 6-1 4 3 2 I 5 6 7 8 9 10 II 12 13 4 5 6 7 8 14 15 16 17 18 19 20 I 21 22 8213 Rill G795* I A 0-+8 8 MB #1 #2 #3 BITS CP CP CP t--t--MEN B213 8270 RC BR5 BR7 ~ BR4 BRB 3 4 WA'Ul* 5 6 7 8 9 II 10 12 tmllT Rill :;;~ ~ I--- 15 14 16 17 I 18 19 20 21 22 EXT -f-- I 19) R I ~ I sza2 IRIC'S) Ce) C2SR A30T B32T 5Z02 H R 11 FCUNO I C32R A32T 24 25 26 27 28 29 30 31 32 WtB3 RII WS4;B RI RI'A~ ~7.A7 I elK ** I-----~S;Q(B) I-- C29D t--- I----- (S) 1f\4Is)- USER MPSNE I--- 1------+---+-----' B25f I--- 24 029F D24M iRESTART~ Rill WJIB5 Rill V ~ 1/ ~ ADSO I I SM INDI- ~ ~M(8) : 33 " ~~~~ "" 34 35 36 37 38 39 40 41 42 " " 43 44 / ~ V ~~ 1 / I ,Iv I V . ~~I/V PVoIlENA B PVoIlEPC :==~A29M (1 )B f-j 1----, I ITI3N f---- I---I---- MB ·SI (8) i I I ~ i I ~ ~ USER M~E(I) IUSER iUDDE( 1) NOTE: * DENOTES MODULES USED ON CABLE ASSEMBLIES.. * '* A 7 "" c I L---..r-:-sP-A-P.~E DE LAYE CATOR I - - - >== CABLE SM I----DELAY ED f---- PCI I. 8 "" 1----~1ll~1!!-8--J-'!.Rull..!,..l-I I----- (1)B f---- I ~ ~ FOUND J SAVE (8) I Rill "" XCT (8 PV:oIlEt.lA Rill I I I--- B vV ~l"'-. a~III'{" ~:':'" I' ' m,'l ~ ,",_ • I I - I---- I C32F1 R EMA o V 'V e32R / SPAP.E SPAP.E I. t---~S(1)B I MS l"'-. I ""1/ /1'- MEMOK 12(1)8 "" 1 C MEN V ~ 1 ! : vV "" . 1 'sPAAE - I--- 81'B4 832M PROTECT SAVE r---- I--LATION I:~~~~B SYNC 23 VI 0- A27T I--BUS A30T i _ MB I MBI 2(J)B 13 44 D ~~ I r- - ~~~~ON r---I Any ~\!., AM SM(B) EMA .03 10 5Z112 ~ ** I--- :::: :;!~ Rill c i I A29S ~ <E.2 KMA7 43 "" '01(1)S~CBI(B} ~~ 'B3(1)~r-.N-O-N_-EX-+----1 S:::E::::EI t--t--- 'i:JI' A26T I -4A27Y ~ FOUND I ~ I---- F(UNO 02(1)8 1 I----- 1 •• !O-:O I 8270 I---_ ~ t--- 2 ~ Rill MB I----- •••·a. ::: ~O;; 11------+-----1 r----- c I .~:( 1)8 I----- '."G* FOUND 1 XCT M8 BR3 42 S~~P I----- ' I 40 41 1~ I-_AR2B_7BT~2_AR_~~7n_~~~I~~~~-~I~--~---+----~--~---+----~--~---+----~V--~~~,7~ }---- B213 39 SKIP OF I ~ I SIGNALS SIGNAL SIGNALS~IGNALS I 9-17 9213 I 38 A2SF XCT 1 I----- 37 30 S2G2 8270 I----- A2S0 Vl633' 36 29 R II ~ !-__-t-__-+.Jtil10Iil"*+G!>.L79S* G 7qF!!1 VlB34* 35 28 RII -1-----1--I----I - - - - A24T I----- A2ST i----+-=::.c=--+-------I A22T 34 27 Rill 8270 I----- A24K KMAS 31 33 26 RRB2 ~i.,,,' :::: '"," ::-i-A2-6-R-+-:;-UN-O-I-t-O;-N-0---i,~7 M8 32 25 Rill I KMA5 BITS 2 24 A24F I D 23 3 6 5 4 DENOTES A MODULES ONLY TO BE FITTED KG,0'9 OPTION IS WHEN INST~LLED 3 2 O-MU-KX09-A-l Module Utilization List 6-3 8 7 6 4 5 2 3 W:!J !J ~K ~ ~~ J D D5 ¢ r---------------~-----------------------------------~~----------------------------------~-------------------------------+f~f~l~--OKMA < ER EMfl3((II) os !/l(B) 1 BR3(1) U -,'-'Rill rv" /\,' ~ I< 'L) OSI ,~ Rill A 2.4 N rv /\ BR 3(0) ~ Rill I EMA4(1] EIYIA 3(1) T AZ", D K. T L F" F K KMAG(lJ K/VIA SO) BR 5(¢) V p V J Rill Rill 1'92.4 AU SO~(B) IH rv/\ Rill M 8R5(rTl) BR4(I/'J) BR4(1) S K KMA 5(1) E. R "->/\ L K OS I (8) D IN Rill Rill A 2.4 A24 Rill Rill AZre liZ", P Rill AZ,,- ~"""f------o. s D(Zl (~) B S D(2l 0)8 c c MPLD(IOP 17¢4-) IO SUS 03 W018 ~ W¢2.3 D2.5 INDICATOR BRAC.K.ET MPSK (lOT 1701) !VI P CF ?A c--------------------.r-=---::> SK I P RQ SD~(B) CL cs rOT 17¢2 (MPEuj rOT 17\214 (N1PCN£) F MPLD (IOT 17¢4) CT SD0(~)B 10 PWRCLR K 8 rOT 1702 TOT 1'7(/!4 u V L SD~(B) PROTECT vtOlATION(I) SP(J(I)B N DK DS2. DS3 DS4 DS5 I I CLKD NON E.X MEM(I) USER MODE-O)8 P ~ PM rv V ~ ¢~BR 3,4 ~/\ AM SY/'IC(I)8 R l(il 2R.; , ~Il ~lJ ~ ~ B 8R3(1) . BR4(1) BRS(I) PWR CLR (8) ----'-''-'--CI-------r'-=--''-'-----='-r-' 'u 'ORIO(I)~~ MEM STROBE(B)-----<>----~r><l ER 7(1 WpJI1'5 ¢---o>BR 5, t:c,7 813 I¢ PWR CLR(B) -= MEII'lSTART-..:.;N'-DI><1 A A 8 7 6 5 4 3 2 D-BS-KX09-A-2 Control (Sheet 1) 6-5 8 .. W:'"zJJU 0 per(l) .PCI(I)B "'-'V MEM START , D Rill DI3 2 3 4 5 6 7 Rill A 27 I¢¢il M P I~FOUND I BY :rOT OAS HLT T p N -= PV 0 R S MB 0¢(l) B MB ¢3 (1)6 EMA L A MS ¢4 (¢) MB 12 (I)B MB(tJz(J)B JAM 'RIll VIOLATION M8¢1(I)B N P J A R(tJ(lJZ B~" S T R0~2 R R0~2 IJ 8J\G F D MB 15(1)8 B~" r= R~(tJZ. R~i2IZ. fl31 :2 Rill A K R(tJ¢Z A32 M BJ.6 K ti NA Me M T P R0¢Z K L T: M8 ~3(0) A27 F PV(! EPC U IJ NA R V Rt'~z 1J3J R~¢2. 5 N A31 C C N MB fl00) 8 :rRI(~)B USER MODe-O)e 13 -;CWlA r= NlB III (~) til'S [J2(fJ) J EXTOl API BK RQ(J)8 N M8¢3(a» IIiJ PWR CLR(B) JAM VIOLATION MB(2l~(J)B MS¢3(i)B I~¢.n. I""OUI/O I -= JAM SAVE (8) DONE (/) VIOLATION r- -Rill I I J. -= C28 I L ___ ~ ME [J3{J) I IO pwR CLR (13) MEM START WI WI K K 04EPC B MB9}IO)B MB 12(1)B AD50(J) MB 12 (I) P E v T R'itJ2 EXT(¢) v -= I~¢ f\. B A32 USER MODE(I) Y PRE- USER MODEO) MB~Z.(I)B SD~(I)B ME 15mB MEIS(I) r A A 8 7 6 5 4 3 2 D-BS-KX09-A-2 Control (Sheet 2) 6-7 8 7 D F"ETCH NORMAL CAL I 21 6 NORMAL 32 2'3 ENTRY I CLR I 12 IA0 I 24 5 ENTRY I ~0 I 10 I 4 3 2 NORMAL FETCH ENTRY 21 12 CLR I I I MCDE~L____________________________________~ USER D PR E USE R /v1 0 DE "'-.1_ _ _ _ _...;::C'-'-'AL=-·=-IR~I'___' CAL ____ ~ _____________________________________ ~ IRI __~ ______4 -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _L -_ _ _ _ _ _ _~ c=J £VEN IF THIS KMA<'BR _____ OC.C.URS) "F"OUNb 1 WILL NOT C.ET SET BEC.AUSE "PRE USER FETCH ENTRY BHOW BOUNDARY ~ibULNlT1~~, CASE(p1 21 I 12 I I CLR 24 MACHINE IS STARTED USER MODE { FORCED XCT ENTRY CAL lA0 ENTRY FOR NORIViAL CAL 33 CLR 24 32 I 23 G0 I Bt:::LOW THE BOUNPARY WITH [)SER MODE ON. RRE: USER MOD£ - DONE 1 I I I I I ADDRESS "REFERENCED. IZ I MODE ((lJ) NORMAL FETCH ENTRY 21 12 I I PRE USER MODE '%."'-_ _ _ _ _-----'-"\3'-'~'--"C"-'-M'_"'A___'1 KMA<'BR c ~_ _ _----,I MAY IKMA <. BR· !=OUND \ FOUND 1 SAVE DEPENDS ON IY/£/YJ STARTI ~IF~O~U~N~D~I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~~~E=M~S~T~A~R~T_.F~o~O~N~b~l~ py 1 FOUND PROTECT VTOLATION _ __ FETCH DAC 1 ~ CONTINU£, PCI _ _ _ _ _I~I=3_~~C=M~A~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~C~L~EAR£b ENTRY \\TAD" CASE(Z) I 2.1 I 12. I CLR I D£FER 24 WHERE: "Y" IS IN THE:" I 31 ENTRY \\y" ClR I I FORCED 24 33 XCT E"NTRY CLR I I c • IRI 1 !='QUND I SAVE I SAV£ - IR.I By PROGRAM IA~ 'CAL" 24 32 ~NTRY "CALli I 23 I Gel : 10 12 21 AREA. PROTECTED LlSER MODE PRE USER MODt • DONt:: I PRE OSER MODE ~i______________________________________~1~3~~~C=M~A~ kNiA ~ BR 1 IRI' FOUND PV FOUND r RI • fOOND I SAV': \ SAVii. 1 IKMA<BR-TI ME-til STARTI FOUND ISAV~ __________________________________________~I~F~O~U~N~D~I____________________=ms~M~S~TA~R~T_·~FO~~~ND~II PROTECT VIOLATION ______________________________________________~1~13~~~c~M~A____________________________________________________~C~L=c~~R~E~D_B~y~P~R~O~GR~A~M~t B JM P "y ; CAS E. (3)L.1~2.:...1~--.!..!I2."----c-:L.1~C~L:-::R~1~7:....:4~~I~Z_:_;_;:!____;;:3;;:;;3~1=;;iC~L::_:_R~:_;;:_;:_<_I-----'2.::..4-'----'---3=-2=--L-'2::..:3'---~G<-"'0'___'---_-'-'1!ZI"'--_--.L-~Z=-'-J____.1___.!.1~Z ---L WHERE. "Y'- IS IN THE KMA <... BR PROTECTED AREA. ________----'-1__________________---'1 MAY Go 0 AWA YI DE PeN 05 FOUND I ON CONTENTS OF "Y_: II<MA<8B-PCI MEMSTAR"rt B FOUNDI5AV£ ________________£IF~O~VN~D~I____________________~M~EM~sT~AR~T~-2~~OU~»D~d PV IRI • fOUND' SAVE 1 USER MODE, PRE USER MODE, PROTECT VIOLATION ETC; SAME AS ABOVE: eliSE. A A 8 7 6 5 4 3 2 D-TD-KX09-A-3 Memory Protect (Sheet 1) 6-9 8 7 NORMAL lOT FETCH 21 2 CLR lOT D PRE I \ I I I 33 I /0 I I CLOCK PULSES D DONE· PRE MEM 11-- FOUND 1 FOUND 1 ~AVE M ODE I USER STARTI IFOUND 1 START· ~I MEM n RESTART IIR! • ,QUN!) PY PROTECT VIOLATION 1 SAVE I. RI • FOUN D 1 113-?-CMA CL.EARED BY SAVE i PROGRAM 1< o 13~CMA FETCH ENTRY OF' NORMAL EX£CWT£ INSTRUCTION ZI 2 C LR 70 XCT OF XC.T I I \ I I I MOD£ # USER MODE t XCT ENTRY VIOLATION XCT £NIRY FINDS SECOND EXECUTE INSTRUCTIONS 33 CLR 70 I I 33 I I o o VIOLATION PRE USER I 2 t + 7~ f FOUND I c 3 13 ->' CMA I USER MODE JAM 4 xCI ENTkY FOR CAL AS IN DWc,,(I) IA0 ENTRY FOR CAL AS IN DWG(J) CLR 24 32 23 ~0 /~ ENTRY USER MODE l(ll 5 6 13~C.MA FORCED BY lAID ENTRY NORMAL CLR 24 I 32 I 2. 3 I (;0 I OF CAL NORMAL FETCH ENTRY I 21 I I~ 12 I CLR I o I PRE. USER c MODE· DONE I XCT o XCT OF XCT Ixc, 'FOUND I ~OL)N D I OF MEM SrART I XCT I FOUND I SAVE roONp I IRI - FOUND 1 SAVE py I • Ir1fM tRI- STARr I FOUND 1 SAVEl CL.EAREP BY P'ROGRA M }: + eLK PULSES NON EX MEM , MEM STROBES MEM OK NON EX MEM B CLEARED FOUND \ ~OVND IFourm! I SAY£, FOVND I· MEM START 1!:3~CMA NOTES: 'i CLOCK PULSE CLOCK PULSE I CLeARED PV PRE PROGRAM IIII£M QK'NEXM 11IEMSTARTI PROT£'CT VI 0 LATIOl'l FQUIID MODE f USER MOPE t USER BY PRE US£R By / NORN\AL. 2 STARTS A MEMORY CYCLE, BUT THt::RE IS NO MEMORY PRESENi TO BE STARTED I SO MEt.'! STROBE PROGR .... M% CLOCK PULSE , SAY£· IR'!:I DOES NOT RETU'R~. 3. BEC.AUSE MEI)'l OK 0) HIE. CONT~OL MEMORY IS RESTARTED (coNTROL MEMORY STALLED BEC.AUSE ME/Y'I STROBE SHOULD HAVE RESTARTED IT), ALSO NON EX MEM IS SET. MODE' DONE.I 13 ---+ CWIA I CLOCK PULSE 4. NORMAL. CLOCK PULS~ 5. NORtYlAL. A B A 8 7 6 5 4 3 2 D-TD-KX09-A-3 Memory Protect (Sheet 2) 6-11 8 6 7 NORMAL FETCI-\ CYCLE FORCED 5 XCT ENTRY 4 'AQJ ENTRY 3 2 I (CAL) H L T LR(llJ_LI--=12=----LI-=L:.::L:.:.R-'--J....l_7-'---'-7--'----'-"0=---1.-=33=----"-:_--=-C=LR'-'--_--II_ _2=4-'--_---'--=3-=2=------1'----=2:...=3'-----LI-=~:...=0=-------,--1_--,'=.0__-,--=2-,-'------'---'-"2~_'___'C=-:L=R--'--...J FOUND 1 _ _ _ _ _ _ _ _ _ _ _L....!:!",=-:EM:.:...--=.ST.!.-'.A.c:::l<'-'--'TI D D FOUND I SAY1~ _ _ _ _ _ _ _ _ _ _ _-11FEio21uiENlQD=IC======:RM!1E}2MOS~T~AQjR~T::::':JF~oIT!Ll~'"bITJII PRE USER D CMA 13 MOD~ ~L_ _ _ _ _ _ _ _ _ _~1~3=~~cM=A~1 USER MODE i·--------------------------~D~07.N~~~·'P~R~E~u~St~R~MDO~D~EI PROTECT VIOLATION ________________wll~3~=z~C~MnA_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~C~~~EA~R~E~D~B~YL_~P~RO~G~R~A~M~~ PIE IRI' FOOND ! SAVEl PV CAL ______________________~I~I~R=I~·I=R~==0~·~EXT~X~________________________________~rR~1~·~r~R~~~01 (IF PIE (I) TH~N NO CAL) PV ~L_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~D~O~N~~_·~p~vl ~ EMA ____________________________________________~lp~V~·~T~I__P~V~·~T~!1 PY ~ EPC ________________________________________________________________---'c=]~ c c B B A A 8 7 6 5 4 3 2 D-TD-KX09-A-3 Memory Protect (Sheet 3) 6-13 2 3 .4 5 6 7 8 0 0 10 lUI ff 10 IUS " W85~ W85~ W85¢ W85~ CO~ I C002 C003 CD04 0 •E •H 10 BUS ~~ 10 BUS ~4 10 BUS ~5 10 BUS Gl6 1: 0 BUS '17 10 BUS !IS 8 C D ," 10 BUS II 10 BUS 13 10 BUS 14 10 BUS IO BUS 16 -1 10 BUS 17 IO OFLO + I-CA INH lOP 4 10 ADDR ~3 API ~ RQ 10 ADDR ¢4 API ¢ GR (I) RG PROG INT RQ IO ADDR ¢5 API ¢ EN IN RD RQ 10 ADDR ¢6 API RG RD STATUS 10 ADDR 1/J7 API GR (I) 10 PWR CLR 10 ADDR ¢8 API EN IN OS ¢ 10 ADOR ~9 OS IO AOOR 10 API 2 GR (I) OS 2 10 AOOR II API 2 EN IN DS 3 10 ADDR 12 API 3 RQ •p •S OS 4 IO ADDR 13 API 3 GR (I) OS 5 10 ADOR 14 API 3 EN IN 10 ADDR 15 DCH RQ •V • SO 0 10 ADDR 16 DCH GRANT SD 10 ADDR 17 DCH EN •T 15 INC MB lOP 2 •H •K •M 10 BUS 12 WRITE RQ .. API 0 EN OUT I SKIP •E 10 BUS ¢8 lOBUS lOP •K • •'P" •S •T •V • 10 BUS ~2 :r 0 RUN (J) 10 SYNC C API 2 RG IN B NOTE . ALL W85¢>'S HAVE PINS C,F,J, L,N,R,U GROUNDED. 8 THIS SIGNAL IS SPECIALLY WIRED FOR I<G09B IN ~OID9A PIN A3IE. A. A. 8 7 6 5 3 2 D-IC-KX09-A-4 I/O Interface 6-15 7 8 4 5 6 2 3 D D FROM COMMENT TO Z (1)3;4 SECTIOti SIGNAL LENGTH WITH BASIC. ...- - ----- . '- ----- - - - - MEMORY ONLY 84 KD~9A IO BIJS W85~ NlE:¢98 AB29,3¢ W850 USE CA'BLES'l'l'1 THRU 9. CABLES# I, Z. W85,0 M£)b9B AB31,32 W850 KD¢9A IOBlJS 84 3 804 G79ra IYIE~9E H35 G79G KC~9A CONT 84- 4 B,9JS G79G ME~qB J35 G79G KC {39il CONT 84 S B0G W~34- F37 W~34 KC!:09A CONT 84 NO. Loe I CD 1,2 c TYPE SECTION ME:09S LOC 'TYPE W,023 ME,09B ~DICATOR PANEL G* DZ5 WWl8 7 A>2J3 G795 IVIE,09B 8 6.03 q "8,07 -- CONT 2.4 MC7(58 MB0-8 G7 G795 IYIE.09B E38 Wl2f33 fYlC7f1B MF9-17 73 W033 MEf09B F38 w~33 'MC7~B CONT 77 "I D38 W033 10 fl¢3 ~7q5 MEI2f9B D38 WrJ33 II B0'3 G795 ME~9B £38 W¢33 MlVl¢9A MB9-/7 ~7 12 B¢7 W(J33 /V'IE.,09B F38 Wr;P33 IVIIVI¢9A CONT "7 "* MM~9A IYIBP--B J I H I F I E I D I c I B I A I I r I I I I A,B,CID,E.IF IHIJ I I I I I I I MEM MEM MC79)B MM¢~A ARE STU TO BUS CABLES A (21D TW.!AI'RS) CABLES I, 2,G, NEED NOT B~ TAPED WITH POLYESTER FOAM. WITI1 EXTENDED MEMORY SY5 (sYS WITH KG~9A) USE CA8LE511'/, TI-iRL> G,IO) 1112. WITH EXT£NDED MEMORY SYS CHECK THAT THERE IS A G797 IN A~I ~B 3U 3 in 7 IND. C 12 34PANEL 4- F38 E38 D38 I~ D n- fn D251 D38 E,38 F38 I CP c KC~qA t Bill I IJNL'E.SS OTHERWISE DENOTED ALL CABLE':> ARE Iq COND FLEXP'RINT IY4' WIDE ADHESIVE BACKED POLYESTER FOAM STRIPS (DEC. PART""12-.058(07) ADHt:SED TO ONE SIDE OF EACH FOR SEPARATION. CABLES TO BE BUNDL!:D 1"1 ~\PPER TUBING (DEC. PARTYlI2-RJS8{o8) H35 J3S F37 IO 'RIBBON CABLE. KDS/l9A I I I I I I B -r- --L- AB Zq,30 AB 31,32. B FRONT EXTENDED FRONT MEMORY 'BAY REAR BASIC BAY BASIC BAY A A 8 7 6 5 .4 3 2 D-IC-KX09-A-5 Cable Connection Type 6-17 CI 86 C2 116 F ~c_, 100 E 3,000 C3 116 L CII 86 R V RIO 100 K 8% T D r-------., I -3V a-IIIV ,I I I I D7 D-662 D6 C4 I D-682 C6 .01 liFO D8 D-662 MFD H D4 D-662 I UNLESS OT~RWISE INDICATED' ~:'lci~... A~J'=~% 2 I -3V : GND L~~R~!':._J B-CS-B 104-0-1 Inverter r-:3",,-" I STRATE r------------1~----------_.------------~------------~------------~~~~+_~--_oB-18V F s N K v r---------------------~~----------------------._----------------------._------~--~~~----~~--~C GND CI 116 C2 86 C3 IItI C4 16 RI2.....--II-.... 100 10% Q3 Q4 D O-....'VV\.--01~/...1 E U UNLESS OTI£RWISE INDICATED' RESISTORS ARE 1/4W; 15% CAPACITORS ARE .... FD TRANSISTORS ARE DEC 2894-18 B-CS-B105-0-1 6-19 Inverter M GND ()S GND CIO UL .. ~ 022 >RI9 R2!5 1,000 1,000 .. ~21 /."":: 110; MFD ~ ( -3V ~'D24 '-===' QI4 RIB 100 10% R24 100 10% R23 6,800 R20 6,800 Fru 1 _~'-C~9 10 .. ~D20 :;:; ~ "g~~2 QI3 '-< Ug~~2 -3.5V I ~, r-------~--~------_.~--------~~--_+--~~~~~----~~------;_--~----~_.~--------~~-~2~.~~~.~ ...~ ~ "~ nJd \_ Q3 DEC 3639B R8 470 Y.. R2 750 >R3 ) 1,500 R1 1,500 C~ 3639B .01 MFD C2 .01 MFD RI3 \1 Q4 DEC 3639B HJ 03i, (MI- '~ ~t~ ~ RI 1,500 ~ 017 .... ... ~~DI{tjQIO ~g~g9B \'-- ) RI4 )1,500 T R22 - CB IO% _ , RI6 150 RI5 1,500 662 -4.2V RI1 1,500 ~ R21 1,500 R27 ~I/~~~, 470 ~ Ril 7,500 25 DEC 3639B - ;,. 100 10% 00 J~FD I?f./o ~ R26 g~IC 1,500 R28 1,500 3639B R29 150 R30 750 ~----------~--------------------------------~-----------.----~~--~~------------------------------~~--~~---'~B -15V UNLESS OTHERWISE INDICATED; RESISTORS ARE 1/4W; 5 'Yo DIODES ARE 0664. TRANSISTORS ARE DEC3009B B-CS-B213-0-1 Jam Flip-Flop R8 330 R5 330 DE3 DE2 f1 AD I N PUT AE \.AF AH AJ A~ -----v-- AL OUTPUT f1 AM INPUT RIO R7 100 R4 100 RI 100 Q3 DEC 3639 AN ~P AR AS TAPS AJ -y-- AU OUTPUT 100 f1 BD INPUT BE ~F BH BJ Bt) -y-- TAPS TAPS AC,AV BC,BV GND UNLESS OTHERWISE INDICATED' RESISTORS ARE 1/4W', 10% DIODES ARE 0-664 DE I - DE4 ARE TECHNITROL, .05 usee, 330.n. TAPS AT .0125u.ec, 00-330-5-1,6012 B-CS-B310-0-1 6-20 Delay BL OUTPUT fl BM INPUT BN \.BP BR BS B1) -y-TAPS BU OUTPUT :: 010 ~ 0664 Oll .1 }- OF }- OK t- ON }- Os t- OV 0664 09 ~: :: ~ 0664 04 .1 0664 08 ~ 0664 03 ~ 0664 07 .1 PO 0664 02 RO :: .1 0664 06 ~ 0664 01 .1 0664 B-CS-R002-0-1 Diode Network r-----------------------------~._------------------------------e_------------------------------~A+IOWA) r------, r-----------------~------~----------------------~r_----~--------_e--___1~~----+:-Oc GNO I I g~~82 i I 018 I 1 0-882 017 0-682 -r-. 012 0-884 Ro----1...- .. 0o----1.... Eo---_I-+-~--{) lo---_--+-O 010 0-884 018 0-882 011 0-884 So---. .--.....--{)T R7 111,000 I \ ~-----.--~~----------------~._----_e----------·--------------__----_e--------------T"""------~<>8-~V :I.. _____________ EXAMPLE OGL2 .J: -3V I LSTRATE ______ JI UNLESS OTHERWISE INDICATED: RESISTORS ARE 1/4W; 5% PRINTED CIRCUIT REV. FOR OGL BOARD IS SIB B-CS-Rlll-O-l NAND/NOR Gate 6-21 ~~D43 ~~D44 .4~D45 ~E ~L R4 10D,000 "04 CI ~ ~l ... 0 1\ ~ ~J~ ~ F . 0'5 .. ?l .... RI l~bo~O R2 121~~.0 ~ - 62 .. "91 f o~ R5 3,000 07 ~~D47 ~ ,rPI~ ~~ 0-862 . ,g~62 H4-- Oil RS 3,000 . o! C3 82 "K . B ..... ~ 0~1 ~7 .,012 o?&;\, r ~2 ~ ,D28 0:;.662 0"17 RI3 RID RII 12r8~~ RI2 121~2 12Ig~~ .,026 RIS 3,000 '8_3l62 U ... Dj!' ... ~I J; U 030 RI7 RI6 3,000 RI9 .4~D31 ,,041 0-662 .. , g~~62 ~6 .~~ ,F; MFD 12'1~~/? R20 ..' 12rg~ g:~62 B-15V ... 1..- INDICATED 1"g~l62 7 ... I UNLESS OTHERWISE .. rP33 0-662 ... ' r~11 " C GNo C4 ~~ 0;'4 f"'II" R9 12,000 10"1. ,... A.IOV(A) ~I~OOO' 'D35 R 14 100,DOD 024 1\ .,...~ N .. .. R7 ..-oV '.025 C2 ~~050 ~.D48 j..-oP ro'b,oOO' 'D16 '~q~! 08 R3 .~46. ~D49 ~ DS2 1,500 TRANSISTORS ARE DEC 3639C RESISTORS ARE IS,OOO RESISTORS ARE 114W,5% CAPACITORS ARE MMFD DIDOES ARE 0- 664 B-CS-S202-0-1 Dual FI ip-Flop r-----------~--------_.--------~~------~~--------~--------~~--------._--------~----------~._--~------<)B-15V R4 3,000 De 023 012 R6 3,poQ 0-662 02 .01 o H E M MFO 021 0-662 ....----...L..l:.....----~..._---oC 019 I 0-882: N p R S u T v CI 018 1 0-662 : MFD 017 .01 R3 3,000 011 05 II 3,000 013 RI3 3,000 I 0-882 1 1 016 1 0-6621 -3V I I 1 1 1 I 1 : -3V IL STRATE _____ ...J1 UNLESS OTHERWISE INDICATED: RESISTORS ARE V4Wi 5"4 DIODES ARE 0-884 B-CS-W005-0-1 Clamped Load 6-22 C3 .01 MFO GNI AA+ I ov (AI AB - 15 RI 15,000 R2 R3 R5 3,000 15,000 IOOPOO RII 10,000 10% R6 R8 100,000 1,500 ~'04 O~ " 02 2,1 ... P,~ .. \l!" 02 ,..~~O AU R22 100,Oeq R24 3,000 R26 Isp!JO O~ '~42 ...-- R33 10,000 10"10 ~~tP RI5 1,500 A~ ... ~ AK 06 .. 039 AT "'"040 0-662 O~ 10% ~~ r~fP O~ "'" R 36 1,500 ) AN AP ...-- fP R32 47 ~010 "'r:6~~ ~" O~ O~.. ~'060 '---- fP "'"048 0-662 R37 3,000 "055 053 1\ 047 0!,62... 0!5 R34 3,000 ~~05;' 051 " C8 C3 0:'8 ~v R28 R30 100,000 ~,500 3~,o ..... ~" "'03 0-662 R20 15,000 rP OV RIO 47 10"1. ... P.~... !P 0!,.9 AR '~34 '-----< 1\ 021 RI7 r,000 ~'031 4~02: C2 3~ "'"023 0-662 RI3 3,000 013 AL AM -'" BO 0- BE~ BF 017 I N W BH~ BJ R4 IS,OOO ~ BL~ :. 012 BN~ BP~ BR~ BS~ BT~ BU~ BV~ UNLESS OTHERWISE R9 3,000 RI2 15,000 10~ "024 BK~ BM R7 100,000 RI6 R 18 3,000 15,000 RI9 100,oco ~~21 ,500 ~ro33 041 ~ ~ I"- 020 D~2-,'" 0;'"2 0-662 ff O~ 036 . 0!5 0~9 AD 030 .. ~t.66~. "'" 03z 0-662 1" 07 , .. R25 IOPOO 10"1. ~ .043 g~P l INDICATED, TRANSISTORS ARE DEC 3639 RESISTORS ARE 1/4 VI, 5% CAPACITORS ARE DIODES 0-664 ARE MMFD C-CS-W103-0-1 Device Selector ~'05O ~ .4~g~162 .. ;:~~ R 35 1,500 '--< ~ R23 47 10% AH R31 3POO "049 044 0-~6~ "'"037 0-662 R27 3,000 5 .4.g_ J;2 C6 ~~fP 09 046 '" R29 1,500 ( ( AJ AE ~~g:l62 ~ .~ CIO .01 MFD .4.8::62 AF I I AC,BC GNO M GNO C GNO r----------------------------.------+----------e--------------------------~~----~--------~A +IOV RIO 08 C5 RI6 10,000 10% Uo---.1 Kcr-j 470 470 MMFO R2 MMFO Q3 IOOV 5% 100 10% 10,000 10% 015 C9 IOOV 5% OEC-S8 022 0662 021 0662 H C2 2 .01 e T-2021 T 2 f l 7 0L 4- 020 01 MFD 0662 019 0662 +E e3 -7.5V RI 1,500 ~-----------.----~~----------;_----~--------------_4------~----~~----~----~------~~~------~__OB -15V UNLESS OTHERWISE INDICATED: RESISTORS ARE 114W; 5% DIODES ARE 0664 B-CS-W612-0-1 Pulse Ampl ifier 019 07 :]11 TI CI RI 100 10% R3 100 10% 013 :]11 T3 R4 R7 R32 M 010 R20 100 10% RI4 R24 R31 R27 C GNO 017 016 -.1.5V UNLESS OTHERWISE INDICATED: CAPACITORS ARE .01 MFO RESISTORS ARE 1/4W; 5% RESISTORS ARE 3,000; 5% o lODES ARE 0664 TRANSISTORS ARE OEC3639B TRANSFORMERS ARE T2071 PARTS LIST A-PL-W640-0-0 015 011 CI5 014 :]11"' T2 06 DB T R23 CI6 04 R6 100 10% RB 100 10',," RI2 RI6 R22 R26 R2B B -15V B-CS-W640-0-1 Pu Ise 0 utput Converter 6-24 DIGITAL EQUIPMENT CORPORATION. MAYNARD, MASSACHUSETTS Printed in U.S.A.
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