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EK-DZV11-UG-001

February 1978

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Document:	DZV11 Asynchronous Multiplexer User's Guide
Order Number:	EK-DZV11-UG
Revision:	001
Pages:	36
Original Filename:

OCR Text

EK-DZV11-UG-001

DZV11 asynchronous
multiplexer
user’'s guide

digital equipment corporation - maynard, massachusetts

Ist Edition, February 1978

The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in this
manual.
Printed in U.S.A.

~ This document was set on DIGITAL’s DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
DECCOMM
DECsystem-10 ~
DECSYSTEM-20

DECtape
DECUS

PDP
RSTS

DIGITAL
MASSBUS

TYPESET-8
TYPESET-11
UNIBUS

*
*
-

W N —

Page

1.3.3
1.3.3.1

1.3.3.3
1.3.34
1.3.3.5
1.3.3.6
1.34

INTRODUCTION&W&MHQ&Wbufibu&w&t»&mmbn*nwtt&bbatfi%*d&fliu*iiflu&lw&hww‘nhwuauwm'&%fi&»hmnn'aw’ouU«‘b’h»wiutucwfiuw»mbumm1“1
pHYSICAL DESCRIMION iw*bbi&w@mifiw&tokowb&b&alfiofim’u&Q&Ot’nuw»flbtlaww&w&vbblhtn«uflttw‘&bihi&»u%wbiqfi&btw1%2
DZV11
.1-3
L
1
. On Configurations
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BCllUInthfaw Cablemwti&#mwmuhnulh*@‘wtnvu*cw&t%uwu»omwnw»tuw»twwbw&&twvnflhwoanw&‘oou%fluuw«wqwm&hwvabh1“3
TWt Cannmtorfi &tofithbwu&inwb%i&bwnu‘ufiInwinmuumbmubruuwwfi&#&w«i&hm"vfimu%mwwhuvimamwnuuui»wwuhuatthuu&&wvtbub1 4
SPECII ICAIIONS ‘«hucflw’»wbuibnwu'fln0»%00&1&ud»flwwtwmmbmuhwihauwbwmfivonfiwwu%tumh'fiwatuhn&v&bflbnbniuuuqowbwibnoiknl '
nvtronmenta ‘on»ui%bumuhnuiuu&t&wkfibuafi»ubmu‘lwuwu&&&d»i&nwu&buutk%ww&ii»mbuumhwwt‘*iauwu»untmu&abawobuwitu1

E wtnca KBRS RO ERER RN FER B U RS R AR E S ER RN R BN B R R R R R R R R R RN R R ERE R R U R AE BB E R RPN BB RS ARR RS R E R TR TR SRR RN
Performanee«;twhw&%%#wlwinuww&wwhwu&&u&fi«w&%b&uoiuitfit&iiw»&w%fimvhn#n%w»fi#»h&fihv%uu‘t«u‘bflwn‘ioflnfltimfitiv&%wihcmuu1 l
ax’-mum

mn iguratlons (E X 2 2 S R

R A R

R RRA RRRR R R

R R R N SRR

Ihroughputwa&wtflvunuuww%w*m*nwubQ@w%um»wuuv%b**@&&wwmabw'buumhub&ttvumu»nuuww&&hmvmuuufiéuwwuuonwu&tn1 I
mlverS&uwbumnfiw«U‘otaw%wbui'flnnit%#to&twu&tuflhwutw&&&w&%ufiu&uwm&mvfibhotu&i&utfi&omv‘w&utib#awamufi«»‘ub&n»1 |
ratl&mrtterflQw#hufl*wfiau&&wtwutthfifwb@#iuictmhhuu&a#mv%autunufi‘&iflua%ub&h&%»biwttbwwmmtiwb«»#n*mfiubuht&u -

Baud Rat@ Gfinmrator &‘tu&&w‘d%otww*luutuwuwwlwiiwmlwW&fi&t%un&‘bhuuufit«&fiwbbhtqbubinuwiwuw&bnb'wt»1“7

perfmrmmnw Summaty nwib*iu&«w&*nflihfim&&utiw&w&Mbkitawu“&vtuuitw“nfi%nw*vwiu&&w»uiiwfimtb&‘bvu&tfiw&1*?
Inttrruptsibnummv%*ifi»%&q’munfi&&&auwt*th&fl%&&htmuu*bti*uwwaw%k&uumu&um%tww%uwhuuububbnbuw&bbbnmuwwuflwfiwas«w*uoua‘1*7

CHAPTER 2
2.1

2.3
2.3.1
2.3.1.1

23.2

SCOPE V&Ovon&b'mlntfitut&nfiwmmlmflfi&w*aiwwmbt*htia&v&uo0»»0&iHunafibutwfiwu«ruutflbi&uww&ndkia&fibfiwubmfituudht#»»wiuu»&t&ln%hozw 1

Jumpcr Cflnfiguratlfin ww&bnnun&uuwvoowttnmhfituflrw»ubmhfifia&itafimuw&bhbimowwwutwwflbbtvbutt&flbfitw&wnnh&adwnfi»Z“ 1
DQV‘W Opcratlun Qiikfifififiwi&&fitbfiti&dfl&dii%*hlbw#u&.**&&*t‘iivWi«0#*&%&&%%%‘*&»&‘1&%&%&v*wb*mlb@‘02” 1
MOd@m Cafltr&l Jumpmr&Uw&&tvvt«uflmmpa &iwo&#&h&&fiw&wtfimwvflu»ut&w&awwebfitbmub&tm«wiu&»w««uit‘wzflz
Madule Installatlanbwflw*bw&vbafififiaflh%hd»tb-t&&uwbndtn&thutbbwwwun%uu*ancw&&&bw&u*mb%filwmwcwmuuwuunbdn»%u002“2
DEVICE REGISTERS

3.2.1
3.2.2

SCOPE fl&h'lv&lbtb‘ddb%itfibbflbibfi‘ib‘h%li&fi&itb*h%&t&«*bthii!flbfibiibwiiflifi"dlfib%ibi&héih&bb’n&fi&mfltwit&%&&w%ttmtiliwiiflwiom3“1
DEVICE REGISTERS uwwwuwtbflO&MnnobflvwliihIuhfl»@&t‘vb&iihi&h&@i'ituwiiitimflnwtiubbn&bwwthib%mununwibau»»&uch“l
Cantral and Statu& R@gl$t¢r&¢bwbb»wwumwaao«w%Huwi*wwwwflwflm&&tuq*am*nabvabmIud&fidmui*wywu»‘uw&#fiuwfi&ww3“l
lever B‘ufferubflwiqwubfiuolnu‘c‘li&uutbin«w&&uuttu¢&wofiu.-b&buwa&tbwflbnii&qn&»uwQlwwiiot&w&wuwhnv&at»&b»tvhwu»3wl

3.24
3.25
3.2.6

Transmitter Control Register.........ccoovviiiiiiiiiiiiiiiiicnsneseenn.
323
M@dem Statufl Regnst@r H»mbQ&%tfi%vufi*l‘fl&‘*#%‘vbfi*ia%fil&*&‘hihiflificw&hbfifi%n0*#0‘»*0&9000:&‘fibflim*t‘tvvtit3“7
Transmlt Data R¢313t¢r tu#wwwwwWwm»UHMmfl*it‘o#wwvbhwfll&#%&l%fiflun*»*»mniuéu»fi0&%&1%*&‘0»&&»'ni&#»a;w%hunut3“8

3.1

Llne Parameter chlster lufivm&vibuflfiwim&&-flkt«&‘clsnulflh%bbthq;thuiu#%dwttu.hqnttwfi&&tcwt&iinnu&uuwoiuauumaws
}

)

’

;

CONTENTS (Cont)

Page

CHAPTER 4

PROGRAMMING

4.1

SCOPELB R R R AR E RS SRRSRR R R RS] LAR A E R AR SR RS SRRSRR
R RS RS R R R R AR REERN SRR LA R R R EEREEEREREESN’ I AR R R RS RS R RN REER) LE R R R RN4“1

4.2

DEVICE ADDRESS ASSIGNMENTSOO".LE AR ERRE NSRSZERS
R R SRR AR EENEES

4.3

INTERRUPT VECTOR ADDRESS ASSIGNMENTS ..... et

4.4

PROGRAMMING FEATURES ...

LR LA
E R E RSN RSN0&4 1
senaaaa SRR

e 4-2

BaUd Rate LA AR R AR R R AR S R R R R R R R R R AR R R R R A R R R R A R R A R A R R A R R R R R A R
Character Length AR ES LR BB AR RSPIR REREDAERERERERR
BB BERERRERF R EB BRSNS R R R TN EN RN

44.1
4.4.2

R R R R S S 4“2
LBAR
R R R RN ESE] 4”2

444

Stop Blts.‘il.&"!h!l“il‘li’vWflh‘bil‘iikl‘*“***fl“004‘5“3'***“#&‘Wb*fib*‘******“fi*fibfifii%* ****** bfiliifiifl*ii.it&'.4‘3
Parlty (A XA AR E SRR R R SRSREENS] LB
A R EEE
N EE N EEBEER
SR EN (22
R AR ES RS R AR SRR
AR R EEEEE] LA R AR R RN AR E SRR EEER R RERES)] LA
R ERE
SR RS ‘Ui*fi4”3

4.4.5

InterruptSo(AR
E R E R E NN HEERE RN (2 AR R R R R SRR R SRR AR SRR R ENDN) L E A RS R NSRSREEEEERER
R EERENE] LA R R R R RS EE SN ERES] ‘0*‘0*.&'.4“3

4.4.3

Emptylng the Sllo SHEIRES R RSO NE S ERRERAES SN (A RS BN EE ) .Qlfl..l.‘y“*‘.flll'fi.‘I‘.“flfll‘ill“fl. UUUUUUUUUUUU fi.‘4m4
ERNERESEES. LE AR RSB EE SRR
S ERERSE] LAAR R N R R R AR AR R RS SRR RS R R R RS R REEREE] ‘41“4
Data Set Contr()l (I EAZEE RS R R RS R R AR R R SRR E R R AR SRR R R R R R R RSl R R R R R R R
R R RRE T R
004‘6

4.4.6

Transmlttlng a Character(I E AR R R R AR R SRR

4.4.7

448

FIGURES

Figure No.
DZV11-A (M7957 Module).................. ettt
e e et e e s baesenareeeas e URRRRTTIS
IS |
DZV11 System Apphcatlons fererereerseererrerernneeearuaronettasseesireaturasssiernranrarases ARSI P
DZV11-B (M7957 Module, H325 and H329) Connectors and Cable

Assembly BC]IU-25) eeeeueeeeereeera e ettt eaaraeretrn
eannnns 1-.

M795; ~ ector Sclectlon‘l' A

Iy
N
"""y LA R R R B AR EREE RSNER] (AR S A RN NN AEESEBEE N (A R RN ]
chlster Blt Asslgnmentsfl".dibdifi&".'.fifil&&"fili‘fifi!l'i".' ........ (LR R R R R R RS R S R R R R R R S R R R R R R R RN LA R R R Z
|

Test Connectors H325 and H329... e
ee e 1-

TABLES

Title

Table No.

Page

2-1
2-2

Items Supplied per Configuration.........cccccvivieeiiiiiiiiiiiieieir
e eeeaaees21
Jumpcr Canfiguratlon 0“*%‘0*‘."*‘0“*‘4&**‘*"60&'*001*"‘Q”fi"i“‘#*fl&fiiflifi#i'&lfi&*!'li‘fi'lt«&flfi llllllllll 0*02‘”2

2-3

Address SWltCh Selectlon (AR AR R AR R AR SR AR RS AR R AR A A R SRR R LR R R R AR R AR RS SRl RN ARRS fldii“**b*fii&wiw*w*#2“3

’

M‘

TABLES (CONT)

Title

Table No.
*

Page

2-4

Vector SWltCh Selectlon L A A AR AR RS AR R RS R R A R R R R A R R R A R R S R R R R R R R A R R R R R A RN nwu«o00\&0!‘*&#10:&»0muntn*thmm2‘4

3-1

DZV]- I ch]ster Address Asslgnments BERESEEREE SR EE RS R A REB SR I R EB BRI RSP ER RS RN RERN BB NSRS
NS W fi'1.03”1

3-2
3-3

CSR Blt ASSIKnments (R R AR R R RS AR RS R R R R R R R N R AR R R
R R
R R R R
R
R
‘1'3“3
RBUF Blt ASSlgnments RERTBAELELEREHERRBERET
R EBED BB R AN R T SRR RPRET RSB TR EERFEN DTN !GOWWW"W"WWW*W*“*VM‘W*""U3“5
»

3-4

LPR Blt Asslgnments R BEEFEOETERASE RN ERF T RDFEFRERF SRR AR E RSP FRERANEARRSE RSP ERENR SRR LA AR R AR RS EESRDE) VW“‘I.‘OU3“6

4-1

BaUd Rate Selectlfln Chart 00&"*Q’.““'UCOQQ.H‘&"U‘11!7‘"&"0&‘0fii#‘fl‘#‘ib‘"W*Ofl’#fiiififlllflflfltfifi/%lll’f"lflfiww.h4~2

CHAPTER 1
GENERAL DESCRIPTION

The DZV11, shown in Figure 1-1, is an asynchronous multiplexer that provides an interface between
an LSI-11 processor and four asynchronous serial data communication channels. It can be used with
the LSI-11 processor in a variety of applications that include data concentration, real time processing
and cluster controlling. The DZV11 provides an EIA RS232C interface and enough data set control to
permit dial-up (auto answer) operation with modems capable of full-duplex operation*, such as the

Bell models 103, 113, 212, or equivalent. Remote operation over private lines for full-duplex point to

point or full-duplex multipoint as a control (master) station is also possible. Figure 1-2 depicts several
of the possible applications for the DZVI11 in an LSI-11 system.

VECTOR SELECT
SWITCH E2

ADDRESS SELECT

Figure 1-1

DZV11-A (M7957 Module)

*The DZVI11 data set control does not support half-duplex operations or the secondary transmit and receive
operations available with some modems such as the Bell 202, etc.

1-1

LOCAL

REMOTE

| Wm&\/m“ _| pATA l
SET

l REMOTE

TERMINAL

<:> DZV11

_ __ _|

oaTa

SET

DzvV11

TELEPHONE

| LSI-1
|

! LINE

]

SYSTEM

2
o)

LSI-11

SYSTEM

|
MA.-0553

Figure 1-2

DZV11 System Applications

The DZV11 has several features that provide flexible control of parameters such as baud rate, character length, number of stop bits for each line, odd or even parity for each line, and transmitter-receiver
interrupts. Additional features include limited data set control, zero receiver baud rate, break generation and detection, silo buffering of received data, and line turnaround.
Program compatibility is maintained with the Unibus option DZ11-A. The only compatibility exception is the number of serial channels supported. The DZV11 does not support 20 mA operation.
1.2 PHYSICAL DESCRIPTION
The DZV11 comprises a single quad size module, 21.6 cm X 26.5 cm (8.51 inches X 10.44 inches), and
is designated as the M7957 module. All input and output leads are available on a Berg header. The
DZV11 connects to the LSI-11 QBUS by the H9270 mounting panel or equivalent. All QBUS input/output signals enter and leave the module via the mounting panel pins.

1-2

1.2.1 DZV11 Configurations
The DZV11 can be supplied in two configurations. The DZV11-A, as shown in Figure 1-1, consists of
the M7957 module only. Cabling assemblies for connection to terminals and modem channels are not
supplied with the DZV11-A, but are available in the DZV11-B. The DZV11-B consists of an M7957
module, BC11U-25 cable assembly, and two accessory test connectors, H329 and H325. This configuration is shown in Figure 1-3.

|__— M7957 MODULE

;CABLE ASSEMBLY

BC11U-25

\ TEST CONNECTOR H325

\TEST CONNECTOR H329

Figure 1-3

DZVI1i-B (M7957 Module, H325 and H329

Connectors and Cable Assembly BC11U-25)

1.2.2 BCI11U Interface Cable
The interfacing cable for terminal and modem connections to the DZV11-B is provided by the BC11U
cable assembly (see Figure 1-3). It consists of four separate cables, 762 cm (25 feet) in length, each
terminated by a separate EIA type connector housing and a common ng housing. Each cable within
the assembly provides nine input/output leads. The EIA connector pinning mmfmmfl to EIA standard
RS232C and CCITT* recommendation V.24. The leads supported by the DZV11-B are:
Circuit AA (CCITT 101)
Circuit AB (CCITT 102)
Circuit BA (CCITT 103)
Circuit BB (CCITT 104)
Circuit CD (CCITT 108.2)
Circuit CE (CCITT125)
Circuit CF (CCITT 109)

Pin 1
Pin 7
Pin
2
Pin 3
Pin 20
Pin 22
Pin 8

Protective Ground
Signal Ground
Transmitted Data
Received Data
Data Terminal Ready
Ring Indicator
Carrier

Signal ground and protective ground are connected
together.

*CCITT - the Consultive Committee International Telegraph and Telephone is an advisory committee established under the United Nations to recommend worldwide standards.

1-3

1.2.3 Test Connectors
Figure 1-4 shows the two accessory test connectors, H329 and H325, that are provided with each
DZV11-B. The H325 plugs into an EIA connector on the BC11U to loopback data and modem signals
onto a single line. The H329 plugs into the M7957 module socket housing and provides staggered
loopback of the data and modem lines. The loopback connections are shown in Figure 1-5.
1.3 SPECIFICATIONS
Environmental, electrical, and performance specifications for the DZV11
ing paragraphs.

are discussed in the follow-

1.3.1 Environmental
The DZV11 operates in an environment from 5°to 50° C(41°to 122° F) andin a relatwe humidity of
10% to 95%.
|
1.3.2 Electrical
Power Consumption
|

1.15A@ +5Vdc
039A@ +12Vdc

For each line the DZV11 provides a voltage level interface whose levels and connections conform to
EIA standard RS232C and CCITT recommendation V.24. The leads supported by the DZV11 are
listedin topic 1.2.2. Each DZV11 meets the LSlel QBUS Interface specification and represents one
unit load as an interface.
1.3.3 Performance
The following paragraphs describe the DZV11 performance capabilities and restrictions.
1.3.3.1 Maximum Configurations - The DZV11 multiplexer is assigned a device address in the floating address space. The floating address space starts at 760010 and extends to 764000. A maximum
configuration of DZV11s would not be limited by floating address space, but would be limited by the
rules governing an intermediate size system configuration. Therefore, a maximum of seven DZV11
multiplexers may reside in a nine by four backplane.

1.3.3.2 Throughput - Each DZV11 is capable of a throughput rate of 10,970 characters per second.
This rate is calculated as follows:

(Bits/Second X No. Lines X Direction) divided by Bits/Character.
(9600 X 4 X 2) 1/7 equals 10,970 Characters/Second.
For a character service routine of 100 us or less, the device throughput rate can be sustained.

- 1.3.3.3 Receivers - The receivers provide serial to parallel conversion of 5, 6, 7, 8 level code with one
start space and at least one stop mark. The character length, number of stop bits, parity generation and
operating speed are programmable parameters for each line. A receiver and transmitter of a corresponding line share the same operating speed with provisions for enabling/disabling of that receive
line.
Each receiver is double-buffered and has an allowable input distortion of 43.75% on any bit. Also, the
accumulated character distortion must not exceed 43.75%. Break detection is provided on each receiver.

Figure 1-4

Test Connectors

325 and H32

H329 STAGGERED TURNAROUND
® RECEIVE 1

TRANSMIT O
" DTRO

# RING 1

L——-‘ CARRIER 1

RING 0 ¥

CARRIER 0 -

DTR 1

RECEIVE 0 =%

TRANSMIT 1

NOTE:
LINES 283 ARE STAGGEMEQ IN THE SAME WAY.

H325 LOOPBACK CONNECTIONS

SCE

SCT

SCR —11

L ::]
SEC RCV

XMIT DATA

RCV DATA
,
REQ TO SEND

CLR TO SEND

Q
.

;

CARRIER —
NEW SYNC J'L——'T
|

DATA SET RDY

TM~

DTR =22
RING

JUMPER

REMOVED

Figure 1-5

Loopback Connections

1.3.3.4 Transmitters — The transmitters provide parallel to serial conversion of 5, 6, 7, 8 level code
with or without parity. The parity sense when selected can be either odd or even. The stop code can be

either 1 or 2 units except when 5 level code is selected. When $§ level code is selected, the stop code can
be set to 1 or 1.5 units. The character length, number of stop units, parity generation and sense, and
operating speed are programmable parameters for each line. The operating speed for the transmitter is
common with the receiver. Breaks are capable of being transmitted on any line. The gross start-stop
distortion for a transmitter’s TTL output will be less than 2.5% for an 8-bit character.
1.3.3.5 Baud Rate Generator — The baud rate generator is a MOS/LSI device which provides the
DZV11 multiplexer with full programmable capability for operating speed selection. Each line has an

independent generator capable of producing 1 of 15 selectable baud rates. Speed tolerance for all rates
is less than 0.3% with a clock duty of 50% + 5%. (See below for rates.)
1.3.3.6 Performance Summary - The following summarizes the programmable features offered for
each line:
|
Character length

5, 6, 7, or 8 level code

Number of stop bits

1 or 2 for 6, 7, 8 level code
1 or 1.5 for 5 level code

Parity

odd, even or none

Baud rates

50, 75, 110, 134.5, 150, 300, 600, 1200, 1800, 2000, 2400, 3600,
4800, 7200, and 9600

Breaks

Can be generated and detected on each line.

1.3.4 Interrupts
The following interrupts are available on DZV11.

Receiver Done Interrupt
Occurs every time a character appears at the output of the receiver buffer register and the Silo Alarm is
disabled. Can be enabled or disabled from the bus.
Silo Alarm Interrupt
Occurs after 16 entries have been made into the receive buffer register by the scanner. This interrupt
disables Receiver Done Interrupt and is rearmed when the receive buffer register has been read.
Transmit Interrupt
Occurs every time the scanner finds a UART buffer empty condition, and the transmitter control
register bit is set for that line. Can be enabled or disabled from the bus.

CHAPTER 2
INSTALLATION

2.1

SCOPE

This chapter contains the procedures for the unpacking, installation, and initial checkout of the
DZV11 Asynchronous Multiplexer.

2.2

UNPACKING AND INSPECTION
The DZV11 is packaged in accordance with commercial packaging practices. First, remove all packing
material and check the equipment against the shipping list. (Table 2-1 contains a list of supplied items
per configuration.) Report damage or shortages to the shipper immediately and notify the DIGITAL
representative. Inspect all parts and carefully inspect the module for cracks, loose components, and
separations in the etched paths.

2.3 INSTALLATION PROCEDURE
|
The following paragraphs describe the installation of the DZV11 option in an LSI-11 system.

231 J umper Configuration

There are 16 machine-insertable jumpers on the M7957 module. (See drawing D-UA-M7957-0-0 for

jumper locations.)

2.3.1.1 Device Operation - Jumpers W10 and W11 must be installed only when the module is used on
an H9270 backplane, or one that applies QBUS signals to the C and D sections of the module.

M7957 module
BC11U-25 cable assembly
H329 test connector
H325 test connector
Print set (B-TC-DZV11-0-1)
DZV11-A and -B
order number MP00462

R HEARX|

1
1

Description

>4 >4

Quantity

Items Supplied per Configuration

>4 K

Table 2-1

Software kit ZJ251-RB
DZV11 User’s Guide
(EK-DZV11-UG)

2.3.1.2 Modem Control Jumpers - There are eight jumpers which are used for additional modem
control support. The jumpers labeled W1 through W4 connect Data Terminal Ready to Request to
Send. This allows the DZV11 to assert both DTR and RTS if using a modem which requires control of
RTS. The remaining four jumpers, W5 through W8, provide connection of the Forced Busy function
to the Request to Send lead. Assertion of RTS places an ON or BUSY condition to the modems that
implement this function. This jumper should normally be cut out unless the modem has the Forced
Busy feature and the system software is implemented to control it. These jumpers must be installed for
diagnostic testing of the DZV11-B option. (See Table 2-2, Jumper Configuration.)

Table 2-2

Jumper

Connection

Wi
W2
w3
W4
W5
Wé
w7

DTR toRTS
DTR to RTS
DTR to RTS
DTR toRTS
RTS to FB
RTS to FB
RTSto FB

\\ 4

2.3.2

Jumper Configuration

Line
03
02
01
00
03
02
01

RTS to FB

Module Installation

To install the M7957 module, perform the following:

Refer to Paragraph 4.2 for descriptions of the address assignments. Set the switches at E30
so that the module will respond to its assigned address. When a switch is closed (ON), a
binary 1 is decoded. When a switch is open (OFF), a binary 0 is decoded. Note that the
switch labeled 1 corresponds to address bit 12, 2 corresponds to address bit 11, etc. (See
Figure 2-1 and Table 2-3.)

ADDRESS SELECTOR

A12

A11

A10

A09

A08

A07

A06

A05

A04

AO03

SWITCH

MA-0915

Figure 2-1

M7957 Address Selection

2-2

51 D1 51
L5 1

L~N

IS5
1 1 551 |
ol

I
=S R
ol

R
O

>4
4

D
N

B
R

A
R
N
(N N

>4 4

I S5
1 1 1 1

B
O
I

A
N
N
I
N

< >

>
3

I
R
A

A
R
R
T
I

NOTE:

> &

I
A
R
R
R
N

163760 | 163770

3
A10

Address Switch Selection

160000
160010
160020
160030
160040
160050
160060
16007
160100

>
> N

Powi

Address

> i

E30
Switch

Table 2-3

X = ON
- = OFF

Vector selection is accomplished by the 8-position switch at E2. Switch positions 7 and 8 are
not used. Switch position 6 corresponds to vector bit 3, 5 corresponds to vector bit 4, etc.
When a switch is closed (ON), a binary 1 is decoded. When a switch is open (OFF), a binary
0 is decoded. (See Figure 2-2 and Table 2-4.)

VECTOR SELECTOR
NOT

,
ON

OFF

vog

V07

V06

V05

V04

VO3

USED

SWITCH

NN
MA-0914

Figure 2-2

M7957 Vector Selection

NOTE:

L%
e
|

1 51

IS5
1 1
1|
<

< b

I 5555
1 111
P4 X

< W

FopQ X X X 8 6 KX X
< X

770

g D4 8 4 X X K X
»< X

I
L I

760

oS LI

300
310
320
330
340
350
360
370
400

P X

o -

E2
Switch
Vector

Vector Switch Selection

Table 2-4

X = ON
- = OFF

If the module is part of the DZV11-A option, perform step 3. If it is a part of the DZV11-B
option, proceed to step 4 for testing.
a.

Insert the module in a quad QBUS slot of the backplane.
CAUTION
Insert and remove modules slowly and carefully to
avoid snagging module components on the card
~ guides and changing switch settings inadvertently.

Run the DZV11 diagnostics, MAINDECs DVDZA and DVDZB, in internal mode to
verify operation. Refer to the listing for assistance. Run at least three passes without
error.

Proceed to step 8.

Insert the H329 test connector in J1 with the letter side facing up. J1 is the cable connector at
the top of the M7957 module.
Insert the module in a quad QBUS slot of the backplane.

CAUTION
Insert and remove modules slowly and carefully to
avoid snagging module components on the card
guides and changing switch settings inadvertently.
Run the DZV11 diagnostics, MAINDECs DVDZA and DVDZB, in the staggered mode to
verify module operation. Refer to the diagnostic listing for the correct procedure. Run at
least three passes without error.
2-4

Replace the H329 test connector with the Berg end of the BC11U cable assembly. Observe
the “This Side Up”’ wording on the assembly. Refer to D-UA-DZV11-0-0 for installation
help.
Connect the H325 test connector on the first line and run MAINDEC DVDZC. Select the
cable test portion of the diagnostic. Three passes are required without error. Repeat this step
for each line.
Run DEC/X11 systems exerciser to verify the absence of QBUS interference with other
system devices.

The DZV11 is now ready for connection to external equipment. If the connection is to a
local terminal through the DZV11-B option, a null modem cable assembly must be used.
Use the BCO3M or BCO3P null modem cables for connection between the BC11U and the
terminal. The H312-A null modem unit may also be used in place of the null modem cables.
If connection is to a Bell 103 or equivalent modem, install the appropriate line of the BC11U
connector into the connector on the modem. A BCO5D cable may be required between the
BC11U and the modem. Refer to Paragraph 2.3.1.2, Modem Control Jumpers, for selection
of jumpers for modem options such as RTS and Forced Busy. All of the cables mentioned,
excluding the BC11U, must be ordered separately as they are not components of a standard
DZV11 shipment. When possible, run the diagnostic DVDZC in echo test mode to verify the
cable connections and the terminal equipment.

CHAPTER 3
DEVICE REGISTERS

3.1

SCOPE

3.2

DEVICE REGISTERS

% | J

This chapter provides a description of each DZV11 register, its format, and bit functions.

The DZV11 contains six addressable registers. A comprehensive pictorial of these registers’ bit assignments is shown in Figure 3-1. Table 3-1 lists the registers and associated DZV11 addresses.

Table 3-1

DZV11 Register Address Assignments
~

Program

Mnemonic

Address

Capability

Control and Status Register
Receiver Buffer
Line Parameter Register
Transmitter Control Register
Modem Status Register
Transmit Data Register

CSR
RBUF
LPR
TCR
MSR
TDR

- 76XXX0
T6XXX2
T6XXX2
76X XX4
76XXX6
T6XXX6

Read/Write
Read Only
Write Only
Read/Write
Read Only
Write Only

"o,

XXX = Selected in accordance with floating device address scheme.

3.2.1 Control and Status Register
The control and status register (CSR) is a byte and word addressable register. All bits in the CSR are

cleared by an occurrence of BINIT or by setting device Master Clear (CSR 04). The format is shown in
Figure 3-1 and the bit assignments are listed in Table 3-2.

3.2.2

Receiver Buffer

The Receiver Buffer (RBUF) is a 16-bit read only register which contains the received character at the
output of the FI/FO buffer. A read of the register causes the character entry to be extracted from the
buffer and all other entries to bubble down to the lowest unoccupied location. Only the Valid Data bit
(RBUF 15) is cleared by BINIT or by setting device Master Clear (CSR 04). Bits 00-14 are not
affected. The bit assignments for the RBUF register are listed in Table 3-3.

MSB

HIGH g LOW

|Rw

| RO

fJo7z

|rRo

Jro

|Rw

|RwW

RIE

MSE

|RO

f“

orod
,

Jcontror

& STATUS
e

TRDY | TIE

lSAlSRL
@

SAE

TLINE | TLINE

——

(CSR)
RO

|RO

| RO

----- aa ARI

RECEIVER

| DATA

BUFFER

|OVRN|

”*&‘1

ERR

DR2

|¥ &

|Ro

Jro

R R

RBUF|

RBUF

|wo

lwo

| RX

|wo

T
T

S/Q|

lapONE|

FRAM | PAR

VALID|ERR | ERR

(RBUF)

N én? < Q"fl

B BRI
R
IS

B
S

p7 | o6 | ps | Da

p2 | b1 | Do

il
wo

LINE

PARAMETER

|/ &

(LPR)

TRANSMIT

| &/o|

|9/4 |

| R

| ENAB

oSS

DR4< | conTROL

S ,,.g-? S §

(TCR)

S é‘?
S

|CODE

|CODE |CODE

/LBRW _JRW _IRW

|[wo

|wo

2 | LINE | LINE

MODEM

fl-—m&

/& S/S

STATUS

DR6

1—:-—&

RO
|RO
|RO
|RO
. wowew sows s § uewme o sl owonw swmes waon m—— w—

JL | LS|

(MSR)
.
-

R
[ T

TRANSMIT | O/ST O/

DATA

WAY

u---&-

O/ T S0
&

(TDR)

|co

|wo

S-S

| BRK
3

[wo
WS

TRIIN

_RwW
§
/YL
_ /L RW__|RW_IRW_|RW__

'DTR | DTR | DTR | DTR |
3

Slal

&/ol

&/o|

/& | S é" < g‘,"

S ,g?

LINE

LINE | LINE | LINE

ENAB | ENAB | ENAB | ENAB
3

-u;&

| wo

| CODE

e°‘§

Jwo

|wo
TSS SR

|BRK

;&th—-;&

---&

» ofiows

AR
S/
/8
S
S
S
S

Jwo
VTSI

|[wo

JTBUF | TBUF
7

|wo

TS T

|TBUF
5

RO
sumee s s
RI 3

[wo

T ——— e

RO
|RO
| RO
e s g e W S W Sa S — s
Ri2

| RI1 |

wo
. S

|wo
S S

RIO

|wo
e S

waw S

0
MA-0552

Figure 3-1

3-2

Table 3-2
Bit

Title

00-02

Not used

Maintenance

CSR Bit Assignments

Function

This bit, when set, loops all the transmitter’s serial output leads
to the corresponding receiver’s serial input leads on a TTL
basis. While operating in maintenance mode, the EIA received
data leads are disabled. Normal operating mode is assumed
when this bit is cleared. This bit is read /write.

Master Clear

When written to a 1, generates “Initialize’’ within the DZV11. A
read back of the CSR with this bit set, indicates initialize in
progress within the device. This bit is self-clearing. All registers,
silos, and UARTS are cleared with the following exceptions:
1.

Only bit 15 of the receiver buffer register (VALID
DATA); the remaining bits 00-14 are not.

The high byte of the transmitter control register is not
cleared by Master Clear.

The modem status register is not cleared by Master
Clear.

Master Scan
Enable

This read /write bit must be set to permit the receiver and transmitter control sections to begin scanning. When cleared, Transmitter Ready (CSR 15) will be inhibited from setting and the
received character buffers (silos) will be cleared.

Receiver
Interrupt
Enable

This bit, when set, permits the setting of CSR 07 or CSR 13 to
generate a receiver interrupt request. This bit is read/ write.

Receiver Done

This is a read only bit that will set when a character appears at
the output of the FI/FO buffer. To operate in interrupt per
character mode, CSR 06 must be set and CSR 12 must be
cleared. With CSR 06 and CSR 12 cleared, character flag mode
would be indicated. Receiver Done will clear when the receiver
buffer register (RBUF) is read or when Master Scan Enable

(CSR 05) is cleared. If the FI/FO buffer contains an additional
character, the Receiver Done flag will stay cleared a minimum
of 1 us before presenting that character.

08-09

Transmitter Line
Number

10-11

Not used

These read only bits indicate the line number whose transmit
buffer requires servicing. These bits are valid only when Transmitter Ready (CSR 15) is set and will be cleared when Master
Scan Enable is cleared. Bit 08 is the least significant bit.

Table 3-2
Bit
12

CSR Bit Assignm

Title

Function

Silo Enable

This is a read /write bit, when set, enables the silo alarm counter
to keep count of the number of characters stored in the FI/FO
buffer. The counter will be cleared when the Silo Alarm Enable

Alarm

bit is cleared. Conditioning of this bit must occur prior to any
character reception.
13

Silo Alarm

This is a read only bit set by the hardware after 16 characters
have been entered into the FI/FO buffer. Silo Alarm will be
held cleared when Silo Alarm Enable (CSR 12) is cleared. This
bit will be reset by a read to the receiver buffer register and will
not set until 16 additional characters are entered into the buffer.
If Receiver Interrupt Enable (CSR 06) is set, the occurrence of
Silo Alarm will generate a receiver interrupt request. Reception
with CSR 06 cleared, permits flag mode operation of the Silo
Alarm bit.

Transmitter
Interrupt

This bit must be set for Transmitter Ready to generate an interrupt. It is read/write.

Enable

Transmitter
Ready

This bit is read only and is set by the hardware. This bit will set
when the transmitter clock stops on a line whose transmit buffer

may be loaded with another character and whose associated
TCR bit is set. The Transmitter Line Number, specified in CSR
08 and CSR 09, is only valid when Transmitter Ready is set.
Transmitter Ready will be cleared by any of the following
conditions:
1.

Master Scan Enable cleared.

When the associated TCR bit is cleared for the line

At the conclusion of the load instruction of the trans-

number pointed to in CSR 08 and CSR 09.

mit data register (low byte only).

If additional transmit lines require service, Transmitter Ready

will reappear within 1.4 us from the completion of the transmit
data register load instruction. The occurrence of Transmitter

Ready with Transmitter Interrupt Enable set, will generate a
transmitter interrupt request.

Table 3-3

Bit

00-07

RBUF Bit Assignm

Title

Function

Received

These bits contain the received character, right justified. The

Character

least significant bit is bit 00. Unused bits are 0. The parity bit is
not shown.

08-09

Received
Character
Line Number

10-11

Not used

Parity Error

This bit is set if the sense of the parity of the received character
does not agree with that designated for that line.

Framing Error

This bit is set if the received character did not have a stop bit
present at the proper time. This bit is usually interpreted as indicating the reception of a break.

Overrun Error

This bit is set if the received character was preceded by a character that was lost due to the inability of the receiver scanner to
service the UART receiver holding buffer on that line.

Valid Data

This bit, when set, indicates that the data presented in bits 00-14
is valid. This bit permits the use of a character handling program that takes characters from the FI/FO buffer until there
are no more available. Thisis done by reading this register and
checking bit 15 until the program obtains a word for which bit
15 is zero,

3.2.3

These bits contain the line number upon which the aforementioned character was received. Bit 08 is the least significant bit.

Line Parameter Regwter

The line parameter register (LPR) controls the operatmg parameters associated with each linein the
DZV11. The LPRis a word addressable, write only register. The line parameters for all lines must be
reloaded following an occurrence of either BINIT or device Master Clear. Table 3-4 lists bit assign-

ments.

3.2.4

Transmitter Control Register

The transmitter control register (TC R)is a byte and word addressable reglster The low byte of the
TCR register contains the transmitter control bits which must be set to initiate transmission on a line.
Each TCR bit position corresponds to a linenumber. For example, TCR bit 00 corresponds to line 00,
bit 01 to line 01, etc. Setting of a TCR bit causes the transmitter scanner clock to stop if the UART for
this line has a transmit buffer empty condition. An interrupt will then be generated if Transmitter
Interrupt Enableis set. The scanner clock will restart when either the transmit data register is loaded
with a character or the TCR bitis cleared for the line on which the clock has stopped. TCR bits must
only be cleared when the scanner is not running, (i.e., Transmitter Readyis set or Master Scan Enable
is cleared.)

The TCR bits are represented in bits 00~03. These bits are read/write and are cleared by BINIT or
device Master Clear. Bits 04-07 are unused and read as zero.

The high byte of the TCR register contains the writable modem control lead, data terminal ready
(DTR). Bit designations are as follows:
Bit
08
09
10
11
12-15

Name
DTR Line 00
DTR Line 01
DTR Line 02

DTR Line 03
Unused; read as zero

Assertion of a DTR bit puts an ON condition on the appropriate modem circuit for that line. DTR
bits are read /write and are cleared only by BINIT. Jumpers have been provided to allow the Request
to Send circuits to be asserted with Data Terminal Ready assertions.

Table 3-4

LPR Bit Assignments

Bit

Title

Function

00-01

Parameter Line
Number

These bits specify the line number for which the parameter information (bits 3-12) is to apply. Bit 00 is the least significant
bit.

Not used

Must always be written as a zero when specifying the parameter
line number. Writing this bit as a one will extend the parameter
line number field into nonexistent lines. Parameters for lines
00-03 will not be affected.

03-04

Character
Length

These bits are set to receive and transmit characters of the
length (excluding parity) as shown below.

——0
O

03
0
1
0
1

5 bit
6 bit
7 bit
8 bit

Stop Code

This bit sets the stop code length (0 = 1 unit stop, 1 = 2 unit
stop or 1.5 unit stop if a 5-level code is employed).

Parity Enable

If this bit is set, characters transmitted on the line have an appropriate parity bit affixed, and characters received on the line
have their parity checked.

Odd Parity

If this bit is set and bit 06 is set, characters of odd parity are
generated on the line and incoming characters are expected to
have odd parity. If this bit is not set, but bit 06 is set, characters
of even parity are generated on the line and incoming characters
are expected to have even parity. If bit 06 is not set, the setting
of this bit is immaterial.

3-6

Table 3-4

Bit

Title

‘

08-11

Speed Code
|

Receiver
Enable

13-15

Not used

LPR Bit Assignments (Cont)

Function

The state of these bits determine the operating speed for the
transmitter and receiver of the selected line.
11

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Baud Rate
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
Invalid

This bit must be set before the UART receiver logic can assemble characters from the serial input line. This bit will be
cleared following a BINIT or device Master Clear.

3.2.5 Modem Status Register
The modem status register (MSR) is a 16-bit read only register. A read to this register results in the
status of the readable modem control leads, Ring and Carrier. The ON condition of a modem control
lead is interpreted as a logical one. Bits 04-07 and 12-15 are unused and read as a zero. Remaining bit
designations are as follows:

)
.

Bit

Name

01
02
03
04-07
08
09
10
11
12-15

Ring Line 01
Ring Line 02
Ring Line 03
Unused; read as zero.
Carrier Line 00
Carrier Line 01
Carrier Line 02
Carrier Line 03
Unused; read as zero.

Ring Line 00

3-7

3.2.6 Transmit Data Register
The transmit data register (TDR) is a byte and word addressable, write only register. Characters for
transmission are loaded into the low byte. TDR bit 00 is the least significant bit. Loading of a
character should occur only when Transmitter Ready (CSR 15) is set. That character which is loaded
into this register is directed to the line defined in CSR bits 08 and 09. The high byte of the TDR is
designated as the break control register.

Each of the four multiplexer lines has a corresponding break bit for that line. TDR bit 08 represents
the break bit for line 00, TDR bit 09 for line 01, etc. TDR bits 12-15 are unused. Setting a break bit
will force that line’s output to space. This condition will remain until cleared by the program. This
register is cleared by BINIT or device Master Clear. The break control register can be utilized
regardless of the state of the device Maintenance bit (CSR 03).

CHAPTER 4
PROGRAMMING

4.1

SCOPE

This chapter contains information for programming the DZVI11 in the most efficient manner. To do
so, the programming controls must be fully understood. The following paragraphs discuss the DZV11
from the programming point of view and describe recommended programming methods.

4.2 DEVICE ADDRESS ASSIGNMENTS
The device address assigned to the DZV11 resides in the floating address space of the LSI-11. This
address space ranges from 160010z to 163776s. Each DZV11 requires increments of 105 address locations and the first option should be configured with an address of 160010s. The initial configured
address assumes that the system consists of only DZV11s in the floating address field. If the DUV11
option is also configured in the floating address field, assign the DZV11 an address which establishes a
gap of 10g address locations between the last DUVI11 and the first DZV11. For example: If the
system consisted of one DUV11 located at 160010, the DZV11 should be configured with an address
of 160030s.

4.3 INTERRUPT VECTOR ADDRESS ASSIGNMENTS
The DZV11 device vector address is selected from the floating vector space. This space ranges from
address 3005 to address 776s. Each DZV11 requires increments of 103 address locations for its two
contiguous interrupt vectors. If the DZV11 is the only option in the floating vector area, configure it
for a vector of 300s. If there are options other than the DZV11 residing in the floating vector area,

other configuration rules must be applied. When configuring the device vector, only the first vector
address must be considered. The first vector, or base vector, must start on a zero boundary.
A zero boundary is one which has the three least significant bits equal to zero. The second vector is
controlled by the first vector and data bit 02. Data bit 02 is generated by the M7957 hardwware.

Any option ahead of DZV11 in the floating vector space which is not in the configuration should not
occupy any vector space gap. For example, if only one DZV11 is in the system the vector for the
DZV11 should be 300. The simplest case is as follows:

Option

Address

Vector

Comment

GAP
GAP
GAP
GAP
GAP
GAP
GAP

160010
160020

No QBUS compatible DJ11
No QBUS compatible DH11
No QBUS compatible DQ11
NoDUV11
|
No QBUS compatible DUP11
No QBUS compatible LK 11
No QBUS compatible DMCI11

DZV11
GAP

300
-

No more DZV1ls

4-1

Each DZV11 requires two interrupt vectors, one for the transmitter section and one for the receiver
section. If simultaneous interrupt requests were generated from each section, the receiver section
would have priority in placing its vector onto the LSI bus. A receiver interrupt to address XXO0 will be

generated from having either a Receiver Done (CSR 07) or Silo Alarm (CSR 13) occurrence. A transmitter interrupt to address XX4 will be generated by Transmitter Ready (CSR 15). Additional prerequisites for generating interrupts are that the individual interrupt enable bits (CSR 06 and CSR 14) be
set. The recommended method of clearing interrupt enable bits is to first raise the processor status
word to level four, next clear these interrupt enable bits and then lower the processor status word to
zero. Using this method prevents false interrupts from being generated.

4.4 PROGRAMMING FEATURES
The DZV11 has several programming features that allow control of baud rate, character length, stop
bits, parity, and interrupts. This section dlscusses the application of these controls to achieve the
desired operating parameters.
4.4.1

Baud Rate

Selection of the desired transmission and reception speed is controlled by the conditions of bits 08-11
of the LPR. Table 4-1 depicts the required bit configuration for each operating speed. The baud rate
for each line is the same for both the transmitter and receiver. The receiver clock is turned on and off
by setting and clearing bit 12 in the LPR for the selected line.

Table 4-1 Baud Rate Selection Chart
11

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

Bits

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

Baud Rate

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
|

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
Not used

4.4.2 Character Length
The selection of one of the four available character lengths is controlled by bits 03 and 04 of the LPR.
The bit conditions for bits 04 and 03, respectively, are as follows: 00 (5-level), 01 (6-level), 10 (7level), and 11 (8-level). For character lengths of 5,6, and 7, the h1gh~0rder bits of the received character
are forced to zero.

The length of the stop bxtsin a serial character string is determined by bit 05 of the LPR. If bit 05 is a
zero, the stop length is one unit; bit 05 set to a one selects a 2-unit stop unless the 5-level character
length‘(bits 03 and 04 at zero) is selected, in which case the stop bit length is 1.5 units.
4.4.4 Pmty
The parity optwn is selected by bit 06 of the LPR. Parityis enabled on transmission and reception by
setting bit 06 to a one. Bit 07 of the LPR allows selection of even or odd parity, and bit 06 must be set
for bit 07 to be significant. The parity bit is generated and checked by hardware and does not appear in
the RBUF or TBUF. The parity error (bit 12, RBUF) flag is set when the received character has a
parity error.
4.4.5

Interrupts

The receiver interrupt enable (RIE) and silo alarm enable (SAE) bits in the CSR control the circumstances upon which the DZV11 receiver interrupts the LSI-11 processor.
If RIE and SAE are both clear, the DZV11 never interrupts the LSI-11 processor. In this case, the
program must periodically check for the availability of data in the silo and empty the silo when data is
present. If the program operates off a clock, it should check for characters in the silo at least as often as
the time it takes for the silo to fill, allowing a safety factor to cover processor response delays and time
to empty the silo. The RDONE bit in the CSR will set when a character is available in the silo. The
program can periodically check this bit with a TSTB or BIT instruction. When RDONE is set, the
program should empty the silo.

If RIE is set and SAE is clear, the DZV11 will interrupt the LSI-11 processor to the DZV11 receiver
vector address when RDONE is set, indicating the presence of a character at the bottom of the silo.
The interrupt service routine can obtain the character by performing a MOV instruction from the
RBUF. If the program then dismisses the interrupt, the DZV11 will interrupt when another character
is available (which may be immediately if additional characters were placed in the silo while the inter-

rupt was being serviced.) Alternatively, the interrupt service routine may respond to the interrupt by
emptying the silo before dismissing the interrupt.

If RIE and SAE are both set, the DZV11 will interrupt the LSI-11 processor to the DZV11 receiver
vector when the silo alarm (SA) bit in the CSR is set. The SA bit will be set when 16 characters have
been placed in the silo since the last time the program has accessed the RBUF. Accessing the RBUF
will clear the SA bit and the associated counter. The program should follow the procedure described in
Paragraph 4.4.6 to empty the silo completely in response to a silo alarm interrupt. This will ensure that
any characters placed in the silo while it is being emptied are processed by the program.
NOTE

If the program processes only 16 entries in response

to each silo alarm interrupt, characters coming in
while interrupts are being processed will build up
without being counted by the silo alarm circuit and
the silo may eventually overflow without the alarm
being issued.
|

4-3

If the silo alarm interruptis used, the program will not be interrupted if fewer than 16 characters are
received. In order to respond to short messages durmg periods of moderate activity, the LSI-11 program should periodically empty the silo. The scannmg period will depend on the required responsiveness to received characters. While the program is emptying the silo, it should ensure that DZV11
receiver interrupts are inhibited. This should be done by raising the LSI-11 processor priority. The silo
alarm interrupt feature can significantly reduce the LSI-11 processor overhead required by the DZV11
receiver by eliminating the need to enter and exit an interrupt service routine each time a characteris
received.
The transmitter interrupt enable (TIE) bit controls transmitter interrupts to the LSI-11 processor. If
enabled, the DZV11 will interrupt the LSI-11 processor at the DZV11 transmitter interrupt vector
when the transmitter ready (TRDY) bit in the CSR is set, indicating that the DZV11 is ready to accept
a character to be transmitted.
4.4.6 Emptying the Silo
The program can empty the silo by repeatedly performing MOV instructions from the RBUF to
temporary storage. Each MOV instruction will copy the bottom character in the silo so it will not be
lost and will clear out the bottom of the silo, allowing the next character to move down for access by a
subsequent MOY instruction. The program can determine when it has emptied the silo by testing the
data valid bit in each word moved out of the RBUF. A zero value indicates that the silo has been
emptied. The test can be performed conveniently by branching on the condition code following each
MOV instruction. The TST or BIT instruction must not access the RBUF because these instructions
will cause the next entry in the silo to move down without saving the current bottom character. Furthermore, following a MOV from the RBUF, the next character in the silo will not be available for at
least one us. Therefore, on fast CPUs, the program must use sufficient instructions or NOPs to ensure
that successive MOVs from the RBUF are separated by a minimum of one us. This will prevent a false
indication of an empty silo.
4.4.7 Transmitting a Character
The program controls the DZV11 transmitter thmugh four registers on the QBUS: the control and
status register (CSR), the line parameter register (LPR), the transmit control register (TCR), and the
transmit data register (TDR).

Following DZV11 initialization, the program must use the LPR to specify the speed and character
format for each line to be used and must set the master scan enable (MSE) bit in the CSR. The
program should set the transmitter interrupt enable (TIE) bit in the CSR if it wants the DZV11
transmitter to operate on a program interrupt basis.
The TCR is used to enable and disable transmission on each line. One bit in this register is associated
with each line. The program can set and clear bits by using MOV, MOVB, BIS, BISB, BIC, and BICB
instructions. (If word instructions are used, the line enable bits and the DTR bits are simultaneously
accessed.)

The DZV11 transmitter is controlled by a scanner which is constantly looking for an enabled line (line
enable bit set) which has an empty UART transmitter buffer. When the scanner finds such a line, it
loads the number of the line into the 2-bit transmit line number (TLINE) field of the CSR and sets the
TRDY bit, interrupting the LSI-11 processor if the TIE bit is set. The program can clear the TRDY bit
by moving a character for the indicated line into the TBUF or by clearing the line enable bit. Clearing
the TRDY bit frees the scanner to resume its search for lines needing service.

4-4

To initiate transmission on an idle line, the program should set the TCR bit for that line and wait for
the scanner to request service on the line, as indicated by the scanner loading the number of the line
into TLINE and setting TRDY. The program should then load the character to be transmitted into the
TBUF by using a MOVB instruction. If interrupts are to be used, a convenient way of starting up a line
is to set the TCR bit in the main program and let the normal transmitter interrupt routine load the
character into the TBUF.
NOTE
The scanner may find a different line needing service
before it finds the line being started up. This will occur if other lines request service before the scanne
can find the line being started. The program must
always check the TLINE field of the CSR when responding to TRDY to ensure it loads characters for
the correct line. Assuming the program services lines
as requested by the scanner, the scanner will eventually find the line being started. If several lines require
service, the scanner will request service in priority
order as determined by line number. Line 3 has the
highest priority and line 0 the lowest.

To continue transmission on a line, the program should load the next character to be transmitted into
the TBUF each time the scanner requests service for the line as indicated by TLINE and TRDY.

To terminate transmission on a line, the program loads the last character normally and waits for the
scanner to request an additional character for the line. The program clears the line enable bit at this
time instead of loading the TBUF.
The normal rest condition of the transmitted data lead for any line is the one state. The break bits are
used to apply a continuous zero signal to the line. One bit in the TDR is associated with each line. The
line will remain in this condition as long as the bit remains set. The program should use a MOVB
instruction to access the BRK bits. If the program continues to load characters for a line after setting
the break bit, transmitter operation will appear normal to the program despite the fact that no characters can be transmitted while the line is in the continuous zero sending state. The program may use this
facility for sending precisely timed zero signals by setting the break bit and using transmit ready
interrupts as a timer.

It should be remembered that each line in the DZV11 is double buffered. The program must not set the
- BRK bit too soon or the two data characters preceding the break may not be transmitted. The program must also ensure that the line returns to the one state at the end of the zero sending period before
transmitting any additional data characters. The following procedure will accomplish this. When the
scanner requests service the first time after the program has loaded the last data character, the program
should load an all-zero character. When the scanner requests service the second time, the program
should set the BRK bit for the line. At the end of the zero sending period, the program should load an
all-zero character to be transmitted. When the scanner requests service, indicating this character has
begun transmission, the program should clear the BRK bit and load the next data character.

4.4.8

Data Set Control

The program may sense the state of the carrier and ring indicator signals for each data set and may
control the state of the data terminal ready signal to each data set. The program uses two registers to
access the DZV11 data set control logic. There are no hardware interlocks between the data set control
logic and the receiver and transmitter logic. Any required coordination should be done under program
control.

The data terminal ready (DTR) bits in the TCR are read/write bits. Setting or clearing a bit in this

word or byte instructions. (If word instructions are used, the DTR and line enable bits will be simulta-

neously accessed.) The DTR bits are cleared by the INIT signal on the QBUS butis not cleared if the
program clears the DZV11 by setting the CLR bit of the CSR.
The carrier (CO) and ring (RI) bitsin the MSR are read-only bits. The program can determine the
current state of the carrier signal for a line by examining the appmpriate bit in the MSR. It can
determine the current state of the ring signal by exammmg the appmprxate bit of the ring register. The
program can examine these registers scparately by usmg MOYVB or BITB instructions or can examine
them as a single 16-bit register by using MOV or BIT instructions. The DZV11 data set control logic
does not interrupt the LSI-11 processor when a carrier or ring signal changes state. The program
should periodically sample these registers to determine the current status. Sampling at a high rate is
not necessary.

DZV11 ASYNCHRONOUS MULTIPLEXER

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USER’S GUIDE
EK-DZV11-UG-001

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