DZV11 Asynchronous Multiplexer User's Guide

Order Number: EK-DZV11-UG

This document is the User's Guide for the Digital Equipment Corporation (DEC) DZV11 Asynchronous Multiplexer, published in 1978.

Purpose: The DZV11 is a hardware module designed to provide an interface between an LSI-11 processor and up to four asynchronous serial data communication channels. It supports EIA RS232C standards and is capable of full-duplex operations with compatible modems (e.g., Bell 103, 113, 212 models).

Key Features & Capabilities:

  • Channel Control: Offers flexible control over parameters for each line, including programmable baud rates (from 50 to 9600 baud), character length (5, 6, 7, or 8 bits), number of stop bits, and odd/even/no parity.
  • Data Handling: Features double-buffered receivers with a 16-entry silo buffering for received data and provides break generation and detection capabilities.
  • Performance: Capable of a high throughput rate of 10,970 characters per second.
  • Interrupts: Supports Receiver Done, Silo Alarm, and Transmit interrupts to manage data flow and signal events to the LSI-11 processor.
  • Data Set Control: Provides limited data set control, including Data Terminal Ready (DTR) signal assertion and monitoring of Carrier and Ring Indicator signals.
  • Compatibility: Program-compatible with the Unibus option DZ11-A (with the exception of 20 mA operation).

Configurations:

  • DZV11-A: Includes only the M7957 module.
  • DZV11-B: Includes the M7957 module, a BC11U-25 cable assembly (four 25-foot cables), and two accessory test connectors (H325 and H329).

Installation & Programming: The guide provides detailed instructions for unpacking, inspecting, and installing the module, including setting jumper configurations for modem control and configuring device address and interrupt vector switches. It also describes the software interface through six addressable registers (Control and Status, Receiver Buffer, Line Parameters, Transmitter Control, Modem Status, and Transmit Data) that allow the LSI-11 processor to manage the multiplexer's operation, data transfer, and line signaling.

EK-DZV11-UG-001
February 1978
36 pages
Quality

Original
3.4MB
EK-DZV11-UG-002
2000
44 pages
Quality

Original
4.4MB
EK-DZV11-UG-002
August 1978
42 pages
Quality

Original
4.2MB

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