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EK-DZQ11-TM-001
2000
122 pages
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DZQ11 Asynchronous Multiplexer Technical Manual
Order Number:
EK-DZQ11-TM
Revision:
001
Pages:
122
Original Filename:
OCR Text
EK-DZQ11-TM-001 DZ@11 Asynchronous Multiplexer Technical Manual dlifgliltlall} e L e e | L s u o n o r h c n y s A 1 1 DZQ Multiplexer Techmcol Monuol S Pepard by Educ_»atlovnal Services | A ‘»Dgt|EqipmentC pratio = - First Edition, October 1984 Copyrlght © 1984 by Dlgltal Equ1pment Corporatlon " | All nghts Reserved | | | ” The 1nformat10nin thlS document1S subject to change w1thout notice. Digital Eqmpment Corporann assumes no respon51b1hty _ for any errors herein. | | o o _.Printedv in UK. ~ The fO”QWiDQ" are trademarkS'Of Di‘gital Equipment Corlp'oration;' egennen DEC | _DECmate» -~ DECUS DECwriter - DIBOL ' MASSBUS ~ o PDP - e"RT'~; P/OS UNIBUS Professional ~ Rainbow ~ RSTS RSX o VAX VMS VT Work Processor CONTENTS GENERAL DESCRIPTION "CHAPTER1 1 2 2.1 2.2 | £ U e ieT - ?'INTRODUCTION PHYSICAL DESCRIPTION .........c.ovieieiiuiniiiieieiiaan. 123 | DZQI11 Configurations ..........oviiiiiiiiiiann... TR £ SR Interface Cables .......... PR A TR Y ee .. 1-6 NS Test Connectors............. TP SPECIFICATIONS‘. T e e e e e T e e e e e G A e e L. 3.2 3.3 CElectrical L. e, Performance e . 2.3 3 Environmental ................ e e 3 3.1 ~ . 3.3.1 3.3.2 EESISENENENINESYCINE 3.4 4 5 W W LWL W W W CHAPTER 3 1 2 2.1 2.2 2.3 2.4 2.5 2.6 128 128 e 18 e e T L 18 _INSTALLATION CHAPTER 2 3.1 3.2 3.3 Interfaces .............. D OO - Maximum Configuratlons ....... e e 18 CTRIOUGNPUL .ot e - 1-9 Receivers ........ ... i, Ceaselade, e 159 Transmitters ........... B P P UPEIPIDRU B Baud-Rate Generator ............ooouviiun.... DU Performance Summary .......... ... e, 19 e Interrupts L R P A SR £ L 0 B | Receiver-Done Interrupt P e 1F10 . 12100 ‘Silo-Alarm Interrupt .........ooeviiiiiiii 1-10 e Transmlt Interrupt ....... e . .3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 3.4 3.4.1 3.4.2 3.4.3 1 2 3 £ 1-8 - e S e 24 SCOPE.-....-;'..............; .......e UNPACKING AND INSPECTION ... .ttt - 2-1 INSTALLATION PROCEDURE.... .' e e 222 ‘Modem Control JUMPETS . ...vvuuriniiiiiiiiiinnanninnneann.. 2:2° - Module Installation ................c i, e .24 Testing DZQI11sin PDP-11 Systems e L e e oo, 2-8 Testingin MicroVAX Systems . ........c.ovuriirrenneannn.. e "DEVICE ADDRESS ASSIGNMENTS ................. SR P - INTERRUPT VECTOR ADDRESS ASSIGNMENTS e 241 2-1 e 2] DEVICE REGISTERS - CSCOPE..o S E e 3 - DEVICE REGISTERS e e eR R eR Control and Status Register........... e S Receiver Buffer ......... e e e e e ey e . TS 15 S 34 Line Parameter Register .. .....vueorueieieaiaa e 35 . Transmitter Control Register ........... R Modem Status Register... ... e e SRt P R RTINSO S 3-8 FR - Transmit Data Register . SERRRE e e e e 3-8 CHAPTER 4 '»V'VPROGRAMMING TN NN NN — T »SCOPE...... RN N R e AR' N . 1 o .2 | PROGRAMMING FEATURES ..... i e e e eInterrupts e ee ee e e s e we N S . . e “Emptying the Silo ..........S IS ST S N PR 3 .4 Transmitting a Character ...........oovvieiineennenneneennee.. Data Set Control i e A PP ‘4-1, | S 4-] | = 43 - 2 SR NV NV RV RV NNV NV NV CHAPTER5 ,TECHNICAL DESCRIPTION e S 2 DR - SCOPE. P L SV S ST LRI E O L S 5-1 CIRCUIT FUNCTIONS.......... ST SRR S IS R RPN TP OB P 1. 3 3.1 Interface Slgnals. o T 3.2 3.2.1 RV RV RV RV RV RV XV XNV AV NV R, RNV RV RV ST ATV RN 322 3.2.3 324 3.2.5 3.2.6 3.2.7 3.2.8 4 4.1 4.2 4.2.1 4.2.6 43 4.3.1 432 44 S S.1 5.2 53 PR IR A R N SN .. 54 I/0 Control .. ... A SN AN sS O S A PP ... 56 - Input Operation. .........cooiieeiiiiinnienniieenie e 5T ~Output Operation ........oviieeeiineeeinneeinnneeenani. 5-8 ~ Vector Operation. . ... vvevvneue et. 59 - Initialize Circuit .......coviiiiiiiineeenneeennnnnnie. 5-10 Interrupt Logic. . ..o vivii i e 5410 Interrupt Transactions . .........uiieeee i - .5-12 LINE MULTIPLEXER..’.‘..'...4.."..-.‘ R L O S P ey e 5130 Hardware Description.. .. .. P N 13 ke UARTs and Control . ..... ... e 5413 Receiver Operatlon. e 4.2.2 4.2.3 4.24 425 P Circuit Operation............ L. .,'. N RS S o Io. 55 55 ... ... ~ BusInterface e eA RO ~ Receiver Control. . .. .. ittt S . “Transmitter Opera_tlon e e e ~ Transmitter Control .....................e Break (BRK) Bits ..o ~ Speed and Format Controle e £ 0 514 S 1T O-1T 519 | 52200 FIFO Buffer............ e i e e i e PR 5-21 FIFO Description. ... ..vvuii e i ie e, 521 ~ FIFOOperation...........oooiiiiiiiiiiiiiian... e 521 + Maintenance Mode .. ... ... i i e 5522 LINE INTERFACE . ... i e e - 5-23 DS CIIPION & ot e e e 5923 EIA RECEIVEIS ..ottt et e et EIA Transmitters. .............. e e, e i POWER SUPPLY. ... o\ oo 5223 5524 5224 . CHAPTERG -MAINTENANCE LW LI L) LI KD = ¥ L N 2 3 SCOPE.'......... e e e e e AR T ey s e PREVENTIVE MAINTENANCE................................... CORRECTIVE MAINTENANCE................................... 6-1 6-1 6-1 6-1 D ST .. ‘General ... Sl S Tools, Test Equxpment and Troubleshootmg Alds.'. P 58 DECX/II Exerc1ser Program...... e e e 622 Maintenance MOGES. . . o oo e e e e - 6-2 Setting Up Procedures................ SR PP ... 6-4 64 e Software Switch Register. e i Parameter Inputs and Dla]ogue e e 655 Functional DeSCTPON .. .. cvurerereeenarinanar e 6-7 © S e ... 6-10 Interprocessor Test (ITEP) ............... R A S I L 2 . T .. ........ ITEP ‘Starting | < 25 I Manua]Tests..................;...'...'........'. ...... R IRIIN Lo 6-18 | CORRECTIVE MAINTENANCE (MlcroVAX SYSTEMS). ..., The Macroverify Diagnostic ...... ..., ... 6-18 6218 ‘Setting-Up Procedures...........ooovvnenenn.. i e ... 6-19 e Bootstrapping Procedure REREe i Macroverify Operation.. ..........eeeieraeaeanenmn e s 6-19 'DZV11/DZQI11 Diagnostic EHXDZ. ...t . 6-20 62200 ee ~ Setting-Up Procedures. . ... et 6-20 S l O T - Bootstrapping Procedure ....... 6221 e Running EHXDZ.... ... S 6-22 ~ Starting-Up.............. 6-24 A P PO TR e R NP ~ Sections ......... S 4 622 - Error Messages........e 624 L. s e e e ey Test Sequence .................. e Lo N R RO RO R RO 1O =t = —_ oR N WU N N A AP ONOTNANAARARARNNANRANDRO s W~ P20 R2TRRTINTDLOOLL SN L 00 XXDP+ Dlagnostlc Programse 6-2 e . 6-2 ~ General.................; ..... ee APPENDIX A IC DESCRIPTIONS L GRGPE e Al A2 Ad - 3 A-1 ...... e AT ‘DC003 INTERRUPT IC DC004 PROTOCOL IC...... JRPNNe ADD A9 ...... T ST Ae DCO005 BUS TRANSCEIVERIC A-13 Coee... e e e DC367B SEMI-CUSTOM VLSI IC...... Description. . .. .. e POS S B A A P Lo A-13 TRSE SR il. PR TI Pin Layout..................BRSO ....oveiiiiiiaiiens ... A-16 ....... . ers * Specifications of Some Paramet ..‘.._..';._....‘..v..... - A-16 '.v...'.. .;..;..‘. - Baud-Rate Accuracy...‘....;, e e IR A-17 ST ...... ........ - Receiver Parameters SANE e ASDT AT Delay. Data and Read/Write Pulses = ACTT e R ...... Y 3341 FIFO SERIAL MEMOR APPENDIX B GLOSSARY OF TERMS | B.1 B2 SCOPE ............ B-1 GLOSSARY......... L e e RS Bl " s o | . 'Page._ ~ M3106 Module i e o A DZQII System Appllcatlons e e ~ A i e e e e e [} .»'o_ [} o_vo e & o _‘:. ', ...... M L T ) Elements of the DZQI11 Option ....................... ooo-oo‘ooo ooooooooooo ~ Test Connectors H325 and H329 ..................... ~ Loopback Connection ............. e e - Jumper Location on M3106 Modulee e ooooooooooooooooooooooo e« 5 ee e e e ¢ s 8 6 8 s 8 8 .8 ne DZQI11 Installation (BC11U-25)............. e ‘e ., e v o 0 s s e e e 0 e . DZQI11 Installation (70-19964-OO)EEEPRRRRE i s eatd s ‘Register Bit A551gnment NS PN G RS e S ~ Labeling Conventions. . . ... .T - Simplified Functional Block Dlagram. N aaaaaaaaaaaaaaaaaaaaa ! I RN - f- --o}ooa».-uoo.ol>.. P B to o : Tifle FIGURES -loooot-c.'oc‘.oo- ,,,, e TR S PR BT SRS .Cl.'l..l...v. I L 1 - DZQI11/Q-bus Interface........... aae i i ee i e e e | ~DataInput Timing..ot Data Output Timing. . .............. R ~ Initialization Signals...................... ... . . ..., CInterrupt Logic ..o e e i | "','.' R ® I s R s R s e R s S s e .... S s N e o ERR ------------------ | FERE SE e v s 4 o @ i s e s s s u. ! ooooooooooooooooooooo ! ooooooooooooooooooooooo ! - - Interrupt Timing . ................. R R | - 8 R | Receiver Control Timing Diagram ...... o ----------------- e e e s ee M e e s P ®. e Transmitter Control Block Diagram .................... - ~ Transmitter Control Timing Dlagram. B FIFO Output Timing...............S EIA Recelvers. I T e S R AR 8 s 0 s 2w 8 o 8 e ¢ & & LR N L e L e R -.‘.'......, ......... l‘. o6 e 6 ." * e e ¢ s e 8.0 8 o s v.s & 2 s s s @« s o @ -------------------- Maintenance Mode Data Flov_» SRR R A SN Interprocessor Test (ITEP).............. S 1 > >S > > > 8 oooooooooooooooooo SO N 1 ! Receiver Control Block Dlagram. e DZQ11 Test Configurations. e - S S e PN S U A e e ® e s 8 s e 2 e eln s s e . ----------------- T - - - DCO003 A Section Timing ...................... PR DCO003 A and B Section Timing ............ W e » e el e | e e e DCO004 Simplified Logic Dlagram e L W e e R e e ~ DCO004 Timing Diagram ..........cuuuiiiiinnn. .. P T R A - DCO005 Simplified Logic Dlagrame e e e i o _ .DCO005 Timing Diagram ............ e s e e e e e e - PinLayoutof the DC367B .........c.oooiiiiiiiiininan., SR *-3341 FIFO Serial Memory e L T Sl e e TABLES ! WU BN NYOVH S REo N o 'Tltle | | LN R I R R T A T A M oooooooooooooooooo | ~ ! ] ~ --------------- Vector Switch Selection ....................... S - Floating Address Assignments .......................e One DUVII and One DZQI] S K L EDRP SRR ---------------- ‘oo-n'...ococuicu ~ ------------------- ‘ _TwoDZQlls SRR EOC O e e e Ee I IEN e Items Supplled per Configuratxon O A Jumper Configuration...................c......... ey e Break Character Response Options.................. UL Address Switch Selection ........ R POPU ooooooooooooooooo I SRR | DCO03 Logic Symbol........ ... VI ................ 1 ! 1 EE T c':\oxoxoxoxoxu:mUu.uumurw'w'w,wwm CAURWN—= 1O UNRARWN— /KW —=O Flrst Part of Q-bus Vector Address Ass:gnmentsL]St Lo SR ~ DZQI1 Register Address Assignments ..............DA oo 2-13 31 ...... P 33 CSR Bit Assignments ........... IR .35 i P - RBUF Bit Assignments ................ 35 e e e s .................. LPR Bit Assignments 'DZQ11/Q-bus Interface Slgnals e e 54 - Register Selection............ e e ey e s e i e L ... AP PSP ~ Transceiver Switching ..................T Byte Selection (Output Operation Only) .......... PP S ~ DC367B Receiver Control Signals................. L e e - DC367B Transmitter Control Signals .................. e R .. - Modem Control and Status Slgnals. e e e e 56 £ DL 5-14 5-17 5230 Diagnostic Programs ............. e e [P IPRRPRRE o B - Multimedia ASSIgNMENtS. ... \'iieetiiiiienae e, 0-2 - Typical Map of DZQI1 Status.........e T e ee 6-5 CVDZA TeStS. vttt .. 628 e L. e e i e e CVDZB Tests............ e Valid Mode Combmat:ons e e e DCO03 Signals . ....oviiiee e . ~ DCO004 Pin/Signal Descrlptlons ..... i - DCO0O0S5 Pin/Signal Descriptions .............. ST AT S S . - DC367B Pin/Signal Descriptions . ............ I SR S SR PR - Baud Rate Accuracy ............... e e 69 6411 A4 ASB A9 A-14 T SH CA-16 CHAPTER1 ~ GENERAL DESCRIPTION i 1 INTRODUCTION o | | | | | R | The DZQ11 is a Q-bus option. Its outhne is shown in Flgure 1-1. The DZQll is an asynchronous | multiplexerthat interfaces between a Q-bus processor.and four asynchronous serial data communication lines. It can be usedin many applications such as data concentration, real-time processing, and cluster ~controlling. The DZQll communications interfacesare compatiblewith RS-232-C (V.28) and RS-423-A o (V.10/X. 26) Thereis enough modem control to permit dial-up (auto-answer) operation with full-duplex “modems* such asthe Bell models 103,113,212, or equivalent. Remote full-duplex working, as acontrol ~ (master) station over private lines, is also possrble for point-to-point or multtpomt operatron Frgure 1-2 | ,shows some poss1ble apphcatlons for the DZQll in a Q-bus system. o | | | All the DZQll parameters can be easrl) controlled These parameters are: ~ Baud rate Character length | Number of stop bits for each lme or even parity for each line 'Odd ~ Transmitter receiver interrupts. " Additional features include: Limited modem control Zero receiver baud rate Break generation and detection ~ Silo buffering of recerved data - Lme tumaround B The DZQl 1 is programcompatrble with the Q-bus DZVI 1 and with the UNIBUS option DZ11-A. The ~ only exceptlon is the number of serlal lmes supported The DZQl 1 does not support 20 mA operatlon | ) Documents describing the DZQ11 are: e e o o DZQll Asynchronous Multiplexer User's Guide- EK- DZQllUG DZQI11 Asynchronous Multiplexer Technical Manual EK DZQllTM Field Maintenance Printset- MPO1795 DZQll Mamtenance Card EK DZQll MC | S | '*> "The DZQ11 modem control does not support half- duplcx opcratron or tht suond ary transmit- md receive | - operatron avaxlable on some modems (such as the Bell 202). J1 - f ADDRESS‘ v' ~ - SWITCH-PACK E28 " VECTOR SWITCH-PACK | ~ Figure I-1 M3106 Module B R CHAPTER 1 | GENERAL DESCRIPTION. 1 INTRODUCT]ON The DZQ11 is a Q-bus option. Its outllne is shown in Flgure 1-1. The DZQll is an asynchronous : multiplexer that interfaces between a Q-bus processorand four asynchronous serial data communication ~lines. It can be usedin many applications such as data concentration, real-time processing, and cluster _controlling. The DZQI 1 communications interfacesare compatiblewith RS-232-C ( V.28) and RS-423-A (V.10/X. 26) Thereis enough modem control to permit dial-up (auto-answer) operation with full-duplex ~ modems* such as the Bell models 103, 113, 212, or equivalent. Remote full-duplex working, as acontrol - (master) station over private lines, is also possrble for point-to-point or mu1t1p01nt operatton F1gure 1-2 shows some possrble apphcatlons for the DZQll in a Q-bus system | 'All the DZQll parameters can be easrl) controlled These parameters are: 'Baud rate e Character length Number of stop bits for each lme Odd or even parlty for each line Transmrtter receiver 1nterrupts .Addltronal features 1nclude | erlted modem control Zero receiver baud rate | Break generation and detection ~ Silo buffering of received data Line tumaround -. N The DZQ] l is programcompatrble wrth the Q-bus DZVl 1 and mth the UNIBUS optron DZl 1-A. The ~ only exceptron is the number of serial lmes supported The DZQI 1 does not support 20 mA operatlon | N Documents describing the DZQl 1 are: | DZQll Asynchronous Multrplexer User's Guide- EK- DZQllUG - 'DZQ11 Asynchronous Multiplexer Technical Manual - EK DZQllTM Field Maintenance Printset- MPO1795 .' DZQll Mamtenance Card EK DZQllMC | The DZQ11 modem control does not support half- duplcx operatton or th sttond ary trmsmu and-receive | - operatron avallable on some modems (such as the Bell 707) | - ~ ADDRESS T E28 . VECTOR | SWITCH-PACK . 'qu TRQ - . . 12 | PHYSICAL DESCRIPTION The DZQ] 1 is made up of two components connected by a rlbbon cab]e The components are: 1. A smgle dual- helght module, 21 6 X 132 cm(8 51 X 5 19 mches) ca]led the M3106 module. All input and output connections are available on a Berg * header. ThlS module mcludes all | SRR - actlve c1rcu1try as well as the lme drxvers and receivers. - 2. Adlstnbutlon pane] 6. 7 >< 8.5 cm (2. 6 X 3.3in) whxch contams four filtered D-type connectors | anda Berg header. This header connects to the M3 106 bymeans of a 40-way rlbbon connector L - NOTE A G7272 Grant Contmulty card may be needed e Refer to Sectlon 2. 3 2 for an explanatlon . REMOTE ~ | Ltoca | . TELEPHONE ' LINE — sev | o o - SET - o = l : L e LOCAL | TERM. . - DzQ1Y | <3 . | | oata |l | . - SRR o N T | | e ; o SET ] |2i S ! TeELepHONE | l .,|‘ =~ <E—®1 | | TERMINAL . | | < DzQ11 , - w = [o2] c | Figure 1-2 DZQIl 1 System Applications * Berg'iS' a r_egiStere_d trademark of the Berg Corporation. | REMOTE e L ‘l_UNE‘ - . ' IR ____ _|oata | seT - LSI-11 SYSTEM | | DATA | 3 DATA RIS o SYSTEM A | DZQll Conf’guratlons R | l 21 | “The basxc optlon supplledis the DZQll M andis made up of the followmg 1. Loglc Module | 2 ‘User’s Guide = M3106 S T EK-DZQllUG S T 4 Tumaround test connector H329 Mamtenance Card EK—DZQll MC e e e L e B el e | .The basrc optlon (DZQI 1-M) can be supphed W1th one of five cablnet kxts for 1nstallatlon into dlfferent SIS »systems These are: IECES RIS ;- CKDZQllDA (21 lnch cable) example of use—PDP—l 1/23S . CK-DZQI11-DB (12-inch cable), example of use — Micro/PDP-11 - CK-DZQ11-DC (30-inch cable), example of use - PDP-11/23+ - CK-DZQ11-DF (36-inch cable), example of use - PDP-11/83 CKDZQllD3 unshlelded optlon (BCl 1U- 25 cable) The first four cabinet kltS are almost 1dentlcal except for the length of the flat I'lbeI'l cables and the - e } 'addltlon of an adapter plate1n the CK-DZQll -DC. They are made up of the followmg 1. BCOS L—xx cable (see NOTE) | 2. HB325 line-loopback connector 3. The distribution panel— 70-19964-00| 4 Mou/ntmg bolts and washers for the dlstrlbutlon panel e A system mtegrated DZQll optlon is a DZQll DP : | | NOTE The distribution panels | provide ‘noise filtering - ~and static discharge protectmn on the communi~ ~ cations lines. The -DC version has an adapter | plate which allows the panel to be mountedin the - PDP- ll/23+ | - | - | BCOSL—xx cables are supplnedin dlfferent lengths * - for each kit as prevnously specnf‘ ed. o The CK DZQll D3 cabmet kitis a cable assembly made up of four cables w1th D—type connectors at ~one end, and the other end connected to a socket which fitsin the module connector. This klt does not_ ~ prowde n01se filtermg or static dlscharge protectlon on the commumcatlons 11nes - ~ ~ S — PANEL DISTRIBUT4-ION 00) (70-1996 M3‘106 MODULE —3 A TEST CONNECTOR H325 TEST CONNECTOR H329 of the DZQ11 Option | ' Figure 1-3 Elements 1 2. 2 Interface Cables R ST B N S:gnal ground and protectlve ground are connectedv L e e ( The connections from the DZQI1use 25pm male submmlature D—type connectors as specrfied for RS-- o ;Crrcult AA (CCITT“‘ 101) Pin ‘1” PR *'*.Prote"ct__ive Ground ~ Circuit AB (CCITT 102) Pin 7 Signal Ground - Circuit BA (CCITT 103) Pin2 Transmitted Data Circuit BB(CCITT 104) Pin3 B Received Data = ~ Circuit CD (CCITT 108.2) Pm 20 = Data Terminal Ready Circuit CE (CCITT 125) Pin22 Ring Indicator | C1rcu1t CF (CCITT 109) Pin 8 Carrler NOTE - together, through the chassis, by jumper Wl on the 70-19964- 00 dlstrlbutlon panel 3 | o ( g l 2.3 Test Connectors o '» Flgure 1-4 shows the two accessory test connectors H329 and H325 o o The H329 plugs mto the module I/ O connector and connects hne O to hne l and l1ne 2 to lme The H325 plugs 1nto an. EIA connector on the dlstrxbutlon panel or BCllU 25 cable assembly, to o 'loopback data and modem 51gnals over a smgle line. The loopback connectlons are shownin Figure 1 5 ( | ) . "H325,.T ‘T_g; ,TA",'? ’~-Q_T ‘VT,H329 l ’Rorssw o Flgure 1’.‘_4 Test,_Connectors H325 vand‘H_329- : CCITT The Internatlonal Consultatrve Commlttee for Telegraphy and Telephonyxs an ad\isory commlttee created under the Umted Natlons to recommend worldw1de standards o H329 STAGGERED TURNAROUND TRANSMITO SRR, >RECEIVE1 1 ——RING DTR,O»_Q'_ L—» CARRIER1 ': - RlNG 0 @—— . 'CARRIERO &————— 7*RECENEO< e DTR1 ‘TRANSMIT1 = NOTE: LINE 2&3 ARE STAGGERED lN THE SAME WAY H325 LOOPBACK’CON_NE-CTIO’NS | SCE - 04 " scr ' GEC XMIT —————» SECRCV —=— XMITDATA - RCV DATA & - TO SEND "~CLR CARRIER NEW SYNC ——— DATASETRDY &——L BT . pTR RING ~ o W1 JUMPER MAY BE REMOVED OR =>—————0 INSERTED — | Figure I-5 LQOPbEICk COnnection - 17 | 13 SPECIFICATIONS o Environmental. electrrcal and performance specrficatrons for the DZQll are lrsted in the followmg ~* paragraphs. 1. 3 1 Enviro-nmental " S ;l Storage temperature - | -0 degrees Cto 66 degrees C- e j.»(32 degrees F to 151 degrees F) ; _,'Opera»ting‘ temperature - -5 degrees C to 60 degrees C o e I (41 degrees F to 140 degrees F) Relative humidity' i ._"'10%to 95% non—condensmg 1‘;3.!2-7"Elec_t’rical'- | o Péwer‘-consumptmn 1100 Aat+5Vde typlcal G T ’Q"bUSi’lO‘ading LI et e 0236Aat+12Vdctyp1cal i ~ Q-bus ac loads - 15acloads e Q- US"dC,IOads 71.0 dc loads | o | ‘_.l 3 3 Performance | ’_ '_The fOHOng par agraphs descrrbe the DZQll performance capabtlltres and restrrctrons o .fl 3.3.1 Interfaces oThe DZQll mterfaces wrth the host computer bus and also w1th the four data o ,-commumcatron lines. 1. | System Bus Interface The DZQ] 1 module mterfaces drrectly to a Q22 or other Qbus via connectors A and B. The» | e Vmodule meets the DIGITAL Q- bus spec1ficatron 2 | 'Serral Interfaces | The DZQ] ] serral mterfaces comply with a subset ofEIA/CCITT standards RS 232 C/V 74 The electrical characteristics are compatlble wrth EIA/CCITT standards RS232 C/V 28 and g S 423/V lO (unbalanced mterface) | 1.3. 3 2 Maxnmum Configuratrons — The DZQll multlplexer is a551gned a devrce address in the | - floating address space. The floating address space starts at 760010g and extends to 763776g. Maximum ..configuratron of DZQ11s is not limited by floatmg address space but1S 11m1ted by the rules controllmg a | vsystem configurauon of average size. | e | | I "As the DZQll needs one backplane AB slotparr it is physrcally possrble to mount: ©« Two M3106 modules in aPDP 11/23.S e . Three M3106 modulesin a Micro/PDP- 11 Four to five M3106 modules in a PDP ll/23+ ) 'These numbers are the absolute maximum, because of the hmlted number of 70- 19964 00 drstrrbutron - panels that can be installedin the rear panel of the mounting box. These numbers may also be hmrted by e ’"the av arlable capacrty of the power supply if other optrons are 1nstalledin the mountmg box 3 | ( »1.3.3. 3 Throughput- Each DZQll is capable of a throughput of lO 970 characters per second (chars/ s). Thrs rate is computed as follows , (BltS/ S >< number of lmes X dlrectlons) d1v1ded by blts/char (9 600 >< 4 X 2)/7 equals 10 970 chars/ S, atd b1ts/ char thh one start and one stop b1t and no panty " The full dev1ce throughput can only be mamtamed when a character servxce routme takes lOO | '_ ‘_mlcroseconds or less The DZQl l hasa max1mum non—standard data rate of 1 9 800 baud. At thls rate the throughputis 22 625 - characters per second. | 1 3.34 Recelvers— The receivers perform serial- to-parallel conversion of 5-, 6-, 7-, or 8 level code ~ withone start bit and at least one stop bit. The character length, number of stop b1ts parlty generation, and operating speed are programmable parameters for each line. Both the receiver and the transmitter of .a correspondmg line share the same operatmg speed and thereceiver line can be enabled or dlsabled Each receiver is double buffered and has an acceptable mput dlStOI‘thI‘l of 43. 75% on any bit. The sum of ~ the character distortion must also not exceed 43.75%. An exception to thisis the stop bit. The stop bit can tolerate an error of 50%, thatis, the receiver will accept a stop bit as short as one half of a bit perlod Break - | - detectionis provided on eachreceiver via aregister bit. In addition, the configuration of switchpack El 3-9 and E13-10 can cause the processor to boot or halt when a b_reakis detected on line 3. 1.3.3.5 Transmttters — The transmitters provide parallel to-serial conversion of 5» 6-. 7- or ' 8-level code with or without parity. The parity sense, when selected, can be either odd or even. The stop code can - beeither 1 or 2 units except when S-level codeis selected. When 5 level codeis selected. the stop code can be set to 1 or 1.5 units. The character length, number of stop units, parity generation and sense. and operating speed are programmable parameters for each line. Thebperating speed for the transmitter is ‘common with the receiver: Breaks can be transmitted on any line. The maximum start-stop dlstomon for the output of a transmltter is less than 2 5% for an 8-bit character. o 13. 3 6 Baud- Rate Generator - The baud-rate generators are completely programmable Each line“has an independent generator which can select 1 of 16 baud rates. Speed tolerance for all rates is better than O 3% The baud rates are shown in Sectlon I. 3 3.7. 1.3.3. 7 each line. Performance Summary - The followmg ]lS'[ shows the programmable features offered for | 3 Character length | 5-. :6-. 7;"@- 85'level code' | - Number of stop bits | - 1 or2 for 6-. 7-, or 8-level code. R ]l orl.5 for 5-level code Parity - ‘_ o Baud vrates - ._ Breaks 'Odd even, or none o . . - 50, 75. llO 1145 150 200 600 1 700 1 800. 7000 2 400 3 bOO 4 800. 7 200, and 9 600 (and non- standard 19 800) . Can be generated and detected on-each lme Line 3 has a hard\xare response to detected breaks w lml when enabled. may generate a HALT or RESET Tlnx taulm can be selected by swnches 5 1.9 | 1.3.4 Interrupts B | .v,;jr’gThe followmg mterrupts are avallable on the DZQll B | 3 4.1 Recelver-Done Interrupt— The recelver-done mterrupt occurs every tlme a character - appears at the output of the receiver buffer register and the 5110 alarmis dlsabled The recelver-done "..~«1nterrupt can be enabled or dlsabled from the bus. . l 3 4. 2 Sllc-Alarm lnterrupt - The sxlo—alarm mterrupt occurs after 16 entries have been made mto_ i '_ ~ the receive buffer reglster bythe scanner. This interrupt dlsables the recelver-done mterrupt and is armed.agam when the receive buffer reglster has been read | 1 3.43 Transmlt Interrupt~ The transmlt mterrupt occurs every tlme the scanner finds a buffer— | ~ empty condition, and the transmltter control reglster blt1s set for that 11ne It can be enabled '- from the bus kR | 1410 | | o or dlsabled . R . CHAPTER 2., - INSTALLATION '2 1 SCOPE | | | ' | | This chapter contains the procedures for the unpacklng, 1nsta11atxon and m1t1a1 checkout of the DZQI 1 | asynchronous multlplexer It contams mformatlon on the following: o e e o | | | Dev1ce and vector address selectron Recommended cables Testing after 1nstallatron F loatrng address and vector ass1gnment 2.2 UNPACKING AND INSPECTION | - S - The DZQI1 is packed following normal commercra] packmg practlces To unpack first removeall - packing material and check the equipment against the shipping list. (Table 2-1 contains a list of supplied items per configuration.) Report any damage or shortagesto the shipper immediately and inform the local | DIGITAL office. Examine all parts and carefully examine the module for damage loose components and breaksin the etched paths . , | | S CAUTION The M3106is supphedin a protectlve sleeve. Do o not remove the sleeve until you are abouttoinstall the module. Protect the module from statlc durmg o mstallatlon | | B WARNING = ~ | .._Procedures which _.call‘ for the ‘removal of the - N system covers should be performed by trained personnel only. Information on such procedures s mcluded for user mformatlon only Table 2 l Items Suppldied per Configuratio'h' A DZQllM Base Optlon | | | '_v-.Descnptlon | f L ~ : Sl s H329 test connector | - DZQIl1 Users Gurde (EKDZQllUG) T < | | S -'Quantity.' L e s . CK- DZQllDA/DB/DC/D3/DF Cabmet kits ; -. A, 74- 28684Ol adapter plate " e BCOSL—IK 1.mch » ) BCOSL-01 | 12-inch Cable - _» cable © Ciai e . BCOSL-03 36-inch cable L R '-H325 test connector ; e 90-06633-00screws 90 06021 01 washers | | B - _ '_' 1' . _»_., s -—,‘ _ : e 1 11 o _ 1 '.:,1' B 1 SRR 4 O 4 g _ — - 23 INSTALLATION PROCEDURE - _ _ S T e A __ 1 '_ _ o i LI _ , 1 1 | ?».__A __ 14 : . o -~"BC.11U-25 ‘cvable'assembly SR . _ ‘A BCOSL2F30-inch e o 1 o . Quantnty ‘ e 10- 19964 00 dlstrlbutlon pane] , e I -1 e 4 s - The followmg paragraphs descrlbe the mstallatmn of the DZQll optron in a Qbus system —'2 3 1 Modem Control Jumpers , ,' R o - | There are eight jumpers used for modem contr01 (Figure 2-1 ). ThejJumperslabelled W1 to W4 connect the o ~ Data Terminal Ready (DTR) circuit to the Request To Send (RTS) circuit. This allows the DZQI11 to assertboth DTR and RTS when using modems that need control of RTS. Thesejumpers must be installed - for running the cable and external dxagnostlc programs The four jumpers W5 to W8 connect the Forced - " ~ Busy (FB) circuits to the RTS circuits. When these jjumpers are installed, asserting an RTS circuit also places an ON or BUSY level on the corresponding FB circuit. J umpers W5 to W8 are normally cut out _unless the} are needed b) the modems used Table 2-2 shows theJumper line a551gnments | | “aF : | T S SR I Y1 ATAL T | b S _ gayp RATE 12222 W12 11f}_’ LE_, W10 RANGE-SELECT T T we OTHER CONFIGURATIONS NOT SUPPORTED ~ BYDIGITAL ~ Figure 2-1 Jumper Location on M3106 Module | Table 2- 2 Jumper Configurauon Jumper Connectlon o Lme W1 DTRtoRTS 3 W2 W3 DTRwRTS DTRtoRTS 2 1 DTRtoRTS 0 W5 W4 RTStoFB 3 W7 RTStoFB W8 RIS©FB 1 0 | - 2 32 Module Installatnon o To mstall the M3106 module perform thetollowmg ‘ T - NOTE Thns checkout procedure should be performed by ‘tramed mamtenance personnel only CAUTION - _Swntch off power before msertmg or removmg ~ modules. S | - ;»f_The M3106 is a fine- lme etch PCB Handle it - carefully to avond damagmg the etch. Take antl statlc measures to protect the module - L The Qbus Interrupt Acknowledge and the DMA Grant sxgnals are dalsy-chamed through the\':- : - ABslots of the Q-bus backplane. If a DZQI11 is followed by a quad-size option in an AB/AB (Q/Q) backplane, it may cause an AB slot-pair.to be left vacant. In order tomaintain the ~ continuity of the daxsy chamed 51gnals aG7272 Grant Contmulty card should be installed in ~ the vacant A slot.. 20 - | | | o Refer to Sectlon 2. 4 for descrxptlons of the address aSSJgnments Set the switches at E28 SO that - the module responds to its assigned address. When a switch is closed (ON), a binary 1 is encoded. When a switch is open (OFF), a binary 0 is encoded. The switch numbered ] is connected toaddress bit 12, 2 1s connected to address b1t 11 and S0 on (Table 2 4) o 3 | "The 10-posmon sw1tch at E13 performs the vector selectlon Sw1tch position 7 is not used - Switch position 6 is connected to vector bit 3, 5 is connected to vector bit4, and soon. Whena ~ switchis closed (ON) bmary 11is encoded When a swflchis open (OFF) a bmaryOIS encoded o ~ (Table 2-3 ) o . 4. Posmon 8 of the vector selectlon swnch is a test swnch Wthh can dlsconnect the DZQIE' | osc1l]ator from a]l c1rcu1try Make sure that this sthch1sin the ON posmon before mstallatton Lo 5 - Posmons 9 and 10 of sw1tch El13 control the DZQI 1 response to a Break character recewed on | ~ Line 3. There are three vahd optlons HALT BOOT and no response Table 2-3 hsts the ,sw1tch selectlons | . | Table 2-3 BreaktCharacter_Response Options | Switch o 'Eff.eCtlof ,Break Character on Line3 ~ ~ o - OFF OFF‘No effect ON OFF OFF _ON RN Causes Processor to halt ON Causes Processor to boot ON - Illegal Condition (normal Operatron) - (specific apphcatlon) (spemfic,apphcatlon) SR ‘Make sure that +5 volts 1S present between AA2 and ground and that +12 vo]ts1S present o between AD2 and ground Measure at the nearest accessrble pomt if the backplane cannot be e accessed . Remove power and 1nsert the modulein an AB slot of the backplane Apply power and make sure that the +5 volts and +12 volts 1s present wrth the module .i o -mstalled | CAUTION | Insert and remove modules slowly and carefully to prevent damage to the module components on the - ,-card guides, and to avoid changmg swntch selectlons = in error. | S “THIS SIDE UP" '-M3106 MODULE | | S CABLE BC11U-25 O T [H]DU [] gl Figure 2-2 DZQI1 Installation (BC11U-25) ) ASSEMBLY ST T'abl've:‘2‘-'4' | -A‘ddi’ess'vSwitvch"fSCl}_eicstAidn | «— MSB 16 15[14. 13| 12111 10| 1 |‘1t1 DEVICE | SWITCH NUMBER ADDRESS ON ON 17760000| 17760010 | 17760020 | ON | ON 17760050 | ON ON 17760070 | ON | oN 17760060 17760100 17760200 Clon| ON ON 17760300 |on| 17760400 lon| 17760500 ON ON 17760600 ON ON| ON 17760030 17760040 ‘ON ON. flQN- ON. ON ON ON | on ON 17760700 ON’ ON “ON 17763760 ON | 17763770 ~ ON = SWITCH CLOSED TO RESPOND TOA LOGICAL1 ON THE BUS RDIRTE © Table2-5 Vector Switch Selection MSB 15 14 |13 el 5 12 l 11 10| 0 [« switcHes —— ~ ~ VECTOR "SWITCH |E13 NUMBER | ADDRESS 1 300 oN 310 310 ON ON “ONf ~REFER TO o SECTION 2.3.2 FOR SETTING | | "OFE13-7TO10 {on ON | ON ON | ON ON | ON ON ON | ON ON 330 ~ 340 350 ON 360 - 370 ON - 400 ON ON | 600 ON ON ON ON "ON ON ON ON 760 ON | ON ON ON | ON ON | O I 'ON = SWITCH CLOSED TO PRODUCE A LOGICAL 1 ON THE BUS 770 U RD'RTQ ~ 70-19964-00. CHA NNELS( o D DISTRIBUTION PANEL © 40-WAY BERG CONNECTOR ‘°i'CABLE;BC05LfXX : i T . I - ._ v - | ‘k(i CREDLINE TOW - MODULE o R Py -.(,Q"BUS BACKPLANE RED LINE N o . GATE ARRAY - TO"AT - T | - ( RDIBET Flgure 2 3 DZQll Installatlon (70 19964 OO) | - 2. 3 3 Testmg DZQllsin PDP 11 Systems | The fo]lowmg diagnostics are available to test DZQI ls 1nstalled in PDP-II systems DZITA and o . DVDZD are only used when a lmk between two processors is to be tested » CVDZA o DZVI I/DZQII Loglc Test— Part 1 -~ CVDZB DZVI11/DZQI1 Logic Test — Part 2 CvDZC DZVI1/DZQl11 Cable/Echo Test CXDZB .DECX/II Module | | DZITA ~ DVDZD ) 'Int el‘proce £ Test Program (ITE ) P) ITEP forssor ’Overlay el i B | S RO o Q Test the optron as follows "Run dlagnostlcs CVDZA and CVDZBin mternal mode to verlfy operauon Refer to the hstmg | for more help Run at least three passes without error. Insert the H329 test connector inJ 1 w1th the letter srde facmg up. J 1 1s the cable connector at the top of the M3106 module | . Run CVDZA and CVDZBin the staggered mode to verlfy module Operatlon Refer to the ~ diagnostic hstmg for the correct procedure Run at least three passes w1thout error. L o .If the unshrelded cab-kit (D3) version is used, replace the H329 test connector with the Berg = end of the BC11U cable assembly. Follow the ‘Thls side up’ mstructlon on the assembly Refer e to Flgure 2 2 for assembly and mterconnectlon instructions. R (; the cab-kit versionsCK- DZQI I- DA DB or-DF are used feed the cable through the rear of | - the cabinet and connect the Berg plug to the dlSU’lbUthl‘l panel Mount the d1str1but1on panelin- the opening at the rear of the cabmet | - ._ The -DC version is provrded with an adapter plate to fit the large opening in a PDP-11/23+. ~ ' Mount the adapter plate on the distribution panel, w1th four ofthe elght SCrews provrded Mount the dlstrlbutlon panel as descrlbed above | | - Connect the H325 test connector on the first line andrun dlagnostlc CVDZC Select the cable- o -test part of the dlagnostlc Three passes are needed w1thout error. Repeat this step for each line. | Run the DECX/ll system exerc1ser to verlfy the absence of Qbus 1nterference wrth other B | . » | I - system devices. o - The DZQI 1 is now ready for connectron to external equrpment If the connection is to 2 local - terminal through either of the two options (BC11U-25 or 70-19964-00), a null modem cable assembly must be used. Use the BC22A, BC22D, or BCO3P null modem cables for connection B “between the option and the termmal The H3 1 2 A null modem unit mayalso be usedin place of the null modem cables. B r | | | - Connectlons between the optlon and a modem should be made usinga BC22E or BCOfl D cabl All ofthe cables referred to, with the exceptton of the BCl 1U-235, must be ordered separatel\ as .they are not components of a DZQll option. If a term1nal is avarlable run the dlagnostrc CVDZC in echo—test mode to xerrf\ the cable | | » connectrons and the termmal equrpment o 2.3 4 Testmgin MlcroVAX Systems The followmg dlagnostlc tests are ava1lable for testmg DZQl lsin MICI'OVAX systems f EHXDZ DZVll/DZQllTest - S EHKMV Macroverrfy MlCI‘OVAX System Test ) o Macroverrfy is a standalone dragnostlc whrch contams a DZVl l/DZQll test module R Refer to the apprOprlate dlagnostrc hstmg, orto Chapters 1 1 and 14 ofthe MlcroVAX Owner S Gurde for ~ details of how to run EHXDZ and EHKMYV. Test the Optlon as follows ) » l .'.',Boot from the MlCI‘OVAX system tests drskette (number 2 of 2) Attach and select the DZQl l | - thatis to be tested - 2 Run EHXDZ for three error—-free passes of the 1nternal (default) test | ,} 3. ‘, | Install the H329 staggered loopback connector on the M3 106 module Run EHXDZ for three . f‘_error-free passes of the staggered test 4 Remoxe the H329 Install the BCOSL cable and the dlstrlbutlon panel 5. 5 If the operatron ofa termmal lmkis to be tested connect the termmal lrne to the distribution R R panel Run the EHXDZ echo test on that line until the linkis proven Depending on the . termrnal a null modem may be needed for thls test. Exrt echo test by " Z (CTRL/ Z) -j6.f Remove all external cables and connectors from the drstrrbutlon panel Boot the CPU tests diskette (number 1 of 2). The Macroverify diagnostic will run automatically when the boot rprocess is complete When the test completes the status of all optrons w1ll be dlsplayed 1. Ifno devrce has a TE ST FAILED status the DZQl 1 1S NOW ready for connectlon to external o ‘equipment. If theconnection is to a local terminal, a null modem cable assembly must be used.” ~ Usethe BC22A, BC22D, or BCO3P null modem cables for connection between the option and o the terminal. The H3 12 A null modem umt may also be usedin place ofthe null modem cables | Connect1ons between the optron and a modem should be made usrng a BC22Eor BCOS D cable ) All of the referenced cab]es must be ordered separately as they are not components ofa DZQl | »opnon : *{2 4 DEVICE ADDRESS ASSIGNMENTS ~ On UNIBUS and Q-bus systems, a range of addresses(iu600103to ux637768)in the top 4K wordss .assrgned as floatmg address space (x“ means all top address b1ts = 1) ) . _'__The first part ofthe hst ofoptrons (sufficrent to include the DZQI 1 ) whrch can be assrgned floatmg de\ice S - addresses is given in Table 2- 6. ‘Rank” grves the sequence of address ass1gnment for both Q-bus and o "UNIBUS optlons a , . | B | ~ N _ 'V‘If addresses are assxgned accordlngto defmed rules configuratron programs can check whrchoptlons are installed in a system. Having a combined list allows us to use one set of configuratlon rules and one v _Configu ratlon progra m for both Q bus and UNIB US system s Table 2 6 Floatmg Address Assngnments, | ~ Rank ) | Devnce . R S Slze “ (declmal) Ty DQ11 R © puly, DUVll* 4 — 4 words' 4words o o LKA ’ V"ZDMCII/DMRII R "‘DZQ]l*/DZVIl* pz32 D (. - ___1-0 : 4words (octal) w0 10 10 4words . Dzi1,DzS11, IR~- TS R~ N g " Modulus dwes I b 1 - 10 o 4wods 10 For example, the address assignment seQUeneesv could be: UNIBUS - Q-bus DbJj1r- ~ DHI1 DQl1l1 DUI11 DUPI1 LKI1A DMCl11 - DZ11 -.NoQbus equ1va]ent ofDJll - No Q-bus equivalent of DH11 No Q-bus equ1va1ent of DQII R DUVI1 ~ No Q-bus equivalent of DUPII - No Q-bus equivalent of LK11A NoQ- bus equivalent of DMCll | ""DZQllandsoon e | - - Devxces of thesame type are given sequent1a1 addresses therefore all DUVl 1Is m a systemwrll ha\ e lovt er : addresses than DZQI ls or DZVI Is. . - For the purpose Of address assxgnment DZQI 1 S and DZVI Is are con51dered as devrces of the same ty pe ~ " The co]umn Szze(deczmal)in Table 2- 6 shows how many words of address space are needed for each device. The column Modulus(octal)is the modulus used for starting addresses. For example. devices with ‘an octal modulus of 10 must start at an address whichis a multiple of 10g. The same ruleis used to select a | gap address ( see a551gnment rules) after an optlon or for a nonexistent device. | The a351gnment rules are as follows : l Addresses startmg at xu60010 are ass1gned accordmg to the sequence of Table 2- 6 | 2 .‘ , Optron and gap addresses are assrgned accordmgto the octal modulus as follows | | a . ‘[.Devrces wrth an octal modulus of 10are assrgned an address ona 108 boundary (the three - e b. | | o o Llowest orderaddress bits=0) | Devrces with an octal modulus of 20 are assrgned an address ona 203 boundary (the four | L lowest—order address bits =O) | ~ | . . 3 Address space equal to the dev1ceS modulus must be allowed for each dev1ce Wthh is e connected to the bus 4, :A one-word gap, assrgned accordmg torule 2 must be allowed after the last dev1ce of each type ‘ ' ThlS gapcould be blgger when rule 2 is apphed to the following rank Sl 5 A one-word gap a551gned accordmg to rule 2, must be allowed for each unused rank on the lrst if ,. ~adevice with a hlgher address1S used This gap could be blgger when rule 2is applled to the o R followmg rank R HE | | o Two e\tamples of address assrgnment follow Table 2- 7 shows addresses for a system withone- DUVI l o - - andone DZQ11. Table 2-8 shows addresses fora system withno DUV1 1 and two DZQ1 1s. Note that ‘the gap. Vector assrgnments (See Sectron 2.5) are also shown in these tables. ._“.._.Table 2 7 is supported by descnptron a of Table 2- 7 Rank Address 1 xxx60010 2 3 xxx60020 - xxx60030 5 6 7 8 | | where thereis no Q-bus device at a specific rank, the UNIBUS device parameters must be used to assrgn - - xxx60070 xxx60100 xxx60110 - xxx60120 to apply the assrgnmem rules L One DUVll and One DZQll SR "DeSIgnatlon, SR T Vector B DIJI1l gap._ B ~ DHIl gap DQlligap xxx60050 xxx600600 how - DUVII gap DUPllgap LKIlAgap DMCllgap -~ DzQIl ,DZQll gap ST e R 310 ST T -'The first floatmg addressis 7600]0 As aDJ1 1 hasa modulus of 108, 1ts gap can be assrgned to 760010 *The next avarlable locatlon becomes 76001 2 R LT | ‘Asa DHI 1 has a modulus of 208, it cannot be a551gned to 76001 2 The next modulo 20 boundar\ is '-760020 so the DHl 1 gap 1S assrgned to this address ‘The next avaxlable locatlonis therefore 760027 o | A DQl 1 has a modulus of 108 lt cannot be ass1gned to 760022 Its gap is therefore assrgned to 760030 s The next avarlable locatlon 18 760032 | - '»[; v2412;~;j' ""' | e . "The DUVI11 hasamodulus oflOg It cannot be ass1gned to 760032 Itis therefore assrgned to 760040 As | »the srze of DUVll is four words the next avarlable address s 760050 Thereis no second DUVl l,so0a gap must be leftto 1nd1cate that thereare nomore DUVl Is. As 760050 = ~isona lOg boundary. The DUV] 1 gap can be a551gned to this. The next avallable addressIs 760052 - _And SO on. Table 2- 8 “Rank 1 2 3 4 5 6 7 8 8 Address Two DZQlls Desngnatlon - xxx60010 - _DJl.l_gap _xxx60020 -~ DHII1 gap - xxx60030 - DQII gap - xxx60040 @ DUVIIlgap xxx60050 DUPI1 gap xxx60060 ~ LKI1A gap ~ xxx60070 @ DMCllgap - xxx60100 1st DZQIl xxx60110 | ~ 2nd DZQI11 'xxx60120—'_. " ' DZQll'gap» | Vector | | -~ 300 310 » Q2 5 INTERRUPT VECTOR ADDRESS ASSIGNMENTS | Addresses between 3008 and 774g are de51gnated as the floating vector space. These addresses are ; assrgnedin sequence as in Table 2-9. | | | | - - Each Device needs two 16 bit locattons for each vector For e'(ample a dewce w1th one receive and one transmit vector needs four words of vector space | - The vector assrgnment rules are as follows l_. | - 2. Each dewce occuples vector address space equal to*Size’ words For e\ample the DLVl 1-J occupies 16 words of vector space If its vectorwas 3008, the next = av ailable vector w ould be 3405, There are no gaps except those needed to align an octal modulus The vector addresses shown in Tables 2-7 and 2-8 are a351gned accordmg to these rules B Table 2-9 Flrst Part of Qbus Vector Address Assngnments Lrst Device I S U DLVIL) DLV11,DLV1I-F "DRVII-B 16 4 4 DRVIl - ~ - DLV1I-E VSVI1 KWVI1 DUVII S DZV11/DZQI1l Size (decimal) 4 : 4 8 -4 I Modulus (octal) - 10 10 10 10 10 10 10 4 10 4 10 ' ) CHAPTER3 DEVICE REGISTERS 3.1 SCOPE This chapter descnbes the format and bit functron of each regrster in the DZQll 32 DEVICE REGISTERS The DZQ11 contains six addressable regrsters Frgure 3-1 shows the b1t assrgnments of these regrsters B - and Table 3-1 hsts the reglsters and related DZQll addresses Table 3-1 " Register Name @ ~Control and Status Reg. - ReceiverBufferr DZQll Regrster Address Assrgnments - =~ ~~ ~~ Line Parameter Register Transmitter ControlReg. Modem Status Register ~ =~ =~ Transmit Data RegiSter‘ e Mnemonic Address SR, Program | CSR~ 76XXX0 RBUF = 76XXX2 LPR 76XXX2 TCR. MSR =~ 'TDR‘ 76XXX4 = 76XXX6 = Read/Write = Write Only e 776XXX6 g Read Only Read/Write Read Only Wr1te Only e | XXX = Selectedin agreement with the floatrng devrce address system 3.2, l Control and Status Reglster | : oL | ~ The control and status register (CSR) can be addressed with a byte or word address All bits in the CSR | ‘are cleared by an occurrence of BINIT, or by setting device Master Clear (CSR<O4>) The format iis shownin Frgure 3-1 and the bit assrgnments are listedin Table 32 S|||o;._A:w:E,<_T~_._m,Busm3wma.iEamEscm_m/.\flm eSTGl VW ZS O0 . 171I0CH((4IESN9DTO)DE.1I2/Y/|T|A&RF/S /e&/|.|vV¢iaS~|L-2yi|aA|SvYivaB~|||ovByRi—Ia-S)e@/ls-|eo/s,Yee=—l]—/—S—]3|Ne———,m.z...,mz:INT|©<80:G1>yYoy 2 . : v 3 Y y Y o Hsw) o o _ ST|oe—— eovecamneio0e.'Illvll‘.'l.llll.ln.l.-l. ——evaaginno—Tl"ll.l' SR90>HZHHaQAw(1-|||LSv¥8w—L©=1IE3iNyaI3N0ivisWS4dA.|aSRvS(oNIINHNEin4VwNi0Vdsg|vHO13SNH:—i)L-DYLsE/T©|||s-EwvAoo1soiIQwe/YfWSv0my,d_voOaL]Al)/||aoN%vm|ov_OONd3u"L)mHlTa1|RA.«05LO3|/N|.5DgS_S1wWoLe7seEouuoo6RL]R/Vdf|3/H/EvS50|T|E|/1||/|]0THm|8oX4OsoSVV1Yydn83<"SoNMv3fR,s;vo-Luyoai|w|l-i3/aM0Q|mo.©o0uoe/ty|lmo/g—m5ll,S2t9.aL+o3l-||/.3io—‘zOoMl0mdoJomHus>l.,o_||]SY|N2.-y&a:o]y|—3oj.zm]d=|ma.94HH33o,x|—odaL6|T+0msldo|Rn.|=ul8E|(..m|:00/ualo|-oxM3|TNTr0dm3zlAoEv,9E0oa4mw4H|YL,.—,dl|ovenmuE2a.lo,|sRll®|.E&oa]w.4mol4zd|wH%m|8n—Lv[_onwo]d]g3/udw|ga_NWsyo|5]OLdHI}Q.oA|||/-o4493muV:ONanNom1dv—mdN|0da/ey|9l,|3vSa1||[4o4/m3dNIsonmu:m3oT8O0.ola|siHR1||SSYw|0yT—|.[|,Ho4O{-d4Ovmmvd|11,YnlBoa|n474V9o—|vmg18HT1aDiD|lYIl1|/|||1]'eool|g444moHmLo,n.4mnuvw0LaeI8gl—yHD|NlY<Ti.OIlTB|EY|||.|Wl/o.2o4|zRmelonWomi!d8/4eNlwo1eS/8aLBTYn|Ro|M|Bl4m1EoO[o,A'd1nI-wliT4tYmS|N018rL-y8nL/RTRY@oSol||[mT'o40OM4C.o,|dN0BnmY|NA8l&@81)NNI!Y.T8"7,.<.11mB0<NdwV_3.,0:mH|X_vm33ul1om>SHLm14h9qNRm3O%g44_y\4|wg (o) 03' o) ” INIT AN 3.2 Table 3- 2 | © - Functlon L Title <02:00> Notused R -~ (MAINT) CSR Blt Assngnments | e | | e output o | <03> - 3 ,Maintenance o _' This is a READ/WRITE bit. When set 1t loops the serlal serial input <04> connections of the transmitter to the corresponding connections of the recelver at the UART. (Used for 100pback test ~ ‘When written toal this b1t generates mrtlallze w1thm the DZQll | e Master Clear (CLR) PR o B o ~ : only) - - A read-back of the CSR with this bit set indicates initialize in - progress within the device. This bit is self-clearing. All registers, . sflos and UARTs are cleared wrth the followmg exceptrons 1L Only bit 15 of the receiver buffer reglster (Data Vahd) is R | cleared the other bits (<14 00>) are not vv 2. ".Thehlg.hbyte ofthetransmlttercontrol reglsterls notcleared by ) | i 3. <05> : | | <06> : ~ S | | 'Master Clear. The modem status reglster 1S not cleared by Master Clear _Th1s read/ write b1t must be set to perm1t the receiver and transmitter ~ control sections to start scanning. When cleared, Transmitter Ready » vMaster SCan - Enable (CSR<15>) is inhibited from settmg, and the recelved character (MSE) | o | o - buffers (sflos) are cleared 'Receiver : ThlS bit penmts the generatlon of an mterrupt when CSR<O7> or Interrupt | - 'CSR<13> is set. Th1s b1t is read/wrlte | | ~ Enable (RIE) - <07> Coe Recei\}erDone - N This is a read—only bit that is set when a character appears at the o - (RDONE) , | " output of the first-in/first-out (FIFO) buffer. For the DZQ11 torun “in the interrupt-per-character mode, CSR<06> must be set and CSR<12> must be cleared. With CSR<06> and CSR<12> “cleared, character—flag mode is indicated. Receiver Done clears ~when the receiver buffer reglster(RBUF) is read or when Master - Scan Enable (CSR<05>)is cleared. If the FIFO buffer contains an - additional character, the Receiver Done flag stays clear forupto 1 - microsecond, while that character bubbles through to the bottom of - - <09:08> ST C<11:10> Transmitter - Line Number = (TLINE B and A) TLINE Not used | | ~ the F IFO. These read- only bits mdlcate the line number whose transmit bufter" needs servrcmg These bits are valid onlywhen Transmitter Ready: (CSR<15>) is set, and are cleared when Master Scan Enable s | | cleared Bit <08> 1s the least—srgmficant bit. | | 3.3 Table3-2 CSR Bit Assignmems (Cont) B Function - <12> SiloAlarm Thls is a read/wrlte bit. When set, it enables the srlo—alarm and'“ Enable prevents RDONE (bit <07>) from causing interrupts. If the . ~ O (SAE) receiverinterrupt enable bit (bit <06>>)is set, SAE enables the silo- alarm(bit <13>)to generate an interrupt after 16 siloentries. If silo- - alarmis not set, then SAE may be usedas aflag to 1nd1cate that 160r R ‘more characters are in the srlo ' | o - <13> e Silo Alarm ~ (SA) BT I ThlSlS a read—only blt set by the hardware after 16 characters have | beenentered into the FIFO buffer. Silo Alarmis held cleared when Silo Alarm Enable (CSR<12>)is cleared. This bitis cleared bya ~ read tothe receiver buffer register and does not set until 16 additional characters are entered into the buffer. If Receiver Interrupt Enable “~(CSR<O6>) is set, the occurrence of Silo Alarm generates a - receiver interrupt request. Flag mode operatlon of the Silo Alarm bit | ~ 1S permitted wrth CSR<O6> cleared <14> - Transmitter Interrupt IS Enable = <15> . ]Transmrtter .~ Ready o ,‘(TRDY) . - ThlSis a read/ write b1t WhICh must be set for Transmltter Ready to | generate an 1nterrupt | - (TIE) - - - | This read-only bit is set by the hardware when the transmitter scanner stops on a line whose transmit buffer may be loaded with another character and whose related TCR bitis set. The transmitter line number, spec1fiedin CSR<09:08>, is only valid when Trans- ~ mitter Ready is set. Transmitter Ready 1S cleared by any of the followmg condrtlons o | 1 When Master Scan Enable1s cleared e _’ 2. When the related TCR bitis cleared for the line number o pointed to in CSR<O9 08> o T If addltlonal transmlt hnesneed service, Transmrtter Ready appears - again within 1.4 microseconds of the completion of the ‘transmit data - register load’ instruction. When Transmitter Ready occurs with . Transmltter Interrupt Enable set, a transmltter mterrupt request 1S generated - | | o | | e 3 2 2 Recelver Buffer o ~ Thereceiver buffer ( RBUFV)isal 6 b1t readonly reglster that contains the recelved character at the output ; - of the FIFO buffer. A read of the register causes the character entry to be removed from the buffer, and all ~ other entries to shift down to the lowest location that is not occupied. Only the Data Valid bit - (RBUF<1 5>)is cleared by BINIT or by setting device Master Clear (CSR<04>). B1ts <l4 OO> are ~ not affected The b1t a551gnments for the RBUF reglster are hstedin Table 3 3. S | ~ Table 3-3 RBUF Bit Assignments . Bit "<O7:OO> . L S 'Function | “ .‘ Title - These bits contam the recelved character rlght JUStlfied the least- ‘ Received "srgmficant bit is bit <00>. For short characters, bits that are not Character ~ | (RBUF D<7: O>) used are logrc low The parlty bit is not shown ~ | -These bits contam the lrne number on wh1ch the Recelved Character o B <09:08> Received - o Line Number (RXLINE Band ~ - RX LINE A) " | ‘was recetved Bit <08> is the least 51gn1ficant | | N Not used | <1 110> ‘Parity Err"ort e "_Thrs b1tis set ifthe sense of the parlty of the recelved character does - <l2> not agree w1th the parlty defined for that lme (PAR ERR) =~ TR Framing Er'rOr - This bitis set if the received character did not have a stop b1t present | at the correct time. This bitis usually 1nterpreted as mdrcatmg thata - (FRAM ERR) ~ ‘_< < 13> | S | break has beenrecerved . | S ; | S - o ’<‘14> SR OVer‘run Error L This b1t becomes set when a recelved characteris overwrltten in the - Data Valid ~ This b1t when set 1nd1cates that the datain b1ts <14: OO> is Vahd - e - 3.2.3 (OVRN ERR) '_UART buffer (by a following character) before it has been o (DATA VALID) transferred by the scanner to the FIF O . o S S This bit permlts the use of a character-handlmg program which again " and again takes characters from the FIFO buffer until there are no "~ more available. Thisis done by reading this register and checlung bit ; <15> untll the program gets a word for wh1ch bit <15> 1S Zero. Line Parameter Reglster | ‘The line parameter register (LPR) controls the operatlng parameters related to each linein the DZQl 1. The LPR must be addressed with a word address andis a write-only register. The line parameters for all B linesmust be loaded again followrng an occurrence ofelther BINIT ordevrce Master Clear. Table3 4hsts » . bit assrgnments o | <01:00> | - - <02> | | Title’ o | Function Parameter Line Number These b1ts spec1fy the line number for which the parameter mformatlon (bits <12 3>)is to apply Bit <OO> is the least srgmficant bit. ~ Not used _Must always be wrrtten as a zero when specrfymg the parametu line | (LINE B and LINE A) - *number. Writing this bit as a one extends the parameter line number field into nonemstent hnes Parameters for hnes OO to O? are not} affected. 35 o Table 3 4 LPR Blt Assngnments (Cont) 5 O <04:03> "Tvitle v""Functlon _“Character "_-These bits are set to receive and transmrt characters of the length' - Length ]”(e\cept panty) shown below "~._(CHARLGTH, : 10 - | s 7bit L Stop C ode s Thxs bit sets the st0p code length 0= 1 unit stop, _1 = 2 umt stop (OI" | __1 5 unit stop if a 5 level code 1s used) i | Parity E'nab]é o - | _If thrs bit is set characters transmrtted on the ]me have an g | apprOprrate parity bit added and characters recelved on the line ha\ e _.thelr parrty checked ,_._‘_”Odd Parm - - (ODD PAR) | . = ) Ifthis brtis set, characters ofodd parltv are generated onthe lme and" R ey incoming characters are expected to have odd parity. If this bitis not set, but bit <06> is set, characters of even parity are generated on the line. andiIncoming characters are expected to have even parity. It S _jbrt <O6>isnot set then the settmg ofthrs b1t W111 not have any effect _Speed’ccde; S i'__The state of these bits determmes the operatmg speed for the“ o e — 0000 == - 0000 “ Not supported by standard software. 08 Baluvd»R_a»te, = = ) - CODE A) | N ?transmrtter and rece1\er of the selected hne D to SPEED B ,Reooégooé_coagoop}'n ~ (SPEED cO)E 15 7110 1345 o -.4150 1200 3600 4800 7200 9600 19 800* | " Table 3 4 LPR Blt Assngnments (Cont) Bit ~ Co<12> o = Title P RN R Functlon ' Receiver G | ‘Thrs bit must be set before the UART receiver loglc can assemble‘ ’ | (RX ENAB) BIN IT or devrce Master Clear Enabled <15:13> “characters from the serial input line. This bitiis cleared followmg a | o | Not used NOTE / .o Y '“ The M3106 module can be modlfied byJumpers W9 to W13, so that code 1111 selects baud rates other than 19 800 This modlficatlonis not supported by DIGITAL | | - ~ ~ 3.24 Transmltter Control Reglster The transmitter control register (TCR)is a byte- and word addressable reglster The low byte of the TCR contains the transmitter control bits, and must be set to start transmission on a line. Each TCR bit position is related to a line number. For example TCR<00>is related to line 00, bit <01> toline 01, and soon. - Setting a TCR bit causes the transmitter scanner clock to stop if the UART for this line has a "transmit buffer empty’ condition. An interrupt is then generated if Transmitter Interrupt Enable is set. The scanner clock restarts when either the transmit data register (TDR)is loaded with a character or the TCR bitis cleared for the line on which the clock has stopped TCR bits must only be cleared when the scanner isnot runnmg (thatis, Transmltter Ready is set or Master Scan Enable is cleared) -_The lme enable blts are representedin TCR<O? 00> These b1ts are read/ write and are cleared b\ BINIT | or device Master Clear Brts <07: O4> are not used and are read as zero. | | ~The hlgh byte of the TCR register contains the modem control srgnal that can be wrltten data termmal | ready. (DTR) The b1ts are defined as follow . 'Bit.’ -~ ~ Name <08> DTRLine 00 <09> ~ <10> <11> <15: 12> DTR Line 01 B 'DTR Line 02 | o DTRLine 03 ~ Not used; read as zero Assertlon ofa DTR blt creates an ON condmon on the approprlate modem circuit for that line. DTR bits ~areread/write and are cleared only by BINIT, Jumpers ha\ e been prox ided to allou the RTS circuits to be | asserted usmg DTR assertions. 5 ST 32. 5 Modem Status Reglster o | ) e | ERE The modem status register (MSR)is a 16- brt read-only reglster A read to thlS regrster gives the status of ~the modem control signals that can be read, Ring and Carrier. The ON condition of a modem control signal| s mterpreted as a logicalone. Blts <O7 04> and < l 5 12> are not used and are read asa zero. The other : Dbitsare defined as follows i e o e . '“Bfit7d f Name o Name o<00> e ng Lme OO ,- C<o1> - L <02> - <03> ' <08> Ring Line 01 <O9> - Ring Line 02 ~Ring Line 03 :<0704> : ~ Not used,; read as ‘;4'<11>;; = Camer Lme OO ~ Carrier Line 01 ~ Carrier Line 02 , - Carrier Line 03 ,Not used read as zero. ZETO ~ ~ - - “ 3 2 6 Transmlt Data Reglster ( The transmit data register (TDR) is a byte- and word-addressable wrlte only reglster Characters for. transmission are loaded into the low byte. TDR<00>is the least-significant bit. Loadmg of a character should occur only when TransmrtterReady (CSR<15>) is set. The character thatis loaded into this registeris routed to the hne definedin CSR<O9 08> The hlgh byte of the TDRis defined as the break; - ’--_---.."contro] reglster | | g | Sl S : A Thereis a correspondlng break b1t for each of the four multrplexer lmes TDR<08> represents the break- ~ bit forline 00, TDR<09> forline 01, and so on. TDR<15:12>are not used. Setting a break bit forces the . '_output of that line to space. This register is cleared by BINIT or device Master Clear. The break control .' reglster can be used‘regardless of the state of the Devrce Mamtenance bit (CSR<O3>) S : CHAPTER 4' PROGRAMMING : '41 SCOPE ~This chapter contains mformatlon for programmmg the DZQl 1 in the most efficxent way. To do so, the e programmlng controls must be completely understood. The following paragraphs dlSCUSS the DZQl 1 o 'from the programmmg pornt of vxew and descrrbe recommended programmmg methods N 4. 2 PROGRAMMING FEATURES | | - | - The DZQ11 has some programming features that allow control of baud rate, character length stop b1ts - parity, and mterrupts This sectlon dlscusses the apphcatron of these controls to get the wanted operatmg B parameters | | ~ . , - | Sl . | - .',f'421 Interrupts : - The Receiver Interrupt Enable ( RIE) and SllO Alarm Enable (SAE) b1tsin the CSR control the way that o | L | the DZQll receiver mterrupts the processor If RIE and SAEare both clear, the DZQI 1 never 1nterrupts the processor In this event the program must regularly check that the datais availablein the silo, and empty the silo when datais present. If the program ~ operates froma clock, it should check for charactersin the silo at least as often as the time it takes for the ~silo to fill, allowing a safety element to cover processor-response delays and time to empty the silo. The - Receiver Done (RDONE) bitin the CSRis set when a characteris availablein the silo. The program can ’*regularly check this bit with a test byte or bit test mstructron When RDONEis set the program should empty the srlo If RIEis set and SAE18 clear theDZQl l mterrupts the processor and forces it to the DZQl l receiver - vector address, when RDONEis set. This indicates the presence of a character at the bottom of the silo. The interrupt service routine can get the character by performing a move instruction from the RBUF. If the ~ program then dismisses the interrupt, the DZQ11 interrupts when another characteris available (which - may be 1mmed1ately if additional characters were placedin the silo while the interrupt was being serviced). - Another way is for the 1nterrupt service routine to respond to the mterrupt by emptymg the srlo before it ’dlsm1sses the 1nterrupt | | | o s o - "If RIEand SAEare both set, the DZQl 1 mterruptstheprocessor to the DZQl l receiver vector when the ~ Silo Alarm (SA) b1tin the CSRis set. The SA bitis set when 16 characters have been placedin the silo after the last time the program has accessed the RBUF. Accessing the RBUF clears the SA bit and the - related counter. The program should follow the procedure describedin Section 4.2.2 to empty the silo , " completelyin response to a Silo Alarm interrupt. This makes sure that any characters placedin the srlo ‘_‘whlle it 1s belng emptled are processed by the program | | | NOTE : S Ifthe program processes only 16 entrles in response o toeach Silo Alarm interrupt, characters comingin ~ while interrupts are being processed build up without bemg counted bythe Silo Alarm circuit. ~ Thesilo may in the end overflow wnthout the alarm | bemg 1ssued T ~ If the Srlo Alarm 1nterrupt is used the program wrll not be1nterrupted when fewer than 16 characters are received. In order to respond to short messages during periods of medium activity, the program should ~ regularly empty the silo. The scanning period depends on the wanted response time to received characters. - While theprogram is emptyrng the silo, it should make surethat DZQ11 receiver interrupts are inhibited. ~ This should be done by raising the processor priority. The Silo Alarm interrupt feature can greatly | ~ decrease the processor overhead that would be needed by the DZQl 1 receiver. Thisis done byremovmg B - the need to enter and ent an mterrupt service routme each time a characteris recelved s 'The Transmltter Interrupt Enable ( TIE) b1t controls transmltter 1nterrupts to the processor If enabled the N - DZQ11 mterrupts the ; processor at the DZQl1 transmitter 1nterrupt vector when the Transmitter Ready (TRDY) bit in the CSRis set ThlS 1ndlcates that the DZQll is ready to accept a character to be ,transmrtted | ) g _Each DZQl 1 needs two 1nterrupt vectors one for the transmrtter section and one for the receiver section. ) . If simultaneous interrupt requests are generated from each section, the receiver section would have ~priority in placrng its vector on the Q-bus. A receiver interrupt to address XXOis generated from having ~ either a Receiver Done (CSR<07>) or Silo Alarm (CSR<13>) occurrence. A transmitter interrupt to address XX4is generated by Transmitter Ready (CSR<15>). An additional prerequisite for generating - interrupts is that the individual interrupt enable bits are set. The recommended method for clearing - Interrupt enable bitsis first to raise the processor status word to level 4; next, to clear these interrupt enable bits; and then lower the processor status word to zero Usmg this method prevents false 1nterrupts from - | ‘berng generated o 4.22 Emptymg the Srlo N | . | | ( o S - The program can empty the silo by performmg consecutlve move 1nstructlons from the RBUF to “temporary storage. Each move instruction copies the bottom characterin the silo so that it is not lost, and clears out the bottom of the silo, allowing the next character to move down for access by a followmg move - = instruction. The program can determme when it has emptied the silo by testing the Data Valid bitin each word moved out of the RBUF. A zero value indicates that the silo has been emptied. The test can be ’"'performed by branching on the condition code following each move instruction. The test or bit test ~ instruction must not access the RBUF because these instructions cause the next entry in the silo to move - - ~ down without savmg the current bottom character. Also, following a move from the RBUF, the next characterin the silois not avarlable for at least one microsecond. Therefore, on fast CPUs, the program mustuse enough instructions or no—operatron instructions to make sure that consecutive moves from the - RBUF are separated by not less than one mrcrosecond This prevents a false 1nd1catron of an emptv silo. « 4, 2 3 Transmlttmg a Character - | | - Theprogram controls the DZQ11 transmitter through four registers on the Q bus the control and status register (CSR), the line parameter reglster ( LPR) the transmlt control reglster ( TCR) and the transmlt data reg1ster (TDR) RS | | | - F ollowmg DZQl 1 1n1t1allzat10n the program must use the LPR to spemfy the speed and character format | - for each line to be used and must set the Master Scan Enable (MSE) bitin the CSR. The program should | o set the TIE b1t1n the CSR if 1t wants the DZQll transmltter to 1nterrupt the processor. | The TCRis used to enable and dlsable transmlssmn on each lme One b1tin this regtster is related to each | - line. The program can set and clear bits by using move, move byte, bit set, bit set byte, bit clear, and bit - clear byte instructions. (If word 1nstructlons are used, the Line Enable b1ts and the DTR b1ts are accessed | | r | together ) . . | R The DZQl 1 transmltter is controlled by ascanner Wthhis contlnuously lookmg for an enabled lme ( Lme, . Enable bit set) which has an empty transmitter buffer. When the scanner finds such a line, it loads the number of the line into the 2-bit transmit line number (TLINE) field of the CSR and sets the TRDY bit, ~ ~ interrupting the processor if the TIE bitis set. The program can clear the TRDY bit by moving a character - for the indicated line into the TBUF or by clearing the line enable b1t Clearlng the TRDY bit allow sthe o . scanner to continue its search for lines needlng serv1ce - To start transmlss1on on an 1dle lme the program should set the TCR bit for that lme and walt for the - scanner to request service on the line, as indicated by the scanner loading the number of the line into "TLINE and setting TRDY. The program should then load the character to be transmitted into the TBUF by using a move byte instruction. If the interrupts are to be used, a useful way of starting up a lineistoset the TCRbitiin the main program and let the normal transmltter 1nterrupt routme load the character|intothe : ‘TBUF S | - %;_NorE - The scanner may find a different line needing ~ service before it finds the line being started up. - | ‘This occurs if other lines request service before the scanner can find the line being started. The program ‘must always check the TLINE field of the CSR ‘when responding to RDY, to make sure that it loads characters for the correctline. Assumingthe - program services lines as requested by the scanner, the scanner in the end finds the line being started. If more than one line needs service, the scanner requests service in priority order as determined ~_byline number. Line3 has the hlghest pnornty and line 0 the lowest - To continue transmrssxon on a line, the program should load the next character to be transmltted into the TBUF each time the scanner requests service for the line as indicated by TLINE and TRDY. Because the transmltters are double buffered a hlgh pI‘lOI‘lty line may request two consecutr\e loads To termmate transmxssmn on a line, the program loads the last character normall\ and waits for the scanner to request an additional character for the lme The program clears the Line Enable bit at tlux time 1nstead of loadmg the TBUF. | | | - ) The normal rest CODdlthl‘l of the transmltted data connection for any lmeis the one state The Break ~ (BRK) bits are used to apply a continuous zero signal to the line. One bitin the TDRis related to each line. - The line stays in this condition as long as the bit stays set. The program should use - to access the BRK brts : f R amove byte mstructton' | If the program contmues to load characters for a lme after settmg the BRK b1t transmrtter operatton. o 8 'appears normal to the program regardless of the fact thatno characterscan be transmitted while the lineis ~in the continuous zero-sending state. The program may use this facility for sending correctly timed zero e -signals by setting the BRK bit and usmg transmit ready interrupts as a timer. Theprogram must also make B - sure that the line returns to the one state at the end of the zero—sendmg perlod before transmlttmg any f BTaddltlonal data characters e The followmg procedure does th1s When the scanner requests service the first tlme after the program has - ~ loaded the last data character, because the linesare double buffered the last datacharacter has only S started transmission. The program should therefore load an all zero character and waitforthe nextservice - request while the last characteris transmitted. ‘When the scanner requests service the second time, the - program should set the BRK bit for the line, and the zero characteriis overwritten. At the end of the zero~ sending penod the program should load an all zero character to be transmitted. When the scanner requests service, indicating this character has started transmnssron the program should clear the BRK bit | and load thenext data character ~ | o | "4 2. 4 Data Set Control | (R | | B D The program may sense the state of the Carrler and ng Ind1cator 51gnals for each modem and may : ~ control the state of the Data Terminal Ready signal to each modem. The program uses two registers to - access the DZQl 1 modem control logic. There are no hardware interlocks between the modem control o o logtc and the receiver and transmltter log1c Any wanted sequence should be done under program control - Y g_’The Data Termmal Ready (DTR) b1tsin the TCR are read/wrlte bits. Settmg or clearmg a b1tinthIS - i - register turns the appropriate DTR siignal on or off. The program may access this register with word or bytel o instructions. (If word instructions are used, the DTR and Line Enable bits are accessed together.) The L DTR bits are cleared by the INIT signal on the Qbus butare not cleared 1f the program clears the DZQl 1 '..‘jby settmg the CLR bit of the CSR - The Camer (CD) and ng (RI) b1ts in the MSR are read—only b1ts The program can determme the ~ current state of the Carrier signal for a line by examining theapproprr ate bitin the high byte of the MSR. It ;‘ | _ - can determine the current state of the ng signal for a line by examining the approprlate bitin the low byte - ofthe MSR. The program can examine these registers at different times by using move byte or bit test byte ~ instructions, or can examine them as a single 16-bit register by using move word or bit test word - | instructions. The DZQ11 modem control logic does not interrupt the processor when a Carrier or Ring signal changes state. The program should regularly sample these reglsters to deterrmne the current status. | ) _"Samplmg at a hrgh rate is- not necessary - CHAPTER S TECHNICAL DESCRIPTION Thrs chapter describes the hardware 1n more detall and explams the functlonal performance of the drfferent circuit elements. It covers the host interface, the multlplexeritself, and the EIA line interface. ~ Signal mnemonics usedin this chapter are the same as those usedin the field maintenance print set. The prefixes foundin the prmt set, however, are not used here. These prefixes refer to the print sheetnumberon - which a signal originates. For example, D6. DVALD H orlgrnates on sheet D6 The pr1nt set is useful but - not necessary for understandmg this chapter | | S | | | Where possrble all figuresin thrs chapter also refer to the sheet number of the field malntenance prmt set where the full schematlc is to be found An example of thlS is shownin Figure 5-1. NDICATESTHAT CSIGNALISINLOGICLOW STATE WHEN TRUE BDINL [ | »{ ATES THAT A INDIC SIGNAL IS IN LOGIC HIGH ~ - 1o STATE WHEN TRUE | CONTROL ~ | RDEVH f——> LOGIC * INDICATES THAT DETAILS OF © " THIS CIRCUIT IS ON SHEET D2 OF THE PRINT SET. RO1B33 Frgure 5-1 Labelrng Conventlons Appendlx A contains pin-for-pm descnptlons of the LSI chlps usedin the DZQII and also the VLSI semi--custom 1C (DC367B) which provrdes most of the functions of the DZQI 1. | 52 CIRCUIT FUNCTIONS ~ T ~ The major functional areas of the DZQll crrcurtry are representedin F1gure 5 2. The numbersin the - o ;blocks refer to the sectlons in Wthh the blocks are dlscussed - | - - Data to be transmlttedon the commumcatlons lmes moves from the Qbus through the bus 1nterface to the o - TDRin the UARTSs. There it is converted from parallel to serial form, and sent to the EIA transmitters. . These transmitters convert the serial data from TTL levels to EIA levels, and send it to the communications line (or modem). The interrupt logic requests service when a transmitter is empty. The - transmitter control determines which of the four specified lines is to be used 1nd1cates Wthh line 1s,1 : ,selected via two CSR bits, and controls the loadmg of data. . | | S I o ».,.,"Data commg from the communlcatlons hnesis converted from EIA levels to TTL levels by the EIA’ B ~ receivers. Itis then converted fromserial format into parallel format by the UARTs The parallel data ~ leaves the UART receiver buffers andis storedin the silo buffer. From there it is transferred to the bus interface. The bus interface places the data on the Q-bus. The interruptlogic requestsservice when the silo ~ buffer has either 1 or 16 characters of received data, as selected under programcontrol The receiver ) control scans the recelver status and controls the loadmg and unloadmg of the srlo . | S o The speed and format control generates clock srgnals for the UARTs Under program control 1t selects | baud rate and stop b1t parlty bit, and character—length parameters o *The break loglc 1nh1b1ts output data SO creatmg a BRK 81gnal The four lmes operate mdependently and' 2 under program control | | | | | The maintenance mode selector prov1des the facrhty to sw1tch the data outputs to the data mputs ThlSIS o used to verlfy module operatlon - | The power supply converts voltages avallable on the Q bus backplane to a negatrve 12 volts as needed by' - | | *._the module [ The drfferent blocks shownin Flgure 5- 2 are descrlbedin more detallin thefollowmg sectlons SNG.‘3OV4HILINI3LVIS-E NOILD3S-B-||-o—B|| 1'Z€G A LINSNVHL 410 ¢vS A s XN NOI13 S ¢SS HADY AS84 NOILD3S PTYS Mv3dg €000Q INIL 1041NOD 1S31 1 |TOHLNOD S Noiwis|N _ o!~8£9g2aB| T31015_a3n1vs~,|3o1lsvae)L| -| ,.| T. . oD| |B vi3 A / dIH-DONO |: o | S | | - -04 | SiH viva vi3 160000 na|s 1tg Y 5N8-0 Al 3AI303Y IOYLNOD l A \ N|OILD3S Z»7ES A|B |y3dng eV ,NONILO3S 5 3 DZQll ro QBUS INTERFACE e 5 3 1 Interface Slgnals F1gure 5-3 shows the srgnalsthat 1nterface the DZQI 1 tothe Qbus and Table 5- 1 defines these srg:nals - S - 5 BDALOO L - BDAL‘I 5L BINIT L - BIRQL BIAKI L CPU BIAKOL - BBS7L - pzal1 BSYNC L ~ BDOUTL BWTBTL ~ BRPLYL CRD1B35 . Flgure 53 DZQll/Q bus Interface g Table 5 l DZQll/Q bus Interface Srgnals L ~ Mnemonic Descrlptlon BINIT L ‘INITIALIZE BINIT L is asserted by the processor to initialize or clear all dewces - BIRQL " Interrupt Request — A dev1ce asserts this signal when its mterrupt-enable and 1nterrupt— o connected to the I/ O bus Thxs 51gnal isgenerated on power-up.. - request flip-flops are set. If the processor status word PSW<7> is 0, the processor | acknowledges the request in response by assertmg BDIN L and BIAKO L o . BIAKIL Interrupt Acknowledge Input and Interrupt Acknowledge Output— Interrupt acknowledge - signal generated by the processor in response to an mterrupt request (BIRQ L). The processor ~asserts BIAKO L whichis routed to the BIAKI L pin of the first device on the bus. If the device iis not asserting BIRQ L, it passes BIAKI L to the next lower priority devicein the e | cham v1a 1ts BIAKO L pm Otherw1se its BIAKO L output 1s mhlblted | ”Bank 7 Select The CPU asserts BBS7 L when an addressin the upper 4K word bank of' ~ | Q-bus address space is placed on the bus. BSYNC L then becomes asserted and BBS7 L [_ o stays actlve for the duratlon of the addressmg cycle | | | | : Synchromze BSYNC Lis asserted by the CPU to 1ndlcate that it has placed an address o _on BDALOO 1to BDALl 5 L BSYNC L stays asserted until the transferis complete R -'Table 5-1 DQZ1 l/QQbus Interface Signals (Cont) | - Mnemonic Descrlptlon | BDINL Data Input - BDIN Lis used for two types of bus operatlons 1. ~ 2 , _When asserted durmg BSYNC L t1me BDIN L 1nd1cates an 1nput transfer and' requiresa response (BRPLY L). BDIN L 1i 8 asserted when the CPU 1S ready to ~ accept data from the DZQl 1. | When asserted wrthout BSYNC L BDIN L mdlcates that an mterrupt operatron isin - | progress ) | . - BDOUT L Data Output - When asserted BDOUT L 1nd1cates that valld data is avarlable on BDALOO L to BDALI5 L, and that an output transfer is in progress. BDOUT Lis ~ deskewed with respect to data on the bus. The DZQll must assert BRPLY Lto complete ~ the transfer. - BWTBT L . | o | Write/ Byte — BWTBT Lis used in two ways to control a bus cycle | 1. Itis asserted durmg the leadrng edge ofBSYNC Lto 1nd1cate that an output sequence | s to follow (DATO or DATOB) 1nstead of an 1nput sequence ». L '2 Itis asserted durmg BDOUT L 1n a DATOB cycle for byte addressmg BRPLY_ L o ReplyBRPLY L1S assertedm response to BDIN Lor BDOUT L and durlng mterrupt- acknowledge transactions. It is generated by the DZQI11 to indicate that it has placed 1ts SR - - data on the BDAL bus, or that 1t has accepted output from the bus R L Data/Address Lines - Theselmes are the b1d1recttonal bus. Flrst the CPU places address | - BDAILOO “information on the bus, then, after the needed device has been addressed, the CPU to - BDALIS ‘L ~ removes the address. Then data is placed on the bus, elther by the CPU for an output ? | | transfer or by the DZQll for an input transfer. ) o Transact1ons between the CPU and the DZQll can be program- 1n1t1ated or mterruptdrrven ~ An mput operation (DATI) is equrvalent to a read Operatlon and an output (DATO) Operatlon 1S equivalent to a write. A DATOB writes a byte. A DATIO cy cle is equivalent to a read-modify-write ~cycle. First an addressing operation is executed, followed by an input word transfer, in a way similar to the ~ DATI cycle. However, BSYNC L stays in the active state after completlng the mput data transfer. This causes the addressed device to stay selected. An output data transfer then follows without any addressing. " After the completion of the output transfer, the device terminates BSYNC L. completmg the DATIO | | }cycle The output part of this cycle can be a byte transfer ‘This is a DATIOB. | S. 3 2 Clrcunt Operatlon 5.3.2. l Bus Interface— Data and control s1gnals move between the Q-_bus and the DZQl ] transmlt | and recelve crrcultry through a group of bus transcelvers multlplexers and latches | The bus transceivers are made up of four DCOOS transceiver chlps These buffer the bus sronals BD ALOO ~ to BDALIS to the device internal data bus lines 00 to 1 5. The device data lines ha\ e three logical states: TTL low, TTL hlgh and drsabled (high 1mpedance) S | - _The DC 00’5 transcen er chlps also decode theaddress and generate the vector The addressis decoded by = - comparing the state of BDALO3 to BDALI 2 with the state of address switches AO3 to A12 (switches1to 10 onswitchpack E28). When a CPU addresses an 1/0 device, it asserts BBS7 L (bank select 7) during - ~address time. This indicates that the addressis in the top 4K words of addressing space, and enables the DCOOS5 transceivers to decode that address. If the address matches the sw1tch selection, the transceivers . .assert MATCH H to the I/O control loglc ~Dur1ng data tlme the transcervers transferdata from the Qbus to the dev1ce data bus llnes 1f the operatron e ~ is adata output transfer If the operation is a data input transfer, the 1/O control logic asserts READ L and ~ RDEV H. This switches the transcelvers mto thexr opp051te d1rectlon where they transfer data from the &devrce data bus to the Qbus | | | , ~ = Sw 1tches VO3 to V08 (swrtches l to 6 on swrtchpack E 1 3) control thegeneratron of vector addresses The . - switches control the state of the vector bits 03 to 08 at the time when theinterrupt logic enables vector B ,generatlon Bit 02, however, is automatlcally controlled by the interrupt logic, and indicates whether a ~ transmltter or a recelver mterrupt is in progress Itis set for a transmltter mterrupt and clear for areceiver o mterrupt 5 When an mterrupt occurs, the loglc state of the vector sw1tches 18 placed on the Qbus lmes The"v SRR transcervers do thlS w1thout the need of READ L or RDEV H from the I/ O control circuit. - - S 3 2 2 1/0 Control ThlS log1c controls the flow of status and data bits between the Q-bus and the R deviceregisters. It monitors the three least—51gn1ficant bits of the address word to determine whichregister ~ is to be read or loaded, and which bytein the register is affected Itmonitors BWTBT L (Write Byte) to | | ~determine if a byte or a wordis being loaded. The CPU can write words or bytes, but reads only words. | ,Control srgnals BDIN L and BDOUT L mdrcate whetherdatais to be moved 1nto the CPU or out ofit. -~ ~ .;Themajor elementin the I/ O control crrcurt is a DCOO4 protocol ch1p ( Frgure 5 2) The ch1p uses blts Ol and 02 of the deVlce data bus to decode the device register address. It then asserts one of the four register | o OUTLB L for a low byte B ~ky If the operatlon i1s an output data transfer ( 1nd1cated by BDOUT L) 01rcu1try external to the DC 367B usesQ - ~ the reglster—select s1gnals (SEDO L to SEL6 L) together wrth e o ol . . | | OUTLB L to produce load pulse WRLB H OUTHB L to produce load pulse WRHBH » OUTLB L and OUTHB L to produce both load pulses L 'ffThrs crrcultry also encodes the reglster-select srgnals to produce RGA and RGB These sxgnals . ~ - | select lines. It uses device data bus bit OO and BWTBT L to| select elther OUTHB L for a hlgh by te. or i o | | (WRLB H.WRHB H, RGB and RGA)are connected to the DC367B chip and enable the appropriate byteor bytes of the device data bus to be loaded mto the selected regxster msrde the DC367B chlp Table5-2 "shows the regrster select1on o L Table 5 2 L H H L H H H "H | e Reglster Selectlon o DCOO4 SEL Lme (Actlve Low) " | Selected ~ L H 56 L L CSR RBUF/LPAR The DCOO4 Chlpis desrgned to connect drrectly to the Qbus and to decode active LOW srgnals at the - BDALOO to BDALO2 inputs. Inthe DZQ11, however, these input pins are connected to the buffered( and | - ~inverted) device data bus lines DALO toDAL2 to reduce Q-bus loadrng Therefore, the decoded outputs - SELO to SEL6 have their order reversed. So pin 17 of the DC004 is now SELO L instead of being SEL6 L, andpin14isSEL6 L instead of being SELO L, and the same for pins 15 and 16. Inthe same way OUTLB L and OUTHB L pins are reversed. Pin assrgnments shownn Appendlx A for the DCOO4 are the standard desrgnated assrgnments o The c1rcu1try extemal to the DC367B also generates two srgnals named WRCSRLB H and WRCSRHB H ~ These are used to write interrupt-enable bits into the DC003 chip. These bits are also copied in the DC367B chip via the RGA RGB decoding process, and are available for read-back purposes. - WRCSRLB L is also used together wrth DALA (CSR b1t 4) to generate Master Clear MCLR L and | ’MCLR H ’If the Operatlon IS an 1nput transfer 1nd1cated by BDIN L, the reglster-select lmes are also used to load ~ data from the device data bus to the Q-bus. The I/ O control generates a load pulse appropriate to the o correct register, and asserts READ L and RDEV H. RDEV H causes the DC367B chip to placethe data - from the selected register on the device data bus (Table 5-3). RDEV H and READ L togetherenable the ~ bus transceivers to transfer the data from the device data bus to the Q-bus (Table 5- 4) All those bits | | : | ~shown as Not Used’ m Figure 3-1 are held at zero by the DC367B log1c Table S- 3 READL RDEVH Transcelver Swntchmg Mode H e L e "‘,'Q—bus to device data bus o ' | Does not occur s | H. H - . ‘ L | ) N L o s ' Qbus dlsconnected/devrce databus open Device data bus to Q-bus Input Operatlon — An 1nput data transfer (DATI bus cycle) proceeds as follovxs 5 3.2.3 1. The CPU places the device address on Q-bus lines BDALOOL to BDALl5 L. and asserts BBS7 L. - BWTBT L is negated at this tlme because all mput transfers are full words (Figure 5-4). 2. The bus transceivers are configured to receive from the Q“bus unless swrtched othermse . o BBS7 L enables the transcervers to decode the address and to assert MATCH H W hth o | R enables the 1/ O control circuit. 3. The CPU asserts BSYNC L. The leadmg edge ofBSYNC L latches the states ofMATCH H _V - N 4. ~ anddevice data bus b1ts 00 to 02 into the protocol chip. These are decoded to produce SE 10 L to SEL6 L. | | | | | | - Next the CPU removes the address from the Q bus lmes negates BBS7 L and asserts " BDIN L.BDIN L causes the I/O control to generate READ L and RDEV H. These signals place the contents of the selected register on to the device data bus and the Q-bus. BDIN L also generates BRPLY L. ThlS mdrcates to the computer that the data is on the bus | _5; The computer:reads in the data, and thennegates BD.IN' L. B | | | o 6. | ‘f‘.The 1/ O control loglc responds to the negatlon of BDIN L by negatmg BRPLY L o e o 7 ';The CPU termmates the bus cycle by negatmg BSYNC L Co 8 V_When BSYNC L becomes negated the protocol ch1p releases the reglster selectlon lmesand the READ L and RDEV H signals. The bus interface returns to its normal condmon of B rece1v1ngfrom the Qbus and transmxttmg to the devnce data bus | . BWTBTL >’ ~ | Frgure 5 4 RD1836 Data Input T1m1ng 5. 32.4 Output Operatlon — The DZQll can acceptdata from the computerm e1ther bytes or words : To write a wordout to thedevice module, the CPU performs a DATO bus cycle. To write a byte it B performs a DATOB bus cycle (F1gure 5- 5) An output data transfer proceeds as follows o | f_ 1 - The CPU places the devrce address on the Q_bus and asserts BBS7 L and BWTBT L. (Durmg o ~ ( ~ address time., BWTBT L is asserted for an output operation and negated for an input operation.) BBS7 L enables the bus interface to decode the address and assert MATCH H to the 1/O - ‘control The bus mterface also apphes address blts OO to 02 to the I/ O control 2 .The CPU asserts BSYNC L. The leadmg edge of BSYNC L latches the states of MATCH H - and bits 00 to 02 into the DC004 protocol chip. If MATCH H is asserted, the Chlp decodes the | ',»reglster address and asserts the approprrate select lme LA 3 | The CPU removes the address from the bus lines and negates BBS7 L. If a byte is to be - }transferred BWTBT Lstays asserted Ifa wordis to be transferred BWTBT Lis negated el _.’At thxs time. theCPU asserts BDOUT L, Wthh allows the DCOO4 protocol chrp to decode the 3 ~ statesof BWTBT L and the latched-in address bit 00. The DC004 uses the signals to assert L - either OUTHB L or OUTLB L, or both, for word transfers (Table 5-4). These SIQnals are T used thh SELO L to SEL6 L to wrrte to the apprOprlate regrsters | | 5 After the DCOO4 chlp recerves BDOUT L 1t 1n1t1ates the Bus Reply s1gnal | .5,-8*__ | o \ [ J( o BDALXX L BSYNCL L | | x e SR 4200\ Y WRHB H/LB H - - 200 TO 300 ns 45 ns MIN | @ ~ INTERNAL WRITE PULSE 7~ RN BDOUT L | 'B"RP_LY'L BWTBTL i ., - — ‘ \ f - -’Lov’v-._=eYTE - Flgure 5 5 | Data Output T1m1ng 6. Next, the CPU removes the data from the bus llnes and negates BDOUT L 7. The DCOO4 ch1p responds to this by negatlng BRPLY L 8 | _The CPU then termmates the bus cycle by negatmg BSYNC L and 1fapphcable BWTBT L | 9. ’When BSYNC L is negated the DCOO4 ch1p negates the reglster select and bvte hnes ' Table 5 4 . BWIBTL Byte Selectlon (Output Operatlon Only) Internal DALO0 | 'Slgnals Asserted | Bytes Selected ~and 'OUTHBL L L OUTLBL 'L_ H v'OUTHBL ‘ | High - 5.3.2.5 Vector Operatlon— The I/O control has the addmonal function of assertm0 BRPL\ Lin response to VTB H from the interrupt control circuit. This action is part of the interrupt sequence. andis . 1ndependent of the BSYNC L and MATCH H. It is d1scussed in Sectlon 5.3.2. 8. fi-» 5.9 o 53. 2 6 Imtlaltze Cll‘Clllt - Extemal to the DC367B a wrrte to CSR<4> starts a2. 4 mlcrosecond( ///v T - one-shot which asserts MCLR L (Master Clear) for the DC367B, and also clears the DC003 chip. The T Q-bus BINIT L srgnal also clears the DCOO3 chlp and generates MDMC L (ModemClear)for the o i - DC367B x MDMC L1S connected to pin 8 of the DC367B ch1p and dlrectly clears the modem reglster b1ts (that1S, - DTROt03); MCLR L, connected to pin 7, has no effect on these. Thereafter, both clears are ORed inside ~ the DC367B and synchromzed to the system clock to provrdea MASTER CLEAR signal for CSR<4> -read-back purposes. The resulting read-back pulse is about 2.7 microseconds long (thatis, about 300 nanoseconds longer than the original), When this clears 1tself 1n1t1alrzatron1S complete on the DZQl I. B Frgure 5-6 shows detalls of these srgnals SR | BITO4 [ | o | 2aps ONE-SHOT | Rt g — BINIT (TO DCOO3) BINITL - MODEM CLEAR L - Flgure 5 6 RD'838 Imtlaltzatlon Slgnals - S, 3. 2 7 Interrupt Loglc — Most of the log1c for 1nterrupts 1S contamedin the DCOO3 mterrupt chip ~ o ) (Figure 5-7). The DC003 ch1p contains two mterrupt channels, one for receiver interrupts and one for transmitter interrupts. The circuit generates a receiver interrupt either when the RBUF has 1 character read} for the computer (Recelver Done 1nterrupt) or when the srlo buffer has 16 characters ready (Szlo | Alarm mterrupt) ~ The Recerver Done 1nterrupt 1s enabled by bit 06 of the CSR The leo Alarm interrupt is enabled b} ‘_ setting bit 12. Setting bit 12, however, inhibits the Receiver Done signal from the RBUF. Therefore o Recelver Done mterrupts do not occur when SllO Alarm 1nterrupts are enabled . & H O 1 D I A 1 9 2 0 ‘ H 3179VvN3-1 45D19'90 3| To DIA3aVv1ivdaH1vlLSsOS-H ng ~ SNg 90 ~H e \ enjen e SEafus evE—— _ 103vIg Sm— _ _ O|WIavSiv | | _ _ HSD -118 "L"f—"-—_—___—_"_“'—— 'SnN8-0 511 m—— " _. _ t e _ _ _ _ | 3H1OIAH8 HTILIWLdNHUYILNI378vYN3 SNE-01-HO0LI N H af HSD 1 8 V1 ? 21907 - <L CE8LAPASAILA CHILLIN ' I0OV4HILNI 3 0 I A 3 0 1 i v a -V 11 YT T o3 =TINYHDT0_4L1N.ODCHILLIW 'SLINDHID 104id - 1NIa8 - 7,v5ig98Ii vOoISWnEVTY378YNH3ILHI"NSN3V0H1LA3A.,0Q2Vavn313Hv1aH,].£L0~0uL_dwNoYq.3yLmN:It&di:H.D_|HS1:0SN8AW-s)n|whHrSN18-0LHOLIA S1-:0 1va BRYEYSEREY B TINNYHD LdNYHILNI 1d.NYHILNI dnuyaiTnMi1 e _ 3ZI1VILING - <l 10YLNOD T1INIG A1NdHE |afl§- The circuit generates a transmrtter mterrupt when a TDRis empty and ready to accept another data output- - ’from the computer The Transmrtter Ready mterrupt is enabled by settmg CSR b1t 14. | Both the Transmttter Interrupt Enable (TIE) and the Recerver Interrupt Enable (RIE) bltS are located _' | . | fphysrcallyin the DC003 interrupt chrp, although they are functlonally part of the CSR Also for read- _back purposes they are duplr catedin the DC367B Chlp ,- The Q-bus Interrupt Acknowledge srgnal (BIAKI L/ BIAKO L)is darsy-chamed through the devrces on | - the Q-bus. Device priority is fixed by the position of the devicein the Interrupt Acknowledge daisy chain. ~ - Inthe DZQI11 interrupt loglc this chain goes through both the receiver section and the transmitter section of the DCO03 chip. It passesthrough the receiver sectlonflrst thereby grvmg receiver mterrupts prrorrty over transmltter mterrupts 5.3, 2 8 - Interrupt Transactlons - When mterrupts are enabled and a condmon occurs Wthh needs o i'servrce the mterrupt sequence proceed s as follows 1 2. ." vThe 1nterrupt logrc asserts BIRQ L the mterrupt request lme (Flgure 5 8) The CPU responds to BIRQ L by assertmg BDIN L and then BIAKI L. BIAKis the bussed. » ~Interrupt Acknowledge signal. Itis passed down the priority cham untrl it reaches that sectlon of - the mterrupt ch1p whrch 1n1t1ated the request - 3. ~ - - - - \ When the mterruptlogrc receives both BDIN L and BIAKI L it asserts VTB H ( vector to gy bus’) to the vector selection swrtches If the interrupt is a transmitter interrupt, the circuit also asserts VBIT2 H. This signal adds four to the base (recelver mterrupt) vector thatis asserted by VIB H. The c1rcu1t also negates BIRQ L. o » | - ER | 5 4. "_,»',VTB Hcauses the I/O control logic to issue BRPLY L to the CPU VTB H causes the busfi o transcervers to place the selected vector on the Q bus lmes Lt 5. .- ‘The computer reads in the 1nterrupt vector, and as a result of recelvmg BRPLY L, it thenl | 'negates BDIN L.Shortly after thrs it also negates BIAKI L. - | 6. The 1nterrupt loglc negates VTB H and VBIT2 H, if apphcable T ":'Thenegatlon of VTB H causes the 1/0 control logic to negate BRPLY L. and the bus | - o - transceivers to. remove the vector from the Q bus lmes | o "-'Anmterrupt transactlon does not need BBS7 L MATCHH BSYNCL orREAD L The mterrupt loglc{ ~ overrides the normal I/O protocol S - | '_ '__A Silo Alarm can be 1dent1f1ed from a Recelver Done mterrupt by checkmg the SIIO Alarm Enable (SAE) - - bit (CSR bit 12) when entermg a servrce routine. | - BSYNCL (UNASSERTED) - BBS7L e S » (UNASSERTED) PR 54 LINE MULTIPLEXER "FigureS—S ;Interrupt Timing | o | 54.1 Hardware Description . o | ~Allfour UARTsS, the baud-rate generators and the control logic are 1ntegrated w1th1n the DC367B Tl’llSis | ~a semi-custom IC containedin a 68-pin plastlc leaded chlp carrter (PLCC) The Recelver F IFOs are ~ external to the DC367B - '_ | | | o S, 4 2 UARTs and Control ~ S. 4 2 1 Recelver Operatlon — The UART (Unlversal Asynchronous Recelver/Transmltter) receiver section does the serial--to-parallel assembly of received characters for each line. It also does parity checking, break detection, and overrun detection. Each UART is double buffered allowmg a full character—ume to remove the received character to a hardware buffer. N | The UARTS are serv1ced by a sample-and hold search-prlorlty circuit. Samplmg priority of the data- ’_ available flagsis highest for line 3 and lowest for line 0. Sample and hold times are separated by 100 nsto allow for Priority Selection settling times. When a flagis found the control logic dep051ts the character* 1nto a 16 x 64 Flrst-In Flrst—Out (FIFO) buffer. ~ - -Serlal data commg in is apphed to the receiver section of the selected UART, which samples the serial input at the receiver clock rate (16 times the data bit rate). A lineis in a continuous marking state when idle. When a start bit arrives, the UART detects the mark-to-space transition. It samples the line again at ~ the time correspondmg to the middle of the start bit. If the lineis marking, the UART logic assumes that the first sample was noise and continues sampling. If it finds that the lineis still spacmg however, the lOOlc assumes it is recetvmg a start bit, and enters data-entry mode. | In data entry mode the UART clocks data b1ts sequentlally into the approprrate bits of the recenmo register. prarlty has been enabled, the UART checks the total of the received data bits plus the parity bit. ~ (It checks for an even total if even parity has been selected, and an odd total if odd parity has been selected. )A panty error causes the UART to set the parlty error—flag b1tin the hlgh b\ te of the RBUF o word. If it is marking, the UART logic * The UART checks to see if the line is marking at the stop-bit time. UART sets the framing-error-flag bit. If the line is spacing instead, the - assumes there is a valid stop bit. thes received character, the parity-error bit, About half way through the stop bit time, the UART transfer - and the framing-error bit. from the receiving register to the holding register. At the sametime, it assertsthe ~ Data Available signal to the receiver control logic. If the previous character has not yet been serviced by * the receiver control logic, the UART sets the overrun-error-flag bt to indicate that the previous character - ~ was lost. It can only be recovered by retransmission. . o ~ The r'e_cl'eiver, cfontfol lof‘ad’_s‘v'the cont.en'tsr'of" the RBUF (djata_‘fland status) into the FIFO buffer fo'r:tranSfe‘r“ to ~ of receiver interrupt to request. the computer. The receiver control circuit determines when and what type 5422 Cdntrbl —"'~;:Fi‘g’ure}549j 'Shows ajbloc'k "diag'r“am‘ of the '.'r’e.'ce'iVé‘r,'c_br.ltverIi_séct‘ion of the R 9442 Receiver - DC367B chip. The function of the control section is to scan the UART status and place UART data - together with the line number and error information in the silo buffer. At the same time, it also indicates - receiver control status (RDONE and SILO ALARM) to the CPU via the CSR, and, if enabled, receiver i T i s i T Lo mterRUpt o to that of the"Tran'sm_i;t c'ontro_l,logic_— it'w_c)rks on a pfiority basis. Line 3 has R Thé scanning log‘icv: is similar B " the highest_ priorfli_ty, and line O the lowest. The following table ;(‘}T'ableFS-S) shows the pins of the DC367B chip that are associated with the“receiv'ejr - control function. - Table 5-5 DC367B Receiver Comrol's.i_g.ial‘sf_ L Pm S 36 o 3;7. ,‘ ) - | i Description Signal FE3 H o IR - RINT H ‘ FramingError Line 3 Output | L Vafid Ou.tput S RCCéiVlef Interrupt Output - 40 A o " = sA’H123;V H SLDSH st SHIOIH ~~ SLDOH and Bit 6 Output Bit 7 a toSilo Dat toSilo DataBit5 to Bit 0 Output Shift In Pulse Ist Byte Output B 54 B | ORDY H Out Ready Input o 64 SLCLRL ; Shift In Pulse 2nd Byte Output - g . 41w42 SLDTH 45150 o Silo Clear Output ~ HETZLHS 3N H£3d -— XN A A # INI 'd3.10313S | - HO012313S /e A 8¢ o 0U 9¢€ A —— [/ H(£-0 - 5-15 A / A sample pulse is generated every 400 ns in the:DC367B,'from an internal clock. The sample pulse - strobe the s highest-priority active UART which has an assembled character. A shift (SHIO1 H)pulseis T - generated 300 ns after the sample puls as long e, as IRDY is High (the FIFO is not full). SHIO1 Hcan occur as early as 300 ns after the character is assembled, or aslate as 700 ns after, because the received character is not synchronized with the internal clock. The SHIO1 H pulse loads the data into the FIFO. ~ B * The second shift pulse (SHI23 H) is generated 800 ns after the leading edge of SHIOI H. Thissecond pulse loads the status information into the FIFO. T ~ The FIFO buffer is made up of 4-bit-wide chips. Data loaded into each chip starts to ‘bubble down’ as £ soon as it is loaded. The FIFO is 16-bits wide; two chips (E10 and E30) are loaded by SHIO1 H, and “another two (E4 and E17) by SHI23 H. The contents continue to ‘bubble down’ after the second o pulse (SHI23). During this time, the chips hold IRDY low and-’prevent; the next UART shift from being ~ sampled. The worst-case ‘bubble-down’ time is about 2.0 microseconds, after which IRDY again goes high. Figure 5-10 shows the timing relationship between these signals. =~ The FIFO buffer is ‘-c»_:il‘ear'ed of all data by the.s-i‘gnal””_SLvC'L:R' L. The buffer become»s*empty‘,’ and prévidés o ~space for 64 characters; IRDY H becomes asserted and ORDY H is cleared. The signal SLCLR Lis ~ generated by the register latch which corresponds to the Master Scan Enable bit of the CSR(CSR<05>). ~ So long as CSR<05> stays clear, the FIFO buffer is disabled in the clear condition. Therefore CSR<05> must be set to allow Receive and Transmit control operation. It is automatica lly cleared by ST Master Clear and by BINITL. R __.ll.ioo_ S "'SH'OT H'». - / e,oofilL '.2‘00' T R R N T / | X -— B N SL_b(o-m H | X 1 DAfA LINE 3 x STATUS x X ~ - RINTH | ._ o '» .»IQVA‘TA‘AV3 . / BN » ) . x X'DAfAL:NEé.x STATUSfiX" SEE NOTE 2 SEE NOTE 3/ R © NOTE 1. ASSUME LINE O AND1 DISABLED. LINE 3 HAS PRIORITY. - NOTE 2. FIFO "BUBBLE-DOWN" TIME MAY BE UP TO 2.0 MICROSECONDS. NOTE 3. ASSUME 16TH CHARACTER. AND SILO ALARM ENABLED. ~ o Figuré 5-10 | Recei_v'e'r Com'r‘_ol Timing Diagram R 5.4.2. 3 Transmltter Operation — Durmg idle time, the UART transmits a contmuous markmg sngnal | and holds the Transmitter Ready signal asserted. The transmitter control cxrcultry uses thlS 51gnal to : 'determme when to 1n1tlate atransmltter 1nterrupt request ~ | _When the computer has data to transmlt toa commumcatlons 11ne it uses a DATOor DATOB sequencef | to address the Transmit Data Register (TDR) and to place the data on the bus lines. The low byte of the | TDR word is loaded mto the holdmg register in one of the four UARTs mtemal to the DC367B | When the data entersthe holdmg register, the next DC367B 1nternal clock transfers the data—-in parallel — from the holding register to a transmitting register. It then produces a start bit, followed sequentially by the - data bits from the transmitting register, least-significant bit first. The data bits may be followed by the ~parity bit, depending on the LPR settlng, and then the stop blt(s) These b1ts are fed vra the break/test o select logic to the EIA level converters. " The transmltter hke the receiver, is double buffered Therefore it can be loaded thh a second character - 'before the flrst character ‘has been moved out - so g1vmg contmuous transmission. - 54.2.4 Transmltter Control— The transmltter control circuit checks the transmitter control reglster | : (TCR) to determine which lines are enabled. It checks the UARTS to determine which are ready to accept new data for transmission. It also enables the loading of data from the CPU to the highest-priority UART. Table5 6 shows the plns of the DC367B ch1p that are assocxated w1th the transmltter control function. - Table 5 6 DC367B Transmrtter Control Sngnals - Pin Signal 32 - WRHB H . Descrlptlon | 'erte ngh Byte Input Write Low Byte Input B WRLB H 33 | o ‘» ‘ 30 - ' | RGB o Select4'o‘r61nput || 3l 39 | N B | n Select2 or6 Input | RGA TINT H ' | | Transmltter Interrupt Output 62 to 63 " »BDTRLZI, : Data’Terminal Ready Output .’Line2 and 3 ) 651068 BSDOO H to - Seri‘al Data Qut Output LineO to Line3 “59 to 60 d - BDTRI_O L | Data Termlnal Ready Output Llne 0 and l | B’SDOSH ) Flgure 5-11 shows a block dragram of the transmltter control SCCUOH of the DC367B Chlp An 1ntemal clock perlodlcallv samples the state of the four Tx Ready lmes of the UARTS This sampl together with the LINE ENABLESs (from the TCR). is applied to a priority selector. This selector chooses ~the hlghest—pnonty line whichis both ready and enabled. Any output from the priority selector setsbit 13 ~ inthe CSR, and asserts TINT pin 39, whichis connected to the DCOO? Interrupt chip. Thlq indicates to ~ the CPU that service is needed , | o s l . While the CPU is responding to this service request, a UART of a higher-priority line may also become Ready. In order to pre the priority ven selector t from changing its output before the - ( o completion of the S service already in progress, the sampling clock is disabled as soon as an output first appears from the ~priority selector. The sampling clock stays disabled until the service routine loads a new character tothe ~waiting UART transmitter. e The output from the priority selector also gates the load pulse so as ’vtodiréCtthe‘data from the device data - bus into that UART which is waiting for service. o Lt __ - - 91117202628 DEVICE . IR Bus I . -2 7 | | B B 1 ) _' TCR S o UNEENABLE 4 , Y W SRR e - 7 TLINE AT , A | SELECTOR [ ENCODE| R / | ] s| TX READY 4/{’ ,CSR,leI» - BIT9 ] SAMPLE " | ENABLE A m — s TuNESB ; cLock 2 e o . | SRR I WRLBH 33— 1 ~ WRHBH 32 a Figure:S-‘lal ».Transmitte'r—Control- Block Di-agram BT . to o Ifthe service routine disables the ‘vline" whose UART is waiting for service ( when transmission i scomplete), R .‘thejsampling clock is again enabled without the need to load a new character. This is done by additional wol - logic, and prevents the service request from permanently staying on that one line. = - L N ~ When a LOAD TCR is performed, the INTH ~ signal is cleared and , is not set again untilanew - character (or line) needs servicing. G e ST ( Flgure 5-12 shows the timing relatlonshrp between the dlfferent pms of the DC367B that are assoc1ated | B | SEae , | | | 'w1th the transmltter control function.. | Agam as with the Recerver Control crrcu1t the Transmlt Control operatlon is drsabled whlle the Master - Scan Enable (MSE) bit stays clear. Because the MSE bitis cleared on power-up by BINIT L ( or on Master Reset) this b1t must be set before the Transmlt Control operatron can start. CSAMPLE L CLOCK AT /—\ _/_\ SAMPLE Hl l/_\ _ SAMPLE DISABLED T 100 TX READY 1 ""/ o JLLL \ | JLL1 B SEENOTE1 "7"”/l L " TX READY2 o w § CTINTH " WRLB H/WRHB H (TDR) TLINEA/B — x* — X:X_ 2~ ¥ ———» SERVICE RESPONSE | "TIME fe—— SERVICE | ——= RESPONSE |= ~ T_IME. NOTE 1 - LINE 2 HAS HIGHER PRIORITY. ASSUME LINE O AND 3 DISABLED - . NOTE 2 — TINT IS HELD OFF DURING WRITE TO TCR PULSE - - NOTE 3 = ALL TIMING EXPRESSED IN NANOSECONDS Flgure 5 12 5 4. 2 5 — | (TCR) (CSR08/09) . V a0 | " WRLB H,'WRHB H Transmltter Control Tlmmg Dlagram Break (BRK) Bnts — The transmlssron and receptlon of BRK bits are closel\ related to the transmission and receptron of data. A break signalis a continuous spacing condmonin the serial data line. ‘When a UART receives a break signal. it interprets the continuous space as a character with a missing - stop bit. Therefore, it sets the frammg—error flag. The program then determmes how to handle a frarnrm‘ - error. . | ~ » : - The frammg—error bit of ehannel 3 may be connected (\1a an 8881 drrver and sw 1tch settmO) to either BHALT L or BDCOK H, to halt or boot the processor. This could also be done by program after normal readmg of the framing error via the recerver buffer but the hard\x are method gn es an 1mmedrate I'ES}')OH\L. B AibréékSighal.‘m'a'y’be transmitted by_i,n-tér'rupt‘ihgthé}fIOW‘_Ofsverial'data leaving the UART. The high byt'e_, ~ of the TDR can be considered as a break register. It contains one BRK bit for each of the four - communication channels. Setting one of these bits inside the DC367B will inhibit the flow of data fromthe 'UART transmitter to the EIA transmitter, and so cause a Break to be transmitted on the communication ~ line as soon as the break bit is written. Break is removed as soon as the break bit is cleared. =~ ~ 5426 Speed and 'Fm?mét‘;_Con'_tr‘(.)l' ~ The sections éontrolling _svp»ee'd_“.and format includefour line- parameter registers (LPRs), a baud-rate generator with four baud-rate selectors (one for each line), and - chip test-select logic which allows an external clock to be used instead of the baud-rate generator. - When the comp writes utaer word outo the LPR, the =~ following events occur, byte writes having noeffect. ‘1. During address time, the b‘u's'.inte;rfavce and I/O C()‘ntrjoil"_.c_ir'cu'itry‘dec'od'e ,the'ad_drefiss and set RGB and RGA to 0 and 1 for the DC367B chip. - 2. Duringda time. data bits ta 00, and 01 (with bit 02 low) are decod to enable ed one of four strobe ~ gates. 3. ’4»;.Bitsr'03 to 07 are s_ffbbed into the apfimpriaté UART t’o'lis,elec't the :n»umbe‘rv of d/a_ta bits, the - number of stop bits, and odd, even, or no parity. . 4 . Bits 08 to 11 :,a're.'strdbed into the apptopriate ‘ba'u‘d—:‘r'ate selector to control the'am'(junt by which ~ -the5 MHz oscillator (connected to pin 6) is divided to produce the UART clock signal. Bit 12 is also latched here for the selected_ line to enab\le/disable'the receiver clock. In 'this'w'a'y'the four functional LPRS are partly in the_UARTS ‘and»par_t‘ly ihv't‘he ba_ud;rate},genérators,'_all n ~ within the DC367B chip. - ~ Inputpin 57 on the DC367B (TSTO) providesa means of operating the chip atabaud rate of either 19:2K baud, or 38.4K baud. By removing the normally made jumper at W10 and installing a jumper at W9 (so ~ ~ placing a HIGH on the TSTO pin) the internal UART baud-rate input is taken directly from pin 56 5 MHz input via the internal divider. A crystal oscillator of 3.6864 MHz at Y2 ~ drives a divider chip (74LS92) at E3. Jumper W11 must be removed. With jumper W12 installed, the (ISTCLK) instead of the - - ~ - divider output connects to the TSTCLK input to provide 38.4K baud operation. With jumper W13 connected instead, the divider provides 19.2K baud opera These tion. speeds can be selected for any line Dbysettingbits8to 11 ofthe appropriate LPR toall 1s. Those lines with a different speed-code selectionare not affected. Theposition of these jumpers can be found from the print set. | 'V”NOTE.'f {7 - Neither the 3.6864 MHz crystal oscillator nor the divider chip, 74LS92, are installed or tested atthe | factory. They must be provided by the user if ~ wanted. ‘v NOTE . Still higher speeds can be obtained by providing - external clock sources. The DC367B chip can ~ ~ operate at up to 230.4K baud when pin 56 is connected directly to the oscillator at Y2. This is also not a supported option, and is not factory- tested. L 520 | | =~ o : ~ For test purposes itis possxble to select the baud rate generator output from the DC367B chip mstead of the serial data/break output. This can be done by placing a High on the test selector ( TESTl H) Wthhis | | normally hardw1red to ground (de-selected) on the PC board | _ S. 4 3 FIFO Buffer 5.4.3.1 FIFO Descnptlon -The FIFO buffer functlons as follows If.space is availablein the buffer - acharacteris written into it. The character then automatlcally propagates downto the first available open slot. Ttis stored there until a characteris removed from the output side. Remammg characters propagate toward the output. Each characteris stored with the followmg format. The data bits are storedin the low - byte or first eight bits, the channel numberis storedin two bits, and the status information (parity, overrun, . ,and frammg error)is storedin three bltS of the high byte B1t 15 when present mdlcates a valid entry - Once any character reaches the output of the buffer a RCCCIVCI‘ Done occurs. ThlS md1cates that a serv1ce B ~ routine may read the buffer to get the character. When the character has been read, a Shift Out pulse (SHO H) causes the contents of the FIFO buffer to propagate down S0 presentmg the next character at | | | | the output of the buffer. B - _The Recelver Done flag1S servnced by the software e1ther on an mterrupt ba51s orona flag—checkmg basis. Either way, the service routine should process all charactersin the FIFO to prevent overheads caused by “entering and leaving the service routine. The service routine affects only the output ofthe FIFO buffer and | ~does not affect the receiver control search logic. | 5.4.3.2 FIFO Operatlon - The silo bufferis made up from four 4-bit X 64 type 3341 serlal memory (o | chlps The chips are arranged as a 16-bit 64-word-deep first-in- first-out (FIFO) memory. Datais entered inthe"* t0p of the memory as describedin the previous section. The IRDY H signal indicates that thereisa space in the top word of the memory. Also, the ORDY H signal 1nd1cates that a wordin the "bottom’ of the - FIFO s wa1t1ng to be shlfted out. and recen er status’ | “The buffer stores full RBUF words Recelved character datais storedin the low byte | data in the high byte - L o - | As descrlbedin Sectlon 5. 4.2.2,the DC367B shlfts datainto the FIFO buffer e1ght bits at a time. Firstthe Jow byte (data)is shifted into the chips at E10 and E30 by signal SHIO1 H; then the high byte (status)is shifted into the chips at E4 and E17 by the signal SHI23 H. This dual operation multiplexes the 8 bit data - _ »bus between the DC367B and the FIFO SO reducmg the DC367B p1nout | ‘The total sh1ft—1n t1me is l 6 mlcroseconds (800 ns per byte). The shlft—m pulses are about 600 ns lonfi leaving 100 ns for data-settling time before the shift-in pulse and IOO ns data—holdmgtlme afterthe pulse. Refer to Figure 5-10. - S | - Datais shxfted out by the CPU as a result of exther a Receiver Done 1nterruptor flag. or a Silo Alarm interrupt or flag. When O/P RDY from each of the FIFO chlps is set, ORDY H becomes set. Thisis apphed to the DC367B Chlp Loglc 1n51de the DC367B gates ORDY H to the output pin RINT as long as SllO Alarm Enable1S clear | Therefore RINTH follows ORDY H directly. If Silo Alarm Enable is set. however. RDONE is - prevented from assertmg RINT H. It canonly be asserted by Silo Alarm on the 1 6threceived character. | RINT H goes to the mterrupt loglc ch1p DCOOl whrch produces a Recen er Interrupt 1fthc RlE bnis stt in the CSR | | | — - Data output from the FIFO bufferis applled to the mtemal DAL bus (and from there to the BDAL hnes of | ~ the Q-bus) when RDRBUF L enables the tri-state buffers at E31 and E32. The datais valid onlyif, atthe ~ startoftheread trme(start of RDRBUF L), ORDY H is set. If not set, it will indicate an empty FIFO. Itis possible to read a character too soon after the last read from RBUF, while the next characteris still - | bubbling through A 2-microsecond gapbetween consecutive readsis needed to prevent this. The state of ORDY H is latched during the RDRBUF L period, to prowde an indication of the vahd/mvahd o | ~ condition, andis presented on line DAL1S H. This bit appears in the RBUF reglster butis physxcally . - generated inside the DC367B chip. The Data Valid bitis generated justas 1t 1s read whlle the other bxts1n\; o | . the RBUFare generated earlter - as the character1S recetved o The trarhng edge of RDRBUF Ltrlggers the one-shot at E9 to produce a shtft—out pulse SHO H but only if o " the Data Valid bitis set (DVALD H s high). This causes the next characterin the F IFO tobubble through . | ~ to the bottom of the FIFO, ready for the next RDRBUF L srgnal If DVALD H is not set, no pulseis generated, and the FIFOis not affected. Also, if the FIFO is empty, no pulseis generated because Data 2 = VahdIS prevented from berng set. The SHO H pulse is about 200 ns wide. | | | R " Frgure 5 1 3 shows the t1m1ng relatlonshlp between the dlfferent srgnals assocrated w1th the F IF O buffer ey - BUBBLE- DOWN TIME ~ ORDYH PR \;,‘_FI‘FO EMPTY | 'RDRBUF L ~ SHOH v ."s,_b-t l‘ ZOOns‘ ~ NOTE: DVALD IS PREVENTED FROM CHANGING DURING RDRBUF L TIME © - RDYBA4AS | - :F’igur_e 5-13 - S. 4 4 MamtenanceMode - FIFOVOutput Timing | - o T .. ~ The DZQ11 can be switched to receive the data thatis bemg transmrtted The four senal data hnes leavmg | the UARTS are applied to both a data selector and the EIA transmitters. The data selector controls the o mputs tothe UART|receivers. In the maintenance mode, the data selectorignores the inputs from the EIA receivers, and routes, instead, the output data to the UART receivers. This internal° wrap-around feature s enabled by setting the Mamtenance b1tin the CSR bit 03 All the approprlate loglc is inside the DC367B Chlp < | 522 ” 55 LINE INTERFACE ) 5.5.1 | | | S o Descnptlon The DZQI1 line interfaceis a sxmple set oflevel converters. All line input 51gnals are fed into EA9637-’ _- type chipsat E23. E22, E34,E38, E37, and E35. Each of these chips is a dual-channelreceiver designed for EIA-compatible 31gnals All line output signals are fed to EA9636-type chips at E19, E20, E21, E24., E36, and E39. Each of these chlps IS a dual channel transmitter also de51gned for EIA- compatlble ~ signals. "~ When the DZQ11is used to mterface w1th alocal termma] it is common practlce to make use of only the Transmit Data and the Receive Data circuits. When 1nterfacmg with datasets (modems), however, the DZQ11 monitors two other signals, and can control one other signal. The one controlled signal can be - : jumpered so as to control two additional dataset circuits. The resulting three controlled circuits, however, can only be controlled together and not mdependently Table 5-7 defines the modem control and status o sxgnals and describes their normal functlon Table S- 7 -‘Signal- . o Functlon Modem Control and Status Sngnals | | | Data Termlnal Ready Enables the local modem to be connected to a remote modem Th1s 51gnal is negated to terminate a call. | Request To Send'h i Holds the modem in the transmtt mode | | : ‘ Used with Bell Model 103E and 113B equlpment Stgnals the modem controll Forced Busy | | - toswitch to another channel. s ’Ring Indlcator R .Indlcates that the local modemls recelvmgarmgmgslgnal fromaremote modem | Carrier Detect | | _. Indlcates that the local modem is recelvmg (Recelved Slgnal a 51gnal from Va remote modem. and that the Detector) sxgnal meets the su1tab1hty criteria oftheA .local modem | | | | | - 552 EIA Receivers ~ The DZQI11 receives three modem s1gnals foreach of the four commumcatlons hnes that it 1nterfaces Carrier Detect, Ring Indicator, and Receive Dataare received and conv erted from EIA levels to TTL “levels. The Carrier and Ring Status signals go to tri-state buffers, and are placed on the device bus DAL lines to be read as the Modem Status Register (MSR). The Receive Data signals go to the DC367B chip 'where they connect to the. mdmdual UARTs (BSDIO H to BSDI3 H) Refer to Flgure 5- 14 (3-STATE BUFFER) |carmErpeteCcT| |MODEM| RING INDICATOR | | o gjato.rri| RmRI | RECEIVEDDATA | "~ "~ | | MODEM | REGISTER B (3-STATE BUFFER) | MAINTENT | DATAIN[ANCE | SERIALIN_ | T - | - | | The DZQl 1 has three modem control hnes for each of the four commumcatlons lmes 1t mterfaces The Transmitter Control Register (TCR) carries a single control bit for each of the four communications lines. B ~ - Thisis converted from TTL level to two EIA levels, by means of two converters for each line. One EIA levelis always used as the modem Data Terminal Ready (DTR) signal. The second level may be jumpered to provide a modem Request To Send (RTS) signal. The EIA level RTS signal may also be jumpered to ~ provide a Forced Busy signal for use with Bell 103E and 1 13B modems (or equivalent) if necessary. All ) - L |SELECTOR | Figure 5—14 EIA Receivers' | | 5. 5 3 EIA Transmltters ~ . IMODE DATA[TM 1 . RBUF three control signals are derived from the single control bit, and are therefore not separately :programmable Refer to Frgure 5- 15 - , | The DZQI 1 Transmlt Data s1gnals are generated by the transmitter UARTs m51de the DC367B Chlp, ~and the four 51gnals BSDOO0O H to BSDO3 H are each converted to EIA levels and fed to the hnes o | 5.6 POWER SUPPLY G | E o The DZQI11 uses the +12V and +5 V avallable on the Qbus backplane and also needs 12 V ThlSis produced by a smtch—mode power supply. : ‘Thecircuit is bu1ltaround a TL494 sw1tch1ng regulator whtch uses pulse-W1dth control to regulate the’ ’—12 V output E In51de the TL494an osc1llator runs at a frequency determmed by the tlme constant of the re51stor and o ~ capacitor connected to p1ns 5 and 6. Thisis about 35 kHz Pins 8 and 1 1 drlve a power transnstor ON and | ’.‘OF F. TRANSMIT | CONTROL | | o o - | REGISTER | DATA TERM RDY L |(HIGH BYTE)| L DATA | TERMINAL READY | MODEM REQ TO SEND . - FORCED BUSY - | TRANSMIT | MAIN- TENANCE | | DATA | REGISTER |——p| MODE | | oata | R SELECTOR D6 | D6} | i | TRANSMITTED DATA ONE OF FOUR CIRCUITS| Figure 5-15 EIA Transmi_'ttérsz - at about +12 V, and the r'ectifyingdiOde is cut off. When the transistor is ON, its collector is positive and through the 0.39 ohm resistor and the inductor, causing a magnetic field to flowsent " Therefore curr collapses and a self-induced etic field develop in the inductor. When the transistor is turned OFF, the magn the rectifying diode, and through flow to power causes voltage ~ voltage develops across the inductor. This to the +12 V supply the from transferred is power charge the output smoothing capacitor. Therefore output—12 Vline. This line is held at—12 V by means of feedback into the TL494, which changes the width of the pulse that holds the transistor ON. The wider the pulse, the bigger the magnetic field build-up, and the higher the output voltage. '~ B B CHAPTER6 6.1 SCOPE S o * | | ~ This chapter explains the maintenance strategy, and how touse the dragnostlc programs to find a defectryer | field- replaceable un1t (FRU). There 1s also a troubleshootmg flowchart ~ 6.2 PREVENTIVE MAINTENANCE 6. 3 CORRECTIVE MAINTENANCE (PDP 11 SYSTEMS) No preventivemaintenance is planned for the DZQI 1. However if you are serwcmg the host system you . | should check vrsually for loose connectors and damaged cables 1 6.3. l General - | - | R ~ You may recognize the need for corrective maintenance because ofa farlure durmg normal operatlon or ~ because of errors detected durmg system maintenance. When an error is detected, run the diagnostic | programs to isolate the fa111ng FRU If necessary, refer to Chapter 2 for 1nstallatlon 1nformatlon ‘Th1s chapter glves a short descrlptlon of the dlagnostlc programs and test modes For detalls refer to the | . - ' program hstlngs | SLom ST | N It becomes necessary to troubleshoot the DZQl lto component level look at the program hstmg on the | ~use ofloopmg features. By using the program to keep the option in the fallmg mode. and by using Chapter5 - and the circuit schematics to find the related circuitry, you may be able to isolate the problem to a failing component This type of ma1ntenance isnot recommended if module replacement 1S possrble , " - 6.3. 2 Tools, Test Equlpment and Troubleshootmg Alds f needed 1f and. ] 6 Table hstedin programs the are maintenance corrective for requirements - The minimum €an programs two first The panels. cover remove to screwdriver a configuration. hardware by the system test the DZQl ] usmg the internal wrap- around feature descrlbedin Sectlon 5.4.4. | Table 6 1 Dlagnostlc Programs | 'Program Tntle V_Program Code - CVDZA ». | : CVDZB = CvDzZC ~ DZVll/DZQll dlagnostlc part 1 of'/' DZVI11/DZQI! diagnostic. part 20f2 | DZV11/DZQ11 cable/echo test o MD—'ll—DVDZDf‘ DZV11/DZQ11 overlay for ITEP - MD-11 DZITA | Interprocessor test program (ITEP) - You can make better checks by using the H329 and H?25 test connectors The H329 connects data llllL S ~and control signalsin a staggered loopback configuration. This connector plugs into the Berg J1 on the module, and allows the diagnosticprogram to check out all the module. The H325 test connector plugs into the modem end of the interface cable. It loops back data lines and control srgnals without staggering ‘the lines. This allows the program to test both the module and the cable These test connectors are shown, -1n Flgure l -4 and their part numbers appear in Table 2- l o | | If it is necessary to troubleshoot to component level an ohmmeter an oscrlloscope and a dual-helght _ extender card are also necessary. Before probmg the module make a good visual mspectlon for damage to - parts or to prmted crrcurts o | | _ " 6.3,3 DECX/ll Exercnser Program ~ - The DECX/11 system run-time exerciser is made up from dlfferent software modules configured torun interactively. The exerciser is umque to the system it exercises, and must be reconfigured if options are addedtothe system. The exerciser is different from the diagnostic programs, which test and test the option againinisolation. The exerciser tests the ability of the option to run in the system environment. It does this by performmg asample of the functlons of the optton whlle also testmg other system components - The DZQll module of DECX/ll 1s CXDZB DZVl l/DZQll module test oy ,6 3. 4 XXDP-l- Dlagnosttc Programs ""6341 General — The dlagnosttc package has three standalone dlagnosttcs (CVDZA CVDZB and - CVDZC ) and an overlay for the interprocessor test program (DVDZD). To run the interprocessor test, - you must first load the ITEPmonitor (DZITA) These programs are available on the media listed in Table 6-2. Details of the programs are grven inthe program ltstmgs ThlS sectlon gives general procedures | | and 1nformatlon B Table 6—.2» i_,_Mu,ltimedia ASS‘:g“mentS, L ~ "~ Diskettes i S (RKO5) (RK06) - ~Part Number B CZZHan* DXDP-l- 43LSI FLP4 ~ CZZMTun DYDP+ 20LSE11#2 '"DlskPacks ~ Title ~ (RKO7) T - AS-C638n-MC BA-F048n-MC L CVZZEnn LSL11 XXDP—l— DIAG PKG.-, CZZRBmnRK6DIAGPKG CZZSBnn RK7 DIAG PKG ~ R L R SR AN-TO69n-MC AM-S469n-MC - AY-T539n-MC . - (RLOI) CZZLDnnRLIDIAGPKGI AX-T502n-MC o (RDOZ) R ‘CSYSAnn 11/23 PLUS SYSTEM CHK ~ BC-T160n-MC e ~ (TU58D) (TU16) | R CZZLNnn DLDP-l- DL2 DIAG PKG S CXYAEnn DDDP+5 DEVICES Sl f CZZZ4nn MMDP+ 2400° MT9 1/2 | CZZZNnn MMDP+ PKG6 MT9 = (TSO4) CZZZ9nn MSDP+ 1600 BPI MT9 . L CZZZVnn TRDP+ TR79 MT - - BC-F916n-MC__ ~ BE-F669n-MC AP-TO71n-MC AP-T421n-MC BB-F751n-MC .?BB‘C631‘11—MC ' The nin the tltles and part numbers mdlcates the revision level and can change when an update takes place | ~ For example CZZZVAO 1nd1cates Rev A, patch O of CZZZV In the same way, BB C63 1B-MC mdxcates | ~ Rev. B in the part number - 6 3 4. 2 Mamtenance Modes — Figure 6 l shows the data paths for the maintenance modes The two | ‘basic programs (CVDZA and CVDZB) can be run in the internal, staggered or external modes. The - ‘cable and echo test (CVDZC) can be selected either to loop characters from the program out through the test connector and back to the program, or otherwise to loop characters from a test console through thev'_ DZQ11 and back out to the test terminal. The interprocessor test program needs another CPU running the test together with the CPU under test. The other CPU may be alocal system, or aremote system(suchas a s turnaround system). Refer to Figure 6-2. In this test, the two processors communicate to check the hardware from end to end. It is possible, however to operate the program w1th an H325 loopback connector mstead of another processor | 1 Q *Q-BUS C oBUs3 =y M3106 INTERNAL M3106 ng " [é STAGGERED ( QBUS { BCO5L :___"___] H325 J LFJ ONE TIME 70 19964-xx e ? Q-BUS 1 EXTERNAL (CVDZA or CVDZB) OR CABLE (CVDZC ONLY) - ONLY ONE TEST CONNECTOR . CAN BE INSTALLED AT ANY EXTERNAL (CVDZA or CVDZB) | OR CABLE (CVDZC ONLY) S < 1 nuLL —— MODEM B ~ TERMINAL M3106 BC11U ECHO (CVDZC ON LY} *A NULL MODEM SUCHAS AN H31 2 MAY BE NECESSARY DEPENDING ON THE TERMINAL USED FOR TEST. — 6-1 | -Mai'fitenan_c_:e' Mode Data FlOw Figure -o -f “' QQBUS 3 | v — - - M3106|} -{— -] | UNVIIBU‘VS;*“ _- REMOTELINK . mobem - * BOTH PROCESSORS MUST BE RUNNING DZITA. N S o ) . b’ o Figure 6-2 "Int,e_xfprov_cesso,rvTést- (ITEP) f 6.3.4.3 o “holsdé, | | Setting Up Procedures — RUnningiwth'é' internal .loo'pba_'ck tes'tl_ needs vn’o"»visévtting up. The S loopback function is enabled by CSR<03>. The staggered loopback test needs the H329 test connector plugged in J1, in place of the cable. The best method of doing this is to power down the computer, unplug ~the DZQ11 module, and swap the interface cable for the H329 test connector. Then install the module - again, taking care not to damage the components on adjacent modules. ' 1NOTE_ ‘ You must install jumpers W1 to W4 if cither test connector H329 or H325 is used (see Section Torun the external test, dis'.é'on‘né_ét the far end of the BCI lUihterfacejéable from the modem orterminal. Plug the H325 test connec into tor the modem end of the cable. If the 70-19964-00 distribution panel is fitted, plug the H325 into the 25-way D-type connector. ~ Thecabletestalso needs an H325, as indica in ted Figure 6-1. The echo test needs a terminal c’On‘neCtéd to ~ the DZQI11. This mayfrieed_a’ null modem, depending on the type of terminal. o ~ - R The :setti'ngéup procedure for 'th_e'interp'ro'ce's‘s'br; t'e}st is different, depending'cm the equipmént available. B 6.3".4.?4 | Softwaré Switch RegiSter —‘- Thfé.‘ diagn05tic prbgr'ams use locatibn 176 for a switch register instead of front panel switches. To change the operating parameters, load the program and then use the ‘ODT slash command to open location 176. Refer to the appropriate program listing for a definition of bits. Assemble the corresponding octal number and enter it into location 176. Then start the program at location 200. e ~ NOTE o »,’Me'm'ory; l‘ocafionsafid co'n'tents,a'xfe give_,, inoctal S - notation in this chapter. - " The si)ftware switch may be :acce"sse‘dWhil'e 'the'.fprdgram_is'.mnning. Préss CTRL/G to Stdp the program R -_"‘_-‘*_jand‘-Ope-n the-s,wit-c;h’regis.-t‘er.v, i ML ' .v: SR (5,;1 o e . | L o and CVDZB) have auto—srzmg capablhtles and - 6.3.4.5 Auto-Srzmg— The two basic tests (CVDZA regrster - may therefore be run wrthout changmg the swrtch w1th1n the floating address and, | ~ The auto—srzer routine detects all DZQI 1 devrce and vector addresses800 baud, internal loopback, and 19 vector area. The values of the other parameters are by default set for 1500 to 1740 (Table 6-3). locatlons ~ the testing of all four lines. These values are storedin a status tablein They are prmted by the console termmal durmg the test. | | | . L e Typical Map ofDZQll Status* Tabl63 | Location‘ o ‘, Contents e - Meanmg 1500 o o - 1502 | i '_0003»00 . 1504 e | - CSR address of first DZQll in system ~ '160-100 | RecervermterruptvectorforfirstDZQl11n system B j"',' TCR bit representsthe actlve lmes to be tested 000017 v 1.506 enabled BT _0'1747‘0 TR ._LPR bits representmgthe followmg receiverstop bits. 1510 IO'OOO‘OO_:_ . .Indrcates the selected malntenance mode where 19 800 baud 8 bits per character and 2 000000 = Internal 000200= External with H325 | IOOOOOStaggered wrth H329 % This tableis an example Look at the program listing for detalls If a supported baud rate is needed enter the approprlate value N | - cs may be run mth ’ - 6.3.4.6 Parameter Inputs and Dlalogue - The CVDZA and CVDZB dlagnostl register and then startthe - parameters specified by the operator. To do this, set bit 00 in the software switch - program at locatron 200. The program responds with a serles of questions.. 1ST CSR ADDRESS (160000 167770) | Answer this questron by typing in the address of the DZQl 1 CSR at wh1chyou want testlng to start Press | | RETURN after all answers. IST VECTOR ADDRESS (300 770) Type the vector of the DZQl 1. Note that all the DZQl 1s must be contrguous for both| address) and vector " MAINTENANCE MODE | | locatrons | [EXTERNAL <H325> (E)] [INTERNAL <DZCSR03 =1>(I)] [STAGGERED <H329> (8)]: 6-5 | Press E I or S ‘as approprlate If runmng extemal all selected lrnes must be termmated by H325 test - < connectors | . o . e . | . NOTE Itis not possrble to mstall more than one H325 SRR ~ test connector in the 70-19964-00 dlstrrbutlonjj-' - _panel at any one time. Itis necessary toselecteach line for test, usmg blt 03 of the software swntch."_| | '.reglster S & s “# OF DZVl l/DZQllS <IN OCTAL> (120) L Type the total number of DZQl ls to be tested . N Other parameters (for example baud rate) that are not 1ncludedin the openmg dlalogue may be entered via ( the software switch register. All other parameters are assigned to all DZQ11sin the system. The program run time is approxrmately 1.5 mmutes on the firstpass and 2.5 mlnutes on the followmgpasses o least three error—free passes Run at Operatlon of the cable and echo test (CVDZC) always needs an openlng dlalogue Spec1a1 swrtch ~selections, however are not needed for normal operatlon Start the program and respond to the s o -wrth an answer followed by RETURN ) VECTOR ADDRESS-v o o _ N TYPe the’vector of the DZQll under test | S CONTROLREGISTERADDRESS- Type the CSR address of the DZQll e B | B | Bi | o ; L : o ~ BAUD RATE-» S | (\ o e under test ) _:' - o e B Gt LB I . HType one of the followmg 50 75 110 135 150, 300 600 1200 1800 2000 2400 3600 4800 7200 "7'or9600 LINE Type the number of the hne that has the H325 test connector on it. The lmes are numbered O 1 At this pomt the test starts. Cable Test CXf the cable test (C) was selected the system prmts | ‘ . WHICH TEST? ECHO OR CABLE (E OR C) TypeEorC asneeded . - questrons_ - CABLE TEST 2 3. <f f f The cable test executesin approximately 15 seconds at 9600 baud. It prints an end—of-pass message after each pass. To change lines, press any key on the console termmal whrle the program is runnmg The - system responds with: LINE At this pomt change the H325 test connector to another lme and type the new llne number The system " | S ~ prints: | CABLETEST ~ and continues - | ‘Echo Test ~ Ifyouselect the echo test (E) when the program asks Wthh test you should answer the baud rate and line f questlons in the same way as for the cable test After the line numberis typed the system prmts S TERMINAL ECHO TEST f ~on the console termmal and prmts - THE QUICK BROWN FOX JUMPED OVER THE LAZY DOGS BACK 0123456789 on the DZQll terminal. To have this message prlnted contmuously, press CTRL/ G on“the console ~ I terminal while the message is being printed by the DZQI11 terminal. The program prints a prompt character on the console terminal and waits for a new switch register setting. Set the swrtch re glster to 377_ to have the program output on the qurck brown fox message contlnuously | To return to the normal flow of dlagnostlc press CTRL/ G and change the swrtch reglster to somethmg’ | | other than 377 - , » The console termmal prlnts TYPE A CHAR ON DZVl 1 /DZQll TERMINAL E Type any prmtable character on the DZQll termmal It w1ll be echoed back to the termmal Ifyou press CTRL/ Con the DZQI 1 termlnal the program pnnts the end—of—pass message on the console | and then continues w1th the ‘quick brown fox message on the DZQll termmal To change lmes type any pnntable character on the console termmal The system prmts LINE i and waits for a response Plug the next line into the DZQl l termmal and continue untll all the lmes have been tested Refer to the hstmg for explanations of error prmtouts 6. 3 4. 7 Functlonal Descnptton — This section gives a short descr1ptron of the dlagnostlc programs _used wrth the DZQll For a more detalls refer to the program llstlngs | CVDZA- ThlSis the first ofa2-part series used for basic optlon checkout. It exercises the read/writebits of the registers, performs simple transmit and receive exerc1ses for each lme and verifies the 1nterrupt R e | capabllmes of the Opthl‘l (Table 6 4) | - Functions Number R (Octal)_- o - Verifies the bus response durlng a read or wrlte to the followmg dewce reglsters T CSR RBUF, TCR, and MSR R | | e vVerlfies that bit CLR can be set and that 1t w1ll clear by 1tself | ) Verlfies that the read/write b1ts of the CSR can be set. Then verlfies that they canbe - cleared. Also verifies that after being set again, they can be cleared by aMaster o :ClearThe bits tested are MAINT, MSE SAE RIE and TIE. e s | Tests that all of the TCR b1ts can be set cleared and cleared by a Master Clear Also tests that the DTR b1ts canbe set, cleared and cleared by a RESET | _' ,-Verlfies that RDONE TRDYTLINE B, TLINE A, and SA are read—only Tests | o that TRDYis zero unt11 a lme is selected and MSEis set | © Teststhat the following CSR bits are read-write: TIE, SAE, MSE, and MAINT : - Checks that settmg CLRin the CSR w1ll clear these b1ts . o X '}Performs reset testlng Also tests read-only b1tsin RBUF and wrlte-only bltsin LPR " g -Performs reset testmg Also tests read-only b1tsin the MSR and wnte-only bltSin the- | | ,Verlfies that settlng DTR causes CO and RI to set under the followmg cond1tlons '_1'. For the same line ifan extemal mode - - R .2 For the staggered line ifin staggered mode o ‘Lmes are staggered as follows: lme 0 w1th hne 1, line 2 with line 3. Th1s test is run | only if an H325 or H329 is connected to the DZQll under test '_Ver1f'1es that TRDYis set when a lmeis ready to be loaded Verlfies that the lme B spemfied by TLINE A and TLINE Bim the CSR applles to the hne selectedin the‘ - .Transmlts one character and receives one character on one line at a tlme The characteris 252. All selected lines will be turned on. Thisis the first time any datais ~ checkedin the receiver. Using switch 09 w1th this test makes a tlght scope loop that | ;transmlts a steady stream of characters TR SR ST | ‘_’:Clears RX ENABin the LPR for each lme to verlfy that each recelvmg lme can be S _dlsabled This test also verifies that the srlo can be emptled by settmg CLRinthe Venfies that the transmitter transmlts characters and the receiver receives characters | ~ Oneline ata time is tested based on valid lines. ThlSis the first pomt at Wthl’l all data o is tested - | | Table 6-4 CVDZA Tests (Cont) | Afi} Test | - vNumber' o '_ Functions 16 - Exercises one line at a time to verify that: R (Octal) 1. The transmitter BRK bit works | 2. The receiver can flag framing errors 3. The recelver can flag parlty errors. 17 Y erlfies that the DZQl 1 does not mterrupt while the processor status does not allow ~interrupts. Also checks that the DZQI 1 caninterrupt when the processor status does | allow 1nterrupts , . | R SC o 20 Verifies that the receiver 1nterrupts before the transmltter even when the transmltter was enabled first | CVDZB This program is the secondof the two basrc optron dlagnostlcs It exercises the transmrtters and receivers in all possible operating modes and at all possible data rates. Error condltlons are 1nduced ~ and the optlon is checked for the abrllty to recognlze these errors (Table 6- 5) Table 6- 5 | Test | | | CVDZB Tests ‘Number Functions | 1 Verifies OVRN ERR and SA one line at a time,‘basedon Vahd lines. As each ofthe_ (Octal) I | first 16 characters are sent, Silo Alarmis tested to be cleared. On the 16th character. the programtests for Silo Alarm to set. Then all the srlois filled and an Overrun error - - is expected on the 65th character. occurs contmuousl) while SWO9=1. 2B 4 | '_ Tests that SAE inhibits receiver mterrupts Sets RIE and checks that SA causes an - 3 ‘ Usrng switch 09 for thls test sends 20 characters onthe lme prewousl\ selected Thrs | B - interrupt on the 16th character. Tests all selected lmes one at atime. o ; Interrupt test on the transm1tter and receiver. Runs all quahtled lines at maximum - speed. | S ’_DZQll relat1ve tlmmg test. - Each selected hne one at a time, runs 16 characters at all baud rates, and 1hLH the highest baud rate with all character lengths. Each following parameter decreasesin time from the previously selected parameter. The time is checked against l}lL prevrous time. The parameters are: l Elght bits per character plus two stop brts at 30 75 110, 134.5, l\O sOO 600 1200 1800 2000, 2400, 3600 4800. 7200, and 9600 baud 8 ~ - 'Nll.m,b:er" o "_(Oetal)‘ e | G - Functions IR | -2 Five, Six, and seven bits per character wrth two stop bltS and at 198K baud. Each‘v line completes all of the checks before the next lrneis tested 5 R | | ~ -' Table6-5 CVDZB Tests (Cont) | . ’}Checks parlty errors in staggered mode only All selected hnes are enabled at thet'v | same tlme Tests for even parlty on odd hnes and odd parrty on even lmes | -CVDZC ThlS program verlfres the cable mterface connectlon between the module and the EIA connector The dlagnostlc 1ncludes a cable test an echo test, and a test of modem control srgnals »_ | The cable test transmlts a bmary count pattern via the test connector to therecervers The data flowis from : “the program out through the 1nterface cable to the test connector, and back ST o o The thrrd test verlfies that settmg DTR for a glven hne causes CO and RI to set. J umpers Wl W2 W3 | ,and W4 must be installed for this test 6. 3 5 Interprocessor Test (ITEP) ~ . | - ~ , The 1nterprocessor test program (ITEP) verrfies the operatlon of the DZQII by usmgit in a communications link with another processor The other processor may be a system at the same locatlon as the system under test, or it may be in a remote communications test center. DVDZDis the DZV1 l/DZQll overlay of the test program It must berun together Wlth DZITA—D ‘the monrtor | program o .PP.JP'-:-*V _[ITEP has the followmg four testmg modes - .Internal loopback mode External loopback mode (full—duplex only) | - One-way-in mode ’Oneway—out mode e 6.3.5.1 StartmgITEPITEP needsa complete communrcatrons loop (Frgure 6 2) Make sure that a -~ - ~ - loopis ‘made with compatrble equlpment The variable parameters mustbe thesame in each of the two processors. The mode must be one of the options listed in Table 6- 6. The system thatis toreceive data first should be loaded and started first. If the modem being used on this system has an automatic answer feature, it should be enabled. The system thatis to transmit first should then be loaded and the connection made. If the CPUis an LSI—ll and the hne clockis to be used it should be enabled before program N f}executron The load addressis 200 } NOTE Refer tothe program hstmg for detarls of restrlctlons, ~error messages, and optlonal selectlons | Table 6 6 Vahd Mode Combmatlons o -A »"CPUNo . VCPUNo 2 One-WanyUt T 'One-Way-In One-Way-Out | B : One+Wa'y;Ih ,) . Internal Loopback A_ | .External LOOpback | Internal Loopback B o External Loopback Extemal L00pback | - ~ (full-duplex) - - full-duplex) | - External Loopbaek . Extemal Loopback - | (full-duplex with . | H325 test connector on end of modem - cable) 6.3.6 Manual Tests | This section contains some short tests that can be performed using the hardware ODT commands. The : examples given here assume that you are familiar with the use of ODT, and that the DZQ11 CSR address is set for 160100. The letter n is used to indicate a number that may change for different systems For an explanatlon of ODT commands refer to the Mlcrocomputer Handbook 'NOTE | o 1. | ' Operator mput is underlmed in the followmg - dlalogues , | . ThlS test verlfies that the CLR b1t w1ll clear the CSR and the low byte of the TCR ’Open the CSR "CIGOIOO/OOOOOOw 160102/0nnnnn & 160104/000000& 1601’06/000000 @ Open the RBUF - Open the TCR Open the TDR @160100/000000 10050I Opeh CSR; enter bits o i | 160102/Onnnnn 1160104/000000 417G Open TCR; enter bits - 160106/000000D e ' @160100/111450 206 160102/onnnnnr— | | set device clear Open CSR; | | e -’160104/007400 @ 16()106/()()()()()0 m Note that low byte of TCRis cleared TheMSR may contam a value ofOO74l7 if the H329is R 7» »,*_0160100/000000 | - connected e Note that CSRis cleared ~ This test makes a basrc check of the transmltter scanner It performs a Master Clear sets the TCRbit for line 3, and then verifies that line 3 appears in the CSR. It clears the TCR b1t for lme o . 3 and then checks that the lme numbersin the CSR are clear fi.Ol60lOO/OOOOOO 20(3 SeeMaster Clear ) 160102/Onnnnn. R '160104/000000_1_(_)_:‘_ _ . 1~60102/Onnnnn_’i - -',»'.-‘1'60100/101450 © - SetMSE and MAINT § om @/000000s ~ Set TCR bit 03 ol | - | R Read CSRfor TRDY setand TX lne =3 - ' 160104/000010 O" f Clear TCRbit03 | 160102/Onnnnn "_‘."160100/000050 S © o | D Resd CSRforTRDY and TLINES cleared S | '»_To perform the same test on hne 2 proceed as follows ~ @160100/000000 208D cgoooooo_s_o_o_, et Master Clear S _..Set MSE and MAINT in CSR 16010200 ~160104/000000 4* ~ Set TCR bit 02 160102/0nnnnn fi 160100/101050_@ ~ e e e Check CSR for TRDY set and Tx line = 2 ~?“’160104/OOOOO40"L © Clear TCRbit02 \160102/Onnnnn" B e ~ 160100/000050 ~ Chec CSR for TRDY k and TLINEs cleared ‘To perform the same test on line 1, proceed as 'foll'ows @160100/0000002077 ' @/000000 50© | ~ Set Master Clear Set MSE and MAINTin CSR 160102/0nnnnn © Set TCR bit 01 51-60104/000000- 28 ) | | - l60102/0nnnnn | Check CSR for TRDY setand Txfne =1~ L .1160100/100450 o 160102/0nnnnn (_D__ | " 160104/000002 0* Clwr TR w01 160102/0nnnnn » - _160100/000050- | Check CSR for TRDY and TLINEs cleared , To perfonn the same test on line O, proceed as follows @ 160100/000000 20T @/000000 50T Set Master Clear 'CSR | Set MSE and MAINTin 160102/0nnnnn @ 160104/000000 1* ~ 160102/0nnnnn A and Tx line= 0 4 DY . Check CSR for TRset 160100/100050 © 160102/0nnnnn © '*160104/000001 0t Clear TCR bit 00 V‘ '160102/Onnnnn - S- Check CSR for TRDY and TLINEs cleared | 160100/OOOOSO . This next test checks that lme 3is the hlghest-prlorlty hne when all lmes are enabled at once. It - checks that hne pnorrty goes from 3 to0. @ 1601 OO/ OOOOOO ZOh o C/oooooo 500 | .160102/0nnnnn:£~f: ~ 160104/000000 17+ R 4_ Set Master Clear Set MSE and MAINTin CSR ._ o -‘ ‘Set'_TCR. bits for lines, 3, 2, 1, afid O‘ | 6-,1_'3 ) | 160102/0nnnnn * " Check CSR for TRDY set and Tx lme=3 (hlghest, ~160100/101450®@ 160102/0nnnnn * ~ 160100/101050@ ~ 160102/0nnnnn @ " S o ',Clea'f-OflilY 'TCR bit 3 "~ | | S ;_’prrorlty hne) R CheckCSR for TRDY set and Tx lme—2(next hlghest '._'..”Prlorlty) . o - © 160104/000007 3* 160102/0nnnnn * 160100/10045© 0 o Check CSR for TRDY set and Tx line = 1 (thlrd hlghest | -prlorlty) | L 160102/ 0nnnn@ n 1160104/000003 1' ( Clear TCRbiOI 160102/0nnnn n * 160100/100050 L Check CSR for TRDY set and Tx line = 0 (lowest S . prlorlty) 160102/0nnnnn @ ~ 160104/000000*1 ‘ ' 160102/Onr1nnn" | ) 160100/000050 | Check CSR for TRDY and TLINEs cleared = .ThlS test checks the receiver wrthout usmg the transmltter scanner. The BRK bltis set and the B o | RBUFis tested to see that it contams a null character and a frammg error o @ 160100/000000 20@ f@/oooooo 50@ 160102/Onnnnn 17470. »' V;Set Master Clear RO Set MSE and MAINTin CSR S SN Load LPRwrth198Kbaud 8 level ZStop blts and lmeO P S 160104/000000 . 1—60106-/0_00000 400(3| . @160100/000250 ® | _"SetBreakbltmTDRforlmeO " "ReadCSR for RDONE set - L < ‘, ERR set for RX S Check RBUF for Data Valrd and F RAM bits ©160102/120000 * 0 ~ 160100/00005@ - - lme = 0, and for all Zeros. in data o 160102/020000 - Check CSR for RDONE cleared . .Check RBUF for DataValld Cle‘affid To perform the same test on 11ne 1 proceed as follows: | Set Master Clear @ 160100/000000 20@1 - e © Set MSE and MAINTin CSR | Load LPRWlth 19 8K baud 8 level 2 stop b1ts and lrnel ~ @/00000 50 160102/0nnnnn 174’71 @ 160106/000000 10006 bit in TDR for line 1 | * Set Break ~ Check CSR for RDONE set @160100/000250 & 160102/120400 * | ~ 160100/000050 & ' 160102/020400 i Check RBUF for Data Vahd and FRAM ERR set for RX line = 1, and for all zeros in data bits Check CSR for RDONE cleared f | ,Check RBUF for Data Valld cleared ) To perforrn thls test on lme 2 proceed as follows C160100/OOOOOO 20_3@1; . 50 | ,C/OOOOOO LF 160102/Onnnnn 17472 160104/000000 & FE7 160106/000000 2000 @160100/000250 © ©160102/121000* 7160100/000050 T = 160102/021000 Set Master Clear - 'Set MSE and MAINTin CSR | Load LPR W1th 19. 8K baud 8- level 2 stop b1ts and line 2 ~ Set Break bit »inTDR for line‘2 | Check CSR for RDONE set Check RBUF for Data Vahd and FRAM ERR set,, for - RX line = 2 and for all zeros in data bits Check CSR for RDONE cleared Check RBUF for Data Vahd cleared | To perform this test on 11ne 3, proceed as follows B * @160100/000000 2060 ~ @/000000 50T SetMaster Clear ~ Set MSE and MAINT in CSR C6-15 | ~ Load LPR with 19.8K baud, 8-level, 2 stop bits, and line 3 - l60102/0nnnnn 17473@ ( . 7160104/000000P - -< [160106/000000 40007 | Set Break bltin TDR for llne 3 ~ Check CSR for RDONE set @1 60100/000250 . © Check RBUF for Data Valid and FRAM ERRset. for Rx line = 3 and for- all zeros in data bltS : » TM ’]160102/121400 A ' ,.Check CSR for RDONE cleared | | ,160100/000050 D | ;160102/021400 Check RBUF for Data Valrd cleared ,v 5. This test transmits and receives some characterson lme 0. It uses 8 level wrth 2 stop blts at - 19. 8K baudin mamtenance mode @160100/000000 207 C/OOOOOO SOD | . S | - . Set Master Clear e e Set MSEand MAINTin CSR o Set LPR brts for 19 8K baud 8 level 2 stop brts lme O | 160102/Onnnnn 1 7470 - o 160104/0()0000 I '_Set TCR b1t 00 _160102/Onnnnn A - '_1_60100/100050® Check CSR forTRD_YD set and Tx "l_ine =' 0 o . 160102/Onnnnn@ - 160104/000001 i L 160106/000000 3771 . Load 377g into TDR i 160104/000001 : B 160102/100377 | .Check RBUF for Data Valld set for OVRN ERR,- | - FRAM ERR, and PAR ERR clear for Rx lrne = Q, and. B for the data to be 377 | | Check CSR for TRDY set and RDONE cleared L Check RBUF for Data Valld cleared | 160104/000001_) .*160106/000000 252*\ = Load 252 into TDR | .' ' 160104/0000001" . 160102/100252 % o - Read RBUF for Data Vahd set, the error brts clear va o lme—O andthedatatobe252 L - Check CSR for TRDY set and RDONE cleared - © 160100/100050@ B Read RBUF for Data Valrd cleared . | 16‘01102/000252_@ 160104/0000001 @ , - 160106/000000 125* Load 125g into TDR * ~160104/000001 © 160102/100125 * CheckRBUFforDataVahdset noerrorblts set. Rxlme' | | | —O andthedatabelng 125 o L Cheok CSR forTRDY set and RDONEcleared 160100/100050® | | ‘ oRead RBUF for Data Vahd cleared o 160102/000125 ' - 160104/000001 _@_) R 160106/0000000* Load a0 into TDR © 160104/000001 * - o lldset noerrors Rxhne—O and _ReadRBUFforDataVa Os . . 160‘102/100000_“_,. ,';_160100/100050 o ~ the data blts being : | Check CSR for TRDY set and RDONE cleared . ThlS test sets the marntenance b1t but d1sables the recelversIt then transmrts a character and o S | L checks to see that it i1s not recetved Set?Master Clear "@160100/000000 208 Set MSE and MAINTin CSR ~ | @/OOOOOO SOLF _ Load the LPR wrth RX ENAB cleared ) 160102/Onnnnn 7470'LF etTCR bit 00 160104/000000 1* 160102/0nnnnn * '. o e | R Check CSR for TRDY set and RDONE cleared 160100/100050 © o EA © 160102/0npnen v | 7160104/000001_(5 1 160106/000000 377" 160104/000001» = l60102/0nnnnn A 160100/100050 s | R Load 377 into TDR ‘ e Gl | Check RBUF to see that Data Valid did not set -‘ Check CSR fo sce that RDONE is clear 617 B sets the lme for 5 level code and then trles to transmxt and recelve 377 Transmltted o 7. ~ »:‘ThlStest bits are maskedin the process and a 37is recerved Thrs verrfies that the UARTs have swrtched o | | : toSlevel e B S ",‘-_0160100/00000020 Ll ‘A.Set Mastef Clear 'o/oooooosow g ‘-'"";:SetMSE and MAINTin CSR S 160102/Onnnnn 17400@ - ':LoadLPR for 198K baud 5 level lme number 0 - .160104/000000 1* B -_’160102/0nnnnn""‘-' © Set TCR blt 00 D 160100/100050@ i P “ A160104/000001. SE ~ 160106/000000 3_7_1_ © o | ChecCSR k for TRDY set and line numbers0 . 1601020mmmm® 160104/000001 * S ‘ (e R Load377into TDR ‘ [ ‘ 1.6'01}02‘/ 100:(‘)’3'7 " | = O data SO ‘, ‘-Read RBUF for Data Vahd set no errors hne 160100/100050 Check CSR for TRDY setand RDONE cleared o '6 4 CORRECTIVE MAINTENANCE (MrcroVAX SYSTEMS) | - ~ Corrective maintenance is performed when operational failures or dragnostlc tests 1nd1cate that the | DZQ11 is defectlve Dragnostlc test programs for DZQI Is 1nstalledin MICI'OVAX systems are hsted | ‘below S - EHKMV EHXDZ Macrovenfy MlCI‘OVAX System Test . DZVll/DZQll Tests The Macrovenfy Dlagnostlc s 6.4 1 | Macroverlfyis a qulck system test whrch1s used , | | e As a first—hne check before usmg dev1ce dlagnostlcs e As a confidence check | e To verlfy the complete system after mstallatlon or malntenance ~ o The Macroverify dlagnostlc runs standalone Itruns automatrcally when the CPU Tests dlsketteis booted. N from one of the RX50 drives. The program, which takes up to four minutes to complete, needs 30K bytes of memory The testmg performed by Macroverrfy does not destroy mformatlon recorded on the drsks | 6411 Settmg—Up Procedures - Power up all dev1ces in the configuratron Set all dlSk drives for ‘; . - I/O. Place a diskettein each RX50 drive. Disconnect any external cables or test connectors from the - DLVJI1 and DZQ11 distribution panels If the system is not set up correctly, Macroverlfy w1ll outputa o .;TEST FAILED message (see Sectlon 6. 4 1. 3) for the approprlate devrcetest. - é in one of 'Macroverify, mouh‘t theCPU Te'ASt_s I di‘ék,ettL 6.4.1.2 Bootstrapping Procedure — To boot I o | the RX50 drives, and type: ;boot from drive 1 - >>>B _DUAl ,Qr:" | v | - | - >'>>B____DUA2‘ . | ‘ ~v;'b00t- ‘fror‘n‘ ’dl"ive2 - runs as soon as the boot ’op_erati()fiis completed . 6.4.1.3 Macrdverify' Operati'bn - 'Macrover‘ify which check for all possible system configurations. : successfully. The program contains routines d -Q—,bus’addresS,“ilfthe if the device responds to itstheaSsigne e device, a test is madeg toseef "~ For each possibl . console on not respond, the followin status message is displayed ~ device does FOUND. NOT I 22z TOR VEC yy, yyyy H CSR WITFOR xxxxGxPER ICETIN t DEVTES “'NO ~ MED. G NOTE ~ - The ,VéctO_r number of devices (such as DZQl;l) with floating vectors, will not be displayed. - ~ N _p’erforthed; A d ad_’dres‘s:, 'avsequence' of user-level tests aissuccess For each device-whiCh responds to its assigne ful test that time The ed. display be will e D messag TEST SUCCEEDED or TEST FAILE o - should take is also displayed. G e | and had no DLVJ1 installed ~ An example of a macroverify test report follows. The system that was tested | | drive 2. was mounted in ‘the DEQNA cables were not connected. No diskette 02B 'POPLCTD >5>>B DUAl 'ATTEMPTING BOOTSTRAP Macroverify vV1l.4 9, l - This MicroVAX 1 is at microcode revision level 5, hardware revision leve ~ and includes support for'F-FLOAT'and G—FLOAT'data types;'»f Time - Testing to TR vTest_(mihs)_ @:38 Memory Disk unit DUAB £:20 p:20 Disk unit DUAl g:20 Disk unit DUA2 Comments (8.50 Mb) TEST SUCCEEDED TEsTTSUCCEEDED'(Rbsl'fixed”disky_ ~ TEST SUCCEEDED~(RXSG'fioppy'disk)> TEST.FAILED_(RXS@»leppy_diSk)< 619 o N | ‘ShQ-floPPY'diskettetiS,mounted:infthtSpdrive“ 'bt the diskette~is mounted'improperly; “ Piease correct and rerun thisvdiagnostictaT | _ ::oLvJ11"'p”g '5" ’_ _1a:4o’h ’}'TfoEv1cE DLVJl'WITH'CSR 7765zz‘h L i DZVll/DZQll f:,v_T"f”'ffléifi'f‘SyT'ETEST SUCCEEDPD B e DEQNA ASd ' e ~ Nor FOUND. -NO. TESTING PERFORMED. ,;;;,,;'___ _,v.;o=1g ~ L TEST FAILED j“ ehPlease verlfy that the cable from the DEQNA-t v7” modu1e to the DEQNA patch panel assembly is ';'correctly connected. Please verlfy that the | ,fuse at the DEQNApatch panel assembly has = rcfrnot blown.j' e E | | _hMacroverify“teet'completed;»- B2 . PEUEA3LF .“>>?'.; | 642 DZVI l/DZQll Dlagnostlc EHXDZ - Device diagnostics, together with the diagnostic supervrsor (VDS) are dlstrrbuted on the MlCl‘OVAX o - System Tests diskette (number 2 of 2). Run the device diagnostic EHXDZ, which runs under VDS, ifan operational failure or the macroverify program 1nd1cates a defectlve DZQll Minimum memory o | requrrement is 512K bytes (mcludlng VDS) o 6 42.1 Settmg Up Procedures - Before runnmg the dlagnostlc make sure thatJumpers Wl to W4 . are mstalled on each DZQll under test TheDZQll 1s shrpped with these jumpers mstalled ) 'Drsconnect all extema] cables from the dlstrlbutlon panel o : .6 4. 22 Bootstrappmg Procedure ~ To boot from theMrcroVAX System Test drskette mount the | dlskette on one of the RXSO drlves and type >>>B DUAI ‘ f“_f"}o‘r; | ) boot from drrve 1 | _ >>>B DUA2 S | | | o | | | boot from drlve 2 - When the boot process is complete the VDS prompt( DS> ) will be dlsplayed You can then attach’ and ) - ‘select’the DZQ11, andrun EHXDZ by means of the normal VDS commands. Thatisto say, commands such as START/ PASS n and SET TRACE wrll functlon There are no EVENT flagsin EHXDZ 6 4.2. 3 RunnmgEHXDZ Thls dragnostlc consrsts of 22 tests Wthh are orgamzedin four parts These are: - Internal loopback tests a Staggered loopback tests b. - Modem test Echo test C. d | - a :._Internal Test In tl‘llS series, tests I to 19 are performed The data lmes are looped back mtemally | 'Detalls of tests 1 to 19 follow e | CSR Test Thxs test accesses the CSR and mampulates each regrster b1t | ‘TCR Test ThlS test accesses the TCR and mampulates each regrster b1t . Transmlt Ready Flag Test ThlS test checks the transmlt ready flag Only one channel is checked. . Transmlt Interrupt Test. ThlS test verlfies that the transmit mterrupt occurs andis at the correct | .prlorlty Only one channelis checked SR -Mamtenance Mode Test. This test verifies that the mamtenance mode loopback works. | correctly. Only one channel1S checked ‘Receive Interrupt Test ThlS test verlfies that thereceive mterrupt occurs andis at the correct, . priority. Only one channelis checked - - | | Interrupt Precedence Test ThlS test verlfies that areceive mterrupt w1ll take precedence overa . -transmrt mterrupt L e , , | Transmlt Ready Test. Tl‘llSis the same as test 3 with the exceptlon that all four channels are | | tested Transmlt Interrupt Test Thls1Sthe same as test 4 W1th the exceptlon that all four channels are i o tested 10. Baud Rate Tlmmg Test. Thrs test verlfles thatmcreasmg the baud rate decreases the 1nter\ al | between transmlt mterrupts | ‘Malntenance Mode Test Tl’llSis the same as test 5 w1th theexceptron that all four channels are tested | Recelve Interrupt Test ThlSis the same as test 6 wrth the exceptlon that all four channels are tested 13. 14 Character Length Test This test verifies that all four channels can transmlt characters of all R | four p0531ble bitlengths | | Stop B1t Test Th1s test verrfles that all four channels can be set for all three possrble stop bit | configurauons , | . .Parlty Bit Test. This test verlfies that all four channels can transmrt characters for all three | p0551ble parlty b1t settings. - 6-21 B 16, Overrun Bit Test ThlS test verrfies that the DZQll can detect an overrun condltlon R | ( 17, LPR Byte Access Test ThlS test venfies that byte acess to the LPR works correctly 1 8. Srlo Blt Test ThlS test venfies that all srlo memory bltSare functlonal and the sflo alarm w1ll be | 19, | PR generated under the rlght condltlons | o Dynamlc Test. ThlS test verlfies that all llnes w1ll functlon at full speed and whendynamlc i o ‘changes are made to programmable lme parameters - b vStaggered Test— Thrs series consrsts of tests 20 and 21 An H329 staggered loopback connector .e S SO must be installedin J1. ~ o | L | - f The H329 connector routes the outputof channelO tothemput ofchannel 1 and vrce versa. Channels | 2 and 3 are connected1n the same way. All four channels are tested | < || i B o ‘j : - ».Detarls oftests 20 and 21 follow 3_ - L .'320 Modem Control Test ThlS test verlfies the modem control functlons It needs manual | = mterventlon and the H329 connector - g , | v - 21 Dynamlc Test Th1s test is 51m11ar to test 19 w1th the exceptlon that tests are performedm .j staggered loopback mode It needs manual 1ntervent10n and the H329 connector | | o c | ‘Modem Test Modem Test consrsts of test 20 only (see Staggered Test) You must 1nstall a H329 B . staggered loopback connector in Jl o e AN R ER < o d “'Echo Test—This test (22) venfies commumcatlons between a DZQl 1 and aterminal. Characters' o ~typed at the terminal are echoed back to the terminal. Echo test has a dialogue which asks the o operator for the parameters of the termmal For example baud rate blts/character parlty, lme to test. LaE | B | | The echo test runs untll you deselect 1t by pressmg CTRL/ Z } 6.4. 2 4 Startmg-Up -Once you have booted the chroVAX System Test dlskette the VDS prompt el | '(DS> ) will be dlsplayed You can then attach the DZQ11 to the bus controller and select it for test. Then you can run EHXDZ. Unless you select a specific test mode, EHXDZ w1ll default tothe 1nternal test. An o example follows of a test in the default mode w1th TRACE set >>>B o e < S DUAl ATTEMPTING BOOTSTRAP | | | lDIAGNOSTIC SUPERVISOR. zz-EHSAA—VG 12- aol o '1;JANe1983'ag:gg,g4'.,*u:;_. e LT 1-."Ds>,attach dzvll hub tta 76@1@@ 3@@‘ "qDS>»se1ect tta,yj ) 'T*,;DS> set tr . ‘DS>lrun ehxdz . Program DZVll/DZQll Funct10na1 Test, ZZ EHXDZ, rev151on 1 Z, 22 tests, | at A0: 03 09 87.';. | | 622 | - | e <\ S 4Test1ng° _;TTA ) 'Test 1: CSR REGISTER TEST Test 2: TCR REGISTER TEST . Test 3: Test 4: TRANSMIT READY FLAG TEST PART ONE TRANSMIT INTERRUPT TEST PART ONE PART ONE MODE TEST NCE 5: MAINTENA . Test Test 6: RECEIVE INTERRUPTCTESTTPART‘ONE. | Test_7:v.RECEIVE;INTERRUPT.TEST PART TwO ’_ Test8:~TRANSMITREADYFLAG TEST'PART TWO | TeSt_Q:»,TRANSMIT INTERRUPT TEST PART WO Test 18: BAUD RATE TIMING TEST .'Test.ll: MAINTENANCE MODE TEST PART TWO Test'12:‘RECEIVE INTERRUPT TEST PART THREE _ Tést»13:‘CHARACTER LENGTH TEST " Test 14: STOP BIT TEST Test'1S:_pARITY BIT TEST -Test'ls:.ovsRRUN BIT TEST ' Test 17: LpR BYTE ACCESS TEST Test-18§ SILO TEST Test 19: INTERACTION TEST ..jEndof run, @ errors detec£ed, pass ¢quht-i$ l,' time is 1 JAN-1983 #@:03:51.17 . DS> . The fo_rmat of -theATTACH command iséXplaihéd below.‘ ‘ DS> ATTACH DZQ11 HUB TTA 760100 300 vector 'l device address name unit (A,B...) | optlon is linked to bus controller : device to be attached ATTACH command - o e 6. 4 2.5 Sectlons - Sectlonis part of the START command By spec1fy1ngthe sectlon you can run ( T 'ftests otherthan 1 to 19. -.The sectrons are:v- : | DEFAULT tests 1 to 19'- T ‘_]INTERNAL — tests1 to 19 j B SRR SRR ~ ALL - tests1to2l (H329 connector needed) MODEM —test20 (H329 connectorneeded) | STAGGERED — tests 20 and 21 (H329 connector needed) | '_‘ECHO = test 22 " (test termmalneeded) | -‘-';Thefollowmg are examples of theuse of SECTION DS> ST/ SEC STAGGERED D5>ST/SECG:ECHO - DS> ST/SEC ALL S 6 4 2.6 - i R T e | B @0 R . S ; run1 tests 20 and 21 ’. run test 22 ; run tests1 to 21 .f T e RS ARt S S ( Error Messages - If a dlagnostlc test detectsan erTor, an error message w1ll be output tothe console. Error messages are describedin the diagnostic listing for EHXDZ. The error message which B followsis from part of a staggered loopback test which was run w1th the H329 connector removed DS> st/sec staggered Program 22 DZVll/DZQll Functlonal Test, '”ZZ—EHXDZ, tests, at @0:04:15.09. SR .'revision_fil;fi,' S L (T "deuTes tlng 'v;TTA‘, h ,]v '.“;'__f .’] “S'f»;' d.v Tv.jb‘p‘ ;' f-;:' T‘ddiTlT .:..\-v Test 20: H329 MODEM CONTROL TEST | | »_' ) o ***i**** DZVll/DZQll Functlonal Test, z2- EHXDZ = 1.0 AEEwkEEs Pass 1, test 28, subtest z, error 3, 1-JAN-1983 oa:o4;16.37’:, Hard error whlle testlng TTA MODEM CONTROL TEST © MSR IN ERROR .‘TthXPECTED-QZGZ(X),-~ | R L | ,. e S ¥ | | O e L , o | (j __: - RBCEIVED aflflo(X) ‘xoa:_ flZflZ(X) col, Rll irl_******** End of Hard error number 3 kAR Akkkk - 6.4.3 TestSequence T | " When a DZQI1 is reportedas defectlve you have the optlon of running Macroverlfy before runnmg . EHXDZ. However 1f the DZQll is clearly mdlcated as bemg defectlve it would be loglcal to run I - Sectlon ALL selects all tests except the echo test. Therefore unless the fault symptoms call for repetmve - Q ~tests of a specific areaof logic, section ALL should be selected for initial test. If NO EITOrS are detected but | symptoms 1nd1cate a defectxve lme the echo test can be run. - v | ~aBus { § asus ¢ - EHXDZ has no specific test for the BCOSL cable or the di_stribtrtion pnnel. | _M3106 affpremma— _M3106 (CONFIGURATION B) - (CONFIGURATION A) Q BUS OR DEFAULT TESTS ~ INTERNAL :1H329 M3106 ' (CONFIGURATION C) 'ALL OR STAGGERED TESTS “TestT | ') QBUS ] TERMINAL | M3106 | T ~ (CONFIGURATION D) ECHO TEST ~ DZQ11 TEST CONFIGURATIONS RD1BBY | Figure 6%.3- ‘DZQl'l Test Configurations_ B i The recommended test sequence is as follows See Flgure 6- 3 for test configuratlons 1. Sw1tch off power Install an H329 staggered loopback connector onlJl (configuratlon C) - 2. | Power up (when the system mlcroverlfy program is complete the console prompt >>> wrll' - 3. 4. be dlsplayed) Boot from the system tests diskette. Atta'chhvand, select the DZQI] for test,;-_, : 625 . 5. Run EHXDZ for three passes of ‘/ SECTION ALL’ If thereis an error, replace the M3 106( ‘-"module (or the H329) S | | Run ECHO test ( configuratlon D) if neededIf thereis an error, replace or reparr the termlnal B o external hne BCOSL or the dlstnbutlon panel To deselect ECHO test, press CTRL/ Z | | Dlsconnect the termmal from the dlStl‘lbUthl‘l panel Remove the dlagnostlc dlskette Reset the system | . | | | L o Boot from the CPUtests dlskette Macrovenfy w1ll run automattcally If a defectlve DZQl 1is . mdlcated check that the address vector and j_]umpers are correct for the system o L _' ‘If the DZQll passes all tests, connect the system for normal operatton | , ,1' :» ~ _ NOTE LR ;Foraconfidencecheckofthe DZQll themternal tests can be run without removing the BCOSL - cable (configuration B). However, external ~ connections should be removed from the dlstrl- | ‘bution panel Sl g i RE LRI I S | ( - IX A APPEND TIONS IC DESCRIP A1 SCOPE common ICs. 4whic:-h are "s_ uSed. in the DZQI 1. The 'smallération This appendix contains data on the LSI'chi‘p e books, are not included. For inform not included in this ~ well described in standard referenc SR | ‘document, read the appropriate manufacturer’s data sheets. A C A2 DC003 INTERRUPT IC | prOVi:»devs.vthe ci'rcui't_s_' to perform an interrupt ‘The interrupt controller is an 1-8_—pin. DIL device that e-pulse’ type arbitration. The device provides two transaction in a computer system that uses a ‘pass-th than the B section. Bus signals use high‘interrupt channels, A and B, with the A section at a higher priority the device to be attached directly to the allow , which a | impedance input circuits or open-collector outputsfrom e the Vcc supply is 140 mA. ‘computer system bus. Maximum current taken ~ Figure A-2, while Figure A-3 shows the timing for both A andB interrup e the signals and pins of the DCO03 by pin and signal name. ~ DCO03 - 'RQSTA_H‘ o - 17 15 12 | 03 - 08 Q L [OBIR 1 EnACLKH ,07'0’ BIAK!I L 0»5 ENASTH | 16 ~ ENA DATAH o) ~ rr‘_up't se_c‘ti.on'is‘showh'in | ~ Figure A-1 is a simplified logic diagram of _thev DCOO3’ IC. Timing for.vthe,-in_te t sections. Table A-1 describes BINITL B ol sBDINL ENBCLKH i | S - BIAKO L [‘r | |NI_TOL D— VECTORH ~ VEC RQSTBH | 02 ENB DATA H Figure_ A--l ' DCOO3' Logic Symbol o R | A SRR e b T ENASTH _ 7-30—= fo— T T e ; :4.1 e T }ka.v ~ ~ RQSTAH - BIRQL . BDINL BIAKIL ~ VECTORH . BIAKO L ~ TIMES A'RElN NAN,OSECONDS, e ~ Figure A2 DC0 A Section 03 Timing | ,\4,(.,01»73, BINIT L ‘MINPOO' - | MIN. CINITO L M—so B 7-35 - _ ENBCLKH - 30 MIN—= | CENBSTH 7-30— [— S BIRQL | 15-65—= RQSTB H j]— CENADATAH ENACLKH ?30M|N———« T ~ ENASTH - RQSTAH . I CBIAKIL 35 MIN —» 3BMIN—s 1 | Lol - VECRQSTBki D NOTE: B 10-45 10-45 VECTORH T 'flMESARElNNANosax»mB e e e T 10-45=-] ~J10-45 5 1'15;65}ff{—:::bE:§§_ | e Flgure A 3 DCOO3 A and B Sectlon Tlmmg A3 S " Table A-1 - DC003 Signals Pin - Symbol I/O' Name_* e Interrupt | Fu‘nction ) 'VECTOR H Vector Gatmg . Slgnal o ”Vector -Request B Thxs 51gnal gates the appropnate vector address to-' - the bus and forms the bus srgnal BRPLY L. e _jV'Ec RQSTBH | When asserted thlS 51gnal mdlcates RQST Bservice ~ vector address is wanted When not asserted it ~indicates RQST A service vector addressis wanted. - VECTOR H is the gating signal for the complete Slgnal ~ vector address; VEC RQST B His normallybit 2 of = -the address b ‘Bus Data In ~ BDINL B The BDIN srgnal always precedes aBIAK 51gnal INITOL. e InitializOut | | ,"Thts is the buffered BINIT L signal used in the | s “deV1ce 1nterface for general 1mt1allzatlon ~ Bus Initialize ~ BINITL | ';When asserted thls 51gnal brlngs all drtve lrnesto‘ therr non-asserted state (e‘ccept INITO L). BIAKOL | N Acknowledge L ~ | ) Bus | Interrupt ~ | BIAKI L).Once passed by a device, it must contmue ~ B v-Acknowledge S ThlS srgnalis the dalsy—chamed signal thatis passed by all devices not requesting interrupt service (see , tobe passed untll a new BIAKI Lis generated BIAKIL "Thls srgnal is the response of the processorto | - BIRQ L true. This signal is daisy- chamed so that ~the first requesting device blocks the signal, while - non-requesting devices pass the signal on as. - BIAKO L to the next device in the chain. The ~leading edge of BIAKI L causes BIRQ L to be B deasserted by the requesting device. Asynchronous BIRQL - Bus Interrupt e Request ) _,-ThlS request is generated when a RQST signal and - ~ the appropriate Interrupt Enable signal become valid. The request is removed after the acceptance of - - the BDIN L signal and on the leading edge of the BIAKI L signal, or the removal of the appropriate - interrupt enable, or by the removal of the approprlate request sngnal Device Interrupt - RQSTB H Request Signal Interrupt | Enable Status B ‘When asserted wrth the enable A/B fllp—flop asserted - ~this signal causes BIRQ L to be asserted on the bus. - This 51gnal line normally stays asserted untll the g N request is serviced. " ENASTH ENBSTH | o 'Thrs 51gnal indicates the state of the mterrupt enable A/B internal flip-flop which is controlled by the signal line ENA/B DATAHand the ENA/B CLK H | clock lme | Pin 15 Interrupt 12 | l/O N_atne A3 Enable clock Symbol | _E’Functlon "ENB DATA_H - ENA/B CLK H signal, determines the state of the B ~internal mterrupt enable A flip-flop. The output of ~ this fhp-flop 1S momtored by the ENA/B ST H -31gnal o | _ | 13 DC003 Slgnals (Cont) ENA DATAH The level on this line, in conjunction with the Enable Date o 14 l‘ Interrupt ~ Table A-l - ENA CLK H ENBCLKH DC004 PROTOCOL IC When asserted (on the posmve edge) interrupt enable A/B flip-flop assumes the state of the ENA/ B o | DATA H sxgnal hne T The protocol chipis a 20-pin DIL device that selects the reglsters prov1dmg the 51gnals necessary to control data flow to and from up to four word registers (eight bytes). Bus signals can be dlrectly attachedto - the device because receivers and drivers are provided on the chip. AnRC delay circuit is provided to slow ~ the response of the peripheral interface to data transfer requests. ‘The circuit is designed so that, if close toleranceis not wanted, only an external 1-kilohm (4 or- 20%) resistor is needed. External RCs can be added to change the delay Ma\umum current taken. from the Vcc supplyis 120 mA o :Flgure A 41is a smphfied logic dlagram of the DCOO4 IC Slgnal tlmmg in relatlon to dlfferent loads1s' - shownin Flgure A-5. Slgnal and pm definmons for the DCO004 are shownin Table A 2. | - 20dVvee omid VECTORH[J BDAL2 L[] BDALT L[ . BDALOL ~19[JENB H 18JRXCXH L 17[JsEL6 - 16[JSELAL BSYNC L[ 15[ SEL2 L ~ BDINL[] 14[]SELOL BRPLY L [T L[ BDOUT lens BSYNCL 13[JouTHBL - 12JouTiBL 1EiNwoL GND ~ Jo 1 - | | LATCH _ENB —— SYNC BDAL2 L[o2}— o 1 LATCH| CP(P(E(? ' DECODER ~ BDAL L [oa]O 17)seLeL "SSEL4L. ' 15[SEL 2 L 1a|secoL —13|OUTHL B L iB —{12jouT ~ BWTBT L|05 8DOUT [os]- N 18]JRXCX H B.RPL-,Y L 1 | ——————o1]vector - BDINL|O7 1linwoL MK-0171 A4 DC004 Simplified Logic Diagram - Figure ( BDAL(2 1 O)L | 15M|N v15MIN ENBH o BSYNCL ' 7 -'i - __ . " SEL(0246)L B ,V. l<—15TO4O BDOUTL' | '%%TTTS t ~ 15M,N_,, l‘_15MIN> i - -| l<——5 TO 30 T | i I ! u- _)__f_J | 5TO30"‘ ]<——>' Fsmso BOINL 5Toso->l ,54— }*——-— —7———*] wol l — I<—5 TO 30 BRPLYL 20T0430—~ T I -foav .<—10T045 ] I | f I * TIME R_EQUIRED TO DISCHARGE RxCx FROM ANY CONDITlON ASSERTED = 150ns ~ NOTE: | TIMES ARE IN NANOSECONDS A-5 DC004 Timing Diagram - Figure A-T - ‘TableA-2 DC004 Pln/ Slgnal Descrlptlons N ~ Signal ~ Pin ) | .' 1 L ‘V'ECTOR{H R T o2 i ~ R | [ .» Vector- Thrs mput causes BRPLY L to be generated through the delay | - circuit. Itis mdependent of BSYNC L and ENB H | B BDAL2 L C | Bus Data Address Lmes These s1gnals are latched at the assert edge of B 3 BDALIL 4 BDAI_D L BSYNCL. Lines?2 and 1 are decoded for the select outputs lmeOis used e for byte selectlon | ’BWTBT ‘L R S B o - S ,*Bus erte Byte- Whrle the BDOUT L mput is asserted thlS srgnal o | ~~Indicates a byte or word operation: asserted = byte, not asserted = word. S ~ " 6 BSYNC L S e L 7 Descrlptlon Decoded w1th BDOUT L and latched BDALO L to form OUTLB L and * ST BDIN L T | 8 - BRP.LY.L o L Bus Reply— Th1s 51gnal is generated through an RC delay by -~ o _latched ENB H. | | Bus Data Out Thisis a strobe 51gnal to effect a data—output transaction. Decoded withBWTBT L and BDALO L to form OUTLB L and OUTHB | o ~ INWD L ) B Bus Data In Thrsis a strobe srgnal to effect a d'ata-tnput ‘transaction;" | B R VECTOR H, and strobed by BDINLor BDOUTL and BSYNC Land 9 R BDOUT L | | E 'Generates BRPLY L through the delay c1rcu1t and INWD L. .. SRR Bus Synchromze At the assert edge OfthlS 51gnal address 1nformatlon is trappedin four latches. When not asserted drsables all outputs except; i | the vector term of BRPLY L. | | ,L Generates BRPLY L through the delay c1rcu1t ~ | In Word Used to gate(read) datafrom aselected regrster tothe data bus - Enabled by BSYNC L and strobed by BDINL. o | e | OUTLB L S Out Low Byte, Out ngh Byte— Used to load(wrlte) data into the lower, 13 - OUTHB L s SR 15 higher, or both bytes of a selected register. Enabled by BSYNC L and N decode of BWTBT L and latched BDALO L, and strobed by BDOUTL. o SELOL SEL2L - ~ SEI4AL 17 SEL6 L S _ | 18 RE N ' o word register has been selected for a data transaction. These signals never ‘become asserted except at the assertion of BSYNC L (then only if ~ ENB H is asserted at that time) and, once asserted are not deasserted - unttl BSYNC Lis deasserted RXCX o Select Lines- One of these four signals is true as a function.ofBDALZ-L' | IfENB H is asserted at the assert edge of BSYNC L. They indicate thata - - | '_ExternalResnstor Capacltor NodeThis nodeis prov1ded to change the - " delay between the BDIN L, BDOUT L, and VECTOR H inputs and “BRPLY L output. The external resistor should be tied to Vcc and the RS L ENBH : capac1tor to ground As an output itis the loglcalinversion of BRPLY L. - Enable — ~Thls srgnal1S latched at the asserted edge of BSYNC L andis & _used to enable the selectoutputs and the address term of BRPLY L. g . S - | A.4 DC005 BUS TRANSCEIVER IC ky device for primary use in peripheral device The 4-bit transceiver 1s a 20-pin DIL low-power Schott n a data bus and peripheral device logic. In addition interfaces. It functions as a bidirectional buffer betweeison circuit for address selection, and a constant ‘to the isolation function, it also provides a compar bus 1/0 and port provides high-impedance inputs addresses. The generator, useful for interrupt vector device ral periphe the On er. comput ofa tion to the data bus o open-collector outputs to allow direct connec standard TTL inputs and 20 mA tri-state drivers. Dataon with d, provide also is l port ctiona bidire a ~ side, | T this port has the opposite polarity to the data on the bus side. | | | si"gn_a] " Three address jumper in-pu‘ts’j__aré_'used to COmp'lare again,s't' threefl‘bus' ‘inp'uts and to ge'ner'até the iver to transce one than more of output the allows MATCH. The MATCH output is open-collector, which The address jumpers can also be putinto a third signal. " be wire-ANDed to form a combined address matchaddress match, allowing for ‘don’t care’ address bits. In the logical state that disconnects that jumper froma fourth high-impedance input line is used to enable/disable ‘addition to the three address jumper inputs, e S e | the MATCH output. sed to the computer bu_s. The o to generate a constant, that can be‘pas Three vector jumper inputs are used the action of the control lines. three inputs directly drive three of the bus lines, overriding | _Two control signals are decoded to givve three operation states: receiver data, transmit data, and disablé. wn inRFigure A-7.T ) fuhctions i»s»sho‘ for the3 TimingA IC.Table diagram _of5theareDC005 fied logic Figure A-6ispinasimpli S giveinn definitions for the DCOO - Signal and Pin 12 Name . Funct’iofi__ | . Open-collect BUSIL '8 BUSIL 17 7 DAT2H ed - carry the invert four tri-state lines e Data — Thesewhen PeripheraldataDevic e receiv the in is iver transce the from BUS<3:0> OH 18 -~ DAT DAT1 H 6 DAT3H 14 IVl H - 15 ) received carried on these lines is mode. When in transmit data mode. inthethedata disabled mode. these lines go passed inverted to BUS<3:0>. When | - open (high impedance). High=1. '- JV2H JV3H 16 13 MENBL 3 Ll MATCH H : resiStors; internal pull-down causes These input‘s. with L Vect'01"Ju'r11pen's"'%." an pin jumper the on open or low A . BUS<3:1> directly drive H is low. A high open condition on the correspondingtheBUSBUSpinpin.if XMIT BU SO Lisnot | that Note on d mitte trans causesa | (low) to be - controlled by any jumper input. | | - v the bus side of the transceiver. set of four lines makesceupinputs; ~ Bus Data- This low = 1. or outputs; high-impedan BUSO L 11 | ‘Table A-3 DCOOS Pin/Si‘gnal'DeSc:r'iption‘s . T . A high s the MATCH output Match Enable- A low on this line enable match circuit. ng forces MATCH low, overridithe | | and :1> matches the state o-f.JA<-3: 1>SR Address Match - When BUS<3 low. is it ise. is open: otherw MENRB L is low. this output A9 Table A 3 'v'Name DCOOS Pm/ Slgnal Descrlptlons (Cont) F unctlon 'Address Jumpers— A connectjon to ground on these mputs allows a - match to occur with a 1 (low) on the corresponding BUS line. An open allows a match with a 0 (high). A connection to Vcc dlsconnects the ' *-correspondmg address bit from the comparlson | | ) Control Inputs - These lmes control the operat1on ofthe transcelver as ‘follows | | | | | REC XMIT 0 1 1 | S ' DISABLE: BUS and DAT open 1 XMIT DATA: DAT to BUS 0 RECEIVE: BUS to DAT 1- | RECEIVE: BUS to DAT o To prevent tri-state overlap condltlons an mternal circuit delays the ~ ~ ~ change of modes between XMIT DATA and RECEIVE mode, and delays the enabling of tri-state drivers on the DAT hnes ThlS action is independent of the DISABLE mode sl JATL JA2L '--'20 vee 14 19 JA3 L 24 18 DATOH 3MATCHH OXMITH - H DAT3 54 66— 17 DAT1 H - DCO05 |15 JV2 H H - 14 JV1 F13MENBL H 7DAT2 8S3 BUL 9+ L CBUS2 GND 16 JV3H 12BUSOL 104 T 11 BUSL }:‘{.@ DATC H BUSO BUS1T | Vi1 ooH DAT1 H AT, - BUS2 Ny CUV2OH DAT2 H ) H Jv3 JA2 H DAT3 BUS3 JA3 53 MATCH H. | CXMIT MK 0170 REC !EI—-VCC [0 GND * Figure A6 DC005 Simplified Logic Diagram A-11 | ' *REcHxGROUNDX* ~ - TRANSMIT DATA TO BUS s g F?5TQ3055' _.1_;4L; kg5To3ons BUS L - OUTPUT — , .i,;‘-q‘; T T - DATf{~fNPUT', s - 1 RECEIVE DATA FROM BUS (BUS INITIALLY HIGH) XMITH(GROUND) ~ RECH 7774 ~ DATH-OUTPUT e |+0TO30ns —— - CoBUSL-INPUTT =~ ] 4 N R0TO30ns S |+~8T030ns RECEIVE DATA FROMBUS (BUS INITIALLY — LOW) "XMrrH{GROUND)t SUEE . RECH T [ = /... [£0T030ns '+ l-0TO30ns [8T030ms ~ VECTOR TRANSFER TOBUS ~ BU - OUTP SL UT = ‘ -~ = 20nsMAX ns MAX 20 ~ ADDRESS DECODING| . BUSL--INPUT X MATCHH CmensL ~ CoxMiTH T + A X 5T040ns | L SR ~ +__i0T040ns RECEIVE MODE LOGIC DELAY T [ RECH ~ DAT (3:0 H (QUTPUT) . LR -Fi’gurevA'-7., DCOOS Tlmmg Dia’grah»l A2 | MK 0174 A5 DC367B SEMI-‘CUSTOMVLSI.IC o | | e e A. 5 1 Descrlptlon TAL Itis o]ogy techn S CMO in tmplemented spec1a1 VLSI sem1custoC)m IC The DC367B is a DIGI tc leade is etther socket or surface mounted and (PLC er carri chtp d = ’packagedin a 68-pm plast t baudrate generator Ts one 16-outputple tonalitems: foursiloUAR ins the followmg funct The DC367B conta11 xers bi-directional mu]t logic, ol ve and contr Section 5.4 glves registers, transmit, recei all necessaryDZQ Figu adescriptionof | and e, devic 10 shows the contentsbeof the ~ buffers and other logic.spemficare5tlonsof the device w1ll glven here, together with a pin descnptlon . the mrcuttry Some | | | | I ~AS. 2 Pin Layout pm | ames then hsts A-4 e Tabl s. name and ers pm posmon to pin numb Figure A-8 shows the layout hnkmgton 14 «—s D11S E DI SRS 29 <« DOS 23 <> D04 24 <> DO3 25« DO2 26 <—>| DO1 L "w—to —» ool S C +V DT1 p—= 60 181 |~ 58 TCK fe— 56 I DU I LT O fws e s AR ~ ORY fe— 54 . pcse7B R T I F . e S GND |— 52 s01 |—= 51 slo p—50 Sst1 b= 49 16 =—»{ D09 BT 18 — GND 19— v 0 a7 21 -] DOE N D | | 12 «— D13 17 <—»{ DO8 1 1 Nc)cn""> 3 1\ o—w B 62 61 | 63 4 67 66 615 61 618 S S G S N — r 7<‘O mOZ le— r—.og «— 00 1 L l l wom """".b 4——@ 'numbers and describes the funct R - A e | R o S - | S . R ' Ry [=—53 . sl2 | 48 . 8l3 b 47 sLa — 46 SL_5.."f—"<45‘ | voop— 4 mPYRS? | »f | Table A-4 DC367B Pm/Slgnal Descrlptlons - Mnemonic . ,F unctlon [y s ‘ f-‘f;{sro e SR GROUND Connects to O V SERIAL INPUT 0 -Data input line 0~ SERIAL INPUT I - Data input line1 SERIAL INPUT 2 - Data input line 2 SERIAL INPUT 3 - Data mput lme 3 | cLOCK-5.0688 MHz clock, active low. » 'MASTERCLEAR LOW Clears all reglsters except DTR reglsters - ,' MODEM CLEAR LOW Clears all reglsters D15 . e DATA LINE 15 Connects to DAL15 H tr1-state output only, notan +5V-COnnectsto'—l-‘SV" ', ' D13 7 e - ‘ e DATA LINE l4Connects to DAL14 H bl-dlrectronal I/ O lme - DATA LIN E 13 - Connects to DALl3 H; tr1 state output only, not an | 1nput b to 17 mcludmg DTRregrsters | ( | DATA LIN ES 12/ 08Connects to DALl 2 H through to DALOS H bi- - toD0O8 - _dlrectlonal I/O lines. . "GROUND - Connects to ’O V |: +35 V Connectsto +5 V 20 e ,*_t026 ) fto DOl ~ DATA LIN ES 07/01- Connects to DALO7 H through DADOI H biR d1rect10na1 I/ O lines. | +5 V Connects to +5 V : DATA LIN E 00 - Connects to DALOO H bl—dlrectronal I/O llne o o “J"_NOT CONNECTEDSpare not connected " REGISTER ADDRESS B/A- RGB and RGA form the address ofthe‘ - register m read/ wrlte operatlons WRITE HI-BYTE HIGH - erte | strobe to hlgh byte of a reglster o WRITE LO- BYTE HIGH erte strobe to low byte of a regrste r | S READ HIGH GRO UND Read strobe from a regxster Connec ts Al4 to 0 V. = y B Table A4 DC367B Pm/Slgnal Descnptlons (Cont) - Pin | ;Mnemomc‘ el :'Functron | " FRAMING ERROR ON LINE 3 H - Output lndlcatmg a break on DV -A hlgh level mdlcates data at end of 5110is vand 'DATA VALID "RI ",RECEIVERINTERRUPT Interrupts CPU if enabled on RDONE or TI o TRANSMITTER INTERRUPT -Interrupts CPU lf enabled on - s23 B VSHIFTIN SILOS TWO AND THREE Sh1ft—1n pulse for silo data on. — '- ,»channel three ‘used to halt or ‘boot a system. [ | o F3H 36 40 | - silo alarm as selected | | PR the two high- order 5110 ChlpS | | s | B ,SL'7" 43 GND ‘ 4 +_V 45 SL5 'SILO DATA 5100 -Silo data lmes 5 to 0 data shlfted from DC367B | Sl » = ’SOll ~ SHIFT-IN SILOS ZERO AND ONE Sh1ft-m pulse for silo dataon o 50 toSL6 to SLO | o 5.2 o - GND '53_ | - IRY . o a - 41‘ o to42 | o SILO DATA 7to6- Srlo data hnes 7 and 6 data shtfted frorn DC367B into silo. GROUND Connects to 0 V. o . +5 V Connects to +5 V mto silo. I [ IR - - | 'GROUND - Connects to 0 V | o the two low-order srlo chrps e | IN READY- Signal to the DC367B that all silos are read} for mput 54 . ORY | - Signal to the DC367Bthat all silosaz re read} foroutput | | OUT READY 55 EMS FULL MODEM SUPPORT- An option (not used on DZQ11) which 56 TCK — Used for chip testing. With TS1 hrgh thlsis selectedin TEST CLOCK 57 "TSO - | o L o - | TSI T ‘when asserted high forces the DC367B to leave D04 to DO7 and D12to ‘D15 in their high-impedance state during read operations on the MSR. - instead of asserting them zero. This allows other modem 1nputs (CTS and | | L DSR) to be enabled to the DAL bus .place of the 19. 8K baud internal baud rate TEST 0 - When htgh selects the baud rate generator outputs mstead of _ the normal serial data outputs. SIO and SI1 must be low to read the spec1f'1c “baud rate out. Used for chip testing. | - TEST 1 - When high, selects the TCK input mstead of 19.8K baud for ~any UARTSs whose line parameters have selected this baud rate. This ~ allows the use of an external clocl\ offrequenC\ 16 times the w anted baud rate. A-15 o Table A-4 DC367B Pm/Slgnal Descuptlons (Cont) Pin L 59 060 Mnemomc - DTO | Functlon a ,DATA TERMINAL READY Actlve-low outputs of the DTR. : to DT1 o o .reglsters for lines O and l ::L:A61T LE 45 V-Connect to +5 A 62 'DATA TERMINAL READY Actlve—low outputs of the DTR ', o to 63 | reglsters for llnes 2 and 3. - 64 . oscL | LM65LLL . to 68, - .'SCXJ.A’ SILO CLEAR LOW - Connects to the clear lmes of the s1lo ChlpS = ' output of the Master Scan Enable latch | SERIAL OUT 0/3 Actlve hlgh serlal output lmes 1dle state is hlgh ~to SO3 A 5 3 Speclficatlons of Some Parameters . - -ThlS paragraph gives specrficatlons of some parameters not glven in the main text. A53l Baud Rate Accuracy — Table A—2 lists the baud rates and thelr drvxder ratlos w1th respect.to the 5 0688 MH:z system clock and glves the computed devxatlon from nommal S . Table A 5 Baud Rate Accuracy -_'LPRbns[f_ Baud Rate 09, 08___v‘ Divisor of 5.0688 MHz (m bits ~clock ~ per second) S0 0001 0010 f6336”{ ~75_ | L 0% 2880 o110 150 % Frequency - deviation | from nommal | 0% 4224 +0.144% 1345 0100 | | MTZIIZ,‘ O%., ‘_ s 1056 0110 600 o111 1200 1000 1001 12400 0% 2 O% . "fenlgbo'al.s 2000 o 158 '"°.»096;3=*' - +o 253%', 132 S 3600 t ', _Table_ A-5 :BaudiRate_Accura,cy'(com)'~ - Divisorof Baud Rate 'LPR bits 11,10, 09, 08 : 5.0688 MHz (inbits clock ~ persecond) 1100 1101 4800 7200 1110 9600 | deviation flom nommal 0% 66 44 -fi','-._,"'o%go B T R B 0% 0%(**) 16 19800'. P 11 11 % Frequency s .(**) Because the standard is. 19200 baud, thxs optton is not supported as 19800 baud represents a +3 125 % | | devxatlon which is not acceptable | .’A 53.2 Recelver Parameters - The receiver w1ll accept an edge mlsallgnment of up to 40% (more i | accurately 43.75%), which represents one sixteenth of a bit from a 50% deviation (as a result of using a 16X clock). This edge misalignment may be caused by either edge jitter or an accumulatlon of edge errors | 'caused by an 1ncorrect clock over the full character transmlssmn - The recelver w1ll also work downtoahalf stop b1t between rece1ved characters HVA 5.3. 3 Read/Wnte Pulses and Data Delay - Each write pulse (WHH and WLH) has to be 390 ns minimum. Data may stay unsteady up to 150 ns after the pulse, but must be steady from then until 45 ns after the pulse has been removed. These specifications will guarantee operatlon in worst case ~ commercial condmons (0 to 70 degrees centlgrade 4.75 to 5 25 volts) “With read operatlons thereis a 50 ns delay worst case between RDH being asserted/ deasserted and data = I ‘bemg steady or bemg removed (hlgh 1mpedance) from the I/ O llnes e A6 3341 FIFO SERIAL MEMORY | The 3341 first-in-first-out memory chip asserts Input Ready when 1t is ready to load data. Each time thft | Inis asserted, the chip accepts four bits of parallel data. When the Shift In pin is de-asserted, Input Ready - also becomes de-asserted after a short delay. When both ptns are Low data starts to shlft tothe output end | of the 64 X 4-bit register. 'When data reaches the output, it asserts Output Ready When Shtft Out1S asserted the ch1p places the ‘data in the output latches (Figure A-9). When the Shift Out pin is de-asserted. Output Ready also B becomes de-asserted after a short delay ‘When both pins are Low the next data (1f available). bubbles | - down to the output. | | | | ‘. : B e - Di—*-_,'i";UOT, S ——\] e - D2 —*sTAGE [ | INPUT READY <~ INPUT g : SHIFTIN = 3 |conTROL| b——— S I LA 64 WORD x 4 BIT 1 foutPuTtfin MAINREGISTER R STAGE [~ Q2 R $>’MA'N REGISTER L 0GIC ?Vss PIN 16: e 'CONTROL LOGIC e B } OUTPUT 1 e~ SHlFTOUT conTRoL| 14 “1Logic | = OUTPUT READY T VGG__ __VPlN 1 R TS R T A P At ~LoGicsymsOL 2 - INPUT | SHIFT| READY e R .o OQuUT e 3 ——sHieTn QYTPUTL TS Rl CREADY [ ' . | _‘ e EE o S | 7 —0os. | a3 pb—10 MASTER RESET (TOPVIEW) vGG C o e[ R ~ INPUT READY [J2 4y o . ) 5 :SHIFTOUT | o ‘[)2.[:»6_ - Ul wo[Jaz ‘ ST o MK 0167 . ?9,,_ ‘Vpp=PINBGND VGG =PINT-12V S 1y : Q2 0307 | vss G - -14-:] ey SHIFTIN E--:, OUTPUT READY opb—11t 6 — 0z | _PINCONFJGUR‘ATION - ST I e e e Figure A9 3341FIFOSer1al Memory S el R e : - ~ APPENDIX B GLOSSARY OF TERMS 'B.l SCOPE | S , - for easy This appendix contalns a glossary of terrns usedin this manual The terms are in alphabetrc order IR o L reference ~ B. 2 GLOSSARY Asynchronous A method of ser1a1 transmlss1on in Wthh datais preceded by a start b1t and followed by o a stop b1t The receiverprovrdes the average t1m1ngto 1dent1fy the data brts Auto-answer The facrhty of a modem or termmal to automatlcally answer a call | -BDAL Bus data and address llne - - Base address The address of the CSR ’ CSR Control and status reglster l standards ) CCITT Comlte Consultatlf Internatlonal de Telephome et de Telegraphle An mternatlona - | commrttee for telephone telegraph and data commumcatlons networks ~ _Dataset See modem | DIL Dual—m lme The term descrlbes ICs and components W1th two parallel rows of pins. 3 DMA Direct memory access. A method Wthh allows a bus master to transfer data to or from system ) - memory w1thout usmg the host CPU | | » _Duplex A method of transmxttmg and recelvmg on the same channel at the same t1me EIA Electrlcal Industrles of Amerlca An Amerlcan orgamzat1on thh the same fUIlCthIl as CCITT : - o EMC Electromagnetlc compatrbxhty The term means comphance w1th field strength susceptlblht\ - and static dlscharge standards. n Wthh regulates and hcences N FCC F ederal Commumcatlons Commlssmn An Amerlcan orgamzatlo | communications equrpment . FIFO Flrst In First Out. The term descrlbes a reglster or memoryfrom Wthh the oldest dataisremoved first. It1s often referred to as a silo. ’Floatmg address A CSR address a551gned to an optlon which does not have a fixed address allocatcd | The address is dependent on other floatmg address dev1ces connected to the bus Floatmg vector ‘An mterrupt vector assigned to an option Wthh does not have a fixed vector alloc ated - The vector 1s dependent on other floatmg vector dewces connected to the bus. Bl - | FRU 'F,iveld—re’pla'ce‘able‘unit. 5 et ,IC' Integrated circuit 1I/OInput/output —_— LSB Least—sxgmficant b1t o LSI 11 bus Another name for the Qbus i ‘Modem The wordis an abbrev1atlon of MOdulatorDEModulator A modem mterfaces a termmal to a - transmlssron llne A modem1S also called a dataset o | - B MSB Most—51gn1f'1cant b1t S Multlplexer A c1rcu1t Wl’llCh connects a number of lmes to one lme e : < : Null modem A cable Wthh allows two termmals Wthh use modem control srgnals to be connected - together dlrectly Only poss1ble over short dlstances PCB» Prmted'ctrcunt .board.S PLCC ’Plastifc-leaded chip carrier | A 'Protocol A set of rules whrch define the control and flow of datain a commumcatlons system Q bus A global term for a specxfic DIGITAL bus on wh1ch the address and data are multlplexed "vVQ22Q18 and Q16 Terms used to define 22- 18 and 16 b1t—address versxons of the Qbus | A‘_‘RFI Radlo frequency mterference . | R SMPS Sw1tch-mode power supply - UART Umversal asynchronous recelver transmltter An 1C used to transmit and receive serial ( asynchronous data on a channel Digital Equipment Corporation - Bedford, MA 01730
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