Digital PDFs

EK-DZ110-TM-002

2000

126 pages

Original

27MB

view download

OCR Version

8.2MB

view download

Document:	DZ11 Asynchronous Multiplexer Technical Manual
Order Number:	EK-DZ110-TM
Revision:	002
Pages:	126
Original Filename:

OCR Text

DZ211

asynchronous multiplexer
technical manual

dlilgliltiall

EK-DZ110-TM-002

DZ11
asynchronous multiplexer

technical manual

digital equipment corporation « maynard, massachusetts

Copyright © 1977, 1978 by Digital Equipment Corporation
The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in this
manual.

This document was set on DIGITAL’s DECset-8000
computerized

typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:

DEC

DECtape

DECCOMM

DECUS

RSTS

DIGITAL

TYPESET-8

DECsystem-10

DECSYSTEM-20

MASSBUS

PDP

TYPESET-11
UNIBUS

Preliminary Edition, January 1977
Ist Edition, November 1977
3rd Printing (Rev), October 1978

CONTENTS

Page

CHAPTER 1

GENERAL DESCRIPTION

1.1

INTRODUCTION .............................................................................................. 1-1

1.2

PHYSICAL DESCRIPTION.............................................................................. 1-2

DZ11 Configurations .......... ererieeeans ereedeees vererrerenhe tereeieetneereresereresenaesansesas 1-3

1.2.1

1.3

GENERAL SPECIFICATIONS. ............ e Re et
aa e aaa 1-8
Outputs....... ettt e ee et ieetr et a et et et et e e araares eerrererntrenarnanseeieereeenreerereroenenns 1-9

DZ11-A, -B, and E ...................e reerteeeetieerreetneerrrerraerataerraaerarneerras 1-9

1.3.1.1

DZ11-C, -D, and -F ............................... 1-9

13.12

Inputs ........................................................................................................... 1-9

1.3.2
1.3.3

1.3.4
1.3.5

Power Requlrements DZ11-A, -B, and B, 1-9
-

Power Requirements, DZ11-C, -D, and -F......... e eeeeitterteereetiseberaeererrerarernes 1-9

'Environmental Requirements
- All DZ11Suiiiiiiiiiiciee

e, 1-10

1.3.6

Distortion- DZ11-A, -B, and -E............. viarbiressiseieeaesesaesesistaseresees 1-10

1.3.7

Interrupts......._..4.,.,............................v....»....-.........;..v ...................................... 1-10

1.3.8

Line Speed.........ccccovmmniviniinnnnnnnn. eeerrensseieeiresssanntienssneiaseneecs e 1-10

1.3.9

Distance (DZ11-A, -B, and E) ..........................................e 1-11

1.3.10
1.4

Distance (DZ11-C, -D, and -F) ....... S

OSO iereerrereneens erieerie 1-11

FUNCTIONAL DESCRIPTION ..ottt 1-11

1.4.1

PDP-11 UnNibDUS INEEITACE. .. eeeeiieeeeeeeeeeeeeeeeee
e eeeeeeeeee e
eseeeeeeeeeserraeeeeeesanene 1-12

1.4.2

~Control Logic.......ccvvevvviiniiirennennnnn, siereiiersnnennrinisnrsensrbniionsiennrensarsseransnnes 1-12

1.4.3

~Line Interface....... et e trerreer

CHAPTER 2

e e raeeras L irierhar
e starenreenees eeerteerrie e, 1-13

INSTALLATION

24.2

SCOPE ...ttt
v et e st e e e s e et e e et e et e araaaeanan 2-1
CONFIGURATION DIFFERENCES ...ttt
eaans 2-1
UNPACKING AND INSPECTION........ccc.cevvvee.e ettt
et earerararaans 2-1
INSTALLATION PROCEDURE......ccccooevvviiiieriieeiet
aaaaa, 2-1
- H317 Distribution Panel and Static Filter InStallation..........oeveveeverreresrrenns 2-1
EIA Option......... . PP PPPPP”. Y |
20 mA Option........ccccuuneene..S SUTUTT ereenenen ettt
e et ae et eraaaans 2-2
M7819 Module Installation.........cc.ccuveneee..e tereentetetteenieeteen
et seaetnraatesnans 2-2

243

M7814 Module Installation ...........cccovenenee. rerineeeens SR et

2.1

2.2
2.3

24.1
24.1.1

24.1.2

i1l

270

CONTENTS (CONT)

Page

CHAPTER 3

PROGRAMMING

3.1

INTRODUCGTION. ...
e e e e e wn3-1

3.1.1

3.2
3.2.1

3.2.2

Device and Vector Address ASSIZNMENES ........oecvvevviveiieeiiiieirneerineereneeeennnne. 3-1
REGISTER BIT ASSIGNMENTS ... 3-2

Control and Status Register (CSR) ..........ovveiiiiiiiiiiiiiiiiiiieeee
000 372
Receiver Buffer (RBUF)............. et
teeeetiereetir et e e et e ettt ettaeaeteerrnreearnneaes 3-6

3.2.3

Line Parameter Register (LPR)........c.ovviviiiviiiiiiiiiic
e 3-7

3.2.4

Transmit Control Register (TCR)..........coviiiiiiiiiiiiiiiiiiic
e, 3-8

3.25

Modem Status Register (MSR)............... et ttrerttreeerteetabeerterabaerrreaeraanes 3-9

3.2.6

Transmit Data Register (TDR)......ccooovvviiiiiiiiiii

e 3-9

PROGRAMMING FEATURES ...t 3-9

3.3.1

Baud Rate............ eeeeteierecareterinestraettaneernresteninsonsetrerettetatsteraseentnteenasaserante 3-9

3.3.2

Character Length...........cooviiiiiiiiiiiiii
e
e 3-10

3.3.3

Stop Bits................... ett eteeeeeteeetteetteeet
e etee et teaeatneerherataeraneerheeraeeranes 3-10

334

PaTIY oot e
et e 3-10

335

I OITUDLS coeeieiie e 3-10

3.3.6

Emptying the Silo ... 3-11

3.3.7

Transmitting@ CRaraCter..........oviiiiiiiiiiiiiiiii et
e et e e eeans 3-12

3.3.8

Data Set Control ........cooeevvviiviiiiiinnnnenn. e eeeertreertreeethreerreeeraeertaerareerranes 3-13

3.4

PROGRAMMING EXAMPLES ... 3-13

CHAPTER 4

DETAILED DESCRIPTION

4.1

SCOPE ..o

4.2

LINE-TO-UNIBUS OVERALL DATA FLOW (RECEIVE) .............................. 4-1

4.3

UNIBUS-TO-LINE OVERALL DATA FLOW (TRANSMIT) ......ccovvvvviennnnne, 4-2

4.4

FUNCTIONAL BLOCK DESCRIPTION......coivtiiiiieiiee

4.4.1

ee es

e st

e sa e s st e e eenaas 4-1

e 4-3

Unibus Interface..........ccccoeeeviiviivinnniiiinnnnnnn. et
et e et e et e e
rrrs 4-3

4.4.1.1

Address SEleCtion .......cuuuviiiiiiiiiiiiii

44.1.2

Interrupt Control ................. U
PPURPRRRURRNY - B, |

44.1.3

e 4-3

Data Transceivers and Output Multiplexers...........cccvveeriiiivineeeiinnnnnee. 4-3

4.4.2

SCANNET ....cevviieieriiie

44.3

Universal Asynchronous Receiver-Transmitter (UART)...........covvvvvieienenieiiennnne, 4-5
DETAILED FUNCTIONAL DESCRIPTION ....ouuttiieeeeeeeeeeeeeeeeeeeeeveeeee
e 4-7

4.5
4.5.1

eOO

TRRRRRRRRRY” B

Address SEleCtion LOZIC......ccuvireveerieeeeeeeeeeee
e eeeeeeeeeeeeeeeeseeeeseeeseeeseseennes 4-7

4.5.2

Receiver Interrupt Control.......ooovvuiiiiniiiiiiiie e 4-7

4.5.3

Transmitter Interrupt Control........cccooovviiiiiiiiiiiiiiii

4.5.4

Data TTaNSCEIVETS.
..uuuiiiiiieieeiiiiiiee ettt ee

e 4-7

e e e e et e s e teaa s eesennseeeeeenas 4-7

4.5.5

OULPUL MU IPIEXETS ..euvniiiiiieiiiie ettt
e ee
esaeeeeenns 4-7

4.5.6

ReceiVEr Control LOZIC.....viiiiiiiiiiiiiiiiiiiiiiee ettt
ee e e eaeeens 4-8

4.5.7

Transmit CONtrOl LOZIC....cuuuiiiiiiiiiiiiiieeeeeeeeeee ettt e e ee

4.5.8

LS4
L 1 o J PR
TRTPPR 4-25

e eeeeeeeeeeans 4-8

CONTENTS (CONT)

Page
4.5.8.1

Control and Status Reglster ......................... Venirenrerenedansecenretsrarernerrnnros 4-25

4.5.8.2

Receiver BUITer......cuuviiiiiiii e 4-25

4.5.8.3

Line Parameter Register ..., 4-25

4.5.8.4

Transmit Control Register......................e eerr et ettt eettrsatesaeaareenas 4-25

4.5.8.5

Modem Status Register............... ettt neatneeettrreteeetre
et ert e rateraranarrans 4-29

4.5.8.6

Transmit Data Register ....... e 4-29

CHAPTER 5

MAINTENANCE

5.1

MAINTENANCE PHILOSOPHY ..o 5-1

PREVENTIVE MAINTENANCE..........cc.ceevvnnennn.. etrttreeettie
e e et e rera e e et enaans 5-1

5.3

TEST EQUIPMENT REQUIRED....................et rretter
et erarieerr et raerareeaaans 5-1

5.4

DZ11 MAINTENANCE SOFTWARE .......ccccooii, 5-2

5.5
5.5.1

Internal Loopback Mode................... e 5-2

5.5.2

Staggered Loopback Mode.............. eee et et e raaa, e 5-2

5.5.3

External Mode ..........et tteeeteeteeeraeeeteetteeaeaan

5.54

On-Line with Terminal.........cccovvvvnenennen.o reereeeenreererararanes et

et tan ettt etnaetreerraearteearrernns 5-2
ettt taearaenans 5-2

APPENDIX A

DZ11 (M7814) TO AN ACTIVE DEVICE INSTALLATION

APPENDIX B

UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART)

APPENDIX C

DUAL BAUD RATE GENERATOR (COMSOIG)

APPENDIX D

INTEGRATED CIRCUITS

FIGURES

Figure No.

Title

Page

1-1

Dle System P2 0] o) § (o 1410 o 1. S 1-1

1-2

DZ11 EIA Module (M7819), Distribution Panel (H317-E), Static Filter

(H7004C), and Cables (BCO6L-0J and BCOSW-135)....c.ccooiviiiiiniinniiiniiin
122

DZ11 20 mA Module (M7814), Distribution Panel (H317-F), Static Filter
Pramcach

H3271 or H327 TUINATOUNA ....vvvviiiiiiiecciiieieee
ettt ettt e e e e saaaraaeree
e 1-5

DZ11 Hardware INnterconneCtions .........cccuuvveirivieieriiiiiiieciiieeeeereereeeereeeeneeenanae, 1-4

[

(H7004B), and Cables (BCO6K-0J and BCOBS-15) ....ivvuviviiiiiiiiiiiineeiieeeeieeeeeen 1-3

FIGURES (CONT)

Title

Figure No

Page

Test Connectors H327, H3190, H3271, and H325 O T e 1-6

H3190 Staggered Line Turnaround...........cccocovviiiiiiiiiiiiiiiii

et 1-7

General Functional Block Diagram.........e PRI 1-12
M7819 Address Selection ..........ceeevvviiiieiiiiiiiiiiiiiccc
e ererrrr e 2-3
MT819 Vector SElECtiON.......ccuuuiiiiiiiiiieie
e
e 2-3

BCO5W-15 and BC08S-15 Interconnectlon ................................... et 2-5
M7814 Address SEIECtiOn .........ccvuiiiiiiiiiiiiiiiic

e 2-6

MT814 Vector SElECtION......uuiiiiiiiiiiiiiie e

BCOAR Cable ..o

e eera s e eaes 2-7

e 2-8

H317F Distribution Panel Terminal Reference...............cccoeevvvviiiiiiniinnnnnn.n. eeeeaas 2-9
Register Bit Assignments........... ereerer
e e e aaaaas eeetereterenetieenrrertiesraetreneransentssnnre 3-3
~

Line-to-Unibus Data Flow (Receive)............oo.........e e

rer e er

e e 4-2

Unibus-to-Line Data Flow (Transmit).......et
e et e e a et aaaanet 4-2
Unibus Interface Block Diagram...........cccccceeneee, et
e et
aaaaene v 4-4
Address Selection SWILChES........covviiiiiiiiiiiiii

e 4-4

A dAress WOord FOTIMAL ....o.veueeveeeeeeieeeeeeeeeeeeeeeseeeeereeeeeeeeeeeeeeeeeeeeeeeeeseseeseresenn, 4-5
Output Data Multiplexer Bit Correlation .............ccoevvvvviiiiiiiiniiiiiin

e, 4-5

Scanner Block Diagram............... T 4-6
UART Block Diagram....................... e ett

aeee et e et e e

e e rreaerans 4-6

Address Selection Logic ..................... ett teeeteeeteetteeetteeetaeettaeerreeataerataeertaaarraeraen 4-9

Interrupt Control Loglc.........................., ......... reverenterennens e 4-11

‘Unibus Data Flow.................... rerieuierarsieeenirnrnrnrranas f ettt et ee ettt rre e raaanans 4-12
RECEIVET COMETOI LOZIC. ... eveeeeeteeeeeeeteeeeeeeee
et eeeeee e eeeeeeeeeeaeeeeeeseeeeeseeneereseeaneens 4-14
-

DZ11 Scanner Timing........ e, et eteeneet
et eieetaeteenereraeraeraerraaaereaaes 4-17

Silo Character Shift Out Tlmmg Dlagram ........................................................... 4-19
Transmit Control Logic..............ccvunveenne. P U 4-21
Transmit Control Timing ..........cccccvvvvvevvnnnnn.. ett

e et e e et e e et e raaeraeraeaanns 4-23

(ON
3 QDT
T4 - 1 o DR 4-26
LPR Diagram.............cccovivvnnrnnnnn... . 4-27
Line Parameter Loading........ccuuiviiiiiiiiiiniiiii

et 4-29

1\ N0 2 B T T ¢ U+ s DU
PROPPRRRTPRI 4-29
DZ11 (M7814) to Active Device CONNECtioN .........ccuuvvvivueeiiiiirieiiiieeeiereeeeeenenneee. A-1
H319 Current Loop Receiver Schematic Diagram ..............coevvviviiviiiiiineiiinnnnennn, A-2

Format of Typical Input/Output Serial Character .................ccccovvvvvvvvevvirerenennnnnn, B-1
UART Transmitter Block Diagram and Simplified Timing Diagram ................... B-2
UART Receiver Block Diagram and Simplified Timing Diagram ........................ B-3
B-4

UART Signal/Pin Designations ........ccccceeeieiieiieiiieeeeieeeieiieeeeeeeeeeeeeeevvenneeeeeeennen, ...B-4
Dual Baud Rate Generator Block Diagram ....... eeetreererenererrereeatratraeerarrraneeannns C-1
COMS5016 Pin Assignments ............................ everieinreereertrrertraaetrrr
et eraereeranonnsens C-2

TABLES

Title

DZ11 Model Configurations.........cc..ccvunennn.n. eereerrreeraaeraa reeerens e errreena . 1-4
DZ11 Performance Parameters...................... reeteeereeirerreeeia
i ——raeearaaraeeeeaarraaeees 1-8

Items Supplied Per Configuration...........c.evvuereenieninniienieesieesenee e, 2-2
DZ11 to Terminal Wiring (Using BCO4R Cable) .......e eertreeert
e raeerraeeraarans 2-8

CSR Bit FUNCIONS .....ooiviiiiiiiiiiiiiiiii i 3-5

RBUF Bit FUNCHOMNS ....evvieeiieieieeiiiieeeeirreee
st eeeeetreeeeesnbteessennveee , v————— 3-7
LPR Bit FUNCHIONS ....coeiiviiiiiiieeieiieeireitiiiieeeeeeeeeettneseeseesssssnrannnessesesssssssnnnaeseens verr3-8

Page

Baud Rate Selection Chart..........ceieviiiiiiiiiiiiiiiinieneeice it
e s e ena e e enes 3-10

(IS

now
T IS I
N‘p_‘l-—t el

Tablé No.

Test Equipment ReqUIred..........ccouuviiiiiiiiiiiiiiiicen
e eeeereeeerenee e -1

UART Signal FUNCHONS .......cccovuiiiiriieiiiieeeeieeeeene
it B-5
Dual Baud Rate Generator Address/Frequency Assignments.........cccccceeeeveernneenn C-2
Dual Baud Rate Generator Pin Functions .........c..ccocccovevviviicninncniiniiniennene, C-3

Vii

CHAPTER 1

GENERAL DESCRIPTION

1. 1 INTRODUCTION
The DZ11 is an asynchronous multiplexer that prowdes an interface between a PDP 11 processor and
eight asynchronous serial lines. It can be used with PDP-11 systemsin a variety of applications that
include communications processing, time-sharing, transaction processing, and real-time processing.
Local operation to terminals or computers is possible at speeds up to 9600 baud using either EIA
RS232C interfaces or 20 mA current loop signaling. Remote operation using the public switched
- telephone network is possible with DZ11 models offering EIA RS232C interfaces. Enough data set
control is provided to permit dial-up (auto answer) operation with modems capable of full-duplex*
operation such as the Bell models 103 or 113 or equivalent. Remote operation over private lines for
full-duplex* point to point or full-duplex* multipoint as a control (master) station is also possible.

Figure 1-1 depicts several of the possible applications for the DZ11 in a PDP-11 system.

IDATASET |- ——
— ) — — — — — — DATA SET

—
u

DzTi

SYSTEM

o | TELEPHONE )

REMOTE

TERMINAL

I TELEPHONE
A LINE

SET b — — — 4)— — — — ——|DATA
SET

DATASET

= —— _9

“LOCAL

TERMINAL

|
|

TT|PATASET

—

MODEMS < <«

DZ11

& TER- | «—sf SYSTEM
MINALS

PDP-11

COMPUTER

| ol

e
S

PPt

COMPUTER

‘11-4332

Fig,ure 1-1

DZI11 System Applications

*The DZ11 data set control does not support half-duplex operations or the secondary transmit and receive
operations available with some modems such as the Bell model 202, etc.

1-1

The DZ11 has several features that provide flexible control of parameters such as baud rate, character
length, number of stop bits for each line, odd or even parity for each line, and transmitter-receiver
interrupts. Additional features include limited data set control, zero receiver baud rate, break generation and detection, silo buffering of received data, module plug-in to hex SPC slots, and line turnaround.

Each DZ11 module provides for operation of eight asynchronous serial lines. Since the module interfaces to these channels with a 16-line distribution panel, 2 DZ11 modules can be used with 1 panel.
Also note that the two versions of the DZ11 (EIA or 20 mA output) consist of different module and
panel types. This fact allows a system to mix EIA and 20 mA by using multiple DZ1 1s.
1.2

PHYSICAL DESCRIPTION

The DZ11 (8-line configuration) comprises a single hex SPC module and a 13.34 cm (5.25 in), unpowered distribution panel, connected by a 4.6 m (15 ft) ribbon cable. Several types of interconnecting
cables are used between the distribution panel and the modem or terminal, depending on the device. A
16-line configuration uses two modules and a single distribution panel connected by two ribbon cables.
The DZ11 modules, cables, static filters,* and distribution panel are shown in Figures 1-2 and 1-3. The
subsequent paragraphs present a detailed description of the physical and electrical specifications of the
S

various DZ11 options and configurations.

DZ11 {(M7819-EIA)
CABLE

(BCO5W-15)

‘\i

STATIC FILTER

(H7004C)

CABLE

(BCOGL-0J)

DISTRIBUTION PANEL

(H317-E)

8884-1

- Figure 1-2

DZI11 EIA Module (M7819), Distribution Panel (H317-E), Static Filter '(H7004C),' |
and Cables (BCO6L-0J and BCO5W-15)

*Static filters are not supplied with earlier modules.

-2

CABLE

(BCO8S-15)

STATIC FILTER

(H7004B)

CABLE

(BCO6K-0J)

DISTRIBUTION PANEL
(H317-F)

8884-2

Figure 1-3

DZ11 20 mA Module (M7814), Distribution Panel (H317-F), Static Filter (H7004B),
—.and Cables (BC06K-0J and BC08S-15)
|

1.2.1 DZ11 Configurations

The DZ11

can be supplied in six different configurations, each designated by a suffix letter (A-F). The

DZ11-A and the DZ11-B options are EIA devices with partial modem control. The DZ11-E is the

combination of a DZ11-A and a DZ11-B. The DZ11-C and the DZ11-D are 20 mA loop output
versions. The DZ11-F is the_' combination of a DZ11-C and a DZI11-D. Table 1-1 lists the various
option configurations and Figure 1-4 shows the required hardware for the various configurations.

)

The DZ11-A and DZ11-B each use an M7819 module that plugs into slot 2 or 3 ofa DD11-B or any
system unit with a hex SPC slot; however, slots in the PDP-11/20 BA11 box cannot be used. The
H317-E distribution panel provides 16 communication lines from 2 M7819 modules (8 lines per module) and is included with the DZ11-A and DZ11-E configurations. The H317-F distribution panel
provides 16 lines for the DZ11-C and DZ11-F configurations, which use the M7814 modules (20 mA
system). The distribution panels require no power and can be mounted in an H960 48.26 cm (19 in)
cabinet. Static filters (H7004C, EIA, and H7004B, 20 mA) are used to prevent problems caused by
electrostatic discharge. A 50-conductor, flat, shielded cable, BCO5SW-15, connects from the M7819
module to the static filter. Cable BCO6L-0J connects the static filter to the EIA distribution panel.
A
40-conductor, flat, shielded cable, BCO8S-15, connects from the M7814 module to the static filter.
Cable BC06K-0J connects the static filter to the 20 mA distribution panel.

1-3

PDP-11 UNIBUS

<
[ ozn-a|

(SPC SLOT)

M7819

BCOSW-15

(SPC SLOT)

'
I

| I

1 a—
]

|I T

LINES ———16

VO L O

(spc stom)|

DZII-D|

|(sPc sLom)

8 LINES
1e
|1

- BCO3

|
|

(20ma OUTPUT)

|
H70048 |
—
g S

8 LINES

LINES ———»16

llllllllll

_ CUSTOMER
SUPPLIED
,

LOCAL
TERMINAL

DATA
~SET

M7814

CABLE

103A OR
EQUIVALENT

*¥%

g S.__Bcoas 15.._.g g

H70048
IO
'

I I |

- BCO5D
TM

M7814

| |

H7004C
|
H7004C l
~——— BCO6L
sS e

8 LINES H317-E 8 LINES

M oz11-¢

& g(EIA QUTPUT) g

“ozi-s

M7819

*3%

TO TELEPHONE
LINES
NOTE

» Not included with DZ11, must be
ordered separately.

11-4333

%% DZ11-E =DZ11-A and DZ11-B

DZ11-F=DZ11-C and DZH—D

Figure 1-4

DZI11 Hardware Interconnections

Table 1-1

Model

Output

‘DZ11-A | EIA

DZ11 Model Configurations

Test

Connector

Module

Panel

M7819

H317-E | H325/H327

H327
M7819
M7819(2) | H317-E | H325/H327 |
H317-F | H3190
M7814
H3190
M7814 H3190
|
M7814(2) | H317-F

Filter

Cables

H7004C

BCOSW BCO6L

H7004C
BCO5W, BCO6L
H7004C
|
(2)
BCO6L
(2),
BCO5SW
H7004B
BCO08S, BCO6K
H7004B
BCO08S, BCO6K
H7OQ4B
BCO08S (2), BCO6K (2)

NOTES
H327 will be replaced by H327 1 in later units.

H3190is not supplied with early units. The shipping

list will indicate which test connector, if any, is supplied.

H7004C, H7004B, BC0O6L, and BCO6K are not supplied with early units. The shipping list will indicate
which static filter and cable, if any, are supplied.

1-4

Static

Modems or terminals are connected to the H317-E EIA panel by cables that attach to 16 DB25P cinch
connectors. These cables are not provided with the DZ11. The BC05D-25 cableis recommended for.
data set interconnections, and the BCO3M cableis recommended for local terminal interconnections.
The BCO5W-15 cable carries the data and control signals for all eight lines. Connections between
terminals and the H317-F 20 mA panel are by customer-supplied cables to 16 (4-screw) terminal strips.
The data signals for all eight lines are carrred to the d1str1butlon panel by the BC08S-15 cable.
Two accessory test connectors, H325 and H3271%*, are prov1ded with each DZ11-A. The H325 plugs

into an EIA connector on the distribution panel or on the end of the BCO5D cable to loop back data
and modem signals onto a single line. The H3271 connects to the module with the BCOSW cable (two
M 7819 modules can be connected to one H3271) and staers the data and modem lines as shownin
Figure 1-5. The connectors are shownmn F1gure1-6
e
L

The 20 mA (M7814 module) optlons also have a staggered turnaround connector (H3190T) The
H3190 connects to the M7814 using the BCO8S cable and staggers the lines as shownin Figure 1-7.

A priority level 5 insert plugs into a soeket on the M7819 or M7814 module to establish interrupts at
level 5 on the Unlbus

Maximum configuratlonallows 16 Dle modules per Unlbus

TRANS @

r———

DTR @

REC ()

REC
1

e RI

s CO 1

et TRANS |

NOTE!

Lines 2 & 3, 4850nd 6870re
staggered the same way.
11-4334

Figure 1-5

H3271 or H327 Turnaround

*Thisis a new item replacing the H327. The H327 may be used until the H3271 becomes available. The H327
plugs directly into J1 on the M7819 module.

TThis 1s a new item; check the Shipping list fOr availability.

1-5

H327

H3271

H325
8639-1

1g ure 1-6

Test Connectors H327 H3190, H3271, and H325
9

1-6

~ 20MA LOOP

- LINEO
=
TRANSMITTER

1
LINE

RECEIVER

AAA

A A

AAN

20MA LOOP

LINE 1
e

TRANSMITTER

LINE

RECEIVER

LINES2&3,4& 5. AND 6&7 ;AR'E'STAGGEHED;THE SAME WAY
-

11-5141

Figure 1-7 H3190 Staggered Line Turnaround

-7

1.3 GENERAL SPECIFICATIONS

The following paragraphs contain electrical, environmental, and performance specifications for all
DZ11 configurations. Table 1-2 lists the performance parameters of the DZ11.

Table 1-2

Description

Parameter
Operating Mode

Data Formatz
S

Character Size

{

Unibuss

High =0

|
|1

Low=1

High=0

Interface
High = 1

Low =1

Data Signal

'Asynchronous serial by brt|-start-and 1, 1 1/2 (5-level codes only), or 2

stop bits supplled by the hardware under program control

Parity 1s programf;electable. There may be none, or it may be odd or even.

Bit Polarities

Control Signal

Full-Duplex

5, 6, 7, or 8 bits; program-selectable. (Does not include parity bit.)

Parity

DZ11 Performance Parameters

EIA Out

20 mA Loop

Low = 1 = Mark

- 0-5mA

15-20 mA

Low=0

High = 0 = Space

High=1"

Low= OFF =~

Low=0

High = 0N

Ordér of Bit

1 Transmlssron/ receptron low order bit first

Baud Rates

" 1 50, 75, 110 134.5, 150 300 600 12001800 2000, 24()0 3600, 4800 7200,

Breaks

Can be»generated'and detected on each line

Throughput

21,940 characters/second = (bits/second X No. Lines
X direction)/(Bits/Character)

Example: (9600 X 8 X 2)/7= 21,940 characters/second
NOTE

The theoretical maximum is 21,940. Actual throughput depends on other factorssuch as type of CPU,
system software, etc.

1-8

1.3.1

Outputs

1.3.1.1 DZ11-A, -B, and -E
- Each line provides voltage levels and connector pinnings that conform
to Electronic Industries Association (EIA) standard RS232C and CCITT recommendation V.24. The
leads supported by this option are:*

Circuit
AA (CCITT 101)

Circuit AB (CCITT 102)
Circuit BA (CCITT 103)
Circuit BB (CCITT 104)
Circuit CD (CCITT 108.2)
Circuit CE (CCITT 125)
Circuit CF (CCITT 109

Pinl -

Pin7
Pin2
Pin 3
Pin 20
Pin 22
Pin8

Protective Ground

Signal Ground
Transmitted Data
- Received Data
|
Data Terminal Ready
Ring Indicator
Carrier
NOTE

Srgnal ground and protectlve ground are connected.
1.3.1.2 DZ11-C, -D, and -F- Each line is a 20 mA current loop used for connection to local terminals. (No data set control is provided.) All lines are active and, therefore, can only drive a passive
device. However, a pair of H319 20 mAreceivers.for
each line may be used to convert from active to
passive operation in order to allow the DZ11 to drive an active device. Refer to Appendix A for
connection details.
1.3.2

lnputs S

The PDP-11 Unibusis the mput for all DZl Is. The Dle A, -B, -C, and -D present one unit load to

the Unibus and the DZ11-E and -F present two unit loads to the Unibus. Four ac loads per module are
presented to the Unibusin the EIA version and five ac loads per module are presented in the 20 mA
version.

1.3.3 Power Requirements, DZ11-A, -B; and -ET |
Typical.
A

2.2
0.13
0.1

‘Maximum
o

25
0.15
| 013

at +5.0 Vdc
at-15.0 Vdc
at+15.0Vdc

134 Power Requirements, DZl 1-C, -D, and -Ft
Typical

Maximum

(A)

2123
0.4
0.12

0.42
0.15

at+50Vdc

~at-15.0Vdc
at +15.0 Vdc

*Circuit CA (CCITT 105 - Request to Send) is connected to circuit CD (DTR) through a jumper on the distribution panel. This allows control of the Request to Send line for full-duplex modem applications that use the RTS
circuit.

+DZ11-E and DZ11-F are twice the above given values.

1-9

1.3.5

Environmental Requirements — All DZ11s

Class C Environment Operating- 5°to 50° C* (41° to 122° F)
Temperature

Relative Humidity

F) and a
10 to 95%. with a maximum wet bulb of 32° C (90°
:
ft/min)
cu.
(3
1/second
1.416
- Air flow
Air flow 2.832 }/second (6 cu. ft/min)
~

Cooling
DZI11-A, -B, -C, and -D
DZ11-E and -F

1.3.6

Heat Dissipation

DZ11-A and -R
|
DZI11-E
|
DZ11-C and -D
|
DZ11-F

2° C (36° F)
minimum dewpoint of

3.99 g-cal/second (57 Btu/hr)
7.98 g-cal/second (114 Btu/hr)
(55 Btu/hr)
3.85 g-cal/second
7.7 g-cal/second (110 Btu/hr)

Distortion - DZ11-A, -B,and -E

in a received character is 40
to mark’ and “mark to space’’ distortion allowed
The maximum “‘space
|
|
o
e
percent.

The maximum speed distortion allowed in a received character for 2000 baud 1s 3.8 percent. All other
2.2
baud 1s
baud rates allow 4 percent. The maximum speed distortion from the transmitter for 2000R
o

percent. All other baud rates have less than 2 percent.
1.3.7

Interrupts

RDONE

Occurs each time a charqcter appears at the silo output.

Silo Alarm. Occurs after 16 éhatacters enter the silo. vRearmed by reading the

TRDY

silo. This interrupt disables the RDONE interrupt.

Occurs when the scanner finds a line ready to transmit on.
_
"~

NOTE

There are no medem interrupts.

4, 6, or 7 by
Normally, a level 5 priority plug is supplied. The interface level can be modified to level
|

using the proper priority plug.
1.3.8

Line Speed

The baud rate for a line (both transmitter and receiver) is program-selectable. Also, the receiver for
each line can be individually turned on or off under program control. (See Table 1-2 for a list of
o

available baud rates)

*Maximum operating temperature is reduced 1.8° C per 1000 meters (1.0° F per 1000 feet) for operation at
altitudes above sea level,

1-10

1.3.9

Distance (DZ11-A, -B, and -E)

The recommended dlstance from computer to DZ11 is 15 m (50 ft) at up to 9600 baud with a BCO5D
cable or equivalent. Operation beyond 15 m (50 ft) does not conform to the RS232C or CCITT V.24
specifications. However, operation will often be possible at greater distance depending on the terminal
equipment, type of cable, speed of operation, and electrical environment. Reliable communication
over long cables depends on the absence of excessive electrical noise. For these reasons, DIGITAL

cannot guarantee error-free communication beyond 15 m (50 ft). However, the EIA versions of the

DZ11 may be connected to local DIGITAL terminals and most other terminals at distances beyond 15
m (50 ft) with satisfactory results if the terminal and computer are located in the same building, in a
modern office environment. Shielded twisted pair wire (Belden 8777 or equivalent)is recommended
andis usedin the BCO3M null modem cable

With cables made with shielded twisted pair wire, such as the Belden 8777, the following rate/distance
table may be used as a guide. This chartis for informational purposes only and1s not to be construed
as a warranty by Digital Equipment Corporation of error-free DZ11 operation at these speeds and
distances under all circumstances.

90 m (300 ft) at 9600 baud
300 m (1000 ft) at 4800 baud
300 m (1000 ft) at 2400 baud
900 m (3000 ft) at 1200 baud
1500 m (5000 ft) at 300 baud
NOTE
The ground potential difference between the DZ11
and terminal must not exceed 2 V. This requirement

will generally limit operation to within a single building served by one ac power service. In other cases, or
in noisy electrical environments, 20 mA operation
should be used.

1. 3 10 Distance (Dle-C -D and -F)

The length of cable that may be used reliablyis a functlon of electrical noise, loop resistance, cable
type, and speed of operation. The following chart is given as a guide; however, thereis no guarantee of
error-free operation under all circumstances.

Speed (Baud)

Belden 8777, 22 AWG,

22 AWG. 4 conductor

(shields floating)

(DEC P/N 9105856-4)

shielded, twisted pairs

inside station wire

(DECP/N 9107723)

19600
4800
2400
1200 and below
1.4

150 m (500 ft)
300 m (1000 ft)
600 m (2000 ft)
1200 m (4000 ft)

|
|

300 m (1000 ft)
540 m (1800 ft)
~ 900 m (3000 ft)
1500 m (5000 ft)

FUNCTIONAL DESCRIPTION

The following paragraphs present a general dCSCI‘lpthI‘l of DZ11 operation. Figure 1-8 is a general
~functional block diagram that divides the DZ11 into three basic components: Unibus interface, control
logic, and line interface.

FOEOT .—.-l

/\ B
nwcoHZC

DATA

ADDRESS

POP-11 |

INTERFACE

'SCANNER

LINE
. INTERFACE

E |

8
LINES

—
- (
|

~ CONTROL

]

Voo
Figure 1-8

1.4.1

‘ i’

REGISTERS |—

PDP-11 Unibus Interface

11-4335

General Functional Block Diagram

The PDP-11 Unibus interface component of the Dle handles all transactions between the Unibus
and the DZ11 control logic. The Unibus interface performs three functions: data handling, address
recogmtlon and mterrupt control. In its data handling function, the interface routes data to and from

the various registers in the control logic and provides the voltage cond1tlon1ng necessary to transmit

“and receive data to and from the PDP-11 Unibus. The address recognition and control logic activates
the proper load and read signals when it recognizes its preselected address on the Unibus. These signals

are used by the data handling function to route the incoming and outgomg data to the desired loca-

tions. The interrupt control functlon initiates and controls 1nterrupt processing between the DZ1 l and
the PDP-11 processor.

1.4.2

Control Loglc

The control logic provides the required timing and control s1gnals to handle all transmitter and re-

ceiver operations. The control logic can be divided into two major sections: the scanner and the reglsters.

The scanner contmuously examines each linein succession and, based on information from the line
interface and the reglsters generates signals that cause data to flow to or from the appropriate line.
The scanner comprises a 5.068 MHz oscillator (clock), a 64- word FIFO rece1ver buffer a 4- phase
clocking network, and other control generatmg log1c

The DZ11 uses four device registers in a manner that yields six unique and accessible registers, each
having a 16-bit word capacity. The six discrete registers temporarily store input and output data,
monitor control signal conditioning, and establish DZ11 operating status. Depending on their functions, some of the registers are accessible in bytes or words; others are restricted to word-only operation. Registers can be read or loaded (written), depending on the operation. The ability to read or
write a register allows the use of two of the device registers as four independent registers.

1.4.3 Line Interface
|
Two of the most important operations in the DZ11 are the conversions from serial-to-parallel and
parallel-to-serial data formats. These conversions are required since the DZ11 is located between the
PDP-11 Unibus (a parallel data path) and either local terminals or telephone lines (serial data paths).
Conversions for each line in the DZ11 are performed by independent universal asynchronous receivertransmitter (UART) integrated circuits. Another component of the line interface, the line receiver or
driver, converts the TTL voltage levels in the DZI11 so that they correspond to those in the external
device input lines (modem or terminal).

1-13

'CHAPTER 2

INSTALLATION

2.1
SCOPE
:
|
This chapter contains the procedures for the unpackmg, mstallatlon and 1mt1a1 checkout of the DZ11
Asynchronous Multlplexer
.

2.2

CONFIGURATION DIFFERENCES

The DZI11 can be supplied with or without a dlstrlbutlon panel The Dle B and -D do not have

dlstrlbutlon panels. Thc followmg list describes the variations.

' DZ11-A

2.3

EIA level conversion with distribution panel
(8 lines)

DZ11-B

EIA level conversion without distribution panel (8 lines)

DZ11-C

20 mA loop conversion with distribution panel (8 lines)

DZ11-D

20 mA loop conversion without distribution panel (8 hnes)

DZ11-E

DZ11-A and DZ11-B

DZI11-F

Dle C and DZ11-D (16 lines)

(16 lines)

UNPACKING AND INSPECTION

The DZ11 is packagedin accordance with commercial packagmg practices. First, remove all packing
material and check the equipment against the shipping list. (Table 2-1 contains a list of supplied items
per configuration.) Report damage or shortages to the shipper immediately and notify the DIGITAL
representatlve Inspect all parts and carefully inspect the module for cracks, loose components, and
separations in the etched paths.

2.4 INSTALLATION PROCEDURE

The following paragraphs should be followed to install the DZ11 option in a PDP-11 system.

2.4. 1

H317 Distribution Panel and Static Filter Installation

Install the H317 distribution panel and static filters according to unit assembly drawmg D-UA-DZ11-

0-0.
2.4.1.1

EIA Option - For the DZ11-A or DZI11-E option, check to ensure that all of the machinemsertableJumpers on the distribution panel are in place. (See Drawing E-UA-5411928-0-0 for jumper
locations.) Thesejumpers are in anticipation of future use of the DZ11 with modems other than the
103; however, two of the Jumpers are now functional. The jumper labeled DTR (refer to D-CS591 1928 0-1) connects DTR to pin 4 or Request to Send. This allows the DZ11 to assert both DTR
and RTS if using a modem which requires control of RTS. TheJumper labeled BUSYis also connected

to the DTR lead for use in modems that implement the Force Busy function. This Jumper should
normally be cut out unless the modem has the Force Busy feature and the system softwareis implemented to control it.

tr1

*
EX R

X
XXMM
*

X
XK EXXK

Panel and static filter mountmg hardware set
Priority insert (95)
DZ11 User’s Manual (EK-DZ110-OP-01)
M7814 module
H7004B static filter (20 mA)
BCO8S cable
BCO06K
-0J filter cable (20 mA)
H317-F distribution panel assembly
|
Print set (B-TC-DZ11-0-11)DZ11,C, D, andF
order number MP00253
H 3190 test connectori

Software kit

poeemd eseed

pemd

peed

eead

peeed

e—)

M7819 module
"H7004C static filter (EIA)
H3271 test connectort
BCO06L.-0J filter cable (EIA)
H317-E distribution panel assembly
H325 test connector
BCO5W-15 cable
»
Print set (B-TC-DZ11-0-6) DZ11, A, B and C
order number MP00132

XX
| =

Description

<
X

Quantity

Items Supplied Per Configuration

PURK
AR XX
XX XXX

Table 2-1

*Shipment contains two of the items listed.

t New item.: An H327 will be shlpped with each M7819 unit until the H3271 becomes available. The shlppmg list

will indicate which test connector is supplled

tNew item: The ’shipping list will ‘i’nclUd"e the H3190 test connector when supplied.

2.4.1.2

20 mA Option - For the DZ11-C or DZ11-F option, refer to D-UA-5411974-0-0. Each line

has a jumper on the distribution panel (W1 through W16) which should bein if the termmal operates
at 300 baud or less Thejumper should be removed for hlgher baud rates.
|

2.4.2

M7819 Module Installation

To install the M7819 module perform the following procedure

L. Ensure that the priority insert (level 5)is properly seatedin socket E52 on the M7819 module(s) (Refer to drawmg D-UA- M7819 0- O)

Refer to Paragraph 3.1.1 for descriptions of the address assignments. Set the switches at E81
so that the module will respond to its assigned address. When a switch is closed (on), a
binary 1 is decoded. When a switch is open (off), a binary 0 is decoded. Note that the switch
labeled 1 corresponds to bit
3, 2 corresponds to bit 4, etc. (See Figure 2-1.)

Atz

AMO.

N
OFF

NOTE:

Address 160000 - A12 through A3,

OFF

160010 - A12 through A4, OFF; A3, ON
177770
- A12 through A3, ON

(OFF= LOGICAL @, ON=LOGICAL 1)

MSB

‘

13 |

12 | 11

‘

————SWITCHES

LSB

l .
“

)

—_

2 T0 7

6 OR7

(DZ11 REGISTERS)
11-4563

Figure 2-1

M7819 Address Selection

Vector selection is accomplished by the 8-position switch at E11. Switch positions 1 and 8

are not used. Switch position 2 corresponds to vector bit 3, 3 corresponds to vector bit 4, etc.
When a switch is closed (on), a binary 0 is decoded. When a switch is open (off), a binary 1 is

decoded. Note that this is opposite of the address switch decoding. (See Figure 2-2.)

OFF

E11

NOTE:
ON

LOGICAL
O

OFF

LOGICAL
1

'VECTOR

\VZ'!

300

V8
ON

OFF

V3
ON

310

OFF

770

OFF

OFF
11-5314

Figure 2-2

M7819 Vector Selection

2-3

If the DZI11 is supplied with the H3271 test connector, perform step 4. If the H327 test

connector 1s supplied, go to step 5.

Inseft the module(s) into an SPC slot and connect the flat shielded cable (BCO5W-15),

ribbed side up, to J1 on the module(s) Connect the other end of the cable, ribbed side
up, to the H3271.*
|
|
CAUTION
Insert and remove modules slowly and carefully to

avoid snagging module components on the card
guides and changing switch settings inadvertently.

Run the DZI11 diagnostic in staggered mode to verify module operation. Refer to

MAINDEC-11-DZDZA, the diagnostic listing. Run at least two passes without error.

Remove fhe BCOSW-ISN cable(s) from the H3271 and install the cable(s) (with smooth

side up) to the static filter socket(s) on the back of the H317-E distribution panel. Refer
to D-UA-DZ11-0-0 and Figure 2-3.

Proceed to step 8.

[Install the H327 test connector in J1 (the cable connector at the top of the M7819) and align
arrows for proper connection.
-

Insert the M7819in its SPC slot and run the DZ11 diagnosticin the staggered mode to verify
module operation. Refer to MAINDEC-11-DZDZA, the diagnostic listing for the correct
procedure Run at least two passes. without error.

CAUTION
Insert and remove modules slowly and carefully to
avoid snagging module components on the card
guides and changing switch settings inadvertently.
7.

Replace the H327 test connector with the BCO5W-15 cable and observe the same caution as
in step 6. Install the other end of the cable at the static filter socket on the back of the
distribution panel. Refer to Figure 2-3 and D-UA-DZ11-0-0.
Connect the H325 (or H315) test connector on the first line and run the diagnostics in
external mode. The test connector may be mstalled on the H317 E dlstrlbutlon panel or on

the end of a BCO5SD cable.

Repeat this step for each line.
9.

Run DEC/XI11 system exerciser to verify the absence of Unibus interference with other

system devices.

*The H3271 has connections for two H7819 cables.

2-4

STATIC
FILTER SOCKET

- SMOOTH.

SIDE

|
BCOSW-15

CABLE

OR
BCO8S-15 CABLE

RIB
SIDE

OUTPUT BOARD

11-4327

Figure 2-3

10.

BCO5W-15 and BC08S-15 Interconnection

The DZ11 1s now ready for connection to external equipment. If the connection is to a local
terminal, a null modem cable must be used. Use the BCO3M or BCO3P null modem cables
for connection between the distribution panel and the terminal. The H312-A null modem
unit may also be used with two BCO5D EIA cables (one on each side of the null modem
~unit). If connection is to a Bell 103 or equivalent modem, a BCO5D cableis required between
~ the distribution panel and the modem. All of the cables mentioned must be ordered separately as they are not components of a standard DZ11 shipment. When possible, run the

diagnostic in echo test mode to verify the cable connections and the terminal equipment.

2-5

2.4.3

V7814 Module Installation

To install the M7814 module, perform the followmg procedure
l.

Ensure that the priority insert (level 5) is properly seated in socket E41. Refer to D-UAM 7814-0-0.

Refer to Paragraph 3.1.1 for a description of address assignments. Set the switches at E72 so
that the module will respond to its assigned address. When a switch is closed (on), a binary 1
is decoded. When a switch is open (off), a binary 0 is decoded. Note that the switch labeled |
corresponds to bit 3, 2 to bit 4, etc. (See Figure 2-4.)

Af2

A1l

A10

)

[

OFF

NOTE:

‘
Address 160000 - A12 through A3,

OFF

160010 - A12 through A4, OFF;

A3, ON

177770
= A12 through A3, ON

(OFF=LOGICAL @, ON=LOG!CAL 1)

13 1 12 | 1

10|

LSB
4 |

SWITCHES

3
o

)

|
N

OR 7

@ 107

(DZ11 REGISTERS)
11-4562

Figure 2-4

M7814 Address Selection

Vector selkect‘ioni.s accomplished by an 8-position Sw_itc‘h at E81 on‘theh module(s). When a

switch is closed (on), ‘a binary 0 is decoded. When
a switch is open (off), a binary 1 is
~decoded. Note that thisis the opposite of the address switch decoding. Also, note that switch
positions 7 and 8 are not used and switch 6 corresponds to bit 3, 5 to bit 4, etc. (Refer to
Flgure 2-5.)
CAUTION
Insert and remove modules slowly and carefully to

avoid snagging module components on the card
guides and changing switch settings inadvertently.

2-6

MSB

' v3

OFF

E81

NOTE:

LOGICALO

OFF

LOGICAL
1

VECTOR

300

OFF

V3
ON

310

OFF

770

OFF

Figure 2-5

11-5140

M7814 Vector Selection

Insert module(s) into their 3351gned SPC slot(s). Connect the BCOSS cable with ribbed side
up, to JI on the module(s).

Skip this step if you have an H3190 test connector; otherwise perform the following.
a.

Connect the other end of the BCO8S cable to the static filter on the back of the distribu-

tion panel (H317-F) with smooth side up. Refer to Figure 2-3 and D-UA-DZ11-0-0.

Run the DZ11 diagnostic in internal (maintenance) mode for two error-free passes.
Refer to MAINDEC-11-DZDZA, the diagnostic listing, for the proper procedure.

Proceed to step 9.

Connect the other end of the BCOSS cable, with smooth side up, to the H3190 test connector.

Run the DZ11 diagnosticin staggered mode for two error- free passes Refer to MAINDEC11-DZDZA, the diagnostic listing, for the correct procedure.

Remove the BCO8S cable from the H3190 test connector and plug it into the static filter
socket on the back of the distribution panel (H317-F) with smooth side up. Refer to Figure
2-3 and D-UA-DZ11-0-0.

Run the DEC/X11 system exerciser to verify the absence of Umbus interference with other
system devices.

10.

The DZ11 is now ready for connection to passive external equipment. This is accomplished
with a customer-supplied cable. Most DIGITAL terminals use a BCO4R cable as shown in

Figure 2-6. Table 2-2 shows terminal connections for connecting a VT05, LA30, or LA36 to

the DZ11 and Figure 2-7 shows the H317F distribution panel for terminal reference. Run an
|
echo test to verify terminal connections.
NOTE
For customer terminals that can only transmit or re- -

ceive in a single direction, the echo test cannot be

If the DZI11 is to be connected to an active device, a pair of H319s are required. Refer to

Appendix A for details on this connection.

Figure 2-6 BCO4R Cable

- Table 2-2

DZ11 to Terminal Wiring (Using BCO4R Cable)

VTO05 Wiring
Mate-N-Lok

VTOS

DZ11

Signal

Color

Terminal No.

Terminal +RCV
Terminal —RCV

White

Black

4 (XMITH)

3
7

Terminal —XMIT

Green
Red

2 (REC—-)
1 (REC+)

Terminal + XMIT

2-8

3(XMIT—-)

DZ11 to Terminal Wiring (Using BCO4R Cable) (Cont)

Table 2-2

LA30, LA36 Wiring
LA30,LA36

DZ11

Mate-N-Lok

Signal

Terminal + XMIT

Terminal — XMIT

White

2(REC—)

3
7

Terminal —REC
Terminal +REC

Green
Red

J(XMIT-)
4 (XMIT+)

Color
Black

Terminal No.
1 (REC+)

NOTE

Terminal RCYV is connected to DZ11 XMIT. Terminal XMIT is connected to DZ11 RCV. Polarity
should always be + to + and — to — for both XMIT

and RCV.
In addition, post 1 is located at the top of the terminal block on the distribution panel and goes in sequence to post 4 at the bottom of the terminal block.

MA-0802

Figure 2-7

H317F Distribution Panel Terminal Reference

2-9

CHAPTER 3
PROGRAMMING

3.1

INTRODUCTION

This chapter provides basic information for programming the DZ11. A description of each DZ11
register, its format, programming constraints, and bit functions are presented to aid programming and
maintenance efforts. Special programming features are also presented in this chapter.

3.1.1

Device and Vector Address Assignments

The DZ11’s device and vector addresses are selected from the floating vector and device address space.
NOTE

The device floating address space is 160010; to
163776,. The vector floating address space ns 300; to
7768

Its floatmg address space follows the DJ11 DHll DQll DUll DUPI1, LK11, and DMCI1.

Its floatmg vector space follows the DCl11; KLll/DLllA -B; DPll DMI11-A; DNll DMI11-BB

and other modem control vectors; DR11- A DR11-C; PA611 reader PA611 puneh DTll DX11;
DL11-C, -D, -E; DJ11; DH11; GT40; -LPSll; DQI11; KW11-W; DUI1; DUPII; DVII; LKll-A;
- DWUN; and DMCI11. If a DZ11 is installed in a system with any of the above listed options, then its
assigned vector and device address should follow the vector and device address of the other options.

Two examples follow. FirSt, the simplest case where there is only one DZ11.
Option

Address

‘GAP
GAP
GAP
GAP
GAP
GAP

160010«
160020
160030
160040
160050
160060

160100
160110

300

GAP

DZ11
GAP

160070

Vector

3-1

Comment

NoDlJlls
NoDHlls
NoDQlls
No DUl1s
No DUPI11s
No LK1l1s

No DMCl1s
No more DZ11s

Next, a system with one DJ11, one DH11, one GT40, one KW11-W, and two DZ]1 1s.
Option

Address

Vector

DJ11
GAP
GAP

160010
160020
160030

300

160040

310

DHI11

Comment

No more DJ11s
DHI11 must start on an address boundary that is a multiple of 20.

160050

GAP

160060

GT40
KWI11-W

330

GAP

GAP
GAP

160070

160100
160110

GAP
GAP

No more DHl1ls
GT40 address is not in the floating address space.
KWI11-W address is not in the floating

320

NoDUlIs
No DUPI
s

160120
-

address space.

NoDQlls

No LK11s
No DMCl1Is

160130

DZ11

160140

340

DZ11

160150

350

GAP

160160

No more DZ11s

3.2 REGISTER BIT ASSIGNMENTS
A comprehensive pictorial of all register bit assignments is shown in Figure 3-1. The four device
registers (DRO, DR2, DR4, and DR6) are subdivided to form six unique registers. This subdivision is
accomplished in DR2 and DR6 by assigning read-only (RO) or write-only (WO) status to each register. Since the reading and writing of DR2 and DR6 accesses two registers, PDP-11 processor instructions that perform a read-modify-write (DATIP) bus cycle cannot be used with DR2 or DR6. Also,
DR2 permits only word instructions, but either byte or word instructions
may be used with DR6. DR0
and DR4 have no programming constraints. In all register operations, the following applies: read-only
bits are not affected by an attempt
to write, and write-only and ‘“not-used” bits appear as a binary 0 if
a read operation is performed. Specific programming constraints for each register are discussed in the
following paragraphs. A description of each bit function is presented in Tables 3-1 through 3-3.
3.2.1

Control and Status Register (CSR)
The control and status register (CSR) contains the states of flags and enable bits for scanning, proces-

sor interrupts, clearing, and maintenance. The 16-bit CSR has no programming constraints. The format 1s depicted in Figure 3-1, and bit functions are described in Table 3-1. Write-only and ““not-used”’
bits are read as zeros by the Unibus, and read-only bits are not affected by write attempts.

3-2

04d>10HLNODoYoYo} oY /oYsoYo}Eo}L*REoYoYo}*oY o}?|o1Y8|/od|0oYS/

]®WHEIN3V(SI44aNTN(EoLnHNgRVwd4gTIE)S.LNav|oAQ1sIilSTvVAaAN|AnNoH3EAO]AWHRYvSV3HSd|HXeV34dVS/Ss©~o/ya©29||1Lxaayn9n3mml|aXanYdignL|XIYv.n§¢ALNaOna<Ago@Ydl[[|]d43vn9d1a|ay|d4IoNiGtS8sY|L|H4v41q41NH¢0D|IH1Nvn£IaaHVdyOIA|y4Z2noSa)ayV|4inLSYagy|4Ynovga©Dyy

)uq1L)|1LvI30n18(sa41N9n01v)yaLvd.m&o/Yyi5La]m|SMd|"YH97|ia|m/oeYSyig|Ta|NMmOy¥E1bldT|.mDdl3a£14m||o0weY3i4Ha4|m|o0vaY3iL4T||mo0Yu3aio4M]|odHa[lvg]nadvjmnN3T||agm93vvyyNN33|e||93mavN0yniNT23T||wmIH9aN1evdI9nTN73T|gMmHIvN1YeINDT37[||aaynn[Ninnm3T||gaaT9nnMvNiiY3[||UgIIMNNvIgNYTT3T

]ouoH||ooyodou|Tou|oulod|od|od||ou|o4odu||~—od

51pl€l4!LoL6080B—90500€020L00
ELES-LL

a>z4a) (4YSD) sin oM. om< om]0| om|g oHmo|\lv/H¥oMmo{L1om|9 om|5 om|| oM5v .oQmSZ omO|u]o|ogMs,0Q1S
SvNi(LYv(SVaI4LNa)Sl) o0>ML2mLugoM0mu9|g||o0¥m9HS|g o0Mbg9 9yMbg o0>9um£go0dum2aZ|g|>o0dmu2)|a|o0xmy0)Z€ 20|a|o4m7n]g1Lryl|o49mn1|g9L4||o4smn|giSLd||odmnb|g1Ly oi1nMY£g€L o4znmiZ9dL|o4mLn}||ygl|J0iomn|igdL

Figure 3-1

3-3

)

Table 3-1

Function

‘Title

Bit

00-02

CSR Bit Functions

Not used

Maintenance (MAINT)

A read/write bit that, when set, causes the serial
output data from the transmitter to be fed back as
serial input data to the receiver. All lines are turned
around. Cleared by BUS INIT and CLR.

Clear (CLR)

A read/write bit that fires a one-shot to generate a
15 us reset which clears the receiver silo, all
UARTSs, and the CSR. After a CLR is issued, the
CSR and line parameters must be set again. CLR
in progress
is indicated by CLR = 1. Modem control registers are not affected, nor are bits 00
through 14 of RBUF.

Master Scan Enable

A read/write bit that activates the scanner to enable the receiver transmitter and silo. Cleared by
CLR and BUS INIT.

Receiver Interrupt Enable

A read/write bit that enables the receiver interrupt.

Receiver Done (RDONE)

08-10

Transmit Line A-C (TLINE)

Cleared by CLR and BUS INIT.

A read-only bit (hardware set) that generates RCV
INT if bit 06 = 1 and bit 12 = 0. The bit clears
when the RBUF is read and resets when another
word reaches the output of the silo (RBUF). If bit
06 = 0, RDONE can be used as a flag to indicate
that the silo contains a character. If bit 12 = 1,
RDONE does not cause interrupts but otherwise
acts the same.

When bit 15 = 1, these three read-only bits indicate
the line that is ready to transmit a character. Bit 15
clears when the character is loaded into the transmit buffer, but sets again if another line is ready. A
-

new line number. could appear within a minimum

of 1.9 us. Bits 08-10 return to line 0 after a CLR or
BUS INIT. These bits are meanmgful only when
bit 15 (TRDY)is true.
11

Not used

Silo Alarm Enable (SAE)

A read/write bit that enables the silo alarm and
prevents RDONE from causing interrupts. If bit 06
= |, the SAE allows the SA (bit 13) to cause an
interrupt after 16 entries in the silo. If bit 06 = O,
the SA can be used as a flag. The bit is cleared by
CLR and BUS INIT.

3-5

Table 3-1

CSR Bit Functions (Cont)

Bit

Title

Function

Silo Alarm (SA)

A read-only bit set by the hardware after 16 characters enter the silo. It causes an interrupt if bit 06

= 1 andis cleared by CLR, BUS INIT, and reading the RBUF. When the silo flag occurs (SA = 1),

the silo must be emptied because the flag will not
be set again until 16 additional characters enter the
silo.

Transmitter Interrupt Enable

A read/wrlte bit that allows an mterrupt if bit 15

(TIE)

(TRDY)
=

Transmitter Ready (TRDY)

A read-only bit that is set by hardware when a line
number 1s found that has its transmit buffer empty
and its LINE ENAB bit set. It is cleared by CLR,
BUS INIT, and by loading the TBUF register.

3.2.2 Receiver Buffer (RBUF)
The receiver buffer (RBUF) register contains the received character bits, with line identification, error
status, and data validity flag. As one of two registers in DR2 (RBUF and LPR), RBUF is accessed
when a read operation is performed (write operatlon accesses the LPR). The programming constraints
for the RBUF reglster are as follows.
1.

Byte instructions cannot be used.

It is a read-only register.
TST or BIT instructions cannot be used because they cause the loss of a character.

The register requires master scan enable (CSR, bit 05) to be set in order to be functional.
When this bit is off, bits 00 to 14 of the RBUF become invalid regardless of the state of bit
15 (data valid) and the silo is held empty. The register format of RBUF is depicted in Figure
3-1 and bit functions are described in Table 3-2. Each reading of the RBUF register advances the silo and presents the next character to the program. Bits 00 through 14 do not go

to zero after a CLR or BUS INIT; however, they become invalid and the silo is emptied. Bit
15 (data valid) does clear to zero. (See Table 3-2.)

3-6

Table 3-2 RBUF Bit Functions
Function

Bit

Title

00-07

Received Character

08-10

Line Number

Not used

Parity Error

This bit indicates whether the received bit had a

Framing Error

This bit indicates impropef framing (stop bit not a

These bits contain the received character. If the selected code level is less than eight bits wide, the
~ high-order bits are forced to zero.

These bits present the line number on which the
character was received.

parity error. The parity bit is generated by hardware and does not appear in the RBUF word.

mark) of the received character and can be used for
break detection.

- This bit indicates receiver buffer overflow. The result is a received character which is replaced by another received character before storage in the silo.
A character is lost but the received character put in

Overrun

the silo is valid.
Data Valid

This bit indicates that the character read from the
silo (RBUF) is valid. The RBUF is read until the
data valid bit = 0, indicating an invalid character
and empty silo. Cleared by CLR and BUS INIT.

3.2.3 Line Parameter Register (LPR)
The line parameter register (LPR) is a 16-bit register that sets the parameters (character and stop code
lengths, parity, speed, and receiver clock) for each line (Table 3-3). Bits 00-02 select the line for

parameter loading. Line parameters for each line must be reloaded after a CLR (bit 04 of CSR) or
BUS INIT operation. The programming constraints for the LPR are as follows.
l.

[t is a write-only register.

BIS or BIC instructions are not allowed.

Byte operations cannot be used.

Table 3-3 LPR Bit Functions

00-02

|| -

03-04

Function

]

Title

Bit

LineNumbex‘?
Character Length
|

These bits select the line for parameter loading

- These bits set the character length for the selected

line. The parity bit is not part of the character

length.

Stop Code

0
0
1
]

0
1
0
]

5 bits
6 bits
7 bits
8 bits

This bit sets the stop code length (0 = 1-unit stop, 1

= 2-unit stop or 1.5-unit stop if a 5- level code is
employed)

Parity

Odd Parity

08-11

Speed Select

This bit selects the parity option (0 = no parity
check, I = parity enabled on TRAN and RCV).

This bit selects the kind of parity (0 = even parity

select, 1 = odd parity select). Bit 06 must be set for
this bit to have effect.

These bits select the TRAN and RCV speed for the
line selected by bits 00-02. Refer to Table 3-4 for a

~ list of available baud rates.

Receiver On
-

This bit must be set when loading parameters to
activate the receiver clock. (Transmitter clock is always on.)
clock off.

A CLR or BUS INIT turns the receiver

3.2.4 Transmit Control Register (TCR)
The transmit control register contains 16 bits for the EIA options (M7819 module) and 8 bits for the 20
mA option (7814 module). The differenceis that the data terminal ready (DTR) lines that make up the
high byte (bits 08 through 15) of the TCR are not used by the 20 mA options because they do not have
modem control capabilities.

The hlgh byte (M7819 only) contains a read/write DTR bit for each line. This byte is cleared by BUS

INIT only, not by CLR. When the high byte is not used (M7814 only), it reads back to the Unibus as
all zeros. Attempts to write into it will have no effect. The low byte contains a read/write line enable
bit for each line. A set bit allows transmission on the corresponding line. Paragraph 3.3.7 explains how

to properly use this bit. This byteis cleared by CLR and BUS INIT.

3-8

Modem Status Register (MSR)

3.2.5

Thisis a 16-bit register used only with the EIA optlons (M7819 module) The 20 mA options (M7814
module) do not have modem control capabll1t1es When not used this register reads all zeros to the
Unibus.

‘

The MSR consists of two bytes: the low byte (bitsOO—07) and the high byte (bits 08-15). The low byte
monitors the state of each line’s ring indicator (RI) lead; the high byte monitors the state of each line’s
carrier (CO) lead. The MSR is the read-only portion of DR6 and has the following programming
characteristics.
|
1.

It is a read-only register.

CLR and BUS INIT have no effect.

Bit format is shown in Figure 3-1.

3.2.6

Transmit Data Register (TDR)

The TDR consists of two 8-bit bytes. The low byte is the transmit buffer (TBUF) and holds the
character thatis to be transmitted. The high byteis the break register with each line controlled by an

~individual bit. When a break bit is set, the line associated with that bit starts sending zeros immediately

and continuously. The TDR is the write-only portion of DR6 and has the following programming
characteristics.

It is a write-only register.

BIS or BIC 1nstruct10ns cannot be used

3.
4.

For character lengths less than 8 b1ts the character loaded into the TBUF must be right

justified because the hardware forces the most significant bits to zero.

The break reg1ster has no effect when runmng in the maintenance mode (1 €., CSR brt 03 =

D).

3.3

It is cleared by CLR and BUS INIT.

Bit format is shown in Fi‘gure 3-1.

PROGRAMMING FEATURES

The DZ11 has several programming features that allow control of baud rate, character length, stop
bits, parity, and interrupts. This section discusses the application of these controls to achieve the
desired operating parameters.
3.3.1

Baud Rate

The selection of the desired transmission and receptlon speedis controlled by the conditions of bits 08
through 11 of the LPR. Table 3-4 depicts the required bit configuratmn for each operatmg speed. The
baud rate for each lineis the same for both the transmitter and receiver. The receiver clock1s turned on
and off by settmg and clearmg bit 12 in the LPR for the selected line.
<

3-9

- Table 3-4
Bits
11

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

3.3.2

Character Length

3.3.3

Stop Bits

3.3.4

Parity

Baud Rate Selection Chart

Baud Rate

0
0
0
0
]
1
]
1
0
0
0
0
| 1
1
1
]

0
-0
1
1

0
1
0
1
0
1
0
1
0
]
0
]
0
|
0
]

50
75
110
134.5

0
0
1
1
0
0
]
1

0
|10
]
1

150

300
600
1200
1800
2000
2400
3600

4800
7200
9600
Not used

The selection of one of the four available character lengths is controlled by bits 03 and 04 of the LPR.
The bit conditions for bits 04 and 03, respectively, are as follows: 00 (5-level), 01 (6-level), 10 (7-level),
and 11 (8-level). For character lengths of 5, 6, and 7, the high-order bits are forced to zero.
-

The length of the stop bits in a serial character string is determined by bit 05 of the LPR. If bit 05 is a
zero, the stop length is one unit; bit 05 set to a one selects a 2-unit stop unless the 5-level character
length (bits 03 and 04 at zero) is selected, in which case the stop bit length is 1.5 units.
The parity option is selected by bit 06 of the LPR. Parity is enabled on transmission and reception by
setting bit 06 to a one. Bit 07 of the LPR allows selection of even or odd parity, and bit 06 must be set
for bit 07 to be significant. The parity bit is generated and checked by hardware, and does not appear
in the RBUF or TBUF. The parity error (bit 12, RBUF) flag is set when the received character has a
parity error.

3.3.5 Interrupts |

The receiver interrupt enable (RIE) and silo alarm enable (SAE) bits in the CSR control the circumstances upon which the DZI11 receiver interrupts
the PDP-11 processor.

If RIE and SAE are both clear, the DZ11 never interrupts the PDP-11 processor. In this case, the
program must periodically check for the availability of data in the silo and empty the silo when data is
present. If the program operates off a clock, it should check for characters in the silo at least as often as
the time it takes for the silo to fill, allowing a safety factor to cover processor response delays and time
to empty the silo. The RDONE bit in the CSR will set when a character is available in the silo. The
program can periodically check this bit with a TSTB or BIT instruction. When RDONE is set, the
program should empty the silo.

3-10

If RIE is set and SAE is clear, the DZ11 will interrupt the PDP-11 processor to the DZ11 receiver
vector address when RDONE is set, indicating the presence of a character at the bottom of the silo.
The interrupt service routine can obtain the character by performing a MOV instruction from the
RBUF. If the program then dismisses the interrupt, the DZ11 will interrupt when another character is

available (which may be immediately if additional characters were placed in the silo while the interrupt
was being serviced). Alternatively, the interrupt service routine may respond to the interrupt by emptying the silo before dismissing the mterrupt

If RIE and SAE are both set, the DZ11 will interrupt the PDP-11 processor to the DZ11 receiver
vector when the silo alarm (SA) bit in the CSR is set. The SA bit will be set when 16 characters have
been placed in the silo since the last time the program has accessed the RBUF. Accessing the RBUF
will clear the SA bit and the associated counter. The program should follow the procedure described in
Paragraph 3.3.6 to empty the silo completely in response to a silo alarm interrupt. This will ensure that
any characters placed in the silo while it is being emptied are processed by the program.
NOTE
If the program processes only 16 entries in response

~ to each silo alarm interrupt, characters coming in
while interrupts are being processed will build up
without being counted by the silo alarm circuit and

the silo may eventually overflow without the alarm
being issued.
If the silo alarm interrupt is used, the program will not be interrupted if fewer than 16 characters are
received. In order to respond to short messages during periods of moderate activity, the PDP-11
program should periodically empty the silo. The scanning period will depend on the required responsiveness to received characters. While the program is emptying the silo, it should ensure that DZ11
receiver interrupts are inhibited. This should be done by raising the PDP-11 processor priority. The
silo alarm interrupt feature can significantly reduce the PDP-11 processo‘r overhead required by the
DZ11 receiver by eliminating the need to enter and exit an 1nterrupt serv1ce routine each time a charac|
ter is received.

The transmitter interrupt enable bit (TIE) controls transmitter interrupts to the PDP-11 processor. If
enabled, the DZ11 will interrupt the PDP-11 processor to the DZ11 transmitter interrupt vector when
the transmitter ready (TRDY) bit in the CSR is set, 1ndlcat1ng that the DZ11 is ready to accept a
character to be transmitted.
|
:
o
3.3.6

Emptying the Silo

The program can empty the silo by repeatedly performing MOV instructions from the RBUF to
temporary storage. Each MOV instruction will copy the bottom characterin the silo so it will not be
lost and will clear out the bottom ofthe silo, allowing the next character to move down for access by a
subsequent MOV instruction. The program can determine when it has emptied the silo by testing the
data valid bit in each word moved out of the RBUF. A zero value indicates that the silo has been
‘emptied. The test can be performed conveniently by branching on the condition code following each
MOV instruction. A TST or BIT instruction must not access the RBUF because these instructions will
cause the next entry in the silo to move down without saving the current bottom character. Furthermore, followinga MOV from the RBUF, the next character in the silo will not be available for at least

I us. Therefore, on fast CPUs, the program must use sufficient instructions or NOPs to ensure that

successive MOVs from the RBUF are separated by a minimum of 1 us. This will prevent a false
indication of an empty silo.

3.3.7

Transmitting a Character

The program controls the DZ11 transmitter through five registers on the Unibus: the control and
status register (CSR), the line parameter register (LPR), the line enable register, the transmitter buffer
(TBUF), and the break register (BRK).
Following DZ11 initialization, the program must use the LPR to specify the speed and character
format for each line to be used and must set the master scan enable (MSE) bit in the CSR. The
program should set the transmitter interrupt enable (TIE) bit in the CSR if it wants the DZ11 transmitter to operate on a program interrupt basis.
~
The line enable register is used to enable and disable transmission on each line. One bit in this 8-bit

BISB, BIC, and BICB instructions. (If word instructions are used, the line enable register and the DTR
registers on M7819 modules are simultaneously accessed.)

The DZ11 transmitter is controlled by a scanner which is constantly looking for an enabled line (line

enable bit set) which has an empty UART transmitter buffer. When the scanner finds such a line, it
loads the number of the line into the 3-bit transmit line number (TLINE) field of the CSR and sets the
TRDY bit, interrupting the PDP-11 processor if the TIE bit is set. The program can clear the TRDY
bit by moving a character for the indicated line into the TBUF or by clearing the line enable bit.
Clearing the TRDY bit frees the scanner to resume its search for lines needing service.
To initiate transmission on an idle line, the program should set the TCR bit for that line and wait for
the scanner to request service on the line, as indicated by the scanner loading the number of the line
into TLINE and setting TRDY. The program should then load the character to be transmitted into the
TBUF by using a MOVB instruction. If interrupts are to be used, a convenient way of starting up a line
1s to set the TCR bitin the main program and let the normal transmitter mterrupt routine load the
character into the TBUF.
NOTE
|
The scanner may find a different line needing service

before it finds the line being started up. This will occur if other lines request service before the scanner
can find the line being started. The program must
always check the TLINE field of the CSR when responding to TRDY to ensure it loads characters for
the correct line. Assuming the program services lines
as requested by the scanner, the scanner will eventually find the line being started. If several lines require
service, the scanner will request service in priority
order as determined by line number. Line 7 has the

“highest priority and line 0 the lowest.
To continue transmission on a line, the program should load the next character to be transmitted into

the TBUF each time the scanner requests service for the line as indicated by TLINE and TRDY.
To terminate transmission on a line, the program loads the last character normally and waits for the
scanner to request an additional character for the line. The program clears the line enable bit at this

time instead of loading the TBUF.

3-12

The normal rest condition of the transmitted data lead for any line is the 1 state. The break register
(BRK) is used to apply a continuous zero signal to the line. One bit in this 8-bit register is associated
with each line. The line will remain in this condition as long as the bit remains set. The program should
use a MOVB instruction to access the BRK register. If the program continues to load characters for a
line after setting the break bit, transmitter operation will appear normal to the program despite the fact
that no characters can be transmitted while the line is in the continuous zero sending state. The program may use this facility for sending precisely timed zero signals by setting the break bit and usmg
transmit ready interrupts as a timer.
It should be remembered that each line in the DZ11 is double buffered. The program must not set the
BRK bit too soon or the two data characters preceding the break may not be transmitted. The program must also ensure that the line returns to the 1 state at the end of the zero sending period before
transmitting any additional data characters. The following procedure will accomplish this. When the

scanner requests service the first time after the program has loaded the last data character, the program
should load an all-zero character. When the scanner requests service the second time, the program
should set the BRK bit for the line. At the end of the zero sending period, the program should load an

all-zero character to be transmitted. When the scanner requests service, indicating this character has
begun transmission, the program should clear the BRK bit and load the next data character.
|
3.3.8 Data Set Control
DZ11 models with EIA interfaces include data set control as a standard feature. The program may
sense the state of the carrier and ring indicator signals from each data set and may control the state of

the data terminal ready signal to each data set. The program uses three 8-bit registers to access the
DZ11 data set control logic. One bit in each register is associated with each of the eight lines. There are
no hardware interlocks between the data set control logic and the receiver and transmitter logic. Any
required coordination should be done under program control.
The data terminal ready (DTR) register is a read /write register. Setting or clearing a bit in this register
will turn the appropriate DTR signal on or off. The program may access this register with word or byte
instructions. (If word instructions are used, the DTR and line enable registers will be simultaneously
accessed.) The DTR register is cleared by the INIT signal on the Unibus but is not cleared if the
program clears the DZ11 by setting the CLR bit of the CSR.

The carrier register (CAR) and ring register (RING) are read-only registers. The program can determine the current state of the carrier signal for a line by examining the appropriate bit of the CAR
register. It can determine the current state of the ring signal by examining the appropriate bit of the
ring register. The program can examine these registers separately by using MOVB or BITB instructions or can examine them as a single 16-bit register by using MOV or BIT instructions. The DZI11
data set control logic does not interrupt the PDP-11 processor when a carrier or ring signal changes
state. The program should periodically sample these registers to determine the current status. Sampling at a high rate is not necessary

3.4 PROGRAMMING EXAMPLES
The following six examples are sample programs for the DZ11 option. These examples are presented
only to indicate how the DZI11 can be used.

- 3-13

|
Example 1 - Initializing the DZ11
The DZI11 is initialized by a power-up sequence, a reset instruction, or a device clear instruction.
Device Clearing the DZ11
001000
001002
001004
001006
- 001010
001012
001014

012737
000020
160100
032737
000020
160100
001374

001016

000000

START:

MOV #20, DZCSR

19:

BIT #20, DZCSR

:Set bit 4 in the
:DZ11 control and
;status register.
‘Test bit 4.

BNE 1$

-If bit 4 1s still
-set, the branch
-condition is true
-and the device clear
‘function is still in
|

HALT
|

;progress.

:The device clear
.function is complete
-and the DZ11 has been
-cleared.

DZCSR = Control and Status Register Address = 160100.
Example 2 - Transmit Binary Count Pattern on One Line
START:

MOV #20, DZCSR

001000
001002

012737
000020

001004
001006
001010
001012
001014

160100
032737
000020
160100
001374

001016
001020
001022

012737
001070
160102

MOV #n, DZLPR

001024

012737

MOV #1, DZTCR

1$:

.Set bit 4 in the DZ11
:control and status
;register.

BIT #20, DZCSR

‘Test bit 4.

BNE 1%

‘If bit 4 1s still set,
‘the branch condition
:is true and the device
-clear function is still
;in progress.
;Load the parameters
:for line O: 8-bit

:character; 2 stop bits;

3-14

110 baud
‘Enable line 0
‘transmitter.

001030

000001
160104

001032
001034
001036
001040

012737
000040
160100
005000

001042
001044
001046

005737
160100
100375

BPL 2§

001050

MOVB R0, DZTDR

001052
001054
001056

110037
160106
105200
100371

BPL 2%

001060

000000

HALT

001026

:Set scanner enable bit
;5 in the control and
;status register.
:Set binary count

MOV #m, DZCSR

CLR RO
|

;pattern to zero.

TST DZCSR

2%:

INCBRO..

‘Test the transmitter
;ready flag (bit 15).
:If branch condition
;1s false, continue;

;otherwise test again.

-Load character to be
‘transmitted.

:Increment binary count.
:If branch condition is
.false, the binary count
;pattern is complete.

RO = Register 0 = Binary Count Pattern
DZCSR = DZI11 Control and Status Register Address = 160100
DZLPR = DZI11 Line Parameter Register Address = 160102
DZTCR = DZI11 Transmit Control Register Address
= 160104
DZTDR = DZ11 Transmit Data Register Address = 160106
Example 3 - Transmit a Binary Count in Maintenance Loopback Mode, with the Receiver “On’’ in the
Interrupt Mode

Output Received Data.to Console
001200

005000

CLR RO

;Set binary count

001202
001204

012701

MOV 1400, R1

001206
001210

MOV #SP, R6

001212
001214
001216

012706
001100
012737
001304
000300

001220
001222

005037
000302

CLR (RVEC+2)

001224

012737
000020

MOV #0, DZCSR

o zero.

001226

:Set R1 to first

-address of data

001400

MOV #INT, RVEC

3-15

‘buffer.
‘Initialize stack
;pointer.
:Set DZ11 vector
-address to start of
;receiver interrupt
‘Toutine.
;:Set up processor
:status word for DZ 11
;receiver interrupt.
‘Set bit 4 in the
‘DZ11 control and
;status register.

160100

001374

19:

BIT #20 DZCSR

‘Test bit 4.

BNE
1$
-

001242
001244

012737

001246

160102

001250

012737

001252

000001

001254
001256
001260

012737
000150

001262

001264

001266
001270

001272
001274
001276
001300

001302

011070

160104

MOV #PAR, DZLPR

MOV #1, DZTCR

MOV #150, DZCSR

- 160100
005737
160100
- 100375

;character; 2 stop bits;
:110 baud; no
;parity; receiver on.
:Enable line 0
:transmitter.

‘Turn scanner on,

;enable receiver

;interrupts,
and loop

TST DZCSR |

BPL2S

110037

MOVB
RO, DZTBUF

105200
001371

BNE2$

000777

BR.

160106

If bit 4 1s still
:set, the branch
:condition is true
:and the device clear
‘function is still in
;progress.
;Load the parameters
-for line 0: 8-bit

INCB RO

:lines back on themselves.
:Test the transmitter
;ready flag.
:If branch condition is
-false, continue;

;otherwise test again.
:Load character to be
:transmitted.
;Increment binary count.
:If branch condition is
.false, the binary count
;pattern is complete.
:Wait for last character
‘transmitted to be
‘received.

160100
032737
000020

001230
001232
001234
001236
001240

Receiver Interfvrup'tflvxservfice Rouvtinfe P
001304
001306
001310
001312
001314

013711
160102

MOV DZRBUF, (R1)

022721

CMP #100377,

100377

001401

001316
001320

000002
012701

001322

001400

(R1)+

BEQ .+2

RTI

MOV #1400, R 1

105737

TSTB TPS

100375

BPL 3$

111137
177566

MOVB (R1), TPB

001342

022721
100377
001370

CMP #100377,
(R1)+
BNE 3$

001344

000000'

HALT

001324
001326
001330
001332
001334

001336
001340

177564

RVEC
= DZ11 Recelver Interrupt Vector Address
DZCSR
= DZI11 Control and Status Word Address

DZLPR= DZ11 Line Parameter Register (Write- Only) Address

DZTCR
= DZI11 Transmit ControlRegister Address
DZTBUF = DZ11 Transmit Buffer Address
- DZRBUF = DZ11 Receiver Buffer Address (Read-Only Reglster)
TPS = Teletype® Punch Status Register Address
TPB = Teletype Punch Data Register Address

@Teletype is a registered trademark of Teletype Corporation.
3-17

;Store received
;character in memory
‘table.
:Check for last

;:character.
|
:Branch condition is
‘true when last
‘transmitted character
‘1S received.
-Exit routine.
;Initialize pointer
:to start of received
:data buffer in memory.
‘Test to see if console
;1s ready.
;Wait, and test again.
-If condition is met,
‘transfer character
‘to console.
‘Check for last
:character.
:Not finished if

;condition is true. :
-finished.

Example 4 - Transmit and receive in Maintenance Mode on a Single Line
The switch register bits (SWR00-SWRO07) hold the desired data pattern (character).
012737
000002

001004
001006
001010

160104
012737
017471

001012

160102

001014
001016
001020
001022
001024
001026

012737
000050
160100
005737
160100
100375

001030
001032
001034
001036

113737
177570
160106
000240

001040

012701

177670

- START:

MOV #LINE, DZTCR

:Select the line for
;transmitting on.
;Choose one ofeight.
;Line #1 selected.
:Select desired line
;parameters for
;transmitting line
:and turn on receiver
-for that line.
;8-level code, 2 stop
;bits, and no parity
-selected.
:19.2K baud selected
‘Note: 19.2K baud i1s
;not used by the
‘customer but can be
;used for diagnostic
;purposes to speed up
'the transmit-receive
;loop to make it easier

MOV #PAR, DZLPR

“TST DZCSR

BPL Test2

MOVB SWR,
DZTBUFF

:Start scanner and set
‘maintenance bit 3.
;Test for bit 15
:(transmitter ready).
‘If the branch condition
:1s false, the transmitter
- ;is ready; if true, go
;back and test again.
‘Load the transmit

MOV #DEL, R1

3-18

|
)

= ;_Characte'r from the
~

NOP

;0 scope.

MOV #N, DZCSR
Test 1:

;switch register.
:No operation. This
;location can be changed
'to a branch instruction

;1f only test 1 is
;desired (replace 000240
;with 000771).
;Delay equals a
:constant that will
;allow enough time for
:the receiver done
.flag to set before
:recycling the test.
:The value will change
‘with baud rate and
:processor. The
;constant given is
;good for 19.2K baud
;on a PDP-11/05.

001000
001002

001046

105737
160100 100402 -

001050

005201

001042
001044

001052

2:
Test

TSTBDZCSR .

BMI 1§

:condition 1S true,
;the receiver done

;flag is set.
;Increment delay.
:If the branch

INCRI

BNE TEST 2

001373

013700
160102

MOV DZRBUF,
R0

001056

001060

000760

BR TEST 1

001054

;Test bit 2 (receiver
;done flag).
‘When the branch

-condition is true, the
;delay 1s not finished.
:Read the DZ11
;receiver buffer to
-register 0. ;Loop back and
;test again.

Example 5 - Transmit and Receive on a Singlé".iLine Ufsing Silo Alarm in Maintenance Mode
001200
001202
001204
001206
001210
001212
001214

MOV #1100, R6

012706
001100
012737
001274
000304
005037
000306

‘Initialize stack
;pointer.
‘Initialize transmitter
-vector address.

MOV #3$, TVEC

‘Initialize transmitter

CLRTVECH+2

;vector processor status

word.

001216
001220

012700
001304

MOV #DBUF, RO

001222

012737

MOV #1, DZTCR

001224

000001
160104
012737
017470
160102
012737
050050
160100

001226

001230
001232
001234
001236
001240
001242

:Set first address of
;input data table
-into RO.
:Enable line O
‘transmitter.

MOV #17470,

:Set up line parameters
:and turn on the receiver
:clock for line 0.
‘Enable transmitter
;interrupt and silo
:alarm. Turn on

DZLPR

MOV #50050,
DZCSR

~
001244

001246
001250
001252
001254
001256
001260

001262

BIT 420000,

032737
020000
160100
001774
013720
160102
000240
000240

;scanner and maintenance

:mode.
‘Test for silo alarm

DZCSR

BEQ 1$

2%:

MOV DZRBUF,
(RO)+
NOP
NOP

;Loop until silo alarm
:flag sets.
‘Read DZ11 silo
-receiver buffer output.
:Delay to allow next
:word in silo to filter
:down to the silo
;output.

3-19

001264

100773

BMI 2§

0012£56
Lui12/0

012700

MOV #DBUF, R0

001272

000764

001304

BR 1$

;Data valid set says
;that word is good,
;go back for more.
;Silo has been emptied.
:Reinitialize data
;table address pointer.
;Do it again.

Transmitter Interrupt Service Routine
001274
001276
001300
001302

112737

000252
160106
000002

MOVB DAT, DZTBUF

:Transmit
;character 252

RTI

| D’ata‘ Table
1304
1306

100252
100252

:Word |
“

1340
1342

100252
000252

;Word 16
;Data valid

}

;not set

:character is
-invalid

NOTE

It is possible to get more than 16 words because they
are being put into the silo simultaneously with the
reading of the silo.

3-20

)

Example 6 — Echo Test on a Single Line (Transmit Received Data)
001000

012737

001002

011073
160102

001004

001006

001010
001012

START

MOV #PAR, DZLPR

;Load line parameters
;for line being used.
:Line 3, 8-bit

MOV #LINE, DZTCR

012737
000010

160104
012737

MOV #n, DZCSR

001014
001016
001020
001022
001024
001026

000040
160100
105737
160100
100375

19:

001030

005737

2%:

001032
001034

160100
100375

001036

013700
160102
110037
160106

MOV RBUF, RO

001040
001042
001044

001046

000765

BR 1%

TSTB DZCSR
|

:character, 2 stop
:bits, no parity,
‘110 baud, and receiver
.clock on.
‘Turn line 3
‘transmitter on.

;Turn scanner on
:(set CSR-5)

:‘Test (bit 7) for
‘RDONE

BPL 1%
|
TST DZCSR

;If bit 7 is not set,
;g0 back and test again.
:Test (bit 15) for
- TRDY

BPL 2%

If bit 15 is not set
;g0 back and test again.
‘Read received data
:word into RO

MOVB RO, DZTDR

3-21

:Load character
‘into DZ11 TBUF
.register for
;transmitting.
;Repeat.

CHAPTER 4
DETAILED DESCRIPTION

4.1

SCOPE

This chapter contains detalled descrlptrons of DZ11 circuit operation and signal flow; it also describes
the DZ11’s interaction with external devices and how it operates as a component of a PDP-11 system.
The text is supplemented by references.to DIGITAL engmeermg drawmgs and spec1f1catlons simphfied dlagrams and appendrces |
,

The Dle supports two types of output line mterfaces EIA and 20 mA loop Each has a separate
module with the following differences.

1. The M7819 module (EIA) supports three modem control leads (data terminal ready, carrier,
~and rmg mdlcator) The M78 14 module (20 mA loop) does not support these s1gnal leads

The receivers and output drivers are dlfferent for each type

The line interface cable, turnaround connector, and distribution panel are different for each
type.

Despite these differences, the Unibus interface logic, scanner logic, and output control logic are identi-

cal and these areas will therefore be discussed once for both modules.
4.2

LINE-TO-UNIBUS OVERALL DATA FLOW (RECEIVE)

When receiving data from a terminal or modem, the DZ11 module interprets a serial data stream and
performs a serial-to-parallel conversion before transferring the data to the Unibus. (Refer to Figure 4L) Each serial line, REC (07:00), connects through the distribution panel to connector J1. The receivers match theincoming signal levels to that of the DZ11, and the datais fed to the receiver control
‘logic, where it passes through a maintenance control crrcurt which allows the DZ11 to “receive’ its

own transmissions during maintenance tests.

From the receiver control logic, the data is fed into the appropriate UART for the serial-to-parallel
conversion. A parallel data format, corresponding to its serial input, is moved to a FIFO storage

“tank,” called a silo, which has a 64-character capacity. When requested by the processor, each character is read from the bottom of the silo (RBUF). The remaining characters shift one position down-

ward and the read character is multiplexed through the bus drivers to the Unibus. For the M7819
module (EIA), the modem control signals (RI and CO) for each line are routed directly to the output
multiplexer.

4-1

m
O

IHEEREEE

BCOBS

BCO5W

CABILE;
DISTB
PANEL

SDI

;

LOOP-

(:00) | BACK

RCVRS

1 CONTROL

MAINT

RDI 1 00)

|s1e-7 | JART
&

SILO

DATA

XCVRS

|BUS D (15:00)| K
11

RBUF

lseriaL pata oUT |

)

RI AND CO(M78I9-ETAONLY)

MSR
_
N

CSR iD_' OUTPUT

~ VECTOR

MUX

TCR —

11-4559

Figure 4-1

Line-to-Unibus Data Flow (Receive)

4.3 UNIBUS-TO-LINE OVERALL DATA FLOW (TRANSMIT)

During a transmit cycle, parallel data is brought in from the Unibus for transmission to one of the
eight terminals (or modems). (Refer to Figure 4-2.) The 16 bus lines, BD (15:00), are fed through data
transceivers and distributed to the device registers and UARTSs. When the DZ11 is ready to transmit, a
character is read from the TBUF and loaded into the appropriate UART for the line. The UART then
performs the parallel-to-serial data conversion, adds the desired character control bits, and sends the
data to the selected transmission line through a line driver, and subsequently to the modem or terminal
connected to that line. The break register connects directly to the drivers. Setting the break forces the
drivers into a continuous ‘“zero sending’’ condition. The DTR modem control lines (M7819 only) go
directly to the EIA drivers.

BCO8S
OR
BCOSW

sSDO

TRAN O0-7

(7:00)

RD(?.OOl

TDR

(Low)

TBUF (7:00)}

UART

pp-07

TBUF

DiISTB
DRIVERS

T
_

PANEL

‘

L= RD (7:00)

TCR,

CSR,

and

MODEMS

> OR
TERMINALS

,
DATA
30(15.001 XCVRS

U||q

RERERRR

TX CONTROL

LPR

RD (15:8)

TDR

RD (15:8)

(HIGH) | BK
BREAK

TCR

RD (15:8)

(HIGH)

DTR (M78I9—EIA ONLY)

DTR

11-4560

Figure 4-2

Unibus-to-Line Data Flow (Transmit)
4-2

4.4

FUNCTIONAL BLOCK DESCRIPTION

4.4.1

Unibus Interface

The DZ11 Unibus interface provides access for the DZ11 system to the PDP 11 Unibus. All signals
that pass between the Unibus and the DZ11 are routed through the interface. This logic can be divided
into three major areas: address selection, data transceiving and multiplexing, and interrupt control.

These are shownin F1gure 4-3. The mterface logic performs the followmg functlons
1.

Selection and recognition of the DZ11 addresses and device registers

Determination of the DZ11 mode of operation with the PDP-11 processor (DATI or DATO

word or byte)

Handling of data to and from the device registers and other DZ11 control elements

Controlling interrupts between the DZ11 and PDP-11 processor.

4.4.1.1 Address Selection — The address selection logic determines
the DZ11 device address and recognizes that address when it appears on the Unibus. A recognized address indicates that the DZ11 has
been selected by the processor or another bus “master.”
The desired address is selected by switches that correspond to Unibus address bits 03 through 12
(Figure 4-4). Bits 13 through 17 are always decoded as binary 1s (Figure 4-5). Bits 00 through 02
determine which device register is to be selected. This bit scheme allows device addresses from 16000X5
to 17777Xs. However, the DZ11 uses only the floating address space from 1600105 to 163770s. A
detailed description of DZ11 address assignments is presented in Chapter 3.
4.4.1.2 Interrupt Control - The interrupt control logic handles the processor to Unibus to DZ11
dialogue to permit processor interrupts. The logic generates the vector address and receives interrupt
commands from the CSR. The DZ11 operates at priority levels SA (receiver) and 5B (transmitter).
When two DZ11 modules are used, the first module (slot 1) has priority over the second (slot 2). The

priority insert establishes the DZ11 priority level by directing the Unibus request and grant signals
from the appropriate Unibus lines to the DZ11. A series of switches permit alteration of the vector

address to suit programming requirements. Refer to Chapter 3 of this manual for vector selection and
assignment.
4.4.1.3 Data Transceivers and OQutput Muitiplexers (Figure 4-6) — The data transceivers and output
multiplexers control data flow to and from the Unibus. The 4:1 multiplexers select the contents of the

CSR, RBUF, TCR, and MSR (MSR not usedin M7814) for transmission to the Unlbus The vector
bits are also transferred to the Unibus by the same logic.
4.4.2
Scanner
|
The scanner generates timing signals for transmission and reception of data between the Unibus and

UARTSs. The scanner timing signals originate at the 5.068 MHz clock, a continuously running signal

that is inverted twice to yield MASTER CLK
L and MASTER CLK H pulses. These pulses control
the baud rate logic, and a divide-by-five counter uses the pulses to generate the CLK H pulses that
drive the phase generator logic. Line sampling occurs during a 4.0
us period, which is divided into four

equal phases. Phase 1 triggers a line counter, which produces the SCAN A, B, and C line-select signals.
Each line is sampled sequentially. (Refer to Figure 4-7.) Phases 2, 3, and 4 are used in the receiver and
transmit control sections and are discussed in detail in Paragraphs 4.5.6 and 4.5.7.

4-3

l UNIBUS INTERFACE
ADDR A(17:03)

REG

AQ1, AD2

MODE

Ct, CO@

!
'

[

ADDRESS

MSYN

WORD

BYTE

?/1

SELECT
! <
L--.__-___
|

BYTE AQQ
- __ SS¥N I

REGISTERS

SWITCHES

ADDRESS

SELECT

6/7

N/A
5

N/A
4

2
4

| 4s5

ADDR

REG

RCVD

BITS

‘

D | LDATA D(15:00)
s K

|
—)
fl

) | pata IN

‘

I
I

NPR, SSYN,
BG

DATA OUT
_

DATA XCVRS &
MULTIPLEXERS

! >

INTR

BR, INTR, BG
I

Dz11 LOGIC

[

SWITCHES

! T INTR

A
|

, |R INTR

INTERRUPT

SACK, BBSY

TO/FROM OTHER

V(8:02)

VECTOR

VECT ADDR

SELECT

FROM OTHER
DZ 11

! RESET

CONTROL

LOGIC

)

11~-4561

Figure 4-3

Unibus Interface Block Diagram

A12

A11

A10

ON
E72 (M7814)

E81 (M7819)
OFF

NOTE:

ADDRESS

160000 - A12 THROUGH A3, OFF
160010 - A12 THROUGH A4, OFF, A3, ON
177770 - A12 THROUGH A3, ON

(OFF = LOGICAL 0, ON = LOGICAL 1)

MA-0803

Figure 4-4

Address Selection Switches

l 15|14 | 13|
L%

10]

SWITCHES —

| 1

11|

12|

s X

X |

0707

6 OR7

(DZ11 REGISTERS)
MA-0804

Figure 4-5

Address Word Format

5.y

xcvrs [*

| [

‘

DN}\L%\

DATA

lI\JI
S

4:1

RD (15:00)

—~
*

RBUF*

B En

f T

RAf

—

«—MSRTM

[+ —CSR BITS (15:03)

MUX

SELA |« INTR VECTOR (VB)
INTR

L—|NTF«>@(SEL-'R_CT)

RA2

UPPER BYTE OF TCR (DATA TERMINAL READY) AND MSR ARE NOT
USED FOR 20mA (M7814) AND WILL READ AS ZEROS.
11-4565

Figure 4-6 Output Data Multiplexer Bit Correlation

4.4.3

Universal Asynchronous Receiver-Transmitter (UART)

The UART is a complete integrated circuit subsystem that transmits and receives asynchronous data
in duplex/half-duplex operation. The transmitter and receiver operate independently and thus can
operate simultaneously. The transmitter accepts parallel binary-coded characters and converts them to
serial formats, and the receiver performs the reverse operation (serial-to-parallel). The UART requires
several control signals to properly time its operation with that of the remaining DZ11 circuitry. Each
UART is a 1602 integrated circuit, and one chip is used for each line. The baud rate, character length,
parity mode, and number of stop bits are selected external to the UART. Figure 4-8 presents a block
diagram of UART operation; a more detailed description of the UART is presented in Appendix B.

4-5

5.068 MHZ

CLK

COUNTER

- LD TBUF

l 1MHz
LINE

COUNTER

PHASE

TRANSMIT

—=

[
——®TRDY

CONTROL

PHASE

SAM
0-7

RDA
-7

SILO
SHIFT IN

<
_

DS
0-7

11-4566

Figure 4-7

Scanner Block Diagram

STATUS
WORD
ENB

DATA BITS

AND GATES
RDO

DATA

ENABLE ——

SERIAL
DATA
INPUT

RCV

SET

CONTROL LOGIC
T

EVEN
PARITY
SELECT

NO
PARITY

PARITY!

" FRAME.

OVERRUN
C

ERR

—-“—m_“—“—_-.

;

SHOWN AS
SINGLE BUFFERING

|
‘

'l_nuiun_cn-

RECEIVER SHIFT REGISTER

CLOCK ___
5
INPUT

? AVAILABLE

DATA HOLDING REGISTER
4

ReseT JREGISTER
DATA

[

EMPTY

AND GATES

(RDE)

IUART

" DATA AVAILABLE
PARITY ERROR
T

FRAMING ERROR

NB2
NB1
NUMBER OF
BITS/CHARACTER
11-1350

Figure 4-8

UART Block Diagram

4-6

BDOO

RD7

4.5

DETAILED FUNCTIONAL DESCRIPTION

4.5.1

Address Selection Logic (Figure 4-9)

The switches and resistor network (shown at the left of Figure 4-9) provide a reference voltage to be

used by the voltage comparators. These voltages are compared with Unibus address bits A03 through
A12. When a switchis open, a hlgh level voltageis compared to theincoming address bit; when a
switchis closed, a low-level voltage is compared The outputs of the Voltage comparators are wireANDed to provide a single output thatis at a high level when the deviceis selected. This only happens
when the voltages on all three voltage comparators match; otherwise, the output remains low and the
device will not respond. For example, if BUS A03 through BUS A 10 are at a high level and BUS A1
and BUS A12 are at a low level, a match only occurs if switches 1 through 8 are closed and switches 9
and 10 are open. From the voltage comparator circuitry, the output is inverted and used by the device
response logic and the register select and control logic, andis also sent to the multiplexer control loglc

(Paragraph 4.5.5).

The device response logic provides a delay to slave sync to allow for decoding and strobing data. LD
DATA H is delayed an additional 100 ns to allow the UARTSs to decode input data lines. Control
signals from the Unibus are gated to select register load commandsin the register select and control
logic. The output of the voltage comparators enables the register load s1gna1 output
4.5.2

Receiver Interrupt Control (Figure 4-10)

The receiver mterrupt signals the processor when the DZ11 receives a character from the terminal and
stores the characterin the RBUF (silo buffer) After processing by the UART, the characteris loaded
into the silo, and CSR bit 07 (RDONE)is set; RDONE causes generation of the RINT signal. RINTis
fed to thereceiver interrupt logic and the BR signalis transmitted to the proeessor via the Unibus at
priority level 5. When the processor status goes below level 5, a BG5 signalis routed through the

priority insert (on the DZ11 module) to the BG IN input of the receiver 1nterrupt chip, causing generation of MASTER, BUS SACK, and BUS BBSY. The MASTER 51gna1is inverted and gated to create
BUS INTR for transmission to the Unibus. The receiver interrupt is also caused by silo alarm. INTR

to strobe the vector address to the Unibus from the output data multiplexer.
is created
4.5.3

Transmitter Interrupt Control (Figure 4-10)

4. 5 4

Data Transceivers (Figure 4-11)

4.5.5

Output Multiplexers (Figure 4-11)

The transmitter interrupt occurs when the DZ11 is engagedin character transmission and the processor must be interrupted to request additional data for transmission. The mterrupt sequence begins with
assertion of TRDY with TIE set, which generates the TINT pulse. TRDYis the result of the line being
enabled and the transmit buffer for that line being able to accept a character. The TINT 31gnal begins
the processor-Dle interrupt dialogue via the Unibus. The transmitter interrupt prlorlty is less than
that of the receiver; therefore, bus grants are received only when a receiver 1nterrupt is not in process.
The transmitter interrupt logic causes generation of the same signals as the receiver logic, 1nclud1ng
strobing the vector address; however, the transmitter vector is located two words after the receiver
vector. For example, a receiver vector of 300 automatically places the transmttter vector at 304

The data transceivers allow the data to flow directly to and from the Unibus. Lines BUS D (15 00)
convert information and control data on the Unibus to the proper levels used by the DZ11 and are sent
to the device registers by way of RD (15:00). Information back to the Unibus is presented to the
transceivers along lines D (15:00), which come from the output data multiplexer.
This logic controls the flow of information (data and interrupt vector) to the data transceivers for

output to the processor via the Unibus. The interrupt control logic sends INTR to control whether the

vector bits or data are to be sent to the data transceivers. The INTR pulse goes low to send vector bits.
The processor sends two lines, BUS A01 and BUS A02; these are inverted to become RA1 and RA2,
which drive the multiplexers’ select lines. When a match condltlon exists in the voltage comparators of
the address selection logic, signal SELis created. This signal, ANDed with RC1 - the inverted BUS Cl1
s1gna1 from the processor (DATI bus cycle) — gates the selected register to the Unibus data transceivers.

4-7

4.5.6 Receiver Control Logic (Figure 4-12)
|
The operation of loading a character into the silo and reading the RBUF is timed by the scanner.
As
shown in Figure 4-13,
at the trailing edge of phase 4 (leading edge of phase 1), the scanner is in-

‘cremented to the next line for sampling. During phase 1, the data available (DA) flag is sampled. If the
flag is set and the silo is not full, a shift-in (SHI) pulse (leading edge of phase 2) moves a character
from
‘the UART for that line to the silo. At the trailing edge of phase 2 (start of phase 3), the reset
data
available (RDA) pulse resets the DA flag if SHI occurred during phase 2. Phase 4 terminates the
RDA
pulse. The Unibus initiates a character shift out of the silo by reading the RBUF (Figure 4-14).

4.5.7 Transmit Control Logic (Figure 4-15)
|
The transmission of a character from the DZ11 is primarily controlle
by
d a network of logic circuits
called the transmit control section. This network generates the timing signals for line selection,
UART
control, and data transfer to the modem or terminal connected to the DZ11.

‘When the TBMT signal goes high, it indicates that the transmitter buffer for the UART being
sampled
is empty. TBMT is inverted and strobes the appropriate line enable (LINE 0-7) signal through the
logic. This occurs under the control of signals SCAN A, B, and C, which provide the
proper selected
line. The transmitter control operates in four phases (Figure 4-16). The phase 1 pulse
is delayed 50 ns
to allow propagation time through the circuit and to avoid race conditions. As phase |
ends.and phase
2 begins, the delay ensures that the proper line is latched up at the 8-bit addressable latch
before data
changes. After passage through D-type flip-flop chips, the line select data reaches the priority
encoder.

The priority encoder outputs signals TLINE A, B, and C, which are sent to the output data

multi-

plexers. Signals from the priority encoder inhibit gates feeding the clock for the D-type
flip-flop chips.
‘This prevents the inputs to the priority encoder from changing until the line has
been serviced or
disabled by the programmer.
|

Character transmission is allowed for the first 400 ns of phases 2, 3, and 4 during CLK H pulses

only.

During phase 1, transmission is inhibited to allow sampling of line enable bits. Outputs
from the
Character Loaded flip-flop and priority encoder are used to generate the transmit ready
(TRDY H)
pulse, which signifies that a line is available for transmission. Transmission is initiated
by loading the
transmit buffer register (TBUF). This causes the Character Loaded flip-flop to set;
TRDY H drops
and cannot be asserted again until this flip-flop is cleared. If all conditions for transmissio
n are satisfied, a 300 ns one-shot allows data strobe (DS) to the UART. DS loads the contents of the
TBUF into

the UART and transmission starts. The correct DS pulse is a function of the TLINE outputs

from the

pin 5, is cleared and G2, pin 4, is disabled. The output of this gate goes low and turns the

priority

priority encoder. Priority level is achieved in the priority encoder by having each ascending
numbered
input take priority over the input with the lower number. The 300 ns pulse is also gated
to pin 14 of the
8-bit addressable latch and opens the latch selected by input pins 1, 2, and 3. During phases
2, 3, and 4,
these inputs are the TLINE bits from the priority encoder; the data input (pin 13) is at ground
level, so
that the latch for this line is cleared. In addition, the pulse causes the priority encoder to
turn off after
it times out. This makes pin 14 of the priority encoder go high and causes a clock output
from pin 11,
G3. This output updates the 8-bit register from the addressable latch outputs and presents
a new set of
inputs to the priority encoder. Pin 11 of G3 also triggers a 150 ns one-shot, which
allows for propagation delay and data settling time at the priority encoder inputs. When this delay times out,
flip-flop G,
encoder on.

The output of E2, pin 6, gates the reset for the Character Loaded flip-flop to clear for
the next transmission. If another line is ready to transmit, pin 14 of the priority encoder will go low
and the TRDY
signal will be reasserted. The TLINE signals will contain the value of the next
line ready for transmission. If the line enable bit is turned off, the 300 ns pulse occurs but no DS will be sent
to the UART
be;callse pin 5 of G4 is low and disables GS5.

|
i

VOL
LTAGE COMPARATOR

EB1

10K
A
10K
|

SWITCH PACK

I O

O I

EC1
BUS A12 L ECGL 11

+O/O—|—

o
10K

| 8

_—13|

AA——

BUS A11 L ——=0O B3 | yout
BUS A10 L Ffl—%o B2 COMP
D2

BUs Aog L ERL1ygy

10K '—I-—O//O—t—l

BUS A0s L ENZ213~ g

10K
VW

| 6

._—15] l

;

—

BUS A07 L EP21203

[

OUT

741500

/:16

8881

10K

l4: _— 17|

WA~

|
"

10K
A

10K

|
|

|
-

<
8136
EUt 11
BUS A06 L ——
() B4

BUS A0s L EX1.2yB3 | 0

¢
-

|| 2{)/01_9_|_J
, ‘
T

| 1 0 _—.20

O=—

L — — ]

)

12905

BUS A04 L EY2 3~lgs COMP
BUS AQ3

EVZ..!O B2

1p2

L °0

aus a0t L_EHT

ouT

;
8837

\
/

STB
7

iL¥e'

8837

—

DL1

°0

<__q7

8837

O0—

DATO

7405138

poO!2 LOAD LCSR L

UseLa D102 LoAD HCSE L
3lseLc D3O

BUS INIT L

P2 CTZ
D3
[O-< LOAD LPR L
el

=150

SEL

D10 LpcsRL

worp P8I0
LOAD TCR L
I\
9
D60
gy

74LS00
)

BUS A00 L—

SELECT L

po D2
SEL A

2lseL s

———=—D6
Yo

— 20|86
[ 4

13-O

EF1

—O

BUS AO2 L
-

8837

RBUS L
ELo

8837

BUS A14 L———*T{O B6

STB

74LS32

l G

EF2

ouT

—O
BUSC1L

—=0

S2 L DATAH

‘

Ek2] ] P6
BUS A13 L ———()} B1

EJ2

Bus- msynLEE! 3~)g, 8136

Ek1[75P3

74L840
8881

BUS A15 L=—21-3(0JB3

DEVICE RESPONSE

BUS CO L

EJ1 BUS SSYN L

PF
T= 100 ns :]'_\470
L

Bus A17 L. 224 10~
11y g454 yout
EE2[
13~
Do5 COMP
BUS A16 LEEZ
13y

100

| |

STB

T3V

)

5 :

%"(

ELT_E

——
7

+5V —

8136

| +ov

(41

INHIBIT SSYN L

‘

—

e
~JEN

pafOH LoAD LTCR L

D° p—‘o LOAD HTCR L '

YTE pe O— LOAD HTDR L
D7[D—L LOAD HTDR L
R6 H
RA2 H

RH1 H
INIT
H

MA-0055

Figure 4-9

Address Selection Logic

4-9

1 VT iNTR

8851

FJ1

STEAL
3
)GRANT
E___g
g

$R29
> 180

+5V

BG INH

)

———Ofssyn

OUTG.

B SACK O

FP1
(FU2)

BRL

E MASTER O~12
@DON
|
P

—

BGIN

CLR

o390

|13

_ BusBBSYL

.BUS SACK L

2L 1OREQ IN SACK[—

RINT L

g R30

INIT H

REQC |~ 9

|
INTR

BUSY [0 10

B6 OUT

20 74104

11
|
741832 )—3)

—AAA— 45V

- R27

gack

{

CLR EN
21!5

RECEIVER
INTERRUPT
|

oo1

50—o

o
BUS SSYN L ES1

.gffi 0>

TR
O SSYN

SACK O—
.

GRANT

N=B
[

STEAL

;

EP1T_

RINTL———QJREQ IN
B6 IN

sACK| -: ,

B6 OUT

113

215

E28

BGOUTH
,

+5V

%R33

10K

I %R34

10K

Lo—" 02 i

%R35

10K

VB5
VB4

+5V

$ R36

I
I
15
20— o024

VB6

+5V

4
l 3{3//(/t}1 ]

]
|

74Ls04

VB7

;

gRL

DONE MASTERD

]
|

10K

{)/O“ |

BUSY jO2

l +5V$n32

—_

INT

74LS04

BUS NPR L

8647

10K

VB3

+5V

DA1

TRANSMITTER

S3 VB2

INTERRUPT

|BG IN He2Y2 2

PRIORITY

INSERT

6DD2 ppyy
5DE2

__ .,

ppsL

BG OUT Ha2Y2
3

4DF2

BG4 OUT H—2T2
4

13DM2 ora L

BG4 IN H—252.5

BRL

12 DU2

BG5 OUT H«2826
BG5 IN He2FP2
7]

11 DK2 pGg7 1N
DL2
0
gpG7 ouT

9 g4 |y
DM2
BG6 QUT H—2N28L—

MA-0056

Figure 4-10

Interrupt Control Logic

4-11

Q15

31 7°

T LINE B H
V3AH

13l

TLINEAH
VB2 H

VB3 H
l

B31

——

RI OH.

74LS157

LINE O H

w1k A2

MAINT H

RDAT0 H

5|
1

?15

Aq 74L81

RDAT1H

LINE1TH

RI1H

s|
|

RDAT 2 H

LINE2 H
Ri2 H

12,

74LS00

BUSDOL

_—

= IB

~
{i>>

sTBO

CcO

10}

o1 74LS152

21 B8O

—

‘

—

D2 H

—

BUS D1 L

INO
D
o

l |

D3}i£

gl_

S8 RD
1 H

81 cu2

c{>

BUS D2 L

| 3

g 6

;

CT2

BUS D3 L
S8 RD 3 H

___)——

S8RD 2 H
|

;

K13

‘*

5
|

]

K
—

S8
RD O H

|1°
i

14"

sTB1
AO

131 b1

—]

RI3 H

S 1

:;AB1

LINE3 H

11y

RDAT 3 H-

D1 H

%
DOH,
d

RA1 H

FO |

1 co

F2 9 L=
STB

‘UNIBUS TRANSCEIVERS

MULTIPLEXER LOGIC

I
A
A
|
T

I
‘

RA2 H

etso

)

RDAT 4 H

LNE 4 H

RI4 H

e
RDAT
5 H
o

CLEAR H

]

VB4 H
I MSCAN EN H

3
1131 12

2 |

|
F3

VB5 H

A3 74LS157

VB6 H

RIE H

RDONE H'

-1 8"

VB7 H

STB

INTR L

LNESH

RI5 H

SEL L—O

8TB1

bo 74LS153
10|21 .
11
7

B
€1

2 1co

131

STBO

{

1,1

DaHY

1
-

D1
2

S0
14
[

’-

10
RDAT
6 H

RI 6 H

RDAT7 H
RI7H

Q15

2180

5] co
DO

D6 H|

| 1

S8 RD4 H

; 13
'

}

—
|

—

S8 RD
5 H

Cv2

S8 RD 6 H

BUS D6 L

{D 4 3

S8RD 6 L

I
I 4CMZBU5
6

D7 L

_}'O
7

‘

-_91_0

|
L

—-—11ZCN2

{1:>>

;

D7 H |

‘

[

6 | \o 7418153

BUS D4 L

| SN

,,STB1 STBO

e 19CP2 busssL

CIESED

i
144

CIMERS

8641

05,1|!

LINE 7 H

S8 RD
7L
|

MA-0057

Figure 4-11

Unibus Data Flow
(Sheet 1 of 2)
4-12

3|vsHov Lv98.4||sn4g12ZLd_
081S Lats | Ot

(Sheet 2 of 2)

4-13

A | 04 N

)

is : ¥ Hea L L

5 —®
o — a— — —

:4
v
4
S
l
,
=X] Pl ovjo . |
\_
snsg 7010

)-2-Y03 ;o090H3AVDo9OdQS4S-H|HH1y|8OigSt-ooLoqygla8qd%4€ESSILSSIW-WLLL]4od466L0 LB||sEH1ZLLiLv|L aaaai_aHH_V:H!i ,- :19S|etizZ;a430sDns1n5gogL—a1—v1La§|]|

Bm—M0'@”®vO—.|___HHHaVO.I3H4YaXHa0lHilAllNN5aaaTaLuIndTtZzOL9SIlya-DLHLHHHTNINe2Mei=o=M|@l”119=”%oLLL0a0M)Yovn8a9gL?TL7—1S.zS9S1mz=at~s:0wo8me10a.i01|_S@SnSv107Lm54y414_+Hoo,Law|ii_b,pz:—SH3IAIFDOSIN—|VmmiHLTI.'CRNG||I|TRGEs||nRCILQAE,EUTEARSDI|N,S__;.GERA/NAAA%D\Te/VTv_D_m—2e|__mom_slL1_.”vtfmNNHZ.I0DrUoAHaaaQaHd8Yya6O¥HH|Ly1SH-LLHH|_|_|
g S

poud

€

(Sheet 1 of 2)

4-14

Receiver Control Logic

£S OIS WHVYV N3 H

8,0 o— 9.0 9 Y0SvL L134ng234avay

Figure 4-12

(FRE)

6'z"

7.13s3d

—ny

vLSIPL

50 mO : 80S1¥L a o9
6 L3S

890°S 03H3INOQH a-LBg_¢: aiva ZLalL_6L1d4nIoHSLNOHIHLS,o VYIN)10Hv v g NI L31HSNIH
z

902

06STVL

P1LEO0-VIN

uyuaaus¥s3aLLssvvHLaaLvvN1aaZInN1VZHoINWOO1LNHoHI[1—[zo—a9£LT8l—2LE—Te—VvVm_uXL0—1e44)]——z¢]]dtyyH33LssNNNIiI¥z€H3ZHsyu333u¥ss£3sL1svvL1vaLavv.LazHaS9WaNNI1L1I—NSvHO9[—HS~1L||—pC€9—gl~Ho}NLrg—£eOyVVnv1wvaLvaz01a444I1T[———V6L¢.tAH44Hv333eI5mssSfwiNNeNnIIILw£GH0HH9|HI—LSYILNAINHVSOSN3Ln1aLnbvyzEaZ—§LLATGIoHztOVaaabAYH(((0LbL)IziogyHY5]5€=L—]1|1=0Z03SVH47IHSLAzLoL0oLqTe1763sYHI_3-,@eq

l
z
Z
L
4433HSSals1vHvaEaHNHIEOL10lN1vNOaO-0~I—8——8o1Vs 0€s4—vO 43SHONIuy33Hss3sL1lvLvaava£r1—/NN0HIVHHY1Ij€N—LVO|Oa—€V19s 0gsq—:]YISNIHY(L)zY bv—ewq10((o300))1yeod0y——vl 200120H3ISYH4O071 N 6i
EL

80S1vL

0 SIVL

musg | St

0d (L)oy

AHD

NS+

€]

Lad—()038LvaTIVAY1L194flo37dWVS1
o9L

oLy

HAO

_=i)

Figure 4-12

4-15

Receiver Control Logic
(Sheet 2 of 2)

€ v

vLSWL

£l

419

NG+ AMN—

NVOS V H

€2aq NI (L)zey— vaasILSs1S4I"vL0SZ L23yLva1IVAV£1 vSaLLSSiIVL0sz LT=3N7VdOWSvs2£H1
L
6
6
5
2
S
1
v
L
4
z—b——0z4g WHEYIVV(1)oed———1_i ¢l a :|—-—OOISHNIYHW aHvZozqlv1avoaauH9|el—b—v1iva L244|oeL LNOD3804.1SLH
b OS2

. é}° 643<SlLFd11NanaAmd.mg_aympo_Sg.mdNmu6V£a1ov6L?|vvSLTdSIaLNTPa1pLYPan)mL1LlurA»UN4aH(T\—1(_LflO;i)0Lf_LYuyvYv1l9—¢€ 3€€|4=mO=—¢Ofoi_.9ruaQ—Loo88o860Lal£svNSaz£o1A0zANlaav8v0SEs4444d€l9—II—II,wmQC(.OI=N])omOP9920o333384848yLL1LLvvvvaadaa1VNVV1IY0AAAV7oLVVVYI3vvy7a¥11A9So€2HvaOy1v1aaHLL|0€(—4Dggv—)al€svLaoz€goz3l9aa9V&0GvzvV4d4s4d444d£l|.Y—]f—]9ilSmMII—O)p|.|65 lAAH)]O0OEmN-ILIL1L333N1NNNN71NT10GAOOvdaOdd3DSDDWNwDWSN1SV3vV3V3a138S8sgS|8S9nS800w046H410311Hv4.99Hv.€21sL1101SSS4S£S9H¥Z0EHHHH
+d0Z1

3SVHd¢“[£||£1[m

e—_SNVHL-LIGIHNI _~u_\0T,vSd,Ld94vI1HS4SN|I1L33(SsI3HAySN)V,v4a1,0971v1S4SI4L1|OLN4I7HSN4__m.AQHL|1vivd\38¥00Y711SD0L1X|31N¥v3NAnNITJiyUrurLuryrarar’_

e_m_I3SSVVHHddva|2:J_L:NVIWQI:H"O:NI:_JH_INVISOLLX3LIN3NITNOONIGV3T3903Lwgyr__u“:Crejou_ry[u2rHdyI4duNYrSulrSuHJdr31uLdAVrSu“'3Tr)buHOdNI3rQ1VdOTWVSVu¥¥ILOVHVHO|OLNI]|(4NEL])m_m

(N0

JEpEpEpERE

S¥€¢

8.9

Figure 4-13
|

vdv SiST 1Qd3WTY1dSWVS ONIYNA 3SYHd35 |

3N6WILFH04O 4 2V1 3T1IOI€ NISGl3N9I1T 4l 8k

DZ11 Scanner T iming

4-17

iS|Y3AIQHvI3ONY 3INIT

LONIL INSNVY V d310VHVHO

4nVgIlAL SNAINN4074 13S %

{ (3

I
T
d
N
V
S
—
>
3
N
W
I
L
4
0
4
L
X
3
N
—
3
N
I
T
I3]SVHvIJaHLyS¥|YTN]L]L:31u|L.O_Nn_sOzI|mS\]T_||aL4vIiHvSdS1ILVNAOY3(1OH8SV)fi9v3\14w4V(vQa3d)LNVIHI0L(4IINH3LISI)NWI[TOdH39¥dN-I]N3FJHE2LLb0J.3SNN38VIONSL4§:|]LLHo4LwIalSR¥AOo4LNE1V-_]I.1-VLHLHS,o4b**LAW]Q8V13Y].Lo7.-_]wa—~|)¥)..(
31dAVS

o261

SELECT (SEL)
1

SSYN
1

RD RBUF
1

DATA VALID (DV)

)

SILO

EMPTY

> SHIFT OUT (SHO)
RDONE

DATA VALID (DV)

SILO NOT

SHIFT OUT (SHO)

EMPTY

RDONE

“—3

WIDTH DETERMINED BY

SILO IC'S RESPONSE TIMES
L

)
Y

SILO OUTPUT IS READ TO UNIBUS DURING THIS TIME
11-4772

Figure 4-14

Silo Character Shift Out Timing Diagram

4-19

S12 TO 815 __|
TBMT H

74LS175

tojo—
DO -D7
5

5lp1
10 B2

13,

S9 SCAN
CH

2lg

S6 LINE 7 H

_
|

ABLE

S10 T LINE C H

50ns

TC9

ReseT

L ave

¢4

c LATCH

|r4Ls32

S9 CLK H——L-O
>

74LS04°\\

—_

STB

74Ls151

| |

fOK

Ga
DO-D7

SIQTLINEAH

R63

N K

9
0—

2
—

0[P

‘

74510

PH
2 L

__S1py

R2(0) |~
7

;

R1(0) "

RoO(1) —

15
00—

o [3

GSO—

%H7

R1(1)6—

RO (0)

+5V

R65

CLK
5

cor
—

39Pf

5.6
K

|2
5

}

;

9602

N A

P—

E106 | g

150ns

sV H

_O—

|
|

$14 éz

1112 |74Lsez 13 S10 TRDY H

STS5 STSh

DCHAR 1[5

LOADED
74LS74

rara

L ul.e 5°°

5
_

13
|

e
8
O—

o
A

c96
—

15/1p0 P§

fADIO—S10 DS 3 L

|14

10
R

9602

300ns - O

T13

[

2o o1 i1he
G1 1

= | 7474

B3O S10 DS 4L

fB2/07- 510 DS 5L

fB1/O—

4 741504 /

S10

fBOJO=
9 S10 DS 7L

——1DB

p—

ofs
|

T“
|

fA2I02-S10 DS 1 L

fA1j0>—S10 DS 2 L

DATA STROBE LINE CLR| 2|74LS00

12
1z

2664K

)

745195 ta3lpt
16 s o L

—OjpA

220 Pf_L

3
H—=

9318

S6 LD TBUF

R2 (1)

|12

DATA STROBE PREVENT

S0-S3

12155

)

13|

S9 V H
'

‘

C95

12074"308/

108
Ty

INH

|131
|

_
5

74LS74

5 |74Ls02
S9 PH 4 L —0O

R3(1)}-=

R3O -

?1
MSCAN

—

74LS175

CLR
$6

S19 T LINE BH

‘

AD-AD

loja

_13lp3

295

ENCODER

CLK]

? PRIORITY
RIOR

130
12

R3(0)

74L504 S 8

ce 11

R2(2)
R3(N|14

CLR

R1(0)

(3|7

ADDRESS-

DATA

= Pf

8BIT

100

£11
t218

Ré7

SS9 PHI L

74L504 > 12

Al-pa3

745259

STB S0

S6 LINE® H
:
‘

12155

: 10
RZ(!)
y

_$0,1,2

5 D1

Ro(}E—
RO(0)
R1 (NH—

74LS157

Yoo

\7aLs02\

S8 RESET H—>

[

11-4568

Figure 4-15

Transmit Control Logic

4-21

'e: My, YATATRL YLATY
2Hd

Figure 4-16

vHd

3719vSsS3yav

1 9-8 HO1V1 N|id

HNI 11X

Transmit Control T iming

4-23

4.5.8

Registers

The DZ11 uses four device reglsters in a manner that yields six uniquely accessible registers, each

having a 16-bit word capacity. The six discrete registers temporarily store input/output data, establish
DZ11 operating status, and monitor control signal conditioning. Depending on the function of the
register, some are accessible in bytes or words; others are restricted to word-only operations. Since
registers can be read or written into, the selection of either a read or write operation allows two of the
device registers to function as four independent registers.
|

The subsequent paragraphs describe the operation of each DZ11 register. Refer to Chapter 3 of this
manual for additional information regarding reglster b1t a351gnments bit functions, and programming
|
,
techniques.
4.5.8.1 Control and Status Register - The control and status register (CSR) comprises two 74L.S175
chips (Figure 4-17). Additional gates are used to control the register and generate signals that are CSR
bits but are not stored in the 74LS175 chips. The Unibus lines, after routing through the DZ11 bus
transceivers, direct the operation of the DZ11 in accordance with the PDP-11 system requirements.

) \\’w/’

Bits RD (03:06), RD12, and RD14 are stored in the CSR chips since they are read or write bits. The
CSR is controlled by LD HCSR, LD LCSR, and LD CSR signals from the address selection logic.
These signals are gated to the CSR chips to yield selection of the upper (HCSR) or lower (LCSR)
portions of the register. The RINT and TINT signals are produced by the outputs of the CSR and
other logic that receive signals required to generate receiver and transmitter interrupt commands.
TheCSR is reset by a RESET L pulse to the CLR input of the chips. The LD CSR signal activates both
CSR bytes and accomplishes the loading of the entire CSR. Several bits (00, 01, 02, and 11) are not
used and have no effect on DZ11 operation.
4.5.8.2 Receiver Buffer — The receiver buffer (RBUF) is a read-only register that contains the received
character (lower byte), the receiver line number (bits 08-10), and four character-condition signals
relating to errors in reception (bits 12-15). Bit 11 is not used in the RBUF. The RBUF read command
is generatedin the address select logic. The RD RBUF signalis inverted and fed to the receiver control
logic to cause the first-in character of the silo to be read from the “bottom” (RBUF) of the silo. The
trailing edge of the RD RBUF command causes a SHO H signal to be sent to the silo to shift the next
character down through the 16-character posmons (Refer to sheet 11 of engineering drawing
M7819-0-1 or sheet 12 of M7814.)
|
:
_
4.5.8.3 Line Parameter Register — The line parameter register (LPR)is a write- only segment of device
register 2 (Figure 4-18). The LPR contains various line parameters such as line number, character
length, stop code, parity, DZ11 baud rate, and a receiver-on bit. Bits 13-15 are not used. The LD LPR
signal is generated by the address select logic and fed to a 500 ns one-shot that drives an 8-bit addressable latch and inhibits SSYN from being asserted on the Unibus. The latch is open and the LD DATA
L signal is gated to the proper UART, selected by RD (02:00). This is the control strobe (CS) signal
that loads the line parameter data for that line (e.g., character length, stop bits, and parity). The CS
signal occurs approximately midway into the inhibit SSYN signal; this allows proper data setup time
for the UART inputs. Refer to Figure 4-19 for the timing of the CS signal.
The second latch records bit 12 and turns on the receiver clock (RCLK) for the selected line. Bits 08
through 11 are strobed into the baud rate generator chips by the CS pulse. The output of this chip is
the transmitter clock (XCLK), whichis gated by the condition of the output from the second latch to
give the RCLK for the UART.
4.5.8.4 Transmit Control Register (Refer to Engineering Drawing M7819-0-1, sheets 5 and 6, or
M7814-0-1, sheets 6 and 7) — The transmit control register (TCR) is a read /write register that comprises
four 74L.S175 chips, two for the low byte (line transmission enable) and two for the high byte. The high
byte is used on the EIA version only and contains the data terminal ready (DTR) flags. Setting or
clearing a bit in this byte will turn the appropriate DTR signal on or off. The low byte contains a line

4-25

enable bit for each line. A set bit allows transmission on the corresponding line. The register is controlled by LD TCR, LD LTCR, and LD HTCR signals from the address select logic. The inputs to the
‘register originate from the Unibus lines and pass through the bus transceivers. The low byte of the
TCR is cleared by RESET L and the high byte is cleared by INIT L.

S b1

H
RD 14

- 74500

7418175
E2e

E99

rR1(ME

J°

Yoo

T INTL

R1 (0)|
8—
12

RD 12 H

r2 (1|2

TIE H

SAE H

r2(@)
|
LI P

R3 (1)2—

rR3 (0)HE—
o

RO (0)°—

CLR

CLK

T1'

" RESET
L

LD HCSRL

——12

74L508
RDONE H—

SILO
ALARM

|7aLso0

E76

E87

74LS32

E100
_

T4LS10
E97

RINT L

7418175

12 D2 ket R2 (1) )

RD
3

MAINT H

R2 (0) | —
4

RD
4

)

RO (1)

CLR H

RO (0)
| >—

Blps

" RD5

5{p1

"RD 6

CR3 (N2

MSCAN EN H

r3 (@) |2

MSCAN EN L

rR1 (M

RIE H

R1 (@) |8—

LD CSR
L
—L—2dy
LD LCSR L

|7aLso0

~|eLr

CLK

i1.

E76,

11-4572

Figure 4-17

CSR Diagram

4-26

MASTER CLK H

MASTER CLK L

RD 9 H

2180

RD 11 H

‘l»
|

6l.,

KoLK o H )

i1:

74508

a1y

X CLK1 H

|
:

741.S08

Bt
RATE
=~ GENERATOR
c1

13 o1

X CLK 2 H

£1

CLK1

CLK @

o |7aLs08 )°

|1
.

RDO H —A
»
RD 1 H —={B

éRsz
>10K

8B e
ADDRESSABLE

LATCH
'

C99
120
P 1 L paTa v —'2{paTAc
—j—
5.

LD LPR L

—1

|14

9602

Y
]
L

?15

[O—

7|50

fajcS3H
os a1

o1
°P1®

RD @ H —Ha
.
RD 1 H —=4B

BAUD

3
RD2 H —¢

1614
5

RATE
—8!'
14|
.
GENERATOR

CS 5 H

Y
cen
fe

3DICLK1

_g7|SSTH
z

17
CLKé1

—

14
e

‘

]

RD 12 H —>1DATA

—

R CLK 3 H

ks
F1E2
(16

f4f>

LaTeH
¢g
NO.2 | TRl

‘

741528

Y
‘
°

8-BIT

ADDRESSABLE

—

741.5259

CLK 3 H

‘

RESET L

_rrfE

?‘5

__E

——
INH SSYN
L

—

> TO UARTS

. o!2
|

VECTOR
H
OR

EXT

Slao
6lco

(olcS 2 H

3
RD2 H —2{¢

' +5V

EXT 1

R CLK 2 H
—

{

—1AD

fp|cS 2 H_
fries t H

R CLK1H

BAUD

14|

7415259

R CLK @H

5016

_1.6_'.A1
15

CLOCKS

EXT 2

4 AD

RD 10 H

;

EXT1

RD 8 H

BAUD RATE

113

—

EXT

182

—

- AQ

—

X CLK 4 H

—

‘

—

‘

7 DO

B1p1

£1 7

CLK1

|1 |

EXT

CLK®

—

—_—

|16} A

Efi‘%'é

GENERATOR

CLKO
8

;

’

||
|

5016

‘

,|74Ls08 2

EXT 2

fol2

CLK1
12

5050

1 Py

CLK

4 H

X CLK 5 H

GENERATOR

14|.,

14f.,

161 74

6lco
bo

741508

‘

X CLK 6H

74508 \8

R CLK 6 H‘

X CLK 7H

|
|

R CLK 5 H

10| 741508 8

R CLK 7 H

11-4573

Figure 4-18

LPR Diagram

4-27

CYCLE

START

END

SEL L

LDLPR L

INH SSYN L
LD DATA H

500 nsec
DATA SETUP TIME, RD LINES (200nsec)

|
j

FS nsec
350 nsec

SSYN L
CS H

LPR STROBE

300 nsec

Figure 4-19

Line Parameter Loading

| l—

4.5.8.5 Modem Status Register (Not Used for 20 mA Version) - The modem status register (MSR) is a
read-only segment of device register 6. The MSR shown in Figure 4-20 examines data relative to the
status of modem operation on each line, such as ring indication (low byte) and carrier-on flags (high

byte). The register is dynamic in that it represents the current state of these lines. These lines must be
continuously monitored as transitions on them do not cause interrupts.

4.5.8.6 Transmit Data Register (Refer to Engineering Drawing M7819-0-1, sheets 5 and 6, or M7814,
sheets 6 and 7) - The transmit data register (TDR) is a write-only segment of device register 6. The
TDR, using four 74LS175 chips, comprises two bytes; the low byte contains the character (TBUF) to
be transmitted, and the high byte contains the break (BRK) bits for each line. When the BRK bit is set,
the line transmits zeros continuously. This is accomplished by a NAND gate for each line that requires
the BRK signal and SDO (serial data out) to produce the TRANS 0-7 L signals. The TDR is cleared
by the RESET L pulse; for character lengths less than eight bits, the character must be right-justified,
as the most significant bits are forced to zero. The TDR is controlled by LD HTDR, LD LTDR, and
LD TDR commands from the address select logic.

DZ11

coe-7 |
MODEM

RI @-7

DISTRIBUTION
PANEL

coo-7

RL 0-7

EIA

RECEIVERS

co 0-7

RI@-7

OUTPUT | pp-15 |N
DATA

_|MULTIPLEXERS

NV
11-4575

Figure 4-20

MSR Diagram
4-29

CHAPTER 5
~
- MAINTENANCE

5.1

MAWTENANCE PHILOSOPHY

‘

The DZ11 maintenance philosophy assumes that proper and regular preventive maintenance can ehm-

inate most equipment failures before they occur. The DZ11 moduleis designed so that module replacement can restore the system to operating status in minimum time. The correctlve maintenance
procedures containedin this manual are designed to assist Field Service personnelin detecting component malfunctions on the DZ11 module and ensurmg proper DZ11 operation within the 1ntegrated
system. Prior to performing the procedures outlined in this chapter, the material presented in the
previous chapters should be thoroughly understood.

5.2

PREVENTIVE MAINTENANCE

Preventive maintenance consists of tasks performed at perlodlc intervals to ensure proper equrpment

operation and minimum unscheduled downtime. These tasks consist of running diagnostics, visual
inspection, operational checks, adjustments, and replacement of marginally operating components.
The preventive maintenance schedule depends on the environmental and operating conditions that
exist at the installation site. Normally, preventive maintenance consists of inspection and cleaning
after every 600 hours of operation or every 4 months, whichever occurs first. For extreme conditions of
temperature, humrdrty, or dust, and with abnormally heavy workloads, more frequent maintenance
may be necessary. Itis recommended that the DZ11 diagnostic MAINDEC-11-DZDZA-REV-PB) be
run once a week as part of the normal preventive maintenance schedule
5.3

TEST EQUIPMENT REQUIRED

Maintenance procedures for the DZ11 require the test equipment and diagnostic programs hstedin

Table 5-1, in addition to standard hand tools, cleaners, test cables, and probes.
Table 5.1

»Equipmelrt

'Designa'tion_l

Manufacturer

Multimeter
Oscilloscope

Test Equlpment Requlred

Triplett or Slmpson
-

" Model 630-_NA ot 260

Module Extender

DIGITAL

Modem Control Connector

DIGITAL

Diagnostics =~

DIGITAL

Type
454 or equivalent

‘W904 Hex.doub_le—sided

H315 or 325
-

MAINDEC-11-DZDZA

MAINDEC-11-DXDZA

MAINDEC-11-DZDZB
Staggered Turnaround

DIGITAL

H3271* or H3190
|

Connector
*H327 may be used in place of H3271.

5-1

DZ11 MAINTENANCE SOFTWARE

5.4

The DZ11 makes use of three different software packages which diagnose problems at the module
level; verify operation at the system level; and verify operation over a communication’s network channel. This software includes:

1. The DZ11 diagnostic (MAINDEC-11-DZDZA)

2. ‘The DZ11 system software exerciser module (MAINDEC-11-DXDZA)
The interprocessor test program (ITEP) overlay (MAINDEC-11-DZDZB).
3.

5.5

CORRECTIVE MAINTENANCE

The corrective maintenance procedures are designed to aid the maintenance technician in isolating and
repairing faults within the DZ11 module. The technician must therefore be equipped to determine that
o
S
|
the DZl is, in fact, at fault
The dragnostrc programs comprlse the basic tool used by the techmclan to isolate faults. The diagnostics exercise the DZ11 in four distinct maintenance modes and provide printouts indicating the results.
The printouts pointthe technician to a particular logic area. The technician then uses standard test
equ1pment (osc1lloscope and probe) to further isolate the fault to a specific 01rcu1t component..

AW~

The four maintenance modes are:
Internal Loopback
" Staggered Loopback
~ External (EIA only)
| On-Llne w1th Termmal
~

5.5.1 Internal Loopback Mode

Thismodeis run first because it is the simplest. Bit 03 of the control and status register (CSR)is set.
The output serial data from the UARTS are turned around into their respective serial data inputs. All
~ lines are turned around 51multaneously, but bypass the EIA level converters (or 20 mA loop c1rcu1ts)
5.5.2

Staggered Loopback Mode

This mode utilizes test connector H3271* for the EIA version, or H3190 for the 20 mA loop version.
The staggered loopbackis desrgned to test the output level converters (EIA) and to check all UART
parameters.

When the staggered loopback mode is run, bit 03 of the CSR must not be set. The lines are turned

around as follows: line O transmits to line 1, line 1 transmits to line 0. The remaining lines are s1m11arly »
paired (1 ¢., lines 2 and 3 4 and 5, 6 and 7)

5.53 External Mode
|
This maintenance modeis usedin the EIA version only. An H315 or H325 loopback connector is
attached to the customer end of the BCO5D cable that originates at the distribution panel

When exercising the external mode, the lines are run to the point where the customer or user connects.
55.4

On-Line with Terminal

During this test, a 20 mA or EIA terminalis connected to a smgle line on the distribution panel. All
lines are checked 1nd1v1dually by means of an ECHO test whichis part of the diagnostics.

*H327 may be used in place of H3271.

5-2

APPENDIX A

' DZ11 (M7814) TO AN ACTIVE DEVICE INSTALLATION

When a 20 mA DZ11 is used with another active device, two H319 current loop receivers must be used.
Figure A-1 provides an example of the connections involved when the DZ11 is used with another
active device, in this case another DZ11. A schematic of the H319 is shown in Figure A-2.

IIA"

llBIl

DZ211

H317F DISTRIBUTION PANEL

DZ11 “A"” REC -

DZ11 A" XMIT -

DZ11 “A” XMIT +

HORNSIEZ NN

DZ11 “A” REC +

H317F DISTRIBUTION PANEL

REC + DZ211 “B"

REC - D211 “B”

XMIT - DZ11 “B”

H319 INPUT

H318 OUTPUT

XMIT + D211 “B”

U—

(@)

=]
e

H319

10 FT. CABLE

BCO4R-XX CABLE

SUPPLIED WITH |

H319

- H319

il
11-5639

NOTE:

THE CABLE ATTACHED TO THE H319 SHOULD HAVE THE
CONNECTOR REMOVED AND RING LUGS ATTACHED TO THE
RED AND GREEN LEADS AS SHOWN.

THE BLACK AND WHITE LEADS IN THE H319 CABLE AND BCO4R CABLE
ARE NOT USED.

Figure A-1

DZ11 (M7814) to Active Device Connection

N @ ,

TL
~

BLK

3] s QW

~ -

WHT

| .m

Bl GRN

‘

@»

24V

Q2132

|4
TM

D664

. D664

D664
- D2
RL
~

RED

11-5640

Figure A-2

H319 Current Loop Receiver Schematic Diagram

A-2

APPENDIX
B

UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART)

The UART is a MOS/LSI device packaged in a 40-pin DIP. It is a complete subsystem that transmits
and transmitter can
and receives asynchronous data in duplex or half-duplex operation. The receiver
converts them to a
and
characters
binary
operate simultaneously. The transmitter accepts parallel
and converts
characters
binary
asynchronous
serial
serial asynchronous output. The receiver accepts
16 times the
be
must
and
separate
are
clocks
them to a parallel output. The receiver and transmitter
desired baud rate. The allowable clock rate is dc to 160 kHz.

Control bits are provided to select: character length of 5, 6, 7, or 8 bits (excluding parity), odd or even
parity; and one or two stop bits for 6-, 7-, or 8-bit characters. For 5-bit characters, 1 or 1-1/2 start bits
are used. The format of a typical input/output serial word is shown in Figure B-1. Both the receiver
and transmitter have double character buffering so that at least one complete character is always
available. A register is also provided to store control information.

le|
-

———— FIRST CHARACTER

DATA8 PARITY STOP1

'START DATA1 DATA2 DATA3 DATA4 DATAS DATA6 DATA7
| Lse

|| NEXT
CHARACTER

‘
|

MSB

START DATA1

STOP2

|
11-2205

Figure B-1 Format of Typical Input/ Output SflerialCharacterA block diagram and simplified timing diagram for the UART transmitter are shown in Figure B-2.
The transmitter data buffer (holding) register can be loaded with a character when the transmitter buffer empty (TBMT) line goes high. Loading is accomplished by generating a short negative pulse on
the data strobe (DS) line. The positive-going trailing edge of the DS pulse performs the load operation,
The character is automatically transferred to the UART transmitter shift register when this register
to the data and transmission begins.
becomes empty. The desired start, stop, and parity bits are added
One-sixteenth of a bit time before a complete character (including stop bits) has been transmitted, the
- end-of-character (EOC) line goes high and remains in this state until transmission of a new character
begins.

A block diagram and simplified timing diagram for the UART receiver are shown in Figure B-3. Serial
asynchronous data is sent to the serial input (SI) line. The UART searches for a high-to-low
(mark-to-space) transition on the SI line. If this transition is detected, the receiver looks for the center
If this point is low (space), the signal is assumed to be a valid
of the start bit as the first sampling point.
start bit and sampling continues at the center of the subsequent data and stop bits. The character is
assembled bit by bit in the receiver shift register in accordance with the control signals that determine
the number of data bits and stop bits and the type of parity, if selected. If parity is selected and does
not check, the receiver parity error (PER) line goes high. If the first stop bit is low, the framing error
(FER) line goes high. After the stop bit is sampled, the receiver transfers in parallel the contents of the

B-1

PARALLEL

DATA INPUT

(DB1—-DB8)

DATA STROBE (DS)

TRANSMITTER BUFFER

U EMPTY (TBMT)
START

STOP

ASYNCHRONOUS -

| '/f

DATA

SERIAL OUTPUT (SO)

START

‘l'QATA T

STOP

END OF CHARACTER
(EOC)

TRANSMITTER TIMING DIAGRAM-

"~ NO.STOP BITS—>p
EVEN

CONTROL
HOLDING
REGISTER

PAR. SEL.———»

NO PARITY——;:”-%
BITS/CHAR. =284

STROBE

TM GEN

25
_

SERIAL
OUTPUT

END OF
» CHARACTER

CONTROL

. OUTPUT
LOGIC

33
(BDO7 —»
BDO6 —»
31
BDOS ——»

DECODER

BDO4 —
DATA |
29
BITS
BDO3 —»

(EOC)

XMTR
SHIFT
REGISTER

XMTR
HOLDING
REGISTER

"+ DATA STROBE

LOAD

‘

TBMTF/F

CLOCK

40
INPUT —»

SHIFT
o2 TRANSMITTER
-+ BUFFER
EMPTY

TIMING
GENERATOR

11-2207

Fig.B-2° UART Transmitter Block Diagram ‘ayrnd _Sfimpli:fied~ Timing Diagram

' BDO1 —»
LBDOO—-'-—.

START

SERIAL INPUT (SI)

RECEIVED

START

DATA

| [,/I

pATA

ASYNCHONOUS

STOP

DATA

AVAILABLE (DA)

PARALLEL DATA OUT
(RD1-RD8)
RESET DATA

AVAILABLE(RDA)

RECEIVER

TIMING DIAGRAM
11-2209

BDOT.

~ DATA BITS

OVERRUN

REC
PARITY
ERROR

REC DATA
AVAILABLE

FRAMING
ERROR

STATUS

14 WORD

ENB
16

AND GATES

BDOO

‘

Errrrrtrges

REC

DATA

ENABLE

——

AND GATES

RESET

DATA‘—-JEP R

AVAIABLE

cLock

INPUT

»g
—

‘

OVERRUN

lc
1

DATA HOLDING REGISTER

SERIAL
DATA
INPUT

PARITY

[

RAME

RECEIVER SHIFT REGISTER

17,

CONTROL LOGIC

VT39

T35

EVEN
PARITY
SELECT

NO
PARITY

DATA AVAILABLE
—

T37

PARITY ERROR
VT

Tse

NB2
NB1
NUMBER OF
BITS/CHARACTER
i1-2208

Figure B-3

UART Receiver Block Diagram and Simplified Timing Diagram

B-3

receiver shift register into the receiver data buffer (holding) register. The receiver then sets the received
data available (DA) line and transfers the state of the framing error and parity error to the status
holding register. When the DZ11 accepts the receiver output, it drives the reset data available (RDA)
line low, which clears the DA line. If this lineis not reset before a new characteris transferred to the
receiver holding reglster the overrun (OR) line goes high andis held there until the next characteris
loaded into the receiver holding reglster

Figure B-4 is a pin/signal designation diagram for the UART. The function of each signal is given in
Table B-1. In the Function column, the references to hlgh and low signals are with respect to the pins
on the UART. This informationis used during servicing of the device. Programmers should refer to
the DZ11 register descriptions (Chapter 3) for information concerning the function of these signals.

19
DA — RECEIVE DATA AVAILABLE
15
OR —# OVERRUN

RESET DATA AVAILABLE »——Q RDA
16

SATUS WORD ENABLE ——0O SWE

FER ———= FRAMING

RECEIVED DATA ENABLE »—O RDE

RECEIVER CLOCK ~»—
| RCP
20

SERIAL INPUT —»——

r‘.

DATA BIT INPUTS
_

—>———

————

‘\—.h—————

23
DATA STROBE —”-—-—00
4

TRANSMITTER CLOCK —#—

ERROR

PER —— RECEIVE PARITY ERROR

RD8

DB8
DB7

RD7

DB6

RD6

DB5

RD5

DB4

RD4

DB3

RD3

DB2

RD2

RD!

gRECElVED DATA BITS

SO —2—2—> SERIAL OUTPUT
DS

TBMT ———— TRANSMITTER BUFFER EMPTY
24
EOC — END OF CHARACTER

TCP

XR CS NB2NB1 NP PE2 SB
37 38

39 |36

NOTE:

Pini=+5V
Pin2=-12V
Pin 3= GROUND

NO PARITY —&
PARITY SELECT

TWO STOP BITS
11-2214

Figure B-4

UART Signal/Pin Designations

B-4

NO.OF BITS PER CHAR{

CONTROL STROBE

|21
EXTERNAL RESET

Table B-1

UART Signal Functions

Pin No.

Mnemonic

Name

5-12

RDI1-RD38

Received Data

Function

Eight data out lines that can be wire

ORed. RDS (pin 5) is the MSB and
RD1 (pin 12) is the LSB. When 5-, 6-,
or 7-bit character is selected, the most
significant unused bits are low. Character 1s right justified into the least significant bits.
13

PER

Receive Parity Error

Goes high if the received character
parity does not agree with the selected
parity.

FER

Framing Error

Goes high if the received character has
no valid stop bit.

Overrun

Goes high if the previously received
character is not read (DA line not reset) before the present character is
transferred to the receiver holding register.

SWE

Status Word Enable

When low, places the status word bits
(PE, OR, TBMT, FE, and DA) on the
output lines.

RCP

Receiver Clock

Input for an external clock whose fre-

quency must be 16 times the desired
" receiver baud rate.

RDA

Reset Data Available

When low, resets the received data
available (DA) line.

Received Data Available

Goes high when an entire character
has been received and transferred to
the receiver holding register.

Serial Input

Input for serial asynchronous data.

- External Reset

After power is turned on, this line
- should be pulsed high which resets all
registers, sets serial output line high,
sets end of character line high, and
sets transmitter buffer empty line
high.

- TBMT

Transmitter Buffer Empty

B-5

Goes high when the transmitter data
holding register may be loaded with
another character

Table B-1

UART Signal Functions (Cont)

Pin No.

Mnemonic

Name

Function

Data strobe

Pulsed low to load the data bits into
the transmitter data holding register
during the positive-going trailing edge
of the pulse.

EOC

End of Character

Goes high each time a full character,
including stop bits, is transmitted. It
remains high until transmission of the
next character starts. This is defined
as the mark (high) to space (low) transition of the start bit. This line remains high when no data is being
transmitted. When full speed transmission occurs, this lead goes high for
- 1/16 bit time at the end of each character.

Serial Output

Output for transmitted character in
serial asynchronous format. A mark is
high and a space is low. Remains high

‘when no data is being transmitted.

26-33

DB1-DBS

- Data Input

Eight parallel data in lines. DB8 (pin

'33) is the MSB and DB (pin 26) is the
LSB. If 5-, 6-, or 7-bit characters are
selected, the least significant bits are
used.

When high, places the control bits

Control Strobe

(POE, NP, SB, NB1 and NB2) into
the control bit holding register.
35

No Parity

2SB

Two Stop Bits

- When high, eliminates the parity bit
from the transmitted and received
character and drives the received parity error (PER) line low. As a result,
the receiver does not check parity on
reception and during transmission the
stop bits immediately follow the last
data bit.
Selects the number of stop bits that
immediately follow the parity bit. A
low inserts 1 stop bit and a high inserts 2 stop bits.

B-6

Table B-1

UART Signal Functions (Cont)

Name

Function

37,38

NB2, NBI

Number of Bits per Character (Excluding Parity)

Selects 5, 6, 7, or 8 data bits per character as follows.

Bits

NB2

NBI

e WV,

Mnemonic

L
L
H

o B

Pin No.

L
H
L
H

Char

(37)

(38)

POE

Even Parity Select

Selects the type of parity to be added
during transmission and checked during reception. A low selects odd parity
and a high selects even parity.

TCP

Transmitter Clock

Input for an external clock whose frequency must be 16 times the desired
transmitter baud rate.

B-7

APPENDIX C

DUAL BAUD RATE GENERATQR (COM.5016)
The dual baud rate generator/programmable divider (COMS5016)is an) N- channel MOS /LSI device

capable of generating 32 externally selectable frequencies from either an on-chip oscillator or an external input frequency. The unit generates 16 synchronous/asynchronous frequencies as shownin Table
C-1. Four address inputs select one of 16 independent receiver or transmitter frequencies (Figure C-1).

The dual baud rate generator is essentially a programmable 15-stage feedback register. An internal
reprogrammable ROM permits the generation of the frequency scheme from an internal crystal clock
or via an external input frequency. Address inputs may be strobed or dc loaded. Full duplex (mdependent receive and transmit frequencies) operatlon is possible with the COM5016

Utilization of one of the frequency outputs permits generatlon of additional lelSlOIlS of the master
clock frequency by cascading COMS5016s. This may be accomphshed by feeding frequency outputs
into the XTAL/EXT input on a subsequent dev1ce

The COM5016 may be driven either by an external crystal or TTL loglc level inputs. COM5016 pin
assignments are shownin Figure C-2; pin functions are describedin Table C-2.

STT -

o>
B

.Tb >

]

‘

D— LATCH

controt

REPROGRAMMABLE

FREQUENCY SELECT

ROM

DIVIDER

22—y

DIVIDER

XTAL/EXT: >——
OSCILLATOR

XTAL/EXT: >——

R >

Ry >
R,
RD

D-LATCH

>____

STR )

—

ey
AND

—

CONTROL

REPROGRAMMABLE
FREQUENCY S ELEC T

ROM

+5V

GND

+12V

J
Figure C-1

|—=fg

11-4406

Dual Baud Rate Generator Block Diagram

- C-1

Table C-1

Dual Baud Rate Generator Address/Frequency Assignments

Transmit/Receive

~Address

0
{0 {1
0O
|1
|0
0
|1
1
1
10
|0
1
10
|1
1
1
10
1
1
1
010
|0
0
10
|1
0|1
|0
O
|1
|1
1
10
J0
1
1
1

10
1
1

Baud

|Rate

Theoretical |
| Frequency

Actual
Frequency

16X Clock

(kHz)

50 | 08

0.8

75
1.2
110
1.76
1345 |
2.152
150
24
300
4.8
- 600
9.6
1200
19.2
1800
28.8
| 2000
32.0
2400
38.4
3600
| 57.6
| 4800
76.8

7200

9600

(19200

1.2
1.76
2.1523
2.4
4.8
9.6
- 19.2
28.8
32.081
38.4
57.6
76.8

|115.2
153.6
307.2

115.2
153.6
316.8

Duty

Percent

Error

0.016

|
|
0.253

50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50

4224
2880
2355
2112
1056
528
264
176
158
132
88
66

50/50

44
33
16

48 /52
3.125

+5v 2]

17 f;

fr 3]

J16 T,

R, 4]

115 Tg

Rg 5

14 T,

R, 6

113 1,

Rp 7]

J12 STT

STR 8]

]11 GND

+2v 9]

110 NC

Divisor

50/50 | 6336

XTAL /EXT 4 1] U 118 XTAL/EXT2

11-4405

Figure C-2

Cycle

(%)

COMS5016 Pin Assignments

50/50

Table C-2

Dual Baud Rate Generator Pin Functions

Pin No.

Symbol

Name

Function

XTAL/EXT1

|Crystal or External Input 1

This input is either one pin of the crystal package or one polarity of the external input.

Vee

Power Supply

+5V supply

Receiver Output Frequency

This output runs at a frequency as selected by the receiver address

4-7

Ra, Rp, R, Rp| Receiver Address

The logic level on these inputs, as

Te-

shown in Table C-1, selects the receiver output frequency, fg
8

STR

Strobe-Receiver Address

A high-level input strobe loads the re-

ceiver address (Ra, Rg, Rc, Rp) into
the receiver address register. This input may be strobed or hard wired to a
high level.

VpD

Power Supply

+12 V supply

No Connection

GND

Ground

STT

Strobe-Transmitter Address

Ground
| "~ A high-level input strobe loads the
transmitter (Ta, T, Tc, Tp) into the
transmitter address register. This input may be strobed or hard wired to a
high level.

13-16

Tp, Tc, T,

To | Transmitter Address

The logic level on these inputs, as

shown in Table C-1 selects the transmitter output frequency, fr.

Transmitter

Output

Fre-

quency

This output runs at a frequency as se-

lected by the transmitter address.

XTAL/ EXT?2

Crystal or External Input 2

This input is either the other pin of the
crystal package or the other polarity
of the external input.

C-3

APPENDIX D
INTEGRATED CIRCUITS
The following pages contain reference information for integrated circuits used within the DZ11. Logic
diagrams and truth tables (where applicable) are shown. In some cases a pictorial of the chip with pin
designations is provided. The integrated circuits in this appendix are listed below:
3341
8136
8641
8647
9318
9602
74LS74
741590
74LS138
74LS151
7415153
74LS155
74LS157
74LS175
7415193
74L.S259

3341 FIFO SERIAL MEMORY

LOGIC BLOCK DIAGRAM
g

— |§LFU°T

62 WORD x 4 BIT

STAGE

—

MAIN REGISTER

7
Dy —&

, 05}';&

STAGE

INPUT READY <>

> SHIFT OUT

LOGIC

[

o g,

10
— Q3

SHIFT IN

> Q4
|

]

LOGIC

]

Vgg=PIN 16

OUTPUT READY

’

Vpp=PIN 8

MASTER

RESET

Vgg=PIN i

PIN CONFIGURATION

LOGIC SYMBOL

| SHIETL

2 —] INPUT

(TOP VIEW)

3 —sHiFTin
|

OUTPUT
READY L

SHIFT IN[] 3

3341

4 —| g

s —] py
6 —|0

INPUT READY [} 2

Qo — 13

127

[]e

1[ja

H ez

D3 : 7

10 j Q3

Voo [] 8

o [] MR

7 — D3

Qo
13[]

QF—1n

14 [7] OUTPUT READY

Do []4
Do

Qy b— 12

16 [] v‘ss |
15 ] SHIFT OUT

—

Q3 |— 10
MASTER RESET

Te
Vgg = PIN 16 +5V
VDD:= PIN 8 GND
1

-12V

Vgg= PIN

D-2

8136 6-BIT, UNIFIED-BUS COMPARATOR

| The 8136 compares two bmary words (from 2 to 6 bltsin length) and 1nd1cates matchmg bit-for-bit of
‘the two words. Inputs for one word are TTL, while those of the second word are high impedance
receivers driven by a terminated data bus; The transfer of information to the output occurs as long as

the STB input is logic 0. Inputs may be changed whlle the STB 1nput is at the loglc 1 level without
|

affecting the state of the output.

}

Vee = (16)
GND=(8) .

STB

R=H1-Z

BUS RECEIVER
.

IC-8136

D-3

8641
QUAD BUS TRANSCEIVER
|
.
|
The 8641 consists of four identical receiver/drivers and a single enabling gate in one package for
interfacing with the PDP-11 Unibus. The transceiver drivers are enabled when ENABLE A and
ENABLE B are both low. The other input of each driver is connected to the data to be sent to the

Unibus. For example, when enabled, DATA
IN 1 (pin 2) is read to the Unibus via BUS 1 (pin 1).
During a write operation, data comes from the Unibus as BUS 1 (pin 1) and is passed through the
receiver to the device as DATA OUT 1 (pin 3).

BUS 1 1

BUS 2 —2
]

12 baTA OUT 4

DATA INl—i—
DATA OUT1 2

DATA IN 2 2
DATAOUT 28 |

8641

DATA OUT 3

GROUND °

ENABLEB

[
o

—_—

DATA IN 11—

ENABLE A:D_

ENABLE B—

—

BUS
1

~_~ |

‘

DATA OUT
1

|
IC-8641

D-4

BUS 4.
DATA IN 4

BUS 3
A DATAIN3

ENABLE A L

—_—

Vee

8647 UNIBUS CHIP

8647

—1l

BUSY c}fila——4

_—'O
3

sTEAL GRANT L (03

GRANT

STEAL

(06)

GRANT
C

BUS BG/NPG

(NPR)

OUT H

=e
14

—QO) sSYN

BSACK [O—
A

INTR

MASTER [D—

ouT O‘_

;

BUS NPR L .

04)

REQ

STEAL

DONE
.

SACK

—Q) REQ IN
—

5
(12)

REQUEST L

i§§

(01)

r——o__J ‘

TAKE

(07)

GRANT
cC

(BR)

—(

)

GND PIN 8

CLREN

?‘5

PIN CONNECTION DIAGRAM

— Ve

BUS SSYN L — 2

— CLRSACKENBL

REQUEST
L —

STEAL GRANT
L —

BUS NPR L — 4

BUSBG/NPGINH —

BUS BG/NPG OUTH — 6

SACK

{>‘;,L

VCC PIN 16

CLR

BUS SACK L

BUS BR/NPR L

BUS BG/NPG IN H {22

SACK

SACHK
'

BG OUT

BG IN

BUS SACK L —

GND — 8

14 — MASTER CLR H

— INIT
H

12 -— SACKH
11

— MASTER L

10 — BUS BBSY L

9 — BUS BR/NPR L

(1) MASTER L
(15)

CLR SACK ENB L

MASTER CLR H (14)

INITH

BUS SSYN L(fl——4>

TM
(10)
._.>
_>, _{ >o—1~—
-aus BBSY L
!

Pin8 = GND

Pin16 = V¢

(13)
1C-8647

‘

9318 PRIORITY ENCODER

The 9318 8-input priority encoder accepts data from eight active LOW inputs and provides a binary
representation on the three active LOW outputs. A priority is assigned to each input so that when two
or more inputs are simultaneously active, the input with the highest priority is represented on the
|

output, with input line 7 having the highest priority.

A HIGH on the Input Enable (EI) will force all outputs to the inactive (HIGH) state and allow new
|

data to settle wthout producing erroneous information at the outputs.

A Group Signal output (GS) and an Enable Output (EO) are provided with the three data outputs. The
GS is active level LOW when any input is LOW; this indicates when any input is active. The EO 1s
active level LOW when all inputs are HIGH. Using the output enable along with the input enable
allows priority encoding of N input signals. Both EO and GS are inactive HIGH when the input enable
i1s HIGH.

TRUTH

TABLE

———

—ee

p——

—

—_

—

|65

—o010

X|H

H
L

I’ q !

— <ol

13O 3

H|L

X
L

X
H

X
L

H
L

H
H

H|H
HIlL

H
L

H|L

H = HIGH Voltage Level
L’—;LOV\{ Voltage Level

HI|L

H
H

3318

AQjo——
7

At 06

A2 lO——

—Q4

245
3

—oO7

colo!®

GSIO——

Ts
GND=PIN

IC-9318

9602 MONOSTABLE MULTIVIBRATOR

+Vce

INPUT

OUTPUT

PIN NO.

'\llm

05/11

06/10

07/09

IL U

{

IL jup

H=HIGH LEVEL

04/12

L=LOW LEVEL
ey

+Vce

f=LOW TO HIGH TRANSITION

\\-:_-_«;v- -

$=HIGH TO LOW TRANSITION

"""

——

156

}—+

INPUTS

CLEAR
14

CLEAR[O—

}—

OUTPUTS

|—

——
11

}—

1C-9602

—JCLEAR

o\
INPUTS

}—

INPUTS

J
OUTPUTS

D-8

EEEE——
GND

INPUTS

Vee

74LS74 DUAL FLIP-FLOP

TRUTH TABLE FOR

7474 STANDARD CONFIGURATION
(EACH FLIP-FLOP)

tht1

Preset

Clear

Dinput

| 1Side

0 Side

High

Low

High

Pin 2(12)

Pin 1(13)

Pin 4(10)

High

X
X
X

Low
High
Low

High
Low
Low

Pin 6

Pin5

Low

High

High
Low
High

Low
High
High

tn = bit time before clock puise.
tn+1 = bit time after clock pulse.
X = irrelevant

REDIFINED CONFIGURATION

" STANDARD CONFIGURATION
PRESET
604 o
02

PRESET
401 oc
02

=
1,06

7474
03
—c

el
1 :Q5

7474

0
'———:”—C

olos

006_5—
Joa

Yo1

CLEAR

PRESET

PRESET
$13

CL1O

7474

|
09

109

7474

Mlc

0 065

A C

w2 D [

09
1|08

12
—p

Olfo9

T1o

113

CLEAR

.IC-7474

\olohi PIN 14

GND=PIN O7

NOTE

IC 7474 is shown. “LS” only signifies low-power Schottky.

D-9

74L.S90 DECADE COUNTER
|
The 741890 decade counter consists of four dual-rank, master-slave flip- flops 1nternally interconnected to provide a divide-by-two counter and a divide-by-five counter. Gated direct reset lines are
provided to inhibit count inputs and return all outputs to zero or to a binary coded decimal (BCD)
count of 9. As the output from flip-flop A is not internally connected to the succeeding stages the
count may be separatedin three independent count modes:

When used as a binary coded decimal decade counter, the CLKBO input must be externally

connected to the RO(1) output. The CLKO input receives the incoming count, and a count
sequence is obtained in accordance with the BCD count sequence truth table shown below.

If a symmetrical divide-by-ten count is desired, the R3(1) output must be externally con-

nected to the CLKO mput The input count is then applied at the CLKBO mput and a divideby-ten square wave i1s obtained at output RO(1).

For operation as a divide-by-two counter and a divide-by-five counter, no external interconnections are required. Flip-flop A is used as a binary element for the divide-by-two
function. The CLKBO input is used to obtain binary divide-by-five operation at the R1(1),
R2(1), and R3(1) outputs. In this mode, the two counters operate independently; however,
all four flip-flops are reset simultaneously.
|
TRUTH TABLES

7490

BCD COUNT SEQUENCE

‘

(See Note 1)

COUNT

R3(1)

R2(1)

RESET/COUNT (See Note 2)

QUTPUT
R1(1)

RG(1)

)

RESET INPUTS
-

‘

o6 | o7 | r3(1| m2t1) | R1(1) | RB(T)

——

F—

’ SET 29

—_—

06 —

R2(1)

P3 —
s

CLR

(1)

)

RO(1)

—

COUNT

‘
:

R3(1)

02 | 03 |

OUTPUT

COUNT

CLKB@

CLK®

‘

(12)
NOTES:

RA(1)
?

)

1. Qutput RB(1) connected to input CLKB@ for BCD

VCC=PIN@5

GND=PIN 1@

~(89)

(@8)

(11)

R1(1)
Q

R2(1)
Q

R3(1)
Q

count,

2. X indicates that either a logical 1 or a Ioglcal g

may be present.

NOTE

(14) CLK @

IC 7490 is shown.

“LS” only signifies

—1

—Q T

' (‘) .

S Qp

low-power Schottky.

(@6) H}

SET ) (87)

O—

{(@3)

o—

(@2) o—

(B1) CLKBg@

o©

)
D-10

IC-7490

741.S138 DECODER/DEMULTIPLEXER

7415138 |_ 15

0001—4

1 IseLA D1 0O—
13

—2 J1seL B D2|0—

3 lseLc p3pi=
11

D4[O0—

D5O£

pejO—>— 7

D7f

FUNCTION TABLE
INPUTS

OUTPUTS

SELECT

ENABLE

G2 | c

AlvYo Yi Y2 Y3 Ya Y5 Y6 Y7

X|H

H
H

HH H

HIH

HlH

H L

LIH

H|lH

L|H

HIH

H H
H

IC-74L.5138

D-11

VYY

741.S138 DECODER/DEMULTIPLEXER (Cont)

(14) y,

ENABLE
INPUTS

(13) .,

(4)
G2A=

‘

628

—O

12)
DATA

OUTPUTS

setect ) g2

—

INPUTS

(9)

(10)

* _)0-“

(7)

{){>

ve
Y7

DATA OUTPUTS

Vce

<.L»

Y6 O——-

‘

B
g
—
SELECT

G2A

G2B

628

G2B

—/

ENABLE

Y2
—/ OUTPUT

GND

74LS151 8-LINE-TO-1-LINE DATA SELECTOR/MULTIPLEXER

STROBE (7)

(ENABLE)

(4)

(Doc,L

D1O

—

(3)

5
outpuT Fr
)

(6)

- OUTPUT

Vee = PIN 16
GND=PIN
8

DATA

SELECT <

(BINARY)

(10)

>0——
_

IC-74151A

NOTE

IC 74151 is shown. “LS” only signifies low-power Schottky.

74LS151 8-LINE-TO-1-LINE DATA SELECTOR/MULTIPLEXER (Cont)

74151 TRUTH TABLE
Inputs

STB

When used to indicate an input, X

Outputs
D3

fo
|

irrelevant.

STB

74151

p— —

6
fO p—

]10

]11
IC-74151B

NOTE
|
IC 74151 is shown. “LS” only signifies low-power Schottky.

D-14

(1)
A0

(6)

‘

)

cBO

(5)

‘\

DATA1<

_J |
}

LG
LnDO

(3)

(7) fl)\

\,}

ADDRESS

(2)>

SO (14) >°—\‘OD

(G‘m

(10)

> OUTPUTS

_‘

‘\

DATA2< o (12)

QE (13)

STROBE 1

{

(15)

(ENABLE)

L—/

GND = PIN 08

]

"
o

ADDRESS
INPUTS

X
L
L

X
L
H

L
H

H
L

H
H

DATA INPUTS

X
L

X
X

STROBE

STB

:
OUTPUT

H
L

L
L

H
X

X
L

X
X

L
L

H
L

X
X

L
L

L
H

)

X
X

X
L
H

(L(J‘!

STB1

STBO

12 D1
11

X
X

J;S

’

CC=PIN 16

74153

' 05 Cco

E09

SECTIONS ' H=HIGH LEVEL, L=LOW LEVEL , X= IRRELEVANT.

A0
S1

ADDRESS INPUTS SO AND S1 ARE COMMON TO BOTH

— B1
10 Al

|02

|14
1C-74153

IC 74153 is shown. ‘“LS” only signifies low-power Schottky.
D-15

STROBE
16

DATA

S[o J : \ : !

741L.S155 DUAL 2-LINE-TO-4-LINE DECODER
{7) OUTPUT

(2)

(1)

1Yo

(6) QUTPUT

1Y
1

(5) QUTPUT

SELECT 1§L[:>x}
B

(4) QUTPUT

1Y3

(9) outpPuT
2Y0

seLecT (13)
A

10ouTtPUT
2Y1

(11) O%;E?T

DQEA (15)

STROBE (14)

[_—0———/

(12) ouTPUT
2Y3

IC-74155

FUNCTION TABLES
y\mz‘//

2-LINE-TO-4-LINE DECODER

OR 1-LINE-TO-4-LINE DEMULTIPLEXER
INPUTS

SELECT

STROBE

OUTPUTS

DATA

1Y0

1Y1

1Y2

1Y3

X
L
L
H
H
X

X
L
H
L
H
X

H
L
L
L
L
X

X
H
H
H
H
L

H
L
H
H
H
H

H
H
L
H
H
H

H
H
H
L
H
H

H
H
H
H
L
H

OUTPUTS

INPUTS
SELECT

STROBE

DATA

‘B

2Y0

2Y1

L
L
H
H
X

L
H
L
H
X

L
L
L
L
X

L
H
H
H
H

L
L
L
L
H

H
L
H
H
H

2Y2

H
H
L
H
H

ZYQ

H
H
H
L
H

NOTE

IC 74155 is shown. “LS” only signifies low-power Schottky.
D-16

741.S157 QUADRUPLE 2-LINE-TO-1-LINE MULTIPLEXER

A0
©

B0 O-

A1l O-

14
A2 O

12
O

B2
©

f2 -

A3 G-

B3 &

soo——Do—~
1

Vee = PIN 16

STB O-

GND =PIN 8

74157

INPUTS

STROBE | SELECT
f1

A1l

X X

L X

STB

?15

OUTPUT
| A B

H‘= HIGH LEVEL, L = LOW LEVEL,
X =IRRELEVANT
1C-74157

NOTE
IC 74157 is shown. “LS” only signifies low-power Schottky.

D-17

74LS175 QUAD D-TYPE EDGE-TRIGGERED FLIP-FLOP

TRUTH

TABLE

INPUT [ OUTPUTS

[R(1)R(O)

H
L

L
H

th =Bit time before
clock pulse.
th+1=Bit time after

clock

manf>Y

(4)

DO o

R3(0)
F2
W

Loz
1

—

———QICLK

renf>
1

74175
D1

(5)
Dio

R1(O) —

(7)

()

QICLK (0)

‘

(6)

CLEAR

CLK
|

rR1}
D1

R1}

RO(1)—2—-

CLR

RO{ (3)
(o)F—>

} QUTPUTS

(2)

R1(1) }—

| — DO

ROf

POy

—

]9
|

p2 o2

D2 (’?12)-(—93
1

R2
—QICLK (o)r—o°

CLEAR

(13)

D3 o

R3{

(1)

(15)

CLOCK

—QICLK (0)—>°
CLEAR

CLEAR

;

Pin (16)= V¢,

Pin (8)=GND

IC-741758

NOTE
|
IC 74175 is shown. “LS” only signifies low-power Schottky. -

\\.w—/'/

[ Blos

puise.

7415193 4-BIT BINARY COUNTER
(13) o
V.~

BORROW

OUTPUT

=PIN 16

GND = PIN 8

(12)

_ CARRY
OUTPUT

DATA

(15)

INPUT A

DOWN

(4)

COUNT

UP
COUNT

DATA

(5).

>0
>0

PRESET

(3)

Q,
OUTPUT

aal

CLEAR

(1)

B
INPUT

PRESET

(2]

-QrT
agl—

CLEAR

DATA

ci 10)

INPUT
C

PRESET]

[—

Qc | —

T
'

OUTPUT Q,,

Qc L

CLEAR

DATA

(9)

TM7

INPUT D

(14)

CLEAR O—

LOAD

NOTE
IC 74193 is shown. “LS” only signifies low-power Schottky.
D-19

‘

O OUTPUT Q

1C-74193 A

DZ11 ASYNCHRONOUS MULTIPLEXER

)

Reader’s Comments

TECHNICAL MANUAL
EK-DZ110-TM-002

Your comments and suggestions will help us in our continuous effort to improve the quality and usefulness of our
publications.

What is your general reaction to this manual? In your judgment is it complete, accurate, well organized, well
written, etc.? Is it easy to use?

What features are most useful?

What faults or errors have you found in the manual?

Does this manual satisfy the need you think it was intended to satisfy?
Does it satisfy your needs?

Why?

Please send me the current copy of the Technical Documentation Catalog, Wthh contams mformatlon on
the remainder of DIGITAL’s technical documentation.

Name

Title

Street .
"

Company ______
Department
A

City

State/Country
Zip

Additional copies of this document are available from:
Digital Equipment Corporation
444 Whitney Street
Northboro, Ma 01532
Attention: Communications Services (NR2/ M15)

B
Order No.

Customer Services Sectlon

EK-DZ110-TM-002

FIRST CLASS
PERMIT NO. 33

MAYNARD, MASS.

BUSINESS REPLY MAIL
NO POSTAGE STAMP NECESSARY lF MAILED lN THE UNITED STATES

Postage will be pald by:

Digital Equipment Corporation

Technical Documentation Department
Maynard, Massachusetts 01754

dlifgliltiall
digital equipment corporation

Printed

U.S.A.