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EK-DYS50-TM-001

January 1983

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Document:	DYS50 Technical Manual
Order Number:	EK-DYS50-TM
Revision:	001
Pages:	164
Original Filename:

OCR Text

EK-DYS50-TM-001

DYS50
Technical Manual

Prepared by Educational Services
of

Digital Equipment Corporation

l1st

The

reproduction

Digital
Rights

Edition,

Equipment

January

Corporation

Reserved

this

material,

part

whole,

is
strictly
prohibited.
For
copy
information, contact the Educational Services
Department,
Digital
Equipment
Corporation,

Maynard,

Massachusetts

@1754.

The
information
in
this document
is
change
without
notice.
Digital
Corporation
errors

assumes

that may

appear

Printed

Mate-N-Lok

subject
to
Equipment
responsibility
for
any
this

trademark

document.

U.S.A.

AMP,

Inc.

The following are trademarks of Digital
Corporation, Maynard, Massachusetts.

Efl@flflflfl

DECwriter

Equipment

RSTS

DECdataway

DIBOL

DECsystem-10

MASSBUS

UNIBUS

DECSYSTEM-20

PDP

VAX

DECmate

Professional

DECnet

Rainbow

Work

DECUS

RSX

P/0OS

VMS
-

Processor

1983

CONTENTS

PREFACE

1-1
1-2
1-2
1-3

MSV11-PK Memory (M8B8O67-KA) ..cceeeeecceces ceees
ISV11-B DECdataway Interface ..... .

1=-3

N
N

o
s
P

> w N
S o

»
e
e

B WW WM
PR

1-3
1-3
1-3
1-6
1-7

1L=10
1-11

INSTALLATION

Introduction ...c.cceceee.. cececscacne ctesecccsesan .
Site Preparation .....ceccecececes ceescsccssecanse cess
Site Power Requirements ...... ceescsascsccsese

[

R HEHRERHERREOO0O0OONNAATBRWWWWWNDNNDH

@
o
o
o
¢
¢
¢

Definition and Scope ...... ceeescsssensne ceccscass
IntrodUCtiOoN .eceecececososoccscsccccscsacscscscsss
Features ...eceececceccee ceesccssececs cecessscscscaes
KDF11-BB Processor (M8189) ...c.cececcecccacs

Related DoCUMENtS ceceeeesecssocsscccccocccscsass
Specifications ...ceececcccccccacscacs ceecessesans

o
o
0
o
°
o
6
o
e
o
®

INTRODUCTION

BAl1l-Y Mounting BOX cececeeccccccccccce ceesans
General Description ..eccecececccceccccces cececeene
DY SYSLEMS .icvetecccocccecosocscsoaccasssssse
DYS50 Functional Description ...... ceeccsesess
Typical DYS50 Cabinet Configurations ........cco0.

CHAPTER
NN NMNNONNNNODNNNNNONNNODNDNNONNNDNNODNNDNNNNNNODNNNNODNON

> w N
N

°
*

i
s
o

o
o
o

el e

o
8

e
o
o
¢

NonmdbhbddbwWwwwwwh
-

CHAPTER

NEMA Enclosure Requirements .....ccceecceccccs
DYS50 Unpacking and Inspection .......... cecesces
Factory Configured Units .......c0.... cececas
Unpacking .eceecececsesecceenceoccscnnaseas
INSPECtiON c.cececcesecasccecacssacssenes

Separate UnitS .ceceeeceeeccecccccasonsansseaas
DYS50 Switches and IndicatorsS .c.ceececcecescccesees
Preliminary Configuration ......ccecececcccncaeas
Mounting the DYS50 ..ceeeececccccccancsccascsaces
Non-standard Enclosure Mounting ...ccceceee..
Standard Cabinet MoUnting .c.ceeceececececcesces
Cabinet AC Power CheCK ..eccecsecoasccsccocsecsnss
DC Voltage Measurement ..c.cceeeececcecsccaascsces
Measurement Of +5 VAC .eeeeeeecccocannsecscss
Measurement Of 412 VAC ceeeecsosccssccccesess
Of f-Dataway Operation ...eecceccececscccccssasess
DYS50 to DECdataway Interface ...ceeecececcceccoces

On-Dataway Operation ....ceceeceececcccccccaccsces
DYS50 Peripheral Interfaces ....cceeeceeccscccsces
Standard INterfaces ...ceccesscscecscccccsces
Filtered Interfaces ..cccececececcecsssccccssccses
H349 Distribution Panel ...ceeceecccsccscsass
DYS50 to I/0 Subsystem Interface ............
Expanding an Existing System .....cccccccccenccecs
Adding New ModulesS ..cececcsccocscccccoscccos
Adding an Expansion Chassis ..... ceccscscsses
Performance Verification .c.eceeccececcccccsccseass

iii

2-1
2-1
2-=1
2-3
2=3
2-3
2-3
2-4

2-5
2-9
2-12
2-14
2-14
2-14
2-18
2—18
2-18
2-19
2-19
2-20

2-20
2-20
2-20
2-21
2-21
2-23
2-23
2-24
2-=24
2—24

MAINTENANCE

3.1

OVEerVIeW

3.2
3.2.1
3.2.1.1

Troubleshooting
Maintenance

ticeeeeecccceccocncncan cececsescsnseenne .

TOOLS ..eceeeceercccecoscoscacoses
Software (DiagnosticCsS)
ceeeeeece..
Level DiagnosStiCS ceceecececececsan

Standalone

3.2.2

DiagnoSticCS veeeeeeeeceoocceses
TroublesShoOting ....eeseeeeeeocncess
DiagnosSticCsS ..eeeeeeeeeeecaccanceess

Hardware
Built-in

3.2.3
3.2.3.1

Hardcore

TesStS

3.2.3.2

Softcore

TestsS

3.2.4

.civeeereccecccccocccososs

ceeeeecececenns ceecccsscsace
.ieeeeeecececceooeccscscasnss
Troubleshooting Flowchart .....c..cecess.

ISV11

3.2.5

INAdicatorsS

DYS50

3.3

ISV11-B

TroubleshoOOtinNg

3.4

Routine

MaintenancCe

3.5

Unit

Removal

and

e..ceeeececececceocccancnsse
......eeeeeeeeeecececoconaees

Replacement

...ceeeeeeeocesoccass

3.5.1

Replacement

3.5.2

Module

3.5.3
3.5.4

Fan Removal and Replacement ....cceceececcoecse
Power Supply Removal and Replacement ........

3.5.5

the

Insertion

BAll-Y

and

ISV11-B

DESCRIPTION

.3.1

.3.2
.3.2.1

DECdataway

e3.2.2

DECdataway Controller
DECdataway Connectors

System Communication

DECdataway

LSI-11

ISV11-B

Operation

N
N

.tuiieeeeececcececnsncacnsnes

SoOftcore

TeStS

c.ceeeccececcsceccoccoccnes

POINtS

[]

.ceeeeecerccececenncnnns

TestS

M8080

ceeeeecccccacecccccccccocses
.eeeeeeeeeeceeccsseoconcccesns

Diagnostics

INAicatorsS

...ceceeeceeses

....eeeeecececees

Hardcore

ISV1I1

TeSt

Interface

...eeececes

.eceeeeeocccoees

MaintenanCe

ISVI11-B

T N

ISV11-B

ISV1I1-B

the

MEMOYY

L]
°

[

and

Built-In

[]

TM w N

Processor

ISVI1-B
W wWwwN

Description

ISV11-B

(ISBll)
....eeceeeen
....... sesecsesenes

DECdataway TerminatorS e..eeceeceecoasocsee
Remote DeviCesS .ieeeececccsncecccesns
TYPICAl DIS
i eeeeeocessccocccnonnacnes

Functional

[
L]

Y -

[]
]

St T

[]

....ceececececes

System

.3.3.1

Link

........ ceccccsseessscas

ceieeeeeeeeececeeanccosoceses

tiieieeeeceesceeccecccoconsooncnncses

Test

Point Description ......cee.e.
M8084 Test Point Description .e..eeeeeess
Module Troubleshooting ......eeeeeeeoccacnnes

Cable

QY S

.3.2.4

Host

......... cecessenn ceceesccsrann
........ ceeccscccsesee cececsnas

System

.3.2.3

.3.3

System

...ccecececceccccccecses ceene

Typical

N
I

NG SO O

...... cecsane Cececccecssecsessnaccans

Application

L L
LA L R R
O R N R
R TR TR T T T
N0V OIANAANAAARA DB D BB WWWWWNN

Introduction
ISV11-B

]

1t eeereeeeceecanooooesscsannnsss

ceeececoccaccss
....ceeceecocess

Module Replacement (Bezel)
.e.eeeecees
Backplane Replacement ...cceeeececccccccccces
Voltage Measurement and Adjustment ......cc...
Measurement .......ccecececccccncccccccccccscs
AQJUSEMENT

CHAPTER

BOX

Removal

(1SN LT
T S

3.6.2

ULV
BB BRWWWWWWWWWN

Control

3.5.6
3.6
3.6.1

AL LI N A
T
R
N
R T
A
T
'
HRWOOII
b
b dwWwWwwNNN

System

3.2.1.2

WWWWwWwuwwuwwwwww W

CHAPTER

....

4-17

4-19

4-21
4-21

4-26
®

Interrupt

TransSfersS

Control

4-28
4-28

FlOWS ...ceeceees cercessecccssesceceae
Specifications ..c.ceceecececcces cecerccesscsncsecne
ISV11-B Signal GloSSAry .eeceeee.-. cescsccessescceecse

4-37

SYSTEM DESCRIPTION

Assembly

.c.iceeececccccccncscncs

Panel

Supply

Input

Power

. AC

Description

Input

H7861

[]

Circuit

+5 V- Control Circuit

+12

V Control

+12

V/+5

Circuit

Regulators

POK/DCOK Circuits
LTC

Generator

H9276 Backplane
w N

Extended LSI-11 Bus Signals
CD Bus Signals
Module Requirements for H9276
Capability
Modules Designed for the H9276
Only

Electrical Protection for
and Double-Height Module

5.2.3.5

Front

5.2.4

Bezel

Assembly

APPENDIX

DYS50

APPENDIX

SPECIAL CIRCUITS

DCPB3

KERNEL

SYSTEM CONFIGURATION

Interrupt

DC@@P4 I/0
DC@@5 Bus

Quad-Height

Control

Address Decoder
Transceiver

G, R NS |
B

Bezel

......

Front
AC

Supply

T, IV
B

Backplane

.
*

...c.ceeceecccses

H9276

Detailed
WWWWNONNDNN
NN

Panel

Power

Input

H7861

ol
oo B o T A

4-38

POWER

4-30

U\
S RO NG I
[

o
o
«

4-26
4-27

..eceececccscecccccsscsssscsscssocces

BAll-Y

)

Interface

4-14
4-15

4-18

Introduction

[
i

.
®

4-13
®

w N

[]
[]
[]

[]
[]

NNNNNONNNNNNNNND
P

Description

Backplane

W N

Problems

.ceceececcocceas e

Transfers

=
=

DMA

=
=
o)

Major

TeSt

W?JW

[]

]

W W 00~
WU Ul

NS
e
W N+

Bus

Port

ST N
[)

Y
L

Y
[]

S
[]

Y
[]

SN
[]

- T T

i
]

i
[]
*
L]

LSI-11

5.2.3.4

o w’

for

Modem

Processing Unit
Serial Line Unit
Serial Transmitter-Receiver
Transmitter
Receiver
Negative Voltage Converters

Functional

fa ot
o
o
o
o
o
L

o
o

Check

Detailed

LSI-11

ISV11-B

mmoumoTumuTonotupnotonutuLuotomy
o

Quick
Manual

(

FeatUreS ..cceccececccccccccccocses
DY SyStelm ..ceceeecececececs ceseccescsens
DYS50 .tieieeerecenocccscencccccccnscnnnss

Block Diagram ..eeecececccoccccceccccccocsse
H9646 Cabinet Configuration ....ceeeececcenccccss
H9646 Cabinet Configuration .....cceeeeeecocccess

H960@ Cabinet Configuration .....ceeeeeeccecocccss
H960 Cabinet Configuration .....ccceeeeecencocess
Site POWEY t.vteeeeeeceseososscoceacccocaoaoncsossnase

DYS50

and

ACCESSOrieS

MOAULES

..vievececcsscccccscccccccscoanscosss

REMOVAl

... ccececesccccscnccosccscoocccsocccss

DYS50
Cover

Switches

COVEY

..cieieeececcsccscccanansoas
..uieieeeesseccccacaccscconccconsecoes

Module

.iieeeeeeeeceeceocsancnoocsens ceecens

DYS50

Backplane

and

INAicCaAtOrS

....eeeeeeeecscoocconnnesns
.ueeeeecccccccsccscocsccconnsnccsses

Bezel

Standard

JUMPELS

(eeieeeeeccccccceccccocsoonoes

Mounting .eceeeecececcecceccees cecececccan
and POWEY ..ceeeeescscocscscccccccccesese

DECdataway

Filter
H349

........ cececesesessscssassensene

Panel
Interface

Subsystem

ISV1I1

DiSPlAGY

I/0

Placement

Distribution

DYS5@

Troubleshooting

AN TN

IR T

U WX

Front

JUMPEYS

NEMA MOUNtING teeeeeteecescceeccessoscccocoooncsss
Hinge Mounting ....ceceeeeeeenes ceecces ceesecseccas

DYS50 Chassis

..... cessesecsscsssssacene
...c.ceeieececccccccccacnes

ceeceeeeccsossesscceascscscccoccccccesee
...ceeeceeceecccocacanccces
.(ivieeeeceececoccconcconanse

RemMOVAl

Fan

[

Power

Front

Backplane

HHEOVONOOULID
WN

Replacement

Module

Replacement
Supply

Panel

.......... cscsene cececsssans ‘e

....ccceceeeee ceacsessessesensessnan

Replacement

Bezel

Module

Replacement

Voltage

ISV11-B
Bus

Single

)

PEPN®

Enclosure

AAJUSE

Option

Interface

.ecccceeccccess cececcccssne

Replacement

..ceceeeeeee

....ceeceeeccccccccccccccoss

teeeeeeeocecesoscecccccccccccses
DECdataway

LSI-11

.cccceeccecee ceesceccsccsesssscsscas

Typical DY SyStem ..cceceesscccescccccocccaccnns
DIS with ISV11-B Interface ....eeeecececececcconses
ISV1]

DiSPlaAY

ISV11-B
MBUBO

ceeceeccessccocccsocccccscocscscssces

Modules

(EAGe=0N)

eeeeeececococcocosscnsccaes

MOAULE

.iveeesccecescccnsscccncsccnccnccnsse

M8084 Module

....c... cecscon Sececcrssesssscrccscns

ISV11-B

Logical

Transmitter

Receiver
Receiver

Organization

Timing

...c.ececececcocccens

..c.eeeccececeececccecconocsens

Simplified Block Diagram ....eeeeeeeeess
TiMing ...eeceeeeeceececceeocaoccsoscencss

el
el el
IT T
T
N R I T
I T
U1
WNWOROINUITNWYW OO O

DYS50

Basic
DYS50

Typical

*® ® o & © & & o & o o ® & & © o O & O & O O O S O O O O O & O O O OO S OO s

BWWWWWWWWWNNNDNONNNDNDNNNNDMDNDNOND NN

AND MODULE CONFIGURATION

Single-Backplane Configuration RulesS .....ececee..
Multiple-Backplane Configuration RuleS .....eoc..

Q
c
s

Qa0

w N+

General

[

HOONOAUIBWNFHFHPRBEIREMERFEREQQO-JO
U B W NHWOWONONUId
WN

—

PDP-11/23B BACKPLANE

NNNNON
P
NN
R
=

APPENDIX C

DMA
LLSI

Interrupt

N TR

TR N

BN B

H=YooOJgoOuTbdWNH

ISV11-B

OUt ....ccccecoceccssccssccscccccsccsns
IN ceccecescescoccccsscsssscscccccsccescs

Transfer
TransSfer

DMA

vououutuiunuouot

OUt .cecceeescscccscccscoscsscsacncncscssos
IN cccececesesocccccsccccnas ceescssocss

Line
Line

Serial
Serial

Interrupt Request to LSI-11l ...ceccceccescn

.ccccccecccsccccccccccccnce

Request

BAll-Y Major AssemblieS ..cccececsscccccccncccccncs
BAll-Y Functional Block Diagram ...... ceesscccnne
BAll-Y Interconnections ..cccececececcseccssccsccons
AC Input SchematiC ..cceecccccsccccccccncccccccns
H7861 Block Diagram .eceeececoccccsccccccsccsccces
Inverter Circuit .ecceeceeccecsccceccccccsccsncssssasns

Current/Voltage Relationship in T3

...ccceccccees

+5 V Control Circult ..ceecececcccescsccsnccaccans
3524 IC Block Diagram .cecceecececccccccscsnscccscsoces

Timing,

+5 V Control Circuit

..ccceccccceccccenes

Timing,

V Control Circuit
+12

...ecececcccccececs.

+12 V Control Circuit ..ceceeeececcscccccscccccccas
es
Block Diagram, NE555 ..... ceccesessssceecesse
412
+5

V
V

Regulator
Regulator

....... cecncocns cesenrse cesssesssee
..ccecceceecocescsoscscccccsccccccncss

Power-Up/Power-Down Timing ....cccce.c.. ceecceacce
POK/DCOK CirCUitS ceseececceccccssacscscccsccscccns
DCOK Power-Up Timing ..ccceceeceescsccccs cesces ceee
Power-Down TiminNg c.ceceececccccccsceccscssccsscecs
LTC

Generator

H9276

.ccecececceccccsccccsssccscccecse secevee

Backplane

...ecceececccsccscsscsccccsccccocss

Interrupt Acknowledge and Bus Grant Signal

Interconnection, H9276 Backplane ....ceccccceececcse
CD Bus InterconnecCtioOnNsS ..ceeecccecceccocscscsccsns

H9276 Backplane Wiring

(Rows A and C)

ec.ccecccen

Front Panel LOGIC tcceeecccccccccccacessscccsccsscs
RUN Indicator WavefOorms ..cceccecccccccsoncccscccesc

DYS50 Kernel System Backplane Configuration .....
DYS50 Bezel printed Circuit Board Factory
Configuration

ceeeeecececcccccccecccccsesaccssssnsns

Factory Configuration of the KDF1l1l-BB (M8189)

o ~Jo

ouluwmww
|I T

Sections A AGnNd B

..ceciecsccsccccscscssssscscccnscces

DCPP4 Simplified Logic Diagram .e.ceecececccccccccscs
DCOP4 Timing Diagram

...cccesecescecccccccccocssas

Timing Diagram

...ccceeccecccccoccccccscacssen

DC@PP4 Loading Configurations .......cccccccecccee
DCPP5 Simplified Logic Diagram ...cccccecceccccecse

DCPA5

PDP-11/23B

(H9276)

Configuration

Single Backplane

...ceeceeccccscccecccccccoreccccccn

vii

oUW
w N

DC@P3 Interrupt Section Timing Diagram ..........
DCPP3 Interrupt Section Timing Diagram

DCO@3 Simplified Logic Diagram ..ccececececceccccccs

ISV11-B M8¢88 Module Standard Configuration .....
ISV11-B M8084 Module Standard Configuration .....

O 00 ~J1 G

wNHOYU

?WWS’D’

¢ceececcecccessssonssccscsssosscsascscsccsccscs

@ DYS50

W WP
I
I
I

.cccececscscscccscscscsssssoacssccooccsaos

Wopowww
N
I
I

the DYS50

Factory Configuration of the MSV11-P (M8067-KA)

PDP-11/23B (H9276) Two Backplane
CoNfigurationsS teeeeeeceeeceeeoeoecoecsosasssnnccesoe
PDP-11/23B (H9276) Three Backplane
Confilgurations .eieeeeeeeeeeeeeeceessssossscancsese

C-3
C-4

WNHF
N
WD

GUUEBNDNDNDN

TABLES
Box

...ceececeeetacceccccsccccccacocnconss

Switches

Backplane
Bezel

and

Factory

Assembly

TeStS

SOftcore

TesStsS

Extended

LSI-11l

Bus

Signal

Bus

Signals

MOAULES

Vulnerable

InNdicatorsS

Jumper

Factory

Hardcore

Quad
U

Contents

DYS5@

...eeecececececcceses

Configuration

Jumper

..........

Configuration

2-6
2-190

2-13

.....

2-14

.ceeeeeeeeecececcacacacecenoocccnans
.tuiveieeeececccrcecacaccooncsnoaceses

4-7

Bus

for

Signal Pin Assignments ......
AssignmentsS ...ceeceeeeccccoccscss

H9276

Compatible

v veeecscesacosocccccnocononsssscasns

Bus

Double

viii

Module

Connector

Pins

PREFACE

This hardware technical manual, like most technical manuals, tends
to be all-inclusive. The information is not restricted to a single
audience. It is addressed instead to several audiences -- none of
which is expected to be interested in the entire document.
Individual chapters, however, are audience-specific. For those who
want to know what to read, and what not to read, the following
describes the chapters.

Chapter

Introduction

This chapter defines the DYS5@#.

who

wants

quick

summary

The chapter

of:

the

is for

DYS58's

individual

the

function,

relationship to the DECdataway, and its available options.

Chapter 2

its

Installation

This chapter contains the information and level-of-detail needed
by individuals who do the installation. It tells how to unpack,
inspect, mount, and power-up the DYS5@. It also tells how the unit

should operate when first turned on, and how to implement some of
its

interfaces.

Chapter

Maintenance

This chapter is for the Field Service or other maintenance person

who

troubleshoots

isolate

how to

faulty Field

replace

Chapter 4

and

repairs

failed

Replaceable

it with a new FRU.

ISV11-B Description

Unit

DYS5@.

(FRU),

tells

and,

once

The first few paragraphs of this chapter are of general

how

interest.

They contain a short functional description of the ISV11-B.
remainder

the chapter

contains

found,

a detailed description of

The
the

ISV11-B logic as shown in the field maintenance print set. It is
service
component-level
and
engineers
that
so
included
n.
informatio
this
technicians will have a permanent record of

Chapter 5
BAll-Y Power System Description
This
chapter
contains
a
complete
physical
description of the BAll-Y mounting box. That is,

DYS50

supply

wiring

modules

and
electrical
the box that the

are plugged into.
It describes in detail: all power
circuits, power distribution, and all backplane and
chassis

for

the

entire
BAll-Y
box.
It
is
included
here
for
and
sSo
that
engineers
and
compohnent-level
troubleshooting
technicians will have a permanent record of this
information.

reference,

CHAPTER

INTRODUCTION

1.1

DEFINITION AND SCOPE

The DYS50 is an LSI-11/23B microcomputer with a DECdataway network
interface. This configuration is called a DECdataway Intelligent
Subsystem
(DIS).
The
DYS50
functions
as
a
fully programmable
DECdataway
network
node.
It
operates
in
an
execute-only
environment
under
the
RSX11-S operating
system.
It
1is
not
a
development

The DYS50

Control

subsystem.

is a product of DIGITAL's Manufacturing

(MDC)

industrial

group.

1local-area

DYS5@8s are the

Distribution and

This group designs hardware and software for
networks

called

intelligent elements

DECdataway

(DY)

in these networks.

systems.

The DECdataway also supports other devices besides DYS5¢s, but
these are fully described in their own manuals. This manual is
about the DYS50 only. Moreover, it is strictly a hardware manual.
It
tells what
a
DYS5@¢
1is,
and how to
install, operate,

troubleshoot, and maintain it. It contains functional and physical
descriptions of the DYSS5@ subsystem and a detailed description of
its

DECdataway

interface,

the

ISV1l.

Where appropriate, some ancillary topics are discussed, but not in
any depth. For example, this manual does not fully describe: the
DECdataway, the DYS5@'s processor, its memory, or its peripherals.

These

devices

manual

describe

descriptions

are

subjects

also

Finally,

This manual

are

DYS50
is,

not

unique

the

operating

maintenance

contained

DYS50

separate

fully discussed

installation

therefore,

Their

Neither

detailed

does

software.

separate manuals.

presumes

just

DYS5@¢.

manuals.

small

a DY network
part

your

this

These

installation.
total

system

documentation package. The total package includes not only all
documents for your particular DY system's hardware complement, but
several DY system operating and maintenance software documents as
well.
Paragraph
1.6
lists
several
existing
documents
that
specifically address these topics.

1.2
Figure

cover cut
From
the

INTRODUCTION
shows
a
DYS5@¢
away.

top,

the

four

DECdataway
interface
modules further.

BAl11l-YA

with

consists

its
a

modules

Mounting

box

panel

KDF11-BB

Processor

MSV11-PK

256

ISV11-B

DECdataway
module,

are

door
removed
and
module
box and four modules.

mounting

are:

modules).

front

There

front

The

processor,

following

with power

supply,

empty

backplane,

and

controls

(M8189

KB memory

slots

for

and

the

module)

(M8@67-KA module)

interface
(consisting
an
M8084
module,
interconnecting cable)

five

memory,

describes

peripheral

interface

an M808#
and
an

options.

1.3
FEATURES
Components
of
the
DYS50
have
a
number
of
significant
features
that, taken together, make it an efficient and versatile performer
in most any distributed processing application. A brief summary of
the important features follows.

— PROCESSOR (M8189)

[~MEMGRY (M8067-KA)
DECdataway
INTERFACE

{8080 AND
STRIPE

M8084)

BA11-Y MOUNTING BOX

MA-0208-82

Figure

1-1

Basic

DYS5@

KDF11-BB Processor (M8189)
1.3.1
module contains:
quad-height
This

management,

frequency clock,

line

central

BDV1l

diagnostic ROM, two serial line units,
1.3.2

and

bootstrap

floating point, and 22-bit

addressing.

This

memory

processor,

compatible

MSV11-PK Memory

(M8@67-KA)

128K

contains

module

quad-height

semiconductor (MOS) random access memory
-- 16 data and 2 parity.

words

(RAM).

oxide

metal

Words are

18-bits

ISV11-B DECdataway Interface

1.3.3

This unit consists of two modules: the M8@8¢ and the M8¢84. They
are connected together with a short ribbon cable. The ISV11-B is

the DYSS5@'s interface to the DECdataway and the host computer. It
manage
to
programmed
1is
that
microcomputer
a
it
in
has
It
communications between the host and the DYS5@4's LSI-11/23B.
starts, stops, boots, and runs power-up diagnostics on the DYS54.
Chapter 4 contains a complete description of the ISV11-B.
1.3.4
This is

BAll-Y Mounting Box
the DYS50 enclosure

(Figure

extended. (22-bit)

nine-slot,
power

supply

DYS50

very

that

provides

1-2).

LSI-11/23
volt,

contains

backplane,

and

+12

BAll-Y

volt

H9276

H7861

and

power

the

backplane. The BAll-Y is just 26.67 cm (1¢.5 inches) high, and
only 27.94 cm (11 inches) deep. All modules, cables, controls,
adjustments, and test p01nts are front-accessible, which makes the
easy

service.

The

equipped

for

easy

in either a NEMA-12 industrial type enclosure, or in a
cabinet. Both the backplane and power supply are Field

mounting
standard

Replaceable

(FRUs);

Units

can

they

swapped

matter

minutes.

GENERAL DESCRIPTION

1.4

The best way to understand how a DYS50 works is to look at its
relationship to the DY system of which it is a part. For that
reason, we will begin with Jjust a brief, and much simplified

description of how a DY system works. Readers interested in a
comprehensive treatment should consult the references listed in
1.6.

Paragraph

DY Systems

1.4.1

its simplest form,

a DY network has a

centrally-located

(host)

-located, smaller computers. The
computer, and multiple, remotely
remotes can be placed anywhere in the local area where dedicated

processing
channel

called

needed.

remotes together

the

Completing

DECdataway,

(Figure

1-3).

the network

which

connects

is a communication
the

host

As the figure shows, DYSS5@s are the distributed elements
The host system can be either a VAX/VMS or
network.
computer,

running

RSX11-M or

RSX11-M

PLUS.

and

all

of the
PDP-11

FOR NEMA

il 'lllllium“'“lll
Uiy |

hr_-.._

MOUNTING

PUSH HERE

TO OPEN

FOR STANDARD
MOUNTING

FRONT ACCESSTO ALL
CABLES, MODULES

ADJUSTMENTS

SPRING HINGED P.S.

FOR EASY SERVICE OR
REPLACEMENT

P.S. ADJUSTMENT
MA-0230-82

Figure

1-2

DYS50

Enclosure

Features

HOST
-

—_——

: ISB11-A
I_._.l..._..-l

DECdataway

TERMINATOR

DECdataway

—: r—4=a1r

:—

DECdataway

TERMINATOR

I -e—— T

i——‘-—‘l
|
| Isv11B | | 1svitB ] | OTHERaway | PL sviie _}! || oTHER
|
way
DECdata
DECdat
|
|
L
_}
L|
|OPTION
l{=-—=
| OPTION
-

i""’""'"1
DYS50

DYS50

]

DYS50

TASK n

TASK n-1

TASK 3

-T

|
I

TASK 2

TASK1

]

-T =

MA-0216-82

A Typical DY System

Figure 1-3

Because they are linked by the DECdataway, DYS5@s are DECdataway
subsystems, and because they are programmable they are called
intelligent subsystems. Thus the name: DECdataway Intelligent
(DIS).

Subsystem

on
DYS5@s are fully programmable and are therefore not dependentrole
the host for performance at their dedicated functions. What all
does the host play? The host is able to communicate with

DYS5¢s

the

via

DECdataway.

«can,

therefore,

effect

communications between tasks in different parts of the network.

each DYS540
It can also start, stop, and monitor the progress of contro
lling
by
d
manage
ly
sensib
be
can
task so that a large system
output
system
total
zes
optimi
that
manner
all its subsystems in a
and

economy.

The economies are of several types. For example, DYS5@s are fully
in an
programmable, but they serve local processing needs
been
have
that
ms
progra
running
by
this
do
They
execute-only mode.

' developed

the

host

and

down-line

loaded

them via

the

DECdataway. Thus the additional hardware and software tools
the

normally needed for program development are required only at
host -- a considerable economy in a large system.

Other economies are achieved because the host can also share its

database or mass-storage devices with the remote systems. All this
is in addition to the fact that distributing the processing, power
more
_in the first place breaks an entire project into smaller

manageable

convenient
improved

tasks,

and

location,

response.

reduced

doing

wiring

achieves

costs,

economies

modularity,

and

Finally
then,
although
DY
System
implementations
may
vary
considerably
from one application to another, they have
in common
a
major
attribute:
they
modularize
a
large
task
into
several
smaller, more manageable ones,
which can be physically dispersed
for
optimum
convenience
and
efficiency.
And
the
DYS5¢
is
the
principal means of accomplishing this modula
rization.

1.4.2

DYS58

Recall

that

DECdataway

Functional

DYS5¢

network

devices

Description

runs

host

its

own

relates

local

programs,

all

and

as
a
sort
of
manager.
Figure
relationship between a single DYS5¢ and:

and

the

DYS50

task
A

local

needs

task.

From

least

three

interface,

block

and

the

figure

diagram

detail.

The

block

this

figure

things:

computer
DYS5¢

1-4
the

can

the

that

the

DECdataway

shows
the
physical
DECdataway, the host,
be

DECdataway

run

and

other

implied

that

interface,

local

programs.

only

(Figure

1-5)

familiar

enough

looking

shows

this

LSI-11

the

computer

diagram with the exception of the block
labeled DECdataway
interface, which makes the DYS5¢ functi
onally unique.
It
is the
only part of that figure that requires furthe
r discussion in this
manual, and a complete description of
it is presented in Chapter
4.,
Discussions
of
the
LSI-11/23B
computer
and
its
various
I/0
options are contained in the refer
ences.

The

ISV11-B

takes

DECdataway

serial-type

messages,

DIGITAL

serial

them

LSI-11

bus-compatible

parallel

address

and

then

makes

data

the

memory.

DYS50

The

DYS5¢
host

via

DYS5¢

data.

I/0

the

serves

DYS50

its

halt,

network

software

that

several

references

The
or

responds

course,

DYS50)

make

this
of

intérrupts

DECdataway.

start,

The

reverse

protocol

this

must

all

function

until

message

addition

listed
in

place

and

data

the

(both

These

matters

Paragraph

1.6.

receive
any

format.
LSI-11

transferring

may contain

are

converts

DYS5@'s

when

receives

simply

would

work.

1local

perhaps

which

format,

process

DECdataway.

the

page.

(DSBC)

transfer
the

processing

the

its

DMA

normally

and

the
some

control

performs

data

program

bus

running

its

message

from

command
or

for

transmit

other

device

hardware,

there

and

the

subject

are

the

host

the

DECdataway
|
— — — —

HOST

[
DYS 50

LOCAL TASK

MA-0215-82

Figure

1-4

Single

DYS58

DECdataway

INTERFACE
(ISV11-B)

LSI-11/23B (KDF11-B)
PROCESSOR WITH
MEM MGMT AND

EXTENDED

FLOATING POINT

LSI-11 BUS —»

(22-BIT)
I

128W MOS MEM

WITH PARITY (MSV11-PK)

/O INTERFACE OPTIONS
® [PV12 (M7959)
® DZV11 (M7957)

—_ e ——_ - J
LOCAL TASK INTERFACE
FOR EXAMPLE:
e PROCESS CONTROL

o TERMINAL CLUSTER

MA-0213-82

Figure

1-5

DYS50

Block

Diagram

1.5
TYPICAL DYSS5¢ CABINET CONFIGURATIONS
Figures
1-6
and 1-7 show some typical configurations
for
H9646
cabinets. These figures show equipment that would be used with the
DYS50 in a process control application. Figures 1-8 and 1-9 show
similar equipment configured in an H960 cabinet.

H332

+—SCREW
TERM.

IPV12

+—{/0

; 874

EXPANDER

POWER

I“"‘IE'

—

—»

CONTROLLER

- 10

BA11-Y

’

iulia =(]

DISTRIBUTION

PANEL

A H349

—

<*—DYS50

(H334)

h
MA-0251-82

1-6

H9646

Cabinet

Configuration

RX02

O—0

Figure

[ DISK

|
IPV12

H332

1/0

-+—SCREW

(H334)

TERM.

le——DYSHO

| H349
DISTRIBUTION
PANEL ——)

OO0

BA11-Y

EXPANDER

Figure

r 874

~=—1 rower —|[l0f
]

—

L_JE'

1-7

H9646 Cabinet

CONTROLLER

Configuration

MA-0249-82

H332

e— SCREW

la—|/O
(H334)

[

iPV12

TERM.

«—SCREW

L334

1/O

:
<

[

«—DYS50

H349
PANEL

T EXPANDER

—|lo000O

CONTROLLER

0000

[

1.8 OO

00}

oin

MA-0250-82

H96¢@ Cabinet Configuration

Figure 1-8

Ic
|

POWER

[ D Cf
| L]0 \

|ss

I
H

—

DISTRIBUTION

BA11-Y

J OO |

RX02

]|
|

DISK

i
«

H332
—SCREW

|
+

IPV12
«—1/0

TERM.

(H334)

e— DYS50

[ = -

H349

DISTRIBUTION
PANEL

“ EXPANDER
BA11-Y

861

POWER

|
Y

r--]

Figure 1-9

H96@ Cabinet Configuration
1-9

I D D I—-_——] A
|

—lifloo00

CONTROLLER

—|

—

|OO0O0

[

1.8 OO

. OO}
ab
MA-D248-82

1.6
The

RELATED DOCUMENTS
following documents are

shipped

with

your

Title

DYS54@.

Document

DYS5@

Technical

DYS5@

Pocket

Manual

EK-DYS50-TM

Service

Card
User's

KDF11-BA

CPU

Module

MSV11-P

User

Guide

EK-DYS50-PC
Guide

EK-KDFEB-UG

EK-MSVQP-UG

DYS50 Field Maintenance Print Set
KDF11-BA Field Maintenance Print Set

MP-01403
MP-92136

MSV11-P

Field

Maintenance

ISV11-B

Field

Maintenance

MP-01239
MP-00609

BAll-Y

Field

Maintenance

Microcomputer

Interfaces

The

following

Digital

Equipment

Accessories

Number

and

Print
Print
Print

Set
Set
Set

MP-01402

Handbook

documents

can

EB-20175-20/89
be

ordered

from:

Corporation

Supplies

Group

P.O.

Box CS2008
Nashua, New Hampshire

@3¢61

Title
Digital

I/0

Document
Site

DECdataway

DPM

Preparation

Subsystem

User

Diagnostic

Guide

EK-OCORP-SP
EK-gPIOS-UG

Guide

User

EK-ISB11-UG

Guide

VAX-11

and

DY32 Hardware Installation
Diagnostic User Guide

Serial

Bus

Remote

Terminal

Diagnostic

Exerciser
Monitor

DPM/DPM-PLUS

consisting

Write

MD-11-CZKCH-D

MD-11-CZKCI-D

MD-11-CZKMP-D

Set
following:

the

Dataway

User

Intelligent

Terminal

DPM/DPM-PLUS

System

Management

AA-J529B-TC

Guide

DPM/DPM-PLUS

and

Write

EK-DPM
@ -DM
@
EK-pPDY32-UG

Documentation

DPM/DPM-PLUS
Subsystem

Write

Tester

Number

User

Guide

Generation

Guide

DPM/DPM-PLUS

Release

DPM/DPM-PLUS

Mini-reference

Notes

AA-J5309B-TC
AA-J531C-TC

AA-K160B-TC

AV-M195A-TC

addition

for

details.

documentation,

available from DIGITAL.

DYS5@

maintenance

training

also

Contact your local DIGITAL representative

SPECIFICATIONS

1.7

The following are the specifications for the DYS54.
CPU

KDF11-BB

Memory

128K words MOS memory

Voltage/Current
DYSS50 A/D

Frequency

Power
Ride-through
Input protection

6 A maxXimum at
3 A maximum at
47 Hz to 63 Hz

115 V
230 V

690 VA, PF=f.6 minimum
15 milliseconds minimum
Fast-blow fuse: 10 A for 115 V
operation, 5 A for 230 V operation

Environmental
NOTE

When

other

mounted

equipment

the

same
cabinet
as
a
DYS5@0,
use
the
environmental limits of the product with
the minimum environmental capability.

Operating

Temperature

80 50
to

(41

Nonoperating

Coambient

122"

-40° to 66° C ambient
(-48° to 151° F)
NOTE

The
maximum
allowable
operating
temperature is based on operation at sea

level. The maximum allowable operating
tem%erature is reducgd by a factor of
for
F/1000 ft)
(1.0
C/1000 m
1.8

operation at high altitudes,
Humidity

Operating

1flopercent Lo 95 percent RH
F) maximum wet bulb
C (89.8
38

2°

Nonoperating

Altitude

(35.6

minimum dew point

19 percent to 95 percent RH
(noncondensing)

Operating

2.4 km

(8,000 ft)

Nonoperating

9.1 km

(30,000 ft)

1-11

Physical

Height

26.416

width

48.26

Depth

(with

door)

(without

door)

Weight

(19.4

(19

32.537

(12.81

(11.6

(46

in)

29.464
20.9

ADDITIONAL

in)

1lbs)

SPECIFICATIONS

Specifications

in
and

the
the

for
all
LSI-11 microcomputer components contained
are provided in the Microcomputer Processor Handbook

DYS50

Microcomputer

Specifications
ISV11-B,

are

appropriate
for

the

for

the

provided

manuals

ISV11-B

Interfaces

are

Handbook.

remaining

DYS5¢

respective

their

shipped

listed

with

Chapter

each
4.

components,
user

system.

except

the

guides.

The

Specifications

CHAPTER

INSTALLATION

INTRODUCTION

2.1

tells

chapter

This

unpacking,

short

checkout

power,

and

not

basic

DYS50

the

for

instructions

primary

there

how

DYS58.

the

install

interfacing,

the

for

preparing

system

that

procedure

are

Included

inspecting,

connecting

operation.

establishes

Finally,

whether

is operational.

The chapter does not cover installation of peripheral devices that
with

interface

basic

DYS5@,

expansion.

the

its

covers

DYS5¢.

interfaces,

Peripheral

and

for

devices

the

only:

some

installation

guidelines

DYS58

are

for

installed

the

its
per

instructions in their respective manuals, one of which is included

with each device.

Chapter

These manuals are

includes

list

referenced where appropriate.

documents

shipped

with

the

basic

DYS5@.

2.2

SITE PREPARATION

The DYS580 is only one of several devices that can be connected to

the DECdataway, and is only one part of a larger host-based
system. This means that its site preparation is provided for in
the preparations for the DECdataway. Therefore its assigned
location should have a DECdataway remote device interface
connector and the appropriate primary power receptacles.
Final

positioning

DYS58

cabinet

must

allow

sufficient

clearance from any obstruction that might hinder air flow to the
cabinet, or easy access by service personnel.
CAUTION

To maintain stability in operating and
cabinet
DYS50
positions,
servicing
configurations must be secured to the
floor or an adjacent cabinet.

2.2.1

Site Power Requirements

Site Power Receptacles do not necessarily mate directly with the
DYS58. And which receptacles are required depends not only on
whether the DYS5@¢ is 115 Vac or 23¢9 Vac, but also on whether or
not a cabinet power controller is being used. The power controller

requirements are different because, since it usually powers more
than one device, its current rating is higher.
2-1

For

example,

power

the

receptacle,

either

type

DYS50

then

type

respectively).

If,

into

cabinet

power

type

going

that

the

(for

other

itself requires a type
higher current rating.

for

plug

directly

must

be,

239

115

Vac

hand,

the

DYS59

controller,

receptacles

receptacle

the

power

DYS5@,

into
for

Vac

but

the

power

C or D site power receptacle
Refer to Figure 2-1.

site

operation

going

controller

example,

plug

must

have

controller

because

its

Note that two power cords are provided with the DYSS5@. One
is for
115
Vac
service and
the other
for
230
Vac
service
as
shown
in
Figure 2-1. Use the one you need and discard the other.

Verify that the site
is
wired
correctly,
receptacle

power receptacle is the correct one, that it
that
the voltage
is
correct,
and
that
the

properly

these
matters,
(EK-OCORP-SP)
.

grounded.

refer

For

the

Digital

complete

Site

discussion

Preparation

CABINET
__________

__________

115V

115V LINE CORD

SITE POWER

PART 17-00143-00

__ -

115V

DYS50

| ]

230V

e
ptpheetéhnpndekn° e/ —— 1

CABINET
____________

__________

230V
SITE POWER

230V LINE CORD
PART 17-143-01

115V

DYS50

° s

0\0“

230V

e e
CABINET

POWER CONTROL BUS

115V

115V LINE CORD

SITE POWER

115V

POWER

@ TROLLER
o

115V

DYS50

-2

115V

g @ 0"

CON-

PART 17-00143-00

230V

T —J

CABINET
D

230V

CID

SITE POWER

—

G—

—

PART 17-14301

CON-

—

——

v—

—

115V

DYS50

TROLLER

O~ S1

230v

b o
NOTE:

m—

230V LINEcORD

POWER

——

POWER CONTROL BUS

CONFIGURATIONS A,B,C, AND D MATCH TEXT EXAMPLES

MA-0211-82

Figure

2-1

Site

Power

Guide

2.2.2
If the
must

NEMA Enclosure Requirements
DYS50 is to be installed in a

some

advance

planning.

enclosures;
they must be
customer
must define
the

that
must

NEMA

DIGITAL

enclosure,

does

not

the

sell

customer

NEMA

type

provided by the customer. Moreover, the
equipment
configuration
that
goes
into

cabinet.
When
specifying
that
configuration,
the
customer
allowances for: heat dissipation, primary power, and I/O
cabling.
Refer
to
Paragraph
2.6.1
for
NEMA
enclosure
mounting
make

instructions

and

dimensions.

2.3
DYS5@ UNPACKING AND INSPECTION
Some DYS5#s are shipped separately and some are already mounted in
cabinets with their customer chosen peripherals.
If your's
is a

separate
cabinet

unit

skip

Paragraph

2.3.2.

mounted

continue.
NOTE

protect

must

not

DIGITAL

2.3.1
Perform
single

the

warranty,

unpack

the

representative

Factory Configured Units
the following unpacking and
and

multicabinet

the

system

customer

unless

present.

inspection

procedure

for

all

systems.

2.3.1.1
Unpacking
-If
the
shipment
must
be
moved
from
the
receiving area, make sure doorways and passageways are wide enough
to accommodate
its
selected

cabinet pallets before trying to move equipment to
location.
Regardless
of
where
unpacking
and

inspection
is
done,
do
not
remove
containers
from
the
pallets
until the shipment is examined for possible damage.
(Reimbursement
for damaged goods removed from the pallet is difficult.)
Perform

the

following

unpacking

procedure.

Make

sure all containers are sealed.
If
record
it
on
the
1Installation
Service Report.

any container
is
Report
or
Field

open,

Check
you

the
have

shipment

against

received

the

packing

correct

list

number

to
and

make
type

sure
of

containers.
If
the
shipment
1is
incorrect,
notify
the
salesman and/or customer, and the Branch Service Manager.
The customer should check with the carrier to locate any
missing items.

Check

all

containers

protrusions,
and

record

Report.

holes,
on

the

for
and

external
smashed

damage.

Look

for

dents,

corners.

Note

any

damage

Installation

Report

Field

Service

Open each container starting with the one
FIRST." Locate the packing slip and check

marked

"OPEN ME
contents of

the

each container against its respective slip.
Identify any
missing items on the Installation Report. Save any ramps
that might come with pallet-mounted equipment.
5.

If reshipment
such as foam

is a possibility, retain packing materials
fillers and plastic
inserts.
In any case,

retain
the
plastic
(antistatic)
individual modules are shipped.
2.3.1.2

Inspection —-Inspect

for

the

damage

stabilizer

Perform
outside

the
of

bags

following
the

which

any

inspection procedure.

equipment

such as scratches,

and/or

cabinet(s)

broken switches,

and broken

feet.

Inspect
inside
the
equipment
and/or
cabinet(s)
for
damaged components such as switches and indicators, or
for
loose and broken cable connections. Make sure all
modules are securely seated in their connectors.
Note

any

damage

found

and

record

Service

Manager

Notify

Inspect

each

cabinet

Installation

Report.

any damage

the

Branch

Report.

found.

and

freestanding

the

Installation

immediately of

peripheral

make

sure it contains the items listed on the transfer sheet.
Check the engineering change order
revision
(ECO REV)
level and serial numbers against the transfer sheet or
ECO status sheets. Record any missing
items,
incorrect
serial
numbers,
or
1incorrect
revision
1levels
on
the

When

inspection

cabinet(s)
cabinet(s)

1is

from
as

complete,

the

remove

shipping

the

pallet.

equipment

and

Remove

the

follows.

Unbolt cabinet(s) from the shipping pallet. The bolts
are on the lower supporting side rails of an H960
cabinet, or at the four corners of an H9646 cabinet,
and can be reached from inside the cabinet.

Raise

stabilizing

feet

above

the

1level

the

casters.

Attach

enclosed

to form a
cabinet(s)
d.

Install

ramp
onto

front

ramp

use

from pallet
floor.

stabilizer

wooden
to

feet

blocks

floor.

with

and

planks

Carefully

hardware

roll

provided.

2.3.2

Separate Units

All components of the basic DYS5@ are shipped in a single carton.
Optional devices are shipped in separate containers, and may
require special unpacking procedures. Consult each option's own
documentation for details.

Perform the following unpacking
1.

procedure for

the DYS54.

Inspect the DYS5@ package for any external indication of
shipping damage. Record any such indication on your Field
Service

Open

report.

the

contents
all

package

with

any

remove

2-2

shortages

items have

Record

and

Figure
been

and

received.

the

contents.

Table

Check

damage

2-1

all

and

items

your

Compare

the

verify

that

for

Field

report.

DATAWAY

230 VAC LINE CORD

115 VAC LINE CORD

INTERFACE

CABLE

FUSE FOR
230V OPERATION

HINGES

MANUALS

MA-0228-82

Figure

2-2

DYS50

and Accessories

2-5

damage.

Service

Table

2-1

Box

Contents

Quantity

Description

DYS50

Door

Top

(with

KDF11-BB,

MSV11-PK,

hinge
Bottom hinge
120 vVac power cord
249 Vac power cord
DECdataway interconnect

1
1
1
1
1

Fuse

Hinge mounting
DYS50 mounting
DYS5¢ mounting

4
4
5

5A/250

Field

ISV11-B)

cable

screws phl pan sems
screws trus phl sem 1¢-32 X 1/2
nuts, tinnerman, 10-32
Maintenance Print Sets (DYS50, BAll-Y, KDFl1-B,

MSV11-P,

ISV11-B)

Technical

Manuals

User

Service

Card

Guides

(DYS54,

KDF11-B,

MSV11-P)

DYS50

Pocket

NOTE

expander

box

(BCA2D-#5).
requires two

which

must

Appendix

A
10

has

two
5
foot
cables
second
expander
box
foot cables
(BC@2D-10),

ordered

for

details.

separately.

Save
the
shipping
container
until
certain
that
return
location is not necessary.

See

and
all
packing
materials
or
reshipment
to
another

Place

the DYS50 on a bench so that its front hangs over
edge of the bench about 4 cm (1.5 inches). Remove the
front module cover by loosening the two knurled, captive

the

screws

down

near

the

(Fiqure

bottom

2-3).

Slide

Without

removing

broken

indicators,

damage.

The

Figure

Record
report.

any

module

2-4.

damage

the

unit

modules,

and

back

pulling

inspect

the

for

out

and

bench.

any

bent

connectors,
or
any other
obvious
configuration should match that shown

not
or

add

any

shortages

modules

Field

the

this

time.

Service

MA-0224-82

Figure 2-3

Module

Cover

KDF
11 PROCESSOR (M8189)

MSV11 MEMORY (8067-KA)

3 [

ISV11 (M8080)

]

*~~RED STRIPE
THIS SIDE

9 [

ISV11 (M8084)

J
MA-0105-82

Figure

2-4

DYS58 Modules

Place
edge
a.

the
of

DYS50

the

work

Remove the
at
either

DYS50

about

bench

and

remove

two
end

its

(12

inches)
the

back

cover

from

retaining screws, just forward of
of
the
front
panel,
that
fasten

cover.

One

these

shown

the

follows.

and
the

Figure

2—5.

Using both hands, place your thumbs against the top
front
edge
of
the
DYS5@,
Jjust
above
the
cover
lock~-release levers, as shown in the boxes in Figure
2-5.
Place
your
index
fingers
against
the
release
levers,
and your middle fingers
under
the
1lip just
above the modules.

SLIDE RELEASE LEVERS

PRESS FORWARD WITH THUMBS

PULL BACK WITH INDEX FINGERS

MA-0227-82

Figure

2-5

Cover

Removal

2-8

of them
While holding

both

the release levers, sliding
center of the front panel.
the
toward
on

Push

the levers in that position, press forward with your
thumbs, and pull back with your middle fingers. The
DYS5@ should release and slide a little way out of
the

cover.

Complete cover removal by gripping

the lip above the

modules with one hand and pulling toward you, while,
with the other hand, holding the top rear edge of the
cover.

Become

DYS59 SWITCHES AND INDICATORS
proceeding any further, study
familiar

with

DYS50 switches and

the

1locations

indicators.

Figure

and

2-6

functions

POWER O.K.
REMOTE

and

RESTART

the

AUXILIARY

OFF

f 7 e? 4

a»

Table

HALT

POWER

SWITCH

+12v
ADJUST

115/230V
SELECT

R ETU RN

+12V

+5V
ADJUST

+5V

DIAGNOSTIC

+5V (GREEN)

DISPLAY (RED)

LSB

MSB

~ | PROCESSOR

L
PARITY

ERROR (RED)

+5V (GREEN)

LCSSBO Oth

] MEMORY
DIAGNOSTIC

DISPLAY (RED)

jaE—

Before

pe———

2.4

T
> ISV11

Figure

2-6

e,
Switches and

MA-0159-82

Indicators

2-9

2-2.

basic

Table

2-2

DYS50

Switches

and

Indicators

Switch or
Indicator

Location

Function

DYS5@

primary

Front

power

switch

When in the ON or 1 position, this
switch connects ac power to the
DYS50 power supply and cooling

panel

fans.
115/2308

Vac

select

switch

Front

panel

When the 115 legend on this
is visible, the DYS50 is

switch

configured to operate on 115 Vac
Primary power. When the 23@ legend is
visible, the DYS50 is configured
for 230 Vac primary power. To change
the switch setting place the tip of
a ballpoint pen in the depression on
the

front

the

switch

or down.
(Note that the
power cord must also be
AUX

ON/OFF

Front

panel

and

push

fuse

and

changed.)

A cable connects this switch to
the

cabinet power controller.
Since all cabinet equipment is
powered from the power controller,
this switch serves as the master
on/off switch for the entire
cabinet.

HALT

Front

panel

In the down position, this
halts program execution by
DYS50

switch

the

processor.

the

execution
start

position,
is

program

enabled

but

automatically.

does

not

downline

- loading procedure from the
dataway host normally starts

the

DYS54.
RESTART

Front

panel

When

this

is moved

momentary—contact

the

released,
do

HALT

it causes the
power-up sequence.

switch

can

start

the

HALT

console
PWR

Front

panel

up,

the

executing

switch

processor

responds

enters

ODT

switch

position

processor
program.

down,

ODT

and

DYS58 to
If the

mode,

commands

the
and

from

terminal.

This indicator lights when power
supply dc voltages are present.

2-10

Table 2-2

DYS50 Switches and

Switch or
Indicator

Location

Function

RUN

Front panel

This indicator lights when the

pECdataway
interface

ISVl
M8080

At power-up, when one of the twelve
ISV11-B ROM-resident diagnostics

diagnostic
display

module

Indicators

processor

(Cont)

is executing

programs.

is running, these indicators
display its number (in octal MSB

the

right)

An error in any one of the first
nine (hardcore) tests causes its
number to be displayed
continuously.

An error in any of the last three
(softcore) tests causes its
number to flash on and off for
ten

DECdataway
carrier

ISV11-B
M8@84

indicator

module

Processor

KDF11

diagnostic

display

Processor
PWR OK

Memory

M8189

module

KDF11
M8@89

seconds.

When the dataway is connected,
this indicator is on when there

is dataway activity. It is off if

there is no activity or if the
dataway is not connected.

These indicators are normally on.

They are not used for processor

diagnostics in the DYS50 because
the processor

is configured

power-up-mode

Zzero.

for

This indicator lights when +5 V
is present on the processor module.

module

MSV11

This indicator lights when a

parity

M8@67

parity error has been detected.

Memory
PWR OK

MSV11
M8@67

This indicator lights when +5 V is
present on the memory module.

module

2.5
PRELIMINARY CONFIGURATION
Configure DYS50 switches and jumpers
DYS5¢0

Primary Power

Switch

OFF

Restart

OFF

HALT

OFF

Auxiliary

OFF

115/230

switch

follows.
or

zero

position

Vac Select Switch -- Make
sure
the
position
matches the voltage being used at your site.

this

Fuse

-- Two fuses are shipped with each DYS58 -- one
in the
fuse holder,
and one loose.
Make sure the correct one is
in
the fuseholder. The 10 A fuse is for 115 Vac operation. The 5

fuse

for

Backplane

230

Jumpers

Vac

operation.

The

usual

configuration

for

these

jumpers

normally

factory

is
shown
in
Figure
2-7.
Make
sure
that
at
1least
W1l
is
installed. W2 and W3 are not needed but do no harm if present.
Backplane jumper functions are explained in Table 2-3.
Bezel

Assembly Jumpers

configured
are

out,

and

shown

in.

These

Figure
Jumper

jumpers

2-8.

functions

2-4. Alternative confiqurations
in Chapter 5, Paragraph 5.2.4.

are

Make

these

sure

are

2-7

Backplane

jumpers

2-12

Jumpers

W2,

explained

MA-0234-82

Figure

W1,

are

and
in

Table

explained

Table 2-3

Backplane Factory Jumper Configuration
Jumper

State

Function

Wl¥*

The H7861 power supply generated LTC

W2, W3

Out

Jumper

* W1

signal is
signal.

must

used

assert

BEVNT

These jumpers have no effect on
DYS50

removed

from

all

operation.

expander

system since only the box containing the
must be the source of the LTC signal.

boxes

KDF11-BB

SIDE 2
J1

W2o0-0

- 000
o

W3 w4
o

)

SWITCH CONTACTS

(S3,S2, S1)

[}

)

LED CONTACTS

{(RUN, PWR OK)

NOTES:
1. VIEW IS FROM THE REAR OF THE BEZEL
WHEN THE BOARD IS MOUNTED ON THE
BEZEL.

2. JUMPERS ARE MOUNTED ON SIDE 2.
MR-6545

MA-0204-82

Figure

2-8

Front

Bezel

Jumpers

multiple-box

(M8189)

module

Table

2-4

Bezel

Assembly Factory Jumper

Configuration

Jumper

State

Function

Wl,

Out

These

Jjumpers

switch

and

to
off,.
is

Out

CPU

This

allow

the

system

turn

mounted

jumper

this

MOUNTING

system

Paragraph

THE DYS50
was
factory

configured

enclosure,

suit

become

the

that

following

installation

enclosure's

familiar

provide

the

CPU

cabinet,

RUN

mounted

skip

2.7.

2.6.1
Non-standard Enclosure Mounting
If
your
DYS5@0
is
being
installed
in

ON/OFF

power

backplane.

enables

indicator because the
in this backplane.

2.6
If
your

AUX

with

industrial

configuration,
installations.

the

its

configuration.
requirements.

enclosures
DYS5@

for

1is

special

procedure

Study

must

the

Although

DYS50s,

designed

industrial
be

DIGITAL

modified

procedure

specify

and

does

simplify

not

their

such

Specifically, the DYS5@ (without its front door or hinges) fits in
a
NEMA
type-12
industrial
cabinet.
(NEMA
stands
for
National
Electrical Manufacturing Association.)
A NEMA type-12 cabinet
is
30.48 cm (12 in) deep. The DYS50 cover has rear mounting holes for
mounting on the rear wall in a NEMA type enclosure
(Figure 2-9).
Since all DYS50 modules, switches, indicators, and adjustments are
front accessible, it is well suited for this type of installation.
For
more
information
about
NEMA
enclosures,
refer
to
DIGITAL
brochure

ED@#1315-126.

For
examples
of
this
type
of
installation,
EK-@PIOS-UG.
Guide
Subsystem User
2.6.2

Standard

Perform

the

standard

cabinet.

Cabinet

following

you

are

power

cord

Install

the

drawing

Mount

the

hinges

(as

shown

Iqstall

the

DYS50

cover

Figure

2-11)

with

hardware

mounting

screws

the

1I/0

installing

the

cabinet

the

DYS5¢

shown

2-1¢)

with

hardware

(as

shown

tighten

the

unit

E-VA-DYS50-900.

provided.
3.

Mounting

assembly

refer

this

the

cabinet

provided.

time.

2-14

Fiqure

not

USE REAR SLOTS FOR
NEMA ENCLOSURE MOUNTING.
DRILL AND TAP FOUR PLACES
FOR 10-32 X 1/2 IN. SCREWS

J”

(PROVIDED).

13.33 CM
{5.25 IN.)

2-9

NEMA Mounting

NE)

Figure

“\

/\;

MA-0229-82

Figure

2-10

Hinge Mounting

2-15

e
9

STANDARD

CABINET

SIDE RAILS

[
0
[
[

' o

[/
o
[

1
o“lly

——

f
0

e—

Al
0

I“

QQQQQQQQQQQ// o——

VUVVIVVVUQD
O

@O
OO OO OO0 O,

[

O VVVVVVVOVVOAVTVOUNIVOOQ

—

——
—

TINNERMAN

gRun—

—

1333cm

25N,
(5.25IN.)

““

I”

46.5 CM

\10-32 X 1/2
SCREW (4)

(18.31 IN.)

ATTACH TINNERMAN NUTS
(PROVIDED) TO SIDE RALLS.

FASTEN COVER IN PLACE

WITH 10-32X1/2 SCREWS
(PROVIDED)}.

FOUR PLACES.
MA-0225-82

Figure

2-11

Standard

Mounting

Slide the DYS50 into the cover until it is stopped by the
locking bolts. Momentarily press the lock-release levers
to
allow the
DYS58 to go
in
the
rest of
the
way,
and
slide
it
in
wuntil
it
1locks.
Now,
tighten
the
four
mounting screws.
WARNING

Note

that

mechanism

all
once

the

DYS50

prevent

way out of
1its
1locking

has

restraining

its
being
its mounting

pulled

cover,

bolts
have
been
released.
Therefore,
when
removing
it
from
its
mounting
cover,
use
extreme
caution to avoid dropping it.
Leave

LED

the module cage cover off at this
indicators are visible during test.

time,

that

the

Rooooo
oo

000000

0o 0

o0 0

e 90 0 0 009000 aQo O

XXX

Yo 0 0 0000

DECdataway

TO CABINET
POWER

CONTROLLER
MA-0221-82

Figure

DECdataway and

Power

Install the power cord and DECdataway interface cable (as
Do not
with hardware provided.
shown in Figure 2-12)
connect

2-12

Place
at

the

DECdataway at

the DYS5@8

front

approximately the

(ON)

position.

this time.

panel
center

power ON/OFF switch

(located

the

front

panel)

the

2.7
All

CABINET AC POWER CHECK
units
in the DYS5@0 cabinet

power

controller.

following

Remove

procedure

get

the

make

their

sure

properly.

that

power

from

the

874

panel

and

use

the

cabinet

power

At the rear of the cabinet, set
power circuit breaker switch to

Set

Plug

the

power

the

cabinet

receptacle.

the main

controller

The

power

the power
g (OFF).

configured

controller

REMOTE/OFF/LOCAL switch

power

circuit

rear

cabinet

cord

indicator

breaker)

1into

(to

the

should

its

upper

main

OFF.

proper
right

on.

Set
the
power
controller
switch to 1
(ON).

Set
the
REMOTE/OFF/LOCAL
switch
to
LOCAL.
All
cabinet
equipment should go on, and the DYS5¢ front panel PWR OK
indicator should go on. The DYS50 fans should operate.

Set
the
REMOTE/OFF/LOCAL
equipment should go off.

the
switch

MAIN

switch

POWER

REMOTE.

front of the cabinet,
set
the
to
ON.
All
cabinet
equipment

2.8

Set
DC

the

AUX ON/OFF

VOLTAGE

using

The

Vdc

and

+12

cabinet

ON/OFF
on

OFF.

MEASUREMENT

Turn on the DYS50
(Figure 2-6).

calibrated
located at

switch

All

breaker

DYS50 AUX
should
go

before.

circuit

the

AUX

regulated

ON/OFF

switch

voltages

must

the

front

measured

panel

with

digital
voltmeter.
Test
points
for
this purpose
are
the lower right of the front panel also shown in Figure

2-6. If these measurements are not within the limits given, do not
try to adjust the power supply until you first refer to Chapter 5.
That

chapter

some

precautions

2.8.1
Use the

contains
that

the
must

correct
be

adjustment

procedure,

observed.

Measurement of +5 Vdc
following procedure to measure +5

Vdc

voltage.

Attach the voltmeter leads as follows.
The plus lead to the plus 5 V test point
The minus lead to the return test point

The

correct

reading

is +5 V + #.15 V.

along

with

Measurement of +12 Vdc

2.8.2

Use the following procedure to measure +12 Vdc voltage.

Move the plus voltmeter lead to the +12 V test point.

The correct

reading

is +12 V + 0.36 V.

OFF-DATAWAY OPERATION

2.9

For this procedure you need to use one of the DYS5@-site terminals
as a console device. Refer to that terminal's user guide to
determine its interface requirements, and connect it to Jl of the
(This is the console interface; it is normally
processor.
configured at the factory for 9608 baud).

Next, turn on the terminal and place the DYS5¢ HALT switch in the
up position. Then, turn on the DYS5@# using the AUX ON/OFF switch

the

front panel.

When power is turned on, the ISV11-B internal diagnostics keep
repeating and produce the following display on the DYS5¢ console.
The explanatory comments in the right column are not part of the
‘

display.

ODT prompt

@ 0 8 6 7

Interrupt test successful

ODT prompt

g 61134

LSI-11

ODT prompt

Instruction test successful

The display repeats continuously about every 10 seconds.

Observe the ISV11-B indicator LEDs and confirm the following.

The ISV11l (M808@0 module) diagnostic indicators display
the number of the diagnostic (in octal, LSB at the left)
being executed. These indicators cycle as the diagnostics
repeat, but the on/off pattern appears random because all
tests do not have the same duration. However, test 13
(octal) is about ten seconds long and is noticeable.

The ISV11l

(M8@84 module)

carrier indicator

is off.

2.10
DYS50 TO DECdataway INTERFACE
The
communications
1link
between
the
DYS54
and its host
PDP-11
computer
is the DECdataway.
This should already be installed.
If

not,
1its
installation
(EK-ISB11-UG).

covered

the

DECdataway

User

Guide

Part of that installation is selecting the DECdataway port address
for
each
connected
device
(by configuring
jumpers at each port
connector).

The

address

marked

location.
on

the

Check

interface

(Figure
2.11

the

port addresses; the lowest numbered
port
connector
at
the
DYS50
site

site

manager

see

correct

one

for

this

DECdataway

the

DYS5¢,

connector

with

its

receptacle

the

address

dataway

the

OPERATION
connected,

terminal

ISV11

simply

inside

the

ISV11l

zero

cycling

The

(M8@80#

ISV11-B

variation

stops

the

terminal

mate

DYS5¢

the

cabinet

display

again.

repeating.

indicators.

The

there

display

observe

marked

installation.

2-12).

The

Observe

two

the

the
the

ON-DATAWAY

When

uses

with

connector

DECdataway

Any

DYS50

diagnostic

left

display

right

(M8#84

dataway

from

module)

from

the

module)

indicators
through a field

carrier

indicator

activity.
above

basic DYS50 system.
As an aid
Chapter 3
(Maintenance), which

results

indicates

lights

fault

when

to
isolating the fault,
refer
presents a detailed discussion
the
1ISV11-B
internal
diagnostics
and
the
significance
variations from the above results.
2.12
DYS5¢ PERIPHERAL INTERFACES
The following paragraphs discuss interfaces

peripherals.

for

some

common

ones.

the

to
of
of

DYS5@

2.12.1
Standard Interfaces
The DYS50 processor is an LSI-11
to
bus

The

device. Its peripherals interface
bus via control modules. These modules plug into the
and connect to the peripheral devices via one or more cables.
various
control
modules
and
their
cabling
requirements
are

the

LSI-11

discussed at
length
in
the Microcomputer Interfaces Handbook.
A
user guide with additional
interface information comes with each
peripheral; sometimes additional cables are included.

2.12.2

Filtered

cables.

Interfaces

In any electrical system, cables that connect pieces of electrical
equipment carry signals that may radiate enough electrical energy
to cause objectionable amounts of electromagnetic
interference
(EMI)
in the local environment. Conversely, any EMI in the local
environment can be conducted into a cabinet on its interfacing

this

that

cabinet

happens

interference may cause

them

contain

sensitive

malfunction.

circuits,

minimize

the

possibility of either problem occurring with the DYS5@, all signal

cables leaving or entering a DYS50 cabinet, do so through
specially constructed
cable
assemblies
that have
filtered
connectors. These connectors are mounted on an H349 distribution
of this type of interface is shown in Figure
panel. An example
2-13.

H349 Distribution Panel
2.12.3
This panel
is provided with all
DYS58 cabinet
panel
provides
simple
and
convenient means
peripheral

equipment

with

the

assemblies.
The
of
interfacing

DYS54.

This 28.32 cm (11.15 in) by 44.19 cm (18 in) hinged panel is held
in its vertical position by two quarter-turn captive screws.

The H349 panel has ten mounting locations (J1 through J15)
for
mounting up to fifteen connector cable assemblies, as shown in
Figure 2-14.
Eleven cable assemblies contain 1 X 4 slots
(J1
through J11) and four contain 4 X 4 slots (J12 through J15). An
adapter is available to transform four of the 1 X 4 slots (J8

through J11) into a 4 X 4 slot. When mounted, each cable assembly
is connected to the DYS5¢ subsystem by ribbon cables. As Figure
2-14 shows, the J6 and J7 positions are normally used for the two

SLU

interfaces

interface and J7 for

the

DYS50's

processor:

a standard terminal.

INSIDE DYS50

H349

CABINET

PANEL

M F
0|0

DLV11-FB

(M8028)

BCO3L-05

‘

Ml F
[]

for

EXTERNAL

PERIPHERAL

BC22A-25

[
FILTERED EIA

RS232 MALE

]

I‘E’ITA'%OERM

CONNECTOR

Figure

2-13

Filter

MA-70968

Placement

the

console

CONSOLE AND
TERMINAL CABLES
INCLUDED

VIEWED FROM

INSIDE CABINET

L
CONSOLE

|43

[T
9
[ |91
]~
SR

J11

]

DZVI

J12

|
s LT\ qne [T
TT s
———————————————————————— *—T——Dzvn

DZV11

VIEWED FROM

REAR OF CABINET
MR-7378
MA-0218-82

Figure

2-14

H349

Distribution

Panel

2.12.4
DYS50 to I/0 Subsystem Interface
For process I/0 applications, the DYS5¢ must contain an M7959 I/0
control module
(IOCM).
This module provides an interface between
the DYS5¢ LSI-11 bus and the I/0 subsystem D-bus.

The interface is completed via a BC@8R cable that plugs into Jl1 of
the M7959 module at one end, and the D-bus-in connector of the I/0
subsystem H334 chassis at the other end (Figure 2-15). The figure
shows the correct way to install
orientation of the stripe on the
information

about

Subsystem User

the

Guide

I/0

this cable by observing proper
side of the cable.
Additional
subsystem
1is
contained
1in
the
I/0

(EK-gPIOS-UG).

2.13

EXPANDING AN EXISTING SYSTEM
If
an
existing
DYS58
system
needs
more
peripherals
to
meet
increased demands, interface modules for the new peripherals must
be added to the LSI-11/23B bus. The following paragraphs tell how
the

add
bus

new modules
if

there

are

existing
no

spare

bus

slots,

and

how to

slots.

D-BUS IN

<=‘§?\e

\\‘<fi
S
<%’“

\\\

% N
\3\fi_————-

D-BUS OUT

TO H334

EXPANDER 4~ |
CHASSIS

1/0 SUBSYSTEM /

[;; [j

H334 CHASSIS

DYS50

L\ \

mlHIIlUIHHHIIIIHHIHIIIHlI
[

HIII

\\\\ gil

-- ii
e
(

HIl l lHJIH1| HI I HI IHI I1NH H

BCOSR

D-BUS CABLE

NOTE STRIPE

ORIENTATION
MA-0222-82

Figure

2-15

1I/0

Subsystem

2-23

Interface

expand

2.13.1

Adding

there

new

New Modules

a spare slot
peripheral device

on
to

the

LSI-11/23B

the

DYS5#.

bus, it is easy to add
While observing LSI-11/23

bus
rules,
(as
explained
in
Appendix
C)
configure
the
new
peripheral's
interface module address, vector, and other options
(if any); plug the module into the spare bus slot, and connect it
to the peripheral with the appropriate cable. First consult each
device's user manual
to determine if there are any restrictions
and
what cables can be used.
In addition,
the DYS5¢
imposes the
following restrictions for adding new modules.
1.

The
1ISV11-B
M8080
module
following the new interface
M8@84

module

must

moved

the

slot

module.

The

ISV11-B

must

remain

slot

The
and

DZV11l vector space is from 300 to 777.
Vectors
304
cannot
be
used
because
they conflict
with

300
the

ISV11-B.

2.13.2
Adding an Expansion Chassis
If
the original
DYS5@0
chassis
does
not
have
enough
room
€for
expansion, you can extend
the
bus by adding
a
BAl1l-YC
expander
box. The rules for adding new modules to the first box must also
be

applied

connect

slot
1
cables
the

the

second

box.

the

first

bus

the

first

chassis

slot,

and

interface
" usable

the

via

addition,

two
via

second

BC@2D

the

M94¢4-0¢

chassis

via

expansion

cables.
an

bus

These

module

M94¢5-YA

must

cables

the

1last

module

(refer
to Appendix C).
(The
option
consists
of
the
two
and
two modules.)
Note that when adding an expander box,

ISV11-B

2.14

moves

PERFORMANCE

the

expander

box.

VERIFICATION

You can verify the performance of the DYS50 and its peripherals
once
communication
is
established
between
the
DYS5¢
and
host
computer
via
the
DECdataway.
When
this
is
done,
the
host
can
down-line load diagnostic software to the DYS5@. Then, using only
a
local
console
terminal,
you can verify that all
DY subsystem
units are operational by running these diagnostic programs.
Each
Program

exercises

feedback

via

some

displays

integral

unit

printouts

about

the

system

unit's

and

provides

performance.

CHAPTER

MAINTENANCE

OVERVIEW

3.1

Corrective maintenance of the basic DYS5@ is relatively simple. It
is a modular device; if it fails, just identify and replace the
failed module.

Identification of

the

failed module

difficult,

sometimes

but

there are tools to help you do that. All that is needed is some
system knowledge and a logical approach to each problem.

The logical approach is not possible without the system knowledge.

You must be aware of, and clearly understand, the DYS58's
relationship to the system of which it is a part (the DY system) .
For

example,

that

the

you want

troubleshoot

from

DYS5#

the

host,

you must first establish that the host itself is operational, and
that the DECdataway is working properly. You must also determine
working.

DYS5@'s

Read

the

interface

DECdataway

the

related material

and

(the

references

and become totally familiar with DY system concepts.

1ISV11l)

Chapter

This chapter describes DYS50 maintenance only. You can find
hardware maintenance information for optional units of a DYS50
subsystem in their respective user guides. These user guides are
included in the documentation package shipped with the DYS5@¢. In
addition to maintenance information, these user guides describe

optional configurations of these units, which may or may not be

incorporated in a given DYS5@¢. For example, many per ipheral
interface modules have jumpers and/or switches used to select
addresses, vectors, etc. All modules in a DYS50 are configured
before shipment. However, factory configurations of user selected
options may not match site requirements in all cases, so if a
module appears to have failed at installation time, check its

configuration. Even when a previously working module fails and is
replaced by a new one, verify that

consulting the appropriate user guide.

is properly configured by

As for the standard modules comprising the basic DYS5@, if there
is ever any doubt about their original factory configurations,
they are listed in Appendix A for reference.

The United States Area Support Group is chartered to provide all
levels of support,
including Field Service training for U.S. Area

support

personnel.

Support

provided

Regional

European

and

training

European

areas

Support.

3.2

TROUBLESHOOTING TOOLS
is impossible to describe all the ways that a DYSS5@ failure can
affect
a
DY
system.
Some
failures
are
easily
isolated
and

corrected;

expertise

others

attendant

your

time

the

exact

symptoms

troubleshooting

thorough

require
all

command.

spent

will,

approach.

knowledge

the

most

used

large

failure

logical

tools

can

resources

failure

extent,

effort.

dictate

beginning

greatly

and

its
your

and

reduce

the

description of the DYS5@'s hardware and
tools.
They
have
a
top-down
structure

intelligently,

obscure

nature

Nevertheless,

following is a brief
software
troubleshooting

that,

troubleshooting

The

the

The

will

help you quickly

zero-in

causes.

even

WARNING

the

DYS50

process

used

controller,

maintenance

not

industrial

initiate

any

procedures or
diagnostic
programs without
first checking
with
local
site
personnel
for
any
required
safety
precautions
and/or
operating
restrictions.
Certain
of
these
processes,
if
interfered
with
in
any

way,

can

pose

personnel,

extreme

and

hazards

may

even

site

have

far-reaching
and
dire
consequences
beyond their immediate vicinity.

3.2.1
Maintenance Software (Diagnostics)
The following is a brief discussion of what maintenance software
will
do
for
you.
How
to
run
and
interpret
system-level
and
standalone

diagnostics

documents,

depends

These

are

3.2.1.1

the
of

is
is,

listed

System

host.

the

are

the

which

Chapter

Level

subjects of other documents. Which
host computer is used in your systen.

Diagnostics

event

DYS50

that failure to a specific
usually achieved by logical
by

running

results.
another,

One

soundness

These

caused

diagnostics

system

failure,

are

run

isolation

DYS56,
if not
immediately obvious,
system-level fault analysis -- that

the system-level diagnostics and
interpreting the
of
these
diagnostics
tests
the
ISBl11
controller;

(called

the

DECdataway

communications

between

exerciser)
the host and

establishes
the DYS5#@s.

the

3.2.1.2 Standalone Diagnostics -- Further isolation of a failure
to a specific field replaceable unit (FRU) in the DYS5@8 is done by
running standalone diagnostics in the DYS5@. These are down-1line
loaded to the DYS5@'s LSI-11/23B computer by CZKMP, a diagnostic
monitor in the host. (CZKMP also down-line loads part of itself to
the ISV1l's RAM memory. From there it monitors the down-line
loaded, standalone diagnostics and communicates with the
operator.) Once down-line loaded, standalone diagnostics are run
by the DYS5#'s LSI-11/23B computer. They can be monitored remotely
at the host in two different modes (host and communication), or
locally (in local mode) at the DYS50 if it has a console terminal.
Hardware Troubleshooting

3.2.2

Before running any diagnostics, perform a quick visual inspection
of the DYS5@ for any obvious signs of trouble. The following are
things

for.

look

Are both ends of the power cord plugged in?

Is the

)

Are both fans operating?

)

Is the power ON/OFF switch on?

fuse okay?

the

position?

select

volt

115/23@

switch

)

Is the power control cable connected?

Are

Do the POWER OK and RUN indicators light?

)

Are

3.2.3

Aside

the

correct

all

HALT,

RESTART,

and AUXILIARY switches

the

positions?

cables

firmly seated?

in good

Built-In Diagnostics

from

correct

the

system

level

and

condition

standalone

and

their

diagnostics,

connectors

there

are

on-board diagnostics contained in the ISV1l's ROM memory. These

are a series of twelve tests (numbered one through fourteen,
octal) that run automatically every time the DYS50 is turned on.
If the DECdataway is connected, these tests run only once,
otherwise they repeat continuously (except in the case of some
error conditions). The tests are also .run once by one of the

system-level diagnostics: the DECdataway exerciser. Associated
with the built-in diagnostics is a display, consisting of four

LEDs, that indicates the number of the test being run. The tests
are of two types: hardcore and softcore.

3.2.3.1
are

Hardcore

called

Tests

hardcore

because

The

first

nine

tests

they

test

basic

characteristics

ISV11-B.

An error in any of these
microprocessor
to
loop
within

3.2.3.2

Softcore

octal)

softcore
with the

the

(processor

are

softcore
flashing

also

describes

the

eight-bit

Tests

-- The last
ROM-resident

three tests
diagnostic

(12,
tests

13,
and 14,
are
called

they do not stop the ISV11-B from communicating
These tests check the operation of the LSI-11/23B

and

memory).

fast

error
in the

the

octal)

it
does
not
impair
the
communications
of
DECdataway.
Table 4-1
(Chapter 4)
describes

ISV11-B

host.

CPU

causes

because

and

tests

the
test,
thus
continuously
the first failed test. A hardcore error
DYS5@'s
communication
interface
is
not
It is,
therefore, prevented from trying to

displaying the number
also
means
that
the
functioning properly.
communicate,
so
that
other devices on the
the hardcore tests.

nine

their

Test

numbers

takes

may

not

the

at the
softcore

seconds,

noticed

the

but

LEDs.

A
failed
test
number
to
be
displayed
seconds. The error number (in decimal)
operator's terminal.
Table 4-2
(Chapter

causes
the
LEDs for 19

displayed

about

tests.

3.2.4
ISV11l Indicators
The LED display for the built-in diagnostics, located on the edge
of the
ISV11-M898@ board,
provides much helpful
information for
DYS5¢

this
A

fault analysis.
display.

LED

the

ISV11-M8#84

on the DECdataway.
increases.

3.2.5
It

DYS58

cannot

total
not

system

3-1

board

flashes

when

flashes

the

not

that

the

subject

the

rate

interpretation

carrier

present

activity

Flowchart

that

DYS5@

until

host

system

the

when

slower

you

troubleshooting

problem

summarizes

Troubleshooting

overemphasized

troubleshoot

Figure

must

devices
it

always

the

aware

has

been

verified

DECdataway.

The

strateqgy

level

documents

DECdataway.

listed

that

for

the

Do
the

doing

Chapter

When

through
direct
observation
or
system
trouble
analysis
vyou
have isolated a particular DYS50 as the source of a problem, you
can then pursue a troubleshooting strategy to further
isolate
it
to
the
1lowest
field
replaceable
unit
(FRU)
in
the
DYS58.
The
Strategy

outlined

flowchart

form

Fiqure

3-2.

The

figure

is
not
meant
to
be
an
exhaustive
treatment
of
all
possible
failures. It is merely a helpful gquide. Troubleshooting strategies
change as more is learned about the problem, but if you begin with
the approach indicated in Figure 3-2,
it should prevent you from
wasting valuable time misreading the symptoms.

M8080

]E:

IENETT]|

e
15

|o T
=C
b
c——

ISV11

TEST NUMBER
DECIMAL OCTAL

LSB

DISPLAY*
MSB

@000)

s+
+
+

@@0O0
0000

O@OO

"
19

1 I

m8084

NINE HARDCORE ERROR CONDITIONS:

0000

PANENTLY IF TESTFAILS(V1

011

®
OOO
QO O @

SOFTCORE ERROR CONDITIONS.
THREE
OCTAL NUMBER FLASHES FOR 10 SEC-

O‘ O ‘

**11

..O.

2w
" '
15

T HASTL
IgVI
REPLAGE
ONDS. ITS DECIMAL EQUIVALENT

IS UPLINE LOADED TO HOST IF DAT-

AWAY IS CONNECTED. THE TEST

CYCLE THEN CONTINUES. COMMUNICATION WITH HOST 1S POSSIBLE.

0000
IF EARORIS 120R 13, REFLACE
'
'O.. ——— NOT USED
o000 @

——FATALERRORMEANSISVIS
ISTOTALLY INOPERATIVE.
REPLACE ISV11. t

*BLACK = ON

*+ TEST 13 (OCTAL) LASTS ABOUT 11 SECONDS. ITS NUMBER IS DISPLAYED
ALL DURING THE TEST, BUT UNLESS IT IS FLASHING, THE TEST HAS
NOT FAILED.

t MODULE REPLACEMENT SUGGESTIONS ARE FOR MOST PROBABLE
FAILURES. OTHER FAILURES MAY SHOW THE SAME SYMPTOMS,
NOTE: THERE ARE TWO NO-ERROR DISPLAY CONDITIONS

|IF THERE ARE NO FAILURES, AND THE DATAWAY IS CON-

NECTED, THE LEDS DISPLAY A ZERO CYCLING FROM LEFT
TO RIGHT THROUGH A FIELD OF ONES.
IF THERE ARE NO FAILURES, AND THE DATAWAY IS NOT
CONNECTED, THE ON-BOARD DIAGNOSTICS KEEP REPEATING. THE LEDS DISPLAY EACH TEST NUMBER AS IT RUNS,
BUT 13 (OCTAL) IS THE ONLY ONE OF SUFFICIENT DURATION TO BE READ EASILY.

Figure

3-1

ISV11l

Display

MA-0104-82

TROUBLESHOOTING AT HOST
5

ANALYZE CUSTOMER

COMPLAINT

DIS

NO |

SUSPECT

|NVESTIGATE OTHER
PROBLEM

YES

RUN CZKMP IN HOST
MODE

GO TO DIS

ISV11 SOFTCORE

—-@

GO TO DIS

DOWN-LINE-LOAD
PERIPHERAL
DIAGNOSTICS

ANALYZE ERRORS
SELECT LOCAL
MODE GO TO DIS

SELECT LOCAL
MODE. GO TO DIS

@
MA-8315

Figure

3-2

DYS50

Troubleshooting

(Sheet

TROUBLESHOOTING AT DIS

CHECK POWER

CHECK 1SV11

CONNECTOR, FRONT

SOFTCORE ERROR

CORD, DECdataway

REPLACE SUSPECT

INDICATORS FOR

PANEL SWITCHES
AND INDICATORS

MODULE

ISIT

14 (OCTAL)

YES

LOCAL MODE. IF

YES

ERROR
FIND
PROBLEM

RUN PERIPHERAL
DIAGNOSTICS IN

THERE IS NO LOCAL
TERMINAL PROVIDE

A PORTABLE

CHECK ISV11 LEDS
FOR HARDCORE

ANY

ERRORS

ERROR

YES

ERROR

ALL
MODULES
REPLACED

REPLACE
MEMORY MODULE

REPLACE
1SV11

REPLACE
PROCESSOR MODULE

CORRECT
PROBLEM

REPLACING MODULES
DOESNOT FIXDIS

GO BACK
TO HOST

CAN'T GET

DIAGNOSTIC REPORTS NO ERRORS,
_BUT DIS STILL DOES NOT WORK

DIS ON LINE
__T_J

DIS

WORKING

EXIT
CALL

CALL
SUPPORT

MA-8316

Figure 3-2

DYS50 Troubleshooting

(Sheet 2 of 2)

ISV11-B TROUBLESHOOTING

3.3

Maintenance philosophy for the ISV11-B is option replacement (both

modules). However, careful analysis of faults using diagnostics
and

available

test

points

should

permit

service

doing

this.

Note

personnel

isolate a problem to one of the two modules. Chapter 4 contains a

troubleshooting

procedure

for

that

the

ISV11-B

operates only as a unit, that is, with the M808¢0 and M8#84 modules
connected together. However, they are not a matched set; a single

module can be replaced

3.4

if necessary.

ROUTINE MAINTENANCE

. if required) for integral
Routine maintenance procedures (when and
units of a DYS5@¢ subsystem are found in their respective user
be
guides (Paragraph 1.6). Most maintenance procedures can the
of
one
out
performed by removing the rear panel and/or sliding
drawers.

3.5
Once

UNIT REMOVAL AND REPLACEMENT
identified, a faulty unit in a DYS5¢ is easily replace
d using
one of
the
following
procedures.
Field
replaceable
units
(FRUs)
include the following:

Entire

Any

DYS50

plug-in

box

(the

BAll-Y)

module

Fans
Power

supply

Control

panel

module

(bezel

module)

Backplane
WARNING

Note

that

mechanism
all

the

once

from
its
caution to
3.5.1
the

DYS5#

prevent

way

its

released.

Use

the

out

restraining
being
pulled
mounting cover,

its

1locking

bolts
Therefore,
when
mounting
cover,

avoid

Replacement

of the
procedure

following

has

dropping

BAll-Y
to

Place

the

AUX

ON/OFF

Place

the

power

it.

Box

remove

switch

1/0

have
been
removing
it
use
extreme

the

DYS50.

the

(ON/OFF)

Unplug

the
cord

power-control
from

their

position.

switch

position.

power

OFF

cable

(if

sockets

front panel. Place these out of the
into
the
rectangular
opening
just

the

used),

the

left

way by
to
the

zero

(OFF)

and

the

end

the

tucking them
left
of
the

front
panel.
Put
the
power-control
cable
in
first.
It
will be held in place by the power-cord plug, which will
be held neatly in place
if you tuck
it
into
the
front

part

for

Loosen

the

knurled-captive

any

two

Remove the
then down.
cables

taking

connector,

and

mechanically

unless

the

carefully,
not

There

3-3).

the DYS5@¢.
bottom and
Remove

opening.

(Figure

you

pay

module

attached

special
its

channel

screws

cover

note

near

the

position

(some

plugged

attention

you

the

this

each

connectors

size

bottom

out

modules.

the

and

can

right

pulling

orientation

keyed

these cables so that
reinstalling the DYS5@.

are

backwards

this).

Also

note

the

can

them

back

neatly when

put

routing

POWER CONTROL

CABLE CONNECTOR TM

[—

AC POWER PLUG ]

RELEASE
LEVER

MA-0220-82

Figure 3-3

in
Remove the two retaining screws that fasten the DYS5# of
forward
just
and
of,
end
place. There is one at each
the front panel

DYS5@ Chassis Removal

(Figure 3-3).

pull it out
Release the DYS5¢ from its mounting cover andpressi
ng the
by
done
is
This
only about two inches.
ng
pulli
while
rs,
finge
index
release levers with your

with your middle fingers hooked under the lip Jjust over
the module cage. Keep in mind that the DYS50 is not
the
restrained in its mounting cover in any way, slide it
ully,
caref
very
cover
the
of
out
rest of the way
supporting it with your hands on both sides.

the reverse of
The replacement procedure for the DYS50 is nearly
. These will
levers
e
releas
the
for
the removal procedure -- except
into its
back
way
the
all
DYS50
prevent you from sliding the

mounting cover. Press the release levers and push the DYS5@ past
that point. Then push the DYS5@ in until you hear them lock.

3.5.2

Module

Insertion

and/or

the

damaged

if modules

removed

upside

Removal
CAUTION

Modules

might

and

with

backplane

power

on,

down.

assembly

are

inserted

It
is absolutely
imperative
that
you
turn
the
power
off
before
trying
to
insert
or
remove
any
DYS50
module.
Use
the
ac
1/0
(ON/OFF)
switch to turn off a DYS54 or
expander box only.
If your

system

has

been
switch to

power

turn

modules

must

modules.
Do
of
the
card

out

process:

First

connector,
prevents

changing
below

pull

and
damage

any

it.

then
to

modules

the

component

module

side

up.

their

only

and

removed

with

components

enough

carefully

components,

switch

settings

force

guide
as

ON/OFF

use

the

Dual

(Figure

3-4).

extreme

its

is
to
as

module

the

caution,

components

handle(s)
really a
it

slot.

its

DUAL MODULE

TO EXTRACT C/;‘.-

~—_
MA.0223-82

3-4

Module

Replacement

from

yank

step
its
This

wunintentional

itself

DYS50 CARD CAGE

Figure

and
two

release
the

ON/OFF

modules.

cage

out

well

the

dual

CARD GUIDES

.
QUAD MODULE

feature

AUX

not grab a module by
cage.
Module
removal

with

remote

can

side

inserted

adjacent

its

you

quad

left

installed

damage

both

the

prevent

your
DYS58,
entire system.,

have

and

off the

Your
DYS5¢
may
modules go only
All modules are

All

controller,

implemented

the

one

Most quad modules are equipped with extractor-type handles that
help with module insertion and removal. Pulling back on both of
these handles at the same time releases the module from Iits

connector, making removal easy. To reinstall one of these modules,
carefully guide it into its slot, making sure that it is in its
proper card guide on both sides. With the extractor handles
extended outward, you will be able to guide the card far enough
into its connector for the forked ends of the handles to engage
the slots on the sides of the card cage entrance (Figure 3-4).

Insertion is completed by pressing on both handles until they are
the card end.

parallel

3.5.3

Fan Removal and Replacement

The DYS5¢ has two cooling fans: one for the modules, and another
for the power supply. To replace either fan, you must first turn
off the power and remove the DYS5@ from its mounting cover in the

manner

previously discussed.

Use the following procedure to remove the power supply fan.
1.

Unplug the ac cord on the right side of the fan.

Remove the four screws that
bracket, fan, and fan bracket
remove that entire assembly

fasten the power supply
to the DYS5¢ chassis, and

(Figure 3-5).

Use the following procedure to replace the power supply fan.
1.

Check the arrow on the side of the new fan for proper
air-flow direction, and also orient the fan so the ac
plug

Attach

Plug

in the correct position.

the

brackets

the

new

fan

and

reinstall

the

assembly.

in the ac cord.

The logic assembly fan appears difficult to remove but is really
quite easy with the following procedure.

Use the following procedure to remove the logic assembly fan.
1.

Unplug the ac cord on the right side of the fan.

Remove the four mounting screws.

Push the fan back as far as it will go and tip the top
forward. By sliding the fan to one side, you will be able

the

slide out one top corner
fan

(Figure

3-5).

and then the other

remove

REMOVE THIS ENTIRE ASSEMBLY

TO REPLACE POWER SUPPLY FAN

AIRFLOW

PUSH FAN BOTTOM BACK
AND TIP TOP FORWARD.
SLIDE SIDEWAYS TO

REMOVE ONE TOP CORNER, THEN THE OTHER.
MA-0231-82

Figure

Use

the

following

3-5

Fan

procedure

Check

the
arrow on
air-flow direction,

Plug

Install

the

right

new

in first
time.

and

Finally,

fasten

cord.

fan

then

the

Replacement

replace

the

logic

assembly

fan.

the

side

the

new

and

fan

also

for

proper

orient

the

fan

the

bottom

position.
in

the

sliding

four

chassis

the

top

mounting

putting

corners

screws,

and

one

plug

the

Power Supply Removal and Replacement

3.5.4

Use the following procedure to remove the power supply.
Turn

power.

off

Remove

cover.

Remove two screws on top of supply and tip back.
Unplug J1

(ac power harness).

Loosen the screws of the dc harness terminal strip and

disconnect it

(Figure 3-6).

Unplug the control board (the small pc board on the left
Figure 3-6) to access J5 and Jé6. Unplug J5 and J6.

Tip supply down to normal position.

Unlock hinges

Lift

(Figure 3-6).

supply out.

Use the following procedure to replace the power supply.
Make sure the power supply hinges are in the unlocked
1.
position; set it in place, and lock the hinges.

Replace: J5 and J6, the power supply control module, the
dc harness terminal strip, the ac power harness, and the
two

3.5.5
This is
mounted
(Figure

Use

the

screws.

Reinstall the DYSS5@# in its mounting cover.

Control Module Replacement (Bezel)

It is
a 7.6 X 11.4 cm (3 X 4.5 in) printed circuit module. panel
front
the
on standoffs, and is located just behind
following procedure to remove the control module.
Turn off
Remove

power.

cover.

Unplug the two cables that plug into the control module.
Remove the four mounting screws that attach the module to
the standoffs, and remove the module.

REMOVE THIS MODULE

TO EASE ACCESS TO
J5 AND J6

TOP VIEW
POWER SUPPLY TILTED BACK

REAR VIEW

J2 DC HARNESS
MA-0400-82

Figure

3-6

Power

Supply

3-14

Replacement

JUMPERS W1, W2, W3 - OUT
JUMPER W4 - IN

FOUR MOUNTING SCREWS

J1 1S POWER SUPPLY {NTERFACE
J2 IS POWER CONTROLLER INTERFACE
J3 1S NOT USED

TM~
MA-0239-82

Figure

Use the
1.

following
Check

3-7

Front

Panel

procedure to

jumpers

Bezel

replace

through

W4.

Module

Replacement

the control module.
Normally,

jumpers

W1,

W2,

and W3 should be out; W4 should be in. However, there are
other configuration options as explained in Chapter 5, so
configure the new module like the old one unless directed
to do otherwise

by the site manager.

Install the module on the standoffs as shown
3-7, and fasten with the four mounting screws.
Reconnect the cables to J1 and J2
Reinstall

the

DYS5#

(J3

its mounting

is not

cover.

used).

Figure

3.5.6
To

Backplane

replace

DYS50

the

from

Having

its

done

mounting

that,

Remove

Replacement

backplane,

remove

all

the

off

manner

backplane

into

Disconnect

the

harness

screws

disconnect

the

backplane

power

and

the

backplane.

backplane

Loosen

the

backplane

mounting

screws

the

card-cage

rear of the power supply
screws
that
fasten
the
enclosure to the DYS5g.

(Figure

Remove

the

cooling

fan.

bottom

two

the
three

rear

3-8),
remove the
of
the
backplane

On the bottom of the
DYS50,
remove
the
six
screws
that
fasten the bottom cover
to the module cage.
This frees
the L-shaped,
bottom-and-back cover
from the DYS5@¢.
The
backplane,
which
is
mounted
to
the
back
part
of
this

Remove

Place,
the

now

the

and

following

accessible.

four

screws

remove

the

procedure

that

replace

that jumpers W1, W2,
backplane are configured

Fasten

the

screws

removed

Reassemble

new

the

backplane

from

the

DYS50,

fasten

the

backplane

backplane.

Verify
new

o0ld

the

and

W3, on
correctly.

the

cover

not

directed

here.

must

the

use

try

to
adjust
Furthermore, if

exact

procedure

following

the

them

without
adjustment is

and

front

with

the

four

one.

DC VOLTAGE MEASUREMENT AND ADJUSTMENT
+5 Vdc and +12 Vdc requlated voltages appear
do

backplane.

reverse.

limits,

end.

harness.

signal

the

described.

cable

cover,

3.6
If the

remove

previously

follows.

Use

turn

the

plugged

Disconnect

modules

end.

first

cover

precautions

procedure

out

first

remeasuring

indeed

necessary,

as
you

given

here.

3 REAR SCREWS

]

BACKPLANE
SIGNAL CABLE

DC HARNESS

4 BACKPLANE —,

SCREWS

BOTTOM

COVER

BACKPLANE

6 BOTTOM SCREWS

MA-0232-82

Figure

3.6.1

3-8

Backplane

Replacement

Measurement

Use a calibrated digital
typical conditions.

voltmeter

measure

the

voltages

under

NOTE

Do not measure the dc voltages without a
load

amps).

the

power

If you do,

readings.

supply

(at

you will get

1least

incorrect

Use the test points provided at the lower right of the front panel
to measure the voltages (Figure 3-9). The +5 Vdc output should be
between 4.85 V and 5.15 V. The +12 vdc
11.64 V and 12.36 V. If either voltage
the following adjustment procedure.

output
is out

should be between
of tolerance, use

R22
+5 V

ADJUST

ADJUSTMENT

ACCESS
@\

HOLE

TEST

POINTS
ADJUSTMENT
ACCESS

HOLE

ADJUSTMENT

TOOL

IF A METAL SCREW DRIVER
IS USED FOR THIS ADJUSTMENT,

COVER THE BLADE WITH
AN INSULATING SLEEVE.
MA-0226-82

Figure

3.6.2

3-9

Voltage

Adjust

Adjustment

Voltage adjustment potentiometers are located on
inside the power supply (Figure 3-9). Access to
is possible through holes in the front panel.

the control board
these adjustments

NOTE

both

the

+12

Vdc

——

may

voltages

Vvdc

supply

supply
cause

need

adjustment,

first.

first

adjust
Adjusting the

beyond

its

range

crowbarring.

The correct output
is
reached
when
a
potentiometer
is near
its
midrange
position.
If
it
must
be
turned
to
near
an
extreme
position to reach tolerance limits, there may
be a problem in the
regulator.

the

power

the

supply

output

control

cannot

board.

brought

within

limits,

replace

CHAPTER 4
DESCRIPTION

ISV11-B

4.1

INTRODUCTION

The

ISV11-B

can

DECdataway.

That

attached

device

is,

that

an LSI-11

interfaces

computer

LSI-11

network.

DECdataway

computers

the

equipped with an ISV11-B
An

computer

LSI-11

The

is called a Distributed Intelligent Subsystem (DIS).
ISV11-B works with all current versions of the LSI-11 famlly of

equipped

computers.

The ISV11-B consists of two quad-height modules: the M8@8¢ and the
(Figure 4-1). These are connected together with a short
M8084
ribbon cable. One of the modules, the M8¢08¢, interfaces with the
LSI-11 bus via its etched edge connector when it is plugged into
an LSI-11 backplane. The other module, the M8#84, does not plug
into the backplane at all; it has no edge connector. It does,
however, occupy a slot in the module cage. It interfaces with the

DECdataway

cable

connector

via

one

meter

cable. This cable and the ribbon cable that
modules are part of the ISV11-B option.

(3.3

ft)

serial-bus

interconnects

M8080
=

—

8 R

INTERCONNECTING

RIBBON CABLE
W

_NiargRsAsEflRERA

—
O

[

/'
M8084

FINGERLESS

DECdataway

RECEPTACLE

SIDE VIEW

REAR VIEW

NOTE: THE M8080 MODULE IS ALWAYS ASSIGNED AS THE LAST
OPTION ON THE LSI-11 BUS. THE M8084 1S ALWAYS ASSIGNED
TO THE LAST AVAILABLE SLOT IN THE MODULE ASSEMBLY AND
DOES NOT PLUG INTO THE BUS. THERE CAN BE EMPTY SLOTS
BETWEEN THE TWO MODULES.

Figure 4-1

MA-7082

ISV11-B Option ~-- DECdataway
to

LSI-11

Bus

Interface

the

two

4.2

ISV11-B

Recall

that

APPLICATION

ISV11-B

plugged into an LSI-11 computer creates a
DIS.
A
DIS
fulfills
a
modular
function
in
a
class of computer
communication networks called DY
(DECdataway)
systems.
These

systems
are
processing in

local

one

systems,

these

area

industrial

networks

that

complexes.

must

first

implement

see

how

see

how

works.

4.3
In its

TYPICAL DY
simplest

computer,
remotes

and
are

SYSTEM

form,

multiple,
deployed

network

has

centrally-located

remotely-located,
throughout

the

site

computers.
The
wherever
dedicated

DISs)

4-2
of

interfaces.
are

are

Intelligent

LSI-11ls

(the

network,

and

Because

they are

linked

DECdataway

called

shows,
the

subsystems,

intelligent

Subsystem

and

are

1ISV11-Bs

the

because

subsystems.

communication
host
and all

the

are

DECdataway,

they

Thus

distributed

their

the

name,

(DIS).

: ISB11-A :
I__T—.J

l
DECdataway
L
I T
T
7\

r—"‘-—1

i ISV11-B:

e e
DIS

| ISV11-B|
—
DIS

|OEHER

_—}

DECdataway

4 jopTion
i

\7/

r—+—q]

| |-

L......'_.._J

——

;

DIS

TASK 2

TASK 3

TASK n-1

l oTHER

TERMINATOR

DECdataway

- :OPTION

TASK1

DECdataway

\//

| : |sv11.3:

——d
:
TASK n

MA-0216A-82

Figure

4-2

Typical

System

LSI-1lls

programmable

HOST

DECdataway

network

are

—_———
oy

TERMINATOR

(host)

smaller

network is a
connects
the

Figure

works in
DY system

typical

processing
is needed.
Completing
the
channel
called
the
DECdataway,
which
remotes together
(Figure 4-2).

elements

distributed

ISV11-B

they

DECdataway

4.3.1

System Host

The host computer of a DY system local-area network can be either
a PDP-11, or VAX/VMS computer. The same DECdataway hardware is
used in either case, but the software is different. Moreover, the

host operating system can regard all units of a local area as
belonging to the same network even though more than one DECdataway
may be used to connect all of them to the host. Different hosts
can support different numbers of DECdataways and each DECdataway
needs a separate ISB11 DECdataway Controller.

the way,

the

and

host

its

DECdataway controller

ISB11

are

not

restricted to any particular network node; they can be at one end
of the DECdataway or at any node along the entire cable. The
host's node, however, does need an ISBll-unique DECdataway
connector.

DY System Communication Link
4.3.2
A DECdataway consists of more than only

cable.

The

DECdataway

its connectors, and its two cable-terminating
controller,
resistors, as well as the cable, are all part of the DECdataway
(Figure 4-2).

4.3.2.1

pair.

Each of these is described briefly.

DECdataway
can be

Cable

up to 4572 m

This

cable

(15,000 ft)

long.

shielded,

twisted

4.3.2.2 DECdataway Controller (ISBl11l) -- One of the DECdataway
nodes plugs into the ISB11 DECdataway controller, which in turn,
plugs into the host computer. This controller manages all
communications between the host and any remote devices attached to
63
to
up
supports
controller
The
cable.
DECdataway
its
remote-device

addresses.

Communication over the DECdataway is synchronous serial at 55,556

bits per second, and is carried out in a block or message-oriented
a
(1)
fashion. Most communications are two-part transactions:

command

message

from

the

host

remote

and,

(2)

response

are
Excepted
the host.
to
back
remote
from the
message
communications from the host to address zero. This address
functions as a broadcast channel for sending command messages from

the host to all remotes at the same time. Remotes are not allowed
to

respond

these messages.

All messages on the DECdataway are formatted in DIGITAL Serial Bus
Control (DSBC) protocol, which makes sure that message content is
not modified during

transmission.

4.3.2.3 DECdataway Connectors -- Each DECdataway has one
controller connector, and from one to 63 remote-device connectors.
The controller connector has only four pins; remote-device
connectors have sixteen.

During

installation,

the extra

pins

the

remote

connectors

are

configured with jumpers that define a device's DECdataway address.
Connectors of devices that use more than one DECdataway address
are configured with that device's lowest address.
4-3

4.3.2.4
are

DECdataway

always

Terminators

terminated

the

-- The

cables

two

DECdataway

characteristic

cable

ends

impedance

(200

ohms)
.
4.3.3

System

Although

are

mentioned
that
DECdataway. This

Remote
not

Devices

concerned

with

them
here,
it
should
be
besides
DISs
attach
to
the
Figure 4-2.

other
devices
was indicated in

If
there were nothing but DISs on the DECdataway,
we could say
that since a DIS uses two addresses, the DECdataway accommodates

them.

numbers

the

But

present,
of

the

interface

since

addresses,

DECdataway

Since

this,

and

not

ISV11-B
to

the

fact,

may

these

other

the

number

always

our

that

true.

devices
DISs

Other

also

that

can

devices may

have

varying

attached

straightforward.

concern

DECdataway,

not

here,
will

and

since

briefly

discuss

DIS's

typical

DIS.

4.3.3.1
Typical DIS -- Fiqure
4-3 shows a typical
DIS.
If you
ignore the block labelled: DECdataway Interface
(ISV11-B),
it is
an
ordinary computer
block
diagram.
It
has:
a
memory
to
store
programs,

receive and
no console,

devices

dispatch data. But a few things are missing: there
and there are no mass storage or boot devices. That

processor

run

the

programs,

where
the
1ISV11-B
comes
1in;
it
takes
devices
that
would
be
needed
if
the

and

I/0

the
place
of
the
DIS
were
not
part

extra

network.

So,

computer
the next

repeat

what

said

the

with a DECdataway interface.
subject for discussion.

outset,

How

that

DIS

interface

LSI-11

works

4.4
FUNCTIONAL DESCRIPTION OF THE ISV11-B
As Figure 4-3 shows, the ISV11-B is itself a computer:
it
processor,
a memory, and two I/0 interfaces. One interface
the DECdataway; the other is to the LSI-11 bus.
4.4.1
ISV11-B Processor
The processor
is an 8@8#¢,
and

and
and

Memory
the memory

combination

has a
is to

ROM

RAM.

4.4.2

ISV11-B

DECdataway

Interface

This
interface consists of
a
Universal
Synchronous
Receiver
Transmitter
(USYNRT)
chip, and a modem.
It responds to commands
from a looping routine in the 8¢84.

Its

function

DECdataway,

1is

and:

demodulate

a
it,

serial,

analog

digitize

its DSBC format, and reassemble it into
also does the reverse of this process.

it,

8-bit

signal

from

disassemble

8088

bus

the
from

format.

MEMORY

8BIT
MP

USYNRT

ISV11 INTERNAL BUS

DECdataway

~ &
ISB11-A (]
|IRSOEIp|

LSI-11 BUS
INTERFACE

e —|——=~—————

LSI-11

INTERFACE

DECdataway

{ISv11-B)

MEMOR

|: <
LSI-11 BUS
53
|
]

1I OPTION 2 l
RPTION
l

LOCAL

>|
I

OPTION n -I
i

Y
1

TASK

INTERFACE

Figure

4-3

DIS with

MA-70818

ISV11-B

Interface

4.4.3
ISV11-B to LSI-11 Interface
This interface consists of: address decoders, data registers, CSRs
and multiplexers.
It responds to commands from either
the LSI-11

bus

Its

function

the

8¢80¢

bus.

convert it to
this process.

8@80

bus

16-bit

8-bit

format

format.

LSI-11

also

does

bus

data,

and

the

reverse

4.4.4
ISV11-B
Upon decoding
a

Operation
specific command
in
its
received message stream
from the DECdataway, the ISV11-B's microprocessor executes one of
the programs stored in the ISV11-B's memory. Among the things that
these various programs cause the ISV11-B to do, are the following.
1.

Down-line
load programs
from the
host
to
LSI-11
Memory
(including
application programs,
operating
systems,
and
diagnostics)

Down-line

load

blocks

data

from

the

host

LSI-11

memory

Boot

the

LSI-11

Halt

the

LSI-11

Run

its

own

ROM-resident

automatically

when

the

4.5
ISV11-B MAINTENANCE
Maintenance philosophy for the

diagnostics

power

ISV11-B

modules).
However,
careful
and
available
test
points

analysis

isolate

the

operates

problem
only

connected

module

are

memory.

These

the

LEDs,
two

(These

option
faults

run

replacement

(both
diagnostics
personnel
to

using

service

modules.

also

on.)

Note

is,

with

the

M8¢8¢

they

are

not

that
and

matched

the

ISV11-B

M8¢84

modules

set;

single

necessary.

series

that

the

they

run

The

continuously

the

number

hardcore

and

tests

are

also

every

run

test

softcore.

one

once

one

run.

only

case

the

Associated

consisting

being

DIS
run

the

ROM

through

the

tests

exerciser.

display,

the

1ISV1l's

time

these

(except

DECdataway

the

(numbered

connected,

tests

diagnostics
the

contained

twelve

automatically

repeat

diagnostics:

tests:

DECdataway

indicates

permit

two

diagnostics

built-in

that

types

However,

conditions).

system-level

that

turned

Diagnostics

are

otherwise

should

unit,

replaced

octal)

on.

error

with

one

on-board

fourteen,
turned
once,

Built-In

There

some

together.

can

4.5.1

four

There

are

Hardcore Tests -- The first nine tests (1 to 11 octal)
4.5.1.1
are called hardcore because they test basic characteristics of the

ISV11-B. An error in any of these
microprocessor
to
loop within
displaying

also

the

means

functioning

communicate,
other

number

properly.

that

devices on

the

that
the

tests causes
test,
thus

the

first-failed

is,

therefore,

DIS's

nine
the

will

test.

communication

DECdataway.

Table

4-1

hardcore

interface

prevented

impair

not

the ISV11-B's
continuously

the

from

1is

error

trying

not

communications

describes

the

hardcore

tests.

Table

4-1

Test

Hardcore

Tests

Module

Description

M8080

This test checks power-up configuration of 8@80
1/0 registers 1 and 2, and does basic 80890
instruction

M8@8 4

This test does individual cyclic
check

M8@84

each

8@98@

and

checks

out

redundancy

ROM.

This test checks writing and
RAM

test.

reading

in the 8@80

RAM addresses.,

This test checks transmission and reception in
USYNRT communications

chip,

using

maintenance

mode.

M8084

the dataway connector

is unplugged

(i.e.,

address 77 is read), this test checks
transmission and reception in the USYNRT through

the modem;

otherwise the test

test checks

M8084

This

M8080

This test checks 8080 I/0 register 2 and 8080
I/0 registers (3--5) that are common with LSI-11
control

M8@80
Both

status

interrupt

registers

system.

(CSR2 and CSR4).

This test checks time-out feature of DMA logic
for

and

ISV11-B

is skipped.

access

LSI-11

This test checks

memory.

LSI-11

interrupt circuit

4.5.1.2
Softcore Tests -- The last three tests
(12,
13, and 14,
octal)
of
the
ISV11-B
ROM-resident
diagnostic
tests
are
called
softcore because they do not stop the
ISV11-B from communicating
with the host. These tests check the operation of the LSI-11 CPU
(processor

and

are

so
fast
softcore
error

memory).

their

Test

numbers

takes

may

about

not

seconds,

noticed

but

the

and

LEDs.

A
causes
the
failed
test
number
to
be
displayed
flashing in the LEDs for 1@ seconds. The error number (in decimal)
is also displayed at the operator's terminal. Table 4-2 describes
the softcore tests.

4.5.2
The LED

ISV11l Indicators
display for the built-in

ISV11-M80#8¢

the

DYS50

fault

this

display.

diagnostics, located on the edge
provides much helpful
information for

board,

analysis.

Figure

4-4

summarizes

the

interpretation

LED

on the ISV11-M8¢84 board flashes when a carrier
is present
the DECdataway. It flashes at a slower rate as carrier activity
increases.

Table

4-2

Softcore

Tests

Test

Module

Description

LSI-11

This test loads a program into LSI-11 memory and
then boots the LSI-11; this checks ability of
ISV11-B

MSV11

LSI-11

interrupt

This

test

runs

words

LSI-11

This

test

runs

loading
LSI-11

the

address

LSI-11

and

data

and

vice

tests

versa.

28K

memory.

LSI-11

it into LSI-11
to run it.

instruction
memory

and

test

booting

the

M8080

:—%

sl T

N A

—

[ o

—
—

ISV

TEST NUMBER

DECIMAL

M8084

DISPLAY*

OCTAL

LSB

MSB

@OOO)

@O @O ) ——— NINEHARDCORE ERROR CONDITIONS:

22
3
2
«
«

O@00O
Q@O0
0000

0000

"11

O
O O®
@ OQO@ )

O . O.

MANENTLY IF TEST FAILS

(ISV11

CAN'T COMMUNICATE WITH HOST)

THREE
SOFTCORE ERROR CONDITIONS.
OCTALNUMBER FLASHES FOR 10SEC
ONDS.

ITS DECIMAL EQUIVALENT

IS UPLINE LOADED TO HOST IF DAT-

AWAY IS CONNECTED. THE TEST

B340
12
14
OO“

GIf ERROR IS ko
12 OR 13, REPLACE

‘ O ..

LSI-11 MEMORY~IF 14, THE PROCESSOR. t
—— NOT USED.

...‘

—— FATAL ERROR-MEANS ISV11
ISTOTALLY INOPERATIVE.

REPLACE ISV11. t
*BLACK = ON

** TEST 13 (OCTAL) LASTS ABOUT 11 SECONDS. ITS NUMBER IS DISPLAYED
ALL DURING THE TEST, BUT UNLESS IT IS FLASHING, THE TEST HAS
NOT FAILED.

t MODULE REPLACEMENT SUGGESTIONS ARE FOR MOST PROBABLE
FAILURES.

OTHER FAILURES MAY SHOW THE SAME SYMPTOMS.

NOTE: THERE ARE TWO NO-ERROR DISPLAY CONDITIONS
1.

IF THERE ARE NO FAILURES, AND THE DATAWAY IS CONNECTED, THE LEDS DISPLAY A ZERO CYCLING FROM LEFT

TO RIGHT THROUGH A FIELD OF ONES.
2.

IF THERE ARE NO FAILURES, AND THE DATAWAY IS NOT
CONNECTED, THE ON-BOARD DIAGNOSTICS KEEP REPEATING. THE LEDS DISPLAY EACH TEST NUMBER AS IT RUNS,

BUT 13 (OCTAL) IS THE ONLY ONE OF SUFFICIENT DURATION TO BE READ EASILY.

Figure

4-4

ISV11l

Display

MA-0104-82

4.5.3
Test Points
This paragraph identifies
test

points.

This

the

locations

information

helps

and

functions

when

ISV11-B

troubleshooting

the

ISV11-B.
Lugs

the
are

for

the

test

points

M8¢80, the three
numbered 4
to 6

points are to
right to left.

the

appear

near

the

left

the

LED

and

4.5.3.1
M808¢ Test Point Description
M808# module test point locations.

Point

Signal

TP4

DMR

TP5

FRPLY

TP6

WAIT

LEDs

test points are to the right
from
left
to
right.
On
the

are

Figure

numbered

Refer

4-5.

of the LEDs and
8¢84,
the
test

Figure

from

4-6

for

4-7

for

Meaning

Internal
H

DMA

request

Failed

receive

Force

8080

wait

4.5.3.2
M80@84 Test Point Description
module test point locations.

DMA

state

Refer

Figure

M8@84

Point

Signal*

TP1

PCS2

TP2

SL5

TP3
TP4

+12
SL5

V
T

TP5

-5

Meaning

BUS

TP6

-12

TP7

TP8

-5

TP9

GND

MEMR

DATA
ENA

8080

H
H

memory

read

USYNRT

serial

USYNRT

output

transmit

enable

modem
to

TP10

SL1

DROPOUT

TP11
TP12

SL1

DATA

SL1

CLOCK

signal

Received
H

dataway

data

Transmitter

USYNRT

clock

from

KHz)
TP13

SL1

Includes

modem

CLOCK

which

Receiver

appears.

clock

USYNRT

(55.556

DIAGNOSTIC

LIGHTS

TEST

POINTS
—

M8080
MODULE

3¢

oo
= e aflf

==—%

L
—
INTERCONNECTING
RIBBON CABLE

TP13
)

DECdataway

CONNECTOR\

CARRIER

M8084

LIGHT

MODULE

Lfiéé#:

]

ISV11-B

Modules

(Edge-On)

] § 1 fiQLWO

4-5

—r

Figure

‘TP4

TP6

\\\QE% oL L
\%flmfifl:fl

;;Dm45
]

DD”

A
=4

.\\;%i

@Jli;;;;fl

—H
[ _1a000000;

o Ul gonndr

Qi{ s /h___zj onnno
Cvfra = = v
N
8080

Figure

4-6

8228

M8@8@

8224

Module

MA-7100

TRANSMITTER

——— e|

[=g

—-

"
r

E—1

-~~~

PROM O

PROM 1%

PROM 2

[le—necarive
VOLTAGE

: O,

CONVERTERS

A ]

0000

1 Op 2O

I .Y
i | o

] o

[] i *Clon]

— ]i

OO0

USYNRT

\\L::lnz 1] s s s s |

pye

LED

il L { by 1]

00 o 1

Jgooooooooooo/

om0
= {1 ]

E?
®eeeee
-

e
|
o

Duugflggflrinm_éggnfi mg‘: =

TP13

RECEIVER

TRV

PROM3

PROM4

SPARE
PROM

SOCKET
MA-2268C

Figure

4-7

M8084

Module

4.5.4
Use
its

Module Troubleshooting
the following procedures to
two modules.

troubleshoot

ISV11-B

Service

personnel can perform most ISV11-B checks with the
installed
because
all
test
points
and
LEDs
are
located
module
edge.
However,
when
it
is
necessary
to
access

points

the

module,

Remove

the

Install

3.
4.

Plug
Let

the

use

the

ISV11-B

following

module

quad-height

M808#

into

the

M8#84

careful

hang

set-up

procedure.

set.

module

extender
(W987).
module extender.
the interconnecting cable.

the
by

CAUTION

nothing

that

components.

that

will

the

M8#84

short

any

touches

its

one

modules

the

internal

4.5.4.1
OQuick Check for Major Problems -- These tests check the
basic functions of ISV11-B modules. They are particularly useful
if the 808% does not run. (All maintenance LEDs are on.) Unless
otherwise indicated, all test points are on the outside edge of
the
M8@84.
Testing
requires a
voltmeter
and
an
oscilloscope
(preferred)

probe.

logic

NOTE

TP7 (+5 V) and TP9 (GND)
power the logic probe.

Using

following

TP9

supply voltages

V +

+12

V +

-12

V +

19%

-5

VB +

ground

can

used

reference,

make

sure

are present.

that

the

TP7

TP3

TP6

-5 VA + 5% at TP8

TP5

Check that the modem transmitter clock, T CLOCK H, is
present on TP12. It is a square wave with period 18 us.
This

test

also verifies

that

the 8088

clock generator

working.

Check that 8080 memory read
present on TPl. This verifies
instructions
that BPOK H

and running.
If not, verify
(E14-12) and READY H (E70-23)

Then

replace

The

carrier-detected

glow)

when

are
BUS MEMR L,
pulses,
that the 8080 is fetching

the

8080

running

on the M8080
are asserted.

(E70).

LED

should

dataway

turn

(dim

connected,

and

bright

turn

off

when the dataway is removed. If the LED stays on, check
that T ENA L (TP4) is high. If
T ENA L is asserted, the
USYNRT chip (E2¢ on the M8@84) or the 8080 program flow
is

defective.

4.5.4.2

Manual

test)

the

unless

the

Modem

dataway

this manual
test
disruption of its
The

test

Test

power-up

Perform

diagnostics

this

fails.

disconnected.

test

Test

Furthermore,

unless the dataway
ongoing activity.

test

does

not

disconnected,

(modem

not

execute
perform

prevent

checks

the

out most of the circuitry interfacing the
USYNRT
dataway.
1In
particular,
it
verifies
the
following

The

transmitter

turns

The

transmitter

transmits

The

modem

The

receiver

The

receiver

chip
to
items.

zeros

analog

one)

The
receiver
detects
detected
(absence
of

and

zeros.

sync

that

locks

the

and

receive

data.

zeros.

the

any

times).

and

transmit

ones

detects

off.

ones

circuits

decodes

following

and

pattern
in

(two

successive
detected.

carrier

pattern

that

transition

drops
1
to

for

carrier
1.5

bit

NOTE

There may be subtle failures in either
the analog or digital circuitry of the
receiver; these can cause occasional CRC

errors

other

may

not

test

suspected,

The

following
)

Two

each
)

Observe
success

tools
6-inch

are

the

be
If

the

ISV11-B.

required

perform

jumpers

with

(or

logic

these

this

failure

replace

carrier-detected

failure.

However,

detected
such

end

Oscilloscope

problems.

failures

alligator

this

test.

clips

miniclips

probe)

LED

after

each

step

determine

Step

Effect

LED

Power up ISV11-B with dataway.

Transmitter idle

Off

Connect jumper 1 from TP4

Transmit 1s

Off

Connect jumper

Transmit @s

Disconnect jumper

Transmit 1s

Disconnect jumper

Transmitter idle

Off

the

DATA

after

scope
S

1
2
3
4
5

test

The

2 from TP2
TP9

it,

repeat

fails,

each

(GND).

step.

Logic @
Logic @
Square wave
Square wave
Logic @
ISV11-B

‘
(18 us)
(18 us)

Logic 1
Square wave
Logic 0
Square wave
Logic 1

DETAILED DESCRIPTION

option

ISV11-B

points

these

observing

with

the

R DATA H (TP11)

R CLOCK H (TP13)

tep

4.6

(GND).

to TP9

ENA L)

consists

two

(18 us)

circuit

printed

quad-height

boards. It is built around two large-scale monolithic integrated
synchronous
LSI
an
and
an 808¢ microprocessor,
circuits:
communications device
(USYNRT).
To understand how the hardware
functions, you must be familiar with the operation of these two
circuits
as
explained
in
the
vendor
manuals.
A
signal
name
chapter.
this
of
end
the
at
glossary appears

Figure 4-8 is a block diagram showing the logical organization of
the hardware on the M8@8¢ ISV11-B microprocessor and the M8@84
serial
1line
wunit.
Logically
the
system
has
three
major
subdivisions organized around two internal buses, one of which is
simply an extension of

left

Figure

4-8)

the

LSI-11

consists

includes the 8080 microprocessor,

circuits,

bus.

This

bus

runs

through

and

both

local

memory

boards,

processing unit to the other two major parts of
interface between the 8088 bus and the DECdataway
Figure

4-8)

unit

(upper

boards.

its associated clock and gating

Communication between microprocessor

8¢98¢

both

local memory.

and

bus.

The processing

elements

entirely

the

M8@84

module.

over

connecting

the

the logic. The
(upper right in

This

subsystem

based on the USYNRT communications chip and connects to the
dataway by a modem. The remaining hardware (lower half of Figure
4-8) is on the M8@8% module. It includes registers, decoders, and
other minor logic elements that connect the 8080 bus to the LSI-11
bus. The LSI-11 bus in turn connects to the LSI-11, its memory,
and

peripheral

equipment.

PROCESSING UNIT

$2 TTL

8224

—>|

SERIAL LINE UNIT

RESET

INT|

[

ack

| ADDRESS

STROBE

L LU

SL3

CONTROL &

[

ADDRESS

5KX8

SL2

RAM

SL6 J2

SL2

pata }

INTERRUPT

PORTAO

1KX8

SLS

BuUS Do-7

KJ
M8084
-

9T-¥

DATA

DMA DRIVERS

PCS 8

[

PORT 2

gOM:TROL

PCS 7

PCS 5.6

[

PORTS

STATUS

PORT 90

DATAWAY

ADDRESS

7x8

SL5

!
)

5X8

SL5

St4

________________________________________

_____

§004
LSt

‘—F, INTERRUPT
CONTROL

PCS 4

]

PORT 1

PORTS 1 & 2
8

2x8

8641

CONTROL

CONTROL LINES

CSRO

PCS 4-7

8080

:cs 7

—

D0-3
‘]

pcss

DE(?C?DERS

o
s

LS 1

MATCH

bces

DCOOS

{/0—15

]

*1 TRANSCEIVERS

B DAL

8A-8F

PCS7

I‘

PORTS

AO-7 §

80-87

SL5

MS080

ADDRESS

PORT BO

[*
8 '

SL1

1&/‘

PCS 2

8080
Bus \

MOoDEM

slsis

CONTROL

DRIVERS [+

USYNRT

L_,

MEM
e

PCS1

SL1.4

PRIORITY

5241

CONNECTOR

INTERRUPT

8228 &

$2 TTL

St4

PCS 2

A0-3

DECODER

8080

DECdataway

CLOCK

pes2

lA3 7

PCS3
CSRO

LS!-11 INTERFACE

INTERNAL LSI-11 BUS EXTENSION

TRANSCEIVERS

PCS 4

_‘

DAL 02

DAL 0-15

PORTE

PORT4

CSR 4

VECTOR

|BUS

DALO-3

PORT3

CSR 2
4|PCcs3

PCS 7
DALO

DALO-3

LS! 1/0 ADDRESSES: 160140 + CSR NUMBER
8080 MEMORY ADDRESSES FOR PORTS: 4000 + PORT NUMBER

MA-2285A

Figure

4-8

ISV11-B

Logical

Organization

The hardware on
each module
appears
in
a
set
of
circuit
schematics, code CS. Each set has a drawing number in the form
X-f-1.
(X is the board designation.) A revised schematic has a

revision letter to the right of the drawing number.

The individual

sheets of each drawing set are labeled for convenient referencing.
For example, the labels on the six sheets of 54-13290-0-1 (M8084
module) are SL1 to SL6, and those on the eight sheets of M8080-0-1

PCS1

are

in signal

These labels serve as prefixes

to PCS8.

to indicate signal origin. They also appear
diagrams for referencing individual prints.

the

text

and

names
block

In Figure 4-8 these labels appear in the lower left corners of
each block to indicate which print contains the logic represented
by the block. Parts of a print are indicated by combining the
letters and numbers along the edges. Paragraphs 4.7 through 4.9
give a detailed description of the hardware on the two modules.
Discussion is geared to the prints, but you should also refer to
Figure

Some

4-8

whenever

necessary.

logic

signals

the

boards

are

available

test

sockets

shown in the lower left on SL6 and the upper right on PCS6. In
some cases the lines to these test pins are not true logic signals
at all, but gate inputs tied to +5 V. Therefore, they play no real
role in system operation; but they can be pulled low to disable
various parts of the 1logic
for GR test purposes.
These pseudo
signals

4.7
This

are

identified

the

prints

PROCESSING UNIT
wunit
occupies
part

both

the

boards

word

test.

and

appears

three

prints:
PCS2, SL2, and SL3.
PCS2 shows the 8@08% microprocessor
with its clock and gating circuits. The 8228 has bidirectional
drivers for the 8 data lines in the 8¢80 bus; the two 74S241ls
below it provide unidirectional driving for the 16 address lines.
The 8224 clock circuit at the left supplies the @1 and @2 clocks
for the microprocessor chip, and the @2 TTL clock for the serial
line

unit.

the

outputs;

places

(All

clocks

beginning

status

are

every

also

sends

information

2 MHz.)

microprocessor

identifying
a

sync

the

machine

signal

cycle,

the

8080

8224.

The

8224

use of the cycle on
to

the

its

responds by sending a strobe to the 8228, causing it to 1load
status into a set of latches.
This frees the data 1lines for
transfers during the cycle. The status information indicates the

kinds of events that occur during the cycle. From the latched
status bits and 808#¢ control signals WR (write) and DBIN (data bus
in),
8228 sets up memory,
I/O control signals, and
interrupt

acknowledgement

for

the cycle.

an instruction, an operand, or an item
A memory read can fetch
from the stack; writing in memory can be for an operand or a stack
item.

Bus

I/0

control

by the

memory control

produced by the 8228

7FFF range

signals

(in

I/0 outputs.

field

However,

signals when

the

print)

the

are

they are also asserted

address

4000

(the area of the ISV11-B address space reserved for I/0

registers).
4-17

The
a

ready

input

the

8088

through the 8224 is high, except when
operation. ENA DMA enables the 8993 SO
WAIT goes low; when the acknowledgement appears
, READY goes
and the 8080 continues. But, the DMA signals have no effect
I/0 WR is true. This prevents an unwanted wait from
hanging

wait

that

high
when

needed

for

DMA

up the 8¢8¢ if DMA signals are generated inadvertently
because an
I/0 operation looks like a DMA operation to DMA
logic.
When the
8080 does
an
input or
output
instruction,
it
puts
the one-byte
address on both the
upper and
lower
half of
the
address
lines.
Therefore, an I/0 port address of 88 or above puts a
one on 1line
15,
which
may generate
ENA
DMA.
The
I/0
WR
prevents
any wait
during an IN instruction; however, the I/O WR occurs later
dur ing
an

OUT,

and

the

8@80

may

enter

the

wait

The RAM and ROM that constitute local
respectively.
The
RAM
is
made
up
of

storing

state

for

memory

are

eight

produce

memory

select

when

the

8080

calls

SL3

least

inputs

select

single

ROM

significant

all

chips

chip

address

select

the

bits

the

set

are

on
1

SL2

cycle.

and

chips,

ROM

SL3

each
up of

is made
each
storing
upper left on

for

memory

the
SL2

read

The select, in turn,
at the lower left on

eight

applied

individual

single

a single bit of each byte in the 1K. The
five
1K X
8
chips
(with
space
for
a
sixth),
entire byte for 1K locations. Logic gates at the

write with an address in the ¢ to 1FFF range.
enables the decoding of address bits 10 to 12

RAM

chips.

the

location.

The

address

When

the RAM is selected and the function
is write, bits from the
eight data lines are written into the eight
RAM chips. The output
of
the
selected
ROM,
or
set
of
RAMs,
is
available
on
the
SL3

memory

bus.
During a read, the data is placed on the 8¢8¢
bus via
multiplexer at the upper
right on SL2.
Drawing TD-ISV11A-g-7
shows the timing of the signals involved
in the 8080 reading and
writing memory.

the

4.8
The

SERIAL
heart

LINE

this

UNIT

unit

is
the
USYNRT synchronous communications
chip at the left on SL5. It is set up for byte
operation by a high
level at pin 22 and connects correspondin
g pins for the left and
right bytes of
its 16 data
inputs-outputs.
These connect to the
eight data lines of the 8¢8¢ bus. The 8080
governs the device by
supplying
control
bytes
and
reading
status.
The
USYNRT
in
turn

uses
the
modem
for
handling
communication
over
the
DECdataway.
Serial
data
received
from
the
modem
at
assembled into bytes, and available
to the processing unit

eight

data

passed

The
Port

The

8080

1lines.

moves

selection

number

generated

Transmit

serially

of
by

appropriate

bytes
is

the

made

ports
either

address

and

is
an

bytes

modem

from

the
I/O0

the

and

over

data

via

the

lines

are

TSO.

address

small,

range.

supplied

from

serial

RSI

interface
decoder

transfer

Therefore,

via

I/0

bus

memory

decoding

its

the

control
a

I/0

right

SL4.
signal
is

access

few

ports.
on

1in

the

address

bits

and

I/0

the

signals

90,

A#,

into the DECdataway connector

and

sufficient

B@, and the USYNRT registers.

select

among

ports

From port Bf the 8¢8¢ can learn its

own dataway port address, wired

available through the gates at the left. SEL 8X enables the USYNRT

data

lines.

Selection among various registers is made by address bits @ to 2,
applied to the USYNRT address inputs on SL5. Register reading and

writing uses separate addresses, so A@3 is connected to the USYNRT
write input. A one enables writing and drives the USYNRT data
lines from the 8@8@ bus through the two 74S241s at the lower

right.
from

When a

the

zero

address

places a

decoder

drives

the

808¢

the data
bus

from

lines,
them.

READ 8X

The

E30

gate below the decoder on SL4 prevents any register selection if
the 8080 should give a read function for a write port.

The remaining two ports are at the upper right on SL5, where
address 98 reads status bits from the USYNRT and modem, and the
LSI-11 interrupt request through E22. Address Af@ loads a byte from
the 8080 bus into the register in E27. The control bits supplied
include enables for transmitter and receiver in the USYNRT
maintenance mode, and for various conditions
interrupts through gates at the upper right.

that

can

request

Selecting maintenance mode inhibits generation of the transmit
enable to the modem (T ENA at CI), even if the USYNRT transmitter
is active (TX ACT). The interrupt request levels are applied to

the latch and priority network at the upper left on SL2. Any
interrupt request produces the INT signal, which goes to the 8084.
An acknowledgement from the 8088 latches the current request,
enables the multiplexer for the SL2 bus (8080 bus data lines), and

selects as multiplexer input an RST instruction encoded from the
number of the highest priority request. The 8988 then executes the
RST as a call to the corresponding location (as listed in the
lower

right on SL5).

table at

the

4.8.1

Serial Transmitter-Receiver

The modem for the serial line unit takes up most of SL1. The basic
time reference is the @2 TTL clock supplied by the 8224 clock
circuit associated with the 8¢8¢ microprocessor. This clock drives

the receiver directly. For the transmitter, the exclusive OR gate
at A7 (with the delay introduced by two inverters at one of its
inputs) acts as an edge detector to multiply the basic clock to 4
MHz. From this, the E28 counter produces the 8X clock by dividing
by nine. This is accomplished by loading 7 at the clock following
the carry out produced by a count of 15. The 8X clock counts the

E23 counter, which runs on a continuous l6-count cycle so that its
two middle bits provide division by 4 and 8. The T (1X) clock

drives the USYNRT transmitter and shifts out the data; the 1X and
2X clocks together are used for biphase encoding of data
transmitted over the dataway. Table 4-3 lists characteristics of
the various clocks.

Table

4-3

Clock

Characteristics

Clock

Period

TTL

B.50

CLK

2.25

444,444

2X CLK

9.@@

111.111 KHz

18.00

55.555

CLOCK

The

modem

(us)

Frequency

coupled

DECdataway

transformer

serial

pins

internal

connects

dataway

connector.

positive

from

the

input.
output

The

two

line

transformer
generates

two

the

and

T1;
18

1-1-1

output

its

the

type.

trains,

the other negative; both have the same amplit
ude
The transmitter uses only one primary coil each way,
is a 5 V signal, either positive or negative.

Zener

connector)

draw

The

line

and

the
the

they

KHz

the

winding

train

KHz

the

secondary

pulse

MHz

draw

diodes
no

great

burning

out

the

Zeners

limit

back-to-back

current

deal.

until

This

the

potential

prevents

operational

output

(shown

the

surge

amplifiers.

During

even

the

though

left

reaches

one

as
so

the

then

dataway

from

transmission

the

transmitter

circuit

output is about 12 V.
There is an effective 10# ohm load with the
dataway connected.
This is due to either the 208 ohm terminating
resistor being in parallel with the cable or
mounted in the middle
of
the
200 ohm cable.
Therefore, the line is actually driven at
about 5 V.

The

only

ENA

one

false,

control

supplied

the

USYNRT

true,

the

modem

When

side

or the other to drive the serial
line. When T
transmitter is disabled, and the receiver picks

the

data

coming

The

disable

outputs,

allow

signal

D8.

external

from

are

for

this

the

and

inputs

external

the

disables,
data

can

the

available

the
be

inputs,
the

clock

the

test

and

substituted

external
at

primary

can

DECdataway.

available

disabling

raw

signal

the
for

connections
test

well

socket

socket.

raw
then.

make

as
on

various
SL6.

received

the

circuit
inputs

data;

internal

ENA is
up any

Test

Conversely,

driven

then

without

clock

and

enters
USYNRT
the
from
Data
-Transmitter
4.8.1.1
clock.
T
transmitter circuit at E31-13 (C8), ANDed with the

the
The

the

other

the

are

two

The

circuit

senses

voltage

drop

gate keeps the J and K inputs to the E12-5 flip-flop high, except
when the data bit is one and T clock is high. Therefore, a zero
enables JK for the whole bit period, and a one enables it for half
the bit period. You can see this in Figure 4-9, which shows the
relationship between data,
flip-flop signals,
and
transmitter
clocks. The flip-flop toggles twice during a zero bit, but only
once during a one. The state of the flip-flop drives one side or
primary.

Therefore,

there

zero-crossings during transmission of a zero on the dataway, but
only one during a one. This is the so-called biphase modulation
technique of data transmission.

slightly,

is failing,
sending data

4.8.1.2

the

Should

Q4 conducts and disables T ENA.

the transmitter
1is disabled
(which may be invalid).

Receiver

Changes

the

Therefore,
even

current

flow

primary are sensed by the receiver circuit (shown
SL1). A switch in direction, caused either by
(secondary)
or transmitter, reverses the state
outputs (shown at the upper right). A string of

if the power

the

USYNRT

through

the

1is

TI1

at top-center on
the serial line
of the raw data
logic components

is shown from left to right, across the center, and in the lower
right of the print. These logic components process this raw data
to detect the start of message, derive data bits and a clock to
pass on to the USYNRT, and detect a dropout of the received
signal. The logic is driven by the 2 MHz @2 TTL clock, which runs
at 36 times the bit rate of the dataway. Therefore, the clock not

only synchronizes the raw data to the ISV11-B, but also provides a
for

sampling

it.

L
T DATA H

@x i

(2X CLK L)

(E12-5)

[

E12 JK

TRAWDATAH

|
|

Figure 4-9

e rrd

Transmitter Timing

resolution

finer

MA-2286

Figure

4-190

components

is
in

simplified

the

print.

The

dual

dataway

applied

same

signal
to

gain

+1
and
high
resistors prevent

dragging

pair

by
for

turn-off

receiver

the

operational

impedance

power

the

position

generated

input

diagram

relative

they

with

appear

primary

amplifiers.

most

the

from

the

These

have

isolation.
The
56K
input
the
ISV11-B
receiver
from

down

the
dataway.
The
bandpass
of
the
filters
at
the
outputs eliminates both high and
low frequency noise,
attenuates the signal to about one third.

amplifier

For

generating

minimum

mV;

this

dataway

occurs

only

after

having

been

the

clock

]

raw data, the threshold comparator uses a referen
ce
guarantees the spec of 10¢ mV, one-third of the 3008

signal.

when

the

been

negative,

signal

positive.

Changes
flip-flop.

the

comparator

above

the

positive

below
in

the

outputs

threshold

the

negative

threshold

raw

data

synchronized

are

after

THRESHOLD

LTER

FLTER

switch

goes

COMPARATOR

|
y

SYNCHRONIZER

VOLTAGE

REFERENCE

but

RAW DATA H
TRANSITION
DETECTED

~LSBIN

TRANSITION

PHASE

DETECTOR

COUNTER

HISTORY

SAMPLE

—"linpuT
CLK

TURN
OFF

SHIFT

LD
— CNT EN

0—
TRANSITION

CLK

TRANSITION

5 1L RpATA L

CARRY |
OUT

CLK

DLYD

$2 TTL H

+3V
—D

—
a

1po—RcLOCK L

—Qqc

PHASE

DROPOUT H

COUNTER
o

Celr

CLK
CNT
EN

CARRY
outTH

MA-2287

Figure

4-19

Receiver

Simplified

Block

Diagram

The logic shown across
three
main
parts:
a

the lower part of Figure 4-10 contains
transition
detector
at
the
left,
a
phase-locked clock generator, and a shift register for recording
recent transition history in raw data from the receiver circuit.

This

history

is necessary for

recognizing

the

start of message

modem dropout.

It also distinguishes between zeros and ones

received

data

timing of major

supplies

the

USYNRT.

and

in the

Figure

4-11

shows

the

followed

by at

least

two

signals associated with this transition processing

logic.

A message

always

starts

with

several

ones

zeros for synchronization. Figure 4-11 shows signal configuration
for a message beginning with 108, followed by several arbitrary

bits,
three

and then a modem dropout. The transition detector generates
signals associated with a transition in the raw data.

Following synchronization of a transition, the first 2 MHz clock
produces the transition-detected signal. This is on for two clock
periods; during that time it turns off the detector to inhibit
further sampling of the raw data. This filters out noise near the
modem comparator
threshold,
preventing
any noise surrounding a
transition from being mistaken for another transition. The second

signal,

detected;
clock

transition
however,

delayed,

has

opposite

the

same

polarity

form

and

transition

offset

one

period.

The difference in these two signals is that transition detected
inhibits
the
detector
(resetting
the
phase
counter),
and
transition low actually represents the transition for processing
by
the
remaining
1logic.
The
third
signal
from
the
detector
produces
the
phase-locked
clock,
which occurs
at
the
end
of
transition

detected.

aw oATA

o /

T————————————————r

masmonoe

—

Figure 4-11

Receiver

Timing

MA-2288

The
of

phase

counter

reaches

reset at every transition, but in the absenc
e
simulates the phase-locked clock every time
it
The
Ts
and
Ns
in
the
timing
diagram
distinguish
clocks
produced
by transitions
(T)
from those
that

transitions

3f¢.

phase-locked

are

not

(N).

for

Figure

serial

4-11

signal

from

can

quite

Each

late

illustrates

the

without

phase-locked

clock

bus.

adversely

shifts

the

bit shifted into the register
of a transition causes a zero
been
idle,
the
phase-locked
consecutive

dropout

transition

flag,

turning

represented

USYNRT

the

The

from

USYNRT

the

samples

represented

phase-locked

exact

real

reception.

transition

history.

one

succeeded

LED.

that

line

From
the

position

incoming
and

Where

the

reflects transition low, detection
to be entered.
After the line has
clock
that
occurs
at
the
fifth

the

arrows

timing

transitions

affecting

bit

theoretical

situation,

bottom

second

the

data

the

at
at

the

clears

on,

the

available

history

the

clock.

zeros)

point

diagram

occurs

two

shift

which

edge

The absence of two transitions
turning off the receiver clock.

the

clock,

trailing

the

data

the

row

sets

the

dropout

The
the

above discussion should provide a basic understanding
of what
receiver does, and how the
incoming data is supplied to the

USYNRT.

the

flag,

But

circuit

understand

schematic

(print

detail

SL1)

how

and

the

logic

works,

turn

complete

timing

diagram

(TD-ISV11A-0¢-8),
which
show
all
associated
signals.
synchronization is provided by flip-flop E8-9 located at

print.

The

transition

detector

each

and three exclusive OR
clock shifts the register,

When

low,

each

clock

inputs;
but
these
ignoring
the
raw

the

left

made

Raw
B3

gates.

data

the

shift

high,

When pin 9 of El1l
sampling the raw data at

the

LSB.

loads

the

data

the

from

are
connected
so
the
register
still
shifts,
data.
Therefore,
each
transition
is
shifted
through
the
register,
giving
a
sequence
of
signals
through
the
exclusive OR gates.
E9-11

and

E9-6

are

transition

detected

and

transition

from

E11-13

delayed.

These gates are driven from pins 13 and 15, and 11
respectively
(not 14 of El1), so they generate signal trains with on times
of
two
clock
periods
(E9-6
offset
by
one
period).
E9-8,
which

generates

thus

Binary
E3

the

phase-locked

occupies

the

counters

plus

after

doing

so.

and

then

fed

MHz

count

counts

detected

phase-locked

clock

clock
of

and

transition-delayed

15,

goes

the

off,

carry

3¢

clock

but

out

the flip-flop. This disables E3 and
continue the count. When El1 reaches 15

phase-locked
a

the

11,

and

time.

and El are confiqured for a count of 36, 17 in
Detection of a transition clears E3 and sets an
flip-flop (E8-5). This allows E3 to count the 2 MHz

transition

When

produces

sets

out

clock,

half

El.

enable-disable

clock

second

inhibits

loads

enables

(total

and

clears

the

restart

the

count.

clears

occurs

each

without

three
El,

39),

from

into

which

the

EI
can

carry

flip-flop;

the

Therefore,

transition, and also when
transition.
E15 is the history

there
shift

Initially the

E11

bits

are

alike:

E9-11

low,

which

causes

the

MHz clock to shift Ell; E9-8 is high, so the phase-locked clock is
low; and E9-6 is also high. When the raw data changes, the next 2
MHz clock shifts Ell. This causes pin 15 to differ from the other
three outputs. In particular, pin 15 differs from pin
goes high, enabling
the load function at both El11 and

13,
E3.

E9-11

"The first clock after detection of the transition loads zero into
E3 and shifts El11 without sampling the raw data. That is, pin 15
remains the same and the transition lies between pins 14 and 13.
With this change, E9-6 supplies a low input to E15 D@ and E2 J.
The second clock loads again, moving the transition between pins
13 and
11.
This causes
E9-8
to drop,
producing
a
phase-locked
clock which shifts E15 and loads zero into El15 R@ since E9-6 is
still low.
E9-11

also

clock

then

drops,

data
E9-6

and
and

were

detected,

sequence

which

counts

reenables

one

shifting

and

shifts

El1,

and

counting.

The

resampling

third

the

raw

shifting out the preceding transition. This raises both
E9-8, dropping the phase-locked clock.
If a transition
E9-11

would

again

high

and

start

the

whole

over.

Serial line transmission always
at
least
two
zeros.
The
final

begins with a few ones followed by
one
and
the
two
zeros provide
a
string of five transitions, a half bit time apart.
Following the
just
defined
procedure,
you
can
see
that
the
first
four
transitions
result
in
four
zeros
being
shifted
into
E15.
This

enables
E2.
At

This

the
the

AND gates at the clear
fifth transition,
the

removes

both

the

hold-clear
on
flip-flop
USYNRT receiver.

dropout
E12-3,

input to the
phase-locked

signal

generating

dropout flip-flop
clock
clears
E2.

the
the

USYNRT

and

the

clock

for

the

Once the system is synchronized to the incoming serial signal, a
transition that occurs before a count of 30 following a preceding
transition produces a phase-locked clock that loads a zero into
E15.
If there is no transition by clock 29, clock 38 counts E3 to

15,
one

and the carry out produces a phase-locked clock that loads a
into E15
(since E9-6 is high). But subsequent detection of a
transition before the next 29 count (restarting the count with no
transition detected ships the extra load) generates a phase-locked
clock
that
1loads a
2zero
into
El15.
Therefore,
a
zero
data
bit
causes
the
1loading
of
two
successive
2zeros
into
the
first
two
stages of E15.
A one
results
in
a
following a pair of shifts. Thus, at
state

represents

the

received

2zero
in
RJ
and
a
one
in
Rl
the end of each bit time, the
data.

Since at this time R@ is zero for either a zero or a one data bit,
trailing edge of the phase-locked clock sets El12-3 to start a
cycle
of
the
R
clock.
Since
the
K
1input
1is
held
high,
the
flip-flop clears in the middle of the next bit time regardless of
the

what the first phase-locked clock brings into R@. The first data
bit the USYNRT actually reads is the second zero in the sync pair.

4-25

If no transition is detected through the fifty-eighth clock, the
fifty-ninth counts E3 to 15 a second time. This produces
a second
nontransition phase-locked clock.
With E9-6 still high and a one

already in E15 R@,
this sets
disabling the receiver clock.

E2,

indicating

modem

dropout

4.8.1.3
Negative Voltage Converters -- The circuit at the
provides
one
-12
V and
two
-5
V supplies
from
+5

SL6

separate

-5

requirements

Each

-5

saturable

supplies

core

necessary

for

handling

the

consists

transformer,

inverter

negative

large

oscillator

rectifier,

left on
V.
Two
power

using

filter,

and

a
a

regulator
chip that produces
the
regulated -5 V.
frequency is about 4@ KHz. The transformer primary has

Oscillator
a

are

PROMs.

converter

three-terminal

square

the

and

square
wave

wave

centered

approximately

-8

ground.

the

Filter

secondary

output

has

the

regulator

V
is

The -12 V converter uses the 9 V square wave across the T3 primary
to drive a charge pump
(C55, D1¢, D11, C56).
The pump output is

superimposed

unregulated

-17

diode
To

-8

this

rectified

secondary output to
converted to a regulated -12

D12.

prevent

oscillators
separate,

plane

separate

1large

from

1inner

single
4.9
This

the

layer

decoupled
ground

instantaneous

coupling

ground

from

plane

into

the

the
and

main

switching

currents

main

supply,

plane

connected

produce an
V by Zener

planes.

the

an
main

The

1in

the

they

have

separate

filter,

ground

and

plane

point.

LSI-11 BUS INTERFACE
unit
handles
all
communication

transfers,

and

processor

and

interrupts)
memory.

between

The

(programmed
the

ISV11-B

bidirectional

transfers,
and

LSI-11

the

bus.

However,

JAV inputs
inputs are

to drive
connected

the

DAL

DMA

internal

bus

the

input
is enabled
for
driving
the
LSI-11
bus
from
its
during one of two events: when the LSI-11 is reading a

control status register
address or data to
the
times the REC
input
is

LSI-11

extension
(PCS4
DAL)
interfaces
to the bidirectional
LSI-11
data and address lines
(B DAL)
via the DC@@5 transceivers at
left on PCS4.

The
XMIT
extension

V c

tHS&

lines,

where

(CSR),

or when the ISV11-B is sending DMA
LSI-11 memory or
I/O bank.
At all other
enabled,
driving
the
extension
from the

enabling

the
for
a

REC

LSI-11
VECTOR
jumper

also

allows

high

levels

the

bus
lines
independently.
These
to place an interrupt vector on

one.

When the I/0 bank select signal BS7 is true at E23-13,
the JA
inputs are compared with levels on certain LSI-11 bus lines. The
lines
are
not
connected
to
the chips
in order;
this allows a
comparison between JA inputs and bus lines
3 to
12.
The match
output is true when BS7 is true and bus lines 3 to 12 contain the
address of the ISV11-B CSRs set into the JA jumpers. A jumper in
is

one.

Type 8641
transceivers are
used
for
interfacing
to
LSI-11
bus
control signals (usually bidirectional). These transceivers appear
on
various
prints,
next
to
the
1logic
with
which
they
are
associated.

Port Transfers
4.9.1
Programmed transfers are

16-bit

control

status

handled

registers

through

from

the

what

LSI-11,

are

regarded

and 8-bit

ports

from the 8@80 microprocessor in the 1ISV11-B. Furthermore, since
addressing
is
from different buses and
the
I/0 banks occupy
different parts of the processor's address spaces, there are two
completely separate address decoders.

The

LSI-11

decoder

standard

DC@@4

(PCS4

right)

enabled

matching the ISV11-B CSR jumper address with the address supplied
on the B DAL lines. Bus control signals come to the DC@@4 via the

transceivers on PCS6, since the same signals are also involved in
DMA control. The sync latches the three least significant address
bits, which are decoded for selecting the CSRs.
(Select signals
are backward, since high levels are applied to the DAL inputs.)

For

output,

The

LSI-11

DOUT

generates

low

high

strobe,

byte

both,

depending on DAL @ and whether WTBT selects a byte or whole word.
For input, DIN gives an INWD strobe. Both the address latch and
the data strobe produce a bus reply through the 8641.

(TCB)

wvia

lower

right

ISV11-B

via

supplies
the

CSRs

CSR@,

corner

the
on

when
on

address
PCS3.

PCS7

one

The

the

only

DAL

request

transfer

other

sets

an 8@80

control

data

the

comes

flip-flop

interrupt.

block
to

The

the

gate

just above provides a read strobe for CSR@, allowing the LSI-11 to
read its own interrupt request and other status information via

the

74LS367

(E7)

purposes

the

address

space.

Decoding

ISV11-B

addresses

the

can

1lower

load

8080

the

ports

1left

corner

CSRs

via

I/0 page

the

LSI-11

PCS8.

bus

For

test

LSI-11

interface

accomplished by the logic at the top on PCS7. There, address bits
@ to 2 are decoded to select the port on an I/0 function when bits

3 to 7 are all

zero.

Only ports 1 and 2

(the E39 and E36 registers

below the decoder) can be written by the 8086, and for these the
select lines also generate write signals on an I/0O write. From
these two ports, the only bit the LSI-11 can read is boot status
(port 1 bit 1)
through CSR@. Setting and clearing port 1 bit 7
boots the LSI-11 by simulating a power-up signal on the DCOK 1line
of the LSI-11 bus. To halt the LSI-11, port 1 bit 6 is handled by
a separate flip-flop, so it can also be set by a power failure.

Port
to

bit

clear

Port

used

The
E4¢0
5

included

interrupt

the

request

port

2 bit 4 do
interrupts
at

flip-flop

not

show

up
LSI-11

the

discussion.

can

other

read

most

bits

from

interrupt

multiplexers

correspond

and

not

@ and
request

8080

few

is
LSI

bit

following

the

CSR4

the

what

left.

three

supplies

and

Port

bytes

the

LSI-11

Interrupt

used

right.

here

at all; they
described
in

ports

are
the

and

plus

control,

via

the

E38

and

not

used;

ports

and

address

the

TCB

(PCS3).

4.9.2

lower

DMA

because
at

CSR2,

CSR3,

Control

requests

from the 8080 to the LSI-11 are handled by the
dual-interrupt circuit at the upper right on PCS4.
The 8080 can make requests on two levels, A and B, associated with
vector
locations 300 and 3@4
respectively in the LSI-11.
Request
inputs to the DC@@3 are held high, so making and dropping requests
on levels A and B respectively, are under writing control in port

standard

DC@@3

and

bit

port

bit

(LSI-11

the
A

bus A and B)
M8¢8¢ via ports 1

request

LSI-11.

BIAKI,

bus

made

Once

the

and

LSI-11

bus

ROST

puts

the

interrupt

referencing

any

DMA

memory,

(PCS7

level

asserts

responds

with

the

DIN

via

BIRQ

and

the

requests

CSR@,

and

signal
to
the
acknowledgement

disables

zero

level

B4),

which half of
the
8080
bus

line

two,

depending

the
8080
address
space
is
section of the LSI-11 address

Before

808@

must

address

bit

the
is

32K-byte

transfers.

the

one

A or

4.9.3
DMA Transfers
The
upper
32K-byte
half
of

interrupt

LSI-11

BIRQ and asserts VECTOR. This produces a
the DC@#4 below and places the vector address on
via the DC@@5 JAV inputs at the left.
The signal

the

28K

current
the

through

VEC

means

of
to

either

LSI-11

DC@@3

Status

available

initiating

set
15

up
on

used
for
space by

any

DMA operation with a
which
is port
2 bit
@
LSI-11
bus.
This
indicates

15,

the

LSI-11 address space is referenced when
one.
Then,
the
8¢8¢
simply
makes
a

reference

the

upper

selected

half

the

half

its

whether

own

Al5 on
memory

space,

to
reference
the
DMA request and control
logic on PCS5 and PCS6.
(A 124K memory would require that AD 16
and AD 17 be set up as well.)
The 8080 must also set BS7
(port 2

LSI-11

space,

using

bit 3)
if the address location lies in the I/0 bank. Two timing
diagrams,
TD-ISV-11A-0-5
and
TD-ISU-11A-9-6,
show
the
relationships among the various quantities involved in output and
input DMA transfers: LSI-11 bus signals, control signals for the
8080,
the
898@
clocks,
and
machine
states.
An
R
or
T
1in

parentheses

transmitted
Addresses

drivers

and

the
data

PCS8.

signal

name

ISV11-B

over

move

between

The

signal

the

ADDR

means

LSI-11

two

received

via

the

bus.
buses

places

the

address

74LS367

the

LSI-11 bus through parts of the driver chips at the left. However,
only 15 bits come from the 8¢88 bus address lines; bit 15 (A8)
comes from port 2 instead. Each data transfer is a single byte,
with the low or high position on the DAL lines selected by A@#.
Data is gated from the 8080 bus to LSI-11 bus by T DATA EN, with
the low byte handled by E68 and part of E46, and the high byte by

E51.

E59 and part of

from

Gating

8@8¢

LSI-11

bus

range

the

bus

controlled by a DMA signal derived directly from the 8080 memory
read, with the low byte handled by E61 and part of E7, and high
byte

by E52 and

8080

memory

part of

ES51.

reference

the

8000

FFFF

produces

ENA

DMA at the upper left on PCS5. This causes the 8080 to wait by
pulling down the 8224 ready input on PCS2. On PCS5 it generates

the appropriate DMA memory read or write level, and a DMA request
that goes out on the LSI-11 bus and also clears flip-flop E15-9 at
the lower left. When the LSI-11 sends the DMA grant in, E12-5
sets, preventing the grant from passing out to the next device.
With the grant on, negation of both the sync and the reply at the
end of the current bus cycle sets E12-9. This generates SACK on
the LSI-11 bus to acknowledge that the ISV11-B has become bus
master; it also drops the request, following which the LSI-11
grant.

the

drops

The acknowledgement also triggers a timing circuit based on shift
register E9 at the upper left on PCS6. SACK sets E19-5 to feed a
the output of

the

E17-8 AND

after SACK goes true. Since the setting of
the clock provides timing for the transfer

E9
by

RO clears
passing a

into

one

LSB

the

and

causes

gate to go low. The output of this gate is fed back to one of its
inputs. This makes the output oscillate, which supplies a
rising-edge clock with a period of 110 ns beginning about half a
period
E19-5,

single one

through the shift

one,

This moving
at

the center

in turn,

controls the column of

of the drawing.

flip-flops shown

in R@ sets T ADDR EN to place

the

address on the LSI-11 bus, and to gate the state of BS7 from port
2 onto the B BS7 line. This indicates whether the transfer is for

memory or the I/0 bank. At the same time a write function turns on
T WTBT to specify an output byte. Time 330 turns on T SYNC, and
time 440 clears T ADDR EN. For writing, 440 also sets T DATA EN to
gate the byte onto the LSI-11 bus, and 558 turns on T DOUT to make
the slave accept it. But for reading, 550 turns on T DIN to tell

the slave to send data; the read level itself gates the DAL lines
onto the 8980 bus, with the transfer time determined by the slave.

With SACK still asserted, the reply from the slave produces the
The freed 8080
that frees the 808¢.
(C7)
DMA acknowledgement
negates the memory signals, negating DMR (PCS5). DMR then cancels
either T DOUT or T DIN, whichever is on. Finally the trailing edge
of RRPLY triggers an identical reset timer based on shift register

El@.

on);

SACK.

Reset
it

time R11¢ turns off T SYNC,

also

sets

E15-9

(at

the

lower

T DATA EN, and T WTBT

left

PCS5)

turn

(if

off

Each
at

request

the

triggers

bottom

prevents

the

clearing

right.

However,

slave

the

sets

the

8¢8¢.

sets

the

PCS6.

from

should

the

generate

When

one-shot

Completion

FRPLY.

affecting

the

time-out

E15-5

circuit

clears

and

flip-flop

the

time out, it indicates failure
reasonable
time;
then
the
flip-flop

signal

produces

DMR

4.10

FUNCTIONAL FLOWS
4-12

through

4-17

show

functional

the

flow,

elements

that

is,

that

into

their

labeled

for

enter

the circuit
the
trouble,

pinpoint
elements that

play

system's
as

on
figures

the

execution.

schematics

role

the

DMA

ACK

free

flows

are

major

signal

All

also

operations

paths

logic

and

logic

elements

are

which

they appear. To help
identify
all
significant
operational sequence. You can

in a given
turn
to
the
referenced
schematics
signals, and pin connections.
then

These

the

transfer

one-shot

This

Figures
of

subsequently goes off, it clears FRPLY but
triggering the reset time to clear the DMA logic.

E19-9,

terms

for

details

circuit,

meant

to
stand
alone;
no
written
description
since
the
detailed
description
of
the
logic,
schematics,
has
already been
presented.
All
lines
are

accompanies

them

geared

labeled

with

the actual signal names from the schematics; wherever
the logic elements are represented by the symbols in
the
schematics.
It has,
however,
been necessary in some cases to use
ordinary blocks
as
logic
elements.
These
are
easily
identified
because the signal lines entering them have arrowheads.

possible

None

the

diagrammed

operations

comprise

only

single

sequence

response

of events.
Rather,
each is made up of several logically distinct
but interdependent sequences, such as an 8¢8@ instruction
followed
in
order
by an
interrupt and another
8¢8¢
instruction.
Another
sequence

from

the

8@8@

LSI-11

instruction

and

circles

indicate

employed

for

power-up

diagnostics

The

these

the

followed

action

order

the

which

sequences.
are

order

ISV11-B.

the

The

hardware

Sections of the hardware
labeled with test numbers.

numbers

parts

are

tested

six

flows are in three pairs, and all operations shown involve
microprocessor.
The
first
two drawings show the movement of
information in either direction through the serial line unit. The

the

pair
show DMA transfers
through
the
LSI-11
bus
interface.
Figure
4-16
shows
an
ISV11-B
interrupt
request
to
the
LSI-11.
Figure 4-17 shows an interrupt request in the opposite direction
,
the only operation that uses elements of both interfaces in the
ISV11-B.
There are many other minor operations,
such as the 8@8¢

reading

You

easily

can

operations

writing

port,

identify

directly

from

and

the

components

the

circuit

LSI-11
that

making

enter

schematics.

into

CSR transfer.
these

simpler

PCS1J 1

SL6 J2

8080

ETC.

PCS 2

INT H

INTERRUPT | |INTRQ 5 H

BUS INT ACK L

PRIORITY

LATCH &

(TEST 6)

ENCODER

TBMT H

SLs [

PORT
A0

MAINT)
L
SLs

——
TX ENA

DRIVERS
PORT
SL6

CLK

TX ACT

| R %t4

BUS DO-7H

BUS VOW L

SEL AO L

DECODER

SEL

ADDRESS

e BUS A045.7 H
|

A00-03 H

PORT

sLa

]

X H

SL5

A03 H

TRANSMITTER

USYNRT

CIRCUIT

(TEST 4)

St1

DP ENA
ADR SEL 0-2

SL1

(TEST 5)

WR
TX CLK

SL6

TSO
T DATA H

CLOCK

.\_/

T CLOCK H

SL1

2X CLK H

SL1

COUNTERS

$2 TTLH

TM (x2+9+48)
SL1

SL1

Figure

4-12

Serial

Line

Out

MA-2289

PCS1 U1

slez2

INT H

INTERRUPT |

8080
ETC

BUS INT ACK L

PCS 2

LATCH &

»|

PRIORITY

T
SEL

TEST 6)

+3V

SL2

o/C

PORT

RDA H

ce-¥

BUSDO-7 H

|BusiowlL

|BUSIVORL

BUS A03-07 H
[

SLS

SL5

CLK

»| RX ENA
DRIVERS

USYNRT

PORT

(TEST
4)

PORT
ADDRESS

(::) _ DECODER

SEL AO L

RSA

T
®

SL5

+3v—D

INTRQ
6 H

ENCODER

(e
SL5

SL2

DROPOUTL >HORRSAH /|-

|nT RQ 7 H

SL5

- (::)

READ
8X L
SL4

ACO-03

SEL 8X H

DP ENA

H
ADR

[SL5

SEL

RSi

RX CLK

R DATA L
R CLOCK L

|$2TTLH

_| DETECTOR,

(TEST 5)

| DROPOUT
H

RECEIVER

CIRCUIT

°
HISTORY.ETC

SL1

)

RAW

DATA

)

TRANSITION

SL1
MA-2290

Figure

4-13

Serial

Line

DMA MEMW H

DMA ENB H

MR H;

SACK L

BUS MEMR L

RDY
8080

»{pcs 5

8DMGI L —»

BUS A15 H

ETC

Fes 2

PCS 5

SACK

DMA

GRANT

B SYNC L PCS 6

560 H

BDMGO L
RARPLY L

PCS 4

330 H »|DMA

TIMER [
PCS 6

——B8 DOUT L

cONTROL|— B SYNC L
= B WTBT L

PCS6 |
PCS B—Y{poa\

B RPLY L —O

DMA

—» PCS 5
Y

L
PCS 5YD— B SACK

PCS 5

L
DMR

PCS 6

DMA ACK H

RESET

»| TiMer |R110H
PCS 6

F RPLY H

ee-¥

Lo}

TIMEOUT |(resT 10)

> PCS 6
AQO H

T ADDR EN H

—

BUS A00-14 H
20 Hing Ro
PORT
2

DRIVERS

—:|5> DRIVERS

}

BUS DO-7 H

.PCSB
. )BUS D~>DALHBL

DAL 0-1 > 0C005
15 H

I BS7 H

PCS 7

—»B BS7 L

XMIT

TRANSCEIVERS

PCS 8 8

PCS 7

PCS 8

8-15

PCS 7

BUS D3 H—| D3 R3
ZORT

AD 15 H

»lPcs 8 16

TDATAENH

Pgs

PCS 4

P’

PCS 7

RBS7 L
'
(FOR TEST ONLY — LOADS OWN CSR’S)
(TESTS 7 AND 11)

[Te]

DRIVERS
-

PCS8 8

]

PCS 8

0-7

T
o

Bk
m

MA-2291

Figure

4-14

DMA Transfer

Out

DMA MEMR H
DMA ENB H

PCS 2

@
®

WAIT L

BUS MEMR L

IRDY

PCS 5

ETC

PCS 5

8080

BUS A15 H

BDMG! L—ef

PCS 2

PCS 5

PCS 5)0—8 SACK
L

pDMA

OH
DMA

SACK H

GRANT

B SYNC L 0@ PCS 6
@

PCS 6

BDMGO L

R RPLY L

PCS 6)—Yrcs

DMA

—{ pcs 5

330 H

TIMER

*1 CONTROL

440 H

—»
B DIN L
—» B SYNC L

»|PCS 6

550 H

DMA ACK H

B RPLY L

—O

PCS 4

—>1

RRPLY L
DMR
L

PCS 6

RESET

TIMER

|R110H

PCS 6

F APLY
H

PeE-¥

TIMEOUT Lrest 10

TMpPCS 6
AOO H

T ADDR EN H

BUS A00-14 H
;

PO Hlho

DRIVERS

0-18

PCS 4

> pcs
s 16

BUS D3 H —{ D3

PORT
2

@
BBS7L

AD 15 H

DRIVERS

8-15

—

DAL 0-15 H

REC

XMIT

PORT

DCO05

PCS 7

PCS8

. BUS DO-7 H

TRANSCEIVERS |

PCS 8

PCS 7

PcS4
.

PCS 8

—

DRIVERS
PCS8

PCs 8}y DAL LB ~BUS
DL

in
=

)
-t

g
o

MA-2292

Figure

4-15

DMA Transfer

BUSDOH

8080

BUSD4H

ETC

BUSI/OWL
BUS A00-07 H

GE-¥

PCS 2

IwWRITE1 H

ADDRESS

WRITEZH

DECODER

PCS 7

BIRQ |—BIRQ L

ENB DAT

8080

PORT

ENA DAT

BIAKI f&— BIAKI L

| bcoos puar BON

v ‘@ ‘@' BDNL

INTERRUPT CIRCUIT VEC RQST B H

ENA CLK

JenscLk
PCS 4

VEC RQST

vecTORpLEoRTM
‘
@

(TEST 12)
DCO04

—0

O-———ip

?:I?SZCENERS
>JV

"1 INPUTS

BUS|B DALO-15L

I—g.
PCS 4

VECTOR

BRALY
PCS 4

Figure 4-16

ISV11-B Interrupt Request to LSI-1l

MA-2293

(::) SL6J2

LATCH& |INTH

INTERRUPT

PCS1 J1

BDALO-15L

DALOHI

REC

BUS

D
»{ DAL
O

B SYNC
L

B WTBT
L

B8 DOUT
L

LAAAY

9¢€-¥

BBS7L

SEL6
MENB

MATCH

PCS 4

+3V

resr | || vomr |
}

OQUTLB

Pl
|

[

ENCODER

sL2

Thyyvbet

Ntz oo

BUS

DO~7

Isws_cLk
———

| |sEL A0

»IWTBT

———— il

BUS DO H

| BUSINTACKL

SEL

[

SYNC

PCS 6

—O

ENB

S)/NTRQ4
H|

PCS 6

—Q

DC0O04

BS7 L

SL5

|
|

PCS 7

—O

(::)

I;
s

DAL
2

DCO05

PRIORITY

]

DAT git;: »| DAL 1

TRANSCEIVERS

LSI INT REQ
H

PorT

ADDRESS [

BUSAC457H

pecoper |

Veusivowti |

DOUT

sS4

PCS
4

8080

ETC

PCS 2

BUS D5 H

PCS 6

WRITE 2 H

8080

PORT

ADDRESS

DECODER [*

BUS A0O—07 H

BUS I/OW L

PCS
7
MA-2294

Figure

4-17

LSI

Interrupt

Request

4.11

SPECIFICATIONS

The ISV11-B places one dc unit load and four ac unit loads
LSI-11 bus, and has the following dc current requirements.
+5
+12

the

3.0 A maximum

@.37 A maximum

LSI-11

Interface

CSRs

160140,

Interfupts

300,

DECdataway Interface
Port addresses

(modem)

Two

consecutive,

into

connector

lower

wired

serial,

LSB first

(DSBC)

8 bits plus @ to 2 stuffing

size

bits

55,556 bits per second

rate

Transmission technique
Transmitter
Receiver
Line

304

Synchronous,

format

Character

Data

160144

Hal f-duplex

Operating mode
Data

160142,

Crystal

timing

From

timing

clock

received

signal

coupled

Transformer

interface

Transmitted

Biphase modulation

5 V peak-to-peak

signal

terminated

into

208 ohm cable

Receivable signal threshold

15¢ mV peak-to-peak minimum

Error-free

300 mV peak-to-peak minimum

Common mode
Receiver

signal

level

isolation

bandpass

35@¢

Vac

6 KHz to

rms,

5¢0@ vdc

13¢ KHz

(-3 dB points)

4.12
This

ISV11-B Signal Glossary
glossary
1lists
all
signals
schematics for the M8¢8¢ and M8084

that
appear
on
the
circuit
modules, as well as the print
on which each appears. Some bus signals are generated on several
prints.
Many LSI-11 bus signals originate outside the ISV11-B as
well
as
inside.
A print
designation
in
parentheses
indicates
a
signal
that
appears
on
that
print
as
an
input
but
is
never

generated

Signal

#1,2,

the

ISV11-B.

CLOCK H

PCS2

Definition

MHz

8224
g2

TTL

PCS2

clocks generated
for

MHz

8224

the

clocks
for

CLK

SL1

Equals

CLK

SL1

For
has

generated

the

8¢80.

USYNRT.

CLOCK

biphase encoding, this
twice the frequency of

clock

CLOCK.

CLK

H,L

SL1

330
449

H
H

550

AD
BAD

15-17

16,17

Intermediate

clock

dataway

rate).

bit

PCS6

Timing

PCS7

High-order

PCS7

signal

transmitter

signals

Expansion

(eight

for

DMA.

address

bits

address

bits

times

for
for

LSI-11

bus.
B

BS7

DAL

PCS7

9-15

PCS4

Bank

select

signal

LSI-11

address

LSI-11

bus

data

select

LSI-11

1/0

DMA.

bus

page

space.
and

address

lines.
B

DCOK

DIN

H
L

PCS7

LSI-11

bus

power

PCS6

LSI-11

bus

master

okay.
requesting

input, or LSI-11 getting vector
address in response to interrupt.
BDMGI

(PCS5)

LSI-11

bus

DMA grant

in.

BDMGO

PCS5

LSI-11

bus

DMA grant

out.

Signal
L

Definition

PCS5

LSI-11

bus

DMA

request.

DMR

DOUT

PCS6

LSI-11 bus -- master has
available for output.

HALT

PCS7

LSI-11

BIAKI

(PCS4)

bus

LSI-11 bus

halt

data

processor.

interrupt acknowledge

in.
BIAKO

PCS4

LSI-11

bus

interrupt

acknowledge

out.

INIT

(PCS4)

LSI-11 bus -- in
initializes only

ISV11-B

interrupt

control.
BIRQ

BOOT

LSI

BPOK

BRPLY

BS7

PCS4

LSI-11

bus

PCS7

Boots LSI-11 by simulating power
up (through control of B DCOK).

(PCS5)

LSI-11

bus

PCS4

LSI-11

bus

reply.

PCS7

Bank select 7 for I/0 page -conditions TBS7 when address

placed

interrupt

power

LSI-11

request

(to

okay.

bus.

SACK

PCS5

LSI-11 bus -- acknowledges that
ISV11-B has been granted master
status in DMA operation.

SYNC

PCS6

LSI-11

bus -- master

address
BUS

A@gQO

BUS

A@@9-15

BUS

D@-7

has

placed

bus.

PCS7

From

BUS

A@@

PCS2

8080

bus address

pCs2,3,7

8088 bus data

lines.

SL2,4

BUS D2 DAL HB L

PCS8

BUS

INT

ACK

PCS2

8080

interrupt acknowledge.

BUS

I/JO

PCS2

8080

reading

8080 data to

LSI-11

bus high

byte.

(port).

I/O register

Signal
BUS

I/0 W

Definition

PCS2

8080

writing

I/O

(port)
.
BUS

OUT

BUS

MEMR

SL2

8080 reading local memory
receiving interrupt RST.

PCS2

8080

reading

MEMW

WTBT

CARRIED

CPU

LED

SYNCH

memory or

addressed

I/O
memory.

PCS2

8080 writing memory or 1/0
register addressed as memory.

PCS6

LSI-11

SL1

Controls

PCS2

8080 signal
first state

bus

write/byte.

carrier-detected

LED.

to 8224 to indicate
in_each machine

cycle.
DAL

@-15

PCS4,

DAL LB2 BUS D L

PCSS

Data

and

address

lines

LSI-11

bus

extension.

LSI-11

bus

data

low

byte

8080.
DIN

DIS

CLK

DIS

I/0

DIS

MEM

DIS

RAW

DATA

DMA

ACK

DMA

MEMR

PCS6

Received

SL6

test

disable

for

test
address

disable

for

8¢8¢g

SL6

test

disable

local

SL6

test

disable

receiver.

PCS6

B WTBT.

PCS5

DMA

CLK.

1/0

decoder.

request

has

memory.

been

acknowledged

LSI-11

bus.

8080

LSI-11

address

LSI-11

address

reading

space.

DMA

MEMW

PCS5

8080

writing

space.

DMR

H,L

PCS5

DMA

request

generates

for 8080 to access
address space.
DOUT

DROPOUT

H,
L

PCS6

Received

SL1

Dataway

4-49

LSI-11

DOUT.

signal

absent.

DMR

Signal
DROPOUT L~
OR RSA H

ENA

DMA

EXT

CLK

Definition

SL5

Dataway signal dropped out (1.5
bit times without transition) or
USYNRT receiver status available.

PCS5

8080 addressing

SL6

8X CLK at test socket; or can
be used for external clock 1if
DIS

EXT RAW DATA H

SL6

EXT R

DATA

FRPLY

H,L

LST

HALT

CLOCK

INT

Q BUS

SL6

test

socket;

external data

for

be used

USYNRT.

External test received data for

A H

reply.

bus

DCS6

Forced

PCS7

Generates

SL2

Interrupt

PCS4

LSI-11 bus interrupt control
waiting for interrupt on A

SL5

PCS4

1/0

PAGE

HALT.

8¢849.

Interrupt

300

requests to 8080.

From B DIN sent by LSI-11

for

CSR.

PCS2

I1I/0R L

PCS2

I1/0 W

8980¢ addressing 1/0 register as

memory location.

8¢8¢ IN instruction
898@¢ OUT instruction

(I/O0 read).
(I/O

write).

I1/0 WR H

PCS7

Equals

I/0 R "OR"

PCS4

Jumper

address

JAV

PCS4

LITE

can

USYNRT.

4-7 H

INWD

receiver clock

test

level, or has vector
DAL lines.

INT RQ

DATA.

RAW

External
for

space.

CLK.

RAW DATA at
DIS

EXT

LSI-11

I/O W.

inputs to

DC@0@5s.

Jumper vector address inputs to
DC@@5s.

1-4

PCS7

Control

4-41

M8¢8¢

LEDs.

Signal
LSI

INT

REQ

PCS7

Definition
Equals

CSR

LSI-11

request

bit

this

for

8089

for

-5

interrupt.
MARGIN

SL6

-5V

test

margin

for

PROMs.
MATCH

PCS4

Address

address

(JA)

addressing
MEM

BUS

D@#-7

SL2,3

Data

bus

DAL

equals

(LSI-11
CSRs).
~

ISV11-B

for

jumper

DC@@5s

output

from

local

memory.

MEMR

PCS5

Equals

BUS

MEMR.

MEMW

PCS5

Equals

BUS

MEMW.

SL2

8080

MEM

SEL

MENB

PCS4

accessing

Enables match

local
with

memory.

DC@@5s.
OUT

PCS3

From

OUT

PCS4

LSI-11

OUT

PCS3

From

OuT

PCS4

LSI-11

SL1

A clock

PHASE-LOCKED

CLK

PORT

OUT

CSR

high

CSR

low

byte.

(train) geared to last
transition detected on
dataway.

signal

ADDR

1-6

(SL4)

Port

address

wired

into

dataway

connector.

R119

RAM

SEL

RAW

DATA

BS7

CLOCK

RDA

H,L

PCS6

Reset

SL3

8080

SL1

Output of modem
circuit.

PCS7

Received

SL1

Receiver

clock derived

incoming

bit

SL5

time

for

DMA.

accessing

RAM.

receiver

BS7.

USYNRT output

available.

the

from

stream.
--

received

data

Signal
R

DATA

H,L

Definition

SL1

Modem

received

data

output

USYNRT.
R

DCOK

READ

PCS7

SL4

Received

DCOK.

8080 reading I1/0 register in

address

range

PCS7

LSI-11

reading

PCS2

Pulled down by the 8224
wait to idle the 8080.

PCS4

ISV11-B is not
information on
lines.

PCS2

Generated by
goes down.

8224

RESET H,L

PCS2

Equals

RESET

H,L

SL6

M8@P84

PCS7

Received

PCS5

Received

BPOK.

PCS4

Received

BRPLY.

SL5

USYNRT output
available.

SL5

USYNRT receiver

active..

PCS5

Send

DMA.

PCS4

CSR address

READ

CSR

READY

REC

RESET

HALT

RPOK

RRPLY

H,L

RSA

ACT

SACK

SEL

SL4

. 8080

RESET

reset

SL4

8080

CSR

@.
on

when

from PCS2

SL4

RESET

HALT.

SACK

for

decoder

range

reading

receiver

I/0

80980 writing

status

outputs.

8@g--87.

I/0 register

90
'

I/0 register AQ

(USYNRT control).
SEL

SL4

8080

DAL

BPOK

(USYNRT status).
SEL

now sending
LSI-11 bus B

accessing

address
SEL

8@--87.

reading

I/0 register

(port address).

Signal
SELECT

1-5

Definition

PCS7

Address

8080

bus
SRPLY

PCS4

STROBE

PCS2

Send

BRPLY.

Send

8224

CPU

status
SYNC
T

ADDR

H,L

decoder

outputs

I/O registers
interface.

SYNC;

8228

for

LSI-11

response

latches

8088

cycle

8228.

PCS6

Received

PCS6

Transmit

address

SYNC.
on

DAL for

buffer

empty.

DMA.
TBMT

SL5

USYNRT

TBS7

PCS7

Transmit

SL1

Transmitter

SL5

USYNRT

PCS6

Transmit

data

PCS6

Transmit

DIN

Transmit

DOUT

CLOCK

DATA

DIN

DOUT

PCS6

ENA

H,L

SL5

H,L

Enable
USYNRT

transmit

BS7.
clock

serial

DISABLE

8080
TEST

output.

DAL for

GR test

PCS6

L
PCS7

Time-out

TTMMO

PCS7

DMA

TMO

ERR

DETECTED
TRANSITION
DLYD

SL1
H

SL1

for

DMA.

disable

mode).

8080

operation.

enable

for

I/O0

DMA.

time-out.

Time-out
to

TRANSITION

DMA.

test disable 8089
register addressing.

PCS7

for

DMA.

transmitter
(when
transmitter active but not

TME

KHz.

modem

L
DISABLE

I/0

PCS6

55,556

data

in maintenance
TEST

error

status

bit

(8089

LSI-11).

Receiver detected
crossing.
Transition
delayed

500

detected
ns.

zero-

inverted

and

Signal
T

RAW

DATA

Definition

SL1

Flip-flop
signal

biphase-encoded data

applied

transmitter

circuit.
T

SYNC

PCS6

Transmit

for

DMA.

WTBT

PCS6

Transmit

B WTBT for

DMA.

ACT

SL5

USYNRT transmitter

VEC

RQST

VECTOR

WAIT

active.

PCS4

Makes vector jumper address
when VECTOR is true.

PCS4

Places vector Jjumper address
(JAV) on B DAL when the 8080
interrupts the LSI-11.

PCS2

SYNC

Puts 8080

in wait

304

state until

DMA

acknowledged.

1,2

WRITE

WTBT

PCS7

Select 8080 I/0 registers
for writing.

PCS6

Received

B WTBT.

and

CHAPTER
BAll-Y

5.1

The

POWER

SYSTEM

DESCRIPTION

INTRODUCTION

BAll-Y power
1.
2.

system has

four major

assemblies.

Power supply (H7861)
Backplane (H9276)

Module

cage

input

panel

(front

panel)

These are identified in Figure 5-1, which shows the BAll-Y with
its cover removed. In addition to the major assemblies, the figure
shows the locations of several subassemblies that are of interest
to anyone servicing the unit. These are:
1.

Module-assembly

2.
3.

AC and dc harnesses.
Bezel PC board assembly.

Power

Figure

5-2

and

power-supply fans.

supply control

links

these

and

power-monitor

components

functionally.

boards.

BEZEL

CONTROL.

P.C.

BOARD

ASSEMBLY

BOARD

DC HARNESS

L// ' i’/&

/ ’4!

FAN

MODULE

ASSEMBLY

FAN

\t‘\I,

‘k
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!.1
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MODULE

gggEEMBLY
Figure

SUPPLY

(‘.\!’ 5%

BACKPLANE

POWER

c7//

)
SUPPLY

AC HARNESS

5-1

BAll-Y

Major

5-1

FRONT PANEL

MA-0233-82

Assemblies

POWER SUPPLY, H7861

wAsTER
BOARD (5414583
ASTER BOARD
(54-14583)

AC IN D—J——L

FILTER

°
|

{70-17971-0)
SWITCHING AND POWER TRANSFORMERS,

*1P44 1" bc VOLTAGE REGULATORS

TO POWER

—

CONTROL
BOARD

CONTROLLER

(5412532)

POWER

J5
13

DC HARNESS

+5 VDC

+12VDC

SIGNAL CABLE

(70-11411-0K)

MONITOR

BOARD

(54-15048)

PANEL
L FRONT
701394900

SIGNAL CABLE (7011411)

|P3|
+12V

TEST

RTN

POINTS

FRONT PANEL

P
MR-6577

MA-10,495

Figure

5-2

BAll-Y

Functional

Block

Diagram

5.1.1
The ac

AC Input Panel
input panel is also

the panel from
line cord.
The

an
to

panel

the

ac mains

includes

the
by

front
either

input

panel.
a

120

connector,

Power

V line
a

line

provided

cord

249

filter,

fuse,

ON/OFF switch, and a switch that makes the correct connections
the fans and the power supply for both 129 VvVac and 24@ Vac line

voltages.
The

output

the

panel

taken

the

fans

and

the

power

supply

by
an
ac
power
harness.
Connector
Pl
of
the
harness
1is
a
Mate-N-Lok connector
(9-pin), while P2 and P3 are molded ac plugs
that break out of the harness to plug into terminals on the fans.

5.1.2
H7861 Power Supply
The H7861 power
supply occupies

the

upper,

rear

quarter

the

DYS50 space.
It is attached to the logic cover assembly with two
releasable hinges. It is fastened to the power supply bracket with
two
screws.
When
the
two screws are removed,
the supply can be

tipped back to allow service access. The entire power supply
be removed easily by removing the two screws, unlatching the
hinges, and disconnecting four cables.
Three

printed

components.

circuit

boards

control

board

The

contain
and

the

all
power

the

power

monitor

can
two

supply

board

are

inserted
in connectors that are mounted on the master board. The
regulated dc voltages generated on the master board are sent to
the H9276 backplane by a dc harness that connects on both ends to
screw terminals.
The signals generated on the control
board are
applied to the backplane and to the front panel by two different
~signal cable assemblies.

5.1.3
H9276 Backplane
The H9276 is a 9 X 4
backplane,
each;
of
are

both

each

double

slot

bused

and

supply
each

quad

the

extended

the

i.e.,

modules

nine

LSI-11

5.1.4
The

front

Front

the

Bezel

panel

can

slots

four

rows

inserted.

Rows

bus

s1gnals,

these

signals

not bused;
This
not

necessity
of
top
connectors,
but
designing
buses
whose
lengths are
modules in a set. The C and D rows
collectively as

nine
be

and

slots.

The pins of the C and D rows are
adjacent
slots
are
connected.

can

however, the pins of
only
precludes
the

also
provides
the
means
for
determined
by the
number
of
of the backplane are referred

CD bus.

Assembly
be

blank

can

equipped

with

and indicators. The switches allow an operator to turn
on and off (only when connected to a power controller),

switches

the power
to reboot

the CPU,
and to suspend the CPU's usual program execution.
The
indicators,
when
1lit,
tell
the
operator
that
the
power
supply
voltages are enough for operation and the CPU is
running.
The
front panel
is connected to the power
supply master
board
by a
signal
cable
and,
if
appropriate,
to
a
power
controller
by
a
twisted-pair cable that can be provided.
5-3

5.2
DETAILED DESCRIPTION
A
detailed
description
of
each

component
of
the
follows.
Figure 5-3 is a unit assembly drawing that
of the power system interconnections.

power

system

shows

details

5.2.1
AC Input Panel
Figure 5-4 is a schematic of the ac input panel. The fans and part
of the power supply master board are shown to present the primary
power

connections.
T4 of the master
board
is the
transformer; D1, C2, and Cl convert the ac voltage
dc voltage, as described in Paragraph 5.2.2.1.

The

line

cord

that

connector,

FL1.

used

ON/OFF

SW2 is
filter
mounted

below

when

voltage

when

5.2.2
Figure
the

the

when

SW2
on
the
the printing

power

inserted

controlled

SW2,

power

controller

not

front
panel
and
is
over the switch lever

start-up

the

male

which

used.

When

supply

in
the
correct
agrees with the

used. SW1 allows the system to run on 12¢ Vac
connecting the line to the power
supply input and
For example,
the fans are provided with
120 vac,
line voltage is 24¢ vac.

H7861 Power Supply
5-5 is a block diagram

power

boards

switch

primary

voltage

being

or 24¢ Vac by
the two
fans.
even

line

nonregqulated

closed, the line voltage is applied through Fl1 and the line
to
the
voltage
selection
switch,
SWl.
This
switch
is

position

line

supplies

The

+12

components

master

board,

are
a

the

H7861 power supply. All of
on three printed circuit
board,
and
a
power
monitor

mounted

control

board.
The master board consists of an ac input circuit,
V regulators, and a +12 V start-up supply. The ac
thermostat
that
protects
the
supply
from
too

thermostat
switch
opens,
disconnecting
ambient
temperature
reaches
85
C
(185

the

+5 V and +12
input includes a
much
heat.
The

the
ac
input,
when
the
F);
the
switch
g;oses

automatically when the temperature returns to 64.4
The ac input circuit converts the 120 Vac or 24¢ Vac
dc

voltage.

This

voltage

1is

applied

C
(148
input to

power

F).
raw

converter

circuit that
is switched on and
voltages
that
are
applied
to

off to produce
rectangular-wave
the
regulator
circuits.
The

rectangular-wave

switching

input

each

input voltage
board causes

circuit

cycle

Therefore,

The

increase
the

output

circuit

inverter

circuit

pulse

maintain

the

duty

voltage

has a
output.
duty

1level

protect

applied

the

supply

decreases,
the
5
V
power
converter

the

rectangular

wave.

maintained at its correct level.
switching
transistor
in
series with
the

This

switch

cycle

that

corrects

will

BEach regulator circuit is a switching
filter
and
includes
overvoltage
and

outputs

regulator
has
a
duty
the
unreqgulated
input

cycle
that
differs
with
the
voltage.
If,
for
example,
the
control
circuit on
the
control

against

overload

are monitored by the control
to the H9276 backplane.

5-4

the

average

converter

output

regulator

with an averaging
overcurrent
circuits
that
conditions.

board.

The

outputs

regulated
are

also

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PWR. SUP.

FAN

IH9276

HARNESS

€

LOGIC

|
I
|

|
TP1+5V

| —

TP2 RTN I

l TP3 +12V

B e

L' __ BEZEL] | _
el

MR-6675

MA-10,494

Figure

5-3

BAll-Y

Interconnections

POWER
ACHARNESS
Sw2

P\1 J1

SW17230V

@’

——

{

: 9

| >V

\_I

> 4 4> l

>6) T

1—6’F\Lr—1r(o—3__8¢(
FL1

—ll

P/O H7861

MASTER BOARD

— —>. 1

—> 1 d: LOGIC

I Ps.
P3> 1 ;j:

> 2

S 2

FAN

I
MA-0214-82

Figure

5-4

Input

Schematic

——————

—q

rCO TROL BD

ili

+12V

Mvastereo
ASTER BD

COMMON

I
=

230 VAC

—

l
THERMOSTAT

had

115 VAC

XXX

CONTROL

SWITCH/PWR
XFMR PRIMARY

\égtngR
AGE

-r—-

12.6

RECTIFIER/
TRANSFORMER VAC_ | FILTER

omae

saaE

A
T @5

_ +5VDC

REGULATOR

aowss

DETECT

RECTIFIER

OVER VOLTAGE_I

| OVER-CURRENT

SECONDARY

CIRCUIT

. +12VvDC

REGULATOR

+12V

PWR XFMR

5V
CONTROL

T @36
A

—

—+12 V START-UP

1
I
I

L—————————

POWER|

BD |
MONITOR
DCOK

CIRCUIT

POK

CIRCUIT

T LTC

|
l

-—l—> B DCOK H
I
I

LTC

GENERATOR

r
I
|

—‘—»BPOKH

MR-6576
MA-0185-82

Figure

5-5

H7861

Block

Diagram

The +12 V start-up supply produces a dc voltage that is necessary
during
start-up operations. When steady conditions are attained,
the +12 V regulated output takes over for the start-up voltage. If
the

+12

start-up

monitor
The

regulated

voltage

board

control

comparing
feed

output

circuits

board

them

should

available

keep

lost
the

during

control

operation,
board

and

the

power

operating.

circuits

monitor

control

board-generated

the

regulated

output

reference

voltages,

and

them

voltage
circuit

back
to
the
main
converter.
When
either
regulated
varies from its prescribed value, the appropriate control
varies the duty cycle of the rectangular-wave as needed.

This forces the output to return to the correct value. Adjustment
potentiometers are provided in each control circuit, enabling the
output voltages to be adjusted to account for initial tolerances
of circuit components.
The
H

power

monitor

that

board

enable

power-down operations.
both when the power is
or

lost

because

generates

the

CPU

failure

5.2.2.1
of
the

signals
out

BPOK

specific

and

BDCOK

power-up

and

The signals are asserted in a set sequence
turned on and when the power is turned off
(the

5.2.2.5).
Also
included
on
the
produces a line-time clock (LTC)

the
CPU,
where
frequency.

two

carry

generates

sequence
board

signal.

described
a

clock

This

vectored

signal
interrupts

AC Input Circuit -- Figure 5-6 shows
power
supply.
The
ac
input
voltage

voltage

the
is

Paragraph

generator

that

is applied at
at
the
1line

ac input circuit
converted
to
dc

by bridge rectifier D1 and capacitors Cl and C2. When the
input is 240 Vvac, Dl corrects the ac voltage, and Cl and C2 smooth
the
ripple
that
appears
on
the
dc
output
of
the
rectifier.
However,

when

the
input
is
1206
Vvac,
D1,
Cl,
and
C2
become
a
doubler.
Therefore,
the
dc
voltage
produced
is
approximately
the
same
for
both
line
voltages
and
can
change
between 208 and 375 vdc.

voltage

This dc voltage is applied to a switching circuit that
transistors Q1 and Q2 and transformer Tl. Q1 and Q2 are

includes
switched

on and off at 3¢ kHz.
The duty ratio
is determined by the +5 V
control circuit on the control board. When the transistors are on,
the corrected dc voltage appears across the primary of transformer

T2
on

(pins

1-2)

and

combined

the windings of T2
side
of
each
winding

with

each

secondary

T2.

The

dots

(Figure
5-6)
represent
the more positive
at
this
time.
When
the
transistors
are

switched off, the voltage across the primary of T2 reverses
polarity instantaneously. The same polarity reversal occurs in
secondaries of T2; then, an alternating wave is generated at

its
the

the
secondaries of T2. Each regulator uses the positive half cycle of
the secondary voltage to produce a positive dc voltage. The +5 V
regulator
winding
also
uses
the
negative
half-cycle
of
the

secondary

(=12

vdc),

voltage

which

produce

used

bias

nonregulated,

ICs

the

negative

power

monitor

voltage

board.

FROM OVER VOLTAGE PROTECT

COMMON-—=

} FROM +56 V CONTROL CKT
FROM 12V

I'*

CONTROL

{

l
~C ¢

115 VAC

3his #

230 VAC

p1[

$R10

TO +5V

RECTIFIER

12.6 VAC

“i

1 2 VSTART-UP
HpHPT1-+1

MR-6556

MA-0194-82

Figure 5-6

The

rest

Inverter Circuit

this

section

expands

the

preceding

short

description

by focusing on the current and voltage relationship in transformer
T2. Figure 5-7 1links the current and voltage waveforms in the
primary and secondary windings of T2. At time A, transistors Ql
and Q2 are off. During this time, a steady current is moving

through the secondary winding of transformer Tl from pin 5 to pin
6 (Figure 5-6). At time B, the +5 V control circuit causes the
current in winding 5-6 to stops moving. A voltage that opposes the
decrease

current

(i.e.,

counter-EMF)

1is

produced

across

winding 5-6; thus, pin 5 becomes negative with respect to pin 6.
in the other
induced
Voltages having the same polarity are
secondaries and the primary of T1l. These voltages forward-bias the
emitter-base junction of both Q1 and 02, turning on the
transistors. Collector current starts to flow from Q1 through the
primary of T2 from pin 2 to pin 6, through Q2, and through
secondary winding 2-1 of Tl1. Then, the corrected dc voltage
appears across the primary of T2, pin 2 being the more positive
side of

the winding.

V34

MR.6557

MA-0195-82

Figure

The
on

current
each

moving

secondary

5-7

the

Current/Voltage

primary of

winding.

time

Relationship

determined

steady

current

the
is

load

moving

in
the
primary
of
transformer
T3
from
pin
6
to
pin
5,
and
transistor Q3, which is part of the +12 V regulator circuit,
is
not conducting. Then, there is no load on secondary winding 7-8 of

T2, and the primary current of T2 is a function of only the +5 V
regulator. At time C, the +12 V control circuit causes the current
in winding 5-6 of T3 to stop moving.
The counter-EMF generated
across the primary winding is coupled to both secondaries of T3,
and
the
polarity of
the
induced
voltage
forward-biases
the
emitter-base junction of Q3. The +12 V regulator starts to operate

and the current drawn from the secondary of T2 is echoed back to
the primary of that transformer.
Then,
the total current in the
primary of T2 quickly grows, as shown by the current waveform in
Figure 5-7.
After

the

sudden

increase

time

more gradual, linear increase,
across the primary winding. At
causes

steady

current

the

primary

current

begins

resulting from a constant
time D, the +5 V control

start

moving

once

voltage
circuit

winding

5-6

of transformer
T1.
The bias voltage
is
removed
from Q1
and
Q2,
turning them off. As the current through the primary of T2 starts
to decrease, the primary voltage reverses polarity to oppose the

changing current.
Now pin 6 becomes
the more
winding 2-6.
The charging path is from pin 6,
capacitors C2 and Cl, and diode D2 back to pin

positive side of
through diode D8
2 of the winding.

The

winding;

then

the

and

cycle

-E

voltage

clamped

across

the

primary

primar? current decays linearly toward zero. When this wvalue is
attained,
repeated.

the

primary

voltage

drops

zero,

the

As Figure 5-7 indicates, the frequency of the voltage waveforms is
constant.
This frequency is determined by circuit components 1in
the +5 V control circuit. However, the duty cycle of the voltage
pulses

can

voltages,

change

(The

duty

show

cycle

the

condition

defined

the

ratio

controlled
t.,./T

and

has

dc
a

maximum value of 50 percent.) For example, if the lo%% on the +5 V
output

increases,

the

control

<circuit

causes

switching

transistors Q1 and Q2 to stay on for a longer period of time to
make up for
increased voltage drops due
to circuit
resistance.
That is, point D and point E in Figure 5-7 move to the right, as
indicated
by the
dashed
lines.
Then,
the
average value
of
the
input to the +5 V regulator
increases; this increase forces the
output

back

its

original

value.

The increased duty cycle forces up the +12 Vdc
as well. Because this output was at the proper

controlled output,
value (we assume),

any increase is false. Therefore, the +12 V control circuit causes
Q03 to switch on later to lower the average value of the input to
the +12 V regulator. The result of this on the waveforms in Figure
5-7 is shown as a dotted line.

5.2.2.2

+5 V Control

Circuit --

Figure 5-8

shows

the +5

circuit. The circuit monitors the +5 vVdc controlled
turning Q2 on and off, controls the flow of current

transformer

T1.

V control

output and, by
in winding 5-6

To monitor
the controlled voltage,
the circuit
includes a
3524
integrated
circuit
(IC)
-a
controlled
pulse-width modulator.
Figure 5-9 shows a block diagram of this IC. When the 3524 is used
in
the
+5
V control
circuit,
the +5
Vdc
controlled
output
is
applied to one input of the error amplifier. The other
input of
the error amplifier
is connected to an internally generated +5 V
reference

(pin

16).

The

error

signal

developed

applied

to
a
comparator
together
with
an
internally generated
sawtooth
waveform
(the
outputs
from
the
internal
oscillator
are
set
by

external components at pins 6 and 7). The comparator output is a
pulse whose width depends on the level at which the error signal
slices the sawtooth. This pulse is applied to NOR gates along with
the
internal oscillator
output
and
both
sides
of
the
internal

flip-flop. The
in both the +5

resulting
V control

output signals at pins 12 and
circuit and the +12 V control

13 are used
circuit.

These output signals from the 3524 IC are related to the internal
signals by the waveforms in Figure 5-1¢.
The circuit components
connected to pins 6 and 7 result in an oscillator output for
a
period

16.5

us.

The

oscillator

output

pulses

(the

top

clock the internal flip-flop, one output of which is shown
second line. The third line shows the sawtooth signal being

1line)

in the
sliced

by the error signal, which is represented by the horizontal solid
line (the dashed line will be explained later); line 4 shows the
resulting comparator output. When the signals shown on lines 1, 2,
and

and

are

NORed,

they

produce

the

output

signals

shown

lines

TO +12V

CONTROL CKT
[

t12v sTARTUP

+5 VDC—

ol
L

R273 3

16 whl

{5 3524 12
R283 3

7
8

10
9

- T1-6

T
“

'__

3
4

—» T1-5

D7
Pt

[PioMASTER|

IBOARD

A\
$
1

I a1

T2-3

NOTE:

OVERCURRENT
DETECT

UNLESS NOTED, LOGIC IS
P/O CONTROL BOARD

MR-6558

MA-0189-82

Figure

5-8

V Control

Circuit

® VREF
ViN

REFERENCE |
REGULATOR

+5V TO ALL
INTERNAL CIRCUITRY

OSCILLATOR

5V
RT ()

OSCILLATOR

(RAMP)

OUTPUT

+5V

FLIP
FLOP
T

NOR

(Y
K

(1Dca
_

ML
COMPARATOR

+5V

INV. INPUT ————
(D

INPUT ®

\L\@M

ERROR

(&) +sENSE

V_{

NON INV.

GROUND®—l
(SUBSTRATE)

-——((5) -SENSE

SHUT

pown

{10K

@5 COMPENSATION

MR-6559
MA.0188-82

Figure

5-9

3524

Block

Diagram

l-— 16.5us ""l

23
INTERNAL F/F

OUTPUT, 1 SIDE

[

['L

[l
I

E2-7 (RAMP)
E2-9 (ERROR)

__ _
______/\__.____A

P 2

2 SR

————

E2-13

E2-12

V1-2(T3)

MR-6560
MA-0193-82

Figure
The

output

5-1¢

from

Timing,
12

V Control

used

Circuit

the

+12

V control

circuit.

The output from pin 13 is applied to transistor pair Q03/Q04
+5 V control circuit. When pin 13 goes low, Q04 is turned on

in the
and Q3

is turned off. Q2 turns off and the current that had been moving
in transformer Tl begins to decrease.
The counter-EMF induced
in
the windings of T1
forward-biases switches Q1 and Q2
in the ac
input

circuit.

Then,

and

switch

and

applied

Q04

the

primary of power transformer T2, as shown by tge 51gna1 of line 7.

When

Therefore,

goes

high,

conducts

and

turned

steady

current

again

and

moves

turned

off.

through

TI1.

Switches
Q1
and
Q2
in the
ac
input circuit
turn off,
and
the
primary voltage of T2 reverses polarity. When the primary current
of T2 has decayed to =zero,
the voltage returns to zero and the
cycle is repeated.
'
The

dashed

lines

controlled

output

show what occurs,
for
example, when the +5 vdc
tends to decrease.
The error signal in the 3524
narrowing the output of the IC's comparator.
As a

increases,

result, switches
Q1 and Q2 in the ac input conduct for a
period of time. The increased duty cycle of the voltages
the windings of T2 counteracts the threatened decrease of

Vdc

controlled

Both

regulator

1longer
across
the +5

output.
circuits

are

equipped

with

overcurrent

detectors.

When such a condition results in either regulator, pin 9 of 71 is
taken near ground and the comparator output pulse width reaches a
maximum. Then, the duty cycle of the power transformer voltages is
lowered

minimum.

Circuit -- The +12 V control circuit is
5-11. The circuit monitors the +12 Vdc

5.2.2.3 +12 V Control
represented in Figure

controlled output and, by turning Q1 on and off, controls the
movement of current in winding 5-6 of transformer T3. The control
circuit includes an operational amplifier, E1, and an NE555 timer,
E3.

block diagram

A simple

the

timer

shown

and C13 are part of the +12 V control circuit).

Figure

5-12

A trigger

(Q5

pulse

applied to comparator B causes both the output phase to generate a

gate and the internal transistor to turn off. The external
capacitor, Cl13, starts to charge at a rate determined by the
amount of current provided by Q5. When the charge voltage on Cl3
reaches the threshold level started by the control input (pin 5),
comparator A causes both the output phase to terminate the gate
and the internal transistor to turn on. C13 discharges through the
internal transistor to ground, and the cycle repeats when the next
is applied.

trigger pulse

The dashed 1lines in Figure 5-13 represents what occurs, for
example, when the +12 Vdc controlled output decreases. The output
of the operational amplifier in the control circuit increases.

Therefore, 05 supplies a larger amount of current to Cl13, which

charges at a more rapid rate. Transistor Q1 turns on earlier to
increase the duty cycle of the secondary voltage of T2 and,
thereby, to aid the slight decrease in the output voltage.

5.2.2.4

Figure

+12 V/+5 V Regulators -- The +12 V regulator is shown in
The

5-14.

circuit

1includes

regulator,

switching

overcurrent sensor, and an overvoltage detector. The main
components of the switching regulator are diode D11, choke coil
.3, and filter capacitor C5. When Q3 is turned on by the +12 V
control circuit, the voltage at the secondary of T2 is applied
across D11, at the input of the LC filter. The constant voltage
across L3 results in a linear current buildup, which is absorbed

by the output capacitance. Therefore, the +12 Vdc output tends to
rise. When the +12 V control circuit

turns off

the voltage

Q3,

across L3 reverses polarity, and L3 discharges through D11 into C5
and the load. The +12 Vdc output decreases until Q3 is turned on
again. This cycle repeats, with the period either increasing or
decreasing, depending on the level of the controlled output;
therefore, the output is a ripple centered at the +12 V level.

Overcurrent

sensing

current drawn
inverting

ground.

from

the

accomplished

comparator

supply reaches 7 A,

El.

input of El1 predominates and the output of

This

ground

applied

the

When

the

the voltage at the
El1

V control

goes to

circuit,

causing it to decrease the duty cycle of the power transformer
voltages to a minimum. Then, the output voltage is decreased to
make sure the current is kept below 7 A. When the overload
condition is removed, typical regulator operation continues.

+12vDC

H'I

O
a

R13

E1\

M-

’

R~ c13

D15

_,_

+12 V START-UP

. 736 F;

P—w-

@
1

]

T35 | 15—,

';
||

| P/O MASTER)

NE555
6

t D3

BOARD

Lw-) I———

{eo

5V
(FROM E2-16, +5 V

VWA

——

$
S
<

CONTROL CKT)

(FROM E2-12,+5 V
CONTROL CKT)
NOTE:

UNLESS NOTED, LOGIC IS
PART OF CONTROL BOARD
MR-6562
MA-0197-82

Figure

5- 11

+12

Control

Circuit

————q——

I
I

7 | DISCHARGE

GENES oEmS e—

l“————‘ e——-

C13

5
—O CONTROL (+5 V)

s lTHRESHOLD COMPARATOR

I
I

TRIGGER

RESET

o3
OUTPUT
MR-6564

MA-0196-82

Figure

5-1 2

Block

Diagram,

NES555

L
|
<

—_—

E3-5

(+5 V)

{T3)

V3-4

(T3)

]

FILTER

INPUT

. .

V1-2

E3-3

E36,7

MR-6561

MA-0191-82

Figure

5-13

Timing,

+12 V

Control

Circuit

T3
I

FROM
12V

J4-7

5 CONTROL

+12 V START-UP

circult

+12V

3
£

¢® START-UP

D12

|_|

L2
r—
+12 @5
A

D15

J_E1\

-4

$R35

R16

TM~

T~ $R15

D26

D24

D13

> T0 J2-8
Q4

1~ C26

-~
9

T0J48

C25
» T0J2-6

* ‘

R30,
D20

L1,

C16, R18

MR-6565

MA-0192-82

Figure

5-14

Overvoltage

+12 V Regulator

protection

provided

the

circuitry

centered

D28, 05, 06, and D24. If the output voltage approaches 14 Vvdc,
Zener diode D2@ conducts, turning on unijunction transistor Q5. Q5
provides gate current for SCR Q6, which triggers on. A near-ground
voltage is applied through D24 to pin 6
ac input circuit. Hence, the transistor

of transformer T1 in the
switches in the ac input

circuit are turned off, and the voltage on the power
goes to zero. Normal operation resumes only when the
condition is corrected and the power is switched off.

transformer
overvoltage

The

the

regulator

regulator,

this

overcurrent

sensor,

1is

shown

circuit

and

Figure

includes

overvoltage

5-15.

switching

+12

regqulator,

detector.

Each

V
an

these

works exactly as its equal in the +12 V regulator, except that the
voltage and current limits are different;
i.e., the overcurrent
starts to operate before 48 A and the overvoltage circuit starts
to operate at 5.7 V. Also present in the +5 V regulator is the -12
Vdc generator, which is, basically, diode D17 and Zener diode D23.

5.2.2.5

two

POK/DCOK

signals,

BPOK

Circuits
H

and

BDCOK

The
H.

power

These

monitor

signals

circuits

are

control

asserted

when

the power is turned on or off, or when a power failure occurs.
They cause the CPU to carry out specific power-up and power-down
operations.
Figure 5-16 shows the bus timing specification that
BDCOK H and BPOK H must meet; these minimum
are met by the circuits shown in Fiqure 5-17.

timing

requirements

+5 VDC

I_VERCURRENT-I
DETECT

ol5

+12 vDC

o2 &

J ek

(SEE +12 V

;SZ‘j_
as |
FC23

+5V GND
TO +12 VDC

-12vDC

TO MONITOR BD
(pok/ocok ckTS)

|, D24

@36A

6.2V

REG FOR

1
|

CROW BAR

D33
Tisv

MR-6566

MA-0187-82

Figure

5-15

Regulator

4 MS (MIN)

|
I
|

|
|

BPOK H

|
|

BDCOK H

‘lfl | }o-5us (MIN)

[ 2N

{MIN)

YTM

DC OUTPUT

4 MS (MIN)

AC INPUT

3 MS(MIN)-+|

70 MS

POWER-UP

POWER-DOWN

SEQUENCE

SEQUENCE
MR-6567

MA-0190-82

Figure

5-16

Power-Up/Power-Down

Timing

[

D
"

IOo

EEA

+12V

R®

6 E2 3
NESSS5
5

b 4

%‘4

c14
hY|

cl2x<

‘1135

¢
D5

B POK H

{

11e

2 s 8

543
2

2 R46

3R8

A
¢

c1s

£a
E

\l
VAl

61-S

P1-J

-12v

$R6

< R5

1
:

+12v
D1

1ov

®s1v

;

R15

L
o

(RN
P
N
C5Nr

6 E3 4

1°NEsS5

~17

A
12V— v

R23

10 .~

i
¢

B DCOK H
(P1-N)

ClINL

-12V
MR-6568
MA-0184-82

Figure

5-17

POK/DCOK

Circuits

The

POK

circuit

power-up

signals

and the DCOK circuit work the same way during a
Figure 5-18 presents the timing of significant
DCOK circuit during such a sequence. The signal at

sequence.

the

Pl1-J is from the secondary of power transformer T3 in the ac input
circuit.
When
the dc
start-up
supply
voltages
have
attained
a
level that is enough to operate the logic, the signal at Pl1-J is
compared
to
a
reference
level
by
voltage
comparator
EIA.
The
output of
ElA,
pin
1,
is high when
the
reference
1level
at
the
noninverting
input
is
higher
than
the
signal
level
at
the
inverting
input. When the signal at El-1 goes high, capacitor C5
charges; when the signal goes low,
C5 discharges through R15 to
ground.
If
the
peak
voltage
of
the
signal
at
P1-J often
rises

above 14.5 V,
and discharges
After the

El-1 goes low
repeatedly.

circuit

starts

occasionally;

operate,

the

therefore,

first

negative

charges

change

- El-1 triggers the timer, E3, and pin 3 goes high. As long
voltage at pin 6 of the timer stays below the threshold at

as the
pin 5,

pin 3 stays high. The timer output is applied to comparator EA4C,
the leading edge of the output being
integrated by R23 and Cl1.
When
E3-3
goes
high,
the
output
at
E4-13
also
goes
high;

therefore, D4 is turned off and @ V are
Q2,
a
field-effect
transistor
(FET).
BDCOK H signal near ground level.

applied to the gate (G) of
Q2
conducts,
holding
the

E3-5

({ C

(THRESHOLD)

M
S

3MS (MIN)

v
e | —

A
T T

BDCOKH |

i A

E4-13 \

—

——

{ [
) J

MR-6569

MA-0198-82

Figure

5-18

DCOK

Power-Up

Timing

When

the
signal
at
E4-13
starts
to
drop,
D4
conducts
and
a
negative voltage is applied to the gate of Q2; ultimately, this
voltage becomes negative enough to turn off Q2. At this time BDCOK
H is asserted. The time constant of R23/Cl1 is such that at least

elapse

that

BDCOK

The

same

from

type

the

time

voltages

become

active

the

time

asserted

asserted.

circuit

causes

the

BPOK

signal

during
the
power-up
sequence.
However,
the
time
constant
of
R25/C12 at the output of timer
E2
is such that at least
100 ms
elapse
from the time BDCOK H goes high to
the time that BPOK H
does

so.

addition,

the

POK

circuit

that have no counterparts
in the
include equals E4A and E4B, which
power—-down
Figure
started

shows

circuits
when

the

relationship

during
ac

respective

inputs

enough

input

cause

Pl1-J

asserted.

only

the

below
approximately
17
V).
forces the BDOK H signal to
DCOK circuit had been turned

Figure

circuit

significant

power-down

sequence.

(Figure

predetermined minimum.
If the input
below 14.5 V), both the POK circuit
just

components

sequence.

5-19

POK/DCOK

makes

DCOK circuit.
These components
set the circuit timing during a

5-17)

the

circuit

input

the

sequence

drops

signal decreases
and DCOK circuit

However,

POK

signals

This

below

greatly (to
cause their

can

decrease

turned

off

(to

In
this
instance,
the
POK
circuit
go low;
so,
the result
is as
if the
off.

5-19

shows this condition. That is, the input signal, P1-J,
so that the inverting input of comparator ElB does
not
rise
above
the
reference
level
at
the
noninverting
input.
Then, the output of E1B fails to go low to discharge capacitor Cé6
before
the
threshold
1level
1is
reached.
However,
the
voltage
has

decreased

divider

equal

E1B

the

still

enough

inverting

(R7/R8).

(in

The

this

input

voltage

example)

El1A

(R5/R6)

the

inverting

cause

low occasionally; therefore, capacitor
before reaching the threshold level.
When

the

voltage

the output
goes high,

timer

of E2
(pin 3)
goes
closing off D5 and

the

differs
input

output

repeatedly

reaches

the

from
of

ElA

its
is
go

discharged

threshold

level,

low.
The output of comparator
causing Q3 to conduct;
thus,

E4D
the

BPOK H signal is negated. Now the POK circuit uses comparators E4A
and E4B to force the BDCOK H signal low. The output of timer E2 is
applied through the comparators to the reset input (pin 4) of each

timer, E2 and E3. This causes the output of E3 to go low and holds
both
timer
outputs
low
regardless
of what
occurs
at
the
timer
inputs. When E3-3 goes low, the output of E4C goes high, closing
off

D4,

turns

the

input

on,

signal,

negating
P1-J,

the

BDCOK

experiences

signal.

only

momentary

fault,

shown in Fiqure 5-19, the power-up sequence starts automatically
when the timer reset inputs are allowed to go high. The BDCOK H
signal is asserted 30 ms after E3-3 goes high, while the BPOK H
signal is canceled some 100 ms later.

5-21

P1-J m
E1-14 L
E2-5

E2-6

E2-3

(¢
)

E4-2

—_—

E24

—

E34

E33

(¢(

(

B POK H

(¢

B DCOK H

8 Ms

[

MR-6570

MA-0203-82

Figure

5-19

Power-Down

Timing

5.2.2.6

LTC

generates

applied
how the

Generator

the

LTC

signal.

Figure

The

12.6

5-20
Vac

shows

output

the

circuit

transformer

that
Tl

to both inputs of comparator El. The waveforms represent
comparator output controls transistor Q1 to generate LTC.

5.2.3
H9276 Backplane
The
BAll-Y
backplane
is

backplane

that

accepts

both

double-height and quad-height modules. The backplane structure is
unique, providing two separate buses, the extended LSI-11 bus and
the CD bus.
These two buses are shown in Figure 5-21, which also
shows the backplane and points out the power and signal connectors
(J1--33).
backplane.

Modules
are
inserted
in
slots
1
through
9
of
the
The extended LSI-11 bus signals appear on rows A and B;
signals appear on rows C and D.

the

CD bus

The

paragraphs

that

when

designing

modules

fisfisfisfl

JHI=

00—
W

for

include
information
the two buses.

12.6|VAC

+12

V START-UP

)

]

that

LTC
\

12.6 VAC —][\—/[\/:\—
E1, + INPUT

/\/\/\

E1,-INPUT

R
MR-6563

MA-0199-82

Figure

5-2¢0

LTC

Generator

necessary

EXTENDED LSI-11 BUS ROWS
A

r
ROW A

SIDE 1
SLOT 1,

CD-BUS ROWS
A

—

ROW B

ROW C

ROW D

(vFo

S iz

S s

2aan

',.,.1
LY 4N

~y "
10C/‘.|9

|3 9

I40

1256
| Ols

",‘I

! 75

| G138

1514

I8"

]

1012

oh
[

——e

sLoToV

Il \\
A2

}i\
A1

.
V1

NOTE:

VIEW IS FROM MODULE

SIDE OF CONNECTORS
MR-6571

MA-0200-82

Figure

5.2.3.1

Extended

5-21

LSI-11

H9276

Bus

Backplane

Signals

The

extended

LSI-11

bus

signals in the H9276 backplane are provided by rows A and B. Most
of these signals are bused to the same pin in all nine slots of
the
backplane.
Certain
defined
spare
pins are not bused.
Also,
interrupt acknowledge and bus grant signals
(BIAKO
L,
BIAKI
L,
L, amd BDMGI L)
are not bused, being connected, instead, as
shown
1in
Figure
5-22.
The
interrupt
acknowledge
and
bus
grant

BDMGO

signals
are
passed
from module
to module
by etch
jumpers
that
connect pin M2 to pin N2 and pin R2 to pin S2 on connector A of
the
module.
Therefore,
there
can
be
no
empty module
positions
between

that
If

the

uses
the

CPU

these

(which

extended

backplane, an
and B of the

occupies

slot

and

LSI-11

bus

1is

M9404 connector module is
last usable slot
in the

connector module is inserted into
second backplane (refer to Paragraph

details).
connect

A pair

one

H9276

Table 5-1 lists
pin numbers.

I/0

device

option

BC@P2D-05 cables

backplane

the

extended

are

continued

second

inserted into connectors A
first backplane,
while an

M9405

the

signals.

slot

1
2.13.2

(rows A and B)
of
and Appendix C for

used with

these modules

another.

LSI-11

bus

signals

and

the

assigned

ROW A

SLOT 1 L‘MZ

N2e }

iom

829?

SLOT 2 30M2

Nzfi

ich

szI§

]

SLOT 8

& M2

N2 4 ]§

5 ®R2

s2e 4

SLOT 9 § M2

NZO‘S

e ®R2

82.—3

PIN M2: BIAKI L

PIN N2: BIAKO L
PIN R2: BDMGI L

MR-6572

PIN S2: BDMGO L

MA-0206-82

Figure

Table

5-1

Slot,

Side

5-22

Interrupt Acknowledge and Bus Grant
Interconnection, H9276 Backplane

Extended

LSI-11

Bus

Signal

Assignments

Pin
A

BIRQ

BDCOK

BIRQ

-12

BPOK

=12

BDAL

GND

BDAL

GND

BDAL

+12

BDAL

+12

SSPARE

BDOUT

BDAL

SSPARE

BRPLY

BDAL

SSPARE

GND

BDIN L
BSYNC L

BDAL
BDAL

4
5

L
L

MSPARE

BWTBT

L
M

MSPARE

BIRQ

BDMR

BHALT

BREF

GND

+12

GND

PSPARE

+5B

Extended

+ Some

LSI-11

memory

connector
B

slots

bus

module

pins

AVl

through

SPARE

BDAL

SPARE

BDAL

BIAKI

GND

BSACK

BIAKO

BDMGI

BBS7

SSPARE
GND

BDAL

BSPARE

BDAL

BEVENT

BDAL

BDMGO

+12

BINIT

GND

BDALY

BDAL1

SPARE

BDAL

pins.

types

may

require

the

AE]l

only)

for

that

5-25

extended
module.

LSI-11

jumpered
bus

rows

from
A

and

5.2.3.2
Figure

CD Bus
5-23

Signals -the

Rows

C and

connections

D supply

pin
CF2
of
any
slot
higher numbered slot.

the

CD bus

connects
only
Pins on side 2

bus.

signals.

only
five of the nine slots are pictured. The +5 V supply is bused to
all
slots on pin A2 of
rows C and D
(i.e.,
pins CA2 and
DA2).
Also, ground connections on pins CC2, CTl, DC2, and DT]1 are bused
to all slots. All other pins connect only to an adjacent slot. For

example,
adjacent

shows

to
of

Clearly,

pin
CFl
of
the row (B2,

the
C2,

etc.)
connect at the adjacent higher numbered slot
(except DT2,
which connects to CT2 of the adjacent lower numbered slot), while
pins on side 1 of the row (Bl, Cl, etc.)
connect to the adjacent
lower numbered slot
(except pin Al, which connects to Cl of the

adjacent higher numbered slot). Then, each slot, except 1 and 9,
has 33 signal connections (i.e., connections other than +5 V and
ground) to both the adjacent higher numbered slot and the adjacent
lower numbered
signals, group
slot
(slot
X)

slot. To help reference to these two groups of 33
1 is defined as making up the signals connecting a
to
its
adjacent
lower
numbered
slot
(slot
X-1),

while group
2
1is defined as making up the signals connecting a
slot to its adjacent higher numbered slot
(slot X+1).
This group
distinction is maintained
in Table 5-2, which lists row C and D
pins for slot X and assigns signal names to each pin. Generally,
group 1 signals are found
are found on side 2 pins.

side

pins,

are

called

out

callout

such

while

group

signals

NOTES

Bus

pins

BC2,

etc.

example,

The

AK1l,

means

row A,

following

spare

pins

bused:
S
SPARE
A

SPARE
1
S
and
M
SPARE

AS1,

side

are

SPARE
B
(in

for

not
8;
M
each

slot,
AKl
1is connected
to ALl
and
BKl is connected to BL1); P SPARE 1
and

are

not

BDMGI

SPARE
L,

bused:
and

The

following

BIAKI

BDMGO

signals
can
Handbook.

If a CPU is installed in slot
AFl1
of
slot
1
(formerly
a
becomes S RUN L.

Descriptions
of
these
Microcomputer Processor

signals

BIAKO

found

1, pin
spare)

the

1979--19890

Wl,
W2,
and
W3
backplane
jumpers
are
removed
when
the
BAll-Y
mounting box is used as an expander box
(without a CPU module).
Otherwise,
these
jumpers
short
together
pins
in
the
first
backplane slot COl1KI to COlLI and DOI1KI to DO1LI, respectively.

ROWC
+BV

SLOT

GND

]

GND

A1A28182C1C2D1D2E1EaF1F2H1H2J
15K 1 KoL LaM{MaN NP
1P2R1R2S1S2T1ToUy 2V1v2

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I —J !— 1 r

I |

A1A28132C1C2D1DzE1E2F1F2H1H2J1J2K1K2L1L2M1M2N1N2P1P2R1R25182T1T2U1UI2V1V|2

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]

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e

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BI C A1A281B2C1C2D1D2E1E2F1F2H1H2J1J2K1K2L1L2M1M2N1N2P1P2R1R28182T1T2U1U2V1V2 ’

GND

CA1A28‘|BZC1CZD1D2E‘|E2F1F2H1H2J‘|J2K1K2L1L2M1M2N1N2P‘|P2R‘|R28282T1T2U1U2V1V } C A1A2B1B2C1CZD1D2E|E2F1F2H1H2J1J2K1K2L1L2M1M2N1M2P1P2R1R25152T1T2U1U2V1V2
l

LZ-S

ROWD

GND

(!_

T 1T 1

A1A28182C1C201DzE1E2F1F2H1H2J1J2K1K2L1L2M1M2N1N2P1P2R R28182T1T2U1U2V1V2

| I LI I i I 1 1 1 I |

T
)
T
O
T
YP
A
I
‘

Iyt

[ |

r Trrrrrrrr
ey

rrrrrrr-t - rrTr T 177 T

A1A281BQC1CQD1D2E1E2F1F2H1H2J1J2K1K2L1L2M1M2N1N2P1P2R1R28132T1T2U1U?V‘]VIQ

A1A2B1B2C1CyD1D2EEgF {FoH H2J1JaK1KaL1 LoM1M2N

NP 1P2R1R251S2T1ToUUaV V9

NOTE:

WITH SOME PROCESSORS, W2 AND W3 INSTALLED ENABLE THE CPU

TO OPERATE

INSLOT 1. IF THE BACKPLANE IS BEING USED AS AN EXTENDED BUS, REMOVE
THE JUMPERS (THE CPU MUST BE PLACED IN SLOT 1 OF THE MAIN
BOX ON LY).
IN THE DYS50, JUMPERS W2 AND W3 HAVE NO FUNCTION. THEY
ARE NOT CONNECTED
TO ANYTHING.
MR-6578
MA-0183-82

Figure

5-23

CD Bus

Interconnections

)

Table

5-2

Bus

Signal

Pin Assignments

Row

Side

INTCON

Group

INTCON

Group

INTCON

Group

GND

Side

V
2,

Group

INTCON

Group

INTCON

Group

INTCON

Group

INTCON

Group

INTCON

Group

INTCON

Group

INTCON

Group

INTCON

Group

7,
8,

Group
Group

2
2

Group

INTCON

Group

INTCON

Group

INTCON

Group

INTCON

18,

Group

INTCON

10,

Group

INTCON

11,

Group

INTCON

11,

Group

INTCON

12,

Group

INTCON

12,

Group

INTCON

13,

Group

INTCON

13,

Group

INTCON

14,

Group

INTCON

14,

Group

GND

INTCON

33,

Group

INTCON

15,

Group

INTCON

15,

Group

16,

Group

INTCON

16,

Group

INTCON

17,

Group

INTCON

18,

Group

INTCON

18,

Group

INTCON

17,

Group

GND
19,
28,

Group

2
2

INTCON

19,

Group

INTCON

20,

Group

INTCON

Group

INTCON

21,

Group

INTCON

21,

Group

INTCON

22,

Group

INTCON

22,

Group

23,
24,

Group
Group

2
2
2
2

INTCON

23,

Group

INTCON

K
L

INTCON

24,

Group

INTCON

25,

Group

INTCON

25,

Group

INTCON

26,

Group

INTCON

26,

Group

INTCON

27,

Group

INTCON

27,

Group

INTCON

28,

Group

INTCON

28,

Group

29,
30,

Group

2
2

INTCON

29,

Group

INTCON

30,

Group

INTCON
INTCON

Group

GND

INTCON

33,

Group

INTCON

31,

Group

INTCON

31,

Group

INTCON

32,

Group

INTCON

32,

Group

5.2.3.3
Module Requirements for H9276 Capability -- Modules used
in the BAll-Y box are of two classes:
those that function with
18-bit addressing and those that function with 22-bit addressing.
A

double-height
module
that
has
been
designed
for
18-bit
addressing capability can be used with both the KDFl11-A and the
KDF11-B processor modules. Such a system is limited to 256 Kb of
memory; however, both the KDF11-A Rev C and later and the KDF11-B

function use
designed
for
backplane
CD
signals.

Quad

designed

modules

compatible
BDAL

module
BIAK

with

18--21

connecting

22-bit addressing
system.
A double-height module
the
CD
bus
can
only
be
inserted
into
the
H9276
bus
rows.
Table
5-3
1lists
the
compatible
CD
bus

the

for

another

connector

and

BDMG

CD Bus
+5

5-3

reason.

CD Bus

these

H9273

long

backplanes

from

jumpers

a
portion
of
each
the wiring of pins M,
and H9276 backplanes.

Signals

INTCON
INTCON

4,
5,

Group
Group

1
1

Group

for

Number

CA2,

DA2

¢crl,

backplane,
they

have

do
etch

permit

not

CC2,

6,
10,

Group

CM2*

INTCON

11,

Group

jumpers

passage

INTCON

13,

Group

INTCON

14,

Group

CS2*

INTCON

17,

Group

DC1

INTCON

19,

Group

DD1

INTCON

20,

Group

DE1

INTCON

21,

Group

DF1

INTCON

22,

Group

DH1

jumpers

between

placed
the

Compatible

DT1,

Quad

the

to
show
the
in rows A and

Modules

DC2

CH1
CN2*
CR2*

Etch

backplane
N, R and S

are
use

CEl
CF1l

INTCON

must

H9276

INTCON

Both

signals.

Signal

passage

with

and

Also,

GND

used

backplane

only.

Figure
5-24
shows
differences between
C of both the H9273

Table

H9276

on
BIAK

CM2

modules
and

and

CN2,

used

BDMG

CR2

signals.

and

H927¢

CS2,

respectively,

backplane

allow

SLOTS

ROW A

x%"

ROWB

Nie }

20|

R1e

Ro#|

ROWC

S1e }%

; M1é

s29

ROWD

N2¢

R2®

Nile }%RM

M29

S1é }%

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X+ émzh N2 3 éRZ?

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S2¢ 3 €

Bfiwzo N2 e } Squ S2e 5 7

X+ &M‘Io

S1e

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Mi®|

Nie

Ri®|

Ni1e

R1e

N2 T
®

R2¢T S2 @1

} (l

M1®

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M2®1 N2e'

}

R1®

S1¢

R1é

S14 3 i

;>H9276

R2®1
S2e

}7
MR-6573
MA-0212-82

Figure

5-24

5.2.3.4

H9276

Modules

Backplane

Designed

Wiring

(Rows

A and

for

the

H9276 Backplane

module

can

use

Only -- Modules

can be used in the H9276 backplane either singly or in sets. The
single, or standalone, module communicates with other modules only
through
the
extended
LSI-11
bus.
A
double-height,
standalone
module
1is
inserted
into
extended
LSI-11
rows
A
and
B.
A
quad-height,

but
A

cannot

module

standalone

use
set

the group
1is

made

2
up

the

group

INTCON

signals

signals.*
of

than

one

module.

The

module

occupying the highest numbered slot of the set must not use the
group 2 INTCON signals. All other modules of the set can use both

the

group

and

group

INTCON

signals.

The

module

the

lowest

numbered slot can use the group 1 signals as test points;* its
group 2 signals communicate with the second module of the set.
Each module after the first communicates with its neighbors with
both the group 1 and group 2 signals except, of course, the last
module of the set, which does not use the group 2 signals.

bus

pins

can

group

created
2

pins

for

each

module

center

set

module.

connecting

For

example,

group
1f

you

have
a
four-module
set,
you
can
create
an
INTCON
4
bus
by
connecting pin CEl to pin CE2 on both the second and third modules
of

the

set.

Module sets can be expanded at any time. However, the set can be
expanded
upward,
only.
That
1is,
if
a
module
1is
added
to
an
existing set, it must occupy the lowest numbered slot of the new
set.

standalone

module

might

have

INTCON

10,

group

shorted

INTCON 11, group 1, and INTCON 13, group 1, shorted to INTCON
14, group 1. Refer to Paragraph 5.2.3.3 for an explanation.

5-30

5.2.3.5
Module

Electrical
--

Protection

for

Quad-Height

Use

only quad-height modules
the
H9276
backplane.
(The

handles

and

Double-Height

that
have
extractor-type
extractor-type
handle
is

in
shown in Figure 3-4). These handles help you to insert and extract
the
module.
More
importantly,
the
card
frame
of
the
BAll-Y
is
designed
so
that
these
handles
prevent
a
module
from
being

inserted
upside
down.
If
a quad module having
plastic U-shaped
handles
must
be
used,
confirm
that
the
module
is
inserted
correctly; i.e., the component side of the module must be on top.

Double modules have only plastic U-shaped handles.
These modules
can be inserted in backplane rows A and B or C and D, depending on
whether they are designed to use the extended LSI-11 bus or the CD
bus,
in order.
Obviously,
it is possible to insert these modules
not

only

backwards

but

also

the

wrong

bus.

Therefore,

electrical
protection
must
be
included
in
the design of double
modules; i.e., the assignment of supply voltages to connector pins
must be done so that
if a module
is incorrectly inserted
in the
backplane, supply voltage will not be applied to signal pins.
Electrical

protection

afforded

the
design
be inserted

designed to
be inserted

for

extended

of
in

LSI-11

bus

double

modules

the
H9276
backplane.
A double
the extended LSI-11 rows (A and

module
B)
can

upside down with no damage to power
supply voltages.
That is, a module pin that is supposed to receive +12 Vvdc, gets
+12 Vvdc whether
the module
is right-side up or
upside down.
The
same protection
is afforded
if the module
is inserted in the CD
bus,
right-side
up
or
upside
down.
Of
course,
an
incorrectly
inserted module will not work correctly.
If the system fails to
operate
(either
totally
or
in
a
specific
area)
after
module

installation
correctly

replacement,

the

backplane

sure

before

methods.

that

all

trying

modules

other

are

inserted

troubleshooting

Unfortunately, the backplane cannot provide protection for modules
designed
to
use
the
CD bus.
Therefore,
the
protection must
be
designed into the module itself. The pins listed in Table 5-4 are
those that must be protected
from incorrect placement of the CD
bus module (the double-module connectors are labeled A and B even
though they are
inserted
in CD bus rows C and D,
in order).
For
example,

backplane

was

module

pins

CA2

designed
for
the
and DA2,
and no

CD bus
receives
+5
Vdc
from
other
voltage.
If the module

inserted
in
the
extended
LSI-11
bus
(A
and
B),
it
receive +5 Vdc, =12 Vdc and +12 Vdc on the pins listed in

5-4.

would
Table

Téble 5-4
Module

Vulnerable CD Bus Double Module Connector Pins
Voltage to Which
Might Be Exposed

AVl,

BV1,

AEl*

AD2,

AS1l,

BD2,

5.2.4
Figure

+12

1linked

with

the

front

and
1indicators.
(Paragraph
2.4
tells
how
and
how
to
interpret
the
indicators.)

components

the
the

BSl

Front Bezel Assembly
5-25
represents
the
1logic

switches
switches

to
of

are

mounted

printed

circuit

board

panel

to
use
the
The
1logic

that

attached

rear of the front panel. A signal cable that plugs into J1
printed circuit board carries the signals between the front

panel

and

the

remote

switch

Indicator

power

supply

connector

1lights

master

board.

the

front

panel.

and

1light

when

the

cabled

power

supply

the

operating correctly and when the CPU is running. D1, the PWR OK
indicator, lights when the B POK H signal from the power supply is
asserted.
D2,
the
RUN
indicator,
1lights
as
1long
as
the
CPU
generates

the

signal

RUN

This

signal

1is

applied

the

positive
E3A. The

trigger
1input
of
retriggerable
one-shot
multivibrator
basic pulse width of E3A is greater than the period
(t)
of
S
RUN
L
(Figure
5-26);
therefore,
E3A
is
continually
retriggered by S RUN L and stays on until S RUN L is negated. The
1 output of E3A causes the RUN indicator to light (the jumper in
W4 is in place when the CPU is inserted into the backplane).
In meeting its more obvious function, switch S2 grounds the B HALT
L signal when it is moved to the HALT position (down). Then, the
CPU can be forced to halt typical program execution from the front
panel
of
either
the
main
box
or
an
expander
box.
To
continue

operation after using the HALT switch, return the HALT switch to
the enable position
(up)
and enter a P command
from the console
terminal.
(Refer
to
Chapter
4
of
the
1979-1989 Microcomputer
Processor

Handbook

for

description

console

CPU

front

ODT

command

but

you

usage.)
Not

only

can

also reboot
switch,
S1,

you

1it.
the

halt

the

When you 1lift
CPU halts and

power-up
sequence,
operating
position

from

the

panel,

can

and release the momentary RESTART
then automatically carries out
a

Figure
5-25
shows
(down).
When
the

switch
S1
in
the
typical
operator
1lifts
and
then

releases
S1,
allowing
it
to
return
to
the
down
position,
a
positive-to-negative
change
1is
applied
to
the
negative-trigger
input of one-shot multivibrator E3B.
This negative change causes
the one-shot to generate a gate of 1 us (minimum)
duration; this
gate first negates BDCOK H and
complete the reboot operation.

then

permits

reasserted

B DCOK H

AAA

VW=

AAA

co°

OFF

- =

PWR OK

|
T HALT

RUN 77

L——

138g

M—

cmes

B HALT L

— e

SPARE

re— —

+5 VDC

AAA

GND

AUX

AAA

SRUNL

LTC

BPOKH

1
o

i
74123
AAA

E3A

S\"—
RESTART

v
|~4m

AAA

[o+]

[4V]

74123

—'l
NOTE:
S2 IS SHOWN IN THE OPERATING

POSITION (UP);
S1 1S SHOWN IN

THE OPERATING POSITION (DOWN).

MR-6679
MA-0186-82

Figure

5-25

Front

Panel

Logic

E3A __r

BASIC

PULSE

I____J

L——|

|——j

S RUN L-—I-

L__

WIDTH

MR-6574

MA-0207-82

Figure

5-26

RUN

Indicator

Waveforms

The third switch shown in Figure 5-25 is the AUX switch, S3. The
the
however,
any function;
for
used
be
can
contacts
switch
following two mutually exclusive functions are the most common.
One function is to operate as a system on/off switch when a power
controller is part of the system;
Jjumpers W1l and W2 must be
removed if this feature is to be used. The other function is to
operate as an on/off switch for the power supply generated LTC
signal; jumpers W1 and W2 must be installed if this feature is to
be

used.

When

used

system

on/off

switch,

connected

applied

the

power

controller by a cable that plugs into connector J2. With S3 in the
ON position,

primary power

distributed by

it through the system.

controller

In the LTC application,

and

S3,

when in the ON position, permits the LTC signal to be used as an
LTC interrupt in the CPU. In the OFF position, S3 grounds the LTC
signal,
which
1is
programs are being

a
necessary
executed.

feature

when

certain

diagnostic

APPENDIX

DYS50

Figures A-1

through A-6 show the

kernel system jumpers and switches.

KERNEL

MODULE

Row1 ([

MEMORY
MODULE

row2 |77

DECdataway

rows |P7ZZ&V3
18 NMB080)

INTERFACE

SYSTEM CONFIGURATION

factory settings for

SWI®
PROCESSOR

oOW2°

811862/

27777
)

OPTION 1
(HIGHEST PRIORITY)
OPTION 2
OPTION 3
OPTION 4
OPTION 5
(LOWEST PRIORITY)

ROW9
VIEW IS FROM MODULE SIDE OF BACKPLANE
H9276 OPTION POSITIONS

STANDARD FACTORY JUMPER CONFIGURATION
JUMPER

“W1

JUMPER
coioe

FUNCTION

THE H7861 POWER SUPPLY

GENERATED LTC SIGNAL IS USED

TO ASSERT BEVNT L SIGNAL

W2, W3

ouT

THESE JUMPERS HAVE NO EFFECT

.ON DYS50 OPERATION

*W1 MUST BE REMOVED FROM ALL EXPANDER BOXES

IN A MULTIPLE-BOX SYSTEM SINCE ONLY

THE BOX CONTAINING THE KDF11-BB (M8189)
MODULE MUST BE THE SOURCE OF THE LTC SIGNAL

Figure

A-1

MA-71018

DYS50 Kernel System Backplane
Configuration

all DYS54

SIDE 2

oflo0o

—_

O'Wi-o o]

—_ ]

Ows oo

SWITCH

°©

CONTACTS

[e]

{RUN, PWR OK)

LED CONTACTS

{3, 62, 81)

NOTES:
1. VIEW IS FROM THE REAR OF THE BEZEL

WHEN THE BOARD IS MOUNTED ON
THE BEZEL.

2. JUMPERS ARE MOUNTED ON SIDE 2.
FACTORY JUMPER CONFIGURATION

JUMPER

FUNCTION

STATE

W1,

ouT

ALLOWS THE AUX ON/OFF SWITCH

TO TURN THE SYSTEM POWER
ON AND OFF
W3

ouT

CPU IS MOUNTED IN THIS

BACKPLANE

ENABLES THE RUN INDICATOR
BECAUSE THE CPU IS MOUNTED
IN THIS BACKPLANE
MA-07378

Figure

A-2

DYS50

Bezel

Factory

Printed Circuit
Configuration

Board

J45 344 143 442

b 74

‘o] vy

+5V PWR ON LED

) S

‘(131ONSOLE

pbf Gy
L2 g [:.mo re=———1
aREkHA
0 440
| 1seT ker1188 opTiON)
|
|
MSPJ

146

0139
J38
137
0J36

—

J21

e
J26
oz

COMMERCIAL INSTRUCTION

|
|

435
34

E78

DIAGNOSTIC

l
I

COMMERCIAL INSTRUCTION

SET

DISPLAY

FLOATING POINT

(KEF11-AA OPTION)
E76

0J32
0J31

430

o)o8

LauD

RATE

SELECT (S2)
OFF

SLU 1

1lCam|

SLU 2

ROM/EPROM

SOCKET
(HI BYTE)
E127

13
1

E75

MEMORY MANAGEMENT

Cmm|ioALoo

Cas

(MMU)

(cPu)

DIAGNOSTIC (S1)

OFF

. -

DATA AND CONTROL

BOOT/

E74

1
Il

(CI1

E114

{1pALO7

E102

15:08

E126 07:00

L -

043

©J15

ROM/EPROM

(LO BYTE)

0117

0J16

[}
S
SOCKET

0J19
0J18

NOTES:

0414

J23

—

0J13

1. INSTALLED JUMPERS SHOW THE

0 J11

2. WHEN MASKED ROM S ARE USED

312

124 ¢ g oJ22

FACTORY CONFIGURATION.

J24 1S CONNECTED TO J23.

J22 1S NOT CONNECTED.

J10

—

3. WHEN EPROM S ARE USED J22 IS
CONNECTED TO J23. J24 1S
NOT CONNECTED.

—
I

4. SWITCHES S1-1,2,4,7, AND

52—-1,5 ARE SHOWN IN

“ON’* POSITION.,

MR-5448

Figure

A-3

Factory Configuration
DYS50

the

KDF11-BB

(M8189)

the

MA-0219-82

16K MOS CHIPS
BITS
r-

BITS

WRITE WRONG

ROW 0

BYTE

BITS

PARITY TESTING

PD1

ROW 1

M8067-KA

ROW LATCH _
17

3112

ROW 2

C 1o

v----010

o1}

SYSTEM

1070

L————— 8

i
|

ROW 0

POV

Tas | | 1a |

|13 |

f12 |

[

!
]

= we
Xo

015!

.._{‘.- 016 1
017

= °K|

o1gl

o1l

L= 2

INHIBIT

Lo I

£33

ROW1{ EB

"E—on

PD1

BY1TE <

JUMPERS

=YY=,

pi——
Fr-=---

ROW 3

STARTING ADDRESS

012

COLUMN LATCH

| 27|
18/22BIT

PING6TO7

=" 1 Galen=

| IMISOH]
TM,
]| paLten[
T, 1
[
45 43 441
6§ 7 8= |

3
i_oa !

ROW 2 {

|CSR ADDRESS JUMPERS

ROwW3

oflllo VDD

POWER JUMPERS

W15 mm W14

Wizwi2
o-:)ow °
-

POWER JUMPERS

ofililo

offilo

o Jo
w2

16K MULTIPLE VOLTAGE DEVICES
NON-BAT BACK-UP

BAT BACKUP

VOLTAGES

-5

w11

w10

W13

w12

+12 vDD
+6 CR

o 3o
wi

—

GRANT CONTINUITY

POWER JUMPERS FOR 16K MOS CHIPS

W1 AND W2 IN FOR

WITHOUT BATTERY BACKUP

Q/Q MACHINE, Q22/Q22

—l— POWER JUMPER IN FOR 64K CHIPS

MACHINE

‘W1 AND W2 OUT FOR

—{J}—— POWER JUMPER IN FOR 16K CHIPS

Q/CD AND Q22/CD MACHINE

—{l—— POWER JUMPER IN FOR BOTH 64K/16K CHIPS

64K SINGLE VOLTAGE DEVICES
NON-BAT BACK-UP

BAT BACKUP

DECOUPLE +5

w12

+5 CR

W13/W15

w14

+5 VDD

VOLTAGES

MA-71488

Figure

A-4

Factory

Configuration

the

MSV11-P

(M8@67-KA)

DYS58

W12

W16

W20

W17

W15

W14

W23

w22 W21

—

p O30

10|

iy
B

{

FACTORY JUMPER CONFIGURATION
IN: W7, W8, W9, W10, W17, W18, W19, w20

OUT:

ALL OTHERS

JUMPER FUNCTIONS
JUMPER

USE

W1-Ww8, w12, w13

LSI-11 BUS ADDRESS

WI-W11, Wi4, W15

VECTOR ADDRESS

W16

HOLD ON B SACK L

W17, W20

DMA TIMERS

W18, W19

CONNECT PINS

W21-W23

RESERVED
MA-7104

Figure

A-5

ISV11-B

M808# Module

Configuration

Standard

fl HE] e 5
g

0L = i

—

L1y

——

—

Zaz ()

10—

i [ e s

7 ¢l
3 13

;3
—0
U

(]

JI_
0000

0 13 13

00000000000

“— E

200 0ho g

————— rmo———=—- 1

[

wW1-w8

FACTORY JUMPER CONFIGURATION

OUT: ALL OTHERS

JUMPER FUNCTIONS

JUMPER

USE

w7, ws

PROM SELECTION

W1-W6, W9, W10

PROM POWER
MMMMMM

Figure

A-6

ISV11-B
Standard

M8@84

Module

Configuration

APPENDIX

SPECIAL

B.l

DC@P@F3 INTERRUPT CONTROL

(Figures B-1,

B-2,

CIRCUITS

and B-3)

The
interrupt control
chip
is an
18-pin,
#.762 cm
(0.300
1in)
center, DIP device. It provides circuits to perform an interrupt
transaction
in
a
computer
system
that
uses
a
pass-the-pulse

arbitration scheme. The device is used in peripheral interfaces
and has two interrupt channels labeled A and B. The A section is

higher

impedance

priority

input

than

circuits

the

high

section.
drive

Bus

open

signals

use

collector

high

outputs,

which allow the device to attach directly to the computer system
bus. Maximum current required from the Voo supply is 140 mA.
B.2
The

DC@P4 1/0 ADDRESS DECODER (Figures
protocol chip is a 20-pin, 0.762 cm

device.

necessary

functions

control

data

flow

into

B-4, B-5, and B-6)
(@#.300 in)
center,

selector,
and

out

providing

DIP

signals

four

word

registers (eight bytes). Bus signals can directly attach to the
device because receivers and drivers are included on the chip. An

RC delay circuit slows the peripheral interface response to data
transfer
requests.
The
circuit
1is
designed
so
that
1if
tight
tolerance is not required, only an external 1K 20 percent resistor
is necessary. External RCs can be added to vary the delay. Maximum
current required from the Vcc supply is 120 mA.

vCC

RQSTA H #
.

ENADATA H

ENAST H

SET

VECTOR HO1

VECRQSTB H

ENA

ENACLK H

be
0
CLR

>%LR°
u

TM\

vce

17D RQSTAH

BDIN L O3

16[D ENAST H

INITO L4
151 ENADATA H
BINIT L s DCOO3 \1henacLk v

_iDc

BIAKO

e o
—
cr | L)

L O6

BIAKI L7
BIRQ L8

GND ]9

131 ENBCLK H

12]1 ENBDATA H
1P ENBST H

100 RQSTB H

BIAKI L

mD’s

BINIT L

BIAKO L
'

BOIN L %

_D"P

BIRQ L

ENBST H

_D—-VECTOR H

Po)

ENBDATA H

SET
oy

D1
ENB

ENBCLK H

CLR

—

CLR

—‘Do__<{>_vecaosra H
vCC

RQSTD H

CLR

INITO L
IC-0173

MA-5505

Figure

B-1

DC@A3

Simplified

Logic

Diagram

BINIT

INITO

300

300:

MIN { MIN
|

7-35

ENA DATA

ENA CLK

30 MIN —-b'l

-—

7-3’:0——»‘I

ENA ST

—

RQSTA

15-65—»‘
:

BIRQ

j— —>:
]

a— 20 -90

[}

{

BDIN

]

:
3smmw—fi

BiAKI

!
35Mm—+i
]

10-45—»

VECTOR H

>
|

—
|

|
|

[
|

12-55 —

BIAKO

|e10-45

fe—12-55

NOTE:

Times are in nanoseconds
11- 4150

MA-5503

Figure

B-2

DC@a3

Interrupt

Section

Timing

Diagram

7-35|

_I_

INITO

ENB DATA H
|

ENB

30 MIN —Di

ST
H

RQSTB

7-30—.:

—

15- 65—

]

|[e—

+——20-90

—f—— | —

——

—

. ——

BIRQ

-—

ENB CLK H

30 MIN—->=

—

ENA CLKH

—— w—

ENA DATA H

—

BDIN

35 MIN —»

]

Jo—
|

VECTOR H

10-451es
|

35 MIN —
|

-3~

BIAKI L

—

RQSTA

———
w—

———

—

ENA ST H

10-45

10-45 ts

< 10-45

]
i

|
|

VECRQSTB H

15—65:4—-—-

15-65

NOTE:
Times are in nanoseconds
11-4151

MA-5502

Figure

B-3

DCP@P3

and

Interrupt

Section

Timing

Diagram

Sections

VECTOR H 1

20 1 vee

BDALZ L 2

19 00 ENB H

BDALI L O3

18 ) RXCX H

BDALO L 4

17 ] SEL6 L

BWTBT L O5

16 0 SEL4 L

BDIN L O7
BRPLY L 8

14 0 SELO L
13 N OUTHB L

BDOUT L o

12 0 OUTLB L

BsYNC L Oe D004 45 0 SEL2 L

GND 1o

1 0 INWD L

[—VW___VCC

ENB H

BSYNC L

ENB

:{>

BDAL2 L

LATCH

c o

D
02

LATCH

—C

DECODER

0—

ol
BDAL!

oo' 1

BDALO L

BWTBT L

<{>

o———SELO
L

LATCH

c o

SEL4L

0———SEL 2L

LATCH

O—SEL6 L

OUT HBL

Jo-

OUTLB L

RXCX H

BRPLY

800

uT L

omn L

—o>

VECTOR H

IC-0174
MA- 5504

Figure

B-4

DCPP4

Simplified

Logic

Diagram

BDAL (2,1,0) L W25 MIN|25 MIN I/////////////////////////j

ens w0) s, | w0000
BSYNC L

-34--

!
|
|

T5-»

SEL (0,2,4,6) L

—-HI Té

{

BOOUT L

15 MIN. —»f

je—
]

]

OUTLB L

—»i T9 j&+—

BDIN

— T11 :4-—

]

—Hl T10 e

]

OUTHB L

|
|

INWD L

fi‘ (l

—»: T12 ja—
|
|

BRPLY L

i T13 f—
|

|
]

g AL ~=PYAY
1

T
I

VECTOR H

>
(

Ry Cx H

—iTi5

— > T16 |—
|

* TIME REQUIRED TO DISCHARGE Ry
Cx FROM ANY CONDITION

ASSERTED =150ns

NOTE :

Times are in nanoseconds
11-4348

MA-550I

Figure

B-5

DC@PP4

Timing

Diagram

Vce

Vee

%son

280.0

FROM

oUTPUT >1
= 200pF

OUTPUT >

= 15pF

4
LOAD

FROM

OUTPUT >~

LOAD

—
150 pF

DIODE
FD777

_L_

LOAD C
11-4349
MA-5499

Figure

B-6

B.3

The

DCP@5

4-bit

DIP,

BUS

logic.

generator,

outputs

logical

Schottky

(Figures

2@-pin,

device.

the

circuit

useful

interrupt

for

allow

inputs

direct

Its

B-7

and

0.762

primary

isolation

comparison

impedance

to
peripheral
inputs and

Configurations

TRANSCEIVER

addition

high

transceiver

low-power

provides

has

DCPP4

for

and

vector

(8.300

use

function,

address

high

B-8)

the

selection

addresses.

drive

(70

center,

peripheral

device

and

The

mA)

in)

bus

open

also

constant
I/O

connection

to a computer's data bus.
a bidirectional
port, with standard
20 mA three-state drivers.
Data on this port
is
inversion of the data on the bus side.

side

port

collector

includes

The

TTL
the

Three

address jumper inputs are used to compare against three bus
inputs and to generate the signal MATCH. The MATCH output is open
collector, which allows the output of several transceivers to be
wired-ANDed to form a composite address match signal. The address

jumpers
can
also
be
put
into
a
third
logical
state
that
disconnects
that
Jjumper
from
the
address
match,
allowing
for
"don't care" address bits. In addition to the three address jumper
inputs,
a
fourth
high
impedance
enable/disable the MATCH output.
Three

can

vector

three
control

passed

the

jumper

inputs

computer

the

bus

signals

1lines,

are

receive data, transmit
from the VCc supply is

are

used

bus.

input

The

overriding

decoded

data, and
100 mA.

give

1line

generate

three

disable.

used

constant

that

inputs

directly

drive

control
three

1is

1line

action.

operational

Maximum

current

Two

states:

required

JAT L

JAZ2 L

~ 20

Vee

JA3 L

MATCH H

3 -

REC H

XMIT H

5 —

DAT3 H

6 =

DC005

DAT2 H

DATO H

DAT1 H

— 16

JV3 H

L 15

JV2 H

- 14

JVI H
MENB L

BUS3 L

8 -

BUS2 L

BUSO b

10—

L 11

8UST L

GND

BUSO

BUST

II>

Jl/\

JA1 L

BUS2 L
JA2

s L
JA3

ll>

;

‘

LIS

Hi-

REC

] Ny

I_
NN
L~
i

XMIT

Jv1

DAT1

Jv2

DAT2

Jv3

DAT3

MATCH

s
B
[\
J

L—f‘v

DAT0

IC-DC 005

MA-5498

Figure

B-7

DCPPS5

Simplified

Logic

Diagram

TRANSMIT

XMIT H

REC H (GROUND)

BUS L-OUTPUT

DATA

fe-sT030ms

H-INPUT

DATA

le- 5 TO 25 ns

FROM BUS

(BUS INITIALLY

HIGH)

(GROUND)

REC H

DAT H-OUTPUT

e 0 70 30ns
HiZ ———
-]
- 8 TO 30ns

BUS L—INPUT

]

le0 70 30ns

RECEIVE

XMIT

-5 70 30ns

RECEIVE

XMIT

BUS

5 TO 25ns
-

DAT

DATA FROM

BUS

(BUS

IN{TIALLY LOW)

H (GROUND)

REC H

DAT H-OUTPUT

HiZ——J__—
-

BUS L — INPUT

l+-0 10 30ns |

e~ 0 70 3005

I—————HiZ

le—
8 TO 30ns

VECTOR

TRANSFER TO

BUS

JV
H

- 20ns MAX

-fi

le- 20ns MAX

l@- 10 TO 40ns

BUS L - OUTPUT

ADDRESS

BUS | — INPUT

DECODING

- X
—>|

MATCH H
—

MENB

j@—
5 TO 40ns

RECEIVE

XMIT H
REC

|- 10 TO 40ns
X

MODE

LOGIC

DELAY

—-»

e~
40 TO 90ns

DAT (3:0) H (OUTPUT)
HZ
- 4892

MA-5500

Figure

B-8

DC@@P5

Timing

Diagram

APPENDIX

PDP-11/23B

BACKPLANE

AND MODULE

CONFIGURATION

C.l
GENERAL
LSI-11 systems can be either single or
yours
1is
a
single
backplane
system

multi-backplane systems. If
(Figure
C-1),
observe
the

following

configuring

C.2
The

three

bus

rules

when

SINGLE-BACKPLANE CONFIGURATION RULES
following are the rules for single-backplane

The

extended

LSI-11

bus

can

support

it.

configuration.
to

i.e., the processor has on-board termination for
of the bus; after 20 ac loads, the other end of
must be terminated with 120 ohms.
2.

The

terminated

The

bus

can

bus

support

can

support

EXTENDED LSI-11 BUS
AL

2 —MSV11-P—f

{

]

4 —QUAD OPTION

5 —DUAL OPTION

6 —QUAD OPTION

7 —DUAL OPTI(I)N
8 —DUAL OPTION

9 —ISV11-B (M8084)
BA11

loads.

3 —ISV11-B (M8080)

C-D BUS
Y

I
—~KDF11-B—

loads.

H9276 BACKPLANE
B
C

i
1

MAIN BOX
MR-6592

MA-0205-82

Figure

C-1

PDP-11/23B
Backplane

(H9276)

Single

Configuration

loads;

one
the

end
bus

If your
observe

system has more than one backplane
the following eight rules.

MULTIPLE-BACKPLANE
C.3
The following are the rules
1.

backplane

The

Both

than

total
ends

terminated
have
have

CONFIGURATION RULES
for multiple-backplane

three
can

the

with

backplanes

have more

number

(Figures

can

than

loads

ohms;

an impedance of 120 ohms and
a termination of 128 ohms.

together.

than

(PDP-11/23B)

the

C-3),

loads.

be more

line

i.e.,

and

configuration.

connected

cannot

termination

120

C-2

24.
must

first

backplane

must

last

backplane

must

the

The cable connecting the first two backplanes (i.e., the
main box and expander box 1)
must be at least 150 cm
(5
ft)
long.
The

cable

connecting

the

backplane

expander

box

the backplane of expander box 2 must be at least 122 cm
(4 £t)
longer or shorter than the cable connecting the
main box and expander box 1. A 365 cm (10 f£t) length of
cable is advised for ease of installation.

The

combined

system

length of

cannot

If the cables
characteristic
systems.

exceed

both cables

488

(16

the

three-backplane

ft).

are customer-supplied,
they must have a
impedance of 120 ohms for the PDP-11/23B

BA11-YA
H9276 BACKPLANE
1 ———KDF11-BB

2 ———MSV11-P

DUAL OPTION

DUAL OPTION——

5 ——QUAD OPTION

DUAL OPTION

QUAD OPTION

DUAL OPTION

9 ———M9404-00

BC02D-05
(TYPICAL)

BA11-YC
H9276 BACKPLANE

10 ————M9405-YA
11

QUAD OPTION

ISV11-B (M8080)

14
15

16
17

ISV11-B (M8084)

NOTES:
1. THE TOTAL DC LOADS OF BOTH BOXES CANNOT EXCEED 20.

2. EACH BC02D CABLE MUST BE AT LEAST 150 CM (5 FT) LONG,

IF CONNECTED FROM THE MAIN BOX TO THE FIRST EXPANSION BOX.
3. EACH BC02D CABLE MUST BE AT LEAST 300 CM (10 FT) LONG,
WHEN CONNECTED BETWEEN THE SECOND AND THIRD EXPANSION BOX.
MR-6594

MA-0201-82

Figure

C-2

PDP-11/23B
Backplane

(H9276)

Two

Configurations

H9276

KDF11-BB

MSV11-P

OPTIONS

BA11-YA
MAIN BOX

6
7

OPTIONS

M9404-00

M9405-00

BC020-03

(TYPICAL)
H9276

BA11-YC

EXPANDER | 14

OPTIONS

BOX

15
16

17
v

M9404-00

M9405-YA

OPTION

BCO2D-10

(TYPICAL)
H9276

21——ISV11-B (M8080)

22
BA11-YC
EXPANDER | 23
BOX
24

25
26
27

ISV11-B (M8084)
MR-6597

MA-0202-82

Figure

C-3

PDP-11/23B
Backplane

(H9276)

Three

Configurations

Backplane
configuration
figures
(Figures
C-1
through
C-3)
are
provided to help you follow these configuration rules. First, you
must
select which
backplane
configuration
is
best
suited
for
a

specific
determine

application.
Use
the
this configuration.

backplane

selector

figures

The

column layout of the
backplanes makes
it
easy to
establish
interrupt and DMA priorities of the modules; i.e., the closer to
the top of the column a module is placed, the higher the priority

the

correct

module.

configure
1.

Furthermore,

placement

cable

extended

LSI-11

system,

Select

the
for

the

specific

Select

the

CPU

and

type

Select

(the

added

column

layout

termination

needed

application
3.

the

and

easily

take

the

following

memory

(MOS,
PROM,
application.

memory

combination

PDP-11/23B

memory,

uses

depicts

interface,

most

Count

the

total

number

module

Count

the

total

number

bus

Select

backplane

position

suited

also

provides

the

sufficient

bus

for

the

KDF11-B).
and

peripheral

options

positions.

confiquration

requirement,

steps.

combination)

needed.

the

modules.

that

answers

position

expansion

the

module

requirement,

and

positions

the

space.

Enter the option names in
selected configuration.

Review the
initial
backplane
if changes must be made.

If
no
changes
are
necessary,
move
to
the
appropriate
backplane configuration table
(Figures A-1 through A-3).
Total

the

any
of
module

power

the

backplane

configuration

determine

consumption and the ac and dc loads.
If
exceed
the
1limits
specified,
modify
the
configuration
or
use
a
new
backplane

these

configuration.

Digital Equipment Corporation . ‘Maynard,
MA 01754 ‘