Digital PDFs
Documents
Guest
Register
Log In
XX-5A452-9E
May 2000
12 pages
Original
0.8MB
view
download
Document:
IM6103
Order Number:
XX-5A452-9E
Revision:
Pages:
12
Original Filename:
http://bitsavers.org/pdf/dec/pdp8/cmos8/_dataSheets/IM6103.pdf
OCR Text
IM6103 CMOS Parallel Input-Output Port (PIO) FEATURES • 20 Programmable I/O Pins • TTL Compatible Inputs and Outputs • Compatible with IM61 00 Microprocessor Family • Low Power Dissipation < 10 mW • Extended Temperatur~ Range, -40°C to +85°C • Single Power Supply GENERAL DESCRIPTION The IM6103 is a Parallel Input-Output Port (PIO) device designed for use in IM6100 microcomputer systems. Its function is to provide a general purpose parallel I/O component to interface ·peripheral equipment to the IM6100 system bus. The functional configuration of the IM6103 is pr'ogrammed by the user software so that normally no external logic is nel:essary to interface a wide variety of peripheral devices such as displ.ays, printers, keyboards, etc. to an IM61 00 micro· computer system. A general purpose all-CMOS microcomputer system with 64 x 12 RAM, 1 k x 12 ROM and 20 I/O 'lines can be built with just four CMOS LSI devices - IM6100 microprocessor, IM6512 (64 x 12) RAM, IM6312 (lkx 12) ROM and IM6103 PIO. PIN CONFIGURATION FUNCTIONAL BLOCK DIAGRAM Vcc PA7/PC'l PBl' PB,O P" PBB PB7 1O.r-......"PC8-11 PA4-1 DXO-l1 , ,PB6 PB, PBe PBJ SH6 SEl7 PB2 PB, PA8-11 ~·'---'-'IRS. IRE, OEVSEl lXMAR ORS,ORF c, SKP/INT 1',-'-_ _---jh/ PSO-11 DEVSEL PSO PAn/ORF OX,1 SELt; DX,0 SEL7 GNO ox. ox, ox. OX2 OX7 OXJ ox. ox, OXB PACKAGE DIMENSIONS ORDERING INFORMATION PART NO. IM6103AMOL TEMPERATURE RANGE _55°C to +125°C OPERATING VOLTAGE RANGE PACKAGE 4-11V 40 Pin Ceramic IM6103AIOL _40°C to +85°C 4-11V 40 Pin Ceramic IM6103 AIPL -40°C to +85°C 4-11V 40 Pin Plastic IM61031PL -40° C to +85° C 4-7V 40 Pin Plastic IM6103 CPL 4-7V 40 Pin Plastic IM6103 MOL O°C to +700 C _55°C to +125°C 4-7V 40 Pin Ceramic IM6103 IDL -40° C to +85° C 4-7V 40 Pin Ceramic - ~ .. u-==uI I 0.&00 - - REF--- 0.012 'D~DlL '·IM6103 ABSOLUTE MAXIMUM RATINGS Operating Temperature .• Industrial IM61031 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _40°C to +85°C Storage Temperature .................................. -65°C to +150°0 Supply Voltage ....... , : . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . : +1.2V Voltage on·Any Input or Output Pin With' Respect to GND ..... -0.3V to Vee Hl.3V NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent device failure. These are stress ratings only and functional operation of the' device at these or any other conditions above tho~e indicated in thii .operational'sectiqns of ,this specification is not implied. Exposure to absolute maximum rating conditions for extended periOds may cause device failures. . DC CHARACTERISTICS VCC = 5V ± 10%, TA = Industrial TEST CONDITIONS: SYMBOL ' PARAMETE.R. 1 VIH Logical "1',; Input \loltage 2 VIL Logical "O"lnput Volta!le.· 3. 4 IlL VOH Input Leakage .Logical "1"Output Voltage OV ";;;V.IN ';;;VCC lOUT =; 0 exceptpins 6,,9 .5 6 VOL .Logical "0" Output. Voltage . lOUT'" 0 10 Output Leakage 7 ICC Supply Current, : CONDITIONS MAX " UNITS ·. VC~1.7 OV';;;VO';;;VCC " TYP· MIN V .0.8 1.0 -1.0 IJA. .. . VCC':'·1~0 V · :0:45 1.0 iJA '. 2.5 mA 7.0 · ·8.0 .8.0 10.0 -1.0 VCC=5V CL = 50pF;TA = 25°C , FCLOCK =. Operating Frequency 8 CIN Input Capacitance 9' Co Output Capacitance . '" pF 'AC CHARACTERISTICS VCC = 5V ±10%;TA =-40u C to +85u C, CL = 50pF, All times in ns, TEST CONDITIONS: , 'SYMBOL. PARAMETER MIN MAX .. 1 tADOS Address Set-Up Time DX-LXMARi- 110 2 tAOoH Address Hold Time LXMARi--oX' 150 3 toEN Output Enable Time. oEVSELi--oX 550 4 toc Output Enable Time tol ;tos Output Enable Time DEVSEL+-':"C1 . OEVSELi--SKP' 550 '400 Data Set-Up'Tim.e oX-oEVSELt ~." Data Hold Time oEVSELt-oX 1!iO 8 toH. tps Data 'In Set-Up Tir:ne Port Data In...,LXMARi- 200 9 tpH Data In Hold Time ' LXMARi--Port Data In 225 10 t01 , tBS Delay Time oEVSEL t ...,Port Data Out Data In Set-Up Time Port Bln"":IRSi- 200 150 5 6 7 11 • 12 200 ,~ 550 .'. tBH Data In Hold Time. I RSi--Por't Bin 13 t02 Output Enable Time ORSt':"Port BOut 14 t02 Output Disable Time ORSi--Port BOut 200 15 t03 . Delay Time IRSi-~IREi- 550 ORSi-:....oRF+ oEVSELt,,:-IREt oEVSELt-ORFt UNITS , 556 ns IM6103-1 ABSOLUTE MAXIMUM RATINGS Operating Temperature Industrial IMM61031. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , .. , -65°C to +150°C Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ". . . . . . . . . . ~ . ; .... , +8V Voltage onAny Input o'r OutP~t Pin With Respect'toGND ;.'.. '. , -0.3V toVCC +0.3V NOTE: Stresses abov9" those listed .under "Absolute Maximum R<!tings" may cause permanent device (ailure. These. are stress ratings only and furwtionaloperation of thedev.ice at these or 'any other co~ditions. above those indicated in'the operational sections of this specification is .not implied. Exposure to 'abs"lute maximum rating'conditions for extended periods may cause device failures. ' DC CHARACTERISTICS VCC = 5V ± 10%, T A = Industrial TEST CONDITIONS: SYMBOL 1 ·TYP Logical "1" I nput Voltage V,L Logical "0" I nput Voltage 3 '" L VOH -_. OV <V,N <VCC -1.0 Logical "1" Output Voltage: 10H ='-0.2 mA except pins 6,9 'vcc-f.o ,VOL Logical "0" Output Voltage, 10L =2.0 mA 5 .. I nput Leakage ' MAX UNITS . V,H _. 4 I MIN CONDITIONS 2 -------- i PARAMETER VCC-1.7 V 0.8 to , jJ.A , V 0.45 -.~-- 6 10 Output Leakage OV<VO<VCC 7 ,ICC Supply Current VCC=5.0V 8 .. 1.0 pA , 2.5 mA pF CL = 50 pF;TA = 25°C FCLOCK= Operating Frequency ----- , ~.1.0 C,N . Input Capacitance 7:0 8.0 Co Output Capacitance 8.0 10.0 9 AC CHARACTERISTICS VCC = 5V ± 10%, TA = _40 c C to +85~C, CL = 50pF,AII times in ns. TEST CONDITIONS: SYMBOL ,. ". 1 tADDS 2 PARAMETER Address Set-Up Time ..... MIN " DX~LXMAR·.J. 80 100 MAX , tADDH Address HoldTime LXMAR.J.-DX 3 tDEN Output Enable Time DEVSEU-DX. 450 4 tDC Output Enable Time DEVSEU-Cj 450 5 tDI Output Enable Time DEVSEL.j..,.·SKP 6 tDS Data Set~Up Time DX-DEVSELt 150 7 330 tDH Data Hold Time DEVSELt-DX 100 8 tps Data InSet-Up Time Port Data .In-LXMAR.J. 150 9 tPH Data I n Hold Time LXMAR.J.-PortDatalri 175 10 tDl Delay Time DEVSE Lt -PortjDataOut 11 tBS Data In Set-UpTime Port Bin-I RS.J. 150 12 tBH Data In Hold Time IRS.J.-,PortB In 100 13 tD2 Output Enable Tirne ORSt-Port BOut, 14 tD2 OutpUt Disable Time ORS.J.-Port BOut 15 tD3 Delay Time I RS.J.-IRE.J. ORS.J.-ORF.J. DEVSEL t-IREt· D,EVSEL t ":"ORFt . UNITS ns I 450 ." 450 200 ,. 450 ... --,-, IM61 03 DXO_ll (4, PCS-l1 PA4-7 SEL6 SEL7 PAS-l1 IRS, IRE •. DEVSEL (4' QRS, ORF· lXMAR , C, SKP/INT PBo-l1 FIGURE 1: Functional Block Diagram. IM6103 FUNCTIONAL PIN DEFINITION PIN NUMBER SYMBOL 1 Vcc 2 PA7 iNPUT!. OUTPUT DESCRIPTION Positive Power Supply I/O Port A'I/O Line (4). Most Significant Bit of Port A in Mode 10. I/O Port' C I/O Line (S) in Modell/OX-Most Significant Bit. I/O PortA5'-A7 (Mode 10). I/O Port Cg -C11 (Mode 11/0X). 6 SKP/INT o lime M~ltiplexed SKP andlNTREO lines to the I M61 00 Microprocessor: - Active Low~ 7 PAS I/O Port A' I/O Line in Mod~ 1 i/l0 Significant Bit of Port A in ModeJ 1. IRS o Input Register' Strobe to .clock data into, Port B in Handshake Mode (Mode OX). Port B Latches.in the data on' the falling edge of I RS (I RS.J,.). ' PAg I/O Port Ag (Mode 11/10). IRE o Input Register Empty output goes high wheri Port B input buffer has been read by the IM6100 microprocessor. It goes low whfiln Port B input buffers are strobed in by I RS.J,.. (Mode OX)." PIO may be programmed to generate an I NTREO on I RE.J,.. Most IM61 03 IM6103 FUNCTIONAL PIN DEFINITION (Continued) PIN I NUMBER SYMBOL a 9 10 LXMAR 11 I DEVSEL 13 ORF DESCR.IPTION C1 output goes low upon completion of Pia Port data transfer· to the IM6100 Accumula· or (AC). This output is an open·drain output to be wire-OR'D with C1 Lines from other IM61 00 peripheral controllers. Address Latch enable signalfrom the IM61 00. Pia clocks in address and control informa. tion from the IM6100 on the falling edge of LXMAR(LXMARt). All Port inputs are Sjlmpled at LXMARt. I/O ORS 12 INPUT! OUTPUT Port A10 (Mode 11/10). Output Register Strobe input to enable Port B 'output· buffers in Mode OX. Port B is tristated when ORS is low. Input·Output Device Select control line from tl:1e IM6100. It performs both the read and write function. The first negative transition after LXMARt,enables the DX output buffers of the selected Pia for a 'read' operation. When DEVSEL returns high, the 'read' operation is terminated. The second negativegoing pulse on DEVSEL serves as a write' pulse to the selected Pia and the IM6100 AC data is written into the selected -PIa register or port on the rising edge. I/O Port A11 (Mode 11/10)-Least Significant bit of Port A. a Output .Register Full output goes high when the IM61 00 writes into Port B in a handshake mode. It goes low. when the peri· pheral device reads Port B by enabling ORS high. The Pia may be programmed to generate an INTREQ onORFt·(Mode OX). I 14 SEL6 A Chip Select Input. Pia has two chip selects, SEL6 and SEL7, thereby enabling up to four Pia chips in a system. 15 SEL7 A Chip Select Input. 16 ~25 DXO~DX9 26 GND I/O The IM6100 System bus (Data and Address). Ground I/O IM61 00 System bus (Data and Address). I/O I/O Port Pin. PBO is the most significant bit, and PB 11 is the least significant bit. IM6103 D~DIL onthe OX bus andCl output (of IM6l03) low when DEVSEL (from IM6l00) inpLit is low. Cl line goes low to indicate an in· put transfer cycle to the IM6l 00. All PIO data transfers to the IM6l00 Accumulator (AC) is an 'OR' transfer, '(i.e., PIO data is OR'ed into the contents of the AC). IM6100 SYSTEM TIMING The tristate bidirectional 12.-bit OX bus is used to transfer data and control information (Figure 3) between the IM6l03 and the IM6l00 fl1icroprQcessor., The IM6l00trilnsmits the device address and control inforr~ation on the OX bus, during the 'execute' phase of an Input~Output Transfer (lOT) instruction. The IM6l03 accepts this information on, the falling edge of the LX MAR (Address, Latch Enable) Signal. During the write operation into, PI'O, the PIO accepis diltil from the IM6l00 Accumulator on the' rising edge of the DEVSEL. During and after the PIO write, the contents of,~he accu mu lator are. not cleared. The address bits (6-7) are compared with the chip select in· puts (SEL6 and SEL7) to address 1 of 4.1'10'5. The lOT ad· dress bits (3-5) are programmed intermilly to respond to the, bit pattern 011. The SEL6 and SEL7 inputs should be~ ternally hard-wired to match the DX6 and DX7 chip seleCt bits. As shown in Fig; 3, DEVSEL goes low, during the first half of an lOT execute machine cycle for a read operation and it goes low again in the second half for a write operation. The IM6l03 responds ,to a 'read" instruction by putting data SKP/INT line goes low during the 'read' DEVSEL' if the IM6l03' is responding to a'skip' iristrudtion, and the 'skip' 'conditio~ is met, therefore causing the IM61DO to skip the next sequential instruction. SKP/INT line reflects the inter· rupt request status of the IM6l00 at all times except during the 'read' DEVSEL. The SKP/INT line goes low if an active interrupt request is pending. During read DEVSE L mode" the SKP/INT indicates the current skip condition. The. bits are interpreted as shown below: DXo BIT • 0 • • • • .', • • • • 'OX" 2 3 4 5 6 7 8 9 10 11 19 110 0 II I 0 SELS I SEL7 I 18 I~' lOT ~I I~, P I O _ I 1-- s~~~6T--I" ,CODE CODE II PIO CONTROL I I" I "I IM6100 OSC OUT' IM6100 T.STATE~ IM6100 IFETCH I , ~~~~: ~L________________~____~r-l~: ______ ,,, +-________________+-________+-___________________________ IM6100 - - - , MEMSEL .L _ _ _..J I DXIO-l1} =="""---- IM6100 OEVSEL' IM610l CI SKPIINT _.;.. ___ -'- ___ LOW FOR REAO ~~~~U~T _________ li,e., All input data lines 1 L'(-~;,;i--X lOT INSTRSAMPLEO BY PIO-.JPIO,OATA, cLKP i s~~:~ ----:~,~J~t~~O- BY IM6100 FOR REAO a,re sampled,} FOR WRITE 'lOT EXECUTE MACHINE CYCLE FIGURE,3: ,, , ,, , 1 ' INT~RRUPT ---1---------------------'-. , ' ' , " INTREQ SAMPLED BY IM6100 IM6103 system timing diagram. OPERATION OF' PORT. BUFFERS -Port B with 12 bits (PBO-PB 11) -Port C with 4 bits (PCa-PC11 ) The IM6103 has 20 I/O pins which can be individuallY pro· grammed in groups of 4, a or12 bits in three different mode$ of operation. In Mode 10,the 20 I/O lines are grouped into 2 ports- ' -Port A with a bits (PA4-PAll) . -Port B with 12 bits (PBO-PB 11) -The four I/O lines associated with PortC in Mode 11 (PCa-PC11) are allocilted to Port A as PA4-PAt. In Mode 11, the 20 I/O lines are divided into three ports: -Port A with 4 bits (pAa-PA11) IM61 03 In Mode OX, therearetwo ports-Port B with 12 bits and, Port C with 4 bits and four lines, for handshake control logic. Four I,in~s of Port A in Mode .11 (PAs-PAn) are reassigned as handshake control lines, They are: -I nput Register Strobe (I RS) -Input Register Empty (IRE) -Output Register Strobe (ORS) -Output Register Empty (ORE) The handshake logic controls the data transfer for the Port B. ' Port C operation remains the same as in Mode 11. For an 'input' transfer in OX Mode, the input register empty (I R E) output goes high to indicate to the peripheral device that the input register is empty (as shown in Fig. 4). The peripheral device 'may then strobe in the new data into Port B with Input Register Strobe (IRS). At this time,IRE goes low to indicate. to the peripheral device that the input buffer is full, and remains low until Port B has been read by the IM6100 microprocessor. IRE then goes high after the IM6100 executes a Read Port B (RPB) instruction to. initiate another input sequen·ce. The data into Port B should be valid only for a short duration before and after I RS makes the 1 to o transition. IRS (PERIPHERAL ~PIO) : . ~tB~H~~~~~~~~~~~~~ (PERIPHERA·L~PIO)~ PORTBOATA FIGURE 4: I 1... Input data transfer (peripheral device to PIO)' For an ~output' transfer in OX mode, the IM6100 micropro' cessorwrites, the data i,nto Port Band its timing is shown in Figure 5. ORF line from the PIO goes high, signaling the peripheral device that the output register is full. The peripheral device may then strobe in the new data from Port B with ORS. Port B stays in the high impedance mode until ORS is activated by the peripheral device. ORF line goes low and remains low until Port B has been written into by the IM6100 microptocessor. ORFthen goes high, initiating an· other output sequence. IM61 00 OEVSEL (SPB/CPB/WPB) J-- 803 -}. . IPIP_PERIPHERDAR~ DRS (PERIPHERAL -PIP) (PIP ~~~~~~~R~L~-- ~ - FIGURE 5: ORF should be set to 0 and IRE to 1 with a :write' command in Mode OX, to initiate the handshaking sequen~e. The IM6100 microprocessor should not write into Port B unti.1 ORF is low for an 'output' transfer and should not read Port B until IRE is low for an 'input'transfer. The peripheral device reads Port B if ORF is high and writes into Port B if I RE is high. The PIO may be programmed to generate an INTREQ (Interrupt Request) to the microprocessor when 0 R F or IRE goes . low by setting the respective Interrupt enable bits, OREN and IREN. IM6100 D E V S E l - - - - - - - - - - - - . IRPB INSTRUCTION) IRE '(PIO ~PERIPHERAL) • tBS. ~... tD3 The IM61 00 monitors the status of OR F (Output Register Full). If it is low (i.e., output register i~ empty), 111.116100 may load data into Port B output buffer with SPB/CPBIWPB instrlJction. ORF goes high adelay timeafterthe rising edge of the 'write' DEVSE L, signaiing the peripheral device that output buffer has new data. During this time, Port B output buffers remain tristateid~ The peripheral device may then enable and read ou't Port B output latches by activating 0 RS (Output RegisterStrobe) high. The falling edge of ORS (from high to low) signals the PIO that the peripheral device no longer needs the valid current information. Port B is tristated and ORF then goes low, thereafter, to indicate another output sequence; The IM6100 may poll the status of ORF or IRE by executing the respective skip instructions SKPOR and SKPI R, by reading the statusregister or by reading "Port AU. In Mode 11 and 10, when handshaking control is not in effect, the execution ofSKPOR and SKPIR Instructions depend on the state of the Port A lines PAll and PAg, respectively. The Interrupt feature is available only in Mode OX. The mode of operation - 11, 10 or OX, is selected by pro, gramming the Status Register (SR). All ports are bidirectional. The execution of a 'write' in· structio~ caused a port to be automatically programmed' to be·an 'output'. The output data may be changed by using the 'set', 'clear' 'or 'write' instructions. The output remains valid until the port bit lines are reset to be inputs. Execution of a 'read' instruction causes a port to be automati· cally set as an 'input' port- i.e., it presents a very high impedance to the I/O lines. Data appearing on the I/O lines will be sampled into the port input latch at every LXMAR pulse and may be read by the IM6100 microprocessor by the 'read' . instruction. In Mode OX, Port B acts as a .tristate bidirectional buffer which is controlled by an external peripheral device. OR F and IRE lines are outputs and ORS and I RS lines are inputs. c..,...---,-- ----- --~~:--~~~---- Output data transfer WIO to peripheral devioe). At power-on, all ports are defined to be input ports and ·the PIO is initialized· to be in Mode 10. With 20 I/O lines partitione(linto the S/12 (i.e., Port A = S .bits, Port B =. 12 bits) format.' IM61 03 STATUS REGISTER INTERRUPT OPERATION The Status Register (SR) has 2 mode bits, MS and Mg which can be modified by the WSR (Write Status Register) instruc· tion. These two bits define the mode of operation for the IM6103 as shown in Figure S. ' The IM6l 03 may be programmed to generate an interrupt reo quest input (lNTREO) when ORF or IRE goes low, by setting the corresponding interrupt enable 'bits, OREN or IREN, to 1. If the IM6l00 interrupt system has been previously enabled, the microprocessor will acknowledge the INTREO input. If the IM6100 J.l.P does not see the higher priority INTREO's, inputs from other peripheral controllers such as IM6102 'Memory Extender/Direct Memory Access/Internal Timer Con· troller (MEDIC) or IM6101 Parallel Interface Elements (PIE) ,in the system" the interrupt service routine should initiate a software poll of the PIO's in the system to identify the parti· cular PIO that generated the INTREO. In Mode OX, the inter· rupt request' status of ORF and IRE may be identified by reading the Status Register. ORINT or IRINT will be set to 0 . if ORF (being low) or I RE (being low) is generating an INTREO. Note that IM6l02 MEDIC and IM6l0l PIE pro· vide an automatic priority vectoring. Ma Mg MODE PORT OPERATION 0 * Mode OX PBO·11, PCS.11, IRS,I RE, ORS; ORF 1 0 Mode 10 PBO·ll, PA4·11 1 1 Mode 11 PBO·11 , PCS·11 , PAS·l1 FIGURE 8: Mode bit assignments. The Mode and Interrupt status bits, ORINT (Output Register empty Interrupt) and IRINT (Input Register empty Interrupt), may be read with the RSR (Read Status Register) instruction. The interrupt status bits are set to 0 if the corresponding flag is requesting an interrupt. In Mode 11/10 the current value of PAll and PAg can be in· terrogated. ,In this mode, Port A tan be either an input or an output. MS andMg are initialized to "11" at power-on. ~ DXg I DXlO I DX11 I ~ Mg IDRINTIIRINT I ~ I Mg I PAll I PAg I ~ ~ FIGURE 9: DX The interrupt feature of IM6l03 is available only in Mode OX. An ORFINTREO may be removed by one of the following methods: • executing a SPB/CPB/WPB Instruction (ORF goes high if Port B is written into), or • setting ORF to 1 with SPA/WPA Instruction, or • by resetting OREN to 0 with a CPA/WPA Instruction, or • by changing to Mode 11/10. BUS SR MODE OX SR MOOEll/1O SR MODE 1111O/OX An IRE INTREO may be removed by: REAO READ WRITE Status register bit assignments. SKIP OPERATiON The IM6l00 may poll the status, of ORF or IRE in Mode OX, by executing a skip instruction,SKPOR or SKPIR. The .lM6l 03 will assert the SKP/INT line low if the corresponding status line (ORF or IRE) is low, causing the next sequential ,instruction to be skipped. During this cycle, ORF and IRE reo main unchanged. In Mode 11/10, SKPOR and SKPI R instruction executions de· pend on the state of PAll and PAg, respectively, Port A may be an input or output port. If ORF is reset to 0 by executing a CLRPA or WPAinstruction to initiate the handshaking sequence, the next SKPOR instruc' tion will cause the next sequential instruction to be skipped. • executing a RPB Instruction (IRE goes high after Port B is read), or • setting I RE to 1 with SPA/WPA Instructions, or • resetting IREN to 0 with a CPA/WPA Instruction, or • changing to Mode 11/10. PIO may be software programmed to generate anlNTREO to the IM6100 by resetting ORF or IRE to 0 with a CPA/WPA Instruction and by setting the corresponding enable bit, OREN or I REN, with a SPA!WPA Instruction in Mode OX. D~UIL IM61 03 PIO INSTRUCTION NOTE: Symbol Definition - "." - AND ",+" - OR Is Replaced By ':,=" - PIO MNEMONICS CONTROL a a a a SETPA (Set Port A) PIO MNEMONICS CONTROL DESCRIPTION' Set PAi to lit' ACi is 1. AC is not cleared. a 1 1 1 RPB DESCRIPTION Read Port B. '0 R' transfer PB to AC. ACi=ACi+PBi; a";;i<) 1 Modell: PAi=PAi+ACj. 8";; i";; 11 Mode 10.: PAi~PAi+ACi.4";;, i";; 11 1 a a a SETPC Mode OX: IREN = IREN + AC8 IRE=IRE+ACg OREN = OREN +AClO ORF ~ORFTACll a a a 1 CLRPA , Mode 11 and OX: PCi=PCi+ACi a";;i";;ll Mode 10.: No operation 1 a a 1 Clear Port A. Clear PAi to a if ACi is 1. AC is not cleared. CLRPC a~i";;ll Mode 1a: .No operation Mode 10.: PAi=PAi'ACi, 4";;i";; 11 a a 1 a WPA . Write Port A. Set PAi equal ,to ACi. ACis not cleared. 1 a 1 a WPC 1 a 1 1 RPC RPA Read Port A, 'OR' transfer PAto AC. \ Mode 11; ACi=ACi+PAi, a";;i";; 11 ACi=ACi,a";;i";;7 1 1 a a SKPOR a 1 a a SETPB Se't Port B. Set PBi to 1 if ACi is 1. AC is not cleared. PBi=PBi+ACi, a,,;; i";; 11 a 1 a 1 CLRPB Clear Parr B. Clear' PBi to a if ACi is 1. AC is not cleared. PBi=PBi 'ACi, a,,;; i";; 11 a 1 1 a WPB Write Port B. Set PBi equal to ACi. AC is not cleared. PBi=ACi, a,,;; i";; 11 Skip the next sequential instruction if PA11/0RF is low. Mode 11 and 10.: Skip if PAll is low. Mode OX; Skip if ORF is low. 1 1 a 1 SKPIR Mode 10.: ACi=ACi+PAi, 4";; i";; 11 ACi=ACi,a";;i";;3 Mode OX: ACa='ACa+IRS ACg=ACg+IRE AClO=AClO+0RS ACn=ACll+0RF ACi=ACi, a,,;; i";; 7 Read Port C. 'OR' transfer PC to AC. Mode 1 T and OX: ACi=ACi+PCi a";;i";;ll Mode 10.: No operation Mode 10.: PAi=ACi. 4";; i";; 11 a a 1 1 Wr,;te Port C. Set PCi equal to ACio. AC is not cleared. Mode 11 and OX: PCi=ACi 8";;i";;11 Mode 1a: No oper~tion Mode 11 :PAi=ACi. a,,;; i";; 11 Mode OX; IREN = ACa IRE = ACg OREN = AClO OR$.= ACll Clear Port C. . Clear PCi to a if ACi is 1. AC is no! cleared. Mode 11,and OX:.pCi~PCi,·ACi . Mode 11: PAi=PAi • ACi, 8";; i";; 11 Mode OX; IREN = IREN'ACa IRE=IRE ;ACg OREN = OR EN 'AClO ORF= ORr; 'ACll Set Port C. Set PCi to 1 if ACi is 1. AC is nO,t clear~d. Skip the next sequential instruction if PAg/IRE is low. Mode 11 and 10.:, SkipifPAg is low. Mode OX: Skip if IRE is low. '1 1 1 a WSR Write Status Register. AC is no't cleared. Ma = ACa Mg = ACg 1 1 1 1 RSR Read Status Register. '0 R; transfer Status register to AC .. ACa = ACa + Ma ACg = ACg + Mg ',ACi = ACi; a";;i<7 Mode 11 and 10.: AClO~ACia+PAll AC1'1= AC 11+PA9 Mode OX; AClO=AClO+0 R I NT , ACll=ACll+IRINT 'D~OIl. IM61 03 ,-I DXo I DXl I DX2 I I DXJ I DX4 I DX5 II DX& I DX7,I.oxallDxg 'I I 1 0 1 II I 1 0 I I 0 I I 0 0 II o 1 0 1 0 O· 1 0 1 1 0 1 ox BUS Ig 110 I 111 I PIOINSTRUCTlON,. 1 PAa 1 PAg PAlO I' PA11 "PORTA 'MODE 11 READ" ~ PAg PAlO 1 PA11 PORT A MODE 11 WRITE PAg PAlo'1 PA11 PORT A' MODE 10 READ PAlO I PA11 PORTA MODE 10 WRITE.. 1 0 1 iRS II IRE laRS I ORF PORT A MODEOX READ' ~I IRE lOREN I ORF PORT A MODE OX WRITE 1 II SEL& I SEL7 I 18 0 11 0 1 0 U 'I PA5 1 I PAS 1 PA7 1 PAa'1 I PA4 I PA5 I I PAS I PA7 1 PAa I 1 PA4 ,II . 0 ' I' 0 0 I DXlo.1 PX11 I I 0 I I' o PAg I PBO I PBl I PB2 II PBJ I PB4 I PB5 I I PBS I PB7 I PBa II PBg I PB10 I PB11 I 0 0 0 I I I 0 0 0 I I I 0 ' -, " .... PORT B MODE 11/10/0X READIWRITE II 0 I .0 I ' 0 II 0 I 0 I PCa II PCg 1 PC10 1 PC11 1 PORT C MODE 11/0X READ 0 II I 0 0 H·o ·1 0 0 1 I 0 II 0 0 II 0 1 I [ § J I PCg I pC l0 1 PC11 I PORT C, MODE 11/0X WRITE 0 I Ma II Mg I PAll I PAg.1 STATUS REG, MODE 11/10 READ 0 I Ma II STATUS REG MODE OX READ Mg I ORINTIIRINTI ~I~l FIGURE 6: I 3 14 STATUS REG MODE 11/10/0X WRITE IM6l03 PIO register bitassignments,' I 5 I I 1 I Bill I 13 II 29 I 30 I 31 I 32 I 33 I 341 3513& I ~7 I 3S I 39 I 40 I PINS I ,2 MODE 1,1 IPC11 IpC101 PCgl PCsl I PAS I PAgl PA101 PAll II PBO I PBl I PB21 PB31PB4 I PB5 I PBS I PB71 PBS I PBgl PS10 I PBlll MODE OX I PC11lpC101 PCg I PCsl I IRS liRE laRS I ORF II PBO I PSI I PB2 I PB31 PB4 I PB5 I PBS I PB71 PBal PBgl PB10 I pB lll FIGURE 7: IM6103 PIO port pin assignments. IM61 03 LXMAR OEVSEL ox CI SKP/INT _ _ _ _ _ j--..J ~~~~~E==S~~ PORT DATA IN ~ PORTOATA------------------------------~----------------~----------------------------~--~r--- OUT __________________~________________________~--------~-------------------JL--- FIGURE 10: IM6103 PIO timing diagram. IM6100 OeVSEL -'-~--...,-----------'----------------. (RPB INSTRUCTION) IRS (PERIPHERAL .... PIO) IRE (PIO -'-PERIPHERAL) . t03 ~ . I ~tBH PORT B DATA ~==""'==""'='"'""''777""'''''''''"''''"'>777''"''''''''"",.,.,., tBS (PERIPHERAL->PIO)~ FIGURE 11:' Input data transfer (peripheral device to PIO). r-\ i IM6100 OEVSEL ~ ~,~:~:;, ~,:;I 11.....-,------------......,1'-,..-_____ \. . -_...... t+ !r------,F ,------- l t 03 -.. ORS (PERIPHERAL->PIP). PORTBOATA (PIP ->PERIPHERAL) - t02 .... - - - - FIGURE 12: - - - - - - - - - - J 1-4- .-. t+_tO_2 ___' _ \~ ______..1 Output data transfer (PIO to peripheral device!,. IM6103 APPLICATION. OF IM6103 Figure 13 illustrates a microcomputer system block diagram using IM6103 in a dual processor system. MASTER CPU IM6103 PIO IM61DO OMAEN ;.... IM6101 PIE UP -- : : --,,••:_--:I:,:R=-E"'----I , ': i .~. '"--OM-A---..I IRS ORF __~O~R~S~~I IM6103 PIO L..,-,r--:~",",,".J CONTROL DMAREUUEST IM6100 SLAVE CPU FIGURE 13: IM6103 PIO t Dual processor system with shared memory. IM6101 PIE PERIPHERAL DEVICES
Home
Privacy and Data
Site structure and layout ©2025 Majenko Technologies
