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XX-5FD1C-C7
May 2000
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IM6102
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XX-5FD1C-C7
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23
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http://bitsavers.org/pdf/dec/pdp8/cmos8/_dataSheets/IM6102.pdf
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IM6102 Memory Extension/ DMA Controller/ Interval'Timer (MEDIC) FEATURES GENERAL DESCRIPTION • Provides Extended Memory Address to 32K Words The IM6102 is a multi-function peripheral controller chip incorporating functions such as memory extension, direct memory access control, and a programmable real time clock. The IM6102 provides necessary control to address up to 32K words of memory, and its DMA channel canbe used with Dynamic RAM Components for "transparent refresh". The programmable real ti me clock is 12-bit long, and its output frequency can be programmed for 5 decades. Itfeatures ahigh degree of system integration, putting into one chip all the functions which are normally available in three or more LSI circuits. As a result of this larg~ integration, the user can design and. produce a compact microcomputer with minicomputer performance. • Simultaneous DMA - Provides Simultaneous DMA Channel that Uses OX Bus During Second Half of a Cycle to Access Memory . • DMA Channel Can be Used for Dynamic RAM Refresh • 12-Bit Programmable Interval Timer • Direct Interface with IM6100 Microprocessor Via Bidirectional DX Bus and Handshake Lines • Hardware Reset • 28 Different I/O Instructions PIN CONFIGURATION PACKAGE DIMENSIONS Vee jiffc)i]T" ! DMAEN 'INTGNT OMAGNT EMA2 [:::: :::::::::::::: r~37161 EMAl EMAO I 2.040 (51.820) I SKP/INT RESET C; UP e;- XTA '0.0201.511 J Go LXMAR OSCOUT lXMAR* DEVSEL XTC· OSCIN XTC OX11 CLOCK OX10 SKP/lNTX GNO OXO OX9 OXl OXB OX2 OX7 OX3 OX6 ox- OX5 s-i ~x I ---I'. 0.070 (l.na) 0.01a 10.457) TYP. TYP. 0.020 (0.508) f+--, 1-0 '. (4.0641 I~·~~;l -U~--t-' ---I. I . 0.160 (4.0641 I-, 0.012 (0.305) TVP. TYP~01.(1°.0251 MIN '0.100' I 0.660--1 I-- (16.764) MAX. (2.540) 40 PIN PLASTIC DUAL-IN-LiNE PACKAGE (PL) ORDERING INFORMATION ORDER CODE IM6102-1 IM6102A IM6102 PLASTIC PKG. IM6102-11PL IM6102-AIPL IM6102-IPL CERAMIC PKG IM6102-110L IM6102-AIDL - MILITARY TEMP. IM6102-1MOL IM6102-AMOL - MILITARY TEMP. IM6102-1 WITH 883B MOLl883B IM6102-AMOLI 883B - 0.050 0.165 (1.270) 14.191) 0.020 (5.0BO) T~~~OO~ J I f---, 0.050 (1.270) ·0.010 (0.254) ---I'I I ~, 0.600 I 0.008(0.203) f--, ~ 1---1 _ 0.125 1--(15.240)-10.012 (0.305) REF. 0.018 (0.457) 0.100 (2.540) (3.175) '0.002 (0.051) ·0.010 (0.254) M1N. 40 P1N CERAMIC DUAL·1N-UNE PACKAGE (DLI NOTE: DIMENSIONS 1N PARENTHESIS ARE METRIC IM6102 Vee PROUT DMAEN INTGNT OMAGNT EMA2 MEMSEL EMAl Symbol Input/ Output 11 LXMAR' o Description LXMAR IM6102 generated by the IFETCH EMAO 12 XTC' o XTC generated by the IM6102 MEMSEL" SKPJINT 13 XTC I CPU external minor cycle timing signal 14 CLOCK I Oscillator OUT pulses from CPU for timing the IM61(i2 DMA transfers. I Multiplexed SKP/INT line from lower priority devices RESET C; UP C; XTA ~ LXMAR osc OUT lXMAR* 5EVill XTC~ OSCIN XTC OX11 CLOCK DX10 SKP/IN"TX GNO OXO OX, OXO I/O Most significant bit of the 12-bit multiplexed address and data I/O bus OX9 17 OX1 I/O See pin 16-DXO OXB 18 OX2 I/O See pin 16-DXO 19 OX3 I/O See pin 16-DXO 20 OX4 I/O See pin 16-DXO OX2 OK;' OX3 OX6 OX. OX5 Pin Number Symbol Inpull Output Description 1 Vee Supply voltage 2 DMAEN Enable the IM6102 DMA channel to transfer data 3 DMAGNT Direct memory access grant from CPU 4 Memory select for read or write from CPU IFETCH CPU flag indicating instruction fetch cycle o 6 Memory select generated by the IM6102 Asynchronous reset will clear Instruction Field to Oa, disable all interrupts, initialize DMA port to READ/REFRESH, initialize timer to "stop", "divide by 2'2 mode" and "enable divide counters" 7 15 16 IM6102 FUNCTIONAL PIN DESCRIPTION 5 Pin Number 8 g UP o User pulse I read or write I XTA I CPU external minor cycle timing signal 10 LXMAR A falling edge of LXMAR pulse from CPU will load external memory address register 21 OX5 I/O See pin 16-DXO 22 OX6 I/O See pin 16-DXO 23 OX7 110 See pin 16~DXO 24 ~)X8 I/O See pin 16-DXO See pin 16-DXO 25 OX9 I/O 26 GNO I/O Power Supply 27 OX10 I/O See pin 16-0XO 28 OX11 I/O See pin 16-0XO 29 OSCIN I Crystal input for timer oscillator Device select for read or write from CPU 30 31 OSC OUT 32 Co o o See pin 29 See pin 32-Co Control lines to CPU determining type of peripheral data transfer 33 C1 34 C2 35 SKP/INT o o o 36 EMAO o Extended memory address field I most significant bitl 37 EMA1 o Extended field memory address 38 EMA2' o Extend'ed field memory address See pin 32-Co Multiplexed SKP/INT input to the CPU 39 INTGNT I CPU interrupt grant 40 PROUT o Priority out for vectored interrupt NOTE: All OX lines are bidirectional with three-state outputs: Pins 6, 8, 11,12,35,40 have active pullups; pins 32, 33, 34 have open drain outputs; pin 15 has a resistive input pullup; all inputs are protected with resistors and clamp diodes. IM6102 ARCHITECTURE The IM6102 is composed of three distinct functions: a) A OMA port that uses the bus during the second half of a cycle to read, write, or refresh memory. The OMA port logic includes a word count register WC, a current address register CA, an extended current address register ECA, and a OMA status register. b) An extended memory address controller that augments the 12·bit addresses generated by the IM6100 micro· processor by supplying a 3-bit address field that may be decoded to select one of eight 4096 word memory fields. The memory extension controller logic consists' of an instruction field register IF, a data field register DF, an instruction buffer register I B, and a save field register SF. c) A realtime clock whose mode and time base rate may be programmed by the user. The clock logic includes a clock enable register CE, a 'clock buffer register CB, a clock counter register CC, and a time base multiplexer. A block diagram of the IM6102 isshown in Figure 1. The IM6102 registers are summarized as follows: A. SimultaneousDMA Channel (Figure 3) CURRENT ADDRESS (CAl REGISTER This register is a 12·bit presettable binary counter. At the beginning of a SDMA transfer, the current address must be set to the first location to be accessed. The content of the CA register is incremented by 1 after a SDMA transfer, and the incremented value is used as the address of the memory location with which the next transfer will be performed. EXTENDED CURRENT ADDRESS (ECA) REGISTER This is a 3-bit presettable binary counter and if the carry enable bit of the DMA status register is set, the 12-bit CA register and the 3 ECA bits are treated as one 15·bit register with the ECA bits most significant. If memory field 7 (all 3.bits at logic one) is selected, the ECA cannot.' increment, but will wrap around in field 7 and an F7 error (F7E) will occur. The Interrupt Enable bit IE in SR11 must be set to enable F7E interrupts. If enabled the F7E will request an interrupt. If the carry enable bit CE in SR9 is not set, the ECA is not incremented when CA goes from 7777Sto DODOS. WORD COUNT (We) REGISTER A 12-bit presettable binary counter is used as a word counter. At the beginning ofa SOMA transfer, the two's complement of the number of 12-bit words to be transferred must be loaded into the WC. If enabled this will initiate the SOMA operation. The, WC register is incre· mented by 1 after a SOMA transfer. If this value becomes zero, word count overflow has occurred and if the I E bit in SR 11 is set, interrupts are enabled and an interrupt is requested. Unless instructed to be in the continuous run mode, a WC overflow inhibits further transf~rs. The WaF is set when the MSB of the WC register makes a "1" to "0" transition. OX 12 LXMAR* MSEL* XTC· IM6100 OMA UP DMAEN PROUT 0 EMA(O·2) ~ INT/SKPX ;: VECTOR INTERRUPT EMA ~ ~ 5i IN ose (4MHz) elK OUT vee GNO FIGURE 1: IM6102 MEMORY EXTENSION/DMA/INTERVAL TIMER CONTROLLER IMEDlC) IM6102 XTA ----'--'-----' XTe LXMAR EMA.w 2J _ _+-_---'''-_ _L-..c:.:c..:...~L---''--......JL---=.::'''-~f'_----....::.'------- XTC' MEMsEt- DMA READ UP MEMORY OMA PORT XTC' MEMSEl" DMA WRITE UP DMA PORT . MEMORY FIGURE 2: MEDIC TIMING FOR DCA I DMA Status Register This register consists of 5 control bits and 2 flag bits for the SOMA feature. For a description refer to the register bit assignments. INTERRUPT VECTOR REGISTER VRO· VR10 VAll COF , WORDCQUNT weo'· well CURRENT ADDRESS CAD· CAl' RFSR !LeAR .- __ R~~.t_ lFSR (7·11) __ ___ . , LEAR REAR IL_. ________________________ ACCUMULATOR ...JI FIGURE 3: SDMA REGISTERS OPERATION The IM6l02 SOMA channel augments the throughput ofthe IM6l00 during DMA operations by transferring data be·· tween memory and peripheral devices. simultaneously with normal processor bus usage. In other words, no memory cycles are. "stolen" from the processor; but the DMA address and data are transferred on the bus during periods that the OX bus is inactive. IM6'102 TABLE 3 SDMA INSTRUCTIONS MNEMONIC OCTAL CODE LCAR 6205 8 LOAD CUR RENT ADDRESS REGISTER (CA) The contents of the AC replace the contents of the CA and the AC is cleared. DMA sequencing is stopped. RCAR 6215 8 LWCR 6225 8 LEAR 62N68 READ CURRENT ADDRESS REGISTER Description: Contents of CA transferred to AC. LOAD WORD COUNT REGISTER (Wei Description: Contents of AC are transferred to the WORD COUNT REGISTER. the AC is cleared WORD COUNT OVERFLOW (WOFI is cleared and DMA operation started. LOAD IMMEDIATE TOEXTENDED CURRENT ADDRESS REGISTER (ECAI Description: Fi,eld N of the lOT instruction is transferred to the Extended current address r~gister. REAR 6235 8 LFSR 6245 8 RFSR 6255 8 SKOF 6265 8 WRVR 6275 8 CAF 6007 8 OPERATION READ EXTENDED CA Description: Extended current addres~ register contents OR'd into ,bits 6. 7. 8. of AC, LOAD DMA FLAGS and STATUS REGISTER Description: AC bits 7-11 are transferred to the DMA STATUS REGISTER and the AC is cleared. ,READDMA FLAGS and STATUS REGISTER Description: DMA Flags and Status Register bits are OR transferred into AC bits 5-11 and Field 7 wraparound error IF7EI is cleared. SKIP ON OVERFLOW INTERRUPT Description: The PC is incremented by 1 if a word count register overflow interrupt condition is present causing next instruction to be skipp'ed. WR ITE VECTOR REGISTER Description: AC bits 0-10 are transferred to the Vector Register and the AC is cleared, CLEAR ALL FLAGS-clears F7E and WOF (and also COF), Clock enable and clock buffer. The DMA process is initiated if the status register is not set to the "stop" mode. TABLE 4 DMA FLAGS AND STATUS REGISTER BIT ASSIGNMENTS '0 2 1 3 4 5 6 7 a 9 10 11 F7E WOF SR7 SRa CE RIW IE where' - dOl;'t care for write and zero for read. F7E Fiel? 7 wrap, around carry error; cleared by CAF, RFSR and RESET WOF Logic one indicates word counter overflow; clear by CAF, L,WCR and RESET CE Carry enable from CAIO-ll) to ECA; cleared !:Iy ~ESET R(W Logic one indicates DMA write (Port to Memory transfer). Cleared (DMA Read) by RESET Enable interrupt when WC overflows or Field 7 error occurs; cleared by RESET IE , SR7,8 00 01 10 11 " Refresh mode; WC is frozen, no UP, DMAEN is don't care Normal mode; DMAEN(H) freezes WC CA and no UP if we has not overflowed; stop if WC overflows Burst mode; DMAEN(H) freezes WC, CA and no UP if WC has not overflowed; refresh condition if WC overflows Stops DMA DMA MODES SR7 = SR8 = 0 REFRESH MODE This is the mode to which the 6102 reverts on RESET. The word count register clock input is disabled, the User pulse (DMA data strobe) is suppressed and the DMAEN input is ignored. However, provided valid DMA transfer conditions are met in a particular memory cycle, the DMA sequencer will be' staded, appropriate timing signals will be generated and the current address register will be clocked. Thus DMA read accesses will be performed continually,with an essentially free-running current address register. ·Read accesses will refresh dynamic memory. No WOF is possible but an F7 Eis possible if bit SR9 is set, enabling a carry from the current address register to the extended current address register. SR7 =0; SR8 = 1 NORMAL MODE This mode is used for normal SDMA operations with static memory. The following instruction sequence can be used: CLA TAD CA LCAR (Clear AC (Get starting address (Load into current address register and clear AC IM6102 TAD SR LFSR IGet DMA status Register Constant IChange status (from refresh to normal TAOWC LWCR for example) IGet two's complement of. block length ILoad word count register and start DMA TRANSFERS Note that LWCR will start the sequencer so it should be the last instruction in the initialization sequence. The ECA register and vector register could also have been initialized in this sequence. The SOMA sequencer samples DMAEN on the rising edge of every XTA and latches the condition of the enable line. If DMAEN is low, the sequencer is enabled, external timing signals XTC', MSEL', UP, LXMAR' are generated, the WC and cA registers are clocked. If DMAEN is high, at XTA (t) time, the signal is sampled and latched and if the WC has not overflowed, the WC and CA registers are frozen, UP is suppressed. If the WOF condition comes up, the SOMA operation stops, regardless of DMAEN level. addressing space of the system from 4K to 32K words. To perform thi~ function, the EXTENDED MEMORY CON· TROLLER maintains a 3·bit extended address which is de· coded by the memory modu les to select 1 of S mernory fields each containing 4096 words of storage. These 4K fields start with FIE LD 0 and progress to FIE LD 7 when 32K of memory is used. All software communication with the controller is via programmed lOT instructions for which a summary 'is included in Table 1. Figure 4 shows, two 3·bit field registers: the Instruction Field, which acts ,as an extension to the Instruction and directly obtained operand addresses and the Data Field, which augments indirectly obtained operand addresses. The program can, therefore, 'use one field for instructions and address pointers and another field 'for data. The selection between Instruction and Data Fields is signalled by the OATAF signal generated by the IM6100. A discussion of the various registers follows. EXTENDED MEMORY ADDRESS (0·2) The DMAEN and UP signals provide a simple interlocked handshaking method for transferring data one or more characters at a time (entire blocks) concurrently with processor operations on the bus. Of course, at all times, independent of DMAEN, the SOMA sequencer can pro· ceed only if other bus usage condftions for DMA opera· tions are met (not IOTA, IAUTOI, PCA, JMS, IJMS, ISZ, DMAGNT, or access of location XOOOOS), NOTE: IAUTOI is an indirect cycle of any autoindexed instruc~ tion; IJMS is indirect cycle of JMS. An autoindexed JMP' instruction may not be ,executed when the DMA m"ode is active. SR7 ; 1; SRS ; 0 BURST MODE This mode is the same as the normal mode except when the word count register overflows. When this happens, the SOMA sequencer wi.ll set the WOF flag and revert to the refresh mqde (ignoring OMAEN, freezing WC and .sup· pressing UP). This mode is used when SDMA operations and dynamic memory refresh must be concurrently per· formed. The system designer must carma I the block lengths to be transferred, the refresh interval, and memory system design according to the application and performance desired. FIGURE 4: EMA REG ISTERS INSTRUCTION FIELD REGISTER (IF) 'The I F is a 3·bit register that serves as an extension of the Program Counter (PC). The IF, however, is not incremented when the PC goes from 7777S to OOOOS. The contents of the I F determine the field from which all instruCtions are taken. Operands for all directly addressed memory reference instructions'also come from the Instruction Field, The,indirect pointer for all indirect· Iy addressed memory reference instructions reside in the Instruction Field. The I F is cleared to Os and the IM6100 Program Counter iS,set to 7777S by RESET. SR7; l;SRS; 1 STOP MODE In this mode, no SOMA operations will take place. Naturally, cycle stealing DMA is still possible, and indeed may be used in any of the modes but the designer must be aware that cycle stealing may adversely affect dynamic memory refresh intervals. LWCR and LFSR may be executed in either order to change mode and start DMA. B. Extended Memory Address Control Figure 4 shows the EMA registers in more detail along with the register transfers caused by various instructions. The EMA function of the IM6102 is program compatible with the DEC POP-S/E KMS·E Memory Extension option. The purpose of the EMA function is to extend the effective DATA FIELD REGISTER (OF) The OF is a 3·bit register which determines the memory field from which operands are fetched in indirectly ,addressed AND, TAD, ISZor DCA instructions. However, the branch address for indirectly addressed JMS or JMP instructions is obtained from the Instruction Field. . The Data Field register may be modified under program control. The DF is set to OS, on reset. , INSTRUCTION BUFFER REGISTER (lB) The I B i; a 3·bit registe~ which serves as an input buffer for the Instruction Field (IF) register. All programmed modifications of the I F register are made through the I B IM6102 register. The transfer from IB to IF takes place at the stored in SF (0-2) and SF (3-51. respectively, and the IF, IB and DF registers are cleared. The INTGNT (Interrupt Grant) cycle stores the "current" Program Counter (PC) in location 00008 of Memory Field 08 and the 'CPU resumes operation in location 00018 of Memory Field 08. The Instruction 'Field and Data Field of the program segment being executed by the CPU before the interrupt was acknowledged are available in the SF register. beginning of the execute phase of the "next" JMP or JMS instruction or immediately upon execution of an LI F instruction. Using this feature, a program seg· ment can ,execute an instruction to modify the I F and then "exit" the program segment before the actual modi· fication of the IF takes place. If instructions could change the IF directly, it would be 'impossible to execute the "next" sequential instruction, followed by'a Change IF instruction. The IB to IF transfer is inhibited if the JMP/JMS ,instruction is fetched from control panel memory, which is restricted to 4K, but the LI F instruction is used here to provide the ability to load the IF register from the I B register. This allows the. control panel routines to be executed transparently while the I B and IF (jiffer and also yields a method for the panel to extract or alter the status of the' primary EMA registers. The I B is' set to 08, on reset. The I B to IF transfer takes place during the second cycle of a JMPI JMS instruction when XTC ma,kes a falling ( I ) transition. INTERRUPT INHIBIT FLIP-FLOP, The I NTR EO (Interrupt Request) line to the IM6100 must be "gated" by the Interrupt Inhibit Flip-Flop so that, when the I nstruction Field is changed under program control, all interrupts are disabled until a JMP or JMS instruction is executed. Since the actual modification of the Instruction Field takes place only after the "next" 'JMP/JMS, this inhibition of the INTREO's ensures that the program sequence resumes operation in tAe "new" memory field before an Interrupt 'Request is granted. Since Interrupt Requests are asynchronous in 'nature, a situation may arise in which an INTREO is generated ,when the I F and I B bits are different. The Interrupt, Inhibit FF guarantees the structural integrity of the program segment.' The II F is cleared on reset. SAVE FIELD REGISTER (SF) The SF is a 6-bit register in'which the IB and OF registers are saved during an Interrupt Grant. When an Interrupt occurs, the contEmts' of I B ,and DF are automatically.' TABLE 5 EMA INSTRUCTIONS MNEMONIC OCTAL CODE GTF 6004S OPERATION GET FLAGS Operation: AC (0) +- LINK AC (2) +- INTREO Line AC (3) +- INT INHIBIT FF AC (4) +- INT ENABLE FF AC (6-11) +- SF (0-5) Descr i ption': LINK, INTREOand INT ENABLE FF are internal to the CPU. The INT INHIBIT FF and SF are in the MEDIC. I RTF 6005 8 RETURN FLAGS, Operation: Description: CbF 62N18 LINK +- AC (0) IB <- AC (6-S) DF<-AC (9·11) ! LINK is restored. All AC bits are available externally during IOTA T6 to restore .other flag bits. The internal Interrupt Systern is enabled, However, the Interrupt Inhibit FF is made active until the "next" JMS/JMP III F. The I B is transferred to I F after the "next" JMS[JiVlP III F. CHANGE DATA FIELD Operation: DF <- NS Descri ption: Change OF register to N (OS-7S)' IM6102 TABLE 5 Continued MNEMONIC OCTAL CODE CIF 62N28 OPERATION CHANGE INSTRUCTION FIELD , Operation: IB - N8 Description: Change IB toN (08-78')' Transfer IB to IF after the "next" JMP/JMS/lIF_ The Interrupt Inhibit FF is active until the "next" JMP/JMS/lIF_ :, CDF, CIF RDF - ,62N38 CHANGE DF, IF Operation: OF <- N8 IB <- N8 Description: Combination of CDF and CI F_ READ DATA FIELD 6214 8 Operation: Description: RIF RIB RMF AC (6-8) <- AC (6-8) + OF OR's the contents of OF into bits 6-8 of the AC, All other bits , are unaffected _' READ INSTRUCTION FIELD 6224 8 G2348 Operation: AC (6-8) +- AC (6-8) + IF D.escription: OR's the contents of I F into bits 6-8 of the AC_ All other bits of the AC are unaffected_ READ INTERRUPT BUFFER READ SAVE FIELD ~AC (6-11) + SF Operation: AC (G-l1) Description: OR',s the contents of SF into bits 6-11 of the AC_AII other bits are unaffected, RESTORE MEMORY FIELD G2448 Operation: / Descrip,tioi1 : , I 6254 8 ' IB OF ~ ~ SF (0-2) SF (3-5) 1;he SF register saves the contents of the IB and DF when an interrupt occurs_ This command is used to restore I B and DF when "exiting" from the interrupt service routine , ' ' I ' in another field_ Transfer I B to I F after the next JMP/JMS/ll F _The Interrupt Inhibit Flip-Flop is active until the next JMP/JMS/ll F_ , L1F - LOAD INSTRUCTION FIELD I +: "OR" e: "AND" +-: "IS REPLACED BY" Operation: IF +-IB Description: Transfer I B to I F and c1ear'the Interrupt Inhibit FF IM6102 OPERAND FETCHING I nstructions are accessed from the cu rrently assigned Instruction Field. For indirect AND, TAD, ISZ or DCA instructions, the operand address refers first to the Instruc· tion Field to obtain an Effective Address which in turn refers to a location in the currently addressed Data Field. All instructions and operands are obtained from the field designated by the I F, except for indirectly addressed operands, which are specified by the DF. Thus, DF is active only in the Execute phase of an AND, TAD, ISZ or DCA when it is directly preceded by an In,direct phase. ADDRESS MODE IF DF AND, TAD, ISZ or DCA Direct m n Operand in field m Indirect m n Absolute address of, operand in field m; operand in ,field n (CALL A SUBROUTINE IN MEMORY FIELD 1 (INDICATE CALLING FIELD LOCATION BY THE (CONTENTS OF THE DATA FIELD CIF 10 SUBRP, JMSISUBRP CDF 20 (CHANGE TO II':>ISTRUCTION (FIELD 1 =6212 (SUBRP~ ENTRY ADDRESS (RESTORE DATA FIELD SUBR /POINTER FIELD 2 FIELD 1 SUBR, ' a CLA RDF TAD RETURN DCA EXIT Each field of extended memory contains eight auto·index registers in addresses 10 through 17. For example, assume 'that a program in field 2 is running (IF ~ 2) and using operands in field 1 (DF = 1) when the instruction TAD I 10 is fetched. The. indirect autoindex cycle is entered, and the contents of location lain field 2 are read, incremented, and rewritten. If address lain field 2 originally contained 0546, it now contains 0547. In the execute cycle, the' operand is fetched from location 0547 of field 1. Program control is transferred between memory fields by the CI F instruction, The instruction does not change the instruction field directly, as this would make it impossible to execute the next sequential instruction; instead, it loads the new instruction field in the I B for 'automatic transfer into the I F when either a JMP or JMS instruction is executed. The OF is unaffected by the JMP and JMS instructions. The 12-bit program counter is set in the normal manner and, because the I F is an extension on the most significant end of the PC, the program sequence resumes in the new memory field following a JMPor JMS. Entry into a program interrupt is inhibited after the CI F instruction until a JMP or JMS is executed. EXIT. a JMPISUBR RETURN, CIF /CALLED SUBROUTINE, /LOCATION IN FIELD 1 /RETURN ADDRESS /STORED HERE /READ DATA FIELD INTO AC /CONTENTS OF THE AC ~ /6202 + DATA FIELD BITS /STORE CIF N INSTRUCTION /NOW CHANGE DATA FIELD /IF DESIRED /A CIF INSTRUCTION (RETURN TO CALLING /PROGRAM fUSED TO FORM CIF N /INSTRUCTION a When program interrupt occurs, the current instruction and data field numbers are automatically stored in the 6-,bit save field register, then the IF and DF are cleared_ The 12-bit program counter is stored in location 00008 of field 08 and program control advances to location 00018' of field 08. At the end of the program interrupt subroutine, the RMF instruction restores the IF and DF from the contents of the SF, Alternatively, the GTF and RTF instructions may be used to handle the Save Field and Link information, The following instruction sequence at the end of the program interrupt subroutine continues the interrupted program after the interrupt has been processed: NO,TE: The I F is not incremented if the PC goes from 77778 to 00008_ This feature protects the user from accidentally entering a nonexistent field. To call a subroutine that is out of the current field, the data field register is set to indicate the field of the calling JMS, which establishes the location of the operands as well as the identity of the return field. The instruction field is se', to the field of the ,starting address of the subroutine. The following sequence' returns program control to the main program from a subroutine that is out of the current field. (PROGRAM OPERATIONS IN MEMORY FIELD 2 _/INSTRUCTION FIELD = 2; DATA FIELD = 2 CLA TADAC RMF ION JMPIO (RESTORE AC (LOAD IB ANDDF FROM SF (TURN ON INTERRUPT (SYSTEM (RESTORE PC WITH (CONTENTS OF LOCATION (00008 AND LOAD (IF FROM IB IM6102 IM6100 control panel memory programs, if used must be careful' in the manner that'EMA regis:ter data is manipulated. Control panel interrupt requests bypass' the device i~terruPt enable flip flop; and 'indeed, are granted even bY,a halted CPU. The interrupts from a i:ontror panel may occur at any , time,'and in particular:whep the IB a'rid iF registers do not contain the same data. The EMA logic irihibits IB to IF transfers in 'control panel memory so that panel routines may execute transparently (in particular, JMP/JMS instruc· tions). The panel routines may alter the IF by executing the II F instruction. USElrS should also note that the GTF and RIB instructions read the SF register, and only the R IF instruction reads the I F register. Note also that the :SF saves the I B register rather than the IF during ,an interrupt. However, interrupts are inhibited until the I F and IB registers are the same. ' The memory extension controller that we have'discussed in this section shows three important design considerations involved in extending memory addressing space. The, first is the concept of hav'ing separate instruction and data fields f6r program flexibility,' Th'e secbnd is the importance' of double bufferi'1g the in~truction field register to maintain structural integrity of programs and the third is the pro· vision for saving the current field status upon interrupts and disabling interrupts uritil a tha~ge of instruction field has' been completely executed. When set to a l-counter runs at selected , rate. If the COF flag is cleared, overflow causes clock buffer to be transferred to the clock counter which 'continues to run. COF flag remains set until cleared with lOT 6135 (ClSA). Also cleared by RESET, CAF. EN3, 4, 5- Assum'ing 2 MHz crystal oscillator cleared by RESET, CAF. Bits 3,4,5 Octal 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7 EN7 - I ' Interval Between Pulses Frequency 0 0 50 Hz 500 Hz' 5 KHz Stop Stop 20 msec 2 msec 200jJ.sec 20 /isec " 2 J.1sec Stop 50.l~Hz 500 KHz 0 . Inhibits clock prescaler when set to 1 :cleared by RESET, CAF.EN3·5and EN7 should not be changed'simultaneously. C. Programmable Real Time Clock The programmable real time clock offers the 6100 user a number of ways to accurately measure and count intervals in order to implement real time data acquisition and data processing systems. The crystal used should have the fOllowing characteristics: RS"; 150 ohms CM = 3-30 mpF (10·15F) Co = 10-50 pF Static capacitance should b~, around 5pF; for the greates~ stabiJity, Co should be around ,12pF ,and the, oscillator is parallel resonant. 0:;:;;;;-,.- CLSK ~~=-.....,.. SET BY CLOCK. COUNTER OVERFLOW . FIGURE I; RTC REGISTERS A discussion of the Real Time Clock registers as ~hown in Fig. 5 follows: CLOCK ENABLE REGISTER . " , ' . This register controls'tlie mode of counting, whether clock interrupts' are allowed, and the rate of the time base of the clock. For a description refer to the register bit assignments. TABLE 6 CLOCK ENABLE REGISTER BIT ASSIGNMEN,TS CLOCK BUFFER REGISTER (CB) '5 ENO . EN2 EN3 EN4 EN5 10 11 EN1 * Don't care forwriteandzerofor read.' , Where ENO When set to 1, enables clock overflow (COF flag) to cause an interrupt. Cleared by, RESET, C.A.F~ EN2,When reset to a O-counter runs at selected rate.O~erfiow occurs every 4096 (212) co'unts.COF flag remains set until cleared by lOT 6135 (ClSA), CAF, RESET. This ,12·bit register stores data being transferred from the AC to the dock counter, or from the clock counter to the AC. It also permits presetting of the clo~k counter. CLOCK COUNTER REGISTER (CC), This register is a , 12·bit binary counter: that may load the clock buffer or be loaded from it. It is driven by a'2 MHz crystal oscillator, wit.h the proper predivision set by the time base selection. When an overflow occurs and if bit 0 of the clock enable register is a logic one, an interrupt :is requ,ested. If, bit 2 is also 1, overflow causes the clock buffer 'to be transferred automaticaily into the clock counter. IM6102' O~OIL TIME BASE MULTIPLEXER CLOCK OVERFLOW FLAG The multiplexe~ provides count pulses to the clock counter , according to the rate set bY,the'clock enable register. Use of , other than a 2 MHz crystal for the clock will result in proportionately different time bases. This flag is set by ~ clock counter overflow. It is cleared by CAF, CLSA and RESET. Its complement ,provides LSB (V R11) of interrupt ve·~tor. If ~NO of clock enable counter is set, COF can cause an interrupt request. The COF is set when the MSB of the, counter makes a "1" to "0" transition. , TABLE 7 RTC INSTRUCTIONS MNEMONIC OCTAL CODE CLZE 6130 8 CLEAR ENABLE REGISTER PER AC Description: Clears the bits in the clock enable register corresponding to those bits set in the AC. The AC is not changed, , CLSK 6131 8 I , OPERATION SKIP ON CLOCK INTERRUPT Description: Causes the program counter to be incremented by one if clock interrupt conditions exists, so that the next sequential' instruction is skipped. CLOE 61328 SET ENABLE REGISTER PER AC Description: Sets the bits in the clock enable register corresponding 'to those bits set in the AC. The AC is not changed. CLAB 6133 8 TRANSFER AC TO CLOCK BUFFER Description: Causes the contents of the AC to be transferred to the Clock Buffer, then causes the coni:ents of the Clock Buffer,to be transferred to the Clock Counter. The AC is n6t changed. CLEN 61348 READ CLOCK STATUS Description: Interrogates the clock Overflow status flip flop by clearing AC, then transferring'clock ~tatus into ACbit O. COF is cleared. CLSA 6135 8 READ CLOCK STATUS Description: Interrogates the clock overflow statusflip flop by clearing AC, then transferring clock status into AC bit O. COF is cleared. CLBA 6136 8 READ CLOCK BUFFER Description: Clears the AC, then' transfers the contents of the Clock Buffer into the AC, CLCA 6137 8 READ CLOCK COUNTER Description: Clears the AC, winsfers the contents of the Clock Counter to the C!ock Buffer, then transfers the contel!ts of the Clock Buffer, into the AC. If EN7 is set to 1 (clock prescaler is inhibited), the CLCA instruction increments the prescaler input by,one. If the clock is in the "stop" mode, but EN7 is not inhibited, the prescaler will not be clocked by the CLCA instruction. CAF 6007 8 CLEAR ALL FLAGS Description: Clears GOF flag (and also F7E, WOF flags), clock enable and clock buffer registers. " " IM6102 SYSTEM CONSIDERATIONS The IM6102 is the highest priority deviCe in a priority interrupt scheme. Itprovides an active low signal on pin 40, POUT,to signal the next lower priority device in the chain. (thus, a high level on POUT indicates that the 6102 is not requesting an interrupti via its "priority· in", PRI'N, input. The IM6102 when requesting an interrupt activates the SKP/INT line low on pin 35 and the ·POUT line low on pin 40 if its interrupt inhibit flip·flop is not set. 'The lOT instructions used by the IM6102 preclude the use of certain device addresses when the system uses IM6101 PIEs. The addresses that may not be used are those given by bits 3 through 7 of the lOT instructions that are used with the IM6102. These addresses are 00101, 01000, 01001, 01010, 01011 corresponding'to lOT instructions 612X, 613X, 620X, 621 X, 622,X, 623X, 624X, 625X, 626X and 627X. The IM6102 does not generate DMAREQ signals to the 6100 because of its simultaneous use of the DX bus. It monitors the DMAGNT signal in order to place,the EMA 0, 1, 2 I,ines on pins 36, 37,38 in a high impedance state while DMAGNT is high. If the application requires other peripherals requiring direct memory access on a cycle stealing basis, for example, bus contention problems will be resolved by the IM6102 as it monitors the DMAGNT line and gets off the bus (by placing all lines in the high impedance state I when DMAGNT is active. If interrupts are enabled and a request is pending, during the first INTGNT cycle, the IM6102, will detect the refer· encing'of locati~n 00008 by the IM6100 in order to save the PC and will suspend simultaneous DMA during that cycle. The logic will in fact suspend simultaneous DMA in any cycle that location 00008 is, referenced, either ,in main memory or control panel memory. This makes it possible to disable automatic interrupt vectoring by grounding the INTGNT line to the IM6102. This will not affect the generation of INTREQ so the IM6100 will have to poll peripheral devices (skip on flag instructionsl to determine the interrupting source. Grounding INTGNT is not possible in extended memory applications since the, INTGNT signal is used to save the Instruction' Buffer and Data Field Register and clear thel F, IBand DF registers. (All' peripheral device interruptservice routines have their entry point at location 00018 of Memory Field 08). ,If no interrupt requests are pending in the 6102 (COF, F7E or WOFI from the DMA or RTC functions, the IM6102 interrupt request flip-flop is clear 'andPOUT, the priority out signal, is high, enabling interrupt requests downstream in the priority chain. In the event that interrupts are en· abled (DMA status bit SRll is set and/or clock enable bit ENO is set) and an interrupting condition occurs (F7E, WOF, COF), the POUT signal goes low asynchronously dis· abling interrupt vectors downstream. If the Interrupt Inhibit Flip-Flop is not set, the SKP/INT line is driven low by the interrupt request. If the IIFF is set, the SKP/INT line stays high until the IIFF is cleared (by RESET or an I B to IF transferl at which time SKP/INT may be driven low. Skip requests will always propagate independently of IIFF during IOTA -DEVSEl- XTC_ Interrupt requests from devices downstream of the IM6'l 02 must also be channeled via the IM6102 in order that the IIFF may condition the request timing. The IM6102 provides a built in pull-up on the SKP/INTX line coming in from devices downstream in the priority chain_ At 5v, the pull-Up looks like a 10K resist6r;' at 10V, it looks like 5K. The execution of any 'lOT instruction will reset I NTGNT to a low level at the end of IOTA time. This lOT instruction will be the first instruction in the interrupt service routine after, saving status. If hardware vectoring is being used, any lOT instruction when INTGNT is high will cause the IM6102 to place a vector address on the bus if it requested an interrupt and pull the Cl and C2 lines.low, thus placing the vector in PC and forcing a branch to the service routine. If the C2 line is left unconnected, the vector address will not be forced into the PC, but will be OR'ed into the AC. The interrupt service routine would have to execute a ClA after its first iOT instruction in order to clear the AC. Note that the lSB of the vector address is determined by the complement of the COF flag and that a DMA interrupt service routine must distinguish ,between the two possible interrupting conditions, a word count overflow ora field ,7 wrap'around ·error. The programmer may read the DMAstatus register with an RFSR instruction and also test the WOF flag with a skip instruction, SKOF. The COF flag may also be tested with the ClSK ,skip instruction. The flag may be read (and cleared) with the ClSA instruction. The skip instructions cause the SKP/INT line to go low during IOTA • XTC time if the flag being tested is set, At all other times, the SKP/INT line carries interrupt requests as modified by the IM6102 interrupt inhibit logic. The flags must always be explicitly cleared by the interrupt service routine., The DMA transfer rate depends on the program. The minimum rate would be obtained if the processor was executing an auto indexed DCA or- an indirect JMS (even if non-autoindexed, DMA is suppressed during indirect phase of JMS). Continuously executing these instructions would cause DMA transfers to occur only every third memory cycle (lFETCHI. The maximum rate could be obtained by e)(ecuting a JMP. loop (JMP to itself); data would be transferred on every cycle and the interrupt routine entered when word count overflows could bump the return address out of the loop. In dynamic memory systems it should be noted that the MEMSEl' signal narrows when the mode changes from write to refresh (burst mode). RESET signals may need to be limited in duration to prevent loss of memory data in dY,namic memory systems. IM6102 The accuracy of the clock counter in the programmable real time clock section of the IM6102 is as follows: CASE 1: Counter running; CC loaded from AC via CB using instruction CLAB (lOT 6133) accuracy is 0 to +1 count. CASE 2: CC loaded from CB automatically on ove'rflow; the accuracy of counting is PIN NUMBER 2 3 6 8 11 12 15 29 31 34 36 37 38 40 PIN NAME RTC ONLY DMAEN DMAGNT MEMSEL * UP LXMAH* GND USED N/C N/C N/C N/C VCC USED USED USED N/C N/C N/C USED XTC~ SKP/INTX OSCIN OSCOUT C2 EMAO EMA 1 EMA2 PROUT , then 6nly dependent on accuracy of oscillator. IM6102 users who do not need all the capabilities of the device may improve systems performance by not using some of the features. To do this properly, certain flins on the device will become unused. The following table summarizes what may be done with certain pins All when using only part of the IM'6102 functions. unlisted pins must be used when implementing any of the three basic features. SDMAONLY EMCONLY EMC& DYNAMIC REFRESI-I USED USED USED USED USED USED VCC GND N/C .USED N/C N/C N/C USED GND USED N/C N/C N/C N/C USED GND N/C N/C USED USED USED N/C GND USED USED N/C USED USED USED GND N/C N/C USED USED USED N/C IMai02 TABLE 1 SUMMARY OF IM6102 INSTRUCTIONS MNEMONIC OCTAL CODE I/O CONTROL LINES C1 C2 CO 6004 6005 62N1 62N2 62N3 6214 6224 6234 6244 6254 0 1 1 .1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 6130 1 1 1 CLSK CLOE 6131 6132 1 1 1 1 1 1 CLAB 6133 1 '1 1 CLEN CLSA CLBA CLCA 6134 6135 6136 6137 0 '0 0 0 0 0 0 0 1 1 1 LCAR , RCAR 0 0 0 1 0 1 1 1 LWCR 6205 6215 . 6225 1 LEAR REAR . LFSR RFSR 62N6 6235 6245 6255 0 1 1 0 1 0 1 1 1 1 SKOF WRVR 6265 6275 1 0 1 1 1 1 CAF 6007 1 1 1 GTF RTF COF CIF COF, CIF ROF RIF RIB RMF LlF CLZE' , . ,. 1 0 1 1 1 OPERATION I CD Get flags, INT INH FF...,. AC(3f. SF (0-5)"'" AC(6-11) ~ Return flags, AC(6-8)"'" IB, AC(9-11) ...,. OF Change Data Field, N ...,. OF Change IF, N"'" IB Combination of COF, CIF . Read OF, OF + AC(6-8)"'" AC(6-8) Read IF, IF + AC(6-8) ""'AC(6-8) Read Save Field, SF + AC(6-11)"'" AC(6-11) Restore Mem. Field, SF(0-2) """IB, SF(3-5)"'" OF Load IF, IB"'" IF Clear Clock Enable Register if corresponding AC bit is set AC not changed , Skip on Clock Overflow Interrupt condition Set Clock Enable f;!egister if.corresponding AC bitis set AC not changed AC"'" Clock Buffer; Clock Buffer"'",.Clock Counter; . AC not changed Clock Enable Register ....,. AC COF ...,. AC(O), Clear COF Status bit Clock Buffer"'" AC' Clock COLJnter ...,. Clock Buffer; Clock Buffer"'" AC AC"'" Current Address Register, 0 '-7AC Current Address Register"'" AC AC"'" Word Count Register, Start OMA, 0"'" AC; clears word count overflow (WOF) N"'" Extended Current Address Register (ECA) Read ECA"ECA + AC(6-8)"'" AC(6-8) AC(7-11) 4 Status Register, 0"'" AC OMA Status Register + AC(5-11 ) ...,. AC(5-11); clears Field 7 Wraparound error (F7E) Skip on Word Count Overflow AC(0-10)"'" Vector Register, 0"'" AC @Clear all flags (F7E, WOF, COF) Clear clock Enable register, clock buffer , NOTES: 1. The internal flags of the IMB100 are defined as follows: LINK -+ AC (0), INTREQ -+ AC (2) and INTERRUPT ENABLE F F ...,. AC (4). 2. When RTF is executed, the LINK is restored from AC (0) and the Interrupt System is enabled after the next sequential instruction is executed. The Interrupt Inhibit FF is set preventing interrupts until the next JMP, JMS or LlF instruction is executed. 3. A hardware RESET clears F7E, WOF, 11 FF and COF. The IF and, OF are cleared to OS. The DMA status register is cleared. (Reed; refresh; disable F1E and WOF interrupts; no carry from CAO to ECA2). The clock Enable register is clEN.red (Disable COF interrupt; disable clock buffer to clock counter transfer on COF; disable counter). Counter/buffer is cleared. , IM6102 TABLE 2 SUMMARY OF IM6102 REGISTER BIT ASSIGNMENTS Current Address Extended Current Address Word Count DMA Status (1) Interrupt Vector (2) RIF Instruction (3) RTF, CI F Instruction GTF, RIB Instruction CDF, RDF Instruction RTF Instruction Clock Enable (5) Clock Buffer Clock Overflow (6) (1 ) (2) (3) (4) (5) (6) DXO DX1 DX2 DX3 DX4 DX5 DX6 CAO CAl CA2 CA3 CA4 CA5 CA6 CA7 ECAO ECAl WC6 WC7 SR6 SR7 VR6 VR7 IFl IFO IBl IBO SFO SFl DFO DFl . WCO WCl WC2 WC3 WC4 VRO VRl VR2 VR3 VR4 WC5 SR5 VR5 IIFF(4) ENO CBO COF CBl EN2 CB2 EN3 CB3 EN4 CB4 EN5 CB5 CB6 DX7 EN7 CB7 DXB DX9 DX10 DX11 CAB CA9 ECA2 WCB WC9 SRB SR9 VRB VR9 IF2 IB2 SF3 SF2 DF2 DFO CA10 CAll CBB CB9 WC10 WC11 SR10 SRll VR10 VR11 SF4 SF5 DFl DF2 CB10 CB11 DMA STATUS F7E; cleared by CAF, RFSR (at IOTA· XTC timel.RESET} ~~~ SR5 Set if Field 7 wraparound carry error SR6 Set if DMA Word Counter Overflow WOF; cleared by CAF, LWCR, RESET BITS SR7 Mode Bit 7} ; Cleared by RESET (REFRESH MODE) SRB Mode Bit 8 See below , SR9 Carry enable from CAO·ll to ECA2 if set - CE SR10 DMA Write if set SRll Enable F7E or WOF interrupt if set - IE VRO·VR10 loaded from AC. VR11 is equivalent to COF IF Instruction Field; cleared to 08 by RESET AND INTGNT II FF - Interrupt Inhibit Flip·Flop; set whenever I B i= IF; (CI F, CDF/CI F, RMF, RTF) cleared by RESET and I B ,.• I F transfer END Enable Clock Overflow (COF) interrupt; cleared (interrupt disable) by RESET, CAF EN2 - When set causes clock buffer to be transferred to clock counter on COF. Counter runs at selected rate; COF remains set until cleared with CLSA, When cleared to 0, counter runs at selected rate, overflow occurs every 212 counts and COF remains set. EN2 is cleared by R ES,ET , CAF EN3, EN4, EN5 - Select interval between pulses, Cleared to 000 by RESET (counter disabled), CAF See below. EN7 Inhibits clock prescaler when set. Cleared by RESET, CAF COF - Clock Overflow status bit; cleared by CAF, RESET and CLSA; complement provides LSB of interrupt vector. SR 7,8 00 01 10 11 Refresh mode; WC is frozen,no UP, DMAEN' don't care Normal mode; DMAEN(H) freezes WC,CA and no UP if WC has not overflowed; stop if WC overflows Burst mode; DMAEN (H) freezes WC, CA and no UP if WC has not overflowed ; reverts to refresh mode if WC overflows. Stops SDMA EN3,4,5 000 001 010 011 100 101 110 111 with 2 MHz clock STOP STOP 20 ,ms interval 2 ms interval 200 /.IS interval 20/.ls interval 2 /.Is interval STOP NOTES: 1. Bits SR 7 and 8 do not change when the DMA controller stops or r.verts to'refresh mode as a result of we overflow. 2. The "overflow" status is defined as set when the most significant bit of a' counter makes a "1" to "0" transition. , IM61.02 ,U~n!L SOMA OPERATIONS TIMING A:IM6100~lg~al~ IM61De asc OUT '.': IM6l00' I T.STA~ES. ·IM61Da LXMAR \ J IM6100 M~MSEl ~. IM61Da XTA IM61DO X-TC .. Ox READ DATA , TO IM61DD ; B.DMA Read LXMAR' MEMSEL" UP ox • READ DATA ". ·TO IM61Da ADDRESS FR0M "'M6l0D ! DMA ADDRESS MEMORY DATA F=R'oM 111/16102 TO USER ';.'! .' C. DMA Read/Refresh . LXMAR' ~ _ _ _ _ _ _ _ _ _ _ _ _",,-_--"J" ,~,-,:,--,--,---,-,--,-_ _ MEMSEL'J ,'-_ _ _ _ _----'--J/ UP XTC' :J ox ADDRESS , FROM IM61DO REFRESH,ADDRESS • FROM IM6102 READ DATA TO IM61DD MEMORY DATA '; i; D. DMAWrlte LXMAR* .. ~ ox'; :, .... ,~ .~ ·:OMAACDRESS . FA'OM IMS102 ADDRESS FROM'I~6'OO ~ ',; I,' USERDATA TO MEMORY L' E. DMA Write/Refresh • ~~~A~' ~",:;,,_ _ _ _ _ _ _ _ _ _ _ _ _ _---,~,-_,-,,-_ _ _ _ __ ,'-________----'____J/ 'MEMSEL" Up .. XTC' ....J ::J ~ ox ADDRESS FROM IM61Da 'READ DATA TO'IM6100 ........ ~ -tMDWR~ REFRESH ADDRESS FROM'IM6102 . IM6102 TIMING DIAGRAM IM6100 OSCOUT .,....,.._.....r IM6100 LXMAR !+-'LlN. - - tOEN ----:-1 .. IM6lDD OEVSEL IM6100 XTA f IM6lDD XTC tAI~ 1-'OIs--1 \. ./ 'D'H~I I- \. \. ---I' ' r f-j--tAIH ox ~ / IM6102DATA TO IM6100 lOT INSTRUCTION rROM IM610D~ TOIM6lD2 ,.' TO IM6lD2 : -.--- _ _ teEN X SKP/INT I --- \-'s'D X SKP/lNTX (FROM OTH ER PERIPHERALS) CD.c1.C2 IM610D AC DATA· - \I --j---tCEN / IM6102 D~DIL IM6102A ABSOLUTE MAXIMUM RATINGS Operating Temperature IndustriallM6102A ............ -40°C to +85°C Storage Temperature ............ -65°C to 150°C Operating Voltage '............... +4.0V to +11.0V Supply Voltage .......................... '. -+12:0V Voltage On Ariy Input or " Output Pin .................. -O.3V to Vcc +O.3V NOTE: Stresses above those listed under "Absolute Maximum ,Ratings" may cause permanent deilice failure. These are stress ratings only and functional operaiion of the devices at these or any other conditions above those indicated in the operation sections of this specification is not Implied. . Exposure to absolute maximum 'rating conditions for extended periods may cause device failures. D.C. CHARACTERISTICS, TEST CONDITIONS: VCC = 10V ± 5%, TA = -40~C to +85°C SYMBOL ,,1 2 VIH Vll 3 4 lil VOH VOL 5 6, 7 8 9 10 PARAMETER Input Voltage High Input Voltage Low CONDITIONS Input Leakagel11 GND:SVIN:SVee -1.0 IOH = OmA Vee-O.Ol IOL = OmA GND:SVouT:SVee -1.0 ' Output Voltage, Highl21 Output Voltage Low Output Leakage IOl Icc Icc CIN Power Supply Current-Standby Power Supply Current-Dynamic Input Capacitancel11 Co Output Capacitance I 11 NOTE: 1. Except pins 15. 29. 31 MIN TYP MAX 70% Vee .' 20% Vee 1.0 UNITS ,V V ,..A V GND+O.Ol 1.0 V ,..A 7.0 900 4.0 8.0 ,..A rnA pF 8.0 10.0 pF VIN-GND or.vcc fe ~ 5.71MHz 2. Except pins 32. 33. 34. 'A.C.CHARACTERISTICS .. , :rEST CONDITIONS: VCC = 10V ± 5%, CL = 50pF, TA = -40°C to +85°C, fc ~'5.71MHz .- ." ., ..... SYMBOL PARAMETER " 1 tUN LXMAR Pulse Width IN 125 2 3 tAIS tAIH 50 50 4 5 tOEN teEN Address Setup Time IN: DX-LXMAR II) Address Hold Time IN: LXMAR(I)-DX Data,Output Enable Time: DEVSELII)-DX 6 tOIS MIN MAX' UNITS ns ns 240 Controls Output Enable Time: DEVSELII)-lines CO,Cl,C2,SII Data Input Setup Time: DX-DEVSELII) TYP 240 50 50 ns ns ns ns 7 TOIH Data Input Hold Time: DEVSELII)-DX 8 9 10 tRST tSID RESET Input Pulse Width SKPIINTX to SKPIINT Propagation Delay tOMlX 11 tOEM DMA Control Signals Delay: XTC-XTC'; MEMSEL-MEMSEL', LXMAR-LXMAR' Enable/Disable Time from DMAGNT to EMA Lines 12 tMOR MEMSEL' Pulse Width READ 300 13 14 tMOW tMOWR MEMSEL' Pulse Width WRITE MEMSEL' pulse Width WRITE/REFSH 15 !Lo LXMAR' Pulse Width 380 240 150 16 tORAT DMA READ Access Time: LXMAR'II)-UPII) 300 150 55 210 ns ns 17 18 19 20 21 22 23 24 25 26 ns ns 250 100 ns 100 ns 50 ns ns ns ns ns ns tOXAS OX & EMA Address Setup Time Wrt LXMAR'(I) tOXAH OX & EMA Address Hold Time Wrt LXMAR'II) tOREN tRUP DMA READ Enable Time: MEMSEL' II)-UPII)~ UP Pulse Width DMA READ 150 ns tOWAT DMA WRITE Access Time: LXMAR'(I)-MEMSEL'(I) 300 ns tOWEN DMA WRITE Enable Time: UP II)-MEMSEL 'II) 210 ns tMWS MEMSEL' Setup Time DMA WRITE MEMSEL'(I)-LXMAR'(I) 50 ns tOMS tOMH twup DMAEN Setup Time Wrt XT A (I) 50 ns DMAEN Hold Time Wrt XTA (I) 50 ns UP Pulse Width DMA WRITE 300 ns ns IM6102 IM61 02-1 ABSOLUTE MAXIMUM RATINGS Operating Temperature Industriai"IM6102-11 ........... -40 0 e:to +85°e Storage Temperature .........•.. -65° eto 150° C Operating Voltage ..•..•.... , . ..•. +4.0V to +7.0V Supply Voltage .. ~ ... : ..••....... , ..•.... " +8.0V Voltage Oll·Any Input or .. Output Pin . • . . . • . . . . . . . . . . .. -0.3V to Vcc +0.3V NOTE: Stresses above those listed under ';Absolute 'Maximum , 'Ratings" may cause' permanent deviCli' failure. These 'are stress ratings only and functional operaticin of the devices at these or any other conditions above: those indicated In the operation, sections of this specification is not implied, Exposure to absolute maximu,r(l rating conditions for extended periods may cause device faiiure's" D"C" CHARACTERISTICS TEST CONDITIONS: Vcc = 5.0V ± 10%, TA = -40"Cto +85°e l' 2 3 4 5 6 7 8 9 10 SYMBOL PARAMETER VIH VIL Input Voltage High Input Voltage Low ilL' V.oH V.oL I.oL Icc Icc CIN, Inplit Leakagel" Output Voltage Highl21 Output Voltage Low Output Leakage Power Supply Current-Standby Power Supply Current-Dynamic Input Capacitancel',1 Output Capac ita noel' I C.o NOTE. 1. Except pinS 15, 29, 31 MIN ' , 'C,ONDITIONS TYP MAX UNITS V V p.A V V p.A p.A mA pF pF Vee-2.0 ' ·GND",VIN",Vee -1.0 ' ',I.oH = -0.2mA ' I.ol = 2.0mA GND",V.oUT",Vee VIN=GND or Vee ' fe - 3.33MHz Vee-Om 20% Vee '1'.0 ' GND+0.01 1.0 800 2,0 8;0 10.0' , -1.0 7'0 8,0 " 2. Except pinS 32, 33, 34. A"C" CHARACTERISTICS fc = 3.33MHz' TEST CONDITIONS: 5.0V ± 10%, CL = 50pF,TA = -40°C to +85°e, SYMBOL 1 tLiN 2 tAIS 3 tAIH 4 to EN ' 5 'teEN 6 tOIS 7 TOIH 8 tRST 9 tSID 10 tOMLX 11 12 13 14 15 16 1r 18 19 20 21 22 tOEM tMOR tMow tMowR !Lo tORAT -tOXAS tOXAH tOREN tRuP tOWA,. tOWEN, tMWS 23 24 tOMS 25 .tOMH 26 twup MIN PA~AMETER LXMAR Pulse Width IN " , Address Setup Time IN: OX-LX MAR (II Address Hold Time IN: LXMAR( Ii-OX Data Output Enable Time: DEVSEL(lI-DX Controls Output Enable Time: DEVSEL( I Hines 'CO,C1 ,C2,SII Data Input Setup Time: DX-DEVSELIII Data I nput Hold Time: DEVSELIII-DX RESET Input Pulse Width ,SKPIINTX to SKPIINT Propagation Delay , DMA Control Signals Delay: XTC-XTC"; 'MEMSEL-MEMSEL", LXMAR-LXMAR" .! ' Enable/Disable Time from DMAGNT toEMA lines MEMSEL" Pulse Width READ MEMSEL" PulseWidt/lWRITE ' , MEMSEL" Pul~e Width'WRITE/REFSH LXMAR" Pulse Width" DMA READ . . ...Access Time: LXMAR"II,-UPII, .. . OX & EMA Address Setup Time Wrt LXMAR" III UP PulseW[d.th DMA, R,EAD PMAWR!TE Access Time: ,LXMAR"III~!i.1EMSEL"I'fl DMA WRITE Enable rir(le: UP ill-ME:MsEL "III MEMSEL:, Setup Time DMA WRITE MEMSEL"(lI~l:XMAR"111 . - , ' " -- 350 350 UNITS ns ns ns ns ns' ns ns' 100 100 500 ns ns 120 " ' , ' 120 "'" 550 700 400 ;160 , 400. '80 , .. ,', 85 260 550 , "MAX 70 100 '125, 125 400 ., OX &EMA Address Hold Ti,meWrt LXMAR"II",I, DMA READ Enable Time: MEMSEL" III-UP.!II OM.A,EN, Setup Time wrt XTA III DMAEN Hole! Time wrt XTA III, UP Pulse Width DMA WRITE TYP 250 ns ns ns ns ns ns ns ns ns ns ns , ; .... ns ri~ 100 100 100, ns ns 550 ns " ('Is ''-; IM81 02 IM6102 ABSOLUTE MAXIMUM RATINGS Operating Temperature, " ." ' i ' : Industrial,IM6102 .•.• ,. . . . . .• . .-40° C .to +85° C Storage Temperature .•... ; •....•• -65°C to 150°C 'Operating Voltage .....•...•...••. +4.0V to +7.0V Supply Voltage' . . . . . . . . . . . • . . . .. • . .• . • • . ... +8.0V Voltage On Any Input or Output Pin .;.; •.. : .. : ....... ; -0.3V to Vee +0.3V NOTE: Stresses above those listed under "Absolute Maximum Ratings': may cause permanent device. failure. These are stress ratings only and functional operation of the devices at these or any other conditions above those indicated in the operation sections of tliis speclflc'ailan "is riot implied. Exposure ,to absolute' maximum rating 'condltions 'for extended periods may cause device failures. . D.C. CHARACtERISTICS TEST CONDITIONS: Vee = 5.0V ± 10%, TA = -40°C to +85° C SYMBOL PARAMETER 1 VIH Input Voltage High 2 VIL ,CONDITIONS MIN Vee-2.0 4 ' VOH Input Voltage Low Input Leakagell' Output Voltage High,2 5 VOL Output' Voltage ·.Low 6 7 IOl Ouiput Leakage GNO~VouT~Vee Icc Power Supply Current-Standby VIN=GNO or Vee 8 Icc CIN 9 10 : Co Power Supply eurrent-Dynami'c Input Capacitance. 1 .Ie ~ III , , GNO~VIN~Vee -1.0 IOH - -0.2mA 2.4 IOl TYP V = 2.0mA V 0:8 1.0 Il A 0.45 V V ,1,0 Il A 1.0 800 Il A 1.8 mA. ,7.0 8,0. 8.0" ',10.0 pF TYP :;MAX -1.0 = 2.5MHz Output Capacitance 1 NOTE: 1, Except pins 15. 29. 31 UNITS MAX pF , 2. Except pins 32. 33. 34. A.C. CHARACTERISTICS TEST CONDITIONS: 5.0V ± 10o/~, CL = 50pF, TA =-40°C to'+85°C, fc = 2;5MHz " SYMBOL .PARAMETER MIN 1 !LIN LX MAR Pulse Width IN 300, 2 tAIS tAIH Address Setup Time IN: DX-LX~AR (!) Addre,ss Hold'Time IN: LXMAR(I)-DX 120 tOEN Data Output Enable Time: DEVSEL(!)-DX 5 teEN " 6 Controls Output Enable Time: DE;VSEL(lHlnes C::O,ei,c:2,S/1 Data Input Setup Time: DX-DEVSELI! I 3 4 7 tOIS TOIH 8 9 tRST. tSIO RESET Input Pulse Width. : SKP/INTX to'SKPIINT'Propagation Deiay 10 tOMlX DMA Control Signals Delay: XTC-XTC'; MEMSEL-MEMSEL', LXMAR-LXMAR' 11 12 13 14 , .15 17 18 Data Input Hold 'Time: .OEVSELI! I-OX, tOEM tMOR, "Enable/Disable Time from DMAGNT to EMA Lines MEMSEL,' Pulse Width READ tMOW tMOWR MEMSEL' Pulse Width WRITE MEMSEL' Pulse WidthWRITE/REFSH tLo 16 ,tORAT tOXAS tOXAH 19 80 LXMAR' Puls.e Width: " DMA READ Access Time: LXMAR'lli-UPi!J ns 'I' , ' , ns ns ,:. I 400 400 ':1 1QO ,100 U,NITS' ns ns· ns ns :1"/ ns 500 .150 ns 150 100 ns I '. , '750 ns ns I ns ns 950 550 ns 350 OX & EMAAddress Setup Time Wrt LXMAR'(lJ OX & EMA Address Hold Time Wrt lXMAR'llJ . DMA READ Enable :nme: MEMSEL' Ill-UPI! J , 750, " ! ! ,, " 120 " 175 ns ns, " " 550 ,350 ns ns, . 750· n~ 550 ns ns 24· tOMS, MEMSEL' Setup Tilne DMAWRITE·MEMSEVIl.J-LX¥AR'IIJ I'. ,; 100 :100' DMAENSetup Time, Wrt XTA iii ' 25 DMAEN Hold Time Wrt XTA I fl 100 UP Pulse Width DMA, WRITE ,750' tOREN 20 'tRUP 21 tOWAT, 22' tOWEN 23' tMwS 26 tOMH twup UP Pulse Width DMA READ DMA WRITE Access Time: LXMAR'11J~MEMSEL',(!1 DMA WRITE Enable Time: UP IIJ-MEMSEL'\'f1 , " . ,,' , , , " ns ns ris, " ", ns " IM6102 IM6102AM (Military) ABSOLUTE MAXIMUM RATINGS .: ,~ Ope~ating Temperature ,,'" , Military IM6102,AM" .... ~ ....... -55°C to +125°C Storage Temperature ,............ -65° C to 150° C Operating Voltage ............... +4.0V to +11.bv Supply Voltage ........................... +12.0V Voltage On 'Any Input or Output Pin ...... , ......... ;. -0.3V to Vee +0.3V NOTE: Stresses above those listed under "Absolute Maximum , Ratings"may cause permarlimt' device failure;, These are stress ratings only and functional operation of the',devices at '. these or any other conditions above those indicated,;ln'the operation sections of this specificatiQn is :not· implied, Exposure to absolute' maximum .rating conditionS "for extended ~eriods may cause devic:e failure~. ' , D.C. CHARACTERISTICS TEST CONDITIONS: Vee = 10V ±,5%, TA = ~55°C to+:125°C .. SYMBOL 1 2 VIH VIL' PARAMETE;R Input Voltage High Input Voltage Low 3 ilL VOH VOL IOL ,,' Output Voltage Highi21 Output Voltage Low Output Leakage" 4 5' 6 7 8 9 10 Input Leakagel11 CC)NOiTIONS ,. 'GND:'oVINSVee -1.0 IOH - OmA IOL'= OmA 'Vee-0:01:, :GNDSVouTSVee VIN=GND or Vee "fcj -'5.0MHz' -1,0 " 'Power Supplyeurrent-Staridby Power Supply Current-Dynamic, Co Output Clilpacitancel1 r ' I .' 'UNITS' 200/0 Vee 1,:0 V V' /J. A , " N GND+0.01 V 1,0" , 9.00 4,.0 /J. A .,' Input Capacitance I 1I .. MAX ',' . 'Icc, Icc CIN NOTE: 1, Except pins 15, 29, 31, T'(P MIN 70% Vee 7,0 8,0 .. ... /J. A mA pF, 8,0 10,0 pF. 2, Except pins 32, 33. 34, , ~: A.C. CHARACTERISTICS ~. TEST CONDITIONS: Vee = 1OV± 5%,CL == 50pF, TA == -55° C to +125° C, fe = i),OMHz' ,~' SYMBOL 1 tLiN PARAMETER LXMAR Pulse Width IN 2 3 tAIS tAIH Address Setup Time IN: DX-LXMAR (II Address Hold Time IN: LXMAR(II-DX 4 tOEN Data Output Enable Time: DEVSEL( I I-DX teEN ' Controls Output Enable Time: DEVSEL( II-lines CO,C1 ;C2,S/I tOIS' 7 TOIH tRST Data Input Setup Time: DX-DEVSEL'II Data Input Hold Time: DEVSEL,II-DX " i' P .' RESET Input Pulse,Width SKP/INTX to SKPflNT Propagation Delay DMA Control Signals Delay: XTC-XTC'; MEMSEL-MEMSEL '. LXMAR-LXMAR' ; UNrr:~ ns ns' ns ns ,', " EnablefDisable Time from DMAGNT to EMA Lines MEMSEL' Pulse Width READ 13 14 15 tLO ' LXMAR' Pulse Width 175 16 17 tORAT DMA READ Access Time: L«MAR',I'-UP,I, 375 70 ' 60 DX & EMA Address Setup Time Wrt LXMAR'j.j" tOXAH DX & EMA Address Hold Time Wrt LXMAR'!I, tOREN DMA READ Enable Time: MEMSEL' ,II-UP,I, 20 tRUP 21 towAT UP Pulse Width DMA READ DMA WRITE Access TirT1e: LXMAR',II-MEMSEL',I, ns: ' 375 '475 ' MEMSEL' Pulse Width WRITE MEMSEL' Pulse Width WRITEfREFSH 275 ' '., " 70 275 ,. 175 'c"' 375 '275 50 22 tOWEN DMA WRITE Enable Time: UP III-MEMSEL ',II 23 24 tMWS MEMSEL' Setup Time DMA WRITE MEMSEL',I,-LXMAR'!li tOMS DMAEN Setup Time Wrt XTA ii' DMAEN Hold TimeWrt XTA ,I, 50 50 UP Pulse Width DM/!'., WRITE 375 ,. ns ns ' , 1,20 tMDR; tMOW tMOWR tOXAS ns ns 120 tOEM 18 19 ns'. ' ns ns, ' I" 250' ',' 260 260 " 11 I 'MAX 60 60 12 25' tOMH 26, twup . , 60 5 tsio tOM LX ' 60 TYP, i35 6 8 9 10 MIN ns .. 1 n,s.., ' ! ',1 ' , ns .. ns ns' ns ns " ns , '" ' i ns , ns ns ns, ns ns ,M8102 IM6102-1M (Military) ABSOLUTE MAXIMUM RATINGS Operating Temperature Military IM6102-1M ........... -55°C to +125°C Storage Temperature ............ . -65° C to 150° C Operating Voltage ................ +4.0V to +7.0V Supply Voltage ......... :.................. +8.0V Voltage On Any InpLit or . Output Pin ................. .-0.3V to Vcc +0.3V NOTE: Stresses. above those listed under "Absolute Maximum Ratings" may cause permanent d('vice failure. These are stress ratings only and functional operation of the devices at these or any other conditions above those indicated if) the operation sections of. this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may cause device failures. D.C. CHARACTERISTICS TEST CONDITIONS: VCC = 5.0V ± 10%, CL = 50pF, TA = -55°C to +125°C SYMBOL PARAMETER 1 VIH 2 3 4 VIL Input Voltage High Input Voltage Low 5 ilL VOH VOL Input Leakagelll Output Voltage Highl21 Output Voltage Low 6 loL 7. 8 9 10 lee lee CIN Co CONDITIONS MIN GND,oVIN,oVee IOH; OmA IOL; OmA -1.0 2,4 Output Leakage 'GND,oVouT,oVee -1.0 Power Supply Current-Standby Power Supply Current-Dynamic Input Capacitancelll VIN-GND or Vee Ie; 2.5MHz MAX 0.8 1.0 7.0 8.0 UNITS V V J.lA V 0,45 V 1.0 J.lA J.lA mA pF 800 2.0 Output Capacitancelll NOTE: 1. Except pl.ns 15, 29, 31 TYP Vee -2.0 8.0 10.0' pF 2. Except pins 32, 33, 34. A.C. CHARACTERISTICS TEST CONDITIONS: VCC= 5.0V ± 10%, T A = -55° C to +125° C, fc = 2,5MHz MIN SYMBOL PARAMETER 1 tUN 2 tAIS LX MAR Pulse Width IN Address Setup Time IN: OX-LX MAR ,J, 3 4 tAIH tOEN Address Hold Time IN: LXMAR, J I-OX 5 teEN Controls Output Enable Time: DEVSEL, J I-lines CO,C1,C2,S/I 6 7 tOIS TOIH Data Input Setup Time: DX-DEVSEL,! 8 9 tRST RESET Input Pulse Width SKP/INTX to SKP/INT Propagation Delay 10 tOMLX 11 tOEM Enable/Disable Time from DMAGNT to EMA Lines 12 tMOR MEMSEL" Pulse Width READ 13 14 tMOW MEMSEL· Pulse Width WRITE tMOWR,. MEMSEL' Pulse Width WRITE/REFSH LXMAR· Pulse Width .- 80 '120 Data Output Enable Time: DEVSEL, J I-DX , DMA Control Signals Delay: XTC-XTC': MEMSEL-MEMSEL·, LXMAR-LXMAR· MAX ns ns 400 400 ns ns ns ns 500 , UNITS ns , 100 100 Data Input Hold Time: DEVSEL'! -DX tSID TYP 300 130 ns ns 130 ns 100 ns 750 950 550 ns ns ns 350 ns DMA READ Access Time: LXMAW, I'-UP. I· 750 ns tOXAS DX & EMA Address Setup Time Wrt LX MAR" , I· 18 tOXAH ns 19 tOREN tRUP OX & EMA Address Hold Time Wrt LXMAW. I· DMA READ Enable Time: MEMSEL' , I ,-UP, I' 120 175 550 350 ns ns 15 16 17 tLO' tORAT ns 21 towAT UP Pulse Width DMA READ DMA WRITE Access Time: LXMAW, I ,-MEMSEL·. I· 750 ns 22 towEN DMA WRITE Enable Time: UP ,j'.-MEMSEL·,! 550 ns 23 24 tMWS MEMSEL' Setup Time DMA WRITE MEMSEL',j ·-LXMAW,j· ns tOMS DMAEN Setup TimeWrt XTA ,I· 100 100 25 26 tOMH twup DMAEN Hold Time Wrt XTA ,I· 100 ns UP Pulse Width DMA WRITE 750 ns 20 ns -- IM6102 APPLICATION IM6100-IM6102 lolerface In a Buffered System. 'IM6100 IM6102 IM6100 DMAGNT(H) DX ----C IM610.0 CHL)'---.... ---------+@ IM6102 CHL)I--.... IM6100XTA(H)----L_~ I Vee IM6100 XTB(H) CD Q~------~L-~ D IM6100 XTC C R <D IM6100 SENDS ADDRESS/DATA TO MEMORY @ USER SENDS DATA TO MEMORY @ USER READS FROM MEMORY @ IM6102SENDS ADDRESS TO MEMORY. @ IM6102 SENDS DATA TO IM6100 <D IM6100 XTB ~,'-------- 1--'--::::""-0( IM6102 UP(L) IM6102 XTC* ...........l~----,.--- IM6102 MEMSEL*(L)
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