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XX-C3226-7A
May 2000
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IM6101
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XX-C3226-7A
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19
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http://bitsavers.org/pdf/dec/pdp8/cmos8/_dataSheets/IM6101.pdf
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IM6101 Programmable Interface Element (PIE) FEATURES. GENERAL DESCRIPTION .• Compatible with IM6100 Microprocessor -. Four Programmable OPERATE Control Lines for READIWRITE on Peripheral Devices The IM6101 is a Programmable Interface Element (PIE) device designed for interfacing various peripheral chips such as UART'si FIFO's, Keyboard Scanner's to IM6100Microprocessor. In this way, thelM6101 eliminates the need for additional external logic betwe'en 6100 JLP and its peripherals. • Four General Purpose FLAGS each of which Is Programmable . d~vices for READING or WRITING on the OX bus by •. Four Separate SENSE Input Lines to Sense ttie Status ofPerlp~eral Devices c . • Chained Vectored Priority Interrupt Structure Possible • Low Power: Less than 1mW @ SV • TTL Compatible at +SV The IM6101 provides the control signals to peripheral activating the WRITE CNTRL and READ CNTRL lines with lOT (Input Output Transfer) instructions. Each IM6101can sample.4 status lines from peripheral devices. It can also generate interrupt requests to the JLP if the corresponding individual interrupt enable bits inthe PIE are enabled and the respective status lines becom.e active. . . The four FLAG Ii nes may be set or reset under program control to send control information to the periphe.ral devices'or to send bi'lary data. . FUNCTIONAL BLOCK, DIAGRAM OXIO.111 • LXMAR DEVSE'L . [ TO ,IM6100 ADDRESS AND. SEt 13-7Q-ADDRESSING Cl PRIN} C2 POUT CONTROL LOGIC INTGNT XTC INT/SKP I ~~~~~~~N TOANO FROM OTHER PIE'S ORDERING INFORMATION ORDER CODE IM6IDI·1 IM61DIA IM61DI PLASTIC PKG .. IM6101·11PL IM6101·AIPL IM6101·IPL CERAMIC PKG. IM6101-1IDL IM6101·AIDL· -, MIlITARY TEMP. IM6101·1M~L IM6101·AMDL MILITARY TEMP. WITH 8838 IM6101·1 MDLl8838 'IM6101·AMDlI 883B - PACKAGE DIMENSIONS . TO PERIPHERAL DEVICES '\' . . 2.Q40(5U201 \', [:::::::::::::::::r~3'7'" PIN CpNFIGURATION . 0160 0025 0.'6351 r--++--"""-,-,,,,,-_ _. .;14,.,.0_64.;MAX,S=t' . .,1 ~':YP. PRIN WRITE~ SENSE 4 READ 2 SENSE 2 ·SENSE 1 READ,1 .C2 . WRITE 1 Cl FL,AG 1 lXMAR FLAG 3 iSEL 6 FL.AG 4 XTC tm7!n. SEt7 GND. DXO OXt1. OXt DX10 DX2 DX9 DX3 OXS ox. FIGURE 1. DXS ", 0.012 o.()(n(0.3051 (0.0251YP. : """""TV,,,,,,,,,,,,,r,,,,,,,,,,,".,,, ... C~ J '. .~~ I-, -II-, -I h 0"~,~:0641 .I--I,~~,-I ' 0.07011.778) 0.018 (0.4571 TYP. TYP. 0.02010.508) 0.100 . MAX. . (2.5401 40 P,iN PLASTIC DUAl·tN·LINE ~ACKAGE IPl) , . 13 . 2:02~:~:3081' 'r I:. [::::::D::::::r~~I' 0.050 (1.2701 ~(1~~~i.J SQUARE 0.165 ,14.1911 0.020 (5.0801 . T~~~Lroo~' jh 0.050 (1.2101 to.Ol0 (0.254) -I\-, . -I h t o.'25 1--110;~,-I g:~:g:~: 0.01810.457) 0.100 (2.5401 (3.1761 REF. to.D02 (0.051) ~O.O.10 (0.254) . MIN. 40 PIN CERAMIC DUAL-iN-LINE PACKAGE IDLI NOTE: DIMENSIONS IN PARENTHESIS ARE METRIC IM6101 IM6101 FUNCTIONAL DESCRIPTION Pin Number Symbol 1 Vee 2 INTGNT Input! Oulput Description +5 volts I A high level on INTERRUPT GRANT inhibits recognition of new interrupt requests and allows the priority chain time to uniquely specify a PIE. 3 PRIN I A high level ON PRIORITY IN and an interrupt request will select a PIE for vectored interrupt. 4 SENSE 4 I The SENSE input is controlled by the SL Isense level I and SP Isense polarityl bits of control register B. A high SL level will cause the SKIP flip flop to be set by a level while a low SL level causes sense and interrupt flip flops to be set by an edge. A high SP level will cause the sense flip flop to set by a positive going edge or high level. A high IE (interrupt enable I level generates an interrupt request whenever the INT flip flop is set (by ar edge!. 5 SENSE 3 See pin 4 - SENSE 4 6 SENSE 2 See pin 4 - SENSE 4 7 SENSE 1 See'pin 4 - SENSE 4 8 SEL 3 Matching SELECTI3-71 inputs with PIE addressing on DX13-71 during IOTA selects a PIE for programmed input output transfers. 9 SEL 4 See pin 8 - 10 LXMAR A positive pulse on LOAD EXTERNAL ADDRESS REGISTER loads address and ccntrol data from DX13-111 into the address register. 11 SEL 5 See Pin 8 - SEL 3 SEL 6 See Pin 8 - SEL 3 13 'XTC The XTC input is a timing signal produced by t~e microprocessor. When XTC is high a low going pulse on DEVSEL initiates a "read" operation. When XTC is low, a low going pulse on DEVSEL initiates a "write" operation. SEL 7 I 15 DX 0 1/0 Inputl Output DX 9 DX 10 See Pin )5 - 1/0. See Pin 15- DX 0 26 DX 11 1/0 See Pin 15 - 27 GND 28 DEVSEL 29 FLAG 4 o The FLAG outputs reflect the data stored in control register A. Flags 11-41 can be set or reset by changing data in CRA via a WRA Iwrite control register AI command. FLAG 1 and FLAG3 can be controlled directly by PIE commands SFLAG1, CFLAG1, SFLAG3 and CFLAG3. 30 FLAG 3 FLAG 4 FLAG 2 See Pin 29 - FLAG 4 32 FLAG 1 o o o o See Pin 29 - 31 See Pin 29 - FLAG 4 24 25 33 The DEVSEL input is a timing signal produced by the microprocessor during lOT instructions. It is used by the PI E to generate timing for controlling PI E registers and "read" and "write" operations. 1/0 See Pin 15 - DX 2 1/0 SeePin15-DXO 18 DX 3 1/0 See Pin 15 - DX 0 19 DX 4 1/0 See Pin 15 - DX 0 20 DX 5 1/0 See Pin 15 - DX 0 21 DX 6 1/0 See Pin 15 - DX 0 22 DX 7 1/0 See Pin 15 - DX 0 23 DX 8 1/0 See Pin 15 - DX 0 The PI E decodes address, control and priority information and asserts outputs C1 and C2 during the IOTA cycle to control the type of data transfer. These outputs are open drain for bussing and require pullup resistors to 34 C2 o See Pin 33 - 35 READI o Outputs READ1 and READ2 are used. to gate data' from peripheral devices onto the DX bus for input tothe IM6100. Note the data does not pass through the PIE. 36 WRITEI o Outputs WRITEI and WRITE2 are used to gate data from the IM6100 DX bus into peripheral devices. Data does not pass through .the PIE. READ2 o o o 38 DX 1 DXO C1 Ill, C21L1- vectored interrupt C11L1, C21HI - READ1, READ3 or RRA commands C1IHI, C21HI - all other instructions Data transfers between the microprocessor and PIE take place via these input/output pins. 16 DX 0 Vee. 37 17 Description 1/0 SEL 3 See Pin 8 - Symbol SEL 3 12 14 Pin Number 39 WRITE2 SKPIINT DX 0 40 POUT o C1 See Pin 35 - READ1 See Pin 36 - WRITE1 The PIE asserts this line low to generate interrupt requests and to signal the IM6100 when sense flip flops are set during SKIP instructions. This output is open drain. A high level on priority out indicates no higher priority PIE interrupt requests are outstanding. This output is tied to the PRIN input of. the next lower priority PIE in the chain. IM6101 TIMING DIAGRAM Timing for a typical lOT transfer is shown in Figure 2. During the IFETCH cycle, the processor obtains from memory an lOT instruction of the form6XXX. During the IOTA the processor places that instruction back on the OX lines@). and pulses LXMAR transferring address and control information for the I OTtransfer to all peripheral devices. A low going pulse on DEVSEL while XTC is high @is used by the addressed PIE alonLwi~ecoded control information to generate C1, C2, SKP and controls for data transfers to the processor. Control outputs READ1 and READ2 are used to gate perfpheral data to the OX lines during this . time. A low going pulse on DEVSEL while XTC is low ® is used to generate WRITE1 and WRITE2 controls. These signals., are used to clock processor accumulator data into peripheral devices. I---------------~ lOT INSTRUCTlON-~~---· XTC J LXMARJ\_ \\-___...Jr- \\-___--1 \\-_--J1 '-----_ _-n-ILXMAA ~ .. ---~ 1l READ (NEGATIVE POLARITY) WRITE WAtTE ~-------------~--~~----r. CFLAG SFLAG --~-----------+~ tOF· -- ----- ---:-----------t-+--+-----'--~ _____________ FLAG (VIA WCAA COMMAND) ----------------------------- J~-------------- -101 SKP7iNT INTERRUPT DATA INTERRUPT DATA -~-~--~----4J Sense FF's are sampled when LXMAR 'Is high by ~he PIE OX data, CO, C1, C2 and ~KP are read by Ihe IM6100 on the rising edge ot'T3 Interrupts are sampled by the IM61Da on the rising edge of T2 of execution cycle FIGURE 2. IM6101 PIE Timing Diagram. All PIE timing is generated from IM6100signais LXMAR, DEVSEL, and XTC. No additional timing signals, clocks, or one shots are required. Propagation delays, pulse width, data setup and hold times are specified for direct interfacing with the IM6100. IM6101 PIE ADDRESS AND INSTRUCTIONS The IM6100 communicates with the PIE and with peripherals through the PIE via lOT. commands. During the IOTA cycle (See Figure 1) an instruction of the form 6XXX is loaded into all PIE instruction registers. The.bits are interpreted as shown below., .,. 3 4' ADDRESS The 5 address bits (3-7) are compared with the select inputs SEL3, SEL4, SEL5, SEL6, SEL7 to address 1 of 31 possible PIE's. Address zero is reserved for lOT's internal to the IM6100. The four control bits are decoded to select one of 16 instructions. Note also that the lOT instructions 66XX are reserved for the Parallel Input/Output Port (P10 - IM61031. 9 '0 " CONTROL FIGURE 3. PIE; Instruction Format. DESCRIPTION CONTROL MNEMONICS 0000 READ1 1000 0001 READ2 WRITE1 1001 0010 0011 1010 1011 WRITE2 SKIP1 SKIP2 SKIP3 SKIP4 .' 0100 RCRA 0101' 1101 1100 ' WCRA WCRB WVR 0110 SFLAG1 1110 0111, 1111 (6007)8 SFLAG3 CFLAG1 CFLAG3 CAF The READ instructions generate a pulse on the appropriate read outputs. This signal is used by the peripheral device to 9.ate data onto the DX bus to be~'OR'ed" with the IM6100 accumulator data. The WRITE instructions generate a pulse on the appropriate write ou~put. This signal is used by peripherals to load the IM6100 accumulator data.on the DX lines. into peripheral data registers. The SKIP instructions test the state of the sense flip flops. Ifthe input conditions have set the sense flip flop, the PIE will assert the SKP/INT output causing thelM6100to skip the next program instruction. The sense flip flop is then cleared. If the sense flip flop is not set, the PIE does not assert the SKP/INToutput and the IM6100 will execute the. next instruction. The Read con@1 Register A instruction gates the contents of CRA onto the DX lines during time 4 to be "OR" transferred to the IM6100 AC. (S.ee Figure 2) . The Write Control Register A, Write Control Register B and Write Vector Register instructionstransferlM6100 AC data on the DXlines during time of IOTA into the appropriate regi~ter. (See Figure 2) Bits 10,110fthe VR;5, 7 of CRA; 8-11 of CRB are don't care bits for these instructions.' . . The SET FLAG instructions set the bitsFL 1. and FL3 in control register A to ahigh level. PIE outputs FLAG1 and FLAG3 follow the data stored in bits FL1 and FL3 of CRA. The CLEAR FLAG instructions clear the bits FL1 and FL3 in control register A to a low level. IM6100 internal lOT instruction CLEAR ALL FLAGS clears the interrupt requests by clearing the sense flip flops. It has no effect on control register output flags FL 1, FL2, FL3, FL4. To clear these output flags, bits 0-3 of CRA must be. cleared usi ng WCRA with bits 0-3 of ACcleared. ® / PRIORITY FOR VECtORED INTERRUPT A hardware priority network uniquely selects a PIE to provide a vectored address. The first lOT command of any type, after the IM6100 signal INTERRUPT GRANT goes high, resets the line INTGNT to a low level. The signal INTGNT is used to freeze the priority network and enable vector generation. Within a given PIE, the internal priority is interrogated during every LXMAR. The highest priority PIE has 'PRIN tied to Vee. The lowest priority PIE is the last one on the chain .. The vector address generated by the PIE consists of 10 bits from the vector register and two bits that indicate the sense input within the highest priority PIE that generated the interrupt. IM6101 A. Daisy-chaining of several PIE chips, o 3 I, B, Interrupt Vector Register Format. 4 10 9 INTERRUPT VECTOR 11 SPRI: Sense Priority SPRI SPRI Conditions' 00 01 10 11 SENSE1 SENSE2 and not SENSE1 SENSE3 and not ISENSE2 or SENSE11 SENSE4 and not ISENSE3, or SENSE2 or SENSE11 , , • All sense mput IIt:1es are enabled for mterrupts, FIGURE 4. IM6101 Priority for,Vectored Interrupt. I/O CONTROL.l.,INES (C1 ANDC2) The type of input-output transfer is controlled by the , selected PIE by activating the Cl, C2 lines as shown, below. These outputs are open drain. C1 C2 H L L , , H DEVIPIE- AC Write H AC ;... AC + DEV/PIE ~'OR'!Read L PC - VECTOR ADDRESS Vectored Interrupt INTERRUPT/SKIP (INT/SKP) Interrupt anc;:lskip info~mation are time multiplexed on the same .lines. Since the IMS,100 samples skip and, interrupt data at separate times (see Figure '1) there is no degradation in sY,stem performance. The PIE, samples the sense flip flops and g~nerates an interrupt request for enabled bits on the rising edge of LXMAR. Interrupt requests are asserted by driving the INT/SKP line low; During' IOTA of SKIP instructions the INT/SKP reflects the SENSE flip flop data., o 2 If the SENSE flip flop is set, the INT/SKP line is driven low to cause thelMS100 to skip the next instruction. This output is open drain. , CONTROL REGISTER A (CRA) , TheCRA can be read ,and written by the IMS'mO via the'RCRA and WCRA commarids. The format and meaning of control :bits are shown below. 6 7, '8 9 10 11 IFL41FL3IFL2IFL1IWP21 ·IWP11·, IIE+E31IE21IEll * Don't care tor WCRA, 0 tor RCRA FIGURE 5. Format for Control Register A. FL(1-4) IE(1-4) Data on FLAG outputs corresponds to data in FL d -4l. Changing theFL bits in CRA changes the correspond-' ing FLAG output. A high level 'on W~(1,2)'" A highlEivel on WRITE POLARiTY bits causes positive pulses at the WRITE outputs (see Figure 1>. ' inter~upts. INTERRUPT ENABLE enables IM6101 CONTROL REGISTER B The CRB can be written by the IM6100 via the WCRB instruction. It has no read back capability. The format and meaning of control bits are shown below. Bits 8-11 are don't care bits. !SL4! SL3! SL2! SL1! SP41 SP3! SP2! SP1! For the Interrupt flip flop to be set, the corresponding interrupt enable bit must be set to 'one'. If the sense input is program'med to be edge sensitive, the flip flop is set when the edge occurs. If it was initially programmed to be level sensitive and then the mode is changed to be edge sensitive, the flip flop will b'e set if the polarity of sense input line corresponds to its SP bit. All conditionS that set the Interrupt flip flop also setthe associated Skip flip flop. In addition, the Skip flip'flop is set when the polarityof the sense input corresponds to its SP bit in the level sensitive mode. . FIGURE 6. Format for Control Register B. SL{1-4) A high level on the SENSE LEVEL bits causes the'SENSE inputs to be level sensitive. A low level on the SL bits causes the SENSE inputs to be' edge. sensitive. The INT FFs are set only if a sense line is set up to be edge sensitive. ' The Skip flip flop is cleared at IOTA READ time by executing a CAF (6007) instruction or' a SKI P instruction on the associated sense inputthat actually skips, In the level sensitive mode, whenever the polarity of sense input does r10t correspond to its SP bit, the sense FF is cleared: The Interrupt flip flop is cleared whenever the sense flip flop is cleared. In addition, it is cleared if the associated sense logic actually creates a vector, the interrupt enable.bit is cleared to a 'zero' or the sense input is programmed to be level sensitive. Detailed operation of resetting Interrupt and Skip flop flops are as shown in Figure 7. SP{1-4) A high level on the SENSE POLARITY bits causes the SKIP flip flop to be set by a high level or positive going edge. A low level causes the SKIP flip flop to be set by a low level or negative going edge. PERIPHERAL INTERFACE LINES SENSE{1-4) The I M61 01 has two latches associated with each sense input.,- a SKIP flip flop and an INTERRUPT flip flop. D Q D INT F/F "'~E,NAC riVE EDGE C '" 1 WHEN ACT IVE LEVEL IS TR UE SL -C '0 INTREQ'" L WHEN ACTIVE EDGE OCCURS 0 SKP = L WHEN ACTIVE EDGE R I -=0 -~ S '--- D Q D SKIP F/F -c f--C R RESET ,LXMAR SKP FF ILl RESET SKP FFi '" CA F + SKP ON i + 1St'" 1) (ACTIVE LEVEL IS FALSE) REseT INT FF (Ll RESET INT FFi '" C~F + SKP ON i + (St '" 1) + VECTOR ON i Figure 7. IM6101 SKIP Flip Flop and INTERRUPT Flip Flop Input'Diagram. IM6101 IM6101A ABSOLUTE MAXIMUM'RATINGS Operating Temperature . IndustriallM6101A .............. -40°C to +85°C Storage Temperature. . . . . . . . . . .. -65° C to 150° C Operating Voltage .................. 4.0V to 11.0V Supply Voltage ........................... +12.0V Voltage On Any Input or Output Pin .................. -0.3V to Vee +0.3V NOTE: Stresses above those listed under '''Absolute Maximum Ratings" may cause permanent device failure. These are stress ratings only and functional operation of the devices at these or any other condition's above those indicated in the operation sections of this specification is not implied. Exposure to absolu.te maximum rating conditions for extended periods may cause device failures. D.C. CHARACTERISTICS TEST CONDITIONS: Vee = 10V ± 5%, TA = -40° C to +85° C , SYMBOL PARAMETER CONDITIONS 1 VIH Input Voltage High 2 VIL Input Voltage Low 3 IlL Input Leakage GND::;VIN::;Vee 4 VOH Output Voltage High 10H = OinA 5 VOL Output Voltage Low IOL = OmA 6 10L Output Leakage . GND::;VouT::;Vee 7 Icc Power Supply Current-Standby Vee~lOV±5% 8 Icc Power Supply Current-Dynamic Vee=10V±5% f=571 kHz 9 CIN 10 Co MIN TYP MAX UNITS V 70% Vee -1.0 20% Vee V 1.0 p.A Vee~O.D1 V GND+O.Ol V 1.0 p.A 1.0 500 p,A 2.0 mA Input Capacitance 7.0 8.0 pF Output Capacitance 8.0 10.0 pF TYP MAX UNITS 150 ns 150 ns -1.0 A.C. CHARACTERISTICS TEST CONDITIONS: Vee = 10V ±5%, TA == -40°C to +85°C, CL = 50pF SYMBOL PARAMETER MIN tDR Delay from DEVSEL to READ 2 iDW Delay from DEVSEL to WRITE 3 tDF Delay from DEVSEL to FLAG 200 ns 4 tDe Delay from DEVSEL to Cl, C2 215 ns 5 tDI Delay from DEVSEL to SKP/INT 215 ns 6 tDA Delay from DEVSEL to OX 215 ns 7 tLxMAR LXMAR Pulse Width 120 ns 8 tAS Address Setup Time 40 ns 9 tAH Address Hold Time 50 ns 10 tDS Data Setup Time 65 ns 11 tDH Data Hold Time 50 ns 1 Note: See Figure 2 for an A.~. Timing Diagram . 50 IM6i01 IM6101-11 ABSOLUTE MAXIMUM RATINGS Operating Temperature IndustriallM6101-11 ............ -40°C to +85°C Storage Temperature ............ -65° C to 150° C Operating Voltage ................... 4.0V to 7.0V Supply Voltage ,................ , . . . . . . . . . .. +8.0V Voltage On Any Input or Output Pin .................. -0.3V to Vee +0.3V NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent device failure. These are stress ratings only and functional operation of the devices at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may cause device failures. / D.C. CHARACTERISTICS TEST CONDITIONS: Vee = 5V ± 10%, TA =-40°C to +85°C SYMBOL PARAMETER 1 VIH Input Voltage High 2 Vil Input Voltage Low CONDITIONS MIN TYP MAX UNITS 0.8 V 1.0 I'A 0.45 V Vcc-2.0 3 III Input Leakage GNDSVINSVCC -1.0 4 VOH Output Voltage High 10H = -0.2mA 2.4 5 VOL Output Voltage Low 10l = 2.0mA V V -1.0 6 10l Output Leakage GNDSVOUTSVCC 7 Icc Power Supply Current-Standby Vce = 5V ± 10% 8 Icc Power Supply Current-Dynamic Vee=5V±10% f=330 kHz 9 CIN Input Capacitance 7.0 8.0 pF; Output Capacitance 8.0 10.0 pF TYP MAX. UNITS 300 ns 300 ns 10 Co 1.0 1.0 I'A 100 I'A 500 I'A A.C. CHARACTERISTICS TEST CONDITIONS: Vee = 5V ± 10%, TA = -40°C to +85°C, CL = 50pF SYMBOL PARAMETER MIN 1 tOR Delay from DEVSEL to READ 2 tow Delay from DEVSEL to WRITE 3 tOF Delay from DEVSEL to FLAG 375 ns 4 toe Delay from DEVSEL to C1, C2 460 ns 5 tOI Delay from DEVSEL to SKP/INT 460 ns 460 ns 6 100 tOA Delay from DEVSELto DX 7 tlXMAR LXMAR Pulse Width 240 ns 8 tAS Address Setup Time 80 ns 9 tAH Address Hold Time .125 ns 10 tos Data Setup Time 80 ns 11 tOH Data Hold Time 100 ns Note: See Figure 2 for an A.e. Timing Diagram. IM6101 IM6101AM ABSOLUTE MAXIMUM RATINGS Operating Temperature Military IM6101AM ............. -55°C to +125°C Storage Temperature ............ -65°C to 150° C Operating Voltage .................. 4.0V to 11.0V Supply Voltage ........................... +12,OV Voltage On Any Input or Output Pin .................. -O.3V to Vee +O.3V NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent device failure. These are stress ratings only and functional operation of thedevicesat these or any other, conditions above those indicated ih the operation sections of this specification is not implied, Exposure to absolute maximum rating conditions for extended periods may cause device failures. D.C. CHARACTERISTICS TEST CONDITIONS: Vee = 10V ± 5%, TA = -55°C to +125°C SYMBOL PARAMETER 1 VIH Input Voltage High 2 VIL Input Voltage Low 3 IlL Input Leakage 4 CONDITIONS MIN TYP MAX 70% Vee GND::;VIN::;Vee VOH Output Voltage High IOH = OmA 5 VOL Output Voltage Low IOL = OmA 6 IOL Output Leakage GND::;Vour::;Vee UNITS V -1.0 20% Vee V 1.0 p.A V Vee-Om -1.0 GND+0.01 V 1.0 p.A 500 p.A 7 lee Power Supply Current-Standby Vee=10V±5% 8 lee Power Supply Current-Dynamic Vee=10V±5% f=571 kHz 2.0 rnA 9 CIN Input Capacitance 7.0 8.0 pF Output Capacitance 8.0 10.0 pF TYP MAX UNITS 10 Co 1.0 A.C. CHARACTERISTICS TEST CONDITIONS: Vee = 10V ± 5%, TA = -55°C to +125°C, CL = 50pF SYMBOL PARAMETER 1 tOR Delay from DEVSEL to READ 2 tow Delay from DEVSEL to WRITE 3 tOF 4 toe 5 MIN 165 ns 165 ns Delay from DEVSEL to FLAG 220 ns Delay from DEVSEL to C1. C2 240 ns tOI Delay from DEVSEL to SKP/INT 240 ns 6 tOA Delay from DEVSEL to DX 240 ns 7 tLxMAR LXMAR Pulse Width 135 ns 8 tAS Address Setup Time 45 ns 50 9 tAH Address Hold Time 55 ns 10 tos Data Setup Time 70 ns 11 tOH Data Hold Time 55 ns Note: See'Figure 2 for an A.C. Timing Diagram. IM6101 IM6101-1M ABSOLUTE MAXIMUM RATINGS Operating Temperature Military IM6101..:IM ............ -55°C to +125°C Storage Temperature ............ -65°C to 150°C Operating Voltage ................... 4.0V to 7.0V Supply Voltage ........................... +8.0V VoltageOn Any Input or Output Pin .................. -0.3V to Vee +0.3V NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent device failure. These are stress ratings only and functional operation of the devicesat these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may cause device failures. D.C. CHARACTERISTICS TEST CONDITIONS- Vee = 5V + - 10% , TA - -55°C to +125°C SYMBOL PARAMETER CONDITIONS MIN 1 VIH Input Voltage High 2 VIL Input Voltage Low 3 Input Leakage GNDSVINSVee -1.0 2.4 ilL 4 VOH Output Voltage High 10H = -0.2mA 5 VOL Output Voltage Low 10L= 2.0mA 6 10L Output Leakage GNDSVOUTSVee 7 Icc Power Supply Current-Standby Vee = 5V ± 10% 8 Power Supply Current,-:-Dynamic Vee=5V±10% f=330 kHz Icc. TYP MAX Vee-2.0 UNITS V 0.8 V 1.0 p.A V -1.0 1.0 0.45 V 1.0 p.A 100 p.A 500 p.A 9 CIN Input Capacitance 7.0 8.0 pF 10 Co Output Capacitance 8.0 10.0 pF TYP MAX UNITS A.C. CHARACTERISTICS TEST CONDITIONS: Vee = 5V + - 10%, TA = -55°C to +125°C CL = 50pF SYMBOL PARAMETER 1 tOR 2 tow Delay from DEVSEL to WRITE \, MIN Delay from DEVSEL to READ 100 330 ns 330 ns 3 tOF Delay from DEVSEL to FLAG 415 ns 4 toe Delay from DEVSEL to C1, C2 510 ns 5 tOI Delay from DEVSEL to SKP/INT 510 ns 6 tOA Delay from DEVSEL to DX 510 ns 7 tLXMAR LXMAR Pulse Width 265 ns 8 tAS Address Setup Time 90 ns 9 tAH Address Hold Time 140 ns 10 tos Data Setup Time 80 ns 11 tOH Data Hold Time 110 ns Note: See Figure 2 for an A.e. Timing Diagram. , IM6101 APPLICATION INTRODUCTION The IM6101, Programmable Interface Element (PIE), provides a universal means of interfacing industry standard LSI devices and peripheral equipment controllers to the IM6100 Microprocessor. The IM6100 configures each PIE for a specific interface during system initialization by programming the control registers within the PIE for write enable polarities, sense polarities, sense edges or levels, flag values and interrupt enables. On power-up, the. registers will contain random bit patterns. The data transfer between the IM6100 and the peripheral devices does not take pla'ce through the PIE. The programmable Interface Element provides the steering signals. for data transfers. This approach was chosen since all the standard LSI elements such as Keyboard chips, UARTs, FIFOs, etc. have internal storage latches and they require only control signals to take data from the bus or to put data on the bus. If some user defined peripheral interfaces do not have these built-in storage elements, discrete CMOS or low powe(Schottkylatches, or flip-flops, must be provided to store the data from the IM6100 until the peripheral device is ready to accept itand to latch data from the peripheral devices until the IM6100 asks for it. INTERRUPT PROCESSING WITH PIE'S The PIEs provide for a vectored priority interrupt scheme. Up to 31 PIEs may be chained t6 obtain 124 interrupt lines. The microprocessor' will recognize, identify and start servicing the highest priority interrupt request within 36.61-'s at 3.3MHz. The INTREQ iines from all PIEs are wire-ANOed together. A PIE ge~erates an interrupt request, if anyone of its four sense lines, which are interrupt enabled, become active by driving the INTREQ line to the IM6100 low. If no higher priority 'requests are outstanding (RESET, CPREQ, HL T or OMAREQ), the IM6100 will grant the request at the end of the current instruction. The content of the Program Counter is deposited in location OOOOs of the memory and the program fetches the next instruCtion from location 0001s. The return address is hence available in location OOOOs. This address must be saved in a software stack if nested interrupts are allowed. The IM6100 activates the INTGNT signal high when an INTREQ is acknowledged. The INTGNT is reset by executing any lOT instruction. The PIEs use the INTGNT signal to freeze the priority network and to uniquely specify the PI E with the highest priority interrupt request. The PIE with the highest priority request sends a unique vector address to the IM6100 when the processor executes the first lOT instruction after the INTGNT. The Interrupt" Protolyping System uses .the lOT instruction VECT (60471 for Vectoring. The 12-bit vector add ress generated by the PI E consists of 10 high order bits from the vector register, defined by the user during system initialization, and two low order bits which indicate the sense input that generated the interrupt. Therefore, if the instruction in location 0001s is . VECT-6047s, the processor will branch to 1 of410cations, depending on which of the sense lines within a PIE generated the request. Each one of these locations must contain a Jump instruction pOinting to the specific service routine for the corresponding sense input. The 36.61-'s interrupt acknowledge time at 3.3 MHz consists of 17l-'s (max) to recognize an interrupt request, 3.61-'s to grant an interrupt request, 10l-'s to execute the VECT for vectoring and 6.01-'s to execute a Jump instruction to a specific service ·routine. . Proper vectoring requires· the following conditions: 1. The IM6100 must be enabled for interrupts with the ION command, 2. The INTGNT output of the IM6100 must be connected to the INTGNT of all the PIEs and the PRIN olthe PIE with the highest priority must be connected to VCC and its PROUT should be connected to the PR IN of the PIE with the next highest priority and so on. 3. The IE bit of the sense line that is expected to generate the interrupt must be set t01. 4. The sense line must be programmed to be edge' sensitive. If a sense line is programmed to be level sensitive, it will not generate an INTREQ nor will it generate a vector. 5. The vector register of the PIE must be initialized with the proper vector. Note that the two least significant bits are generated by the PIE itself. 6. The C1 and C2 lines of all the PIEs must be wired together with the C1 and C2 of the IM6100 and pull up resistors must be provided on these lines since thePIE C1 and C2 outputs are open drain. TheSKP/lNT line of the PIE must be wired with the INTand SKP lines of the IM6100. If the PIE OX lines are buffered, the external bus must be enabled 'onto the PIE OX with the XTB being active high and the PIE OX bus must be enabled onto the external bus when the C1line of a PIE is active low (during RCRA, REA01, REA02 or vectorl. 7. The vector address will be generated with the first lOT· of anykind after the INTGNT., 8. Notealso that a successful skip on a sense line will reset an interrupt request by the sense line, il any. One should not thus turn on· the interrupt system after a 15uccessful skip on a sense line expecting that the sense line that was just tested will generate a request. SKIP HANDLING WITH PIE'S Each PIE provides for four SENSE lines. The active state of the SENSE inputs can be programmed to be a low level, high level, positive edge or negative edge. There is a SENSE FF in the PIE associated with each SENSE line. This FF is set when the SENSE line is "active" The state of the SENSE FF can be tested by the SKP comman9s, When the IM6100 executes a SKIP in. struclion, it will skip the next sequential instruction if the SENSE FFi is set. lithe skip is successful, the FF will be cleared. If the sense line was set up to be edge sensitive, it can, therefore, be tested for the 'set' state only once. If the FF is set by a level, it will be cleared by the successful skipand then, set immediately by the active level. IM6101 If the SENSE FF was set by an edge, and the respective IE bit is enabled: the PIE will generate an INTREQ to the IM6100. Provided the priority conditions are met, the PIE will supply the vector address to the IM6100 when it executes the first lOT instruction of any kind, after the INT.REQ has been granted. If the vector address is generated by FFi, one may still skip once on sense line i. It should be noted that if priority vectoring is inhibited by grounding PRIN, !in INTREQ will be cleared only if SKIPi instruction is executed to test the FFi that generated the req·uest. Note also that an INTREQ will not be , gerierated if the sense line was set up to be level sensitive. In certain instances, one may be interested in restoring the set state of a SENSE FF after it has been successfully tested and cleared and if the SENSE line has been programmed to' be edge sensitive. For example, assume that SENSE1 is programmed to be positive edge sensitive (SL1 = D, SP1 = 11. The transition from a 0 to 1occurred; SENSE FF1 is set; SENSE1, is at a 1 level. SKIP1 instruction will clear SENSE FF1. The SENSE 'FF1 can be set, under program control, by creating an internal edge. This 'is accomplished, in this specific instance,by programming SP1 to a 0 and then back to a 1. Since SP1 is in CRB and it cannot be read from the' PIE, the CRB constant must be stored in user memory, for example, location KCRB. a CLA TAD KCRB AND K7740 WCRB TAD K0020 WCRB KCRB, CRB K7740, 7740 K0020, 0020 IGet CRB constant ISP1 = 0 IWrite CRB to clear SP1 ISP1 = 1 ' IWrite CRB to set SP1 ICRB constant Software systems employing Skip's on a Sense input while allowing the same input to, create an Interrupt should pay 'attention to the fact tliat the Skip and Interrupt flip flops are synchronized by LXMAR from the IM6100. Since there is no LXMAR during 10TB of an 1/0 instruction: the following can occur. Assume that the following two instruction sequence is used: SKIP SENSEX JMP-1 ISENSE F/F SET? INO: WAIT FOR IT, Where SENqEX is also Interupt enabled. Now, assume that the appropriate 'Edge' occurs during the fetch state of the ~kip instruction. The Edge causes both flip flops to be set and the LXMAR produced at IOTA time creates an Interrupt request., The ,Skip, instruction execution causes a Skip and clears the Skip flop flop. However, the Interrupt flip flop will not reflect the fact that the Skip flip flop has been cleared .until after the next LXMAR occurs. So, the Interrupt request. remains active during 10TB time since ,the 10TB cycle does not have a LXMAR. The IM6100 honors the Interrupt request since the next LXMAR doesn't occur until after the lOT is finished. The Interrupt servicing routine will not Skip again if iUries to find the device that created the Interrupt. .Note that the proper Vector Address will still be generated. , PIE INSTRUCTION FORMAT The IM6100 communicates with the PIEs using the InputOutput Transfer IIOTI instructions.,The firstthree bits, 02, are always set to 68 11101 to specify an lOT instruction. The standard PDP-8/E'·, convention is to set the next 6 bits, 3-8, to specify 1 of 64 1/0 devices and then to control the operation of the selected I/O device by using bits 9-11. However, the PDP-8/E interfaces are not standardized si nce a specific pattern of bits 9-11 could specify' completely different operations in different 1/0 devices. For example, the pattern 000 in bits 9-11 could mean a read operation for Interface A, a write operation for Interface B, a skip instruction for Interface C and so on since the operation for any lOT instruction depends entirely upon the circuitry designed into the 1/0 device interface. The lOT instruction format for the PIE is different from that used by PDP~8/E"; interfaces'. The first three bits are., as usual, set to 68 to indicate an lOT instru·ction. The next'5 b,its, 3-7, specify 1 of 31 PIEs and !hen the operation of the selected PIE is controlled by bits 8-11 in 16 uniquely specified ways. For example, the specific pattern 0000 in bits 8-11 'means exactly the same operation for all PIEs, namely activate' READ1 line. Of the 32 possible combinations of bits 3-7, the pattern 00000 is reserved for internal Processor iOT instructions a'nd hence not available as a PIE address .. ' Recommended address aSSignments for the IM6101-PIE (Programmaple Interface Elementi are as follows: , 000 00 Internal lOT 1600XI and DEC HS RDR 1601XI 000 01 DEC HS PUNCH 1602XI and DEC TTY Keyboard 1603XI DEC TTY PRINTER (604XI 000 10 INTERCEPT PIE-UART Serial Interface, 000 11 INTERCEPT PIE-UART PRINTER Interface 001 00 IM6102 c MEDIC REAL TIME CLOCK 001 01 001 10 ' Reserved for Intercept Option - 1 001 11 Reserve,d for Intercept Option - 2 IM6102-MEDIC EMCIDMA ' 010 00 010 01 IM6102-MEDIC EMC/DMA 010 10 IM6102-MEDIC EMC/DMA 010 11 IM6102c MEDIC EMC/DMA 011 00 IM6103-P10 011 01 IN6103-P10 IN6103-P10 ' 011 10 IN6103-P10 01,1 11' USER 100 00 USER 100 01 USER 100 10 100 11 USER 101 00 USER 101 01 USER 101 10 USER 101 11 USER 1,10 00 USER 110 01 ,USER 110 10 L,JSER 110 11 USER 111 00 Reserved for Intercept Option, - 5 111 01 Reserved for Intercept Option - 4 111 10 Intercept FLOPPY DISK System 1675XI 111 11 Reserved for Intercept Option - 3 D~DIL IM6101 PARAMETER DEFINITION Minimum Peripheral device write data setup time w.r.t. leading edge of WRITE twpo (lM6100) + tOW·(MIN) (lM6101) - toso (IM6100) Minimum Peripheral device write data hole ti(Tle w;r.t.·leadlng.edge of WRITE tOHO (IM6100)-t twpo .rIM6100) - tow (MAX) (lM6101) Maximum' Peripheral device read data enable 'time tEND (lM6100) - t,oR (IM6101) proc~ssor. The IM6403 makes provisions for a' crystal osCillator and internal divider chain to specify the data transfer rate. In the IM6402' the data transfer rate ,is controlled by an ,external timing source, for example, a . Baud Generator. A funCtional block diagram of .the PIE/UART/Ity16100 interface is shown below. The UART is configured, in this' specific example, to interface with an ASR-33 Teletype which has a data format that consists of 11 bits - a start bit; 8 data bits and 2 stop bits. The UART is clocked at 16X ttie data rate. For the 10 character per second ASR-33, the UART clock frequency would be 1.76 KHz. An 8-bit data word from the IM6100. Accumulator is loaded. into the, Transmitter Buffer Register via inputs TBR8-TBR1 when the Transmit Buffer Register Load (rBRU signal makes a zero to one transition. A high level on Transmit Buffer Register Empty (TBRE) indicates that the buffer is ready to accept a new character for transmission. The microprocessor checks the status of TBRE via SENSE;2 before it transmits a new character to .the UART by pulsing WRITE1. The start bit, data bits and stop bits appear serially at the Transmit Register Output (TRO)' A serial data stream on the Receiver Register Input (RRD is clocked into ihe Recei.ve Buffer Register. A'!1igh level on Data Received'(DR) indicates that a character has been received. Th~ contents of Receiver Buffer Register appear on the outputs RBR8-RBR1 when a low level is applied to Receiver Register Di.sable <HRD) input. The RBR outputs are tristated when RRD is high. A low level on Data Received Reset (DRR) clears the DR flag. RRD and DRR ·TIMING REQUIREMENTS ON PERIPHERAL DEVICES The timing required on peripheral devices is affected by the combined delays of the IM6100 and IM6101 devices. The table above describes 'thepe,ripheral device. timing requirements with respect to the data given forthe IM6100 and IM6101AC characteristics. The values at any operating frequency, temperature and/o~ power supply voltage can be evaluated by substituting the calculated values for the IM6100 and IM6101 parameters in the defining expressions. ASYNCHRONOUS SERIAL INTERFACE WITH PIE AND UART The IM6402/03 Universal Asy~chrorious Recei~erl Transmitter is a general, .purpose programmable serial device for interfacing' an asynchronous serial data channel to a parallel synchronous data channel. The receiver converts a serial word with siart, data, parity and stop bits to a 'paralfel data word and checks for parity, framing and' data overrun errors: The transmitter section converts a parallel data wordiilto a serial word with start, . data" parity and stop bits. The data word length may be 5, 6, 7 or 8 bits. Parity may be odd or even. Parity checking and generation can be inhibited. The number of stop bits may be 1 o~ 2 or 1 1/2 when transmitting a 5 bit code. ThelM6402l03 can be used in' a wide' variety of applications including interfacing'modems, Teletype'· and remote data acquisition systems to the IM61 00 (Tlicro- J .'," I • PIE/UARTIIM6100 INTERFACE ,r-JlflAYSTAL I DX(O) " DX(I1) IM6100 LXMAR DEVSEL INTGNT XTC ~t Cl C2 SKP INTREQ Vee .. " co i::= Vee :::E0CJ:te ~~~ SEt.6:. 1 SEL7 = 0 , . $ .' ~ ' ~ DX (11) ~ TBR (;) RBR (1), 1-+' DX (11), . ." PIE IM6101 WRITE DX (11) . ~ TBR (8) RBR (8) ~ DX (4) "r READl WAITE 1 UART.· IM6402 ~ 'w DX(O) ~ ~ ~ , DX (4) ~ .,..NI-" UUz a:-'I-U "'wZ .... SELECT CODE: SEL3 = 0 SEL4 = 1 SEL5 = 1 / II SENSE1r ~. ~ ~ ORR RRD fiiii[ PI = 1 DR· TBRE RRI CLS1 = CLS2 = 1 8.0.1•.811. 2 Stop BU, SSS = 1 RRC::: TAC = 1.76 KHz 110 Saud Rate ~ 1: TRO j ----------- 110 BAUD SERIAL PORT 'CRYSTAl S 2.5 MHZ. No Plrlly IM6101 IM6100 data bus lOX) to receive and transmit characters. may be tied together to clear DR as the register data is being read. The microprocessor monitors the status of the DR flag via SENSE1 to see if a new character has been received before it reads the information stored in tile buffer register by pulsing READ1 low. The NAND gate is used to load the UART with the leading edge of the WRITE pulse since the IM6100 data is valid only with respect to the leading edge at higher operating frequencies. The UART interface uses only the low order 8 bits of the PIE CONTROL REGISTER ASSIGNMENTS FOR IM6402 UART INTERFACE: ' WP1 = 0 1 0 CRA I- CRB I- 2 3 5 4 -I 1 0 2 3 7 6 WP1 5 4 1011 -I IE2 IEll 7 6 SL2 SL11 9 8 IE2 = 1 IE1 = 1 SP2 SP11 SL2 = 0; SP2 = 1 SL 1 = 0; SP1 = 1 Active low WRITE1 (TBRLl Interrupt enable for SENSE2 (TBRE) Interrupt enable for SENSE1 (DR) If vectored interrupts are used (PIN = 1 or is part of a priority chain) the Interrupt Vector Register must be loaded with the desired vector address . .SENSE2 (TBRE) active on 0 to 1 transition SENSE1 (DR) active on 0 to 1 transition PIE ADD~ESS AND CONTROL ASSIGNMENTS: OCTAL CODE EXTERNAL COMMANDS '0 1 2 3 4 5 6 7 8 9 10 11 11 1 o10 1 1 1 o10 ·0 0 o 1 lOT 1 1 1 Address o10 1 1 6340 Activate RRD low to transfer Receiver Register contents onto the OX lines and clear the Data Received Flag. 6341 Activate TBRL low to transfer data from the OX lines to the Transmit Buffer Register. 6342 Skip the next instruction if the internal SENSE FF1 was set by a positive transition on Data Received (DR) and then clear SENSE FF1. 6343 Skip the next instruction if the internal SENSE FF2 was set by a positive transition on Transmit Buffer Register Empty (TBRE) and. then clear , Sense FF2. READ1, 1 o10 0 0 1 1 WRITE1 11 1 o10 1 1 1 01 0 1 0 o I SKIPl 11 1 o10 1 1 1 o10 0 1 1 1 SKIP2 OCTAL CODE INTERNAL COMMANDS 0 11 1 2 1 o I 3 4 5 6 7 8 9 10 11 0 1 1 1 o10 1 0 o lOT 11 1 Address o10 1 1 1 o10 1 1 DESCRIPTION I 6344 'OR' transfer Control Register A to the AC. 1 1 6345 Transfer AC to Control Register A 1 1 6355 Transfer AC to Control Register B I 6354 Transfer AC (0-9) to Vector Register (0-9) RCRA 1 o10 1 0 WCRA 1 1 DESCRIPTION 1 o 11 1 0 , WCRB 1 1 1 o10 1 1 1 o 11 1 0 WVR o D~DIL IM6101 PIE Address and Control Assignments: EXTERNAL COMMANDS I 0 1 " 2 1 1 , OCTAL CODE 3 4 5 6 7 8 9 10 11 o 11 0 1 0 oI 0 0 1 lOT 6502 o I SKIPI Addreto; DESCRIPTION Skip,and clear if SENSE1 is low -'used to detect the status of the receive line. r I 1 1 011 0 1 o I '0 0 1 1 0 6506 I Set FLAG1 to put the transmit line high ("MARK") SFLAGI , I 1 o 11 1 0 1 oI 0 0 1~ 6507 Clear FLAG1 to put, the transmit line Io.w ("SPACE") I 6516 Set FLAG3 to enable the paper tape reader 1 I 6517 Clear FLAG3 to disable the ,paper tape reader OCTAL CODE D.ESCRIPTION CFLAGI I 1 1 011 0 1 o 11 0 '·1 1 o .. SFLAG3 I 1 o 11 1 0 1 0 oI 1 1 1 CFLAG3 INTERNAL COMMANDS, 0 I 1 1 ' 1 3 4 5 6 7 8 9 10 11 o 11 0 1 0 01 0 1 0 , RCRA 2 lOT I 1 1 Address o II, 0 1 . o, 0I 0 1 0 01 6504 'OR' transfer Contrql Register A to AC 1 I 6505 Transfer AC to 'Control Register A 1 I 6515 Transfer AC to Control Register B o I 6514 Transfer AC 10-9) to Vector Register 10-9) .wCM , 11 1 011 0 I' 0 o 11 1 0 WCRB 11 1 o 11 0 1 0 , o 11 1 0 " WVR' IM6101 Subroutines for programmed lOT transfers: Program Listing: IREFER TO THE APPLICATION BULLETIN HeSS I"ROM BASED SUBROUTINE CALLS WITH THE IIM61~0" FOR THE IMPLEMENTATION OF A ISOFTWARE STACK. THE ROUTINES IN THI S INOTE ASSUME THAT THE SUBROUTINES IARE RESIDENT IN RAM AND ARE CALLED BY ITHE CONVENTIONAL JMS INSTRUCTION. IINPUT-OUTPUT ROUTINES FOR UART IINPUT ROUTINE READS AN 8-BIT CHAR IFROM .THE UART INTO THE AC RIGHT IJU5IFIED. THE OUTPUT ROUTINE XMT5 IA CHAR FROM THE AC TO THE UART AND ITHEN CLEARS THE AC. IU5ER DEFINED MNEMONICS IREAD UART DATA RUART"634~ IWRITE UAR,. WUART-6341 5KPDR=6342 SKPTBR=6343 INPUT I 15KP IF DATA REeD ISKP IF XMT ROY e IENTRY FOR SUBROUTINE SKPDR JMP! .-1 IWAIT FOR' DATA READY 320e 3291 3202 8ee" 6342 521" 3283 3204 3215 3216 7208 021lJ7 56121" 321!l7 8377 K"377 I 0377 32U 321'1 3212 S"S" 6343 5211 OUTPUT I 9 SKPTBR JMP .-1 IWAIT FOR XHT. RDY 3213 3214 3215 6341 729S 56U' 1WART CLA JMP I OUTPUT IWRITE UART IRETURN CLA RUART AND K0377 JMP I INPUT 63~EJ IAC<- UART ISTRIP 121-3 IRETURN & CLA IM6101 TELETYPE INTERFACE WITH PIE A simple economical program controlled serial in'terface for a Teletype can be built using only the Programmable Interface E.lement. The interface uses one Sense line to receive serial data, one Flag line to transmit serial data and one Flag line to control the Teletype paper tape reader, as shown be,low, Timing for proper transmit pulse widths, setting and clearing FLAG1, and proper receiver sampling times, testing SENSE1 ,is created via software timing loops. PIE Control Register Assignments 9, 10 0 CRA 1 CRB ·1· SP11 SL11 SL1=1;SP1=O 11 ;1 SENSE1 is level sensitive and active low: IM6100/PIE/TELETYPE INTERFACE 4 MHz rl1 ox (0) OX (11) IM6100 LXMAR DEVSEl INTGNT XTC ~~r C1 C2 SKP INTREO co ::::: tt:...II-U ¢wZI::!:tI)C)( SELECT CODE: SElJ 1 SEl4 0 SElS 1 SEL6 SEl7 0 0 x> ... ..J~~ ::: ox ~::: ~:: ;; (0) - FLAGl TELETYPE TRANSMIT SENSEl IM6101 P'E ~= - ~~~ UU~ TelETYPE RECEIVE FLAG3 TELETYPE READER CONTROL OX(ll) "-'" IM6101 Subroutines for program~ed lOT transfers: Transmit character routine: The transmit routine takes an 8-bit character from the Accumulator and transmits it to the Teletype via FLAG1. FLAG1 is initially set high.or "mark". For each character, the program sends out a startbit ("space" - zero), 8 data bits with the least significant bit first and 2 stop bits ("mark" - one). Program listing: ITELETYPE .XMT ROUTINE IFLAGI IS INITIALISED TO I (MARK) ICHAR TO BE XMTED IN AC4-11 INOMINAL .BIT TIME .9.119 MS 14KHZ OPERATION FOR IM611l1l lAC AND L CLEARED AFTER XMT IUSER DEFINED MNEMONICS TMARK~65116 TSPACE"6507 JIlIl" JIl" I 3""2 JIl03 JIlll4 XMT. """" 316" 1235 3161 I 1611 II DCA TEMPI TAD M8 DCA TEMP2 TAD TEMPI JIlll5 JIlll6 6507 4225 TSPACE JMS DELAY JIlll7 JIlIIl Jill I 70111 74311 5214 JIll 2 31113 65117 741" TSPACE 3"14 6506 TMARKi JIl I 5 4225 JMS DELAY JIll 6 311 I 7 2161 52117 ISZ TEMP2 JMP LOOP 311211 31121 31122 65116 4225 4225 TMARK JMS DEl..AY JMS DELAY 31123 31124 7311" 561111 CLA CLL JMP 1 XMT 31125 3826 JIl27 311311 31131 II31611 II "" i 236 3162 11611 31132 3833 2162 5232 LOOP. RAR SZL JMP .+3 IXMT MARK (I) IXMT SPACE(Il) ISAVE AC 1-8 IN TEMP2 IRESTOREAC ISTART.BIT ITIME OUT BIT· IXMT 8 DATA BITS LSB FIRST IXMT BIT IN L IJMP IF IXMT " SKP IXMT ITIME .OUT BIT 19.1182 MS NOMINAL <.IS ERROR ' DELAY. IIDCA "" I! TEMPI TAD H693 DCA TEMP3 TAD TEMPI ISZ TEHP3 JMP· .-1 IXHT 8 BITS ISTOP BI T 12 STOP BITS IRETURN 19."43 MS ISAVE AC 1-693 IN TEHP3 IRESTORE AC !TIME OUT LOOP 19.009 MS JMP 31134 5625 31135 31136 77711 6513 H8. M693. """" """" TEMPI. TEHP2. TEHP3. "1611 11161 111162 Illl"" 777" 6~13 .161! II II I! II II II Ill! II Ill! I! DELAY IRETURN IM6101 Receiver character routine: The receive routine accepts a serial data string from ihe Teletype which consists of a start bit, 8 data bits with the least significant bit first and 2 stop bits and assembles them, right justified, into an 8-bit word in the Accumulator. Each bit is sampled in the middle of the bit interval. The user can read character by character from the Teletype reader by' turning the reader off after receiving each character and then reeriabling it under. program control to fetch the next character in sequence The routine assumes that the program is waiting for a character from the Teletype. .3180 ITELETYPE RECEIVE ROUTINE ISENSEI IS INITIALISED TO BE LEVEL ISENSITIVE AND ACTIVE LOW lAC AND L ARE CLEARED. CHAR IN AC 4-11 Program listing: IUSER DEFINED MNEMONICS SKPL0Io1=6502 . RDRON-6516 RDROFF-6517 3U'9 RCVE" 8""" 7309 ISKP IF TTY IN IS 8 IENABLE RDR IRDR OFF 1235 3161 8"90 CLA CLL TAD M8 DCA TEMP2 3194 6516 RDRON IENABLE RDR 3105 3106 6502 5305 SKPLOW JMP .-1 IWAIT FOR START BIT , 3107 31111J 1330 3162 TAD M349 DCA TEMP3 1-349 IN TEMP3 3111 3112 2162 5311 ISZ.TEHP3 JMP .-1 11/2 BIT DELAY 3181 3192 3193 START" 14.532 MS 3113 3114 6502 5305 SKPLOIo1 JHP START 3115 6517 RDROFF 3116 4225 DATA" JMS DELAY IFALSE START BIT IGOOD START BIT ITURN OFF RDR IFU1.1. BI T DELAY T,O THE IMI DD1.E OF NEXT BIT 1<.15% ERROR 3117 3128 3121 3122 7100 6592 7920 7919 CLL SKPLOW CML 3123 3124 2161 5316 I.SZ TEMP2 JHP DATA IRCVE 8 BITS 3125 ·3126 7012 7912 RTR RTR IRIGHT JUSIFY 3127 5799 JHP I RCVE IRETURN 3138 7243 11.=1 IF HARK RAR H349" 7243
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