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XX-A2A67-2E

2000

352 pages

Original

35MB

Document:	PDP-7 Maint
Order Number:	XX-A2A67-2E
Revision:
Pages:	352
Original Filename:	http://bitsavers.org/pdf/dec/pdp7/PDP-7_Maint.pdf

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CONTENTS (continued)
Chapter
3 (cont)

Break, Contro I (32) ••••••••••••••• ~ ................. ~ ~ ••••
Interface •••••• " .................................... -.....,..... .

3-36

'Device Selector (36) ...... e . . . . . . . . . . . . . . . . . . . . . e'. e • • • •

3-37

Inf~rmation Collector (33) ................. " " ••••••••••

3-39

Information Distributor (34) ............................ e ~ •

3-40

.................................

3-40

MB Bus Drivers (28)

.......................

3-31'
3... 33

I/O Skip Control and I/O' Trap

CORE MEMORY •••••••••••••, •••••••••••••••• "•••••••••• ~ ••••

4-1

Me~ory Organization .. " e._ .. " " . . . . . . . e .... " • • • " • " • • • • • • " " " • " •

4-1

Circui't Operations e . . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . . ~ ..
Ferrite-Core Memory Array •••••••• : ......... '•.•••••••••

4-2
4-2

Memory Selectors Type G202 and Memory Selector
Matrixes Types G60l and G602 ................... :." ,,'.

4-4.

Inhibit Dri'/ers Type G201 ........... " .................. .

4-8

Sense Amplifiers Type GOal and Master Slice
Con tro I Type G002 •

4-8

e" . . . . . . . . . . . . . . "

Memory Contro I

. . ..

........................... ........ '.'

4-10

Memory Curren t Sources

.............. "

.............................

4-11

. . . . . . . . . '• • • • • • • • • It • • • • • • • • • • • • • • • •

5-1

Teletype (Model 33KSR) and Control Type 649 ............. " ..... .

5-3

............................

5-3

Logical Functions .......... " ................,... ~ ........ " ...... ..

5-5

INPUT/OUTPUT

• • • • • • ,'.

~.'

Block Diagram Discussion

..................................
Perforated Tope Reader and Control Type 444B ..............

5-6

Circuit Operations

5-8

LogIcal Functions ............................................... " ..
5~ 11

Circuit Operations ............ ". ..........."."
........... ,,' •••
'
Tope Punch and Punch Control Type 75D

...................

Logical Functions ......................
Circuit Operations

II • • "

.............. .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . of

vii

•

5-15
5-16
5-18

CONTENTS (continued)
Page
OPTIONAL EQUIPMENT

• • • • • • • • • • • • • • • • • • e· • • • • • • • • • • • • • • • • • • • •

Automntic Priority Interrupt Type 172

•••••••••••••••••••••••••

6-1

oO . . . . . . oO.

6-1

Logical Functions ................................................. .

6-3

Block Diagram 0 iscussion ....

oOoO

. . . . . . . . . . . . . . . . . . . . oO • • • •

.................................... 6-7

Circuit Operations

..........................

6-12

Logical Functions .............................................. ..

6-13

Circuit Operations

6-14

Data Interrupt Multiplexer Type 173

........................................ ., ......... .

Extended Arithmetic Element Type 177 .

6-1

oO.

6-17

Logical Functions ............................................... .

6-17

Circuit Operations

6-22

INTERFACE

••

,. • • • •

oOoO . . .

oOoOoOoOoOoO.oOoOoOoO .. oOoO

.. oO

••••••••••••••••••••••••••••••••••••••••••

7-i

Interface Conn€..:tions and Signal Identification

Loading and Driving Considerations .......
Information Collector (lC) (33)

.oO . . . oO

Information Distributor (10) (34)
Device Selector (DS) (36)

oO .. oOoO .. oOoOoO . . . . . . . oO.

• • oO.oOoO.oO • • oO • •

. . . . . oOoOoOoO • •

RUN STOP (20)

oOoO

...

oO"

oOoO

oO.oO.oO • •

. . . oO

oOoO.oO • • • oO . . . . . . . . . . . . oO

.....

.. oO

. . . . . . oO

.. oOoOoOoOoO

If "oO . . . . . . . . . . . . . ..

. . . . oOoOoO . . . . oO .. oOoO ••

oOoOoOoO.oO . . .

oO .. oOoOoO

7-16
7-18

7-26
7-26

........................................... 7-26
7-26

RUN ('1) (23)

MB (36)

7-14

..................................... 7-24

PWR CLR and NE G. PWR CLR (20) ..................

S'G f'J (B) (20) ........

7-1

.................................................. 7-26

10 T (36) ••••••••••••••••••••••••••••••••••••••••••••••••••

7-27

................................................. 7-27
REQUEST SLOvV CYCLE (36) ................................ 7-27

ACB (34)

PR0GRAM INTERRUPT REQ UEST (32) ...

oOoOoO.oO . . . . . oO.oO • •

oO • • •

. . . . . . oO

7-27

DATA RQ (24) ••••••••••••••••••' •••••••••••••••••••••••••••

7-28

. riA (Data Address) (29) .....................................

7-28

viii

CONTENTS (continu ed)"
Chapter
7 (cant)

Page
DATA ADDR ACC (32)

•

• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 41 •

....................... .. ...

DATA I N (Transfer 0 irectian) (32)

7-29

·...... ., ................................. .

7-29

MBB (28 and 36)
DATA ROY (32)

INSTALLATION

•

•••••••••••••••••••••••••••••••••••••••

•

••••••••••••••••••••••••••••••••••••••••

•

·................................... .

7-30
7-30

8-1

Site Preparation "••••••••••••••••••••••••••••••••••••••••• ".

8-1
8-1

Space Considerations
II.

8-1

Power Requirements .................................... .

8-3

Environmental Conditions •••••••••••••••••••••••••••••

8-3

Preparation for Sh ipment

8-4

Teletype Shipping Procedure ••••••••••••••••••••••
Installation ••••••••••••••••

7-29

o I {Data Information} (30) ...................................
DATA ACC (32)

7-29

•

• • • • • • • • • • • • • • • • • • • • • • • • • • • • . • • • • • • • • • • • • • • • • • • • 4t •

8-5

9-1

Controls and Indicators ••••••••••••••••••••••••••••••••

9-1

Operator Console Controls and Indicators ••••••••••••

9-1

..............................
Tape Reader Controls ................................ ..

9-11

Indicator Panel

9-11

Teletype Controls

•

••

•••••••••••••••••••••••••••••••••

9-9

·................................... .

9-15

................

9-16

Loading Binary Data Using READ-IN Key ................. .

9-17

Loading Data Under Program Control ....................... .

9-18

Assembl ing Program With PAL •••••••••••••••••••••••••••

9-19

Operating Procedures

Manual Data Storage and Modification

........................................
Local Teletype Operation ................... .......... .

Teletype Code

...............................

Programming
ix

9-20
9-24
9-24

CONTENTS ( con tJ n u e d )
Page

Chapter

.............................................. 10-1
10-5
Preventive Maintenance ................................
Mechanical Checks ................................... 10-5
Power Supply Checks .................................. 10-6
Marginal Checks ·.................................... . 10-8
Memory Current Check ................................. 10-15,
10-16
Sense Amplifier Check
........................
Corrective Ma intenance
........................... 10-16

MAINTENANCE

••••••••••••

10-17

System Troubleshooting •••••••••••••••••••• i' ••••••••••••

10-18

Prel iminary Investigation

Circuit Troubleshooting
Repair

................................ 10-22

............................................... 10-27

Spare Ports

••••••••••••••••••

·.................................... . . H3-28

V:Jiidaticn,Test ••••••••••••••••••••••••••••••••••••••••

10-33

Log Entry •••••••••••••••.•••••••••••••••.••••• e . • • • • • • •

10-34

ENGINEERING DRAWINGS

11-1

.......................................... 11-1
Circuit Symbols .......................................... 11-1
Drawing Numbers

Logic Signal Symbols ••••••••••••••••••••••••••"•••••••••••••

................................... 11-4

Logic Levels

Standard Pu!ses •••••• : ...... .
FLIP CH IP Standard Pulses
Level Transistions

11-4

..............................

11-4
11-5

·..................................... . 11-5

......................................... 11-6
W,odu Identification ·..................................... . 11-6

Coordinate System
~e

Example

........... ...................................... . 11-7
'

CONTENTS (continued)
Page

Appendix

iNSTRUCTION SUMMARy ••••••••••••••••••••••••••••••••••••

MODEL 33ASR/KSR TELETYPE CODE (ASCII) IN BINARY FORM

SIGNAL. GLOSSARY •••••••••••••••••••••••••••••••••••••••••

A1-1
A2-1

A3-1

TABLES
Table

1-16

1-1

Program Library

6-1

EAE Bit Assignments and Operations ............................... .

6-18

7-1

Output S·ignals ................................................. .

7-2

Input Signals

........................................ ., ....... .

7-6

7~3

Prewired Information Distributor Connections

..................... .

7-19

7T4

lOT Pulse Code Assignments .................................... .

7-25

9-1

Operator Console Indicators

9-2

Operator Console Switch Regbters ................................ .

9-4

9-3

Operator Console Switch Controls and Indicators ................... .

9-4

Operator Console ManlJal Keys ................................... .

9-7

9-5

Teletype Console Controls

.....................................

9-10

9-6

Tape Reader Controls •••••••••••••••••••• ~ •••••••••••••••••••••

9-11

9-7

Indicator Panel Indicators •••••••••••••• e . • • • • • • • • • • • • • • • • • • • • • • •

9-11

9-8

Readin Mode (R 1M) Loader Program .............................. .

9-9

Teletype Code

...............................................

9-17
9"':'21

10-1

Maintenance Equipment ........................................... .

10-1

10-2

Maintenance Controls and Indicators ................................ .

10-3

Power Suppl y Output Checks ..................................... .

10-7

10-4

Marginal Test Programs ............................................. .

10-12

10-5
10-6

Spare Parts for Printer Keyboard-Model KSR 33 ••••••••••••••••••••

10-29

Teletype Maintenance Tools ........................................... .

10-7

PDP-7 Module List

...........................................

10-29
10-30

·10-8

Suggested Spare Semiconductors ................................. .

10-32

• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • III

ILLUSTRATIONS
Fi~
,I

1-1

Programmed Data Processor-7 .......................................

xvii

1-2

Maior Registers, Simplified Block Diagram.........................

1-3

Instruction Word Format •••• oo • • • oo • • oooooooo.oooooo • • • • • • • • • • • • • • • • • • • oo.

1-10

1-4

Basic PDP-7 Cortlpone:~~ Lc>~ations .............

o . oo............................

1-13

3-1

Processor Detailed Block Diagram

3-2

Device Selector Logic Diagram .... oooo • oooo oo . . . . . oo . . . . . . . . . . . . . . . . . . . . oo.oo oooo oo.

3-38

4-1

Core Memory System Rlock Diagram ......... oo .. oo .... oo . . . . . . . . . oo . . . oo • • • • •

4-2

Simple Core Memory Plane Showing Read:/\,!Vrite
Sense, and Inhibit \"J:nriinqs .... ~ ....... oo .. oo . . . . oo . . . . . . . . . . oo . . . oo • oo . . . ..

4-3

Typical Core Selection Circuit and Drive Current Path

.oooo . . . . . oo . . . . . . . .

4-6

4-4

Mern<:>ry Control Timing .. oo . . . . . oo . . . . . . oo . . . . oo .. oooo . . . . . oo . . . . . . . . . . . . . . . . . . . . oo.oo

4-7

4-5

Inhibit Logic for One Memory Cell .............. oooo.oo . . . . . oo . . . oo . . . . . . oo • • • • oo

4-9

5-1

Input/Output Informati:>n Flo"'! oo • • • • • • • • oo . . . . . . . . . . . . . . ,• • • • • • oo • • • • • •

5-2

Block Diagram of Keyhoard/Printer Control Type 649 •• '.oo . . . . . oo . . . . . . . .

5-2

5-3

Tope Format and Rcanf->r BIJff<=>1" Register Bit Assignments ............. .

5-10

5-4

Reader Buffer in Binary Mode ............. oo • • • • • • • • • oo • . • • • • • • • • • • •

5-13

5-5

. Effect of Delayed Sampl ing

5-15

6-1

Automatic Priority Interrupt Type 172 BlOCk Diagram •••.•••

6-2

Data Interrupt ~Aultiplexer Tlpe 173 Block Diagram ................ .

6-13

6-3

EAE Instruction Bit Assiglli1ii:~nts ............. oo • • • • • • • • • • • • • • • ' • • • • •

6-21

7-1

Channel Assig:1ments for thf~ Inforrr.ation Collector ••••••.••••••••••

7-18

8-1

Installation Outl ine Drawing

9-1

Opera tor C~)!'$O I e

9-2

Teletype Console

9-3

Tape Reader

9-4

Indicator Panel ...........................

10-1

Marginal-Check Panel ••••' •••••••• oo . . . . . . . . . . . . . . . . . . . . . . oo . . . . . .

11-1

DEC Symbots .•..•••••.•••••••••••••.•••••••••••••••••••• " ••••

11-2

Standard Negative Pu Ise

........................................

11-4

• • • • • • • • • • • • • • • • • • • • • • e_ • • • • • • • •

oo ..

oo • • • • • • •

..................................

3-2

6-2

8-2
9-1

_ . . . . . . . . . . . . . . . . . . . . . . . . II • • • • • • • • • • • • • • • • • • •

9-10

•••••••••••••••••••••••••••••••••••••••••••••••

'9-12

xii

................................. .

•••

9-13
10-4

ILLUSTRATIONS (continued)
Figure

11-3

FL IP CH IP R-Seri es Pulse ••••••••••••••••••••••••••••••••

11-5

11-4

Typical DEC Logic Block Diagram ••••••••••••••••••••••••

11-7

ENGINEERING DRAWINGS
Drawing
Power Suppl ies And Control
RS-B-728

Power Suppl y (+10 and -15) •••••••••••••••••••••••••••' •••

11-8

RS-B-738

Power Supply (0-20 marginal check supply) ••••••••••••••••

11-8

RS-B-778

Dual 15-Vo I t Power Suppl y ••••••••••••••••••••••••••••••

11-9

RS-B-779

Power Suppl y (one 10v and three 15v floating suppl ies) ••••••

11-9

RS-C-739

Power Supply (Memory) •••••••••••••••••••••••••••••••••

11-10

RS-B-W505

Low-Vol tage Detector (for 739) ••••••••••••••••••••••••••

11-11

RS-B-G800

Control for 739 Power Supply .•••••••••••••••••••••••••••

11-11

RS-B-832

Two-Step Power Control •.•••••••••••••••••••••••••••••••

11-12

System Modules'
RS-C-4706

Eight-Bit Teletype Receiver

•••••.•••••••••••••••••••••••

RS-C-4707

Eight-Bit Teletype Transmitter

•••.•••••••••••••••••••••••

11-13

11-14

FLIP CHIP Modules

.....................................

RS-C-B210

PDP-7 Accumulator

RS-C-GOO1

DC Sense Ampl ifier

11-16

RS-B-G002

Ma5tcr Slice Control

11-17

RS-B-G201

In hi bit Dr i v er .......................................... .

11-17

RS-B-G202

Memory Selector •.••• " •••••••••••••••••••••••••••••••••

11-18

RS-D-G601

Memory Selector Matrix •••••••••••••••••••••••••••••••••

11-19

RS-D-G602

Memory Selector Matrix •••••••••••••••••••••••••••••••••

11-21

xiii

11-15

ENGINEERING DR,AWINGS (continued)

Basic POP-7 Processor logic

11-23

WO-D-7-0-18

Stol"dard C. P. Bus Schedu Ie •••••••••••••••••

ML-0-7-0-19

Central Processor Module Map

•••••••••••••••••••••••••••

11-25

85·-D-7-0-20

Special Cycles and Key Functions •••••••• ~ ••••••••••••••••

11-27

FO-0-7-0-21

Flow Diagram

•••••••••••••••••••••••••••••••••••••••••

11-29

85·.. 0-7-0-22

Timing

...............................................

11-31

85-0-7-0-23

Run and Special Modes ••••••••••••••••••••••••••••••••••

11-33

B5-0-7-0-24

Maior and Minor States_ ••••••••••••••••••••••••••••••••••

11-35

85-0-7-0-25

MA, MB, arid PC Control ••••••••••••••••••••••••••••••••

11-37

85-D-7-0-26

AC Control and link •••••••••••••••••• ,__••••••••••••••••••.

11-39

85-0-7-0-27

Memory Control • '•••••••••••••••••••••••••••••••••••••••

11-41

8S-0-7-0-28

MB Bus Drivers •

11-43

B5-D-7-0-29

MA and PC Registers .................................... .

11-45

85-D-7,.. 0-30

MB Register ....•....•.•.........••..•.••••..••••. ~ •••••

11-47

85-0-7 -0-31

AC Registers (Sheet 1) "••.••..•..•••••.•.•••••••••••••••••

11-49

B5-0-7-0-31

P.C Registers (Sheet 2) ................................... .

11-51

B5-0-7 -0-32

Interrupt Control

11-53

85-0-7-0-33

Information Col lector ••••••••••••••••••••••••••••••••••• -

11-55

B5-0-7 -0-34

Information Distributor •••••••••••• _•••• ~ •••••••••••••••••

11-57

N\l-O -7 -0-35

Device Selector Module Map

••••••••••••••••••••••• "•••••

11-59

BS-0-7-0-36

Device Selector ••••••••••••••••••••••••••••••••••••••••

11-61

\ND-O-7-0-37

Console Panel Wiring Oiagram ••••••••••••••••••••••••••••

11-63

Cl-O-7-0-38

CP Cables Out 1L1 to 1 M12 (Sheet 1)

.....................

11-65

c: l-D-7 -0-38

CP Cables Out ll1 to 1M12 (Sheet 2)

11-67

CL-O-7-0-38

CP Cables Out 1L1 to 1M12 (Sheet 3)

11-69

Cl-D-7-0-38

CP Cables Out 1ll to 1M12 (Sheet 4)

11- 71

'NO-O-7 -0-39

Device Selector Bus Schedule ............................ .

11-73

B5-D-7-0-40

Central Processor Modification for EAE

11-75

o• • • • • • • • • • • •

o• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •

••••••••••••••••••••••••••

xiv

o• • • • • • • • • • • • •

ENGINEERING DRAWINGS (continued)
Drawing
Basic PDP-7 Core Memory Logic (Type 149)
BS-E-149-0-4S

Inhibit Drivers and Sense Ampl ifiers Core
Memory 0 and 1 •••••••••••••••••••••• '. • • • • • • • • • • • • • • • • •

11-77

BS-E-149-0-49

·.................... . 11-79
"Y"Axis Selection 4K Core Memory ·.... ................ . 11-81
"X Axis Selection of Core Memory ·.................... . 11-83
"Y" Axis Selection of Core Memory ·.................... . 11-85

ML-D-149-0-S0

Standard Memory Module Map •••••••••••••••••••••••••• ., •

11-87

WO-0-149-0-S1

Resistor Panels •••••••••••••••••••••••.•••••••••••••••• .,.

11-89

CL-D-149-0-S2

Memory Stack Connector Configuration •••••••••••••••••• .,.

11-91

BS-E-149-0-46
BS-E-149-0-47
BS-E-149-0-48

"X 1\ Axis Selection 4K Core Memory

Basic PDP-7 Input/Output Equipment
Perforated Tape Punch and Control Type 7SD
BS-0-7S0-0-2

Punch Control

••••••••••••••••••••••••••••••••••••••• '. •

11-93

Perforated Tape Reader and Control Type 4MB
BS-0-444B-0-2

Reader Control •••••••••••••••••••••••••••••••••••••••••

11-95

ML-0-444B-0-3

Reader 444B and Punch 7SD t-Aodule Map •••••••••••••••••••

11-97

WO-0-444 B-O-S

Reader 444B and Punch 7S0 Bus Schedule

..................

11-99

................................

11-101

Teletype Control Type 649
85-0-649-0-2

Keyboard/Printer Control

POP-7 Options
Extended Arithmetic Element Type 177
FO-0-177-0-2

EAE Flow Diagram (Sheet 1) ••••••••••••••••••••••••••••••

11-103

FD-0-177-0-2

EAE Flow Diagram (Sheet 2) ••••••••••••••••••••••••••••••

11-10S

FO-D-177-0-3

EAE Modul ~ Mop

................. "...................... .

11-107

85-0-177-0-4

EAE States

.............................................

11-109

ENGINEERING DRAWINGS (continued)
Drawing
PDP-7 Options (continued)

85-0-177-0-5

EAE Step Counter and Control ...... oo . . . . . . . . . . . . . . . . . . . . . . . . . .

11-111

85-0-177-0-6

EAE Register Control ........... oooo ..... oo .. oooo.oo • • • • • oo • • oooooooooooooo

11-113

85·-0-177-0-7

Main Time Chain

oo.oo.oo .... oooo oo.oo oooo ... oooooo.oooooooo • • oooooo.oooo.oooooo.

11-115

85-0-177-0-8

MQ Register .. oooo.oo.oo . . . . . . oo . . . . oo • • oo . . . . . . . . . . . . oooooooo . . . . oo.oo . . . . oo.

11-117

85-0-177-0-9

AC Inverters .. oo ..... oo • • • • oo .. oo • • • oo.oooo.oooo . . . . . . . . . oo • • • oo . . . . . . . . oo • •

11-119

Cl.-D-177-0-10

EAE Cable Schedules

....................................................... .

11-121

WD-0-177-0-12

Pin and Block Layout EAE oooo.oooo .... oo ... oo .. oo .. oooo .. oooo .. oo .... oooo ..... oo ....

11-123

Data Interrupt Multiplexer Type 173

8S-0-173-0-2

Data Interrupt Multiplexer Control

.......................

11-125

85-0-173-0-3

Data Interrupt Multiplexer Data
Input/Data Addresses ............................................................ ..

11-127

ML-D-173-0-5

Data InterruF't Multiplexer Module ivi\ap

.. oo ..... oo ....... oo . . . . oo . . . .

11 ..·l:!9

WO-0-173-0-8

8us Schedu Ie ..............................................................
..
.

11-131

~utomatic Priority Interrupt Type 172

85-0-172-0-2

Automatic Priority Interrupt Control ....... oo.oooo ..................... oooooo

11-133

85-0-172-0-3

Automatic Priority Interrupt System (Sheet 1) .................... oo . . . ..

11-135

85-0-172-0-3

Automatic Priority Interrupt System (Sheet 2)

..............

11-137

ML-D-172-0-5

Module Map .......... oo ....................... oooo .. oo . . . . . . . . . . . . . . . . oooo .. oo . . . . . . . . .

11-139

WO-D- 172-0-6

Pin and Block Layout

........................................................ ~ •

11-141

xvi

':;;;;~~~:,~,~~ci=

ii,~~'i_,~""~~~j-.

'-'~ ,''111

Figure 1-1

Programmed Data Processor-7

xviii

CHAPTER 1
INTRODUCTION

AND

DESCRIPTION

The Digital Equipment Corporation (DEC) Programmed Data Frocessor-7 (PDP-7) is a general
purpose, stored-program, solid-state digitol computer designed for use in laborotories, computing centers, or process control systems. The PDP-7 is single-address, fixed l8-bit word~
length, ~i nary computer using l's compl ement arithmetic and 2's compl ement notation to
facilitate multiprecision arithmetic. A basic PDP-7 contains a 4096- or 8192-word, random
access, ferrite-core memory which can be expanded in increments of4096 words to a maximum capacity'of 32,768 words by the use of additional memory modules and a DEC Type 148 Core
MemoryE:dension Control. High-capacity, flexible input/output circuits permit the computer
to operate with all modern types of data processing equ ipment and many types of process-control
instrument,s.
The basic PDP-7 includes the processor {with operator console}, 4096-word core memory,
input/output control with a device selector that permits selection of up to 64 I/O devices and
is expandable, information collector, information distributor, and real-time clock. The pro4

cessor provides fa~iI Hies for program interrupt, data interrupt {for use with high-speed I/O
devices}, I/O status check, I/O skip, and I/O trap (which provides the basic hardware necessary for a time-shared or multiuser system). The input/output equipment supplied with a
basic PDp·-7 system consists of a high-speed perforated tape reader (300 char/sec); a high-speed
paper tape punch (63.3 char/sec); and a Model 33 KSR Teletype unit {l0 char/sec}.
The PDP-7 is completely self-contained and requires no special power sources, air-conditioning,
o'r floor bracing. The PDP-7 draws its primary power from a single source of l15v, 60-cps,
single-phase power, and from this source produces all required operating voltages.

Upon re-

quest, PDP-7 systems can be supplied to operate from 220v, 50- or 60-cps supplies. Built-in
provisions for vary;ing the + 10 and -15v suppl ies that power the logic permit the operation of
the logic to be checked under marginal conditions. The computer is constructed with standard
DEC FLIP CHlp™ modules and power supplies.
TM FLIP CHIP is a trademark of the Digital

Equipment Corporation
1··1

This manual provides information required for maintaining a basic PDP-7 system. The manual
also provides information concerning the following commonly used options: Type 177 Extended
ArIthmetic Element, Type 172 Automatic Priority Interrupt, and Type 173 Data Interrupt MultiplE~xer •

COMPUTER ORGANIZATION
The computer consists of a processor (with operator console), a core memory, interface equipment, and input/output equipment. Figure 1-2'illustrates the interrelationship of these
elements. All arithmetic, logic, and system control operations are performed by the processor.
Te,mporary information storage is provided by the various registers of the processor 'and by associated input/output devices. Permanent information storage (longer than one instruction time)

is provided by the core memory. During each computer cycl e lasting 1 .75 fJsec, the core
m~emory automatically performs a read operation and a write operation under the control of

timing signals produced by the processor.

Interface circuits permit connections to a variety

of peripheral equipment, and are responsible for detecting all I/O select codes and for providing necessary input or output gating. Individually programmed data transfers between the processor and peripheral equipment take place through the accumulator. The data break faci! it>,
p~~rmits single or multiple data transfers to be initiated by a high-speed I/O device; each

transfer using ,the data break is completed in a single computer cycle. The interface circuits
also permit peripheral equipment to perform certain control functions, such as instruction skipping or the initiation of a program interrupt to transfer program control.

Processor
The processor performs logical and arithmetic functions, controls the storage and retrieval of infc)rmation on core memory and controls the flow of information to and from peripheral equipment.
The processor consists of control logic and six major registers. Associated with the processor is
the operator console, which permits the information contents of memory and of the major registers

tc) be manually established, modified, or examined.

1-2

mO-n
..,e

---I

CI)
AOORESS

"->

CONNECTION TO INPUT/OUTPUT
EQUIPMENT USING THE DATA

8REA~

0
0

..,
:;:0
CI)

"'""" I I....", ~II

OATA

~~~--------------------r-r---------~

tf81~~~~

CONNE(TlO~j TO STANDARD
AND OPT:ONAL INlJiJT I OUTPUT
[QUIP... n~T USING PROG'lAMMED

(lATA TRANSFEfiS

CONT~

..-

- --- -

I. .

.-1 ACCUMULATOR

..,CI)

MAJOR

-0

GENERATOR

~E~E.-l

I PROCESSOR
L- -- - -

c..

-r- -- -- r - -

_ _ __

-t-\

in"

INSTRUCTION
REGISTER

STATE

Vl
-.
3

r -:-- -1- . - - - - - . . . - - ---t-~l
I --L

0
A

~EYS aMOO£

SWITCHES

INDICATORS

-.0

I
I

..,

I
I

LINK

ATA

,--,

~~~~~~~------------~

-.-.1

I
I

~~M~

Accumulator (AC) and Link (L)
The AC is an l8-bit register which performs arithmetic and logical operations on the data and
serves as a transfer register for programmed information transfers between core memory and
peripheral equipment. The link isa l-bit register which extends the arithmetic facility of the

AC and simplifies the programming of arithmetic operations. The link serves primarily as a
carry or overflow register for the AC.

Memory Address Register (MA)
This 13-bit register holds the address of the core memory location currently being ~sed. Two
additional bits are wired into the basic PDP-7 but are used only if the memory storage capacity
is extended beyond 8192 words by means of the memory extension options.

Memory Buffer Register (MB)
This la-bit register serves as a buffer for all information passing to or from core memory from the
processor or external devices using the data break.

Instruction Register (lR)
This 4-bit register holds the operation code of the instruction currently being performed.

Program Counter (PC)
This l3-bit register holds the address of the memory location from which the next instruction is
to be taken.

As in the MA, two "additional bits are provided, but are used only in conjunction

with the memory extension options.

N\ajor State Generator
The major state generator is a multistate device which can assume anyone of four stable states,
each corresponding to one of the fO'Jr major control states of the processor. One or more states
are entered to execute a programmed instruction, but only one state exists at anyone time.

1-4

Operator Consol e

All. manual controls and all processor readouts and indicators are located on the operator
console. The!e may be classified as follows:
1.

associated register. To facilitate presetting numbers specified in octal
notation, the switches assoc iated with each register are grouped in threes.
The order of significance is from right (least significant) to left {most significant} •

2. Keys and mode switches, used to initiate specific computer functions.
3. Register indicators, used to display the contents of an assoc iated register. A lighted indicator lamp denotes a binary 1 in the associated bit of
the register.
4. Pr imary power sw itc hes .

Core Memory
The high-·speed random-access core memory of the basic PDP-7 is a 4096-word coincidentcurrent core module with a read/write cycle time of 1.75 IJsec. In each cycle, the memory
reads an l8-bit word stored in the memory location specified by the MA, transfers the word
into the MB, and rewrites the word into the same memory location. Extension of the core
memory capacity to 8192 words may be accompl ished merely by the addition of another 4K
memory module, and requires no modifications to the processor. Extension of memory capacity
beyond 8K requires the use of the memory extension options {memory modules and memory extension control}.

Interface
The interface control I inks the processor to input and output stations, calls the stations, and
collects and distributes the input/output data. It also controls the interleaving of high-speed
data transfers between programmed instructions during the data break {cycle stealing}; senses

1-5

the status of I/O devices and permits the status sensed to cause an instruction to be skipped;"
inaiates program control transfers; and, in multiuser or time-shared systems, traps illegal instruct ions.
No additional interface equipment is required for the connection of standard DEC peripheral
equipment to the PDP-7. If special-purpose devices are to be connected to the PDP-7, a
suitable interface may easily be constructed using the standard I ine of FL IP CH IP modules
manufactured by DEC.

Input/Output
The standard input/output equipment provided with a basic PDP-7 consists of a Model 33 KSR
Teletype unit and DEC Type 649 Teletype Control, a Digitronics Type 2500 Perforated Paper
TClpe Reader and DEC Type 444B Reader Control, and a Teletype BRPE Perforated Tape Punch
and DEC Type 750 Punch Control.

T1eletype and Control
The Teletype unit is a standard machine operating from serial ll-unit code characters at a
rate of 10 char/sec. The Teletype provides a means of supplying dota to the computer by means
of a keyboard, and of typing output data from the computer on a page-size paper roll. The
Teletype control converts serial characters from the keyboard into parallel form for acceptance
by the computer, and converts para II el computer output data into serial form for acceptance by
the printer. The keyboard and printer, and their associated control circuits, form two separate
and distinct information channels, thol.,lgh information typed on the keyboard is always printed
by the printer.

!)erforated Paper Tape Reader and Control
The reader senses information contained on 8-channel, fanfold paper tape photoelectrically,
(It a rate of 300 char/sec. The control contains a data register, a flag, and Jogic circuits
which permi t reader operation to be controlled by the stored program ..

1-6

Perforated Paper Tape Punch and Control
The high-speed paper tape punch perforates a-channel, fanfold paper tape at the rate of
63.3 char/sec. The control contains a dato register, a flag, and control logic. All punching
operations are performed under the control of the stored program.

Processor Options
The processor options described in this manual are the Type 177 Extended Arithmetic Element I
The Type 172 Automatic Priority Interrupt, and the Type 173 Data Interrupt Multiplexer.

Extended Arithmetic Element
The extended arithmetic element (EAE) facilitates high-speed multiplication, division, shifting,
normal izing, and register manipulation. Installation of the EAE adds an l8-bit mul tipl ierquotient register (MQ) and a 6-bit step counter register (SC) to the computer. The contents of
the MQ are continuously displayed on the operator console. The EAE operates asynchronously
with resp€~ct to the computer cycl e, thereby permitting computations to be pe:-formed in the
minimum possible time. Further, EAE ;nstructions ar€: microcoded so that several operation~
can be performed by one instruction. Average multiplication time is 6.1 llsec, average division
time is 9 ~sec.

Automatic Priority Interrupt
The automatic priority interrupt (API) inCf€::lSeS the caparity of the PDP-7 to handle data transfers of information to and from I/O devices by directly identifying an interrupting device
without the need to scan flags. The API is particularly useful in ensuring rapid servicing of
I/O devices which retain their information for a limited period {such as the real-time clock or
analog-to-digital converters}. The API provides 16 automatic interrupt channels arranged in a
priority sequence in which channel Os has thehighest priority and channel 178 the lowest. The
priority chain guarantees that if two or more I/O devices request an interrupt concurrently,
the first interrupt is granted to the device with the highest priority. The requests of the other
devices are registered and are later serviced in order of priority. Multilevel interrupts are
permissible, where a device of higher priority supersede!; an interrupt already in progress.

1-7

Data Interrupt Multiplexer
The- data interrupt multiplexer permits the single data break facil ity of the PDP-7 to be used

by up to four high-speed I/O devices. Each devi ce must supply 18 data lines, 15 address lines,

a h'onsfer direction signal, and a break request signal. When a data break is granted by the
processor, each informatio., transfer is completed within one computer cycle. The maximum
combined transfer rate is 570,000 l8-bit words/sec.

FUNCTIONAL DESCRIPTION
Th,e PDP-7 performs arithmetic or logical operations upon data stored in the core memory. The
nature and sequence of these operations is determined either by a series of instructions, also
stored in memory (programmed operation), or by operation of keys and switches on the operator
console (manual operation). Manual operation is restricted to the following: starting and stopping programmed operation; continuing programmed operation after a temporary halt; setting
the starting address (memory location) of a program into the memory address register; depositing
information in manually selected memory cells; examining the contents of manually selected
memory cells; and the ;;election of special modes. For mointenance or debugging purposes, 0
de~posit or examine operation may be repeated manually to permitvisual monitoring by means of

the register ind icator lamps on the operator console or bysignal tracing with an oscilloscope.
During programmed operation, the processor retrieves from memory the first instruction specified

by the program, executes the instruction during one or more computer cycles (each cycle lasting
1 ,,75 ~sec), and then proceeds to retrieve and execute the remaining instructions specified by
the program sequence. All arithmetic, logical, or control operations of which the computer
is capable are performed as a function of three major determinants: the instruction 'retrieved
from memory; the major control state establ ished; and timing pulses produced by the processor.

Instructions
Instructions are of two types: memory reference and augmented. All instructions contoin an
operation code (specifying the nature of the instruction) in bits

through 3.

Memory reference instructions cause information to be stored in or retrieved from memory, and
contain a memory address as well as an operation code. All memory reference instructions

1-8

require one computer cycle in which the instruction is retrieved, and all except the jump
instructiorl require a second cycle in which to execute the instruction specified by the operation
code. The jump does not cause storage or retrieval of information, but transfers control of the
processor from one block of consecutive memory locations (containing instructions) to a different
block of consecutive locations. The jump instruction is normally completed in one computer
cycle. If indirect addressing is employed, two cycles are required for the jump and three cycles
for other memory reference instructions.
Augmented instructions do not require reference to memory. Since no address is required,
bits 4 through 17 are decoded to initiate various operations to extend or augment the operation
code. Because no storage or retrieval operations are performed, most augmented instructions
can be completed in one computer cycle. Augmented instructions are divided into three classes:
1. Instructions having an operation code of 648 are EAE instructions.
2. Instructions having an operation code of 708 are input/output transfer
(lOT) commands, and are used to control or test the status of I/O devices,
or to effect an informatio~ transfer.
3. Instructions havi ng an operation code of 748 are operate (OPR) commands,
and are used for basic processor data manipulation such as instruction skipping
as a function of register condition, shifting, rotating, etc.
The formats of the various types of instruction words are ill ustrated in Figure 1-3: Appendix 1
contains'a list of the instructions performed by the PDP-7.

Major Control States
The computer operates in one of four major control states during each machine timing cycle.
One or more states are entered to execute an instruction. The states are fetch, execute, defer,
and break and are determined by the major statE~ generator. Only one state exists at a time
and all states, except break, are determined by the programmed instruction being executed.

1-9

OPPATIOH

ADOAESS

COO[

10 " 12 113 114115116117

'--...-'
INOIRECT
AOORtSS~

•

&IT 15 A ,

Memory Reference Instruction Bit Assignments

DEVICE
SELECTION

OPERATION
CODE 70

r ,0 1

CLEAR Ae
AT EVENT
TIUE , IF
81T IS A 1

GENERATE
AN ItOP 2
PULSE AT EvENT
TIME 2 IF BIT
IS A I
,.-..J--..

'--.......-----'

SUB-OEVICE
SELECTION

SUB-DEVICE
SELECTION

'--r--'

GENERATE
AN 1/01' 4
PULSE AT
EVENT TIME
4 IF BIT IS
AI

GENF.RATE
AN I10P I
PULSE AT
EVEItT TIME
I IF BIT 15
A I

lOT Instruction Bit Assignments

'iF liT e
IS A I

I'IOTAT£ I
OPEJUTION
coer.:: 74
,

r? i '

I 2

----.
I 3

CLA
IF BIT
IS A ,

,..-........

~~I;~O: %.

/ SZL

Z POSITIONS
IF A'
.--'---,

IF BIT
IS A I

14 I ~ I 6 I 7 i 8

""--v-'
CONTAINS
A 0 TO

~
CLL
IF BIT
IS A I

:,.~~~

IF' BIT 7
IS A t

S~A SPA' MLT I RTA ' ATL '
IF BIT I' BIT IF BIT IF BIT IF BIT
IS A , IS A I IS A I IS A 1 IS A ,

CIIIL
IF BIT
IS A I

...--'---.,.--"--..~,--)-,~

9 1 10 j "

REVERSE
SKIP

~~Nill~

9.10." If
BIT II IS A I
SNL
If BIT

jl2 I 13 I

---...--'~~
RAR
RAL
OAS
IF BIT
.15 A I

IF BIT IF BIT
IS A " IS A 1

1 '7

~
eMA
IF BIT
ISA 1

IF
7
IS A 0
52A
If BIT

,r5AO

SUA
IF BIT
15:0 IS 1.0,
IF 81T I
IS A 0

Group 1 Operate Instruction Bit Assignments

OPERATION
COOE 74

AOORESS SIZE
NUMBER

110 1" 112 1,3 I 14 1,5

\-...;--'
CONTAINS
AlTO

SPEClry
Gfl04P 2

~~---------------------------------------y----------------------------------~
NUMBER LOADED INTO THE At

Group 2 (LAW) Operate Instruction Bit Assignments

Figure 1-3

Instruction Word Format

1-10

Fetch (F)

A new instruction is obtained when this state is entered. The contents of the memory cell
specified by the PC are placed in the MB, and the operation code (bits 0-3) of this instruction
word is placed in the IR. The contents of the PC are then incremented by 1. If a single-cycl e
instruction is fetched, the operations specified are performed during the last part of the fetch
cycle; then the next cycle is a fetch state for the next instruction.

If a 2-cycle instruction is

fetched, the succeeding control state is either defer or execute.

Defer (D)
When bit 40f a memory reference instruction is a 1I the defer state is entered following the fetch
state I to perform the indirect addressing. The memory location addressed by the instruction contains
the address of the operand I and access to the operand is deferred to the next memory cycle (execute).

Execute (FJ
This state is established only when a memory reference instruction is being executed. The contents of the memory cell addressed are brought in'to the ~AB; and the operation specified by thl?
contents of the IR is performed.

Break (B)
'Nhen this state is establ ished , the sequence of instructions is broken for a data interrupt or a
program interrupt.

In both cases, the break occurs only at the completion of the current in-

struction. The data break interrupt allows information to be transferred between" core memory
and an external device. When this transfer has been completed, the program sequence is resumed from the point of the break. The program interrupt causes the sequences to be altered.
The contents of the PC and the contents of the I ink are stored in core memory location 0000,
a'nd the program continues from location 0001 .

Tin:'ing
Seven times (designated T1 through T7) occur in sequence during each computer cycl e. At
each time, two pulses are generated, of which one is 40 nsec and the other is 70 nsec wide.

1·-11

ThE~se time pulses cause gating circuits to perform seque'"!tial or synchronized logical or control

opE3rations. The narrow pulses are used for operations where timing is critical, such as the
simultaneous sampling and incrementing of a register; the wider pulses are used to initiate gating
operating where timing is less critical. The intervals between successive pairs of timing pulses
permit gates and registers to settle before any new operation is initiated,. During each computer
cycle, memory reading occurs between times T2 and T3; memory writing starts at time T4 and
occupies the remaining portion of the cycle.

PHYSICAL DESCRIPTION

The basic PDP-7 is housed in three standard DEC metal computer cabinets bolted together to
form an' intergrated console.

In each cabinet, double doors at the front (held closed by mag-

netic latches) provide access to the wiring side of all module mounting panels.

Double rear

doors provide access to a plenum door on which the power supplies are mounted; the plenum
door is latched by a spring-loaded pin at the top.

Opening the pi enum door permits access to

the modules. A fen, mounted in the bottom of each cabinet, draws air through a dust filter
to coot the modu t es. The a irstream passes over the modul es and is exhausted through louvered
openings in the top of the cabinet I at the front.

Four casters permit ralobil ity of the computer.

Figure 1-4 shows the locations of components in the basic PDP-7. Note that the perforated
tape reader and punch are mounted in the center bay above the operator consol e. The Teletype
unit may be mounted on its own stand (suppl ied with the equipment) or may be placed on the
c()nsole table.

For additional physical data, refer to the table of physical data given below,

and to the Installation section of this manual.

SPECIFICATIONS

Physical
Cabinet He ight

69-1/8 inc hes

Cabinet Vlidth

61-3/4 inches

Table Width

68-15/16 inches

Cabinet Depth

33-9/32 inches

Table Depth

19-7/8 inches

1-12

BAY 3

BAY 2

BAY

POWER SUPPLY

C
""l
CD

r---._--..-

738

BLANK

~.
0

SYSTEMS MODULES
MOUNTING PANEL

POWER SllF'Pl Y
728

-0
I

"I
()
0

------_..PO;l;(H SUPPLY

179

INDICATOR PAP~EL

BLANK

8LANK
INDICATOR PANEl

MEMORY LOGIC

AIR BAffLE PANEL

MARGINAL CHECK
PANEL

TRIPLE fAN
MOUNT ING PANEL
(REMOVE.D fOR leK
OR MORE Of
CORE M[MORYI

MEMORY ARRAY
PERfORATED
TAPE
PUNCH

BLANK

8LAII.K

------SYSTEMS MQOUt. £S
MOUNTING fANlL AN~
TELETYPE DHIVER

- -...---BL.ANK OJ( ~o CYCLE
STfPOOWN
1 RAN·;fOHMUI

---_._-----

-0

1--._ _ ... TR,PLE FAPl
... OUNTING PAIIIEL
(k(MQV[O FOR 16K
OR MOHr

CORf MeMORYl

1---- - ---- -.-- - - - - TRIPL£ fAN
MOUNTING PANEL

f---------

ME MORY LOGIC

J
A

-a

---

-D

1A"'E
READER

728

PROCESSOR

lOGIC

'----it-a,_E

(!)

BLANK
POVlE~

CONTROL

8~2

POWER SUPPLY
728

8LANK

- ~

MEMORY
POWER SUPPLY

739

1-----.-

M
~

'---

U
R[AR VIEW

BLANK

::J

CII

BLANK

OPlRATOR
CO,,"SOL£

f--

::J

-o·

::J

r.n

r--

J~
- II
!\ ~'''''''''' \ r
-

POWER SUPPLY

BLANK

I-

--------

-0

BAY 3

I-

778

BAY 2

BLANK
POWER SUPPLY

BAY I

BLANK

OEVICE Sf.LEC10R
ANO I/JlMJAl CO'HROl rUNC liONS lOGIC

c
0

II PEF/fORATED TAPr.
R(ADfR/PUNCH !l
CONTHOl lOGiC
828
POWER
R[CEPTACL(

U
FRONT VIEW

Cabinet Door CI earance

14-7/8 inches at back

Cabinet Weight (3 cabinets)

1100 Ibs

Teletype Height

8-3/8 inches

Teletype Width

18-5/8 inches

Tel etype Depth

18-1/2 inches

Teletype Weight

40lbs

Electrical
Power Requirements

115v, 60 cps, single phase, 17 amp for standard
PDP-7 (can be constructed for 220v or 50 cps
upon spec ial request)

Power Dissipation

2200w

Digital Signal Levels

ground and - 3v

Ambient Conditions
Operating Tempercture

50 to 122 0 F

Operating Humidity

o to 90% re lative hum idity

Storage Temperature

32 to 122 0 F

Storage Hum i di ty

less than 90%

Heat Dissipation

7150 Btu/hr

Functional
Cycle Time

1 .75 tJsec

Word Length

18 bits

Core Memory Size

4096 or 8192 words, expandable to 32,768
in increments of 4096 words.

Instructions

16 basic instructions (13 memory reference
and 3 augmented). The augmented instructions
are microprogrammed to produce more than
1 75 commands.

1-14

64 different devices can be individually

Input/Output Capability

selected and addressed by 3command pulses.

PERTINENT DOCUMENTS

Publications
The following publ ications serve as source material and compl ement the information in this
manual.
1. Digital FLIP CHIP Modules catalog, C-105, printed by DEC. This book
presents information pertaining to the function and spec ifications of the FLIP
CHIP modules and module accessories used in the PDP-7.

2. System Modules catalog, C-100, printed by DEC. This book presents
information pertaining to the function and specifications of the basic system
modules and module accessories used in the PDP-7.

3. Programmed Data Processor-7 Users Handbook, F75~ printed by DeC.
Programming, instruction format, an"d genera I computer function are presented
in this document.

4. PDP-7 Software Package. Perforated program tapes and descriptive
matter for the Program Assembly language {PAL}, utility subroutines, and
t'he maintenance programs {Maindec} are contained in this package prepared
by DEC. The content of the package is listed in Table 1-1.

5. Instruction manuals and Maindec programs for appropriate input/output
devices are prepared by DEC.

6. Technical Manual, Keyboard Send and Receive Sets (KSR), Bulletin 273B
(Vols. 1 and 2). This manual covers operation and maintenance of the Tele~
type unit.

1-15

7. Parts, Model 33 Page Printer Set, Bulletin 1184B. This illustrated parts
breakdown can be used as a guide to disassembly, reassembly, and ordering
parts of the Tel etype un it.
8. Technical Manual, High-Speed Tape Punch Set (BRPE), Bulletin 215B.
This manual covers operation and maintenance of the tape punch unit.
9. Parts, High-Speed Punch Tape Set (BRPE), Bulletin 1154B. This illustrated parts breakdown can be used as a guide to disassembly, reassembly,
and ordering parts of the tape punch un it.
10. Digitronics Perforated Tape Reader Model 2500 manual. This book
covers the installation, use, theory of operation, and maintenance of the
tape reader un it .

TABLE 1-1
Number

PROGRAM LIBRARY
Number

Name

Dig i to 1-7- 1-S

Symbolic Tape Editor

Digital-7-23-10

Dig ita t -7-2 - S

FORTRAN 11 System 8K

Buffered Input/
Output Package

Digital-7-24-10

Assembler - Basic
and Extended

Pen Follow Subroutine

Digital-7-25-10

Character Display
Subroutine

Digital-7-30-A

Floating Point
Package

Digital-7-31-A

Multiply Subroutine

Digitol-7-32-A

Divide Subroutine

Digital-7-33-A

Double Precision
Integer Package

Digital-7-34-A

Unsigned Mul tiply
Subroutine

Digital-7-35-A

Unsigned Divide
Subroutine

Digital-7-40-U

Master Tape Duplicator

Digital-7-3-S
Digital-7-4-S

DDT (Debugging Tape)

Digital-7-10-0

Teletype Output
Package

Dig ita 1-7- 1 1- 10

Tic Toe

Digital-7-12-1

F F Loader

Digital-7-13-1

Readin Mode Loader

Digital-7-14-0

Octal Print Subroutine

Digital-7-15-0

Decimal Integer Print

Digital-7-20-10

. PDP-7 DECtog

Digital-7-21-10

PDP-7 DECtrieve

Digital-7-22-10

PDP-7 DECtape
Subroutine
1-16

TABLE 1-1
Number

PROGRAM LIBRARY (continued)

Name

Digital·-7-41-U

Tape Reproducer

Digital-7-43-U

CAL Handler Type I

Digitol-7-44-U

CAL Handler Type III

Digital-7-45-M

Type 57A Compiler

Digital·-7-50-M

Tel eprinter Input/
Output Test

Dig ita 1-7-51-M

Clock Interrupt
Test Program

Digital-7-52-M

CONTEST II

Number

Name

Digital-7-53-M

Reader and Punch
Test

D igi ta 1-7-54-M

Maindec 401
(Instruction Test)

Digital-7-55-M

Maindec 402
(Checkerboard)

Digital-7-56-M

Maindec 403
(Address Test)

Digital-7-57-M

Maindec 410
(RPB Test)

One copy each of publ ications 3 through lOis suppl ied with each PDP-7 system. Copies of .
items 1 or 2 or additional copies of items 3 through 10 can be obtained from the nearest DEC
district office or from:
Field Service Department
Digital Equipment Corporation
146 Main Street
Maynard, Massachusetts 01754

U. S. A.
Additional copies of items 6 through 9 can be procured from:
Teletype Corporation
5555 Touhy Avenue
Skokie, Illinois 60076
U.S.A.

The engineering drawings I isted in the table of contents are reproduced in Section 11 as an
aid to understanding and maintaining the PDP-7. All the logic diagrams are included, but
schematics are given only for those modules nof' described in the DEC System or FLIP CHIP

1-17

Module Catalogs. A complete set of formal engineering drawings and module schematics is.
supplied separately with each PDP-7 system.

Should any discrepancy exist between the draw-

ings in this manual and those suppl ied with the equ ipment, assume the formal drawings to b~
correct.

ABBREVIATIONS
Listed below are the most commonly used abbreviations of registers, key operations, components,
il1structions, and signal names.

Instruction mnemonics not included in this list will be found in

Appendix 1, Instruction Summary. Signal names not included in this list will be found in
Appendix 3, Signal Glosser}' ~

This appendix contains an alphanumerical I ist of all signal

names which appear on the engineering drawings, together with the number of the drawingo.n
which each signal is generated.
AC

Accumu Iatar

CRY

Carry

ACS

Accumulator Switches

CY or CYC

Cycle

ADDR

Address

Defer {state}

API

Automatic Priority
InterrlJpt

Data Address

DAC

Address Switches

Deposit Accumulator
Contents

Break {state}

DCD

I~D

Bus Driver

Diode-Capac itor- Diode
Gate

I~GN

Begin

Data Information

BK RQ

Break Request

DIV

Divide

Complement

DLY

Delay

CAL

Call Subroutine

Deposit

CHAN REQ

Channel Request

Device Set ector

CHAR

Character

DPN

Deposit Next

CLA

Clear Accumulator

Execute {state}

CLK

Clock

EAE

Extended Arithmetic
Element

CLR

Clear

EMA

CONT

Continue

Extended Memory Address
Register

Central Processor

EMB

Extended Memory Buffer
Register

1-18

EN or ENB

Enable

Output

EPC

Extended Program Counter

OPR

Examine

Operate (class of instruction)

EXN

Examine Next

Overflow

Fetch (state)

Pulse Ampl ifier

FLG

Flag

Punch Buffer Register

HLT

Halt

Program Counter'

Information Coil ector

Program Interrupt

Information Distributor

PIC

Program Interrupt Control

INH

Inhib it

PIE

Program Interrupt Enable

INT RQ

Interrupt Request

POV

Possible Overflow

INVTD

Inverted

PROG

Program

I/OP

Input/Output Pulse

PUN

Punch (tape)

lOT

Input/Output (information)
Transfer

PWR ClK

Power Clock

PWR ClR

Power Clear

Instruction Register

Reader Buffer Register

ISZ

Index and Skip if Zero
(i nstruct i on)

RD FLG

Reader Flag

RDR

Reader

JMP

Jump (instruction)

RPT

Read Paper Tape

JMS

Jump to Subroutine
(instruction)

Request

KBD

Keyboard

RTN

Return

Link

Sense Amplifier

LAC

Load Accumulator

SAD

Skip if Accumulat<:>r Differs

LUI

Line Unit In (Teletype
keyboard buffer)

SEL

Select

SKP

Skip

Special Pulse

STS

Strobe

Switch

SYNC

Synchronize

TAD

Two's Complement Add

Timing Pulse (70-nsec)

Timing Pulse (40-nsec)

LUO

Line Un it Out (Teletype
pr inter buffer)

Memory Address Register

Memory Buffer Register

Multipl ier Quotient
Register

Major States

MUL

~ultiply

1-19

XCT

Execute (instruct ion)

XOR

Exclusive OR

SYMBOLS AND TERMINOLOGY

Digital Logical Symbols
A complete Iist of thedig'ital logic symbols used in the engineering drawings of this manual
ccm be found in Appendix 1 •

Conventions and Notations
Conventions and notations on engineering drawings and in text describing the PDP-7 are used
as follows:

Programming notation for the inclusive OR function.

Programming notation for the exclusive OR function.

Programming notation for the AND function.

Programming notation for an information transfer.

Design notation for the inc lusive OR function and program notation for addition.
Design notation for the AND function.

--+

Design notation for an information transfer accompl ished by a single signal
(used without parentheses).

( )

The contents of a storage device.

C(A) VC(B):#>C(A) The contents of register B are OR combined with the contents of register A

orA V B =>A

and the result is stored in register A.

A2(1)orA~

Bit 2 of register A is the state corresponding to a binary 1, or contains a 1 •

+1-+ A

The contents of register A are incremented by 1 •

O~A

A~B

The content·s of register A are jam transferred into register B.

Other terms used in this manual are defined as follows:
absolute address - a number used directly to specify any memory location.
Twelve bits are required to address 4K, 13 bits to address SK, 14 bits to
address 16K, and 15 bits to address' 32K.

1-20

address of the operand - the location of a core memory register currentl y
containing the operand.
clear - to clear a register is to establish the state corresponding to binary 0
in all bits of that register.
:Iock break - an interruption of the main program, lasting one computer
cycle. During this cycle, a real time clock increments the contents of
memory location 78 by 1. When the clock is enabled by a programmed
instruction, a clock break occurs every 1/60 sec. If memory location 78
c)verflows, the clock flag is set and may cause a program break •
.command - a signal that causes a specific operation to occur as the complete
or partial execution of an instruction or microinstruction.

~yc1e stealing - a suspension of the main program for one computer cycle

caused by the clock break or data break facil ities to effect an operation or
transfer information with ~ore memory.

,data break - an interruption of the main program lasting one computer
cycle. During this cycle an information transfer takes place between core
memory and a high-speed I/O device. The data break is requested by the
I/O device when it is ready for .the transfer, and the break occurs as s~on as
the processor reaches an II instruct ion done" situation.
effective address - the address of the operand as specified by an instruction
word or by an absol ute address.
flag - a fl ip-flop or signal that indicates a specific equipment status or
condition. Flag signals are used to identify an I/O device which requires
servic ing, as. well as for other purposes.

1·-21

instruction - an l8-bit word which is stored in memory and is identified by
a distinct operation code in the four most significant bits. When retrieved
from memory, an instruction word causes specific operations to be performed
by the processor.
microinstruction _. a command to perform a specific operation, identified by
the placement of lIs and O· j in bits of an instruction word other than those
which contain the operation code. Several microinstructions can be combined within a singl e instruction word.

In effect, the entire word is used

as an operation code, and is decoded by gati.ng circuits within the processor
to produce mul tipl e command pulses.
operand - a stored binary number to be operated upon.
program interrupt - an interruption of the main program initiated by peripheral
equipment which requires servicing. When the processor reaches an lIinstruction done" situation, control of the processor is transferred to a subroutine
which identifies the interrupting device. The transfer of cor-trol takes place
during the break cycle. After the interrupting device has been identified,.
a further subroutine services it and then transfers control of the processor back
to the main program.
set - to set a flip-flop is to establ ish the state corresponging to binary 1 •
subroutine - a series of stored instructions which is not part of the main program but may be reached by means of a JMS instruction. A subroutine may
contain instructions that service peripheral equipment, or instructions for
an operation that must be repeated many times. At the conclusion of a subroutine, control of the processor may be returned to the main program.

1-22

CHAPTER 2
LOGIC

FUNCTIONS

Both manual and programmed operation of the PDP-7 are required for the performance of any
complete task. Manual operation is normally limited to the following: storing a br.ief loader
program; modifying or exam ining data or addresses in a program that is already stored; or
establishing the starting conditions for programmed operation. In programmed operation, data
and the sequence of 'instructions which constitutes the program are loaded into the core memory;
the starting address of the program is manually established; and the computer is manually started.
The computer then successively executes the instructions specified by the program.

For main-

tenance purposes and to facilitate debugging, provision is made for advancing the program one
cycle at a time or one instruction at a time.
This chapter describes the sequence of events that takes place during each of the manua I operations or instructions that the PDP-7 can perform. Reference is made throughout the descriptions
to the flow diagrams.

FLOW DIAGRAM INTERPRETATION
Two flow diagrams are provided: one, contained in engineering drawing 20, shows the events
that take place during each of the possible manual operations; the other, contained in engineering drawing 21, shows the events that tak~ place during the execution of progra,mmed instructions. The two flow diagrams are sim ilar in their arrangement. At the extreme left are shown
the timing pulses which initiate events at various times in the cycle.

In the flow diagram of

manual operations, these timing pulses are designated KEY MANUAL and SPO through SP4.
In the flow diagram of programmed operations, the timing pulses are designated T1 through T7.
Times (in ~sec or nsec) appearing in boxes that straddle the horizonta I boundary Iine separating
two timing pulses represent the time interval that elapses between the occurrence of those two
pulses.
Events initiated by a specific timing pulse are shown in rectangular boxes placed between the
boundary I ines associated with that pulse.

It is important to note that all such events are

2·-1

initiated simultaneously by the timing pulse if they form part of the event sequence. For example, in following the deposit (DP) sequence on engineering drawing 20, at time SP2 the
event AS 1 - PC is followed in the sequence by DAC - IR and ACS 1- AC. The vertical separation
does not imply that the AS 1- PC operation precedes the other two; on the contrary, they are
all initiated simultaneously. The vertical separation merely facilitates,the illustration of branches
to other possible sequences.
Events in a sequence which is not specifically designated by a key name or instruction name
are assumed to be common to all sequences (e.g., O-MA at time SP1, engineering drawing 20).
Where a common sequence branches into two or more.sequences, depending on the operation in
progre~s,

the operation associated with a given sequence is identified immediately below the

branch. For example, at time SP2 the event AS1- PC occurs in a sequence common to both
examine (EX) and deposit (DP) operations. The sequence then branches; if an examine operation
is in progress, pulse S P2 initiates the event LAC- IR, but if a deposit operation is in progress
LAC -IR does not occur; instead, pulse SP2 initiates events DAC- IR and ACS1-IR. Similarly,

several separate sequences may be followed by a common sequence. Thus, on engineering
drawing /0, each or the separate sequences associated with the START, CONTINUE, EXA!',1INE,
and DEPOSIT operations 'is followed by the event 1- TP1 which takes place at time, SP4.
~~ote that some of the events specified in the rectangles of the flow diagram are unconditional;

that is, they invariably occur at the specified time when the operation with which they are
associated is in progress. Thus, when the START key is pressed, the event AS 1 - PC always
takes place at time S P2. Other events are conditiona I upon the state of control fl ip-flops or
r,eg ister bits. Conditiona I events are represented in the rectangl es by a statement of ,the requ ired
condition which is separated from the conditional event by a colon. Thus, at time SP2 of a
read-in operation (engineering drawing 20), the statements in the rectangle indicate that if
the read paper tape (RPT) fl ip-flop is in the 0 state, the contents of the address switch reg ister
eire transferred to the PC (RPT (0): AS1- PC). However, if the RPT flip-flop is in the 1 state,

1! is added to the contents of the PC and the operation code DAC (deposit content of accumulator
in specified memory cell) is set into the instruction register (RPT (1): + 1- PC DAC-IR).
()n engineering drawing 21,

the seven time pulses that occur during each computer cycle are

shown at the left. The column immediately ·to the right contains the events as~ociated with

2-2

memory which occur during every computer cycle, regardless of the maior control state estabIished. Certain conditional events, whose occurrence is dependent on factors other than the
major state, are also contained in this column designated Events Common. The other events
on this drawing are grouped according to the major state established.

Each major state (fetch,

defer, execute, and break) lasts for one computer cycle. All programmed instructions start
in the fetch state.
The exact mechanism by which the CP performs a function specified by an event shown on the
flow diagram is found by referring to the appropriate engineering logic diagram and the corresponding circuit description. When tracing a transfer function, it is best to begin by examining
the input and control gating of the register to which the transfer is being made. Thus, to trace
the function AS 1- PC, first exam ine the logic diagram of the PC; it will be found that a set
of input gates is triggered by a pulse designated AS1- PC. To find out how this pulse is generated, examine the logic drawing of the PC control. When there is doubt where a pulse or
level is generated, consult Appendix 3. This Clppendix I ists all command pulses and control
levels in alphanumerical order of their designations, together with the number of the engineering
logic diagram on which ere shown the circuits which gene:-cte any given signal.
NOTE: It is very important that maintenance personnel familiarize
themselves as soon as possible with the flow diagrams of manual
operations, C P operations, and EAE operations. These flow diagrams
hold the key to an understanding of system operation and provide
much information that is valuable when troubleshooting.

PRELIMI NARY OPERATIONS
C ircu it protection and primary control of a II power entering the computer is governed by the
circuit breaker mounted on the 2-step power control unit located at the rear of the cabinet.
Manual control of primary power is governed by the lock switch and POWER switch located on
the console panel. With the lock switch in the unlocked position, turning on the POWER
switch energizes a relay in the power control unit, which, in turn, energizes the computer
logic power supply immediately. A second relay in the power control unit imposes a delay of
5 sec before the memory power supply is energized. This delay ensures that all ac transients
in the computer have completely decayed before the memory is energized. Similarly, when

2--3

the POWER switch is turned off, the memory power suppl ies are deenergized immediately; and
the computer logic power is maintained for 5 sec longer. In each case, the delay ensures
that switching transients cannot cause current surges which would destroy information stored
in the core memory.
[)uring the 5-sec turnon delay period, an integrating circuit enables a variable clock. While
the clock is enabled, it emits standard negative pulses at a repetition rate of 200 kc. These
PWR C lK {power clock} pulses repeatedly clear the RUN and memory control fl ip-flops and
trigger "two NAND gates, which are enabled by the 0 condition of the RUN flip-flop. The
output pulses from the gates trigger two pulse amplifiers, which produce the PWR ClR NEG
{power clear negative} and PWR ClR POS (power clear positive) pulses. These PW~ ClR pulses
ore supplied to the interface to establish initial conditions in peripheral equipment. Thus, if
clny flip-flops are set by switching transients during the first 5 sec after power turnon, they are
immediately cleared by the PWR ClK or PWR ClR pulses. This establishes correct initial conditions and ensures that a stored program cannot be accidentally started or disturbed.
The lock switcn, in its uniocked position, connects ell ~h£: console keys and switches to the

-15v supply, thereby permitting them to generate the levels required to start the computer
,and to perform manual operations. When a program has been started manually, the lock switch
may be turned to its locked position. This grounds all the console keys and switches to prevent
manua I interference with the program. A second deck of the lock switch bypasses the POvVER
switch, so that power cannot be acc identa Ily turned off whi Ie a program is runn ing.

MANUAL OPERATIONS
Keys and switches on the operator console have three functions: they permit information to be
stored in core memory; they permit the contents of a specified core memory cell to be displayed
for visual exam ination; and. they perm it the execution of a program to be started and stopped.
Operation of the START, CONTINUE, EXAMINE/EXAMINE NEXT, DEPOSIT/DEPOSIT NEXT,
or READ-I N keys generates the KEY MANUAL level transition to start the special pulse generator. The special pulse generator produces five tim ing pulses, designated S PO through S P4,
which initiate a II functions performed as p~rt of a manual operation. All five keys cause the
RUN flip-flop to be clecred at time SPO in order to stop any operations already in progress.

2-4

(Note that although it is not logical to press the START key when a program is running, it
could be accidentally pressed and must therefore be made to stop current operations.) After
the clearing of the RUN flip-fiop, there is a 10-jJSec pouse to allow the completion of any
EAE operations in progress. Thereafter, the sequence of operations depends upon which key
was operated.

The START key initiates execution of a program which has been loaded into memory. After
starting the special pulse generator and clearing the RUN flip-flop, the key causes the fol, lowing events to take place:
1. At time S Pl, the memory address reg ister (MA) is cleared in preparation
for entering the starting address of the program from the ADDRESS switches.
A complete clear is required, because only binary l's are transferred to the

MA.
2. At time SP1, a BGN pulse is generated wh;ch clears the instruction
register (lR), the read paper tape (RPT) and other special mode flip-flops,
and establishes initial conditions in the registers of I/O devices. The multistate device of the ma jor state generator is forced into the fetch state in
preparation for extracting the first programmed instruction from memory,
and the program counter (PC) is cleared.
3. At time SP2, binary l's of the starting address preset on the ADDRESS
switches are transferred into the PC.
4. At time SP3, the RUN flip-flop is set to the 1 state, thereby conditioning
a NAND gate between the special pulse generator and the main timing chain.
Timing pulse SP4 triggers this gate and causes the main timing chain to generate tim ing pu Ise T1. Thereafter, the C P operates under control of tim ing
pulses generated by the main timing chain and successively executes programmed instructions until the RUN fl ip-flop is set to the 0 state.

2-5

CONTINUE Key'
The CONTINUE key causes the CP to continue execution of a program after a temporary hal,t.
Pressing the key clears the RUN flip-flop during SPO and the MA during SP1. Since a halt
may take place at the end of any memory cycle, the CP must continue with the type of cycle
that was predeterm ined by the cycle in which the ha It was requested. Thus, the only further
action required by the CONTINUE key is to set the RUN flip-flop to 1 at time SP3 and to
cause timing pulse SP4 to initiate operation ofthemain timing chain. The CP then continues,
execution of the program from the point at which it was halted.

STOP Key
The STOP key provides a means of halting a program at the conclusion of a memory cycle.
Pressing the key conditions a gate which is triggered at time T5 of ,the memory cycle. The
output pulse produced by the gate clears the RUN flip-flop, thereby preventing timing pulse
lPlfromre-entering the timing chain to initiate a new cycle. The CP, therefore, halts at the
conclusion of the memory cycle during which the RUN flip-flop was cleared.

DEPOSIT/DEPOSIT NEXT Key
Ihe DEPOSIT/DEPOSIT NEXT key, when momentarily set to DEPOSIT, causes a binary number
that has been preset on the ACCUMULATOR switches to be deposited in the memory cell specified

by the ADDRESS switches. When momentarily set to DEPOSIT NEXT, the key causes a binary
number preset on the ACCUMULATOR switches to be deposited in the memory cell specified by
the PC. Setting the key to DEPOS IT clears the RUN flip-flop at time SPO and the MA at time
SP1. A memory cycle which will perform the operation is then initiated as follows:
1. At time SP1, a BGN pulse is generated to clear special mode and· I/O
device flip-flops; .the PC is cleared; and the major state generator is forced
to the execute state.

(Refer to the key function flow diagram on engineer-

ing logic diagram 20.)
2. At time SP2, the binary lis contained in the ADDRESS switches are transferred to the PC. Then the binary lis contained in the ACCUMULATOR
switches are transferred to the accumulator register (AC), and the operation
code for DAC (deposit AC) is set into the IR.

2-6

:~.

At time SP3, the contents of the PC are transferred into the MB. This

step is necessary because after time SP4, the processor will enter an execute
<:ycle in which the contents of the MB are transferred to the MA at time T1 •
The fact that the status of the Iink, trap flag, and extend mode are also set
into the MB is of no importance in a deposit operation, because those bits
of the MB are not sampled by the MA.
4. At time SP4, the contents of the PC are incremented by 1 to facilitate
a further manual operation at the next location after completing the deposit
operation. Timing pulse SP4 then starts the main timing chain.

Note, how-

ever, that the RUN flip-flop remains in the 0 state, and that in consequence,
the CP will halt at the end of the execute cycle.
5. At time T1 of the execute cycle, since this is not a CAL (call subroutine}
fnstruction, the contents of the MB are transferred to the MA (C P flow diagram,
engineering logic diagram 20).
6. At time T3 of the execute cycle, the contents of the AC are transferred to
the MB; and during the remaining portion of the cycle, this data is written
into. the specified memory cell. Since the RUN flip-flop is not set, the CP
'halts after time T7, and the deposit operation is complete.
Setting the key to DEPOSIT NEXT causes the CP to perform an operation that is almost identical
to a deposit operation. The difference is"that the PC is not cleared at SP1, nor are the contents
of the ADDRESS switches set into the PC at time SP2. The number preset on the ACCUMULATOR
switches is therefore deposited in the memory cell specified by the PC instead of by the ADDRESS
switches.

Note that the contents of the PC are incremented at time S P4. Therefore, after an

initial deposit operation, use of the DEPOSIT NEXT position causes deposits to be made at
consecutive memory locations without resetting the ADDRESS switches.

EXAMI NE/EXAMI NE NEXT Key
The EXAMINE/EXAMINE NEXT key, when momentarily set to EXAMINE, causes the contents
of the memory cell specified by the ADDRESS switches to be transferred to the MB cmd AC.

2-7

When the transfer is complete, the contents of the MB, -MA, and AC may be visually checked

by means of the associated indicator lamps.
The MB and AC contain the contents of the specified memory cell; the MA contains the address
preset on the ADDRESS switches; and the PC contains the address of th~ next consecutive memory cell. Thus, a number of consecutive memory cells may be examined without resetting the
ADDRESS switches between each operation. When momentari Iy set to EXAMI NE NEXT, the
key causes the contents of the memory cell specified by the PC to be transferred to the AC for
visua I exam ination.
Setting the key to EXAMINE clears the RUN flip-flop during time state spa and the MA at time
SP1. A memory cycle which will perform the operation is then initiated as follows:
1. At time SP1, a BGN pulse is generated to clear special mode and I/O
device f1 ip-flops; the PC is cleared; and the major state generator is forced
to the execute state. (Refer to the key function flow diagram on engineering
logic diagram 20.)
2. At time SP2, the address specified by the ADDRESS switches is transf~rred
to the PC, and the operation code for LAC (load AC) is set into the IR.
3. At time S P3, the contents of the PC are transferred to the MB. {This step
is necessary for the reason stated under DEPOSIT/DEPOSIT NEXT Key, No.3.}
4. During time state SP4, the contents of the PC are incremented by 1, and
timing pulse SP4 starts the main timing chain.
5. At time T1 of the execute cycle, since the instruction is not CAL, the
address contained .in the MB is transferred to the MA, and the AC is cleared.
6. At time T3, the contents of the addressed memory cell are read into the
MB, and an XOR (exclusive OR) operation is performed on the MS and AC.

Since the AC was previously cleared, this results in a direct transfer of the
contents of the MB into the AC, where they are available for vis~al examination.
Since the RUN fli'p-flop is not set, the CP halts at time 17, and the EXAMINE
operation is complete.

2-8

Setting the key to EXAMINE NEXT causes the CP to perform an operation which is almost
identical to an EXAMINE operation. The difference is that the PC is not cleared at time
SP1, nor are the contents of the ADDRESS switches set into the PC at time S P2. The word
loaded ini'o the AC for examination is therefore brought from the cell specified by the PC
instead of by the ADDRESS switches.

Note that the contents of the PC are incremented at

time SP4 1"0 permit examination of consecutive locations without resetting the ADDRESS switches.

REPEAT Switch
Turning on the REPEAT switch causes the C P to repeat the operation specified by one of the
manual kE~Ys, at intervals determined by the setting of the SPEED controls on the console panel,
for as long as the key is held down. After completing a DEPOSIT or EXAMINE operation, use
of the REPEAT switch in conjunction with a DEPOSIT NEXT or EXAMINE NEXT operation permits deposition in, or examination of, successive memory cells without specifying each address.
Turning on the REPEAT switch causes timing -pulse SP4 to trigger a one-shot which produces a
delay. The length of the delay is adjustable by means of the coarse and fine SPEED controls
on the operator console. When the one-shot reverts to its stable state, the level transition
that appears at the output term ina I is appl ied to the spec ia I pulse generator and in itiates time
state SPO once more. The CP then repeats the operation associated with the manual key that
is pressed.

READ-IN Key
The READ-IN key permits information punched in binary format on paper tape to be loaded
into memory at successive memory locations, starting at the address specified by the ADDRESS
switches. When in the binary mode, tape holes 1 through 6 of each, Iine of tape contain onethird of an l8-bit word; hole 7 is not punched unti I the last Iine of the last character that is
to be read, and hole 8 is always punched to cause the line to be read. When the READ-IN
key is pressed, the processor selects the reader in binary mode, then waits for the reader to
read three Iines of tope and assemble these in the reader buffer in the form of an l8-bit word
(and a Iso waits unti I the READ-l N key is released). When the reader buffer is fu II, its contents
.are transferred to the AC and then deposited in memory. The process of reading three Iines of
tape, assembl ing the information into an la-bit word, and depositing words at consecutive

2-9

memory locations continues until the reader encounters a Iine of tape in which hole 7 is punched.
The reader then stops and the processor executes the last 18-bit word read and deposited {th~
hc)le 7 being in the last line of this word}.
Pressing the READ-IN key causes the RUN fl ip-flop to be cieared at time SPO and the MA

to be cleared at time SP1. The following sequence of events then tokes place:
1. At time SP1, a BGN pulse clears the special mode flip-flops, including
the RPT (read paper tape) fl ip-flop to establ ish initial conditions. The PC is
cleared, and the rna jor state generator is fdrced to the execute state.

2. At time SP2, the address specified by the ADDRESS switches is set into
the PC, and the operation code for DAC is set into the IR.

3. At time S P3, the RPT fl ip-fl op is set to 1.

4. At time SP4, the AC is ~cleared and the contents of the PC are transferred
to the MS. At th is time a command is generated that selec~s the reader in
binary mode and causes it to read three I ines of tape successively into the
reader buffer. When the reader buffer is full, the reader flag is set to 1 •

5. The processor now waits for three conditions to be fulfilled:
a. The RPT flip-flop is in the 1 state (this condition was fulfilled
at time S P3).

b. The reader flag is set to 1 (indicating that the reader buffer
is full).
c. The READ-I N key is released.

If the processor were not forced

to wait for this condition to be fulfilled, the rapid action of the
reader might cause several words to be deposited at the starting
address, with consequent loss or inval idation of information.

of these three conditions- are combined in

The levels representing assertion

2-10

(1 gate; whichever of the three conditions is fulfilled

last causes a level

transition to occur at the output of the gate. This transition starts the main
timing chain and initiates a computer cycle in the execute state.

6. The events in the execute cycle follow the pattern already described
for a deposit operation. However, the CP does not stop at time 17 because
timing pulse TP7, combined with the 1 state of the RPT flip-flop, causes
the generation of tim ing pulse SPO of a second readin operation • However,
the RUN fl ip-flop is cleared at time SPO.

7. At time SPl of a second (or subsequent) readin operation, no BGN pulse
is generated, because the READ-I N key has been released.

Further, since

the RPT flip-flop remains set, the PC is not cleared at time SPl and the
contents of the ADDRESS switches are not transferred to the PC at time S P2.
Instead, the contents of the PC are incremented by 1 at time SP2. Thus,
la-bit words transferred from the reader buffer to the AC are deposited at

consecutive memory locations.
8. When the reader encounters a line of tape which has hole '7 punched, the
assertion level produced by hole 7 causes the RPT fl ip-flop to be cleared cmd
the RUN fl ip-flop to be set at time T5.
9. At time T7, since the computer is in the execute state and the RUN fl'ipflop is set, timing pulse TP7 forces the maior state generator to the fetch state
and restarts the main timing chain. At time Tl of the ensuing fetch cycle, the
contents of the PC are transferred to the MA. Therefore, since at that time the
PC conta ined the memory address of the last word read from paper tape, the
processor executes that word. The word may be any instruction, but sensible
choices for the programmer would be either a HLT {halt} instruction to allow
manual control of the program before starting or a JMP (jump) instruction that
would provide entry to the start of the program.

SINGLE INSTRUCTION Switch
The SINGLE INSTRUCTION switch, in combination with an F SET level ("instruction done"
situation), generates a RUN STOP signal that resets the RUN flip-flop and halts the CP at the

end of the current memory cycle. However, the F SET ("instruction do~n) 'eveJ is generated

only during the cycle that completes the execution of an instruction and does not appear during
a fetch or defer cycle which must be followed by an execute cycle • .Thus, when the SINGLE

It.JSTRUCTION switch is turned on, the CP halts after completing each instruction; and the
nc~xt instruction must be initiated

by pressing the CONTfNUE key.

When the SINGLE STEP

and SINGLE INSTRUCTION switches are both turned on, the SI NGlE STEP switch takes precedence; and the CP halts after each memtny cyc'e.

PROGRAMMED OPERATIONS
The normal mode of PDP-7 operation is the execution of programmed instructions.

~ro9rammed

operation can be modified by a program interrupt {produced by peripheral equipment to trans-

fer contrel of the CP from the main program to a subroutine}. The main program can also be
temporarily interrupted by means of a data break or a clock break. Ouring a data break,
lesting one memory cycle, a high-speed peripheraJ device, which has a 15-bit address-register
CIS well

as an la-bit data register, can transfer information to or from memory. During a clock.

break, also lasting one memory cycle, a real-time clock may add 1 to the -contents of memory
location 7. If on overflow occurs, a program break is_ initiated; otherwise, the main program is
resumed.
When a program is to be executed, the starting address of the program is preset on the ADDRESS
~iwitches, and the START key

is momentarily pressed.

The CP thereupon fetches the first

'instruction from the specified address and executes it, at the same time adding 1 to the contents
lof the PC.

Succeeding instructions are obtained from numerically consecutive memory locations,

unless a JMP or JMS instruction changes the contents of the PC so that instructions are obtained
from another block of numerically consecutive locations in a different section of memory.
Programming is simplified and memory space is conserved if the programmer arranges the instructions for some operation that must be performed many times during the course of the progr~m
in the form of a subroutine. A subroutine i's c group of instructions contained in a numericaJ!y

2-12

consecutive block of memory locations that do not form part of the main program sequence.
These subroutines may be entered from any part of the main program by means of a JMS (iump
to subroutine) instruction which stores in memory the location of the next main program instruction (that is, the contents of the PC). The next instruction to be executed is the first instruction of the subroutine. Exit from the subroutine and return to the main program sequence is
obtained by means of a JMP I (jump indirect) instruction, which directs the CP to the location
containing the next main program instruction and causes the instruction found in that location
to be executed.

Instructions
The following explanations of the functions performed during the execution of each instruction
assume thcJt the PDP-7 is energized and is operating normally and that the address of the next
instruction to be performed is held in the PC. Therefore, each instruction explanation begins
at the start of the fetch cycle.
The instructions performed by the PDP-7 are of two kinds: memory reference instructions and
augmented instructions. A memory reference instruction contains an operation code in bits 0
through 3, and the location in memory of the word upon which the operation is to be performed
in bits 5 thro~gh 17. If bit 4 is a 1, it is an indication that the address contained in t_he instruction word is not that of the operand itself, but is the location containing the address of the
operand. Th is facil ity is known as indirect addressing.

Indirect addressing has many uses; for

example, it may be used with a jump inst~uction to permit re-entry into the main program from
a subroutine; it permits a memory location outside the current 8K field to be addressed when
the extend mode is enabled; and it permits a programmer to gain access to an operand whose
absolute address is determined by the program itself but is known to be contained in a specific
memory location.
An augmented instruction requires no reference to memory. An operation code in bits 0 through
3 identifies the instruction as an OPR/LAW, lOT, or EAE instruction. The contents of the
remaining bits specify operations to be performed by timing pulses T5 1 T6, and T7 during a single
computer cycle. More than one such microinstruction may be combined into a single instruc_-tion provided that there is no logical confl ict between the operations specified.

2-13

The following paragraphs describe·the memory referenc~ instructions first and then the augmented
instructions. The load accumulator (LAC) and operate (OPR) instructions are described in
detail, as representative of the memory reference instructions. and augmented instructions,
respectively. Remarks on the remaining instructions are confined to important points that may
not be obvious from the flow diagram. All of the explanations assume that direct addressing is
employed (bit 3 contains a 0). An explanation of the use of the auto-indexing locations and of
the use of a defer cycle. to permit indirect addressing follows the descriptions of the memory
reference instructions. The descriptions of both memory reference and augmented instructions
also assume that no I/O device has requested a break of any kind. The conditions under which
a break may_ be granted and the events that take place during the ensuing break cycle are described-after the explanation of the augmented instructions.

Memory Reference Instructions

~.oad Accumulator (LAC) - The LAC instruction is a memory reference instruction which requires

a fetch cycle and an execute cycle. During the fetch cycle, the address of the LAC instruction is trunsferred from the PC to the W\A, and the contents of the PC are incremented by J.
A read operation transfers the contents of the memory cel i addressed into the MB and bits 0

through 3 are transferred directly into the IR as the operation code of the instruction to be exe:cuted. The contents of the MBare then re·written into the memory cell from wh ich they were
read. Finally, the major state generator is set to the execute state. During the execute cycle,
the operand is extracted from memory and loaded into the accumulator. The following detailed
description of the sequence should be read wh ile referring to the flow diagram and to the specified engineering logic diagrams.
At time T1 of any fetch cycle, the instruction register must be cleared. The F level is NAND
combined with the T1 pulse (B5/ 24); and the gate output, after amplification an:! inversion,
iis applied to the direct clea'r inputs of the four IR fl ip-flops.

(In a simi lor manner, the lR is

cleared at time T1 of a break cye Ie and at time T2 of certain execut n . cycles. The IR is not
cleared during a defer cycle.) Also at time Tl, the F negative level is NAND combined
with the T1 pulse (A7, 25) to produce a PC 1- MA pulse. This pulse is appl ied to a set of MA
input gates (29) and opens those which are ~Iready conditioned by a negative level from a PC

fl ip-flop in the 1 state.
2-14

Note that the PC1- MA pulse is applied only to bits 5 through 17 of the MA register. Bits 3
and 4 of this register are used only in coniunction with memories of 16K capacity or more
and must receive a separate transfer puls~ (EPC 1- EMA) from the memory extension control
unit. The F level and T1 pulse are also NAND combined in the PC control logic (C6, 25)
to produce a +1- PC pulse which increments the contents of the PC by 1. The +1- PC pulse
complements bit 17 of the PC register (08, 29), and is also applied to a gated pulse amplifier.
If this gate was already conditioned by a ~17 (1) level, a carry pulse complements bit 16.
The carry is propagated toward bit 5 by a series of gated pulse amplifiers and stops when it
first encounters a bit in the 0 state. The flip-flops have a controlled internal delay so timed
that the MA input gates open and close before the incrementing pulse causes any fl ip-flop to
change state. It is this internal delay which permits the PC register to be sampled and incremented by simultaneous pulses without transferring the incremented, rather than the original,
contents to the MA.
At time T2 of every computer cycle, the MB is cleared and a read operation is prepared. Time
pulse T2 is applied to an isolating gate (B3, 25), and the output of the gate causes a pulse
..Jmplifier to produce the O-PC pulse. The TP2 pulse sets the READ flip-flops of the memory
control (27) to 1 and is NAND combined with the MA4,(0) level to produce the TP2 • SEL 0,1
pulse (A8, 27).

Note that the MA4 bit is always 0 unless more than 8K of memory capacity

is in use. The MA5 bit is decoded by the memory control to produce either a SEL 0 or' a SEL 1
level which is used to select one of the two 4K memory stacks in the standard 8K field. The
SEL level is combined with the 1 output of the READ flip-flops to produce an appropriate SEL·
READ LEVEL I which is appl ied to memory. The action of the memory is discussed in detai I
in Chapter 4. The effect of the SEL and SEL • READ levels is to enable the half-select X and
Y read circuits in memory. The TP2 • SEL 0, 1 pulse is applied to a delay network in memory
to produce a strobe pulse which is applied to the sense amplifiers of the memory. This strobe
pulse clears the READ 2 fl ip-flop and is returned to the main tim ing chain as the STB RT N
pulse, which initiates the generation of T3 and clears the READ 1 flip-flop.
When the strobe pulse occurs, the memory sense amplifiers compare the signal level in the sense
winding of each core plane with a reference level. In planes where coincident read currents
have caused a core in the 1 state to change to the 0 state, the sense signal is greater than the
reference level; and the associated sense amplifiers (SA) produce standard negative pulses •

. 2-15

These SA pulses are appl iedto the" MB input gates (30) and set the corresponding MB fl ip-flops.
The SA -MB input gates are normally enabled by an MB STS INA negative level generated in
thE~ MB control (25).

Thus, the contents of the addressed memory cell are transferred to the MB

unless the gates are specifically inhibited by the control logic. The conditions under which
inhibition occurs are discussed in Chapter 3 under the head inq of Memory Buffer Register Control.
During a fetch cycle, when the MB is loaded with an instruction word consisting of an operation
code and the address of the operand, the four most significant bits (which contain the operation
code) are transferred directly into the IR,as well as into the MS. The negative pulses from
sense amp I ifiers SAO through SA3 are appl ied to lR input gates that are conditioned by the
fetch level (B7, 24), and set the IR fl ip-flops accordingly.
After the strobe pulse has occurred, the contents of the various registers are as follows:
ADDRESS switches

Z (address of the first instruction, which
in this example is LAC Y)

Z+l

MBO through MS3 contain octal 20 (= LAC)
MB4 (0) (= no indirect address)
MB6 through MB 17 contain Y (address of operand)
t

IRO through IR3 contain octal 20 (= LAC)

In the instruction reg ister I the states of IRO (0) and lR 1 (1) are decoded to produce an IA 1 leve I
and a IA3 level. The states of IR2 (0) and IR3 (0) are decoded to produce an IBO level. The

rA3 level, which identifies the instruction as a memory reference instruction, is NAND combined with the existing fetch (F) and MB4 (0) levels (C 1, 24) to establ ish a SET level. This
ground level conditions the DCD gate (B3, 24) associated with a pulse ampl ifier which sets
an execute (E) state into the major state generator at time T7. At the same time the ground
level disables input L of module J21 to prevent any break request from being granted until the
instruction has been executed.
At time T4, timing pulse TP4 sets the INH flip-flop of the memory control logic (C6, 27), thereby
e:nabling the inhibit supply of the memory. At time T5, both WRITE flip-flops are also set and,
iln conjunction with the SEL 0 level, establ ished coincident writing currents through the cores

2-16

of memory cell Z. All cores of the addressed cell are driven by full-select write currents.
However, those in planes which correspond to MB bits containing a 0 are inhibited from changing state by a half-select inhibit current in the read direction. Thus, the contents of the MB
are writtel' back into the cell from which it was read.
At time T6, timing pulse TP6 resets the WRITEl, WRITE 2, and INH fl ip-flops. The writing
operation is now complete.
At time 17, timing pulse TP7 INVTO is applied to the OCO gates of the major state generator
(24) and, in combination with the E SET level established during T3, sets the execute (E) state.
The RUN flip-flop is still set, and the RUN (1) level is NANO combined with timing pulse T7
(AS, 25) to produce a O-MA pulse which clears all the flip-flops of the MA. The RUN (1)
level is also combined with a SLOW CYC (not slow cycle) level to condition a OCO gate at
the entry to the main timing chain (D1, 22). The TP7 pulse (delayed 150 nsec) is combined
. with a STOP CP TC {not stop central processor timing chain} level which signifies thc:Jt the
extended arithmetic element does not require an interruption. The resulting pulse triggers the
nCD gate and energiz~s a pulse ampi ifier (02, 22). The output of this pulse ampl ifier caus.as
the generation of timing pulse TP1, thereby initiating the second (execute) computer cycle.
At time Tll of ~he execute cycle, the absence of an lAO signal at terminal S of module. 05
(C 1, 25) results in the production of a CAL (not CAL instruction) level. This level is NAND
combined in the MA control (A7, 25) with the T1 timing pulse and another negative level
resulting from the absence of a defer (D) I~vel .. The output of the NAND gate is applied to
a pulse amplifier which produces an MB1- MA pulse. This pulse opens all MA input gates
which are already conditioned by a negative level from an MB fl ip-flop in the 1 state; thus
the address of cell Y (containing the operand) 'is set into bits 5 through 17 of the MA. The (E)
level of the major state generator is NAND combined with the lA 1 level produced by the IR,
and the output of the gate is inverted to produce an E • IA 1 level (02, 26). The E " IA 1 level
is NAND combined with the IBO level and inverted to produce an E • LAC level. The E • LAC
level enables a NAND gate which is opened by time pulse T1 to trigger a pulse amplifier in the
AC control logic (A6, 26). This pulse amplifier produces a O-AC pulse which clears all the
fl ip-flops of the accumulator.

2-17

During the execute cycle, the contents of memory cell Yore read into the MB and then rewrittEln into memory in exactly the same manner as for cell Z (during the fetch cycle). Therefore,
the following paragraphs describe only those events pecul iar to the execute cycle. After the
strobe occurs, the contents of the various registers are as follows:

Z+l

Contents of cell Y

Octal 20 (= LAC)

All zeros

At time T3 of the execute cycle, the E • IA 1 level is combined with the T3 timing pulse. The
resulting pulse is appl ied to pulse ampl ifier PA2 of module H2 in the AC control logic, and
the output of the pulse ampl ifier is an XOR - AC pulse. This pulse is appl ied to a set of accumulator register input gates which are normally used to complement the accumulator in on
exclusive OR operation. However, since the accumulator was cleared at time T1 (of the execute cycle), no carry pulses can be generated; and tht effect is a simple transfer of mcm~r}{
buffer l's into the corresponding bits of the accumulator.
After the operand has been rewritten into memory cell Y (starting at time T4) the MA is cleared,
ClOd the interrupt control is interrogated to determ ine the state to be set into the rna jor state
~Jenerator for the next cyc Ie.

If any I/O device has initiated a break request, the interrupt

control log ic (32) establ ishes a negative BK RQ (break request) level wh ich is appl ied to
terminal K of module H20 in the major state generator. Then, provided that neither a D SET
nor on E SET level has previously been establ ished by the nature of the instruction, a B SET
oround level appears at terminal N of the module. This level, in combination with timing
pulse TP7 I NVTD, sets the rna jor state generator to the break (B) state so that the i/O device
may be serviced.

If there is no break request, the BK RQ combines with D SET and E SET

~evels to produce an f SET level; and, at time T7, a new fetch cycle is initiated to extract
\

~he next instruction from memory address Z+ 1.

Note that a break request is never granted un-

til the current instruction has been executed. Thus, a break can be granted only after comple1~ion of a 1-cycle instruction; after the execute cycle of a multicycle instruction; or after a

break cycle to continue a block transfer or other operation involving several break cycles.

2-18

Exclusive OR (XOR) - The exclusive OR logical operation is performed between the contents
of the AC and the contents of the MB and req~ires a fetch cycle and an execute cycle. During
the fetch cycle, the operation code 24 is set into the IR; arid the address of the operand is set
into bits 5 through 17 of the MB. At time T1 of the execute cycle, the address of the operand
is transferred from the MB to the t-M.. At time T2, the MB is cleared; and a read operation set~
the operand into bits 0 through 17 of the MS. The E negative level of the major state generator
is NAND combined in the AC control with the IA 1 negative level produced by the IR decoder.
The resulting E • IA 1 negative level is combined in the AC control with timing pulse T3 to produce a negative XOR-AC pulse. This pulse opens AC input gates already conditioned by MS
bits in the 1 state and complements the associated AC bits. When the AC has previously been
cleared (as in the LAC instruction), the XOR -AC command can be used for a simple transfer
of binary l's from _MB to AC.

One's Complement Add (ADD) - The ADD instruction adds the contents of the MB to the con-

tents of the AC in l's complement arithm~tic and requires a fetch cycle and an execute cycle.
,During the fetch cycle, the operation code 30 is set into the IR; and the address of the operand
is set into bits 5 through 17 of the MB. At time T1 of the execute cycle, the address of the
operand is transferred from the MB to the 1M. At time'T2, the MB is cleared; and a read
operation sets. the operand into bit~ 0 through 17 of theMB. At time T3, the E • IA 1 negative
level causes an XOR operation to be performed in the manner already described.

In the AC

control, the E negative level is further combined with the IB2 level produced by the IR decoder
to produce an E • ADD level. The E • A~D level, in combination with timing pulse T4, produces a negative AC <;RY (accumulator carry) pulse.

This carry pulse opens accumulator

input gates in which the state of each AC bit is compared with the state of the
corresponding MB bit. Carries are propagated where necessary. A carry pulse generated by
bit ACO causes a negative END CRY (end carry) pulse to be generated. The END CRY pulse
is applied to the complementing input of the AC17 flip-flop; if this is already in the 1 state,
further carries are propagated toward bit ACO.

Two·s Complement Add (TAD) - The TAD instruction adds the contents of the MB to the contents
of the AC in 2'5 complement arithmetic and requires a fetch cycle and an execute cycle. During
'the fetch cycle, the operation code 34 is set into the IR; and the address of the operand is set

2-19

into bits 5 through 17 of the MS. 'At time T1 of the execute cycle, the address of the operand
is transferred from the MB to the f.AA. At time T2, the MB is cleared; and a read operation sets
the operand into bits 0 through 17 of the MS. At times T3 and T4, XOR and carry operations
are perfonned as described for the ADD instruction. At time T5, an overflow from bit ACO
causes generation of a TAD CRY (2 1s complement carry) pl.Jbe which sets the LINK flip-flop
t() 1. The effect of the Iink depends upon what instruction follows; it may be sensed by an

augmented instruction to cause a skip, for example.

~xecute (XCT) - The XCT instruction causes the CP to execute the instruction contained in the

memory cell' addressed. The instruction requires a fetch cycle plus the cycles required to perform
the instruction contained in the cell. During the fetch cycle of an XCT instruction, the operation code 40 is set into the IR; and the address of the instruction to be performed is set into
bits 5 through 17 of the MS. At time T1 of the execute cycle, the address of the instruction
i:s transferred from the MB to the I'M. At time T2, the IR is cleared,and a fetch,state is forced.
Between times T2 and T3, the contents of the addressed memory cell are read into the MB; and
the four most significant bits {containing the operation code} are set into the IR. The CP then
executes the instruction which was contained in the cell addressed by the XCT instruction.
f'-lote that even if the subject instruction is a memory reference instruction, the effective address of the operand is available without reference to the PC, so that the program sequence is
unaltered. In other words, the CP acts as if it were performing the subject instruction in place
()f the XCT instruction, then proceeds to the instruction following the XCT instruction.

}ndex and Skip if Zero (~SZ) - The ISZ instruction increments the contents of the addressed cell
by 1, using 2'5 complement arithmetic. If the incremented number is 0, the next instruction is
skipped. The ISZ instruction requires a fetch cycle and an execute cycle. During the fetch
cycle, the operation code 44 is set into the IR; and the address of the operand is set into bits

.5 through 17 of the MS. At time T1 of the execute cycle, the address of the operand is transferred from the Iv'B to the M..A. Between times T2 and T3, a reod operation sets the operand
into the MS. The E level derived from the maior state generator is combined in the MB control
with the IA2 and IBl levels produced by the IR decoder. The resulting E • ISZ level conditions
'0 gate which

is opened by timing pulse TP3 to produce a +1- MB negative pulse. This pulse

complements the least significant bit of the' MB and is also appl ied to the MB gates which

2-20

propagate carry pulses. If the MB overflows (which can only happen when the contents of the
MB become 0), bit MBO generates a carry pulse which is combined in the PC control with the

E • ISZ level. As a result I a negative pulse is generated which increments the contents of the
PC by 1. Starting at time T4, the incremented contents of the MB are written back into the
memory cell addressed by the ISZ instruction.

Note that at time T1 of the fetch cycle, the

address of' the ISZ instruction was set into the MAj and the contents of the PC were incremented
in the normal manner. If the incremented contents of the MB were not 0 and therefore produce~
no overflow at time T3 of the execute cycle, the next instruction is fetched and executed.
An overflow from the MB, however, causes thE~ contents of the PC to be incremented again,
so that the instruction immediately following ISZ in the program is skipped.

Logical AND (AND) - The logical AND operation is performed by a transfer of O's from the
MB to the AC. Thus, at the end of the operation, all bits of the AC have been cleared except
those bits which contained a 1 both in the AC and in the operand before the operation started.
The AND instruction requires a fetch cycle and an execute cycle. During the fetch cycle,
operation code .50 is S€t into the IR; and the address of the operand is set into bits 5 through
17 of the MB. During the execute cycle, the address of the operand is transferred from the MB
to the MA at time T1. Between times T2 and T3, the operand is read into the MS. The E level
derived from ~he major state generator is combined in the AC control with the IA2 and IB2 levels
from the IR decoder to produce an E • AND level. This level conditions a NAND gate, which
at time T5 is triggered to produce an MBO-AC pulse. The MBO-AC pulse clears all AC bits
corresponding to MB bits which are in the. a state. AC bits which are already in the 0 state
remain O's, regardless of the state of the corresponding MB bit. AC bits which are in the 1
state rema in l's onl y if they correspond to MB bits in the 1 state.

Skip if AC is Different From Operand (SAD) - The SAD instruction sets the operand into the MB
and performs an XOR operation between the MB and the AC.

No carry pu Ises are propagated,

so that if the initial contents of the AC are identical to that of the MB, the end contents of
the AC will be a, and the next instruction will be performed

If anyone bit of the AC differs

from the corresponding bit in the MB, the next instruction is skipped. The SAD instruction
~equires a fetch cycle and an execute cycle.

During the fetch cycle, the operation code 54

is set into the IRi and the address of the operand is set into bits 5 through 17.of the MB. The

contents of the PC are incremented in the norma I manner. At ti me T1 of the execute cyc Ie I
the address of the operand is transferred from the MB into the MA; and a read operation sets
the operand itself into the MB .. The E level derived from the major state generator-is combined
in the AC control with the IA2 and 183 levels from the IR decoder to produce an E • SAD level.
The E • SAD level conditions a gate which is opened at time T3 to proquce a negative XOR
pulse. The XOR pulse cause~ MB bits in the 1 state to complement the corresponding bits of the
AC.

No carry pulses are propagated I so that if the initial contents of the AC are identical

to that of the MB, the resultant contents of the AC are all O·s. A 17-input AND gate in the
AC control samples the status of all the AC fl ip-flops at ti me T5 and generates an AC =0 level
only if all flip-flops are in the 0 state. The AC =0 I~vel is combined in the PC control with
the E • SAD level to generate a +l-PC pulse which increments the contents of the PC by 1.
Thus, if the initial contents of the AC were identical to that of the operand, the next instruction is skipped. If anyone AC fl ip-f1op is in the 1 state after the XOR operation (indicating
that the contents of the AC were different from that of the operand) I the AC =0 level is net
produced by the AC control gate / and the +1- PC pulse is not generated. The CP I therefore,
proceeds to the next instruction and executes it. The XOR operation is repeated at time T6 to
restore the original contents of the AC.

-Deposit AC in Memory (DAC) - The DAC instruction depc>sits the contents of the AC, in memory
at the address specified in the instruction. The instruction requires a fetch cycle and an execute cycle. During the fetch cycle, the operation code 04 is S&t into the IR, cnd the address
of wh ich the contents of the AC are to be deposited is set into bits 5 through 17 of the MB.
At time T1 of the execute cycle, the address for the dep::>sit is transferred from the MB to the
MA. The E level derived from the maior state generator is combined in the MB control with
the lAO and IB1 levels from the IR decoder to produce an E • DAC level. This level causes
(In AC1-;MB pulse to be generated at time T3. The AC 1- MB pulse opens the gates connecting
the output of the ACto the input of the tAB. A write operation (starting at time T4) deposits
I·he new contents of the MB into memory at the address speci fied by the DAC instruction.

Note

that although read currents ore appl ied to the addressed cell, the combination of the E and lAO
:evels in the MB control produces an MB 5TS I NH {MBstrobe inhibit} level that inhibits the gates
between the sense ampl Hiers and the input of the MB. Therefore I the original contents of the
IJddressed cell are not transferred into the MB I and so are lost. Note also that when a pseudo-DAC
instruction is used for loading information from perforated tape, the RPT (1) Ieve I causes the generatic j

2-22

of a SEl-RRB pulse at time T2, which transfers the contentsofthereader buffer into the AC.
For further details, refer to the description of the READ-I N key in the Manual Operations
paragraph'. At the end of a readin operation, the combination of the RPT (1) level and a reader
hole 7 signal clears the RPT flip-flop and sets the RUN flip-flop at time T5. The fetch state

is then establ ished for the execution of the next instruction. However, if the readin operatio!"
is to continue, the RPT (1) level causes the MB to be cleared at time T7 and starts the special
pulse generator.

Deposit Zero in Memory (DZM) - The DZM instruction clears the memory cell at the address
specified in the instruction and requires a fetch and an execute cycle. During the fetch cycle,
the operation code 14 is set into the IR; and the address for the deposit is set into bits 5
through 17 of the MB. At time T1 of the execute cycle, the address for the deposit is transferred from the MB to the MA. At time T2, the MB is cleared; and a read operation is initiated
in the normal manner. The E level derived from the maior state generator is combined in the
MB control with the lAO level from the IR decoder, thereby inhibiting the gates between the
memory sense ampl ifiers and the MB.

Information previously stored in the addressed cell is

read, but does not reach the MB and is therefore lost. A norma I write operation takes place,
starting at time T4; but since the MB was cleared, 0 is -written into the addressed cell. At
the end of the execute cycle, the fetch state is established in preparation for execution of the
next instruction.

Jump to Subroutine (JMS) - The JMS instruction permits exit from the main program into a
subroutine and requires a fetch and an execute cycle. During the fetch cycle, the operation
code lOis set into the IR; and an address (Y) is set into bits 5 through 17 of the MB. At time

T1 of the execute cycle, address Y is transferred from the MB into the MA. At time T2, the
MB is cleared and the input gates are inhibited; so that the normal read operation destroys the
original contents of cell Y. At time T3, the current program count and the status of the I ink
are transferred to the MB; the PC is then cleared. This information is written into cell Y and
is available there when re-entryinto the main program is desired. At time T4, the address Y
is transferred from the MA to the PC; and, at time T5, the contents of the PC are incremented
by 1. The end contents of the PC are Y+ 1, the address from which the first instruction of the
-subroutine is fetched.

2-23

Call Subroutine (CAL) - The CAL instruction is equivalent to the instruction JMS 20. During
the fetch cycle, the operation code 00 is set into the IR; and the IR decoder produces lAO and
IBO levels. These are combined in the MB control with a B (not a break state) level to produce
a CAL level. At time T1 of the execute cycle, the CAL level is combined in the MA control
with the E level derived from the major state generator and generates q 20- MA pulse. This
pulse sets octal 20 into the ~ by setting flip-flop MA13 to the 1 state. The 20-MA pulse
also sets fl ip-flop IR2, thereby setting opera.tion code 10 (JMS) into the IR. Thereafter, the
C P proceeds to execute the JMS instruction, depositing the Iink status and current program
count at memory location 20 and taking the first instruction of the subroutine from memory
location 211 as described in the explanation. of the JMS instruction.

}ump (JMP) - The JMP instruction transfers control of the C P to a sequence of consecutive
memory locotions that begins at the address specified in the instruction. The JMP instruction
requires only one cycle (fetch), during which the operation code 60 is set into the lR; and the
memory location from which the next instruction is to be taken is set into bits 5 through 17 of
t'he MS. The IA3 and IBO levels derived from the IR decoder are combined in the major state
logic to "roduce a JMP level which conditions two gates in the PC control. At time T5, one
of these gates is triggered to produce a 0 - PC pu Ise wh ich c Iears the PC. At time. T6, the
second gote is triggered to produce on MB 1- PC pu Ise wh ich transfers the address spec ified
by the JMP instruction into the PC. The major state generator is then set to fetch, and, during
the following cycle, the next instruction is fetched from that address •

.Indirect Addressing and Auto-Indexing
When bit 4 of a memory reference instruction contains a 1, the CP interprets the contents of
bits 5 through 17 as the memory location where the address of the operand may be found .. At
time T7 of the fetch cycle, the rna ior state generator is set to defer instead of to execute. At
time T1 of the defer cycle, -the contents of the MB are transferred to the MA (unless the instruction is CAL). The ty-1B is then cleared, and a reed operation sets the contents of the addressed
cell into the MB, which now holds the effective oddress of the operand. If this address is one
of the eight auto-indexing locations lOS through 17 , decoding gates in the MAgenerate a pulse
8
which increments the contents of the MB by 1 at time T3. If the instruction containing the
indirect address was a JMP instruction, the' PC is cleared at time T5; the effective address of

2-24

the next instruction is transferred from MB to PC at time T6; and the maior state generator is
set to fetch at time T7. If the instruction was not a JMP I no action occurs at times T4 through
T6. The major state generator is set to execute at time T7.· At time T1 of the execute cycle,
the effective address of the operand is transferred from MB to PC. The machine then performs
the operation specified by the instruction upon the operand contained in the indirectly address('d
cell.
The eight auto-index locations may contain either the effective address of an operand or an
instruction, depending on the program requirements. When used as direct addresses, they are
identical to other memory locations. When used as indirect addresses, however, their contents
are incremented by 1 each time they are addressed. Thus, use of the auto-indexing locations
facil itates the repetition of an arithmetic process on a series of numbers without perform ing
separate arithmetic operations on the addresses concerned. The PD P-7 Users Handbook expla ins
the uses of the auto- index locations from the programmer's viewpoint.

Augmented Instructions
The augmented instructions are of three types: EAE instructions with the operation code 64,
discussed with the EAE logic functions; lOT {input/output transfer} instructions with the operation
code 70; and ~ PR/LA W {operate/law} instructions with the operation code 74. These instructions do not need a memory reference and are therefore completed in one cycle {fetch}. Bits 4
through 17 are decoded to produce command pulses for the various possible operations. Since
these take place at different times, several operations may be combined in a single instruction.

Operate (OPR) - The bit assignment of an OPR instruction is shown in Figure 1-3., It wi II be
seen that bit 5 is used in one instruction only, i.e., clear accumulato'r (CLA) for which the
octal code is 750000. All other instructions of the OPR class have octal codes beginning with
74. The functions performed at times T1 through T4 of an operate instruction are exactly the
same as those which occur in the fetch cycle of any other kind of instruction. The IA3 and IB3
levels from the IR decoder are combined in the AC control with the MB4 (0) level to produce
the OPR level. This level conditions two gates: one is triggered at time T5 to perform one setof
operations and the other gate is triggered at time T7 to perform the second set of operations.
'The first set of commands consist of the following:

2-25

1. If bit 5 is a 1, the AC is cleared.
2 •. If bit 6 is a 1, the link is cleared.
3. If bits 7 and 13 are 115, the AC is rotated one place right, (and will be
rotated again during time T7)w
4. If bits 7 and 14 are lis, the AC is rotated one place left (and will be
rotated again during time T7).
5 •. If bit 12 is a 1, the RUN flip-flop is cleared and the program is halted
at the conclusion of the current memory cycle.
6. If bit 8 is a 0, anyone of the following conditions increments the contents of the PC to skip the next instruction: link is not 0 (bit 9 is a 1); AC
is not 0 (bit 10 LS a 1); AC is negative (bit 11 is a 1).
7. If bit 8 is a 1, the conditions that produce a skip are inverted (link is
0, AC is 0, or AC is positive).
The second set consists of the following operations which take place in time T7:
1. If bit 13 is CI 1, the AC is rotated one place right.
2. If bit 14 is a 1, the AC is rotated one place left.
3. If bit 15 is 0 1, the contents of the accumulator switch register are inclusively OR combined with the contents of the AC.
4. If bit 16 is a 1, the I ink is complemented.
5. If bit 17 is a 1, the AC is complemented.
Note that because of the nature of the rotate operations, a rotate operation may not be combined
with any other operation of the same set. For example I a single instruction may clear the I ink
(first set) and rotate the AC one place (second set); but a 2-place rotation (both sets) precludes
the instruction from performing any other operation.

2-26

law (LAW) - The LAW instruction is a special case or an operate class instruction and has the
operation code 76. The IR decoder produces IA3 and IB3 levels which are combined in the
AC control with the MB4 (1) level to produce nn OP LAW level. This level conditions two
AC control gates: one is triggered at time T5 to clear the AC and the other at time T6 to perform an XOR operation between MB and AC. This effectively places the entire instruction in
the AC. Thus, an address-sized number {15 bits}, preceded by the operation code, can be loaded
into the AC without using an extra memory location. The various uses of the LAW instruction
are described from the programmerls viewpoint in tbe PDP-7 Users Handbook.

Input/Output Transfer (lOT) - lOT instructions are augmented instructions which can be microprogrammed to address on I/O device and to generate up to three time pulses to initiate and
control the operation of the device. When an lOT instruction is executed, if bit 14 is a 1,
the AC is cleared at time T5; if bit 17 is a 1, an IOP1 pulse is also generated at this time. If
bit 16 is a 1, an IOP2 pulse is generated at time T7.

Ifbit 15 is a 1, on IOP4 pulse is gen-

erated at time T1 of the following cycle. For a description of the device selection and control processes I refer to Chapter 3.

Break Cycle

A break cycle provides a temporary interruption of the main program during which information
may be transferred to or from a high-speed peripheral device or a subroutine may be initiated
to service a s low peripheral device. Reference to the flow diagram (21) shows that a break
cycle may be entered under the following conditions {which indicate an "instruction done"
situation}:
1. After the fetch cycle of an OPR, LAW, lOT, or directly addressed JMP
instruction.

2. After the defer cycle of an indirectly addressed JMP instruction.
3. After the execute cycle of a directly or indirectly addressed memory
reference instruction.
4. After a break cycle to continue a block transfer or other operation
involving several break cycles.
2-27

When a break request from peripheral equipment is granted, one of three possible sequences
takes place during the break cycle.

If two or more break requests appear simultaneously,

break sequences are granted in the following descending order of priority: data break, clock
break, and program break.

Data Break
A data break may be granted to a high-speed I/O device containing registers which can simultClneously supply or accept a 15-bit address word, an l8-bit data word, a break request signal,
and a direction-of-transfer signal. When a data break is granted, the IR is cleared; and the
address spec ified by the I/O device is set into the MA at time T1 of the break cyc Ie.

If the

I/O device specifies an outward transfer, the contents of the addressed memory ce II are read
into the MB between times T2 and T3 and are available there for samp\ ing by the input register
of the I/O device.

If an inward transfer is specified, the gates between the sense ampl ifiers

and the MB are inhibited. As a result, any information contained in the cell is destroyed, and

the cell is cleared. At tIme T3 of the break cycle, the input gates I inking the MB directly to
the output reg ister of the I/O device are triggered; and the incom i ng data is set into the MB.

A normal write operation, starting at time T4, writes the data into the memory cell. Use of
the Type 173 Data Interrupt Multiplexer permits up to four high-speed I/O devices to share
the data interrupt channel.

(Refer to Chapter 6 for further details.)

After completion of the

high-speed transfer, a fetch state is established for continuation of the program, unless a further break request exists.

In this case, another break cycle follows.

Clock Break
)~ reai-time clock, which can be enabledordisobled under program control by the appropriate

lOT instruction, is included in each PDP-7system. Vvhentheclockisenobled, each clockputse
initiates a break request. When the break is granted, the IR is cleared at time T1 of the break
cycle. The clock address 78 is set into the 1M and the clock count request flip-flop is cleared.
Between times T2 and T3, the contents of memory location 78 (the clock count) are read into
the MB; and, at time ,T3, the contents of the MB are incremented by 1. A norma I write opera-'
Hon, starting at time T4, deposits the incremented clock count in memory location 78*

j'ncrementing the 1v1B did not cause an overflow, a fetch state is establ ished at time T7 to

2-28

"oWl

continue the main program (unless there is a further break request).

If incrementing the clock

count caused the MB to overflow, a carry pulse is generated by bit MBO. This carry pulse sets
the clock: flag to 1, thereby ihitiating a program break.

Possible programming uses of the

real-time clock are described in the PDP-7 Users Handbook.
Note that when the automatic priority interrupt (API) option is included in the PDP-7 system,
the real-time clock is removed and the API is connected in its place. The real-time clock
may then utilize one of the API channels.

For further details of the API, refer to Chapter 6.

Program Break
Slow I/O devices, such as the Teletype or paper tape reader, require an interval of several
mill iseconds between the time one information transfer is performed and the time when the
device is ready for the next transfer. During this interval, the PDP-7 can perform many hundreds of programmed instructions. When one or more such devices have been enabled by the
programmed instructions, the program break facility permits the CP to continue execution of
the main program until slJch time as a device indicates, by setting its flag, that it is ready
to send or rece ive information. The setting of any device flag generates a program break request, and at the first "instruction done" situation the C P enters a break cycle in which the
address of the next main program instruction, together with the status of the link, trap flag,
and extend mode are stored at location

o. Control of the processor is then transferred to a

subroutine starting in location 1, which scans all the device flags to discover which device
caused the interrupt. Identification of the interrupting device may provide entry to a further
subroutine for servicing the device. At the conclusion of the servicing subroutine, the main
program may be reentered by a jump indirect to location 0, which transfers program control to
the addre~ stored at location

A program break is granted when all of the following conditions are fulfilled:
1. The program interrupt focil ity has previously been enabled by a programmed

ION instruction.

2. The setting of a device flag has generated 0 program break request.
3. There is no data break in progress or waiting.

2·-29

4. There is no clock (or" API) break in progress or waiting.
5. There is no program break in progress.
At time T1 of the break eye Ie, the IR is cleared, and at time T2 the MB is cleared. The memory generates read currents which clear location 0, but the MB input gates are inhibited so
that any information previousl y contained in that location is destroyed. At time T3 the Iink
status is set into bit MBO, the extend mode status into bit MB 1, and the trap flag status bit into
MB2. The contents of bits PC3 through PC 17 are transferred to the corresponding bits of the
MB and the PC 'is cleared. At time T4, the contents of the MA are transferred to the PC; note,
however, that the MA was cleared at time T7 of the 'previous cycle and was not reloaded, so
its contents are still O. Also at time T4, a normal write operation is begun which deposits the
contents of the MB in memory at location O. At time TS, the contents of the PC are incremented
by 1, so that the next instruction will be taken from location 1 in which a subroutine starts.
l'he program interrupt enable fl ip-flop is cleared to prevent any other program breaks until
the interrupt is enabled by a programmed instruction at the conclusion of subroutine operations.
t~ote,

however, that dato breaks and clock (or API) breaks may still be granted. If the program

is operating in the trap mode and the program break was initiated by the trapping of an illegal
instruction, the contents of the PC are again incremented by 1 at time T5. Thus, control of
the CP is transferred to a subroutine starting in memory location 2 in order to identify the
trapped instruction and take appropriate action. If no data break or clock break request has
been originated during the break cycle, a fetch state is estobl ished at time T7 and the first
"s,ubroutine instruction is fetched during the ensuing fetch cycle. If a data or clock break re(luest exists, a further break cycle is granted before the subroutine is entered.

Trap Mode
'Nhen the PDP-7 forms part of a real-time or multiuser system, the trap mode permits the use of
~jophisticated programming in the main program and guarantees this against interference from

()Iher users operating in a different section of memory. When the main program is operating in
Ireal time, it is particularly important to ensure that the processor cannot be halted, involved
:in lengthy operations, or thrown into a loop from which it cannot escape. The I/O trap provides
the basic hardware necessary to provide protection aga inst such disturbances.

2-30

When the trop mode is enabled by turning on the TRAP switch and by a programmed ITON
(I/O Trap On) instruction, the following illeg(ll instructions are trapped: all lOT instructions;

011 HLT (halt) instructions; and all XCT (execute) instructions. When an illegal instruction
is detected, the trap flag is set, thereby preventing execution of the instruction. Instead, a
-,

program break request is initiated. When the break is granted, control of the CP is transferre~
to a subroutine starting at memory location 2, which initiates procedures for identifying the
trapped instruction and for tak ing appropriate action. The reason for trapping holt instructions
is obvious; lOT instructions are trapped because, if not well planned, they could involve the
CP in lengthy operations to the detriment of the real-time operations; XCT instructions are
trapped because if the subject instruction were also on XCT, a loop situation could arise in
which the CP would never encounter on "instruction done" situation, so that all control would
be lost.

2-·31

CHAPTER 3

PROCESSOR
This chapf'er describes in detail the logic elements which perform the logic functions described
in Chapter 2. Descriptions of registers consider the effect of the various control signals applied;
descriptions of control elements consider the output signals and explain the conditions under
which each of these is generated. Many types of FLIP CHIP modules consist of a number of
similar components (e.g., Type W607 contains three identical pulse amplifiers) •. Where necessary the individual components of a module are identified by their input and output terminal
letters (e"g.,

NOR gate NPR of module J5). In addition, references to the zone of the engi-

neering drawing in which the component is located aid in identification of a particular component.
All logic circuit elements of the processor are shown on the block diagram of Figure 3-1. These
elements consist of the maior registers and their associated control elements, the timing generators for the compurer system, the manual controls, and the special program feature cont:·ols
(data break control, program interrupt control, I/O skip, I/O trap, etc.).

MAJOR REGISTERS

AC Register (30, 31)
The AC is the maior arithmetic register of the CP and is involved in most of the mathematical,
logical, and I/O transfer operations performed by the computer. This register consIsts of 18
Type B210 Accumulator FLIP CHIP modules at locations 1EF2 through 1EF19. The AC has a
storage capacity of 18 bits. Each flip-flop of the AC can be individually set or cleared, in
programmed operation, by means of gated signals from other registers or from external equipment. The flip-flops can also be set (but not cleared) by means of the ACCUMULATOR switches
on the operator console. The AC may also be cleared collectively I or its contents incremented

by 1, complemented, rotated, or shifted right or left. The status of each flip-flop in the register
is shown by an indicator on the operator console.

3-1

FRO~

ADDRESS

FROM INPUT/OUTPUT EQUIPMENT
USING PROGRAMMED STATUS
CHECK!>

SKIP _ _ _ _ ...

INPUT/O\JTPUT EQUIPMENT
U!>ING DATA 8REAK TRANSFERS

iliA
CONTROL

-I~

I/O SKIP
CONTROL

MEMORY
ADDRESS
REGISTER

~_.L-__

....----....

ADDRESS

TO CORE
-.. MEMORY

IIOP 1,2,4
TO DEVICE SELECTOR OF INTERFACE

04------

LINK

FROM INPUT/OUTPUT EOUIPMENT
VIA THE INFORMATION COLLECTOR
OF THE INTERFACE

TO INPUT/OUTPUT EQUIPMENT VIA
THE INFORMATION DISTRIBUTOR OF
THE INTERFACE

DATA

4---------1
IB
MEMORY
BUFFER
REGISTER

AC
CONTROL
FOR INPUT/OUTPUT EQUIPMENT
USING DATA BREAK TRANSFERS

DIRECT CONNECTION AVAILABLE FOR ANY
INPUT lOUT PUT EQUI?MENT DR FOR
DEVICE SELECTOR OF INTERFACE

~EMENT MB

6:¥; BE~~~MT~~TN~~~~~

INPUT/OU

MB
CONTROL

CLEAR AC

~O._R_ST_A_T_E_S_(_IN_S_T_RUC_T_IO_N_ST_A_T_ES.:.,:I_ _ _ _ _ _ _ _ _ _ _---1

l~OR

DIRECT CONNECTION AVAILABLE FOR

~____~r-________________O_A_T_A__~~~:~~~~RY

DATA

~-----4----------------~~

STATES (F,D,E,B I

::::E::C:::..;::::::::_TE_O_ _ _ _ _ _ •_ _ _-I

~-A_R-E-A_O_Y_----------___4
PROGRAM
INTERRUPT
SYNC.

TRANSFER DIRECTION
--------..:::..:..--"--'-----.

DATA BREAK REQUEST

BREAK
REQuEST

--------~~~------------~

DIRECT CONNECTION AVAILABLE FOR
ANY INPUT/OUTPUT EQUIPMENT

POWER
CLEAR PULSE
~---

Figure 3-1

Processor Detailed Block Diagram

3-2

Each Type 8210 module is a double-height module containing one buffered-output flip-flop, a
carry pulse amplifier, and all the required transistor gating elements. The flip-flop is set or
cleared'by a positive pulse from a gating circuit; the gates are conditioned by negative levels
and are triggered by negative pu Ises.
All bits of the accumulator are cleared collectively by a 0 -

AC pulse applied to input ter-

minal EV of a transistor gate connected to the direct clear input (ES) of the fI ip-flop.
Each bit of the AC may be individually set by a positive pulse from the information collector
applied to terminal EU, which is connected to the direct set terminal (ET) of the flip-flop.

Ara

unused transistor gate permits a bit to be set by application of a negative pulse to terminal FL.
Rotate right operations are performed by a pair of transistor gates to which the RAR pulse is
applied (at terminals EN and EJ). These gates set or clear the associated flip-flop according
to the status of the adiacent flip-flop of greater significance. The (1) level of this flip-flop
is applied to terminal EH, and the (0) level to terminal EM.
Rotate left operations are performed by a simi lor pair of gates to which the RAL pulse is applied
(at terminals EL and ER). These gates are conditi~ned by the (1) level (terminal EK) and the
(0) level (terminal EP) of the adiacent flip-flop of less significance.
Each bit of the AC m,ay be cleared by a 0 in the corresponding bit of the MB. The MB (0) level
is applied to terminal FH and clears the AC flip-flop when an MBO -

AC pulse is applied to

terminal FF.
Each bit of the AC may be set by a 1 in the corresponding bit of the accumulator switch register.
The (1) level from the corresponding ACCUMULATOR switch is applied to terminal FK, and the
ACS1 pulse to terminal FJ.
Complementing is accomplished by applying a positive pulse to both the direct set and direct
clear inputs of the flip-flop, through isolating diodes. Complementing is performed by any
one of the following: .
1. A neg.ative C

- AC pulse is applied to terminal FT; a transistor inverts

the pulse.

3-3

2. A positive pulse from the XOR NAND gate; this gate is conditioned

by an MB (1) level applied to terminal FV, and is triggered by a negative
XOR

AC pulse applied to terminal FU. The output of the gate com-

plements the AC flip-flop.

3. By a carry pulse from the adiacent AC bit of less significance. The
negative carry pulse is applied to terminal Fp· and is inverted by a transistor.
Carry pu lses from one bit to the adjacent bit of greater signi ficance are generated by a pulse
amplifier contained in the Type 8210 modu Ie. A carry from bit ACx to bit ACx-l is generated
under the following conditions:

1. When bit ACx contains a 1, and a carry pulse is received from bit ACx+1 •
The negative ACx (1) level conditions terminal FD of a NAND gate; the incoming carry complements bit ACx and triggers the NAND gate. The output
of the gate triggers the carry pulse amplifier which transmits a carry pulse
to bit ACx-l .

2. During an ADD or TAO instruction, an XOR operation is first performed
between the MB and the AC. After the XOR operation, an AC CRY pu Ise is
applied to all bits of the AC at terminal FR of a NAND gate. If the level
inputs of this gate are conditioned by an MBx (1) level applied to terminal
FV and an ACx (0) level applied to terminal FE, the AC CRY pulse causes
the gate to trigger the carry pulse amplifier and a carry is transmitted to
bit ACx-1. The resu lting changes of state in fl ip-flops of greater significance
may result in additional carries being propagated as described in 1 (above).

Link (26)
The link (L) is on extension of the AC and is used for data overflow. The link consists of a
single Type B210 Accumulator module at location IEF1. Storage capacity is a single bit. The
link is capable of the some functions as the AC and can be operated independently of, or in
coniunction with, the AC. The status of the link is shown by an indicator on the operator

console.

3-4

The link is cleared by anyone of the following conditions:
1. By a BGN pulse at time SPlof any key operation
2.

By a microprogrammed rotate right command, if bit AC17 is 0

3. By a microprogrammed rotate left command, if bit ACO is 0
4.

By a microprogrammed clear link command (bit MB6 is 1) at time T5

of the computer cycle
The link is set by anyone of the following conditions:
1. By an EAE SET L pulse originating in the extended arithmetic element
2. By a microprogrammed rotate right command, if bit AC17 is 1
3. By a rotate left command, if bit ACO is 1
4.

By timing pulse TP1 of the computer cycle, if the AC overflowed rfuring

the previous cycle
The link is complemented:
1. By an ACO CRY (overflow) during a EAE multiply or divide operation
2.

Bya TAD CRY pulse generated: by an AC overflow during 2 1s comple-

ment addition; by a microprogrammed complement link command in an operate
instruction; or by a complement link command originating in the EAE

Program Counter (29)
The PC governs the core memory address from which the next instruction wi II be drawn. This
register consists of 15 Type B201 Flip-Flops at locations 1018 through 1032 and 7 Type 8620
Carry Pu lse Ampl i fi ers "at locations 1E21 through 1E27. The PC has a storage capac i'ty of 15
bits. In normal (nonextended) operations, on ly 13 of these are used. The 13 fl ip-flops containing these 13 least significant bits can be individually set either by gated sign"als in automatic

3·-5

operation or by the ADDRESS switches in manual operatIon. The PC con only be cleared collectively. The inclusion of complementing gates and carry pulse amplifiers permits the contents
of the PC to be incremented by 1 injected into the least significant bit. The status of each
fUp-flop is shown by an indicator on the operator console.

Memory Address Reg ister (29)
The (MA) contains the address of the core memory cell currently selected for reading or writing.
This regi.ster consists of 15 Type 8201 Flip-Flops at locations 1A18 through 1A32. The MA has

a storage capacity of 15 bits. Each flip-flop of the MA can be individually set by gated signals from other registers but can only be cleared collectively. The status of each flip-flop is
shown by an indicator on the operator console.

Memory Buffer Register (30)
The (MB) serves as a data buffer between the processor and the core memory. This register consistsof 18 Type B201 Flip-Flops at locations 1C2 through 1C19 and 9 Type B620 Carry Pulse
Amplifier; at even-numbered locations 1 B2 through 1 B18. The MB has a storage capacity of
18 bits. The register flip-flops can be individually set by gated signals but can onlty be cleared
collectively. The circuitry of the MB is very simi lar to that of the MA with the addition of the
pulse amplifiers and complementing gates which allow the contents of the MB to be incremented
by 1, injected into the least significant bit. The status of each flip-flop is shown by an indicator on the operator console.

Ma jor State Generator (24)
The mu Itistate device which generates the four major state levels is composed of four NAND
gates: three are contained in a Type B115 FLIP CHIP module at location H18, and the fourth
in another similar module at-location J17. When disabled, each NAND gate produces a negative level at its output terminal; when fully enabled by three negative levels, the gate produces a ground output level. The gates are so interconnected that the output signal of each
gate is applied to one input terminal of each of the other three gates. Thus, if the fetch produces a ground output, this signal disables the other three gates, so that each produces a negcltive output. These three negative output signals are returned to the input terminals of the

3-6

fetch gate to maintain it in the fully enabled state. If a positive pulse is now applied to the
output of t'he execute gate, this pu Ise keeps thE~ defer and ~reak gates disabled, but also disables the fetch gate. Terminals F and E of the execute gate remain enabled by the negative
levels from the defer and break gates, but terminal D makes a transition from ground to - 3v
when the fetch gate is di~abled. The execute gate is now enabled by three negative input
levels, so that its ground output level is maintained after the setting pulse is ended. Setting
pulses for the multistate device are provided by two Type R602 FLIP CHIP modules in locations
J18 and H19. Each module contains two pulse amplifiers, which produce a standard positive
lOO-nsec pulse. Each pulse amplifier is provided with two DeD gates enabled by the combination of a ground level and a positive pulse. In principle, any state can be entered from any
other state; however, certain necessary modifications to this principle are made by the maior
state gati~g.
During the execution of programmed instructions, the conditions established during any given
cycle determine the maior state for the next cycle. At time T7, those conditions are implemented by combining an F SET, D SET, E SET, or B SET level with timing pulse TP7 to produce

a pulse that sets the multistate device. However, when ~larting a program, or w.hen performing
a manual operation, a fetch or execute state ,may be established by oth~r means.

A fetch state is establ ished by one of the fo lIowi n9 sets of condi tions:

1. When the 5T ART key is depressed r the positive START level generated
by the key circuits is combined with f'iming pu Ise SPl of the key cycle.
The resulting pulse triggers pulse amplifier PAl in module J18 (B2, 24)
which sets the multistate device to the fetch state.

2. A Pil -

MA pulse, inverted in module J30, triggers pulse amplifier

PA2 of module J19 and establishes a fetch state.

3., When a program is running in the trap mode, and an illegal XCT instruction is trapped, a positive TRAP FLAG (0) level (produced only when
the TRAP FLAG fl ip-flop is set) is combined with the XCT CY (1) signal.
This establishes a fetch state immediately, to avoid implementing the illegal
'instruction.
3·-7

4. During normal operation, an F SET level is ·combined in a OeD gate
with timing pulse TP7 I NVTD B; and the resulting output of the gate triggers
pulse amplifier PAl of module J1B to establish a fetch state.
The positive F SET level is generated by a NAND gate in module J21 (01 1 24) and appears at
output terminal H of the gate. This gate normally produces a negative F SET level; however,
when all three inputs are enabled by negative D SET, E SET, and BK RQ levels, the ground

F SET level appears at the output. The D SET level indicates that the current instruction does
not cont~in an indirect address which wou Id require a defer cyc Ie to follow the fetch. The
E SET level indicates that the current cycle is not a defer cycle which would require an execute cycle to follow it. The BK RQ level indicates that no I/O device is in need of servicing.

An execute state is established under the following conditions:

1. When any operation key other than the START key is depressed, a negative START level derived from the key circuits enables a NAND gate in
module J22 (B3, 24). When the BGN pulse of the key cycle is added, the
gate triggers pulse amplifier PA2 of module J18 and establishes the execute
state.
2. During programmed operation, an E SET level conditions one input of
a OCD gate; and timing pu lse TP7 I NVTD B causes the gate to trigger the
associated pulse amplifier and establish the execute state.
The ground E SET level is generated by one of three NAND gates located in modules J21, H20,
and K19 (e1, 24). A ground E SET level appears at terminal H20U if all of the following conditions are met: the current cycle is operating in the fetch state; the operation code stored in
the IR produces an IA3 level (indicating that the instruction is not a single-cycle law, operate,
olr lOT instruction); and bit MB4 is 0 {indicating that the instruction contains the direct address
of the operand}. The ground E SET level appears at terminal J21 F if the current cycle is operating in the defer state and the operation code produces an IA3 level. The ground E SET level
(appears at termInal K19R if the RPT flip-flop is set (during a readin operation).

3-8

A defer state is established during the fetch cycle of any memory reference instruction or JMP
instruction which contains a 1 in bit 4. The negctive F level and MB4 (1) levels are combined
in NAND gate JKL of module J21, and the output of the gate is inverted in inverte~ PRS of
module J20. The output of this inverter and the output of NOR gote NPR of module J21 are
both applied to inverter TUV in module J20.

Note that both the NAND gate and the NOR

gate must give negative outputs to produce the ground 0 SET level at terminal J20U. The NOR
gate gives a negative output when the lA3 level from the IR decoder is at ground (this condition
is not ful.filled when the lR contains 60 JMP, 64 EAE, 70 lOT, or 74 OPR/LAW), or when the
I SO level is at ground (this condition is equivalent to an I BO assertion and occurs when a JMP
code is held in the IR).
A break state is established if a break request conditions NAND gate KLMN of module J21
(D1, 24), provided that neither a D SET nor an E SET level has already been establ ished for
the following cycle. These conditions can be fulfilled at time 17 of the fetch cycle of an OPR,
LAW, lOT or directly addressed JMP instruction; during the defer cycle of an indirectly addressed JMP instruction; during the execute cycle of any multicycle instruction; and during a
break cycte.

Instruction Register (24)
The IR flip-flops, together with the input gates and the output decoder, are shown at the right
of engineering drawing 24. All four flip-flops are cleared simultaneously by the output pulse
of pulse amplifier RNPM in module J16. This pulse amplifier is triggered by anyone of the
following conditions:
1. A BGN pulse applied to inverter input terminal H15E (C5, 24)
2. A timing pulse T1 applied to NAND gate NPR of module H16, when the
gate is conditioned by an F (fetch) level
3. A timing pulse T1 applied to NAND gote JKL of modu Ie H16, when
the gate is conditioned by a B (break) level

3-9

4. A timing pulse T2 applied to NAND gate DEF of module H16, when the
gate is conditioned by an E·XCT level. (The E.XCT level is generated by
combining the 1A2 and I BO levels from the IR decoder with the E (execute)
level in NAND gate RSTU of module J17. The output of the gate is inverted
and the E·XCT level appears at terminal H17U, provided that the trap flag
is not set.)

A 4-bit operation code may be set into the IR in one of the following ways:
1. When an F level conditions the four input gates in module H13, a binary 1 pulse from anyone of sense amplifiers SAO through SA3 sets the cor-

responding IR flip-flop to 1 •
2. During execution of a CAL instruction, the 20 -

MA pu Ise generated

in the MA control is applied to inverter input terminal J15D (C8, 24). The
inverted pulse sets flip-flop IR2 to 1, thereby substituting a JMS (octal 10)
operation coce for the CAL (octal 00) code he Id in the IR.

3. During a deposit, deposit next, or read paper tape operation, a
DP+DPN+READ-I N+RPT (1) level conditions NAND gate STU in module
J12.· The gate is triggered by timing pulse SP2 of the key cycle and sets
operation code 04 (DAC) into the lR by setting flip-flop IR3 to 1.

4. During an examine or examine next operation, an EX+EXN level conditions NAND gate LMN in module J12. This gate is triggered by timing
pulse SP2 of the key cycle and sets operation code 20 (LAC) into the IR by
setting flip-flop IRl to 1.
The operation code is decoded by two sets of NAN D gates and inverters. The gates of modu Ie
H14 and the inverters of module H15 decode the outputs of flip-flops IRO and IR1. Gating
levels lAO through IA3 and IA3 appear at terminals H15J, M, R, U, and T, respectively. The
gCJtes of module J14 and the inverters of module J15 decode the outputs of flip-flops IR2 and

IR3. Gating levels ISO through lB3 appear at inverter output terminals J15J, M, R, and U,
n:spectively.

3-10

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pulse, which triggers a Type R302 one-shot in modu Ie K20 (02, 22). The oeD input gate of
this one-shot is conditioned by a positive SLOW CYC level; and, at the conclusion of the delay
period, the level transition which appears at output terminal k20M initiates generation of pulse

TPl of a new cycle.
Every lOT instruction fetched from memory causes the minor state generator to produce negative
IA3 and IB2 levels. These levels are applied to input terminals Rand P, respectively, of
module J23 (C4, 23), where they are NAND combined with the I/O TRAP (0) level. Thus,
provided that the I/O TRAP flip-flop has not been set, the gate gives an output which is inverted and appears as a negative lOT level at terminal H23K. Each I/O device that- requires a
slow cycle must generate a negative REQUEST SLOW CYC level. This level is NAND combined with the lOT level in module J22 (05, 23) to produce the positive SLOW eye and negative SLOW Cye levels. The inverter in modu Ie H22, in turn, produces the negative SLOW eye
and positive SLOW eye levels. These four levels control the gates that determine the signal
paths through the timing chain for normal and slow cycles (engineering logic diagram 22). The
total delay of the slow cycle is factory adiusted to accommodate the slowest I/O device in use.
When the tape reader is loading information into memory I each tape character is read into the
reader buffer as the result of an operation in "the READ-IN mode which utilizes timing pulses
SPO through SP4 of one key cycle • However, the reader buffer assembles an 18-bit computer
word by storing three type characters successively in different sections of the buffer. The information transfer between reader buffer and processor must be delayed unti I the reader buffer

is full. During readin, therefore, the RUN flip-flop is not set during the key cycle. Instead,
a negative READ-I N level (generated by releasing the REAO-l N key after initiating the operation) and a negative RPT (1) level condition the NAND gate in module K14 (D2, "22). When
the reader starts to read the third tape character, the RD FL AG flip-flop is set I indicating that
the reader is .eady to transfer information, and the negativeRO FLAG level conditions the third
input of the gate. The last level to appear causes a positive-going level transition at terminal
K14H, therby initiating a timing cycle during which the complete word is transferred from the

reader bu ffer into the processor. When the transfer is complete, the reader flag is reset I and
the timing signal generator is halted unti I another word is ready for transfer.

3-15

Run Control (23)
The RUN flip-flop controls the continuous succession of normal computer timing cycles.

When

the flip-flop is set to 1, and there is no slow cycle or stop timing request, timing pulse TP7 of
thE~ current cycle (delayed by 150 nsec) is permitted to reenter the timing chain and generate

timing pulse TP1 of the next cycle. When the RUN flip-flop is reset to 0, it disables a gate in
the reentry path and stops the computer I unless other conditions permit a new eye Ie to be initiated. (Refer to the descri ption of the tim ing signal generator for detai Is.) The CP may be
halted by the program but must then be restarted by a manual START or CONTI NUE operation.
The RUN flip-flop is an unbuffered flip-flop contained in a FLIP CHIP Type R201 module which
also contcin') two DCD gates for clear inputs and three for set inputs. The flip-flop is reset to

o by the following events:
1. When power is turned on after a shutdown, PWR ClK negative pulses
are inverted in module H22 and applied to a DCD clear input (terminal
H26E) in order to establish initial conditions.
2. When any console key is depressed to initiate an operation, the SPO
timing pulse is applied to direct clear input terminal H26K, thereby causing
any operation already in progress to be halted at the end of the current
memory cyc Ie.

3. A negative RUN STOP level generated by the STOP, SINGLE STEP,
or SINGLE INSTRUCTION key (20) is inverted in module H22. The inverted signal appearing at terminal H22R conditions level input terminal
H26J of a DCD gate. Timing pulse T5 is inverted in module J26, and
the inverted pulse, applied to terminal H26H, triggers the gate and clears
the RUN flip-flop.

4. A positive HL T pu Ise is appl i ed to terminal H26E to trigger a DCD gate
and clear the RUN flip-flop.

The HlT command is generated by NAND com-

bination (in module J24) of the I/O TRAP (0) level, an MB12 (1) level, and
an lOP 1 pu Ise. The tv1R 12 (1) leve lis derived from the execution of an OPR

3-16

instruction containing a HLT microinst'ruction •. The RUN flip-flop is
cleared at time T5. The CP halts after time T7 of the same cycle.
The RUN flip-flop is set under the following conditions:
1. Depressing the START or CONTINUE key generates a negative
START+CONT level (20), which is NAND combined in module J25 with'
the SP3 timing pulse. The positive pulse produced by the gate is applied
to terminal H26S. where it triggers a DCD gate and sets the RUN flipflop.
2. During a readin operation, a positive RPT (1) level conditions terminal
H26V of a DCD set gate. The pulse input of this gate (H26U) is triggered
when a RDR HOLE 7 level is NAND combined with timing pu Ise T5 of the
c:ycle in which a hole 7 was detected. (A hole 7 indicates that the processor is to interpret and execute the last word read.)

I/O Pulse Generator
I

Timing pulses for the control of I/O devices are generated in modules K30 and K31 (A8, 22).
M.odule K30 is a FLIP CHIP Type B115 containing three NAND gates; the output of each gate
triggers on associated pulse amplifier in module K31 to produce a standard negative 4O-nsec
pulse. Any instruction of the lOT closs generates a negative lOT level, which is applied to
all three NAND gates. The subsequent generation of I/O pulses depends on the state of memory buffer bits MB15, MB16, and MB17. If bit MB15 is l,on lOP 4 pulse is generated at
time T1 of the computer cycle; if bit MB16 is 1, an lOP 2 pulse is generated at time T7; if bit
MB17. is 1, an lOP 1 pu Ise is generated at time! T5. These pu lses are routed to the device
selector; there they are combined with device 'selection levels to generate lOT command pu Ises
that control the operation of 'the selected I/O device or trigger control gates in the CP.

Manual Controls (WD-D-7-0-37)
The manual controls provide means of energizing and de-energizing the computer; selecting
modes of operation; manually inserting data i.nto registers and core memory; and visually examining the status of the most important registers. Wiring connections to the"keys and switches

3--17

on the operator console panel are shown on engineering drawing WD-O-7-0-37. The logic for
gating signals produced by the keys and switches is shown on engineering drawing BS-D-7-0-20 •

.!!!.terlock and POWER Switches - One deck of the key switch is connected in parallel with the
P()WER switch and is closed when the switch is in the locked position. Thus, with the key.
switch in the locked position, it is impossible to ruin a program because accidentally turning
off the POWER switch does not interrupt the primary power circuits. To shut down the computer, the key switch must be placed in the unlocked position and the POWER switch in the
off position. A second deck of the lock switch suppl ies either ground or -15v to the key and
mode switches. In the locked position, the key switch grounds all key switches to disable them.
thereby preventing accidental interference with a program that is running.

Key Circuits - When the computer is energized and the lock switch is in the unlocked position,
operating any of the keys or turning on the SINGLE STEP, SINGLE INSTRUCTION, or REPEAT
switches supplies -15v to a terminal on connector 2B29 or 2B32. The gating circuits shown on
engineering drawing :0 combine key signals to generate vorious levels. These levels start the
special pulse generator and condition control gates, as necessary, to cause the event sequences
shown in the flow diagram inc ludcd on the drawing.

Indicator Circuits - Indicators on the operator console are 28v incandescent lamps driven by
Type 4903 Light Bracket Assembl ies or Type 4904 Short Light Bracket Assembles. These assemblies contain a number of transistor switches, each connected between an indicator and
ground. One side of each indi cator is connected to the -15v supply.

A common ground po-

tential is connected to the emitter of each transistor through parallel-connected diodes, which
provide the appropriate base-emitter bias. Each transistor switch is turned on by a negative
signal level derived from a fl ip-flop and connected to the base through a resistor. When a
flip-flop is in the 0 state, it supplies a ground potential that cuts off the transistor switch and
extinguishes the associated indicator lamp. When a flip-flop is in the 1 state, it supplies a
negative potential to the transistor switchj and the indicator lamp lights. The potential applied
to a lighted indicator lamp is approximately 14v, which provides adequate visibility while
.Emsuring very long lamp life.

3-18

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Document

the AC contains a binary number, and the XOR transfer -is followed by the propagation of carry
pulses and then by an end-around carry of an overflow from bit ACO, the contents of the MB
are added to the contents of the AC in lis complement arithmetic. If the overflow from bit
ACO is set into the link instead of into bit AC17, then the contents of the MB are added to the
contents of the AC in 2 15 complement arithmetic. The XOR -

. AC pulse is generat,ed by any

one of the following conditions:

1. An XOR pulse originating in the EAE is applied to terminal J3E(A6, 26)
"and initiates an XOR command.

2. "During execution of any LAW instruction, a negative OP LAW level
conditions AND gate MN of modu Ie J3. The gate is triggered by timing
pulse T6 and initiates the XOR commcmd.

3. During the execute cycle of a LAC, XOR, ADD, or TAD instruction,
(1

negative E • IA1 level conditions AND gate HJ of module J3. The gate

is triggered by timing pulse T3 and initiates an XOR command.

4. During the execute cycle of a SAD instruction, a negative E • SAD leyel
is generated by combining the E level from the maior state generator with
the 1A2 and I B3 levels from the IR decoder in NAND gate RSTU of module
H12 (B1, 26). The output of the gate, inverted, is the E • SAD level and
conditions AND gates PR and KLof module J3 (AS, 26). Gate KL is triggered

by timing pulse T3 and initiates an XOR command; a second XOR command
is initiated when gate PR in module J3 is triggered by timing pulse T6.
The AC CRY (AC carry) command pulse is generated by pulse is generated by pulse amplifier
circuit FDEC in modu Ie H5. During the execute cycle of either a TAD or an ADD instruction,
the E • TAD or E • ADD ground level is applied to NOR gate NPR of module J5 (B6, 26) to
generate the E . TAD + ADD negative level. This level conditions NAND gate DEF of module
J4. The gate is triggered by timing pulse T4, and the positive pulse appearing at terminal J4F
triggers the pulse amplifier which generates the AC CRY pulse. The pulse amplifier may also
be triggered by a positive EAE CRY pu 15e originating in the EAE.

3-21

The END CRY (end-around-carry) command is generated by pulse amplifier circuit FDEC in
module H3 and causes an overf,low from bit ACO to be added to bit AC17, with further corry
pulses a~ necessary. A negative E • ADD level conditions NAND gate TUV in module J4.

If bit ACO contai ned a 1 before the carry operation, and changes to 0 as the resu It of carry
pulses from less significant bits, an ACO CRY pu Ise is generated. This pu Ise, after inversion,
triggers the pulse amplifier STU in module Ha, and the output pulse from this amplifier triggers
NAND gate TUV in module J4, thereby initiating generation of the END CRY pulse. The
END CRY pu Ise complements bit AC17, further carry pulses being generated as necessary.
The TAD CRY (2 1s complement addition carry) command pulse is generated by pulse amplifier
circuit RNPM in module H3. This pulse complements the link whenever one of the following
conditions occurs:

1. An EM CML (EAE complement link) command pulse originating in the

EAE triggers the pulse amplifier that generates the TAD CRY pulse.

2. An OPR instruction, microprogrammed to compl ement the link, contains
a 1 in bit 16. The MBB16 (1) level conditions NAND gate TUV in module
J5 (85, 26), and the gate is triggered by an OP 2 pulse. A TAD CRY pulse
is then generated at time T7 of the computer eyc Ie.

3. During the execute cycle of a TAD instruction, a negative E • TAD level
conditions NAND gate NPR in module J4 (B6, 26). If the AC overflows,
this gate is triggered by the ACO CRY (B) pulse and initiates generation of
the TAD CRY pulse.
The C

AC command pulse is generated by pulse amplifier circuit RNPM in module H5.

This pulse complements each individual bit of the AC and occurs when on EAE CMA (EAE complement AC) command pulse, originating in the EAE, triggers the pulse amplifier. The C -

pulse also occurs at time 17 during the execution of an OPR instruction which is microprogrammed
for a CMA operation by the insertion of a 1 in bit 17. The MB17 (1) level conditions NAND
gate JKL in module J4 (B6, 26), and the gate is triggered at time T7 by an OP 2 pulse.

The

"()P 2 pulse is generated by NAND-combining the negative OPR level with timing pulse T7 in
gate NPR of module J8 (C2, 26), ond applying the resulting pulse to pulse amplifier LNM in
module H8.

3-22

The RAR and RAL command pulses eire generated at terminals Nand 0, respectively, of pulse
cunplifier module H4. Each of the two pulse amplifiers is triggered by a NAND gate, which
is conditioned by an MBB13 (1) level (for RAI{) or an MBB14 (1) level (for RAL). These gates
are strobed by an AC ROTATE pulse at time T5 and initiate generation of the RARor RAL /
pulse .If the instruction word contains a 1 in bit 7, the MBB7 (1) level 'conditions a NAND
gate which is triggered by an OP 1 pulse at time T7 and produces an additional A,C ROTATE

pu Ise. Thus, one RAR or RAL pu Ise is generated at time T5 for a l-place rotate operation;
if a 2-place rotate is microprogrammed, a second RAR or RAL pulse occurs at time T7. Rotate
command' pulses originating in the EAE are applied to the input terminal of the RAR or RAL
pulse amplifier (terminals H4R and H4F, respectively)" and initiate generation of the RAR or
RAL command pu Ises.
The MBO -

AC command pulse is generated by pulse amplifier circuit RNPM in module H6

and appears at terminal H6N. This command pu Ise causes MB bits in the 0 state to set the
corresponding bits of the AC to the 0 ~tate. During the execute cycle of a logical AND instruction, the E level from the maior state generator is combined with the IA2 and I B2 levels from
the lR decoder in NAND gate KLMN of moduie H12 (C1 ,26) and produces a negative E • AI'~D
level. The E • AND level conditions NAND gate NPR in modu Ie J6 (C6, 26), whi.ch is triggered by timing pulse T5 and causes generation of the MBO The ACSl -

AC pulse.

AC command pulse is generated by pulse amplifier FDEC in module H6 and ap-

pears at terminal H6D. This command pulse causes the contents of the ACCUMULATOR switches
on the console to be transferred into the AC.

The ACS1 -

AC pulse is generated at time

SP2 of a DEPOSIT or DEPOSIT NEXT key cycle. This command pulse may also be generated
during the execution of an OPR instruction containing a 1 in bit 15. The MBB15 (1) level
conditions NAND gate JKL in module J6, and the gate is triggered by an OP 2 pulse at time
T7, thereby causing generation of the ACS 1 -'

AC pu Ise.

The ADD 0'1 level is generated whenever the AC overflows during an ADD instruction. This
level conditions a link input gate which is strobed by timing pulse TPl of the following cycle
and sets the link to 1 if there has been an overflow. The ADD OV level appears at the junction

of terminals D7F, D7L, D8J, and D8E. All four of the inverters connected to these terminals
must produce a negative output level for an ADD OV negative level to be established. The

3·-23

posibility of an overflow is detected by applying the ACO (0) status to NANDgateNPR in
module D9 (B4, 26). If this bit contains a 0 after data has been XOR transferred to the AC,
but before the <:arry pulses are generated, there is the possibility of an overflow. The gate is
strobed by timing pu lse T4 and, if bit ACO contains a

a, the POV flip-flop is set. The buffered

IR~3 (0) level and the POV (1) level now fulfill two of the conditions for the production of an

ADD OV level. However J the states of bit MBO and bit ACO must now be sensed to determine
whether an overflow has in fact occurred. The comparison is made by the two NAND gates in
module 07. If, after the carry, bit MOO and bit ACO both contain a 1, there has been transfer
of a 1 with no overflow. Terminal D7L, therefore, remains at ground potential and prevents
generation of a negative ADD OV level. Similarly, if bits MBO and ACO both contain a 0
after the carry, no transfer at all has taken place between these bits; and terminal D7F remains

at ground potential. However, if bit MBO contains a 1 and bit ACO contains a 0 after the carry,
an overflow has taken place. Both NAND gates are disabled under these conditions, and the

ADD OV level is generated by a negative output level from all four inverters. The ADD OV
level conditions a link input gate which is strobed by the following timing pulse TP1 and sets
the link. A few nsec later, timing pulse T1 resets the POV flip-flop.
The OP SKP (operation skip) negative level is generated at tenninal H10F and conditions a
gate in the PC control that increments the contents of the PC when an OPR instruction contains
anyone of six· possible skip microinstructions. The OP SKP level will be generated and the
contents of the PC incremented at time T5 if anyone of the following sets of conditions is fu 1-

fi lied:
1 • Bit 8 is 0, bit 9 is 1, link is set.

2. Bit 8 is 0, bit10isl, contents of AC are zero.
3. Bit 8 is 0, bi t 11 is 1, bit ACO is 1 (sign negative).

4. Bit8isl, bit 9 is 1, link is not set.
5. Bi t 8 is 1, bit 9 is 1, contents of AC are not zero.
6. Bit8isl, bit 9 is 1, bit ACO is 0 (sign positive).
The AC=O and ACID levels ore generated by the NAND gates contained in modules J8, J9, and
Jl0 (Al, B1, 26), which sample the contents of each individual bit of the AC and give a ground

level at terminal Jl0V if, and only if, all bits are O.

3-24

Note that when more than one skip condition is specified in a single instruction, the combined
skip condition is the inclusive OR of the individual conditions when bit 8 contains a O.

How-

ever, when bit 8 contains a 1, the combined skip condition is the AND of the individual conditions specified in bits 9 through 11 •

Program Counter Register Control (25) - All of the command pulses which clear the PC, increment its contents, or cause a transfer of informcltion into the PC from other registers are generated in the control logic circuits shown at the bottom right of engineering drawing 25. This
logic element consists of six pulse amplifiers which generate the command pulses, together with
diode gates and inverters which determine the conditions under which each pulse amplifier is
triggere~ •

The pulse amplifier circuit FDEC at location D17 generates a 0 clears bits 5 through 17 of the PC.

PC command pulse whic h

Bits 3 and 4 are used in conjunction with an extended

memory and are cleared by a pulse from the Type 148 Extend Mode Control option.

Bits 5 through

17 of the PC are cleared by anyone of the fo lIowing conditions:
1. At time SPl of a key cycle, after operation of the START I EXAMI NE,
or DEPOSIT key

2. At time T5 of the fetch cycle of a JMP instruction, in preparation for
the transfer of a new address from the MB

3. At time T3 of the execute cycle of a JMS instruction or at time T3 of
CI program break cyc Ie

4. At time SPl of a key cycle during a readin operation, provided that
the RPT flip-flop is in the 0 state.
The pulse amplifier circuit RNPM at location D16 generates an AS1 -

PC command pulse

which causes the contents of the ADDRESS switch register to be transferred into the PC. The
command pulse is generated by either of the following conditions:

1. At time SP2 of a key cycle, after operation of the START, EXAMI NE,
or DEPOSIT key
3-·25

2.' At time SP2 of a key cycle during a readin operation, provided that
the RPT flip-flop is in the 0 state.
The pulse amplifier circuit FDEC at location 016 generates an MBl PC command pu Ise which
causes the contents of bits 5 through 17 of the MB to be transferred into the PC.
receive a similar command pulse from the extend mode control. The MB1 -

Bits 3 and 4

PC pulse is genyo"'!!,

erated at time T6 of the fetch cycle of a JMP instruction; the information transferred is theaddress from which the next instruction is to be fetched.
The pulse amplifier circuit RNPM at location 017 generates the MAl-

PC command pulse

at time T4 of the execute cycle of a JMS instruction, or at time T4 of a program break cycle.
The contents of the MA are the address at which the current program count is to be deposited;
this address is 0 for the program break.
The +1 -

PC pu Ise increments the contents of the PC by 1 and is generated by two cascaded

pulse amplifiers: FDCE at location J16 and SPNM at location F26. The second pulse amplifier
introduces a deley of 20 nsec between the time at which the flip-flop outputs are sampled by
the PC -

MA pulse, and the time at which the contents of the PC are increr.1ented during a

fetch cycle. The gating associated with these two pulse amplifiers causes the incrementing
pulse to be generated by new instructions and during skip, jump, and special mode operations.
The incrementing pulse is generated in the following circumstances:

1. At time SP2 of a read paper tape operation
2. At time SP4, following operation of the EXAMI NE or DEPOSIT key
3. At time T1 of a fetch cycle
4. At time T5 of the execute cyc Ie of a SAD instruction if the contents of
the AC are not O. The E • SAD and ACID levels which condition the NAND
gate in modu Ie 014 are both generated in the AC control.

5. At time T5 of the execute cycle of a JMS instruction, or at time T5 of
a program break cycle. The E • JMS component of the level which conditions

3-26

terminal E of module D12is generated by the'maior state generator and
IR.decoder (24); the PROG • B component is -generated in the interrupt con-

trol (32).
6. During the execute cycle of an ISZ instruction, at time T3, if a carry
pulse is generated by bit MBO of the MB, indicating that the contents of
the MB are O.
7. At time T5 of an OPR instruction microprogrammed for one of the six
possible skip operations, if the conditions for the skip are fu Ifi lied. The
OP SKP (operation skip) level and the OP 1 pulse applied to terminals Pand R of module D12 are both generated in the AC control.
8. At ti~e T6 of a program break cycle after an illegal instruction is trapped,
when the system is operation in the trap mode. The positive TRAP pu Ise that
is applied directly to pulse amplifier input J16F is generated by a one-shot
when the TRAP FLAG flip-flop is set •.
9. During an I/O device identification operation, when the flag of the
selected device is set.

Memory Address Register Control (25) - All of the command pulses which cause a flow of information into the I'M are generated by the control circuits shown at the top right of engineering drawing 25. This control element consists of two Type B602 FLIP CHIP modules, each
containing two 40-nsec pulse ampl ifiers; a Type B113 FLI P CHI Pmodule containing four diode gates
and associated inverters; and a Type B115 FLI PCHI Pmodule containing three diode gates and a5SOC iated
inverters.
The pulse ampl ifier circuit RNPM at location A 15 generates standard negative pulses which
clear the entire MA under either of the following conditions:
1. At time SP1 of a key cycle after operation of any key except the STOP

key.

3-27

2. At time T7 of each computer cycle, provided that the RUN flip-flop is
in the 1 state. This action prepares the MA for the insertion of a new address
at time T1 of the following cycle.
The pulse amplifier circuit RNPM at location A17 generates a PCl -

,MA pulse which trans-

fers information from the PC to the MA at time Tl of every fetch cycle. The address set into
the MA by this action is that of the next instruction to be executed.
The pulse amplifier circuit FDEC at location A17 generates a MBI -

MA pulse which transfers

information from bits 5 through 17 of the MB into the corresponding bits of the MA. The tro nsfer occurs at' time T1 of a defer or execute cycle, provided that the instruction below executed
is not CAL (call subroutine). Either a 0 ground level at terminal A14D or an E ground level
at terminal A14E conditions terminal A14L with a negative level. A negative CAL level derived from the MB control conditions terminal A14M. 'A'hen timing pulse Tl reaches terminal
A14K, the positive pulse which appears at terminal N triggers the MBl The pulse amplifier circuit FDEC at location A15 generates a 20 -

MA pulse amplifier.

MA pulse which sets

octal 20 into the MA during the defer or execute cycle of a CAL inst.uction. The NAND
gate RSTU of module A14 is conditioned by a negative 0 or E level and by a negatrve CAL
lE~vel derived from the MB control.

When timing pulse Tl reaches terminal R, the positive

pulse which appears at terminal U triggers the 20 -

MA pulse amplifier.

Memory Buffer Register Control (25) - All the command pulses which clear the MB, increment
its contents, and cause or inhibit a transfer of information into the MB are generated by the
logic circuits shown at the left of engineering dra~ing 25. Four pulse amplifiers contained in
two Type B602 FLIP CHIP modules and one Type B620 Pulse Amplifier generate command pulses.
A Type B684 Bus Driver provides negative or ground levels, which condition or inhibit the
gates connecting the MB to the memory sense amplifiers. Diode gates and inverters combine
various levels and timing pulses to select the conditions under which each command pulse is
Henerated.
The 0 -

MB command pulse clears the entire MB register and is generated by the pulse amp-

lifier circuit RNPM at location 01. This pulse amplifier is triggered by the BGN pulse of a key
cycle, at time T2 of every computer cycle,. and at time T7 of an execute cycle initated by a
Ireadin operation.

3-28

The Type 8684 bus driver at location A10 produces a negative MB STS I NH (not MB strobe inhibit) level continuously, thereby permitting the logic 1 pulses generated by core memory
sense amplifiers to set the corresponding MB flip-flops during the read operation in every cycle.
During certain operations, however, the contents of a memory cell are not transferred into the
MS. For these operations, a ground MS STS INH level inhibits the gates between the sense
amplifiers and the MS. Anyone of the following conditions causes generation of the MB STB

INH level:

1. During a program break cycle, the negative PROG • B level generated
by the interrupt control is applied to t'erminal T of diode gate modu Ie H21
and is inverted.

2. A high-speed I/O device requesting a break cycle to deposit information
in memory generates a negative DATA-IN level, which conditions terminal

H21 K. When the data break is granted, the negative DATA • B level produced by the interrupt control conditions H21 J and causes the NAND gate
to produce a ground level at the input of the bus driver.
3. During the execute cycle of a JMS or DZM instruction, the E level

from the major state generator conditions terminal H21 Ei and the lAO level
produced by the IR decoder conditions terminal H21 D. The NAND gate
then produces a ground level output wh ich is applied to the bus driver.
The +1

MB command pulse increments the contents of the MB by 1 and is generated by two

cascaded pulse amplifiers: FDEC of module C1 and EHD of module F26. These pulse amplifiers
are triggered by anyone of the following conditions:

1. Time T3 of a defer eye Ie, when the contents of the MA are one of the
auto-indexing locations 10 through 17. All of these locations, but only
these, are defined by a 0 in MA bits 5 through 13 and a 1 in bit 14. The
MAS-13 (0) and MA14 (1) levels are combined in module 06 with the D
level from the maior state generator cmd condition input terminal P of a
NAND gate in module 02. When timing pulse T3 is applied to terminal
D2N, the gate is triggered, and its positive output pulse causes the 'pulse
amplifiers to generate the +1

MB pulse.
3··29

2. When a real-time clock is in use and is enabled by the program, the
CLOCK • B level produced by the interrupt control when a clock break is
granted conditions NAND gate JKL in module D2. Timing pulse T3 triggers
the gate and causes generation of the + 1 -MB pulse.
3. During the execute cycle of an ISZ instruction, the E level from the
major state generator and the IA2 and IB 1 levels produced by the IR decoder
are NAND combined in module D5. The output of the gate is inverted and
conditions NAND gate DEF in module D2. When timing pulse T3 is applied
to term inal D2D, the gate is triggered and causes generation of the + 1 - MB
pulse.
The AC 1- MB command pulse 'is generated by pulse ampl ifier circuit RNPM of module C 1 and
causes the contents of the AC to be transferred into the MB. This command is generated only
during the execute cycle of a DAC instruction. The E level from the major state generator is
NAND combined in module D5 with the lAO and IBl levels produced by the IB decoder. The
output of the gote is inverted and conditions NAND gate TUV in module D2.. When timing pulse
1'3 is appl ied to term inal T,the gate is triggered and causes generation of the AC 1

MB pu Ise.

The PCl- MB command pulse is generated by pulse amplifier circuit FDEC in module D1 and
c:auses the contents of the PC to be transferred into the MB. This command is generated by any
one of the following conditions:
1. During a read paper tape operation, the RPT (1) level conditions NAND
gate DEF in module D9. Timing pulse SP4 triggers the gate, and the positive
pulse which appears at terminal F triggers the pulse ampl ifier.
2. Dliring an examine or deposit operation, the EX+EXN+DP+DPN level generated by the key circuits conditions NAND gate JKL in module D3. Timing
pulse SP3 of the key cycle triggers the gate and causes generation of the
PC 1- MB pulse_
3. During a program break cycle or the execute cycle of a JMS instruction,
the E· JMS+PROG-S level conditions NAND gate DEFofmodule D3.

3-30

Timing pulse T3 triggers the gate and causes generation of the PC 1 - MB pulse.
The derivation of the conditioning level was explained in condition 5 for
the +1- PC pulse (PC control).

I/O Skip Control and I/O Trap
I/O Skip Control (32) - The I/O skip control Edement provides a means of skipping an instruction as a function of the performance of an lOT instruction microprogrammed to sense the state
of a device flag. The flag sensing gates are shown at the botton right of eng ineering drawing

32. Each of the diode gates conta ined in modul es L13 and M 13 is cond it ioned by a negative
level g'enerated by the flag of the associated device. The gate is strobed by an lOT command
pulse generated in the device selector; and, if the device flag is set, an 10 SKP pulse is generated, which causes the contents of the PC to be incremented by 1. (Refer to the description
of the PC control and engineering drawing 25.) The lOT command pulse occurs at time T5 and

is generated by combining the device selection signal decoded from bits MB6 through MB11 with
an I/OP 1 pulse initiated by a 1 in bit MB1S.

I/O Trap (23) - The I/O trap permits time-sharing of the processor by two programs' running in
different memory fields by ensuring that instructions which would halt the machine, or would
cause interference between the two programs, are not executed. Specifically, the I/O trap
monitors the program for lOT instructions, for XCT instructions whose subject instruction is also
an XCT (such instructions could put the machine into a loop from which it co,uld not escape),
and for instructions of the operate class containing a microprogrammed HLT command. Whenever one ot these illegal instruct'ions is detected by the trap, a program break is substituted
for the trapped instruction. The contents of the PC, together with the status of the I ink, the
extend flag, and the trap flog, are stored in location O. Control of the CP then transfers to
locotion 2, and the subsequent sequence of events depends on the nature of the trapped instruction.
To enable the trap mode, the I/O TRAP flip-flop (B5, 23) is set by NAND-combining a negative I/O TRAP SW level, a negative trap enable level (MB12 (1) • MB13 (1) ), and a negative
lOT 0002 command pulse. The I/O TRAP (l.) level conditions the various gates which detect
conditions requiring that the TRAP FLAG fl ip··flop be set.

3-31

The TRAP FLAG fl ip-flop is set when the I/O TRAP fl ip",:,flop is set and anyone of the following
sets of conditions occurs:

1. Any lOT instruction is detected. 'The minor states IA3 ·182 are produced
by all lOT instructions and are NAND combined in module J23 (C4, 23) with
the I/O TRAP (1) level. Timing pulse T3 strobes this gate to produce a positive
output pulse, which sets the TRAP FLAG flip-flop.
2. A microprogrammed H LT command is detected. The H LT command is generated by an OP') pu Ise in combination with an MB 12 (1) level; both these
signals are NAND combined in module J24 (B5, 23) with the I/O TRAP (1)
level. The gate produces a positive ILL HLT pulse which sets the TRAP
FLAG fl ip-flop.
3. If an execute (E) state is set into the maior state generator, and the IR
contains the operation code for execute, an E • XCT level is produced. This
level is NAND combined with timing pulse T2 in module L24 (C8, 23), thereby
setting the SCT CY fl ip-flop to 1. The SCT CY (l) level is NAND combined
in module H24 (B8/ 23) with the I/O TRAP (1) level, and with the IA2 and
IBO minor state levels produced by the IR. Timing pulse T2 strobes the gate
to produce a positive ILL XCT pulse which sets the TRAP FLAG fl ip-flop.
The XCT CY flip-flop is reset to 0 by timing pulse TP7 of the same memory
cycle.
The sett ing of the TRA P FLAG fl ip-flop produces a negative TRAP FLAG (1) 'Ieve I, which is
applied to the program interrupt control and generates a PROG RQ level.

(For details of

how this level causes a program break, refer to the discussion of the program interrupt control,
below.) When a program break is granted by the break control, a PROG • B level is generated.
This level is NAND combined with timing pulse T4 of the break cycle in modules J22 and K19
to reset the TRAP FLAG and i/O TRAP fl ip-flops, respectively.
l"he resetting of the TRAP FLAG fl ip-flop generates a positive-going level transition at its output terminal E; this transition triggers the one-shot in module L32 (B3, 23) into its astable state.
The negative level which then appears at output terminal M of the one-shot increments the contents of the PC at time T6 of the break eyc Ie.
3-32

Break Control (32)
The break control contains all the logic elements required for causing an interruption of the
main program to permit an external or auxi Iiary device to be serviced, and for returning to
the program sequence when the servicing operation has been completed _ The break c:ontrol
provides for the following three distinct classes of interruption:
1. A data channel break, which lasts for one computer cycle and permits Cln
E~xchange of information between the central processor and a high-speed

-I/O device capable of transferring 15 address bits and 18 data bits in parallel.
2. ·A clock channel break, which also lasts for one computer cycle and permits
a real-time cl.ock to add 1 to the contents of memory location 7 8

:3. A program break, which stores the current program count in memory loca~ion 0 and initiates a subroutine (beginning in location 1) to find and service

a slow I/O device which has requested a break. In the following discussion
of the break control, component and signal references are to engineering
logic diagram 32, unless otherwise stated_

Data Channel Control - A data break request, since the break never lasts for more than one
computer cycle, takes priority over all other forms of break request. A high-speed I/O device
may originate a data break request by placing a - 3v DATA RQ level on the request line connecting the device to the computer.

In the interrupt control, the DATA RQ level is NAND

combined with timing pulse T5 (DLY) of a current computer cycle; and the resulting positive
pulse sets the DATA SYNC fl ip-flop (A 1, 32) to 1. The positive DATA SYNC (1) output of the
flip-flop is NOR combined with similar levels from the CLOCK SYNC and PROG SYNC flipflops _ If anyone of these flip-flops is set to 1, a negative BK RQ leve I appears at term ina I
L15J (A8, 32) and is transm itted to the major state generator. Completion of the current instruction permits the major state generator to produce a negative B (break) level which is
applied to the interrupt control. The B level is NAND combined with the DATA SYNC (1)
level to produce a negative DATA • B level at terminal L23J (A2, 32). At time Tl of the
break cycle, the DATA • B level is NAND combined with timing pulse Tl to produce a DATA
ADDR-MA pulse at terminal L16H (el, 32). This pulse causes the memory address contained
3·-33

in the address register of the I/O device to be transferred into the CP memory address register.

At time T3, the DATA • B level is NAND combined with timing pulse T3 to produce a negative

MB INFO -OUT pulse at terminal L16U. This pulse indicates to the I/O device that information for outward transfer is available in the memory buffer. If the requesting device is transmitting a negative DATA IN level, this is NAND combined with DATA·B and T3 to produce
a negative DATA INFO- MB pulse at terminal l16N (C1, 32). This pulse opens the data
channel interrupt input gates of the memory buffer. During the remaining portion of the break
cycle, the memory performs a normal write operation, depositing the received information (or
rewriting the transmitted information) in memory. If the device has no further information to
transmit or accept, the DATA RQ line goes to ground level. This DATA RQ ground level is
inverted and combined with the T5 DlY pulse in NAND gate NPR of module l17 to reset the
DATA SYNC flip-flop to O. As a result, a BK RQ negative level is applied to the major state
generator and permits it to enter the fetch state so that the main program can continue.

Siock Channel Control - The real-time clock consists of a Schmitt trigger (Type W501 FLIP
CHIPmodule) which produces square pulses when fed from a source of6.3v, 60 cps. The output pulses of the Schmitt trigger are appl ied to the pulse amplifier in location l25, which
produces standard 70-nsee negative pulses (B3, 32). The clock is enabled by a ClON instruction (700044 ); the device selector decodes the instruction and produces an lOT 0004 pulse

which clears the ClK FLAG flip-flop. This pulse is NAND combined with MB12 (1) to set
the CLOCK ENABLE flip-flop to 1. The next clock pulse is NAND combined with the CLOCK
ENABLE (1) level and sets the elK COUNT RQ flip-flop. Timing pulse T5 of the current cycle,
delayed by 50 nsec, is NAND combined with the ClK COUNT RQ (1) level and sets the ClK
SYNC fl ip-flop. The C lK SYNC (l) Ieve I is appl ied to modu Ie l22 and generates a BK RQ
level that initiates a break cycle at the earl iest opportunity.

If no data break is in progress,

the ClK SYNC (1) and B levels are NAND combined to produce a ClOCK·B level at terminal
L23M (A3, 32). At time T1.of the clock break cycle, the ClOCK·S level is combined with
timing pulse T1 in NAND gote DEF of module 1 L24 (B 1, 32). The output of the gate triggers
(I

pulse amplifier which generates a 7 -MA negative pulse. This pulse clears the ClK COUNT

RQ flip-flop and sets bits MA15, MA16, and MA17 to 1, thereby addressing location 7 of the

memory. At time T3 of the break cycle, the CLOCK"B is NAND combined with the timing
pulse T3 to produce a +1- MB pulse (MB control, 25). If the resulting increment causes the

3-34

memory buffer to overflow, an MBO CRY pulse is generated (30) and is combined with the
ClOCK·S level (C2, 32) to set the ClK FLAG flip-flop to 1. The setting of the CLOCK
FLAG fl ip-flop is one of the conditions which can cause a program break, as described below.

If there is no overflow and the clock flag is not set, timing pulse T5 of the break cycle (delayed
by 50 nsec) is combined with the ClK COUNT RQ (0) level to clear the ClK SYNC flip-flop.
During the remaining portion of the clock break, the incremented contents of the memory buffer are written into memory location 7. If no other break request has been originated before
time T5, the major state generator is set to fetch at time T5, and the processor continues the
main program. However, while the ClK ENABLE flip-flop remains set, a clock break will
,occur every ·1/60 sec. A C lOF instruction (700004 ) is required in order to disable the clock;

the lOT 0004 pulse clears the ClK FLAG flip-·flop and is combined with the MB12 (0) level to
clear the C lK ENABLE fl ip-flop.
Note that when the Type 172 Automatic Priority Control (API) option is included in the system,

it replaces the standard real-time clock. The real-time clock and the associated ClK ENABLE
and ClK FLAG flip-flops are removed, since the API contains corresponding logic. The negative IN~ RQ levei from the API is connected to terminal E of the ClK COUNT RQ flip-f!:)Pi
and the same level, inverted in module J20, is connected to terminal F.

Program Break Control - A program break may be initiated by the Teletype, the punch, the
tape reader, and other slow-speed peripheral equipment. The break may be requested whenever the setting of the associated flag indicates that a device is ready for an information transfer, or the status of the device requires some other kind of action. The setting of the real-time
clock flag {indicating that the contents of memory location 7 have overflowed} or the trap
flag (indicating that an illegal instruction has been trapped) can also initiate a program break.
However, the program interrupt control (PIC) may be disabled by the program to delay the
granting of a program break. until a particular sequence of operations has been completed.
The PIC is enabled by cn ION instruction (700042 ). The device selector decodes the instruc8
tion to produce an lOT 0002 pulse. This is combined in NAND gate TUV of module L21 (B4,

32) with the MB12 (1) level, and sets the PIE (program interrupt enable) flip-flop. Similarly,
an IOF instruction (700002 ) clears the PIE, fl ip-flop. The (1) level of any device flag which
8
has been set enters the interrupt control through one of the 7-channel gates In locations L14
3-35

and M14. Providing that the PIE flip-flop has been set"andthat the maior state generator is not
already in a break state, the flag generates a PROG"RQ level (FLAG- PIE (1) B= PROG RQ,
see AS, 32).
At time T5 of the current cycle, the PROG RQ level is NAND combined with timing pulse
T5 DlY and sets the PROG SYNC flip-flop. The setting of this flip-flop produces a negative
BK RQ level which is applied to the major state generator. When the CP reaches an "instruction done ll situation, the maior state generator establishes a break state, and the B {break}
level is "combined with the PROG SYNC (1) level. Provided that neither a data break nor
a clock break has been requested in the meantime, a" negative PROG -S level appears at terminal
L23U (AS, 32). The PROG-S level is used in the I/O trap logic and, at time TS, is combined
with the TS timing pulse to reset the PIE flip-flop. The PIE (0) level, inverted, clears the
PROG SYNC flip-flop. Since the PIE fl ip-flop can only be set to 1 by another ION instruction, a second level of interrupt is prevented. The flow diagram (21 )shows the complete sequence of events which takes place during the break cycle of a program break.

INTERFACE

All information transfers between the CP and I/O equipment (other than devices Which use the
dlata break facility) take place under program control by way of the interface equipment and
the accumulator register. Selection of an I/O device and generation of control pulses ta~es
place in the interface logic. Gating circuits to control information flow are located at the
input of the receiving register. The interface logic consists of three elements:
1. A device selector which decodes the lOT instruction to be executed,
addresses the appropriate I/O device, and generates up to three lOT command pu Ises for control purposes.
2. An information collector which gates incom ing information into the
accumu lator reg ister.
3. An information distributor, consisting of bus drivers capable of driving
an output bus system through which information is transferred from the accumulator register to I/O devices"

3-36

Device Selector (36)
The device selector (engineering drawing 36) contains a decoder module, a gate module, and
a pulse amplifier module for each I/O device. In the standard PDP-7 system, 20 sets of device
selector equipment are supplied, of which 6 are unassigned. The decoder module decodes
bits MB6 through MB11 of an lOT instruction word held in tt,e MB and produces a ground deviceenabl ing level and a negative gating level. The negative level enables the gates of the associated gating module which route any lOP pulses generated to the addressed device. The
positive.pulse which appears at the output of each gate is applied to a pulse amplifier which
generates a standard 70-nsec command pulse for control Iing the operation of the addressed
device. The following discussion of the device selector is based on Figure 3-2, which shows
the logic of the selection equipment associated with one I/O device.
The decoder consists of a Type 8171 FLIP CHIP Diode Gate containing twelve diode inputs and
two inverters. The input terminals of the module are connected to the bus drivers associated
with the (1) and (0) levels of memory buffer bits MB6 through MB 11. A device assertion leve I
is obtained by clipping O'Jt diodes associated with unasserted levels of the selection code (e.g.,

if the selection code were 010101, the diodes removed would be the ~1) level diodes of bits
MB6, MB8, and MB10, and the (0) level diodes of bits MB7, MB9, and MB11). The positive
assertion level for the selected device appears at terminal D of the decoder module, and may
be routed to the device for enabling purposes. The negative level appearing at terminal E is
cppl ied to the gating module.
The gating module consists of a Type R111 FLiPCHIP Diode Gate containing three inverters,
each having two diode inputs. The negative clssertion leve I for the device enables one input
of each of the inverters; the second input of each inverter is connected to one lOP timing
pulse bus. An IOP1 pulse appears at time T5 of the computer cycle in which the lOT instruction
is executed, if bit 17 of the instruction word contains ali an IOP2 pulse appears at time T7
of the same cycle, if bit MB16 contains a 1; and an IOP4 pulse appears at time T1 of the
following computer cycle if bit MB15 of the instruction word contains a 1. The selection of a
device causes any lOP pulses generated to be applied to the pulse amplifer module of the corresponding device selector channel.

3··37

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"89111

M810101

I
BUS CONNECTIONS
'ROil WOlOR'I'
IU"ER REGISTER
!IUS ORIVER OUTPUT
OF PROCESSOR

I
I
I

I
WI~(II

"SII(OI

"SH(II

I
I

_-.J

Figure 3-2

I lOT DEVICE

~~D~Ei~~~L.E

E
--"",-,L.U...I"':D:---""'" ! CAN 6£ USED
FOR S<.OW C'!'CLE
REQ'JEST I

Device Selector logic Diagram

3-38

Positive pulses from the gating module of a selected dev.ice are applied to corresponding pulse
amplifiers contained in a Type W607 or Type W640 FLiPCHIP module. The pulse amplifiers
of a Type W607 modu Ie produce standard - 2. 5v, 70-nsec output pulses. Those of a Type W640
module normally produce a - 2.5v, 400-nsec pulse, but by jumpering the appropriate terminals
on the module, the pulse length can be extended to 1 tJsec if the nature of the I/O device
requires it. Each module contains three pulse amplifiers. One of these, triggered by an IOPl
pulse, produces on lOT XXOl pulse {where XX is the device number}, which may be used to
sense the status of a device flog. The second, triggered by on IOP2 pulse, produces an lOT
XX02 pu'lse which may be used to clear the device flag and read the contents of the device
buffer register into the accumulator rp,gister. The third pulse ampl ifier, triggered by an lOP4
pulse, produces on lOT XX04 pulse which may be used to transfer data from the accumulator
register through the information distributor into the device buffer. All three pulses may also
be used te) initiate control functions within the selected device.

Information Collector (33)
The information collector consists of 18 7-chonnel NAND gates Type R141, each of which is
associated with one bit of the AC.

Each channel has an upper hal f and a lower half correspond-

ing, respE:!ctively, to bits 0-8 and 9-17 of the AC.

If an I/O device occupies only one-half

of a channel, the other half may be used for other purposes. From engineering drawing 32 it
will be seen that in the basic PDP-7 system, the paper tape reader occupies the whole of
channell; the associated gates are strobed by an lOT command pulse 0102 generated in the
device selector. The status reg ister (for flag mon itoring) occupies the upper hal f of channe I 2;
the lower holf of this channel is not used. The MQ register of the EAE occupies all of channel

3; the Teletype LUO occupies the lower half of channel 6; and the EAE step counter occupies
the lower half of channel 7. Provision is made to accommodate an optional DECtape machine
on channel 4, a magnetic drum device on channel 5,and tape status and drum status signals
in the upper halves of channels 6 and 7, respectively. The information collector can be expanded
almost indefinitely by adding gate mC?dules. The first expansion, which adds six channels, requires 18 Type R141 Diode Gate modules and 6 Type W607 Pulse Amplifier modules .. Additional
expansions, in increments of six channels, require only Type 141 Gate modules.

3-·39

Information Distributor (34)
The information distributor of the basic PDP-7 system consists of 9 Type R650 Bus Drivers and
16 Type W021 Cable Connectors to distribute the bus driver output signals.
Type R650 module contains two inverters and two bus drivers.

Note that each

Negative logic 1 assertion levels

from the AC appear as ground logic 1 assertion levels on the distribution buses. The information
distribution can be expanded almost indefinitely by adding W021 Connectors, with additional
bus drivers if the maximum load (5 ma) on the standard drivers is likely to be exceeded.

MB Bus Drivers (28)
The 1 and 0 levels of the MB flip-flops are available for distribution within the CP and to external devices connected to the data channel.

Nine Type B684 FLIP CHIP Bus Driver modules

are used for the 1 levels, and nine for the 0 levels. Each module contains two bus drivers,
clOd each bus driver can supply up to 40 ma of load.

3-40

CHAPTER 4
CORE MEMORY

Data and instruction storage and retrieval are performed in the PDP-7 by the core memory.
The standard PDP-7 is equipped with a DEC Type 149A Memory Module which can store 4096
18-bit w()rds and which requires a 12-bit address. The addition of a DEC Type 147 Core

Memory' Module expands the memory capacity of the Type 149A Memory Module of the standard PDP-7 to 8192 words.

No auxiliary equipment is required since the extra address bit re-

quired for sel ecting addresses in either 4K memory array is provided by the existing 15-bit
memory address register (MA). Memory capacity can be further expanded by increments of
4096 or 8192 words to a maximum of 32,768 words. Expansion beyond 8K requires 'the use of
a DEC Type 148 Memory Extension Control and of the remaining two bits of the MA. All information enters and leaves core memory via an input/output register designated the me.mory
buffer register (MB). This manual describes the operation of the 8K memory; the basic principles and methods of access to this memory are equally applicable to larger or smaller capacities.
For information on methods of accessing extended memories, refer to the maintenance manual
for the Type 148 Memory Extension Control.

MEMORY ORGANIZATION
Each 4K core memory module used in the PDP-7 is a simple, coincident-current, ferrite-core
array assembled from core planes 64 cores wide by 64 cores deep. Each module is operated by
read, write, and inhibit currents originating In transistor power supplies and gating circuits.
Figure 4~1 shows the interrelationship of the elements which constitute the core memory system. The MA and tv'B are located in the cenlral processor (CP). Timing signals which control
memory functions are derive.d from the CP timing signa I generator in order to synchron ize memory operations with CP operations. The memory cycles continuously perform a read operation
during time states T2 and T3 and a write oper<ltion during time state.) T5 and T6. This permits
random bidirectional access to any memory cell within one 1.75-l-lsec computer cycle. Both
reading and writing operations are performed during each cycle, since reading from a
memory cell destroys the content. Thus, if·the information is not to be lost I it must immediately

4-1

be rewritten into thesame cell from the MB. The only exceptionstothis .rule occur during a
data break in which the direction of transfer is into the computer core memory and during the execution of DAC, JMS, or DZM instructions.

FROM MEMORY
ADDRESS REGISTER
OF PROCESSOR

ADDRESS (MA 0 -11 )
SELECT ......
READ
WRITE

.....

MA4.MA5

-~
FROM POWER CLEAR
AND TIMING PULSE
GENERATORS OF
PROCESSOR

TIMING PULSES

MEMORY
r--- SELECTOR

DATA (MB 0-11)

FROM MEMORY
BUFFER REGISTER
OF PROCESSOR

MEMORY
SELECTOR
SWITCHES
(G2021

....

......

MEMORY

CONTROL

SELECT

IN~

X AXIS

MATRIXES
(G601 G602)

READ)WRITE
SUPPLY CURREN1:S

FERRITE CORE
MEMORY ARRAY

INHIBIT
DRIVERS
(G2011

INHIBIT
SUPPLY CURRENT
STROBE ...

TO MEMORY BUFFER
REGISTER AND
INSTRUCTION REGISTER
Of PROCESSOR

...

SENSE
AMPLIFIERS
(GOOI)

DATA (SA 0-11)

-...

i
MASTER
SLICE
CONTROL
(G002)

Figure 4-1

Core Memory System Block Diagram

CIRCUIT OPERATIONS

Ferrite-Core Memory Array
The standard memory array consists of 18 planes, each having 4096 ferrite cores arranged in a
64 by 64 square. Each core can assume one of two stable magnetic states corresponding to
binary 1 and binary O. Each core is traversed by four windings. An X read/write winding
passes through all the cores in one horizontal row; a Y read/write vdnding passes through all
the cores in one vertical row; the sense and inhibit windings each I-'oss through all the cores in
the plane. An example of this winding is in Figure 4-2 for a 4 by 4 core plane.

In Figure4-2,

passing a current from right to left (write direction) of the diagram through the X2 winding

4-2

produces a magnetic field that tends to change all the cores in that row from the 0 to the 1
. state .'Pass.ing a current from bottom to top of the diagram through the Y3 winding produces a
similar effect on the cores in that row. Neither the X current nor the Y current is, by itself~
strong enough to change the state of any core. However, if both X2 and Y3 currents are turned
on, the ITWJgnetic fields due to the two current'S are mutually re inforcing in one core through.
which both windings pass. The combined strength of both' fields causes this, and only
this, core (in each plane) to change state to the 1 condition. In the PDP-7 system, an array
consists of 18 planes, with all the correspond ing address windings connected in common so that
each pla~e can be considered equivalent to one bit of a storage cell. Thus, in the previous ex"

ample, the core located at coordinates X2Y3 on each' plane will change to the 1 condition unless
it is prevented from doing so by an inhibit current.

READ

INHIBIT

Iv l
WRITE

WRITE~READ
INHIBIT
WINDING

Figure 4-2

Simple Core Memory Plane Showing Read/Write,
Sense I Qnd Inhibit Windings

4-3

If the storage celt consisting of X2Y3 cores is to contain O's as well as lis, the cores in the
planes which correspond to 0 bits must be prevented from changing state when the writing currents are turned on. This is accompl ished by passing a current through the inhibit windings of
those planes. The magnetic field due to the inhibit current has a direction and ampl itude
which partially cancels the fields due to the writing currents. Thus, even though both X and Y
writing currents are present in all the X2Y3 cores, those cores in planes where on inhibit is also
present will remain in the 0 condition. After setting or resetting cores, all of the read/write
and inhibit currents are turned off without affecting the state of any cores.
To read the information stored in the X2Y3 cell, currents must be passed through all the X2
and Y3 windings in the opposite direction 1 thereby tending to change all the X2Y3 cores to
the 0 condition. Cores X2Y2 of all planes which were inhibited during writing, and eire thus
already in the 0 state, induct only a very small signal into the sense windings. However, X2Y3
c:ores which were in the 1 state will change back to the 0 state when both the X2 and the Y3
read currents are turned on. The resulting flux change will induce a relatively large signal into
the associated sense windings. After ampl ification, these binary 1 signals complete the information transfer by setting the corresponding MB fl ip-flops.

Memory Selectors Type G202 and Memory Selector Matrixes. Types G601 and G602
The memory selectors decode the information contained in the MA and perform memory cell
selection; the memory matrixes, controlled by the memory selectors, route read and write current pulses to the selected memory cell. In each memory array, address bits MA6 through

MAll select read and write lines in the matrix of the Yaxis; bits MA12 through MA18 select
read and write lines in the matrix of the X axis. Drawing E-149-0-49 shows the circuits for
Y axis selection. Note that address bits MA6 through MA8 are decoded by the four Memory
Selector Type G202 modules shown at the left of the diagram and known as drive selectors.
Address bits MA9 through MA 11 are decod~d by the four G202 modul es shown at the bottom

c)f the diagram and known as ground selectors. The selector modules provide pulses to open
oates in the Memory Selector Matrix Type G60'1 and G602 modules. A similar arrangement
of memory selectors and memory selector matrix modules provides selection of read/write lines

4-4

on the X axis, as shown in drawing E-149-0-4B. A schematic diagram of a memory selector is
contained in drawing RS-S-G202. Schematic diagrams of the matrixes ore contained in drawings RS-D-G60l and RS-D-G602.
The following discussion of the core selection process is based on the simplified schematic diagram of Figure 4-3. This diagram shows the logic switching circuits involved in the generation
of read and write currents for cell 46 on the Y axis. When cell Y46 is to be read, the address
set into the MA contains MA6(1), MA7 (0), MAS (0), MAlO (1), and MAll (0) which are applied as "negative assertion levels to the selector module.

Negated ground levels corresponding

to MA8 (1) qnd MAll (1) are also applied to the selector modules. The MA6 (1) and! MA7 (0)
negative levels enable transistor switches Q4 and Q5, respectively, of the drive selector module
at location A 1OJ similarly, the MA9 (1) and MAlO (1) levels enable transistor switches Q4 and
Q5 of the ground sel ector module at location A 13. The MAS (0) and MA 11 (0) levels are both
negative, thereby enabl ing transistor switch Q7 in both modules. Transistor switch Q2 in each
module is disabled by a negated ground level corresponding toMA8 (1) and MAll (1). These
levels ore establ ished as soon as the cell address is loaded into the MA during time s1-ate T1 of
the complAer c yc Ie.
At time T2, timing pulse TP2 sets the READ 2 fl ip-flops (Figure 4-4). The setting of the READ
1 Hip-flop, in combination with the state of the field select bits MA4 and MAS, causes 0 SEL
1 • READ 1 level to be applied to the G202 Pulser Selector, which in turn applies a pulse to the
read pulser ,thereby connecting read drive bus 4 to the positive supply. Simultaneously, the
READ 2 (1) level enables transistor switch Q4 in both drive and ground selectors. The surge of
current through the transistors causes pulses to be generated which open pulse gates PG1 and
PG4. A read half-select current then flows from the read/write memory current supply through
the read pulser, pulse gatePG 1, diode 01, the cores of cell Y46, diode 03, and pulse gate
PG4 to the read/write common negative line. This half-select read current is factory adjusted
to approximately 330 rna. At time T3, the READ flip-flops are both cleared in preparation for
a write operation.
At time T4, timing pulse TP4 sets the WRITE 1 and WRITE 2 flip-flops, thereby enabling the
write pulser and transistor swi tch Q8 in the drive and ground selector modul es. The resul ting
pulses connect write drive bus 4 to the positi~e read/write current supply and opens pulse gates

4·-5

CORES 01'

r-------------1I:1(j,Q ~ t

CELL Y46
L-__~___________________+_--------~-------~R~EA~O~OR~[~S~-- __ -

+ READI WAITE
S!.PPLY

TO CELLS
Y40 THRU Y4~

",N

$[1. I-READ I
H

SEL I

T
G202
802

P,R

SEL I-WRITE I

PG3

MAO
~---------_r---~~----+_-------WRITE

01 READ 2
WRITE 2

M•• iOI
MAS 111

MA1 101

M:.6 (Il

0:5 - - ot '

I
I
I
I
I
01
T
I
I
I
Qll
U
I
Q4
V
I
L ____________________ I
~

DRIVE $[LECTOR

Figure 4-3

,...-_-., ...Q

SUPPLY

-------,I
Ot

WRITE 2

MAti 10\

1llA11 I II

MAIO III

MAgill

Qll

L _________________
GROUND SELECTOR

Typical Core Selection Circuit and Drive Current Path

PG2 and lPG3. A write half-select current then flows from the supply, through pulse gate
PG2, diode 04, the drive Iines of the cores of cell Y46 (in the opposite direction to the read
pulse), diode 02, and pulse gate PG3 to the read/write common negative line.

o
I

200

400

TPI TP2

(90t

(480)

1000

: (160)

(300)

MB-i
STROBEttRTN

1200

TP4

TP3

MA CHANGE

t~ DONE

800

600

1400

TP5

t t
(120)

TP6
(210)

(240)1

LAST FF CHANGE

~ I

INH

l1020 WRITE 1

510

I
1450

t11S0)

..
TP601

980

1,'-____
__r
READ1

1490

I
REA02

;'1
' - - - - - "

WRITE 2

980

480

I
.1
I
I
I
I

NOTES:

1. ALL TIMES FROM MEMORY ADDRESS CHANGE
2. TRANSMISSION DELAYS CAUSE INHIBIT
CURRENT THROUGH CORE TO RISE BEFORE
AND DECAY AFTER WRITE CURRENTS

Figure 4-4

Memory Control Ti ming

4-7

1750

TP7

jMf BO'S CHANGE

1600

I
1480

Inhibit Drivers Type G201
The PDP-7 memory is wired for 19 Inhibit Driver modules Type G201. Each of these modules
energizes the inhibit winding of one memory plane. Note , however, that the 19th plane is
not used in the PDP-7 system unless the Type 176 Parity Checking option is in use, in which
case a 19th plane and an inhibit driver module are added and usad for a parity bit. A schematic diagram of an inhibit driver is shown in drawing RS-B-G201, and the connection of the
inhibit drivers in the memor'y system is shown in engineering logic diagram BS-E-149-0-45.
Figure4-5shows the internallogiccircuitsofan inhibitdriver. A negative INH B level is applied
tc~ the module at terminals F and J and is NAND 'combined with the negative 0 level of the associa-

ated MB bit in transistor switches Q5 and Q2. The combined signal output of transistor switch
Q5 enables pulse gate 1, which provides the principle on/off switching for the inhibit current.
The INH B • MB (0) signal and the appropriate array SEL signal are NAND combined in transistor
gate Q2 or Q3. If a negative SEL 0 level is present, transistor Q3 conducts and enables pulse
gate 2, thereby routirig the inhibit C'Jrrent into the inhibit winding associated with bit X of
memory array O. If a negative SEL 1 level is applied to transistor gate Q4, pulse gate 3 is
enabled and routes the inhibit current into the corresponding bit inhibit winding of memory
array 1. The. memory control logic ensures that SEL 0 and SEL 1 levels can never be applied simultaneously.

Inhibit current is applied to the inhibit winding of the cores through a bol un wh ich

balances the winding with respect to ground, thereby minimizing the effects of stray capacitance and permitting increased operational speeds in the memory. Each Type G201 Inhibit
Driver can sustain a current of 350 ma for 500 nsec; however, in the PDP-7 system, the inhibit
current is normally set at approximately 290 rna.

Sense Amplifiers Type GOal and Master Slice Control Type G002
The PDP-7 memory contains 19 Sense Amplifier modules Type GOal and one Master Slice Control module Type G002. Eighteen of the sense ampl ifiers supply a standard negative pulse to
the MB when an associated core changes from the 1 state to the a state during a read operation.
The 19th sense ampl ifier provides a parity bit when the Type 176 Parity Checking option is in
-use. The master slice control suppl ies all the sense ampl ifiers with closely controlled reference

4-8

r r-CUR;;;NT-;;' ~ - - - ,
v

INHB

I
I

•

INHIBIT

POWe;R SUPPLY

1<>----+--- SEL 1
'----+---+--SEL 0

. . ..;..;.....---+--MBX (0)

t--e------"

INHiBIT
WI/llOINQ
ARRAY 0

Figure 4-5

• CURRENT
RETURN

INHIBIT
WINCING
ARRAY 1

Inhibit Logic for One Memory Cell

voltages for use in clamping and comparator stages. Drawings RS-B-GOOl and RS-B-G002
contain schematic diagrams of the sense ampl ifier and the master sl ice control, respectively.
The connection of these modules in the memory system is shown in drawing BS-E-149-0-45.
Each sense ampl ifier conta ins a 2-stage dc preampl ifier, a rectifying sl icer, an output gate,
and a pulse ampl ifier. The first stage of the dc preampl ifier has two separate gated difference
amplifiers, which share a co·mmon push-pull output stage. One input difference amplifier accepts a pulse input from the sense winding of the associated plane in memory array 0, together
with a SEL 0 ground level which gates on the difference amplifier .. The other input difference
amplifier accepst a pulse from the corresponding plane in memory array 1 and a SEL 1 enabling
level. The enabl ing levels are provided by the memory control logic and ensure maximum
stobil it Yo The sl ieer suppresses nodes induced into the sense winding of a me~ry plane by the

4-9

read/write current pulses. Therefore, only the much larger signal produced by a core changing
state con produce an output from the sense ampl ifier •

III order to obtain an output pulse of the correct shape and duration, a strobe pulse is applied
to the output gate of the sense ampl ifier. The strobe pulse is obtained by combining ti ming
pulse TP2 of the computer timing chain with a field selection signal, applying the resulting
pulse to a delay network, and reshaping the delayed pulse in a pulse ampl ifier.
The strobe pulse is precisely timed with respect to the read current pulse, so that sensing occurs
at the instant when the signal induced into the sense winding reaches maximum peak ampl itude
(Figure 4-4). If a core changes state, the slicer enables the output gate, and the strobe pulse
causes the gate to produce a 40-nsec output pulse. Th is pulse is reshaped in the pulse ampifier
and appears at the output termina1 of the module as a standard negative pulse which sets on
MB fl ip-flop.

The master slice cOlitiol module contains three reference voltage diode networks, each wi!n on
associated emitter follower output voltage control. The adjustment ra.nge of the first stage
clamp potential is from 5.0 to 6.5v; that of the second stage clamp potential is from 11 .5 to
12.4v; and that of the sl ice level is from 5.0 to 10.Ov. The first and second stage clomp levels
ore factory preset at 6.5v end 11 .4v, respectively, under a 50-me load. The sl ice level is
normally preset to 6.8v and may be adjusted so that the sense amplifier gives symmetrical deviations when the sense amplifier +lOv supply is varied to the upper and lower 'marginal levels.

Memory Control
The memory control logic generates signals which perform memory array ·selection and initiate
the generation of read, write, and inhibit currents at the appropriate times in the computer
Icycle. The logic diagram of the memory control is contained in drawing B5-D-7-0-27 I and

loll references in the following discussion of the memory control are to this diagram unless
otherwise stated.

4-10

Address bits MA4 and MAS are decoded by NAND gates in modules C21 and C22 and produce
SEt 0, SEL 1, SEL 2, and SEL 3 control signals. Each of these signals enables the sense amplifier gates associated with a particular 4K memory array. VVhen memory capacity is limited to
SK, bit NlA4 is always 0, and bit MAS selects one of the arrays in the 8K field designated.
At time T2 of the computer cycle, timing pulse TP2 sets the READ 1 and READ 2 flip-f.lops.
The READ 1 ground level output is combined with the MAS(O) or MAS(l) level to produce a
SEL • READ (1) B level which enables the read current pulser in the address selection circuits.
The negative READ 2 (1) level is app\ ied to the drive selectors and ground selectors. At time
T3, the STROBE 0, 1 pulse clears the READ 2 flip-flop first in order to disable the read/write
current pulsers; 30 nsec later, the STROBE RTN pulse clears the READ 1 fl ip-flop to disable all
the read ~~ates in the drive and ground selectors • The setting of the WRITE flip-flops resulsts
in similar actions, except that the WRITE 2 fl ip-flop opens the write gates in the memory selectors, thereby reversing the direction of the current pulse through the memory cores.
The memory control logic includes bus drivers which provide adequate current to drive the
memory selectors and to gate the inhibit drivers. The NAND gates in module C29 (AB, 27)
combine address bit MA4 with timing pulse YP2 for the generation of a separate strobe pulse
for each of two 8Kmemory fields. When memory capacity is limited to 8K, the TP2 • SEL 0,

1 pulse is used. The resul ting strobe pulse is applied to both 4Karrays of the 8K memory field".

Memory Current Sources
A Type 739 Power Supply is used in coniunction with the Core Memory Type 149B. The Type
739 unit contains two independent,. floating power suppl ies. One supply provides read/write
current, and the other provides inhibit current for a complete PDP-7 system, regardless of the
capacity of the memory. A Type 728 Power Supply provides +10v and -15v to energize the
memory logic. Both the 728 and 739 units are located at the rear of equipment bay 1, behind
the memory. Circuit schematic diagrams for the 739 are shown in engineering drawings
RS-C-739B, RS-B-W505, and RS-B-G800.

Engineering drawings RS-B-728 shows the circuit

schematic for the Type 728 Power Supply.

4-11

CHAPTER 5

INPUT/O UTPUT

Peripheral equipment may either be asynchronous with no timed transfer rates or synchronous
with a timed transfer rate. Devices such as the CRT displays, teleprinter-keyboard, and the
line printer can be operated at any speed up to a maximum without loss of efficiency. These
asynchronous devices are kept on and ready to accept data; they do not turn themselves off
between transfers. Devices such as magnetic tape, DEC tape , the serial drum, and card equipment are timed-transfer devices and must operate at or very near their maximum speeds to be
efficient.
Some of the timed-transfer devices can operate independently of the central processor after
they have been set in operation by transferring a continuous block of data words through the
PDP-7 delta interrupt facil ity. Once the program has supplied information about the location
and size of the block of data to be transferred, the device itsetf takes over the work of actually
performing the transfer. The data interrupt facil ity logic is described in Chapter 2 and the
circuit operations in Chapter 3.
Separate parallel buffers are provided on each input/output device attached to the basic PDP-7.
The high-speed perforated Tope Reader Control Type 444B contains an l8-bit buffer and binary
word asserpbler. The high-speed perforated Tope Punch Type 75D, and the teleprinter and the
keyboard of the Teletype and Control Type 649 each contain separate 8-bit buffers. These
devices are described in th is chapter.
Separate parallel buffers are also incorporated as part of DEC standard I/O peripheral equipment options. Information is transferred between the accumulator and a device buffer during
the execution time of a single-cycle lOT instruction. Because the maximum time the accumulator is associated with anyone external buffer is 1 .75 I-lsec, many standard I/O devices
can operate simultaneously under control of the PDP-7 •
. Figure 5-1 shows the data path between device buffers and the AC through the information
collector or information distributor.

5-1

OATA TRANSfERS VIA DATA BREAK

KSR 33

KEYBOARD
INFORMATION

COLLECTOR

••

...

18. BIT I. 75 " •• e

'l:OP PULSES
INFORMATlON
DISTRIBUTOR

••
•

CONTROL PULSES
TO SELECTED
DEVICE

* INCLUDED WITH OPTION

Figure 5-1 Input/Output Information Flow

SERIA L

INF~
TO 33 KSR
4--PRINTER

. l.-

AC,O
THROUGH

SHIFT

LUO
CLOCK
CLOCK AND
FREOUENCY
DIVIDER

TELETYPE
INTERFACE

LUI
CLOCK

FROM
PROCESSOR

~ AC 17

if - UNIT - CODE SERIAL t4FORMATION

....-

LINE UNIT OUT
(9-Bl", LUOl

ACCUMUL.I>.T·j~

LUO
CONTROL
P"!....

i• I

LUO FLAG

'"> i='">
~

LUI FLAG

H I
<I:

.......

•

TO
}

PROCESSOR
1/0 SKIP
FACILITY

oJ)

LUI
CONTROL

. FFIOM 33 I(SR

SERIAL
INFO ..

CONTROL

LINE UNIT OUT
tt -

UNIT - CODE SERIAL INFORMATION

,ff.YBOARO
.. '

{8-BIT LUll

IC to
THROUGH

Ie.7 ......

......

TO
PROCESSOR
INFORMATION

COLLECTOR

Figure 5-2 Block Diagram of Keyboard/Printer
Control Type 649

5-2

TELETYPE (MODEL 33 KSR) AND CONTROL TYPE 649
The Teletype Model 33 KSR is a keyboard send-receive unit, util izing a 3-row keyboard and
an 8-level code operating on serial information at sp'eecJ; "up to 100 words/min. Internal iumper
connections are made within the Teletype, as specified in the TTY manual, for full duplex
operation with local copy provisions. No other modifications are made to the Teletype for use
with the PDP-7. The Type 649 Control, used with the Teletype, provides conversion in both
directions between the serial information used by the Teletype and the parallel information
used by the processor. The logical organization of the Teletype and control is shown in
Figure 5-2. (Note that in the figure the Type 649 Control is shown in two separate blocks:
Teletype Receiver and Teletype Transmitter.) Information is manually injected by means of
the Teletype keyboard and is carried in serial form to the Teletype receiver where it is assembled
into parallel form. The receiver is also known as an incoming I ine unit (LUI). From the rece iver, the parallel information is passed to the CP via the information collector. information
from the CP is transferred in parallel form to the Teletype transmitter, where it is shifted into
the printer in serial form. The transmitter is also known as an outgoing I ine unit (LUO).

Block Diagram Discussion

Teletype Keyboard
Information is typed out on the keyboard in the some manner as on on ordinary typewriter. As
each key is pressed, a code combination is set up to correspond with the selected character.
This is converted to serial form by a distributor arrangement which relates a given bit position
to a given time interval in the distributor cycle.

Teletype Printer
Serial information entering the printer is automatically typed on a page-width roll. The Teletype printer uses the same information code as the Teletype keyboard.

Teletype Receiver (LLJI)
The serial information generated by the keyboard must be converted into parallel form before it
can be accepted by the CP. This is aecompl ished by the Teletype .receiver •. Each successive

5-3

bit of information compris'ing ecch character is fed to the input of the flip-flop register in the
receiver. Initially, the bit is deposited in the least significant fl ip-flop. When the next bit
appears, 0 shift pulse occurs and each previousl y deposited bit is transferred to the flip-flop
which is one order higher, wh ile the new bit is deposited in the least significant fl ip-flop.
This process continues until all the bits of the character being transferred have been deposited
in the receiver fl ip-flop register, at which time a flag is raised and can be sensed by the program. The contents of the receiver are transferred to the AC via the Ie.

Teletype Transmitter (LUO)
The parallel" information util ized by the computer must be converted to serial form before it
con be" handled by the Teltype printer. This is accomplished by the Teletype transmitter which
is fed an 8-bit character by the AC of the CP via the 1D of the interface. The eight bits are
first deposited in the fl ip-flop register of the transmitter. This register contains nine fI ip-flops,
the least significant eight being used for temporary storage of the character and the ninth being
the transfer fI ip-flop. A shift pulse transfers each successive bit of the character to the next
higher order fl ip-flop I a move at a time, putting each bit sequentially into the transfer fl ipflop. From the transfer fl ip-f1op the bits are appl ied to the Teletype printer, through an output
circuit.

Clock and Frequency Divider
()peration of the Teletype receiver (LUI) requires an input clock signal whose frequency is eight
times the baud frequency of the Teletype keyboard unit. This signal is used to control the
strobing of Teletype information into the receiver during the center of each baud (which is the
most rei iable time for sensing) and to control the shifting of information through the flip-flops
of the receiver. The Teletype transmitter (LUO) requires an input clock signal whose frequency
is twice the frequency of the transmitter. Clock pulses are produced by a 14.08-kc crystal
dock driving a 6-element hinary counter which serves os a frequency divider to provide the
required pulse frequencies.

5-4

Logical Functions

Keyboard and Printer
The Teletype Model 33 KSR (keyboord-send-receive) can be used to type in or print out information at a rate of up to 10 char/sec. Signals transferred between the 33 KSR and the keyboard
printer control logic are standard serial, ll-unit-code Teletype signals. The signals consist of
marks and spaces which correspond to idle and bias current in the Teletype and O's and l's in
the control and computer. The start mark and subsequent eight character bits are 1 unit of time
duration and are followed by a 2-unit stop mark.

Teletype Code
Each of the (64 type) characters and 32 control characters is represented by an 8-bit standard
ASCII code. The Teletype 8-level code is Iisted in the Appendix. The teleprinter input and
output functions are logically separate, and the programmer should think of the printer and
keyboard os individual devices.

Keyboard Control
The keyboard control contains an 8-bit buffer (LUI) which assembles and holds the code for the
lost character struck on the keyboard. The keyboard flag becomes a 1 to signify that a character has been assembled and is ready for transfer to the accumulator. This flag is connected to
the computer program interrupt and input/output skip facil ity and may be cleared by command.

Teleprinter Control
The teleprinter control contains an 8-bit buffer (LUO) which receives a character to be printed
from AC bits 10 through 17. The LUO receives the 8-bit code from the AC in parallel and
transmits it to the teleprinter serial Iy. When the last bit has been transmitted, the teleprinter
flog is set to 1. This flag is connected to the computer program interrupt and input/output
skip facil ity. It is cleared by programmed command.

5-5

Teletype Instructions
The following instructions are used for the Teletype:

KSF

700301

Skip if the keyboard flog is set to 1 •
If the fl ag is 0, the next instruction
is executed. If:t is 1, the' next
instruction is skipped. The flag is
set only when a character has been
completely assembled by the buffer.

KRB

700312

Read the keyboard buffer. The contents of the buffer are placed in bits
10-17 of 'the AC and the keyboard
flag is cleared.

TSF

700401

Skip if the teleprinter flag is set.

TLS

700406

Load printer buffer and select. The
contents of AC 10- 17 are p I aced in
the buffer and printed. The flog is
cleared before transmission takes
ploce and is set when the character
has been prir.ted.
Circuit Operations

]reletype Keyboard and Printer
Complete technical information on these units may be found in the applicable instruction
manuals suppl ied with the computer. (Refer to the Iist of pertinent documents in Chapter 1 of
this manual.)

~Keyboard/Pri nter Contro I

The keyboard printer contro.l provides the required conversion between the parallel information
used by the CP and the serial information used by the Teletype unit. It also provides the program flogs which cause a program interrupt or an instruction skip based on the availabil ity of
the Teletype unit. It thus controls the rate of information flow between the processor and the
Teletype as a function of the program. The control is shown on engineering drawing BS-D-649-0~
It consists of a Type 4706 Eight-Bit Teletype Receiver (LUI) at location R2B2, a Type 4707

5-6

Eight-Bit Teletype Transmitter (LUO) at location R2B 1, a Type 4225 Clock at location R2B4,
a Type 4225 Eight-Bit Binary Counter at location R2B3, and the KSR 33 Driver attached to the
bock panel wiring of the keyboard/printer control logic panel.

Receiver (LUI) - The receiver accepts serial information from the Teletype keyboard and converts it to parallel form by means of an 8-bit flip-flop register. Each typed character consists
of eight bits plus l-unit start space and a 2-unit stop mark. As each character is typed on the
keyboard l the serial pulses making it up are fed to the KSR 33 driver and to the input of the
flip-flop register (input of the least significant flip-flop). Shift pulses (of the same frequency
as the bit frequency of the transmitted character) move each of the stored bits to the next
higher order fl ip-flop each time another bit (pulse) appears. When the register is filled, the
character is complete and an LUI FLG signal is produced by the keyboard flag fl ip-flop. When
the character is transferred to the AC, the lOT 0302 pulse clears the flag.

NOTE: An indicator lamp and a cut-out toggle switch are provided
on the handle end of the 4706 module to provide maintenance personnel with a visual indication of the flog signal and a means of
disabl ing the signal to prevent the reading of new characters by the
program.

An LUI ACTIVE signal, generated by the active fl ip-flop I is used to disable the transmitter (LUO)
when the receiver is in use so that the LUO cannot be operated until 1.5 Teletype units of time
have elapsed after the last LUI operation has been sensed by the AC.

Transmitf'er (LUO) - The transmitter accepts parallel information from the CP (through the I D)
and converts it to serial form by means of a 9-bit fl ip-flop register. The eight bits of each
transferred character are first loaded simultaneously in the eight least significant flip-flops.
A series of shift pulses, at a frequency of 220 cps, successively shift each bit in turn into the
ninth (mc)st significant) flip-flop. This is the transfer flip-flop. From the transfer flip-flop,
the bits ore passed to the line driver, the KSR driver, and to the Teletype printer. When the
transfer of all bits of the character has been completed, a LUO FLG sign 1 is put out by the
teleprinte~ flag fl ip-flop.

When the next character is ready to be loaded into the register from

the CP, the lOT 0402 pulse clears the flag and an lOT 0404 pulse reloads the register.

5-7

NOTE: An indicator lamp and a cut-out toggle switch are provided
on the handle end of the 4707 module to provide maintenance per-:sonnel with a visual indication of the flag signal and a means of
disabl ing the signal to prevent the writing of new characters by the
program.

A lUO ACTIVE signal, generated by the control, is used to disable the receiver (lUI) when
the transmitter is in use. The flip-flop register is provided with a power clear signal to reset
all fl ip-flops when the cc)mputer is initially turned on.

Clock and Frequency Divider - A 14.08-kc crystal ~Iock producing 400-nsec positive pulses
provides the master timing source for the Teletype system. Although the actual frequencies
required by the keyboard and printer are respectively 880 and .220 cps, the higher frequency
of 14.08 kc is used to insure operational stobil ity. The necessary frequency reduction is

accomplished with a binary counter, consisting of six flip-flops connected in a counting chain.
Each fl ip-flop changes state whenever the next lower ft ip-f1op changes from 1 to o. Thus, the
pulse frequency of a given fl ip-flop output is half that of its input. Since the LUI clock input
is tapped off at the fourth flip-flop, the 14. 08-kc clock frequency will have been divided by
4
2 , or 16, giving the required frequency of 880 cps. Similarly, the LUO clock signal is topped

6
off at the sixth fl ip-flop, and the original clock frequency will be divided by 2 , ~r 64, giving
the required frequency of 220 cps.

PERFORATED TAPE READER AND CONTROL TYPE 444B
A Digitronics Model 2500 Perforated Tope Reader and a DEC Type 444B Reader Control are
standard equipment suppl ied with every PDP-7 system. The tope reeder is a timed-transfer
device which senses the holes punched in 5, 7, or 8-channel paper or Mylar-base tope at a
maximum rate of 300 lines/sec. When used in the PDP-7 system, the standard input medium is
B-channeltape. The reader control contains on l8-bit output register which is loaded by the
reader, together with all the logic elements necessary for starting and stopping the reader under
program control, and sensing the state of the output register.
The reader is normally mounted in the center of boy 2, immediately above the operator console.
The reader control occupies one half of a mounting panel near the bottom of bay 3 (the other
half of the panel is occupied by the punch control).

5-8

The mechanical and electrical operation of the reader is fully described in the manufacturer's
manual which is supplied with the PDP-7 system and is identified in the list of Pertinent Documents
in Chapter 1 of this manual. Therefore, the following paragraphs describe only the logical
functions of the reader and control, and the operation of the Type 444B Reader Control.

Logical Functions
Operation of the reader is controlled entirely by the program. When the reader is selected by
the appropriate lOT instruction, the broke is released and the clutch engages the capstan to
move the tape past the photocells. The feedhole is sensed first, and generates a level transition
which causes sensing of the information channels. The sensing of information channels is delayed until the holes have advanced far enough to ensure that punched holes transmit the maximum possible amount of I ight to the photocells and that tape skew due to worn guides will not
couse loss of information. For each hole punched in a given Iine of tape, a corresponding bit
of the RB {reader buffer} is set to 1. Information can be read from the tape and assembled in
the reader buffer in either of two modes: alphanumeric, or binary.

Alphanumeric Mode
The alphanumeric mode, used for reading eight channels of informotion, is selected by on
RSA instruction of the lOT class. Each select instruction causes one line of tape to be read
and the information to be placed in bits 10-17 of the RB. See Figure 5-3.

Binary Mode
The binary mode, used for reading 18-bit binary words, is selected by an RSB instruction of the
lOT class. One binary word occupies three I ines of tape. Each select instruction causes three
successive I ines of tape to be read, each Iine containing six bits of binary information. The
first line, containingthemost significant bits, is read into bits 12 through 17 of the RB.
The RB performs as a 3-stage, 6-bit sh ift register.

When the first I!ne of tape has been read,

a shift pulse causes t~e contents of RB12-17 1'0 be shifted bodily into RB6-11, and at the same
time reads the second line of tope into RB 12-17. A second shift pulse shifts the contents of
the first line of t~pe into bits RBO-5, the contents of the second line of tope into RB6-11, and

5-9

CHANNEL

CHANNEL
6

CHANNEL
4

CHANNEL

8
~

,--"--..

11 112 113 I 141151161 17
110 I'--v--'
'--..--'
'---r-'
'-----'

UNUSED

CHANNEL

TAPE CHANNEL
8

FEED

00000 0 000
00000 0 000
00000 0 000

DIRECTION OF
TAPE MOVEMENT

~
MOST
SIGNIFICANT
OCTAL BIT

LEAST
SIGNIFICANT
OCTAL 81T

SECOND
SIGNIFICANT
OCTAL BIT

Alphanumeric Mode

SECOND LINE REAO

FIRST LINE READ

THIRD LINE READ

t
CHANNEL
6
~

CHANNEL

,--A--.

2
,.--A--,

I I 12 I
0

3 14

'--y-I

'--y-'

CHANNEL
5

CHANNEL

"
CHANNEL
6

CHANNEL

,.--A---..

r---'--t

"-r-'

I-..y--I

'--v---'

CHANNEL

CHANNEL
6
~

CHANNEL
4

CHANNEL

,--A-.

112 1 13 1 14115 116 17 1

'---v---I

"--.r--'

'--.,--'

'--y--J

CHANNEL

TAPE CHANNEL

DIRECTION OF
TAPE MOVEMENT

-4

FEED

00000 0 000
00000 0 000
00000 0 000

} FIRST LINE REAO }

} SECOND LINE READ
}

BY ONE

INSTRUCTION

THIRD LINE READ

FIRST LINE READ
} BY NEXT INSTRUCTION

Binary Mode
Figure 5-3

Tope Format and Reader Buffer Register Bit Assignments

5-10

reads the third line of tope into RB12-17. The complete binary character is now assembled in
bits RBO- I7 and the reader flag is set, indicating that the reader buffer is full. When reading
in binary mode, hole 7 is never punched; hole a is ignored, but a character is not read unless
this hole is punched. The tape format for binary mode is shown in Figure 5-3.
When a program is being stored by use of the READ-IN key, the processor forces the reader
into the binary mode and executes a pseudo-DAC instruction each time the reader Hog is set.
If a hole 7 is punched, the processor interprets this as an instruction to stop the reader and to
execute the last la-bit word read.

Perforated Tape Reader Instructions
RSA

700104

Select reader in alphanumeric mode.
One a-bit character is read and placed
in the reader buffer. The reader flag is
cleared before the character is read.
When transmission is complete, the flag
is set.

RSB

700144

Select reod~( in binary mode. Three
6-bit characters are read and assembled
in the reader buffer. The flag is immediately cleared and later set when character assembly is completed.

RSF

700101

Sk.ip if reader flag is set.

RCF

700102

Clear reader flag; then inclusively OR
reader buffer into AC.

RRB

700112

Clear reader flag. Clear AC and then
transfer contents of reader buffer to AC"

Circuit Operations
The logic of the Type 444B Reeder Control is shown on engineering drawing BD-0-444B-0-2.
The reader control contains two maior groups of logic elements: the reader buffer (RB) and the'
control logic.

5-11

Rleader Buffer (RB)
The reader buffer provides temporary storage for alphanumeric or binary characters read by the
tope reader. The RB contains two Type R203 FLIP-CHIP Triple Flip-Flops, each flip-flop having
a direct clear and a DCD set input. These modules are used in bits RBO through RBS. For bits
RB6 through RB1?, Type R202 FLIP-CHIP Double Flip-Flops are used, each flip-flop having a
direct clear input and DC 0 set and clear inputs. When reading in alphanumeric mode, bits
RB10 through RB1? are used. Tape characters are read directly into these flip-flops, and the
r,emaining bits are not used. When reading in binary mode, the input gating causes the register
to function as a 3-stage, 6-bit shift register. A simplified diagram of this configuration is shown
in Figure 5-4. After the first I ine of tape has been read into bits RB 12 through RB 17, an
RD SHIFT 1 is applied to all the DCD input gates of bits RB6 through RB17. Bit RB12 then
determines the condition of bit RB6, and RB1? that of RB11, with a corresponding transfer in
intermediate bits. Simultaneously, the second line of tape is read into RB12 through RB1?
When the third line of tope is ready for reading, RD SHIFT 1 and RD SHIFT 2 pulses are generated simultaneously and applied to the DCD input gates. The RD SHIFT 2 pulse shifts the
contents of bits RE6 through RB11 into bits RBO through P.BS. The RD SHIFT 1 pulse operates
in the same manner as before.
The (1) output of each RB fl ip-flop (ground level) is inverted and appears on terminals of the
W020 connector in location Bland of the W021 connectors in locations B2 and B3. Three
Type R107 Inverters, each containing seven inverters, are used for this purpose. The connector
at location B1 routes the levels to indicators; the connectors at B2 and B3 provide connections
"to the IC.

,Control Logic
The control logic circuits generate all the levels and pulses required for starting and stopping
the reader and for producing shifts when reading in binary mode.
At power turnon, PWR CLR negative pulses from the CP are applied to inverter JK in module B9
(01, 444B-0-2) and c1ear the RD MODE, RD RUN, and RD FLAG flip-flops. This some clearing
action is also initiated by a BGN pulse at time SPl of a manual operation, or by an lOT 0102
pulse from the device selector. This cleori,ng action establ ishes initial conditions.

5-12

The reader is started by an I,OT 0104 command pulse applied to inverter HF in module 89
(C2, 444S-0-2)"

This pulse appears ~henever the reader is selected, and triggers a pulse

ompl ifier wh ich produces a 5T ART pulse at terminal A4K. The START pulse performs three
functions:
1. It clears all the reader buffer fl ip-flops, together with the RD FLAG,
IRD 1 and RD2 fl ip-flops.
2. It sets the RD RUN fl ip-flop to 1, thereby starting the tape reader.
3. If bit 12 of the MB contains a 1, the START pulse triggers a DC D gate
that sets the RD MODE flip-flop to 1 • -When this flip-flop is in the 0 state,
a ground BINARY level is produced at inverter output terminal Bal
(C3, 444B-0-2) to select the alphanumeric mode. When the RD MODE
flip-flop is set to 1, a negative BINARY level appears at terminal Bal
to select the binary mode.

Note that the RD MODE fl ip-flop may also be

set to 1 when on RPT (l)B level is established by a manual readin operation.
ACO

AC!l

AC6

ACii

ACl2

1C17

t---+----+------+-+-__
FlO SHIFT 2 - - - - - - 0 [ ) ( 2 0 o - - - - -

~--~Q-~~~----------

RD SHIFT 1 o--........-~D<Jo--DD<1--- -

--+--~~~~

---oD<J---C>D<J

READ IN O--............ :lII-l...•.J
LEVEL
HOLE'

REAO IN O---.----L~U

LEVEL
HOLE 6

Figure 5-4 Reader Buffer In Binary Mode

5-13

f'Jegative levels produced by 13 5 in the first six bits ~f the tape are inverted and condition the
set DCD gates of flip-flops RB12 through RB17. Ground levels produced by 0·5 are directly oppi ied to the :eset DC 0 gates. The levels produced by holes 7 and 8 condition an additional
set of NAND gates which do not open unless strobed by an ALPHA-N pulse. The leyel transition produced by the feed hole causes Schmitt trigger FLR in module A3 to change state. If the
RD RUN fl ip-flop is set to 1, the output of the Schmitt trigger sets the delay one-shot in
module 84. 'The purpose of this one-shot is to delay the instant at which the reader buffer
samples the output of the photocells until the center I ine of the tape holes coincides with the'
center of the feed hole. There are two reasons for th is. Using a correctl y 01 igned tope, sampling at the leading edge of the feed hole would take place before the other holes were centraliized over the photocells, so that the output of the photocells would not yet have reached its
maximum value. More important, if worn tape guides have caused skew in the tope, sampling
elt the leading edge of the feed hole might cause loss of information from holes 7 and 8, as
shown in Figure 5-5. Delaying the sampling instant ensures that under tolerable conditions of
skew all photocells produce some output, so that no information is lost.
Vvhen reading alphanumeric mode, the RD STRB output pulse from the one-shot triggers a DC D
gate conditioned by a ground BINARY level, and the output of the gate causes on RD SHIFT 3
!signal to appear at pulse ampl ifier output terminal A4U. This pulse, i~verted, becomes the
ALPHA-N negative pulse which strobes the hole 7 and hole 8 NAND gates. At the same time,
the RD STRB pulse triggers two other DCD gates conditioned by a BINARY level. One of these
gates causes generation of an RD SHIFT 1 pulse at pulse ampl ifier output terminnl B5K; the
other causes generation of a RD SHIFT 2 pulse at terminal B5U. These RD SHIFT pulses strobe
all the DeD input gates of the RB flip-flops and read a line of tope into bits RB10 through RB17.
The ALPHA-N pulse, inverted, sets the RD FLAG fl ip-flop.
When reading in binary mode, the DeD gate A4P, R is disabled by the negative BINARY level,
and therefore the ALPHA-N pulse is not generated. Since the NAND gates for holes 7 and 8
ar~ not strobed, these holes ore not read.

However, hole 8 is always punched, and the nega-

tive level, inverted, permits generation of the RD SHIFT signals by conditioning DCD gates
A5E, F and ASS, T.

5-14

FEED
HOLE

-A--A--A- -A--A---r\--A--A--Pr

-\..:;J--U--Q--G'--Q-- 'C;r--Q--Q--v- I
.

A. CORRECTLY ALIGNED TAPE

DIRECTION
OF TAPE

.--J

SAMPLING AT FEED HOLE
CENTER: MAXIMUM OUTPUT
SAMPLING AT LEADING
EDGE: REDUCED OUTPUT

.T-S.~~~~=CX
~~-=--C-::'I::~Q=_=-0~--[;l~
~Q_~~
_
_U
u _~.-~_U
- _V-- - SKEW ANGLE..J

B. SKEWED TAPE
.

SAMPLING AT FEED HOLE
CENTER: ALL HOLES GIVE
SOME OUTPUT
SAMPLING AT FEED HOLE
LEADING EDGE: HOLE LOST

Figure 5-5

Effect of Delayed Sompl ing

The RD SH 1FT 2 pulse that accompanies the reading of the first Iine of tape sets the RD 1 fl ipflop. The output of this fl ip-flop conditions the DC 0 set gate of the RD 2 fl ip-flop I and when
the RD SHIFT 2 pulse of the second line of tape appears, the flip-flop is set. The RD 2(1)
output conditions the DCD set gate of the RD FLAG flip-flop, and when the third line of tape
is read, the accompanying RD SH 1FT 2 pulse sets the RD FLAG fI ip-flop.
The setting of the RD FLAG fl ip-flop indicates to the CP that the reader buffer is full. The
positive-going level transition produced by the RD FLAG fl ip-flop clears both the RD MODE
and the RD RU N fl ip-flops. ~Iearing the RD MODE fl ip-flop reestablishes the alphanumeric
mode; clearing the RD RUN fl ip-flop stops the reader.

TAPE PUNCH AND PUNCH CONTROL TYPE 75D

The Teletype Tape Punch Set (BRPE) and the DEC Type 75D Punch Control are supplied with
each PDP--7 as standard equipment. The tape punch is a timed-transfer device capable of

5-15

punching 5-, 7-, or a-channel tape at a maximum rate of 63.3 char/sec. In the PDP-7 system
the standard output medium is a-channel tape. The punch control contains an a-bit data
register, whi -:h is loaded from the AC through the information distributor. It also contains all
the logic elements necessary for starting and stopping the tape punch and supplying it with the
appl icable data

The tape punch is mounted in the center bay, above the tope reader. The punch control is
located near the bottom of boy 3.
The mechanical and electrical operation of the tape punch is fully described in the manufacturer1s manual suppl ied with the PDP-7 (refer to the I ist of Pertinent Documents," in Chapter 1
c)f this manual). Consequently, the following paragraphs describe only the logical functions
c)f the tape punch, and the operation of the punch control.

Logical Functions
()peration of the tape punch is normally controlled entirely by the program. However, the
()perator may bunch :aoder tape (feed hole on! y punched) by pressing the PUNCH FEE D button
on the console or he may force on the punch power by setting the console PUNCH switch.
'Nhen the tape punch is selected by the Hrst punch lOT instruction, the" punch is turned on and
clfter a l-sec delay (during which the punch motor comes up to speed), punching begins. Subsequent punch instructions are executed immediately. The punch control functions os a buffer,
c]

control unit, and a solenoid and motor driver for the tape punch. When a tape punch opera-

tion is selected by on lOT instruction, a pulse estobl ishes the operating mode of the control
(alphanumeric or binary) and causes certain of the lis stored in AC to be transferred to the
buffer register of the punch control via the information distributor. If the mode is alphanumeric I
the lis are transferred from AC bits 10-17. If the mode is binary, the lis are transferred from
AC bits 12-17. The fl ip-flops containing lis then enable a series of gates which trigger solenoid drivers and upon receipt of the punch command, a hole is punched in the tape in each
channel where a corresponding 1 was present in the AC. When a I ine of tape has been punched,
the buffer register and PUN ACTIVE fl ip-flops are cleared, and the PUN FLAG is set to indicate
to the CP that the punch is ready for a further punching instruction. After the last punch como

mand, the motor remains energized for an additional 5 sec.

5-16

Alphanumeric Mode
The alphanumeric mode is used for punching 8-channel tape, and is selected by a. PSA instruction of the lOT class. Each select instruction causes one line of tope, consisting of eight bits,
to be punched. A hole is punched in each tape channel whose corresponding bit in the AC is

a 1. A feed hole is always punched.

Binary Mo~
The binary mode is used for punching l8-bit words and is selected by a PSB instruction of the
lOT class" Moles are punched corresponding to bits l2-17 of the PB. Bit 11 (hole 7) is never
punched and bit 10 (hal e 8) is always punched. This establishes the standard format for binary
information on tape. Since only six dota bits are punched at a time, a complete 18-bit word
requires three lines on the tape and consequently involves three separate PSB instructions.

Tape Punch Instructions

PSA

700204

Punch a line of tape in alphanumeric
mode. The punch flag is immediately
cleared and then set when punching is
complete.

PSB

700244

Punch a Iine of tape in binary mode.
The punch flag is immediately cleared
and then set when punching is complete.

PSF

700201

Skip if the following instruction if the
punch fl ag is set.

PCF

700202

Clear the punch flag.

The fotlo~ing instruction will clear the accumulator and cause a I ine of tope to have only the
feed hole punched:

PSA +10

700214

Clear AC and punch.

The following instruction as used 0}1 the PDP-4 is also available, but is generally replaced with
the more direct PSA.
PLS

700206

Same as PSA.

5-·17

Circuit Operations
Punch Control Type 750 may be divided into the following maior functional circuit groups:
control logic, punch buffer and solenoid drivers, and motor logic. These elements are all
shown on engineering drawing 85-0-750-0-2.

Control Logic
The operation of the punch is entirely under program control, and the control logic contains
(JII

the circuits which interpret a punch instruction and indicate to the CP when a punching

operation is complete. PWR CLR pulses generated in the CP at turnon are oppl ied to
terminal D of the connector in module B30. These pulses, inverted, trigger a pulse ampl ifier
in module B22, which clears the punch buffer. The buffer clearing pulses appear at terminal B22K. The buffer is also cleared if an lOT 0202 command pulse and on MB15 (0) level
couse a pulse to appear at terminal B22U. ·In both cases the PUN MODE fl ip-flop is also
cleared.

The elements which respond to program control are the PUN MODE fl ip-flop, which determines
whether alphanumeric or binary characters will be punched on the tape; the PUN ACTIVE fl ipflop, which starts and stops the motor; and the PUN FLAG, which is set to 0 at the beginning
of a punching operation and is set to 1 when the punch ing of a character is complete.
The PUN MODE fl ip-flop is cleared by on lOT 0202 command pulse. The fl ip-flop is set by
an lOT 0204 pulse, produced by an instruction to punch, if bit 12 of the instruction contains

a 1, specifying binary mode.. When set, the PUN MODE fl ip-flop forces a 0 into bit 11 of
the punch buffer (hole 7) and a 1 into bit 10 (hole 8). When the PUN MODE flip-flop is in
the 0 state (for alphanumeric mode) bits 10 and 11 of the punch buffer are set by the corresponding bits of the AC •
The PUN FLAG and PUN ACTIVE flip-flops are cleared by on lOT 0204 pulse, produced by
an instruction to punch

When a charac;ter has been punched, a PilN DO·NE level is produced

which clears both these flip-flops and the buffer register. The PUN FLAG (1) level appears

5-18

at terminal T of the W021 connector in location 830, dnd is routed to the break control in
the CP. The PUN ACTIVE (1) level is utilized in the motor logic.

Punch Buffer, Solenoid Drivers, and Synchronization
The punch buffer (PB) is an a-bit register which provides temproary storage for information
supplied by the AC. The PB (1) levels condition the solenoid driver input gates. Flip-flops
PB10 through PB 17 are cleared by PWR CLR pulses at power turnon, by an lOT 0202 command
pulse, and by the PUN DONE signal produced ofter the punching of each character

The

DCD set gate of each fl ip-flop is conditioned by the $tate of the corresponding bit of the AC
and is !riggered by an lOT 0204 pulse. Thus, binary l·s are transferred from the AC into the
PB. The solenoid drivers are controlled by 2-input NAND gates.
One input of each gate is conditioned by the corresponding PB (1) level; the other input is
enabled by a 5-msec signal generated in the synchronization circuits.· During this 5-msec
period each gate that is fully enabled causes the associated solenoid driver to energize the
solenoid, and a hole is punched· in the corresponding tape position. The solenoid driver for
the feed hole punch receives only the synchronizing signal and produces a feed hole for every
operation.
The synchronizing signal is generated by a magnetic pickup on the punch drive shaft and appears
when the punch cams are at or near top dead center. The timing of the signal is adjustable.
The synchronizing signal triggers the Schmitt trigger in module A 19, and the level transition
which appears at terminal A 19F triggers the 5~'msec one-shot in module A20, provided that
the DCD input gate is conditioned by a PUN READY level. In its quiescent state, this one-shot
produces a ground PUN DONE level at terminal A20V which is appl ied through the bus drivers
in module A21 to the solenoid driver input gates. When the synchronizing signal arrives, the
level at terminal A20V changes to - 3v and causes the bus drivers to enable the solenoid driver
input gates for 5 msec, after which punching of a character is complete and the PUN DONE
level reappears. The resul ting positive-go ing level transition clears the punch buffer and the
PUN ACTIVE flip-flop, and sets the PUN FLA.G.

5··19

~otor logic

The punch is turned on and off under program control, but the motor requires 1 sec to attain
full speed. To el iminate del ay in the execution of successive punch instructions, it is desirable
to keep the motor running for 5 sec after a I ine of tape has been punched, so that a further
punch instruction can be executed immediately. The motor logic provides the required control
signals for th is purpose.
rhe Type R302 delay one-shot at location B28 delays the execution of the first punch instruction
for 1 sec to allow the motor to come up to speed, and the Type 4303 Integrating One-Shot at
location R2B4 keeps the motor running for 5 sec after execution of the last punch instruction.
These functions are accompl ished as follows:

1. If the PUN ACTIVE flip-flop is set by a punch lOT instruction, or if the
console TAPE FEED pushbutton is pressed, a PUN RQ level is produced at
terminal B27H and sets the integrating one-shot to its unstable state. The
negative level produced at the (1) terminal of the integrating one-shot is
inverted and causes a relay driver to energize relay Kl, thereby starting the
motor.

2. Punching cannot begin until a ground PUN READY level appears at
NAND gate output terminal B27N and conditions the OeD input gate of
the 5-msec one-shot of the synchronizing one-shot (refer to, the explanation
of the synchronizing logic). The PUN READY level appears only when
all three inputs of NAND gate KLMN of module B27 are conditioned by the
negative levels. One of these inputs is conditioned by the PUN RQ level.

A second input is conditioned by the negative (1) level of the integrating
one-shot. The th ird input is conditioned by the inverted (0) level of the
l-sec delay one-shot at location B28. When the integrating one-shot is
set and starts the motor, the pos itive-going level transition appearing at the

(0) terminal triggers the 1-sec delay one-shot into its unstable state. The
output of the delay one-shot/ inverted/ disables the NAND gate in module
B27 to prevent a PUN READY level from being generated while the motor is
gotheri n9 speed.

5-20

3. After 1 sec, when the motor has attoined full speed, the delay one-shot
reverts to its stable state. The ground level which appears at the output terminal B28M is inverted and causes a negative level to be applied to terminal B27N. All three inputs of the NAND gate are now conditioned, and a
ground PUN READY level appears at the output of the gate.
4. After a character has been punched, the PUN DONE level transition
clears the PUN ACTIVE flip-flop, thereby producing a ground PUN RQ
level that disables NAND gate KLMN of module B27 and removes the
level that held the integrating one-shot in its unstable state. The
PUN READY level disappears immediately, preventing further punching.
However I the integrating one-shot does not yet change state, and therefore
the motor continues to run. At the end of its 5-sec timing period, the
integrating one-shot reverts to its stable state, thereby causing relay K1
to be de-energized and the motor to be stopped. Note that the 5-sec
timing period of the integrating one-shot does not begin until clearance
of the PUN ACTIVE flip-flop removes the PUN RQ signal th':lt holds I"he
integrating one-shot in the unstable state .If a further PUN RQ signal
is generated before the end of the timing period, timing action is immediately halted. Thus, the integrating one-shot does not revert to its
stable state and stop the motor until a full 5-sec period has elapsed since
the last punch instruction was completed.

5-21

CHAPTER 6
OPTIONAL EQUIPMENT

AUTOMATIC PRIORITY INTERRUPT TYPE 172
The op~iclnaJ Automatic Priority Interrupt (API) Type 172 connects up to 16 I/O devices to the
program interrupt fac it ity of the PDP-7 pr~essor and allows each dev ice to initiate a program
interrupt based on a prewired priority. The"'Afl provides direct identification of an interrupting
device so that the interrupt subroutine is not re~:lut~ed to determine this by scanning device flags.
The API also executes multilevel interrupts in whicRa high-priority device may be granted an
interrupt that supersedes an interrupt already in progress. These functions permit more devices
to be serviced with greater speed and efficiency.
The API occupies three mounting panels, whose location depends to some extent upon what
other options are .included in the PDP-7 system. The location of each module within the panels
is shown in the API module map, engineering drawing ML-D-172-0-5.

Block Diagrclm Discussion
The API consists of a control element, a priority chain, and an address selector. The real time
clock of the processor is assigned to channel 178 of the API. The relationship of these elements
to each other and to the processor is shown in Figure 6-1.
When the API option is included in a PDP-7 system, it is connected in place of the real-time
clock of the basic system and has a corresponding priority (lower than data break interrupt requests, but higher than program interrupt requests).

An interrupt request from a device con-

nected to the API is granted if the following conditions are met:
a. The API is in the enabled condition (by program control).
b. The requesting channel is in the enabled condition (by program control).
c. There is ho data interrupt request present or data interrupt in progress.
d .. There is no interrupt in progress on a higher priority channel.
e. There is no interrupt in progress ()n the requesting channel.

6-1

I .

s'me

MS6(0 - Me ttl I~

I
J
1

CAC + PWR CLR_ A

top t, 2. 4
PWR CLR

PIt -.MA
PROCESSOR
AND
INTERFACE

--.....

INT RQ

MAt4IA
THROUGH
MAITIA

J 1 -"

1 --.
I
I
I
I
I

6.3V. so'\,.

PSE (I)

CONTROL

Pl8t-..MA

-......

PRIORITY
CHAIN

ADDRESS
SELECTOR

L ____

r-.

-...
CLR·
ClK
FlG

eLK
FlG

I
I

OBK

(t6l

......

tlHAN RQ U61

REAL-TIME
CLOCK
(CH 17)

Ft,.AGS
CLEAP
FLAGSJoo.,

I
I
I
I
I
I

(/0
DEVICES

- - --- - - -- - - J
DATA OUT

-""""

OATA IN

lOT PULSES

Figure 6-1

Automatic Priority Interrupt Type 172 Block Diagram

Each channel in the API system is assigned a unique, fixed core memory location (408 through

57 ), When a~ interrupt is granted, fhe next instruction is taken from the memory location
8
(Issigned to the requesting channel.

Control
The control element contains all the logic required for enabling or disabling the entire priority
system or selected channels, in response to lOT instructions. The control element also generates
the interrupt request (lNT RQ) level signal, which causes the processor to grant an API interrupt
(equivalent to a clock break in the basic system) at the first available opportunity.

yri ori ty Cha i n
The priority chain contains a set of three fl ip-flops for each channel, designated bXX1, bXX2,
<lnd bXX3, where XX represents the channel number.· Each bXXl flip-flop, when set, enables
the associated API channel.- Setting and clearing of these flip-fiops is accomplished by lOT
instructions in conjunction with the content of bits 2 through 17 of the-accumulctor. At time
T3, a SYNC pulse opens gates which are cond:tioned by a bXX1 (1) level and a CH FLG
(channel flag) level. The output pulses from gates associated with enabled requesting channe!s
set the assoc iated bXX2 fl ip-flops. The bX~2 (1) output from the highest priority fl ip-flop generates a CHAN RQ (channel request) level for the associated channel, and disables gates which

6-2

prevent a CHAN RQ level from being generated by channels of lower priority. Only ,one
channel at a time can generate a CHAN RQ level. The channel request level generated by
the requesting channel which carries the highest priority is applied to the address selector element, which generates the memory address assigned to that channel and an INT RQ {interrupt
request} level. When the processor grants an API break,itgenerates a Pil - MA pulse. The
Pil - MA pulse sets the address generated by the address selector into the MA of the processor,
and transmits it to the API where it sets the bXX3 {hold break} flip-flop of the requesting channel. The level transition that occurs when the bXX3 flip-flop is set to 1 cl ears the device flog.
This flip-flop remains set until a OBK {debreak} pulse is generated by the control element. It
is also cleared by a CAC (clear all channels) instruction.

Address Selector
The address selector consists of four NOR gates which set l's or O's into bits 14 through 17 of
the MA to produce the memory address of the channel in which a CHAN RQ level is generated.
The channel address is transferred into the MA at time T1 of the API break cycle. Circuits are
also contained in the API address selector that assure that MA 121A is always a 1 and MA 131A
is always a 0 when the API is granted an interrupt; hence the memory address range of 40 - 57 •
8
8

Real-Time Clock
The real-time clock consists of a Schmitt trigger, a pulse amplifier, and a clock flag flip-flop.
The Schmitt trigger input receives a 6.3 vac, 60 cps signal from a processor power supply, and
the trigger output is coupled to the pulse amplifier, which produces 100-nsec pulses at the rate
of 60 per second. Each clock pulse sets the clock flag flip-flop and, if its channel is enabled,
requests em API break. -One channel (CH 17 ) is assigned to the real-time clock and one is
8
assigned for overflow from the core memory location containing the clock count.

Logical Functions

Channel Allocation

The API provides 16 automatic interrupt channels arranged in a priority chain so that channel 00
has the highest priority and channel 178 has the lowest priority. Each channel is assigned a

6-3

unique, fixed memory locet·ion in ·the range 408 (CH OOa) through 57a (CH 17 ). Each I/O
8
device is assigned a unique channel in order of device operating speed. The higher-speed devices are assigned to the higher-priority channels. The priority chain guarantees that if two
Ol~ more devices request an interrupt concurrently, the first interrupt is granted to the device

with the highest priority. When this device has been serviced, further'interrupts are granted
to the other devices, in order of priority.

Multi-Instruction Subroutine Mode
This mode is generally used to service an I/O device that requires control information from the
PDP-7. Such devices are alarms, slow electomecha~ical devices, teleprinters, punches, etc.
Each device requires a servicing subroutine that includes instructions to manipulate data and
give further instructions, such as continue, halt, etc., to the interrupting device. When an
interrupt is granted, the contents of the channel memory location are transferred to the MB and
executed. If the instruction executed is JMS Y, the system operates in the multi-instruction
subroutine mode. The contents of the program counter and the condition of the link are stored
in location Y, and the device-servicing s~broutine sterts in Y + 1. (Note that it is often useful
to store the content of the AC before servicing the device and to restore the AC prior to exiting
from the servicing routine.)
The interrupt flag is normelly lowered by the 172, but can be lowered by an lOT instruction if
desired. Program contro~ now rests with the servicing routine.
A return to the main program is accompl ished by an instruction sequence that restores the AC
clOd link, issues a debreak lOT, and gives a jump indirect to location Y (where the contents
of the PC prior to interrupt are stored). The debreeking lOT requires no channel designator,
since the interrupt priority chein automatically releases the correct channel and returns it to
the receptive state. This lOT normally inhibits all other interrupts for one memory cycle to
4~nsure that the jump indirec·t Y is executed immediately.

·rhe following program example illustrates the action that takes place during the multi-instruction
subroutine mode. Assume an interrupt on channel 03.

6-4

Memory Location

Instruction

Operation

1000

ADD 2650

Instruction being executed when interrupt request
occurs.

004:3

JMS 3000

Instruction executed as a result of interrupt on
channel 03. The JMS determines multi-instruction
mode.
The link, condition of the extend mode, and the PC
are stored in location 3000.

3000

3001

First instruction of servic ing routines stores AC.

DAC 3050

Instructions servicing the interrupting in/out device.

3002
3003
3004
3005
3006
3007

LAC 3050

Restores AC for rna i n program.

3010

DBR

Debreaking lOT releases channel.

3011

JMP 13000

Return to ma i n program sequence.
Next instruction executed from here unless another
priority interrupt is waiting.

1001

Single-Instruction Subroutine Mode
In some instances, it is desirable for the PDP-·7 to receive information from an external device
but not to send control information to the device, such as in the counting of real-time clock
pulses to determine elapsed time. The single--instruction subroutine mode simplifies programming
a counter.
An interrupt request is subject to the same conditions as in the multJ-instruction mode, and the
appropriate memory location is addressed as described previously. Then the single-instruction
subroutine mode is entered if the channel memory location does not contain a JMS instruction.
Normally the instruct.ion is ISZ.

In any case, since the single instruction constitutes the entir~

subroutine, the interrupt system automatically lowers the interrupt flag, debreaks the interrupting channel, and ,returns the channel to the receptive condition.

6-5

If the ISZ instruction is used, the 172 acknowledges on1.y the incrementing operation and
neglects the skip to avoid changing the contents of the program counter. If an overflow results

frc)m the incrementing, a flag is set. This flag can be entered in another channel or the interrupt system to cause a further program interrupt.
The following program coding illustrates operation in the single instruction subroutine mode.
Assume an interrupt on channel 06.
Memory Location

Instruction

Operation

1200

DAC 1600

Operation being executed when interrupt occurs.

0046

ISZ 3200

Instruction executed as a result of break on channel 06. If overflow, flag is set, PC not changed.

1201

LAC 1620

Next instruction in sequence of main program.

Automatic Priority Interrupt Instructions
The following instructions are added to the PDP-7 with the installation of the Type 172 API
option. Some instructions, for example CAC and ASC, can be micro?rogrammed.
()ctal Code

Mnemonic

CAe

705501

Clear all channels. Turn off all channels.

ASC

705502

Enable selected channel (5). AC bits 2 through 17
are used to select the channel{s).

OSC

705604

Disable selected channel (s). AC bits 2 through 17
are used to select the channel (s).

EPI

700004

Enable automatic priority interrupt system. Same
as real-time clock CLON.

DPI

700044

Disable automatic priority interrupt system. Some
as real-time clock CLOF.

ISC

705504

Initiate break on selected channel (for maintenance
purposes). AC bits 2 through 17 are used to select
the channel.

DBR

705601

Debreak. Returns highest priority channel to receptive state. Used to exit from multi-instruction subr~utine mode.

Operation

6-6

AC bits 0 to 1 are available for expansion of the basic automatic priority interrupt system to

4 groups ()f 16 channels.
Circuit Operations

Control
The control circuits generate seven conditioning levels and ten command pulses for the operation
of the API system. The logic circuits which produce these signals are shown on engineering
drawing BS-0-172-0-2.
The PWR CLR + CAe positive pulse provides a means of collectively clearing all fl ip-flops contained in the API, either automatically at power turn-on or under program control. The PWR
CLR + CAC positive pu Ise appears at pulse ampl ifier output terminal E3K. This pulse ampl ifier
is triggered either by PWR CLR POS pulses applied to OeD gate E3E, "F, or by IOP1 pulses
generated in the processor and inverted by inverter LMN of module E7 (C1, 172-0-2). The
inverted pulse is applied to OeD input E3H; and, if the level input of this gate is conditioned
by an 10 55 level, the pulse amplifier is triggered end generates the PWR CLR + CAe pulse.
The 10 55 and 10 56 levels are the basic enabling and disabl ing levels for the entire API system. These levels are generated by decoding the content of bits 6 through 11 of the MB in
NAND gates at locations F3 and F4. The 10 55 assertion levels appear at terminalsF3E (negative) and F3D (ground). The 10 56 levels appear at terminals F4E (negative) and F40 (ground).
The PSE (1) (priority system enable) negative level conditions the NAND gates associated with
channel 00. The PSE (1) ground level conditions a OeD gate, which resets flip-flop b003 in
the priority chain when triggered by a COMMON DEBREAK pulse. The PSE (1) levels are
generated by the PS ENABLE flip-flop, which is set by an EPI (enable priority in"terrupt) instruction and reset by a DPt" (disabl e priority interrupt) instruction. These lOT instructions contain a 1 and a 0, respectively, in bit 12, wh ich condition NAN 0 gates J KL and DEF in module
A12. An lOT 0004 command pulse, generated in the device selector, triggers whic:hever gate
is conditioned and sets or resets the flip-flop. The PS ENABLE flip-flop must be set by an EPI
instruction before the API can initiate an interrupt from any channel.

6-7

The ASe 5502 command pulse appears at pulse ampl ifier: output terminal E3U. This pulse
amplifier is triggered by an IOP2 pulse generated in the CP and inverted by inverter PRS of
module E7. The inverted pulse is applied to OeD input E3P and triggers the pulse amplifier
when the gate is conditioned by an 10 55 ground level. The ASC 5502 pulse sets all bXX1
flip-flops of the priority chain whose DeD set gates are conditioned by a 1 in the corresponding bit of the AC.
The DSC 5604 command pulse appears at pulse ampl ifier output terminal E5K. This pulse
amplifier is triggered by an inverted IOP4 pulse applied to DCD input 5E, when the OeD
gate is conditioned by an 10 56 ground level. The pse 5604 pulse resets all bXXl flip-flops
of the priority chain whose OeD reset gates are conditioned by a 1. in the corresponding bit of
the AC.
The ISC 5504 command pulse appears at pulse amplifier output terminal E4K. This pulse amplifier is triggered by an inverted IOP4 pulse applied to OeD input terminal E4E, when the
gate is conditioned by an 10 55 ground level. The Ise 5504 pulse sets the bXX2 fl ip-flop of
any channei selected by the insertion of a 1 in the corresponding bit of the AC. The setting
of the bXX2 fl ip-flop initiates a break request by the selected channel (or by the highest priority channel if more than one has been selected). This command initiates a break'request on
the selected channel or on the highest priority channel selected, independent of the channel
enable/disable conditions. The channel MUST be disabled if there is no device connected to

it. If a device is connected to the channel, the channel can be enabl ed, but the program
must consider the status of the external device. The ISC instruction allows diagnostic routines
to initiate a break on any channel, independent of external operations.
The negative INSURE DEBREAK level is generated by the INSURE DEBREAK flip-flop and
appears at terminal A15J when the flip-flop is set to 1. This level is applied to terminal J30P
of the break control in the ~P (drawing B5-0-7-0-32) and forces a BK RQ condition for one
cycle at the end of an API break.

This ensures that an indirectly addressed JMP instruction

providing exit from a break routine will be executed immediately. The INSURE OEBREAK flipflop is set by any instruction -that generates a OBK (debreak) command and is reset to 0 by
timing pulse T3 of the following cycle.

6-8

The DEBR (debreak) command pulse appears at pulse amplifier output term inal E5 (C3, 172-0-2).
This pulse not only sets the INSURE DEBREAK flip-flop, but also triggers a pulse amplifier to
produce a COMMON DEBREAK command pulse in the priority chain. The DEBR command pulse
is generated by either of the following conditions:
a. An IOP1 pulse, inverted, is combined with an 10 56 ground level in
OCD gate PR of module E5 to trigger the pulse ampl ifier.
b. The INT RECOGN IZED fl ip-flop is set during time T1 of the API break
cycle by a PI1--MA pulse generated in the break control of the CP. The
INT RECOGNIZED (1) negative level conditions one input of the NAND
~Jate in modul e E8.

If two other inputs are conditioned by an F (fetch)

level and a JMS level, then at time T5 of the fetch cycle the gate is triggered and causes the pulse ampl ifier to generate the DBK pulse. If the
following cycle is also to be a fetch, the F SET level from the major state
generator is combined with tim ing pulse T7 of the current cycle to reset the
'NT RECOGNIZED flip-flop.
The OVERFLOW FLAG (1) level is generated during an API break in which the instruction in
I

the assigned memory location of the requesting channel is 15Z. If the indexing operation
causes an overflow, an MBO CRY (B) pulse triggers gate NPR of module A12 and sets the
OVERFLOW FLAG fI ip-flop. The (1) output is appl ied to another channel of the priority chain
and initiates a break request. The OVERFLOW FLAGfl ip-flop is cleared when the interrupt is
granted.
A SYNC command pulse appears at pulse amplifier output terminal E9N. This pulse amplifier
is triggered by NAND gate RNPV of module E8 which is operated at time T3 of each cycle in
which the INT REC level and the 10 DEVICE 56 are both present. The presence of these levels
assure that no SYNC pulse will be issued when the API tries to debreak (DEBR) and return to
the main program sequence. The 5Yt"-lC command pulse sets the bXX2 fl ip-f1op of all API
channels which have been enabled and are re1questing an interrupt with a CH FLAG level.
The PIBl - MA pulse appears at pulse amplifier output terminal E9H. This pulse amplifier is
triggered when a PI1 - MA pulse appears, indicating that an interrupt has be,en granted. The

6-9

PI1- MA pulse is generated in the processor break cont.rol circuits at time T1 of the break
cycle, and forces the maior state generator to the fetch state. This pulse appears at terminal
Il 25H and is identical to the CLOCK 7 - MA pulse of the basic POP-7 system (82, BS-0-7-0-32).
The PI 81 - MA pulse is applied to all channels of the priority chain, thereby setting flip-flop
bXX3 of the highest priority enabled. Setting of this fl ip-ffop turns on the channel and clears
the flag of the device to which an interrupt has been granted.

Address Selector
The address selector circuits generate negative levels which condition the input gates of bits
14 through 17 of the MA, thereby setting the memory address assigned to the requesting channel
into the MA. The address selector circuits also generate the INT RQ level which sets the API
SYNC (ClK SYNC in the basic system) fli'p-flop of the break control (engineering drawing
85-D-7-0-32). The CHAN RQ (channel request) levels of all channels in the priority chain
are appl ied to the four NOR gates in modules A16, A17, A18, and A19. Only the highest
priority requesting channel generates a CHAN RQ level, so that only one address at a time
con be set up. In addition to the four MA addressing levels generated by the NOR gates, an
MA l21A level is generated with each address by disconnecting the ground jumper on terminal P
of module C27 in the MA (B6, B5-D-7-0-29). This wiring modification, in coniun~tion with
the fact that MA131A is never set to 1 by the PIB - ~AA pulse (B6, B5-D-7-0-29) produces the
desired range of memory locations (40 - 57 ).
8
8
The tNT RQ (interrupt request) level appears at terminal A14M. Any address selected by a
selected channel causes one or more of the N OR gates to apply a ground output level to the
NOR gate in module A20. The INT RQ level is then generated from A20D, unless the PS
ENABLE fl ip-flop is in the 0 state. In that case, the negative P5E (O) level is inverted in
module A14 and grounds the INT RQ line.

~)riority Chain

Each channel of the priority chain consists of three flip-flops, four NAND gates, an inverter,
(]nd a pulse ampl ifier connected in a configuration that is identical in each channel. The logic
of the priority chain is shown on engineering drawing B5-D-172-0-3. Only channel 01 is described below ,since all other channels operate in an identical manner.

6-iO

Channel 01 is enabled when fl ip-flop bOll is set. The setting pulse is provided by a OCD gate
conditioned by a 1 in bit 3 of the AC and triggered by an ASC 5502 command pulse from the
control element. Similarly, the channel is disabled when fl ip-flop bOll is reset by the combination of a 1 in bit 3 of the AC and a DSC 5604 command pulse from the control element. When
channel 01 is enabled under program control, the bOll (l) le/el conditions one input of NAN D
gate KLMN in module E14 (C2, 172-0-3). Another input is conditioned by a CH 1 FLG (channell flag) level generated in the associated I/O device. At time T3 of the computer cyete,
the NA~D gate is triggered by a SYNC pulse from the control element; and the output of the
gate sets fI ip-flop b012. This fI ip-flop may also be set by the combination of a 1 in bit 3 of
the AC and anlSC 5504 command pulse from the control element. Use of the ISC instruction
causes a break to be initiated on the sel ected channel without a prior enabl ing instruction.
NAND gate KLMN in module C10 is conditioned by three levels. The input at terminal M is
a negativE~ level indicating that channel 01 is enabled and that the associated device has requested a break. The input at terminal L is a negative level indicating that there is no break
already in progress on this channel. The input at terminal K is a negative level indicating
that no break is in progress on a channel or higher priority, and that t',e API system as a whol e
is enabled. If these conditions are all met, then the gate becomes fully enabled and generates
a CHAN 01 RQ (channel 01 request) ground level at terminal C1 ON. The CHAN 01 RQ level
is appl ied to the control element, where it generates the memory address assigned to channel 01,
as well as an interrupt request level, which is applied to the break control of the CPo When
the interrupt is granted, the break control generates a command pulse which sets the API address
levels into the MA, and causes the control element to generate a PIB1 pulse. This pulse triggers
NAND gClte DEFH in module C1 0, since the gate is already conditioned by the priority level and
a b012 (1) level. The output of the gate sets the b013 flip-flop to 1. The positive-'going level
transition which appears at terminal B1 as of this flip-flop triggers a pulse amplifier in module
B9, and produces a CLR FLG 1 pulse at terminal B9U. This pulse clears the I/O device flag to
indicate that an interrupt has been granted.
Note that any bXX2 fI ip-flop, which is in the 1 state, produces a ground level at terminal H,
thereby disabling the associated NAND gate RSTU. The inverted output of a disabled RSTU
gate disables inputs 0, K, and R of the thre,e NAND gates associated with the next channel of

6-11

lower priority. This prevents the lower priority channel. from generating either a CHAN RQ
or a ClR FlG signal. When the flags of several devices are set concurrently, the bXX2 flipflop in each of these channels is set by the SYNC pulse. However, the CHAN RQ levels appear
one by one, in order of channel priority.
All flip-flops in all channels are cleared by a CAC+PWR elR pulse generated in the control
element at power turn-on or when a CAe (clear all channels) instruction is executed.
While an interrupt is in progress on channel 01, the'b013 flip-flo:p':r~~c;ins se't. At the end of
the interrupt, both flip-flops b013 and b012 are reset to O. Flip-flop b013 is reset by a
COMMON DEBREAK pulse from the control element, and fl ip-flop b012 is reset by the level
transition of b013 • Note that the COMMON DEBREAK pulse triggers a OCD gate condition
by a ground level from the channel of next higher priority. Therefore/although the COMMON
DEBR pulse is appl ied to all channels, only the channel to wh ich the interrupt was granted is
cleared.

DATA INTERRUPT MULTIPLEXER TYPE 173
Data Interrupt Multiplexer Type 173 consists of 60 FLIP CHIP modules contained in two mountt

ing panels. When this option is added to a standard PDP-7 system, the location of the mounting
panels is somewhat dependent upon th~ number and type of other optional equipment in the
system. When the 173 option is designed into a specific PDP-7 system, convenience may require that the multiplexer be located in a specific portion of the console. Module map
ML-D-173-0-5 shows the locations of modules within the panels. Data Interrupt Multiplexer
Type 173 permits the direct transfer of information between the PDP-7 core memory and one of
four high-speed I/O dev'ices which can supply 15 address lines, 18 data I ines, a request line,
cand a transfer direction line. The multiplexer services the devices in a preset priority order
cand routes the address and data suppl ied by each devi·ce into the data interrupt channel of the
standard PDP-7 system. The data interrupt channel has priority over all other interrupt requests.
'Nhen a data break is granted by the central processor on completion of the current instruction,
the transfer takes place during one computer cycle, under the control of the I/O device. The
maximum combined transfer rate of four devices connected to the CP through the multiplexer
Us 570,000 18-bit words per second.

6-12

logical Functions.
Figure 6-2 shows a block diagram of the logical elements of the data interrupt multiplexer and
their relationship to the central processor. When one or more of the devices connected to the
multiplexer generate a channel DATA RQ level (- 3 volts), the multiplexer control transmits
to the CP a DATA RQ level which causes the DATA SYNC f:ip-flopin the interrupt control to
be set at time T5 DL Y (delayed) of the current cycle. At time T6 of the same cycle, the multiplexer control selects the device having the highest priority. When the central processor reaches
an II instruction done" situation and grants a break cycl e, the following events take place:

ADDRESS
{
LINES FROM
SPECIFIC DEVICE

CH 0 ADDRESS (I5)

CH I ADDRESS (15)

CH 2 ADDRESS (15)

CH 3 ADDRESS (15)

ADDRESS

ADDRESS
MIXER

(15)

...
~

CH 0 OATA (18)

CH 1 OATA (18)
DATA
{
LINES FROM
SPECIFIC DEVICE

....
~

CH 2 DATA .(IB)

DATA
MIXER

DATA (18)

CH 3 DATA (18)

...-

PROCESSOR

MPXB
(4)

CH 0 DATA RQ

.-.

.. T5

CH 0 DATA IN/OUT-.

.. T6

CONTROL
LINES OF
Df:VICE CH 0

DATA IN lOUT (XFER DIRECTION)

.. CH 0 AOOR ACCEPT
~

.. CH 0 OATA ACCEPT
""
.... CH 0 DATA READV

....

MULTIPLEX£R
CONTROL

(5)

Figure 6-2

-....

..-.

REQUEST SLOW CYCLE {IF REQUiRED) ....
'.- ADDRESS ACCEPTED

(5)
CONTROL
{
LINES OF
DEVICES CH 1- 3
(SAME AS CH 0)

DATA REQUEST

.. DATA ACCEPTED

.. DATA READV

Data Interrupt Multiplexer Type 173 Block Diagram

a. At time T1 of the break cycle, the processor transfers the address supplied
by the requesting device into the MA, and the multiplexer returns a negative
ADDR ACC (address accepted) pulse to the requesting device.
b. At time T3, if an in transfer has been specified, the processor transfers
the data suppl ied by the device into the MB, and the multiplexer returns a
DATA ACe (data accepted) pulse to the requesting device.

6-13

c. At time T3, if-an out transfer has been spe'cified, the information that
was stored in the addressed memory cell is held in the MB, and the multiplexer returns a DATA ROY (data ready) pulse to the requesting device,
indicating that the requested data is ready for sampl ing.
d. At time T5 the multiplexer priority chain is cleared"and the processor
interrogates the DATA RQ line.
e .. If the DATA RQ line is still at -3 volts, the processor grants another
break cycle, and the events described in a .through d are repeated until all
requesting devices have been serviced in order of priority. If the DATA RQ
line is at ground, indicating that there is no further data request, the processor fetches and executes the next programmed instruction.

Circuit Operations
The following discussion of the detailed operation of Data Interrupt Multiplexer Type 173 is
based on engineering logic drawings BS-0-173-0-2 and 85-0-173-0-3. References to these
drawings are given in full. Reference is also made to the break control of the central processor I
shown on engineering logic diagram 0-7-0-32; such references are identified by the number 32
in parentheses .

.Data Interrupt Multiplexer Control
Each of the four I/O devices which may be connected to the multiplexer must supply a - 3 volt
CH X DATA RQ level when it is ready to receive or transmit data. The four request lines are
OR combined in module A3 of the multiplexer (C5, 0-173-0-2). A data request from any or
all of the four I/O devices results in the transmission of a negative DATA RQ level to the break
control of the central proce"ssor. This DATA RQ level is AND combined with timing pulse
T5 DL Y to set the DATA SYNC fI ip-flop (A 1, 32). In the break control, the OAT A SYNC (1)
level is inverted in NOR gate NPRSV of module L22 (A7, 32) to produce a negative BK RQ
level which is applied to the major state generator. When the proceS:3or reaches an II instruction
done II situation, the rna jor state generator establishes a break state. The B (break) and OAT A
SYNC (1) levels are combined to produce ci DATA· B level.

6-14

In the multiplexer, the CH X DATA RQ level conditions a gate which is triggered by' timing
pulse T6 of the current computer cycle to set the associated MPX fl ip-flop. There are four
flip-flops, designated MPXO through MPX3. The inverted (l) level of each flip-flop holds all

fl ip-flops of lower priority in the 0 state by pull-over action. Thus, only one fI ip-flop at a
time can be set, and if two or more I/O devices have genernted a DATA RQ level concurrently,
the MPX flip-flop which is set at time T6 will be that associated with the device of highest
priority.
The MPX (1) level performs five functions, as follows:

a. -It conditions the address mixer gates whi'ch connect the address lines of
the requesting device to the MA.

b. It conditions the data mixer gates which connect the data I ines of the
requesting device to the MB.
c. It is NAND combined in module A6 with the CH RQ IN level to produce
a DATA IN level for transmission to the break control of the processor.

d. It is applied to one input of a two-input diode AND gate in a Type R1'41
modul e at location A5. The outputs of the seven gates in th is modul e are

NOR combined. As supplied, the second input of each gate is disabled by
a ground connection; however, if any of the four I/O devices requires a
slow cycle, the associated gate may be conditioned by the CH DATA RQ
and MPXB negative levels to generate a negative RQ SLOW CYe level for
transmission to the processor timing circuits.
e. It is appl ied to the input of a bus driver, whose output conditions three
NAND gates conta.ined in a Type R111 modLile. The Type R111 modules for
channels 0 through 3 are at locations C12 through C15, respectively.

each channel, one NAN D gate is triggered by an ADDR ACC (address
accepted) pulse from the processor; the output of the gate causes an associated
Type W607 pulse amplifier to transmit a CHX ADDR ACC (channel address
accepted) pulse to the requesting device. The second of these gates is triggered

6-15

by a DATA ACC {data accepted} pulse during an inward transfer, and causes
the associated pulse amplifier to transmit a CHX DATA ACC pulse to the
requesting device. The third gate is triggered during an outward transfer by
a DATA RDY {data ready} pulse, and causes the associated pulse amplifier
to transmit a CHX DATA ROY pulse to the requesting device.- The three
control pulses (ADDR ACC, DATA ACC, and DATA RDY) are generated in
the processor (as the DATA ADDR- MA, DATA INFO -MB, and MB
INFO·- OUT pulses, respectively) and are transmitted to the multiplexer
. control.
At tim~ T5, timing pulse T5 {inverted} is applied to the direct clear inputs of all four MPX
flip-flops and resets them to o. If no other I/O device has generated at CH DATA RQ level
in the meantime, the DATA RQ line is at ground and permits timing pulse T5 DLY to clear the
DATA SYNC fl ip-flop in the break control. At the conclusion of the break cycle, the processor will then fetch and execute the next programmed instruction. If, however, a further
C:H DATA RQ level has been generated, the DATA SYNC flip-flop will remain set and the
processor will grant furrher data break cycles until all requesting devices have baen ser·/ic·~d
in order of priority.

Address Mixer and Data Mixer
The address mixer consists of 15 Type R141 Diode Gate modules at locations Bl0 through B24,
C1nd 3 Type B105 Inverter modules each containing 5 inverters. Each Type 141 module contains
seven two~input diode AND gates whose outputs are NOR combined. Three of these diode
AND gates are unused.

In the remaining four gates, one input is conditioned by one of the

MPXB levels; the other input is conditioned by an address line from the associated device. The
~lround level that appear:s at terminal 0 of the Type R141 module when one of its gates is en-

clbled is appl ied to an inverter of the Type B105 module. The resulting negative level conditions
the input gate of the corresponding bit of the MA.
The data mixer is similar in operation to the address mixer, except that the input gates are conditioned by the device data lines and that there are 18 bits instead of 15. The Type 141 modules
CJre located ot positions A7 through A24, a~d the Type 8105 modules at positions 83, B4, C1,

6-16

and C2. EClch inverter in each mixer is equipped with 'a 15-milliampere clamped load; these
loads are contained in Type W005 modules at locations C6 through C8.

EXTENDED ARITHMETIC ELEMENT TYPE 177
The Extended Arithmetic Element (EAE) Type 177 isa standard option for the PDP-7 to facilitatp
high-speed multiplication, division, shifting, and register manipulation. The EAE contains an
18-bit multiplier quotient register (MQ) , a 6-bit step counter register (SC) , two sign registers
and the EAE control logic. The two panels of EAE logic are installed just below the operator
console in bay 2 of the PDP-7 computer. The content of the MQ register is continually displayed on the operator console iust below the ACCUMULATOR indicators.
The Extended Arithmetic Element hardware operates asyncronously to the basic computer cycle,
permitting computations to be performed in the minimum possible time.

Further, since the EAE

instructions are microprogrammed, it is usually possible to simplify programming and shorten computation time by microcoding exactly the arithmetic operation desired.

Logi ca I Func ti ons

I nstructi ons
The EAE instructions are broken up into two parts: The first part permits register manipulation
as microprogrammed in the instruction while data is being fetched; the second part is the specified operation itself. Signed and unsigned multiplication would, for example, differ in the
microprogrammed first part where the sign manipulation is done. The bit configuration for the

EAE instructions is shown in Figure 6-3 and defined in Table 6-1. The set-up phase of the instruction is broken up into three event times. ~I\icroprogramming for all but the set-up commands uses only the first two event times. The bits corresponding to the third event time then
specify the step count of commands such as multiply, divide, and the shifts. The unassigned
operation code (010) should not be used as it is reserved for future EAE expansion.

6-·17

TABLE 6-1

EAE BIT ASSIGNMENTS AND OPERATIONS

Bit
Positions

Bits

0, 1, 2, 3

1101

Function
EAE ope rat ion code.

Place the AC sign in the link. Used for
signed operations.

Clear the MQ.

Read the AC sign into the EAE AC sign
register prior to carrying out a stepped
operation. Used for the signed operations
multipl y and divide.

6, 7

Toke the absol ute val ue of the AC. Takes
place after the AC sign is read into the EAE
AC sign.

Incl usive OR the AC with the MQ and read
into MQ. (If bit 5 is a 1, this reads the AC
into the MQ) •

Clear the AC.

9,10,11

000

Setup. Specifies no stepped EAE operation,
and enables the use of bits 15, 16, and 17.
It is used as a preliminary to multiplying,
dividing, and shifting s'igned numbers.
Execution time is one cycle.

9,10,11

001

Multiply. Causes the number in fhe MQ to
be multipl ied by the number in the memory
location following this instruction. If the
EAE AC sign register is 1, the MQ will be
complemented prior to mul tipl ication. The
exclusive OR of the EAE AC sign and the
I ink will be pi aced in the EAE sign reg ister
(the sign of product and quotient).
The product is left in the AC and MQ, with
the lowest order bit in t.i,Q bit 17. The program cont inues at the Iocat ion of th is instruction plus two. At the completion of
th is instruct ion the link is c Ieared and if the
EAE sign was 1, the AC and MQ are

6-18

TABLE 6-1
Bit
Positions

EAE BIT ASSIGNMENTS AND OPERATIONS (continued)
Bits

Function

9,10,11

001 (continued)

complemented. The step count of this instruction should be 22 (octal) for a 36-bit
multiplication, but can be varied to speed
up the operation. The execution time is
4.2 to 8.7 ~sec, depending on number of
1 bits in the MQ.

9,10,11

010

Th is is an unused ope rat ion code reserved
for possible future expansion.

9, 10, 11

011

Divide. Causes the 36-bit number in the
AC andMQ to be divided by the l8-bit
number in' the register following the instruction. If the EAE AC sign is 1, the
MQ is complemented prior to starting the
division. The magn itude of the AC is
taken by microprogramming the instruction.
The exclusive OR of the AC sign and the
I ink are pi aced in the EAE sign. The part
of the dividend in the AC must be less than
the divisor or overflow occurs. In that case
the 'I ink is set at the end of the divide;
otherwise, the link is cleared. At the completion of this instruction, if the EAE sign
was a 1, the MQ is complemented; and if
the EAEAC sign was 1, the AC is complemented. Thus the remainder has the same
sign as the div idend. The step count' of th is
instruction is normal Iy 23 (octal) but can be
decreased for certain operations. The execution time is 3.5 ~sec in the case of divide
overflow or from 9.0-12.6 ~sec otherwise.

9,10,11

101

Long right sh ift. Causes the AC and MQ to
be sh if ted right together as a 36-bit reg ister
the number of times specified in the step
count of the instruction. On each step the
I ink fills AC bit-O I /\C bit-17 fills MQ
bit-O, and MQ bit- i 7 is lost. The I ink
remains unchanged. The tim e is O. 1 n
+ 1.6 }Jsec, where n is the step count.

6-,19

TABLE 6-1

EAE BIT ASSIGNMENTS AND OPERATIONS (continued)

Bit
Positions

Bits

9,10,11

110

Long left shift. Causes the AC and MQ to be
shifted left together the number of times specified in the step count of the instruction. On
each step, MQ bit 17 is filled by the link;
the link remains unchanged. MQ bit 0 fills
AC bit 17 and AC bit 0 is lost. The time is
O. 1 n + 1 .6 I-lsec, where n is the sh ift count.

9,10,11

100

Normal ize. Causes the AC and MQ to be
shifted left together until either the step
count is exceeded or AC bit a f. AC bit 1 •
MQ bit 17 is filled by the link, but the link
is not changed. The step count of this instruction woul d normal! y be 44 (octal).
When the step counter is read into the AC,
it contains the number of sh ifts minus the
initial shift count as a 2 1s complement 6-bit
number. The time is O. 1 n + 1 .6 I-lsec, where
n is the number of steps in the sh ift counter
or the number required to effect normal ization,
wh ichever is less.

9,10,11

111

Accumulator left shift. Causes the AC to be
shifted left the number of times specified
in the shift count. AC bit 17 is filled by the
I ink, but the I ink is unchanged. The time is
O. 1 n + 1 .6 I-lsec, where n is the step count.

Function

Specify the step count except in the case of
the setup command, wh ich does not change
the step cou nter •

12-17

On the setup command ani y, causes the MQ
to be complemented.

On the setup command onl y, causes the MQ
to be inclusive ORed with the AC and the
result placed in AC. (If the AC has been
cleared, this will rloce the MQ into the AC).,

On the setup command only, causes the AC to
be inclusive ORed with the SC and the results
placed in AC bits 12-17. (If the AC has been
cleared, this will place the SC into the AC).

6-20

EAE ()PERATION

CODE (6'U

IF 81Ta1
*"

~~1_2__~3-4 4~5 ~:-4 1~_8~~EA_:_C~'!_M~_~_N~Dl_1_1~_12~1_1_3_~114~,_1_5~_1_6~_17~1
1

___

I
J

I
I.J
I
~
I

n 6~
:I

~
~
....

;t- - -- - I ! _IF~S'IO{

DIVIDE
tOO NORMALIZE

I EVENT
TIME 1
I (EAE
T3)

I
I
I

101 LONG RIGHT
t a LONG LEFT
1 t 1 AC LEFT

MULTIPLY

011

000 SETUP

oat
at 0

0.....

~I--~-:o:-+-+--·---+-----...J.-----i"

I
I
I

I
I

~---i-

I
I

~11
~
~

~
~

SHIFT
(IF EAE COMMA NO "I- 0001

- -,, 1:811 1 'I - - - I
I
I
I
L ___

Figure 6-3

(IF EAE

I COMMAND=OOO)

1 ____ L___

EVENT

~ TlME 2

(EAE T4)

~---r-~--

L ___ ~l ___

COUNT

u
«
1\

EVENT
TIME 3
(EAE T5)

(/)

EAE Instruction Bit Assignment

Execution of Instructions
EAE instructions which do not require reference to memory take one computer fetch cycle plus
the time required to complete the EAE operations. The 'processor timing chain is stopped at the
end of the fetch cycle, and is restarted when EAE operations are complete.
EAE i nstructi ons which requi re reference to memory (to fetch an argument) occupy a fetch cyc Ie
and a hybrid cycle, plus the time required to complete the EAE operations. DurinS-J ~the fetch
cycle, the EAE instruction is fetched from memory and partially executed. During the first
portion of the augment fetch cyc Ie I the norma I events of a fetch cyc Ie occur; that is I at time
T1 the IR is cleared, the content of the PC is transferred to the MA and is then inc;-emented by
1; at time T2 the MB is cleared and a read operation is initiated, the content of the addressed
cell being strobed into the MB between times T2 and T3, and the READ flip-flops being cleared
at time T3. These events result in the argument being retrieved from the memer), location immediately following the location whi ch contained the EAE instruction. At time T3 of the hybrid cycle a START MUL, DIV pulse generated in the EAE forces the major state g~nerator to
~he execute state and at the same time forces the operati on code for D ZM (14 , or lAO, I B3)
8
into the instruction register. During the remainder of this cycle, the processor writes the content

6-21

of the MB back into memory; then the EAE generates a STOP CP TC level which prevents timing
plJlse TP7 from being returned to the start of the processor timing chain and so stops the timing
circui ts of the processor. EAE operations ore then timed and counted by logic elements of the
EAE and multiplication or division starts. At the conclusion of these operations, a START CP

Te pulse restarts the proc'essor timing chain, permitting the processor to fetch and execute the
next instruction.
Sheet 1 of the EAE Flow Diagram, engineering drawing FD-D-177-0-2, shows the possible sequences of events during a fetch cycle in which an EAE instruction is ~tched, and the events
which take place at times T2 and T3 of an ensuing hybrid cycle (in whtch an argument is fetched).
Sheet 2 of the EAE Flow Diagram shows the events which take place under control of the EAE
.timing, during the period when the processor timing chain is inhibited. Operations concerned
with starting and ending the EAE sequence are shown in the top ri ght portipn of the diagram;
the last point in the START/END sequence, designated ENTRY 1 may leadt into the Multiply,
Divide, or Shift sequences. Mu Itiply or Divide sequences also entai I entry.., into the ADDER/
SUBTRACTOR st:quence. The counting precess performed by the step counter'register is shown
:"';"i-

at the bottom left of this flow diagram, and the events which take place when· the SC register
:...r.

overflows (indicating that a II required steps have been -performed) are shown at the bottom right. '
Program examples of the use of the EAE are given in the PDP-7 Users Handbook, F-75.

~Circuit Operations

The logical circuits of the EAE are shown on block schematic engineering drawings BS-D-177-0-4
through B5-D-177-0-9. Drawing B5-D-7-0-40 shows special control signal interface between
the processor and the EAE option. Refer to these drawings when cnalizing the circuit operations
c~f this option.

6-22

CHAPTER 7
INTERFACE

INTERFACE CONNECTIONS AND SIGNAL IDENTIFICATION

All signals passing between the processor of the PDP-7 and the peripheral equipment are routed'
through the interface section of the computer. Interface connections are made either by coaxial cable c)r by ribbon cables terminated in a Type W021 Signal Cable Connector •. This cable
connector is described in detail in the Digital FLIP CHIP Modules Catalog, C-105. The cable
connector plugs into the appropriate FLIP CHIP module receptacle. Interface cable connections
made to the module mounting panels of the processor are shown on engineering drawing
CL-D-7-0-38 with detai led signal and terminal identification information. The interface is so
designed that the information collector and infc)rmation distributor can be expanded (with suitcble bus drivers) a Imost indefinite Iy to support any desired array of peripheral equipment, up
ro the most expansive computing system imag:nable.

All logic signals that pass between the PDP-7 and the I/O equipment are standard DEC levels
or standard DEC pulses. Logic signals are assigned mnemonic names that indicate the condition
represented by assertion of the signal. Standard levels are either ground potential (0.0 to O.3v)
designated by an open diamond (
diamond (
angle (

<»

or are -3v (- 3.0 to -4.Ov) designated by a solid

. ) . Standard pulses in the p()sitive direction are designated by an open tri-

t> ), and negative pulses are designated by a solid triangle (

... ). Pulses

originating in R series modules are positive-going pulses which start at - 3v, go to ground for
100 nsec, then return to - 3v. Pulses originatIng in W series modules are bipolar, are always
referenced to ground, are 2.5v in amplitude (2.3 to 3.0v) with a 2v overshoot, and are of
400-nsec durati on (or 1 llsec if se lected on the W640) •
Tables 7-1 and 7-2 provide cable connections and logic circuit identification for basic PDP-7
interface signa Is.

7-1

TABLE 7-1

OUTPUT SIGNALS
Signal Origin

Signal

Symbol

Interface
Connection

Terminal

Module
Type

Logic

Block Schematic
Drawing

ACBO(l)

lL1D- 1L9D

1K3J

R650

Information
Distributor

BS-0-7-0-34

ACB 1(1)

1L1E- 1L9E

lK3T

R650

Information
Distributor

BS-0-7-0-34

ACB2(1)

1L1H- 1L9H

1K4J

R650

Information
Oistributor

BS-D-7-0-34

ACB3(1)

1L1 K- 1L9K

1K4T

R650

Information
Distributor

BS-0-7-0-34

ACB4(1)

1L1M- 1L9M

lK5J

R650

Information
Distributor

BS-0-7-0-34

ACB5(1)

1L1P- 1L9P

lK5T

R650

Information
Distributor

B5-0-7-0-34

ACB6(1)

1L1S- 1L9S

1K6J

R650

Information
Oistdbutor

BS-0-7-0-34

ACB7(1)

1L1T- 1L9T

lK6T

R650

I nformati on
Distributor

BS-0-7-0-34
•

ACB8(1)

1L1V- 1L9V

lK7J

R650

Information
Distributor

BS-0-7-0-34

ACB9(1)

-0

lM10- 1M9D

1K7T

R650

Information
Di stributor

BS-D-7-0-34

ACB 10(1)

1M lE- lM9E

1K8J

R650

Informati on
Distributor

BS-0-7-0-34

ACB11 (1)

lM1H- 1M9H

1K8T

R650

I nformati on
Distributor

BS-0-7-0-34

ACB 12(1)

lM1K- lM9K

1K9J

R650

I nformati on
Distributor

BS-0-7-0-34

ACB13(l)

lM1M- lM9M

1K9T

R650

Information
Distributor

BS-0-7-0-34

ACB 14(1)

-0

lM1P- 1M9P

1K10J

R650

InforiT;~tion

BS-0-7-0-34

Distributor
ACB 15(1)

1M1S- lM9S

1K10T

7-2

R650

Information
Distributor

BS-0-7-0-34

TABLE 7-1

OUTPUT SIGNALS (continued)
Signal Origin

Signal

Symbol

Interface
Connection

Terminal

Module
Type

ACB 16(1)

1M1T- 1M9T

1 Kl1J

R650

Information
Distributor

85-0-7-0-34

ACB17(1)

1M1V- 1M9V

1K11T

R650

Informati on
Distributor

BS-0--7-0-34

lOT 7001

20130

2C13H

W640

Oevice
Selector

B5-0-7-0-36

lOT 7002

II-

20110

2C13N

W640

Oevice
Selector

B5-0-7-0-36

2011E

2C13U

W640

Oevice
Selector

B5-0-7-0-36

2013E

2C14H

W640

Oevice
Selector

BS-0-7-0-36

2011 H

2C14N

W640

Oevice
Selector

BS-0-7-0-36

lOT 7004
lOT 7101
lOT 7102

.
-..
.

Logic

BIQck Schematic
Drawing

lOT 7104

2011K

2C14U

W640

BS-0-7-0-36

lOT 7201

Device
Selector

2013H

2C15H

W640

Oevice
Selector

BS -0 -7-0-36

lOT 7202

2011M

2C15N

W640

Oevice
Selector

BS-0-7-0-36

2D11P

2C15U

W640

Oevice
Selector

B5-0-7-0-36

lOT 7204

lOT 7301

2013K

2C16H

W640

Oevice
Selector

B5-0-7-0-36

lOT 7302

... 20115

2C16N

W640

Oevice
Selector

BS-0-7-0-36

lOT 7304

It-

2013M

2C16U

W640

Oevice
Selector

BS-0-7-0-36

lOT 7401

2011 TI
2D13P

2C17H

W640

BS -D -7 -0-36

lOT 7402

... 2011V

Oevice
Selector

2C17N

W640

Device
Selector

B5-D-7-0-36

7-3

TABLE 7-1

OUTPUT SIGNALS (continued)
Signal Origin

Signal

Symbol

Terminal

Module
Type

2D12K,
-.. 2013S

2C17U

W640

Oevice
Selector

BS -D-7-0-36

IC'T 7501

20140

2C18H

W640

Device
Selector

. BS-0-7-0-36

lOT 7501 (B)

....

.2D14M,
20150

2C18H

.W640

Device
Selector

BS-0-7-0-36

2D14E,
2015H

2C18N

W640

Device
Selector

BS-0-7-0-36

1==
lOT 7404

lOT 7502

Interface
Connection

Logic

Block Schematic
Drawing

I()T 7504

II-

2D14H

2C18U

\N640

Device
Selector

BS-0-7-0-36

rOT 7601

r. 2015K

2C19H

W640

Device
Selector

BS-0-7-0-36

lOT 7602

II>

2C19N

W640

Oevice

B5-0-7-0-36

lOT 7604

2015M

Se lect")r
2014K

2C19U

W640

Device
Selector

B5-0-7-0-36 '

"~BBO(l )

•

2C3D

18220

B684

MB Bus
Drivers

B5-0-7-0-35

MBB 1(1)

• 2C3E

1B22N

B684

MB Bus
Drivers

BS-0-7-0-35

MBB2(1)

•

2C3H

1B230

B684

MB Bus
Orivers

BS -0 -7-0-35

~ABB3(1)

• 2C3K

lB23N

B684

MB Bus
Orivers

B5-0-7-0-35

MBB4(1)

•

1B240

B684

MB Bus
Drivers

B5-0-7-0-35

/V\BB5(l)

• 2C3P
• 2C35

lB24N

B684

MB Bus
Orivers

B5-0-7-0-35

1B250

B684

MB Bus
Drivers

B5-D-7-0-35

1B25N

B684

MB Bus
Drivers

B5-0-7-0-35

MBB6(1)
~'ABB7(1 )

2C3M

• 2C31

7-4

TABLE 7-1

OUTPUT SIGNALS (continued)
Signal Origin

Signal

Symbol

Terminal

Module
Type

2C3V

1B260

B684

MB Bus
Drivers

B5-0-7-0-35

2C3D

1B26N

B684

MB Bus
Drivers

B5-0-7-0-35

• 2C4E
• 2C4H
• 2C4K
• 2C4M
• 2C4P
• 2C4S
• 2C4T

1B270

B684

MB Bus
Drivers

B5-0-7-0-35

1B27N

B684

MB Bus
Drivers

BS-0-7-0-35

1B280

B684

MB Bus
Drivers

B5-0-7-0-35

lB28N

B684

MB Bus
Drivers

BS-0-7-0-35

18290

B684

MB Bus
Drivers

B5-0-7-0-35

1B29N

B684

MB Bus
Drivers

BS-D-7-0-35

1B30D

B684

MB Bus
Drivers

B5-0-7-0-35

• 2C4V
• 2C1D
• 2C1E

·lB30N

B684

MB Bus
Drivers

B5-0-7-0-35

B9D

B684

MB Bus
Drivers

B5-D-7-0-35

B9N

B684

MB Bus
Drivers

B5-D-7-0-35

• 2C1H
• 2C1K

B11D

B684

MB Bus
Drivers

BS-D-7-0-35

811N

8684

MB Bus
Drivers

BS-D-7-0-35

• 2C1M
• 2C1P

8130

B684

MB Bus
Drivers

B5-D-7-0-35

S13N

B684

MB Bus
Drivers

B5-D-7-0-35

•
•

MBBS(1)
MBB9(1)
MBB10(l)
MBB11 (1)
MBB 12(1)
MBB 13(1)
MBB 14(1)
MBB 15(1)
MBB16(1)
MBB17(1)
MBB6(0)
MBB7(O)
MBB8(0)
MBB9(0)
MBB10(O)

,
MBS 11(0)

Interface
Connection

7-5

Logic

Block Schematic
Drawing

TABLE 7;"1

OUTPUT SIGNALS {continued}
Si gna I Ori gin

Signal

Symbol

MBB 12(0)

•

BGN(B}

Interface
Connection

Terminal

- Module
Type

2C15

B15D

B684

MB Bus
Drivers

85-0-7-0-35

...

2C28U

W640

Timing

B5-0-7-0-22

NEG PWR
CLR

....

2C28H

W640

Spec.
Cyce

B5-0-7-0-20

PWR CLR

1C28P

W640

Spec.
Cyc.

BS-0-7-0~20

DATA ADDR
ACC

1L16H

W607

Interrupt
Control

BS-0-7-0-32

lL16N

W607

Interrupt
Control

B5-0-7-0-32

1L16U

W607

Interrupt
Control

B5-0-7-0-32

DATA ACC

---

DATA ROY

TABLE 7-2

Logic

Block Schematic
Drawing

INPUT SIGNALS
Signal Destination

Signal
::

Symbol

Interface
Connection

Termina I

Module
Type

Logic

Block Schematic
Drawing

RBO -

•

1N15D

lM15F

R141

Information
Collector

BS-D-7-0-33

RBt

• lN15E

lM16

R141

I nformati on
Collector

BS-0-7-0-33

lN15H

tM17F

R141

Information
Collector

B5-0-7-0-33

1N15K

1M18F

R141

Information
Collector

B5-0-7-0-33

RB4

• 1N15M

1M19F

R141

Infcr:-,'oti on
Collector

B5-D-7-0-33

RB5

•

lM20F

R141

I nformati on
Collector

BS-0-7-0-33

RB2
RB3

•
•

1N15P

7-6

TABLE 7-2

INPUT SIGNALS (continued)
Signal Origin

Signal

RBS
RB9
RB10
RB 11

RB12
RB13
RB14
RB15
RB16
RN17
MQl
III- AC

MQ2

Terminal

Module
Type

1 N15S

lM21F

R14l

Information
Collector

BS-0-7-0-33

lN15T

lM22F

R141

Informati on
Collector

BS -0 -7-0-33

1N15V

lM23F

R141

Information
Collector

BS-0-7-0-33

lN160

lM24F

R14l

Informati on
Collector

B5-0-7-0-33

1 N16E

lM25F

R141

Informati on
Collector

8S-0-7-0-33

lN16H

lM26F

R141

Informati on
Collector

BS-O··7-0-33

lN16K

1M27F

R141

Informati on
Collector

B5-D-7-0-33

lN16M

1M28F

R141

Information
Collector.

85-0-7-0-33

lN16P

lM29F

R141

Information
Collector

B5-D-7-0-33

lN16S

IM30F

R141

Information
Collector

B5-0-7-0-33

1 N16T

lM31F

RI41

Information
Collector

B5-0-7-0-33

lN16V

lM32F

R141

Information
Collector

BS-D--7-0-33

lN32S

lM15K

R141

Information
Collector

BS-0-7-0-33

•

N190

lM15L

R141

Information
Collector

B5-0-7-0-33

N19E

1M16L

R141

Information.
Collector

BS-0-7-0-33

N19H

lM17L

R141

Information
Collector

BS-D-7-0-33

•
•
•
•
•
•
•
•
•
•
•

RB7

MQl

Interface
Connection

•

RB6

Symbol

•
•

7-7

Logic

Bloc k Schema ti c
Orclwing

TABLE 7-2

INPUT SIGNAL~ {continued}
Signal Destination

Signal

MQ3
MQ4
MQ5
MQ6
MQ7
MQS

Symbol

•
•
•

Interface
Connection

Terminal

Module
Type

N19K

IM1SL

R141

Information
Collector

B5-0-7-0-33

N19M

IM19L

R141

Information
Collector

B5-D-7-0-33

N19P

IM20L

R141

Information
Collector

85-0-7-0-33

N195

IM21L

R141

Information
Collector

B5-0-7-0-33

N19T

IM22P

R141

Jn forma ti on

85-0-7-0-33

Logic

Block Schematic
Drawing

Collector
N19V

IM23L

R141

Information
Collec'tor

B5-0-7-0-33

N20D

IM24L

R141

Information
Collector

BS-D-7-0-33

N20E

IM25L

R141

Information
Collector

B5-D-7-0-33

N20H

IM26L

R141

Information
Collector

B5-0-7-0-33

N20K

1M27L

R141

Information
Collector

BS-0-7-0-33

MQ13

• N20M

IM28L

R141

Information
Collector

B5-D-7-0-33

MQ14

•
•

N20P

IM29L

R141

Information
Collector

B5-0-7-0-33

N20S

IM30L

R141

Informati on
Collector

BS-D-7-0-33

N'20T

IM31L

R141

• Information
Collector

85-D-7-0-33

N20V

IM32L

R141

Information
Collector

BS-D-7-0-33

N210

IM15N

R141

Information
Collector

B5-D-7-0-33

MQ9
MQ10
MQl1
MQ12

,MQ15
MQ16
MQl7
[)TIO

•
•
•
•

•
•
•

TABLE 7-2

INPUT SIGNALS (continued)
Si gna I Destination

Signal

Symbol

Interface
Connection

Teminal

Module
Type

N21E

lM16N

R141

Information
Collector

BS-0-7-0-33

N21H

1M17N

R141

Information
Collector

BS-0-7-0-33

N21K

lM18N

R141

Information
Collector

BS-0-7-0-33

N21M

lM19N

R141

Information
Collector

BS"";0-7-0-33

N21P

1M20N

R141

Information
Collector

BS-0-7-0-33

N21S

1M21N

R141

Information
Collector

BS-0-7-0-33

N21T

lM22N

R141

Information
Collector

BS-0--7-0-33

N21V

11\\23N

R141

Information
Collector

BS-0-7-0-33

N220

lM24N

R141

Information
Collector

BS-0-7-0-33

N22E

lM25N

R141

Information
Collector

BS-0·-7-0-33

N22H

1M26N

R141

Informati on
Collector

BS-0-7-0-33

N22K

1M27N

R141

Information
Collector

B5-0,-7-0-33

N22M

1M28N

R141

Information
Collector

B5-0-7-0-33

N22P

1M29N

R141

Information
Collector

BS-0-7-0-33

OTI15

• N22S

lM30N

R141

Informati on
Collector

BS-0-7-0-33

OTI16

•

1M31N

R141

Informati on
Collector

BS-0-7~O-33

OT11
OT12
OT13
OT14
OT15
OT16
OT17
OT18
OT19
DTI10
OTl11
OTI12
OTI13
OTI14

•
•
•
•
•
•
•
•
•
•
•
•
•
•

N22T

7-9

Logic

Block Schematic
Drawing

TABLE 7-2

INPUT SIGNALS (continued)
Signal Destination

Signal
'-'-:

DTll7
'CA5
CA6
CA7
CAS
CA9
CAlO
CAll
CAl2
CA13
CA14
CAl5
CA16
CAl7
. DATA FLo/
LP FLAG
BLOCK
FLG/STOP
FLAG

Symbol

Block Schematic
Drawing

Interface
Connection

Terminal

Module
Type

N22V

lM32N

Rl4l

Information
Collector

BS-0-7-0-33

N23P

1M20R

Rl4l

Informati on
Collector

BS-0-7-0-33

N23S

1M21R

Rl41

. Information
Collector

BS-D-7-0-33

N23T

1M22R

Rl41

Information
Collector

BS-0-7-0-33

N23V

1M23R

R141

Information
Collector

BS-0-7-0-33

N240

IM24R

Rl41

Information
Collector

BS-0-7-0-33

N24E

lM25R

Rl41

Information
Collector

BS-0-7-0-33

N24H

1M26R

R14l

Information
Collector

BS -0
, -7-0-33

N24K

IM27R

R141

Information
Collector

BS-0-7-0-33

N24M

lM2SR

Rl4l

Information
Collector

BS-D-7-0-33

N24P

lM29R

R14l

Information
Collector

B5-0-7-0-33

N24S

lM30R

R141

Information
Collector

B5-0-7-0-33

N24T

lM31R

R141

Information
Collector

B5-0-7-0-33

N24V

lM32R

R14l

Informati on
Collector

B5-0-7-0-33

• N250
• N25E

1,\'\ 15T

R141

Informati on
Collector

B5-0-7-0-33

1Ml6T

R14l

Information
Collector

B5-0-7":0-33

•
•
•
•
•
•
•
•
•
•
•
•
•
•

.r.

7-10

Logic

TABLE 7-2

INPUT SIGNALS (continued)
Signal Oestination

Signal

Symbol

ERR-FLG

•

OFF ENO

•
•

Block Schematic
Orawing

Interface
Connection

Terminal

Module
Type

N25H

1Ml?T

R141

Informa ti on
Collector

BS-0·-7-0-33

N25K

lM18T

R141

Informati on
Collector

BS-0-7-0-33

N25M

lM19T

R141

Information
Collector

BS-0-7-0-33

• N25P
• N255
• N25T
• N25V
• N26E
• N26H

1M20T

R141

Informati on
Collector

B5-0-7-0-33

1M21T

R141

Information
Collector

BS-0--7-0-33

lM22T

R141

Informa ti on
Collector

BS-0·-7-0-33

lM23T

R141

Informati on
Collector

BS -0 -7-0-33

lM25T

R141

Information
Collector

B5-D-7-0-33

lM26T

R141

Information
Collector

B5-0-7-0-33

N26K

1M27T

R141

Informati on
Collector

B5-0-7-0-33

N26M

1M28T

R141

Information
Collector

85-0-7-0-33

• N26P
• N26S
• N26T

1M29T

R141

Information
Collector

85-0-7-0-33

lM30T

R141

Information
Collector

8S-D-7-0-33

1M31T

R141

Information
Collector

8S-D-7-0-33

TT8

• N26V

lM32T

R141

Information
Collector

8S-0-7-0-33

DR LATE

• N270

lM15V

R141

Information
Collector

8S-D-7-0-33

TIMING
ERR
REVERSE
GO
MARK
TRK ERR
UNABLE
TTl
TT2
TT3
TT4
TT5
TT6
TT7

•
•

7-11

Logic

TABLE 7-2

INPUT SIGNALS (continued)
Signal Destination

Signal

Symbol

Interface
Connection

Terminal

Module
Type

lM16V

Logic

Block Schematic
Drawing

R141

Information
Collector

85-0-7-0-33

lMl7V

R141

Information
Collector

B5-o-7-0-33

lM18V

R14l

Information
Collector

B5-0-7-0-33

lM19V

R141

Information
Collector

B5-0-7-0-33

lM20V

R141

Information
Collector

B5-0-7-0-33

lM21V

R141

Information
Collector

85-0-7-0-33

N27T

lM22V

R141

Information
Collector

B5-0-7-0-33

N27V

lM23V

R141

Information
Collector

85-0-7-0-33

MISS CHAR

• N6V

M24Y

R141

Information
Collector

B5-0-7-0-33

SCl

•
•

N26K

M27V

R141

Information
Collector

85-0-7-0-33

N26M

M28V

R141

Information
Collector

85-0-7-0-33

• N26P
• N265
• N26T
• N26V

M29Y·

R141

Informati on
Collector

85-0-7-0-33

M30V

R14l

Informati on
Collector

B5-0-7-0-33

M31Y

R141

Information
Collector

85-0-7-0-33

M32V

R14l

I nforr"1ati on
Collector

85-0-7-0-33

A18M

B201

B5-0-7-0-29

A19M

B201

85-0-7-0-29

"e:

PARITY
ERR
READ
COMP ERR
EOF

WRITE.
LOCK
LOAD
POINT
END
POINT
TRo WR/LR
REWIND

SC2
SC3
SC4
SC5
SC6
oA3(1)
DA4(1)

• N27E
• N27H
• N27K
• N27M
• N27P
• N275

•

• B31K
B31M

•

7-12

TABLE 7-2

INPUT SIGNALS {continued}
Signal Destination

Signal

OA5(1}
OA6(1)
DA7(1)
DAS(l)
DA9(l)
DA 10(1)
OA 11 (1)
OA12(1)
DA 13(1)
OA14(1)
DA 15(1)
OA 16(1)
DA 17(1)
010(1)
011(1)
012(1 )
013(1)
014(1)
015(1)
016(1)
017(1)
OIS(l)
019(1 )
0110(1)
0111(1)
0112(1)
0113(1)

•

Symbol

Terminal

Module
Type

• B31P
• B31S
• B31T
• B31V
• C310
• C31E
• C31H

A20M

B201

BS-0-7-0-29

A21M

B201

BS-0-7-0-29

A22M

B201

BS-0-7-0-29

A23M

B201

BS-0-7-0-29

A24M

B201

BS-0-7-0-29

A25M

B201

BS-0-7-0-29

A26M

B201

BS-0-7-0-29

C31K

A27M

B201

BS-0-7-0-29

C31M

A2SM

B201

BS-0-7-0-29

C31P

A29M

B201

BS-0-7-0-29

C31S

A30M

B201

BS-0·-7-0-29

• C31T
• C31V
• A10

A31M

B201

55-D-·7-0-29

A32M

B201

BS-0-7-0-29

C2M

B201

BS-0-7-0-30

C3M

B201

BS-0-7-0-30

C4M

B201

BS-0-7-0-30

C5M

B201

BS-0-7-0-30

C6M

B201

BS -0-7 -0-30

•
•
•

•

Interface
Connection

• AlE

Logic

Block Schematic
Drawing

• A1H
• A1K
• A1M
• AlP
• A1S
• A1T
• A1V
• A20
• A2E

C7M

8201

BS-0-7-0-30

CSM

' B201

BS-0-7-0-30

C9M

B201

BS-0-7-0-30

C10M

B201

BS-0-7-0-30

C11M

B201

BS-0-7-0-30

C12M

B201

BS-D-7-0-30

A2H

C13M

B201

B5-0-7-0-30

A2K

C14M

B201

B5-0-7-0-30

A2M

C15M

B201

B5-0-7-0-30

•

7-13

TABLE 7-2

INPUT SIGNALS {continued}
Signal Destination

Signal

0114(1)
0115(1 )
0116(1)
0117(1)·
DATA RQ
57A SLOW
eyC

Symbol

Interface
Connection

• A2P
• A25
• A2T
• A2V

•
•

2D15S

Terminal

·Module
Type

C16M

B201

85-0-7 -0-30

C17M

8201

85-0-7-0-30

C18M

8201

85-0-7-0-30

C19M

B201

·85-0-7-0-30

L23D

. B105

Interrupt
Control

85-0-7-0-32

2B26

B171

Device
Selector

85-0-7-0-36

Logic

Block Schematic
Drawing

LOADING AND DRIVING CONSIDERATIONS
All interface circuits within the PDP-7 consist of series Rand W FLIP CHIP modules. 'When interconnecting" these circuits with those in the periphera I equipment, it is important to keep the ioad
on each circuit within its driving abi lity. Driving and loading capabi lities of most DEC modu les
used in the PDP-7 and in standard DEC optional equipment are specified in detai I in the Digital
FLIP CHIP Modules Catalog, C-105.
All inputs to series R modules consist of either diode gate or diode-capacitor-diode (DCD) gate
circuits. All inputs draw current in the same direction. Each diode gate input at ground level
draws 1 rna. A diode gate with an internal clamped load resistor can drive an 18-ma external
load. A flip-flop consists of two cross-connected diode gates. The direct set and clear terminals draw 1 rna. The output capability is 20 rna, less 2 rna for the load resistor permanently
connected in the flip-flop, and 1 rna required to condHion the opposite side of the flip-flop.
The flip-flop can, therefore, drive a 17-ma external load.
The DeD gate circuits on flip-flops and pulse amplifiers draw 2 rna at the level inputs and 3 rna
at the pulse inputs when the level is conditioned; 1 rna when the level input is disabled. When

7-14

two oeD gates are driving both sides of the same flip-fl~p, the load on both pulse inputs totals
only 4 mo. When the level inputs are tied together as in a complement configuration, the total
input load is only 3 ma.
Capacitive loading adversely affects the performance of series R modules; therefore, where long
lines are being driven, extra clamped loads should be added to sufficiently discharge the cable
capacitance. As a genera I ru Ie, an extra 2 ma of clamped load current shou Id be added for
every foot of wire beyond 1-1/2 ft. An exception to this rule is the R650 Bus Driver module.
This module is designed to drive coaxial cable of 100-ohm characteristic impedance through a
series driving resistor. If coaxial cable is not used, t~e direct output may be used, provided
that the lines are short. If reflections occur on the line, the resistive output of the bus driver
mey be used to correct the problem. Shunt termination on the far end of the transmi~sion line
is not recommended.
The R650 Bus Driver has two types of outputs: the fast and the slow (or ramp} output. Using the
fast output, the bus driver operates as a fast amplifier. When the ramp output is used, an integrating capacitor is inserted between the input of the bus driver and the output stage, causing
the output lines to move from ground to -3v or in the reverse directioll in approximately 800 nsec.
This connection, which is desirable to reduce crosstalk between lines, is used on the ACB (buffered accumulator) lines.
The W640 Pulse Amplifier modules should be carefully terminated. "If sufficient noise is generated at the output of these modules, regeneration may result. For this reason, it is recommended
that output lines of W640 Pulse Amplifier mpdules be well shielded~ The outputs of W640 modules may be either 400 nsec or 1 lJsec in width.. All connections on the standard PDP-7 use the
400 nsec pulse width.
All input signals to the PDP-7 are received by diode gates or inverters. Diode gates inputs
draw 1 ma of current from the driving circuit, shared among all inputs at ground potential. Inverter inputs draw 2 ma when the signal is at -·3v and provide no load when the signal is at
ground potential.
Timing is, in general, determined by the machine itse If. However I the following timing considerations apply to the modules. The Rlll Diode Gate sets up in approximately 50 nsec in

7-15

E~ither direction under normal load conditions.

Fall times are faster with heavier loads, and

the best method to speed up a slow Rl11 Diode Gate is to connect an external load across the
input to ground. The DCD gates set up in 400 nsec, as measured from the end of tf,e preceding
1100-nsec pulse; and the pulse input must return to - 3v for 400 nsec before the next pulse is
(Jpplied. Series R pulses are 100 nsec in width, measured from the 10% point of the leading
E!dge to the 90% point of the trailing edge. Fall time is not critical on these pulses, provided
that the pulse has returned to - 3v in time to come up for the next pulse.
All outP'ut signals from the PDP-7, routed through the interface, have been provided with adecluate buffer~ng to meet the input requirements of all.normal I/O equipment. Whenever it bec:omes necessary for the user to draw out other signals (besides those connected in the standard
interface), care must be taken to ensure that the input loads presented to the sources of these
signals does not exceed their driving ability. When it is evident that the source would be
clverloaded, a suitable driver must be provided between the signal source and the I/O device
employing the signal.
NOTE: Numbers in parentheses included an headings of the remainder of this chapter designate the last digit of the block schematic engineering drawing for the logic circuit or signal discussed. ·

INFORMATION COLLECTOR (lC) (33)
The IC reads data or status information into the AC from various periphera I devi ces. Seven IC
channels or levels, are available in the basic machine. Each of these channels are wired to a
sHgnal cable connector corresponding to an upper half (bits 0-8) and a lower half (bits 9-17) of
the AC. On the basic machine the paper-tape reader occupies one complete channel, the
Teletype occu'pies the lower half of a channel and the status register occupies (nominally) one
channel. If no card reader, card punch, or line printer is connected to the system, the lower
half of the status register channel may be used for other purposes. Thus, in the basic machine,
the equivalent of five free channels is avaHable for additional Ie inputs~ Channel availability
of the Ie is specified as follows:

7-16

Level

Use
All 18. connections employed for RB

First 9 connections employed for status signals of
IORS instruction (lOT 0314)

3, 4, 5
6

All 18 connections open and assignable
First 10 connections are open and last 8 connections
are assigned to Teletype unit

First 12 connections are open and last 6 connections
are assi gned to the step counter (SC) of the Type 177
EAE option

Each leve I, or channel of the IC consists of one 2-input negative AND gate (two series-connected
transistors) for each of the 18 possible bits of an input word. The two inputs are usually supplied
by a data signal and an lOT pulse which is common to each bit of the input word. The output
from the seven channe!s for each bit are NOR combined to set the appropriate accumulator flipflop. One bit for each of the seven channels is provided by a Type R141 Diode Gate module;
the entire IC being constructed of 18 of these modu les •.
When designin-g a PDP-7 system, if is necessary to consider the number of collector channels
required by peripheral equipment. ,f more than seven channels are required, the IC will have
to be expcmded to accommodate the additional information. The expansion requires 18 Type

R141 Diode Gate modules, six Type W607 Pulse Amplifier modules and the appropriate mounting
panel and hardware. This expansion is connected into one full channel of the standard IC and
adds six additional information channels. Further expansion requires only additional R141 modules, each group of 18 adding an additional seven channels. Figure 7-1 represents the channel
assignments for the standard IC.

7-·17

NISI
CABLE
SLOTS

NI?I

NI91

I
I

I
I
INI6

CHANNEL

STANDARD

PAPER
TAPE
READER

N211

I NIB

I N20

I
I
IN22

N25 J

I
I N24

I
I N26

I
I N28

STATUS

TTY

OPTIONAL
STATUS

OPTIONS I

630

OPTIONS 2

Des

OPTIONS 3

Figure 7-1

N27 I

N23 I

177
EAE
MQ

550
DEC TAPE
DATA

347
SUBR .
DISPLAY
ASR

57A
MAG TAPE
CA

340 DISPLAY

x,v

DAC

PUNCHED
CARD
READER

A-D

550
DEC TAPE
STATUS

57A
MAG TAPE
STATUS

177
EAE
SC

343
SLAVE
DISPLAY
STATUS

138

Channel Assignments for the Information Collector

INFORMATION DISTRIBUTOR (10) (34)
The ID provides a series of buffered output channels for connecting peripheral dev'ices to the
()utput of the AC. These output channe Is are powered by 18 Type R650 Bus Driver modu les •••
c>ne for each bit of the AC. In the basic ID, each of these modu les has termina Is Hand S connected to ground. This causes an output ramp with a rise time of about 800 nsec. Without
these terminals grounded, the rise time is about 50 nsec. Each R650 output wi" deliver about
20 ma to ground. Extension of the ID increases the rise time of the output ramp, as a result of
increased loading. Consequently, the previously-mentioned ground connections should be removed when the ID is expanded in order to maintain a satisfactory rise time in the output. The
prewired connections to the interface cable receptacles of the ID are listed in Table 7-3.
Data contained in the AC is available as static levels to supply information to I/O devices.
These static levels can be strobed into an flo device register by lOT pulses from the ,device
selector. The static level of each ACB output signal is at - 3v when the bit contains a binary
() and at ground potential when that bit contains a binary 1. The ACB signals are applied to
f-he interface connections through Type R650 Bus Driver modules.

7-18

TABLE 7-3 PREWIRED INFORMATION DISTRIBUTOR CONNECTIONS
Wire

Signal Name

Color'

Connector
Terminal'

To Data Multiplexer (C10)
GND

W/BLK
W/BRN

N1D

W/RED
W/ORN

GND
N1E

T6
GNDo

W/YEL
W/GRN

DATA RQ
GND
DATA IN
GND
ADDR ACC
GND
DATA ACC
GND
DATA ROY

N1R
N1S

GND

W/YEL
W/GRN

N1N
N1P

W/RED
W/ORN

N1L
N1M

W/BLK
W/BRN

t\11J
"11 K

W/GRY
WHT

~nF
~nH

W/BLU
W/VIO

N1C

RQ SLOW CY

W/BLU

N1T
GND

W/V~O

N1U
N1V

W/GRY

GND
To API
-

W/BLK
W/BRN

GNO
F SET
FETCH

W/YEL
W/GRN

N2D

GND

W/RED
W/ORN

N2C

N2E
GNO

lAO

N2F
N2H

7--19

7-20

TABLE 7-3

PREWIRED INFORMATION DISTRIBUTOR CONNECTIONS (continued)

Wire
Color

Signal Name

Connector
Terminal

To DECtape (continued)
W/RED

GND

·W/ORN

N3R
N3S

W/YEL

GND

W/GRN

t\13T

W/BLU

GND

W/VIO

. N3U
N3V

W/GRY

GND
To API
---

W/BLK
W/BRN

GND
INS DBK (1)

N4D

W/RED
W/ORN

GND
T3

N4E

W/YEL
W/GRN

GND
T5
GND
T7
GND
INT REC
GND
INT REC NOT

W/RED
W/ORN

INT RQ

W/GRY

N4R
N4S

GND

MBO CRY (B)

W/BLU
W/VIO

N4N
N4P

GND

W/YEL
W/GRN

N4L
N4M

W/BLK
W/BRN

N4J
N4K

W/GRY
WHT

N4F
N4H

W/BLU
W/VIO

N4C

N4T
GND

PI1

[> MA
GND
7-21

N4U
N4V

TABLE 7-3 PREWIRED INFORMATION DISTRIBUTOR CONNECTIONS· (continued)
Wire
Color

Signal Name

Connector
Termi~al

e::: .

To 57A
W/BLK

GND

N5C

W/BRN

ERF-ERF ENB/V ED GE FLAG .

N5D

W/RED

GND

W/ORN

wco-weo ENB/H EDGE FLAG

N5E

W/YEL

GND

N5F

W/GRN

TCR

N5H

GND

W/BLU
W/VIO

T READY

N5K
GND

W/GRY
WHT

ADDR ACC
DATA RDY

W/ORN

DATA RQ

N5R
N5S

GND

W/YEL
W/GRN

N5N
N5P

GND

W/RED

N5l
N5M

GND

W/BLK
W/BRN

N5J

JOB DONE

N5T
GND

W/BLU
W/VIO

N5U
N5V

W/GRY

GND
To OS for 57A

W/BLK
W/BRN

GND
lOT 7001

W/RED
W/ORN

N6C
N6D

GND
lOT 7101

N6E

W/YEL

GND

N6F

W/GRN

lOT 7201/IOT 1001

N6H

7-22

TABLE 7-3 PREWIRED INFORMATION DtSTRIBUTOR CONNECTIONS (continued)
Wire
Color

Signal Name

Connector
Terminal

To DS for 57A (continued)
W/BLU

GND

N6J

W/VIO

lOT 7301/IOT 0501

N6K

W/GRY

GND

N6L

WHT

lOT 7304
GND

W/BLK
W/BRN

N6M

lOT 7401

·N6N
N6P

W/RED

GND

N6R

W/ORN

lOT 7404/IOT 0502

N6S

W/YEL

GND

---

W/GRN

REWIND

W/BLU
W/VIO

N6T
GND

MISS CHAR

W/GRY

N6U
N6V

GND
To 340

W/BLK
W/BRN

GND
BLOCK FLAG/STOP FLAG

W/RED
W/ORN

DATA FLAG/LP FLAG
GND
DATA RQ

W/BLU
W/VIO

DATA IN

W/BRN

N7F
N7J
N7K

GND
ADDR ACe

W/BLK

N7E

N7H
GND

W/GRY
WHT

N7D

GND

W/YEL
W/GRN

N7C

N7L
N7M

GND
BGN

N7N
N7P

7-23

TABLE 7-3

PREWIRED INFORMATION DISTRIBUTOR CONNECTIONS (continued)

Wire
Color

Signal Name

Connector
Terminal

lIS

To 340 (continued)
GND

W/RED
W/ORN

DATA ROY

N7S
GND

W/YEL
W/GRN

N7R

ERF-ERF ENB/V EDGE FLAG

N7T

W/BLU

GND

N7U

W/VIO

weo-weo ENB/H EDGE FLAG

N7V

W/GRY

GND

W/BLK

lOT 7301/IOT 0501

N8D

W/BRN

lOT 7404/IOT 0502

N8E

W/RED

lOT 7601/IOT 0601

N8H

W/ORN

GND

W/YEL

lOT 7501 {B)/IOT 0701

N8M

W/GRN

lOT 7502/IOT 0702

N8P

W/BLU

lOT 7201/IOT 1001

N8S

W/VIO

lOT 1002

N8T

W/GRY

lOT 7602/IOT 1004

NaV

WHT

GND

DEVICE SE LECTOR (DS) (36)
The DS generates lOT pulses that control information transfers between the processor and peripheral equipment. The DS consists of a series of Type B171 Diode Gate, Type Rll1 Diode Gate,
and Type W640 Pulse Amplifier modules. The DS is expandable, as are the Ie and 10. The lOT
pulse code assignment is given in Table 7-4.

7-24

TABLE 7-4
00 1 RT Clock
10 Symbol
2 Prog. Interrupt
Generator
Type 33
4 RT Clock

11 Analog-toDigital or
Digital-toAnalog
Converters

01 Standard
. Perforated
Tope Reader
and Control
Type 444B
02 Standard
Perforated
Tape Punch
Type 750

13 A-D-A
Stimulus

03 1 Keyboard
2 Keyboard
410RS

Flag

lOT PULSE CODE ASSIGNMENTS
60 Serial
Drum
Type 24

~O Auto Magnetic

51 Digitol-toAnalog
Converter
Type 180

61 Serial
Drum
Type 24

71 Tape Control
Type 57A

52D-to-A
Converter
Type 180

62 Serial
Drum
Type 24

72 Tape Control
Type 57A

53 D-to-A
Converter
Type 180

63 Automatic line
Printer
Type 64

73 Tope Control
Type 57A

20 Memory
Increment
Type 197

21 Relay Buffer
Type 140

22 Inter-Processor
Buffer
Type 195

23 Inter-Processor
Buffer
Type 195

33 1 33 KSR Skip
2 CI.ear All
F!ags
4 Open

Tope Control
Type 57A

f
04 Teleprinter

24 Incremental
Plotter
Control
Type 350

64 Card Punch
(IBM 523)
Control
Type 40

74 Tape Control
Type 57A

05 Displays
Types 34A,
30D, or 340

15 2nd DECtape
Control
Type 550

25 Plotter

55 Automatic
Priority
Interrupt
Type 172

65 Automatic
Line Printer
Type 647

75DECtape
Control
Type 550

06 Displays

16 2nd DECtape
Control
Type 550

26 Plotter

56 API
Type 172

66 Automatic
line Printer
Type 647

76DECtape
Control
Type 550

07 Display
and
light Pen

17 Boundary
Register
Type KA70A

27 Memory
Parity
Type 176

·37

67 Cord Reader
Type CR 01 B
or Type 421

77 Memory
Extension
Type 148

PWR CLR AND NEG PWR. CLR (20)
These signals are 400-nsec pulses produced by W640 Pulse Amplifiers at location 2C28. These
pu~ses are made available to I/O equipment through connections made at the device selector of

the interface. External equipment can make use of these pulses for clearing operations during

the power turnon period. The pulses are generated during th" l-sec interval after the POWER
swHch is set to on.

BGN(B) (20)
The buffered BGN (Begin) signal is supplied to extern~1 equipment through a connection in the
device selector of the interface. This signal is a 400-nsec, - 3v pulse generated by a W640
Pulse Amplifier at location2C28 during timing pulse SP1 ·CONTINUE NOT. The signal is used
in I/O equipment to clear registers and reset control flip-flops to initial conditions when the
START key on the operator console is used.

RUN STOP (20)
The RUN ~TOP signal is supplied to external equipment through a cont')ection in the device
selector of the interface. This signal is a - 3v level used to indicate to I/O devices that the
STOP key on the operator console has been operated to ha It the program.

RUN(l) (23)
The 1 output of the RUN flip-flop is supplied to external equipment through the interface circuits.
This signal is at - 3v when the computer is performing instructions and is at ground potential when
the program is halted. Magnetic tape and DECtape equipment make use of this signal to stop
transport motion when the PDP-7 halts, and thus prevents the tape from runninOg off. the end of
the reel.'

MB (36)
Bits 6-11 of an lOT instruction held in the MB are used to select the I/O device to be serviced
in a programmed data transfer. Complementary output si gna Is from MB flip-flops 6-11 supply
the input to the device selector which gener~tes the appropriate lOT pulses according to instruction bits contained in theMB.

7-26

lOT (36)
lOT putses are generated in the device selector as a function of the contents of MB bits 6-11.
These pulses are used in I/O devices for various functions such as: clearing flags, gating data,
setting operation modes, etc. The last digit of any lOT pulse designation corresponds to the
number of the lOP pulse which causes generation of that lOT pulse (e.g~, combination of a
device code XX with an lOP 4 pulse produces an lOT XX04 pulse).

ACB (34)
Informatiol1 contained in the AC which is to be transfe.rred to external equipment under program
control 10 is buffered in the information distributor by 18 Type R650, Bus Drivers. Each of these
bus driver circuits produces a positive ACB level when the associated AC bit is a 1.

REQUEST SLOW CYCLE (36)
The REQUEST SLOW CYCLE ground level signal is supplied by the device selector to request
that all lOT instructions that address a specific device be a computer slow cycle. This signal
is addedar the time a slow I/O device is added to the computer systerr.. The lOT instructions
for this device are decoded in a Type B171 Diode Gate module. The ground level output at
terminal 0 when the device is selected, is used to request the slow cycle by connection to the
input of another Type B171 module. This latter module is used as a ground level NOR gate for
all such request signals, and negative output on terminal 0 of this module is applied to the
processor timing circuits (zone 06 of drawing 22). The Type B171 modu Ie which receives the
SLOW CYCLE REQUEST signals from various devices is located at B26 of the OS. Locations
C26 and C27 are available for expansion of this facility (to OR in the slow cycle requests) if

more than 12 I/O devices requiring slow cyc Ie operation are connected to the computer.

PROGRAM I NTERRUPT REO UEST (32)
The flag of an external device can be used to request a program interrupt. At the time the device requires servicing, the condition of the flag, connected to the Type R141 module in location L14 c)rM 14 of the processor I can be used to request a program break. (The flag of the
external device should also be connected to the I/O skip facility so that the lOT 01 pulse

7-27

can be sensed by the interrupt program to determine the !=ievice requesting the program break.)
The PROGRAM INTERRUPT signal level is the NOR of requests from many devices that require
programmed attention. ~t the time the program break is entered, a program subroutine is initiated to determine which device, of many, is to be serviced; then to perform the appropriate
service operation (usually by supplying or receiving data under program .control). The flags
shc)wn connected to the R141 module in location M14 on drawing 32 are only suggested, and are
changed if these devices (the display, DECtape, etc.) are not included in the system.

DATA RQ (24)
A high-speed I/O device may originate a data break request by placing a - 3v DATA RQ level
on the r"equest line connecting the device to the computer. In the interrupt control, the DATA
RQ level is synchronized with timing pulse T5 of the current computer cycle, and sets the
DATA SYNC flip-flop to 1. This causes a BK RQ level to be transmitted to the major state
generator. Completion of the current instruction permits the maior state generator to enter a
break state, producing a (8) level. This (B) level is combined with the DATA SYNC level to
produce a negative DATA·B level.

An external device connected to the data break facilities of the computer must supp,ly a DATA
RQ level, a 15-bit core memory address for the transfer I a signal indicating the direction of
the transfer as into or out of the computer core memory, and input or output connections' to the
MB for 18 data bits. The DATA RQ leve I is sent to the computer at the time the data is ready
for a transfer into the PDP-7 or when the data register in the external device is ready to receive
information from the PDP-7. This request level must be - 3v for assertion, meaning a request
for a data break, and drives a transistor base requiring 2 ma of input current.

DA (Data Address) (29)
The data address given by an' I/O device is transferred to the MA by connections made at the
DA level input of a NOR gate in each module of the MA. Transfer of the address is accomplished
during a DATA ADDR ACe pu Ise of a break cyc Ie.

7-28

DATA ADDR Ace (32)
At time T1 of the break cycle, the DATA·B level is NAND combined with timing pulse T1 to
produce a DATA ADDR ACC pulse (called DATA ADDR

~ MA pulse in early systems).

This pulse causes the memory address contained in the address register of the I/O device to be
transferred into the processor MA. This pulse is also transmitted to the external device as an
acknowledgment that its address has been accepted.

DATA IN (Transfer Direction) (32)
This signal, specifying the direction of data transfer for a data break, is received by the computer from the requesting device. Transfer direction is referenced to the computer core memory,
not to the device. This signal is a - 3v level to determine the transfer direction as in, or is
ground to determine an out transfer.

01 (Data Information) (30)

The 18 01 lines establish the data to be transferred into the MB from an external derice during
C" data break in which

the direction of transfer is into the PDP-7. The 01 signal levels must be

presented to 2-input negative NAND diode gates at the binary 1 input of the MB and are transferred into the MB by the DATA ACC pulse. This information in the MB is then written into
core memory during a normal write operation. The 01 signals must be -3v to designate·a binary 1
or must be ground potential to specify a binary 0, and must be available at the time the break
request is made.

DATA ACC (32)
buring a.data break cycle when the external device is requesting a transfer into the PDP-7,
time T3 and the DATA· B level produce a negative DATA ACe (called PATA INFO

~ MB

in early systems) pulse. This pulse strobes the data input gates of the MB to transfer a data word
from an external device into the MB. This pulse is also provided as an output for device syn- .
chronization. Starting at time T5, the information in the MB is written into core memory by the
norma I write operati on •

7-29

MBB (28 and 36)
Data break transfer from core memory to an I/O device is made via the MB; whose output is
buffered for this purpose by 18 Type R684 Bus Drivers. Each bus driver is capable of driving
a40-ma load. Gating of the information is accomplished at the receiving end by the DATA

RDY pulse. The MBB output terminals are located in the device selector.
DATA ROY (32)
During time T3 of a data break cycle in which the transfer dir"ection is out, the DATA· B level
and time 3 causes a negafive DATA RDY (in early systems called MB INFO

OUT)

plJlse to be generated. This pulse may be used to strobe the MBB information into the external
dE~vice buffei; for this purpose the signal may be delayed within the device to strobe the data

into the buffer after an appropriate setup time. Note that the transfer must be made prior to
time T2 of the next computer cyc Ie.

7-30

CHAPTER 8
INSTALLATION

SITE PREPARATION

Space Considerations
Space must be provided at the installation site to accomodate the PDP-7 and all peripheral
equipment and· to allow freedom of access to all doors and panels for maintenance.

In larger

systems, ·consideration should be given to human engineering factors which minimize the effort
required by an operator seated at the operator console to obtain visual or physical access to
all controls, indicators, input bins, and output hoppers of all equipment in the system. A
basic 3-cabinet PDP-7 requires a floor space 68-15/16 inches wide and 76-5/32 inches deep
with a minimum service clearance of 14-7/8 inches at the back. A 4-cabinet PDP-7 requires
a space 85-3/32 inches wide, and a 5-cabinet PDP-7 requires a space 101-1/4 inches wide t
both with the same depth and service clearance as that given above. An additional width of
19-3/4 inches is required for each additional computer cabinet which is bolted to the main
frame or console cabinet. Figure 8-1 indicates the space requirements, cable access, and floor
. loading for a 3-cabinet PDP-7. This diagram can also be used in planning the installation of
all I/O equipment housed in standard DEC computer cabinets if it is borne in mind that other
cabinets do not have the table at the front of the operator console and that 1-1/4-inch end
panels must be added to the side of each mul ti pie-cabinet configuration constructed of 19-3/4
inch cabinets bolted together. The standard Teletype Keyboard Send Receive set requires a
floor space approximately 18-5/8 inches wide by 18-1/2 inches deep. Signal cable length
restricts the location of the Teletype to within 18 inches of the side of the computer.

Environmental Cond itions
No special environmental condition need be met for proper operation of the PDP-7. Ambient
temperature at the insta Ilation 5 i te can vary between 50 and 122 degrees Fahrenhe it (between
10 and 50 degrees centigrade) with no advers~ effect on computer operation. However, to
extend the IHe expectancy of the system, it is recommended that the ambient temperature at

8-1

CAIIl.E ACCESS
(TYPICAL FOR 3 CA8INETS)
CASTER S.....AI. RADIUS

SWIHGN'l DOOM (to)

LOAD POINT

17t"

50a"

76f2

27~-l

29'

REMOVEA81.E
END PANEL

---,

IL. ____ .JI

SCREEN (TYPICAL
FOR 3 CA8INETS)

"3'2
3"

84'

---------- - - -

.--------68~·------------------.--------~
FLOOR PLAN

"t.·~---l

"'r~---- 27 ik·

n·r

ic=Jr27;i"

\'..J/

\:::y
SIDE VIEW

Figure 8-1

Installation Outl ine Drawing

8-2

the installcltion site be maintained between 70 and 85 degrees Fahrenheit (between 21 and 30
degrees centigrade). During shipping or storing of the system, the ambient temperature may be
permitted t'o vary between 32 and 122 degrees Fahrenheit (between 0 and 50 degr;ees centigrade).
Although all exposed surfaces of all DEC cabinets and hardware are treated to prevent corrosion,
."

_",,1;.«"'

...

exposure of systems to extreme humidity for long periods of time should be avoided to prevent
rusting.

Power Requirements
A source of 115-volt (± 17 volts), 60-cycle (±O.5 cycle), single-phase power capableof supplying at least 30 amperes must be provided to operate a standard PDP-7. To allow connection
to the power cable of the computer, th is source should be provided with a Hubbel Twistlockflush
receptacle (or its equivalent) rated at 30 amperes at 250 volts. Power dissipation of a standard
PDP-7 is approximately 2200 watts, and the heat dissipation is approximately 6600 Btu/hour.
Upon special request, a PDP-7 can be constructed to operate from a 220-volt (±33 vol ts),
60-cycle (±0.5 cycle), single-phase power source or from a 100-volt (± 15 volts), 50-cycle
(±O.5 cycle), single-phase power source.

PREPARATION FOR SHIPMENT
The following shipping practices are followed by the factory in preparing a system for del ivery
to a customer and should be adhered to by the customer in any future shipment or relocation.
Usually a shipment consists of at least three parcels containing the computer main frame, the
Teletype, and a carton containing related documentation, cables, and other miscellaneous
material. Shipping weight of a standard 3-cabinet main frame is approximately 1150 pounds.
Shipping weight of the Teletype equipment is approximately 60 pounds, and the miscellaneous
equipment carton weighs up to 100 pounds.
The cabinet of a PDP-7 syste'm is prepared for shipment as follows:
a. The cabinet is placed upon a sturdy wooden pallet and held in place by,
passing a bolt through the center of the tubular frame on each side of the
bottom of the cabinet .. This bolt is secured by a nut on the underside of the
pallet.

b. The console table is removed fro,m the cabinet by removing the two
mounting pins which attach the table extension arms to the side of the cabinet at the back; then the pins are returned to their position in the cabinet.
c. Modules are taped within the mounting panels, and the power cables
are coiled and toped to the floor of the cabinet. The plenum door is then
bo Ited shut.
d. The console table is cushioned by pocking material and attached to the
outside of the cabinet by metal straps. A wooden protector plate, wrapped
in pOcking material, is strapped to the front of the cabinet to cover the
operator console.
e. A ful f-height plastic bag is placed over the entire cabinet.

f. A wooden cover plate with appropriate packing material is placed on
top of the cabinet, and metal shipping straps are run vertically around the
cabinet, over Tne cover plate, and under the pc; let. 'lVhen preparing the
cabinet for overseas shipment, boards are nailed between the cover plate

and the pallet to form a shipping crate which totally encloses the cabinet.

Teletype Shipping Procedure
The Teletype is packaged in the original manufacturer's shipping carton and is prepared for
shipment to the customer as follows:
a. The Teletype is disconnected from the computer cabinet.
b. The back panel of the stand is removed, all cables are disconnected,
and the power pack 'is removed.
c. The Teletype console is removed from the stand and attached to a
wooden pallet by four shipping screws. The pallet is then placed in the
shipping carton and corrugated packing material is placed on all sides of
the consol e.

8-4

d. The stand is placed in the shipping carton above the Teletype console.
The power pack is individually wrapped in shipping material and pocked
within the stand; then the bock of the stand is attached by means of the two
normal mounting screws.
e. Additional pocking material is added and the carton is sealed.

INSTALLATION PROCEDURE
No special tools or equipment are required for installation of a PDP-7 system. A fork-I ift truck
or other pallet-handling equipment and normal hand tOools, including shears to cut the shipping
straps, 'shou Id be' avo il abl e for rece iving and install ing the equi pment. To insta II the computer:
1. Place the computer cabinet package within the installation site near the
final location. Cut the shipping straps and remove all packing material.
Remove the console table from the side of the cabinet, and remove the prot'ector plate from the front of the cabinet. Open the rear doors, remove the
rhipping bolts which hold the plenum doors closed, and open the plenum doors.
Remove the bol t which holds each side of the cabinet to the pellet. 51 ide~ the
cabinet off of the pallet, using a ramp (approximately 4-3/4 inches high)
from the floor to the top of the pallet. Move the cabinet to its final locaHon within the installation site (this location must be within 18 feet of the
primary power connector within the site).
2. Remove the tape which holds the modules in place within the mounting
panels and the tape which holds the power cables to the floor of the cabinet.
Assure that all modules are securely mounted in their connectors.
3. Remove the pins from the table mounting guide at each side of the back
of the cabinet; install the console table by passing the extension arms through
the open ings in the front of the cabinet and into the gu ides at the back of the
cabinet; then replace the pins by passing them through the extension arms and
guides.-

8-5

4. Open the Teletype carton and remove the pocking material. Remove
and unwrap the power pack. Remove the stand from the sh ipping carton.
Remove the Teletype console from the carton, holding it by means of the
wooden pallet attached to the bottom. Remove the Teletype console from
the pal let and mount it on the stand or console tab! g, as desired. Snap the
power pack in place within the top front of the stand, and connect the
Teletype console to the power pack (a 6-lead cable' attached at the console
is connected to the power pack by means of a wh ite plastic Molex 1375 female connector which mates with a male output plug on the power pack).
Pass the 3-wire power cable and the 7-conductor signal cable (which is
terminated in a female Amphenol 143-022-04 connector) through the opening at the lower left-hand corner of the Teletype stand; then replace the
back cover of the stand by means of the two mounting screws.
5. Adjust the stabilizing feet on the four corners of the computer cabinet
and on any I/O equipment. Adjust the leveling devices on the feet of the
Teletype stand.
6. Remove the fan and fil ter assembl ies from the bottom of the computer
cabinet by disconnecting the captive screw at each side of the filter housing.

51 ide the rear portion of the cable port toward the rear door. Pass tQe lorger
diameter computer power cable out through the cable port, pass the Teletype
signal and power cables into the cabinet through the cable port I and pass
any other I/O equipment signal cables through the cable port; then replace
the back half of the cable port and the fan and filter assembly.

7. Connect the 3-prong male connector of the Teletype power cable to the
female connector at the end of the smaller diameter power cable within the
computer cabinet. Connect the male connector of the Teletype signal cable
to the mating connector at location R3B on the rear door of bay 2. Be sure
that the computer lock switch is turned fully counterclockwise and that the

8-6

POWER switch is set to the down position; then connect the computer power
cable to the primary power source.
8. Set the POWER switch to the up position and note that the POWER indicator lights. Computer logic power should go on immediately, and memory power after approximately 5 seconds.

9. Install the printer paper roll in the Teletype printer/keyboard, insert a
blank tape in the tape punch.

10. Set the Teletype LINE/OFF/LOCAL switch to LINE and strike several
keys, noting whether or not the printer operates. Make the same check
with the switch in the LOCAL position. After completion of the checks, set
the LINE/OFF/LOCAL switch to OFF.

11. Set the PUNCH feed switch on the operator console to the up position.
Observe that the punch motor runs, then return PUNCH feed switch to the
down position.

12. Press and hold the punch FEED pushbutton • The motor should start
the instant the pushbutton is pressed. After one second, the punch should
punch feed-holes only in the tape and should continue punching feed-holes
as long as the pushbutton is pressed. When the pushbutton is released,
punching and tape movement should stop, but the punch motor should conf'inue to run for approximately 5 seconds.
13. Load the RIM loader program by placing the RIM loader tape in the
reader as described in Chapter 9 of this manual, setting the READY/LOAD
switch to the READY position, and then pressing the READ-I N key. After
completion of the loading operation, check the contents of the appropriate
memory cell for accuracy. The procedure for checking the contents of a
cell is described in Chapter 9, and Table 9-8 indicates the addresses used
and the contents of each address.

8-7

14. Set the POVv'E.R switch to the down position and observe that the computer cycles down. Memory power should go off immediately I and computer
logic power after approximately 5 seconds.
This completes ,the installation of a standard PDP-7 system. Before co~mencing normal use I
verify the operating capabil ity of the system. Perform the Power Supply Checks as described
under Preventive Maintenance in Chapter 10 of this manual and run all Maindec dianostic
programs supplied with the PDP-7 system as described in the associated documents.

CAUTION
Whenever the PDP-7" system is operating I make sure that the area
is clear atop of the cabinet. The vents located at this point are
vital to the proper cooling of the computer. Never use this space
as a storage shelf.

8-8

CHAPTER

OPERATION

CONTROLS AND INDICATORS
Manual control of the PDP-7 and its peripheral equipment is effected by controls, switches,
and keys ,located on the operator console and the individual peripheral devices. Visual indication of computer status and content of registers and control fl ip-flops is given on the operator
console where this information relates to the central processor.

Similar information relating to

the memory and peripheral equipment is given on a separate indicator panel.

Operator Console Controls and Ind icators
The controls and indicators of the operator console are shown i.n Figure 9-1.

MEMORy BUffER

LINK PIE RUN

FErCH

()'Ef(q EXECUTE BREAK

INSTRUCTION

cee c c c c COOn

ODIJDDaCODcr:"~tlQ:aao:a
ACCUMULATOR

PROGRA!II COUNTER

ctl.fJCIJCOOOt:!QDIJCDOOO

c:arlOOOOnDCTIaOPD

MULTIPLIER Q00TlEN1

MEMORY AOD'lE55

ACCUMULATOR

TRAP

EXTEND

SINGLE STEP

[i'~

E;YrJ ErCI G:.cI ~

,~;_c

Sf AlIT

STOP

CONTINUE

[x,\M''il

DE POSIT

RUID

r~J

'!J.,t
~

&r~~~

~.;~;,/.

~,;X
~)

EXoHWIE

D(POSIT

t~dj

:;;},~:.",

Figure 9-1

.~.:

I I

.j. . . . . . . . . . . . . ;"

(~) ..
,",

;."'-.:..

. . . 0·····'.·········(
';~ j'"

Operator Console

. 9-1

SINGLE IN Sf

POWER

PUNCH FEED

•.• ~" ij;.' '..

SPEED

REPEAT

Indicators
The contents of the various registers, the current major state of the computer, and the states of
various flip-flops are shown by the indicators on the operator console. Lighted indicator lamps
d,enote the presence of binary 1's in the associated register bits and flip-flops. Table 9-1 lists
the indicators mounted 0:1 the operator console and explains their functions.

TABLE 9-1

OPERATOR CONSOLE INDICATORS

Indicator

Function

MEMORY BUFFER
Indicators

Indicate the contents of the MB. Usually
the contents of the MBdenote the word
read or wr itten at the core memory address
held in the MA.

ACCUMULATOR
Indicators

Indicate the contents of the AC. The contents of the AC are the result of an arithmetic
operation, a control word for output to an
external control I data read in from some
peripheral device, or data for transfer out to
a peripheral device.

MULTIPLIER QUOTIENT
Indicators

Indicate the contenh of the MQ. The MQ
holds the multiplier at the beginning of a
multipl icotion operation and the least significant hal f of the product at the concl usion. It also holds the least significant
half of the dividend at the start of a divide
operation and at the end holds the quotient.

PROGRAM COUNTER
Indicators

Indicate the contents of the PC. The PC
holds the address in core memory from
which the next instruct ion is to be taken.

MEMORY ADDRESS
Indicators

Indicate the contents of the MA. The
contents of the MA denote the core memory address of the word currently or previously read or written. The address of
each new word is set into the MA during
time state T1 of the computer cycle.

9-2

TABLE 9-1

OPERATOR CONSOLE INDICATORS (cont)

Indicator

Function

FETCH, EXECUTE, DEFER
BREAK Indicators

Give the major operating state of the
computer·during the next memory cycle.

INSTRUCTION
Indicators

Give the current operating instruction
of the computer in binary code. This
may be 1 of 16 possible combinations.

LINK
Indicator

Indicates the status of the I ink.

The

I ink is used as an extension of the AC,
as on overflow register in 1 's complement arithmetic operations, and as a
carry register in 2's complement arithmetic operations.

RUN
Indicator

Indicates that the RUN fl ip-flop is set
to 1. When this indicator is lit, the
timing circuits are enabled, and the
computer is performing an instruction.

PIE
Indicator

Indicates Program Interrupt Enabled.
Th is occurs whenever the regu lar program is hal ted for some reason, such as
a program break to transfer information
between the computer and the I/O
devices.

Switch Registers
The switch registers provide a means of manucJlly inserting data and addresses into the processor.
On each switch, the upper position selects a binary 1 for the associated bit and the lower position selects a binary O. Table 9-2 lists the switch registers and explains their functions.

9-3

TABLE 9-2

OPERATOR CONSOLE SWITCH REGISTERS

Control

Function

Ace UMULATOR
Switches

Provide a means of manually setting
information through the AC into core
memory. The 18-bit switch register
also functions as a set of sense switches
which may be sensed by the program.

ADDRESS

Provide a means of manually specifying
an address of a given core memory cell.
Th is may be done ei ther to establ ish the
starting point of a program or as part of
an examine or deposit operation. The
upper position indicates binary 1, the
lower indicates

S~\/itches

Switch Controls and Indicators
Switch controls and indicators, or pushbutton controls are used to initiate certain modes of
()peration in the computer.

In these controls, a switch position does not denoTe a bit content

nnd the indicator is not necessarily lighted by the associated switch. Table 9-3 lists the
switch controls and indicators and explains their functions.

TABLE 9-3

OPERATOR CONSOLE SWITCH CONTROLS AND INDICATORS

Control or Indicator

Function

=:===================================================================
POWER
Switch and Ind icator

The switch controls primary power to
the computer and all external devices
attached to it. The on positlon is up.
The indicator lights when primary
power is turned on.

REPEAT
Switch and Indicator

The switch causes the operation initiated by pressing the CONTINUE,
DEPOSIT NEXT, or EXAMINE NEXT
key to be repeated as long as the key
is held in the on (up) position. This
switch triggers a one-shot with an adiustable delay. The.signal fro'm this

9-4

TABLE 9-3

OPERATOR CONSOLE SWITCH CONTROLS AND INDICATORS (cont)

Control or Indicator

Function

REPEAT
Switch and Ind icator
(cont)

one-shot restarts the cycle each time it
has reached completion.. The indicator
I ights when ,he mode is enabled.

SPEED
Controls

Vary the repeat interval from 40 microseconds to 7 seconds. The Ieft-hand
knob is a 5-position coarse control; the
right-hand knob is a continuously variable fine control. Slowest speed is
obtained with both knobs rotated to the
extreme counterc lockwise position.

SINGLE STEP
Switch and Indicator

The switch causes the computer to stop
at the end of each memory cycle. This
switch generates a RUN STOP signal
that resets the RUN fl ip-flop to
Repeated operation of the CONTINUE key
momentarily overrides the RUN STOP
signal so that the program is advanced
one step at a time. The indicator I jghts
when the mode is enabled.

SINGLE INST
Switch and Indicator

The switch 1 when in the up position,
causes the computer to stop at the end
of each instruction. This switch, in
combination with an F Set levF;l, generates a RUN STOP signal that resets
the RUN fl ip-flop and halts the computer at the end of the current memory
cycle. If the CONTINUE key is depressed wh i Ie this swi tch is on, the
RUN STOP signal is temporarily overridden; and the program is run one
instruction at a time. Vv'hen both
switches are on, SINGLE STEP takes
precedence over SINGLE INSTRUCTION. The Indicator Iights when the
mode is enabled.

9-5

TABLE 9-3

OPERATOR CONSOLE SWITCH CONTROLS ANq INDICATORS (cont)

Control or Indicator

Function

PUNCH FEED
Switch

Controls perforated tape punch power.
When this switch is in the down position, punch power is under program
control. \Iv'hen th is swi tch is in the up
position, punch power is on (independent of the program).

PUNCH FEED
Pushbutton

Causes tape to be punched with feed
holes only. Approximately 2 feet of
such "Ieader" should be punched before the punch is placed under program
control.

EXTEND
Switch and Indicator

The switch enables the extend mode of
the optional Type 148 Memory Extension Control to be used with all console keys and switches performing memory reference functions. The ind i cator
I ights when the mode is enabled.

TRAP
Switch and Ind'icator

The switch permits the trap mode to be
engaged by an ITON instruction in the
program. When in use, the trap prevents the computer from carrying out
harmful or undesirable instructions
which might be given when the computer is operating in a time-shared
mode. When such on illegal instruction appears, it sets a trap flag; and a
program break is initiated. The indicator lights when the mode is ena~led.

The following manual keys are used to initiate basic general operations of the processor.
(Note: The starting cycle is initiated by activating any manual key.) Table 9-4 lists the
keys and the ir functions.

9-6

TABLE 9-4

OPERATOR CONSOLE MANUAL KEYS
Function

Control or Indicator
START

Key

STOP

Key

When depressed, initially clears the
RUN fl ip-flop, delays ~ 0 microseconds to allow all operations both internal and external to cease, then sets
the computer to the Fetch State, loads
the program counter with the contents of
the 15 bit address switch register, sets
the RUN fl ip-flop and starts the computer time chain. Thus operation of the
progr'am is started, at the address specified by the contents of the ADDRESS
switches (AS).
Stops the computer program when depressed by clearing the run fI ip-flop
during time five (T5) of the main computer cycl e •

CONTINUE
Key

Causes the computer to resume operation, at the point at which it was
stopped. Beside the normal off (leV'el)
and (down) positions, this key also has
a latched on position, obtained by
I ifting the key.

EXAMINE/EXAMINE NEXT

When the EXAMINE/EXAMINE NEXT
control is raised the EXAM I NE function
is in itiated. The effect of th is key is to
place the contents of the core memory
cell, specified by the ADDRESS switches,
into the AC and MB. This operation is
performed by clearing the PC and forcing the computer into the execute cycle
of an LAC instruction. At the completion of the operation, the MA contains
the contents of the ADDRESS switches,
and the PC contains the address of the
next consecutive memory cell.

Key

Vvhen the EXAMINE/EXAMINE NEXT
control is pressed the EXAMINE NEXT
function is initiated. This functIon is

9-7

TABLE 9-4

OPERATOR CONSOLE MANUAL KEYS (cont)

Control or Indicator

Function

--:============================================================
EXAMINE/EXAMINE NEXT
Key (cont)

similar to that of the EXAMINE function, except that the PC is not cl eared
but is used to load the MA directly
rather than from contents of the ADDRESS switches. At the completion 6f
the operation, the contents of the various registers is the same as for an examine operation.

DEPOSIT/DEPOSiT NEXT
Key

When the DEPOSIT/DEPOSIT NEXT
control is raised the DEPOSIT function
is initiated. This key places the contents of the ACCUMULATOR switches
into the core memory cell whose address
is specified by the ADDRESS switches.
This operation is performed by forcing
the computer into the execute cycle of a
DAC instruction. At the completion of
the operation, the contents of the ACCUIv\ULATOR switches is in the AC end
MB, and the MA contains the contents
of the ADDRESS switches. The PC contains the address of the next consecutive
memory cell.
When the DEPOSIT/DEPOSIT NEXT control is pressed, the DEPOSIT NEXT function is in itiated. Th is function is sim iI or
to that of the DEPOSIT function, except
that it places the contents of the ACCUMULATOR switches into the core memory
cell whose address is spec ified by the
contents of the PC. The contents of the
PC are then incremented by 1. At the
compl etion of the operation, the contents
of the various registers are the same as for
a deposit operation.

READ-IN
Key

Is used to read paper tape punched in the
binary mode into a block of core memory.
The first address of the memory block must
be spec ified by the contents of the ADDRESS
switches. When the key is depressed the

9-8

TABLE 9-4

OPERATOR CONSOLE MANUAL KEYS (cont)

Control or Indicators

Function

READ IN
Key (cont)

address specified in the ADDRESS switches
is placed in the PC and MB. The execute state is ~et in the major states and
a DAC instruction is set in the IR. The
read paper tope fl ip-flop (RPT) 1s set I
the reader is selected in the binary mode,
and the first three I ines are read from
tape. The reader then hal ts. The condition that the KEY LEVEL is present is
required to establIsh initial conditions.
This level must be absent in order that
information may be placed in consecutive core locations. Vv'hen the key is
released the remainder of the tape will
be read. The readin mode may be terminated by having a hole 7 punched in
the last I ine on the tape, or by pressing
the STOP or EXAMINE ke·y.

LOCK
Switch

Prevents accidental disturbance of a
program in progress. With this switch
turned clockwise, all console switches
and keys, except the ACCUMULATOR
and ADDRESS switches, are disabled.
In the counterclockwise positon, all
controls operate normally.

Teletype Controls
The Teletype is shown in Figure 9-2. Table 9-5 lists the Teletype controls and explains their
functions.

9-9

(

":
:;-

-T.i.''--.- J, .:..):. '.4.'- V. 0. (;1 0. eJ. 0 .. U . . (1 U. 0----I....i ,..,/ {...;; ~J .~..; ~J ~.) V ~j ':.J '.::i
I \,,),,{.) Uvt) U tJ\.},\~).~.:.Juu "x,) t j I

dol

~'
). '. J

~ ~' ~.'

~i :'....
...ta
'I.~# 't,J. t •. -.!"'!
'~
}••'....
'1........
.. ..~f"~~'"-..."" . . ; .".,)'·,:'".t
.i ••

_,_____ :::---=-_::::_~--' .____--"

.-------."'"-"..-.'. . . .

TABLE 9-5

\
\
:I
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~

~~ 1I
\I

,I
t

-.-~

"'~I_"
Figure 9-2

Teletype Console

TELETYPE CONSOLE CONTROLS

Control

Function

KEYBOARD

Provides a means of supplying input
data lin the form of typed characters,
to the computer and/or the page
printer, depending on the setting of
the LINE/OFF/LOCAL swi tch •.

LINE/OFF/LOCAL
Switch

Controls the appl ication of primary
power to the Teletype and controls
data connec tion between the Tel etype
and the central processor. In the
LINE position, the Teletype is energized and connected as an I/O device
of the computer. In the OFF position,
the Tel etype is de-energ ized. In the
LOCAL position, the Teletype is energized for off-I ine operations; and the
signal connections to the processor are
broken. Both I ine and local use of the
Teletype requires thpt the computer be
energized through the POWER switch.

9-10

Tape Reader Controls
The tape reader is shown in Figure 9-3. Table 9-6 I ists the tape reader controls and explains
their functions.

Figure 9-3

TABLE 9-6

Perforated Tape Reader

TAPE READER CONTROLS

Control

Function

POWER ON
Switch

Applies power to the power supply,
capstan drive motor, and fan motor.

READY/LOAD Switch
and
Tape Vv'idth Selector
Knob

In its clockwise position, the READY/
LOAD switch de-energizes the brake
and pinch roller to allow tape insertion.
The knob may be moved in or out to
handle different tope levels.

9-11

Indicator Panel
The indicator panel is shown on Figure 9-4.
theIr functions.

Table 9-7 I ists the indicator panel indicators and

FlAG

T T BUFFER

C CDCc~:a

ICC a"cEl
,

RUN

BINARY

FLAG

C C C

Figure 9-4

TABLE 9-7

BeY

C!JdtiC~c

omcctJccc

P T R BU""£'l

clI!III!"!:r1C~'
;'-.,. -c~c:~a""C~,CD"·
o

Indicator Panel

INDICATOR PANEL INDICATORS

Indicator

Function

BREAK STARTED
Indicators

Indicate which channels of the Automatlc Priority Interrupt option are requesting an interrupt.

CHANNEL ON
Indicators

Indicate which channels of the Automatic Priority Interrupt option have
been enabled by the program.

READ
Indicators

Indicate the status of the READ 1 and
READ 2 flip-flops. Since a read operation occurs during each cycle I these
should appear to glow faintly whenever
the computer is cye! ing, but should go
out when the computer is stopped.

9-12

~'j

TABLE 9-7

INDICATOR PANEL INDICATORS (cont)

Indicator

INH
Indicator

Function
Indicates the status of the 1NH (inhibit)
flip-flop in the memory control. Since
inhibit current flows during each cycle,
this indicator should appear to glow
faintly whenever the computer is cycling,
but should go out when the computer is
stopped •

WRITE
Indicators

hidicates the status of the VvR ITE 1 and
WRITE 2 flip-flops. Since a write operation occurs during each cycle, these
indicators should appear to glow faintly
whenever the computer is cyc ling, but
should go out when the computer is
stopped.

fLAG
'Indicator
(TT BUFFER)

Indicates the status of the Teletype
KEYBOARD FLAG f1 ip-flop. When this
indicator is lit I the T~let)'re LUI is ready
for a data transfer.

TT BUFFER
Indicators

Indicate the contents of each of the eight
bits of the Teletype buffer (LUI).

ACT

Indicates the status of the PUN ACTIVE
fl ip-flop. Th is ind i catnr is lit rluring
tape punch ing operations.

Indicator

BINARY
Indicator

Indicates the status of the PUN MODE
flip-flop in the punch buffer. VI/hen this
indicator is lit I tape is being punched in
the binary mode.

FLAG

Indicates the status of the PUN FLAG
flip-flop. VVhen this indicator is lit"
the punch buffer is ready for a data
transfer.

Indicator
(PTP BUFFER)

9-13

TABLE 9-7

INDICATO'R PANEL INDICATORS (cont)

Indicator

Function

PTP BUFFER
Indicators

Indicate the contents of the punch control buffer. When tape is being punched
in binary mode, only the six least sign ificant ind icators are read.

. RUN
Indicator

Indicates the status of the RD RUN
flip-flop. When this indicator is lit,
the reader is reading tape.

BINARY
Indicator

Indicates the status of the RD MODE
flip-flop. When this indicator is 1ft,
the reader is reading tape in the binary
mode.

FLAG
Indicator
(PTR BUFFE R)

Indicates the status of the RD FLAG
fl ip-flop. When this indicator is lit,
the tape reader is ready for a data
transfer.

PTR BUFFER
Indicators

Indicates the contents of the reader buffer. When the reader is operating in
binary mode, the indicators are read as
a 3-stage, 6-bit shift register.

OPERATING PROCEDURES
Many means are available for loading and unloading PDP-7 information. The means used are,
of course, dependent upon the form of the information, ti me Iimitations, and the peripheral
equipment r:onnected to the computer. The following. procedures are basic to any use of the
PDP-7, and although they may be used infrequently as the programming and use of the computer
become more sophisticated, they are va luable in preparing the initial programs and learning
the function of machine input and output transfers •

. 9-14

Manual Data Storage and Modification
Programs and data can be stored or modified manually by means of the facil ities on the operator
console. Chief use of manual data storage is fTlClde to load the readinmode loader program into
the computer core memory. The readin mode (RIM) loader is a program used to automatically
load programs into PDP-7 from perforated tope in RIM format. This program and the RIM tape
format are described in the PDP-7 Users Handbook F-75 and. in Digital Program Library descriptions. The RIM program is I isted in Table 9'-S for rapid reference and can be used as an
exercise in manual data storage. To store data manually in the PDP-7 core memory:
1.. Turn the lock switch counterclockwise and set the POWER switch to the
. up position.
2. Set the ADDRESS switches to correspond with the address of the first word
to be stored. (In the case of the RIM loader program, this is 17762 ).
S
NOTE: Whenever an address in core memory is given in this section,
it is intended to apply to an SK memory. To translate this to the correct 4K memory address, subtract 1OOOOS.

3. 'Set the ACCUMULATOR switches to correspond with the binary content
of the first word. (In the case of the R1M loader program, th is is zero.)
4. Momentarily lift the DEPOSIT/DEPOS IT NEXT key to deposit the word
in memory.
5. Note the contents of the four storage registers (AC, MB, MA, and PC)
as given by their respective indicators after completion of the deposit operation. The AC and MB must both contai n the data word just deposi ted I the
MA must contain the ~ddress of the core memory cell in which the word was
deposited, and the PC must contain the address of the next consecutive core
memory cell (MA+l).
6. Store all additional data words by momentarily depressing the DEPOS IT/
D.EPOSIT NEXT key to the DEPOSIT ~EXT position after each succ~ssive

9-15

data word had been set up on the ACCUMULATOR switches. The contents
of the PC will be incremented by 1 during each deposit next operation, thus
setting up the a~dress of the core memory cell to be used for the next operation. The R1M loader contains the following program:

TABLE 9-8

"-----0
I

Address
(octo I)

Content
(octo I)

Tag

Mnemonic

17762/

0
700101
617763
700112
700144
637762
700144

0
RSF
JMP .-1
RRB
RSB
JMP IR
RSB

117762
057775
417775
117762

OUT,

L 17763/

<, 17764/

; 17765/
:; 17766/
. 17767/
, 17770/
17771/
17772/
. 17773/
'. 17774/
. - 17775/
17776/
!;;

f-'

)

READIN MODE (RIM) LOADER PROGRAM

GO,

617771

Comments

/READ ONE BINARY WORD .
/WAIT FOR WORD TO COME IN
/READ BUFFER
/READ ANOTHER WORD
/EXIT SUBROUTINE
/ENTER HERE I START READER
/GOING
/GET NEXT BINARY WORD

JMS R
DACOUT
XCT OUTI /EXECUTE CONTROL \VORD
JM:" R
/GET DATA WORD
0
/STORE DATA WORD
JMP G
/CONTINUE

-~•. ~
,< / .:. :.: . ~ --;
.......
-..r
7. To recheck a loaded program, set the ADDRESS switches to the starting
I

;

address and momentarily set the EXAMINE/EXAMINE NEXT key to the EXA/'ll! f'·lE position. After the first cell has been checked, the remaining cells

may be examined in sequence simply by repeatedly setting the switch to the
EXAMINE NEXT position without adjusting the ADDRESS switches. The
contents of any cell can be 01 tered by repeating steps 2 through 4, using the
address of the cell in question.

Loading Binary Data Using READ-IN Ke)1
Binary format tapes (including the R1M loader tape) can be loaded directly into the computer
without the need of a prestored program. This is accompl ished as follows:
1. Turn the computer lock switch counterclockwise and set the POWER
switch to the up posi lion.

9-16

2,. Set the tape reader POWER ON switch to ON.
3. Set the READY/LOAD switch to LOAD (clockwise) and insert the binary

tClpe. The tape is placed in the right-hand loading bin of the reader, and,
during reading, travels to the left-hand bin. Vv'hen the tape is properly
positioned, there will be three bit positions to the rear of the sprocket
wheel and five bit positions to the front.
4. Set up the starting address of the tape (found on the leader) on the
ADDRESS switches.
5. Press and release the computer READ-IN key.
6. Set the tape ·reader READY/LOAD switch to READY. The tnpe wi II be
read automatically.

Loading Data l)nder Program Control
Information (in other than binary format) car. be stored or modified in the computer automatical-

Iy, only by executing programs previously stored in memory. For example, having the RIM
loader stored in the core memory allows RIM format. tapes to be loaded as follows:
1. Turn the computer lock switch counterclockwise and set the POWER switch
to the up position.
2. Set the tape reader POWER ON switch to ON.
3. Set the READY/LOAD switch to LOAD and insert the tope into the tape
reader.
4. Set upthe starting address of the RIM loader program (17770) by mp-ons
of the ADDRESS switches.
5. Press and release the computer START key.

9-17

6. Set the tape reader READY/LOAD switch to READY. The tape will be
read automatically. The program contained on the tape may be initialized
and started automatically after being loaded. This occurs because some
tapes in RIM format are concluded with address 0000 and a data word equal
to one less than the starting address of the program iust read. Therefore,
after the last tape character is read, the program starting address is taken by
the program counter as the address of the next instruction to be executed.

Assembl ing Programs With PAL
Programs prepared in binary format and written in PAL, symbolic language can be assembled
into binary, machine-language program tapes by PAL as described in appropriate Digital Program Library documents. Basically, this operation is accomplished as follows:
1. Energize the computer by turning the lock switch counterclockwise and
setting the POWER switch to the on (up) position.
2. Energize the tape reader by setting t~e PO'vVER ON switch to 0 N.
3. Store the RIM loader program, either manually or by use of-the REAOI N key I as previousl y described.
4. Load the PAL assembl er program by means of the assembl er tape. Since
the assembl er tape is in RIM format, it can be loaded by the method described
under Loading Data Under Program Control. When the tape has been run, the
AC should contain all O·s.

If it does not, a checksum error has been detec-

ted; and the program has been improperly stored. When this occurs, the tape
must be rerun until the AC does finally contain all O·s at the conclusion of
the loading process. When this result is achieved, the program has been
properly stored. Repeated errors indicate defects in either the assembl er tape
or the PDP-7 system.
5. Set the tape reader READY/LOAD switch to the LOAD position, and insert the PAL symbolic language tape (which is to be converted into machinelanguage, binary format) into the tape reader.

9-18

6. Set up the starting address of the PAL assembl er program (0020) on the
ADDRESS switches of the operator console. (Set accumulator switch 10 up
to indicate ASCII, or down to indicate FIODEC.)

7'. Press and release the CONTINUE key.
8. When assembly is complete, the assembler will ,stop with all lis in the
AC.

Teletype Code
The 8-bit code used by the Model 33 KSR Teletype unit is the A'me.rican Standard Code for Information Interchange (ASCII) modified. To convert the ASCII code to Teletype code add 200
octal (ASC II - 2008 = Tei'etype). Th is code is read in the reverse of the normal octal form used
in the PDP-7 since bits are numbered from right to left, fr9m 1 through 8, with bit 1 having the
most sign ificance. Therefore, perforated tape is r~ad:

8
Least Significant
, Octal Bit

Most Significant
Octal Bit

Tape is loaded into the reader:

The Model 33 KSR set can generate all assigned codes except 340 through 374 and 376. Generally, codes 207, 212, 215; 240 through 337, and 377 are sufficient for Teletype operation.
The Model 33 KSR set can detect all characters, but does not interpret all of the codes that it
can generate as commands • The standard number of characters printed per I ine is 72. The sequence for proceeding to the next I ine is a carriage return followed by a Iine feed (as opposed
to a Iine feed followed by a carriage return). Key or key combinations required to produce
octal codes from 200 through 337, 375, and 377 are indicated in Table 9-9 with the associated
ASCII character.

9-19
1

TABLE 9-9
Octal
Code

TELETYPE CODE

Character
Name

ASCII
Character

Teletype
Character

Key or Key
Combinations

220

Null/Idle

NULL

CTRL @

201

Start of Message

SOM

CTRL A

202

End of Address

EOA

CTRL B

203

End of Message

EOM

CTRL C

204

End of Transmission

EOT

CTRL D

205

Vv'ho Are You

WRU

CTRL ·E

206

Are You

CTRL F

207

Audible Signal

BELL

CTRL G

210

. Format Effector

CTRL H

211

Horizonto I Tabu lotion

H TAB

CTRL I

212

Line Feed

CTRL J

213

Vertical Tabulation

V TAB

CTRl K

214

Form Feed

CTRL L

215

Carriage Return

CTRL M

216

Shift Out

CTRL N

217

Shift In

CTRL 0

220

Device Control Reversed
for Data Line Escape

DCC

CTRL P

221

Dev ice Control On

DCl

CTRL Q

222

Device Control (TAPE)

DC2

CTRL R

223

Device Control Off

DC3

CTRL S

224

De\lice Control (:tA-Pf)

DC4

CTRL T

2"'::-

Error

ERR

CTRL U

226

Synchronous Idle

SYNC

CTRL V

227

Logical End of Media

LEM

CTRL W

230

Separator, Information

CTRL X

231

Separator I Dota Del imiters

CTRL Y

232

Separator, Words

CTRL Z

233

Sp.parator, Groups

SHIFT CTRL K

9-20

TABLE 9~9

TELETYPE CODE (cont)

Octal
Code

Character
Name

ASCII
Character

234

Separator I Records

SHIFT CTRL L

235

Separator I Files

SHIFT CTRL M

236

Separator I Misc.

SHIFT CTRL N

237

Separator I Misc.

SHIFT CTRL 0

240

Space

241

Exclamation Point

242

Quotation Marks

243

Number Sign

244-

Teletype
Character

Key or Key
Combinations

Space

Space Bar

.
..

SHIFT
SHIFT

SHIFT #

Dollar Sign

SHIFT $

245

Percent Sign

SHIFT %

246

Ampersand

SHIFT &

247

Apostrophe

250

Parenthesis, Beginning

(

SHIFT (

251

Parenthesis, Ending

)

SHIFT )

252

Asterisk

SHIFT *

253

Plus Sign

*
+

SHIFT +

2[>4

Comma

255

Hyphen

256

Period

257

Virgule

260

Numeral 0

261

Numeral 1

262

Numeral 2

2cS3

Numeral 3 .

264

Numeral 4

265

Numeral 5

266

Numeral 6

267

Numeral 7

SHIFT

9-21

TABLE 9-9
Character
Name

Octal
Code

TELETYPE CODE (cont)·
ASCII
Charucter

Teletype
Character

Key or Key
Combinations

270

Numeral 8

271

Numeral 9

272

Colon

273

Semicolon

;

274

Less Than

SHIFT

275

Equals

<
=

SHIFT

276

Greater Than

SHIFT

277

Interrogation Point

SHIFT ?

300

SHIFT @

301

Letter A

302
303 .

Letter B

Letter C

304

Letter D

305

Letter E

306

Letter F

307

Letter G

310

Letter H

311

Letter I

312

Letter J

313

Letter K

314

Letter L

315

Letter M

316

Letter N

317

Letter 0

320

Letter P

321

Lett~r Q

322

Letter R

323

Letter S

9-22

TABLE 9-9
Octal
Code

TELETYPE CODE (cont)

Character
Name

ASCII
Character

Teletype
Character

Key or Key
Combinations

324

Letter T

325

Letter U

326

Letter V

32:7

Letter W

330

Letter X

331

Letter Y

.332

Letter Z

333

Bracket, Left

[

SHIFT K

334

·Reverse Virgule

SHIFT L

335

Bracket, Right

]

SHIFT M

336

Up Arrow (exponentation)

337

Left Arrow

t
......

3~O through 374 are not available

375

Unass igned Contro I

376

Not Available

Delete/Idle/Rub Out

t
SHIFT 4--

ALT MODE

DEL

RUB OUT

Local Teletype Operation
The Teletype can be used as an ordinary typewriter in the following manner:.
1. Set the computer lock switch to the counterclockwise position.
2. Set the computer POWER switch to the up position.
3. Set the Teletype .LINE/OFF/LOCAL switch to the LOCAL position.
4. Type out the desired information on the Teletype keyboard.

PROGRAMMING
Refer to i-he PDP-7 Users Handbook F"'75 for information on basic programming of the system.
Refer to individual Digital Program Library documents for specific information on the format,
specifications, and procedure for using a particular program language, such as PAL or FORTRAN.

9--23

CHAPTER 10
MAINTENANCE

Maintenance of the PDP-7 consists of procedures repeated periodically as preventive maintenance and tasks performed as corrective maintenance in the event of equipment malfunction.
Maintenance activities require use of the eqlJipnent I isted in Table 10-1 , or equivalent, as
well a~ the use of standard hand tools, cleansers, and test cables and probes.

TABLE 10-1

MAINTENANCE EQUIPMENT
Manufac turer

Equipment

Designation

Mu l1'i meter

Triplett or Simpson

Mode I 630- NA or 260

Oscilloscope

Tektronix

Type 547

Plug-in Unit

Tektronix

Type CA

CI ip-on Current Probe

Tektronix

Type P6016

X 10 Probe

Tektronix

P6008

Recessed tip, 0.065 inch
for wire wrap terminals

Tektronix

206-052

Current Probe Ampl ifier

Tektronix

Type 131

Hand Unwrapping Tool

GardnE~r-Denver

500130

Hand-Operated Wire-Wrap
Tool with a 26263 Bit for
24 AWG wire and 18840 sleeve

Gardner-Denver

14H1C

FLIP CHIP Module Extender*

DEC

Type W980

Paint Spray Can*

DEC

DEC Blue 5'150-S65

Air Fil ter*

Research Products Corp.

EZ Clean 2-inch
Type MY

F ilter-Kote*

Research Products Corp.

By Name

Teleprinter Input/Output Test*

DEC

Digital-7-50-M

Clock Interrupt Test Program*

DEC

Digital-7-S1-M

CONTEST 11*

DEC

D igital-7-52-M

*One is suppl ied with the equipment

10-1

TABLE 10-1

MAINTENANCE EQUIPMENT (continued)

Equipment

Manufacturer

Designation

Reader and Punch Test*

DEC

Digital-7-53-M

Maindec 401 (Instrur.tion Test)*

DEC

Digital-7-54-M

Maindec 402 (Checkerboard)*

DEC

Dig i ta 1-7-55-M

Maindec 403 (Address Test)*

DEC

Digital-7-56-M

Maindec 410 (RPB Test)*

DEC

Dig ita 1-7-57-M

*One is suppl ied with the equipment
The Maindec routines are diagnostic programs designed to exercise or test specific functions
within the computer system.
in readin "mode format.

Maindec routines are prepared as perforQted-poper program tapes

Each tope is accompanied by a detailed description of the program

contained on the tape, procedures for using the program, and information on analyzing the
program results to locate specific circuit failures.

Use of these routInes is indicated at the

appropriate points in this manual as they apply to preventive or corrective rna intenance of the
standard PDP-7 system.
Turn off all power before extracting or inserting modules. Access to controls on the module
for use in. adjustment, or access to points used in signal trac ing can be gained by removing the
module (use a straight, even pull to prevent twisting of the printed-wiring board), connecting
a Type 'N380 FLIP CH IP Module Extender into the vacated module connector in the mounting
panel, and then inserting the module into the extender.

CAUTION
FLIP CH IP modules may be harmed by removing or inserting them
with power on. Failure is not caused by the transient voltage but
rather by brushing the free module against ,one plugged in. Failure
to one or both modules may result. Do not remove FLIP CHIP
modules with power on.
T~e procedures presented here assume that the reader understands the function of the keys,

switches, and indicators on the operator console and is familiar with machine programming as
described in the PDP-7 Users Handbook F-75.

10-2

In additic)n to the controls and indicators on the oper'ator console, the indicator panel, and on
the Teletype unit (described in Tables 9-1 through 9-5~ maintenance operations use controls
and indicators on the marginal-check panel (which is mounted at the top of bay 3, in the front
of the computer) and on the Type 832 Power Control. The function of these oontrolsand indicators is described in Table 10-2, and the marginal-check panel isshown in Figure 10-1 •

TABLE 10-2

MAINTENANCE CONTROLS AND INDICATORS
Function

Control or Indicator

Marginal-Check Panel
Voltmeter

Indicates the output voltage of the marginal-check
poser supply in either polarity.

Toggle switches
(four)

The bottom switch applies a -15v marginal-check voltage
to the Teletype control. The active position for the
switch is up. The second switch from the bottom appl ies
a +10v marginal-check voltage to the Teletype -control.
The active position is ~p. The other two switches are
not used.

Selector switch

Controls. the output of the marginal-check power supply.
In the +10 Me position, the output is positive and is connected to the orange +10 MC connector. In the - '15MC
position, the output is negative and is connected to the
green -15 Me connector. The center position is off and
disconnects the output from the marginal-check power
supply.

Elapsed time meter

Indicates the cumulative total number'of hours during
which the computer has been energized, and so provides
a unit of measure that is more appropriate than calendar
time for determining preventive maintenance schedules.

10-3

TABLE 10-2

MAINTENANCE CONTROLS AND INDICATORS (continued)

Control or Indicator

Function
Marginal-Check Panel (continued)

Control Knob

Controls the output of rhe marginal-check vol tage to any
level between 0 and 20v.

832 Power Control
Protects the computer p~wer source from overload due to

Circuit breaker

failure of the computer power circuits.
REMOTE/OFF/LOCAL
switch

Allows control of the computer primary power from the
back of the mach ine during ma intenance.

In the

REMOTE position, application and removal of computer
power is controlled by the lock and POWER switches on
the operator console. In the OFF position the computer
is de-energized, regardless of the position of switches on
the operator console. In the LOCAL position the cOn;lputer
is energized regardless of the position of operator console
switches or door inter locks.
MEM. POWER switch

Controls the appl ication and removal of operating vol tages
for the memory circuits.

!'!'".~~~~~

10 15 20
5 ."\,,,\ 1'1- I,/ 25
..,{X·'

~:!~. ~~~.~~

··I./.>

r ····"",,-'.1
..

~,~~>=:~.' ~:~~~:::,.O-,?~

OFF

+10MC

Ii
f
\;,

- 15MC

Figure 10-1

Marginal-Check Panel

10-4

PREVENTIVE MAINTENANCE
Preventive maintenance consists of tasks performed periodically during the operating life of
the equipment to ensure that it is in satisfactory operating condition. Faithful performance of
these tasks helps to forestall incipient failures by discovering progres~ive deterioration and
correcting minor damage at an early stage. Data obtained during the performance of each
preventive maintenance task should be recorded in a log book. Analysis of this data indicates
the rate of circuit operation deterioration and provides information for determining when components should be replaced to prevent failure of the system. Preventive maintenance tasks
consist of mechanical checks, which include cleaning and visual inspections; marginal checks,
whic~ aggravate border-line circuit conditions or intermittent failures so that they can be de-

tected and corrected; and checks of specific circuit elements such as the power supply, sense
ampl ifiers and master sl ice control, and memory selectors.
All preventive maintenance tasks should be performed as a function of conditions at the instal~·
lation site. Perform the mechanical checks at least once each month or as often as required
to allow ~fficient functioning of the air fil ter. All other tasks should be performed on a regular schedu Ie, at an interval determined by the rei iabi Iity requ irements of the system. A typi,
cal recommended schedule is every 600 equipment operating hours or every four months,
whichever is completed first. The most important schedule to maintain is that of the simplest
procedure--the mechanical checks. Many hours of computer down time can be avoided by
rigid adherence to a schedule based upon the condition of the air filter. Machine failures
can occur due to overheating caused by the air filters becoming so dirty that no cooling air
can be drawn into the cabinet by the fans.

Mechanical Checks
Assure good mechanical operation of the equipment by performing the following step~ and the
ind icated corrective action for any substandard condition found:
1. Clean the exterior and the interior of the equipment cabinet using a
vacuum cleaner or clean cloths moistened in nonflammable solvent.
2. Clean the air filters of the b~ttom of the cabinets. Remove each filter
by removing the fan and housing,. which are held in place by two knurled

'10-5

-.....

and stotted captive screws. Wash each filter in soapy water and dry it in
an oven or by spraying with compressed gas. Spray each filter with FilterKote (Research Products Corporation, Madison ,Wiscons in) •
3. Lubricate door hinges and casters with a light machine oil. Wipe off
excess oil.

4. Visually inspect the equipment for completeness and general condition.
Repaint any scratched or corroded areas with DEC blue tweed point number

5150-565.
5. Inspect ':III wiring and cables for cuts, breaks, fraying, wear, deterioration, kinks, strain, and mechanical securi ty. Tope, solder, or replace
any defective wiring or cable covering.

6. Inspect the following for mechanical security: keys, switches, control
knobs, lamp assemblies, jacks, connectors, transformers, fans, capacitors,
elapsed tinle meter I etc. Tighten or replace CiS required.

7. Inspect all module mounting panels to assure that each module is securely
seated in its connector.

8. Inspect power supply capacitors for leaks, bulges, or discoloration.
Replace any capacitors giving these signs of malfunction.

Power Supply Checks
Perform the following power supply output checks outl ined in Table 10-3. Use a mul timeter
to make the output vol tage measurements with the normal load connected. Use the osc i1loscope
to measure the peak-to-peak ripple content on all dc outputs of the supply. The +10 and -l5v
suppl ies are not ad justabl ei therefore I if any output vol tage or ri ppl e content is not with in
specifications, the power supply giving these indications should be considered defective and
troubleshooting procedures should be initiated. Refer to the engineering drawing I isted in
the toble.

10-6

TABLE 10-3
Measurement
Terminals at
Power Supply
Output

Nominal
Output
(Volts de)

POWER SUPPLY OUTPUT CHECKS
Acceptable
Output
Range
(Volts)

Maximum
Output
Current
(Amperes)

Maximum
Peak-to- Peak
Output Ripple
(Vol ts)

Type 728 Power Suppl y (RS-B-728)
Red (+) to
Yellow (-)

+10

+9.5 to 11 .5

7.5

0.7

Yellow (+) to
Blue (-).

-15

- 14 • 5 to 16.5

8.5

0.4

Type 778 Power Supply (RS-B-778)
Red (+) to
Blue (-)

-15

-14.5 to 16.5

8.5

0.6

Type 779 Power Supply (RS-B-779)
Orange (+) to
Yellow (-)

+10

+9.6 to 11 .0

7.5

1.0

Yellow (+) to
Blue (-)

-15

-14. 5 to 16.0

8.0

0.4t

Red (+) to
Yellc)w (-)

+15

+14 .5 to 16.0

7.5

1•1

Yellow (+) to
Green (-)

+15

+ 14.5 to 16.0

7.5

1•1 .

Check the operation of the variabl e-output Type 738 Power Supply wh ich produces the
marginal-check voltages. With all of the normal/marginal switches in the normal (down)
position, make the following measurements at the color-coded connector at the right side of
any convenient module mounting panel:
1. Connect a multimeter between the yellow (-) and black (+) terminals;
set the +10 MC/OFF/-15 MC switch to the -15 Me position, and turn the
control knob clockwise to assure that at least -20 volts can be produced by
the supply (as indicated on the multimeter). Record the indication given
on both the marginal check vol tmeter on the panel and on the multimeter.

10-7

These indications should be equal ± 1 volt. Connect the oscilloscope to the
yellow terminal, and measure the peak-to-peak ripple content to assure that

it is no more than 1.0 volt. Turn the control knob fully counterclockwise;
set the +10 Me/OFF /-15 MC switch to the OFF position, and disconnect the
multi meter and oscilloscope.
2. Connect the multimeter between the green (+) and block (-) terminals;
set the +10 MC/OFF /-15 MC switch to the +10 MC position, and turn the
control knob clockwise to assure that at least +20 volts can be produced by
the supply. Turn the control knob fully counterclockwise, set the
+10MC/OFF/-15MC switch to the OFF position, and disconnect the multimeter.
The Type 739 Power Supply output is not measured during this check, since it is monitored
and adjusted during the Memory Current Check.

Marginal Checks
Marginal checking uti! izes the Maindec di~gnostic programs to test the functional ca~bil ities
of the computer with the module-operating voltages biased above and below the nominal levels.
Biasing the operati ng vol tages aggravates borderl ine c ircui t cond i tions with in the modu I es to
produce failures which are detected by the program. When the program detects an error I it
usually provides a printout or visual indication which is helpful in locating the source of the
fault, and then hal ts. Therefore I marginal components can be replaced during scheduled preventive maintenance to forestall possible future equipment fail ure. The biased operating
voltages at which circuits fail are recorded in the maintenance log.

By plotting the bias vol t-

ages obtained during each scheduled preventive maintenance, progressive deterioration can be
observed and expected failure dates can be predicted.

In this manner these checks provide a

means of planned replacement. These checks can also be used as a troubleshooting aid to
locate roorginal or intermittent components I such as deteriorating transistors.
Raising the operating vol tages above +1 Ov increases the transistor cutoff bias that must be
overcome by the previous driving transistor I therefore low-gain transistors fail.

Lowering the

bias voltage below +10v reduces transistor base bias and noise rejection and thus provides a
o

10-8

test to detect high-leakage transistors. Lowering this voltage also simulates high-temperature
conditions (to check for thermal run away). Raising and lowering the -15v supply increases
and decreases the primary collector supply voltage for all modules and so affects output signal
voltage.
Since marginal voltages attainable vary for different circuit changes and/or system configurations, determine the expected marginal-check voltages for a. specific system from the initial
factory test records and any subsequent test rec.ords in the maintenance log. A record of margins obtained at the factory for a specific system is provided with each system and serves as a
base for all preventive and corrective maintenance procedures. With time and normal circuit
operation deterioration, margins will decrease. This decrease does not affect reliable operation
of the machine until there is I ittle or no margin at all.. The normal slow rate of margin decay
can be used to predict the time at which the system should be refurbished to prevent sudden
failure. Margins do provide a measure of circuit performance and so can be used to certify
correct or defective operation. However, failure of a system to obtain the some margins year
after year does not constitute a defect in the operation of the system. For example, if a
specific margin decreases at the rate of 0.5'· per year, no trouble is indicated. If this margIn
suddenly decreases by 0.7v in six months, troubleshoot.ing procedures should be undertaken to
determine the couse of this rapid change.

CAUTION
Do not increase the -15v margin beyond -lav. Foil ure to observe
this precaution may couse seriolJs damage to the logic elements.

Marginal check voltages are supplied to the various sections of the processor through connections made to the module connectors in each mounting panel. Each marginal check voltage
may be adiusted throughout the range of 0 to 20v by means of the control knob and voltmeter'
located on the marginal-check control panel. The selector switch eil this panel selects either
the +10 or the -15 marginal-check voltage. Power supply leads to the module connectors in
the mounting panels are color-coded as fo110ws:

10-9

Orange

+lOv marginal-check supply

Red

+lOv normal power supply

Black

Ground

Blue

-15v normal power supply

Green

-15v marginal-check supply

Marginal check and normal supply voltages are distributed to each of two module rows in each
mounting panel by means of two SPDT switches on the marginal check panel of each assembly.
There 'are two positions for each SPDT switch: normal {down} and marginal-check (up). Therefore the modules in one mounting panel (two rows) 'may be marginally checked while all other
rows'maintain normal voltage.

In each module mounting panel, the upper switch controls the

+lOv supply and the lower controls the -15v supply (with mounting panel viewed from the connector side and switches on the left).
To perform the checks:
1. Assure that all normal/marginal-check switches on each module mounting panel are in the normal (down) position (normal +lOv arid -15v power
suppl ies are being used).
2. Set the +10MC/OFF/-15MC selector switch on the marginal-check control panel to the +10 MC position.

3. Adiust the output of the marginal-check power supply so that the marginalcheck voltmeter indicates 1Ov.

4. Set the +10 normal/marginal switch for the first ?Jnel row to be checked
to the marginal-check (up) position.

5. Start computer operation in a diagnostic program or routine which fully
utilizes the circuits in the panel to be tested. If no program is suggested by
the normal system appl ication, select an appropriate Maindec program from
Table 10-4. To completely test the PDP-7, all Maindec programs listed in
Table 10-4 should be performed at,elevated and reduced voltages for each
supply terminal (+10, -15) and for,eachmodulemountingpanel indicated in
the table.
10-10

6. Decrease the marginal-check power supply.output until normal system operation is interrupted. Record the marginal-check vol tage. At
this point marginal transistors can be located and replaced I if desired.
Readjust the marginal-check power supply output to the nominal +lOv
level.

7. Restart computer operation. Increase the marginal-check supply output until normal computer operation is interrupted, at which point record
. the marginal-check vol tage. Transistors can again be located and replaced.
Readiust the marginal-check power supply to the nominal +lOv level.

8. Return the normal/marginal switch to the normal (down) position.

9. Repeat steps 4 through 8 for each of the other panels to be checked by
biasing the +lOv line.
10. Set the +10 MC/OFF/-15 MC selector switch on the marginal-check
power supply to the -15MC position and adiust t~e output until the
marginal-check voltmeter indicates 15v.
11. Set the -15 normal/marginal switch to the marginal-check (up) position
for the first pane I row to be checked I then repeat step 5.
12. Repeat steps 6 and 7, readjusting the morqinal-check power supply to
the nominal -15v level at the end of each step. Return the normal/marginal
switches to the normal (down) positic)n.
13. Repeat steps 10 through 12 for each other module mounting panel row
to be tested by biasing the -15v line.
14. Set the +10 MC/OFF/-15MC selector switch to the OFF position.

10-11

TABLE iO-4
Mounting
Panel
Row
Tested

MARGiNAL TEST PROGRAMS
Diagnostic (MAl NDEC) Test

Clock
Interrupt
Test
Digital-7-51-M

Memory
Checkerboard
Test 402
Dig ita 1-7- 55- M

Address
Test 403

Contest II

Reader and
Punch Test

Teleprinter
Test

Digital-7-56-M

Digital-7-52-M

Digital-7-53-M

Digital-7-50-M

+10, -15

CP
1A

+10

CP
1B

+10

+10, -15

CP
lC

+10

+10, -15

CP
1D
o
I

+10, -15
**
*
+10, -15

CP
1F

+10, -15

CP
lK

+10, -15

CP
1L
CP

-'.

+10, -15

*
**
+10, -15

+10, -15

* This check made with third (from the top) toggle switch on marginal-check panel in the ON (up) position.
**This check made with bottom toggle switch on marginal-check panel in the ON (up) position.

TABLE 10-4
Mounting
Panel

MARGINAL TES} PROGRAMS (continued)
Diagnostic (MAINDEC) Test

Memory
Checkerboard
Test 402
Digital-7-55-M

Address
Test 403

Contest II

Reader and
Punch Test

Teleprinter
Test

Digital-7-56-M

Digital-7-52-M

Digital~7-53-M

Digital-7-50-M

MEM
1A

+10

MEM
1B

+10

MEM
1H

+10

MEM
1J

+10

Row
Tested

Clock
Interrupt
Test
Digital-7-51-M

CP
1N

OS
2A

**
*
+10, -15

+10, -15

OS
2B

*
**
+10, -15

+1'0, -15

+10, -15

DS
2C

*
**
+10, -15

+10, -15

+10,-15

Reader/Punch
3A

**
*
+10, -15

+10, -15

Reader/Punch
3B

*
**
+10, -15

+10, -15

Teletype
Control

*
**
+10, -15

Teletype
Control

* This check made with third (from the top) toggle switch on marginal-check panel in the ON (up) position •.
•• 1

I..

'--

-~, -

••••

!I._L -_ ........... ,..:~,..I_,..h~,..L- rY"1npl in the ON (UD) oosition.

+10, -15

Memory Current Check
Measure the read/write and inhibit currents in the core memory. These currents should be approximately equal to the values specified on the memory array label (approximately 330 rna
and 290 rna, respectively). This label indicates the optimum memory setting determined at the
factory. Allow the equipment to warm up for approximately 1 hr before making measurements.
Vv'henever poss ibl e th is check should be performed at an amb i ent temperature of 25°C.

Com-

pensate measured read-write and inhibit currents by subtracting 1 rna for every degree of ambient temperature above 25°C. (Add 1 rna for each degree below 25°C.) The memory current
c:heck dnd sense ampl ifier check procedures must ~ be performed when the equipment temperature is beloY" 20°C.
Measure the read/write current using the asci i loscope and cI ip-on current probe at the read
side of a fully selected drive I ine of the X or Y axis G202 ~;\emory Selector Switch. The

READ terminals are either Land P, or M and N of a G202 module. Refer to the G202 module
schematic. Synchronize the oscilloscope v/ith the negative transition of the READ signal found
elt location 1B202H. Adjust the read/write current to 330 rna or to the value specified on the
memory anay label by rotaticn of R16 in the G80a read/write power supply control module.
In a similar manner, measure the inhibit current by c.:mnecting the clip-on current'probe at a
proper terminal of the inhibit connector lccoted at 1B10. See drawing G201 for the appropriate
i'nhibit terminal. Synchronize the oscillos.cope on the negative transition of the INH(B) line
found at location 1B1OJ. Ad just the inhibit current to 290 rna or to the value indicated on the
memory array label.
To obtain consistent measurements, the current probe should be positioned to indicate read
current as a negative pulse, and write and inhibit currents as positive pulses as displayed on
1the oscilloscope. All current ampl itude measurements should be made just before the knee in
the curve of the trail ing ed$e of a pulse. Note that read and write currents are measured from
Ibase Iine to peak ampl i tude, not from peak to peak.

'10-14

Sense Amplifier Check
The GOOl Sense Amplifier modules are adjusted for optimum efficiency through marginal checking techniques. Perform the marginal checks \.Ising the Memory Checkerboard Program,
Maindec 402. See Table 10-4 for marginal power supply used, and set the SPOT switches
accordingly. Check end adjust each SA circuit so that approximately equal positive and negative margi~s can be obtained, using the +10v marginal power supply.
Sense amplifiers are located at 1H and lJ, 1 through 19. The master slice control is located
at 1H20.

CORRECTIVE MAINTENANCE
The PDP-7 is constructed of highly reliable transistorized FLIP CHIP modules. Use of these
circuits and fa ithful performance of the preventive maintenance tasks ensure rei at ively I ittl e
equipment downtime due to failure. Should a malfunction occur, the condition should be
analyzed and corrected as indicated in the following procedures. No test equipment nor special
tools are required for corrective maintenance other than a broad bandwidth oscilloscope and a
standard multimeter. However, a cl ip-on current probe such as the Tektronix Type P6016 with
a Type 131 Current Probe Amplifier is very- helpful in monitoring memory currents. The best
corrective maintenance tool is a thorough understanding of the physical and electrical characteristics of the equipment. Persons responsible for maintenance should become thoroughly
famil iar with the system concept, the logic drawings, the operation of spec ific modul e c ircu its,
and the location of mechanical and electrical componf"nts.

It is virtually impossible to outline any specific procedures for locating faults within complex
digital systems such as the PDP-7. However, diagnosis and remedial action for a fault condition can be undertaken logically and systematically in the following phases:

10-15

1. Prel iminary investigation to gather all in'form~tion and to determine
the physical and electrical security of the computer.
2. System troubleshooting to locate the fault to within a module through
the use of control panel troubleshooting, signal tracing, or aggravation
techn iques •
3. Circuit troubleshooting to locate defective parts within a module.
4. Repairs to replace or correct the cause of the malfunction.
5. Validation tests to assure that the foul t has been corrected.
6. Log entry to record pertinent data.

Prel iminory Investigation
Before commencing troubleshooting procedures, explore every possihle source of information.
Ascertain all possible information concernir.9 any unusual function of :the machine prior to the
fault and all possible data about the symptoms given w~en the fault occurred, such as the program in progress, condition of operator console indicators, etc. Search the maintenance log
to determine'if this type of fault has occurred before or if there is any cyclic history of this
kind of fault, and determine how this condition was previously corrected. When the entire
machine fails, perform a visual inspection to determine the physical and electrical security of
clll power sources, cables, connectors, etc. Assure th'1t the power supplies are working propE~rly and that there are no power short circuits by performing the Power Supply Checks as de-

scribed under Preventive Maintenance. Check the condition of the air fil ter in the bottom of
the cabinet. If th is fil ter becomes clogged, the temperature within the cabinet might rise
sufficiently to couse marginal semiconductors to become defective.

10-16

System Troubleshooting
Do not attempt to troubleshoot the system without first gathering all information possible concerning the fault, as outlined in the Preliminary Investigation.

Maindec Diagnostic Programs
The Maindec ·Diagnostic Programs listed in Table 10-1 are provided for locating sources of
malfunction within the processor, memory, and I/O equipment. Since these divisions encompass
the complete PDP-7 system, any trouble may be located generally by the Maindec programs,
and a local program loop may be devised to pinpoint· the malfunction to a specific module.
Maindecs 401, 402, and 403 specifically test processor and memory functions. Maindec 410
tests functioning of the reader and punch buffBr. These diagnostic programs are particularly
useful under marginal checking conditions.
Maindec 401 tests the instruction cycl ing, processor registers, and controls (including the PC).
Maindec 402 tests memory core storage by producing bit patterns in the cores that will cause
worst-noise conditions within the core array. Defective cores are detected in this manner.
Maindec 403 tests address sel ection, and is, therefore, a powerful means of troublt~:shooting
the entire memory address system, incl uding the MA register, MB register, memory sel ector
switches I and all controls associated with these functions.
Each Maindec diagnostic program instruction manual contains full particulars for loading the
program, interpreting the results, and operating the PDP-7 for diagnostic testing. Chapter 9
of this maintenance manual also contains instructions for loading and starting Maindec programs.
Commence troubleshooting by performing that operation in which the malfunction was initially
observed, using the same program. Thoroughly check the program for proper control settings.
Careful checks shoul d be made to assure that 'the PDP-7, and not the peripheral equipment, is
actually at fault before continuing with corrective maintenance procedures. Faults in equipment, check with transmits or receive information, or improper connection of the system frequently
gives indications very similar to those caused by computer malfunction. Faulty ground connections between peripheral equipment and the computer are a common source of troub1e. From

10-17

th(lt portion of the program being performed and the general condition of the indicators, the
logical section of the machine at fault can usually be determ ined.
If the fault has been isolated to the computer but cannot be immediately localized to a specific
logic function, it can usually be determined to be within either the core memory or the processor logic circuits. Proceed to the Memory Troubleshooting or Logic Troubleshooting procedures.
When the location of a fault has been narrowed to a logic element, continue troubleshooting to
locate the defective module or component by means of signal tracing. If the fault is intermittent,
a form of aggravation test should be employed to locate the source of the fault.

Memory Troubleshooting
If the entire memory system fails, use the multimeter to check the outputs of the 739 Power
Supply. Measure the voltages at the terminal strip as indicated on eFlgineering drawing RS-B-739.
Do not attempt to adjust this supply. If the supply is defective, troubleshoot it and correct the
CCluse of the trouble; then adjust the output voltage by performing the Memory Current Check.

If the power supply is functioning properly I proceed as follows:

The following test set-up permits sequential addressing (in binary form) of the core memory
through the MA register and read/write memory selectors.
1. De-energize the computer.
2. Connect a jumper from 1 K21 H to ground.
3. Restore computer power and press the START key.
This discussion references the X and Y axis selection drawings, SS-E-149-0-46 and
BS-E-149-0-47 and the memory control drawing BS-D-7-0-27. Looking at the X and Yaxis
drawings, note that a core address is selected by a combination of two G202 switch selectors:
one on the left side of the a~ray; the other on the bottom of the array. READ or WRITE transi-:tions, buffered by the SD module at location 1 B30, trigger all G202 selectors which generate
and distribute the actual read/write current to specific cores. In each axis, selection of the
two G202 switches is accompl ished by the bit configuration in the MA register. The actual

10-18

read/wrih~ current pulses flow from the positive supply line, through a left G202 selector,

through a horizontal core matrix Iine, through the core and diodes, down a vertical core matrix
I ine to a bottom G202 selector, and into the negative return line.
A train of' current spikes will be seen, and missing spikes will then represent malfunctioning
addresses.. Read currents are at terminals E and M; write currents are at terminals K and P of
each drive seiector. Before loading a Maindec Address program to find specific address malfunction, trace the read/write gating pulses from the BO module at 1830 and all the Hand J
terminals of every G202 module. A G202 Switch Selector module cannot select without the
gating pulse. If the read/write currents are not as specified on the memory array. labels, adiust
the Type G800 control module current accordingly.
Perform the Memory Address Test program (Maindec 403) to locate defective core memory
addresses. Compl ete the entire program and record all addresses which fail. Inspect the
record of failure addresses for common bits. Refer to engineering drawings BS-E-149-0-46
and BS-E-149-0-47, and check the memory selectors that decode common bits of the failing
addresses. Also check the assoc iated resistor board and memory matrix modul e.

If an address is dropping bits, use the operator console·to deposit all binary l's in that address.
Then examine the contents of the address to determine which bit position is not being set
(contains a 0). Check the sense amplifier, inhibit driver, and resistor board for the associated
bit. Also check the memory inhibit current as described in the Memory Current Check.

If an address is picking up bits, use the operator console to deposit all binary O's in that address,
and proceed as described in the previous paragraph.
To locate the cause of a specific address failure, use the oscilloscope and current probe to
trace recld and write current while performing a repetitive program such as the Memory Address
Test program or the Memory Checkerboard Test program.
Perform the Memory Checkerboard Test program (Ma indec 402) to tro,-,bleshoot all other memory
conditions.

10-19

Logic Troubleshooting

If the instructions do not seem to be functioning property, perform the Instruction Test program
(Maindec 401). This test hal ts to indicate instructions that fail. Wnen an instruction fails, as
indicated by the operator console indicators when the program stops, or by the diagnostic printout that follows the error halt, consult the descriptive manual for the Maindec 401 to obtain an
interpretation that will local ize the fault.
If the computer interrupt system or the Teletype teleprinter do not seem to be functioning properly, p~rform the Teleprinter Test Program, ~igital 7-50-M. If the tape reader or punch operaHon is questionable, perform the Reader and Punch Test (Digital-7-53-M) or the RPB Test
(Maindec 410).
Refer to the Teletype and Oigitronics documents for detailed maintenance information on the
Model 33 KSR set, BRPE Tape Punch Set, and Model 2500 Perforated Tape Reader.
Signal Tracing
If the faul t has been locoted within c functional logic element, program the computer to repeat
'Some operation in which all functions of that element are util ized. Use the oscilloscope to trace
signal flow through the suspected logic element. Oscilloscope sweep can be synchronized by
control signals or clock pulses, which are available on individual module terminals at the wiring
side (front) of the equipment. Circuits transferring signals with external equipment are most

I ikely to encounter difficulty. Trace output signals from the interface connector back to the
origin, and trace input signals from the connector to the final destination. The signal tracing
method can be used to certify signal qualities such as pulse amplitude, duration, rise time, and
the correct timing sequence. Refer to the table on engineering drawing 8S-0-7-0-22 to check
or adjust the timing of circuits in the main timing chai'1 or special timing chain generators.

an intermittent malfunction occurs, signal tracing must be combined with an appropriate form of
aggravation test.

Aggravation Tests
Intermittent faults should be traced through aggravation techniques.

Intermittent logic mal-

functions are located by the performance of marginal-check procedures as described under
Preventive Maintenance.

10-20

Intermittent failures caused by poor wiring connections can often be revealed by vibrating

modules while running a repetitive test program. Often, tapping a wooden rod held against
the handles of a suspect panel of modules is a useful technique. By repeatedly starting the
test program and vibrating fewer and fewer modules, the malfunction can be localized to
within one or two module~. After isolating the malfunction in this manner, check the seating
of the modules in the connector; check the module connector for wear or misal ignment, and
check the module wiring for cold solder joints or wiring kinks.

Circuit Troubleshooting
The procedure followed for troubleshooting and correcting the cause of fau1ts with in spec ific
circuits depends upon the downtime I hnitiations of equipment use. Where downtime must be
kept at a minimum, it is suggested that a provisioning parts program be adopted to maintain
one spare module, power supply, or standard component which can be inserted into the cabinet
when system troubleshooting procedures have traced the fault to a particular component. Static
and dynamic bench tests can then be performed without interfering with system operation.
Where downtime is not critical, the spare parts I ist can be reduced and module troubleshooting
procedures can be performed with the modules in-I ine (within the system). Although in-line
module troubleshooting extends the downtime of the system, it is economical of personnel time
because the module can be program exercised to locate the cause of the fault more rapidly.

Module Circuits
Basic functions and spec ifications for standard system modules used in the PDP-7 are presented
in the FLIP CHIP Modules catalog, C-105. Circuit schematics are provided in Chapter 11 of the
manual for all modules not described in the catalog. Schematic diagrams of all modules are
provided in the set of formal engineering supplied with each system. The following design considerations may also be helpful in troubleshooting standard modules.
1. Forward-biased silicon diodes are used in the same manner as Zener
diodes, usually to provide a voltage differential of O.75v. For instance,
a series string of four diodes is used to produce the -3 vdc clamp voltage
used in most modu les.

10-21

2. The state of DEC fl ip-flops is changed by an incom jng pulse which turns
off the conducting transistor ampl ifier. Since these fl ip-flops use PNP
transistors, the input pulse must be positive and must be coupled to the base
of the transistor. Flip-flop modul es that accept negative pulses to change
the state invert this pulse by means of a normal transistor inverter circuit.

3. Fixed-length delay lines such as the W300 are extremely reliable and
very seldom malfunction. However, if a malfunction should occur, these
delay lines should not be replaced on the printed-wiring board. In such
cases the entire module should be returned to DEC for repair.

4. The W607 and W640 modules both contain three independent pulse
ampl ifiers, each with its own input inverter.

Output pulse duration is de-

termined by the time required to saturate the interstate coupl ing transformer.
No multivibrotors or other RC timing circuits are used in the pulse amplifiers.

Jr.-Line Dynamic Tests
To troubleshoot a module while maintaining its connection within the system:
1. . De-energize the computer.
2. Remove the suspect module from the mounting panel.
3. Insert a W980 FLIP CHIP Module Extender into the mounting panel connector which normally hoi ds the suspect module.
4. Insert the suspect module into the module extender. All components
and wiring points of the module are now accessible.
5. Energize the computer and establ ish the program conditions desired for
troubleshooting the module. Trace voltages or signals thro'Jgh the module,
using a dc voltmeter or an oscilloscope, until the source of the fault is
located.

10-22

In .... line Marginal Checks
Marginal checks of individual modules can be performed within the computer to test specific
modules of questionable rei iabil ity, or to further localize the cause of an intermittent failure
which has been localized to within one module mounting panel by the normal marginal checking
method. These checks are performed with the aid of a modified W980 FLIP CH IP Module Extender. To modify an extender for these checks:
]. Disconnect module receptacle terminals A, B, and C from the male
plug connection terminals.. This can be accomplished by cutting the
printed wiring for these I ines near the plug end and removing a segment of
this wiring in each line.

2. Solder a 3-ft test Iead to the printed wiring for terminals A, B, and C.
IMake this solder joint close to the receptacle end of the extender, certainlyon the receptacle side of the wiring break.. Observe the normal precautionswhen making this connection to assure that excessive heat does not
delaminate the printed-wiring board and that neither solder nor flux provides conduction between lines.
3. Attach a spade lug, such as an AMP 42025-1 Power Connector to the
end of each test lead and label each lead to correspond to the A, B, or C
terminal of the receptacle to which it is connected.
To marginal check a module within the computer:

1. De-energize the computer.
2.. Remove the module to be checked from the module mounting panel; re-

place it with the modified extender, and insert the module in the extender.
3a. If the +lOv marginal check is to be performed, connect test lead A to
the +1 Ov orange connector terminal at end of the panel. Connect test lead

B to the normal -15v blue connector terminal and test lead C to black
ground connector ..

10-23

3b •. Vv'hen performing the -15v marginal check, connect test lead A to the
normal +lOv red connector, test lead B to the -15v green connector terminal, and test lead C to the black ground terminal. Keep all SPOT switches
in the down position.
4. Restore computer power, adiust the marginal-check power supply to
provide the nominal vol tage output I and start operation of a routine which
fu lIy uti Iizes the modul e be ing checked. The procedures and routines suggested in Preventive Maintenance for use in marginal checking the computer can be used as a guide to marginal checking modul es.
5. Increase or decrease the output of the marginal-check power supply un-

til the routine stops, indicating module failure. Record each bias voltage
at which the module fails. Also record the condition of all operator console
controls and indicators when a failure occurs. This information indicates
the module input conditions at the time of the failure and is often helpful in
tracing the couSe of a fault to a particular component part.
6. Repeat steps 4 and 5 for each of the three bias vol tages.

If margins of

±5von the +10 vdc supplies can be obtained, and the -15 vdc' supply can
be adiusted between -7v and -18v without module failure, a module can be
assumed to be operating satisfactorily.

If the module fails before these

margins are obtained, use normal signal tracing techniques within the
module to locate the source of the faul t.

Static Bench Tests
Visually inspect the module on both the component side and the prin-ted-wiring side to check
for short circuits in the etched wiring and for damaged components. If this inspection fails to
reveal the couse of trouble or to confirm a fault condition observed, use the multimeter to
measure resistances.

10-24

CAUTION
Do not use the lowest or highest resistance ranges of the multimeter when checking sem iconductor devices. The Xl a range is
suggested. Failure to heed this warning may result in damage to
components.
Measure the forward and reverse resistances of diodes. Dio~es should measure approximately
20 ohms forward and more than 1000 ohms reverse.

If readings in each direction are the

some, and no parallel paths exist, replace the diodes.
Measure the emitter-collector, collector-bose, and em itter-base resistances of transistors in
both directions. Most catastrophi c fail ures are due to short c ircu its between the con ector and
the emitter or are due to an open circuit in the base-emitter path. A good transistor indicates
an open circuit in both directions between collector and emitter. Normally 50 to 100 ohms
exist between the emitter and the base or between the coil ector and the base in the forward
direction, and open-circuit conditions exist in the reverse direction. To determine forward
and reverse directions, a transistor can be considered cs two diodes connected back-to-back.
In this analogy PNP transistors are considered to have both cathodes connected together to
form the base, and both the emitter and collector assume the function of an anode.

In NPN

transistors the base is assumed to be a common-anode connection, and both the emitter. and
coil ector are assumed to be the cathode.
Multimeter polarity must be checked before measuring resistances, since many ~eters (including
the Triplett 630) apply a positive voltage to the common lead when in the resistance mode.
Note that although incorrect resistance readings are a sure indication that a transistor is defective, correct readings give no guarantee that the transistor is functioning properly. A more
reliable indication of diode or transistor malfunction is obtained by using one of the many inexpensive in-c ircu it testers commerc iall y ava ilable.
Damaged or cold-solder connections can also be located using the mut"timeter. Set the multi-.
meter to the lowest resistance range and connect it across the suspected connection. Poke at
the wires or components around the connection, or alternately rap the modul e I ightly on a
wooden surface, and observe the multimeter for open-circuit indications.

10-25

Often the response time of the multimeter is too slow to detect the rapid transients produced by
intermittent connections. Current interruptions of very short duration, caused by an intermittent connection, can be detected by connecting a 1 .5v flashlight battery in series with a
1500-ohm resistor across the suspected connection. Observe the voltage across the 1500-ohm
resistor with an oscilloscope, while probing the connection.

pynamic Bench Tests
In general, a module which fails marginal in-line tests, or is suspect for other reasons, should
be returned to DEC for repa'ir or replacement. Many modules require special equipment for
dynamic testing, since the timing of pulse amp' ifiers and delay modules must be rigorously
maintained within narrow limits. Dynamic tests, therefore, should be oriented only toward
discovery of defective semiconductors. Dynamic tests may be carried out by means' of a Type
H901 Patchcord Mounting Panel connected to the computer power supply outputs by means of
Type 914 Power Jumpers .. Simulated ground-level signals may then be applied to the module
under test, using Type 911 Patchcords, and output termina Is of tbe module under test can be
monitored by an oscilloscope connected to terminals on the front of the Type H901 panel.
(Simuiated negative-level signal inputs are not required, since FLIP CHIP module input terminals are internally clamped at -3v, so open input terminals simulate a -3v signal input.)
Repair
Repairs to FLIP CHIP modules should be limited to the replacement of semiconductors. In all
soldering and unsoldering operations in the repair and replacement of parts, ovoid placing
texcessive solder or flux on adjacent parts or service lines. When soldering sem.iconductor devices {transistors, crystaf diodes, and metall ic rectifiers} which may be damaged by heat, the
following spec ial precautions shoul d be taken:

1. Use a heat sink, such as a pair of pi iers, to grip the lead between the
device and the joint being soldered.

2. Use a 6v soldering iron with an isolation transformer. Use the smallest
soldering iron adequate for the work.

3. Perf~rm the soldering operation in the shortest possible time, to prevent
damage to the component and delcm~nation of the module.etched wiring.
10-26

When any part of the equipment is removed for repair"and replacement, make sure that all leads
or wires which are unsoldered, or otherwise disconnected, are legibly tagged or marked for
identification with their respective terminals. Replace defective components only with parts
of equal or better quality and equal or narrower tolerance.

Spare Parts
Each user of the PDP-7 system should establish a spare parts stock which is in accordance with
the extent of the available repair facilities. The following considerations will be of help in
determining what spare parts should be stocked.

Teletype
Users who do not have maintenance personnel trained in the maintenance and repair of Teletype
units should keep a complete Model 33 Keyboard Send Receive Teletype near the computer. If
the on-line unit becomes defective, the spare should be substituted to avoid computer downtime.
However" many users do have facilities for the maintenance of Teletype units. It is suggested
that such users should stock the spare ports listed in Table 10-5 end the Teletype maintena~ce
toots listed in Table 10-6.

FLIP CHIP W\odules
All users should stock a minimum of one spare module of every type used in the PDP-7 system.
A list of these modules is given in Table lO-7~ When a marginal check or other troubleshooting
procedure reveals a faulty module, that module should be withdrawn from the unit and the spore
substituted in its place. The defective module should be returned to DEC for repair or replacement. Module repair service is offered by DEC at a very moderate cost.
Users who have adequate maintenance personnel and faci! ities may wish to repair defective
modules, at least to the extent of replacing defective semiconductors; more extensive repairs
are not recommended. Such users should stock the sem iconductors and integrated circuits listed
in TablelO-8asaminimum.

Experience with the system will show what other semiconductors

could usefully be stocked.

10-27

Miscellaneous Parts
Table 10-9 contains a I ist of miscellaneous parts useful in the maintenance of the PDP-7.

TABLE 10-5

SPARE PARTS FOR PRINTER KEYBOARD-MODEL KSR 33

Quantity

Item

Part No.

1
2
2
1
2
1
1
1
1

Circuit board
Tape fee sprocket
Lever, universal
Fuse (3.2 amp)
DIstributor brush
Dust cover
Dust cover spring
Power pack assembly
Bel t gear

181821
183071
180086
120167
180979
183067
183068
182134
181420

Vendor*
Teletype Corp.
Teletype Corp.
Teletype Corp.
Teletype Corp.
Teletype Corp.
Teletypl?; Corp.
Teletype Corp.
Teletype Corp.
Teletype Corp.

* All items are available from the Digital Equipment Corporotion or from the Teletype Corporation.

TABLE 10-6

TELETYPE MAINTENANCE iOOlS

Quantity

Item*

Part No.

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

8 oz scale
32 oz scale
64 oz scale
set of gauges
offset screwdriver
offset screwdriver
8 crochet hook
12 crochet hook
spring hook push
spring hook pull
screw holder
handwheel adaptor
handwheel
contact adjustment tool
gauge

110443
110444
82711
117781
94644
94645
151952
151959
142555
142554
151384
181465
161430
156170
180587

All items available from Digital Equipment Corporation or Teletype Corporation.

10-28

TA8LE 10-6· TELE·TYPE MAINTENANCE TOOLS (continued)
Quantity
1
1
1
1
"1
1
1
1

. Item*
gauge
bending tool
gauge·
extractor
tweezer
tommy wrench
tommy wrench
key lever remover

Part No.
180588
180993
183103
182697
151392
6617
73404
151383

* All items available from Digital Equipment Corporation or Teletype Corporation.

TABLE 10-7

PDP-7 MODULE LIST

Type

Name

8104
8105
8113
8115
8117
8124
B171
8201
8204
8210
8360
8602
B620
B684
GOOl
G002
G201
G202
G60l
G602

Inverter
Inverter
Diode Gate (2-input negative NAND)
Diode Gate (3-input negative NAND)
Diode Gate (6-input negative NAND)
Inverter
Diode Gate (6-input negative NAND for DS)
Flip-Flop
Four FI ip-Flops
PDP-7 Accumulator
Delay with Pulse Ampl ifier
10 MC Pulse Ampl ifier
Carry Pulse Indicator
Two Bus Drivers
DC Sense Ampl ifier
Master SI ice Control
. Inhibit Driver
Memory Set ector
Memory Set ector Matrix
Memory Selector Matrix

10-29

TABLE 10-7

PDP-7 MODULE LIST (continued)
Name

Type
G800

ROO2
R107
Rlll
R141

R201
R202
R203
R302
R601

R602
R603
R650
WOOS
W020
W021
W040
WSOl
WSOS

V'l/607
W640
1404
4225
4303
4407

4706
4707
728
738

739
778

779
832

Control for 739 Power Supply
Diode Network
Inverter
Diode Gate (2- input negative NAND)
Diode Gate (7 two-input negative AND gate NOR combined)
Flip-Flop
Duol FI ip-Flop
Triple Flip-Flop
De lay {one-shot or rnonostabl e mu I tiv ibrator}
Pulse Ampl ifier
Pulse Ampl ifier
Pulse Ampl ifier
Bus Driver
Clamped Load Resistors
Indicator Coble Connector
Signal Coble Connector
Solenoid Driver
Schmitt Trigger
Low Voltage Detector
Pulse Amplifier
Pulse Ampl ifier
Variable Clock
Eight- Bit BCD or Binary Counter
Integrating One-Shot
Crystal Clock
Eight-Bit Teletype Receiver
Eight-Bit Teletype Transmitter
Power Supply (+10 and -15)
Power Supply (0-20 marginal check supp·'Y) .
Power Suppl y
Dual lS-V Power Supply
Power Suppt y (one 10v and three 15v floati ng suppl ies)
Two-Step Power Control

10-30

TABLE 10-8

SUGGESTED SPARE SEMICONDUCTORS*

FLIP CH IP Series

Transistors

Diodes

-A Series Modules

C1-106
DEC999
21'~ 1304
2N1305
2N1305B
2N1305W
OEC2219
DEC2894-1
DEC2894-3
DEC3009
NS-3033-3
NS-3033-5
NS-3033-9
21'J3608
2N456A

0-007
0-662
0-664

IrSeries Modules

SOA-8
16J1
OEC2894-1
OEC2894-3
2N2904
2N3009

0-662
0"':664
0-668
1 N750A
6.8AZ5

R Series Modules

OEC2894-1
OEC2894-3
0£C3009
OEC3639

0-662
0-664
1N74B

W Series Modules

16J1
2N398A
2N1184B
OEC1305
OEC2894-1
OEC2894-3
OEC3009
2N3568
4JX1C741

0-003
0-007
0-662
0-664
0-668
0-670
1 N1217

*A quantity of four of each transistor and diode is recommended until the user can determine
quantities by ause-rate figure.

10-31

TABLE 10-8

SUGGESTED SPARE SEMICONDUCTORS* (continued)

FLIP CHIP Series

Trans istors

G Series Modules

SDA-6
SDA-8
DEC999
DEC1008
DEC2894-1

Diodes

D-662
D-664
D-670

lN429

2N3110

* A quantity of four of each transistor and diode is recommended until the user can determine
quantities by a use-rate figure.
Val idation Test
Following the replacement of any electrical component of the equipment, a test should be performed to assure the correction of the fault condition and to make any adjustments of timing or
signal levels affected by the replacement. This test should be taken from the preventive maintenance procedure most appl icable to the portion of the system in which the error was found.
For example, if a filter capacitor is replaced in a section of the 728 Power Supply, the ripple
check for that section shou Id be repeated as spec ifi ed under Power Suppl y Checks.

If repairs

or replacements are made in an area wh ich is not checked during preventive maintenance, the
appropriate diagnostic program (Maindec) should be run or an appropriate operational test
should be devised. For example, if a flip-flop is repaired or replaced, the register or control
function performed by the flip-flop should be completely checked by manual setting and clearing, by improvised programmed exercise of the function, or by performance of the appropriate
d iagnosti c program.
When time permits, it is suggested that the entire preventive maintenance task be performed
as a val idation test. The reasons for th is are:
1. If one fault has been detected and corrected, other components may be
marginal.
2. While the equipment is down and available, preventive maintenance can
be performed and need not be scheduled again for four months (or the normal
period) •

10-32

Corrective maintenance activities are not completed until they are recorded in the maintenance
log. Record all data indicating the symptoms given by the foul t, the method of fault detection,
the component at fault, and any comments which would be helpful in maintaining the equipment in the future.

10-33

CHAPTER 11
ENGINEERING

DRAWINGS

This appendix contains reduced copies of DEC block schematics, circuit schematics, and
other engineering drawings nceessary for understanding and maintaining this equipment. Only
those drawings which are essential and are not available in the referenced pertinent documents
are included. Should any discrepancy exist between the drawings in this chapter and those
suppl ied with the equipment, assume that the latter drawings are correct. A complete listing
of the drawings in this appendix is presented in the table of contents.

DRAWING NUMBERS
DEC engineering drawing numbers contain five groups of information, separated by hyphens.
A drawing number such as BS-0-9999-1-5 consists of the following information reading from
left to right: a 2- or 3-letter code specifying the type of drawing (8S); a l-Ietter code specifying the original size of the drawjng (D); the type number of the equipment (</999); the manufacturing series of the equipment (1); and the drawing number within a particular series (5).
The drawing type codes are:
BS, block schematic or logic diagram

Ml, module list

Cl, cable list

RS, replacement schematic

FD, flow diagram

WD, wiring system
CIRCUIT SYMBOLS

The block schematics of DEC equipment are multipurpose drawings that combine signal flow,
logical function, circuit type and physical location, wiring, and other pertinent information.
Individual circuits are shown in block or semiblock form, using special symbols that define the
circuit operation. These symbols are similar to those appearing in both the FLIP CH IP Modules .
Catalog cmd the System Modules Catalog but are often simplified. Figure A1-1 illustrates
some of the symbols used in DEC engineering drawings.

11-'1

NON-STANDARD SIGNAL

-----00

GROUND LEVEL PULSE

.NEGATlVE PULSE

-----0

GROUND LEVEL

•

NEGATIVE LEVEL

-----OC>

LEVEL TRANSITION USED AS A PULSE
OR TRIGGERING ON THE LEADING EDGE
OF A GROUND LEVEL

------11(>

TRIGGERING ON THE TRAILING EDGE
OF A PULSE

-15V LOAD RESISTOR CLA~PED AT -3V

,~ ,-+
2

PNP

TRANSISTOR INVERTER

t. BASE

2. COLLECTOR

3. EMITTER

-v

Figure 11-1

DEC Symbols

11-2

GROUND -LEVEL NAND, NEGATIVE-LEVEL
NOR DIODE GATE

-v

GROUND-LEVEL NOR, NEGATIVE -LEVEL
NAND DLODE GATE

t. PULSE INPUT
2. CONDITIONING LEVEL INPUT
3. PULSE OUTPUT
2
DIODE·-CAPACITOR-DIOOE
GATE

PULSE INVERTER

PULSE AMPLIFIER
t. PULSE INPUT, POLARITY INDICATED
BY INPUT SIGNAL
2,3. TRANSFORMER -COUPLED PULS~
OUTPUT. EITHER TERMINAL MAY
BE GROUNDED

8
FLIP-FLOP (MOST FLIP-FLOPS HAVE ONLY SOME
OF THE FOLLOWING):
I. DIRECT-CLEAR INPUT
2.GATED~LEAR INPUT
3. DIRECT-SET INPUT
4. GATED'SET INPUT
5. COMPLEMENT INPUT
6. OUTPUT LEVEL, -3 V IF 0.0 V IF I
7. OUTPUT LEVEL, 0 V IF 0, - 3 V IF ,
8. CARRY PULSE OUTPUT,UPON BEING CLEARED

o
2

!
DE

t=::
Figure 11-1

DELAY (ONE-SHOT MULTlVIBRATORl
I. INPUT PULSE
2. OUTPUT LEVEL,-3V DURING DELAY
3,4. TRANSFORMER-COUPLED PULSE
OUTPUT. EITHER TERMINAL MAY
BE GROUNDED

DEC Symbols {continued}

11-3

LOGIC SIGNAL SY0BQLS

DEC: standard logic signal symbols are shown at the input of most circuits to specify the enabling conditions required to produce a desired output. These symbols represent either $tandard

DEC logic levels, standard DEC pulses, standard FLIP CHIP pulses, or level transitions.

Logic Levels
The standard DEC logic level is either at ground (0 to - 0.3v) or at - 3v (- 2.5 to - 3.5v).
Logic signals are generally given mnemonic names which indicate the condition represented by
assertion of the signal. An open diamond (--<» ind,icates that the signal is a DEC logic
level an~ that ground represents assertion; a solid diamond (

~ indicates that the signal

is elso a DEC logic level and that - 3v represents assertion. All logic signals appl ied to the
conditioning level inputs of capacitor-diode gates or diode-capacitor-diode gates must be
present for a specified length of time (depending on the module used) before an input pulse

will trigger operation of the gate.
Standard Pulses

DEC standard pulses are 2.5v in amplitude with reference to either ground or -3v,.depending
upon the type of module used. The width of standard pulses is either 40, 70, or 400 nsec as
required for specific circuit configurations. The standard 2.5v negative pulse (-2.3 to - 3.5v)
is indicated by a solid triangle (----It- ) and is always referenced with respect to ground, as
shown in Figure A 1-2.

GND-------

-2.5V -

-- -

PULSE

r-WIDTH-t1

Figure 11-2

Standard Negative Pulse
11-4

The standard positive pulse is the inverse of the negative pulse and is indicated by an open_
triangle (---t». The positive pulse goes either from - 3v to ground or goes from ground to
+ 2 .5v (+ 2 • 3 to + 3. Ov) •

FLIP CHIP Standard Pulses
Two types of pulses, R series and B series, are utiliz.ed in FLIP CHIP circuit operation. The
pulse produced by R-series modules storts at -3v, goes to ground (-0.2v) for 100 nsec, then
returns to -3v. This pulse is shown in Figure Al-3.

10 0/0

-O.2V - - -

,~_____ L - - 1

-3V

,- - -

-I--~I------

r--- 'OONSEC~

r--<400NSEC

Figure 11-3

FLIP CHIP R-Series Pulse

The B-series negative pulse is 2.5v in amplitude and 40 nsec in duration and is similar to the
one shown in Figure Al-2.

If this pulse is applied to the base of an inverter, the inverter

output will be a narrow pulse, similar in shape to the R-series standard pulse. The B-series
positive pulse, which goes from ground to +2.5v, is the inverse of the B-series negative pulse.

Level Transitions
Occasiona lIy, the transition of a level is used at an input where a standard pulse is otherwise
expected and a composite symbol (

.~ is drawn to indicate this fact.

The triang Ie is

drawn open or sol id depending respectively on whether the positive (- 3v to ground) or the
negative {ground to - 3v} transition triggers circuit action. The shading of the diamond either
is the same as that of the triangle to indicate triggering on the leading edge of a level, or is
opposite that of the tr·iangle to indicate triggering on the trailing edge.

Nonstandard signals

{power supply outputs, cal ibration reference levels, etc.} are indicated by on arrowhead
(--..) pointing i~ the direction of signal flow.

11-5

COORDINATE SYSTEM
Each engineering logic drawing is divided into 32 zones (4 horizontal and 8 vertical) by mar!ginal map coordinates.

Figure references in the text are usually followed by a letter and a

digit specifying the zone in which the referenced circuit is located.

Physical reference to a

drawing area such as ·'ivwer left ll or "upper center" may also be used.

MODULE IDENTIFICATION
Two designations appear in or near each circuit symbol or inside the dotted I ine surrounding
multiple circuit symbols shown on engineering drawings. The upper designation consists of
four characters which specify the module type. Modules are identified by this designation in
the Digital System Modules Catalog while FLIP CHIP modules are described in the FLIP CHIP
Modules Catalog. Modules not described in the catalogs are described in this manual or in
other referenced pertinent documents.
The lower designation is the module location code. The leftmost character of this designation
is a number indicating the cabinet in which the module is located. The next character is a
letter indicating the mounting panel in which the module is located. The last character consists of one or two numbers specifying the module location within the mounting panel. As an
example, the designation lA22 indicates that this module is mounted in location 22 of mounting panel A in cabinet 1. Terminal J of this module is designated at lA22J.
Module mounting panels which can accommodate more than one row of modules may be used
in the construction of certain equipment.

For this equipment, a letter is assigned to each row

of modules within a mounting panel. When a particular device is contained within one cabinet, the number 1 may be om itted from the reference designations appearing on the associated
drawings for that device.
Certain modules are indicated on engineering drawings by the normal 4-digit type number
followed by the suffix R or by c number and R. These modules contain removable jumpers
that connect certain output terminals to clamped load resistors. The suffix R indicates that all
clamped load resistors on that particular module are used; and since replacement modules are
shipped with all.clamped load resistors connected, a new module can be substituted for the

11-6

old without any modifications. A suffix such as 2R indicates that the two clamped load resistors connected to output terminals designated by letters closest to the beginning of the alphabet are to remain connected. All remaining iumpers connecting clamped load resistors to
output terminals are to, be removed. As an example, the designation 1103-3R indkates that
the iumpers associated with output terminals H, L, and P of a Type 1,103 Inverter module are
to remain connected, while the iumpers associated with output terminals T, W, and Z, are to
be removed. The standard Type 1103 is thereby modified into a Type 11 03-3R.

EXAMPLE
Figure A1-A illustrates DEC symbols and nomenclature. The circuit shown is a Type 4303
Integrating Sing,le Shot used to control the enabling time of several gates. The module is
located in the twelfth position from the left {when viewed from the front or wiring side} of
mounting panel B (the second row of modules from the top) in cabinet 1. The symbol marked

DELAY is a monostable multivibrator with two complementary outputs, terminals LJ and W.

The output at terminal U is connected to terminals 2D18F and lB15M while the output at
terminal W is connected to terminal 1D02F.

TO lB15M
TO 1D02F

SAFE
TO 2D18F

4303
I 1812
1

U W-

DELAY

I
I

lC12H
START
lBl1J

VARIABLE
D

SAMPLE
lC21Z

L ____

R5 'lOKQ
TIME

Figure 11-4

OPEN
lB13H

Typical DEC Logic Block Diogram

11-7

01.11

REO~----'-----------~~----------~~------~~--------~HJ+IOY

-~~~~~~------~~------~------------~------------~----~----~~------~O-I~

• HEYMAN MFG. CO.
TAB TERMINALS

..o"E:

IN ORDER TO KEEP OUTPUT VOLTAGE WITHIN THE FOLLOWING LIMITS:
+IOV: +9.5 TO +IIV
-15V: -14.5 TO -16V
THE LOADING SHOULD BE WITHIN TI'E FOLLOWING LIMITS'
BOTH SIDES
+ 10 V () TO 1.0 AMPS
LOADED
- 15 V 1.0
TO
8.0 AMPS
ONE SIDE
+ IOV 0 TO 7.5 AMPS
.LOADED
-15 V 1·0
TO
8.5 AMPS
~g~A~roJ~E5t~~T:Ulll~U~!jns ARE LIMITED BY THE FOLLOWING

CONVERSION CHART ----.

Power Supply (+10 and -15) RS-B-728

RE~

FI
MDX 5AMP
SLO-BLO

REO

CZ
3!!,oOO

25V
MFD

2!lW

8LU

HEYMAN TA8 CONNECTORS
CINCH JONES TERM. STRIP

BLU

-----§-O;---f=---F--- - - - ----c>-----f""
TRANSISTOR

a DIODE CONVERSION CH"'Rf~_

,"
---- --'-----_.~
---.------l --- -_
-----_
....-.--_._- .---- .. --.-------- ---- _._--- .
-----'-'- -.-.- .....
- - - - ---------- --- - - ---- -.- ." -- .- -- -.•.

~---

--:-

Power Supply (0-20 marginal check supply) RS-B-738
11-8

01
IN320e

INO.I4110---_..,..... . . III'-..

REO

.-____________

-0
.~--------~~------~~~~~O~--~---------+---_o

+
0-

Co2
35,000

""0
211\1

02
IN3201

•

C3
35,000
.. FO

IBY

I-lAMPS

211v

"'~~8R~N~--~------~------~~------~~k~U----~-------1~--o

PRIMARI£S
TWISTED
RED a WHT

8LUE

T2
DEC
T-41513

BRN

-0
-0

03
IN3208

-0

REO •

~------------+--------4~-------+--~~--~------~~--O

C4
3!l,000

MFD

211v

D4
IH3208

.. HICY"'AN NFG. CO. TA8TERIlIINAL IN PLASTIC BUSHINGS

CI
3~OOO

IoIFD
25V

ISV 1-8A1oiPS

BRN

C::J CINCH 'JONES TERNINAL STRIP

:.tj" '''J1t~ld

t ..

- ,"
! _. __ ' _

IILU •

-0
-0

-.-.~

_. . -." ".
RT

',010. DE CONVERS,ION., CH,
, ,
:-..iiiOi
_ __ _ --- ~-' ...
" , .. -- .-- _ ..
-.
-

-~.

~.- -'~:=~'.

Dual 15-Volt POlwer Supply RS-S-778

UNLESS OTHEItWISE INDICATED
HEYMAN .. FG CO TABTERNINAL IN PL.ASTIC BUSHING

*
c:J ClINCH JONES TER,MIHAL STRIP

."--_. ._-""Jt'"
.- .+
TRANSISTOR 8< DIODE CONVERSION

!!,~!9'~

Iii-Sib.-

--'--"-'-'

.... - ....

_.-

-_. ._-

__ • __ , --.

---

...

- - .. ~=-- .. - .

CH~ART
,

_" .-,----

"."

--. .-

Power Su;pply (one lOv and three 15v floating supplies) RS-S-779
'11-9

-I'

1'-;'"\ ACME
:1\14\I .......
I I

FAN

I ag OED ~6~~D

1 13

r--

T-1-~7109
IDEC #1(24)

~1~~1'O% I

,-------I-n
-

TI
EXMA..E

~'~~G

I
I ~

....:./
JONES
STRIP

RED

DRN

YEL

2f !I wsl i'

BlU

AC
SUPPllEO WITH
TRANSfORMER

I1"X=~--~~~--~r"I----~
GRN-YEl

IP 3

I~
I~

ORN

BRN

03'
BRN-YEL
8LU-YEL

II~ REO- VEL
'i~14

WliT

SLU-YEL

IIi?

GRN

I
I

liGAN - VEL
R4
50
25W

ORN

10"10

:;>

)

O
I:aW
I "IoMF

)

0 -

3 AMPS

i
I
II

I
I

)

35 - 55 v

I
I

RII

~~.~ n~KI
"?2W

BLU

~o03 QvMfD
r __-:.;.A=.E..J.:..AO:::;....:;A;.:,;H:.-x:B:..;.T--L:SP::,--ICISBU=_..J.B::.;K"--I..:.;A.::,.Jt;!AF~-'"':>--...... W:H~J.~ I
IOVIAI A ().
"REO
~ AA
1 ~- 5 10.K. SIGNAL
V---------.-----t---II---+-----t-------'-B;;.;:L:.:;U--<::~>--A"""B-I
BN,...
I ~~-I6 I }
INHIBIT POSITIVE TEMR COEFF.
;;:"'

-i-1

-15'1

GND

co_------+---t-....-II-....- -....-------li!loA-<::~)-...!~

{

INHIBIT

POWER SUPPLY CONTROL GaOO

At.

RI K

?R 2
50
25W

?R6

50
25W

;'~OO ':=~C6

GRY

i~(;8

12G~/. : INDICATED

CAPACITORS ARE 9,OI)O',IOOV i MFD
DIOGES ARE IN 3212
TRANSISTORS ARE 2N3716
KI IS 115vAC POTTER 6 BRUMFIELD
KRP IIAGRELAY

~~~o

+
~::: ~J~o

:I·

~C)I

BLI<

;;:r:.~&MF 0

05
IN4001

;

~~~.I~~IO~o~~----~>__......~I_----~~B~lU~~3

~.19 ~'*KI

R13:

I YEL-

REG

UNLESS OTHERWISE

•

YEl

Td~I~At.:

I
I

VEL

i ~ I}'

r-~--~----~~~~~~I--~_

I ~ RED-YEL

·IIII.~ :::-

r----'

'---+~"*-~-A-IEi

~T IsP IBu

>BI< C)AJ

50V

~I
BN

R E AD/ WRITE POWER SUPPLY G BOO

I BlK/ 8
!I GRY]
RI2

III}
I

L..---....

JONES
STRIP

Power Supply V~ory) RS-C-739

25'Y~

40 - 60'1
0 - 2 'AMPS

I
I

I}
I
I

I
--e>---------(>-~L______________j_B-M--"o--TGBRRNy/-<.J
I
~
L:~=-9_J
AC

33~.!

THERMISTOR,
10"10 AT
I CARBORUNDUM PT. NO. A 09 05P - 8
OR EQUIVALENT)

R/W POSITIVE TEMP. COEFF.
THERMISTOR, 330""', : 10% AT 25"1c
I CARBORUNDUM PT: NO. A 0905 P-8
OR EQUIVALENT I

.....-----------_o

r------------~~----.:...

A .10 V (A I

r--------~----+_-------_1~----_oC

GNO

7,500

Q2
DEC 2894- 3

TRIMPOT
SOJRNS

5,000

01
114M 6.8 AZ5

R3
68,000

R4
6,600

10%

Fj5
1,000

~-------------~~-~~-----------------~08-eV

UNLESS OTHERWISE INDICATED:
RESISTORS ARE 1I4W, 5%
DIODES ARE 0 - 6,6-4

NOTES

.,]V.IO%

Low-Voltage Detector (for 739) RS-B-W505
R3
5,600
2W

Rle
10,000

It4W

TO POSITIVE

RI7

MFO
50V

II4W

0.1

COEFF. TliERMISTCR
330AAT 25/"c

~FOOO
8P

RIS

1,000
BOURNS

08
1H429
6.2V
S,.

R6
6,980
MF
II8W

RIS
2,000

~~OO

I/8W
- 8K
AA. JOVIA)

R5
1,200
5%

560
I12W

RII
1,000

10.000
5%

C2
.01

MFO

5,.

RJ,4
47
2W

470

Q4
DEC2219

L..---_O
012
0-664

TO SERIES
REGULATOR
8AS£

RI3
10,000
09

UNLESs OTHER'h1SE INDICATED'
RESISTORS ARE 1/4"'; 10,.
DIODES ARE 0-6S2
III,. RESISTORS ME I,. i 100 PPM

112W
...._ ....!!::[).;;;:6:..:::64~_·_41-O O.K.
-----------r--------~-----oAE
SIGNAL
R4
RI2
RI
226
7,500
011
560
MF
V2W
0-664
VN
L - -_ _ _4~___- + ___- - - - - - - - - - - + _ - - - - - _ + - - - - _ o 8 - 1 5 V
_.------------_.-----~~----vc OND

_________________

Control for 739 Power Supply RS-B-G800

'11-11

#18 aLI<

------------------------------------------------------------------------~----~GNO
CI

REO r --

o-----____~-------------------~--14-R~E~O~----._----------------------------~~

}

Cl~~i~~+_~~~~orc~._----~------------------------------~----------------~----------~----_*~~~~~~ ~~~YO~F
WHTI

#14 WHT

S'TERIoI
JONES STRIP
W541-6

NOTES:

g:,~;'OAi9:o~i~~CJ~~ Ig5d~~~L .,iy~~TI~lglI 20SP 4B4,II511
CORNELL OUBLiER.
C2 a C3 CAPACITOIII BATHTUB-OEC PURCH.. SPEC WCAF-OOOI
ZX.I~FO 600VOC C~OjELL DUBLIER.

~~ +g~~ti ~::+g~ ~~~5~PpOS

*"7505-1(3
1<1 RELAY#I040'S-SS7 NORMALLY OPEN 11511AC COIL
SEC DELAY
QUICK OPERATE. SLOW RELEASE,
1<2 RELAY ... ,040-8-58 NORMALLY OPEN 11511AC COIL 3-5 SEC DELAY
SLOW OPERATE QUICK RELEASE.
1<3 RELAY .... EM-I IISVAC EBERT ELECTRONICS.
cal CIRCUIT BREAKER ""190-220-101 ZOAMPS 2:1011, eo eYe-CURVE .4

TRANSISTOR

3·'

a. OIOOE CONVERSION

Two-Step Power Control RS-B-832

----------~---~~----------------------------------------------------------~JC OHO

__________~--__ +_------._------._--------------~._--------~------~-----------OV+~NlfaEO

•

010
1N429

05
0-662

0-&62

~--~~--~--------------------~------~--_.--~
UNLESS OTKERW'SE INDICATED'
RESISTORS A"tE 114W",IO'"
RS, RIO a R16 ARE 'TEI.- LAB

TRANSiSTOR !r DIODE CO!>jVERSIO~

:~~B~_U:::c

"OT[5

.. ~.5v 2~O 0", .., 5-1.

~~~__~:t~~~~~:~1.~~~~~·~_.~_~_L_--__- -_-__:_~.l_______.__________________________~

11-12

•

I",.Z.

0-662

0-862

__----------------~----------~a-l5V

81T1
R43

81T ..

B'T3

relT
R602

I~, !O'!lt

R11

100

1elT
RIOl&

R89

100

I!J._~ ___.--'o

......______

]BIT
RI248

100

~VIT'
RI!>2

]elT
RI421

100

100!

'fW",

I'"~::::::::::;9-:;;1;...Jcr~-~·-+"1"+)-..'-_-_-_--_-_B:::.:I~T..:;=-·!-_-_-_-_--.°t-_~c.
...----------.:::8!..!IT.....:;::..Q-~-------(..,>-_t<,--p_---!e~I~T...:'::..-~_~---.H_-fc:>-'t-----------....e:.:.I~T~""'-'-k----t+-_H)-~-------_-....:e'""I.!..T...::~:..~_-_-_-"'1·H_-<~-+crt---------.:::B.:..:IT'-I;:..!o-_--_-t+~--I~"t-·-_-_-_-_--"'el....T-'8...-_-_-'1--I-<~I--'1r-A-o~VIA'

·;'"QI6--Q-I!>"-r-~b4'"":-t:~-Ir-o-J--+t-~re-~-5"J1.-9·Q-I-4-Q-'3"""R-F-o~-<H-~-+t-~-1O-%""Q-I2-Q-;IIt-RI-:4-%t-t(--t-Ir-68-~~-8:""'0-1O-0-9"68-~-:-2-t-t--+t-M-~-%""Q-8--0~1~R-,I-IO-,:H---HM}1-~-ik-23"""Q6--Q-5"'~~-'~-~-I:>+-t-I:t-M-~-'4I""'Q4--Q-'
-~-~-4!>-I(H---t~-tr-~-~-:

;

R58

1140

R44 OIB
017 Ar.

~~ 014

« <

R4!> ~

( R41

....

R13

R51

>-R81

R91

?R72 029 •
R86
02B A.. IL 030

~_ 019

ROO 034
033.

<,.

RI26 ~

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RI09

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a'1

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R108
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<
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(

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......0-2-0-1

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0!>8

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061

...

060,.

.!i.

R39
R67
RI03"~
t-r-~~E:::~~fJ~~;;;;;t~~~;d;g~~~~~==:~AA~A~ji~~~;;~;;~R~Q~4~dg~~~==l===~~:Eft~~;;~~~R~iZ~O~_~~~~~~~~A~~A~A~tt::::::=l========JJ~ll~

-I!>Y

lil37

R55 ~

CII

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:A~016 .0f'S;" r-.~17
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66,000

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(R28

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RZI

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(rE!568f~~020 .~~

Reo

R22

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A30

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0l!,

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...

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024
<
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AI46
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~

2l-0~T
C
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2200

Ti2bo

RII

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r O-662 ;> 112W

O!>

RI2

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r

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IN

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L~ r-jb~
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R20
~
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Q37
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RIS C

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>
>

R29

UNLESS OTHERWISE INDICATEO:
RESISTORS ARE 3POO OHMS
RESISTORS ARE 114 W
RESISTORS ARE 5%
CAPACITORS ARE MMFO
OIOOES ARE 0-664

CO~\IfO

01
OS
CLOCK

()l'
DATA

.p
ENABLE

ACTlVE

RI
I,!!OO

0---<)0- ",~T-'I--'-"""""r
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..
067
a.J

......

066

ir:SNiAl~~~iL~~iR~::l~~ORP *1162

REf 89-4701

RI28

~.OIO

TRANSISTOR .. DIODE CONVERSION CHART

Eight-Bit Teletype Receiver RS-C-4706

c,y_
.01 MFD

D53

R158

OUT 3

OUT 4

r---r---~~~~~r---f---~~-'~~r--'~--~~-'~-1~~~~~~~~~~--f~~~--~~-f---f---1~--~~-f---f---'~--~~-f---f---t~--~~-r-,~-oOCGNOI

045

0-662

046

0-662
047
0-662

L+~~----iH~----~ ~~---+±1-----41-+4~---+~-----4i-~-----~-+---~~~~----~+---~~~~--

r-t----../V\.~_+.....

__~~~~~~~---1~r---~~+4~~--rr~---<~-15V

o.a

0-662

C!IO ~r
6 tiD

I
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059

OUTPUT

W
OUTPUT

CLOCK

UNLESS OTHERWISE INDICATEDRESISTORS ARE 3,000
1,000 1,500 e. 3,000 OHM RESISTOl\S ARE 114Wi 5%
ALL OTHER RESISTORS ARE 114 W; 10%

5
CLEAR

FLM

DIODES ARE 0-664
TRANSISTORS ARE 2N 1154

iF-~;:IiZ:~s~~EE~~tgNICS CORP#1762
REF as 4701

Eight-Bit Teletyp

)nsmitter RS-C-4707

r---------"--------------------------------~--~~--------------------------------------------------.-------~ ~D

--~-------------4~---------------~r---~------·-t~-----e-----------------.----------e------4~----------<lV.IDVNI F~

l~ I"~'

03
'0-662

SLICE
LEVEl..

RI
41

UNLESS OTHERWISE INDICATEDRESISTORS ARE 114W;1O'1o
RO,IOOIlRI6 ARE"TEL-L.AB

Master 51 ice Control R5-B-G002

------....--.-------------~------------~--------.------------------------------~--------------------------------OA+l0VIAI

0120

R29

:e
N

o
STACK
SELECTrON

Jo-....-.I f-.-.-+-r
INHIBIT

RETURN

~--------------------+-----------_4~~~--------OR

:r----.---------------4_--"--------~--------------------------4_-----------~~------------_oT

' - - - - * - 0 U T. p.

RI
El80

RI2
6BO

RI4
680

RIS
470

UNLESS OTHERWISE INDICATED:
RESISTORS ARE 1/4W; 10.,.
CAPACliORS ARE MMf'D.

Inhibit Driver RS-B-G201

11-17

R21
680

R23
680

R25
470

R27
470

--~----------~,---------------,-----------~----------------------~-------oA+'O~1

--~------------~--~r---------+------------f-------------------------------{)C GNO

06
0-662

05
0-662
WRITE

'---II~"""-OJ

C9
R35

2,200

R3E1 f-OI

2,200 MFD

5'11t!i%

04
0-662
03
0-662

680

~-'---~-------------4~--

--------------~--~r-------------~'---~------------~r---~------~~15V

TRANSISTOR & DIODE CONVERSiON CHART
.Il

Memory Selector RS-B-G202

11-18

r
I
!

t-Ho-+--_--~

1_ 70-+-_--1-..

T19

v~~5-;I

T2~'%)21

~2S

PUIG I

PLUG 2

036

I-FO-+--_____

2-~

Ds2

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1-6 o-+-_...+~

VIEW FROM
aJUPOHENT SlOE

PLUG

PLUG
4

1- Eo--t--_--~

1- So-+-_-+--.

PUIG S

::~O~i
•
i
7

=T5

.!!2.It;
LETTERS OF PLUGS ARE ON PRINTED
CIRCUIT SlOe: OF BOARD.
NUMBERS ARE ON CCIol~ENT SlOE

OFEIOARO-

EXAMPLE

I-e

1-3

~CO-+--

__- - _

1-3 O-+-_-+--.

FIRST HUIIISER (f l REFERS TO PLUGS.
SECOHO LETTER (e) OR H.... 6ER (3)
F<EFERS 1"0 PINS.

1-8~
I~
1-2
I

L.u.J

=T3

•

UNLESS OTHERWISE !~OICATEl>
RESISTORS ARE 2,200,V4W; 10%
DOOES ARE D-664
TRANSlSTOlS ARE DECIOO8
TRAHSf~RS AA:E T-2060

4-i.

Memory Selector Matrix RS-D-G601

11-19

4-K

~-J

4-0

I
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(
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1-11-

PLUG I

I-I!

PLUG 2

1-6o-t-_-+--.

PLUG

I-Eo-+---.----.
I-!I

o-t-.--+-..,

PUIS

LfTTEilS ~ PLUGS ARE ON PRlNTEO
C1'ICI.:IT SIDE OF BOAR D
NUleERS "liE 011 COMPONENT SlOE
OF eoARO.

1- CC-+----.----..,

£XAMP'_E

1-30-+-+--+.....
I-C

1-3

FIRST ICIMeER (II

REFERS

m PLUGS

~~ "fu~:i_CI OR NUMBER f3l

1-80-+---+---,

I-Zo-+-+--+-......
UN..ESS OTMl:ltW1se: INOICATEO:
RESISTORS ARE 2.200; IMW; 10%
0100[5 ARE 0-664
TRJ.NSlSTORS ARE OECIooe

11I4H8fORIoIER3 All E

T- 200&0

1-40-+---..----,

I-ID-+-_-+-....,

TR"NSISTOR II DIODE CON,£RSION CHART

~~~--+"lii?~~
II
C-6G4
-t ;'>G<Je'----H1
[------+-----1
4lQ----P!J.lf~-----+jLI-----+--_-_--l

Memory Selector Matrix RS-D-G602

11-21

I
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BS-D-7-0-28

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MA and PC Registers

BS-D-7 -0-29

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PACKAGES IN Mi::>.
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K.r; I

lOT 7541 (8)

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BS-D-7-0-34
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APPENDIX .1
INSTRUCTION SUMMARY

MEMORY REFERENCE INSTRUCTIONS
Mnemonic
Symbol

Octal
Code

Machine
Cycles

Operation
"Executed

CAL

Call ~ubroutine. The address portion of
this instruction is ignored. The action
is identical to JMS 20.

DAC Y

Deposit AC. The content of the AC is
deposited in the memory cell at location Y.

JMS Y

1()

Jump to subroutine. The content of the
PC and the content of the L is deposited
in memory cell Y. The next instruction
is taken from cell Y + 1 •

DZMY

Deposit zero in memory. Zero is d'eposited in memory cell Y.

LAC Y

Load AC. The content of Y is loaded
into the AC.

XORY

Exclusive OR. The exclusive OR is
performed between the content of Y
and the content of the AC, with the
result left in the AC.

ADD Y

Add (l's complement). The content of Y
is added to the content of the AC in lis
comp I ement arithmetic and the resu It is
left in the AC.

TAD Y

Two1scomplement add. The content of
Y is added to the content of the AC in
2 15 complement arithmetic and the resu It
is left in the AC.

Al-l

MEMORY REFERENCE INSTRUCTIONS (continued)
Mnemonic
Symbol

Octal
Code

Machine
Cycles

XCT Y

Operation
Executed
Execute.

The instruction in memory cell

Y is execut~d.
ISZ Y

Increment and skip if zero. The content
of Y is incremented by one in 2's complement arithmetic. I f the restJ It is zero,
the next instruction is sk ipped.

ANDY

AND. The logical operation AND is performed between the content of Y and the content of the AC with the result left in the AC.

SAD Y

Skip if AC is different from Y. The content of Y is compared with the content
of the AC. If the numbers are di Herent I
the next instruction is sk ipped.

JMP Y

Jump to Y. The next instruction to be executed is taken from memory cell Y.

EAE I NSTRUCTI ON LIST
Mnemonic
Symbol

Octal
Code

Operation
Executed

EAE

640000

Basic EAE command.

LRS

640500

Long right shift.

LRSS

660500

Long right sh i ft I signed (AC sign = link).

LLS

640600

Long left shift.

LLSS

660600

Long left sh ift, signed (AC sign = L).

ALS

640700

Accumu lator left shi ft.

ALSS

660700

Accumulator left shift, signed (AC sign = L).

Al-2

No operati on.

EAE INSTRUCTiON LIST (continued)
Mnemonic
Symbol

Octal
Code

NORM

640444

Normalize, unsigned. 'M'aximumshift is 44 S •

NORMS

660444

Normalize, signed (AC sign = L).

MUL

653122

Multiply, unsigned. The number in the AC is multiplied by the number in the next core memory address.

MULS

657122

M.dtiply, signed. The number in the AC is'multiplied by the number in the next core memory
address.

DIV

640323

Divide, unsigned. The 36-bit content of both ,the
AC and MQ is divided by the number in the next
core memory location.

DIVS

644323

Divide, signed. The content of both the AC an'd
MQ as a lis complement signed number is divided
by the number in the next core memory location.

IDIV

653323

Integer divide, unsigned. Divide ,the number in
the AC as an l8-bit unsigned integer by the ,number in the next core memory location.

IDIVS

657323

Integer divide, signed. Same as IDIV but the
content of the AC is a l7-bit signed number.

FRDIV

650323

Fraction divide, unsigned. Divide the l8-bit fraetion in the AC by the lS-bit fraction in the number
in the next core memory location.

FRDIVS

654323

Fraction divide, signed. Same as FRDIV, but the
content of the AC is a 17-bit signed number.

LACQ

641002

Replace the content of the AC with the content
of the MQ.

LACS

641001

Replace the content of the AC with the content
of the SC.

CLQ

650000

Clear MQ.

Operation
Executed

Al-3

EAE. INSTRUCTION LIST (continued)
Mnemonic
Symbol

Operation
Executed

Octal
Code

ASS

644000

Place absolute value of AC in the AC.

GSM

664000

Get sign and magnitude. Places AC sign in the
link and takes the absolute value of AC.

OSC

640001

Inclusive OR the SC into the AC.

OMQ

640002

Inclusive OR AC with MQ and place results
in AC.

CMQ

640004

Complement the MQ.

lMQ

652000

load MQ

I NPUT/OUTPUT TRANSFER I NSTRUCTI ONS
Mnemonic
Symbol

Octal
Code

Operation
Executed
Program Interrupt

IOF

700002

Interrupt off. Disable the PIC.

ION

700042

Interrupt on. Enable the PIC.

ITON

700062

Interrupt and trap on. Enable PI C an.d trap
mode.
Real Time Clock

CLSF

700001

Skip the next instruction if the c lock flag is
set to 1 •

CLOF

700004

Clear the clock flag and disaQle the clock.

CLON

700044

CI ear the c lock flog and enobl e the clock.
Perforated Tape Reader

RSF

700101

Skip if reader flag is a 1 •

Al-4

INPUT/OUTPUT TRANSFER INSTRUCTIONS (continued)
Mnemonic
Symbol

Octal
Code

Operation
Executed

Perforated Tape Reader (continued)

ReF

700102

Clear reader flag, then inclusively OR the content of reader buffer into the AC.

RRB

700112

Read reader buffer. Clear reader flag and AC,
and then transfer content of reader buffer into AC.

RSA

700104

Se lee t reader in a lphanumeric mode. One
8-bit character is read into the reader buffer.

RSB

700144

Select reader in binary mode. Three 6-bit
characters are read into the reader buffer.
Perforated Tape Punch

PSF

700201

Skip if the punch flag is set to 1 •

PCF

700202

Clear the punch flag.

PSA or

700204
700206

Punch a line of tape in alphanumeric mode.

PLS
PSB

700244

Punch a line of tape in binary mode.
I/O Equipment

I/ORS

700314

Input/output read status. The content of
given flags replace the content of the as'"
signed AC bits.

TTS

703301

Test Teletype and skip if KSR 33 is connected
to computer.

CAF

703302

Clear all flags.

SKP7

703341

Skip if processor is a .PDP-7.

Al-5

INPUT/OUTPUT TRANSFER INSTRUCTIONS (continued)
Mnemonic

Symbol,

Operation
Executed

Octal
Code
Teletype Key~oard

KSF

700301

Skip if the keyboard flag is set to 1 •

KRB

700312

. Read the keyboard buffer. The content of the
buffer is placed in AC1 0-17 and the keyboard
flag is cleared.
Teletype Teleprinter

TSF

700401 .

Skip if the teleprinter flog is set.

TCF

700402

Clear the teleprinter flag.

TlS

700406

load teleprinter buffer. The content of
ACl 0-17 is placed in the buffer and printed.
The flag is cleared before transmission takes
place and is set when the character has been
printed.

Automatic Pri?rity Interrupt

CAe

705501

Clear all channels. Turn off all channels.

ASC

705502

Enable selected channel(s}. AC2-17 are
used to select the channel(s}.

OSC

705604

Disable selected channel(s}. AC2-17 are
used to select the channel (s).

EPI

700044-

Enable automatic priority interrupt system.

OPI

700004

Disable automatic priority interrupt system.

ISC

705504

Initiate break on selected channel (for maintenance purposes). AC2-17 are used to
select the channel.

OBR

705601

Debreak. Return highest priority channel to
receptive state.

Al-6

INPUT/OUTPUT TRANSFER INSTRUCTIONS (continued)
. Mnemonic
Symbol

Octal
Code

Operation '
Executed

Event
Time
Memory Extension Control

SEM

707701

Skip if in extend mode.

EI:M

707702

Ente:r extend mode.
';

LEM

707704

Leave extend mode.

EMIR

707742

Exte~nd mode interrupt restore.

OPERATE INSTRUCTIONS
Mnemonic
Symbol

Octal
Code

OPR or

740000

Event
Time

Operation
Executed
Operate- group or no operation. Causes a 1cycle program delay.

NC)P
CMA

740001

Complement accumu lator • _ Each bit of the AC
is complemented.

CML

740002

Complement link. -

OAS

740004

Inclusive OR ACCUMULATOR switches. The
word set into the ACCUMULATOR switches is
OR combined with the contentof the AC, the
result remains in the AC.

RAL

740010

Rotate accumu lator left. The content of the
AC and L are rotated one position to the left •

RLR

740020

. Rotate accumu lator right. The content of the
AC and L are rotated one position to the right.

HLT

74()040

Halt. The program is stopped at the c:onc lusion of .the cyc Ie.

SMA

740100

Skip on minus accumulator. If the content of
the AC is negative (2 15 complement) number
the next instruction is sk ipped.

Al-7

OPERATE I NSTRUCTI ONS (continued)
~".

---- - .........__ .. __. -," ·-· ......x·._-.·~,....

JIv1nemonic
Symbol
••.,:::':".

Octal
Code .

·.--::~'-::;:'R :T:'=~_",:;"'::'M:'~"'_' ~.:.:.:.__ ,

_: ~~: .. ~-:<::,:,,"

740400

Event
Time

Operation
Executed

Skip on zero aCCLtmu lator. If the content of
the AC equals zero (2 15 complement), the next
instruction is skipped.

Skip on non-zero link. If the L contains a 1,
the next instruction is skipped.

"'-,

,SKP'·

741000
741100

Skip. The' next instruction i$ unconditionally
skipped.

Skip on positive accumulator. If the content
of the AC is zero (2 1s complement) or a positive number, the next instruction is skipped.

SNA

741200

SZL

741400

Skip on zero link. If the L contains a 0, the
next instruction is skipped.

RTl

742010

2,3

Rotate two left. The content of the AC and
the L are rotated two positions to the left.

RTR

742020

2,3

Rotate two right. The content of the AC and
the l are rotated two positions to the right.

Cll

744000

Clear link. The L is cleared.

STl

744002

2,3

Set link. The L is set to 1.

744010

2,3

Clear I ink, then rotate left. The L is cleared,
then the Land AC are rotated one posi tion
left.

RCR

744020

2,3

Clear link, then rotate right. The L is cleared,
then the Land AC are rotated one position
right.

CLA

750000

Clear accumulator. Each bit of the AC is
cl'eared.

Skip on non-zero accumu lator'. If the content
of the AC is not zero (2 1s complement), the
next instruction is skipped.

Al-8

OPERATE INSTRUCTIONS (c'ontinued)
Mnemonic

Symbc)1

Octal
Code

Event
Time

Operation ..
Executes

CLC

750001

2,3

Clear and comp:ement accu~ulcitor. ":. '£qclL bi:t
of the AC is set to contain a 1 •
. ....

LAS

750004

2,3

Load accumulator from switches. The word"set
into the ACCUMULATOR switches 'isloQded
into the AC.

GLK

7500'10

2,3

Get link ~ The content of L is set into Ac'i 7 ..

LAw N

76XXXX

Load the AC with LAW N.

Al-9

APPENDIX 2·

. MODEL 33ASRlKSR TELETYPE CODE (ASCII) IN BINARY FORM

.. MOST SIGNIFICANT BIT

1 - HOLE PUNCHED - MARK
0- NO HOLE PUNCHED - SPACE

LEAST SIGNIFICANT BIT ~

8 7 6 5 4 S 3 2 1
~-

SPACE

0 0

1---

o 0 0

NULL/IDLE

START OF MESSAGE

0 0

END OF ·ADDRESS

0 0

0 1 0

,C
1---

END OF: MESSAGE

o 0

0 1 1

END OF TRANSMISSION

0 0

WHO ARE YOU

0 0

1 0

ARE YOU

0 0

1 1 0

BELL

0 0

1 1 1

(

FORMAT EFFECTOR

0 0 0

)

, H9RIZONTAL TAB

0 0 1

1---

"",","-

1---

IG
1---

ft-, '

1-I
1---

1---

LINE FEED

0 1 0

VERTICAL TAB

0 1 1

FORM FEED

CARRIAGE RETURN

1 0

1---

-IN

1---

Q
10---

SHIF"r OUT

0 1

o 0
1

1 1 0

SHIFT IN

DCO

1 0

READER ON

TAPE (AUX ON)

1 U

1 0
1 1

--1-

-- R

•

1---

o 0

10---

1 1

0 0 0

0-l-

0 0

READER OFF

1 0

---

(AUX OFF)

1 0

1 0 0

-V

-- -

ERROR

1 0

SYNCHRONOUS IDLE

1 0

7
---...

LOGICAL END OF MEDIA

1 0

1 1 1

1 1

0 0 0

1 1

0 0

1 1

1 0

1 1

!"--

Z
~-

","".L.

-....
I

RUB OUT

1 1

1 0 0

1 1

1 0

1 1

1 1 0

..--

1 1

1 1 1

i--

-.
_.,...

t---

~j~

;,....

4110

'--v-...I'----v-----./

41"

...... 1 0

1 0

SAME

..... 1 1 0

SAME

-".

.... 1 1 1

A2-1

SAME

APPENDIX

SIGNAL GLOSSARY

The following is a I ist of,' the signals used on the engineering drawings for the POP-7o Each
signa I is I isted in alphanumerica I order and the number of the drawing in which it originates
is listed in the adjacent column to the right.
Engineering
Drawing
Number

Signal

ACIO

BS-0-7-0-26

ASC 5502

85-0-172-0-2

AC=()

B5-0-7-0-26

ASI- PC

85-0-7-0-25
85-0-7-0-24

BS-0-7 -0-31,

B
B SET
B SET
8GN

85-0-7-0-22

8GN (B)

85-0-7-0-20

Signal

ACO(O)
through

AC8(O)
ACO(1)

sheet 1

through

AC8 (1)
AC9(0)

BINARY

through

and

AC 17(0)
AC9(l)

85-0-7-0-31,
sheet 2

POS}

AC17(1)
S5-0-7-0-25

ACSO(l )
through

80- D-444B-0-2

BINARY

through

AC1-+ MB

85-0-7-0-34

BK RQ
BK RQ Neg
BK RQ Pos
BK RQ Neg

85-0-7-0-32

85-0-7-0-26

ACS'I7 (1)

CAL

ACO E2U

CAL

and

85-0-7-0-32

CHAN RQ 00

AC17 E19U
ACS1- AC
AC CRY

Engineering
Drawing
Number

. through

CHAN RQ 07
85-0-7-0-26

. 85-0-7-0-25

85-0-172-0-3,
sheet 1

ADD OV

CHAN RQ 08

ALPHA

CHAN RQ 17

sheet 2

CH17 FLG

85-0-172-0-2

and

through

8D-0-444B-0-2

ALPHA-N

A3-1

B5-0-172-0-3,

- - ' ... ".

-.~...' - ' r ..

A4--_ ....... _ . . . .. . . . . . ,.'-. . .' . . . . . . _""' '""_._ .~. . . . . . . ._ .......... __ ......-_"-..--. . . . . . __ . . . "__ _. . . . . .
.., .... ~........~ .~ .. ~....... ,., ..""
-,

"'I

•... - . -

...., -"<1' ... ,,,

.. ~ . . . . . '

......~

Signal

Engineering
Drawing

Number
C1.j(~~.uN!.f{Q (O)

ClK COUNTRQ (1)

Cl1<:' "Et4ABtE ':'(0)
ClK ENABLE (l)
C1;:(<' '(0)"- ',' ,'::
ClK (1)
ClK SYNC, (0)
elK SYNC (1) ,
CLOCK 7- MA

c'ur FLGS' -; ,
CLR FlG 0 '
through
~,L:' fJ,.G 7~:. " ,

ClR flG 8
through

-, ClR fLG 17

....

_.. ,.

f,(. r~'

-,.. w

. 85-0-7-0-32
-<

"-'

BS~D-75P:'~
BS-0-172;0~j,
shee't 1 " "
".

B5-0-7-0-3, ,
sheet 2

COMMON DEBREAK 85-0-172-0-2

CONT

E·AND
E·SAO
E.ADO
E·TAO

85-0-7-0-20

85-0-7-0..;26

E·LAC
E·ISZ - I NT REC
(PC+1 )
ENS NEXT

85-0-172-0-2
85-0-172-0-3,
sheet 1

85-D-7-0-26

EX+EN
and

85-0-7 -0-20

EX+EN+OP+OPN

o
D,SET
o SET

85-0-7-0-24

EXO SW
and

B5-0-7-0-32

DATA·S

B5-0-173-0-2

DATA-S Pos

F
F 5ET
F SET

and"
DATA-S .Neg

85-0-7-0-32

DATA, IN'~:"'"

85-0-173-0-2

DATA INFO-MB

85-0-7-0-32

DATA RQ:;

85-0-173-0-2

through

'85-0-7-0-32

IA3
lA3
180

FLAG FOR'

(CHANNEL 16)

DATA 5YNC (1)

D5C 5604

through

85-0-172-0-2

;' _,~, _.~;>'

85-0-172-0-2

DPtDN

FLG INO

85-0-7-0-24
85-0-172-0-24
85-D-444B-0-2

lAO

DATA 5YN~ (0)

and ,:'

WO-0-7-0-37

EXO(1}

'DATA AOOR-MA

D~K

BS-0-7-0-24

E·IAl

END CRY

-..... .,

E·JMP+PROG B
E SET
E SET
E·XCT

85-0-7,-0-20

. A3-2

183

85-0-7-0-24

Signal
! ' _,r i, <~.' '/1

IC 10(1)

through

' ', ',:: ~.:..,'",::, . :,:" '~''':;'~-''~~''' :' ~"'-':'~"" --_~~"._BS~U~Z~O.=2.4__. ,
B5-D-649-0-~
'~~-EY~~'~~~C"-' ~' , ":,' ~~~'b~;~~'~~';--~~

IC17(l )

K5R 33' DRIVER, .

ILL HLT

and

L!~~. 0)."
:' \. \
-,,' ~«',

BS-D-7 -0-23

and"'"

ILL XCT

INH
and
INH'(B)

85-0-7-0-27 .,:

INSURE DEBREAK

B5-0-172-0-2

INT RQ

BS-0-172-0-2

lOP '1
lOP 2
lOP 4

85-0-7-0-22

I/O SKP

85-0-7-0-32

. ...
...

..... ",~.,)

'-'~'..

•

f~" ~

.... '

' ..

."',

,.~

~Ior'

85-~,t9-1?:-_~

t.:

.; ~

',"-

,.....

; ~

MAl- PC
....

MA3(O) \ .

through ':,
MA17(O)

and

B5-D-7-0-23

,~(~,

MA3(1)
through" ..
MA17(l)
~

B5-0-7-0-36

MA121A

and

I/O TRAP (1)
and
I/O TRAP (l)B

85-D-7-0-23

15C 5504

85-0-172-0-2

HLT

85-D-7 -0-23

HOLE 7

80-D-444B-0-2

HOLlE 8P

BO-0-444B-0-2

MA141A
through
MA171A
MBO(1)
through
MB17(1 )
MBO-AC

85-D-7-0-30'
'
.~

MB1-MA
and
MB1-PC

INT RECOGNIZED (0)

B5-D-172-0-2

85-0-172-0-2
,

~~BBO(1J

, ' ', ..' ,_ ,~" .thrpVgh' '
MBB17(1 )
A3-3

" , j

B5-D-7-0~2S
,

MB INFO-OUT
...
MBBO(O)
throtJgh, .
MBB17{O),
and .:'"
)00
if

INT RECOGNIZED {l)
lOT (DBR)
and
lOT .5601

. ('
.~

- i _'.~ ..

Note: XX may be 00 through 76

and

"",."

'. ! ... --,

\UJO""FLAG "\

lOT CLA
lOT XXOl
lOT XX02
lOT XX04

,-..

LUI ACTIVE ~
LUI CLOCK
LUI FLAG
Ltib~~CTt\tE ~
LUO CLOCK

lOT

and

85-D-7':'0.-26)

LINK (0)

r' \'.~

~!,

,,'

.I..

~''''''''''''--''_.''.1'''

_ _ _ _ ..
~

__ ...

.......... , _=....... . . __

~_,

.....

.~_.,

..,M",

:3 ~i 'Nr:,~Q

En9i.'"!f!~ring

'ijSJ9QQ~

Drawing

BS-D-7-0-~~ri

BS-D":i5{}lol~

MOTOR START (SCR)
r

MPX B SEL 0
th.~o.ugh:. ~",~ ,:
MPX B SEl3

. "": --.,..

thrp16Jhr -,:2-2
MPX 3
OP 1

t',

,:. a!ld~ ~."! -d· Of.

8S-D-7 -O-f6;

OP2

OPLAW
O~R.G,' .. ~~,.;
OP SKP
OPSKP
OP SKPEN~'"

8S-0-7-0-26

OR: SK.P. EN.~, '
f)VE~F~O.W:F:LAG (O)

and

8S-0-172-0-2

OVERFLOW FLAG (1)
PB10"(O)' .;~...:
PB'17· (0)'

and

.
'

8S-0-750 ... 0-2

}

BS-0-7-0-32

PSE

85-0-172-0-2

PU,N ACTIVE (0)
PU·N'ACT1VE (1)
PUN OONE
PUN FLAG (0)
PUN FLAG (1)
PUN GO
PUN READY
PUN RQ
PUN SYNC L

B5-0-750-0-2

PWR CLR
PWR C LR Pos

.8S-0-'7-0-20

PWR CLR+CAC

85-0-172-0-2

PWR CLR (P)
and
PWR CLR (N)

85-0-750-0-2

PIBl- MA

BS-D-177-0-2

and
85-0-7-0-23 .

PCl- MB

PC3(O)
through
PC17(O)

through
PC 17(1)

PROG·B

PROG RQ
PROG SYNC (0)
PROG 5YNC (l)

RAR

PCl- MA.

and
~C3,O), ,

8S-0-7-0-26

PWR CLR Neg

'-'

PB10 "(1) ;. "
tnrough . ." .
PB 17 (1)

and

. 85-0-7-0-32

and

," PIE(l)

-I""f!'

-', ;

throllgh~~ ..,'

PIE(O)

-"'.',

MPXO

,...

)

; '. BS-D-l73-0-2

.,.

Eng i neer i ng
Drawing . .
Number

....

POV(1)
'!?

and

ft'.

'i. • •:

Sig~al

~~. '.,:.:~... 2:~ .::.:.~==..:.:-:::::_:.::=::::._..::-.::_.:.:_ . ::. __-:;,;;.: '.' ::Num.ber:....::~.~.::_,

::,M~~"ij& It:Jl:*-2a

85-D-7-0-29

85-D-7-0-26

RAL

RBO(1 )
through
. RB 17(1)
ROl (0)
RDl (l)
R02 (0)
R02 (1)
RD FLAG (0)
RD _FLAG (l)

80-D-444B-0-2

-------.----------------------~--------~~----------------

,.. 'Engineering' ." ,..

-=--:

DrawJ~n9

• Signal

Drawing
Numb~r

N:uin'ber

RD MODE (0)
RD Jv\ODE (1)
RD RUN (0)
RD RUN (1) ~
RD SHIFT 1
RD SHIFT 2
RD STRB

...- .....,..... _

..... ,'<.~"~.,,

: "· :. "··~.;s£[E-:et.:·(r '~-:;::';:,::'~~':: . . "'::.::~:::::..-:.~:.. :=::..,::..::::..:.::... =::::-;;',::::::::::'..
......

(;

.;;'.

< '~:"

~",~

,.. -:',:

/~~.t.

/t.

as-D.-7~-23t
, ; . ) '.
.~i .\1\

~,C~:,
t
:
.:.~ . td

BS-D-7-.0~'22)'

SP4

REPEAT

BS-0-7.-0-20:

BS-0-7-0-23

RUN (8)TO IND

BS-0-444B-0-2

t..

••••.••.•

-,~,'

BO- 0-4448.... (9.;;. 2
"";

START K

I/O device)

RPT (1)
RPT (0)
RPT (1)B

" ";,'.

START

arid

REQUEST SLOWCYCLE (from any' slow

...

:~,'

START+CONT
and
START-EX+DP

STROBE RETURN

BS~ D~ 149:- q~45

STB RETURN

85 .. 0;7-O~ 20·~·

SYNC

85-[)'17:7-0-2

"'.

RUN (1)
85-0-7-0-23

•

. "4_

•

. ')!:.;

T1
through

RUN (1)B

SEL 0
SEL 1
SEL READ (1)B
SEL 0 WR ITE (l)B
SEL l/\READ (1)B
SEL 1l\WRITE (l)B
SEL 2AREAD (1)B ~
SEL 21\WRITE (1)B
SEL 3/\R EA D (1) B
SEL 3AWRITE (l)B

BS;... D~ f~9:"6~45

SL9~.'YC.~eg
SPO
through

85-0-7-0-20

SEL- RRB IMUMI
and
SEL- RSB IMIlMI

a~d--:!-·"···<·

SLOweyC Pos

READ IN

SAO
through
SA17

•

~tg~ ~~~ ~~g}

READ (2)B

RUN STOP

'tt'..

,Sj:L.f&l".l(~·,. ~~o

BD-0-444B-O..;;i2

READ 1 (1)
READ (2)

and

'" ·---__ ~ne.e.r,ulg-_~

"'u,

85-0-7-0-20

B5-0-7-0-22
•
.. . , ."'1':..

T5-D

85-0-149-0-45

85-0-7-0-25

BS-D-7-0... 32

TAD CRY·',
~

..: :

85-0-7-0-26'

TAPE FEED

8S-0-750-0-2

TPl
through
. TP7 .:, "
and TP7 INVTD

. BS-D-7-0~22

TP2 SEL 0, 1
and
TP2 5EL 2, 3.
TRAP
,..
and
TRAP (1)

. •i

BS- 0~7 - 0:'" 2-7:
.. .

.....

<.'

BS-0-7-0-27

j. . . •

A3...,5·

WD-D-7--0-37
'.

..'

, ..
. .~

•

..1

.'"

•

:'.,~ •.

"'\"

O~AC

o~.

....

~: BS~O:..'-o-2lt

.. B'S~D-7~... 26·

NtA}.

0-:" MS'·

'O-PC

85-0-7-0-25

+l.-Me.
.
,

"+l~PC

. Engineering
Drawing

Number

':,~

WRitE (2)8-

·~6R.:"AC

Signal

'~:"'~ftE'(2)
. .··'~~·tr<· .'.,
:.

, Engineering
·.... ,~.QtQWi "9
·(·N~bcr

85-D-7-0-23,
"85-0-7~0-25

,.
. 20~MA

85-0-7-25

3301
3302
3304 "

85-0-7-0-36

·7001 .
7002
7004
through
7701
7702
7704

85-0-7-0-36

.""

;;0101 ,

P102
. 0104
through

85-0-7-0-36 .

0401

0402.
0404
.----~---------~.~------~------------------------~----

A3-6