Digital PDFs

XX-A828E-0A

1966

100 pages

Original

3.3MB

Document:	PDP-7 InterfMan
Order Number:	XX-A828E-0A
Revision:
Pages:	100
Original Filename:	http://bitsavers.org/pdf/dec/pdp7/PDP-7_InterfMan.pdf

OCR Text

INTERFACE AND
INSTALLATION MANUAL

OIG ITAL EQUIF'MENT CORPORATION '

MAYNARD, MASSACrlU5ET TS

F-78A
3/66

PDP-7 INTERFACE AND
INSTALLATION MANUAL

DIGITAL EQUIPMENT CORPORATION

•

MAYNARD, MASSACHUSETTS

CONTENTS
Chapter
INTRODUCTION •••.•••.••.•..•....•..•.••••••..••••••••••••••••..•.•••

Programmed Data Transfers .....••••....••.••••.•.••.••......•••..••.•

Data Break Transfers ....•...•..•.•••.••..•••.•.•.••••.••••••••.•••••

Pertinent Documents

Logic Symbols ... • • • • . . . . • . . . • • • • • . . • • • . • • • . • . • • • . • • . • . • • • . • . • • • . . • •

PROGRAMMED DATA TRANSFERS •.•....•.••...•••.•••••••.•••.••••.••.••

TimingCycle ..•.•••..••.•••••••••••••••••••.•••.•••••.•••••.•••.••

lOP Generator .•.........••••.•..•••.••••••••.•••••••...••••.••••••

Device Selector (OS) .••••...•.•..•'. . . . • . • . • • . . • • • . • • . • • • . . • • • . . . • • • •

Slow Cycle Facility.................................................

Input/Output Skip (lOS) ....•....•••••••••.•••..•••.•..........•.....

Information Collector (lC) •.•••..•••••••••••••..••.••......•....•....

Information Distributor (10) .•.••.••.•.•• ••••••••••••••••••. .•••••••.•.

Data Transfers into the PDP-7 . . . . . • . . . . • . . • . • • . . . • . • • . . . . . . • . • . • • . . . . •

Data Transfers out of the PDP-7 ...•.•..•••.•••••.••••••••••••.•.•..•.

Program Interrupt (Pi)................................................

Multiple Use of lOS and PI .... ...•••....••.... .•...•.• . .•• .•••••.•.••

Example of Programmed Data Input and Output. . . . . . • • . . . . • . • • • . • • • . • . • •

DATA BREAK TRANSFERS •.....•••.•..••••.•...•.••.•••••••.••.•••••••..•

Data Break Fac iI ity .......•.•..•...•.••..••••••.•..•••..•..•........

Data Address . . . . . . . . • . . . . . . • • . • . • • • • • . • • • • • . . • • • • • . . . • . . . . . . • . . • . . .

Data Information Input and Output ............•.......•.•...••..•••...

DIGITAL LOGIC CIRCUITS .••..•.••••••.•••••••..•.•..•.•••.•••••.•.•••.

Inverters ...•••••..••.•••...••..••.•.•..•••.•••••.•.••...•..•.•....

Bus Drivers ...••.•....•...••••..••.•..••••.•.••..•.••••....•.•••...

Pulse Ampl ifiers ..•......•.......................•.•..•.•••••.•.••..

Diode Gates •..•••...•.•....•..•.•.•••••.•.••........•.•.•••.•..... ,

INTERFACE CONNECTIONS •......•..••..•.....•..••••..••••.••..•.•...

Interface Connections and Signal Identification
iii

CONTENTS (continued)
Chapter
5 (cont)

Loading and Driving Considerations ••••••• ~ •••••••• • •• " ~. "0' • " • • •• • • •••
Device Selector ••.•..•...••.• " .....••.•.••.•.• ...

• • • • • • • • • •

• •

43
73

Information Coil ector ••••••••••••••••••••••••••• " •• ',' • • • • • • • • • • •

Information Distributor ••••••••••••••• ',' • • • • • •• • • .. • • • • • • • • • • • • • • •

Power Clear Output Signals •••••• " • •• • • • • • • • • • •.• • .. • •• •.• • • • • • • • • • •

Begin Buffered Output Signal .....................................

RU,n Output Sig.nal ..................................

•

Slow Cycle Request Input Signal ••••••••••••••••••..• '.' • • • • • • • • • •• •

Program Interrupt Request Input Signal •••••••• ~ • • • • .• • •• • • . • • • • . • . •

Data Break Request Input Signal ••••••••••••••••••.• ••• • • • • • • • • . • •

Transfer Direction Input Signal •••••••••••••••••••••••••••••.•••••

Data Address Input Signal....... •• • • •• .. • • • • • • • • • • • • • • ... • • • • • • • • • •

Address Accepted Output Signal ••••••••••••••••••••••••••••••••••

Data Information Input Signals •••••••••••••••••••••••••••••••••••

Data Ac~epted Output Signal •••••••••••••••••,...................

Data Ready Output Signal •••• , ••••••••••••••••••••-••••••• -. • • • • • •

Data Information Output Signals. • • • •• • •• • • • • • • • • • • • • • • • • • • • • • • •• •

•

:• • •

•

INSTALLATION PLANNING
Physical Configuration ••••••••••••••••••••••••••••••••••••••••••••••

Environmental Requirements ••••••••••••••••••••••••••••••••••••••••••

Power Requirements. • • • • • • • • •• •• . • • • •• • • • • • . • •• • • . . . . • • • • • . • . • •• • •• •

Cabl ing Requirements .••••.•.•••••...•.••••.••••••••••.• ~ • • • • • • • • • • .

PDP-7 DEVICE SELECTOR AND INFORMATION COLLECTOR
REQUIREMENTS FOR STANDARD OPTIONS •••••••••••••••••••••••••••••••

Appendix

ILLUSTRATIONS

Typical PDP-7lnstallation • ••• •••••••••• ••••••••• •••••• •.•••••••••••••••••

vii

Logic Symbols ......................................................... .

ILLUSTRATIONS (continued)

Programmed Data Transfer Interface Block Diagram •••.• '" •.•••••..•••••....•

Decoding of lOT Instructions •..•..•.•••••••••••••••••.•••.•••••••••••••••

Programmed Data Transfer Timing Diagram •..•••.•.••..•••..•••..•••.•..•.••

lOP Generator ••.••..••.•••.•••••••••••••••••••••.•••••..••.••..•••.•••

Generation of lOT Command Pulses by Device Selector ••••.•••••••••..•••••.•

Typical Device Selector (Device 34) •.••••.•.••••••••••••••••.•••••.•••••••

Slow Cycle Facility •.•••..•••.••••.•••••••.•••••••••••.••••.•••.••.•••..

Input/Output Skip Fac iI ity •..•.•.•.••.••••••••••••••.••.•••••..•••••.••.•

Information Collector and Information Distributor •••••••••••.••••.•••..••••••

Programmed Data Input Transfer ••.•..•.•"•.••••.•••.••••••••••••.••.••••...

Programmed Data Output Transfer ...•.•••••••.•.•••••••.•.••.......••••••.

Program Interrupt Facility ..•••.••.•••.••.••••••.••••••••••.•.•••••.•••.•.

Multiple Use of lOS and PI ...••.•.••.•...•••••...•••••••• "••••••••••••••..

Programmed Data Input Flow Diagram ....•.••••..•.•••••.•••....•••••••.•..

Programmed Data Output Flow Diagram .••.•••.•..•.•.••.•••••••..•.••••••.•

Data Break Transfer Interface Block Diagram •••..••••••••••••••••••••••••.•.

Data Break Transfer Timing Diagram .•.....•••••..••. '" ••••••••••••.•••..•.

Data Break Fac iI ity Interface of Computer .••..••••.•••••••••...••••....••••

Data Address Input Interface of Computer ••.•...•••.•.•••••.•..••••.••••.•.•

Data Information Input and Output Interface of Computer ...•••••••••••.••••..

Inverter Circuit •.....••••••••.•••.••••.•••••••.••••.•..••••.•..•..••.•••

Bus Driver Output Circuit .••..•..•..•••.•••••••••••••••.•••••••••...•.••.

Pulse Ampl ifier Output Circuit .•.•.••.•.••••.•..•.•••••••...••••••••••..•.

Diode Gate Circuit .••.•.•••••••.••••.••••.••••••••••••.•.•••••.•••.•.•.

Interface Cable Connector Locations and Assignments ••••••••••.•.••.••••....

Information Collector Channel Assignments ...•.••.•••...•..•••.•.•••••...••

Basic PDP-7 Component Locations ••.••.•..••••••.••.•••..••••.••••.••••.•.

Typical PDP-7 System Component Locations .••••••••••.•.•..••..••.••••••.•.

Basic PDP-7 Installation Dimensions •.•..••••••••....•..•..••.•...•...••..•

TABLES
Table

Page
Input Signals .••••.•..••••••.•••••••••.••••••.•••••••.••..••..•...••....

Output Signals ..••••.•••••••.•••••••.•.•.••••••••••.••.••••••••.•••••••

Prewired Interface Connections ••.•..•.•.•••••••••••••.••••••••••••••••.•.

lOT Code Assignments ••••••••••••••...••.••••••••••••.•.••....•••.•••••.

Installation Data ••.•••••••••••••••••.••...••••••••••••••••••••••.•••..••

CHAPTER 1
INTRODUCTION

Since the processing power of a computer system depends, in large measure, upon the range and number
of peripheral devices that can be connected to it, the Programmed Data Processor-7 (PDP-7) has been
designed with a very broad, flexible, and expandable interface. This manual defines the interface characteristics of the computer to allow the reader to design and implement any electrical interfaces required
to connect devices to the PDP-7. This manual also provides information for planning the installation of
a PDP-7 system. Information in this manual applies only to PDP-7 systems with serial numbers above 100.
Refer to the PDP-7 Interface and Installation Manual, F-78, dated 1/66, for information on systems with
serial numbers below 100.
The PDP-7 is a digital machine designed for use as a general-purpose computer, an independent information handl ing faci Iity, or as the control element in a complex processing system. The PDP-7 is a singleaddress, fixed l8-bit word length, parallel processing binary computer using lis complement arithmetic
(2 1 s complement arithmetic faci Iitates mu Itiprec i sion operations). Cyc Ie time of the random-access core
memory is 1 .75 jJsec, permitting a computation rate of up to 285,714 additions per second.
Programming features of the computer include indirect addressing, microprogramming (combining instructions
to occur in one 1 .75~sec machine cycle), and programmed monitoring of peripheral devices. Real-time
features of the computer include program interrupt (entry into a subroutine caused by a request from an
I/O device), input/output skip facility (program flow modification as a function of the status of a selected
peripheral device), and high-speed data break channel (direct input/output access to computer core memory for cycle-steal ing data transfers at a rate of over 10 mi Ilion bits per second). Eight autoindex registers
simplify sorting, searching, and multiple input/output list processing operations. An operator console provides manual control and visual indication of programmed operations.

An l8-bit switch register per-

mits manual entry of data and instructions, or status information to be sensed by the program. The console
displays all active registers, including the memory address register, memory buffer register, accumulator,
link bit, machine state, instruction register, program counter register, and multiplier quotient register of
the optional extended arithmetic element.
The basic PDP-7 system consists of a Type KAl7 A Processor, a Type 149 Core Memory, and a Type KAl1 A
I/O Package composed of FLIP CHIP

circuit modules and solid-state power supplies. These hybrid silicon

™ FLIP CHIP is a trademark of Digital Equipment Corporation, Maynard, Mass.

circuits have an operating temperature range exceeding the limits of 32° to 122°F, so no air-conditioning
is requ ired at the computer si te. Standard 115v, 60-cps power operates the computer. The basic system
is self-contained in a 3-bay cabinet 69-1/8 inches high and 61-3/4 inches wide. This unit weighs approximately 1150 Ib, requiring no subflooring or bracing.
In addition to the standard tape reader, tape punch, and Teletype keyboard/re~ader, the PDP-7 system
can operate over 64 input/output devices. Existing interface designs permit connection of a number of
DEC options to the computer, including devices such as line printers, magnetic: tape transports, magnetic
drums, card equipment, analog-to-digital converters, CRT displays, and digitClI plotters. The PDP-7
system can also accept other types of instruments or hardware devices that have an appropriate interface.
The simple I/O techniques of the PDP-7 allow inexpensive, straight-forward device interfaces to be
real ized. Any device interface needs control to determine when an information exchange is to take place
and to specify the location(s} in the computer core memory which accept or yield data. Either the computer program or the transferring device may exercise this control. Transfers made under control of the
computer program are called programmed data transfers. Transfers made under control of the external
device are called data break transfers.

PROGRAMMED DATA TRANSFERS
The majority of I/O transfers occur under control of the computer program. The maximum real istic rate of
transferring 18-b it words is 33 kc in the program interrupt mode.

Normally this speed is well beyond that

required for laboratory or process control instrumentation .. To transfer and stqre information under program
control requires about six times as much computer time as under data break control.

In terms of real time,

the duration of a programmed transfer is rather small due to the high speed of the computer.
To real ize f~1I benefit of the built-in control features of the PDP-7 programmed I/O transfers should be
used in most cases. Controls for devices using programmed data transfers are usually simpler and less
expensive than controls for devices using data break transfers. Analog-to-digital converters, digital-toanalog converters, digital plotters, I ine printers, message switching equipment, and relay control systems
typify equipment using the programmed data transfer channels.
Using programmed data transfer channels, simultaneous operation of devices is llimited only by the relative
speed of the computer with respect to the device speeds, and the search time required to determine the
device requiring service. The percent of computer time taken for I/O servicin!~ is roughly:
4
%1/0 time = sum of device rates (in cps) x service time (fJsec per interrupt) x 10For comparison, it takes less t-han 3% of computer running time to read or write conventional IBMcompatible magnetic tape at 556 bits per inch and 75 inches per second.

DATA BREAK TRANSFERS
Devices which operate at very high speed or which require very rapid response from the computer use the
data break transfer channel. This channel permits an external device, almost arbitrarily, to insert or extract words from the computer core memory, bypassing all program control logic. Because the computer
program has no cogn izance of transfers made through this channel, programmed checks of input data are
made prior to use of information received in this manner.
The data break is particularly well-suited for devices that transfer large amounts of data in block form,
e. g., high-speed magnetic tape systems, high-speed drum memories, or CRT display systems containing
memory elements.

PERTINENT DOCUMENTS
The following publications serve as source material and complement the information in this manual.
1. Digital Logic Handbook, C-105. This book describes the functions and specifications of FLIP CHIP modules and module accessories used in the PDP-7, control interfaces,
and peripheral devices.
2. PDP-7 Brochure, F-71. This leaflet presents the basic functions of the PDP-7
hardware, software, instructions, and standard optional equipment.
3. PDP-7 Users Handbook, F-75. This book contains computer organization information, detailed information on the function of interface facilities, and descriptions of the timing and operations performed by all instructions.
4. PDP-7 Maintenance Manual, F-77 A. This manual gives functional description, principles of equipment operation, interface, installation, operating
procedures, and detailed maintenance information for machines with serial numbers
above 100.
5. Instruction manuals for appropriate input/output device options used in PDP-7
systems are avai lable.
6. PDP-7 Price List, F-72. This leaflet contains current price information on the
basic computer, computer options, and standard input/output equipment.

LOGIC SYMBOLS
Figure 2 defines the symbols used to express digital logic circuits and signals in the illustrations of this
manual.

DEC STANDARD NEGATIVE PULSE

--{>

•

DEC STANDARD POSITIVE OR POSITIVE-GOING PULSE
DEC STANDARD NEGATIVE LEVEL
DEC STANDARD GROUND LEVEL
FLOW
-15V LOAD RESISTOR CLAMPED AT -?Iv

PNP TRANSISTOR INVERTER
1. EMITTER
2. BASE
3. COLLECTOR

LOGIC AND GATE FOR
NEGATIVE SIGNALS
WITH COMPLEMENTARY
OUTPUT SIGNALS

LOGIC OR GATE FOR
GROUND LEVEL SIGNALS
WITH COMPLEMENTARY
OUTPUT SIGNALS

LOGIC NAND GATE FOR
NEGATIVE SIGNALS

DIODE-CAPACITOR-DIODE GATE
1. CONDITIONING LEVEL INPUT
2. TRIGGERING PULSE INPUT
3. PULSE OUTPUT

FLIP-FLOP (BISTABLE MULTIVIBRATOR)
1. GATED SET-TO-l INPUT
2. GATED CLEAR-TO-O INPUT
3. DIRECT CLEAR-TO-O INPUT
4,5 OUTPUTS

Figure 2

Logic Symbols

INVERTING BUS DRIVER

B OR W SERIES
PULSE AMPLIFIER. OUTPUT
CAN BE MADE POSITIVE OR
NEGATIVE BY REVERSING
GROUND AND SIGNAL OUTPUT
TERMINALS

R SERIES PULSE AMPLIFIER.
OUTPUT ALWAYS POSITIVE,
REFERENCED TO -3V.

OPTIONAL DEVICE SELECTOR
LOGIC AS USED FOR ONE
SELECT CODE

Figure 2

Logic Symbols (continued)

CHAPTER 2
PROGRAMMED DATA TRANSFERS

The PDP-7 is a parallel-transfer machine that collects and distributes data in bytes of up to 18 bits.
Figure 3 shows information flow within the computer to effect a programmed data transfer with input/output
equipment.

lOP
PULSES

BITS 0-3

..-------.

MEMORY
BUFFER
REGISTER
(MB)

IOT

IOP
GENERATOR
BITS 15-17

DEVICE
SELECTOR
(OS)

COMMAND
PULSES

BITS 6-11

ACCUMULATOR
REGISTER
(A C)

CONNECTIONS
TO INPUT I OUTPUT
DEVICE

SLOW CYCLE
REQUEST

Figure 3

Programmed Data Transfer Interface Block Diagram

All programmed data transfers take place through the accumu lator, the 18-bit arithmetic reg ister of the
computer. The computer program controls the loading of information into the accumulator (AC) for an
output transfer, and for storing information in core memory from the AC for an input transfer.

Information

in the AC for output transfer is power ampl ified and suppl ied to the bussed connections of many peripheral
devices by the information distributor (I D). Then the program-selected device can sample these signal
Iines to strobe AC data into a control or information register.

Input data signals arrive from many periph-

eral devices at input mixer circuits of the information collector (IC), which transfers data into the AC.
In the input/output skip facil ity (lOS), command pulses from the device selector (DS) sample the condition
of I/O device flags.

The lOS allows branching of the program based on the condition or availability

of peripheral equipment, effectively making programmed decisions to continUE! the current program or
to jump to another part of the program, such as a subroutine that services an I/O device.
The DS generates command pulses during execution of input/output transfer (lOT) instructions. All instructions stored in core memory as a program sequence are read into the memory buffer register (MB) to
be executed. The operation code in the four most significant bits (bits 0 through 3) of the instruction is
transferred into the instruction register (lR) and decoded to produce appropriate control signals.

When

the operation code is recognized as an lOT instruction, the lOP generator produces time-sequenced lOP
pulsesasa function of the three least significant bits of the instruction (bits 15 through 17 in the MB). The
lOP pulses, with an I/O device selection code in bits 6 through 11 of the instruction, are suppl ied as bus
inputs to all gates of the DS. The gating circuits of the DS associated with a sp1ecific device are enabled
by the select code to regenerate lOPs as specific lOT command pulses.

Figure.4 shows the decoding of an

lOT instruction and Figure 5 indicates the timing of the lOP and lOT pulses.

OPERATION CODE
70 a =lOT INSTRUCTION

DEVICE
SELECTION

CLEAR AC AT EVENT
TIME 1 IF BIT IS A 1

r-~

I :< I :< I :.: I :.: I >: I :.: I
'---y-'

'---y-'

"---y--'

SUBDEVICE
SELECTION

lOP PULSE
GENERATION
CONTROL

Figure 4

Decoding of lOT Instructions

One lOT instruction can generate one, two, or three sequential lOT pulses. These command pulses are designated by the octal code of the twelve least significant bits of the instruction in which they are generated;
e.g., lOT 3401 (usually bits 4 and 5 are unused and are assumed to be O's unless. otherwise specified).
These lOT command pulses from the DS go to the lOS, the IC, and to a specific I/O device whose action
they control.

In this manner, the program produces commands to transfer data into or out of I/O devices;

to cause the program to skip or not skip an instruction based on the condition of (In external device flag;
or to start, stop, or perform operations in devices controlled by a command pulse.
lOT instructions can use the normal computer cycle time of 1.75 Ilsec, or can occur in a slow cycle adjusted to the speed of the slowest I/O device. The device selector can be wired to cause entry into a
slow cycle for any device, when its select code is in the lOT instruction being executed.

Figure 5 shows

the timing of command pulses for devices using the normal or slow cycle and the availability of the AC
for transfers.

t
I

1- 240 ....,
I NSEC

I
I

1---640 NSEC----J..- 270 - l
I
I NSEC I
T2
13
T4

/+:210..!.-240,..../
I NSEC I NSEC I
T6
T7

I 120 --I
I NSEC I

-3 VOLTS

NOT READY
READY

ACCUMULATOR CLEARED FOR
DATA INPUT TRANSFER
IF MB 14 CONTAINS A 1

NOT READY

120 ,....-+j

I NSEC

1---640 NSEC--I-270-l
I
I NSEC I
13
T4

!.-210,..!
I NSEC I
T6
J

T5
J

~_T6+100 NSEC

T4+IOONSEC--+IL______________________________________~

GROUND

T5 + 20 NSEC--+ !....________-'

GROUND

T7+20 NSEC-....
! ________-'

-3 VOLTS
GROUND

TI + 20 NSEC OF NE X T CYC L E - ! ' - -______---'

-3 VOLTS

rIOT XXOI

T5+40 NSEC-!~______--,

GROUND

-3 VOLTS
lOT XX02

GROUND

T7+ 40 NSEC-!....________-'

-3 VOLTS

lOT XX09

GROUND

TI + 40 NSEC OF NEXT CYCLE--+!...._______-'

-3 VOLTS
(0)

I
I

COMPUTER TIME

MEMORY BUFFER
REGISTER OUTPUT

150
NSEC

I--

NORMAL CYCLE

-- --I

120
I
NSEC-+j

ANY lOT INTRUCTION (FETCH) CYCLE
(1.36 MICROSECONDS+2 PRESET PERIODS)

I
-+j

PRESET ACCORDING TO SLOWEST
I PRESET ACCORDING TO SLOWEST I
I'-;~0--r-- I/O DEVICE,! MICROSECOND ~ 110 DEVICE,I MICROSECOND ----!
T5 N EC T6
MINIMUM
T7
MINIMUM
TI

I
I

-+j

120
r-NSEC

I.- 210

I
120 I
I"-NSEC I

1-240~

r----640 NSEC~N2;E~"""
T2
13
T4

T6 NSEC T7

I...,

NSEC

GROUND

-3 VOLTS

~325 NSEC

NOT AVA/LABI E
AVA/LABL E

ACr.uMULATOR DATA FnR
OUTPUT TRANSFER

NOT REACT'

ACCUMULATOR CLEARED FOR
DATA INPUT TRANSFER
IF MBI4 CONTAINS A 1

NOT READY
READY

rop GENERATOR COMPOSITE
OU' PUT (400-NSEC PULSES)

GROUND
-3 VOLTS

REAc~r

~ T6+ 100 NSEC

I-T4 .,...'0 NSEC

T4+ tOO NSEC=-:;j
'--------------------------------------------------------------------------------'
T5 +20 NSEc-1

T7+ 20 NSEC-!
lOP I

OPTIONAL DEVICE SELECTOR
COMPOSITE OUTPUT
1400-NSEC PULSES)

-J

I
I
I

120
j4-NSEC
I
1----640 NSEC~270 -I
T2
13 NSEC T4

TIMING PULSE GENERATOR
COMPOSITE OUTPUT
(70-NSEC PULSES)

I-T4+20 NSFC

-3 VOLTS

IOP 2

~~25 NSEC

READY

IOP4

-0

NOT AVAILABLE
AVAILABLE

ACCUMULATOR DATA FOR
OUTPUT TRANSFER

OPTIONAL DEVICE
SELECTOR OUTPUT
(400-NSEC PULSES)

GROUND

MEfv'f)RY BUFFER
REGIS TE R OUTPUT

lOP GENERATOR
OUTPUT
(400-NSEC PULSES)

i - I NSEC

150 -l

TIMINr, PULSE GENERATOR
COMPOSITE OUTPUT
(70-NSEC PULSES}

-l I 120
I 150,.-j
r- NSEC
I NSEC I
I I

I- 120

I NSEC I

COMPUTER TIME

ANY lOT INSTRUCTION (FETCH) CYCLE
(1.75 MICROSECONDS)

_:~~~~

T5+40 NSEC-I

T1+20 NSEC---I
OF NEXT CYCLE

rop 4

IOT XX02

TI+40 NSEC--I
OF NEXT CYCLE

IOT XX04

T7+40 NSEC-I
IOT XXOI

( b) SLOW CYCLE

Figure 5

lOP 2

Programmed Data Transfer Timing Diagram

Devices which require immediate service from the computer program, or which take considerable computer
time to discontinue the main program until transfer needs are met, can use the program interrupt (PI) fac il ity.
In this mode of operation, the computer can initiate operation of I/o equipmEmt and continue the main
program until the device requests servicing. A signal input to the PI requestinH a program interrupt causes
storing of the conditions of the main program and initiates a subroutine to service the device. At the conclusion of this subroutine, the main program is reinstated until another interrupt request occurs.

TIMING CYCLE
Cycle time of an lOT instruction is either normal or slow, depending upon the device addressed (see
Figure 5). All devices use the normal cycle unless the device selector for the selected equipment is wired
to request a slow cycle.
The normal lOT cycle time is 1 .75 fJsec, or equal to a normal computer cycle. At computer time 5 (T5)
10Pl is produced, at time 7 (T7) IOP2 is produced, and at time 1 (Tl) of the next cycle IOP4 is produced.
Time 1 of the next cycle can be used for IOP4, since time 1 is normally used only to prepare to read the
next instruction into the MB from core memory; so the IR and MB still contain the same information. The
time from the start of 10Pl to the start of IOP2 is 450 nseci from the start of IOP2 to IOP4 is 150 nsec.
If consecutive lOT instructions occur, the time from the start of IOP4 in the first instruction to the start
of IOP1 of the second instruction is 1 • 15 fJsec.
The slow lOT cycle time produces lOP pulses at the same computer times as during a normal cycle; however,
the delay between timing pulses is adjustable from a 1 fJsec to 4 fJsec.
cations to the delay modules can produce even longer time delays.

Under special conditions modifi-

In all cases, delays are set to ac-

commodate the slowest device using the slow cycle feature of the computer (this timing exists for all devices
requesting a slow cycle). A complete slow cycle requires a 3.36 fJsec minimum.

lOP GENERATOR
The logic circuits of the lOP generator are shown in Figure 6. When the instruction register decoder
detects an lOT instruction (the operation code in bits MBO-MBS = 111

), it generates the lOT signal.
2
The lOT signal conditions one input of each of the three gates that trigger pulse ampl ifiers to produce
the lOP pulses. Each 3-input NAN D gate is operated by the condition of a bil" in the lOT instruction
and a computer timing pulse, to produce one of the sequential lOP pulses.

Eac:h lOP pulse goes to one

gate of all device selector channels to allow generation of an lOT command pulse at one of the three sequential event times within the instruction. Figure 6 shows the computer timinH pulses and instruction bit
conditions which generate each lOP pulse for the three event times.

EVENT
TIME I

EVENT
TIME 2

EVENT
TIME 3

Figure 6

lOP Generator

DEVICE SELECTOR (DS)
The DS selects an I/O device or subdevice according to the address code of the device specified in bits 4
through 13 of the lOT instruction. Selection of the device can request a slow cycle. The DS then generates lOT command pulses for each lOP pulse received, and transmits these commands to the 105, the IC,
and/or the device . Generally, lOT command pulses are used as follows:
Command

Use

lOT XX01

Applied to the 105 to sense the condition of the
device flag.

lOT XX02

Appl ied to the IC to transfer data into the computer I
or appl ied to the device to initiate a data transfer
from the computer and clear device flags.

lOT XX04

Appl ied to the device to initiate some operation
(start, read, etc.).

Each group of these command pulses requires one channel of the DS, and each channel requires a different
address {or select code}. One device can, therefore, use several channels of the DS.

Figure 7 shows

generation of command pulses by several channels of the DS.

lOP 1
lOP2
lOP 4
MBBS
MBS7
MSSS
MBB9
MBSIO
MBS11
}

COMMAND
PULSES TO
DEVICE 34

I
I
I

I
,/

BUSSED INPUT
TO ALL DEVICE
SELECTORS

Figure 7

Generation of lOT Command Pulses by Device Selector

The logical representation for a typical channel of the DS, using channel 34, is shown in Figure 8.

6-input NAND gate wired to receive the appropriate signal outputs from MB6-11 for select code 34 activates the channel.

In the DS module, the NAND gate contains 14 diode input terminals; 12 of these con-

nect to the complementary outputs of MB6-11, cmd 2 are open to receive subdevice or control condition.
signals as needed.

Either the 1 or the 0 signal f~om each MB bit is disconnected by removing the appro-

priate diode from the NAND gate when establishing the select code. The ground level output of the
NAND gate indicates when the lOT instruction selects the device, and can therefore request a slow cycle

for the device. This output also enables three gating inverters, allowing them "to trigger a pulse ampl ifier
if an lOP pulse occurs. The positive output from each pulse amplifier is an lOT command pulse identified
by the select code and the number of the initiating lOP pulse. Three inverters receive the positive lOT
pulses to produce complementary lOT output pulses. A pulse ampl ifier modu Ie can be connected in each
channel of the DS to provide greater output drive or to produce pulses of a specific duration required by
the selected device.

Figure 8

Typical Device Selector (Device 34)

SLOW CYCLE FACILITY
Up to twelve devices can request a slow lOT cycle by connecting the ground-level select signal output
of the DS channel to the slow cycle request facility. This facility consists of a 12-input diode NOR gate
for ground levels as shown in Figure 9.

None of the basic PDP-7 input/output devices require a slow

cycle.

LEVELS FROM DEVICE SELECTOR
TO REQUEST SLOW CYCLE FOR
UP TO 12 DEVICES

Figure 9

Slow Cycle Facility

INPUT/OUTPUT SKIP (lOS)
The condition of an I/O device flag and generation of an lOT pulse combine in the lOS to cause the program
to skip over one instruction. Incrementing the program count without executing the instruction at the current
program count causes skipping. The lOS facil ity consists of multiple 2-input ANID gates with outputs connected in parallel to allow any gate to trigger the pulse ampl ifier which producc~s the 10 SKIP pulse. A
flag or status level from the device and an lOT XX01 pulse from the appropriate channel of the DS provide
input connections to each gate as shown in Figure 10. In this manner an lOT instruction can check the
status of an I/O device and skip the next instruction if the device requires servicing. Programmed testing
in this manner allows the routine to jump out of a sequence to a subroutine that services the device tested.
Assuming that a device is already operating, a possible program sequence to test its availability follows:
Address

Instruction

100,
101,
102,

703401
600100
10XXXX

Remarks

/SKIP IF DEVICE 34 IS READY
/JUMP .-1
/ENTER SERVICE ROUTINE FOR DEVICE 34

Figure 10

Input/Output Skip Facility

When the program reaches address 100, it executes an instruction skip with 7034m. The skip occurs only
if device 34 is ready when the lOT 3401 command is given.

If device 34 is not ready, the flag signal

disqual ifies the 105 gate, and the skip does no1" occur. Therefore, the program continues to the next instruction which is a jump back to the skip instruction.

In this example, the program stays in this waiting

loop until the device is ready to transfer data, at which time the gate in the 105 is enabled and the skip
occurs. When the skip occurs, the instruction in location 102 transfers program control to a subroutine
to service device 34. This subroutine can load the AC with data and transfer it to device 34, or can load
the AC from a register in device 34 and store it in some known core memory address.

INFORMATION COLLECTOR (lC)
The information collector is a 7-channel gated Input mixer that transfers bytes of up to 18 bits into the AC
from signals suppl ied by an external device. Each channel consists of 18 2-input diode AND gates, triggered by a common lOT command pulse from the DS. (Usually the lOT instruction that strobes information
into the AC via the IC is microprogrammed with bit 14 containing a 1.so that the:! AC is cleared at event
time 1 ~) Figure 11 shows the IC logic circuit configuration.
The perforated tape reader and I/O status bits each occupy one l8-bit IC channel. The teleprinter occupies eight bits of a third channel. The remaining four and one-half channels are available for connection
to any peripheral and optional input equipment. Each PDP-7 input option connects directly into one or
more channels of the IC. For operation of more than seven input devices, the Ie is easily expandable in
blocks of seven channels to accommodate any number of channels.

INFORMATION DISTRIBUTOR (lD)
The ID is an output bus system that transfers information from the AC to external devices. Accumulator
output signals are buffered by 18 bus driver circuits and driven through cables to the I/O package.

The

ID in the I/O package contains nine la-bit connection points, or channels, for each bussed signal; one
channel receives bussed connections from the processor, seven channels are avaiiable for individual device cable connections, and one channel is for external expansion of the ID. (The paper tape punch and
teleprinter receive AC output signals directly from the bus drivers and do not require connection through
the ID.) If all seven channels are used, the ID can be expanded to any number ()f output channels by
adding suitable non-inverting buffering and distribution channels similar to the sfandard I D.

ONE PAIR at;.RIPS

TERMINAfx~ANSION

~VEN
~
[g~NECTIONS

::l FOR 10
').

TER....At

PAIRS :VICE

- - STRIPS

?NN~/6~~C~~G?~g~E~:O~~~~~
RMINAL STRIPS

7 . . . /"
. . . U ),. CABLE
~__ CONNECTIONS
D)

INFORMATION
DISTRIBUTOR
IN I/O
PACKAGE

Figure 11

Information Collector and Information Distributor

I
I
POP-

EXTERNAL
DEVICE

Figure 12

Programmed Data Input Transfer

DATA TRANSFERS INTO THE PDP-7
lOT XX02 and lOT XX04 command pulses control an external input device as indicated in Figure 12.
When ready to transfer data into the PDP-7 accumulator, the device sets a flag connected to the lOS.
The program senses the ready status of the flag and issues an lOT instruction to read the contents of the
external device buffer register into the AC. Usually this instruction contains a clear AC command and an
lOT XX02 (lOT XX12) to effect the transfer. If the AC is not cleared before the transfer, the resultant
word in the AC is the inclusive OR of the previous word in the AC and the word lrransferred from the device buffer register. To clear the AC prior to the transfer, bit 14 of the lOT instruction should contain
a 1. This microprogramming clears the AC at event time 1 (computer time T5), and an lOT XX12 pulse
causes the transfer to occur at event time 2 (computer time T7).

Following the transfer (possibly in the same instruction) the program issues an lOT XX04 command pulse
to initiate further operation of the device. This pulse also clears the device flag.

For simpl icity, the

transfer path in Figure 12 shows only a single channel of the IC gates.

DATA TRANSFERS OUT OF THE PDP-7
lOT XX02 and lOT XX04 command pulses control an external output device as indicated in Figure 13.
The AC is loaded with a word (e. g., by a LAC instruction); then the lOT instruction is issued to transfer
the word into the control or data register of the device by an lOT XX02 pulse, and operation of the device
is initiated by an lOT XX04 pulse. The word transferred in this manner can be a character to be operated
upon, or can be a control word sampled by a status register to establish a control mode.
Connecting an output device to the PDP-7 interface adds at least three commands to the instruction repertoire. These commands use an lOT XX01 pulse to skip ·on the ready condition of the device flag, an
lOT XX02 pulse to effect a transfer from the AC to the device, and an lOT XX04 pulse to initiate operation of the device.

PROGRAM INTERRUPT (PI)
When a large amount of computing is required, the computer should process data rather than simply wait
for an I/O device to become ready to transfer data. The PI faci! ity, when enabled by the program, reI ieves the main program of the need for repeated flag checks by allowing I/O device ready flags to automatically cause a program interrupt break. At the break location, program control transfers to a subroutine
which determines the requesting device and initiates an appropriate service routine.
The basic PI faci! ity can accommodate interrupt requests from nine devices and is expandable. As shown
in Figure 14, the PI facility receives a negative signal from the flag of a device to request an interrupt.
This flag signal input to the PI can also connect to the 105 facility to allow the program interrupt subroutine to detect the device requesting the interrupt if multiple devices are connected to the PI. On
Figure 14, note that any fI ip-flop or flag signal connected to an input of any of the six 3-input NOR
gates of the I/O package triggers the interrupt control circuits of the processor to cause a program interrupt break, (if a break is not already in progress and if the interrupt system is enabl ed).

/
/

\-~--

.....:>
.....0..
:>

o
.....
o

-0
<D

E
o'0>
o'-

Q..

COMPUTER PROGRAM
rNTERRUPT FACILITY
NO BREAK STARTED
PROGRAM INTERRUPT
FACILITY ENABLED

EXTERNAL
DEVICE
COMPUTER
110 SKIP
FACILITY

Figure 14

Program Interrupt Facility

If only one device is connected to the PI facil ity I program control can be transferred directly to a routine
that services the device when an interrupt occurs. This operation occurs as follows:

Address
1000
1001
1002
0000

0001
2000
3001
3002
3003
1003
1004

Remarks

Instruction

/MAIN PROGRAM
/MAIN PROGRAM CONTINUES
/INTERRUPT REQUEST OCCURS
INTERRUPT OCCURS
/LlNK, EXTEND AND TRAP FLIP-FLOP STATES,
/EXTENDED PROGRAM COUNT,
/ AND PROGRAM COUNT (PC==1003)
/ ARE STORED IN 0000
/ENTER SERVICE ROUTINE
JMP SR
/SERVICE SUBROUTINE FOR
/INTERRUPTING DEVICE AND SEQUENCE TO RESTORE
/AC, AND RESTORE LAND EPC IF REQUIRED
ION
/TURN ON INTERRUPT
JMP I 0000
/RETURN TO MAl N PROGRAM
/MAIN PROGRAM CONTINUES

MULTIPLE USE OF lOS AND PI
In common practice, more than one device is connected to the PI faci Iity. Therefore, since several devices
can cause an interrupt, the lOS must identify the device requesfing service. When an interrupt occurs, a
routine is entered to identify the device requesting an interrupt and to branch tel an appropriate service
routine. The device can be identified by lOT XXOl pulses that sample a device flags and causethe program to branch or not branch according to the status. Figure 15 shows connecti()ns for three typical devices. The following programming example illustrates these functions.
Address
1000
1001
1002
0000
0001
FLG CK

Remarks

Instruction

/MAIN PROGRAM
/MAIN PROGRAM COUNTINUES
/INTERRUPT REQUEST OCCURS
INTERRUPT OCCURS
/STORE LINK, EPC, AND PC
/(PC=1003)
/ENTER ROUTINE TO DETERMINE WHICH
JMP FLG CK
/DEVICE CAUSED INTERRUPT
/SKIP IF DEVICE 34 IS REQUESTING
lOT 3401
SKP
/NO - TEST NEXT DEVICE
/ENTER SERVICE ROUTINE 34
JMP SR34
lOT 4401
/SKIP IF DEVICE 44 IS REQUESTING
/NO - TEST NEXT DEVICE
SKP
/ENTER SERVICE ROUTINE 44
JMP SR44
/SKIP IF DEVICE 54 IS REQUESTING
lOT 5401
/NO - TEST NEXT DEVICE
SKP
/ENTER SERVICE ROUTINE 54
JMP SR54

COMPUTER
/
110 SKIP
'./
FACILITY / , " ' -

/ ,' / ~
./' /
".,

/ ,' /
/ ,' /
"
/
/,
"/
/"
"/
/."
"
/ COMPUTER
,,"'-

(

PROGRAM
INTERRUPT
FACILITY

'''-...

I
I

".-

I
I
I

Figure 15

Multiple Use of lOS and PI

~Of:3~~~

~i('i-~-:'

Assume that the device that caused the interrupt is an input device (e. g., tape reader). The following
example of a device service routine might apply:
Tag

Instruction

DAC TEMP
lOT XX12
DAC I 10
ISZ COUNT
SKP
JMP END

Remarks
/SAVE AC
/TRANSFER DATA FROM DEVICE BUFFER TO AC
/STORE IN MEMORY LIST
/CHEC K FOR END
/NOT END
/END. JUMP TO ROUTINE TO HANDLE END OF
/L1ST CONDITION

/RESTORE LAND EPC IF REQUIIRED
/RELOAD AC
/TURN ON INTERRUPT
/RETURN TO PROGRAM

LAC TEMP
ION
JMPIO

If the device that caused the interrupt was essentially an output device (receiving data from computer),
the lOT - then - DAC I 10 sequence might be replaced by a LAC I 10 - then - lOT sequence.

EXAMPLE OF PROGRAMMED DATA INPUT AND OUTPUT
The following example, explaining the function and connections of the Teletype unit and Type 649B
Teletype control, summarizes interfacing a device with programmed input and output data transfers, using
both program interrupt and I/O sk ip fac it ities.

Figure 16 shows the sequence of operations for a transfer

into the computer from the keyboard, and Figure 17 shows the sequence for printing information transferred
out of the computer.
Assume that a program is in progress and the keyboard of the Teletype is manuall)' operated to send information into the computer. When the key is struck, the control generates the 8-bit character and shifts
it into a keyboard buffer one bit at a time. When the character is complete in the register, the keyboard
flag is set to request a program interrupt.

If the program interrupt is enabled (mean ing the program in

operation can be interrupted), when the flag is rclised a break occurs at the conclusion of the instruction
in progress.

During the break cycle the contents of the link, trap mode bit, extended program counter

(EPC), and the program counter are stored at core memory address 000000, and the next instruction is
taken from address 000001 .
This instruction is usually a jump to an interrupt routine which checks the status of flags for all equipment
connected into the system. When this routine issues lOT instruction 700301, the 1 status of the keyboard
flag is identified and program control jumps to a subroutine that services the keyboard. This subroutine
. (assuming that the Land EPC need not be restored before returning to the main prc)gram) could consist of
the following:
24

OPERATING
PROGRAM

KEYBOARD
OPERATIONS
AND SUBROUTINES

BREAK REQUEST

BREAK GRANTED
(PROGRAM INTERRUPT DISABLED TO PREVENT OTHER
INTERRUPTS FROM OCCURRING UNTIL THIS INTERRUPT
IS COMPLETED)

-~~-I
I

CONTINUE PROGRAM

T
Figure 16

Programmed Data Input Flow Diagram

OPERATING
PROGRAM
INITIALIZING
COMMAND

TELEPRINTER
OPERATIONS
AND SUBROUTINES

BREAK
REQUEST

BREAK
GRANTED

I
CLEAR
TELEPRINTER
FLAG

CONTINUE PROGRAM

T
Figure 17

Programmed Data Output Flow Diagram

Octal

Mnemonic

700312-

KRB

06XXXX

DAC I STORE

20XXXX
700042
620000

LAC AC SAVE
ION
JMPIO

Remarks
/CLEAR AC, THEN LOAD AC FROM CONTENTS
/OF KEYBOARD BUFFER, AND CLEAR KEYBOARD
/FLAG
/WRITE CHARACTER AT ADDRESS CONTAINED
/IN AUTOINDEX REGISTER IISTOREII
/RESTORE AC FROM LOCATION IIAC SAVEll
/ENABLE INTERRUPT SYSTEM FOR NEXT CHARACTER
/RETURN TO MAIN PROGRAM FROM ADDRESS
/STORED IN 00000 WHEN BREAK WAS STARTED

Upon completion of this subroutine the main program continues and the keyboard awaits the next manual
key operation.
Assume that the main program has accumulated and stored data in core memory, and that the data is to
be printed by the Teletype while the main program conti~ues. When the program recognizes the need to
print, it initial izes a print subroutine (by setting an autoindex register equal to the core memory address -1
for the dater, establ ishing a check for the last character to be printed, initial izing a counter to track the
number of characters printed, etc.) and then enters the print subroutine to print the first character. The
basic print subroutine might be similar to the following:
Octal

Mnemonic

22XXXX

LAC I 10

44XXXX
741000
60XXXX
700406

ISZ COUNT
SKP
JMP END
TLS

700042

ION

620000

JMPIO

Remarks
/LOAD CHARACTER INTO AC FROM ADDRESS
/SPECIFIED BY AUTOINDEX REGISTER 10
/COUNT CHARACTERS
/NOT LAST CHARACTER
/LAST CHARACTER
/TRANSFER CHARACTER FROM AC INTO PRINTER
/BUFFER, CLEAR PRINTER FLAG, AND INITIATE
/PRINTING
/RESTORE LAND/OR EPC IF NECESSARY, THEN AC
/ENABLE INTERRUPT SYSTEM FOR NEXT CHARACTER
/BREAK
/RETURN TO MAIN PROGRAM FROM ADDRESS
/STORED IN ADDRESS 000000

Exit from this subroutine reestabl ishes the main program which now continues until interrupted by a program break. Having been initiated by the subroutine, mechanical printing of the first character continues
until complete, then raises the print flag. The print flag in the 1 state indicates that the teleprinter has
printed the last character and is ready to receive another character, and requests a program interrupt. If
the interrupt system is enabled, at the end of the current instruction the break state is entered to store the
contents of the L, EPC, and PC in address 000000. The next instruction is then taken from address 000001,
and program control is transferred to the interrupt routine. The program interrupt routine, as described
27

previously for the keyboard, senses the status of flags for all devices connected to the interrupt facility
until it determines the device requesting serViCE!. When the TSF instruction is given (lOT 700401) to skip
on the ready status of the printer flag, the print subroutine is again entered to load and print the next
character. At exit from the subroutine the main program is reentered from the point of the program break.
If the main program is an arithmetic routine that uses the I ink or a routine using extended memory, the
AC, L, and EPC must be restored by the device service routine prior to issuing the ION instruction. Restoration of the L is accompl ished by an instruction sequence such as:
Octal

Mnemonic

Remarks

200000
740010

LAC 0
RAL

/LOAD WORD CONTAINING L
/ROTATE TO RESTORE L

Restoration of the EPC is described in the PDP-7 Users Handbook, F-75, under the description of the
Type 148 Memory Extension Control.

The AC should always be restored by the :service routine.

CHAPTER 3
DATA BREAK TRANSFERS
The data break facility allows one I/O device to transfer information directly with the PDP-7 core memory
on a cycle-stealing basis. Up to four dbvices can connect to the data break facility through the optional
Type 173 Data Interrupt Multiplexer.
Data break information transfers occur directly between the computer MB and a data register of the device,
and therefore do not affect the arithmetic or program control elements of the PDP-7. Transfer rates of up
to 571,000 words per second, or over 10 million bits per second, can be realized through this independent
data handling channel.
Figure 18 shows information flow to effect a data break transfer with an I/o device. Figure 19 indicates
timing requirements for input and output control and data signals, and the availability of register data
signals.

DATA
ADDRESS

MEMORY
ADDRESS
REGISTER
(MA)

(15)

DATA
INFORMATION
(18 BITS IN)
MEMORY
BUFFER
REGISTER
(MB)

DATA
INFORMATION
(18 BITS OUT)

DATA
BREAK
FACILITY

CONNECTIONS TO
INPUT I OUTPUT
DEVICE

ADDRESS
ACCEPTED

DATA
ACCEPTED

DATA
READY

...

DATA BREAK ...
REQUEST
:-" TRANSFER
.... DIRECTION (IN)
~

Figure 18

Data Break Transfer Interface Block Diagram

External devices requesting storage or retrieval access to core memory supply the following signals to
the computer:
DATA BREAK REQUEST

- 3v for assertion

TRANSFER DIRECTION

- 3v for into PDP-7, ground for out

DATA ADDRESS (15 bits)

- 3v for 1, ground for 0

DATA INFORMATION (18 bits)

- 3v for 1, ground for 0

~
,-

.'1

600 NSEC

DATA BREAK
REQUEST

NO REQUEST

T7
I
--T

Tl
1
I

390 NSEC

I
al

600 NSEC

T3
T4
T5
I
I
I
- - - - ----.- -- - - - - - - - - , - - - , - -

EARLIEST POSSIBLE TIME TO REMOVE REQUEST
'.:...:'T~N~F~DRES~ACCEP~D _ _ _ _ _ -.J

----------------,

NOT AVAILABLE

.,.

T2
I

LATEST POSSIBLE TIME
TO REQUEST A BREAK
FOR THE NEXT CYCLE

REQUEST

TRANSFER
DIRECTION

a,.

T5
T6
L _____ I _

COMPUTER TIME

760 NSEC

LATEST POSSIBLE TIME TO DETERMINE DIRECTION IS T3
____________________________________

T6
I
---T

1.-,20 NSEC
,
" - - 6 4 0 NSEC

TI
"

T3
,

REQUEST MUST BE REMOvED BY T5
IF NEXT CYCLE IS NOT TO BE A BREAK

EARLIEST POSSIBLE TIME TO REMOVE DIRECTION IS AT END
_DATA
__
_ _(IN)
_OR
_DATA
__
_(OUT)
____________ _
OF
ACCEPTED
READY

AVAILABLE
LATEST POSSIBLE TIME TO
DETERMINE ADDRESS iSTI- .,
OF BREAK

NOT AVAILABLE
DATA ADDRESS

EARLIEST POSSIBLE TIME TO REMOVE ADDRESS
IS AT END OF ADDRESS ACCEPTED

AVAILABLE

NOTAVAILABLE - - - , - DATA INFORMATION
(TO COMPUTER)

-,
LATEST POSSiBLE TiME TO DETERMINE --,
INPUT WORD IS AT T3

AVAILABLE

w
o

GROUND
ADDRESS ACCEPTED
(70-NSEC PULSE)

-3 VOLTS

tEARLIEST POSSIBLE TIME TO REMOVE INPUT WORD
IS AT END OF DATA ACCEPTED
------------

TI
GROUND
DATA ACCEPTED
(70-NSEC PULSE)

-3 VOLTS

u
I

T3
GROUND
DATA READY
(400-NSEC PULSE)

-3 VOLTS

!==

NOT AVAILABLE

DATA INFORMATION
(FROM COMPUTER)

AVAILABLE
NO BREAK
BREAK CYCLE

BREAK

Figure 19

Data Break Transfer Timing Diagram

T2+325 NSEC

The computer provides the following signals to the device using the data break facility:
Standard DEC 70-nsec negative pulse when

ADDRESS ACCEPTED

device-supplied address is strobed into MA.
Standard DEC 70-nsec negative pulse when'

DATA ACCEPTED

device-supplied information is strobed into MB.
Standard DEC 400-nsec negative pu Ise when

DATA READY

information is avai lable in MB for strobing
by external device. The external device can
use this pulse to strobe the MB information into
its register either directly or (when gate set-up
time is required) after a delay of up to 1 !-,sec.
DATA INFORMATION (18 bits)

- 3v for 1, ground for 0

DATA BREAK FACILITY
The data break facility controls entry into the break state to execute a data break, and produces the
pulses that strobe address and data into the computer and indicate data is ready to be strobed out of the
computer. Figure 20 shows the interface circuits of the data break facility.
Data break requests are synchronized with the computer timing cycle and the execution of instructions
by a DATA SYNC flip-flop. The T5-DlY pulse (T5 delayed 50 nsec) sets this flip-flop if the DATA
BREAK REQUEST (or DATA RQ) signal level is at - 3v (making a request), or clears it if the request is
not made (signal level is at ground). When set, the DATA SYNC flip-flop causes generation of a BK RQ
(or BREAK REQUEST) signal level that establishes the break state for the next cycle if the current cycle
completes an instruction. Therefore, to initiate a data break the DATA BREAK RE QUEST signal must be
present (negative) at the time the T5-Dl Y pulse occurs during the cycle immediately preceding the break.
Similarly, when the break is granted the DATA BREAK REQUEST signal must be removed (ground or open)
by the time the T5-DlY pulse occurs or the next cycle will also be a break state.
Note that a break state (but not a data break) can also be caused by a program interrupt (PROG SYNC (1)
signal) or by the real-time clock (ClK SYNC (1) signal).
The 1 status of the DATA SYNC flip-flop combines with the break condition of the major state generator
to produce a DATA. B signal level that enables generation of the ADDRESS ACCEPTED (or ADDR ACC),
DATA ACCEPTED (or DATA ACC), and DATA READY (or DATA RDY) pulses.

Figure 20

Data Break Foci lity Interface of Computer

The 70-nsec negative ADDRESS ACCEPTED pu Ise occurs at T1 time of all data break cyc les to strobe the
15 device-supplied DATA ADDRESS signals into the computer MAand EMA (extended MA) registers.
This pulse, available at the interface, can be used by the device to remove the DATA BREAK REQUEST
signal or to clear or change the data register in preparation for the next cycle.
The 70-nsec negative DATA ACCEPTED pulse occurs at T3 time of the data break cycle if the devicesupplied TRANSFER DIRECTI'ON signal level is at - 3v to specify a data direction into the computer.
This pulse strobes the 18'devic,e-supplied DATA INFORMATION signals into the MB and is available at
the interface for use by the device to clear and/or change the data buffer register for the next cycle.
The direction of a dat<:J break transfer is always ,stated with respect to the computer. The TRANSFER
DIRECTION signal should be - 3v to specify a tra'n'sferinto the PDP-7, or should be ground to specify
a transfer out of the PDP-7. This signal should be presen~(:1t th~ time the data break request is mode;
however, it need not be present unti I T3 of the break cy<;:I,e.'
The 400-nsec negative DATA READY pulse occurs at T3time of all data break cycles. This pulse is not
used in the computer but is produced for the device to u,se directly, or delayed to allow for gate setup
time, to strobe the 18 computer DATA INFORMATION signals into its data buffer register.

DATA ADDRESS
Fifteen DATA ADDRESS (or DA) signals are recieved from the external device to specify the core memory
address to be used for the data break transfer. These signals are - 3v to signify a binary 1. They shou Id
be present when the data break request is made, but may be delayed if they are settled prior to T1 time
of the break cycle. These sign~ls'are received by'a2-input NAND gate at the 1 input of each MA flipflop and extended MA flip-flop. Since the MA contains 13 bits, the flip-flops are designated MAS through
MA17. The two extension fl ip-flops are added to the IT,Iost significant end of the register and are designated EMA3 and EMA4. Each of these flip-flops is loaded with the information on the DATA ADDRESS
lines suppl ied by the device when the ADDRESS ACCEPTED pu Ise occurs. The data break fac iI ity generates the ADDRESS ACCEPTED pulse at T1 time of a break cycle caused by a negative DATA BREAK
REQUEST signal. Figure 21 shows this data address interface logic of the computer.

DATA INFORMATION INPUT AND OUTPUT
Input data from an external device is received by the MB during a data break as 18 DATA INFORMATION
(or DI) signal levels. The DATA INFORMATION input signals should be present when the data break
request is made, but can be delayed if they are settled prior to T3 time of the break cycle. Each - 3v
signal (binary 1) enables a 2-input NAND gate at the 1 input of an MB flip-flop. The DATA ACCEPTED

pulse strobes all these gates. This pulse is generated in the data break facility at T3 of the break cycle
by negative DATA BREAK REQUEST and TRANSFER DIRECTION signals which request an input data break.
Figure 22 shows the data information input interface to the MB.

Figure 21

Data Address Input Interface of Computer

Output data from the computer during a data break is supplied to the external device as an- l8-bit MB
buffered DATA INFORMATION word. The negative binary 1 output of each MB flip-flop is buffered by
a non-inverting bus driver and supplied to the interface connection for strobing by the device. The
DATA INFORMATION signals are available by T3 time of the break cycle and must be strobed by the
DATA READY pulse (or a pulse derived from it) no later than 400 nsec after T2 time of the cycle following the break. Figure 22 also shows this data information interface logic of the computer.

Figure 22

Data Information Input and Output Interface of Computer

CHAPTER 4
DIGITAL LOGIC CIRCUITS

All component circuits in the PDP-7 are standard digital logic circuits as described in the Digital Logic
Handbook, C-105. Functiona I operation of basic circuits, typica I appl ications, and detai led descriptions
for the complete line of circuit modules available for construction of interfaces are presented in this catalog. The PDP-7 uses four types of circuits to transmit or receive signals from other equipment--inverters,
bus drivers, pulse amplifiers, and diode gates.

INVERTERS
Type B105 Inverter modu les are used throughout the computer for gating, inverting, and buffering. The
DATA BREAK REQUEST (or DATA RQ) signal is received from external equipment by a B105 in the data
break facility. The PROGRAM INTERRUPT REQUEST (or PROGRAM REQ) signal is received from I/O
devices by a B124 Inverter module. Internal common collector connections on groups of three inverters
facilitate use of this module as a logical NOR gate for negative signal levels.
The Type B201 FI ip-Flop modules in both the MA and MB use two series-connected inverters as 2-input
NAND gates. Schematically, these i'nverters are identical to _those of the B105 modu Ie. In data break
transfers, these gates receive the DATA ADDRESS signats in theMA and receive the DATA INFORMATION
signals in the MB. In each case the inverter nearest the flip-flop is triggered by an internally generated
70-nsec pulse, and the data signal is received at the' inverter with the grounded emitter.
Each inverter is analogous to a switch. If the inverter base is at - 3v and the inverter emitter is at ground,
the PNP transistor is saturated and a condu~ting pathi~ es~abli~hed between the emitter and collector. If
the base is at ground, the emitter-collector path is open-circuited (i.e., will not allow current to flow)
and there is no static-load. When the base input is at-'3v, the static load is1 ma • The base can reject

o.5v of noise. Delay through the inverter is approximately 12 nsec for I ig-htly loaded inverters driven by
a pulse. Figure 23 shows the inverter circuit' schematically.

BUS DRIVERS
Type R650 Bus Driver modules are used by th~ ID to drive AC'output lines in programmed data output
transfers. The R650 contains two inverting bus drivers for-driving heavy current loads to either ground or
negative voltages. In this application, terminals H'and S are grounded to insert an integrating capacitor
into the circuit to avoid ringing on long lines. The driver operates with typical output rise and fall delays
37

of 50 nsec, and total transmission time of 800 nsec for output rise and 700 nsec for output fall. If this
ground connection is removed, the bus driver operates with typical rise and fall times of 25 nsec, typical
total transition times of 60 nsec for output rise and 65 nsec for output fall. The standard DEC level output
can drive 20 ma of external load at either ground or - 3v. Figure 24 is a schematic of the output circuit
of the bus driver.
-3V

-t5V

L4'."

56,u F

£~rA.·.
~

Figure 23

Inverter Circuit

+10V
410
.J\.

O.01/LF

~-= 82.fi
OUTPUTS

500
.J\.

-15V

Figure24

Bus Driver Output Circuit

Type 8684 Bus Driver modules are used by the MS to drive the DATA INFORMATION or MBS lines in
data break output transfers. The 8684 contains two noninverting bus drivers and a - 3v supply. Each bus
driver provides standard DEC output levels capobleof driving ±40 rna. Delay through the driver is approximately 30 nsec. The output circuit is similar to that of the Type R650 shown in Figure 24.

PULSE AMPLIFIERS
Type W640 Pulse Amplifier modules in the DS reproduce or buffer lOT command pulses. The W640 contains
three standardizing pulse amplifiers. Delay thrc>ugh the pulse amplifier is approximately 40 nsec. Output
pulses can be either 1 ~sec (if E and F are connected together) or 400 nsec wide (E and F open). No

connections should be made to terminals E or F (L or M, S or T) other thqnshorting them together to obtain
l-\Jsec'output pulses. Output is a DEC standard 2.5v, 400~nsec pulse (1- \Jsec, , if E and F ~re shorted)
which o~curs every time the- input signal meets the input requirement. The output is negative if the
positive terminal is grounded. Each output can drive lOrna of load (equivalent to 10 inverter bases).
These amplifiers should not be used without a terminating resistor; typical values are 47 to 150 ohms.
A schematic of the output circuit is shown in Figure 25.

390.1\.

-15V

Fi~ure 25

Pulse Amplifier Output Circuit

A Type W607 Pulse Amplifier module in the data break facility provides'fheADDR ACC, DATAAC'C,
and ~ATA RDY pulses. The W607 contains three standardizing pulse a~plifiers. The output is a stand.ard
70-nsec, 2.5v pulse. Delay through the pulse af'!1plifier is apprpximately 20 nsec. It occurs at the output every time the input signal meets the input requirement. The output is n~gati.ve if the positive terminal
is grounded. Each output can drive lOrna of load (equivalent to 10 inverter bases). These amp.'ifiers
should not be used with-out a terminating resistor. When driving 1 to 5 rna of load, the line may, be ter-:minated by 47 ohms to ground; and when driving 6 to 10 rna of load, 82 ohms to ground. These values
are approximate and depend on length of the line. The output circuit is similar to that of the Type W640
shown in Figure 25.

DIODE GATES
Type R141 Diode Gate modules are used in the IC and lOS to receive signals from peripheral devices.
The R141 consists of seven 2-input diode AND gates for negative signals whose outputs supply the inputs
to a diode NOR gate. Back-to-back diode circuit operations are facilitated by an internal bias resistor
connected to the input of each second stage diode. The bias holds the input of the second stage at - 3v
unless one of the first stage inputs is grounded. The total transition time is 45 nsec for output rise and
70 nsec for output fall. The input receives standard 100-nsec pulses, standard levels of - 3v and ground,

or 70 nsec negative pulses. Input load is 1 mCl per input pair shared by the gmunded inputs. When any
pair of inputs is not being used, at least one of the two must be grounded.

Fi~Jure 26 shows the basic

circuit configuration.
-15V
O.7V

INPUTS

-t5V

+tOV

INPUTS

I
I

Figure 26

Diode Gate Circuit

A Type 8171 Diode Gate module is used in the I/O package to receive SLOW CYCLE REQUEST signals.
The 8171 is a 12-input diode NOR gote for ground level signals. An additioncil inverter allows complementary output signals. Typical total transition time is 40 nsec for output fall land 60 nsec for output
rise. Static input load is 1 .25 ma.
A Type 5115 Diode Gate module in the data break facility receives the TRANSFER DIRECTION (DATA
IN) signal from the external device. The 8115 consists of three 3-input diode NAND gates for negative
signals. The TRANSFER DIRECTION signal supplies one input to one of these glates. The remaining two
inputs are supplied by a negative level and a negative timing pulse produced within the computer. The
1 • 25-ma static load is shared by all inputs at ground.

CHAPTER 5
INTERFACE CONNECTIONS

INTERFACE CONNECTIONS AND SIGNAL IDENTIFICATION
All signals interchanged between the PDP-7 processor and the peripheral equipment pass through the
interface section of the I/o package in the computer. Interface connections are made either by coaxial
cable or by ribbon cables terminated in a Type W021 Signal Cable Connector (described in detail in the
Digital Logic Handbook, C-105). The cable connector plugs into the appropriate FLIP CHIP module receptacles in rows Hand J of bay 3 (containing the I/O package). Figure 27 shows the relative location
and signals assigned to these connectors. Some cable connections, for the Type 177B EAE option for example, are made directly to the processor in bay 2. In genera I, a II interface connections to the processor
are made through the I/o package, except for options that are normally installed at the factory when the
system is bui It.
In any system, bays are numbered from left to right as viewed from the front. Rows of modules are lettered
from top to bottom within one prewired option. Module receptacles are numbered from left to right as
viewed from the wiring side at the front of the machine or from right to left as viewed from the module
side at the back of the mach ine. Term ina Is of a modu Ie receptac Ie are assigned capita I letters from top
to bottom, omitting G, I, 0, and Q. For example, A03E in the I/o package is in the top module row (A),
the third connector from the left (03), and the fifth terminal from the top (E).
All logic signals that pass between the PDP-7 and the I/o equipment are standard DEC levels or standard
DEC pulses. Logic signals have mnemonic names that indicate the condition represented by assertion of
the signal. Standard levels are either ground potential (O.O to - 0.3v) designated by an open diamond

(----<» or are - 3v (- 3v to -4.Ov) designated by a solid diamond (

. ) . Standard pulses in the posi-

tive direction are designated by an open triangle (--I> ), and negative pulses are designated by a solid
triangle (---.. ). Pulses originating in R series modules are positive-going pulses which start at - 3v, go
to ground for 100 nsec, then return to -3v. Pulses originating in B or W series modules are bipolar, are
always referenced to ground, are 2.5v in amplitude (2.3 to 3.Ov) with a 2v overshoot, and are of 400-nsec
duration (or 1 I-Isec if selected on the W640) .
Tables 1 and 2 provide connections, distribution, and logic circuit information for the basic PDP-7 interface signals. Numbers in the "Drawing Number" column of these tables should be prefixed by
"BS-D-KA lA-O-" or IBS-D-KA77A-0-" to form the complete number of engineering drawing that shows

DATA ADDRESS 3-8

DATA ADDRESS 9-17

DATA ADDRESS 3-8

DATA ADDRESS 9-17

ti ~~ O'l"I

g-o

,....
~ ~~ I

~Zcp

O'l

g-o

C\J

co
N

173 SIGNALS

172 API MBB'S

173 SIGNALS

_ct)

340 SIGNALS

57A SIGNALS

'.37 A SIGNALS

C\J
<[

_ct)

,....

C\J

139E SIGNALS

10 0

r<l

172 API CHANNEL FLAGS 0-7

C\J
N

.ct)

10 f-

138E SIGNALS

O'l

172 API SIGNALS

,....

~Zcp

172 API CHANNEL FLAGS 10-17

O'l

.2
-+-

~g;
f-

C\J

ct)

<[
,....

1-°
52
~

0::

I-~
LL
Z

-I

C\J

CD
0::

r<l

,....

0
10
10

,....

CD
<J

0
10
10

,....

0::

::!:

,....

172 API CHANNEL FLAG CLEARS 0-7

!::I

172 API CHANNEL FLAG CLEARS 10-17

IC LEVEL 7 9-17

177 EAE

IC LEVEL 7 0-8

IC 0-8 TO PROCESSOR

IC LEVEL 6

IC 9-17 TO PROCESSOR

SC: SIGNALS

I-

w
o ~~

O-B

IC LEVEL 5 9-17

MISCELLANEOUS PROCESSOR SIGNALS

Ie LEVEL

5 0-8

MISCELLANEOUS PROCESSOR SIGNALS

IC LEVEL

4 9-17

PROCESSOR TIMING PULSES

0
<J

I- z
0

o 1 - <i=[
::!:
0::
0

IC LEVEL 4 0-8

MISCELLANEOUS PROCESSOR SIGNALS

Ie LEVEL :3 9-17

MISCELLANEOUS PROCESSOR SIGNALS

r<l

IC LEVEL 3 0-8

MBB 4 (0) - 12 (0)

MBB 0 (1)- 8 (1)

I-~

I-

- - --MBB 0 (1)-8(1)

MBB 9 (1)-17 (1)
MBS 9 (1)-17 (1)

-+U

ID
C

ID
-'l

I-~

r...

....J

I-f<[

:!:

0::
0

CD
1-0::

I/)

~
c
o
c

I-

I/)

O'l

E
c

-0

I/)

-+C

~
rID

-+C

signal destination or signa I origin in the I/o package or processor. Table 3 Iists the prewired interface
term ina Is and connectors. This prewiring simpl ifies insta Ilation of standard PDP-7 options. Because of
the large number of options avai lable, there is redundancy in the interface-connector wiring. This redundancy has been planned so that two options not likely to be included in the same system use a common
connector. Some wiring changes and/or ground jumper disconnections are required when connecting any
device wh ich the interface connectors are not prewired to receive. Note that a Iternate term ina Is of the
Type W021 Signal Cable Connectors carry ground lines for cable shields. These grounds on terminals C,
F, J, L, N, R, and U are not listed in Table 3.

LOADING AND DRIVING CONSIDERATIONS
All interface circuits within the PDP-7 consist of series Rand W FLIP CHIP modules. When interconnecting
these circuits with those in the peripheral equipment, it is important to keep the load on each circuit
within its driving ability. Driving and loading capabilities of most DEC modules used in the PDP-7 and
in standard DEC optional equipment are specified in detail in the Digital FLIP CHIP Modules Catalog,
C-l05.
All inputs to series R modu les consist of either diode gate or diode-capacitor-diode (DCD) gate circuits.
All inputs draw current in the same direction. Each diode gate input at ground level draws 1 ma. The
output of a diode gate with an internal clamped load resistor can drive an la-ma external load. A flip. flop consists of two cross-connected diode gates. The di rect set and c lear terminals draw 1 ma. The output capability is 20 ma, less 2 ma for the load resistor permanently connected in the flip-flop, and 1 ma
required to condition the opposite side of the flip-flop. The flip-flop can, therefore, drive a 17-ma external load.
The DCD gate circuits on flip-flops and pulse amplifiers draw 2 ma at the level inputs, 3 ma at the pulse
inputs when the level is conditioned, and 1 ma when the level input is disabled. When two DCD gates
are driving both sides of the same flip-flop, the load on both pulse inputs totals only 4 ma. When the
level inputs are tied together as in a complement configuration, the total input load is only 3 ma.
Capacitive loading adversely affects the performance of series R modules; therefore, where long lines are
being driven, extra clamped loads should be added to sufficiently discharge the cable capacitance. As
a general rule, an extra 2 ma of clamped-load current should be added for every foot of wire beyond
1-1/2 ft. An exception to this rule is the R650 Bus Driver module. This module is designed to drive coaxial cable of 100-ohm characteristic impedance through a series driving resistor. If coaxial cable is not
used, the direct output may be used when the lines are short. If reflections occur on the line, the resistive output of the bus driver may be used to correct the problem. Shunt termination on the far end of the
transmission line is not recommended.

TABLE 1 INPUT SIGNALS
Signal Destination in I/o Package KA71A

Signal

Symbol

RSOO(l )

Module
Terminal

Module
Type

Logic
Element

Drawing
Number

---+

E01F

R141

RB01(1)

---+

E02F

R141

RB02(1)

----.

E03F

R141

RB03(l )

--+

E04F

R141

RB04(1)

---+

E05F

R141

RB05(l)

---+

E06F

R141

RB06(1)

---+

E07F

R141

RB07(l)

---+

E08F

R141

RB08{l)

---+

E09F

R141

RB09(1)

---+

F01F

R141

RB 10(1)

---+

F02F

R141

RBll (1)

---.

F03F

R141

RB 12(1)

---+

F04F

R141

RB 13(1)

---+

F05F

R141

RB14(l)

---+

F06F

R141

RB 15(1)

---+
---+

F07F

R141

F08F

R141

RB 16(1)

Interface
Connector

'Signal Destination in Proc:essor KA77A
Module
Terminal

Module
Type

Logic
Element

Drawing
Number

TABLE 1

INPUT SIGNALS (continued)

Signal Destination in I/o Package KA71A

.J:o..

Signal

Symbol

RB 17(1)

--+

MQOO(l)

---.

MQ01(l)

Signal Destination in Processor KA77A

Module
Terminal

Module
Type

Logic
Element

Drawing
Number

F09F

R141

H03D

E01L

R141

--+

H03E

E02L

R141

MQ02(l)

--+

H03H

E03L

R141

MQ03(1)

--+

H03K

E04L

R141

MQ04(l)

--+

H03M

E05L

R141

MQ05(1)

--+

H03P

E06L

R141

MQ06(1)

--+

H03S

E07L

R141

MQ07(1)

--+

H03T

E08L

R141

MQ08(1)

--+

H03V

E09L

R141

MQ09(l)

--+

H04D

F01L

R141

MQI0(1)

--+

H04E

F02L

R141

MQll (1)

--+

H04H

F03L

R14l

MQ12(1)

--+

H04K

F04L

R141

MQ13(1)

--+

H04M

F05L

R14l

MQ14(l)

--+

H04P

F06L

R141

Interface
Connector

4
-

Module
Terminal

! --

Module
Type

Logic
Element

Drawing
Number

TABLE 1

INPUT SIGNALS (continued)

Signal Dest~nation in I/o Package KA71A
Signal

Symbol

MQ15(l)

Signal Destination in Processor KA77A

Interface
Connector

Module
Terminal

Module
Type

logic
Element

Drawing
Number

--+

H04S

F07l

R14l

MQ16(1)

--+

H04T

Foal

R14l

MQ17(l)

--+

H04V

F09l

R14l

DTlOO(l)

--+

1H05D

E01N

R14l

DTIOl (1)

--+

1H05E

E02N

R141

DTI02(1)

--+

lH05H

E03N

R141

DTI03(l)

--+

1H05K

E04N

R141

DTI04(l)

--+

1H05M

E05N

R141

DTl05(l )

--+

1H05P

E06N

R141

DTI06(l)

1H05S

E07N

R141

DTI07(l)

--+

1H05T

E08N

R14l

DTl08(l)

--+

1H05V

E09N

R14l

DTI09(l)

--+

1H06D

F01N

R14l

DTllO(1)

--+

1H06E

F02N

R141

DTlll(1)

--+

1H06H

F03N

R141

DTI12(l)

--+

1H06K

F04N

R141

Module
Terminal

Module
Type

logic
Element

Drawing
Number

TABLE 1

INPUT SIGNALS (continued)

Signal Destination in I/o Package KA71A

""'-I

Signal Destination in Processor KA77A

Signal

Symbol

Interface
Connector

Module
Terminal

Module
Type

Logic
Element

Drawing
Number

DTl13(1)

--+

1H06M

F05N

R14l

DTl14(1)

--+

lH06P

F06N

R14l

DTI15(1)

---+

1H06S

F07N

R14l

DTl16(1)

--+

1H06T

F08N

R141

DTl17(1)

----+

1H06V

F09N

R141

CA03(1)

--+

H07K

E04R

R14l

CA04(1)

--+

H07M

E05R

R141

CA05(1)

----+

H07P

E06R

R141

CA06(1)

---+

H07S

E07R

R141

CA07(1)

--+

H07T

E08R

R141

CA08(1)

---+

H07V

E09R

R14l

CA09(1)

---+

HOOD

F01R

R141

CAl 0(1)

---+

HOSE

F02R

R14l

CAll (1)

---+

HooH

F03R

R14l

CAl 2(1)

----+

HOOK

F04R

R14l

CAl 3(1)

--+

HOSM

F05R

R14l

Module
Terminal

Module
Type

Logic
Element

Drawing
Number

TABLE 1 INPUT SIGNALS (continued)
Signal Destination in I/o Package KA71A
Signal

Symbol

Signal Destination in Processor KA77A

Interface
Connector

Module
Terminal

Module
Type

Logic
Element

Drawing
Number

CA14(1)

--+

H08D

F06R

R141

CA 15(1)

---+

H08S

F07R

R141

CA 16(1)

---+

H08T

F08R

R141

CA17(l)

H08V

F09R

R141

DATA FLG

--+

H09D

E01T

R141

BLK FLG

---+

H09E

E02T

R141

ERR FLG

--...,

H09F

E03T

R141

OFF END

----+

H09K

E04T

R141

MISS IND

H09M

E05T

R141

REV STATUS

H09P

E06T

R141

H09S

E07T

R141

MRK TRK ERR

--+

H09T

EOST

R141

UNABLE

--+

H09V

E09T

R141

DR LATE

--+

H10D

E01V

R141

PARITY ERR

---+

H10E

E02V

R141

READ COMP ERR

H10H

E03V

R141

Module
Terminal

Module
Type

'--------

Logic
Element

Drawing
Number

TABLE 1 INPUT SIGNALS (continued)
Signal Destination in I/o Package KA71A
Signal

EOF
WRITE LOCK
LOAD POINT
END POINT
TRD/WR LR
A/B FR
~

--0

TTIOO(l)
TTIOl (1)
TTl02(l)
TTI03(l)
TTlO4(1)

Symbol

Signal Destination in Processor KA77A

Interface
Connector

Module
Terminal

Module
Type

Logic
Element

Drawing
Number

•

H10K

E04V

R141

--+

H10M

E05V

R141

H10P

E06V

R141

H10S

E07V

R141

Hl0T

EOSV

R141

H10V

E09V

R141

F02T

R141

F03T

R14l

F04T

R14l

F05T

R141

F06T

R14l

•
•
--+
--+

•
--+
--+
--+
--+

TTl05(l)

•

F07T

R14l

TTI06(1)

--+

FOST

R14l

TTl 07(1 )

•

F09T

R14l

R141

R14l

REWIND
MISS CHAR

--+
--+

HllD

F01V

HllE

F02V

I
!
II

Module
Terminal

Module
Type

I
I

Logic
Element

Drawing
Number

TABLE 1

INPUT SIGNALS (continued)

Signal Destination in I/o Package KA71A
Signal

Symbol

Signal Destination in Processor KA77A

Interface
Connector

Module
Terminal

Module
Type

logic
Element

Drawing
Number

•

HllH

F03V

R141

----+

HllK

F04V

R141

•

HllM

F05V

R141

----+ '

HllP

F06V

R141

----+

HllS

F07V

R141

(F08V)

----+

HllT

F08V

R141

(F09V)

----+

HllV

F09V

R141

PIE (1)B

----+

E01J

R141

RDR FlG(l)

----+

E02J

R141

PUN FlG(1)

----+

E03J

R141

KBD FlG(l)

----+

E04J

R141

F PRINTER FlG(l)

----+

E05J

R141

DPY FlG(l)

----+

E06J

R141

ClK FlG(l)

----+

E07J

R141

ClK EN(l)

•

E08J

R141

----+

E09J

R141

57A JOB DONE

(F04V)
(F05V)
(F06V)
(FON)
I

Module
Terminal

Module
Type

logic
Element

Drawing
Number

57A JOB DONE(l)

TABLE 1 INPUT SIGNALS (continued)
Signal Destination in I/o Package KA71A
Signal

Symbol

Module
Terminal

Module
Type

Logic
Element

SC12(1 )

F04J

R141

SC13(1)

F05J

R141

5C14(1)

F06J

R141

SC15(1)

F07J

R141

SC16(1)

F08J

R141

SC17(1)

F09J

R141

---

Interface
Connector

Signal Destination in Processor KA77A
Drawing
Number

EICOO

---I>

E13D

E01D

R141

EIC01

---C>

E13E

E02D

R141

EIC02

----t>

E13H

E03D

R141

EIC03

--t>

E13K

E04D

R141

EIC04

----t>

E13M

E05D

R141

EIC05

----t>

E13P

E06D

R141

EIC06

--I>

E13S

E07D

R141

EIC07

--C>

E13T

E08D

R141

EIC08

--I>

E13V

E09D

R141

--I>

F13D

FOlD

R141

EIC09
-----

Module
Terminal

Module
Type

Logic
Element

Drawing
Number

TABLE 1

INPUT SIGNALS (continued)

Signal Destination in I/o Package KA71A
Signal

Symbol

EIC10

Signal Destination in Processor KA77A

Interface
Connector

Module
Terminal

Module
Type

Logic
Element

Drawing
Number

--t>

F13E

F02D

R141

EICll

---I>

F13H

F03D

R14l

EIC12

---I>

F13K

F04D

R141

EIC13

---{>

F13M

F05D

R141

EIC14

--t>

F13P

F06D

R141

EIC15

--t>

F13S

F07D

R141

EIC16

--t>

F13T

F08D

R14l

EIC17

--f>

F13V

F09D

R141

DA03

H32K

C18M

B201

DA04

--+

H32M

C19M

B201

DA05

--.

H32P

C20M

B201

DA06

H32S

C21M

B201

DA07

--+

H32T

C22M

B20]

DA08
,

--+

H32V

C23M

B201

DA09

---+

J32D

C24M

B201

DA10

--+

J32E

C25M

B201

Module
Terminal

Module
Type

Logic
Element

Drawing
Number

Ul
"-.)

_._---_.-

TABLE 1

INPUT SIGNALS (continued)

Signal Destination in I/o Package KA71A
Signal

Symbol

Signal Destination in Processor KA77A
Drawing
Number

Module
Terminal

Module
Type

Logic
Element

prawing
Number

J32H

C26M

B201

--+
--+
--+

J32K

C27M

B201

J32M

C28M

B201

J32P

C29M

B201

J32S

C30M

B201

DA16

--+
--+

J32T

C31M

B201

DA17

--+

J32V

C32M

B201

DIOO(1)

H30D

E02M

B201

H30E

E03M

B201

H30H

E04M

B201

DI03(1)

--+
--+
--+
--+

H30K

E05M

B201

DI04(1)

--+

H30M

E06M

B201

DI05(1)

--+

H30P

E07M

B201

D 106(1)

•

H30S

E08M

B201

0107(1)

--+

H30T

E09M

B201

0108(1)

--+

H30V

E10M

B201

DAll
DA12
DA13
DA14
DA15

•

Interface
Connector

Module
Terminal

Module
Type

logic
Element

DlOl (1)
DI02(1)

TABLE 1

INPUT SIGNALS (continued)

Signa I Destination in I/o Package KA71A

Signal

Symbol

DI09(1)

--+

Dll0(1)

Interface
Connector

Drawing
Number

Module
Terminal

Module
Type

Logic
Element

Drawing
Number

J30D

EllM

B201

--+

J30E

E12M

B201

DIll(1)

--+

J30H

E13M

B201

DI12(1)

--+

J30K

E14M

B201

DIl3(1)

--+

J30M

E15M

B201

Di i4(1)

--+

J30P

E16M

B201

DI15(1)

--+

J30S

E17M

B201

DI16(l)

--+

J30T

E18M

B201

D117(1)

--+

J30V

E19M

B201

ICOO(1)

---+

Jl0D

HJ2JL

B210

ICOl (l)

--.-.

J10E

HJ3JL

B210

iC02(1 )

---+

jiOH

HJ4JL

B210

IC03(1)

--.-.

J10K

HJ5JL

B210

IC04(1)

--+

J10M

HJ6JL

B210

IC05(1)

--+

Jl0P

HJ7JL

B210

IC06(1)

--+

Jl0S

HJ8JL

Module
Terminal

Module
Type

Logic
Element

Signal Destination in Processor KA77A

- -

B210
- _ .. _-_.--

-~-

TABLE 1

INPUT SIGNALS (continued)

Signal Destination in I/o Package KA71A

0'1
0'1

Signal

Symbol

IC07(1)

---+

IC08(1)

Signal Destination in Processor KA77A
Drawing
Number

Module
Terminal

Module
Type

Logic
Element

Drawing
Number

JI0T

HJ9JL

B210

--+

J10V

HJ10JL

B210

IC09(1 )

--+

JllD

HJllJL

B210

IC1 0(1)

--+

JllE

HJ12JL

B210

ICll (1)

--+

JllH

HJ 13JL

B210

IC12(1)

--+

Jll K

HJ14JL

B210

IC13(1)

--+

JllM

HJ15JL

B210

IC14(1)

--+

JllP

HJ16JL

B210

IC15(1)

--+

J11S

HJ 17JL

B210

IC16(1)

--+

JllT

HJ18JL

B210

IC17(1)

--+

J11V

HJ19JL

B210

lOT 0102(B)

--+

E01E

R141

lOT 0304(B)

--+

E01H

R141

MQl----. AC

--+

E01K

R141

lOT 7502

--+

E01M

R141

lOT 7404

--+

E01P

R141

Interface
Connector

J23E

Module
Terminal

Module
Type

Logic
Element

TABLE 1

INPUT SIGNALS {continued}

Signal Destination in I/o Package KA71A
Signal

Symbol

lOT 7602
lOT 7304

Interface
Connector

Signal Destination in Processor KA77A

Module
Terminal

Module
Type

Logic
Element

Drawing
Number

--+

E01S

R14l

--+

E01U

R14l

Module
Terminal

Module
Type

Logic
Element

Drawing
Number

TABLE 2

OUTPUT SIGNALS

Signal Origin in I/O Package KA71 A
Signal

Symbol

Interface
Connector

ACBOO(1 )

--<>
--<>
--<>
--<>
--<>
--<>
--<>
--<>
--<>
--<>
--<>
--<>
--<>
-<>
-<>
-<>

ACB01 (1)
ACB02(1 )
ACB03(l )
ACB04(1 )
ACB05(l)
OJ

ACB06(l )
ACB07(l )
ACB08(1 )
ACB09(l )
ACB1O(l)
ACB 11 (1 )
ACB12(l)
ACB13{1 )
ACB14{l)
ACB15(l)

Module
Terminal

Signal Origin in Processor KA77A

Module
Type

Logic
Element

Drawing
Number

Module
Terminal

Module
Type

Logic
Element

Drawing
Number

H14D-H21 D

W021

M03J

R650

AC Bus Drivers

H14E-H21 E

W021

M03T

R650

AC Bus Drivers

H14H-H21 H

W021

M04J

R650

AC Bus Drivers

H14K-H21 K

W021

M04T

R650

AC Bus Drivers

H14M-H21M

W021

M05J

R650

AC Bus Drivers

H14P-H21 P

W021

M05T

R650

AC Bus Dr i vers

H14S-H21 S

W021

M06J

R650

AC Bus Drivers

H14T -H21T

W021

M06T

R650

AC Bus Drivers

H14V-H21V

W021

M07J

R650

AC Bus Drivers

J14D-J21 D

W021

M07T

R650

AC Bus Drivers

J14E-J21 E

W021

M08J

R650

AC Bus Drivers

J14H -J21 H

W021

M08T

R650

AC Bus Drivers

J14 K-J21 K

W021

M09J

R650

AC Bus Dri vers

J14M-J21M

W021

M09T

R650

AC Bus Drivers !

J14P-J21 P

W021

M10J

R650

I
I AC Bus Drivers

J14S-J21 S

W021

M10T

R650

I AC Bus Drivers

18
l

TABLE 2

OUTPUT SIGNALS (continued)

-,-

Signal Origin in I/O Package KA71 A
Signal

Symbol

Interface
Connector

ACB 16(1)

--<>

ACB17(1)

--<>

IOTOO02

--{>

IOTOO04

Module
Terminal

Signal Origin in Processor KA77A

Module
Type

Logic
Element

Drawing
Number

Module
Terminal

Module
Type

Logic
Element

Drawing
Number

J14T-J13T

W021

MllJ

R650

AC Bus Drivers

J14V-J13V

W021

MllT

R650

AC Bus Drivers

D25F

R603

--{>

D25M

R603

IOT0102

--{>

D21T

R603

IOT0104

---{>

D21F

R603

IOT0202
- - ' ...
IOT0204

---t>

D22M

R603

---{>

D22T

R603

IOT0302

---t>

D23F

R603

IOT0304

---{>

D23M

R603

IOT0402

---I>

D23T

R603

IOT0404

--t>

D24F

R603

IOT0502

---{>

C23F

R603

IOT0504

---{>

C23M

R603

IOT0602

---I>

C23T

R603

IOT0604

----t>

C24F

R603

------

TABLE 2

OUTPUT SIGNALS (continued)

Signal Origin in I/O Package KA71 A
Signal

Symbol

IOT0702

Interface
Connector

Signal Origin in Processor KA77A

Module
Terminal

Module
Type

Logic
Element

Drawing
Number

--t>

C24M

R603

IOT0704

--1>

C24T

R603

IOTOO02{B)

--+

J07B

029U

W640

IOTOO04{B)

--+

H28M

D29N

W640

IOT0102{B)

--+

F14H

W640

IOT0302{B)

--+

F14N

W640

IOT0304{B)

--+

F14U

W640

IOT0502{B)

--+

E32H

W640

IOT0504(B)

--+

H26K

E32N

W640

IOT0602(B)

--+

H260

E32U

W640

IOT0604(B)

--+

H26E

F32H

W640

IOT0702(B)

--+

F32V

W640

IOT0704(B)

--+

F32U

W640

Ion 001

--+

032H

W640

Ion 002

--+

032N

W640

IOT1004

--+

032U

W640

lJl

-.0

H26H

Module
Terminal

Module
Type

Logic
Element

Drawing
Number

TABLE 2

OUTPUT SI GNALS (continued)

Signal Origin in I/O Package KA71 A
Signal

Symbol

Module
Terminal

Module I Logic
Type
Element

Drawing
Number

IOTll01

J24D

F30H

W640

IOTl102

--+

J24E

F30N

W640

IOTll04

--.

E30H

W640

IOTl201

--+

F30U

W640

IOT1202

--.

E31 N

W640

E31U

W640

F31H

W640

F31 N

W640

_1~_Tl20~J~~ __
0-..

Interface
Connector

Signal Origin in Processor KA77A

J24H

I --+
.-- '." . . . -....... '......-J .-. --. ._._.. ········--t--·-·----···-,.-·. ·-·.--·--+
IOTl302 I --+
H23E
IOT1301

I0T1304

Module
Terminal

Module
Type

Logic
Element

Drawing
Number

F31U
W640
DS
6
I -'---l-I_H2_3K_---+-_----+_--+_-----t
_ _-+--_-+---_-+---_ _-+-_ _

IOT2101
I

--+
--+

E27H

W640

E27N

W640

IOT2102 I
_..
,--+1--IOT2104

--+ I

_-t-

E27U

W640

IOT7002

I --+ I H24D

F27H

W640

--_ .. __.__-1-.

IOT7004

--+

H24E

F27N

W640

IOT7102

--+

H24H

F27U

W640

IOT7104

H24K

E28H

W640

TABLE 2

OUTPUT SIGNALS (continued)

Signal Origin in I/O Package KA71 A

()..

.......

Signal

Symbol

IOT7202

---+

IOT7204

---+

IOT7301

---+

IOT7302

IOT7304

--+

IOT7401

IOT7402

Interface
Connector

Signal Origin in Processor KA77A

Module
Terminal

Module
Type

Logic
Element

Drawing
Number

H24M

E28N

W640

H24P

E28U

W640

F28H

W640

F28N

W640

F28U

W640

H24T

E29H

W640

---+

H24V

E29N

W640

IOT7404

H25D

E29U

W640

IOT7501

J23D

F29H

W640

IOT7502

---+

J23E

F29N

W640

IOT7504

---+

J23H

F29U

W640

IOT7601

---+

E30H

W640

IOT7602

E30N

W640

IOT7604

---+

J23K

E30U

W640

--+
--+

J03D
J03E

MBB04(O)
MBB05(O)

H24S

Module
Terminal

Module
Type

Logic
Element

Drawing
Number

D07D

B684

MB Bus Drivers

D07N

B684

MB Bus Drivers

TABLE 2

OUTPUT SIGNALS (continued)

Signal Origin in I/O Package KA71 A
Signal

Symbol

Interface
Connector

MBB06(B)

--+
--+
--+
--+

MBB07(0)
MBB08(0)
MBB09(0)

Logic
Element

Drawing
Number

Module
Terminal

Module
Type

Logic
Element

Drawing
Number

J03H

D09D

B684

MB Bus Drivers

J03K

D09N

B684

MB Bus Drivers

J03M

D11 D

B684

MB Bus Drivers

J03P

D11 N

B684

MB Bus Drivers

J03S

D13D

B684

MB Bus Drivers

J03T

D13N

B684

MB Bus Drivers

MBB12(0)

J03V

D15D

B684

MB Bus Drivers

MBBOO(1 )

--+

H02D

W21

D22D

B684

MB Bus Drivers

MBB01 (1)

--+
--+

H02E

W21

D22N

B684

MB Bus Drivers

H02H

W21

D23D

B684

MB Bus Drivers

H02K

W21

D23N

B684

MB Bus Drivers

H02M

W21

D24D

B684

MB Bus Drivers

H02P

W21

D24N

B684

MB Bus Drivers

MBBll (0)
0-

Module
Type

--+
--+
--+

MBB10(0)

I'.)

Module
Terminal

Signal Origin in Processor KA77A

MBB02(1 )
MBB03(1 )
MBB04(1 )
MBB05(1 )

•
•
•

H02S

W21

D25D

B684

MB Bus Drivers

MBB07(1 )

--+ I
--+

H02T

W21

D25N

B684

MB Bus Drivers

MBB08(1 )

--+

H02V

W21

D26D

B684

MB Bus Drivers

MBB06(1 )

TABLE 2 OUTPUT SIGNALS (continued)
Signal Origin in Processor KA77 A

Signal Origin in I/O Package KA71 A
Signal

Symbol

MBB09{1 )

•

MBB1 0(1)
MBB11 (1)
MBB12(1 )
MBB13(l )
MBB14(1 )
0W

MBB15(1 )
MBB16(1 )
MBB17(1 )

Interface
Connector

Module
Type

Logic
Element

Drawing
Number

Module
Terminal

Module
Type

Logic
Element

Drawing
Number

J02D

W21

D26N

B684

MB Bus Drivers

J02E

W21

D27D

B684

MB Bus Drivers

J02H

W21

D27N

B684

MB Bus Drivers

J02K

W21

D28D

B684

MB Bus Drivers

J02M

W21

D28N

B684

MB Bus Drivers

J02P

W21

D29D

B684

MB Bus Drivers

J02S

W21

D29N

B684

MB Bus Drivers

' 18

J02T

W21

D30D

B684

MB Bus Drivers

J02V

W21

D30N

B684

MB Bus Drivers

•
•
•
•
•
~

Module
Terminal

TABLE 3
Signal

PREWIRED INTERFACE CONNECTIONS

Terminal

Signal

Terminal

57 A Automatic Magnetic Tape Control
ACB 00(1)

H16D

ACB 09(1)

J16D

ACB 01(1)

H16E

ACB 10(1)

J16E

ACB 02(1)

H16H

ACB 11 (1)

J16H

ACB 03(1)

H16K

ACB 12(1)

J16K

ACB 04(1)

H16M

ACB 13(1)

J16M

ACB 05(1)

H16P

ACB 14(1)

J16P

ACB 06(1)

H16S

ACB15(1)

J16S

ACB 07(1)

H16T

ACB 16(1)

J16T

ACB 08(1)

H16V

ACB 17(1)

J16V

lOT 7002

H24D

lOT 7404

H25D

lOT 7004

H24E

PWR CLR NEG

H25E

lOT 7102

H24H

BGN (B)

H25H

lOT 7104

H24K

MBB 12(1)

H25K

lOT 7202

H24M

MBB 12(0)

H25M

lOT 7204

H24P

H25P

lOT 7302

H24S

H25S

lOT 7401

H24T

H25T

lOT 7402

H24V

H25V

ERF-ERF ENB

J25D

H07D

WCO-WCO ENG

J25E

H07E

TCR

J25H

H07H

T READY

J25K

CA 03(1)

H07K

DATA ACC

J25M

CA 04(1)

H07M

ADDRESS ACC

J25P

CA 05(1)

H07P

DATA IN

J25S

CA 06(1)

H07S

DATA RQ

J25T

CA 07(1)

H07T

J25V

CA 08(1)

H07V

TABLE 3
Signal

PREWIRED INTERFACE CONNECTIONS (continued)
Terminal

Signal

Terminal

57 A Automatic Magnetic Tape Control (continued)
CA 09(1)

H08D

DR LATE

H10D

CA 10(1)

H08E

PARITY ERR

H10E

CA 11 (l)

H08H

READ COMP ERR

H10H

CA 12(1)

H08K

EOF

H10K

CA 13(1)

H08M

WRITE LOCK

H10M

CA 14(1)

H08P

LOAD POINT

H10P

CA 15(1)

H08S

END POINT

H10S

CA 16(1)

H08T

TRD/WR LR

H10T

CA 17(1)

H08V

A/B FR

H10V

REWIND

HllD

MISS CHAR

HllE

57A JOB DONE

H11 H

(F04V)

Hl1 K

(F05V)

H11M

(F06V)

Hl1P

(F07V)

H11 S

(F08V)

Hll T

(F09V)

HllV

138 Analog-to-Digital Converter
H10D

Hl1 D

H10E

HllE

H10H

Hl1 H

H10K

(F04V)

Hl1 K

H10M

(F05V)

H11 M

H10P

(F06V)

Hl1P

H10S

(F07V)

Hl1S

H10T

(F08V)

HllT

H10V

(F09V)

HllV

TABLE 3
Signal

PREWIRED INTERFACE CONNECTIONS (continued)
Terminal

Signal

Terminal

138 Analog-to-Digital Converter (continued)
H23D
H23E
H23H
(F04V)

H23K

(F05V)

H23M

(F06V)

H23P

(F07V)

HllS

(F08V)

HllT

(F09V)

Hl1V

139 Multiplexer
ACB 09(1)

J20D

lOT 11 01

J24D

ACB 10(1)

J20E

lOT 1102

J24E

ACB 11 (1)

J20H

lOT 1201

J24H

ACB 12(1)

J20K

CA 12(1)

J24K

ACB 13(1)

J20M

CA 13(1)

J24M

ACB 14(1)

J20P

CA 14(1)

J24P

ACB 15(1)

J20S

CA 15(1)

J24S

ACB 16(1)

J20T

CA 16(1)

J24T

ACB17(1)

J20V

CA 17(1)

J24V

140 Relay Buffer
ACB 00(1)

H19D

ACB 09(1)

J19D

ACB01(l)

H19E

ACB 10(1)

J19E

ACB 02(1)

H19H

ACBll(l)

J19H

ACB 03(1)

H19K

ACB12(1)

J19K·

ACB 04(1)

H19M

ACB 13(1)

J19M

ACB 05(1)

H19P

ACB 14(1)

J19P

ACB 06(1)

H19S

ACB15(1)

J19S

ACB 07(1)

H19T

ACB 16(1)

J19T

ACB 08(1)

H19V

ACB 17(1)

J19V

TABLE 3
Signal

PREWIRED INTERFACE CONNECTIONS (continued)
Terminal

Signal

Terminal

172 Automatic Priority Interrupt
Clear Flag 0-7

H12D

Clear Flag 8-17

J12D

Clear Flag 0-7

H12E

Clear Flag 8-17

J12E

Clear Flag 0-7

H12H

Clear Flag 8-17

J12H

Clear Flag 0-7

H12K

Clear Flag 8-17

J12K

Clear Flag 0-7

H12M

Clear Flag 8-17

J12M

Clear Flag 0-7

H12P

Clear Flag 8-17

J12P

Clear Flag 0-7

H12S

Clear Flag 8-17

J12S

Clear Flag 0-7

H12T

Clear Flag 8-17

J12T

Clear Flag 0-7

H12V

Clear Flag 8-17

J12V

ACB 00(1)

H18D

ACB 09(1)

J18D

ACB 01 (l)

H18E

ACB10(1)

J18E

ACB 02(1)

H18H

ACB 11(1)

J18H

ACB 03(1)

H18K

ACB 12(1)

J18K

ACB 04(1)

H18M

ACB 13(1)

J18M

ACB 05(1)

H18P

ACB 14(1)

J18P

ACB 06(1)

H18S

ACB 15(1)

J18S

ACB 07(1)

H18T

ACB 16(1)

J18T

ACB 08(1)

H18V

ACB 17(1)

J18V

Channel Flag 0-7

H22D

Channel Flag 8-17

J22D

Channel Flag 0-7

H22E

Channel Flag 8-17

J22E

Channel Flag 0-7

H22H

Channel Flag 8-17

J22H

Channel Flag 0-7

H22K

Channel Flag 8-17

J22K

Channel Flag 0-7

H22M

Channel Flag 8-17

J22M

Channel Flag 0-7

H22P

Channel Flag 8-17

J22P

Channel Flag 0-7

H22S

Channel Flag 8-17

J22S

Channel Flag 0-7

H22T

Channel Flag 8-17

J22T

Channel Flag 0-7

H22V

Channel Flag 8-17

J22V

TABLE 3
Signal

PREWIRED INTERFACE CONNECTIONS (continued)
Terminal

Signal

Terminal

172 Automatic Priority Interrupt (continued)
MBB 06(1)

H27D

IOP1

H28D

MBB 07(0)

H27E

IOP2

H28E

MBB 08(1)

H27H

IOP4

H28H

MBB 09(1)

H27K

ClK FlG (1)

H28K

MBB 10(0)

H27M

lOT 0004 (B)

H28M

MBB 10(1)

H27P

PWR CLR NEG

H28P

MBB 11 (0)

H27S

BGN (B)

H28S

MBB 11 (1)

H27T

MB 12(0)

H28T

H27V

lOT 00 EN

H28V

173 Data Interrupt Multiplexer Control
T5

J28D

J28E

DATA RQ

J28H

DATA IN

J28K

DATA ACC

J28M

ADDR ACC

J28P

DATA RDY

J28S

DATA SLO RQ

J28T
J28V
177 Extended Arithmetic Element

MQ 00(1)

H03D

MQ 09(1)

H04D

MQ 01 (1)

H03E

MQ 10(1)

H04E

MQ 02(1)

H03H

MQ 11 (1)

H04H

MQ 03(1)

H03K

MQ 12(1)

H04K

MQ 04(1)

H03M

MQ 13(1)

H04M

MQ 05(1)

H03P

MQ 14(1)

H04P

MQ 06(1)

H03S

MQ 15(1)

H04S

MQ 07(1)

H03T

MQ 16(1}

H04T

MQ 08(1)

H03V

MQ 17(1}

H04V

TABLE 3
Signal

PREWIRED INTERFACE CONNECTIONS (continued)
Terminal

Signal

Terminal

177 Extended Arithmetic Element (continued)
ACB 00(1)

H14D

ACB 09(1)

J14D

ACB01(1)

H14E

ACB 10(1)

J14E

ACB 02(1)

H14H

ACB 11 (1)

J14H

ACB 03 (1)

H14K

ACB 12(1)

J14K

ACB 04(1)

H14M

ACB13(1)

J14M

ACB 05(1)

H14P

ACB 14(1)

J14P

ACB 06(1)

H14S

ACB 15(1)

J14S

ACB 07(1)

H14T

ACB 16(1)

J14T

ACB 08(1)

H14V

ACB 17(1)

J14V

SC1-AC

Jll D

MQ1-AC

JllE
Jll H

SC 12(1)

J11 K

SC 13(1)

Jl1M

SC 14(1)

Jll P

SC 15(1)

Jll S

SC 16(1)

Jll T

SC 17(1)

JllV
340 Precision Incremental Display
H10D

Hll D

H10E

HllE

H10H

H11 H

H10K

(F04V)

Hll K

H10M

(F05V)

HllM

H10P

(F06V)

HllP

H10S

(F07V)

Hll S

H10T

(F08V)

HllT

H10V

(F09V)

HllV

TABLE 3
Signal

PREWIRED INTERFACE CONNECTIONS (contiinued)
Terminal

Signal

Terminal

340 Precision Incremental Display (continued)

ACB 00(1)

H17D

ACB 09(1)

J17D

ACB 01 (1)

H17E

ACB 10(1)

J17E

ACB 02(1)

H17H

ACB 11 (1)

J17H

ACB 03(1)

H17K

ACB 12(1)

J17K

ACB 04(1)

H17M

ACB 13(1)

J17M

ACB 05(1)

H17P

ACB 14(1)

J17P

ACB 06(1)

H17S

ACB 15(1)

J17S

ACB 07(1)

H17T

ACB 16(1)

J17T

ACB 08(1)

H17V

ACB 17(1)

J17V

lOT 0602 (B)

H26D

STOP FIG

J26D

lOT 0604 (B)

H26E

340 LP FLG

J26E

lOT 0704 (B)

H26H

DATA RQ

J26H

lOT 0504 (B)

H26K

DATA IN

J26K

H26M

ADDR ACC

J26M

H26P

DATA ACC

J26P

H26S

BGN

J26S

H26T

V EDGE FLG

J26T

H26V

HEDGE FLG

J26V

550 DECtape Control
DTI 00(1)

H05D

DTI 09(1)

H06D

DTI 01 (1 )

H05E

DTI 10(1)

H06E

DTI 02(1)

H05H

DTI 11 (1 )

H06H

DTI 03(1)

H05K

DTI 12(1)

H06K

DTI 04(1)

H05M

DTI 13(1)

H06M

DTI 05(1)

H05P

DT114(l)

H06P

DTI 06(1)

H05S

Drl 15(1)

H06S

DTI 07(1)

H05T

DTI 16(1)

H06T

DTI 08(1)

H05V

DTI 17(1)

H06V

TABLE 3
Signal

PREWIRED INTERFACE CONNECTIONS (continued)
Terminal

Signal

Terminal

550 DEC tape Control (continued)
ACB 00(1)

H15D

ACB 09(1)

J15D

ACB 01 (1)

H15E

ACB10(1)

J15E

ACB 02(1)

H15H

ACB 11 (1)

J15H

ACB 03(1)

H15K

ACB 12(1)

J15K

ACB 04(1)

H15M

ACB 13(1)

J15M

ACB 05(1)

H15P

ACB 14(1)

J15P

ADB 06(1)

H15S

ACB15(1)

J15S

ACB 07(1)

H15T

ACB 16(1)

J15T

ACB 08(1)

H15V

ACB 17(1)

J15V

DATA FLG

H09D

lOT 7501

J23D

BLK FLG

H09E

lOT 7502

H23E

ERR FLG

H09H

lOT 7504

H23H

OFF END

H09K

lOT 7604

H23K

MISS IND

H09M

RUN (1) B

H23M

REV STATUS

H09P

MBB 12(1)

H23P

H09S

550 lOT 7501

H23S

MK TRK ERR

H09T

550 lOT 7541

H23T

UNABLE

H09V

PWR CLR NEG

H23V

Unspecified Data Break Device
MBB 00(1)

H02D

MBB 09(1)

J02D

MBB 01 (l)

H02E

MBB 10(1)

J02E

MBB 02(1)

H02H

MBB 11(1)

J02H

MBB 03(1)

H02K

MBB 12(1)

J02K

MBB 04(1)

H02M

MBB 13(1)

J02M

MBB 05(1)

H02P

MBB 14(1)

J02P

MBB 06(1)

H02S

MBB 15(1)

J02S

MBB 07(1)

H02T

MBB 16(1)

J02T

MBB 08(1)

H02V

MBB 17(1)

J02V

TABLE 3
Signal

PREWIREO INTERFACE CONNECTIONS (continued)
Terminal

Signal

Terminal

Unspecified Oota Break Oevice (continued)
0100

H300

0109

J300

0101

H30E

01 10

J30E

0102

H30H

01 11

J30H

0103

H30K

01 12

J30K

0104

H30M

01 13

J30M

0105

H30P

01 14

J30P

0106

H30S

01 15

J30S

0107

H30T

DI 16

J30T

0108

H30V

0117

J30V

H320

OA 09

J320

H32E

OA10

J32E

H32H

OA 11

J32H

OA 03

H32K

OA 12

J32K

OA 04

H32M

OA 13

J32M

OA 05

H32P

OA14

J32P

OA 06

H32S

OA15

J32S

OA 07

H32T

OA16

J32T

OA 08

H32V

OA17

J32V

J28D

J28E

OATA RQ

J28H

OATA IN

J28K

OATA ACC

J28M

AOOR ACC

J28P

OATA ROY

J28S

DATA SLO RQ

J28T
J28V

The R650 Bus Driver has two types of outputs: fast and slow (or ramp). Using fast output, the bus driver
operates as a fast amplifier. When ramp output is used, an integrating capacitor is inserted between the
input of the bus driver and the output stage, causing the output lines to move from ground to - 3v (or
reverse) in approximately 800 nsec. This connection, desirable to reduce crosstalk between lines, is
used on the ACB (buffered accumu lator) lines.
The W640 Pulse Amplifier modules should be carefully terminated. If sufficient noise is generated at the
output of these modu les, regeneration may resu It. For this reason, it is recommended that output lines of
W640 Pulse Amplifier modules be well shielded. The outputs of W640 modules may be either 400 nsec or
1 ~sec in width. All connection.s on the standard PDP-7 use the 400 nsec pulse width.
All input signals to the PDP-7 are received by diode gates or inverters. Diode gate inputs draw 1 rna of
current from the driving circuit, shared among all inputs at ground potential. Inverter inputs draw 2 rna
when the signal is at - 3v and provide no load when the signal is at ground potential.
Timing is, in general, determined by the machine itself. However, the following timing considerations
apply to the modules. The Rl11 Diode Gate sets up in approximately 50 nsec in either direction under
normal load conditions.
The DCD gates set up in 400 nsec, from the end of the preceding 100-nsec pulse; and the pulse input must
return to - 3v for 400 nsec before the next pulse is applied. Series R pulses are 100 nsec in width,
measured from the 90% point of the leading edge to the 10% point of the trailing edge. Fall time is not
critical on these pulses, provided that the pulse has returned to - 3v in time to come up for the next cycle.
All output signals from the PDP-7, routed through the interface, have been provided with adequate buffering to meet the input requirements of normal I/O equipment.

Whenever it becomes necessary for the

user to draw out other signals (besides those connected in the standard interface), care must be taken that
the input loads presented to the sources of these signals do not exceed their driving obi lity. When it is
evident that the source would be overloaded, a suitable driver must be provided between the signal source
and the I/O device employing the signal.

Device Selector
The DS generates lOT pulses that control I/O equipment and effect information transfers between the
computer and peripheral devices. The DS contains a section for standard devices (program interrupt control, real time clock interrupt control, tape reader, tape punch, Teletype units, and display equipment;

or device select codes 00 through 07), and a section for optional equipment (used to expand the DS for
all other select codes). Each channel of the ()ptional DS consists of a Type W103 Device Selector module
and a W640 Pulse Amplifier module.
Complementary output signals from bits 6-11 of the lOT instruction in the MB ~::Ire di stributed to all
channels of the optional DS. These six bits serve as a device select code. The 1 or 0 signal from each

MB bit is wired or disconnected in each WI03 module to enable a gate only wlhen a pre-established select
code occurs in the lOT instruction. When enabled by the correct select code, the WI03 module reproduces any lOP pulses as complementary lOT command pulses. Positive lOT pulses are buffered by a circuit of aW640 module before being transmitted over long cables to peripheral devices. These pulses are
used in I/O devices for ,functions such as clearing flags, gating data, setting operation modes, etc. The
last digit of any lOT pulse designation corresponds to the number of the lOP pulse which causes generation
of that lOT pulse (e.g., combination of a device code XX with an IOP4 pulse produces an lOT XX04
pulse). lOT select code assignments are given in Table 4.
Pu Ise outputs of the WI03 Device Selector modu Ie are 100-nsec or 400-nsec co,lIector outputs and can
drive any standard R-series FLIP CHIP module located in the proximity of the I/O package. However,
most options are located at some distance and require signal transmission over relatively long cables.
The W640 Pulse Amplifier modules are capable of driving cables and are wired into appropriate locations
to transmit lOT pulses to external devices. The W640 produces 400-nsec pulses (or 1-jJsec pulses when
appropriate terminals are connected together).

Information Collector
The IC reads data or status information into the AC from various devices. SeveniC channels or levels are
available in the basic machines. Each of thesE~ channels is wired to a signal cClble connector corresponding to an upper half (bits 0-8) and a lower half (bits 9-17) of the AC for optional equipment, or is wired
directly to controls for the standard PDP-7 I/O equipment. On the basic machine, the paper-tape reader
occupies one complete channel, the Teletype occupies the lower half of a channel, and the status register
occupies (nominally) one channel. If no card reader, card punch, or line printer is connected to the
system, the lower half of the status register channel may be used for other purp1oses. Thus, in the basic
machine, the equivalent of five free channels is available for additional IC inputs. Channel availability
of the IC is specified as follows:

TABLE 4
00 1 RT Clock
10 Symbol
2 Prog. Interrupt
Generator
4 RT Clock
Type 33

lOT CODE ASSIGNMENTS

20 Memory
Increment
Type 197

60 Serial
Drum
Type 24

70 Auto Magnetic
Tape Control
Type 57A

01 Standard
Perforated
Tape Reader
and Control

11 Analog-toDigital or
Digital-toAnalog
Converters

21 Relay Buffer
Type 140

61 Serial
Drum
Type 24

71 Tape Control
Type 57A

02 Standard
Perforated
Tape Punch

12 A-D-A

22 Inter-Processor
Buffer
Type 195

62 Serial
Drum
Type 24

72 Tape Control
Type 57A

03 1 Keyboard
2 Keyboard
4 laRS

13 A-D-A
Stimulus
Flag

23 Inter-Processor
Buffer
Type 195

33 1 33 KSR Skip
2 Clear All
Flags
4 Open

73 Tape Control
Type 57A

04 Teleprinter

24 Incremental
Plotter
Control
Type 350

74 Tape Control
Type 57A

05 Displays
Types 34F,
300, or 340

25 Plotter

55 Automatic
Priority
Interrupt
Type 172

65 Automatic
Line Printer
Type 647

75 DECtape
Control
Type 550

06 Displays

26 Plotter

56 API
Type 172

66 Automatic
Line Printer
Type 647

76DECtape
Control
Type 550

07 Display
and
light Pen

17 Boundary
Register
Type KA70A

27 Memory
Parity
Type 176

67 Card Reader
Type CR 01 B
or Type CR 02A

77 Memory
Extension
Type 148B

Use

Level

All 18 connections employed for RB of the tape reader.

First 9 connections employed for status signals of 10RS
instruction (lOT 0314), and last 6 connections are assigned to the step counter (SC) of the Type: 177 EAE
option, when present.

3-5

All 18 connections open and assignable.

First 10 connections are open and last 8 connections
are assigned to Teletype unit.

First 12 connections open and assignable.

Each level or channel of the IC consists of one 2-input negative AND gate for each of the 18 possible
bits of an input word. The two inputs are usually supplied by a data signal and an lOT pulse which is
common to each bit of the input word. Outputs from the seven channels for eClch bit are NOR combined
to set the appropriate accumulator flip-flop. One bit for each of the seven channels is provided by a
Type R141 Diode Gate module; the entire IC is constructed of 18 of these modules.
When designing a PDP-7 system, it is necessary to consider the number of IC channels required by peripheral equipment. If more than seven channels are required, the IC must be expanded to accommodate
the additional information. Expansion requires a Type 175 Information Collect-or Expander consisting of
18 Type R141 Diode Gate modules, 6 Type W640 Pulse Amplifier modules, and the appropriate mounting
panel and hardware. The Type 175 option connects into the standard IC throus,h two signal cable connectors reserved for this purpose, and adds seven additional information channEds. Figure 28 represents the
channel assignments for the standard IC.

Information Distributor
Data in the AC is available at the ID of the computer interface as static levels. lOT pulses from the DS
can strobe these static levels into an I/O device register. The static level of E~ach ACB output signal is
- 3v when the bit is a binary 0 or is at ground potential when the bit is a binary 1 •
The binary 1 output of each AC flip-flop is power amplified by a Type R650 Bus Driver module in the
processor and is applied to the ID for distribution to output devices. These modules have terminals Hand
S connected to ground so that the output signals have a rise time of approximatlsly 800 nsec. (Without
these terminals grounded the rise time is about 50 nsec.) Each R650 output del'livers about 20 ma to ground
The ID provides a series of nine output channels for connection to external deviices for the buffered AC
signals in locations 13-21 of rows Hand J of the I/O package. The prewired connections of the ID to the
interface cable receptacles are listed in Table 3.
76

CHANNEL I
,-

CHANNEL 2

CHANNEL 3
A

JI\

H03

H04
~

CHANNEL 4
A
H05

H06:
I

CHANNEL 6

CHANNEL 5
\(

H07

Hoe:

HOg

I
I
I
I

'J
'J

OR
STANDARD
TAPE
READER

STATUS
EXTENDED

I ARITHMETIC
I ELEMENT

,
I
I
I

177
STEP
COUNTER
SC12-17

HIO

TAPE
I CONTROL

57A
STATUS
OR

DEC TAPE
CONTROL
550
DATA INPUT
DTIO-17

PRECISION
INCREMENTAL
DISPLAY
3.40
DISPLAY
ADDRESS
COUNTER

STANDARD
TELETYPE
KEYBOARD
BUFFER

DECTAPE
CONTROL
550
STATUS

PRECISION
PRECISION
INCREMENTAL 'INCREMENTAL
DISPLAY I DISPLAY
340
I
340
X REGISTER I Y REGISTER
I

ANALOG-TODIGITAL
CONVERTER
139

ANALOG-TO-'ANALOG-TOI DIGITAL
DIGITAL
CONVERTER I CONVERTER
138
138
I
ADBO-8
ADB9-17
I

* DATA LINES PREWIRED; NO CABLE CONNECTORS NEEDED
Figure 28

I MAGNETIC

MAGNETIC
TAPE
CONTROL
57A
STATUS

J
I

HII

OR
EXTENDED
ARITHMETIC
ELEMENT
177
MULTIPLIER
QUOTIENT
REGISTER

A'--_ _ _---.,

MAGNETIC
TAPE
CONTROL
57A
CURRENT
ADDRESS

ADDITIONAL
STATUS

CHANNEL 7

Information Collector Channel Assignments

I
I

Power Clear Output Signals
The PWR CLR POS and PWR CLR NEG pulses generate in the I/O package during the first 5-sec interval
following setting of the POWER switch to the on position. These pulses initialize and clear processor
registers and controls during the power turnon period, and are available to perform similar functions in
external equipment. The PWR CLR POS signal is a 375-kc, 10CHlsec positive pulse generated in the
Type R401 Clock module at location C15. The PWR CLR NEG signal is a 400·-nsec negative. pulse produced in a pulse amplifier of the Type W640 module at location C13 that is triiggered by the PWR CLR POS
pu Ises.

Begin Buffered Output Signal
The BGN (B) signal is supplied to external equipment through a connection in the I/O package interface.
This signal is a 400-nsec, - 3v pulse generated by a W640 Pulse Amplifier at location C13 of the I/O
package during timing pulse SP1-CONTINUE NOT. In I/O equipment, the siignal clears registers and
resets control fl ip-flops to initial conditions when the START key on the PDP-7 operator console is operated.

Run Output Signal
The 1 output of the RUN flip-flop is supplied to external equipment through the interface circuits. This
RUN (1) signal is at - 3v when the computer is performing instructions and is at ground potential when
the program is halted. Magnetic tape and DECtape equipment use this signal to stop transport motion
when the PDP-7 halts, preventing the tape from running off the end of the reel.

Slow Cycle Request Input Signal
The device selector supplies the SLOW CYCLE REQUEST ground level signal tel request that all lOT instructions which address a specific device be executed in a computer slow cycle. This signal is added
at the time a slow I/O device is added to the computer system. lOT instructiolns for the device are decoded in a Type W103 Device Selector module. The ground level output at terminal BD when the device
is se lected requests the slow cyc Ie by connection to the input of a Type B171 Diode Gate modu Ie. Thi s
latter module is used as a ground level NOR gate for all such request signals, cmd a negative output on
terminal D of this module is applied to the processor timing circuits. The Type B171 module which receives the SLOW CYCLE REQUEST signals from various devices is located at E14 of the I/O package.

Program Interrupt Request Input Signal
The flag of an external device can request a program interrupt. When the device requires servicing, the
condition of the flag, connected to the Type B124 Inverter module in location D27 of the I/O package,

can request a program break. (The flag of the external device shou Id also be connected to the I/O skip
facility so that the interrupt program can sense the lOT 01 pulse to determine the device requesting the
program break.) The PROGRAM INTERRUPT signal level is the NOR of requests from up to nine devices
that require programmed attention. The program interrupt faci Iity can be expanded to accommodate requests from nine additional devices by inserting another Type B124 module in location 028 of the I/O
package. When the program break is entered, a subroutine is initiated to determine which device, of
many, is to be serviced,and then to perform the appropriate service operation (usually by supplying or
receiving data under program control).

Data Break Request Input Signal
A high-speed I/O device may originate a data break req,uest by placing a - 3v DATA RQ level on the
request line connecting' the device to 'the computer. In the interrupt control, the DATA RQ level is
synchronized with delayed timing pu'lse T5 (T5-DLY) of the current computer cy~le, and sets the DATA
SYNC flip-flop to 1. This causes a BK RQ level to be transmitted to the major state generator. Completion of the current instruction permits the major state generator to enter a break state, producing a (B)
level. This (B) level corribin'es with the DATA SYNC level to produce a negative DATA~B level.
An external device connected to the data break facility of the computer supplies a DATA RQ level, a
15-bit core memory address for the transfer, a signal indicating the direction of the transfer as into or
out of the computer core memory, and input or output connections to the MB for 18 data bits. The DATA
RQ level is sent to the computer at the time the data is ready fora' transfer into the PDP-7 or when the
data register in the external device is ready to receiv~ information from the PDP-7.

This request level

must be - 3v for assertion, meaning a request for a data break, and drives a transistor base requiring 2 ma
of input current.

Transfer Direction Input Signal
This signal, specifying the direction of data transfer for a data break, is received by the computer from
the requesting device. Transfer direction is referenced to the computer core memory, not to the device.
This signal is a - 3v level when the transfer direction is in, or is ground for an out transfer. A 3-input
NAND diode gate for negative levels receives this signal at terminal N18F. The gate also receives the
internally generated DATA·B level and T3 pulse to cause generation of the DATA ACC pulse which strobes
the DI lines into the MB.

Data Address Input Signa I
During an ADDR ACC pulse of a break cycle, the data address given by an I/o device is transferred to
the MA by connections made at the DA level input of a NOR gate in each module of the MA.

Address Accepted Output Signal
At time T1 of the break cycle, the DATAeB level NAND combines with timinH pulse T1 to produce an
ADDR ACC pulse (called DATA ADDR ---.. MA pulse in early systems). This pulse transfers the memory
address in the address register of the I/O device into the processor MA. This pulse also acknowledges to
the external device that its address has been accepted.

Data Information Input Signals
The 18 DI lines establish the data to be transferred into the MB from an extern~:ll device during a data
break in which the direction of transfer is into the POP-7. The 01 signal levells; presented to 2-input
negative NAND diode gates at the binary 1 input of the MB, are transferred into the MB by the DATA
ACC pulse. This information in the MB is then written into core memory during a normal write operation.
The 01 signals are - 3v to designate a binary 1 or ground potential to specify C~ binary 0, and should be
avai lable at the time the break request is made •

. Data Accepted Output Signal
During time T3 of a data break cycle, when the external device requests a transfer into the POP-7, the
DATAeB level causes a negative DATA ACC pulse (called DATA INFO --+ MB in early systems) to be
generated. This pulse strobes the data input gates of the MB to transfer a data word from an external device into the MB. This pulse is also an output for device synchronization. Sturting at time T5, information in the MB is written into core memory by the normal write operation.
Data Ready Output Signal
During T3 of a data break cycle in which the transfer direction is out, the DATA·B level causes a negative DATA RDY (in early systems called MB INFO ---+- OUT) pulse to be generated. This pulse may strobe
MBB information into the external device buffer; for this purpose the signal may be delayed within the device to strobe the data into the buffer after an appropriate setup time. Note that the transfer must occur
prior to T2 of the next computer cycle.

Data Information Output Signals
Data break transfer from core memory to an I/O device is made through the MB, whose output is buffered
for this purpose by 18 Type B684 Bus Drivers. Each bus driver is capable of driving a 4O-ma load. The
MBB output terminals are in the I/O package.

CHAPTER 6
INSTALLATION

PLANNING

PHYSICAL CONFIGURATION
The basic PDP-7 is housed in a three-bay cabinet and consists essentially of mounting panels of FLIP CHIP
modu les. Figure 29 shows the physical location of the memory , processor, I/O package, operator console, tape reader, and tape punch within the basic system. Space is available for optional equipment
below the table in the center bay and above the I/O package in the right bay. For example, a threebay PDP-7 with 8192 words of core memory could also include an Automatic Priority Interrupt Type 172B
and have space foranalog-to-digital or CRT display options. Larger systems are constructed by adding
standard computer bays to either or both sides of the basic machine and/or in free-standing cabinets.
Memory options above 8K mount in bays to the left of the processor and additional I/O options mount to
the right of the I/O package. The location of many options is fixed for technical reasons. For example
the Extended Arithmetic Element Type 177B mounts above the Power Receptacle Type 828 in the center
bay of the basic machine. Preferred locations for most options are shown in Figure 30.
Each standard DEC cabinet bay can accommodate twelve module mounting panels. However, the top and
bottom locations are reserved for indicator panels, fans, e.tc., and should not be used to mount logic circuits. Standard cabinet bays are joined by removing end panels and bolting the frames together. Overall dimensions are then reduced by the width of the removed end panel (1-1/4 inches per side); weight is
reduced 45 pounds per end panel. Access to all logic wiring is from the console side of the computer.
All cabinet bays are mounted on four heavy-duty casters. The floor plan for the basic PDP-7 shown in
Figure 31 can be used for installation planning.
Table 5 summarizes physical and electrical data for the basic PDP-7 and for most optional equipment.
The number of cabinet bays required for a particular installation can be determined from this table.

ENVIRONMENTAL REQUIREMENTS
The PDP-7 processor and input/output devices operate satisfactorily under ordinary conditions of humidity,
shock, and vibration in a 50° to 122°F temperature range. However, a 70° to 85°F temperature range and
a 30 to 80% humidity range are recommended. Consult the system heat characteristics listed in Table 5 if
room air-conditioning is planned.

BAY 3

BAY 2

BAY 1
5-1/4 INCH
MOUNTING PANEL

INDICATOR
PANEL

TAPE
PUNCH

149

MEMORY

MARGINAL CHECK
PANEL

F
H

BLANK

FANS
A-

BLANK

"In

TAPE
READER

.. .....

CONSOL

I ~

lb!
:::::~~if¥ :::::

lr-\JI

KA77A
PROCESSOR

H
J

OOQ)

TABLE

KA71A

I/O PACKAGE

BLiNK
L

N
FANS

828
POWER RECEPTACLE

J
FANS

FRONT

BAY 3

BAY 2

BAY 1

TYPICAL
4 INCHES

738
POWER SUPPLY

---r
BLANK

BLANK
BLANK
728
POWER SUPPLY

SPACE
AVAILABLE
ON
REAR DOORS

REAR SPACE REQUIREMENTS
EQUIPMENT
TYPE

VERTICLE
SPACE REQ'D

728A POWER SUPPLY
734A,B,C POWER SUPPLY
743A POWER SUPPLY
772 A POWER SUPPLY
778 A POWER SUPPLY
779A POWER SUPPLY
832 POWER CONTROL

8 INCHES
8 INCHES
12 INCHES
8 INCHES
12 INCHES
12 INCHES
8 INCHES

728
POwER SUPPLY

728
POWER SUPPLY

779
POWER SUPPLY

728
POWER SUPPLY

UNAVAILABLE
(TABLE)
832C
POWER CONTROL
--15 DELAYED,
REAL TIME
TRANSFORMER

739
POWER SUPPLY
728
POWER SUPPLY

BLANK

REAR

Figure 29

728
POWER SUPPLY

Basic PDP-7 Component Locations

739
FlELAY PANEL

BAY 0

BAY I

BAY 2

BAY 3
INDICATOR
PANEL

TAPE PUNCH
149

149

MEMORY

MARGINAL CHECK
PANEL

I
0

34 DISPLAY
OSCILLOSCOPE
FANS

FANS

176 MEMORY
PARITY CHECK

rll
~1

In
It'--J

I ~
TAPl
READER

.......

BLANK
KA77A

BAY 5

f
TU55
DECTAPE
TRANSPORT

138},39 '
ALD CONVERTER
MULTILEXER

TRAlpORT

AA03B
MULTIPLEXER
EXPANSION

BLINK

TUt
DECTAPE
522
MAGNETIC TAPE
INTERFACE
520/521
MAGNETIC TAPE
INTERFACE

(FOR [U551
172 AJOMATI'C
PRIORITY INTERRUPT

gPiRATgR
CONSOLE

BLANK

BAY 4

BLANK
57A
MAGNETIC
TAPE CONTROL

oo~

TABLE

PROCESSOR
BLANK

BLANK

IJ3
DATA INTERRUPT

177 EJENDED
ARITHMETIC

MULTlrEXER

ELEIENT

KA71A
I/O PACKAGE'

550
DECTAPE
CONTROL

KB03 DEVICE
SELECTOR
EXPANSION
175
I. C. EXPANSION

FANS

828
POWER RECEPTACLE

FANS

BLANK

BAY 2

BAYI

BAY 0

FRONT

BAY 5

BAY 4

BAY 3

738
POWER SUPPLY

72B
POWER SUPPLY
728
POWER SUPPLY

728
POWER SUPPLY
728
POWER SUPPLY

726
POWER SUPPLY

779
POWER SUPPLY
n6
POWER SUPPLY

726
POWER SUPPLY

UNAVAILABLE
(TABLE)

726
POWER SUPPLY

832C
POWER CONTROL

728
POWER SUPPLY

739
POWER SUPPLY

739
RELAY PANEL

-15 DELAYED, REAL
TIME TRANSFORMER

REAR
NOTE:
IF 522 INTERFACE IS USED, TWO
MOUNTING PANELS ARE REQUIRED

Figure 30

Typical PDP-7 System Component Locations

72B
POWER SUPPLY

POWER REQUIREMENTS
The PDP-7 requires a source of 115v, 60-cps, single-phase power. On specic]l request, all equipment
can be factory wired for 50-cps and/or 220 to 250v power. The power source must maintain the nominal
voltage within ±100/0 under normal and transient load conditions. The electrical characteristics of individual units are given in Table 5.

C.ABLE ACCESS
(TYPICAL FOR 3 C,o,BINETS)
REMOVEABLE
END PANEL.

CASTER SWlVAL RADIUS

SWINGlfllG PLENUM
DOORS 1:3)

---.r---..----.~---..
t_--4'''-_r---I-----+-------614" - - - - - - - \ - - - - - - - - . - j

SWINGING DOORS (to)

LOAD POINT

REMOVEABLE
END PANEL

,,~
8

---,

L ____ J

SCREEN (TYPICAL
FOR 3 CABINETS)

27ik"

-1--+-1-+
29"

4 32

8 3"
4

7 II
343"2

~--~-----+-----

14--------------------- 68ffi15" -------------------------~
FLOOR PLAN

Figure 31

Basic PDP-7 InstQllation Dimensions

CABLING REQUIREMENTS
All system power sources shou Id have 115v, 30-amp, Hubbel Twistlock flush receptac les (or their equivalent) to mate with equipment power cables.

TABLE 5

INSTALLATION DATA *
Service Clearance
Required (inches)

Dimensions (inches)

Standard PDP-7
Core Memory Modu Ie 147

Height

Width

Depth (incl.
tables)

69-1/8

61-3/4

61-1/4

---

Panels

Current (Amps)
Heat Dissipation Power Dissipation
(KW)
(BTU/hr)

Cabinets

Weight (Ibs.)

Front

Rear

Nominal

Surge

1150

8-3/4

14-7/8

7150

2.1

---

----

Data Interrupt MJltiplexer 173

----

-----

Extended Arithmetic Element 1778

Dual DECtape Transport 555

17-1/2

---

DECtape Control 550

69-1/8

22-1/4

27-1/16

Automatic Magnetic Tape Control 57 A

Magnetic Tape Transport 570

32-1/8

32-3/8

Magnetic Tape Transport 545

69-1/8

22-1/4

27-1/16

Serial Drum 24

69-1/8

22-1/4

CRT Display 340

0.5

7.5

204

0.06

---

5.5

7.5

2040

0.6

1.5

2.75

612

0.18

---

408

0.12

408

0.12

2-1/4

1.5

3.2

585

0.172

255

8-3/4

14-7/8

1.5

3.2

585

0.172

600

18-5/16

14-7/8

2114

0.62

281

8-3/4

14-7/8

1564

0.460

850

14-7/8

9800

2.9

400

18-5/8

14-7/8

2114

0.62

27-1/16

1540

0.45

408

0.12

69-1/8

Slave Di splay 343

69-1/8

22-1/4

18-Bit Relay Buffer 140

Data Communication System 630 (8 line)

---

----

Automatic Line Printer and Control 647

52-57

30-1/4

Card Reader and Control CROl B (100 cpm)

8-1/4

Typical Standard Cabinet Bay (empty)

69-1/8

22-1/4

27-1/16

Memory Extension Control 148B**
Core Memory Module 149A
Priority Interrupt 172B

Magnetic Tape Transport 50

Oscilloscope Display 34F**

A-D Converter 138E; 64Channel Multiplexer
Control 139E

500

---

700

8-3/4

5900

1.73

350

8-3/4

2350

0.69

408

0.12

---

0.6

0.77

612

0.18

---

4080

1.2

1350

5304

1.56

6-5/8

0.57

204

0.06

100

8-3/4

14-7/8

•

REMARKS
Standard POP-7

Core Memory Module 147 (continued)

Dual DECtape Transport 555

Magneti c Tape Transport 570

Card Reader & Control CR01 B

Third bay has space for fhie panels of options.

20-32K memory requires five-bay configuration.

Provision is made for installation of this unit
in bay two of standard PDP-7.

Nonstandard cabinet.

Table top model.

Oscilloscope Display 34F

Requires one panel of additional
cabinet space.

Draws no extra power.
Core ,AAemory Module 147
Fits in first bay of basic PDP-7.
12-16K memory requires minimum four-bay
configuration.

Extended Arithmetic Element 1778
Fits in second bay of standard PDP-7.

Table model dimensions are given. Also can
be mounted in two mounting panel positions.

Space for control logic is provided in
basi c I/o package.

DECtape Control 550

Oscilloscope RMS03 requires additional
panel or may be mounted externally.

Mounted in standard bay.
*This information is invalid for PDP-7 I s with serial numbers below 100.
** Mounted within basic computer

CRT Display 340
Requires one panel in bay three for
cable connection to the external
cabinet.
87

Nineteen-wire ribbon cables with Type W021 Cable Connectors provide signal connection between the
computer and optional equipment in the basic computer cabinets or in cabinets bolted to the basic computer bays. These cables are connected by plugging the W021 Connectors into standard FLIP CHIP module
receptac les •
Fifty-wire shielded signal cables with Amphenol 115-114P male connectors at both ends interconnect
the processor and peripheral equipment in separate free-standing cabinets. Any special equipment using
these cables must have Amphenol 115-1145 female connectors and 1391 shells to accept signal cables.
Unless otherwise specified, power cables are supplied in 25 ft lengths, permanently wired at one end to
individual units. Signal cables come unattached in 25 ft lengths. Power and 50-pin signal cables measure 11/16 and 13/16 inch in diameter, respectively.
All free-standing cabinets require independent 115v receptacles. However, these units may be turned on
or off or controlled from the PDP-7 console.
Cabl es are connected to cabi nets through a drop pane lin the bottom of cabi nets. Subfloori ng is not
necessary because cabinets are elevated from the floor by casters to afford sufficient cable clearance.

APPENDIX 1
I·.

PDP-7 DEVICE S~LECTOR AND INFORMATION
COLLECTOR REQUIREMENTS FOR STANDARD OPTION,S
•

The standard d~vice selector on a PDP-7 with a tape reader, tape punch, and Tel~fype contains 12 spare
selector channe'ls. Each selector channel in a PDP-7 with a serial number o~er

roo requires a' W1 03'

Device Selector module and a W640 Pulse Ampl ifier module (three circuits producing 40'O-nsec or 1":'!-'sec
pu Ises).
The standard information collector on a PDP-7 with a tape reader, tape punch; and' Teletype contains
5 spare inpuf.ch'annels. One Type 175 Information Collector Expansion 'option extends the st6ndard IC
by seven additional channels, making a total of 12 avai lable channels. The 1"75 requires one channel of
the standard. Ie;, the total number of availabl:e channels is 11 •
The following list specifies the number of DS and IC channels required for standard DEC options for the,
PDP-7. By using the following list, the need for DS or IC expansion ca~easily bedetermined~,for a;ny
system configuration containing standard DEC options. If required,these expansion ~I~~ents shou!~ be:
included in purchase orders and construction requisitions. In cases where only half a channel is required,
the remaining half is available for other options. Half channels are designated as 0.5L for the left half
(bits 0 through 8) or 0.5R for the right hal f (bits 9 through 17).

Option
Second Console Teletype and Control 649B
Memory Extension Control 148B
Memory Pari ty 176
Memory Increment 197
Memory Boundary Register KA70A
Automatic Priority Interrupt 172B
Data Interrupt Mu Itiplexer 173
Extended Arithmetic Element 177B
DECtape Control 550
Automatic Magnetic Tape Control 57 A
Serial Drum 24
Incremental Plotter and Control 350

OS Channels

Option

IC Channels

asci lIoscope Display 34F

Precision CRT Display 300

Symbol Generator 33 (for 300)

Precision Incremental Display 340

Subroutine Option 347 (for 340)

Character Generator 342 (for 340)

Slave Display 343 (for 340)

Photomultiplier Light Pen 370

Relay Buffer 140

Analog-to-DigitaIConverter 138E

General Purpose Multiplexer 139E

O.5R

Digital-to-Analog Converter MOl A

Data Communications System 630

O.5R

Automatic Line Printer 647

Card Reader and Control CROT B
Card Reader and Control· CR02A
Interprocessor Buffer 195

ma·aD D
EQUIPMENT
CORPORATION

MAYNARD,MASSACHUSETTS

5119

Printed in U.S.A.

15 -3/66