PDP-7 Interface and

This manual provides comprehensive information for designing and implementing electrical interfaces to connect peripheral devices to the PDP-7 computer, as well as guidelines for system installation. It is specifically applicable to PDP-7 systems with serial numbers above 100.

The PDP-7 is an 18-bit, parallel processing binary computer with a 1.75 µsec core memory cycle time. It supports a wide range of I/O devices through two primary data transfer mechanisms:

1. Programmed Data Transfers: These transfers are controlled by the computer's program, using the Accumulator (AC) as an intermediary. Key components involved include the Device Selector (DS) for generating command pulses, the Information Collector (IC) for inputting data to the AC, and the Information Distributor (ID) for outputting data from the AC. Features like Input/Output Skip (IOS) allow program branching based on device status, and Program Interrupt (PI) enables devices to request service from the computer. These transfers can operate in normal (1.75 µsec) or slow (adjustable, min 3.36 µsec) cycles.
2. Data Break Transfers: Designed for high-speed I/O devices, this channel allows external devices direct, cycle-stealing access to core memory, bypassing program control. It achieves transfer rates of over 10 million bits per second, primarily for block data transfers (e.g., magnetic tapes, drums). Devices request data breaks, provide memory addresses, and specify transfer direction.

The document also details the digital logic circuits (inverters, bus drivers, pulse amplifiers, diode gates) that form the PDP-7's interface, providing their functional characteristics. Interface connections are thoroughly described, including signal identification, loading/driving considerations, and prewired interface connections for various options. Finally, it covers installation planning, including physical configuration of the 3-bay cabinet (expandable for options), environmental requirements (temperature, humidity), power requirements (115v, 60-cps), and cabling specifications. An appendix lists Device Selector and Information Collector channel requirements for standard DEC options.