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DEC-15-HQFA-D

June 1971

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Document:	FP15maintVol1
Order Number:	DEC-15-HQFA-D
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DEC-15-HQFA-D

PDP-15 SYSTEMS
FP15
FLOATING POINT PROCESSOR
MAINTENANCE MANUAL
VOLUME 1

DIGITAL EQUIPMENT CORPORATION • MAYNARD, MASSACHUSETTS

1st Edition June 1971

The material in tbis manual is for informational purposes and is subject to change without
notice.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
FLIP CHIP
DIGITAL

PDP
FOCAL
COMPUTER LAB

CONTENTS
Page

Page

CHAPTER 1

INTRODUCTION

1.1

General

1-1

1.2

Floating-Point Processor Physical Description

1-1

1.3

Functional Description

1-2

1.3. 1

Operating Cycles

1-2

1.3.2

Major Register Functional Descriptions

1-3

3.7.4

Extended Integer

3-12

3.7.5

Sing Ie -Preci s ion Integer

3-12

3.B

Interrupt Cycle Interface

3-14

3.B.1

INT 1 Cycle

3-14

3.B.2

INT 2 Cycle

3-14

3.9

Interrupt Cycle

3-15

3.10

FP1S/CPU Control

3-17

CHAPTER 4

INSTRUCTION SET

CHAPTER 2

MODULE DESCRIPTIONS

2.1

General

2-1

4.1

Introduction

4-1

2.1.1

M23B Synchronous Up/Down Counter

2-1

4.2

Converting Negative Integers To Sign and Magnitude Format

4-1

2.1.2

M159 Arithmetic Logic Unit

2-1

4.3

Normalize

4-1

2.1.3

M 191 Carry Look -Ahead Generator

2-2

4.3.1

Normal ization (Except Store, Divide, or Reverse Divide)

4-2

2.1.4

M24B Right-Shift Parallel Load Register

2-3

4.3.2

Store, Divide, or Reverse Divide

4-2

2.1.5

M1701 Data Select~r

2-3

4.4

Rounding

4-2

2.1.6

M 1713 16-T 0-1 Data Selector

2-4

4.5

Guard Bit

4-6

4.6'

Floating-Point Addition and Subtraction

4-6

4.6.1

EXP Cycle

4-6

4.6.2

FUN Cycle

4-B

CHAPTER 3

FP15/PDP-1S INTERFACE

3. 1

Introduction

3-1

4.6.3

Processing of Subtracted Quantities

4-10

3.2

FETCH Cycle Interface

3-1

4.6.3. 1

Overflow

4-10

3.3

FETCH (Indirect) Cycle Interface

3-3

4.6.4

Processing of Added Quantities

4-10

3.4

FETCH Cycle Description

3-3

4.6.4. 1

Overflow Interrupt Due to Addition or Subtraction

4-10

3.5

OPAND Cycle Interface

3-7

4.6.4.2

Overflow Interrupt Due to Rounding

4-10

3.6

OPAND Cycle Description

3-B

4.6.4.3

Underflow Interrupt Due to Normalizing

4-11

3.6.1

Double-Precision Floating-Point Format

3-B

4.7

Integer Add and Subtract

4-12

3.6.2

Single-Precision Floating-Point Format

3-B

4.7.1

EXP Cycle

4-12

3.6.3

Extended I nteger Format

3-B

4.7.2

FUN Cycle

4-12

3.6.4

Single-Precision Integer Format

3-12

4.7.3

Overflow

4-13

3.7

WRITE Cycle

3-12

4.7.4

Integer Reverse Subtract~on

4-13

3.7.1

Store JEA

3-12

4.B

Floating-Point and Integer Multiply

4-13

3.7.2

Double-Precision Floating Point

3-12

4.B.l

Calculation of Exponents

4-13

3.7.3

Single-Precision Floating Point

3-12

4.B.2

Determining Sign of Product

4-13
iii

ENGINEERING ORA WINGS

ILLUSTRA TIONS

Title

Art No.

Page

Drawing No.

1-1

Cabinet Housing FP15 Logic

15-0568

1-1

D-FD-FP 15-0-45

Fetch Cycle Flow 1

3-4

1-2

System Interconnecting Cabling

15-0575

1-2

D-FD-FP15-0-46

Fetch Cycle Flow 2

3-5

1-3

FP15 Functional Block Diagram

15-0574

1-3

D-FD-FP 15-0-47

Fetch Cycle Flow 3

3-6

2-1

M238 Synchronous Up/Down Counter

15-0573

2-1

D-FD-FP 15-0-48

Opand Cycle Flow 1

3-9

2-2

M159 Arithmetic Logic Unit

15-0571

2-2

D-FD-FP15-0-49

Opand Cycle Flow 2

3-10

2-3

M191 Carry Look-Ahead Generator

15-0576

2-2

D-FD-FP15-0-50

Opand Cycle Flow 3

3-11

2-4

36-Bit ALU, Full-Carry Look-Ahead in Three
Levels

15-0577

2-2

D-FD-FP15-0-51

Write Cycle Flow

3-13

D-FD-FP15-0-62

Interrupt Flow

3-16

2-5

M248 Right-Shift Parallel Load Register

15-0572

2-3

D-FD-FP 15-0-58

NOR TS 1 Cycle Flow

4-3

2-6

M1701 Data Selector

15-0569

2-4

D-FD-FP 15-0-59

NOR TS2 Cycle Flow

4-4

2-7

M1713 16-To-1 Data Selector

15-0570

2-5

D-FD-FP 15-0-57

Float & Integer Div Fun Cycle

4-5

3-1

Major Signal Interface Diagram

15-0567

3-1

D-FD-FP 15-0-52

Add, Sub, Rev Sub, Exp Cycle

4-7

3-2

Memory Interface--FETCH Cycle

3-2

D-FD-FP15-0-53

Add, Sub, Rev Sub, Sub Cycle

4-9

3-3

Memory Interface--FETCH Cycle (Indirect)

3-3

D-FD-FP 15-0-54

Floating Mul & Div Exp Cycle

4-17

3-4

Memory Interface--OPAND Cycle

3-7

D-FD-FP15-0-55

Float & Integer Mul Fun Cycle

4-18

3-5

INT 1 Cycle Interface Diagram

3-14

D-FD-FP 15-0-56

Integer Divide Exp Cycle

4-23

3-6

INT 2 Cycle Interface Diagram

3-15

D-FD-FP15-0-57

Float & Integer Div Fun Cycle

4-24

3-7

CPU;rP15 Sample Program

3-17

D-FD-FP 15-0-60

ASIGN Swap & Float Control

4-27

4-1

Converting Negative Integers to Sign and
Magnitude

4-1

D-FD-FP15-0-61

Fix Flow

4-29

4-2

Guard Bit and Rounding

D-FD-FP15-0-63

Maint Flow 1

4-32

4-3

Flow Diagram for Setting Guard

15-0580

4-6

D-FD-FP15-0-64

Maint Flow 2

4-33

4-4

Multiply Simplified Flow Diagram

15-0581

4-14

4-5

Multiply Algorithm

4-6

Floating-Point Divide Simplified Flow Diagram

4-7

Floating Point Divide Algorithm

4-20

4-8

Integer Divide Algorithm

4-25

4-9

Branch Instruction Flow Diagram

15-0583

4-30

5-1

H963E Cabinet (Bay 1R), Rear View with Mounti ng Panel Door Open

15-0568

5-1

5-2

FP15 Indicator Bus Connections

15-0585

5-2

Figure No.

15-0578

4-2

4-15
15-0582

4-19

Page

TABLES
Title

Page

1-1

FP15 System Characteristi cs

1-1

1-2

FP15 System Features

1-2

1-3

Operand Transfer and Cycle Time

1-2

5-1

FP15 Floating-Point Processor Major Components

5-1

5-2

Signal Cable Connections

5-2

5-3

FP15 Floating-Point Processor Engineering Drawings

5-5

Table No.

CHAPTER 1
INTRODUCTION

1.1

Table 1-1 (Cont)
FP15 System Characteristi cs

GENERAL

This chapter provides a physical and functional description of the FP15 Floating-Point Processor. The
physical description includes lists of FP15 system parameters and special features.
Physical Characteristics
1.2

FLOATING-POINT PROCESSOR PHYSICAL DESCRIPTION

Size

19-in. wide by 21-in. high

Weight

50lb

The FP15 Floating-Point Processor consists of four racks of Medium Scale Integrated logic (MSI) and

No. of Racks

TTL logic located as shown in Figure 1-1. The interconnecting cabling associated with the FP15 is

Type of Logic

TTL and MSI

shown in Figure 1-2. The floating-point processor logic uses an operating voltage of +5 Vdc that is
supplied from an H721 Power Supply, with 115V or 220V input and +5 Vdc output fused at 20A. A
716 Power Supply provides the power for the indicator panel. The operating characteristics of the
FP15 are listed in Table 1-1; Table 1-2 includes some of the more significant features of the FP15.

Table 1-1
FP15 System Characteristics

H963E
BAY lR
BB15 INDICATOR

PANEL

FPl ~ INDICATOR

PANEL

1-----------I-- -

Operating Characteristics
BB15 OPTION

Power Requirements

115V, ±15%
12A
50 ± 1 Hz, 60 ± 1. 2 Hz
Single Phase
230V, ±15%
6A
50 ± 1 Hz, 60 ± 1. 2 Hz
Single Phase

PANEL

-FP15 LOGIC -

1-----------H721 POWER SUPPLY

DISPLAY (OPTIONAL)
734B POWER SUPPLY
PC05 READER PUNCH
BLANK
FANS
BA15

H721 POWER SUPPLY

Power Consumption

1.4 kW max

DW15 LOGIC

841-C POWER CONTROL

Temperature Range

50° - 120°F

828 POWER RECEPTACLE

BLANK

Relative Humidity

10 - 95%

FRONT

REAR

Heat Dissipation

4800 btu/hr

, 5-0568

Figure 1-1

Cabinet Housing FP15 Logic

1-1

i.3

FUNCTiONAL DESCRiPTiON

The FP15 Floating-Point Processor functional block diagram is shown in Figure 1-3. Before describing
716
P0WER
SUPPL Y

INDICATOR
PANEL

H721 POWER
SUPPLY

I--

each of the major elements in the diagram, it is necessary to introduce the various operating cycles in
the FP15; they are:

1
*BBI5 OPTION
MEMORY

--1

i t
4-If

FLOATING
POINT
PROCESSOR

FP15
~

a.
b.
c.
d.
e.
f.
g.

PDP-15
CENTRAL
PROCESSOR

i lBB CONTROL CABLd
1
MOL CABLE

MEMORY CONTROL CABLE

BB option is not ,nstalled, cables are directly routed to memory_

FETCH
OPAND
EXP
FUN
NOR
WRITE
INTERRUPT

15-0575

Figure 1-2

System Interconnecting Cabling
1.3.1

Operating Cycles

During a floating-point instruction, the FP15 is in one of the operating cycles. Each cycle is approxTable 1-2
FP15 System Features

imately 900 ns and is divided into three time states (300 ns per time state). The cycles can be extended in time due to shifting and aligning. In turn, each time state is subdivided into four phases
(75 ns per phase). The following paragraphs provide a brief description of the major events that occur

Directly or indirectly addressable up to 128K of core.

during each cycle.

Performs arithmetic operations on 18- or 36-bit integers and 36- or 54-bit floatingpoi nt numbers.

FETCH - In the FETCH cycle the instruction word (first word) is loaded into the FP15 Instruction Regis-

Allows execution of in-line code--CPU instructions and floating-point instructions
may be interspersed as desired.

I/O Processor can access memory on a shared basis with the floating-point processor; however, the I/O Processor takes pri ority over the FP15.

When an undesired condition (Underflow, Overflow, Abnormal Division, or Memory Protect Violation) occurs, the FP15 interrupts the CP stored program and automatically identifies the source of the interrupt.

Worst-case multiplication and division times on normalized operands do not exceed
24ps.

Possesses ability to convert floating-point numbers to integers and integers to
floating-point numbers.

Remainder, product, and align bits in FMQ are accessible by appropriate software.

Unnormalized and unrounded arithmetic may be specified.

A class of non-memory reference instructions is available. These instructions use
existing contents of FMA and FMB and require no memory reference.

Built-in maintenance logic (maintenance mode) allows single or multiple substeps of
an instruction. All major registers and control can be examined at the end of each
step.
Designed to operate with existing PDP-15 options (Memory Protect, Memory Relocate, etc.) with no increase in cycle time.

ter (IR) and the address of the operand is loaded into the FP15 Address Register (AR). If indirection
{indirect addressing} is requested, the FP15 remains in the FETCH cycle to obtain the effective address.
OPAND - In the OPAND cycle the operand(s} is transferred from memory to the FP15. The number of
operands transferred depends on the format in Tab Ie 1-3.

Table 1-3
Operand Transfer and Cycle Time

Format

No. of Operands

Cycle Time

Single-precision integer

One operand

(1) 1.2 ps

Double-precision integer and
Single-precision floating-point

Two operands

(2) 2.4ps

Double-precision floating-point

Three operands

(3) 3.6 ps

If non-memory reference instructions are specified, the OPAN D cycle is bypassed and no operands are
transferred from memory to the FP15.

1-2

~I__~M~E~M~O~~~B~U~S_ _ _ _ _ _ _ _~_ _ _ _ _ _ _ _ _ _ _~I

OORE
MEMORY

FUN - In the FUN cycle, the actual arithmetic or logical operatio.. is performed. The cycle time iePDP-iS
CPU

I " ........... ~ ................................................ ~ ~ .. ~ ........... -~-- --~~ - - - - - - - - - ,

quireci is the basic 900 ns, pius the additionai time required for shift, muitipiy, and divide operations.
NOR - In the NOR (normalize) cycle, the FMA is normalized by shifting. Rounding may also be requested. The basic NOR cycle requires 900 ns, plus an additional 150 ns for each shift necessary to

FP15 FLOATING
POI NT PROCESSOR

7-BIT
DIR

J-

l5-BIT
DAR

I-

normalize.
1S-BIT
JEA
REGISTER
(JMSEXIT
ADDRESS)

WRITE - During the WRITE cycle, the operands are transferred to memory. The operands transferred
from the FP15 to memory are:

r--,

12-BIT

I NRS;~I~~~I~N Ie-

FP15
CONTROL

I
I
L __ J

(IR)

36-BIT
BUFFERED
MEMORY BUFFER

Single-precision integer--one 2 1s complement operand
TO ALL MAJOR
REGISTERS

Double-precision integer--two 2 1s complement operands
Single-precision floating-point--2 I s complement exponent and high-order mantissa

(BMBl
l7-BIT
ADDRESS
REGISTER
(AR)

CONTROL A SIGN

36~ BIT
ARITHMETIC
LOGICAL
UNIT
(ALU)

Double-precision floating-point--2 I s complement exponent and high-order and
low-order mantissas.

SIGN CONTROL

Each transfer requi res about 1.2 J-lS.

1.3.2
la-BIT

1a-BIT
EPB

EPA

Major Register Functional Descriptions

Buffered Memory Buffer Register (BMB) - The 36-bit Memory Buffer Register is loaded from the memory

bus 18 bits at a time. The output of this register is connected to the ALU, the instruction register,
ALU
BUS

'---

3S-BIT
FMA

and the address register. All inputs from the memory pass through the memory buffer.
35-BIT
FMB

Instruction Register (IR) - The 12-bit Instruction Register stores bits 6 through 17 of the instruction
word retrieved from memory during the FETCH cycle. Bits 6 through 17 remain in the IR until another

1
'----

instruction is fetched from memory.
lS-BIT
SHIFT
REGISTER

3S-BIT
FMQ

L ________________

Address Register (AR) - The 17-bit Address Register stores the effective address used in fetching or

(SCl

storing operands.
Arithmetic Logic Unit (ALU) - The 36-bit ALU performs both arithmetic and logic operations in the

Figure 1-3

FP15 Functional Block Diagram

EXP ~. In the EXP cycle, during floating-point addition and subtraction, the mantissa with the smaller
exponent is aligned with the mantissa having the larger exponent. Alignment occurs by right-shifting
the smaller mantissa.

FP15. The output of the ALU is connected to all major registers via the ALU bus. Most major registers are available as inputs to the ALU.
EPA - The 18-bit EPA is a synchronous up-down counter used to store the 2 1s complement exponent
associated with the mantissa loaded in the FMA. The most significant bit of the EPA represents the

In the EXP cycle, during floating-point multiplication and division, the exponent is calculated. In

sign of the exponent.

integer format, negative integers in 2 1s complement format are converted to sign and magnitude num-

ponent is bit 9. The value of this bit is extended from bit 9 through bit O. The EPA is loaded from

bers during the EX P cycle.

the ALU bus and keeps track of the exponent associated with the mantissa in the FMA.

For single-precision floating-point format, the most significant bit of the ex-

1-3

FMA - The 35-bit FMA stores an integer operand during integer arithmetic or a mantissa during

B SIGN - The 1-bit B SIGN register stores the sign of the operand loaded into the FMB. A 1 in this

floating-point arithmetic. The FMA is loaded from the ALU and can be shifted left or right. The

FMA can also be loaded and shifted simultaneously from the ALU bus during multiplication and division. The EPA and A SIGN/FMA are the floating-point accumulator.

Shift Counter - The shift counter performs the following functions:
a.

Keeps track of the number of words to be fetched from memory during the OPAND
cycle.

Keeps track of the number of words written into memory during the WRITE cycle.

FMQ - The FMQ is a 36-bit extension of the FMA or FMB and is used primarily during arithmetic op-

Keeps track of the number of shifts required for multiply and divide operations.

erations. Bits shifted out of the FMA or FMB, during alignment for addition and subtraction, are

Limits the number of shifts during normalizing to a maximum of 35

shifted into the FMQ. The most significant bit in the FMQ is used for rounding, if requested. The

Controls the number of shifts required during al ignment.

FMQ can be loaded from the ALU bus, or directly from the FMA, and has a shift-left and shift-right

Checks for exponents having differences which exceed 35

A SIGN - The l-bit A SIGN register stores the sign of the operand loaded into the FMA. A 1 in this
register indicates a negative number; a 0 indicates a positive number.

capability.
JEA - The 15-bit JEA address register points to the interrupt handling routines in core that service the
EPB - The l8-bit EPB register is loaded from the ALU bus and stores the 2 1s complement exponent associated with the mantissa loaded in the FMB. The most significant bit of the EPB represents the sign of

floating-point interrupts (underflow, overflow, abnormal divide, and FP memory trap). This register
is loaded by software control.

the exponent. For single-precision floating-point format, the most significant bit of the exponent is
bit 9. The value of this bit is extended from bit 9 through bit O.

Diagnostic Instruction Register (DIR) - The 7-bit DIR determines the number of steps through which an
instruction is to be sequ~nced.

FMB - The 35-bit FMB register stores an integer operand during integer arithmetic or a mantissa during
floating-point arithmetic. Unlike the FMA, the FMB can only be shifted right for alignment. The

Diagnostic Address Register (DAR) - The 15-bit DAR specifies the address in core where the contents

FMB is loaded directly from the ALU bus. The EPB and B SIGN/FMB are a second operand register.

of the registers are to be stored.

1-4

CHAPTER 2
MODULE DESCRIPTIONS

2.1

The M238 Counter is used in the EPA, DIR, and DAR registers in the FP15 Floating-Point Processor.

GENERAL

This chapter provides descriptions of the following modules used in the FP15 Floating-Point Processor:

Figure 2-1 i~ an example of how the M238 Counter is used in the DIR register (see drawing
D-BS-FP15-0-14) .

M238
M159
M191
M248
M1701
M1713

2. 1 . 1

SYNCHRONOUS UP/DOWN COUNTER
ARITHMETIC LOGIC UNIT
CARRY LOOK-AHEAD GENERATOR
RIGHT -SHIFT PARALLEL LOAD REGISTER
DATA SELECTOR
16-To-l DATA SELECTOR

NOTE
The up count is inhibited by +3V in the DIR register,
indicating that this register can only be decremented.

CARRY L E1

M238 Synchronous Up/Down Counter

BORROW L Fl

M238

The M238 Synchronous Up/Down Counter consists of two DEC 74193 4-b it synchronous up/down count-

H24

ers. Synchronous operation is provided by having all flip-flops in the counter clocked simultaneously
DATA INPUTS

so that the outputs change at the same time. The flip-flops are master-slave flip-flops and the outputs

~~~; ~~
MO 16

MO 17

LOAD

LO OIR H

CLEAR

GNO

CLR

are triggered by a positive-going transition of one of two count (clock) inputs. One input is designated U (up count); the second input is designated D (down count). The direction of counting is de-

{

F2
H2
L1

DIR 14 (1) H
}
D I R 15 (1) H
OIR 16 (1)H DATA OUTPUTS

01 R 17 (1) H

termined by the count input that is pulsed while the other count input is high.
UP COUNT

~OWN COUNT

The outputs of the flip-flops may be preset to any desired state by entering the data at the data inputs

{+3V H 19 U1 J2
01 R OWN P L ...;,K=2_ _ _ _----'
15-0573

while the load input (L) is low. The output will change to reflect the input, regardless of the count
Figure 2-1

pulses.

M238 Synchronous Up/Down Counter

A clear input (CLR) forces all outputs low on receipt of a high clear input. The clear input is independent of the count and load inputs.

2.1.2

M 159 Arithmetic Logic Unit

The M159 4-bit Arithmetic Logic Unit (ALU) contains a single DEC 74181 integrated c:ircuit. Nine of
Both borrow and carry outputs are available for cascading the up-counting and down-counting opera-

these ALU modules are used in the FP15 Floating-Point Processor to perform 36-bit arithmetic and logic

tions. When counter underflow occurs, the borrow output produces the same width pulse as the down-

operations, as shown on drawings D-BS-FP15-0-19 through D-BS-FP15-0-27.

count input. When counter overflow occurs, the carry output produces the same width pulse as the
count-up input. Cascading is accomplished by connecting the borrow and carry inputs to the count-

This integrated c:ircuit performs 16, 4-bit arithmetic operations when the MODE control (MC) input is

down and count-up inputs, respectively, of the next counter.

low and 16 logic functions when the MC input is high. The functions are selected by applying

2-1

combinations of function select inputs SO through 53. For FP15 applications, the function select and
E2

MC inputs are generated by the ALU control logic shown on drawing D-BS-FP1S-0-33.

FP15-0-19
M2

Only two arithmetic operations, A plus B and A minus B minus 1, are selected in the FP1S; five logic

functions, A, -A, B, -B, and logical 0 are performed in the FP1S. The combined ALU truth table for

M159
003

51
I NPUTS FROM
M1701 DATA
SELECTORS

FP1S arithmetic operations and logic functions is listed as follows:

K1
H1

1
0
0

a
1
0
0

0
1
0

1
0

0
1
0
1

a
a

0
1

•
0
0
0
1
1
1
1

Output Function
51

'J1

ADD 00 H
Ann.

('\1

-~~ ~,

ADO 02 H

OUTPUTS

ADO 03 H
CNOS

CARRY IN

MODE

MODE CONTROL

Mode Control
52

Function Select Inputs
S3

1
0
0
0

a
1
1

A plus B (arithmetic operation)
A minus B minus 1 (arithmetic operation)
A (logic function)
-A (logic function)
B (logic function)
-B (logic function)
Logical 0 (logic function)

A=B
P

CARRY

PROPAGAT E

CARRY

GENERATE

FUNCTION
SELECT
INPUTS {

~~: _P_l_ _ _--'
51

H.....:.:....;----~

Ml
SO H - - - - - - - - - '
15-057 ,

Figure 2-2

M 159 Arithmetic Logic Unit

FP15-0-28

In addition, a comparator output, A=B, is provided when the four A inputs are equal to the four B inputs if the function A=B=l is selected. A full-carry look-ahead provides fast, simultaneous carry generation by the M 191 module.
Figure 2-2 shows the ALU configuration for bits 00 through 03 in the FP15 Floating-Point Processor.

FP24 P03 L

FP 24 G03 L

FP25 P02

P2
G2

FP 25 G02

FP 26 POI L

FP26 GOI L

FP 27 POO L

FP 27 GOO L

FP33 CNOO L Fl

FP28 PPOO L

G E2

FP28 GGOO L

FP28 CN03 H

FP28 CN02 H

P
M191
E13

CN+Z

CN+Y

PO
GO

CN+X

FP28 CNOI H

CN
15-0576

2. 1.3

M 191 Carry Look-Ahead Generator

Figure 2-3

M 191 Carry Look-Ahead Generator

The M191 Carry Look-Ahead Generator, consisting of two DEC 74182 integrated circuits, is a highspeed generator capable of anticipating a carry through a group of ALUs. A 13-ns delay occurs for
M1S9-ALU'S

each look-ahead level. The M 191, when used in conjunction with the M159 ALU, provides carry,

rN'
I-L!.

generate-carry, and propagate-carry functions for 36-bit words.
Figures 2-3 and 2-4 show how the M191 is used.

~~~--~~~~~~~~--~~

M19!

Each carry look-ahead circuit is associated with four ALUs (16 bits). Each circuit generates the anticipated carry through its respective group of ALUs, as well as providing a Generate (G) and Propa-

MI91

gate (P) input to a third carry look-ahead circuit associated with the last ALU; hence, the term fullcarry look-ahead in three levels (36 bits).
Depending on the selected function of the ALUs, the carry look-ahead circuitry determines whether a
carry will be propagated through the particular ALU, or whether the selected function will generate a

2-2

15- 0577

Figure 2-4

36-Bit ALU, Full-Carry Look-Ahead in Three Levels

carry. If a carry is produced, it is directed into the next ALU in line. This seauence is continued for

where

each of the four ALUs in the section. The carry look-ahead circuitry then "Iooks" at the G and P sig-

nals of all four ALUs and determines whether a carry should be inserted into the next four ALUs and
into the third level of carry look-ahead. This process is continued for the second section of ALUs
(next 16 bits). Finally, the third level of carry look-ahead determines whether a carry should be in-

NXX

GXX

True H

PXX

= True H

GGXX = True H

serted into the final ALU by examining the resulting G and P inputs of the other two look-ahead cir-

PPXX
cuits.
The truth table for the first-stage carry is as follows:

True L

2.1.4

= True H

M248 Right-Shift Parallel Load Register

The M248 Right-Shift Parallel Load Register consists of two 4-bit DEC 7495 Right-Shift Parallel Load

True Carry Insert = L

Registers connected to allow right-shifting between 4-bit sections. The registers perform load or rightPOO

L
L
H
L

GOO

L
L
H
H

shift operations, depending on the logical input to the MC. When a logical 0 is applied to the MC
NOO

C N +X

L
H
H
L

H
H

L
L

input, the output of each flip-flop is connected to the succeeding flip-flop and right-shift operation
is performed by clocking at the input designated RS.

During this time, the input designated LS is

inhibited. When a logical 1 is applied to the MC input, the flip-flops are decoupled (to prevent
right-shift); the register is loaded with parallel inputs when the input designated LS is clocked. The
register can be configured for left-shift operation by connecting the output of each flip-flop to the
parallel input of the previous flip-flop.

True Carry Insert = Low
The M248 Right-Shift Parallel Load Register is used in the EPB, FMA, FMB, and FMQ registers in the
POO

GOO

NOD

C N +X

FP15 Floating-Point Processor.

Each module is capable of handling 8 bits. Figure 2-5 shows a sample

of the application of this module in the FP15 Floating-Point Processor.
L
H

L
H
L

L
L
H
H

L
L

L
H

H
H

L
L
L
L

H
H

H
H
H
H

H
H
H

FP15-0-18

L
L

M248
E07

ADD 20 (H)

VI A

ADD 21 (H)
ADD 22 (H)

V2 B
U2 c

A SI
B Rl
C PI

EPB 02 (1) H}
EPB 03 (1) H
EPB 04 (1 I H
DATA OUTPUTS

ADD 23 (H)

S2 D

o NI

EPB 05 (1) H

SERIAL INPUT

EPB 01 (HI

UI SI

RIGHT SHIFT

EB RS H

P2 RS

EPB LOAD

EPB LD

N2 LS

MODE CONTROL

-EPB Me H

R2 Me

DATA INPUTS

{

The following are the logic equations for a carry look-ahead stage:

, 5-0572

CNOl = C NOO * GO + GO * Po
C N02 = Gl*~ + Po*Go *G J + Gl*GO*C

Figure 2-5

M248 Right-Shift Parallel Load Register

C N03 = P2*G 2 + G l *G 2 *P l +GO+Gl*G2*PO+GO*Gl*G2*CN

2.1.5

GGOO= P3 *G 3 + P2 *G 3 *G 2 +Pl*G3*G2*Gl+G3*G2*Gl*GO

The M1701 Data Selector contains two DEC 74153 Dual 4-Line-to-1-Line Data Selector/Multiplexer

PPOO

= P3+ P2 + ~+P 0

M1701 Data Selector

integrated circuits. These integrated circuit modules comprise input multiplexers A and B of the

2-3

36-bit ALU in the FP15 Floating-Point Processor. They are also used as input muitipiexers to the shift
counter, MPO, FMA, and FMQ registers. A complete block schematic of the input multiplexers is
shown on drawings D-BS-FP15-0-19 through D-BS-FP15-0-27.

2.1.6

tvH713 16-To-1 Data Selector

The M1713 16-To-1 Data Selector contains a single DEC 74150 integrated circuit. It is used in the
output multiplexer section of the FP15 Floating-Point Processor, where up to 16 major register outputs

For each section of each IC, one of four data inputs is selected by combinations of address input signals A and B. The selected data input is strobed to the output by a low strobe signal. Refer to the
following truth table for a typical input multiplexer A section.

are selected for transfer to the common MPO bus. The block schematic of the output multiplexer is
shown on drawing D-BS-FP15-O-03.
Data inputs are selected by combinations of data select signals MXA, MXB, MXC, and MXD, which
are generated by the multiplexer control logic shown on drawing D-BS-FP15-0-05. The strobe inputs

Data Inputs

Address Inputs

Output

Strobe
A

x
0
0
1
1
0
0
1
1

x
0
0
0
0
1
1
1
1

0
1
x
x
x
x
x

x
0
1

x
x

x
0
1
x
x

x
x
x
x

lector follows:

1
0
0
0
0
0
0
0
0

x
0
1

0
0
1
0
1
0
1
0
1

x indicates irrelevancy.

Address input signals A and B are common to both sections of each IC. Figure 2-6 is a typical application of the M1701 Data Selector in the FP15 Floating-Point Processor.

{
DATA INPUTS

ADO 0 ' "
FMQ 04 (I) H
FMA 03 (1) H

FP15-0-19

THRU

MI701
A03

MXBl

{

ADO 02 H

MXAI

DATA

INPUTS

FMO 03 (1) H
FMA 02 (1) H

0
1

01
El
Fl

OUTPUTS

3
S
, 5-0569

Figure 2-6

2-4

M1701 Data Selector

Data Select Inputs
MXD

MXC

MXB

MXA

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

* Signal mnemonics vary as shown on drawing D-BS-FP15-0-03.

COMMON {
SELECT
INPUTS

FPI5-0-27

are wired to ground so that each IC is always enabled. A typical truth table for the 16-to-1 Data Se-

Data Input*
Selected

DIR12
JEA12
ADD30
ADD12
FMQ30
FMQ12
FMB30
FMB12
EPB12
FMA30
FMA12
EPA12
IR12
BMB30
BMB12
MPI12

Figure 2-7 is a typical example of the manner in which the M1713 Data Selector is utilized.

FPI5-0-03

BUSY (1) H
A SIGN (1) H
ADD 18 H
A SIGN (1) H
FMQ 18 (1) H
BSIGN(I)H
FMB 18 (1) H
IN PUTS

B SIGN (1) H
EPB 00 (1) H
FMA 18 (I) H
A SIGN (1) H
EPA 00 (Il H
SC12 (1) H
BMB 18 (1) H
BMB 00 (1) H
MPI 00 (1) H
MXA L

SELECT LI NES {
TO SELECT ONE
OF 16 INPUTS

MXB L
MXC L
MXD L

012
M1713

T2
MI
Nl
PI
RI
SI
LI
Fl
HI
Jl

MPO 00 L OUTPUT

Kl
M2
L2
K2
E2
F2
H2
J2
N2

STROBE

15·0570

Figure 2-7

M1713 16-T0-1 Data Selector

2-5

CHAPTER 3
FP15/PDP-15 INTERFACE

3.1

3.2

INTRODUCTION

FETCH CYCLE INTERFACE

This chapter describes the interface between the CPU, FP15, and memory. This interface is described

Prior to the FETCH cycle, the floating-point instruction from memory is strobed into the FP15 BMB.

by discussing the major events that occur during the FETCH, OPAND, WRITE, and Interrupt (INT) cy-

During the FETCH cycle, the operand address is strobed into the FP15 Address Register (AR) (see Fig-

cles, followed by a flow diagram description of each cycle. The EXP, FUN, and NOR cycles, inter-

ure 3-2). If indirection is specified, a second FETCH cycle is performed to obtain the effective ad-

nal to the FP15, are described in Chapter 4. Figure 3-1 shows the various control signals associated

dress.

with the interface.
Every instruction is monitored by both the CPU and the FP15, which are in parallel on the memory bus.
Bits 00 through 05 of the instruction are examined for an octal code of 71. The 71 is recognized by
the CPU as a NOP and by the FP15 as a floating-point instruction. The CPU strobes the instruction
MEMORY

into the memory input (MI) register and then into the instruction register (IR), while the FP15 strobes
the instruction into the BMB register.
~
(.)

fo-

<I:

f0II)

II)

D::

<I:

D::

.J (.)

D::

(J)~

1&.1
D::

.JQ.

Q.
II..

IJJ
0:

0:
0

~II.. a<I: ....

Q. ~
II..

Ul(J)

D::

j:!

c...

II..

D::

The CPU executes the 71XXXXS (NOP) and makes a second memory reference to the next location, as

if it were fetching the next instruction. This memory request (M REQ) actually fetches the operand

<1:'

00
0:0

address that is the second half of the two-word FP15 instruction. The normal interface signals between

.J .J ~ .J 0
Q.o D::
~ ::!: II.. ~ ~

0: 0:

the CPU and memory take place; i.e., the CPU specifies an address, READ cycle, and issues M REQ.
After M REQ is placed on the memory bus, the contents of the 8MB in the FP15 are strobed into the IR;
FP15
FLOATING POINT
PROCESSOR

CPU

the DIS CP ACT and DIS CP RD RST signals are generated to inhibit the CPU from making further memory requests. Address Acknowledge (ADDR ACK) is returned from memory to clear M REQ in the CPU.
The memory then places the operand address on the memory data line (MDL) and issues RD RST. The

DIS CP ACT

DIS I/O ACT

operand address is strobed into the 8MB in the FP15.

DIS CP RD RST

The CPU does not see the operand address because DIS CP RD RST prevents RD RST from loading the MI
Figure 3-1

Major Signal Interface Diagram

and halts the CPU in Time State 3, Phase 3 (TS03*PH03).

3-1

SUBCYCLE

M REQ,ADDR, RD

o -M REQ~
REMOVE ADDR FROM MDL
SET FETCH
t-

~Z
00
0.. _

71XXXX S '" MI
MRLS

e>U

0- MRLS ~

Z=>
_0::::

= 0 .. ADDR ACK
INSTR ON MDL AND
RD RST ISSUED
71XXXXS ... BMB

I ·MRLS ACK

OZ
...,Ju..

71XXXXS - IR
(EXECUTED AS NOP)
M REQ

1--0 - MRLS ACK

til
til
W

o -M REQ 4

DIS CP ACT, DIS RD RST

0
0

.ADDR ACK

I
r-O
- ADDR ACK
i

I BMB - IR

0::::

MOL _ BMB~OPERANO AOOR ON
FP MRDA
MDL & RD RST

~ISSUEO

0::::

0..

0 ... FP MRDA... ·
BMB - AR

0..

::>
t-

til

~
~

::>
0

710000S ... MI .-MRLS
0 ... MRLS~

I;.-MRLS ACK

-- 0 - MRLS ACK

REMOVE DIS CP RD RST
FPU ISSUES FP RD RST
8 ON MOL

I-WITH 710000

~FP MRLS ACK

I--0 ... FP MRLS ACK
Figure 3-2 Memory Interface--FETCH Cycle

3-2

CPU REMOVES ADDR FROM MDL
MEM PLACES INSTR. ON MDL
71XXXXS RECOGNIZED AS
FLOATING POINT INSTR.
AND IS STROBED IN BMB OF
FPU AND MI OF CPU. CPU
COMPLETES REST OF MEM CYCLE.
71XXXXS STROBED INTO IR
IN CPU

I
I

REMARKS
CPU REQUESTS MEM. CYCLE
MEM. ACKNOWLEDGES ADDRESS

I·ADDR ACK

t- t-

~tIl

MEMORY

FLOATING POINT UNIT

CENTRAL PROCESSOR

M REQ IS MADE FOR LOCATION
CONT AINING OPERAND ADDR.
CPU RD RST IS DISABLED, WHICH
INHIBITS RD RST FROM RESTARTING
CPU CLOCK.
OPERAND ADDR STROBED INTO
BMB. 71XXXXS STROBED INTO
IRINFPU.
REST OF MEM CYCLE COMPLETED.
OPERAND ADDR
STROBED INTO AR
CPU BECOMES ACTIVE
FP RD RST LOOKS UKE
RD RST TO CPU. CPU
STROBES 710000S INTO MI.
THE EXECUTION OF THE 710000
INSTRUCTION WAITING FOR CPU
ACTIVE TO SET (WAITING TO ISSUE
M REQ)

The FP15 now issues MRDA (Memory Release and Data Acknowledge) which releases the memory for

3.4

FETCH CYCLE DESCRIPTION

additional requests and acknowledges receipt of the data (operanda ddress). The memory cycle is completed when the memory issues MRLS ACK, clears MRDA in the FP15 which, in tum, clears MRLS ACK
(Memory Release Acknowledge). The operand address, which was loaded into the BMB, is now strobed
into the FP15 AR. Since the CPU did not receive the operand address, it is still waiting for data from
memory. The FP15 places a 7100008 on the MDL, clears DIS RD RST, and sends RD RST to the CPU.
The CPU loads the 7100008 into the MI and generates MRLS. The FP15 generates MRLS ACK to allow
the CPU to complete its cycle.
The CPU executes the 7100008 but is prevented from making a M REO because of DIS CP ACT. The
CPU waits in TS03*PH02 until completion of the FP15 instruction. The memory interface is now free
for I/O memory requests.
3.3

The FP15 detects a floating-point instruction by monitoring MDL bits 00 through 05 for a 71XXXX
while FP SET FETCH is true (see drawings D-FD-FP15-0-45 through D-FD-FP15-0-47). FP SET FE:CH
indicates that the CPU is fetching an instruction. When the 71XXXX is detected, the contents of the
8
MDLs are strobed into the FP15 BMB bits 18 through 35 and the floating-point operation is started.
The PI and API facilities are disabled at this point, to prevent an interrupt during the floating-point
instruction.

The CPU executes the 71XXXX as a NOP and makes a memory request for the next instruction that is
8
actually the operand address associated with the floating-point instruction. The FP15 sets BUSY,
DIS CP ACT I DIS RD RST I and loads the contents of BMB bits 18 through 35, which contain the
floating-point instruction, into its IR. BUSY starts the floating-point phases and time states and

FETCH (INDIRECT) CYCLE INTERFACE

DIS RD RST prevents the CPU from seei.ng the RD RST of the memory request for the operand address.
If bit 00 of the second FP15 word (address) is a 1, specifying indirection, a second FETCH (indirect) .

cycle is performed. This word, which is in the FP15 AR, and is the address of the effective address,
is placed on the MDL (see Figure 3-3). The FP15 requests a memory cycle and the contents of the operand address (effective address) are accessed from memory, placed on the MDL, and RD RST issued.
The address is then strobed into the BMB register. The FP15 issues FP MRDA to memory, which releases memory for further requests. The effective address, which was transferred into the BMB, is now
strobed into the AR and represents the address of the first operand.

The CPU waits in TS03*PH03 for RD RST. When RD RST is retumed by memory, the FP15 strobes the
contents of the MDL into BMB bits 18 through 35 and issues MRDA to memory. The memory responds
by issuing MRLS ACK which clears MRDA. The FP15 now completes the CPU memory request by clearing DIS RD RST, enabling 710000 (NOP) onto the MDL, and issuing FP RD RST, which strobes the
8
NOP into the CPUls MI. The CPU responds with MRLS and the FP15 returns MRLS ACK. The CPU begins to execute the NOP but cannot issue a M REO because DIS CP ACT holds the CPU in TS03*PH02,
thus allowing I/O memory requests to be made.

If bit 00 of the second FP15 word (address) is a 0, no indirection is specified and this cycle is omitted.

The FP15 loads BMB bits 18 through 35 (operand address) into the AR and determines if an I/O memory
SU B- CENTRAL
CYCLE PROCESSOR FLOATING-POINT UNIT

MEMORY

REMARKS

request is pending. If one is pending, the FP15 waits; if not, the FP15 determines if indirection has
been requested. When indirection has not been requested, the FP15 enters the OPAND cycle, if an

V')
V')

o
o

«
~

6
w

AR .. MDI.:
THIS IS THE INDIRECT CYCLE
M REO, ADDR, MRD,
ADDR ACK
AND THE INDIRECT ADDRESS
0" M REO __
IS STROBED INTO AR.
REMOVE ADDR FROM MD L
0 .. ADDR ACK
OPERAND ADDR PLACED
DDR ON MOL AND ON MDL AT RD RST.
RD RST ISSUED
REST OF MEMORY
CYCLE COMPLETED

operand FETCH is requested, or the EXP cycle, if no operand FETCH is requested.

If indirection has been requested, the FP15 places the contents of the AR onto the MDL and issues

M REO. When RD RST is received from the memory, the contents of the MDL are strobed into BMB
bits 18 through 35 and then loaded into the AR. The FP15 then enters OPAND or EXP, as described
above.

u..
u..

0 .. MRLS ACK
BMB .. AR
If bit 00 of second word is 0 (Direct Addressing) omit indirect cycle.

Two other operations are also performed in the FETCH cycle. If the instruction is ADD, SUBTRACT, or
FIX, the FMO is cleared during TS03 of the FETCH cycle. If the instruction is a Reverse Divide, the
FMA is loaded into the FMO; if the instruction is a Reverse Subtract I the FMA is loaded into the FMB

Figure 3-3

Memory Interface--FETCH Cycle (Indirect)

during TS02.

3-3

This drawln, and s~dlc:dlOft'. nerem, .,. Ihe prop-

I ;:~"~,E;'.~ ~=:':::'.:'::"~:: I

STAR~

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written permlSSla.,

D
YES

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P

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FP¢8
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8MS 18 -35

FP// MDL

EN
FP¢rD

FF' RD RSTOLY

FPI¢ FP

FP/~I

DIS

I/O ,qCT

FPU
IRI¢ • I
STORE

YES

10
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NO.

DESCRIPTION
PARTS LIST

UNLESS OTHERWISE SPECIFIED

DECIMALS
.XXX =.005
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('{ (~ E

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DEC ~ORM NO
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3-4

SCALE
SHEET

TI'\ls drawlnland SpieCl"catJoM,lIef'ein••nth prep.

el't)l of [hal!.1 Equipment COrporabon and ~.N not be
reprodl.lClid or copied or uMCIln whole or In ~rt H
theb''''lfortMomanl.lf.eturwOlU.. ofifllmllwd:hOut

wntten perml55I011

MP.. £Q

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ITEM

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3-5

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erty 01 01£""' EqUlpmlEnt Curpor.t"~n Ind VI.II not be
reprQ(\1,JtC'd or eop'ecI or ayO In ~ or ifl pert e,

tne- tlU" for tne m"nuflctrJre or UI~ Df ams W/ttHnIt

"""tte" perm'S'511;tr

ONLY
FORRDD
FLOATING
+ SUB + FIX

IFP¢9 TS ¢ 3

c
FP33
S(Il <= H
51 = H
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S2 "

53 ..

FP3~

(/;ADD ¢¢ -35

(/l3

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FIIlST USED ON OPTIONIMOOEl

UNLESS OTHERWISE SPECIFIED
>

DECIMALS
.xxx" .005

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3-6

SCALE
SHEET

3.5

OPAND CYCLE INTERFACE

After the FETCH cycle, the FP15 enters the OPAND cycle. If an instruction is specified in which
operands are not fetched from memory (bit 10 of the floating-point instruction word on a 1), the
OPAND cycle is omitted completely and no memory reference is made. The current contents of the

If bit 10 of first word (71XXXXS) is set, the OPAND cycle is omitted completely. If the bit is 00, the OPAND cycle is performed. However,

certain operations in the OPAND cycle are excluded based on the following format:

FMA are used as the operand.

Double-Precision Floating Point - All Operations Performed
Single-Precision Floating Point - Omit Low-Order Mantissa
Double-Precision Integer
- Omit Exponent
Single-Precision Integer
- Omit Exponent and Low-Order Mantissa

For memory reference instructions, the operand or operands from memory are transferred to the FP15
during the OPAND cycle. The number of operands is dependent on the format specified and is defined

SUBCYCLE

CENTRAL PROCESSOR

FLOATING-POINT UNIT

MEMORY

REMARKS

in the note associated with the OPAND cycle in Figure 3-4. This description assumes doubleprecision floating-point format in which the maximum number of operands (three) is transferred from
memory. The first operand transferred is the exponent. The FP15 requests a memory cycle (M REQ)

I-

and transfers the effective address in the AR to memory via the MDL. Memory then places the first

oa...

operand (the contents of the address specified) on the MDL and issues RD RST. The FP15 strobes the

dress plus one). As a result, the address in the AR is incremented so that the next memory access will
transfer the second operand. The memory cycle is exactly like that described for the exponent operand.

one). The address in the AR is incremented a second time to obtain the third operand address. The
memory cycle is like that described for the exponent operand.

8MB - EPA
AR + 1 -AR

V')
V')

;:::

z
«

'"wo
The third operand (low-order mantissa) is in the next sequential location (high-order mantissa plus

~O - MRLS ACK

operand into the BMB and releases memory.
The next operand (high-order mantissa) to be obtained is in the next sequential location (exponent ad-

AR - MDL
M REO, MRD
I .... ADDR ACK
0- M REO"
REMOVE ADDRESS
FROMMDL ~O-ADDRACK
EXPONENT ON MDL
MDL - BMB-------r AND RD RST
FP MRDA____
ISSUED
o _ FP MRDA •
.... MRLS ACK

AR - MDL
M REO, MRD,

"s:

&-------+-

~~~~!=-r:~D::~ACK
I~

'"
o
J:

I
I

MDL - BMB
FP MRDA

d -r:

HIGH ORDER MANTISSA ON MDL &
RD RST ISSUED

'.MRLS ACK

o - FP MRDA--

AR + 1 - AR

0 _ MRLS ACK

FPU REQUESTS MEMORY CYCLE
WITH CONTENTS OF AR ON MDl.
FPU REMOVES ADDRESS FROM
MDL. FPU WAITS FOR EXPONENT
EXPONENT TRANSFERRED TO
FPU AND STROBED INTO
BMB. MEMORY
CYCLE COMPLETED
ADDR REGISTER INCREMENTED
FP REQUESTS MEMORY
CYCLE WITH INCREMENTED
OPERAND ADDRESS
HIGH-ORDER MANTISSA
STROBED INTO FPU MEMORY
BUFFER
MEMORY
CYCLE COMPLETED

AR - MDL
M REQ, MRD & -'-ADDR ACK
0- M REQ •
REMOVE ADDR FROM MDL~O _ ADDR ACK

FP REQUESTS MEMORY
CYCLE WITH TWICE-INCREMENTED OPERAND
ADDRESS

1
BMB~ISSUED

LOW-ORDER MANTISSA
STROBED INTO FP
MEMORY BUFFER

LOW ORDER MANTISSA
ON MDL & RD RST

MDL FP MRDA

o - FP MRDA4!::::

I~ 0 _ MRLS ACK

~RLS ACK

BMB - FMA 00-35

MEMORY CYCLE
COMPLETED
CONTENTS OF BMB 00-35
STROBED INTO FMA

AR + 1 - AR

Figure 3-4

Memory Interface--OPAN D Cycle

3-7

3.6

OPAND CYCLE DESCRIPTION

During the OPAND cycle, the FMB and/or EPB is loaded from memory jf the instruction specified is an
arithmetic instruction (Add, Subtract, Multiply, or Divide). For other types of instructions {including
Reverse Subtract and Reverse Divide}, the FMA and/or EPA is loaded. For integer format, the EPA is
not loaded.

ihe shift counter is decremented a second time to a count of O. ihe third memory reference is simi iar
to the second except that the address is again incremented to fetch the third operand (low-order mantissa). The -STROBE signal loads the low-order mantissa into the low-order bits of the BMB. If the
instruction is an arithmetic type, the B SIGN/FMB is loaded. If the instruction is a Fix, Load, Float,
Reverse Subtract, or Reverse Divide, the A SIGN/FMA is loaded. The A multiplexer is again selected
after the fetch of the third operand so that the A SIGN/FMA or B SIGN/FMB can be loaded as a

Drawings D-FD-FP1S-0-48 through D-FD-FP1S-0-S0 are flow diagrams of the OPAND cycle. The cy-

36-bit word from the 36-bit memory buffer.

cle is initiated when OPAND goes to 1. At TS02*PH01 of this cycle, an FP M REQ is issued.
The shift counter is decremented and now produces a borrow which indicates that all operands have
Since a WRITE operation is inhibited (-ALL WRITE), a memory read will occur. The address of the op-

been received. At this point, the OPAND cycle is cleared and the EXP cycle is enabled.

erand, located in the AR, is gated onto the MDL via the output multiplexer (MPO). FP M REQ, after
a delay to allow the MDL to settle, produces M REQ to initiate the memory cycle.
When memory receives the address, it issues ADDR ACK, which clears FP M REQ. The data (operand)

3.6.2

and RD RST are then placed on the MDL by the memory. Before strobing the data into its memory buf-

In single-precision Roating-point format OR 11 = 0, IR 12 = 1), the shift counter is loaded in the

fer, the FP15 waits for FP CYCLE. This signal is delayed by RD RST DLY to allow time for the data to

FETCH cycle with a count of 1 (SC 16 = 0, SC 17 = 1). A memory reference is made just as for

settle before it is strobed. When the data is strobed into the buffer, the FP15 issues FP MRDA and the
memory responds with MRLS ACK, whi ch clears FP MRDA to complete the memory cycle.
The data format must now be determined. For each format I the shift counter is loaded with one less
than the number of operands to be transferred to the FP15, so that the shift counter will detect a borrow
rather than a 0 condition. For example, in double-precision integer format the shift counter is loaded
with 1. Transferring the first word to memory decrements the counter to 0; transferring the second word
decrements the counter to produce a borrow indicating completion of the transfers.
3.6.1

Double-Precision Floating-Point Format

Single-Precision Floating-Point Format

double-precision floating point and the exponent operand is strobed into the low-order bits of the BMB,
, as a result of -STROBE. The B side of the ALU is selected for the first word of single-precision floatingpoint format. The first word consists of nine bits of exponent and nine bits of mantissa. The nine bits
of exponent are loaded in the EPA or EPB. The value ?f bit 09 (exponent sign) is extended through
bit 00. The nine bits of the mantissa remain stored in bits 18 through 26 of the BMB, since the
A SIGN/FMA or B SIGN/FMB are loaded 36 bits at a time. The exponent bits in the BMB are cleared
(bits 27 through 35).
At the end of the memory reference, the shift counter is decremented to O. Since no borrow is detected, a second memory reference is initiated to fetch the 18 bits of high-order mantissa from memory.

If double-precision, floating-point format is specified (IR 11 = 1, IR 12 = 1), the shift counter is

The address in the FP15 AR is incremented to access the next sequential memory location. The 18 bits

loaded, during the FETCH cycle, with a count of 2 (SC 16 = I, SC 17 = 0). A signal designated

of high-order mantissa are loaded into the high-order bits of the BMB by STROBE. The A side of the

-STROBE loads the low-order bits (8MB bits 18-35) of the memory buffer with the operand. The A side

ALU is selected and the A SIGN/FMA or B SIGN/FMB is loaded with the 27 bits of mantissa.

of the ALU is selected. If the instruction is a Fix, Load, Float, Reverse Subtract, or Reverse Divide,
an MA SEL signal is generated that causes the EPA to be loaded. If an arithmetic instruction is speci-

At the end of the cycle, the shift counter is decremented and produces a borrow indicating that the op-

fied (Add, Subtract, Multiply, or Divide) MA SEL is not generated and the EPB is loaded.

eration is complete. The OPAND cycle is cleared and the EXP cycle is enabled.

The shift counter is decremented and, if no borrow is generated, the second memory reference of the
OPAND cycle is initiated.
The second memory reference is similar to the first. The address in the AR has been incremented to ac-

3.6.3

Extended Integer Format

cess the next sequential memory location (high-order mantissa). The shift counter is now at a count of

In extended integer format (IR 11 - 1, IR 12 = 0) the shift counter is loaded with a count of 1

1 (SC 16 = 0, SC 17 = 1). ihe SiROBE signai ioads the high-order bits of the memory buffer (BMB bits

(SC i6 = 0, SC i7 = 1) during the FEiCH cycie. ihe normai memory reference is made, and STROBE

00-17) with the second operand.

causes the 18 bits from memory to be loaded into the high-order bits of the BMB.

3-8

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3-11

After completing the transfer, the shift counter is decremented to 0, no borrow is detected, the AR is

The various types of store instructions are described below:

incremented, and a second memory reference is initiated.
The second memory reference causes the 18 bits in the next sequential memory location to be loaded

3.7.1

Store JEA

into the low-order bits of the BMB by -STROBE. The A side of the ALU is selected and the FMA or

If the instruction is Store JEA, the contents of the JEA are transferred to the output multiplexer (MPO)

FMB is loaded with the 35-bit integer.

and then to the MDL.

After the transfer of the second word, the shift counter is decremented from 0 to a borrow condition.
The OPAND cycle is cleared and the EXP cycle is enabled.

3.7.2

Double-Precision Floating Point

In double..;precision floating-point format, the shift counter is loaded with a count of 2. The first word
3.6.4

Single-Precision Integer Format

(contents of EPA register) is transferred to the output of the multiplexer. When the shift counter is

In singl-precision integer format (IR 11 = 0, IR 12 = 0) only one memory reference is made. The shift

decremented to 1, the second word (high-order mantissa ADD 00-17) is transferred to the output of the

counter is loaded in the FETCH cycle with a count of O. A memory reference is performed to obtain

multiplexer. When the shift counter is decremented to 0, the third word (low-order mantissa ADD

the operand. The operand is loaded into the low-order bits of BMB 18-35. The value of bit 18 (sign

18-35) is transferred to the output of the multiplexer.

bit) is entered through bit 00. The A side of the ALU is selected and the A SIGN/FMA or B SIGN/
FMB is loaded.

3.7.3

Single-Precision Floating Point

At the end of the cycle, the shift counter is decremented from 0 to produce a borrow that clears the

In single-precision floating-point format, the shift counter is 1; EPA bits 09 through 17 and FMA bits

OPAND cycle and enables the EXP cycle.

18 through 26 are transferred to the output of the multiplexer. When the shift counter goes to 0, FMA
bits 00 through 17 are transferred to the output of the multiplexer.

3.7 WRITE CYCLE

If a Store instruction is specified, the WRITE cycle is initiated. During the WRITE cycle the contents
of the desired major registers are written into memory. Drawing D-FD-FP15-0-51 is a flow diagram of
the WRITE cycle. At TS02*PH03 of the NOR cycle, the shift counter is loaded with one less than the
number of words to be transferred to memory.
The FP15 places the contents of the AR on the MDl and issues a delayed FP M REQ that allows for
settling time. The AR contains the address where the first operand is to be stored. Memory receives
the address on the MDL and issues ADR ACK indicating receipt of the address. This signal also clears
FP M REQ and enables the data to be placed on the MDL.

3.7.4

Extended Integer

The shift counter is loaded with a count of 1 for this format. When the shift counter is 1, the highorder bits (ADD 00-17) are transferred to the output of the multiplexer and, if the shift counter is 0,
the low-order bits (ADD 18-35) are transferred to the output of the multiplexer. When an Integer
Store instruction is specified, positive or negative integers are transferred from the FMA to the FMB
and are l's complemented during FUN*TS02. At NOR*TS01, the FMB is incremented so the contents
of the FMB are now a 2 1s complement representation of the integer in the FMA. During the WRITE cycle, the sign (A SIGN) of the FMA is examined. If the sign is positive, the integer is a positive integer and the contents of the FMA are stored in memory. If A SIGN is negative, however, the contents

The particular word (depending on the count in the shift counter) is strobed on the MDL. FP MRDA

of the FMB are stored in memory, since the FMB is the 2's complement of the FMA and negative inte-

is delayed by ADDR ACK to allow address settling. The operand is strobed into memory by FP MRDA.

gers are 2 1s complemented before being transferred to memory.

Memory responds with MRlS ACK that clears FP MRDA to complete the cycle.
The number of memory references during the WRITE cycle depends on the instruction and/or data for-

3.7.5

Single-Precision Integer

mat. When the shift counter produces a borrow, the WRITE cycle is terminated. BUSY and DIS CP

When a single-precision integer Store instruction is specified, the contents of the FMA are transferred

ACT signals are cleared and control is returned to the CPU.

to the FMB and lis complemented during FUN*TS02. At NOR*TSOl, the FMB is incremented and now

3-12

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NO

FP3¢ LOAD Sc..

WITH COUNT
2. = D P1=
1= SPF+ DPI

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S TORE

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FP¢"I T3 *- P3

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3-13

represents the 2's complement of the FMA. During the WRITE cycle, A SIGN is examined. If it is
positive, the contents of the FMA are stored in memory; if it is negative, the 2 1s complement of the

CENTRAL
PROCESSOR

SUBCYCLE

FLOATING-POINT
PROCESSOR

MEMORY

REMARKS

negative integer are stored in memory. This 2 1s complement is contained in the FMB and, consequently,
the contents of the FMB are stored in memory.

0 ... DIS CP ACT
M REQ·CP ACT r---

1 + DIS C~C1ADDR ACK

3.a

~DISRDRST

INTERRUPT CYCLE INTERFACE

0 .. M REQ
~I- ADDR ACK
RD RST

The following conditions in the FP15 can cause an interrupt in the CPU.
a.
b.
c.
d.

Overflow
Underflow
Abnormal division (divide by zero)
Memory violations (trap)

An interrupt generated as a result of an overflow or underflow condition can occur during the FUN

CPU CONTINUES FROM TS03*PH02
CPU MAK ES MEMORY REQUEST
FP15 COMPLETES MEMORY CYCLE

FPMRDA~

..-..
w
....J

::I:

MRLS ACK
0 ... FPMRDAd
....... "0 .. MRLS ACK
o ... DIS RD RST
12oo00a .. MDL
VFP RD RST

uot:;

>- -Ie LL
UV'l>-~~

I-"""'I~
~

- e.
Z

cycle, where the arithmetic operation is being performed, or during the NOR cycle, where the result

120000a ... MIA'

of an arithmetic operation is being normalized. An abnormal divide interrupt can occur only during

MRLS~

the FUN cycle; a m~mory violation interrupt can occur during the FETCH, OPAND, or WRITE cycles.

0 .. MRLS .....

If an interrupt should occur while an FP15/CPU cycle is in progress, the cycle is completed, the re-

FP15 FORCES JMS*O (120oo0a) ON
MOL AND COMPLETES CPU CYCLE
FP MRLS ACK

,~O ... MRLS ACK

MI ... IR

maining sequence is aborted, and INT 1 and INT 2 interrupt cycles are initiated.

0 .. DIS CP ACT

120000a (JMS *0) LOADED IN IR

If an interrupt caused by a memory violation occurs in the OPAND cycle while the exponent is being
Figure 3-5

fetched, this part of the sequence is completed, fetching of the high-order and low-order mantissas is

INT 1 Cycle Interface Diagram

aborted, and the interrupt occurs. If the interrupt occurs during fetching of the high-order mantissa,

3.a.2

INT 2 Cycle

The FP15 completes this part of the cycle and aborts fetching of the low-order mantissa.

The FP15 initiates a second dummy setup that forces the CPU to accept the JEA (JMS Exit Address) instead of the contents of location 0 (see Figure 3-6). The JEA address is under programmer control and
wi II vary depending on the cause of the interrupt.

3 .a. lINT 1 Cycle
When a floating-point interrupt is raised, the FP15 forces a JMS*O to the CPU by placing 120oo0 on
a
the MDL. Figure 3-5 shows the communication between the CPU and FP15. It is assumed that a memory violation interrupt occurred during the fetching of the high-order mantissa. When the high-order
mantissa has been fetched, the OPAND cycle is aborted and a dummy setup initiated. The FP15 removes DIS CP ACT and the CPU is allowed to make a memory request. DIS RD RST is raised and the
FP15 completes the memory cycle. The FP15 then removes DIS RD RST, places 120000 (JMS*O) on
a
the MOL, and issues FP RD RST. The 12ooo0 is strobed into the MI in the CPU and then executed.
a
The remainder of the cycle between the FP15 and CPU is completed.

3-14

EXIT ADDRESS +0
+1
+2
+3
+4
+5
+6
+7

0
JMP OVR
0
JMP UNO

JMP DIV
0
JMP TRAP

/GO TO OVERFLOW
/GO TO UNDERFLOW
/GO TO DIVIDE
/GO TO MEMORY VIOLATION

In the example presented, where a memory violation caused the interrupt, the JEA address +6 will contain the address of the PC (71XXXXa instruction) +3 when the JMS is complete. JEA +7 may contain
a jump instruction to an entry of a service routine associated with the interrupt.

3.9 INTERRUPT CYCLE
SUBCYCLE

CENTRAL
PROCESSOR

FLOATING
POINT UNIT

MEMORY

REMARKS

On entering INT 1, DIS CP ACT is removed; this allows the CPU to continue (see drawing
D-FD-FP15-0-62). When CP Active is clocked high, and a M REQ is made by the CPU to obtain the
next instruction, the FP15 is set up to take control over memory. In addition, DIS RD RST is raised to

M REQ·CP ACT-

1 - DIS CP A:1ADDR ACK

CPU MAK ES MEMORY REQUEST
FP15 COMPLETES MEMORY CYCLE

1 -+ DIS RD RST

O-+MREQ~

J~
J:

FPMRDA~

wI-,w

o ... FP MRDA-c1

u LL
>->u~

N~
I-=>

-«
w
...,

o ... DIS RD RST

DIS RD RST. The FP15 issues MROA and the memory responds with MRLS ACK to complete the cycle.

JEA +0 OVR} rEA ADDRESS - MDl
2 UND MI FP RD RST
4 DlV
6 TRAP

Control is returned to the CPU. The FP15 then initiates a dummy setup that places 1200008 on the

MRLS ACK

~ 0 -

MOL via the input multiplexer (MPI) and output multiplexer (MPO). FP RD RST is also placed on the

MRLS ACK

MOL. At this point, the FP15 simulates memory and communicates with the CPU to complete the cyFP15 FORCES JEA ADDRESS ON MDL
AND COMPLETES CPU CYCLE

~"'O ... FP MRLS ACK

o ... DIS CP ACT

cle. The 1200008 is loaded into the MI register in the CPU. When the CPU receives the 1200008, it
issues MRLS. The FP15 responds with FP MRLS ACK, both are then cleared and the INT 2 cycle is initiated •

MRLS~
~FPMRLSACK

0- MRLS

the CPU. Memory responds to the CPU M REQ with ADDR ACK, places the contents of the specified
address on the MOL, and issues RD RST. The CPU never sees the contents of the address because of

- ADDR ACK

~RDRST

inhibit communication between the CPU and memory, and DIS CP ACT is raised to temporarily suspend

The INT 2 cycle is similar to INT 1 except that the JEA address, instead of 1200008 , is placed on the
JEA ADDRESS IS ACCEPTED BY CPU
AS IF IT WERE CONTENTS OF
LOCATION 000000 8 •

MOL, the CPU executes the 1200008 as a JMS*O and makes a second M REQ. The FP15 again suspends the CPU with OIS RO RST I gains control of memory, and completes the memory cycle. The JEA
address is placed on the MDL along with FP RO RST. At this point, the FP15 releases control to the
CPU and simulates a memory so the CPU can load the JEA address into the MI register. The CPU can

Figure 3-6 INT 2 Cycle Interface Diagram

now complete its cycle which was initially suspended by the FP15. The action is concluded by BUSY
and DIS CP ACT being cleared, thereby retum ing control to the CPU.

3-15

'hI" gr•• ,nc _nca ~PK,IO(;at>ons, t>e~n. are the ptOJ)

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I

FP¢:3 MPI_MFb
M PO _

MLD

120000
._MDL

~::/1'Ir;;;i~~i<7B
---I'MPQ

JEA.+

¢;~, 1, ORt<. _MLD

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3.10

FP15/CPU CONTROL

As an aid in understanding the exchange of control between the CPU and the FP15, Figure 3-7 shows
a typical program describing what instructions the CPU would see and what instructions the FP15 would
see if the program were executed. The first instruction (DAC 500) is recognized by the CPU and the
contents of the accumulator are deposited in location 000500. The second instruction is a floatingpoint instruction that is recognized by both the CPU and FP15. The next three sequential locations
(000110,000111, and 000112) are recognized by the FP15. The FP15 takes control and forces a
710000 NOP on the MDL so that the CPU does not use the floating-point operand address as an instruction. Consequently the CPU waits, since the FP15 has control of memory. When the FP15 completes the instruction, both the CPU and FP15 again monitor the next instruction fetched from core.
A similar process can be traced through the remaining steps in the program.

DLD = Double Precision Floating Point Load
DAD = Double Precision Floating Point Add
DST = Double Precision Floating Point Store
000097
000100
000101
000102
000103
000104
000105
000106
000107
000110
000111
000112
000113
000114
000115
000116
000117
000120
000130
000500
CP SEES
040500
XXXXXX
713150
710000
CP WAITS
716140
710000
CP WAITS
713750
710000
CPU WAITS

040500
713150
000110
716140
000113
713750
000116
200130
740040
XXXXXX
XXXXXX
XXXXXX
XXXXXX

xxx xxx

XXXXXX
XXXXXX
XXXXXX

XXXXXX

DAC SOO
DLD 110
DAD 113
DST 116
LAC 130
HLT
EXP A
HIGH MANTISSA AUGEND
LOW MANTISSA
EXP B
HIGH MANTISSA ADDEND
LOW MANTISSA
EXPONENT
}
HIGH MANTISSA SUM
LOW MANTISSA

/CPU INSTRUCTION
/FPU INSTRUCTION
/OPERAND ADDRESS
/FPU INSTRUCTION
/OPERAND ADDRESS
/FPU INSTRUCTION
/SUM STORED
/CPU INSTRUCTION
/CPU INSTRUCTION

77m7
000000
FPU SEES
/CPU INSTRUCTION
/CPU WRITES INTO LOC 500
/FPU INSTRUCTION
/FPU FORCES 710000 TO CP
/FPU SEES CONTENTS
/OF 000110, 000111 & 000112

713150
000110

XXX XXX
XXXXXX
XXXXXX
716140
000113
XXX XXX

/FPU INSTRUCTION
/FPU FORCES 710000 TO CP
/FPU SEES CONTENTS
/OF 000113, 000114 & 000115

XXX XXX
XXXXXX
713750
000116
XXXXXX
XXXXXX
XXX XXX

/FPU INSTRUCTION
/FPU FORCES 710000 TO CP
/FPU WRITES INTO LOC.
/000116,000117 &000120

200130
777m
740040

/CPU INSTRUCTION
/CONTENTS OF 000130
/PROGRAM HALTS
Figure 3-7

CPU!FP15 Sample Program

3-17

CHAPTER 4
INSTRUCTION SET

4.1

INTRODUCTION
EXIT

The following paragraphs describe the classes of instruction used in the FP15. Several functions are
FMA

applicable to many classes; these will be described first. The flow diagrams of the instructions specify

CONVERSION

where these functions occur, if applicable. These functions include: converting negative integers to
NO

sign and magnitude format, normalizing, and rounding.

4.2

CONVERTING NEGATIVE INTEGERS TO SIGN AND MAGNITUDE FORMAT

When a 2's complement negative integer is loaded into the FMA during the OPAND cycle, it is converted to sign and magnitude format during the EXP cycle. Two's complement positive integers are already in sign and magnitude format and require no conversion. If the instruction requires no memory
reference, the number in the FMA is in sign and magnitude format. Two's complementing the number
again is undesirable, since it would convert the sign and magnitude number back to a 2's complement
!

C
__DO_N_E_ _)

number.

'5-0576

For FMA conversion during TS01 of the EXP cycle, FMA is complemented as a result of COMP MA

Figure 4-1

Converting Negative Integers to Sign and Magnitude

(see Figure 4-1). This signal takes the l's complement of the integer in the FMA and puts it on the
ALU bus. During PH03*TS01, the number on the ALU bus is strobed back into the FMA.

In EXP*TS02, INCB is generated which puts the contents of the FMB plus one on the ALU bus. This
number is strobed back to the FMB during PH03*TS02. The number now in the FMB is the 2's comple-

When the FP15 sequences to TS02 of the EXP cycle, INCA is generated; this puts the contents of the

ment of the number originally contained there and is a negative number in sign and magnitude format.

FMA plus one on the ALU bus. During PH03*TS02, INCA-P is generated, and the output of the ALU
bus is strobed back to the FMA. The number now in the FMA is the 2's complement of the number initially contained there and is a negative number in sign and magnitude format.

4.3

NORMALIZE

Normalizing a mantissa in the FMA consists of left-shifting the FMA until the most significant bit is a
For FMB conversion, during T501 of the EXP cycle, the FMB is complemented as a result of COMP MB.

1, which eliminates all leading zeros. For every left-shift of the FMA, the EPA is decremented. If

This signal takes the l's complement of the integer in the FMB and puts it on the ALU bus. In

the specified instruction is a Store or Divide, and normalizing is requested, the mantissa is normalized

PH03*TS01, COMP MB P is generated which strobes the l's complement integer back into the FMB.

during FUN*TS01. Otherwise, the mantissa is normalized in NOR*TS01.

4-1

4.3.1

Normalization (Except Store, Divide, or Reverse Divide)

If the specified instruction is not a Store or Divide type instruction, and normalizing is requested, the
normalizing process occurs in NOR*TSOl. Prior to this time, the shift counter is loaded with 428 {at
FUN*TS03*PH03 Time}. The NOR SEL signal sets up the conditions for the NORM P pulses that actually cause the normalizing. For each NORM P pulse, the FMA is shifted left and the EPA and shift
counters are decremented. If the instruction specified is not a Multiply, zeros are shifted into the
least significant positions of the FMA. If a Multiply instruction is specified, the NORM P pulses shift
the FMQ left as well as the FMA. As a result, FMQ 01 is shifted into FMA 35 and 0 is shifted into

A second round can occur during floating-point addition if the addition produced a carry out of the
ALU (see Figure 4-2). When this occurs, the FMA is right-shifted and the EPA is incremented, putting the correct number back into the FMA. The bit shifted out of the least significant bit of the FMA
is shifted into a guard bit and, if rounding is requested, +1 is added to the least significant bit of the
FMA.
The following example shows two numbers being added resulting in a carry. The EPA is incremented
and the FMA right-shifted. Since the least signif~cant bit of the FMA is a 1, the guard bit is set.
When rounding is requested, +1 is added to the least significant bit of the FMA.

FMQ 35.
Example:
When FMA 01 goes to 1 (NORM DONE), or when the shift counter produces a borrow (SC BORROW),
normalizing is terminated and the, logic on FP09 is reset to allow the phases and time states to continue.

.101 + .110 = ? Three-bit registers assumed for simplicity.
2
2
ADDITION

A borrow indicates that normalization is not possible because the number is O. Refer to Drawings
D-FD-FP15-0-58 and D-FD-FP15-0-59 for a detailed flow of normalize.

I
\

4.3.2

FMA

FMB

I0 I

I 1 I0

Store, Divide, or Reverse Divide

When a Store or Divide instruction is specified, and normalizing is requested, a NOR SEL signal
(FP40) is generated that enables NORM P to left-shift the FMA and to decrement the EPA for each
left-shift (refer to Drawing D-FD-FP15-0-57). The FP15 sequences to PH03*TSOl of the FUN cycle

and remains IIstopped

Carry,

in this state until normalizing is completed.

Before generating NORM P, the shift counter is loaded with octal 43 (35

) if the specified instruc10
tion is a Divide or Reverse Divide, and is loaded with 428 (34'0) if the specified instruction is a Store.

I I I I
0

'G~~0Q

and increment EPA

For each NORM P pulse, the FMA is shifted left and both the EPA and shift counter are decremented.
Zeros are shifted into the least significant positions of the FMA. Normalizing is complete when

ROUNDING

FMA 01 goes to a 1 (NORM DONE), or when the shift counter produces a borrow (SC BORROW). In
either case, the logic on FP09 is II reset " and the phases and time states are allowed to continue.

4.4

ROUNDING

The FP15 can specify rounded or un rounded arithmetic by IR14 of the instruction word.
During alignment of the mantissas in floating-point addition, either the FMA or FMB (depending on
whi ch has the smaller exponent) is shifted right. Bits shifted out of either register are shifted into the

FMQ. If rounding is requested, and FMQ 01 is a 1, +1 is added to the least significant bit of the
FMA or FMB, whichever was being shifted.

4-2

Figure 4-2

Guard Bit and Rounding

r~proc:luced or copted or uHd In whole or in p.rt as
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4-4

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.-------'''------, FP 38

.-------'''-----,FP32
M)(,q; PMA It

:=.rt ;51, MODE
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p,:.. U BUS

FMQ ARE
SHIFTED LEFT

,------'1<'--------, FP3¢

>i(

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MQ7. P

'~.-~--:::z-;:-;;c:.--I ~= 4-.5

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r---....--lI~-----, FP3 ¢

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FP4-3
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r-------~~----;

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FP38

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TO INTERRUPT
FLOW
r-----~L------.FP43

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FP39

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DESCRIPTION

PART NO,

ITEM
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"O"-OO"-D

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UNLESS OTHERWISE SPECIFIED
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FLOAT

DIV FUN C::YC LE

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4-5

If the +1 added to the FMA causes a carry out of the ALU, the FMA is right-shifted and the EPA is in-

MULTIPLY OR DIVIDE OR FIX

ADD OR SUBTRACT

FP12(NOR.T1)*FP40(FLOAT'" FIX)

FP36 ADD+ SUB SEL
I

cremented.
FP31 MP,( + DIV + FIX

For floating-point Multiplication and Division, rounding can occur. If the multiplication or Division

LOAD JEA
FMOOl (1)

operation causes FMQ 01 to go to a 1, the guard bit is set. With this bit set,and rounding requested,
BMB BIT 19 (1)

+ 1 is added to the least significant bit of the FMA.
For a Fix instruction, bits in the FMA and FMQ are right-shifted. If, upon termination of the shifting
process, FMQ 01 is set, the guard bit is set. A rounding request will then ~ause +1 to be added to the
least significant bit of the FMA.

4.5

GUARD BIT

The guard bit is used to determine whether rounding should occur if rounding is requested (see Figure

I~-o~eo

4-3). This bit is set under the following conditions:
a.

b.
c.

During floating-point Addition, when a carry is produced out of the ALU, the FMA
is right-shifted and, if the least significant bit of the FMA is a 1, the guard bit is
set.

Figure 4-3

Flow Diagram for Setting Guard

EPA/A SIGNjl=MA are transferred to the EPB,/B SIGN/FMB during the FETCH cycle and the Reverse
Subtract instruction loads the minuend into the EPA/A SIGN/FMA.

During floating-point multiplication and division, if FMQ 01 is a 1 after the multiplication or division operation, the guard bit is set.

4.6.1

During a Fix instruction, upon completion of the shifting process, if FMQ 01 is a
1, the guard bit is set.

The first function performed in the EXP cycle for floating-point addition or subtraction is a check to

EXP Cycle

The contents of the guard bit are saved in bit 01 of the JEA word on a Store JEA
instruction •

determine if the specified instruction is an Add, Subtract, or Reverse Subtract (see ,Drawing

The Load JEA instruction restores the guard bit to a 1 if bit 01 of the JEA operand
fetched from memory is set.

the FMA and 0 indicates that the FMB is disabled from the ALU. A test is now made to determine if

D-FD-FP15-0-52). If it is a Reverse Subtract, A-0-1 is transferred to the ALU bus where A represents

A=B; if so, the FMA is known to be 0 and STOP AUGN (1) is set. If the specified instruction is Add
When the next instruction is specified (provided it is not a Floating-Point Test, Load JEA, Store JEA,

or Subtract, 0-B-1 is transferred to the ALU bus, where 0 indicates that the FMA is disabled from the

or Branch), the guard bit is cleared.

ALU and B represents the FMB. A test is made to determine if A=B; if it does, the FMB must be equal
to 0 and STOP ALIGN (1) is set. In effect, then, no alignment will occur for a zero FMA or zero
FMB and the FUN cycle is initiated. Also, if the difference between the EPA and EPB is greater than

4.6

FLOATING-POINT ADDITION AND SUBTRACTION

and double-precision floating-point numbers. The manner in which these arithmetic operations are

42 , STOP AUGN (1) is generated, no alignment occurs, and the FUN cycle is initiated. However ..
8
if the FMA and FMB are non-zero and the difference between the EPA and EPB is less than 42 , align8
ment is initiated. EPA-EPB-1 is placed on the ALU bus and, if the exponents are equal, the mantissas

implemented is similar and will be described, with differences pointed out as they occur.

are already aligned and the FUN cycle is initiated.

In floating-point subtraction, the minuend is loaded into the EPA/A SIGN/FMA via the Load instruc-

If the exponents are not equal, the sign of the result of EPA-EPB is determined. A negative sign

tion and the subtrahend is loaded into the EPB/B SIGN/FMB via the subtract instruction. If, as a re-

(ADD18H) indicates that the EPB is greater than the EPA and the FMA must be aligned. A positive

sult of some previous computation, the proposed subtrahend for the next subtraction is in the FMA, a

sign (ADD18L) indicates that the EPA is larger than the EPB and the FMB must be aligned. At this

Reverse Subtract instruction can be issued. In this event, the contents (subtrahend) of the

point, the shift counter is loaded with EPA-EPB-1, if the EPA is larger than the EPB or with EPA-EPB-l

The FP15 can perform floating-point addition, subtraction, and reverse subtraction for both single-

4-6

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D
31

DURING THE

OPAND

CYCLE OF ROD OR SUB

"THE FIdS IS LOADED
WITH ,I-IE ARGUMENT
FOR REV 51)8 THE
FMA

LOADED

FP37

FP37
SA 1-1
IS SMIlLLER
THAN EPa

FMA

SELECTED

EPa IS SMALLE
THAN
EPA
FMB 'SE"LECTED

FOR

SHlF,ING

FOR

EPA

SHIFTING
~P37

STOP ALIGN

WILL BE SET IF
FP32 A ZERO OR FP.
B ZERO IS SET OR-IF
EPA - [;PB>'3S /0

COUNTER, FM8
SHIFT RIGH~
FMB SS-FMQ

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ITEM
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DIMENSION IN INCHES

TOLERANCES
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4-7

and carry insert (EPA-EPB+l-1) if the EPB is larger than the EPA. This is to set up the shift counter so

to -1 and the second to ol! zeros T which is detected as en SC CARRY. This indicates termination of

the proper amount of shifts are performed to align the exponents.

mantissa alignment.

Ta determine whether the FMA or FMB is to be selected for shifting, the signs of EPA and EPB are ex-

If the FMB is selected for shifting as a result of EPB being smaller than EPA, SA will be low and the

amined, in addition to the sign (ADD1S) of the result of EPA-EPB. The three cases, in which the FMA

shift counter is loaded with EPA-EPB-l. This quantity is a positive number and the counter is decre-

is selected for shifting, are listed below:

mented for each shift until an SC BORROW is detected; this is why EPA-EPB-1 is required rather than

is loaded with EPA-EPB-l or 1. The first shift of the FMB decrements the counter to zero, and the

Example:

second shift of the FMBdecrements the counter to all ones, which is detected as SC BORROW to con-

+3
-(+5)
-2

EPA
EPB

-5
-(-3)
-2

EPA
EPB

Since the exponent associated with the mantissa not being shifted is the true exponent of the result, it
is necessary to load the EPB into the EPA, if the FMA was selected for shifting. While alignment is
taking place, the time state generator is disabled. On completing the alignment process, the time
state generator is restarted, and the FUN cycle is initiated.

EPA-EPB

EPA negative and EPB positive. The sign in this case is always negative indicating
that the EPB is larger (more positive) than the EPA.
Example:

clude the alignment.

EPA-EPB

Negative EPA, negative EPB, and a negative sign for EPA-EPB. In this case, EPA
is smaller (more negative) than EPB in order for a negative sign to occur.
Example:

EPA-EPB. For example, assume that the EPA contains +3 and the EPB contains +1. The shift counter

Positive EPA, positive EPB, and a negative sign as a result of EPA-EPB. With both
quantities positive and a negative result for EPA-EPB, the EPA is smaller than the EPB.

-5
-(+2)

EPA
EPB

. -7

EPA-EPB

4.6.2

FUN Cycle

In the FUN cycle, the A side of the ALU is disabled if the FMA is 0 and the B side of the ALU is disabled if the FMB is 0 (see Drawing FP15-0-53). When the EPA differs from the EPB by more than 35

,
10
the side of the ALU associated with the smaller exponent is disabled. This prevents additional shifting

For all other possibilities, the FMB is selected for shifting. Up to this point, the FMA and FMB have

and is time saving. For example, if EPB is greater than EPA by 1000, EPA has to be shifted 1000

been examined to see if either is OJ the shift counter has been loaded with EPA-EPB (if EPA < EPB) or

times and is, thus, a very small number compared to EPB. In fact, the number is so relatively small it

EPA-EPB-l (if EPA> EPB) to provide an accurate count of the number of shifts required to align expo-

can be considered O. Consequently, the B side of the ALU is disabled, the 1000 shifts are prevented,

nents; and the mantissa register associated with the smaller exponent has been selected for shifting.

and the time necessary to perform these shifts is saved.

If STOP ALIGN is set, this indicates that mantissa alignment is not necessary as a result of one of the

The following two rules of addition and subtraction with respect to the sign are used.

following conditions:
a.
b.
c.

Zero FMA
Zero FMB, or
EPA-EPB> 35

During addition, quantities with like signs are added, while quantities with unlike
signs are subtracted.
Examples:

-5

+5
+(+2)

+(+2)

-3

If STOP ALIGN is not set, alignment is performed, and either the FMA or FMB is selected for shifting.
NOTE

The mantissa with the smaller exponent is selected for shifting. If the EPA is less than the EPB, SA H

In the example on the right the two quantities are subtracted although the operation specified is addition.

is generated and the FMA is shifted. The shift counter is loaded with EPA-EPB, which will be a negative number in this case. The counter will be incremented with each shift until an SC CARRY is detected (counter going from all ones to all zeros). For example, if the EPA contained +2 and the EPB
contained +4, the shift counter is loaded with -2. The first shift of the FMA increments the counter

During subtraction, quantities with like signs are subtracted, while quantities with
un I ike si gns are added.
(continued on page 4-10)

4-8

dr-.".

and ~s. MNm." the PI'DP'
ettYOfDiaitalEQUiPMMCoIlIorationand .....llnotbe

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..ntt:.n parml$llion.

FP27

IF Th'ERE W,<JS

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If'eS<.i{. T IS TWo'S

ADD

COMPU! MENT€"D

FP37
SA H

YES
FP33

FP3"3

AUS

1-1

,HE" A SlDE (FMA'; OFTII.

E B SIDE (FMS)CFTH
,£9U:';
WILL BE fl
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PH!j .3

NRD+I FMAL WILL
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~g~0r;I!i~D IS0;:07

FMQ

¢ I

({ill)

FP3G>

r---_ _-'-N-'-O~NRD+ I

INT

CYCLE

NRD -fI L WII..t. 8e
7RVc W.I,IC"/v /?OUNDIM

fzS NOT /i'Eo,VE.:5TcD
O.R IF FMQ i2l1 (e)
OR IF S8('

B
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UNLESS OTHERWISE SPECIFIED

DESCRIPTION

ITEM
NO.

OIMUtSION IN INCHES

TOLERANCES
DECIMALS

FRACTiONS

.005

:::!: 1/54

:::!::

M~TERI~L

FINISH

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4-9

Sign

b.
(cont)

Examples:

+5
-(+2)

+5
-(-2)

Example:
-3
(with overflow) -(-6)

o0 1 1
o1 10

1 1 0 1

FMA
FMB

tOverflow, 2's complement

NOTE

result, complement sign

In the example on the right the two quantities are
added although the operation specified is subtraction.

t
Sign complemented

Referring to the flow diagram again, quantities with unlike signs during addition and like signs during

o0 1 1

= +3

2's complement of result

subtraction are actually subtracted. Thus A-B-l is put on the ALU bus for these cases. Conversely,
quantities with like signs during addition and unlike signs during subtraction are actually added. In

If rounding is not requested or FMQ 01 is a 0, 1 is added to the FMA to compensate for the incorrect

these cases, A+B is put on the ALU bus.

result. The result is then loaded into the FMA.

4.6.3

4.6.4

Processing of Subtracted Quantities

Processing of Added Quantities

If the quantities are being subtracted and the FMB contains the mantissa with the smaller exponent, it

When two quantities are to be added (addition with like signs or subtraction with unlike signs), A+B is

must be determined if rounding has been requested and whether FMQ 01 is a 1. If both conditions are

put on the ALU bus as described previously. If FMQ 01 is a 1 and rounding is requested, +1 is added

true, A-B-1 is put on the ALU bus. An additional 1 is subtracted to account for the rounding of the

to the least siglificant bit of the FMA.

FMB (A-B-1 =A-[B+1]). This is accomplished by putting A-B-1 on the ALU bus rather than just A-B.
If rounding has not been requested, or FMQ 01 is a 0, a carry insert of +1 is added and A-B-l+1, or
simply A-B, is put on the ALU bus. This quantity, in both cases, represents the result that is loaded
into the FMA. However, if overflow occurs, it indicates a wrong assumption was made and the result
in the FMA is incorrect. This is explained in detail in the following paragraphs.

A check is now made for an overflow condition. A floating-point overflow causes a signal designated
GRT to be issued. The FMA is right-shifted to transfer the overflowed bit back into the FMA; the EPA
is incremented to compensate for the shift. ADD 35 is examined prior to the right-shift--if this bit is
a 1, FMQ 01 becomes a 1 after the right-shift and the guard bit is set. The FMA is now loaded with
the results of A+B on the ALU bus. If no overflow occurs, the FMA is not right-shifted, the guard bit
is not set, the EPA is not incremented, and the FMA is loaded directly with A+B from the ALU

4.6.3. 1

Overflow - For quantities that are actually subtracted (addition with unlike signs or subtrac-

bus.

tion with like signs), the sign of the result is assumed to be the same sign as in the FMA. If no overflow occurs, the sign of the result is correct. If overflow occurs, it indicates an incorrect sign has
Overflow Interrupt Due to Addition or Subtraction - If the addition or subtraction operation

been assumed. If this occurs, the assumed sign is complemented and the actual result is 2's comple-

4.6.4.1

mented. Two examples follow--the first shows that the assumed sign is correct, the second shows that

results in an exponent greater than 217_1 (3777778)' a temporary overflow occurs. The result contained in the EPA, after the overflow, is no longer the true result. However, the true result can be

the assumed sign is incorrect.

calculated by adding the contents of the EPA, after the overflow, to 217. The contents of
Example:
(no overflow)

4-10

Sign

A SIGN/FMA are unchanged.

o1 10

o0 1 1

FMA
FMB

o0 1 1

= +3

-3
+3

4.6.4.2

Overflow Interrupt Due to Rounding - If rounding is requested, and the rounding operation

tNo overflow, sign

produces a carry out of the ALU, the ~MA is right-shifted and the EPA is incremented. If the EPA

correct, resu It correct

contains 3777778 and is incremented, an overflow interrupt occurs and the interrupt cycle is initiated.

4.6.4.3

Underflow Interrupt Due to Normalizing - Normalizing is accomplished by left-shifting the

FMA and decrementing the EPA for each left-shift. If, during this process, the EPA contains 4000008
and is decremented to 377m8' an underflow interrupt occurs. The contents of the A SIGN/FMA are
18
correct. The EPA no longer contains the true result; however, this can be obtained by adding _2 to
the contents of the EPA after the underflow occurs.
Example:

EPA

400000

-1
Result left in EPA
18
True result = -2 + 3777778

3777778

It is possible for the underflow to eliminate the condition that causes the temporary overflow during the
addition or subtraction. If underflow does not remove this condition, the overflow interrupt becomes a
permanent interrupt and enters an interrupt cycle (see Parcigraphs 3.8 and 3.9).

4-11

4.7

INTEGER ADD AND SUBTRACT

The FP15 can perform addition, subtraction, and reverse subtraction using either single-precision or
extended-precision data formats. Addition, subtraction, and reverse subtraction are performed in a
similar manner and will be explained using Drawings D-FD-FP15-0-52 and D-FD-FP15-0-53 for reference.

One of the last things performed in integer addition or subtraction is to determine the sign of the resuit.
This is accomplished by assuming the previous sign of the FMA is correct. If so, there is no carry generated out of the ALU, and the addition or subtraction of the FMA or FMB is done in the normal manner. The A SIGN represents the sign of the result and the contents of the FMA yield the true number.
However, if a carry occurs out of the ALU, this indicates that the sign has been assumed incorrectly.
I f this is the case, the existing contents of the FMA are 2's complemented and the A SIGN is complemented. Several simplified examples follow that illustrate this concept. Note that a bad assumption

4.7.1

EXP Cycle

can only be made when the ALU is specified to do an A-B function.

In the EXP cycle, negative integers (stored in memory in 2's complement format) are converted to sign
and magnitude format. For example, if the specified instruction is a Load or Reverse Subtract with a

Example: Bad Assumption (Integer Add)

negative argument, the argument is converted to sign and magnitude format and loaded into the FMA.
If the instruction is an Add or Subtract, with a negative argument, the argument is converted to sign

A SIGN

B SIGN

FMA

-2

FMB

+(5 )
8

Result
(i ncorrect )

and magnitude format and loaded into the FMB. The negative integers are converted from 2's complement to sign and magnitude format by l's complementing and incrementing the 2's complement integer.
For example, the number -58 in 2's complement format is 1.011. One's complementing and incrementing this number yields 1.101, which represents -58 in sign and magnitude format.

ALU Performing
A-B Function

Bad assumption (ADD 00 H)
(2' s comp Iement FMA)
4.7.2

FUN Cycle

In the FUN cycle, the signs of the operands are compared. If the specified operation is an integer

(Complement A SIGN)
A SIGN

add and the signs are unlike or an integer subtract and the signs are alike, the ALU is selected for

Result +3
8
(correct)

A-B-1 operation (a straight A-B function is not possible). The -1 is compensated for by a carry insert
which puts +1 in the ALU bus along with the contents of the FMA. Actually, the ALU performs an
A-B-1+1 function which reduces to A-B. A represents the FMA, and B represents the FMB. The FMB
is subtracted from the FMA and the result is loaded into the FMA.

If the specified operation is an integer add and the signs are alike or an integer subtract and the signs
are unlike, the AlU is selected to perform an A+B f,mction which really adds the contents of the FMA
to the FMB and puts the results into the FMA.

If the two quantities are positive and added together, it is possible for an integer overflow to occur.

Example: Good Assumption (Integer Add)
A SIGN

B SIGN

QJ + I 0
~ 0

Good assumption (ADD 00 L)

This is detected as a carry out of the ALU (ADD 00 high). If this occurs, the FP15 goes into an inter-

(Do not 2's complement FMA)

rupt cycle.

(Do not complement A SIGN)

4-12

FMA

-2

8
ALU Performing
A+B Function

Result -3
(correct)
8

the EXP and FUN cycles, operation is similar since the subtrahend is in the FMA and the minuend is in

Example: Bad Assumption (Integer Subtract)
A SIGN

B SIGN

the FMB for both integer reverse subtraction and integer subtraction.

0
D

FMA

FMB -(+6 )
8

ALU Performing
A-B Function

35
However, the correct result can be computed by adding 2 to the existing contents of the FMA after
the interrupt. The A SIGN remains unchanged.
Example:

Result
(i ncorrect )

t
Bad assumption (ADD 00 H)

(2's complement FMA)
(Complement A SIGN)

Result -1
8
(correct)

4.8

A SIGN (0)

FMA 3000078

B SIGN (0)

FMB 07m7

A SIGN (1)

400006

Result left in FMA
35
Correct Result = 2 +

000006
000006

8
8
8

FLOATING-POINT AND INTEGER MULTIPLY

In order to multiply two numbers in floating-point format, the following basic functions are performed:
calculation of exponent, determination of the sign of the product, and multiplication of the mantissas.

Example: Good Assumption (Integer Subtract)
A SIGN

B SIGN

GJ
G

These are described in the following paragraphs.
0

[2J 0
t

FMA

-6
8

FMB -(+1 )

ALU Performing
A+B Function

4.8.1

Calculation of Exponents

During the EXP cycle, the contents of the EPA and EPB are gated into the ALU where the EPA is added
to the EPB (see Figure 4-5). The sum is strobed back into the EPA. In floating-point multiplication

-7
8

Good assumption (ADD 00 L)

operations, recall that the exponents are added while the mantissas are multiplied. In integer multiplication, there is no exponent calculation.

(Do not 2's complement FMA)
(Do not complement A SIGN)

4.8.2

Determining Sign of Product

The sign of the product is determined in the EXP cycle before the mantissas are multiplied. If the multiplier and multiplicand have the same sign, the sign of the product is positive. If the signs differ,
4.7.3

Overflow

the resultant sign of the product is negative. In either case, the resultant sign is strobed into the

35
If the addition or subtraction operation results in a magnitude greater than 2 -1, an overflow inter-

A SIGN. Negative integers are converted to sign and magnitude format; positive integers are already

rupt will occur. The result contained in the FMA, after the overflow, is no longer the correct result.

in sign and magnitude format.

4.8.3
4.7.4 Integer Reverse Subtraction

Multiplication of the Mantissas

The mantissas are multiplied by a series of additions and right-shifts of the FMA during the FUN cycle.

Integer reverse subtraction and integer subtraction are similar to each other except for the fact that, in

Before the actual multipli cation occurs, however, the shift counter is preloaded with a constant of

integer reverse subtraction, the contents of the FMA are transferred to the FMB during the FETCH cycle

428 (34

and the FMA is loaded with the subtrahend when the integer reverse subtraction is specified. During

), the contents of the FMA are transferred to the FMQ, and the FMA is then cleared. The
10
rules for multiplication of the mantissas are:

4-13

Test the least significant bit of the FMQ.

EXP CYCLE
NOTE·

If FMQ 35 is a 1, add the contents of the FMB to the contents of the
FMA and shift and load the FMA and shift the FMQ right as one 70-bit
register.

If FMQ 35 is a 0, do not load the FMA with A+B, but merely shift the
FMA and FMQ right.

No EXP cycle for Integer Multiply.

Decrement the shi ft counter and test for a borrow.
a.

If a borrow is detected, the multiplication is complete.

If no borrow is detected, repeat the fj rst step.

After a borrow has been detected, the multiplication is complete if it is a floatingpoint multiply. If it is an integer multiply, the contents of the FMA and FMQ are
swapped and the multiplication is complete.

Figure 4-4 shows a simplified flow diagram of the above rules. For floating-point multiplication, the
most significant bits of the product are retained in the FMA. For integer multiplication, as a result of

FUN CYCLE

NOTE:
Shift counter loaded
with 3410_ However,
3510 counts will occur
before borrow is produced. L..----r--~
DONE

the swap, however, the most significant bits of the product are retained in the FMQ.

NOTE:
Floating point multiplymost significant bits-FMA

4.8.4

Multiply Algorithm

Integer multiplymost significonl bils-FMQ

In order to depict the multiply algorithm, Figure 4-5 Shows a simplified example where the number 5
(101 ) is to be multiplied by the number 4 (100 ), EPA and EPB are both equal to 3, so in the final
2
2
product, the binary number will be shifted six places to the right. Initially, the shift counter is
loaded with 2, the FMA is transferred to the FMQ, and the FMA is cleared.
NOTE
The shift counter is loaded with one less than the number of stages in the FMQ. Since the example uses a
three-stage FMQ, a count of 2 is pre loaded into the
shift counter. In the case of the FP15, the shift counter is loaded. with 428 (34 10), actually 3510 shifts may
occur before a borrow is produced.

In the first step, the least significant bit of the FMQ is tested. Since it is a 1, the contents of the
YES

FMB are added to the contents of the FMA and the entire FMA and FMQ are shifted right as one 6-bit
register. Each time a shift occurs, the shift counter is decremented. The shift counter now contains a
count of 1 •
In Step 2, the least significant bit of the FMQ is tested again. Since it is a a in this case, the FMA
and FMQ are merely shifted right. The shift counter is again decremented (this time to 00).

4-14

1~-Q58'

Figure 4-4

Multiply Simplified Flow Diagram

Initial Conditions:

410 x
EPA
EPB
FMB

In Step 3, the least significant bit of the FMQ is tested again and is a 1. Consequently, the contents

x 1012 = ?

1002

of the FMB are added to the contents of the FMA and the FMA and FMQ are shifted right. The shift

510 = 20 10

counter is again decremented to 11, indicating a borrow condition. This signi fies that the multiplica-

3
= 100
FMA = 101
FMQ = 000

tion is complete and the product is .010100 x 26. This number is 010100. in binary after the binary

After Swap

If this were an integer multiply, the FMA and FMQ would be swapped. In the example presented, a 1

FMA = 000
FMQ = 101

is contained in the FMQ after the swap. For integer multiply, any 1 contained in the FMQ after the

point has been shifted six places to the right.

swap results in an overflow interrupt. Therefore, a product up to a maximum of 35 bits in length
After Swap
FMA = 000
FMQ = 101

Step 1

Test least significant bit
(LSB of FMQ)
If 1, add FMB to FMA

FMA

and
Sh ift FMA and FMQ right

FMA

and
Decrement Shift Counter

(length of the FMA) is possible in the FP15 for integer Multiplication. Drawings D-FD-FP15-0-54 and

FMQ

FMA

D-FD-FP15-0-55 represent flow diagrams of multiplication in the EXP and FUN cycles, respectively •

FMB

I I 0 I 0 I 1 I 0 I I FMQ

10'l,"GI'aI"~~MQ
I I 0 I Shift Counter
I0 I

Step 2
Test LSB of FMQ

FMA

I Shift Counter

I I I I I I I FMQ
0

~~~~~~

If 0, shift FMA and FMQ right

FMA

and

! 0 I 0 I 1 I 0 I 0 I 1 I FMQ

I I I Shift Counter

Decrement Shift Counter

I 0 I 0 I Sh ift Counter
Step 3

Test LSB of FMQ
If 1, add FMB to FMA

o
0

I I I I I I I
I
~~
0

and

0'1,'10'1,1:

Shift FMA and FMQ right
and

Decrement Shift Counter

o
SC Borrow

EPA + EPB = 3 + 3 = 6

Multiply Complete

6
Answer = .010100 x 2 = 10100 = 248 = 20
10
2

Figure 4-5

Multiply Algorithm
4-15

4.8.5 F!oating-Point Overflow

It is possible that this temporary underflow can be eliminated during the NOR cycle if rounding is re-

The following paragraphs describe the interrupt exceptions which can occur during floating-point mul-

quested. ihis is possibie only if the EPA just underfiowed, since rounding can oniy increment the EPA

tiplication. An overflow or underflow in the EXP cycle is temporary, since it can be removed by an

once and only if a carry was generated out of the ALU. If the underflow condition is not removed, an

underflow or overflow I respectively, in the FUN cycle.

underflow interrupt wi" occur at NOR *T 502.
In effect, two negative quantities are added with a result too small to be shown in the register. The

4.8.5. 1

Overflow Interrupt - EXP Cycle - A temporary overflow can occur if a positive EPB is added

to a positive EPA with a negative result. An example of this is:

change of sign in the EPA from negative to positive is detected as an underflow. The bit (EPA 00 going from a 1 to a 0) is preserved until the NOR cycle, where it is possible for rounding, if requested,
to eliminate the condition causing the interrupt.

377m8

EPA

EPA 00
.. (SIGN)
0.11
111

0000018

EPB

0.00

400000

= Result

111

4.8.5.3

000

001

set, and rounding is requested, 1 is added to the least significant bit of the FMA. If this operation

1.00
000
t.SIGN

000

produces a carry out of the most significant stage of the ALU, the FMA is right-shifted and the EPA is

Overflow Interrupt - NOR Cycle - At. NOR*TS02, the guard bit is examined. If the bit is

incremented. If the EPA contains 377m 8 before it is incremented, an overflow interrupt will occur

The overflow condition is detected as a result of the sign bit (EPAOO) going from 0 to 1.
It is possible that this temporary overflow can be eliminated during the NOR cycle if normalize is requested. Decrementing the EPA during normalize may reduce the number so that it can be contained in
the EPA. If so, the temporary overflow condition is eliminated. If the condition is not removed, an

and the interrupt cycle is initiated.
It is possible during rounding that incrementing the EPA will remove the condition causing the temporary underflow in the EXP cycle. If the condition is not removed, the interrupt flag is raised. For example, assume that the EPA contained 3m77S in the EXP cycle due to underflow and that a rounding
request was made. The rounding caused a carry out of the ALU that necessitated right-shifting the

overflow interrupt will occur at NOR*TS03.

FMA and incrementing the EPA. Incrementing the EPA to 400000 removed the temporary underflow.
4.8.5.2

Underflow Interrupt - EXP Cycle - A temporary underflow can occur if a negative EPB is
4.8.5.4

added to a negative EPA with a positive result. An example of this is:

Underflow Interrupt - NOR Cycle - If normalize is requested, it is performed during the

NOR cycle for floating-point multiplication. As the mantissa is being left-shifted, the EPA is being
decremented. During normalize, if the EPA should be decremented from 400000 to 377777, an under-

400000

EPA

EPA 00
(SIGN)
1.00
000

400000

EPB

1.00

000

1000000

Result

10.00
000
l.SIGN

000

4-16

flow interrupt wi II occur at NOR*TS03 and the interrupt cycle is initiated. This is detected as a re000

000

sult of EPA 00 going from 1 to a O.
It is possible during normalize that decrementing the EPA will remove the condition causing the tem-

porary overflow in the EXP cycle. If the condition is not removed, the interrupt flag is then raised.

8
T'I"

dr"w""

ill"ld spec,flc.ttons. h.~n. IIr. the prop-

to-tyo! DISltal EquipmentCorpor.r.onanc! sn,lIlIotbe

'tprodl.lc:ed or copted or uNCI In whole or '" part as
the bu" for the manlJf.ctul't or s.ale of Items without
.... ntten p'Tml~llon.

o
FP37

:t>,,(~)

EPA

¢1J (t;)
ADD 18

EPB

c
FP.,.3

1-+ UND SYNC.
SRVe UNDERFLOW
FOR pOs"rBLE lNTER.RU r IN NOR,

TO FVNCYCLE.

cYC.LE

FUN

FP38
MPY -r
ODD

DI V

SIGNS

/'-----.,

qLf)

I~
10

Q..

1"10

FPC

8LL
~Q

FUN

CYCLE

ITEM

DESCRIPTION

NO.

PARTS UST

FIRST USED ON OPTION

MODEL

DalEHSIOtIIN INCHES

TOlERANCES
DECI...... fMCTIONS
....OUS
;t: .005
:!;: 1/64
~ 0-30'
FINAL SUIIFACE QUAUTt
/
JIDIOV£ MJRftS AND .IM $tWtP

'"z
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b~~~~~~~~~nu~:---~-----gu----~-~-·~-~~~-~~~~··~~-~~~O_&T-~--lA
TITLE

I=:::-!"!~¥--~"-IF LOAT I r'<C
~Xp

CORNERS

MATERIAL

I
U

rv uL ~ J Iy'

CYCLE

SCALE

'"
I
U

DEC FORM NO
ORO 100

IID-DU-OEau

DO NOT SCALE DRAWING

UNLESS OTHERWISE SPECIFIED

SHEET

4-17

,.dteProp-l
II1I'I.
=!r!~'::~,:O~."ufKtl.lI'9 or . . . 0' itMna wrthout

ThISdfaw.n'andt.pICl1'tcabonl.~n . •

crty 01 Dille.: Equlpmen' Cor'JIQrati(lft and ..... 11 not be
feflr<ldUt"tod or co~ (If <Iud In
or in PoIrt as.

0
FP¢9
FUN

FP38

FP.33

FP.38

FP32.
FP~q.

FP33

FP39

FP38

FP.38

FP32

FP:32

FP.39

FP.32

FP,39
FP3<J

FP39

FP3'J

FP32

FP32.

, - - - - - - ' " - - - - - - , F P J0

TO NOR CYCLE
80RROW>-------------------~

IFIR5TU~EOONOP MOD

DESCRIPTION

PDPI5
>

UN E

II:

UNLESS OTHERWISE SPECIFIED
OfW(NSIOH I-N INC"tES

TOLERANCES
[)(CIMALS
~

.DD5

FRACTIONS
~ 11M

ANGLES
~

0-]0'

LOAT & INTEGER

FtE~OV~N:~R:,.~:OE 8~~~~~H£P
CORNERS

V1UL FU N CYCLE

MATERIAL

(

FINISH

4-18

ITEM
NO.

I
I

REV.

SCALE
SHEET

4.8.5.5

Integer Overflow - The only interrupt possible during integer multiply is an integer over-

flow. After the FMA and FMQ are swapped, the FMQ is examined. If the FMQ is not zero, an overflow interrupt occurs and the interrupt cycle is initiated.
NOR CYCLE

4.9

FLOATING-POINT DIVlSION

To perform floating-point division in the FP15, both the dividend and divisor must be normalized. The
dividend is normalized in the FUN cycle. The basic functions performed in the division process include calculation of exponents, determination of the sign of the quotient, and division of the mantissas. These are described in detail in the following paragraphs. Refer to Figure 4-6 which represents
a simplified flow diagram of floating-point division.

4.9. 1

DISABLE
SHIFT
COUNTER

Calculation of Exponents

During the EXP cycle, the contents of the EPA and EPB are gated onto the ALU where the EPB is subtracted from the EPA. The difference is loaded back into the EPA. In floating-point division, the
exponent associated with the divisor is subtracted from the exponent associated with the dividend.

4.9.2

Determining Sign of Quotient

The sign of the quotient is determined in the EXP cycle before the mantissas are divided. If the dividend and divisor have the same sign, the sign of the quotient is positive. If the signs are different,
the quotient is negative. In either case, the sign of the quotient is stored in A SIGN.

4.9.3

Division of the Mantissas

The dividend mantissa is divided by the divisor by a. series of subtractions and left-shifts of the FMA.

LEFT SHIFT
AND LOAD FMA
WITH RESULT
OF SUBTRACTION

This process is performed in the FUN cycle and can be reduced to the following rules:
1.

Normalize the dividend and divisor. If the divisor is not normalized, an abnormal
divide interrupt will occur. To keep track of the number of shifts as a result of
normalize, the shift counter is loaded with an octal count of 438 (3510). Each
shift decrements the counter and, on completion of normalize, the counter is disabled. If more than 35 shifts occur and the number is not normalized, the FMA is O.
15- 0582

Subtract the FMB from the FMA and test the sign of the difference (located in
ADD 00):
a.

Figure 4-6

Floating-Point Divide Simplified Flow Diagram

If the sign is positive,
• 'Shift a 1 into the least significant bit of the FMQ.
. Left-shift and load the FMA with the difference just obtained.
(continued on page 4-20)

4-19

{continued}
NOTE

Example: O. 111 ~ 0.101 = ?

(.875 ,0 ~ .625

If this is first subtraction, and a 0 sign is produced,
the EPA is incremented. This condition applies only
to the first subtraction.

b.
4.

I o· I

STEP 1

. Shift a 0 into the least significant bit of the FMQ.

Subtract FMB from FMA
Test sign
If 0, (a) increment EPA (only for first subtraction)
(b) shift 1 into LSB of FMQ
(c) left shift and load difference - FMA

Test whether the most significant bit of the FMQ is a 1.
a.

Exponent calculation and sign of result are determined in EXP cycle and are not shown here.

FMA
0.111
FMB
0.101
EPA
0
EPB
0
FMQ = 0

If the sign is negative,

Left-shift the FMA.
3.

NOTE

= 1. 4)

If the bit is 1, the division function is complete. Before this fact is detected, the FMA is left-shifted and loaded (if a negative sign) or leftshifted (if a positive sign) and should not have been. It is therefore necessary to shift the FMA right. Otherwise the bit shifted out of the MSB
of the FMA will be lost.
.
If the bit is 0, repeat Steps 2 and 3.

Swap the FMA and FMQ.
will contain the remainder.

10. 1

FMB

.1 0. I 0 I 1 I 0

SIGj/1 /

I o. I I 0 I 0 I

STEP 2
Subtract FMB from new FMA
Test sign
If 1, (a) shift 0 into LSB of FMA
(b) left shift FMA (no load)

- I o. I I I
til.l I I

__....---~.:.....
FMQ(. 11 10)

Difference

SIGN

FMA
Left-shi fted
FMA

Divide Algorithm

Drawings D-FD-FP15-0-54 and D-FD-FP15-0-57 are flow diagrams of the EXP and FUN cycles during

STEP 3

floating-point division. Figure 4-7 is an example of how the divide algorithm is implemented. The

Subtract FMB from FMA
Test sign
If 0, (0) shift 1 into LSB of FMQ
(b) left shift and load difference - FMA

FMB, respectively. According to the rules just described, the first step is to subtract the FMB from the

I 1. I 0 I 0

New FMA

SIGN

- I o.

FMB

rI ° I I I o:J:ew
io.

FMA, since both numbers are already normalized. The first subtraction produces a 0 sign which causes:

Difference

SIGN

* a.
b.
c.

New FMA

The FMA will now contain the quotient and the FMQ

number 0.111 2 (0.875 10 ) is divided by 0.101 2 (0.625 10 ), These numbers are loaded in the FMA and

Difference

___________ ~~(~~ 1)/-/- -/____ _

4.9.4

FMA

FMQ

the EPA to be incremented,
a 1 to be shifted into the FMQ, and
the result of the subtraction to be left-shifted and loaded into the FMA.

(.1 0

FMA

~ToJ>0 I FMAaf~,
right shift

(FMA-FMB) produces a sign of 1 which causes:
a.
b.

a 0 to be shifted into the FMQ, and
the FMA to be shifted left.

The most significant bit of the FMQ is still not a 1, so the process continues. The third subtraction
produces a 0 sign which causes:
a.
b.

4-20

a 1 to be shifted into the FMQ, and
the result of the subtraction to be left-shifted and loaded into the FMA.

FMQ

FMA

The most significant bit of the FMQ is not a 1, so the process continues. The second subtraction

-L.---.JI ,. . . ._0....L.--0~---'----I

.......0---.L1_1--r......'_0

FMB;FMQ after swap

NOTE
EPA was incremented due to 0 sign from first subtraction.
The binary point is thus relocated from. 101 to 1.01 or
2
1.2510' The true answer should be 1.4 but this number
cannot be represented with three binary bits. The closest answer without exceeding the true answer is 1.25 10 ,

--------------------* MSB of FMQ = 1 Division complete
Figure 4-7

Floating Point Divide Algorithm

This condition causes a 1 to appear in the most significant bit of the FMQ indicating the division is

4.9.S.2

complete. However, the FMA has been left-shifted and loaded with the result of the last subtraction.

subtracted from a negative EPA with a positive result. An example of this is:

Underflow Interrupt - EXP Cycle - An underflow interrupt can occur if a positive EPB is

This occurred before it was detected that the divide was complete. As a result, a bit was shifted out
477777

EPA

(EPA 00)
fSIGN
111
100

377777

EPB

011

111

000

111

110

of the MSB erroneously. Consequently, the FMA is right-shifted to restore the bit and then the contents of the FMA and FMQ are swapped. The FMA now contains the quotient and the FMQ contains
the remainder.

1 07m6
Since the EPA was incremented in the first step. the final answer of " 101 2 if the FMA is adjusted to
1.01 2 " This yields a decimal number of 1.2S, whereas the true answer should be 1.4. However, with
three bits it is impossible to represent 1.4 in binary form; the closest approximation to this number
without exceeding it is 1" 2S. Much greater accuracy is obtained in the FP1S which uses 36-bit man-

t. SIGN

111

In effect, two negative quantities are added with a result too small to be shown in the register. The
change of sign in the EPA from negative to positive is detected as an underflow. The sign bit (EPA 00
going from a 1 to a 0) is preserved until the NOR cycle where it is possible (if rounding is requested)

tissas.

to eliminate the condition causing the underflow. This is possible only if the EPA underflowed by 1
During the NOR cycle, several additional events happen (refer to Drawing D-FD-FP1S-0-S9). If the

since rounding only increments the EPA once and only if there was a carry generated out of the ALU.

MSB of the FMQ is a 1 after the FMA and FMQ are swapped, the guard bit is set r and rounding is re-

If the underflow condition is not removed, an underflow interrupt will occur at NOR*TS02.

quested, +1 is added to the least significant bit of the FMA. If the guard bit is 0, the FMA is checked
Overflow Interrupt - FUN Cycle -It is possible to get an overflow interrupt during the first

at NOR*TS02 to see if the FMA is O. This is done by selecting the ALU for A-B-1 operation, where A

4.9.S.3

represents the FMA, and B = 0 (by being disabled from the ALU). If A = B is true, FMA = O. In this

shift of the divide operation. If the first subtraction produced a 0 SIGN, the EPA is incremented. If

case, EPA/A SIGN is cleared. With the guard bit set, the zero check of the FMA is not performed.

the EPA contained 3777778 and is incremented to 400000 8 , an overflow interrupt will occur at
NOR*TS03.- This is detected as a result of the sign bit (EPA 00) going from a 0 to 1 condition.

4.9.S

Interrupts

4.9.S.4

Underflow Interrupt - FUN Cycle - If normalize is requested, it is performed during the

Five possible interrupt exceptions can occur during floating-point Division: EXP cycle overflow and

FUN cycle for floating-point Division. As the mantissa is left-shifted, the EPA is decremented. Dur-

underflow and FUN cycle overflow, underflow, and abnormal di vide. The conditions causing each

ing normalizer if the EPA should be decremented from 400000 to 377777, an underflow interrupt will

type are described below.

occur at NOR*TS03. This is detected as a result of EPA 00 going from a 1 to a O.

4.9.S.1

4.9 .S. S Abnormal Divide - FUN Cycle - If the most significant bit of the divisor (FMB) is not a 1,

Overflow Interrupt - EXP Cycle - An overflow interrupt can occur if a negative EPB is sub-

an abnormal divide interrupt is initiated indicating an unnormalized or 0 FMB. This interrupt is not

tracted from a positive EPA with a negative result. An example of this is:

delayed unti I NOR*TS03 as is the case with overflow and underflow interrupts. The interrupt is raised
3000028 = EPA
4000008

EPB

7000028 = Result

,SIGN
000
= 0.11

000

010

= 1.00

000

1.11

000

010

immediately at FUN*TS01.

4.10

FLOATING POINT REVERSE DIVIDE

In a Divide instruction, the dividend is loaded into the FMA by a Load instruction and the divisor is
The sign bit (EPA 00) going from 0 to 1 is preserved until the FUN cycle. If normalize is requested, it

loaded into the FMB by the Divide instruction. However, assume that as a result of some previous op-

is possible that decrementing the EPA during normalize will remove the overflow condition. If so, an

eration, a number which is to be used as a divisor is left in the FMA. In this case, a Reverse Divide

overflow interrupt will not occur. If the overflow condition is not removed, an overflow interrupt will

instruction can be issued that gates the divisor from the EPA/A SIGN;1=MA to the EPB/B SIGN/FMB

occur at NOR*TS03.

during the FETCH cycle and loads the dividend into the EPA/A SIGN;1=MA.

4-21

iNiEGER DiVISION

4.11

4.11.2

FUN Cycle

Integer division in the FP15 is accomplished during the EXP and FUN cycles. The most significant bits

In the FUN cycle, the actual division process consists of a series of subtractions which, depending on

of the dividend and divisor must be 15 (normalized) before the actual division can be performed. Be-

the sign of the difference, cause the FMA to be (l) left-shifted or (2) left-shifted and loaded with the

cause of the integer divide algorithm, the dividend must be larger than the divisor for integer division;

difference just obtained. Again, depending on the sign, FMQ 35 is set temporarily storing the quo-

otherwise, the quotient is fractional and the FMA is ultimately zeroed.

tient. The algorithm can be reduced to the fol lowing set of rules:

The dividend is loaded into the A SIGN/FMA as a result of the Load instruction; the divisor is loaded
into the B SIGNj1=MB as a result of the Integer Divide (IDV or EDV) instruction. If the divisor is

Load the shift counter with the value of the EPA obtained during the EXP cycle.

Clear the FMQ.

Subtract the FMB from the FMA.

negative, it is converted to sign and magnitude format.
1.
4.11.1

EXPCycle

If the sign of the difference (AD 00) is positive:
· Transfer 1 to the LSB of the FMQ

Normalization of the dividend and divisor is performed in the EXP cycle. The FMA contains the divi-

· Left-shift and load the FMA with the difference obtained

dend and the FMB contains the divisor; the contents of the FMB are then transferred to the FMQ.

· Increment the EPA, if this is the first subtraction. This increment of the
EPA is performed merely as a matter of routine for integer divide, and is
primarily used for floating-point Division.

If the most significant bits of the FMA and FMQ are ls, nothing further occurs during the EXP cycle
2.

except that the contents of the FMQ are transferred back to the FMB. Three other possible conditions

If the sign is negative:
· Transfer a 0 to the LSB of the FMQ

that can occur are:

· Left-shift the FMA
a.

If the MSB of the FMA is a 1 and the MSB of the FMQ is not a 1, the FMQ is shifted
left. Each left-sh ift causes the EPA to be incremented. The process is terminated
when the MSB of the FMQ becomes a 1.

Example:

o
b.
c.

FMQ

FMA

EPA

o
o

If the MSB of the FMQ is a 1 and the MSB of the FMA is not a 1 the FMA will be
cleared since the divisor is larger than the dividend. No integer divide will occur.
If neither the MSB of the FMA nor FMQ is a 1 both are shifted left. If the MSB of
the FMQ becomes a 1 before the MSB of the FMA, this relates back to Step 2 and
no integer divide can occur. If the MSB of the FMA becomes a 1 before the FMQ,
the FMQ will continue to be shifted left; however, the EPA is incremented for each
left-shift of the FMQ not accompanied by a left-shift of the FMA.
When both the MSB of the FMA and FMQ are 1s, the contents of the FMQ are transferred back to the FMB and the EXP cycle is concluded.

4-22

4.11.3

If the division is integer, decrement the shift counter and check for a borrow.
1•

I f no borrow occurs, go back to Step 3 and repeat the process.

If a borrow is generated, the divide function is completed. However, the last
left-shift or left-shift and load was performed before the borrow was detected;
this causes the MSB to be shifted out of the FMA and an erroneous remainder
would resu!t. The FMA is shifted right to correct the condition.

Swap the contents of the FMA and FMQ. The quotient is now in the FMA and the
remainder in the FMQ.

Divide Algorithm

Drawing D-FD-FP15-0-56 is a flow diagram of integer divide during the EXP cycle and Drawing
D-FD-FP15-0-57 show~ the flow during the FUN cycle. A better understanding of integer divide can
be obtained by reviewing the rules just described using the flow diagram for reference. An example
of integer divide using two 3-bit numbers is shown in Figure 4-8. For clarity, only those registers
that change as a result of a particular action are shown.

Tt'li. dr.wln, and 19KificIItioM. MrWn.•re the prop.
.tty 01 0IQfbI1 Eqt.1IDmtnt Cotpcntion _
""11 not be
ntpCOduoIdorcopillclorUMdin . . . . orinPllrt ••
ttl. Mild for aM m.nutKtu.. or .... or ....... wiIhOUt

EXP B

wn""n potrmlMion.

FP39
r----.:I<~--...., FP3¢

r------'~---- FP3f

FP3J

FP4-3
FP.:39
FP.32.

FP34

FP54

FP3e

FPj9

FP33

':P33

FP43

St:=7Z:cRO
TOP St'{ZFTING
ANSWER ~ ZERO

FP34
FP.3e

FP.34FP!J2.

T51/J2

T5¢Z

FFj4

FP34

FP39

FP33

FP.33

FP3fj

FP43
FP.39
~

10
iii I
~(S.>
Z I
~

TO FUN CYCLE

FP34

FP.34

a...

FPJ9

FP32

FP38

:!:

FP32

8LL
~O

FP3e
FPtf>9

ITEM
NO.

DESCRIPTION

UNLE S THERWI E SPECIFIED
UNLESS OTHERWISE SPECIFIED t,;;.~=:.==--+.;,~~

TO FUNCYCLE

DIMENSION IN INCHES

TOLERANCES
OfelMALS

:: .005

o
z

fRACTIONS
=: 1/64

ANGLES

INTEGE R DrVI DE
EX? CYCLE

=. 0·30'

AEMO~N:;A:R~:£ .~~~ip
CORNERS

MATERIAL

/
AN ISH

'"r

DEC FORM NO

SCALE
SHEET

4-23

Th'$ ml.,nl lnO spocritcdlonS. MIreuI. Ire the prop
ertyo' Chcltlil EquipmentCorl)Ofl110n Inc! $haIll'IOtbe
reproduced or copw:<l tiT used in whole or In part.s
theb.a$"jorthemanu'acturtlor~oilt.rn,wttiwui

wnnen perrmSSlOn

r-----'~----, f:P38

,----:-"'-::-----, FPJ8

.----~~--...., FP32

MX,q;

FMA It.
FMQ ARE
SHIFTED LEFT

o
. - -_ _---'L--_ _- - , F P3

9 . - - - - - - > " - - - - - - , FP3fP

.--_ _.....JI~_ ___, FP3¢ L -_ _ _, - -_ _- - '

FF43

, - - - - ' - - - - - - , ,"'P4-3

FUN-TI' P2
'-Ol/OSC

FP39
r - - - - - - - , - - - , FP 43

. - - - - - ' - - - - , F F /I

. - - - - - ' - - - - - , F PI/

r------'~-----,FPJ9

,-------''------, F P 4 3

, - - - - - - - - - - - , FP43

. - - - - - ' - - - - , F P II

, - -_ _- - - ' L -_ _- - ,

FP:J8

r------'''-----,FP32
TO INTERRUPT
FLOW
r---~L-----, FP4S

t>-

" I

FPJ8

i11

\()

FP32

LL
:::0
8LL
~Q

FP:J9

FP39

FP32

B
FP3i!.

DESCRIPTION

ITEM
NO.

NLE

UNLESS OTHERWISE SPECIFIED
DlM1NSlON IN INCHES

TOlERANCES
DECIMALS
:- .00&

ntACTtorIS
::: 1/64

ANGlES

&, I \jTEC~~
FUN Sye LE

;:; Q"3O'

ItE. .cr:":':R::[ .=~H'P

CQRNfRS

MATERiAl
(

}

FINISH
DEC tOR~ NO
DQD !02A

4-24

,
(

;

4.11.4

Interrupt Exception - Abnormal Divide

The only interrupt that can occur as a result of performing integer division is abnormal divide. AbEXP CYCLE
FMQ

EPA
0

FMB .. FMQ
Shift FMQ left
Increment EPA

normal divide occurs if the most significant bit of the FMB is 0 (FMB 01=0). The abnormal divide in-

FMB

FMA
0

terrupt flag is raised immediately at FUN*TS01.
0

0
4.12

In a Divide instruction the dividend is loaded into the FMA with a Load instruction and the divisor is

INTEGER REVERSE DIVISION

loaded into the FMB by a Divide instruction. If, as a result of some previous computation, the pro0

FMQ .. FMB

posed divisor is in the FMA, a Reverse Divide instruction can be issued. This instruction causes the
divisor to be gated from the FMA to the FMB during the FETCH cycle and causes the dividend to be
loaded into the FMB.

FUN CYCLE
FMQ

SC
EPA .. SC
0- FMQ

Increment EPA
1 .. FMQ
Left shift and load FMA with
difference
Decrement SC

1 .. FMQ
Left shift and load FMA with
difference
Decrement SC
Right shift FMA

/I
I
I0

I-

0
0

II
I

4.13

INTEGER STORE

For single-precision Integer Store instructions, A SIGN and bits 19 through 35 of the FMA are stored
in 2 1s complement format at the argument address (refer to Drawing D-FD-FP15-0-58). For extended

integer Store, A SIGN and bits 01 through 35 of the FMA are stored in 2 1s complement format in two
locations starting at the argument address. If the result of an arithmetic operation resulted in a nega-

II
I

FMB

FMA

tive answer, the answer is converted to 2 1s complement format prior to being written into memory.
Twols complementing is accomplished by lis complementing the negative answer in FUN*TS02 and incrementing this value in NOR*TS01. No operands are fetched from memory during a Store instruction.

4.13. 1

Overflow Interrupt

If any of the high-order bits (bits 00-18) are a 1 during a single Integer Store, an overflow interrupt is

initiated at FUN*TS01. No interrupts are possible with double Integer Store instructions.
0

Swap FMA and FMQ

Remainder

•

4.14

I I

FLOATING-POINT STORE

Quoti ent

= 011 2

For single-precision floating':'point Store instructions, the first word is stored in 2 1s complement format
3

at the argument address and consists of bits 09 through 17 of the EPA register and bits 18 through 26 of
the FMA. The second word consists of A SIGN and bits 01 through 17 of the FMA and is stored in the

Figure 4-8

Integer Divide Algorithm

argument address plus one. For double-precision floating-point instructions, the first word is stored in
the argument address and consists of bits 00 through 17 in the EPA register. The second word is stored
in the argument address plus one and consists of A SIGN and bits 01 through 17 of the FMA. The third
word is stored in the argument address plus two and consists of bits 18 through 35 of the FMA.
Floating-point Store instructions require no fetch from memory.

4-25

Normalize, if requested, occurs at FUN*TS01 and rounding, jf requested, OCCUiS at NOR*TS01.
Rounding of double-precision floating-point Store instructions cannot be specified. If rounding is requested for a single-precision floating-point Store instruction, bit 27 of the FMA is examined. If it is
a 1, 1 is added to the FMA, bit 26. If bit 27 is a 0, no rounding occurs. Bits 27 through 35 are then

4.15

SWAP, LOAD AND SWAP

The Swap instruction swaps the contents of the FMA and the FMQ. I f the instruction is a load and
Swap, the operand from memory is loaded into the FMA and then the contents of the FMA and FMQ
are swapped.

zeroed. The following interrupt exceptions can occur during a single-precision floating-point Store
instruction. The only interrupt exception that can occur during a double-precision floating-point

Drawing D-FD-FP15-0-60 is a flow diagram of the Swap instruction. The swap occurs at

Store instruction is an underflow interrupt due to normalize, which occurs at NOR*TS03.

FUN*TS01 *PH03. The contents of the FMQ are gated to the A side of the ALU bus, and the contents
of the FMA are gated into the FMQ. The A side of the ALU bus is enabled through the ALU by de-

4.14. 1

EPA Underflow or Overflow Interrupt

fault (nothing specified), and the ALU output is strobed into the FMA completing the swap.

During a single-precision floating-point Store instruction, either an EPA overflow or EPA underflow
interrupt can occur at NOR*TS02*PH03. If the EPA is positive, the high-order bits (bits 01 through

4. 15. 1

Underflow Interrupt

08) of the EPA are checked. A 1 in any of these bit positions initiates a temporary overflow. If the

If, as a result of normalize, the EPA is decremented from 400000 to 377777 , an underflow interrupt

EPA is negative, then the high-order bits of the EPA are checked for Os. A 0 in anyone of these bit

will occur and the interrupt cycle is initiated.

positions initiates a temporary underflow.
4.16
4.14.2

Underflow Interrupt Due to Normalize

If normalize is requested, the FMA is left-shifted and the EPA is decremented. If the EPA contains

FLOAT, LOAD AND FLOAT FMA

The two basic types of Float instructions are:
a
b.
0

400000 and is decremented to 377777 , an underflow interrupt occurs at NOR*TS03. It is possible
8
8
that the condition causing the EPA overflow interrupt at NOR*TS03*PH03 is eliminated when the EPA
is decremented during normalize. If so, no interrupt is raised. If not, the temporary EPA overflow
interrupt becomes permanent and is raised at NOR*TS03. The normalize underflow interrupt can occur
for both single- and double-precision floating-point Store instructions.

Load and Float FMA, and
Float FMA

The Float class of instructions convert integer format to floating-point format. The Load and Float instructions require a memory reference cycle(s) to fetch an operand(s) from memory. The Float FMA instruction merely floats the existing contents of the FMA with no operand fetch involved. Floating an
integer is accomplished simply by loading the EPA with 43 , which effectively relocates the binary
8
point to the left of the number. The integer is thus converted to a floating-point number--the mantissa

4.14.3

Overflow Interrupt Due to Rounding

is contained in the FMA and the exponent of 35

If rounding is requested, for a single-precision floating-point Store instruction, FMA bit 27 is ex-

is contained in the EPA. The following example
10
shows the integer 58 being converted to a floating-point number. The EPA is loaded with 3 since a

amined. If it is a 1, 1 is added to FMA bit 26. Should a carry occur out of the ALU as a result of

3-bit integer and 3-bit EPA and FMA have been shown for simplicity.

this operation, the FMA is right-shifted and the EPA is incremented. If the EPA contained 0003778
and is incremented to 000400 , an overflow interrupt is raised at NOR*TS03.
8

EPA=~

FMA =

0.101

= 0.101

x 2

= 58

It is possible that the condition causing the EPA underflow interrupt at NOR*TS02*PH03 can be elimi-

Drawing D-FD-FP15-0-60 is a flow diagram of the Float instruction. If a Float instruction is specified,

nated if the EPA is incremented during a rounding request. This condition can occur only if the EPA

a signal called FLOAT SELECT is generated at FUN*TS01. At FUN*TS01*PH03, a Float Select P sig-

just underflowed as the EPA can only be incremented once due to rounding.

nal causes the EPA to be loaded from the ALU bus with a constant of 43

4-26

(35

).
10

~.-

-- -

.- -

-- -

I
FLOAT

FM A

SWAP

,c,ND

FMQ

[FP31

\FPI2 FUN

IFPI2. FiJN ~ TI

irP31

SWAP

*- TI r

IFP41

FLOAT

FLOAT SEl

IPP41 SWAP

/FP¢q

IFP41 FIX +FLOFjT

PH (t 3

IFP41 FLOATSfLB

4 3 13

,0I

5J:L

A Lv..

J
IFP.33 B TO A l.u.

IFP32 EPA

IFP.,., SWrlP M~

c
1

I
I IFPn MI..S I

.------L.I--,
IFP.32

ALS

,---

IFP32. MXB1 [FP33 AURI

PI
If<. 1 "

I
I
I

FMPt _

FMQ. J MXBI,

SIGN
POS
(¢)
IR. 17 (j)

IFP/3. IRI7

,q SIGN CONTROL

(I~

I
NILS

F M Q --.. A S I DE OF ADDER; A l.I fl
FMGI,_IlDD£R OI)TPUT BY DEFAULT

ADDcR.... FMA BY DFFflIJL7" ~ filS

eLK

Pl.ILSE

I
[FP32 A 5JGN-I'~

COMP

IF< II<:. (I)

ASIGN
IF< I f (I ')

FPI2 FUN

rFPI3

fPI3 IRf(,,(')-/-.TR 17 (I)

IFP3:2.

pPTS

FP/2

FUN

T'3

"* p~ J

IFP32

FPTB

ZRII.

(I)

\FPI3 IR '" (I)

~
<.0

* T.3J

YP/3 IR f"7 (~)

FPI:2. FUN lJE'1:a*~

FP3B.

I eLK

eLK

PULS,E

PULSE
PI7TA

[FP.32. AS/GN+ J

I
B

YE~

I A S I GN-t- ¢ J
FP3c:
FIRST USED ON OPTIONIMODEL

QTvj

DESCRIPTION

NO.
l iTEM

PART NO.

PARTS LIST

'-r>
cr

I-

A
z

t'J
Z

~ '"
:I:

!DEC ~ORM NC

DRO IOZ-B

MATERIAL

NEXT HIGHER ASSV.

FINISH

SCALE
SHEET

SI;l~;'
NUMBER
DFDFPI5-2) OF

DIST.,

I I , , I I

~I REV.

Oe
I

4-27

In order to load the constant into the EPA, it is first specified at the input to the B multiplexer by a

of the FUN cycle. At this time: the FMA and FMQ right-shifting process is initiated. Shifting is

FIX or FLOAT SEL signal. An AUA1 signal enables the 43 to the output of the ALU. This is accom8
plished by forcing SO and S2 low and Sl, S3 and MODE high.

accomplished by the FIX SHMA P signal that is generated for each shift.
The shift counter is incremented each time a shjft occurs. The counter is tested after each shift to see
if a carry is generated. If not, the FMA and FMQ are shifted until a carry is generated. At this

4.17

FIX, LOAD AND AX

point, the FMA and FMQ have been shifted the required number of places to fix the floating-point

The Fix or Load and Fix instructions convert floating-point format to integer format. If the instruction

number. The operation is concluded by "resettingll the logic on FP09 to allow continuation of the

is a Fix, no memory reference is required. An example of this is the FIX EPA (FMA) instruction that

phase and ti me states.

converts the existing contents of the FMA to integer format. If the instruction is a Load and Fix, a
memory reference is required to load the FMA with the operand from memory.

4.18

LOAD JEA AND STORE JEA

The Load JEA instruction loads the JEA register (bits 07-17) from bits 21-35 of the BMB. The guard
Drawing D-FD-FP15-0-61 is a flow diagram for the Fix type instruction. The diagram is divided into

bit is loaded from BMB 19.

two major branches--one for a positive EPA and one for a negative EPA. If the EPA contains a negative number, the floating-point number is a fraction that cannot be converted to an integer and the

The JEA register is loaded by a LD JMS P signal that occurs during FUN*TS01.

FMA is cleared.
The Store JEA instruction occurs during the WRITE cycle where the operand is written into memory
NOTE
At FUN*TS01, FIX ZERO is generated if the EPA is negtive. This signal forces a logical zero on the ALU bus
and at Phase 2, a FIX ZERO P signal strobes the ALU
output (zero) to the FMA resulting in a zero FMA.

If the EPA is positive, the floating-point number can be converted to an integer and the Fix operation
is initiated. The ALU is selected for A-B-1 operation during the FUN cycle. IIA II represents the
EPA, and IIB" represents a special constant that is 35

for a Fix instruction. At this point a test is
10
made to determine if the EPA is equal to 43 , If so, the Fix operation is completed, If not, 43 is
8
8
subtracted from the EPA and the difference is loaded into the shift counter from the ALU bus. If the
difference is positive (EPA 43 ), the number cannot be fixed since 35 or more shifts would shift the
10
8
number completely out of the FMA; in this case, a Fix Overflow is generated and the Fix operation
ceases. An interrupt sequence is initiated due to the overflow resulting from EPA 43 , The interrupt
8
sequence consists of INT 1 and INT 2 cycles that lead to a service routine in the CPU associated with
the overflow. The interrupt sequence is described more fully in Chapter 3,

(see Paragraph 2.10). JEA bits 03-17 are gated to MPO bits 03-17, and the A SIGN and guard bits
are gated to MPO bits 00 and 01, respectively.

4.19

BRANCH

The Branch instruction provides the programmer with a means of altering the program sequence. Bits
13-17 of the instruction word are used as a mask to test for certain conditions such as zero or non-zero
FMA, positive or negative A SIGN, and FMA carry. Figure 4-9 is a simplified flow diagram of the
instruction. As an example, assume the programmer wishes to test for FMA = 0 and to branch if it is.
The test mask would have bit 17 on a 1 to test the FMA. If the FMA is 0 and a Branch instruction has
been specified, the Branch test is successful. If indirection has been specified, the indirect cycle
must be completed. This is indicated by CHANGE H which occurs when no indirection is specified or
when indirection is specified and has been completed. The FP15 enters an INT 1 cycle that forces the
CPU to begin execution of a JMP*O instruction. The INT 2 cycle is initiated and the FP15 forces the
CPU to accept the contents of the address register that contains the address specified by the Branch instruction. If the Branch is not successful, the instruction is exited, and is cleared at the end of

If the difference between the EPA and 43 is negative, the operand can be converted from floating8
point to integer and the Fix operation proceeds. The shift counter is loaded with the negative quantity that results from EPA-43 (where EPA < 43 ), Logic on FP09 causes the FP15 to stop in TS02*PH03
8
8

4-28

FETCH*TS03*PH03. Indirection, if specified, must be completed before BUSY is cleared. The INT 2
cycle is completed at INT 2*TS03*PH03 to complete the instruction. The Branch instruction can be
microprogrammed on an inclusive OR basis.

8
."w..........,'"......: ....".

Th"
an tho .....:
.rry 0/ OI&.t.1 EQUJ~ Corpomion Ind ..,.11 not be
reproduc.cl or c:o~JId or u.sed 1ft whole or In part "'
tt.. DI'II for tht m.nuf.:tu,. or .... Of iIIIm. wtttw:ut
written pemuqlon.

I I

!
D

IFPllrUN(I)H

I I,," I 19:.~N- 9 Id Jrg~3~J 2 I

FIX

FMA

FPSI

FIX

!
D
YEi;i;

EPA NeG?

P41

r FIX

I rP4/ FIX SEL 1
-

Z!ERO

b '''-1''

I FP3f?
/9 LS
I
L D S F'"MA WITH

! FIX Z! E R

I AUA

AUB

P-P33

EP,t:? - 4~B IS NOT
NcGr:JTIVe

-nDD 18

IFP 4.3

I FP 4-3

F-IX OVA'

OVIT

I I='P <;L3 INr

eN ¢ ¢ L

A- 8 - I

+- FLOAT ,sELl
! FIX t='"P+1

A U

C;~t;

PH0:;:1 (/) '"
FP~9

l~ ..".,

FP31 A =B H

;~e:

(!)

! c '- R

;:-.P~O

1-9

FPq.3

IrP-+1 F'JX 5H M A

FP~t1J INoR* T~e:* GU/7RD (cP)!

IFP"'f1 r/X COUNT-I!

A I, R(.I8119

FP3'3

P:~~(I)

!
FPI7

EPA

l ¢ ...,. /? SIGN

r ~ ~ EP/9

!..-

! rP~' FIX P

--~L(j !

43 8

F' FP41!

r l 0 GIC,qt, (2J
EP;t:i

%!.t:ROS

I--~

LrDp :;:IS¢C

..sET H

F"P1Z'9

SHIFT COVNTcR t,0190
WIT/-! &.P~ - <:f3a

ll ...

I Fps8 MM c.
!

ST FHA!::>£:

FP09

l-..t"--[

FPC

f---

FPSa. AMC.

tC
e I

HFPC

/PIx.. SHMA P I

-0....

F,.,.,.'

m
LL

1
,

;9;'f'S
/V1;'f'S
UP COV/vT TNe

IOOC C.;RR >'

",0

f.2--

Y€.s

I< SET

S YIVC.

rF'~9

ICZl- 57FFeJ9
PHASE

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FIRST USED ON OPTION/MODEL

DESCRIPTION

QTv·1

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DIMENSION IN INCHES.

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4-29

4.20
DO NOT BRANCH
CLEAR BUSY AT
FETCH * T3 * P3

YES

MODIFY FMA

The class of instructions used to modify the FMA are:
a.
b.
c.
d.
e.

FP31 BRANCH

Zero EPA (A SIGN) FMA
Normalize EPA (A SIGN) FMA
Make A SIGN positive
Make A SIGN negative
Complement A SIGN

The flow diagram for control of A SIGN is shown in Drawing D-FD-FP15-O-58. This diagram is applicable to making the A SIGN positive or negative, or complementing the A SIGN. If IR16 and IR17

FORCE CPU
TO BEGIN
EXECUTING
JMP*O

of the instruction word are a 0 and 1, respectively, the A SIGN becomes 0 (positive) at

FP32 FMA" 0

FUN*TS03*PH03. If IR16 is a 1 and IR17 is a 0, the A SIGN becomes a 1. If both IR16 and IR17 are

FP13 IRI7 (1)

ls, the A SIGN is examined and complemented at FUN*TS03*PH03.

FP32 NEGATIVE ASIGN

4.20.1

FP13 IRI6 (I)

FP32 POSITIVE ASIGN
FP13 IRIS (I)

Underflow Interrupt Due to Normalization

The only possible interrupt for this class of instructions is an underflow interrupt as a result of normalize EPA/A SIGN./FMA. If the exponent of the result is less than 400000 (_2 '7 ), an underflow inter8
rupt occurs since the resultant exponent cannot be correctly represented in the EPA.

FORCE CPU
TO ACCEPT
CONTENTS OF
FPI5 AR

FP32 NON ZERO Frv:A
FP13 IRI4 (1)

4.21

DIAGNOSTIC INSTRUCTIONS

FP40 GUARD" I

The FPl5 maintenance mode provides the user with the capability of sequencing through any floating-

FP13 IR13 (1)

point instruction step by step. Each instruction contains a number of steps determined by the format I
type of instruction, and operand values. One step is counted at each of the following times.
FETCH * TS03 * PH03
FETCH * TS03 * PH03
OPAND * TS03 * PH03
OPAND * TS03 * PH03
OPAND * TS03 * PH03
EXP
* TSOl * PH03
EXP
* TS02 * PH03

'~·O~83

Figure 4-9

Branch Instruction Flow Diagram

EXP
FUN
FUN

* TS03 * PH03
* TS01 * PH03
* TS02 * PH03

FUN
NOR

* TS03 * PH03
* TSOl * PH03

NOR
NOR

* TS02 * PH 03
* TS03 * PH03

(if indirection)
(if not immediate)
Depends on data format
}

(1, 2, or 3 words)

(FMA and FMB aligned - 1 step count for every
align shift.)

(FMA and FMB are multiplied or divided here-1 step count per shift. FMA also fixed here-1 step count per every fix shift.)
(FMA normalized here--l step count per every
normalize shift.)

(continued on page 4-31)
4-30

WRITE
WRITE
WRITE

* TS03 * PH03
* TS03 * PH03
* TS03 * PH03

(i f a Store type)
(i f a Store type)
(i f a Store type)

}

Depends on data format
(1, 2, or 3 words)

strobed into the FP15 address register. The FP15 executed instruction stops in TS03*PH03 of the
FETCH cycle. When the dummy cycle is complete and stop clock is present, the signals that were previously inhibiting the CPU are cleared and control is returned to the CPU. At this time, BUSY is a 1,

For example, if a single-precision floating-point Add instruction was specified, a step is counted at
the following times:

the instruction has stopped executing at TS03*PH03 of the FETCH cycle, stop clock is present, and
maintenance mode is enabled.

No. of Steps
FETCH * TS03 * PH03
OPAND * TS03 * PH03
OPAND * TS03 * PH03
EXP
* TSOl * PH03
EXP
* TS02 * PH03
EXP
* TS03 * PH03
FUN
* TS01 * PH03
FUN
* TS02 * PH03
FUN
* TS03 * PH03
NOR
* TS01 * PH03
NOR
* TS02 * PH03
NOR
* TS03 * PH03

The next floating-point instruction fetched from core should logically be a maintenance instruction,
such as a Diagnosti c Read or Diagnostic Step and Read. Since BUSY is a 1, any floating-point in-

Two OPAND cycles

struction wi II be treated as a maintenance instruction. The instruction from core is now loaded into
(1 step count for every align shift)

1 to 35*

the DIR and the next word is loaded into the DAR. The CPU is again disabled by DIS CP RD RST and

1
1
1

waits in TS03*PH03 for the next RD RST to occur.

The CPU/memory reference cycle is completed, DIS CP RD RST is removed, the FP15 places a 710000

1 to 35*

1
1

In the preceding example, the number of steps ranges from 11 to 79 and, depending on how many align
shifts and normalize shifts, must be performed.
The FP15 maintenance mode is initiated by a DMN (Diagnostic Mode On) instruction. CPU instructions are handled in the normal manner and are not affected by the FP15 at this point.

NOP on the MDL, the CPU strobes the NOP in the MI register, and the memory cycle is completed.
Upon completion of the memory cycle, the FP15 goes into diagnostic operation.

4.21. 1

Diagnostic Read

If bit 11 in the DIR is a 0, the instruction in the DIR is interpreted as a Diagnostic Read instruction.
The FP15 instruction is only partially complete at this point; the contents of sixteen 18-bit words are
transferred one at a time from the FP15 to memory starting at the argument address. The words are
transferred in the f.ollowing order:

Drawings D-FD-FP15-0-63 and D-FD-FP15-0-64 are flow diagrams of the events occurring during
maintenance mode. The first floating-point instruction received after the FP15 is in maintenance
mode is handled in a manner similar to that described in the memory interface; in other words, the instruction is loaded into the CPU instruction register and the FP15 instruction register. The next word
(operand address) is loaded into the FP15 8MB; a dummy cycle is initiated to prevent the CPU from
sensing the operand address as an instruction. DIS RD RST prevents the CPU from accepting the operand address and the CPU is idle waiting for RD RST. The FP15 forces a 710000 NOP on the MDL; the
FP15 now simulates memory to complete the CPU/memory reference. The operand address is then

1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.

8MB 00-17 {Buffered Memory Buffer}
BMB 18-35
SC 12-17 and IR 06-17 (Shift Counter and Instruction Register)
EPA 00-17
A SIGN and FMA 01-17
FMA 18-35
EPB 00-17
B SIGN and FMB 01-17
FMB 18-35
B SIGN and FMQ 01-17
FMQ 18-35

* Depends on operand va lues.
4-31

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srop eLK 1 - - -....

RETURNS

CONTROL 70 C,P

W/7H t!JLlSY :; I, FETCH:: I
STOP eLK::: I J MlllNT MODE

=I
FIRST USED ON OPTIONIMOOEL

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BUSY

FIRST USED ON OPTIONIMODEL

QTY.

ITEM
NO.

DESCRIPTION
PARTS LIST

UNLESS OTHERWISE SPECIFIED
DIMENSION IN INCHES.

TOLERANCES

A
I

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4-33

12.
13.
14.
15.
16.

ADD 00-17 (ALU)
ADD 18-35
JEA 00-17 (JM5 Exit Address)
5T A 00-17 (see following Note)
AR 00-17 (Address Register)

indirection, the OPAND cycle is bypassed; if the instruction is integer, the EXP cycle is bypassed,
etc. The FP clock, which was halted at TS03*PH03, is restarted (see D-FD-FP15-O-64). At this
point, the flow sequences through a decision network that determines whether a step has occurred.
The FP15 is stopped if any of the following conditions occur:

A memory cycle is initiated for each transfer. Each time a word is transferred, the MPO counter is incremented.
NOTE
The 5T A 00-17 is a status word comprised of the following information:
5TA 00
STA 01
STA 02
STA 03
STA 04
STA 05
STA 06
STA 07
STA 08
STA 09
5TA 10
STA 11
STA 12-17

FP15 BUSY
FETCH CYCLE
OPAND CYCLE
EXP CYCLE
FUN CYCLE
NOR CYCLE
WRITE CYCLE
INT 1
INT2
TIME STATE 1
TIME STATE 2
TIME STATE 3
DIR 12-17

-EXC*T503*PH02

When FP15 is in TS03*PH02 and is not in the EXP I
NOR, or FUN cycle.

EXC*FPCA*PH02

When FP15 is in PH02, FP clock is present and an
EXP, NOR, or FUN cycle is specified.

ALIGN MA P

When FP15 is doing an alignment to align mantissas.

BR5

When the FMB is doing a right shift.

CARRY P

During each shift that occurs in a multiply or divide
operation.

INT DIVIDE P

During an integer divide operation.

SHMA P

When the FMA is being shifted during a Fix instruction.

NORM P

When a normalize operation is taking place.

For each of the preceeding steps that occurs, the DIR is decremented. The Diagnostic Step and Read
is initially loaded with a value 710100+0, where n is the desired number of steps. If the number of

The DAR is also incremented; thus, the sixteen 18-bit words are transferred to 16 sequential memory
locations starting at the argument address. When a count of 16 is reached, the MPO counter generates
a carry that sets TRANS EN. TRANS EN clears the FP15 and control is returned to the CPU for the

steps completed is less than n, -the logic determines whether the FP15 is at the end of the NOR, or
WRITE cycle, or in an interrupt sequence. If the FP15 is not in any of these states, the Diagnostic
Step and Read causes another step to be performed •

next instruction. The Diagnostic Read instruction may be executed indefinitely without affecting the
partially completed instruction.

If the FP15 is at the end of a NOR or WRITE cycle or in an interrupt sequence, and the instruction is
not completed (BUSY=1), the clock is stopped and the current contents of the registers are transferred
to memory. If the FP15 is at the end of a NOR or WRITE cycle or in an interrupt, and the instruc-

4.21.2

Diagnostic Step and Read

tion has been completed, the clock is not stopped and the current contents of the registers are trans-

If bit 11 of the word in the DIR is a 1, the instruction is handled as a Diagnostic Step and Read. The

ferred to memory. When the 16 words have been transferred, an MX CARRY is generated, the memory

instruction is sequenced through one or more steps and, depending on instruction type, format, and

cycle is completed, the FP15 cleared, and control is returned to the CPU for the next instruction. If

operand values, a new cycle may be entered. For example, if indirection is specified, the instruction

the FP15 instruction is not completed (BUSY=1), the point of entry is via the diagnostic instruction

is sequenced through another FETCH cycle; if a non-memory reference instruction is specified with no

path. If the instruction has been completed, (BUSY=O) the point of entry is through the initial path.

4-34

CHAPTER 5
INSTALLATION AND MAINTENANCE

5.1

INSTALLATION

The FP15 Floating-Point Processor is installed in the H963E Cabinet (Bay lR) of the PDP-15/20/30/40

7161NDICATOR
POWER SUPPLIES

{~ -----------I-FP15

Systems. This cabinet contains the PC15 and BA15 and may also include the BB15. When the FP15 is

- - -

FP15 LOGIC

- --

------------

included in a new system, it is completely installed and tested at the factory before the system is
shipped. The following paragraphs describe how to install, interconnect, and test an FP15 that is to

H721 POWER SUPPLY

be installed in an existing PDP-15 System. Table 5-1 summarizes the major components supplied as
H734B POWER SUPPLY

part of the FP15 Floating-Point Processor. A complete list is provided on drawing D-UA-FP15-0-0.
Figure 5-1 shows the general location of the major components installed in the H963E Cabinet.

BLANK

H721 POWER SUPPLY

Table 5-1
FP15 Floating-Point Processor Major Components

841-B POW ER CONTROL
BLANK

Quantity

Item

Part Number
REAR CABINET

1
1
1
1

FP 15 Wi red Assemb Iy
FP15 Indicator Panel
H721 Power Supply
716 Indicator Power Supply

D-AD-7007243-o-o
D-UA-7006331-0-0
H721
716

15-0568

Figure 5-1 H963E Cabinet (Bay 1R),
Rear View with Mounting Panel Door Open

5.1.1

Field Insta"ation Procedures
Step

Procedure
Remove the H950-P (5-1/4 in.) Cover Panel below the BB15 Indicator Panel. Install the FP15 Indicator Panel in this location.

NOTE

If the FP15 is to be installed in early PDP-15 Systems
with 783 Power Suppl ies mounted on the rear door of the
H963E cabinet, an H950-C 19-in. mounting panel door
will be included and substituted for the original rear
door of the H963E Cabinet.

REAR DOOR

Install the 716 Indicator Power Supply on the inside right wall of
the cabinet (as viewed from the rear). Mount the 716 directly below the existing 716 that provides power to the BB15 Indicator Panel.

Install the H721 Power Supply on the rear door of the cabinet directly above the existing 734D Variable Power Supply.

Locate the FP15 logic wired assembly directly above the H721 Power Supply on the rear door of the cabinet. Fasten securely to the
rear door with the mounting hardware supplied. Be sure to use the
spacers.
5-1

5.1.2

indicator Panel/power Supply Wiring

Table 5-2
Signal Cable Connections

Connect the FP15 Indicator Panel and associated 716 Indicator Power Supply as follows:
Procedure

Step

Connect black wire between the FP15 Indicator Panel ground tab
and the cabinet chassis ground.

5. 1.3

Connect orange wire between the +6.5V tab on the FP15 Indicator
Panel and the orange tab on the 716 Power Supply.

Connect both 716 Power Suppl ies to cabinet chassis ground.

Connect a red and white twisted pair between the AC tabs on the
716 Power Supplies.

H721 Power Supply Wiring

Connector Locations
Cable
Function

KP15

FP15

BB15

MM15A

OUT

Memory
Data lines

J02

H29

J29

B02

A02

B02

If BB15 does not contain KM15, KTl5, or
MP15, connect FP15J29 to MM15A-B03.

Memory
Control lines

J03

H30

J30

B03

A03

B03

Under conditions Iisted above, connect
FP15-J30 to MM15AB02.

API Control

H03

H31

J31

B05

This cable is not requi red to be connected to memory.

Procedure

Step

Connect the red and white twisted pair from the 841 B Power Control
to the H721 Power Supply ac input terminals (TB2-1 and 2). Refer
to D-CS-H721-0-1 for internal connections.

Connect a black wire from TB2-8 to cabinet chassis ground.

Disconnect the console power switch lead from the existing H721
Power Supply (TB2-6) and connect it to the added 721 Power Supply
at TB2-6. Connect a wire from TB2-6 on the original H721 to
TB2-7 on the added H721. These connections wi II connect both
H721 thermostat circuits in series with the console power switch.

Remarks

FP15 INDICATOR PANEL VIEWED FROM REAR

5.1.4

Signal Cable Connections

Table 5-2 is a signal cable connection chart that indicates how to connect the FP15 into an existing
PDP-15 System.
NOTE
The connections place the FP15 between the KP15 and
the BB15.
15-0585

When the system does not include certain BB15 options (KM, KT, or MP), ignore the BB15 cable connections and connect the FP15 directly to the MM15A as indicated in the table.

5.1.5

Figure 5-2

FP15 Indicator Bus Connections

Indicator Bus Cable Connections

Connect the FP15 Indicator Bus cables to the FP15 wired assembly indicator cable connector card locations (J03, J04, J05, and J06) as designated in Figure 5-2. Dress the indi cat or bus cables between
the FP15 wired assembly and the H721 Power Supply.

5-2

5.1.6

Handwire list

The KP15 must be modified per handwire list supplied in the FP15 Installation Kit.

5.1.7

Postinstallation Checks and Tests

B SIGN, FMQ

B SIGN denotes the sign of the FMB; FMQ 1
through 35 denotes the value of the quantity
stored in the FMQ.

MAJOR STATE, TIME STATE

Denotes the current major state and time
state of the FP15. The FP15 could be in the
FETCH, OPAND, EXP, FUN, NOR, WRITE,
INT 1, or INT 2 major states and in TS01,
TS02, or TS03. The BUSY indicator indicates
that the FP 15 is in the process of perform ing
some function which it has not yet completed.
For example, the FP15 may be sequenced
through an instruction in Diagnostic Mode.

DIR

The DIR indicators denote the number of
steps to be sequenced through for an instruction in Diagnosti c Mode. The value represented by the indicators is decremented for
each step which occurs.

STAL

The STAL indicator denotes that a 71XXXX 8
floating-point instruction has been detected
by the FP15.

TS4

The T54 indicator, when on, denotes that
the FP15 has control of memory and, when
off, indicates that the FP15 is simulating a
memory.

ST PHAS

This indicator denotes that the FP15 is temporarily halted and is not advancing through
the various phases, time states, and major
states.

MDL EN

This indicator denotes that the MDL lines
are enabled and that data is about to be
p Iaced on these lines.

L MIT

This indicator denotes that the FP15 is in the
second FETCH cycle (indirection).

MAINTENANCE

The indicator panel has five maintenance
indicators that perform the following functions:

MAT

This indicator denotes that a Maintenance
(Diagnostic) instruction has been decoded.

MANT MODE

This indicator denotes that the FP15 is in
Maintenance (Diagnostic) mode.

SEL DIAG

This indicator denotes that a Diagnostic instruction has been selected.

DIAG

This indicator denotes that a Diagnostic instruction is being executed.

TRNS EN

This indicator denotes that the sixteen 18bit words representing the contents of the
various registers have been written into memory.
(contin~ed on page 5-4) .

Make a final check of the completed installation to ensure that:

All modules are correctly installed in the FP15 wired assembly.

b. Major components are securely mounted in the cabinet.
c.

Cable and wired connections are correct, and cables and harnesses are dressed and
fastened within the cabinet.

Apply primary power to the cabinet by closing the circuit breaker on the 841B Power Control. Test for
+5V at any of the G829 modules.
Run the FPU 01 Random Exerciser diagnostic program to test FP15 Floating-Point Processor operation.

As a further test to ensure that the FP15 is correctly installed and operational, load and run the Instruction Test diagnostic program MAINDEC-15-DOTA.

5.2

MAINTENANCE

The FP15 Floating-Point hardware includes built-in diagnostic hardware that allows any floating-point
instruction to be sequenced through step-by-step and allows the user to obtain a printout of each register as each step of an instruction is performed. An indicator panel, also supplied with the FP15,
providing a visual display of the major registers. The stepping of the instruction and the printout is
accomplished under software control. The diagnostic programs assume that the CPU and memory are
functioning and operating properly, and are designed to minimize actual troubleshooting since malfunctions can be isolated before troubleshooting techniques have to be used. The following paragraphs
describe the FP15 Indicator Panel and the diagnostic programs used.

5.2.1

FP15 Indicator Panel

The FP15 Indicator Panel is used as a maintenance aid and is located directly above the BB15 Option
Panel. The indicator panel consists of the following indicators.
EPA
JEA

A SIGN, FMA

Denotes the state of the 18 bits in the EPA
register.
Bit 00 denotes the state of A SIGN, bit 01
denotes the state of the GUARD bit; bit 02
is not used; bits 03 through 17 denote the
JEA exit address in memory.
A SIGN denotes sign of operand in the FMA;
FMA 1 through 35 represents the value of the
operand in the FMA.

5-3

DISABLES
RD RST

The FP15 indicator panel is equipped with
the following three disable indicators:
This indicator denotes that the CPU is inhibited from using the RD RST from memory.

CP ACT

This indicator denotes that the CPU is temporarily suspended from sequencing through
phases and time states.

I/O ACT

This indicator denotes that the FP15 is doing
a memory reference cycle (FETCH, OPAND,
or WRITE).

5.2.3

Instruction Tests

The instruction tests perform the following major functions:
a.
b.
c.
d.
e.

Verify that the diagnostic instructions are operating correctly.
Provide loop information for debugging.
Check whether a II FP 15 reg i sters can be cleared and then set to a Ills.
Exercise the FP15 instructions in Diagnostic Mode in a general fashion.
Run automatically until an error is detected.

The error is identified at a 6-digit location (address of program listing). A copy of the contents of the
major registers can be obtained at the time of the error. For further isolation of a malfunction caus-

FP MEMORY CONTROL

COND

5.2.2

The FP indicator panel has five indicators associated with the FP15 Memory Interface.
These indicators are described below.
This indicator denotes that an FP memory request is being made. The indicator remains
on during the memory cycle.

M REQ

This indicator denotes that an FP memory request is initiated.

RD RST

This indicator denotes that the FP15 is simulating memory and has placed data on the
MDl.

MRDA

This indicator denotes that the FP15 has received data from memory and is releasing
memory for additional requests.

MRLS ACK

This indicator denotes that memory is free to
accept additional memory requests.

ing the error condition, a scope loop is utilized.
In order to run the instruction test, the program FPSTEP I which is a separate independent program,
must be preloaded in core. The FPSTEP program allows diagnostic mode stepping of any FPU instruc-'
tion. The operator must specify the instruction to be stepped and must specify either an argument or
data to be used with the instruction.
The FP STEP program can perform the following major functions:

5.2.4

Diagnostic Programs

In addition to the bui It-in diagnostic hardware and indicator panel, the following test programs are

Scope loop any FP 15 instruction at any step rate.

Automatically step any FPU instruction to completion using a pre-set step rate,
with or without typeouts of the FPU registers.

Step any FP15 instruction with complete control over step rate and register typeouts
between steps.

Restart at any time without affecting the program.

Random Exerciser

The FP15 Floating-Point Processor Random Exerciser is a test program to simulate system usage for preventive maintenance. A PDP-15 Computer with 8,192 word memory and an FP15 Floating-Point Pro-

available.

cessor are necessary to run the program. The complete FP15 Instruction Test Hardware Diagnostic
Instruction Test - Part 1

FPIT 01

MAINDEC-15-DOTA

series should be run prior to running the random exerciser. The following system parameters are se-

Instruction Test - Part 2

FPIT 02

MAINDEC-15-DOUA

lected:

Instruction Test - Part 3

FPIT 03

MAINDEC-15-DOVA

Diagnostic Mode Stepping

a.
b.
c.

MAINDEC-1S-DOWA

Floating-Point Diagnostic
Random Exerc iser
FP STEP

50 or 60 Hz power
API or no API
The amount of memory to be initialized

MAINDEC-1S-DOSA
After system parameter selection, the instruction and data format are selected. Hardware operations

These test programs are described in the following paragraphs. Before these programs are run, the

and software calculations can then be performed on specified operands or on randomly selected func-

System Exerciser should be run on a daily basis for preventive maintenance.

tions.

5-4

Table 5-3 (Cont)

The random exerciser contains a real-time clock (RTC) routine to keep track of time and uses a 24 hour
clock (for example, 2:00 p. m. is 14:00). The program will print:
Drawing No.
Disable RTC
Type in time
When time is reached enable RTC
Time
Errors are detected in the random exerciser program by comparing a software calculated arithmetic result to the actual FPU completed result. Occurrence of an error condition causes an error typeout
format to be printed.

5.3

ENGINEERING DRAWINGS

Engineering drawings pertinent to the FP15 Floating-Point Processor are listed in Table 5-3 and included in a separate volume entitled FP15 Floating Point Processor, Engineering Drawings.

Table 5-3
FP15 Floating-Point Processor Engineering Drawings

Drawing No.

D-UA-FP15-0-0
A-PL-FP15-0-0
D-DI-FP15-0-67
D-AD-7007243-0-0
A-PL-7007243-0-0
D-MU-FP15-0-66
A-PL-FP15-0-66
D-BS-FP15-0-0l
D-BS-FP 15-0-02
D-BS-FP15-0-03
D-BS-FP15-0-04
D-BS-FP15-0-05
D-BS-FP15-0-06
D-BS-FP15-0-07
D-BS-FP15-0-08
D-BS-FP15-0-09
D-BS-FP15-0-10
D-BS-FP15-0-11
D-BS-FP15-0-12
D-BS-FP15-0-13
D-BS-FP15-0-14
D-BS-FP15-0-15
D-BS-FP15-0-16
D-BS-FP15-0-17
D-BS-FP15-0-18

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Title

Floating Point Processor
Floating Point Processor
Drawing Index List (FP15)
Wired Assy (FP15)
Wired Assy (FP15)
Module Utilization
Module Utilization
Memory Interface Cables
Memory Dri vers
Output Multiplexer (MPO)
Multiplexer Inputs (MPI)
Multiplexer Control
Memory Receivers
Buffered Mem Bits 00-17
Buffered Mem Bits 18-35
Ti me State Generator
Memory Interface Ctrl 1
Memory lnterface Ctrl 2
Memory Interface Ctrl 3
Instruction Register (IR)
Diagnosti c Inst Reg (DIR)
Address Register (AE)
Diagnostic Address Reg (DAR)
A Exponent Register (EPA)
B Exponent Register (EPB)

D-BS-FP15-0-19
D-BS-FP15-0-20
D-BS-FP15-0-21
D-BS-FP15-0-22
D-BS-FP15-0-23
D-BS-FP15-0-24
D-BS-FP15-0-25
D-BS-FP15-0-26
D-BS-FP15-0-27
D-BS-FP15-0-28
D-BS-FP12-0-29
D-BS-FP15-O-30
D-BS -FP 15-0-31
D-BS-FP15-O-32
D-BS-FP15-0-33
D-BS -FP 15 -0-34
D-BS-FP15-0-35
D-BS-FP15-0-36
D-BS -FP 15-0-37
D-BS-FP15-0-38
D-BS-FP15-0-39
D-BS-FP15-O-40
D-BS-FP15-O-41
D-BS-FP15-0-42
D-BS-FP15-O-43
D-BS -FP 15-0-44A-SP-FP15-0-70
A-SP-FP15-O-71
A-SP-FP15-O-72
D-CS -H721-0-1
C-CS-716-0-1
D-FD-FP15-0-45
D-FD-FP 15-0-46
D-FD-FP15-0-47
D-FD-FP 15-0-48
D-FD-FP15-0-49
D-FD-FP15-0-50
D-FD-FP 15-0-51
D-FD-FP 15-0-52
D-FD-FP15-0-53
D-FD-FP 15-0-54
D-FD-FP15-0-55
D-FO-FP15-0-56
D-FD-FP 15-0-57
D-FD-FP 15-0-58
D-F D-FP 15-0-59
D-FD-FP15-0-60
D-FD-FP15-0-61
D-FD-FP15-0-62
D-FD-FP 15-0-63
D-FD-FP 15-0-64

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Title

Arith Logic Unit 00-03
Arith Logic Unit 04-07
Arith Logic Unit 08-11
Arith Logic Unit 12-15
Arith Logic Unit 16-19
Arith Logic Unit 20-23
Arith Logic Unit 24-27
Arith Logic Unit 28-31
Arith Logic Unit 32-35
Carry Look Ahead
JMS Exit Address Reg (JEA)
Shift Counter (SC)
Instructi on Decoder
Manti ssa & Exponent Ctrl
Adder Control
Load & Store Control 1
Load & Store Control 2
Add & Subtract Ctrl 1
Add & Subtract Ctrl 2
Multiply & Divide Ctrl 1
Multiply & Divide Ctrl 2
Normalize Control
Misc Inst Control
Diagnosti c Control
Error Check
Indicator Cables
Acceptance Specification
Insta lIati on Speci fi cation
FP15 Hand Wire List
H721 Power Supply
716 Power Supply
Fetch Cycle Flow 1
Fetch Cycle Flow 2
Fetch Cycle Flow 3
Opand Cycle Flow 1
Opand Cycle Flow 2
Opand Cycle Flow 3
Write Cycle Flow
Add, Sub, Rev Sub, Exp Cycle
Add, Sub, Rev Sub, Sub Cycle
Floating Mul & Div Exp Cycle
Float & Integer Mul Fun Cycle
Integer Divide Exp Cycle
Float & Integer Div Fun Cycle
NO R TS 1 Cycle Flow
NOR TS2 Cycle Flow
ASIGN Swap & Float Control
Fix Flow
Interrupt Flow
Maint Flow 1
Maint Flow 2

5-5

APPENDIX A
SIGNAL GLOSSARY

Signal Mnemonic

logic Print

Address Acknowledge or Power Clear.

BIT 02 SEl

FP15-0-04

Sets bit 02 to indicate JMS type instruction.

FP15-0-36

Indicates an addition of two quantities with like signs.

BMB 00-3S

FP1S-0-3S

ADD 00-17 SEl

FP1S-0-3S

Used for selecting MPO address lines during a Store instruction.

ADD S

FP15-0-36

Indicates addition of two quantities with unlike signs (actually
a subtraction).

Used for loading the FMA during a non-arithmetic function and
for loading the FMB during an arithmetic function. This signal
generates AUB on D-BS-FP1S-0-33 to select the A side of the
AlU.

BRANCH EN

FP1S-0-41

Indicates that a successful branch test has occurred.

ADD lS-3SSEl

FP1S-0-3S

Used for selecting MPO address lines during a Store instruction.

BMB 27-35 SEL

FP15-0-35

ADR ACK (1) B

FP1S-0-01

Notifies the peripheral devices of receipt of MREQ, memory address, and mode of operation (read or write).

A signal used to load bits 27 through 35 of the BMB into the
EPA or EPB when single-precision floating-point format is specified.

ALIGN MA

FP15-0-37

Indicates that FMA is to be aligned during addition or subtraction. Also indicates that the exponent associated with the FMA,
in this case, is less than the exponent associated with the FMB.

BRANCH TEST

FP15-0-41

Indicates a successful branch test was made and a branch is to
be performed.

BRS

FP15-0-37

ALIGN MB

FP15-0-37

Indicates that FMB is to be aligned during addition or subtraction. Also indicates that the exponent associated with the FMB,
in this case, is less than the exponent associated with the FMA.

In EXP cycle during addition or subtraction, BRS (FMB Right
Shift) causes shifting of FMB to align mantissas.

BUSY

FP15-0-11

Indicates that the FP15 is busy and sets up certain conditions
for floating-point operation.

Signal Mnemonic

Logic Print

AA + PC

FP15-0-05

ADDA

Function

ALL WRITE

FP15-0-12

Indicates that the FP15 is in a WRITE cycle or a diagnostic routine.

CARRY P

FP1S-0-39

Generates the strobe that loads the FMA or FMQ after each
sh ift.

-ALL ZEROS

FP15-0-37

Indicates that the difference between EPA and EPB is not greater than 35 10 ,

C DIY (Combined
Divide)

FP1S-0-31

This signal represents the OR of Divide and Reverse Divide.

AR LOAD

FP15-0-15

A signal used to load the AR at FETCH*T3*P3.

C DIY INT P

FP1S-0-38

A SEL, B SEL

FP1S-0-0S

Used to select one of four inputs to be gated through M 1701
Data Selector.

Used in the EXP cycle of Integer Divide for negative integers
to increment the FMB containing the negative integer.

CHANGE

FP15-0-1l

Indicates that the FP15 has finished the FETCH cycle.

A SIGN, B SIGN

FP1S-0-32

The sign bits of the FMA and FMB, respectively.

CHECK EN

FP1S-0-37

AUA, AUB

FP15-0-33

Address lines for selecting the A side of AlU.

Determines whether format is floating-point or integer addition
or subtracti on.

AUA1, AUB1

FP1S-0-33

Address lines for selecting the B side of ALU.

CLK 00-17

FP1S-0-07

A signal used to clock bits 00 through 17 of the BMB.

AUS

FP1S-0-33

Strobe line for multiplexer connected to the A side of ALU.

CLK lS-35

FP15-0-08

A signal used to clock bits lS through 35 of the BMB.

AUS1

FP1S-0-33

Strobe line for multiplexer connected to the B side of AlU.

CLR BMB 00-17

FP15-0-35

A ZERO, B ZERO

FP15-0-32

Used to detect whether the FMA or FMB registers, respectively,
are cleared. (Equal to Zero.)

Clears bits 00-17 when a positive 2's complement singleprecision integer number is loaded into the BMB.

CLR EPA P

FP15-0-40

BIT 00-01 DIS

FP15-0-04

Sets bits 00 and 01 to indicate jump type instruction.

During normalize, FMA is checked to see if it is O. If so,
ClR EPA P clears EPA and A SIGN.

A-I

Signal Mnemonic

Logic Print

Function

Signal Mnemonic

Logic Print

Function

ClR EXC

FP1S-O-29

A signal used to clear EXP I FUN I or NOR cycle upon receipt
of an interrupt or Branch instruction.

DIV COUNT SEl

FP15-0-39

Enables EPA to inputs of shift counter during FUN cycle of Integer Divide.

CaMP

FP1S-0-36

Indicates that an overflow has occurred during subtraction.

DIV EXP

FP1S-0-39

Initiates EXP cycle during floating-point division.

DlV EXP P

FP1S-0-39

Used in detecting possible overflow or underflow in the EXP cycle during division.

DIVlDE(1)H

FP1S-0-43

Indicates abnormal divide has been detected.

DIV INC P

FP1S-0-38

Used to produce EPA UP on first shift of divide if first subtraction result is positive.

DlVMQ

FP1S-0-38

Produces AUA to enable FMQ to AlU bus for subsequent swap
of the FMA and FMQ at the end of the divide.

CaMP MA

CaMP MB P

FP1S-0-34

Used during integer arithmetic when a negative 2 s complement
number is used. This number is converted to sign and magnitude
by complementing and incrementing the FMA. CaMP MA complements the FMA.
Used during integer arithmetic when a negative 2 1s complement
number from memory is used. The number is converted to sign
and magnitude format by complementing and incrementing the
FMB. CaMP MB complements the FMB.

CaMP SUB

FP1S-0-36

Complements the result if an overflow occurred during a subtraction .

DlV MQ SH

FP1S-0-38

Produces MXA 1 which enables FMQ to be shifted left in the
FUN cycle during division.

CN 00

FP1S-0-33

Indicates a carry inpuf to the least significant stage of the AlU.

DIV P

FP1S-0-38

CN 01-08

FP1S-0-28

Carry inputs to each AlU from the carry look-ahead generator.

A pulse used to produce AlS and MlS during division in order
to strobe the FMA and FMQ. A DIV P pulse is produced for
each shift during Divide.

COND

FP15-0-11

Indicates that the FP1S is making a memory request.

DlV SHRT P

FP1S-0-38

COUNT A IT P

FP1S-0-39

Shifts FMA and FMQ left during EXP cycle of Integer Divide.

Produces ARS which shifts the FMA right one place at the end
of the divide process and prior to the swap.

CP ACT DIS

FP1S-0-0l

Disables CPU cycle to allow FPU to communicate with memory.

DlV SWAP P

FP1S-0-38

CP RD RST DIS

FP1S-0-0l

Inhibits CPU from seeing data on MDl.

Produces AlS and MlS which causes the contents of the FMA
and FMQ to be swapped.

C SUB

FP1S-0-31

This signal represents the OR of Subtract and Reverse Subtract.

DlV ZERO

FP1S-0-43

A divide-by-zero operation has been attempted.

DUMMY EN

FP1S-0-0S

A signal used in the dummy fetch of the FETCH cycle.

DAR ClK

FP1S-0-16

A signal used to increment the Diagnostic Address Register during Maintenance Mode.

EPA GRT

FP1S-0-36

Increments the EPA during a floating-point or Fix instruction
due to a carry out of the AlU.

DATA ACK l

FP1S-0-0l

N oti fies memory that it may remove the data from the bus.
EPA lD

FP1S-0-32

A signal that loads the EPA.

DCH SYNC

FP1S-0-06

Indicates I/O Processor wants memory access.
EPA MOVE P

FP1S-0-35

DlAG

FP1S-0-42

Indicates next instruction fetched from core will be interpreted
as a Diagnostic instruction

Used during Reverse Divide or Reverse Subtract to load the contents of the EPA into the EPB.

EPA UP

FP1S-0-32

A signal (that increments the EPA).

EPB SEl

FP1S-0-37

Selects EPB to be inputted to B side of AlU when calculating
exponent during multiplication and division. Also used to transfer EPB to EPA if EPB > EPA during addition or subtraction.

EXC

FP1S-0-11

Indicates that the FP1S is in the EXP I FUN, or NOR cycle,
which are all internal cycles within the floating-point processor.

EXIT INT + BRANCH

FP1S-0-41

Indicates completion of interrupt or Branch instruction.

EXP

FP1S-0-11

Denotes exponent cycle which is used to align or calculate exponents of the operands.

EXP EXC
(Exponent Exception)

FP1S-0-37

Used during exponent alignment and indicates that difference
between exponents is too large to be aligned.

EXP ONES

FP1S-0-37

Indicates EPB - EPA is greater than positive 3S.

EXP SEl

FP15-O-33

A signal used to enable the EPA during shifting operations.

EXP ZEROS

FP1S-0-37

Indicates EPA - EPB is greater than positive 35.

DlRDWN

FP1S-0-42

Decrements the DIR for each step of a Diagnostic Step and Read
instruction
0

DIS CP ACT

FP1S-0-10

Used to disable the CPU in order to allow the FP1S to gain control of memory.

DIS I/o ACT

FP15-0-10

Used to prevent I/O from gaining control of memory bus during
floating-point operations.

DIS RD RST

FP15-0-10

Used to disable the CPU from seeing a RD RST signal and allowing the FP1S to gain control of memory.

DIV ADD SH

FP15-0-38

Produces MXB during Divide if subtraction produces positive resuit. MXB shifts subtracted result left on inputs to FMA.

DlV ASH

FP1S-0-38

Produces MXA during Divide if subtraction produces negative
result. MXA enables FMA to be shifted left.

DlV COUNT P

FP1S'-0-39

Used to increment the EPA and left-shift the FMQ in the EXP
cycle of Integer Divide.

A-2

Signal Mnemonic

Logic Print

Function

FETCH

FP1S-0-1l

Denotes FETCH cycle where the instruction is strobed into the
FP1S Instruction Register.

FIX COUNT

FP1S-0-41

Establishes the number of shifts required to fix the floatingpoint numbers.

FIX + FLOAT SEL

FP1S-0-41

Indicates a Fix or Float instruction has been selected.

FIX P

FP1S-O-41

Used to load the shift counter with the difference between 3SlO
and the EPA and indicates the number of shifts required to fix
the number.

FIX SHMA

FP1S-0-41

Upcounts the shift counter and right shifts the FMA and FMQ
during a Fix instruction.

FIX SEL

FP1S-0-41

FIX ZERO

Signal Mnemonic

Logic Print

Function

INCA P

FP1S-0-34

Used during integer arithmetic when a negative 2 1s complement
number from memory is used. This number is converted to sign
and magnitude by complementing and incrementing the FMA.
INCA increments the FMA.

INCB P

FP1S-0-34

Used during integer arithmetic when a. negative 2 1s complement
number from memory is used. Th is number is converted to sign
and magnitude by complementing and incrementing the FMB.
INCB increments the FMB.

INT

FP1S-0-43

Indi cates an interrupt has been detected.

INT + API ST

FP1S-0-OS

Indi cates that a Trap has been found.

Indicates a number greater than 1 which can be fixed.

INT CHECK 1

FP1S-O-43

Check for overflow of negative integer during single-precision
Integer Store instruction.

FP1S-O-41

Indicates a Fractional number that cannot be fixed. A SIGN
and EPA are cleared.

INT CHECK 2 P

FP1S-O-43

FLOAT + RX

Checks for overflow of positive integer during single-precision
Integer Store instruction.

FP1S-0-40

Designates floating-point instruction or Fix instruction.

INT COMP P

FP1S-O-3S

FLOAT SEL P

FP1S-0-41

Loads 438 in the EPA during a Float instruction.

Loads the complement of the FMA into the FMB during Integer
Store.

FLOCK

FP1S-0-11

Used to set up the FETCH cycle during the start of a floating
point operation.

INT DIV P

FP1S-0-39

Used during integer divide to generate signals indicating whether FMA, or FMQ, or both, are to be left-shifted.

FMA STROBE

FP1S-0-36

This signal causes the FMA to be reloaded if an overflow occurs
out of the ALU.

INT DIV STOP

FP1S-0-39

Generated when both FMA and FMQ are normalized during Integer Divide.

FPCA, FPC

FP1S-O-09

Floating-point clock outputs.

INT INC P

FP1S-0-3S

Used for incrementing the FMB during an Integer Store.

FP MRDA

FP1S-O-1O

Memory Release, Data Acknowledge. Used to indicate to memory that cyc Ie is completed and data has been accepted.

INT MPY OVR

FP1S-0-43

Indicates an overflow has occurred during Integer Multiply.

I NTRP SYNC (1) H

FP15-0-10

FP MREQ

Used to disable program interrupt and API w~en STALL is set.

FP1S-O-l0

A memory-request made by the FP15. Memory senses the request as ~ CPU memory request.

INT 1, INT 2

FP1S-0-ll

FP MRLS ACK

FP1S-0-10

Used to simulate MRLS ACK generated by the memory to complete memory cycle.

This signal is raised during an overflow, underflow, or divide
by zero condition to indicate entry to a Service routine in the
CPU.

I/O ACT DIS

FP1S-0-0l

FP RD RST

FP1S-0-10

Used to simulate Central Processor in order to complete memory
cycle.

Disables I/O processor to allow FP1S to communicate with memory.

IR CLK

FP1S-O-13

FP WAIT

A signal used to clock the IR.

FP1S-0-09

Locks floating-point processor in TS03*PHOl during the dummy
FETCH.

JMS SEL

FP1S-0-43

Forces JMS exit address onto MDL Iines-:

FUN

FP1S-0-11

Denotes function cycle whi ch includes the actual instruction to
be executed.

LD DIV COUNT

FP1S-0-39

Causes shift counter to be loaded with 438 in the EXP cycle during Integer Divide.

GG 00, GG 01

FP1S-0-28

Carry generate outputs from carry look-ahead logic used to
speed up carry propagation through the ALU.

LD EPA, LD EPB

FP1S-0-3S

Used to load the EPA or EPB register, respectively, during the
OPAND cycle.

G01-G07

FP1S-O-20
through -26

Carry generate outputs of one of the 4-bit ALU circuits used in
carry look-ahead circuitry.

LD IR

FP1S-0-08

A strobe signal used to load the DIR when a floating-point instruction has been detected.

GRT

FP1S-0-36

Generated (greater than) when a carry occurs out of the MSB of
the ALU during addition, subtraction, or rounding.

LD JMS P

FP1S-0-41

A pulse used to load JMS during FUN*TS1.

LD MA

FP1S-0-35

Used to load theFMA during the OPAND cycle when a nonarithmetic or reverse arithmetic instruction is issued.

LD MB

FP1S-0-3S

Used to load the FMB during the OPAND cycle when an arithmetic instruction (except for Reverse Subtract or Reverse Divide)
is issued.

GUARD

FP1S-0-40

Indicates that rounding is possible.

HFPC

FP1S-O-40

A clock pulse used for normalizing numbers - two HFPC pulses
(half FPC) are required per shift during normalize.

A-3

Si gna I Mnemon i c

Logic Print

Used to load the shift counter with 438 to limit the number of
shifts during normalize.

MPY SHRT

FP15-0-39

During floating-point or Integer Multiply, this signal causes
FMA and FMQ to be right-shifted.

FP15-0-37

A pulse used to load the shift counter to check the number of
shifts needed for alignment of mantissas.

MPY SWAP P

FP15-0-38

FP15-0-36

Produces ALS and MLS in order to zero the FMA and strobe the
FMA into the FMQ at the beginning of the FUN cycle in multipli cati on.

Indicates A SIGN and B SIGN are both positive or both negative.

MQ INT

FP15-0-39

Used in Integer Divide during the EXP cycle to enable the FMB
to the ALU bus.

MQINTP

FP15-0-39

Produces MLS which strobes the FMB into the FMQ.

MRD

FP15-0l

Selects read/restore memory cycle.

Signal Mnemonic

Logic Print

Function

LD NORM COUNT

FP15-0-40

LD SC P
LIK E

Function

LIMIT

FP 15-0-11

Allows FP15 to perform only one level of indirection.

MA CH ECK

FP 15-0-37

Check to see if FMA is equal to O.

MB CHECK

FP15-0-37

Checks to see if FMB is equal to O.

MAINT MODE (1) H

FP15-0-41

When set, this signal indicates maintenance instructions are to
be performed.

MA MOVE P

FP15-0-35

Used during Reverse Divide or Reverse Subtract to load the contents of the FMA into the FMB.

MREQ

FP15-0l

The signal is generated by the CPU requesting start of a memory
cycle.

MAT CLR

FP15-0-10

Indi cates that the maintenance instruction is complete and the
register contents have been written into memory.

MRLS

FP15-0l

The CPU issues this signal to release memory for additional requests.

M CLR

FP15-0-41

Indi cates a Debreak instruction or a Power Clear condition.

MRLS ACK (1) B

FP15-0l

Notifies device that memory has accepted data and is terminating memory cycle.

MDL EN

FP15-0-11

Enables data from the FP15 to be placed on the MDL.
MRS

FP15-0-32

A signal that causes the FMQ to be right-shifted.

MDl OO-MDl 17

FP15-0-0l

18 memory data lines providing bidirectional transfer of address
and/or data from memory.

MWR

FP15-0l

Selects clear/write memory cycle.

MPIOO-17

FP15-0-04

Each MPI line can receive one of four different input signals.
Data on the output line is determined by select signals MOA
and MOB.

MXA, MXB

FP15-0-32

Used as select signals to supply data from one of four sources to
the FMA.

MXA, MX B, MXC I
MXD

FP15-0-0S

Select lines to select one of 16 possible inputs to MPO.

MXA1, MXB1

FP1S-0-32

Used as select signals to supply data from one of four sources of
the FMQ.

NOR

FP15-0-11

Denotes normalize cycle, where an operand is to be normalized.

NOREN

FP15-0-32

A signal which causes normalize to occur when requested.

Memory Release, Data Acknowledge. Issued by the FP15 to indicate data has been received and to allow additional memory
requests.

MRDA

MPO 00-17

FP15-0-03

18 output multiplexer lines that transfer one of sixteen 18-bit
words to memory.

M PWR-OK

FP15-0l

Memory power is applied to the memory circuits.

MPY + DIV EXP P

FP1S-0-39

Used to produce EPS LD which strobes ALU contents into EPB in
the EXP cycle of Multiply or Divide.

MPY + DIV ODD

FP15-0-38

This signal indicates negative quotient.

NORM DONE

FP15-0-40

Indicates FMA 01 is on a 1 and normalize is completed.

MPY + DIV OVR P

FP1S-0-43

Indicates an overflow has been detected during multiplication
or division.

NORM P

FP15-0-40

Pulse used for normalizing FMA. A NORM P pulse is generated
for each normalize shift.

MPY + DIV UND P

FP15-0-43

Indicates an underflow has been detected during multiplication
or division.

NOR SEL

FP1S-0-40

Indicates normalization has been requested.

ODD

FP15-0-36

Indicates sign bits (A SIGN and B SIGN) are not equal.

MPY EXP P

FP15-0-39

Used in detecting possible underflow or overflow in the EXP cycle during multiplication.

OtJAND

FP1S-0-11

Denotes OPAND cycle in which the operand(s) is fetched from
memory.

MPY P

FP15-0-39

Used to produce ALS and MRS in order to load the FMA and
shift FMQ right during multiplication.

OPAND DWN P

FP15-0-12

MPY SEL

FP 15-0-38

Produces A+B which strobes FMA + FMB into the ALU.

Down counts the shift counter during the OPAND cycle. Up to
three down counts are possible depending on number of operands
requ i red from memory.

MPY SHAD

FP15-0-39

Produces MXA and MXB during floating-point and Integer Multiply which causes the added result to be shifted right at inputs
to FMA and also enables FMQ for right-shift.

OVR (1) H

FP15-0-43

Indicates an overflow has been detected.

POl-P07

FP15-0-20
through -26

Carry propagate outputs from the ALU where a carry is propagated at the output of a 4-bit ALU circuit.

A-4

Signal Mnemonic

Logic Print

Propagate output from the carry look-ahead circuitry used to indicate a carry was propagated from previous stage.

STALL RESET

FP15-0-10

Used to reset the STALL fl ip-flop as a result of a PI or API
break.

FP15-0-3S

Used to inhibit the stepping of the shift counter during floatingpoint Divide (FUN cycle). PREP SC loads the shift counter at
NOR*T3.

STALL STB

FP15-0-06

Monitors MDl lines and strobes data into FP15 when 71XXXXS
has been detected.

STEP P

FP15-0-42

Indicates first step of Diagnostic Step and Read instruction.

RD RST (1) B

FP15-01

Notifies the CPU that the data from memory is on the bus and
ready to be strobed into the MI register.

STOP ALIGN

FP15-0-37

RND

FP15-0-40

Indicates that rounding has been requested and is about to take
place.

Used during EXP cycle of addition or subtraction when exponent
difference is greater than 35 and denotes that alignment is completed or no al ignment is to be performed.

STOP ClK

FP15-0-42

RND+l

FP15-0-36

Occurs during addition at FUN*T1 as a result of mantissa alignmenta

Halts the FP15 Clock to allow sixteen lS-bit words to be transferred to memory during a Diagnostic Step and Read or Diagnostic Read instruction.

ROUND MA P

FP15-0-40

Indicates FMA is to be rounded if guard is set.

STOP DIV

FP15-0-3S

Stops the division process when the divisor is normalized.

R SET (1) H

FP15-0-09

A signal that clears R SET SYNC which allows ST PHASE to reset in order to start the phase and time state generator.

STORE COMP

FP15-0-35

Indicates that the contents of the FMB are written into memory.
This signal is raised for a negative integer.

R SET SYNC

FP1S-0-09

Used to reset ST PHASE in order to reset the FP clock.

STORE JEA
STORE OVR P

FP1S-0-41
FP15-0-43

STORE RND P

FP15-0-35

Used to round on a single-precision floating-point Store instructiona

STORE SEL

FP1S-0-35

Used to select inputs to the multiplexer during a WRITE cycle.

STORE UND P

FP15-0-43

Indicates that underflow has been detected during normalization
of a single-precision floating-point Store instruction.

ST PHASE

FP1S-0-09

Used to stop the phase during arithmetic operations.

SUB A

FP1S-0-36

Indicates a subtraction of two quantities with unlike signs (actual Iy an addition).

SUB S

FP1S-0-36

Indicates a subtraction of two quantities with like signs.

Signal Mnemonic

Logic Print

Function

PPOO, PP01

FP15-0-2S

PREP SC

RT CP

FPlS-O-ll

Allows CPU to complete cycle since the FPl5 simulates an NOP
which is transmitted to the CPU.

SC ADDR A,
SC ADDR B

FPl5-0-30

Selects one of two address lines on the M170l Data Selector
wh ich is outputted to the sh ift counter.

SEL A, SEL B

FP15-0-37

SEL A is ~enerated when the absolute value of EPA-EPB is greater than 2 7. SEL B is generated when the absolute value of
EPA-EPB is greater than 2 17_1.

SEl C, SEl D

FP15-0-37

SEL C is generated when EPB is more positive than EPA and both
are positive quantities. SEL D is generated when EPA is more
negative than EPB and both quantities are negative.

Function

Used to store the JEA.
Indicates that overflow has been detected during normalization
of a single-precision floating-point Store instruction.

SEL DIAG

FP15-0-42

Maintenance mode is enabled and the instruction on which
maintenance is to be performed was loaded.

SWAP MQ P

FP15-0-41

Used to swap the contents of the FMA and FMQ.

SET BMB 00-17

FP15-0-35

Sets bits 00 through 17 to all l's when a negative 2's complement single-precision integer number is loaded into the BMB.

TRANSFER

FP15-0-42

SET FP

FP1S-0-10

Indicates that the CPU is fetching the address of the argument.

TRANS EN

FP15-0-10

SET OVR

FP1S-0-43

Detects overflow during multiplication or division.

Enables Transfer P which initiates transfer of sixteen 1S-bit
words to memory.
Used during Maintenance mode to indicate completion of transfer of data from sixteen registers to memory.

TRANS EPB

FP1S-0-37

SET SC 17

FP1S-0-30

Used to indi cate the number of operands or the number of write
cycles to be performed.

Transfers contents of EPB into EPA during exponent alignment
when the EPB is greater than the EPA.

TRANSFER P

FP15-0-42

SET UND

FP15-0-43

Detects underflow during multiplication or division.

Initiates transfer of sixteen lS-bit words to memory during Maintenan ce mode.

SET ZERO

FP1S-0-39

Indicates a zero quotient and also that shifting is halted.

FP15-0-09

Various time state of the time state generator.

SKIP ZERO

FP15-0-39

Decreases amount of time between carry pulses for multiplication when a shift rather than an add and shift is to be performed.

TS 1 (1), TS 2 (1),
TS 3 (1)
UND (1) H

FP15-0-43

Indi cates an underfl ow has been detected.

UND SYNC (1) H

FP1S-0-43

Used for storage of temporary underflow condition.

WRITE

FP15-0-11

Denotes WRITE cycle in which data is written into memory.

WRITE DWN P

FP15-0-02

Down counts the shift counter during the WRITE cycle. Up to
three down counts are possible.

SO, 51, S2, S3
STALL

FP1S-0-33
FP15-0-10

Address selection lines used to specify arithmetic or logical operations to be performed by ALU (see FP15-0-33).
Generated during detection of a 71XXXXS op code denoting an
FP instruction.

A-S