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Document:	DU11 Single Line Programmable Synchronous Interface Maintenance Manual
Order Number:	EK-DU11-MM
Revision:	001
Pages:	104
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OCR Text

DU11 single line
programmable
synchronous interface
maintenance manual

dlilgliltiall

EK-DU11-MM-001

DU11 single line
programmable

‘synchronous interface
maintenance manual

digital equipment corporation - maynard, massachusetts

Preliminary Edition, October 1973

1st Edition, January 1974
2nd Printing, March 1974
3rd Printing, December 1974

The material
in this manual is for informational
purposes and is subject to change without notice.

= -‘Di'g’itéil EQUibment Corporation assumes no respon- sibility for any errors which may appear in. this -

manual.

Printed in U.S.A.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

PDP

FLIP CHIP

DIGITAL

FOCAL
COMPUTER LAB

UNIBUS

4/79-14-

'CONTENTS
Page

CHAPTER 1
1.1

1.2
1.2.1

INTRODUCTION
SCOPE

Data

1.2.1.1
1.2.1.2
1.2.2

e e

1-1

. . . .. ... ... .....

Communication Techniques

1-1

. . . . . . .. ... . ... ... ... ......

Pulse Coding

1-1

. . . . . . . . . . . . .

e e e

e e

1-1

Pulse Code Transmission . . . . . . . v v v v i ot e e e e e e e e
Data Communication SYStems . . . . . . v v vt e e e e e e e e e

1-1
1-3

1.2.2.1

Synchronous Systems

. . . . . . . . . .

1.2.2.2

Computer Application

... . . . . . . . .

e e e

. .

e e e e

e e

. . . . . . .

e e e,

1-5

1.4

-PHYSICAL DESCRIPTION

. .. ... ... .... e
e
e e e e

1-5

1.5

SPECIFICATIONS

Environmental

e e e e e e e

1-5

GENERAL DESCRIPTION

. . ... ... .. .. e e

1-3

1.3

1.5.1

e e e i T e e e e e e e e e

. ... ... ... L e

e e

e e e

1-6

e e 16

1.5.2

Electrical
. ... ... ... ... ... .. ..., S
£

1.5.3

Performance

. .. ... AP S

1.5.3.1

Baud Rates for Synchronous Communications

. . . . . . . .L

1-6

1.5.3.2

Baud Rates for Isochronous Communications . . . . . . o v v v v v v v v ...

1-6

1.6
-

. . . .

DATA COMMUNICATION TECHNIQUES AND SYSTEMS

ENGINEERING DRAWINGS

1.6.1

Basic Signal Names

1.6.2

Flip-Flop Signal Names

'CHAPTER 2

INSTALLATION

2.1

INSTALLATION

. . . . . . . o

. . .

2.1.1.1

Standard Configuration

e e e e e e e e e e

e e e

2-1
2-1

. . . . . . . . . . . . i

2-1

Current Mode Configuration

. . . . .. .. ... .. ... ... ........ -

Installing the Modem Cable Harness

2-1

. . . . . .. .. . . .. ..., 21

2.1.3

Unibus and Interrupt Vector Address A351gnments

214

Jumper Assignments

. . . . . .. L L

2.1.5

Priority Assignment

CHAPTER 3

1-6

.........................

2.1.2

INITIAL TESTING

1-8

Mounting the DUI11 in the Computer

2.2

. . . . . .e

2.1.1

2112

s s

. . .. . . .. .. ... .16

..................

L L

e e e

2-5

e e e e e

2-5

. . .. ...
.P

e e e e e e e e e e e e

2-6

. . ......... S

3-1

DEVICE REGISTERS AND INTERRUPT REQUESTS

3.1

SCOPE

3.2

DEVICE REGISTERS

. . . .

. . . . . .

e e e e e e e e e e - 3-1

e e

3.2.1

322

3.2.2.1

3.2.2.2

Bit Assignments

. . . . . . ... ...

e e

. . . . .. L L L L L

e e e

3-2

CHAPTER 4

'THEORY OF OPERATION

4.1

SCOPE . . . . . e
e e
e - 4-1

4.2.1

Initialization and Programming

4.2.2

Handshaking Sequence

4.2.4

Basic Operation

Data Flow Analysis

s s 3-10

............................... -

- 4.2.3

e e

e e e

INTERRUPT REQUESTS

FUNCTIONAL DESCRIPTION

3.3

. . . . .

Lol oo - 3-1

. . . . . . e e

. . .. .. .. S

. . . . . . . . i

... . . . . . .

- ii

e e

S
e

4-1

e e e e e e e e 4-1

.42
e 42

. e

4-7

CONTENTS (Cont)
Page
4.2.4.1

Data Source and Destination

4.2.4.2

Data Flow

4.2.5

42.5.1
42.5.2
42.5.3

e e e

. . . .. ... ... ... .... e

4-7

e e e e e e e e e e

e e

. . . . . . .

Functional Block Diagram Description . . . . .. .. ... I .. 4-11

ClearLogic . . . . v

i v i it e e Ce

4-11

e e

4-11

. . . . . . .. ... .. .... .. 4-11

Address Selection and Mode Control Logic

Receiver Status Register (RXCSR) . . . . o v

4.2.5.4

Transmitter Status Register (TXCSR)

4255

Clock Control Logic

4.2.5.6

RCVR Input Select Logic

it i

...................... 4-11

. . .. ... ... e

e e e e

e e e e e e e e e e e 4-11

e e

42.5.9

. . . . . . ... ... ... ... ..... e 4-12
e e e e e e e e e e e e e 4-12
. . ... ... ..... e
RCVR Logic
e e e e e e e e e 4-13
XMTR Logic . . ... ... ... ....... e e e
e e e e e . e e e e e . 4-13
. . . . . e
Data Set Change Detector

4.2.5.10

Data Output Multlplexer

425.11

BusDrivers

4.2.5.7

4.2.5.8

4.2.5.12
4.2.5.13

4.3
4.3.1

............................. 4-13
. . . . . . . . . ..o e e e e e e e e e e e 4-13
. . . . . . ... ... ... ... e e e e e e e e 4-13
Interrupt Control Logic
EIA Level Converters

ClearLogic

. . . .. e

Address Selection and Mode Control Logic

4.3.2.1

Typical DATI Logic Operation

4.3.2.2

4.3.2.3
4.3.3
434

4.3.5
4.3.6

4.3.6.1
4.3.6.2
4.3.7

4.3.7.1
4.3.7.2

RCVR Input Select LOZIC

e e e e e e e e e e e e e 4-19

e R R 4-20

. . . . . .. ... ... .... P

4-20

RCVR Logic Initialization and Programmmg e A
e e e e e
e e e
RCVR Logic Operation

T 4-21

Clock Control Logic

RCVRLOZIC

XMTR Logic

. . v v v ii e e

5.2.2
5.2.3
5.2.4
5.2.5

5.3
54
5.5
55.1

5.5.2

5.6

4-35

........... P
XMTR Logic Initialization and Programmmg
4-35
XMTR Logic Operation . . . .. .......e e
4-35

Logic
Data Set Change Detector

5.2.1

4-22

. . ... ....

InterruptControlLoglc

5.2

. . .. . . . .. ... 4-15

. . . . . .. . ..

. « v v v v v

4.3.8

5.1

e e e e e e 4-14

.. .. ... ... ... e 4-15
Typical DATOB Logic Operation . . . . . ... ... ... ... ... ... 4-16
4-16
. . . ... ... ST
Typical DATO Logic Operation
4-19
oo oo
.
. . . . . . . . . ..
Data Output Multiplexer Logic

4.3.9

CHAPTER 5

e e e e e e e e e e e 4-14

. .. ... ... ... ....... e e e

4.3.2

e 4-14

e e

e e e

e e e e e e e e

e e e e e e

. .. .. e

DETAILED DESCRIPTION

. . . . . . o o o v it i 4-43
e e e 4-43

e e e e e e e e e e

PROGRAMMING REQUIREMENTS AND RECOMMENDATION S
INTRODUCTION

. . .

e e e e e e e e e e

e e

e e e e

PROGRAMMING THE TRANSMITTER IN THE SYNCHRONOUS MODE
Loading the PARCSR

. . . . .. ... e e e e

........

e e

e
e e
e e e e e e
Enabling the Transmitter . . . . . .. .. ... e
Detecting the Last Character of the MESSAZE . . v . e e e e e e e e e e e e
e e e e e
Transmitting Initial Sync Characters to Establish Synchromzatlon e
SO L
..
..
. . .
Transmitting Sync Characters to Maintain Synchronization

PROGRAMMING THE RCVR IN THE INTERNAL SYNCHRONOUS MODE

PROGRAMMING THE RCVR IN THE EXTERNAL SYNCHRONOUS MODE

PROGRAMMING THE XMTR IN THE ISOCHRONOUS MODE
Loading the PARCSR

Enabling the XMTR

.. R S e
.. . . ...

. ......
...... :

............. .

e e

e e e e e e e ..

e e e e
. . . . ... ... ... ...... e

PROGRAMMING THE RCVR IN THE ISOCHRONOUSMODE

..
. . . ... . . ...

)
/
\

CONTENTS (Cont)
Page

MAINTENANCE

CHAPTER 6

SCOPE . . . vt it i e R o c..

MAINTENANCE PHILOSOPHY

6.2

6.3

PREVENTIVE MAINTENANCE

. . ... .. .. .. ... e e e ...

6.4

TEST EQUIPMENT REQUIRED
CORRECTIVE MAINTENANCE

. . . ......
.. P e e e e e e
. . .. . . . . .

6-1
6-1

Maintenance Modes
. . . . . . . L L.
e
e e e e
System Test Mode . . ... ... e
e e e e e e e e e e
e e e
Internal LoopMode
. ...
.. .. O
External LoopMode . ... ... .. PN (U

6-2
6-2
6-2

6.1

6.5
6.5.1

6.5.1.1
6.5.1.2
6.5.1.3

. . . .. e

e e e e L.

APPENDIX
A

REPRESENTATIVE MODEM FACILITIES AVAILABLE

APPENDIX B

ADDRESS ASSIGNMENTS

B.1

FLOATING VECTORS

B.2

FLOATING DEVICE ADDRESS

APPENDIX C

IC SCHEMATICS

. .. ........ AUS . ... B
. . . ...
. e e e

e e e e e oo ...

ILLUSTRATIONS
Figure No.
1-1

Asynchronous Technique

Synchronous Format

- 1-3
1-4
1-5
2-1

2-2
2-3

24
2-5

2-6
2-7

2-8

2-9
3-1
S

Title

3-2
3-3
3-4

35
4-1

4-2

4-3
4-4

Format

. . . . . . . .. e

e e e e e e

. . . . ... ... .. ......... e

Typical Communication System Using the DU11 Interface

Page

e eI

1-2

e e e e e e e e e e e e

1-3

. . ... ... ... ... .. .

16
DU11 Major Components . . . . .. e
e e e e e e e e
e e
e e
e
eS BV
Flip-Flop Signal Names
. . . . . ... .. ... ... ...
... ...
. 18
Standard Configuration (DU11-DA) Using DD11-B Mountmg Panel ... ... 2
DU11-DA (M7822 Module) Mountedin DDI11-A
. . . . . . .. . ... ..
.
... 2-3
DU11-DA (M7822 Module) Mounted inDD11-B
. . . . . . ... .. ... ... ... .. 2-3
Current Mode Configuration (DU11-EA) Using DD11-B Mounting Panel
... ....... 2-4
DUI11-EA (M7822 Module and DF11-G Converter) Mounted in DD11-B° . . . . . ...
. 2-5
BCO05-25 Cable Harness Used to Connect DU11-DA to Bell 201 Modem . . . . . .. ... 26
BC02W-25 Cable Harness Used to Connect DU11-EA toBell 303Modem . . . ...... L 27
DU11 to Modem Connection
. . ...
. e e e e e e e e L. 28
Modem Test Connection Installation . . . . . . .. I ... 28
Receiver Status Register (RXCSR) . . . .. . . . . . . .
oo oo 3-2

Receiver Data Buffer (RXDBUF)
. ... ... ... e
e
e
Parameter Status Register PARCSR)
. . . .. e e e e e e e e e ..

3-5
36

Transmitter Status Register (TXCSR)
. . . .. .
... .. ... ... e
e
e e
Transmitter Data Buffer (TXDBUF) . .. ...
.. .. PP N
DU11 to Modem Interface Diagram
. . ..
. .. e e e e e e e e e e
e i
e e e
Handshaking Sequence Timing Diagram . . . . . . . e e e e e e e
e e e
Basic Operation Flow Diagram . . . . . . .. .. ... ... .. e
e e e e e
e
DU11 Functional Block Diagram
. . . . . . . . . .. ...
e

3-7
3-9
4.3 4-3
4-5
4-9

ILLUSTRATIONS (Cpnt)

4-5

Page

Title

Figure No.

Clear Logic e e e e e e e e e e ee

e e e e e e e e e e e

e e

e 4-14

4-6

DATI Timing Diagram

4.7

DATOB Timing Diagram

4-17

4-8

DATO Timing Diagram
. . ... ......... e [
Data Output Multiplexer Logic . . . . ... ....... e
e e

4-18

4-9
4-10
4-11
4-12

. . . ... ...
.. ... . e

. . . . . . o o

RCVR Input Select Logic

v e e e

e e e e

. v v o e e e

e e 4-20

e e e

e e 4-21

4-13

RCVR LOZIC

4-14

4-15

RCVR Internal Synchronous Mode Timing Dlagram (Example I)
RCVR Internal Synchronous Mode Timing Diagram (Example. II)

4-16

RCVR External Synchronous Timing Diagram . . . . . ... ... ... ... ....... 4-32

4-17

RCVR Isochronous Mode Timing Diagram

4-18

XMTR Logic

4-19

XMTR Synchronous Mode Timing Diagram

. ... ... ... ... e

4-20

- XMTR Isochronous Mode Timing Diagram

. . . . ... ... ... e

e e 4-41

4-21

Interrupt Control Logic Timing Diagram

6-1

DU11 Maintenance Diagram

C-1

7442 Package and Logic Diagrams

. . . . . .

e e e e e 4-19

e e e ee

. . .. ... ..............e e

L 4-17

e 4-18

. . . . . . e e e e e e e
e e ee

~ External Loop Maintenance Mode Interconnection Dlagram

Clock Control Logic

T e

4-23

e e e e e e e e e e : 425
.............. 429
e e 4-33

.. ... . ... ... ... ..... e e e

e e e e e e e e e

. . . . . . JE

e e e e e e

e e e e

e e e 4-36

e e e 4-37
4-45

. . . . . ... ... ...... e C

e e

. . . . . ... ... ... S

C-2

DEC 74123 IC Illustrations

C-3

DEC 74123 IC Output Pulse Width vs External Timing Capacitance

. . . . . . v v v v v v v v o v

C-4

74153 Package and Logic Diagram

C-5

74174 Logic Diagram

. . . ... ... .... e

C-6

74175 Logic Diagram

. . . . . . ... ...

C-7

74H74 Logic Diagram

. . . . . .. e

. . . . . ... ... e

e e

.e C

C-2

. . . .. ... ... ..

C-2

e e e

C-3

e e.

e e
....... e

e e i e i e e e e e

e e e e e e e e e

e e e

e e

e .

C-4

C-5

TABLES

‘Title

Table No.
1-1

Representative Message Codes

1-2

Computer Communications Appl1cat1ons

2-1

Jumper AsSignments

3-1

DU11 Register Address A351gnments S

3-2

. . . . . .. ... ... . L. PR B
T

. . .. .. ...

Receiver Status Register Bit Description

e ee

. . . e [ |

3-3

- Receiver Data Buffer Bit Description . . . . . . ... ... ... ... ...
...

3-4

- Parameter Status Register Bit Description

. . . . . . ... e e e

3-5

Transmitter Status Register Bit Description

. . . . . oo

3-6

Transmitter Data Buffer Bit Description . . . ... ... [
Bus Address Register Select Bit Configurations . . . . . . . . ...
... . .
... ...
Bus Operation Control Bit Configurations . . . . . . ...
.. [

4-1

4-2
4-3

Maintenance Mode to Data Source Relationship

4-4

PARCSR Mode Select Bit Conflguratlons

6-1

Test Equipment Required

e ee e

B-1

Priority Ranking for Floating Vectors

B-2

(starting at 300 and proceeding upwards)
. . . . . . ...
..o
Floating Address SEQUENCE . . . . . v v v v v v e e e
e .
Floating Device Address ASSIgNMents
. . . . . . o oot v vt
i
i

B-3

. . . . . .e

. . . . . ... ... .. ..........
e e
|

C-1

e ..
N

DUl 1 SINGLE LINE PROGRAMMABLE SYNCHRONOUS INTERFACE

MAINTENANCE MANUAL |

CHAPTER
1
INTRODUCTION

SCOPE

1.1

If, instead of using one binary digit for our character,
we

use two, we have more characters to choose from. OQur

This manual provides a complete description of the DUI11
Line Interface including installation, theory of operation,

choice for a one-bit code was limited to two: 0 or 1. Our

programming, and maintenance. The level of discussion

choice for a two-bit code is four: 00,01, 010, or 11. If we

assumes that

the

reader is familiar with basic digital

~ choose a three-bit code, our choice is eight: 000, 001, 010,

computer theory.

011, 100, 101, 110, and 111. It can be shown that for a

This chapter contains introductory information. It includes

characters available will be 2". In communications parlance,

instead of calling these codes one-bit codes, two-bit codes,

code with a character makeup of n bits, the number of
description

of data

communication

techniques and

systems, a general description of the DU11, a physical

etc., they are called one-level codes, two-level codes, etc.

description

Although any arbitrary meaning can be assigned to a code

of the DUI11, DU11

specifications, and an

explanation of engineering drawing conventions.

character, it is more practical for the majority of operations

to let the characters represent numbers, punctuation marks,

12 DATA

COMMUNICATION

TECHNIQUES

AND

spaces, and letters of the alphabet. In addition to these,
some special codes use characters for other meanings.

SYSTEMS

1.2.1

Data Communication Techniques

There are several techniques used for the transfer of data

1.2.1.2

communication signals. Each has its partlcular advantages

code characters, it is necessary
to arrange their elements in

and disadvantages.

Pulse Code Transmission
— In order to transmit

a way that will allow their reception without uncertainty.
There are several techniques by which this may be done;

1.2.1.1

Pulse

Coding
— Standard

data

communication

these techniques fall into two broad categories: serial data

messages are sent in some form of pulse code. There are

transmission and parallel data transmission.

several varieties of pulsed codes used in the transferral of

data in digital form. Binary signals, by their very nature, are

Because the DU11 is a serial communication interface, only

natural elements for digital data codes. Such codes are said

serial data transmission techniques will be discussed.

to be in “‘binary format.”
There are

A formatted binary code can represent different symbols

two basic techniques of serial data transmis-

sion: asynchronous

and

synchronous.

These

two

tech-

only by allowing sufficient binary elements for each

niques as well as a third, isochronous, will be discussed in

symbol.

the following paragraphs.

If we

think

of one binary digit (or “bit”)

representing each symbol, we have only two choices: one
symbol represented by the ‘“‘on” state, the other represented by the “off”” state. With such an arrangement, we

1.2.1.2.1 Asynchronous Serial Transmission — This tech-

could let the “on”

or one state represent “no” and the

nique enables data to be transferred as it becomes available.

“off” or zero state represent ‘‘yes.” While it would be

This is possible by framing each data character with a begin

difficult with

such an

arrangement, we

could convey

signal (START bit) and an end signal (STOP bit), so that

messages of a very limited nature from a remote station

the equipment receiving the data (the interface receiver)

(such as the answer to “Is the temperature at your station

knows when a data character is being presénted on the

over 70° F?”).

communication line and when the line is inactive.

1-1

(LINE=1)
DATA

Lssl

(LINE=0)

1L— STOP BITS
BITS

DATA

BIT

START

11-2233

| Figure 1-1 Asynchronous Technique Format
Hence, each character consists of three parts: a START bit,
the data bits, and a STOP bit (Figure 1-1). A START bit is

The disadvantages of the asynchronous serial data transmission technique are:.

a line state (usually a zero) that lasts for 1 bit time. The

data bits represent the actual binary character being
transferred. In many applications the characters are 8 bits
long with the least significant bit being sent out and
received first. A STOP bit is a line state (usually a one) that
lasts for 1, 1.42, or 2 bit times; it indicates that character
transmission is complete. The STOP bit enables the

Separate timing required for both transmitter
and receiver.

Distortion

depends
-

interface receiver to check synchronization after each

sensitive

because

incoming

the

receiver

signal sequences

become synchronized. Any distortion in these
‘sequences will affect the reliability wrth which

character transmission. If the STOP bit is not received
properly, i.e., it is not presented on the line immediately
after the last data bit, the character received is considered

the character is assembled.

erroneous and re-transmission is necessary.

Speed limited because a reasonable amount of

margin between characters must be built in to
accommodate distortion.

Clocking for the interface transmitter and interface receiver

during asynchronous transmission is provided by two

Inefficient because at least 10 bit times are

required to send 8 bits of data. If a 2 bit time

different sources that are asynchronous to one another. The
transmitter clock is enabled when data is available for

STOP bit is used, it takes 11 bit times to

transmission and clocks the character onto the line. The

transfer 8 bits of data.

receiver clock is enabled whena START bit is detected on
the line and samples the data bits as they are presented on

1.2.1.2.2 Synchronous Serial Transmission — This tech-

the line. The receiver is also equipped with a counter that

nique does not use START and STOP bits to accomplish

complete

synchronization. Instead, the entire block of data (message)

character and a STOP bit are received (the receiver must

is preceded on the line by a synchronizing code. When the

know the number of bits per character), the receiver clock

interface receiver recognizes this code (henceforth referred

counts the

character

bits

received.

When

to as sync characters), it locks in and, using a counter,

is disabled until the next START bit is detected.

assembles the data characters which follow. Hence, as in the
asynchronous

the following advantages:

Can be generated easily by electromechanical

equrpment (eg., Teletype. keyboard)

the

receiver

must

know the

This technique requires that the clocking for the interface
transmitter and interface receiver be provided by a common

- clock source. The clock signal is provided to the transmitter

and receiver on lines separate from the data line. At the
transmitter, the clock signal serves to clock the data onto

Can be used easily to drive mechanical equrp

the line. At the receiver, the clock signal gates the data in.

ment (e.g., Teletype printer).

technique,

number of bits per character.

The asynchronous serial data transmission technique has

‘Figure 1-2 illustrates the timing for a synchronous commu-

Characters can be sent asynchronously (as they

nication system using modems.

become available) because each character has its

®Teletype is a registered trademark of Teletype Corporation.

own synchronizing information.

1-2

|¢-.| 1BIT TIME

'MODEM CLOCK

||||||||||||||||||||||||||||||||||||||||
© 1t
58|

DATA

0
0 0 1t
|
|

1
0
1
||
|
|

l¢——— SYNC CHARACTER ——#te———DATA CHARACTER ——»
|

11-2234

Figure 1-2 Synchronous Format
c.

As shown in Figure 1-2, the modem provides the clock, the

The
-

going edge of the clock and the receiver samples the data on
TN

common-carrier

equipment required

accommodate this mode of operation is more

transmitter presents the data to the line on the positive

expensive

than the

equipment

required

for

transmit

asynchronous modes of operation.

the negative going edge. If the transmitter pauses at any

time and fails to inhibit the clock, the receiver will continue
to

sample

the

line,

synchronization

lost

and

the

The advantages of the synchronous serial data transmission
technique are:

Modem timing sources can be used for both

Interface

cannot

1.2.1.2.3 Isochronous Serial Transmission — This tech- |

receiver

does

over a synchronous modem. Character synchronization is.
“achieved via START and STOP bits; a common ‘timing

source is used for both the transmitter and receiver.

not

require

clock-

synchronizing logic as the asynchronous technique does.

equipment

nique is essentially the transmission of asynchronous data

transmitter and receiver.

Mechanical

receive this format directly.

remainder of the message will be erroneous.

‘The isochronous technique does have advantages over the
asynchronous technique. Clocking for isochronous operations emanates from the modems andis synchronous to the

Highly efficient because there are no bit times

wasted with the use of START and STOP bits.
All bits on the line are data, with the exception

data;

hence, the receiver does not require clocksynchronizing logic and d1stortlon sensitivity is low making

hlgher speeds possible.

of ‘the sync characters at the beginning of the

bit stream.
d.

1.2.2

Low distortion sensitivity because the timing is

1.2.2.1

Data Communication Systems

Synchronous Systems — Synchronous modulator-

provided along with the data.

demodulators (modems) have permitted a higher rate of

Higher speeds are achievable because of the low

grade facility. The nature of these transmission techniques

distortion sensitivity.

data transmission than asynchronous modems over a voice
~ has also resulted in higher efficiency by eliminating the

need for synchronizing information with every character.

The disadvantages of the synchronous serial data transmission technique are:
a.

The logic design of interfaces to a synchronous modem is
sent synchronously, not

considerably easier than the design of an asynchronous

asynchronously (asynchronous transmission is

interface because there is no need for bit synchronization

Characters must be

desirable for most real time and mechanical

applications).

One bit time added to or missing from the

- and sampling hardware. Most synchronous modems supply
all the timing necessary to receive each bit as it is made

available from the modem. The difficulty in designing a
synchronous modem interface is to design the capability of

data-bit stream can cause the entire message to

communicating in the message formats used in synchronous

be faulty.

communications.

Table 1-1

Representative Message Codes

Character

Meaning

SYN
SOH
STX

ETX
ACK
NAK

Function

Synchronizing signal

Establish character framing

Start of heading signal
Start of text signal

Precedes block message heading characters
Precedes block of text characters

End of text signal
Acknowledge signal
Negative acknowledge signal

Terminates a block of characters started with STX
* Affirmative acknowledgment of message received
*Negative acknowledgment of message received

* ACK and NAK are sent by the station that received the message to the station that originated the message.

It is not the purpose of this manual to discuss the format

for synchronous communication in detail. However, a brief
description of these formats is outlined below
to facilitate

the reader’s understanding of synchronous interface design.

Because the synchronous transmission technique provides

Processor To Terminal
1

only bit recovery timing, there must be a way to establish

Idle Line

’

character framing and message framing. This is accom-

SYN

plished by using codes (usually ASCII) that are assigned for

SYN

synchronous message formatting purposes. Representative

message codes are listed in Table 1-1.

ACK

SYN

A typical message that might be sent between two devices
- (a terminal and a processor) follows.
|

SOH
To Terminal

|
Terminal To Processor

SYN

STX

SYN

No. 4
|

Balance is

SOH
'

User Terminal

N4
l

$100

Idle Line

STX
|

|
Terminal To Processor

Req. Balance

of Account
No. 14325
'

ETX

LRC (check character)

SYN |
SYN

SYN

ACK

Idle Line

v
1-4

1.2.2.2 Computer Application — Electronic computers are

often connected into communication systems to help

transmit and process digital data. By using computer

systems to concentrate data from many low-speed terminals

over one voice grade facility, significant improvements can
be made in the efficiency of a data communication system.
Since most long-range communication systems are

connected through common carrier facilities, a communication system using a computer should be interfaced to the
correct type facility. There are two basic types of common
carrier facilities to which computers must be interfaced: asynchronous serial and synchronous serial. We have

version and is completely contained on the M7822 module.
The basic version is compatible with the Bell 201 synchronous modem or equivalent. Model DU11-EA is simply the
basic version adapted to current mode operation. The
DU11-EA version consists of the basic M7822 module plus
- the DF11-G current mode converter. The DU11-EA is
compatible with the Bell 303, wide band, synchronous
modem or equivalent. A typical communication system

using the DU11 is shown in Figure 1-3.

Interface operation is completely program controlled. The

mode of operation (synchronous or isochronous), character
length (5, 6, 7, or 8 bits plus parity if selected), parity

already pointed out the advantages and disadvantages of
these two types of facilities. Based on these advantages and
disadvantages, Table 1-2 shows typical speeds and appli‘cations of these two techniques.

enable and sense (odd or even), sync character configuration, and duplex mode (full or half) are all selected via

1.4 PHYSICAL DESCRIPTION |

~As shown in Table 1-2, there are three basic communication

The DUI11 interface is completely contained on a single
M7822 Quad Integrated Circuit module (Figure 1-4). This

applications to be solved by the computer communications

engineer:

module can be mounted easily in the PDP-11 processor

small peripheral controller slot (exceptions noted in
Chapter 2) or in one of four slots in a DD11-A or DD11-B

Low speed terminal equipment, such as Teletypes.
Medium speed terminal equipment.

peripheral mounting panel.

Intercomputer communications.

1.3

the program.

GENERAL DESCRIPTION

The DU11 interface is a single line, program controlled,
double-buffered communication interface. It provides serial
to parallel and parallel to serial data conversion, EIA* to
TTL (transistor-transistor logic) and TTL to EIA voltage
level conversion and modem control for full or half duplex

“All DU11 operating power is provided by the mounting
panel in which it is installed. The power is taken from the
mounting box power supply. For proper operation, the
module requires +5V @2.2 A,-15V@0.17 A,and +15 V

communication systems.

The DUI11 is compatible with all PDP-11 family computers

and is available in two models. Model DU11-DA is the basic

@ 0.07 A.

The mounting panel also connects the DU11 to the Unibus.

All Unibus input/output signals enter and leave the module
via the mounting panel pins. Refer to Chapter 2 for Unibus
to mounting panel connection.

. Table 1-2

Computer Communications Applications

Speéd

Low

0 to 300 baud

Medium
300 to 3000 baud

‘High

Asynchronous

Synchronous

o Electfomechanical terminals such as

Operations tend to be asynchronous at

Unbuffered terminals such as paper

Buffered terminals such as displays,

keyboard printers and Teletypes.

tape readers and punches, card readers

buffered card readers, and line printer

and line printers.

configurations.

Not frequently used.

Intercomputer communications.

5000 baud and up

*EIA — A standardized set-of signal characteristics (time duration,
voltage, and current) specified by the Electronic Industries
Association.

these speeds.

COMMUNI CATION FACILITIES

PDP-11

COMPUTER UNIBU_S

PARALLEL
DATA

> INTERFACE

(SYSTEM No.1)

DU11

RIAL

SER)
DATA
-

BELL

EQ%J(I)\;AL?rENT |

SERIAL
DATA

BELL

‘EQ%J(I)\}A?:ENT
—

PARALLEL

INTERFACE
DU11

DATA

UNIBU

PDP-11

2] COMPYTER

(SYSTEM No.
2)

25f1t

25§t

11-2235

Figure 1-3 Typical Communication System Using the DU11 Interface
Major DUI11 components are also labeled on Figure

Current mode operation (100K baud maximum) is 'poésible

interface Unibus address, the priority plug which deter-

DU11 logic.

1-4: the rocker switches which are used to select the

only with the DU11 EA Current mode speed 1s 11m1ted by

mines the bus request (BR) priority level of the interface
- (BR5

plug

normally

installed

factory),

the

SAR

Even though the DUI1 can receive and transmit infor-

(receiver) and SAT (transmitter) chips, and ]umpers w2,

mation at such a high rate, it may, in most cases, be

W4—W6, and W9—W16 (a complete description of the

impractical.

jumpers is providedin Paragraph 2.1.4).

1.5 SPECIFICATIONS

Since the service of the data buffers relies

solely on the program, little time if any would be left for
other events. This problem would be compounded if the

interface were operating in full duplex mode.

Environmental, electrical, and performance specifications

for the DU11 are contained in the following paragraphs.
1.5.3.2

1.5.1 Environmental

Baud

Rates

for

Isochronous

Communica-

tions— EIA/CCITT baud rate (10K baud maximum) is

Ambient temperature |

limited by data set interface level converters. Current mode

10° to 50° C (50° to 122 F)

operation baud rate (100K baud maximum) is limited by
DU11 logic.

Relative humidity

20% to 95% (without condensation)
1.6

1.5.2 Electrical

ENGINEERING DRAWINGS

A complete set of engineering drawings entitled DU11 Line
Interface,

DC voltage requirements

Engineering

Drawings

provided with each

+t5V@2.2A

interface. The general logic symbols used on these drawings

-15V@0.17 A

are described in the DEC Logic Handbook, 1972. Specific
symbols and conventions are also included in the PDP-11

+15V@0.07 A

system manuals. The following paragraphs describe the
signal nomenclature conventions used in the drawing set.

Electrical Characteristics

Flectrical

characteristics

of this interface meet EIA

1.6.1

standard RS-232C and PDP-11 Unibus Interface specrfi-‘

Basic Signal Names

| Srgnal names in the DU11 print set are in the followrng

cations.

basic form:

1.5.3

Performance

The following paragraphs discuss the baud rate limitations

of the DU11 and related program response time.
- 1.5.3.1 Baud

Rates

for

Synchronous

SOURCE

SIGNAL NAME

POLARITY

SOURCE indicates the drawing: number of the print from

Communica-

which the signal originates. The drawing number of a print

tions — EIA/CCITT* baud rate (10K baud maximum) is

is located in the lower right-hand corner of the print title

limited by modem and data set interface level converters.

block (Dl D2, D3, D4, DS, and D6).

*CCITT
— The Consultive Committee International Telegraph and
Telephone is an advisory committee established under the United
Nations to recommend worldwide standards.

1-6

W15

ROCKER
SWITCHES

W13

w12

PRIORITY

RECEIVER

TRANSMITTER

CHIP

W11

W10

W14

W16

PLUG
6843-2

Figure 1-4

DU11 Major Components

SIGNAL NAME is the proper name of the signal. The

names used on the print set are also used in this manual for
correlation between the two.

Interface signals fed to or received from the Bell 303

modem via the mounting panel backpanel wiring and
DF11-G level converter are preceded by the M7822 module
pin number:

POLARITY is either H or L to indicate the voItage level of

H
AF1 D6-DTR (1)

the signal: H means +3 V; L means ground.

1.6.2
For example, the signal

' D5- TX DONE H
originates on sheet 5 of the engineering drawings and is

read, “When TX DONE is true, this signal is at +3 V.”

Flip-Flop Signal Names

Flip-flop signal names add an extra d1mens1on Although
flip-flops have only two outputs, four signal names are
possible (Figure 1-5). The two real outputs are RX DONE
(1) H on pin 5 and RX DONE (0) H on pin 6. The two
additional outputs are simply the real outputs reidentified.
RX DONE (1) L is electrically the same as RX DONE (0)
H, and RX DONE (0) L is electrically the same as RX
DONE (1) H.

Unibus signal lines do not carry a SOURCE indicator. These
signal names represent a bidirectional wire-ORed bus; as a

result, multiple sources for a particular bus signal exist.
Each Unibus signal name is prefixed with the word BUS.

Y
—D
F/F

Interface signals fed to or received from the Bell 201
modem via the Berg connector on the M7822 module are
preceded by the jack and pin numberin parentheses:

—C
v

H
| S RX DONE (1)

- b& - Rx DONE (1) L

Ds— RX DONE (0) L
6
——— RX

DONE

(O)
H

11-2236

(J1-DD) EIA DATA TERM RDY (This signal is

Figure 1-5

shown on engineering drawing D6.)

1-8

Flip-Flop Signal Names

CHAPTER
2
INSTALLATION

21 INSTALLATION
2.1.1

Connect a wire between A02N2 and CXXUI,
where XX is to slot location of the M7822

Mounting the DU11 in the Computer

module.

There are two DU1 1 installation configurations:

The

standard

NOTE

in which the;_u,v -

configuration,

~ Jumper W16 must not be installed if the

DU11-DA interfaces with the Bell 201 syn-

DU11 is being installed in the DDll B

chronous modem or equ1valent

mounting panel.

The current mode cOnflguratlon in lwhjch the = o
- '2’.'14-.1'."2 Current 'Mode | Configutation' ‘—_I‘n this configu-

DUI11-EA interfaces with the Bell W1de band’_.* ‘ration, the DUI1-EA must be installed in the DD11-B
303 modem or equivalent.
| mountmg panel as shown1n F1gures 2-4 and 2-5.
|

2.1.1.1 Standard Configuration—- In this c'onfigUrationl,' |

NOTE

the DU11-DA can be mounted in the small peripheral

The DD11-A mountmg panel cannot be usedin

- controller slot in the PDP-11/05, 10, 35, 40, 45, and 50

o the current mode configuration because it will

processors or in any one of four slots in the DD11-A or

DD11-B peripheral mounting panels (Flgure
DD11-A mounting

~_not accommodate the DF11- G level converter.

2-1). The

panel (Figure 2-2) is used in the

2. l 2 Installmg the Modem CableHarness
A different cable is required to connect the DU11 to the |

PDP-11/15 and 20 computers, while the DD11-B (Figure

2-3) is used in the PDP- 11/05 10 35 40 45, and 50‘»
computers.

The DU11-DA cannot be mounted in the small

[

TM~

NOTE=@

Bell 201 modem than to the Bell 303 modem. The
BCO5C-25 cable harness (Figure 2-6) is used for the
DUI1-DA configuration; the BCO1W-25 cable harness

peripheral controller slotin the PDP11/15 and
20 processors.

| DDl 1-A and DD11-B mo,Unting.reqfiireme’nts"are somewhat
different. When using the DD11-B mounting panel, the

- (Figure 2- 7)is used for the DU11-EA configuration.

H'.To mstall the cables refer to F1gure 2-8 and proceed as
follows

Berg

converts the full-wave rectified +8 V‘/rm‘s mounting panel

Install the G8000 module in slot AO2 of the

- Connect a wire between AO3V2 and AO2V2.

DD11-A.

the

DUl

module

Align the Cinch connector (DU11-DA configuration) or the Burndy connector (DU11-EA

proceed as follows:

connector

(DU11-DA configuration) or the DF11-G
connector module (DU11-EA configuration).

bypasses a voltage dropping resistor and the G8000 module

the EIA level converters. To 1nstall the G8000 module,

Position the Berg connector such that the
- connector name and pin number markings are
visible and mate it fully and squarely with the

DU11 is simply installed
in the mounting panel; however,
when using the DD11-A, jumper W16 (engineering drawing
D1) and module G8000 must also be installed. Jumper W16

input signal to a positive dc voltage which is used to drive

configuration) to the receptacle located on the
rear of the modem.

Mate the connector and tighten the two holddown screws using a screwdriver.

LLNa
3TNA
(€28LINON)

3naow -

(SNAaiNNV-1 09)

SDLHD3IgNHODL)D3IWN3NAQODW

(31avd ~

(LNVHDALINILNOD 0E6MN)~
(LeL9)

2-2

v-£v89

SECTIONS

MODULE SIDE VIEW
11-2237

*GRANT Continuity Module (G727) must be installed in each slot that does not receive an interfadé

logic module.

NOTES:

1. Can be mounted in slots 1,2,3,0r4
2.

Can be M920 or BC11-A

3. Can be M920,BC11-AorM930

Figure 22 DU11-DA (M7822 Module) Mounted in DD11-A
SECTIONS

///
ULE/{///NOT5/77////////////// |
//M/ T///e z/////Q{fJ A D/M///
/7 //%//% /
/ ///

‘ :v

cLots 2

MODULE SIDE VIEW
:

.
11-2238

*¥*Grant Continuity Module (G727) must be installed in each slot that does not receive an interface logic module.
NOTES:

1. Can be mounted in slots 1, 2, 3, or 4
2.

Can be M920 or BC11-A

3. Can be M920, BC11-A or M930

Figure 2-3

DU11-DA (M7822 Module) Mounted in DD11-B

2-3

LELER

dOL1I3IN OD

S1J3INOD)OlIW3AOW
dO1I3NNOD
ITNAON

O-L140

3T7NAON

SECTIONS

(NOTE 2)

///
//
///////////

// ‘

MODULE SIDE VIEW
11-2239

*Grant Continuity Module (G727) must be installed in each slot that does not receive
an interface logic module.
NOTES:

PWON=

" Can only be mounted in slots2or3

The DF11-G connector and converter must be mounted in the same slot as the M7822 module
Can be M920 or BC11-A

Can be M920 BC11-A or M930

Figure 2-5 DU11-EA (M7822 Module and DF11-G Converter) Mounted in DD11-B
Unibus and Interrupt Vector Address Assignments
The Unibus and interrupt vector addresses must be deter2.1.3

" mined prior to operating the DU11. The Unibus address is

switch selectable; the interrupt vector addresses are jumper
selectable (Figure 14 for physical location).

to as the device address)
The Unibus address (also referred
is controlled by ten rocker switches located in the address

The interrupt vector addresses are also floating and are

established at the factory in accordance with the vector
addressing scheme described in Appendix B. If it is
necessary to change the vector address, simply change
jumpers W9—W14 as required. Jumpers are cut to obtain a
logical zero. Jumpers W9—W14 are located in the interrupt
control logic (engineering drawing D4). These jumpers

control vector address bits 08—03; hence, vector addresses

can be generated within the range of 000 to 774; however,

‘selection and mode control logic. The position of these
the required address state (0 or 1) of
switches determines

software requires that the vector address fall within the
floatmg address range of 300 to 777.

bus address bits 12—03. If a rocker switch is set to ON, the

switch contacts are closed and an address state of O is

required on the related address bit to address the DUII.
Hence, electrically the DU11 can have any device address
within the range of 760000 to 777777; however, Digital

NOTE

If a vector address is selected which falls

outside the floating address range, the software

Equipment Corporation software requires that the device

address fall within the floating address range of 760010 to
763776. Refer to Appendix B for a complete dlscussmn of

must be modified accordingly.

DU11 address assignments.
2:1.4

Jumper Assignments

NOTE

" Jumpers are used at various points in the DU11 circuitry to

If a device address is selected which falls

increase flexibility and to meet the floating vector address

must be modified accordingly.

description of the DU11

- outside the floating address range, the software

requirement described in Appendix B. For a complete

2-5

jumpers, refer to Table 2-1.

25 FT HARNESS

MALE

CINCH

CONNECTOR

(DB-51226-1)

(CONNECTS TO

FEMALE

BERG

(CONNECTS TO

MODEM)

DU11 MODULE)

CONNECTOR

(DEC NO. 1209941)

6808-3

Flgure 2-6

BCO5C-25 Cable Harness Used to Connect DU11 DA to

Bell 201 Modem

2.1.5 Priority Assignment

2.2 INITIAL TESTING
|
|
The DUI1 must be tested prior to placing the unit into

The priority level is determined by the priority plug located
on the DUI1 module. The DU11 normally has a priority

operation.

level of BR5. However, the priority may be changed by

For

engineering

specification,

simply replacing the BRS plug with a plug wired for a

vided with each DU11 delivered.

initial

test

procedures, refer

A-SP-DU11-0-4,

which

to the
is pro-

different priority level.
|

NOTE

Before running diagnostics on interface model
DU11-DA,

NOTE

disconnect

the

modem

cable

(BCO5C-25) from the rear of the modem and

If the priority level is changed, the software

install the modem test connector as shown in

must be modified accordingly.

Figure 2-9.

2-6

25 ft

HARNESS

CONNECTS
CONNECTSTO

TO DU11

MODEM

MODULE

MALE

FEMALE

BURNDY

BERG

CONNECTOR

(DEC NO. 1209941)
6843-1

Figure 2-7

BCOlWZSCable HarnessUsed to Connect DU11-EA to

Bell
303 Modem

-MALE BERG CONNECTOR

S22 .2
S22 .

MALE

CINCH

S2e/l |/~ FEMALE BERG CONNECTOR \

|Em=

BCO5C-25

CONNECTOR

BELL 201 MODEM

(]

CABLE

(REAR)

DUl M7822 MODULE

CINCH CONNECTOR
FEMALE

N I
I
a. DUI{-DA CONFIGURATION

MALE
FEMALE

BURNDY

BERG CONNECTOR

CONNECTOR

BELL 303 MODEM

G (++++- <) (REAR)
BCO1W -25 CABLE
MALE BERG

CONNECTOR

FEMALE BURNDY CONNECTOR

CONNECTOR
MODULE

b. DUi{—-EA

CONFIGURATION
11-2333

Figure 2-8 DUI11 to Modem Connection
~ MODEM
—— CABLE

(BCO5C-25)

CINCH
CONNECTOR

INSTALL CINCH
CONNECTOR
HERE

MODEM

)

TEST
CONNECTOR

)

6808-2

Figure 2-9 Modem Test Connection Installation

2-8

~ Table 2-1
- Jumper Assignments

J umper No. and Location

Normal Configuration

Function

- W2/D5

Removed

This jumper may be installed to enable the receiver to

synchronize internally upon receiving just one sync
character, thereby negating the normal requirement of

receiving

two

contiguous sync characters to achieve

synchronization in the internal synchronous mode.

W4/D6

Installed

This jumper may be removed to disable CLR OPT L

(Clear Option), thereby preventing clearing of bits 03,
02,

and

in the RXCSR (see Chapter 3 for bit

descriptions and Chapter 4 for signal functions).

W5, W6/D6

Installed

- These jumpers

may

removed

disconnect

the

secondary data channel between the modem and the
-DU11. Removed at customers request.

W9-W14/D4

Floating

These jumpers

control

the

receiver

and transmitter

interrupt vector address (Paragraph 2.1.3) bits:
Jumper -

Address Bit

BUS D03

‘W10

BUS D04

W11

- BUS D05

W12

BUS D06

W13

W14
W15/D4

Installed

-BUS D07

BUS D08

This jumper may be removed to inhibit the BUS NPR L
input to the interrupt control logic. (Removed only if

PDP-11/20 processor is used without KH option.)

Wi16/D1

This jumper must be installed if the DU11 is mounted in

Removed

DDI11-A

2.1.1.1).

peripheral

mounting

panel

(Paragraph

CHAPTER
3
DEVICE REGISTERS

AND INTERRUPT REQUESTS
3.1

SCOPE

facilitate the programmer’s understanding of the purpose of

This chapter provides a complete description of the DU11

each register relative to interface operation and to simplify

device registers and the interrupt requests employed to

software preparation.

service those registers.

3.2.2.1 Title Assignments — Register titles and functions
3.2

are listed below:

DEVICE REGISTERS

All software control of the DU11

is performed by means of

five device registers. These registers have been assigned bus

addresses and can be read or loaded (with the exceptions

RXCSR
— programmed and monitored (read/

write) to control the RCVR (receiver) portion
of

noted) using any PDP-11 instruction referring to their
addresses.

the

interface;

status, requests,

Address assignments can be changed via the

communicate

interface

and supervisory data to the

modem; and to monitor status and supervisory

rocker switches to correspond to any address within the

data inputs from the modem.

floating address range of 160010 to 163776.

b.
3.2.1

RXDBUF — monitored (read only) to detect
interface RCVR status flags and RCVR parallel

data outputs.

The five device registers and associated DU11 addresses are
listed in Table 3-1.

~¢c.

PARCSR — programmed

(write

only)

establish the overall operating parameters of the
DU11, i.e., the mode of operation (synchro3.2.2

nous or isochronous), word length (5, 6, 7, or 8

Each of the five device registers plays a specific role
in

bits plus parity), parity (enabled or disabled),

controlling and monitoring DU11 operation. Register titles,

parity sense (odd or even), and sync character

bit titles, and read/write capability labeling are intended to

configuration.

Table 3-1
-

DU11 Register Address Assignments

Mnemonic

Address

Program Capability

Receiver Status Register

RXCSR

16XXX0

Receiver Data Buffer

RXDBUF

16XXX2

Parameter Status Register

PARCSR

16XXX2

Transmitter Status Register

TXCSR

16XXX4

Read/Write

Transmitter Data Buffer

TXDBUF

16XXX6

Write Only

Read/Write
-

Read Only

- Write Only

XXX = Selected in accordance with floating device address scheme described in Appendix B.

3-1

— programmed and monitored (read/
TXCSR
write) to control the XMTR (transmitter)

The following figures and tables describe register content.

control and monitor the maintenance mode

The mnemonic INIT is used frequently in the following

Figures 3-1 through 3-5 illustrate the register formats.
Tables 3-2 through 3-6 list bit descriptions.

portion of the interface, to control the resetting
and initialization of the interface, and to
operation of the interface.

tables and refers to the initialization signal generated by the
processor. The processor will issue an INIT signal for any

TXDBUF — programmed (write only) to pro-

one of the following conditions:

vide parallel data to the interface XMTR for

~a. . A programmed RESET instruction is processed.

serial transmission to the modem.

DATA

During a power fail sequence, INIT is asserted when poWer
is going down and again when power is coming up.

CLR [car-| rec | SEC

The power fail sequence occurs.

attempts to program the “not used” bits or “read-only”
bits have no effect on the bit.

The processor START switch is pressed.

3.2.2.2 Bit Assignments — The bit names indicate the
function of the bit. The bits that are defined as “not used”
or “write-only” are always read as 0. In the same respect,

[DATA[srripl

©O06

rx | mrx

|PATA|

R/W

.00

scu | SEC | REQ | DATA | yot

R
|

R/W
|

R/W

R/W
|

R/W

11-2244

Figure 3-1 Receiver Status Register (RXCSR)

Bit

Table 3-2

Receiver Status Register Bit Description

Name

DAT SET CH

(Data Set Change)
.

Description

- When set, this bit indicates a modem status change.

This bit is set by a transition of any of the following lines:
®

Ring

® (lear To Send
®

C(arrier

® Secondary Received Data
® Data Set Ready

If bit 05 of this register is set, the setting of this bit will cause

a RCVR interrupt.

Read-only bit;'cleared by INIT, Master Reset, and the DTI

‘SEL 0 (RXCSR read strobe).

RING
(Ring)

This bit reflects the state of the modem Ring line. When set,
this bit indicates that a Ring signal is being received from the
modem. Read-only bit.

3 -2

Table 3-2 (Cont)
Receiver Status Register Bit Description

Bit
13

Name

Description

CLR TO SD

‘This bit reflects the state of the Clear to Send line from the

(Clear to Send)

modem. When set, this bit indicates that the modem is on and
ready to accept data from the interface for transmission.
- Read-only bit.

CARRIER

This bit reflects the state of the modem carrier. When set, this

(Carrier)

bit indicates the Carrier is up. Read-only bit.

REC ACT

When the internal synchronous mode is selected, this bit is set

(Receiver Active)

when the proper number of contiguous sync characters (either

1 or 2, normally set for 2) have been received. If external
synchronous or isochronous mode is selected, this bit follows

the state of the Search Sync bit (bit 04 of this register). See

Paragraph 5.3 for RCVRsynchronization information.

Read-only; cleared by INIT, Master Reset, and SCH SYNC'(I)
H (Search Sync) making 1 to O transition.
10

This bit reflects the state of the Secondary Recelve Data line

SEC RCV DAT

- (Secondary Receive Data)

from the modem

This bit provides a receive channel for supervisory data from
the modem to the processor. Read-only b1t
09

DAT SET RDY

This bit reflects the state of the Data Set Ready linevfrom the

(Data Set Ready)

modem. When

set,

this bit indicates that the modem is

powered up and ready to transmit and receive data. Read-only

| - bit.
08

STRIP SYNC

This bit determines whether sync characters received from the

- (Strip Sync)

modem are to be presented to the program for reading. When
this bit is set, receive characters that match the contents of the

Sync register. do not cause a RCVR interrupt provided no

errors are detected, i.e., bit 15 of the RXDBUF is clear.
Read/wnte bit; cleared by INIT and Master Reset.

RX DONE
(Receiver Done)..

This b1t is set when synchronlzatlon has been achleved and a
character has been loaded into the RXDBUF, provided the

~ STRIP SYNC bit is not set. If the STRIP SYNC bit is set and
the received character is a sync character without errors, i.e.,

‘bit 15 of the RXDBUF is clear, this bit will not be set.

When set, this bit will cause a RCVR interrupt request
provided bit 06 of this register is set.

//_~\\

Read-only bit; cleared by INIT, Master Reset and the DTI

SEL 2 (RXDBUF read strobe).

3-3

Table 3-2 (Cont)

Receiver Status Register Bit Description
Bit

Name

Description

RX INTEB

(Receiver Interrupt Enable)

When set, allows a RCVR interrupt request to be generated
when the RX DONE bit is set.

Read/write bit; cleared by INIT and Master Reset.
05

DAT SET INTEB

(Data Set Interrupt Enable)

~ When set, allows a RCVR interrupt request to be generated
when the DAT SET CH bit is set.

- Read/write bit; cleared by INIT or Master Reset.

SCH SYNC

When set in the internal synchronous mode, enables the RCVR

(Search Sync)

synchronization logic and causes the RCVR to start comparing
‘incoming data bits to the contents of the Sync register in an

attempt to recognize a sync character.

When set in the isochronous mode, enables the RX DONE flag - generation logic.

When set in the external Synchronous mode, enables the RX
DONE flag generation logic and causes the RCVR to start
framing incoming characters.

Read/write bit; cleared by INIT and Master Reset.

SEC XMIT

(Secondary Transmit Data)
|

This bit reflects the state of the Secondary Transmit Data line
to

the

modem. This bit provides a transmit channel for

supervisory data from the modem to the processor.

- Read/write bit; optionally cleared by INIT or Master Reset.
02

REQTOSD

When set, this bit causes the Request to Send line to the

(Request to Send)

modem to be asserted. The Request to Send line is a control

lead to the modem. This line must be asserted before the
interface can transmit data.to the modem.

Read/write bit; optionally cleared by INIT and Master Reset.
DATA TERM RDY

When set, this bit indicates the interface is powered up,

(Data Terminal Ready)

programmed, and ready to receive data from the modem.
Setting this bit causes the Data Terminal Ready line to the
modem to be asserted. The Data Terminal Ready line is a
control lead for the modem communication channel. When
asserted, it permits the interface to be connected to the

‘Read/write bit; optionally cleared by INIT and Master Reset.

channel.

|OVRN|

{

«—————»
08

FRM | PAR

err | ERR | ERR | ERR

NOT USED

07+

+ 00

RCVR DATA

— READ ONLY ————

|
11-2240

Figure 3-2 Receiver Data Buffer (RXDBUF)

Table 3-3

Receiver Data Buffer Bit Description
Bit

Name

Description

RX ERR

This bit is set whenever one of the three receiver error bits is set (logical

(Receiver Error)

OR of bits 14, 13, and 12).

Read-only bit; cle'ar‘ed only when bits 14, 13, and 12 are cleared.
14

OVRN ERR

When set, this bit indicates that the processor has failed to service the RX

(Overrun Error)

- DONE flag within the time required to load another character into the

RXDBUF, i.e., (1/baud rate) X (bits per character) seconds. Hence, the
-previous character was over-written (lost).
Read-only bit; cleared by INIT, Master Reset, and DTI SEL 2 (RXDBUF
read strobe).

FRM ERR

When set, indicates that character received was not followed by a valid

(Framing Error)

STOP bit. This error only occurs in the isochronous mode of operation..
Read-only bit; cleared by INIT, Master Reset, and DTI SEL 2

- PARERR

‘When set, indicates that the parity of the received character does not agree

(Parity Error)
|

with the parity programmed (odd or even). If parity is not programmed,

this bit is always cleared.

~ Read-only bit; cleared by INIT, Master Reset, and DTI SEL 2.

07—-00

RCVR DATA

(Receiver Data)

This register holds the received character for transfer to the program. The
-

buffer is right justified for 5, 6, 7, or 8 bits. If parity is received it is also

loaded into the buffer at the next vacant higher order bit position.
-

Therefore, if a 5-bit character plus parity is framed by the RCVR, the

‘parity bit would be loaded into bit position 05 in the RXDBUF and
presented to the program for reading. If an 8-bit character plus parity is

framed, the parity bit would not be presented to the program for reading.

Read-only buffer; cannot be Cleared, INIT or Master Reset sets the buffer
to all ones.

3-5

10
ORD

L\gglEGLTH

ngel POy

-> 0]6)

O7<=
|

PAR

SYNC REGISTER

A SEN
—

ol
-

WRITE ONLY

41
11-22

Figure 3-3 Parameter Status Register (PARCSR)

Table 3-4

Parameter Status Register Bit Description

Bit

13 and 12

Description

Name

MODE SEL
(Mode Select)

These bits control the mode of operation. Modes-are selected as
|
|
|
follows:
- Mode
Internal Synchronous
External Synchronous
Isochronous

Bit 13

Bit 12

1
1

1
0

Any other mode select bit combinations will produce errors in
the interface.

Write-only bits.

11 and 10

WORD LEN SEL

(Word Length Select)
»

These bits control the length of characters received and

transmitted by interface. Word length (not including parity) is
|

selected as follows:

Bits per Character
5
|

Bit 11
0

7
8

1
1

Bit 10
-0
1
0
1

Write-only bits.

PAR ENB
(Parity Enable)
|

If this bit is set, parity will be generated by the XMTR and
checked by the RCVR. If character length is less than eight bits,

the parity bit is loaded into the RXDBUF for reading by the

program. If bad parity is detected at the RCVR, the parity error
flag is set (bit 12 of the RXDBUF).

Write-only bit.

3-6

Table 3-4 (Cont)

Parameter Status Register Bit Description

Bit

“Name

- Description

PAR SEN SEL-

" When the Parity Enable bit (bit 09 of this register) is set, the

(Parity Sense Select)

- sense of the parity (odd or even) is controlled by this bit. When

this bit is set, even parity is generated by the XMTR and checked
for by the RCVR (the program does not have to provide a parity
bit to the XMTR). When this bit is cleared, odd

parity is

generated and checked
‘Write-only bit.

07-00

Sync Register "

- This register contains the sync character. The sync character is
used by the RCVR to detect received sync characters and thereby

achieve syachronization

- The sync character is used as a fill character by the XMTR when
~operating in

the

synchronous

mode.

Fill characters

transmitted when the program fails to provide characters to the
XMTR fast enough to-maintain continuous transmission, i.e.,

(1/baud rate) X (bits per character) seconds - 1/2 (bit time).

(A
\

15
14 13
12
w10 09 08 07
06
ImainT| ss | ms | ms | rRx | NoT|MsT | Tx | Tx

05
|oONa

R/W

ONA 'oata | cix | o1 | 0o | Inp |useD | RST
R/W

R/W

R/W .

|BREAK

R/W

03
HALF

R/W

"R/W
1t-2ea42

~ Figure 3-4 Transmitter Status Register (TXCSR)
(/'

- .Bit

15
.

Table 3-5

Transmitter Status Register Bit Description
- Name

Description

DNA

This bit is set by the XMTR when a fill character is

(Data Not Available) -

‘transmitted. This applies only to the synchronous mode of

operation and is caused by late program response to a TX
'DONE interrupt request.

The processor response to TX DONE must be within
~(1/baud

rate) X (bits

per

character) seconds- 1/2 (bit

~time). If not, the fill character is transmitted.

If bit 05 of this register is set, setting this bit causes an
- XMTR interrupt request.

B Read only bit; cleared by INIT, Master Reset, and DTI SEL

. 4 (TXCSR read strobe)

3-7

Table 3-5 (Cont)
Transmitter Status Register Bit Description

Bit

Description

Name -

This bit is used in the internal loop and external loop

MAINT DATA

maintenance modes by the diagnostic program to simulate

| -(Meintenance Dat

an input to the RCVR. Refer to Chapter 6 for more
detailed information on the use of this bit.

Read/write bit; cleared by INIT and Master Reset. -

This bit is used in the internal loop and external loop

SS CLK

- maintenance modes by the diagnostic program to simulate
the XMTR and RCVR clocks. Refer to Chapter 6 for more
» detailed information on the use of this bit. |

(Single Step Maintenance Clock)

fiead/write bit; cleared by INIT or Master Reset.
of operation
These bits are used to select the normal mode
or one of three maintenance modes. Modes are selected as

MSO01/MS00

12and 11

(Maintenance Mode Select 01 & 00)
-

foll'ow_s:
R

—

External Maintenance Loop

Bitll

~System Test

—_—O
= O

Bit12
|
1
OO

|
Mode
_.
Normal
Internal Maintenance Loop

Refer to Chapter 6 for more de’tailedvinformatio.n on the

maintenance modes-and their use.

- Read/write bits; cleared by INIT and Master Reset.
10

RX INP

This bit monitors the RCVR input in the internal loop and

(Receiver Input)

external loop maintenance modes.

| | Read-only... .

This bit is used to .generate a CLR (Clear) pulse, which

MSTRST

the registers and the XMTR and RCVR and
initializes

(Master Reset)

inhibits the BUS SSYN L (Slave Sync) signal. Refer to
Chapter 4 for more detailed information on the effects of
|

the CLR pulse.

- Write-only.
07

TX DONE

(Transmitter Done)

‘This bit is set by INIT and Master Reset and when the first
bit of the character contained in the XMTR register is

placed on the XMTR output line. If bit 06 of this register is

| set when this bit is set, an XMTR interrupt request is
| generated.

'Read-only bit; cleared by LD TXDBUF (TXDBUF load

- strobe).
3-8

Table 3-5 (Cont)
Transmltter Status Reglster B1t Descrlptlon

- Bit

Name

De,scrip tion

| When set, this b1t allows an XMTR 1nterrupt request to be

TXINTEB

- (Transmitter Interrupt Enable)

“generated by the TX DONE bit.

Read/Wrrte brt;_'cleared by INIT and Master Reset.

DNA INTEB

When set, this bit allows a XMTR interrupt request to be

(Data Not Avfiilable Interrupt Enable)| generated by the DNA bit.
Read/write bit; cleared by INIT and Master Reset.
| SEND

When set, this bit enables the XMTR and transmission will

(Send)

start when a character is loaded into the TXDBUF. This bit

must remain set until the entire message:
is transmitted. If
not, transmission of the character currently in the XMTR
register is completed and the XMTR will enter the idle
state.

Read/write bit ; cleared by INIT and Master Reset.
03

HALF DUP

When: this bit is set, operation will be in the half duplex

(Half Duplex)

mode. In this mode the RCVR is disabled whenever b1t 04 -

of this regrster is set.

Read/wrrte brt cleared by INIT and Master Reset
00

When thrs bit is set the serral XMTR output is held in thev -

~ BREAK(Break)

space (constant LOW) condition; otherwise, operation is
normal. This bit is used by the diagnostic program in the

internal loop or external loop maintenance modes to inhibit
the XMTR output while inputting data to the RCVR via bit

14 of this register.
Read/write bit; cleared by INIT and Master Reset.

> 08

NOT USED

> 00
XMTR DATA

‘WR

R E ONL Y

11- 2243

Figure 3-5 Transmitter Data Buffer (TXDBUF)

3-9

Table 3-6
Transmitter Data Buffer Bit Description

Bit
07',“00;

:}»Nam.‘e; o

Description |

- XMTR DATA -

" This Treg’ister is loaded by the tp’rog‘ram With the character to be |

(Transmitter Data)

transmitted. Character length is from 5 to 8 bits. The character is
right-hand justified. If a parity bit is programmed, it is generated by
the interface.
|

3.3

Write-only bits; an INIT or Master Reset places all ones in this

_register.

INTERRUPT REQUESTS

The DU11 uses BR interrupts to gain control of the bus and
cause a program interrupt, thereby causrng the processor to

‘The standard DUI11 interrupt priority level is BRS.
- However, the priority level can be changed by replacing the
‘priority plug.

branch to a subroutrne a

The interface uses two -interrupt vectors: one for the
RCVR section and one for the XMTR section. If simultaneous RCVR and XMTR 1nterrupt requests occur, the
RCVR has priority.

- The DU11 interrupt vector addresses are floating. Floating
vector addresses are used for all options and are assigned
according to the scheme described in Appendix B. The

vector addresses can be changed via jumpers W9-W14 in

~ the interrupt control logic.

Both the XMTR and RCVR sections of the interrupt
control logic handle interrupt requests from two sources. A XMTR interrupt request is generated by the setting of the

TX DONE bit or the DNA bit provided the TX INTEB and

‘the DNA INTEB bits are set.A RCVR interrupt request is

NOTE

If the DU11 priority plug or an interrupt vector

~address is changed, all DEC programs or other

generated by setting the RX DONE bit or the DAT SET CH

software referring to the standard priority level

set.

changed.

or interrupt vector addresses must also be

bit, provided the RX INTEB and DAT SET INTEB bits are -

3-10

CHAPTER 4

THEORY
OF OPERATION

4.1

b. . _ConVerts serial data inputs (from the modem)

SCOPE

This chapter provrdes a detailed descrrptron of the DUI11
interface.

The

description is

functional

description

to parallel outputs (to the computer).

provided in two parts: a

and a detailed logic description.

Discussions make frequent reference to the DU11 Engi-

Inhibits RCVR (receiver) operation when trans-

mitting in the half duplex mode.

neering Drawmg Set provrded with each DU11.

d.
42

Establishes synchronization prior to allowing

F UNCTIONAL DESCRIPTION

The DU11

received data
to be transferred to the computer.

is a single line, program controlled, double

buffer communication interface. The purpose of the DU11

interface is to establish a data communication line between
a PDP-11 computer
(a parallel input/output device) and a

mterface is capable of

handhng synchronous and 1sochronous com-

handling variable length characters (5, 6, 7, or 8

bits plus parity)

'®

with

the

data character to the

modem

data received from the
|

for transmrssron

modem status 'change

Sync (fill) character being transmrtted to

Provides

control

signals to the modem and

verifying received character parity (odd or

4.2.1

even)

Before the DU11 interface can begin to handle data, it must

for mamtenance purposes.

Initialization and Programming |

be 1mt1ahzed and programmed

: Inrtralrzmg the interface prepares it to be programmed. All
registers are mrtrahzed all flip-flops are cleared, and the

controlling the modem.

In line with these capabilities, the mterface performs the
followmg Operatrons

followmg con-

monitors modem status lines.

inhibiting the XMTR (transmrtter) data output
-

of the

the modem.

'generating a‘parity bit (odd or e\'/'en)’whjoh is
~transmitted

one

XMTR ready to accept another character
-

operating' in half duplex or full duplex mode

any

modem

synchronized
-

mumcatlon data

response

drtrons

“Bell 201 or 301 modem (a serial input/output device). The

Generates interrupt requests to the program in
|

Converts parallel data mputs (from the computer) to serial data outputs (to the modem)

RCVR and XMTR are forced to the idle state. When the
RCVR is in the idle state, the RXDBUF (Receiver Data

Buffer) is set to all 1s, the RCVR Sync register is cleared,
and the RCVR timing and control logic and output flags are
cleared. When the XMTR is in the idle state, the XMTR
output is a constant MARK (HIGH), the XMTR timing and

control logrc is cleared, and the XMTR output flags are set.

4.1

Programming the DU11

When modem no. 2 places a call to modem no. 1:

establishes its operating param-

eters. General operating parameters are controlled by the

PARCSR

(Parameter

Status

while

specific

Modem no. 1 asserts RING to DUI1 no. 1.

DUILI1 no. 1 asserts DATA TERM RDY (Data

~ operating parameters pertaining directly to the RCVR,
XMTR, and maintenance circuitry are controlled by the

Terminal Ready).

RXCSR (Receiver Status Register) and the TXCSR (Trans-

mitter Status Register). The PARCSR is programmed to
select

the

mode

operation (isochronous,

internal

Modem no. 1 sends CARRIER to modem no. 2. |

Modem no. 2 asserts CARRIER to DU11 no. 2

synchronous, or external synchronous), word length (5, 6,

7, or 8 bits plus parity), parity (enable or disable), parity

and sends CARRIER back to modem no. 1.

sense (odd or even), and sync character configuration. The
RXCSR is programmed to enable or disable the RCVR data

handling logic, strip sync logic and interrupt logic, and to

communicate interface status, requests and supervisory data

to the modem. The TXCSR is programmed to select the

maintenance mode (normal, internal loop, external loop,

Modem no. 1 then asserts CARRIER to DU11

no. 1 and the SCH SYNC (Search Sync) bit is
" set at DU11 no. 2 to enable the RCVR

“f.

and system test); drive the maintenance clock; provide a

DUI11 no. 1 asserts. REQ TO SD (Request to
Send) to modem no. 1.

maintenance data input; reset and initialize the overall

interface; enable or disable the XMTR data handling logic,
g.

data output logic, and interrupt logic; and select the

Modem no. 1 asserts CLR TO SD (Clear to

Send) to DU11 no. 1

interface duplex mode (half or full).

Once these three registers are programmed, DU11 operation
can begrn Assuming the RCVR and XMTR data handling
and interrupt logic is enabled, the XMTR will begin
outputting serial characters when a characteris loaded into

the TXDBUF (Transmitter Data Buffer) and the RCVR will
begin accepting serial characters when they appear on the
~

The SEND and TX INTEB (XMTR Interrupt
~

Enable) bits are set at DU11 no. l to enable the
XMTR.

Note that the modem DATA SET RDY (Data Set Ready)

line.

output must be asserted before any data communication
can actually take place. The DATA SET RDY line indicates

4.2.2 Handshakmg Sequence |

Handshaking sequences serve to establish the data communication channel. This becomes necessary when the inter-

that the modem is powered up and conditions are go.

to something other than a modem, e.g., a limited distance
be required; the program
adapter, handshaking may not
simply initiates data communication by loading a character

with the normal communication data. The SEC XMIT

face is connected to a modem. If the interface is connected

Supervisory data may also be transmitted simultaneously

(Secondary Transmit) and SEC REC (Secondary Receive)
lines provide a supervisory data communication channel.

‘into the TXDBUF.

All data communications can be terminated by simply

If a handshaking sequence is necessary, the program must

~ clearing the Data Terminal Ready bit in the RXCSR.

be written accordingly. The followrng paragraphs explain atyprcal handshaking sequence

4.2.3

The handshaking sequence is initiated when the modem at

Basic Operation

The basic operation flow diagram (Figure 4-3) provides a

one data communication station places a call to a modem at
another data communication station. A call may be placed

general description of communication systems using the
DUI11 interface. Only major steps are shown in an attempt

simply by pressing the modem RING button if only two
stations are linked in the communication system or

~to

give

the

reader

general

understandrng

of overall

interface operation.

drahng-up statron no. 1 on the modem at station no. 2 if

‘The DUI11 interface may be used in two basic c_onfigu-

o more than two statrons are linked.

rations: the long distance system which uses modems for

(Once initiated, the handshakrng sequence W111 be executed

- data transmission over telephone lines, and the local system

as programmed. Frgure 4-1 illustrates a DU11 to modem
interface; Figure 4-2 111ustrates the handshaking sequence

| ’whrch uses a limited drstance adapter (LDA) to link-up the
1nterfaces

4-2

DATA TERM

RDY

DATA TERM RDY

REQ

TO SD

<-REQ TO SD

SEC

XMIT

SEC XMIT

TO SD

CLR TO SD

RING

CLR
-

CARRIER

DU
PDP-1{

«—

INTERFACE

SEC

MODEM
# 1

REC

DATA

CARRIER

COMMUNICATION

MODEM

FACILITIES

#* 2

SEC REC-

SET RDY

DATA

RECEIVE DATA

SET RDY

DU
1
INTERFACE

e—s

PDP-1{

¥# 2

XMIT DATA

RECEIVE DATA

CLK

RX CLK

CLK

TX CLK

11-2332

Figure 4-1

DU11 to Modem Interface Diagram

RING H (DU11 No. 1)
o——

'DTR (0)

H (.Dun

No.j)

CARRIER

H (DUit No.2)

SCH SYN (1) H (DU11 No. 2)

CARRIER H (DU11

No.1)

RTS

(0)

(DU No.1)

CLR TO

(DUt1 No. 1)

SEND

(1)

H (DU11 No. 1)

INTEB
(1) H (DU1f No.t)

1-23n

Figure 4-2

Handshaking Sequence Timing Diagram

PROGRAM

COMPUTER

REQUESTED

TURNED-ON

PROGRAM

PROGRAM
LOADED NEXT

CHARACTER INTO

TXDBUF

LOADS PARALLEL

INTERRUPT

POWER

DUMNM

PROGRAM

POWERED-UP.

READS

SEND (1) H =1

AND INITIALIZED

RXCSR

XMTR ENABLED

TRANSMISSION
OF CURRENT
CHARACTER

COMPLETE

REC ACT

(1MH=1 RCVR
SYNCHRONIZED

RCVR FRAMES

CONTROL

XMIT SERIALLY

RING

SYNCHRONOUS

OUTPUTS CHAR-

BIT SET

REGISTERS
PROGRAMMED

ACTER AND

MODE OF

ASSERTS TX

OPERATION

THE CHARACTER,

TRANSFERS
IT

TO THE RXDBUF
AND ASSERTS

DONE H

RX DONE
(1) H

YES

PROGRAM

EXECUTES

ENTIRE -

HANDSHAKING

PROGRAM

MESSAGE -

SEQUENCE

~READS RXDBUF

LOADED INTO
TXDBUF

CHARACTER
“ FRAMED
DU11

PROGRAM

CONNECTED

INITIATES DATA
TRANSMISSION

TO MODEM

RCVR

RECEIVES

XMTR SERIALLY

INPUT DATA

ANOTHER

OUTPUTS SYNC

CHARACTER

CHARACTER TO

RECEIVED

MAINTAIN SYNCHRONIZATION
WITH RCVR

CHARACTER LOST
1--OVRN ERRH

0 SEND (1) H

]

Figure 4-3

Basic Operation Flow Diagram

e s,

11-2331

4.5

Referring to Figure 4-3, note that the interface is auto-

that the RCVR at the receiving station is synchronized with
the XMTR at the sending station. Once REC ACT (1) H

matically powered up and initialized when computer power
is turned on. The program also initializes the interface via

the

MSTRST

(Master

asserts,’the RCVR frames the very next character, transfers

bit in the TXCSR and

the character to the RXDBUF, and asserts RX DONE (1)

normally does so just prior to programming or reprogramming the control registers.

H. This assertion causes a RCVR interrupt request to be
generated. The processor branches to an interrupt service

Once the interface is programmed, data communication can

program

Reset)

subroutine

‘program or by the modem operator. The program initiates
simply by loading a

ultimately reads
to

read

the

RXDBUF. If the

RXDBUF

before the next
character is framed and transferred to the RXDBUF, the
character previously framed is lost and OVRN ERR H

commence. Data communication can be initiated by the

communication

and

fails

(overrun error) is asserted.

character into the

- TXDBUF. The XMTR then outputs that character to its

modem, which transmits it to the modem at a remote
station. The modem operator initiates data communication

4.2.4 Data Flow Analysis
|
As previously stated, the DU11 is a program controlled

by dialing a remote station on the modem. The modem at
the

remote

station

detects

the

call

and

communication interface capable of providing a full duplex

communication channel between a PDP-11 computer and a

asserting RING to its own interface. The interface then

Bell 201 or 303 modem. Because the interface is program

generates a RCVR interrupt, which causes the processor to

controlled, there are obviously two types of data flowing.
into and out of the unit: control data and communication

responds

branch to

an interrupt service subroutine. The service
- subroutine directs the processor to execute the handshaking
sequence and load a character into the TXDBUF.

- XMTR is enabled [SEND (1) H asserted], the XMTR begins
to output

the

character to the modem and asserts TX

DONE H to request the next character of the message. The
modem transmits the character to the modem that placed

the call. If more characters are to be transmitted, the
program responds to the TX DONE H flag and loads the

next character into the TXDBUF. When transmission of the

current character is complete, transmission of the next

character begins.

When

all

characters

data.

If the

comprising

the

“message have been loaded into the TXDBUF and TX DONE
H is asserted, the program clears SEND (1) H.

As soon as transmission of the current character is

complete, the XMTR output marks (Constant HIGH). Note
that TX DONE H will not change state after SEND (1) His

cleared.
If, during message transmission, the program fails to load
the TXDBUF before current character transmission is

424.1 Data Source and Destination
— Data is input to
the interface from two sources. The program inputs control

data and communication data to the interface via the
Unibus. The modem inputs communication data to the
interface via the modem cable. Communication data input
to the interface by the program for transmission can be

output immediately to

the modem. However, commu-

nication data received by the interface from the modem
cannot be presented to the program for reading until the

interface RCVR is synchronized with the incoming data.

4.2.4.2

Data Flow — Control data is loaded into the DU11

control registers (RXCSR, TXCSR, and PARCSR) and from

there controls the operation of the interface. Communication

data to be transmitted is loaded into the
TXDBUF; communication data received is loaded into the

RXDBUF (Figure 4-4).

complete, one of two operations will result, depending on

To program (load) the control registers, the program places
the A bits (register address bits), the C bits (bus operation

synchronous mode, a sync character will be output to
maintain synchronization with the RCVR (synchronous

control bits), and the D bits (control data bits) on the
Unibus. The A and C bits are applied to the address
selection and mode control logic. The D bits are applied to

mode is programmed, the XMTR will simply pause until the

TXCSR,

the mode of operation. If the XMTR is programmed for the

‘mode requires continuous transmission). If the isochronous
next character is loaded into the TXDBUF and then resume
operation.

Data reception is initiated when input data is provided to

the RCVR, provided SCH SYNC (1) H is asserted. Before

the RCVR can begin framing characters for reading by the

program, however, REC ACT (1) H must assert indicating

the bus receivers and from there routed to the RXCSR,
RCVR logic, and XMTR logic. The address

selection and mode control logic decodes the A and C bits

and

generates the required strobe to load the control
register addressed. If, for example, the PARCSR register is

addressed, the LD PARCSR (Load PARCSR) strobe is

generated and identical PARCSR registers in the RCVR

logic and XMTR logic are loaded. Once the control registers
are programmed, DU11 operation can begin.

SERIAL DATA
~
RXDBUF DATA
PARALLEL

OUTPUT
D<15:00>

BUS

DRIVERS

DATA

SCH SYNC

OUTPUT |RXCSR DATA

|e@

MULT
-

(D3)

PLExer

DAT — BUS

(D3)

DATA
@

PARCSR

ALO2
ALO

SCH- SYNC

RX CLK

STRIP SYNC

PARCT-'L

RCVR

|DATA

Logic

(D5)

‘

MAINT

‘.

DATA

]

,‘

MODE

(D5.D6)

SELECT

DTR (0) H

RTS

(0O)

EIA DATA TERM RDY

SEC TX (0O) H >

EIA REQ TO SD

EIA SEC XMIT-

BBSY INTR

RXINTEB
DAT

- (RXCSR) | RX DONE

SET

DAT

INTEB

(D5,06)

SET

eia UEVEL

[*+

MODEM

RING

( SEE

DATA

LR 10 5D

DONE

BELL 201

CONVERTER

PARCSR
RX

SERIAL

DATA IN

OUT

MAINT

‘

SK‘IQER> CEGISTER
s?%fis

BR REQ BGOUT

DATA |

1
RX DONE

FROM T XCSR

ATA

LOGIC

SERIAL

Txcsr

SERIAL

SELECT

STRIP SYNC

[

RCVR
INPUT

EIA

NOTE

EIARING

DATA
|

SET

23TN Sas

BBSY

INTERRUPT‘DAT e

DTI

|JX DONE

ONA

*UNIBUS

TX INTEB

DNA

" ADDRESS

INTEB

(D4)

MODE

ouT

SELECT

‘

BUS,

RCVR'S

CONTROL

(D3)

MSYN | LOGIC
(D2)

CLK

EXT
_

PARCSR DATA

xMTR
_ TO DATA OUTPUT

TTL SEC REC

TTL TRS CLK

‘
A

CLK

CLR

MAINT

LOGIC.
BUS

INIT |

(p2.06)

CLR

MODE

SELECT

MAINT DATA
OPT

’

cLock

LOG IC

LeveL

[+ *BELL 303

CONVERTER

fe—

MODEM

(SEE NOTE 2)

EXT

—

DTR (1) H

RTS (1)

SEC

TX TXx

H
(1)

NOTES:|

CLK
>

SEND
HALF

* DF11-G

CONTROL | REC CLK

(D5)

CLK

CLEAR

REC

SERIAL DATA OUT

}

TRS

TTL DATA SET RDY

)

CLRTO

TLL

]

RING

TTL CARRIER

(D5)

TTL

g MULTIPLE XER

[

}

BREAK

MAINT MODE
[ TXCSR DATA

DATAIN.
TTL

;

TTL SERIAL

TX CLK

RXINP

(TxcsR)

XMTR
LOGIC

TX DONE

STATUS
REGISTER

TXDBUF DATA

LD TXCSR

TXCSR DATA |

DNA

MSTRST

REC

EIA

‘|

®1

EIA

‘

SEND

XMIT DATA

;

EIA TRS CLK

:
TXDBUF

f
(05;06)

LD PARCSR

SELECTION
AND MODE

£17 SEC REC

EIA DATA SET RDY

;

CLK EXT

ADDRESS

‘>

SERIAL DATA

]

MSYN

MAINT

R
SSYN|

;

RXCSR

A<17:00>
,C <01:00>

SSYN

D<15:00> |

DATA SET RDY

CLRTO

EIA CARRIER

‘

VECTOR

‘

SEC REC

(D6)

SEL

EIA

DETECTOR [
CHANGE

CONTROL
Losic

CARRIER

1. Interface Model DU11—-DA consists of

DUP

the Bell
2.

(D5)
.

* NOT PART OF DU11

t he '\M7822 Module and interfaces with
201 Modem.

Interface

Model

DU11-EA

consists of

the

M 7822 Module and the DF11-G level converter
and;interfaces

with the

Bell 303 Modem.

Wide Band

11-2321

)]

|
|

| |

Figure 4-4

DUI11 Functional Block Diagram

The program can now initiate data transmission by loading
a character into the TXDBUF in the XMTR logic. To load
- the TXDBUF, the program places the proper A and C bits

and the character to be transmitted on the Unibus. The
address selection and mode control logic decodes the A and

C bits and generates the LD TXDBUF (Load TXDBUF)
strobe to load the character into the TXDBUF. The XMTR

then outputs the character serially to the modem. The

character is transmitted by the modem at the transmitting

station to the modem
at the receiving station. Assuming the
RCVR

synchronized,

the

RCVR frames

the

serial

character and raises the RX DONE output, which causes a | |
RCVR interrupt request and the interrupt vector address to

sent to the

processor.

The

processor responds by

branching to a interrupt service subroutine and reading the
RXCSR to determine the nature of the interrupt. Upon

determining

that

DONE

interrupt

has

been

requested, the program places the RXDBUF A bits and

4.2.5.2

Address Selection and Mode Control Logic — The

address selection and mode control logic decodes the A and

C bits placed on the Unibus by the program and generates

the gating and strobe signals necessary to perform the
operation decoded. Upon receiving the A and C bits, the

logic decodes the bits and generates strobes to load data
from the Unibus into the RXCSR, TXCSR, PARCSR, or

TXDBUF. The A and C bits are also decoded to select the

data output multiplexer output via the DAT - BUS (data
- to bus) and ALO2 and ALO1 (address lines) control signals.

The BUS SSYN (Bus Slave Sync) line to the Unibus is

raised to signify completion of transfer. The MSYN (Master

Sync) input is asserted by the program whenever it

| addresses a Umbus device.

4253 Receiver Status Register (RXCSR) — The RXCSR
stores control data for the RCVR section of the DU11 and

DATI bus operation C bits on the Unibus. The address

also monitors modem control lines and RCVR interrupt

selection and mode control logic decodes the A and C bits

~ requests. The RXCSR is a 16-bit read/write register that can

and enables the RCVR output to the data output multi-

be programmed by word or byte (high or low).

plexer and the bus drivers, thereby placing the RXDBUF
| contents on the Unibus.

4.2.5.4

4.2.5 Functional Block Diagram Description

Functionally, the DU11 can be divided into twelve logic
sections, each section performing a specific function in
accomplishing the overall task of data handling. The
followmg paragraphs describe the specrfic function of each

logic section (Figure 4-4).

4.2.5.1

Status

(TXCSR) — The

maintenance data for the DUI1 and monitors the XMTR

interrupt requests. The TXCSR also monitors the RX INP

(RCVR Input) line

the internal

and external loop

maintenance modes. The TXCSR is a 16-bit read/write
register that can be programmed by word or byte (high or

low).

Clear Logic — The clear logic initializes the inter-

face logic. The CLR (clear) and CLR OPT (Clear Option)
pulses combine to initialize all DUI1 registers, flip-flops,

and the XMTR and RCVR logic. BUS SSYN L

Transmitter

TXCSR stores control data for the XMTR section and

is also -

inhibited as long as CLR is asserted. These pulses are
generated by BUS INIT or MSTRST (Master Reset). BUS

INIT is received by the interface whenever
the computerSTART switch is pressed, the processor executes a RESET
instruction, or the power fail sequence occurs. MSTRST is

programmed controlled and is generated by setting the

MSTRST bit in the TXCSR. The MSTRST bit is normally
set to clear the DU11 prior to programmmg

Wh11e the clear logic normally provrdes both the CLR and

CLR OPT outputs, CLR OPT may be disabled by removing
jumper

W4 (engineering drawing D6). With CLR OPT
disabled, the interface may be cleared without clearing the

modem control lines, hence the handshaking sequence does
not have to be repeated each time the interface is cleared.

4-11

4.2.5.5

Clock Control Logic
— The clock control logic
decodes the maintenance mode select bits and selects the
XMTR and RCVR clock inputs. There are three possible

~clock sources: the

modem, the programmable SS CLK

(Single Step Clock), and the system test clock that is
contained within the clock control logic. If the normal
operating mode is decoded, the modem clocks are selected.

If the internal loop or external loop maintenance mode is

decoded, the SS CLK is selected. If the system test modeis

decoded, the system test clock is selected Maintenance
_modes are drscussedin more detailin Chapter 6.

When the DUI1 is transmitting in the half duplex mode,
the

SEND

asserted

and

HALF

1nh1b1t1ng the

DUP

(Half Duplex) inputs are

RX CLK, thereby disabling the

RCVR. This circuit is necessary because a half duplex
modem by defimtron transmits to the RCVR at the
sending station as Well as to the RCVR at the receiving
station.

The CLK EXT (Clock External) output -is used in the

~external loop

maintenance

length of character to be framed (5, 6, 7, or 8

mode. The modem test

bits plus parity)

~connector must be installed in this mode. The CLK EXT
- output is looped back by the modem test connector and
~ used to-drive the XMTR and RCVR. See Chapter 6 for a
| ~detarled descrrptlon of theexternal loop mode operation.

- 4.2.5.6 RCVR Input Select Logic — The RCVR input

select logic decodes the maintenance mode select bits and

parity (enabled or disabled)

"parityusense.(Odd or even)

sync character configuration.

~ The method of achieving synchronization is the principle

selects the RCVR data input accordingly. There are three

difference between the modes of operation:

possible data sources: the modem (SERIAL DATA IN),
the XMTR (SERIAL DATA OUT), and the program

~a.

(MAINT DATA). The modem data input is selected in the
normal operating mode while the XMTR data is selected in
the system test mode. In the internal loop and external

In the internal synchronous mode, two contig~uous sync characters must be recognized by the

RCVR logic to achieve synchronization. Once
synchronrzatron is achieved, the RCVR starts

loop maintenance modes, either the XMTR data or the
~MAINT DATA may be selected. Note that in the external

framing on the very next character bit. The
|

"loop maintenance mode the modem test connector must be

XMTR output back to the RCVR 1nput select logrc via the
SERIAL DATA IN lrne

zatron W1ll be lost

|
NOTE
|
Whenever the program activates the MAINT
'DATA input in either the internal loop or
external loop maintenance mode, the BREAK

The external synchronous mode is desrgned for

)

use with communication equipment which
accomplishes synchronization external to the

-DUL1 interface. The external synchronization

logic prohrbrts RCVR operatlon by inhibiting
the assertion of SCH SYNC until synchroni-

bit in the TXCSR must be set to inhibit the

recerved characters must arrive at the RCVRin

~a continuous serial bit stream or synchroni-

* installed. The modem test connector serves to loop the

zation with the XMTR has been achieved. When

XMTR data output. This removes the possi-

- external

bility of two sunultaneous data inputs to the

synchronization

achieved,

SCH

SYNC asserts, forcing the RCVR logic to the

RCVR.

synchronized

state.

The RCVR then starts

framing immediately, begrnnrng with the very

" next character bit.

In addition, the RCVR input select logic provides the RX
INP monrtor signal to the TXCSR. The RX INP line enables
- program monitoring of the RCVR serral data input in the

internal loop and external loop marntenance modes

In the isochronous mode, each received char-

’

acter
is preceded by a START bit and succeeded by a STOP bit, which serves to synchronize the RCVR. In this mode, the receiver

4.2.5.7 RCVR Logic— The RCVR logic constitutes the

simply does not start framing until it recognizes

“receiver section of the DUl1 and includes a double
buffered programmable RCVR, synchronization logic, and

a START bit. It then frames the character

following the START bit and looks for a STOP

RX DONE (Receiver Done) generation logic. The RCVR

- bit. If a STOP bit is not detected, the character

received is considered invalid, flagged as such,

logic detects the serial received character, accompllshes

synchronization, frames the received character, raises the

and held for reading by the program. Hence, in

RX DONE flag, and holds the framed character (for

- the isochronous mode, characters need not be

program reading) until the next characteris framed.

preceded by sync characters and need not arrive

- contiguously at the RCVR.

‘Once the RCVR logic is enabled, it operates as pro-

"grammed The SCH SYNC input enables the RCVR logic.

| »The STRIP SYNC (Strip Synchronization Character)’.input

‘The contents of the PARCSR determine:

~determines whether received sync characters are to be
permitted to set the RX DONE flag. If STRIP SYNC is

mode

operation

(internal

synchronous,

asserted,

external synchronous, or isochronous)

all sync characters are discarded provided no

errors are detected.

4-12

4.2.58 XMTR Logic — The XMTR logic constitutes the
XMTR section of the DU11 and includes
a double buffered
programmable XMTR, data not available logic,TX DONE

the TXCSR BREAK bit is set, the BREAK input to the

(Transmitter Done) generation logic, and break logic.

input enables the program to inhibit the XMTR output,

Once the XMTR is enabled, it operates as programmed. The

input ‘select

SEND input enables the XMTR logrc The contents of the

marntenance modes

The BREAK input inhibits the XMTR output ‘Whenever

XMTR logic asserts and inhibits the XMTR output. This

while inputting data directly to the RCVR via the RCVR

logic in

the

1nternal

and

external

loop

PARCSR determme

4.2.5.9
a.

Data Set Change Detector— The data set change

detector monitors the modem status inputs and detects any

mode operation (synchronous or isochronous)

‘status change. The status lines are routed to the data output

multiplexer as part of the RXCSR. When a status changeon

b. length of character to be transmrtted (5,6, 7,

or 8 bits plus parrty)

any one of the lines occurs, the DAT SET CH (Data Set
Change) flag is raised to cause a interrupt request. The DAT

parity (enabled or drsabled)

SET CH flag is cleared by DTI SEL 0 L (RXCSR Read

parity sense (odd or even)

serviced.

sync character configuration (used as fill char-

4,2.5.10

-acter in synchronous mode).

multiplexer controls the DU11

Strobe), which is generated when the interrupt request is

Data Output Multiplexer — The data output

data output to the bus

driver. There are three possible data outputs: the RXCSR,
the TXCSR, and the framed character and error flags from

the RCVR logic (RXDBUF). The data output is selected by

There are d1st1nct drfferences between the two modes of
operat1on

~a.
~

- 4.2.5.11 Bus Drivers — The bus drivers apply the data
output to the Unibus. The drivers are enabled by the

In the synchronous mode, the XMTR receives a
parallel transmit character from the program,
generates parity if programmed serially outputs

-DAT - BUS (data to bus) input from the address selectron

raises the TX DONE flag to request the next

4.2.5.12

character. If the program fails to provide the
character

before

transmission

fill

characters

maintain

transmission until another

the

(become bus master) and causes a program interrupt to a

interrupt address vector. There are four different reasons
for the DU11 to request an interrupt.

continuous

data character is

provided. Whenever a fill character is trans-

- a.

mitted the DNA (Data Not Available) flag is

TX DONE — XMTR is ready to accept another

raised to notify the program of fill character
transmission.

Interrupt Control Logic — The interrupt control

logic enables the DU11 to gain control of the Unibus

current character is complete, the XMTR out-

puts

and mode control logrc

- the character plus parity to the modem, and

the address bit inputs (ALO2 and ALOI)

character for transmission.

'b.

DNA — XMTR is transmitting a fill character

In the isochronous mode, the XMTR receives a

and wishes to notify the program.

parallel transmit character from the program,
generates

parity

programmed, outputs

¢c.

START bit, serially outputs the character plus

parity, outputs a STOP bit, and raises the TX |
DONE

flag

However,

to request the
the

isochronous

character.

mode,

RX DONE — RCVR has framed a character and
~

wishes the program to read it.

DAT SET CH — modem status has changed and
wishes to notify the program.

if the

program fails to provide the next character

before transmission of the current character is

All interrupts are enabled or disabled via the program. The

complete, the XMTR simply pauses until the

TX DONE and DNA interrupts are referred to as XMTR

next character
is provided. Hence, the DNA flag

interrupts and are enabled by setting the TX INTEB and

is never used in the isochronous mode.

DNA INTEB bits, respectively, in the TXCSR. The RX

4-13

DONE and' DAT SET CH interrupts are referred to as

RCVR interrupts and are enabled by setting the RX INTEB

and DAT SET INTEB bits, respectively, in the RXCSR.

201 and the Bell 303 interface connections

merely to provide the reader with a complete

When an interrupt request is generated, the interrupt

picture of DU11 interface connections.

control logic is enabled, the bus is requested and granted,

identified

and acknowledged, and the

vector address and services the interrupt.

4.3

DETAILED DESCRIPTION

The following paragraphs provide a detailed logic level

description of the functional blocks listed below:

The BG OUT (Bus Grant Out) line propagates the BG IN to
the Unibus whenever the DU11 is not requesting the bus or
presently has control of the bus. This, in effect, accom-

plishes the daisy chaining of BG IN to all devices on the
same BR level.

The NPR (Non-Processor Request) input improves NPR
latency. When this input is asserted, the BG OUT output is

Ao o

interrupt

Clear Logic

Address Selection and Mode Control Logic
Data Output Multiplexer Logic
RCVR Input Select Logic

the

- processor branches to the subroutine identified by the

Clock Control Logic

SRR

NOTE

The functional block diagram includes the Bell

XMTR Logic

RCVR Logic

|
-

Data Set Change Detector

Interrupt Control Logic

inhibited, thereby inhibiting the granting of the bus via the
BG IN input to any device on the same BR level as the

4.3.1 Clear Logic

DU11 and electrically further from the processor.

The clear logic generates the CLR outputs when the BUS
INIT signal is detected or bit 08 of the TXCSR is set

4.2.5.13

EIA Level Converters — The EIA level converters

- (Figure 4-5 and engineering drawings D2 and D6). When

the logic level signals to the operating

BUS INIT L is asserted, the CLR logic outputs are asserted

voltage levels of the Bell 201 modem. All logic signals

and remain asserted until BUS INIT is cleared. When bit 08

- merely convert

‘ranging from 2.4 to 3.5V are converted to +6 V. All
ground (0 V) logic signals are converted to-6 V. The EIA

is set, the 6 us one-shot is triggered on the leading edge of (
LD TXCSR HB H (Load TXCSR High Byte). The CLR

level converter threshold voltage is 1.5 V. Any inputs less

outputs are then asserted for the duration of the one-shot

than 1.5 V- will not cause the converter to switch.

(6 ps).

TXCSR HBH

DB 08 H

oNE-

SHOT

CLR H

‘

BUS INIT L-L__——:DIMTH

I[:

o—

—

L“L‘L_
—0o

CLRL

CLROPT L
1M1-2319

Figure 4-5 Clear Logic

~ While the clear logic normally provides three outputs, the

Table 4-1

CLR OPT output may be disabled. The CLR OPT output

Bus Address Reglster Select Bit Configurations

resets RXCSR bits

1, 2, and 3 and thereby clears the

control lines to the modem. By removing jumper W4, CLR

‘Bus Address Bits

OPT is disabled and the DUI1 may be cleared without

00*

clearing the control lines; hence, with jumper W4 removed,
the handshaking sequence does not have to be repeated
each time the DU11 is cleared.
NOTE

When CLR

H is asserted, BUS SSYN L is

RXCSR

- RXDBUF

PARCSR

- TXCSR

TXDBUF

inhibited for the duration of the pulse.

*This bitis set for DATOB operations on the hlgh byte

4.3.2

of the RXCSR or TXCSR.

Address Selection and Mode Control Logic

‘

The address selection and mode control logic decodes the A
and C bits placed on the bus by the program and generates

the gating and strobe signals necessary to perform the
operation decoded (engineering drawing D2).

Table 4-2
Bus Operation Control Bit Configurations

The DUI11 address selection and 'mode control logic
features rocker position address selection switches. These

Mode

switches (SWO—SW9) control the input to one pin of each
of the ten comparators. The inputs to the other comparator

pins are controlled by bus address receiver bits 03—12. If
the bus address bit input matches the switch input, the

- comparator is satisfied and the

output pin goes HIGH

(+3 V). For example, if rocker switch SW9 is set to the ON
position (closed), bus A12 L must be cleared (+3
V) to
- satisfy the comparator.
‘To address the

such

DATIP

DATO

DATOB

Note: DATI causes data to be transferred out
of the interface. DATO causes data to

DU11, the program must generate a bus
address

placed

the

bus,

C00

DATI

be transferred into the interface.

address that matches all the rocker position switch inputs.
When

Control Bits

C01

all the

comparators are satisfied and COMP H (Compare) asserts.
Whenever the program generates a device address, DEV

ADDR H asserts because all device addresses are relegated

4.3.2.1 Typical DATI Logic Operation — When the proces-

sor places the necessary address and control bits on the

to the uppermost 4K of address space and MSYN (Master

Unibus

SYNC) accompanies all addresses. Hence, ADRS SEL L is

RXCSR, the logic operation is as follows (engineering
drawing D2 and Figure 4-6):
-

asserted

enabling

the

BUS

SSYN circuit, enabling the

decoder and conditioning the AND gate.

Thus,

the DUII

is selected and the

remaining A bits

perform

DATI

(Read)

on the

The processor places the proper A and C bits on

the Unibus and waits

(A00—AQ02) and C bits, (C00, C01) must be decoded to

operation

150 ns (minimum) to

allow for signal skew (75 ns) and logic delay
(75 ns) before asserting BUS MSYN L (Master

generate the gating and strobe signals. The A bits select the
particular register. During DATOB operations, the A bits

Sync).

also indicate the register byte (high or low) to be loaded.
Refer to Table 4-1 for bit configurations required to select

each register. The C bits select the mode of operatlon

If the interface still has BUS SSYN L asserted

from a previous bus cycle, the processor waits

Refer to Table 4-2 for C bit configuration.

until BUS SSYN L is cleared and then asserts

BUS MSYN.

The following paragraphs explain ‘the operation of the
remaining logic with respect to DATI, DATOB, and DATO

bus operations.

The assertion of BUS MSYN L causes ADRS

SEL L to assert.

4-15

ADRS SEL L asserts DAT - BUS L and com-

LD TXCSR HB H asserted loads the high byte
of the TXCSR (engineering drawing D5)..

250 ns after the assertion of ADRS SEL L, BUS

When the processor detects BUS SSYN L, it
waits 75 ns and clears BUS MSYN L.

The processor then waits another 75 ns and
D lines.
clears the A, C, and

When the interface detects the clearing of BUS
MSYN L, it immediately clears LD TXCSR HB
H and 250 ns later clears BUS SSYN L.

bines with CLO1 H, ALO2 H, and ALO1 H

which are cleared to enable the DTI SEL OL
decoder output.

‘e.

Referring

engineering

drawing D3,

the

assertion of DAT
- BUS L enables the bus

SSYN L asserts provided CLR H is cleared.

drivers. ALO2 H and ALO1 H cleared select the
RXCSR output from the data output multi-

plexer.

Referring back to engineering drawing D2,
250 ns after the assertion of ADRS SEL L, BUS

SSYN L asserts provided CLR H is cleared (the

assertion of CLR H inhibits BUS SSYN L).
g.

When the processor detects BUS SSYN L, it
~

gating, then strobes the data from the interface
and clears BUS MSYN L.

43.2.3 Typical DATO Logic Operation — When the pro-

waits 75ns to allow for skew and internal

The

processor

then

waits

cessor places the necessary A, C, and D bits on the Unibus

- to perform a DATO (load) operation on the TXDBUF, the
logic operation is as follows (engmeermg drawing D2 and
Figure 4-8):

another 75 ns to

‘ensure that no errors occur and clears the A and

C lines.

The processor places the proper A, C, and D
bits on the Unibus, waits
150 ns, and asserts
BUS MSYN L provided BUS SSYN L from the

When the interface detects the clearing of BUS

previous bus cycle’ is cleared.

MSYN L, it immediately clears DAT - BUS L

inhibiting the bus drivers and clears BUS SSYN

L 250 ns later. The Unibus is now free for other

use.

SEL L to assert.

4.3.2.2 Typical DATOB Logic Operation — When the program places the necessary A, C, and D bits on the Unibus to
perform a DATOB (Byte Load) operation on the high byte
of the TXCSR the logic operatlon is as follows (engmeermg
drawmg D2 and Figure 4-7):

The program places the proper A, C, and D bits
on the Unibus and waits 150 ns (minimum) to
allow for signal skew (75 ns) and logic delay
(75 ns) and asserts BUS MSYN L, provided

DTO SEL 6 L asserted triggers the 350 ns

€.

LD TXDBUF (1) H asserted loads the TXDBUF

and, after a 150 ns delay, inhibits BUS SSYN L.
f.

350 ns after the one-shot is triggered, it resets
and, after a 150 ns delay, causes BUS SSYN L
to assert provided CLR His cleared.

The assertion of BUS MSYN L causes ADRS
SEL L to assert.

ADRS SEL L combines with CLO1 H and ALO2
H asserted and ALO1 H cleared to enable the

When the processor detects BUS SSYN L, it
waits 75 ns and clears BUSMSYN L.

The processor then waits another 75 ns and
clears the A, C, and D lines.

DTO SEL 4 L decoder output.

L decoder output

~one-shot -causing
LD TXDBUF (1) H to assert.

"BUS SSYN L from the previous bus cycle is

C.
'

ADRS SEL L combines with CLO1 H, ALO2 H,
~and ALO1 H asserted to enable the DTO SEL 6

~ cleared.

The assertion of BUS MSYN L causes ADRS

DTO SEL 4 L asserted causes LD TXCSR HB H
to assert (INH LB H asserted inhibits LD

TXCSR LB H).
4-16

When the interface detects the clearing of BUS

MSYN L, it immediately clears DTO SEL 6 L
and 250 ns later clears BUS SSYN
L.

]

A (17-03) L
BUS
BUS A (02-0N)L

BUS C(O1-00)L
|

+3V

BUS MSYN L

- +3V

ADRS SEL L
o

([-/
|

DAT=BUS H
'

TM
TSNSMIN.J

‘

+3V

43V

BUS D (15-00) L.

/jl '

—

DTI SEL OL

BUS SSYN L

(_/ AN

A
.

43V

250ns

;l '
1-2312

BUS D(I15-08)L
BUS A(17-03) L

BUS A 02

BUS A Of

BUS A 00 L
|

oV
+3V

BUS C (01-00) L

+3V

BUS MSYN L

|
—

+3V

ADRS SELL
+3V

DTO SEL 4L

INHB LB H =
TXCSR HB H

BUS SSYN L

'v_

250NS

- Figure 4-7 DATOB Timing Diagram

+3V

BUS D(15-@92)L

BUS A (17-93) L*3v
+3V

|
j'

BUS A (@2-g1) L

BUS C(aI) L

+3V-

BUS C(Z@)L

ov—

+3v

75ns

I MIN.

BUS MSYN L .

ADRS SEL L

t3Vi

DTO SEL 6 L

+3V

——
1500
—o|
350ns—-+'t

LD TXDBUF (1) H

{

BUS SSYN L

Figure 4-8

_ STROBE L

TX DONE H

(FROM RXDBUF)

RX DB @7 H

(FROM RXCSR)

RX DONE (1) H

(FROM TXCSR)

DATO Timing Diagram

TO BUS
DRIVER

(1
OF 8)
DO
TX INTEB (1)H

(FROM RXDBUF)

RX DB @6 H

(FROM RXCSR)

RX INTEB (1) H

ALO1

TRUTH

BO
AQ
DATA

AL@®2 H|
SELECT

TABLE

AL®1

H |

OUTPUT

)
2

@
1

AZ, A1
B@,B1

D@, D1

Co,CH

AL@2 H

11-2345

Figure 4-9 Data Output Multiplexer Logic
/“\

(FROM TXCSR)

4-18

4.3.3 Data Output Multiplexer Logic

H and MS 01 (1) H are cleared, thus asserting
EN BIT WID
H which enables the MAINT DATA (1) H input and the RX

The data output multiplexer logic decodes address bits A02

~and AO1 and selects one of three register data inputs to be

INP output. Also in internal loop maintenance mode, MS

output to the bus drivers. Figure 4-9 shows one of a total of

00 (1) H is asserted enabling the SERIAL DATA OUT H

eight multiplexers used in the DU11. Refer to engineering

input. In the external loop maintenance mode, MS 00 (0) H
and MS 01 (1) H are asserted, enabling the MAINT DATA

drawing D3 for a complete logic picture.

(1) H and SERIAL DATA IN inputs and the RX INP
4.3.4

output. Note that the modem test connector is installed in

RCVR Input Select Logic

The RCVR input select logic decodes the maintenance
mode select bits and selects the RCVR data input accord-

“the external loop maintenance mode; hence, the SERIAL
DATA IN input originates from the XMTR (Figure 4-11).

In the system test mode, MS 00 (1) H is asserted enabhng

ingly.

There are three possible data sources (Figure 4-10 and

SERML DATA OUT H.

engineering drawing D5): the modem (SERIAL DATA IN),

- NOTE

[MAINT DATA (1) H], and the XMTR

In the internal and external maintenance modes

nance mode select bit configurations and corresponding

two data sources (Program and XMTR) can be
simultaneously input to the RCVR; hence, care

the

program

(SERIAL DATA OUT H). Refer to Table 4-3 for mainte-

‘data sources.

must be taken when programming these modes

The maintenance mode select bits enable the proper data

The

to assure that only one of the sources is active.

break logic is provided for just that
purpose. When the BREAK bit is set the XMTR

source inputs. In the normal operating modes, MS 00 (0) H

is asserted and MS 01 (1) H is cleared enabling the SERIAL

output (SERIAL DATA OUT H) is inhibited.

DATA IN input and disabling the RX INP (Receiver Input)

Refer to Paragraph 4.3.7 for a description of

output. In the internal loop maintenance mode, MS 00 (0) .

- MS

EN BIT WID H

(1) H—:)D°

MS 00 (0) H—

the break logic.

MAIN

iD—RX INP H

DATA (1)
H

(TO RCVR)

~ (FROM

MODEM) SERIAL

DATA

MS 00 (1) H

(FROM

XMTR) SERIAL DATA OUT H
‘

11-2317

Figure 4-10

RCVR Input Select Logic

Table 4-3
Maintenance Mode to Data Source Relatlonshlp

Maintenance Mode
|

Maintenance Modé Select Bits .

Data Sdurce

MS 01

MS 00

Normal Opération_

Internal Loop

Program or XMTR

External Loop

Program or XMTR

System Test

XMTR

4-19

modem

TXCSR

XSk

| o e

uone

CONNECTOR

.}
]

RCVR
INPUT |_

B
EIA SERIAL DATA IN

SERIAL DATA IN

SELECT

LOGIC

RCVR
LOGIC

‘

RX CLK H
-

. REC CLK
|

LEVEL

CLOCK
CONTROL
|

EIA

PR
REC CLK

EIA

CLK EXT H

>__"

CLK EXT

LOGIC

L.TX CLK H}

CONVERTER

TRS CLK

EIA TRS CLK

XMTR
LOGIC

SERIAL DATA OUT H

EIA XMIT DATA

11-2316

Figfire 4-11 External Loop Maintenance Mode Interconnection Diagram

4.3.5 Clock Control Logic

(Half Duplex) and SEND (1) H inputs are asserted, REC

select bits and selects the XMTR and RCVR clock inputs
accordingly (Figure 4-12 and engineering drawing D5).

The SS CLK inputs are provided for maintenance purposes.

The clock control logic decodes the maintenance mode

CLK
is inhibited.

This program controlled clock is used in the internal and

Different clocks are used for different modes of operation.

external loop maintenance modes and can be operated very

In the normal operating mode, MS 00 (0) H is asserted
enabling the modem clock inputs (TRS CLK and REC
CLK) that are routed to the XMTR and RCVR. In the
internal loop maintenance mode, MS 00 (1) H is asserted
enabling the SS CLK (1) H input to drive the XMTR and
RCVR. In the external loop maintenance mode, MS 01 (1)
H and MS 00 (0) H are asserted, enabling SS CLK (0) H and

slowly via the program to facilitate troubleshooting.

The SYS TST CLK H output is also Iused for maintenance
purposes. This output is used to provide an asynchronous
clocking source for the system test mode.

the TRS CLK and REC CLK inputs. SS CLK (0) H drives

4.3.6

RCVR Logic

CLK EXT, which is routed to the modem test connector,

The RCVR detects the serial received character, accom-

inputs (Figure 411). In the system test mode, MS 01 (1) H

detects errors, raises the RX DONE flag, and holds the

looped back, and applied to the TRS CLK and REC CLK

plishes

and MS 00 (1) H are asserted enabling the internal system

synchronization, frames the received character,

framed character (for program reading) until the next

‘test clock to drive the XMTR and RCVR. In this mode, the

character is framed (Figu_re 4-13 and engineering drawing

modem clock inputs (TRS CLK and REC CLK) are
inhibited.

When the DUI11 is transmitting in the half duplex mode,
the REC CLK input is disabled. When the HALF DUP (1) H

4-20

Before RCVR operation can begin, the RCVR 1ogic must be

initialized and the PARCSR, TXCSR and RXCSR registers
programmed.

——— SYS TST CLK H

MSO1 (1) H

MS00 (1) H —

(FROM MODEM) TRS CLK —QD

@TXC

LKH

MSO0O
(O) H —

‘

MS00 (1) H ——

(FROM MODEM)
REC CLK

SEND (1) Hfij——,_d

HALF DUP (1) H

ss CLK (0) H

SSCLK (1) H

__D— RX CLK H

D__ LK ExT

MSO1 (1) H

‘
11-2318

Figure 4-12

Clock Control Logic

data source is the modem In the maintenance modes, data

4.3.6.1
RCVR
Logic
Initialization
and
Pro- gramming — The RCVR logic is initialized by BUS INIT or

inputs from the XMTR and the program may be selected as

by setting the MSTRST bit, which causes the assertion of |
the

CLR inputs.

The CLR

L input

resets

discussedin Paragraph 4.3.4.

all RCVR

Table 4-4

flip-flops
and the CLR H input forces the RCVR to the idle
state. In the idle state, the RXDBUF is set to all 1°’s and the

PARCSR Mode Select Bit Configurations

sync register and all timing and control logic and output
flags are cleared.

Mode

Mode Select Bits

The RCVR
is then programmed by loading the PARCSR,
TXCSR,

and

RXCSR.

program

the

Isochronous

PARCSR the

- External Synchronous

PARCSR load strobe is asserted, PARCSR bits 13—08 are

loaded into the control register,

Internal Synchronous.

PARCSR bits 07—00 are

-0

loaded into the sync register, and the SYNC INTR and

SYNC MODE flip-flops are set or reset in accordance with

Programmlng the RXCSR d1rectly controls the operation of
“the RCVR logic. The SCH SYNC bit must be set or RCVR

~the state of PARCSR bits 13 and 12. Bits 13 and 12 select
‘the RCVR mode of operation. Table 4-4 lists the bit

bit enables RCVR logic to strip (discard) all received Syne

- Programming the TXCSR establishes the source of the
-~

operation is inhibited. The assertion of the STRIP SYNC

configuratlon for each mode of operation.

RCVR serial data input. In the normal operating modes, the

characters provided no errors are detected. Note that the
- RX INTEB bit must also be set or RX DONE flags will be

4-21

ignored by the interrupt control loglc

After one bit time delay the RCVR begins shifting in the

4.3.6.2 RCVR Logic Operation — The following
paragraphs provide a detailed description of RCVR logic
operation in each of the three operating modes. Figure 4-13
illustrates the RCVR logic and the timing diagrams (Figures

first bit of the first character (bit S) in search of a sync
character. As each bit is shifted into the RCVR register a

4-14 through 4-17) illustrate logic operation in response to

different character input configurations in each mode. The
characters on each timing diagram are numbered in the
order of their arrival at the RCVR input.

Before the RCVR logic can be discussed, the programmed

duplicate bit is also shifted into the RXDBUF, so that the
RXDBUF is always an exact duplicate of RCVR register.
- After each bit is received, the RCVR compares the content
of the RCVR register to that of SYNC register. When a
complete sync character has been shifted into the RCVR
register, the two registers match and the RCVR asserts
MDET H (Match Detect). MDET H triggers the MATCH
asserting

MATCH L. Because

errors are

operating parameters must be established.

one-shot,

In the following discussions, the only operating parameter

Character) also asserts. RST CHAR L has no effect,
however, as DATA RDY L (Data Ready) is cleared.

detected (RX ERR H cleared), RST CHAR L (Reset

that changes is the mode of operation which naturally must
correspond to the particular mode being discussed. Other-

MATCH L resets after 400 ns and sets the 1st IN flip-flop.

wise, the control registers are programmed as follows for
the entire RCVR d1scu381on

The PARCSR is programmed for an 8 bit

~b.

The TXCSR is programmed for the normal

character with odd parity and a sync character

The RCVR then starts framing on the very next bit (bit D
‘of the second character). When framing starts, the RCVR
ceases shifting each received bit into the RXDBUF and
~ inhibits the comparator until an entire character has been
received in the RCVR register (character length specified by

PARCSR). At the center of the last character bit (the parity
bit

mode of operation (maintenance mode select
bits cleared).

in this

case), the RCVR performs the following

operations simultaneously:
a.

The RXCSR is programmed to enable the

RCVR (SCH SYNC bit set), strip sync characters (STRIP SYNC bit set), and enable RX
DONE interrupts (RX INTEB bit set).

checks parity

~b.

compares framed character to sync character

¢.

parallel transfers the framed character into the
RXDBUF.

4.3.6.2.1 Internal Synchronous Mode — In the internal
- synchronous mode, characters must arrive at the RCVR in a
continuous serial bit stream; character synchronization is ~ The RCVR then asserts PE (parity error) if parity is
incorrect and keeps MDET H asserted if the second
accomplished within the RCVR logic. To accomplish
character is a sync character. However, in this case the
synchronization, the RCVR must recognize two contiguous

* sync characters and, upon doing so, assert REC ACT (1) H,

thereby enabling the RX DONE flag to be asserted for all

second character is a data character, with good parity;

~ hence, 200 ns later the MDET H flag is cleared, DR (Data

succeeding received characters.

As previously stated, the program prepares the RCVR logic
for operation by initializing the logic and programming the
control registers. In the internal synchronous mode, bits 13
and 12 of the PARCSR are set. Therefore, when the
PARCSR load strobe occurs, the SYNC INTR flip-flop and
the SYNC mode flip-flop are set (Figure 4-14).

Ready) is asserted, and the following ensues:
a.

RST CHAR L clears

the 1st IN flip-flop resets

DATA RDY L asserts and is ANDed with
MDET H cleared to reset the SYNC flip-flop
and ANDed with REC ACT (0) L asserted to
trigger the DRR (Data Ready Reset) one-shot.

'RCVR operatwn is enabled when SCH SYNC (1) H asserts.

The assertion of SCH SYNC (1) H causes SYNC (1) L to
assert when RX CLK H goes low which, in turn, asserts the
SS (Search Sync) input to the RCVR; thus, the RCVR is
enabled.

- 4-22

Clearing the SYNC flip-flop clears SYNC (1) L,

which re-initializes the RCVR logic and inhibits
RCVR operation.

SYNC

INTR

SYNC

b PARCSR (1)
H

INTR
F/F

RCVR

SERIAL
e

CLR H
|

DB 13,

11,10,8 H

» RX DBOT00 H

‘

TIMING AND

CONTROL LOGIC

RRC

]

RECACT (O)H—D

RDEAJSY

a60ns

DBO9 H

o /,

DBi2 H

SS/FE

PARCSR

W
n
5

o@
o
S

_—
.

DBI3 H—+iD
"

PARCSR (1) H

>¢ R

ISOC H

CLR

¢ g

;

’

SCH SYNC (1)H DS p—sSYNC(1)H

SYNC

:
SCH SYNC (O) ) H (
CL R H

DATA RDY L
MDET H

RX CLK H

-s
|
|x

F/F

C .

[ SYNC(O)H

CLR H

-1
&
=

> <a
=

|MDET

MATCH

]

SHOT | MATCH

400 ns
ONE -

SEL

x
e

)

.
FRM ERR H

OVRN ERR H

MDET

PAR ERR H STRIPSYNC

(1) H

)

RX ERR

‘

RX ERR H

REC

NOTE:
1 Jumper W2 is normally removed.

DTI

L ()

—_—

MDET H

ACT (1)

DATA RDY L

DONE

DTI SEL 2L—]C

LR L

F/F
R

REC ACT (0) L

DRR

+Vv

—— RX DONE (1) H

400ns

ONE
SHOT

+— RX DONE (0) H

DATA RDY
‘ L

RST CHAR L
RX ERR H
,

"See

REC ACT (O} H

___h

S .

—RECACT (1) H

;A:(,:l O

MIP/DFE

REC

(0) H

DB 07-00 H

p 5

tst

QNET [ DATA RDY
L (1)

DATA RDY H

PARITY | ©
INHIBIT | &
=
S

DB13 H

SCH SYNC (1) H

RCVR REGISTER =
|
I

——

(SAR CHIP)
‘

DATA IN

RX CLK H

‘L

)

?
CLRL

SYNC (1) L

INTR H

(SEE NOTE 1) W2

SYNC

CLR

STA-DR L

11- 2320

Table 2-1 for jumper

discriptions.

- Figure 4-13

RCVR Logic

4-23

CLR H
LD PARCSR(O}H

I:/ l (RCVR INITIALIZED)
(

SYNC INTR H

LD TXCSR HB/LB H

LD RXCSR HB/LB H

. (RCVR PROGRAMMING COMPLETE)

SCH SYNC (1) H

)
STRIP SYNC (1} H

SYNC (1) L

SERIAL

RCVR INPUT

FIRST CHARACTER

SECOND CHARACTER

[

THIRD CHARACTER

FOURTH CHARACTER

FIFTH CHARACTER i

[

SIXTH CHARACTER

]

[s]v|n]ecfeciujafripiofafr[aJcfnu]afrifpls[y[n]c]cnlalr]rsTvInTc]clu]alr]e[s[y[n]clc][ulalr]e|s][y[n]c]c][n][alr]r]
_

RX CLKH

M DET H

MATCH L

DATA RDY L

‘4_]

/;151

RST CHAR L

;

,CEELJ;—-4OOnS

DR
~

(RCVR ENABLED)

q (RCVR ENABLED)

PAR ERR H
RX ERRH

{ ]

///

| //
J//% \

RX DONE (1) H

/ :

' X\

\\\

J//

DTI SEL 2L

CHARACTER

RECOGNIZED

SYNCHRONIZATION
-NOT ACHIEVED

K /( ///
\\\ ( //
\

\EI

| (RCVR LOGIC SYNCHRONIZED)

SYNC CHARACTER

NOT RECOGNIZED

RECOGNIZED

\\\

e !; ‘
NN a

\\\

”L__>¥

SYNC CHARACTER

]

[7/{///
<i:;_'

. :>§i;

]

:i:kfi;400ns

SYNC

t}
_ \1:l“g

CLR STA-DRL

REC ACT (1)H

! //:Efi

—Edfgfk———400ns

}

SYNCHRONIZATION
ACHIEVED

K4:f7

PARITY ERROR AND RX
DONE FLAGS RAISED

PROGRAM READS

RXDBUF

11-2322

Figure 4-14 RCVR Internal Synchronous Mode
Timing Diagram (Example I)
4-25

Triggering the DRR one-shot asserts CLR

200 ns later asserts the DR flag while MDET H remains

asserted. PE causes the assertion of PAR ERR H (parity

STA - DR L (Clear Status and Data Received)

~which clears the DR flag.

error) and RX ERR L. With RX ERR L asserted, RST

CHAR L is cleared and the AND gate connected to the RX
f.

400 ns after it is triggered, the DR one-shot

~ DONE flip-flop is conditioned. When the DR flag causes the

clears DATA RDY L, thus allowing SYNC (1) L

assertion of DATA RDY H, the AND gate is satisfied and

to assert again when RX CLK H goes LOW.

RX DONE (1) H is asserted. RX DONE (1) H causes a

RCVR interrupt request and the program responds by
reading the RXDBUF, which causes DTI SEL 2 L to assert.

The assertion of SYNC (1) L enables RCVR
operation.

The assertion of DTI SEL 2 L triggers the DRR one-shot
asserting CLR STA - DR L, which clears the DR and error

After a one bit time delay, the RCVR starts shifting in the

flags. The trailing edge of DTI SEL 2 L clears RX DONE

bits

(1) H. Note that the sixth character (a sync character) was

comprising

the

third

character.

Note

that RCVR

not stripped in this case due to a parity error.

operation is inhibited when the first bit (bit S) of the third
character arrives at the RCVR and is not enabled until RX

To go a bit further and explain other situations that may

CLK H goes LOW at the center of the bit S; hence, bit S is

lost. Also note that the RCVR is again searching for a sync

develop when operating in the internal synchronous mode,

character; each time a bit is shifted into the RCVR register

an additional timing diagram is provided (Figure 4-15).

it is duplicated in the RXDBUF and the RCVR register is
As Figure 4-15 illustrates, the first two characters received

compared to the Sync register. Hence, the third character

by the RCVR are sync characters with no errors. At the

will not cause a match because the entire sync character is
not received.

center of the parity bit of the first character, MDET H
asserts causing MATCH L and RST CHAR L to assert.

The RCVR simply continues shifting bits in until a match
occurs. The match will occur at the center of the parity bit

400 ns later, MATCH L clears setting the 1st IN flip-flop.

of the fourth character. At that time, MDET H is asserted

DR flag asserts causing DATA RDY L to assert. DATA

At the center of the parity bit of the second character, the

and RST CHAR L and MATCH L assert; MATCH L resets

RDY L is ANDed with REC ACT (0) L true and triggers the

400 ns later and sets the 1st IN flip-flop. The RCVR starts

DRR one-shot.

framing on the very next bit received (bit S of the fifth

character).

The DRR one-shot asserts CLR STA < DR L, which clears

“the DR flag. 400 ns later, DATA RDY L resets and sets the
At the center of the parity bit of the fifth character, the

REC ACT flip-flop; thus the RCVR is synchronized.

RCVR simultaneously checks parity, does a sync character
The third character received is also a sync character with no

comparison, and transfers the framed character into the

RXDBUF. The fifth character is a sync character with good

errors.

parity; hence, the DR flag asserts, DATA RDY L asserts

asserted and MDET H remains asserted. DATA RDY L then

At the center of the parity bit, the DR flag is

and is ANDed with REC ACT (0) L causing CLR STA + DR

asserts and is ANDed with RST CHAR L true and RX ERR

L to assert. If CLR STA +« DR L should fail to assert at this

H false to trigger the DRR one-shot. The DRR one-shot

time, the next character received would cause an overrun

asserts CLR STA - DR L and the DR flag
is cleared. Thus

error. CLR STA « DR L clears the DR flag. Approximately

the sync character is stripped, i.e., not presented to the

400 ns later, DATA RDY L clears and REC ACT (1) H

program.

asserts on the positive-going edge of DATA RDY L; thus,
the RCVR logic is synchronized. Note that REC ACT (1) H

“The fourth character received is a data character with a

conditions the AND gate connected to the set input of the
RX DONE flip-flop.

The RCVR continues framing with the sixth character; at
the center of the parity bit for the sixth character, the

parity error. At the center of the parity bit, the PE flag is

asserted causing PAR ERR H and RX ERR H to assert.

MDET H is cleared causing RST CHAR L to clear and,
200 ns later, the DR flag is asserted and DATA RDY H

asserts, causing RX DONE (1) H to assert. RX DONE (1) H
causes a RCVR interrupt request and the program responds

RCVR simultaneously checks parity, does a sync compar-

by reading the RXDBUF, which causes DTI SEL 2 L to

ison, and transfers the framed character into the RXDBUF.
The sixth character is a sync character with bad parity.

assert. CLR STA + DR L then asserts clearing the DR and
PE flags. The trailing edge of DTI SEL 2 L clears RX DONE

Hence, the RCVR asserts the PE (parity error) output and

(1) H.

427

CLR H

[

LD PACSR(O) H

SYNC INTR

LD TXCSR HB/LB H

LD RXCSR HB/LB H

(RCVR PROGRAMMED)

SCH SYNC() H

STRIP SYNC (1) H

SYNC (1) L

SERIAL
RCVR INPUT

]

\L(RCVR ENABLED)
FIRST CHARACTER

sy [nfclc|nla]r]rP

SECOND CHARACTER

Sle]NICICIHIIAIR]P

THIRD CHARACTER

FOURTH CHARACTER

s|y|nfc]c ]H]A[RIP

DJAITIA]C]HIA]R[P'

FIFTH CHARACTER

D]Al’T]Alc
j

[hlafrR]P

SIXTH CHARACTER

DIAlT[AICIHIA]RIP

{

RX CLK H

-t
:

M DET H

j.uxhoms

MATCH L

DATA RDY L

RST CHAR L

A
e
[

PAR. ERR H
OVRN ERR H

ERR H

REC ACT(1) H

RX DONE (1) H

[

STA

]
//

DTI SEL-2L

CLR

\—aj;— 400 ns

DR L

SYNC CHARACTER

SYNCHRONIZATION

RECOGNIZED

ACHIEVED

SYNC

CHARACTER

STRIPPED

RX
PE

DONE

FLAG

AND

RAISED

PROGRAM READS

PROGRAM FAILS

RXDBUF,RX DONE

TO READ RXDBUF,

FLAG RAISED

11-2323

Figure 4-15

RCVR Internal Synchronous Mode

Timing Diagram (Example II)

4-29

interrupt request. The program responds to the interrupt

The fifth character received is also a data character but with
no parity error. The DR flag causes DATA RDY H to assert

request by reading the RXDBUF which causes DTI SEL 2 L

which, in turn, asserts RX DONE (1) H. The RCVR

to assert. CLR STA - DR L then asserts clearing the DR

interrupt request is generated; thWGV@I‘, the program fails to
read the RXDBUF before the next character (the sixth

flag. The trailing edge of DTI SEL 2 L clears RX DONE (1)
H.

character) is framed and transferred into the RXDBUF.
Hence, the fifth character is lost (overwritten) and the OE

4.3.6.2.3

(overrun error) flag is asserted at the center of the parity bit

each character presented to the RCVR is preceded by a

Isochronous Mode — In the isochronous mode,

for the sixth character causing the assertion of OVRN ERR

- START bit and succeeded by a STOP bit. Hence, the

Hand RXERR H.

RCVR synchronizes on each received character; therefore,

The program then responds to the RCVR interrupt request

ously (Fi1gure 4- 17)

characters need not be presented to the RCVR contigu-

caused by the fifth character and reads the RXDBUF, DTI

‘When the PARCSR is programmed for the isochronous

SEL 2 L asserts, CLR STA+ DR L clears the DR and OE

flags, and the trailing edge of DTI SEL 2 L clears RX
DONE (1) H.

mode, bits 13 and 12 are cleared. Therefore, when the

- PARCSR load strobe occurs, the SYNC INTR flip-flop and
the SYNC mode flip-flop are cleared.

External Synchronous Mode
— In the external

RCVR operation is enabled when SCH SYNC (1) H asserts.

synchronous mode the RCVR logic sets to the synchro-

The assertion of SCH SYNC (1) H in this mode causes REC

4.3.6.2.2

nized condition when the SCH SYNC bit is set (Figure

ACT (l) H to assert immediately and SYNC (1) L to assert

4-16).

“when the REC CLK H input goes low. REC ACT (1) H

As previously stated, the program prepares the RCVR logic
ming the control registers. In the external synchronous

SYNC (1) L has no effect since the OR gate connected to
the SS/FE line is already receiving a low from the SYNC
mode flip-flop. This is done to ensure that the RCVR FE

‘mode, bits 13 and 12 of the PARSCR are set to 1 and 0,
respectively. Therefore, when the PARCSR load strobe

line. Normally in the isochronous mode the FE flag output

conditions the RX DONE flip-flop AND gate. However,

for operation by initializing the RCVR logic and program-

(Framing Error) flag has absolute control over the SS/FE

occurs, the SYNC INTR flip-flop is cleared and the SYNC

is held LOW by the SAR chip; when a framing error is

mode flip-flopis set.

detected, the SAR chip forces FE HIGH asserting FRM
ERR H and RX ERR H.

RCVR operation is enabled when SCH SYNC (1) H asserts.
The assertion of SCH SYNC (1) H in this mode causes REC

In the isochronous mode, RCVR operation is initiated

ACT (1) H to assert immediately and SYNC (1) L to assert
~when the RX CLK H input goes low. REC ACT (1) H

when a START bit is detected on the input. Any mark to

- conditions the RX DONE flip-flop AND gate while SYNC

sample the input line at the theoretical center of the

space (HIGH to LOW) transition causes the RCVR to

(1) L places a HIGH on the SS input to the RCVR. In this

START bit. If a low level input is detected the RCVR starts

mode a HIGH on the SS line causes the RCVR to start

framing by sampling the center of succeeding data bits and

framing on the very next character bit received. Hence, the

shifting the data into the RCVR register. When an entire

RCVR begins framing on bit S of the first character and at

character is framed (as defined by the PARCSR) the RCVR

the center of the parity bit of the first character (which, in

tests the input line for a valid STOP bit, checks parity,

this case, is a sync character with good parity), asserts
MDET H and the DR flag. MATCH L, DATA RDY H, and

compares the framed character to the sync character, and
- parallel transfers the contents of the RCVR register (minus

RST CHAR L assert, causing CLR STA- DR L to assert,
thus clearing the DR flag. Note that the RX DONE flip-flop
AND gate is inhibited by RST CHAR L, hence the sync
|
characteris stripped.

the START and STOP bits) into the RXDBUF.

In this case the first character is a data character with good

- parity and a valid STOP bit; hence, the DR flag asserts,

DATA RDY H asserts, and RX DONE (1) H asserts causing

The RCVR continues framing as the second character (a

data character with good parity) is received. At the center

reading the RXDBUF, DTI SEL 2 L asserts triggering the

RCVR

interrupt

request.

The

program responds by

of the parity bit, MDET H is cleared and the DR flag is

DRR one-shot which asserts CLR STA

asserted. RST CHAR L clears and DATA RDY H asserts,

assertion of CLR STA <« DR L clears the DR flag.

causing an RX DONE (1) H to assert generating a RCVR

trailing edge of DTI SEL 2 L clears RX DONE (1) H.

4-31

DR L. The
The

CLR H

LD PARCSR (O)H

SYNC INTR H

LD TXCSR HB/LBH

LD RXCSR HB/LB H

(RCVR PROGRAMMING

COMPLETE)

SCH SYNC (1) H

STRIP SYNC (1)H

SYNC(IL

\‘1 (RCVR ENABLED)

SERIAL RCVR

~INPUT

RX CLK H

REC ACT (1)H

/
|

FIRST CRARACTER

SECOND CHARACTER

ISIYINICICIHIAIRIPlDIAlTJAlclHIAlfilfl

B \—ficva SYNCHRONIZED)

MDET H

T\ ,

\J
MATCH L
'

400ns

oR
DATA RDY

/fl

400ns

RST CHAR L

RX DONE (1) H

\“l/

<\J7 d

DTI SEL2L

CLR STA-DRL

400ns

SYNC CHARACTER

‘

" RX DONE

FLAG RAISED

PROGRAM READS
RXDBUF

1N-2324

»Flgure 4-16 RCVR External Synchronous Timing Diagram

4-32

CLR
H

LD PARCSR

(1)H

SYNC INTR

1SOC H

LD TXCSR HB/LBH

LD RXCSR HB/LB H

SCHSYNC(1)H

STRIP SYNC (1)H

SYNC (1)L

FIRST

SERIAL RCVR INPUT

CHARACTER

o | al
T alc]H laRr][P
START BIT

START

THIRD CHARACTE

a[r]P

FOURTH

plalT]alcH
STOP

START

CHARACTER

CHIA ]’R[P

START

STOP

MDET
H

MATCHL

FRM ERR
H

PAR ERR H

/_\

L
a

RX DONE
(1) H

DTI SEL 2 L

"CLR STA -DRL

PROGRAM READS
RXDBUF
AND SYNC CHARAC TER STRIPPED

£
N

400 ns

RX DONE
FLAG RAISED

RST CHAR L

|
——

*SL& 400 ns

- DATA RDY L

\—

)

RX ERR

-3_]*400 ns

@Efl
f/\fi//i/fi?

ACT(1)H

]

REC

STOP BIT

[s [Y BN Lc (vl

RX CLK

SECOND CHARACTER

}—

RX DONE
AND FE FLAGS RAISED

PROGRAM READS
RXDBUF, RX DONE
AND PE FLAGS RAISED

11-2325

Figure 4-17

RCVR Isochronous Mode

Timing Diagram

4-33

The RCVR then waits for the next START bit. When it

The XMTR is then programmed by loading the PARCSR

arrives, the RCVR begins framing the second character. The

and TXCSR. To program the PARCSR, the PARCSR load

second character is a sync character with good parity and a

~valid STOP bit. Hence at the center of the STOP bit, MDET
H and the DR flag assert. MDET H asserts RST CHAR L
and triggers the MATCH one-shot. The DR flag triggers the

strobe is asserted, PARCSR bits 13 and 11—08 are loaded
into the

control register,

and PARCSR bits 07—00 are

loaded into the fill register. Bit 13 selects the XMTR mode
of operation. If bit 13 is cleared, the XMTR operates in the

DATA READY one-shot and DATA RDY L is ANDed with

isochronous mode; if bit 13 is set, the XMTR operates in

RST CHAR L true and RX ERR H false to trigger to DRR

the synchronous mode.

one-shot. CLR STA - DR L asserts clearing the DR flag;

thus the sync character is stripped.

Programming the

The RCVR then receives the next START bit and begins

The SEND bit must be set or XMTR operation is inhibited.

framing the third character, which is a data character with

If the BREAK bit is set, the XMTR data output is disabled.

good parity but an invalid STOP bit. Hence, at the center of
the theoretical STOP bit, the FE flag
is asserted causing
-

TXCSR directly controls the operation of

XMTR logic and enables or disables the XMTR data output.

FRM ERR H and RX ERR H to assert. 200 ns later the DR

flag asserts and MDET H clears. DATA RDY H then asserts,
RST CHAR L clears and RX DONE (1) H asserts causing a

RCVR interrupt request. The program responds by reading

the RXDBUF, DTI SEL 2 L asserts, and CLR STA - DRL

the

normal

operating

mode

the

external

loop

maintenance mode is selected via the maintenance mode

select bits, the EIA XMIT DATA output is enabled (Figure

4-18). Note that the TX INTEB and DNA INTEB bits must
be set or the TX DONE and DNA flags will be ignored
by

the interrupt control logic.

asserts and clears the DR and error flags. The trailing edge

of DTI SEL 2 L clears RX DONE (1) H.

4.3.7.2

The RCVR then receives the START bit for the fourth

character and starts framing. The fourth character is a sync

character with bad parity and a valid STOP bit. Therefore,
at the center of the STOP bit the PE flag is asserted causing
PAR ERR H and RX ERR H to assert; 200 ns later, MDET

H and the DR flag are asserted. DATA RDY H asserts

causing RX DONE (1) H to assert generating

a RCVR

interrupt request. The program responds, DTI SEL 2 L
asserts, CLR STA « DR L asserts, DR clears, DTI SEL 2 L

clears, and

RX DONE (1)

H clears; thus

the SYNC

character was not stripped due to a parity error.
43.7

XMTR

Logic

Operation — The

following

para-

graphs provide a detailed description of the XMTR logic in

each of the two operating modes. Figure 4-18 illustrates the
- XMTR logic. The timing diagrams (Figures 4-19 and 4-20)

illustrate logic operation in response to different program
“inputs. The character outputs from the XMTR are shown
on the timing diagrams and are numbered in the order of

their transmission.

Before the XMTR logic can be discussed, the programmed
operating parameters must be established. In the following

discussions, the only operating parameter that changes is
the mode of operation. Otherwise, the control registers are

programmed as follows for the entire XMTR discussion

XMTR Logic

The XMTR accepts parallel characters from the program

raises the TX DONE flag to request the next character, and

serially outputs the current character to the modem. Before

unless stipulated differently:

The PARCSR is programmed for an 8 bit
character with odd parity and a sync character

XMTR operation can begin, the XMTR logic must be
- initialized and the PARCSR and TXCSR
. registers pro-

grammed (Figure 4-18 and engineering drawing D5).

' 43.7.1 XMTR

Logic

Initjalization

and

Program-

ming — The XMTR logic is initialized by the CLR H input.
"CLR H asserted forces the XMTR to the idle state. In the

idle state the timing and control logic is reset, the XMTR"

The TXCSR is programmed for the normal
mode of operation (maintenance mode select
bits cleared), to enable the XMTR (SEND bit

set), to enable the XMTR output (BREAK bit
cleared), to disable TX DONE interrupts (TX

INTEB bit cleared), to enable DNA interrupts

TX DONE H flag is asserted, and the EOC L (End of

(DNA INTEB bit set), and to operate in the full

Character) flagis asserted.

duplex mode (HALF DUP bit cleared).

4-35

. viva

203 7

Mv3y8(1)H

- omsg8I-f YILINXo1I30T

L W (O) OOSW
M31S1934 HLWX

43X3NdILTNN

XH170

1114

- 4Nn8ax1

410 H

431S1934

4-36

CLR H'___J_—-lk
LD PARCSR
(O) H

‘

ISOC H

.‘I»

LD TXCSR HB/LBH

SEND ()H

BREAK (DH |

;

LD TXDBUF (O)H

XMTRSER!ALDATAOUTHV'

EéCL—l _

— |

SECOND CHARACTER

VAR

THIRD

CHARACTER

—

DTISEL 4L
RST DNA

s|{v[n]clciulalr]|els|[y|[n|[c|c|u]a]r]A|[o]a]r]alc|u]alr]er

TX INTEB (DH —L

PNAINTEB ()H —L \{

FIRST CHARACTER

U |

::2 J
|
11-2327

Figure 4-19 XMTR Synchronous Mode
|

Timing Diagram

4-37

4.3.7.2.1

Synchronous Operation— In the synchronous

4.3.7.2.2

mode, once the XMTR is enabled and outputs the first
character bit stream, it will continue to output characters

Isochronous

Operation —In

the

isochronous

mode, the XMTR adds START and STOP bits to- each
character transmitted. If the program fails to load the

TXDBUF before transmission of the current character is

contiguously using fill characters whenever the program

- complete, the XMTR simply pauses until the TXDBUF is

fails to load the TXDBUF.

loaded. As a result, fill characters are never transmitted and

As previously stated, the program prepares the XMTR for

the DNA output is never asserted.

operation
by initializing the XMTR logic and programming

Once the XMTR is initialized, the PARCSR and TXCSR

the PARCSR and TXCSR (Figure 4-19). In the synchro-

registers are programmed. In the isochronous mode, bit 13

nous mode, bit 13 of the PARCSRis set.

of the PARSCR is cleared. Note that the TX INTEB b1t is

set in the following discussion (Figure 4-20).

The prOgram then initiates character transmission by
loading a sync character into the TXDBUF causing TX

The

DONE H to clear. When the TXDBUF load strobe resets,
the

XMTR synchronizes on the

program

then

initiates

character

transmission

loading a character into the TXDBUF, thereby clearing TX

HIGH to LOW

DONE H. After the TXDBUF load strobe clears, the XMTR

transition of TX CLK H, delays until the next LOW to

synchronizes on the next HIGH to LOW transition of TX

HIGH transition of TX CLK H, and then transfers the

- CLK H and delays until the next LOW to HIGH transition

contents of the TXDBUF plus a parity bit if programmed

of TX CLK H. When TX CLK H asserts, the XMTR

into the XMTR register. The XMTR then places the first bit

transfers the contents of the TXDBUF plus START, parity

of the first character (bit S) on the TRO (Transmitter

(if programmed), and STOP bits into the XMTR register,

Output) line, asserts TX DONE H, and clears EOC L.

places the START bit on the TRO line, and asserts TX

DONE H. When transmission of the START bit is complete,
the XMTR places the first character bit (bit D) on the TRO

The XMTR then serially shifts the first character onto the

line and clears EOC L. While the XMTR serially shifts the

TRO line. When the parity bit is placed on the TRO line,

first character bits onto the TRO line, TX DONE H causes
a

the XMTR asserts EOC L. At the center of the parity bit,

XMTR interrupt request. The program responds by reading

the TXDBUF is checked to determine whether the program

the TXCSR and loading the second character into the

has loaded in another character. In this case the program

TXDBUF, thus clearing TX DONE H.

did not service the TXDBUF because the TX INTEB bit
was cleared; hence, the XMTR interrupt request was not

When the XMTR completes transmission of the parity bit,

generated. To maintain continuous transmission, the XMTR

the STOP bit is placed on the TRO line and EOC L is
asserted. The next character has been loaded into the
TXDBUF and the TXDBUF load strobe has cleared;

transfers the contents of the fill register (a sync character)
plus parity into the XMTR register, places the first bit on

the TRO line, clears EOC L, and asserts DNA H causing a

therefore, when the XMTR completes transmission of the

XMTR interrupt request. The program responds by reading

STOP bit, the contents of the TXDBUF plus the START,

the TXCSR causing DTI SEL 4 L to assert. DTI SEL 4 L

parity, and STOP bits are transferred into the XMTR

sets the DNA flip-flop asserting RST DNA L. RST DNA L

clears DNA H, which resets the DNA flip-flop.

When transmission of the START bit is complete, the
XMTR places the first bit of the second character on the

The program then loads a data character into the TXDBUF

TRO line and clears EOC L.

and sets the TX INTEB bit in the TXCSR. When the

While the second character is being transmitted, TX DONE

TXDBUF is loaded, the TX DONE H is cleared.

H causes another XMTR interrupt request and the program

The XMTR then completes transmission of the second

responds by reading the TXCSR and loading the third

character. When the parity bit is placed on the TRO line,

character into the TXDBUF and TX DONE
H is cleared.

EOC L is asserted and, at the center of the parity bit, the
TXDBUEF is checked for the next character. At the end of

-Also during transmission of the second character, the

the parity bit, the next character (the third character) plus

program clears the SEND bit in the TXCSR thus disabling

parity is transferred into the XMTR register, the first bit is

the XMTR. Hence, after the XMTR places the STOP bit for

placed on the TRO line, TX DONE H is asserted, and EOC

the second character on the TRO line and asserts EOC L, it

L is cleared. This TX DONE H will generate a XMIR

pauses until it is enabled again. While the XMTR pauses, its

interrupt request because the TX INTEB bit is set.

TRO line continues to Mark (HIGH).

4-39

can
LD PARCSR (O)H

ISOC

[

BREAK (1) H

LD TXDBUF (O)H

N
FIRST CHARACTER

START

TX CLK

TX DONE

TX INTEB (1) H

EOC

.DTI SEL4L

SEGOND

STOP

R
~

STOP

THIRD CHARACTER

—_FOURTH

START

STOP

START

CHARACTER

STOP

T
||

CHARACTER

START

]
-

|
|

L
‘

1__]

]
.

‘
it-2328

‘Figure 4-20 XMTR Isochronous Mode
Timing Diagram
4-41

When the program enables the XMTR by setting the SEND
bit, the XMTR synchronizes

The first event is the assertion of RX DONE (1) H, which
causes the assertion of REQ A H, INTR REQ H, and BR

on the HIGH to LOW

transition of TX CLK H, delays until TX CLK H asserts,

REQ

transfers the contents
of the TXDBUF plus the START,

processor. If BUS SACK L is cleared, the processor asserts

L. BR REQ L is placed on the Unibus to. the

parity and STOP bits into the XMTR register, places the

BG IN H. BG IN H causes BUS SACK L to assert clearing

START bit on the TRO line, and asserts TX DONE H.

BR REQ L and blocking the BG OUT H signal to devices
connected to the same BR level but electrically further

If the program fails to service the TXDBUF before

from the processor. The processor receives the SACK signal

transmission of the third character is complete, the XMTR

and clears BG IN H. Assuming BUS BBSY L and BUS

simply pauses until the TXDBUF is serviced.

SSYN L are cleared from any previous bus cycles, BUS

SACK L clears immediately, the V2 flip-flop sets, BUS
BBSY L, BUS INTR L and the interrupt vector address
assert, and the CLR INTR H AND gate is conditioned. The

4.3.8 Data Set Change Detector Logic
- The data set change detector logic monitors the modem

processor receives BUS INTR L, waits 75 ns to allow for

control lines, routes the lines to the data output multiplexer as part of the RXCSR, and asserts DATSET CH (1)

Unibus skewing, and asserts BUS SSYN L. BUS SSYN L
asserts CLR INTR H and CLR INTR L. CLR INTR H sets

H whenever thereis a changein any one of the control lines

the REQ A flip-flop, which combines with the V2 flip-flop

(engineering drawing D6).

to inhibit further RCVR interrupt requests; CLR INTR L

clears INTR REQ H, which clears the busy flip-flop thereby

~ All five control lines are electrically identical and consist of

clearing BUS BBSY L, BUS INTR L, the vector address,

a receiver, a 600 ns delay line and an Exclusive-OR gate.

and CLR INTR L.

Any level change at the receiver input is applied immediately to one Exclusive-OR input and delayed a minimum of

The interrupt control logic will now begin processing the

600 ns from the other input. This produces a 600 ns pulse

TX DONE flag, which was raised a short time after the RX

at the output of the OR gate. Hence, the Exclusive-OR gate

DONE flag. The TX DONE

flag asserted REQ B H;

is satisfied causing the DATA SET CH f{lip-flop to set

therefore, INT REQ H asserts again as soon as CLR INTR L

~asserting DAT SET CH (1) H. When the program reads the

RXCSR, DTI SEL O L is asserted resetting the DATA SET

responds by asserting BG IN H.

CH flip-flop on its trailing edge.

cleared. BR REQ L then asserts and the processor

Meanwhile, the processor begins

executing the

RCVR

~interrupt service subroutine and reads the RXCSR causing
4.3.9
The

Interrupt Control Logic
interrupt

control logic enables the DUll

the assertion of DTISEL O L. DTI SEL O L clears REQ A H

after a 20 ns delay, thereby resetting the REQ A flip-flop

to gain

and

control of the Unibus (become bus master) and cause the
~

processor to branch to an interrupt vector that contains the

new PC and PS words (engineering drawing D4).

enabling subsequent RCVR interrupt flags to be

processed.

The assertion of BG IN H, on the other hand, initiates

Before RCVR and XMTR interrupts can be generated, the

basically the same sequence of operation as just described

~RXCSR and TXCSR must be programmed to enable the

for the RX DONE flag with one exception, the V2 flip-flop

interrupt control logic. In the operations discussed in the

is always reset when XMTR interrupt flags are processed,

following paragraphs, the RX INTEB and TX INTEB bits

thereby asserting bit 02 (BUS D02 L) of the interrupt

are set in the RXCSR and TXCSR, respectively; hence, the

vector address.

interrupt control logic can be activated by a RX DONE or

In reference to the BG OUT H output of the interrupt

TX DONE flag. If RX DONE and TX DONE flags occur

control logic, note that BSY (1) L asserted or INTR REQ H

simultaneously, the RX DONE flag takes priority.

cleared asserts EN GR H, provided BUS NPR L is cleared. If

In the sequence of operations illustrated by the interrupt

. BG IN H is asserted while EN GR H is asserted, BG OUT H

control logic timing diagram (Figure 4-21), it is assumed

is asserted thus propagating the grant to the next device on
the Unibus. The assertion of BUS NPR L absolutely inhibits

that the Unibus is clear and that all inputs are cleared with
~ the exception of RX INTEB (1) H and TX INTEB (1)
H.

the propagatlon of the grant.

4-43

T \ RN

_—

Figure 421 Interrupt Control Logic
Timing Diagram
4-45

CHAPTER 5
' PROGRAMMING REQUIREMENTS
AND RECOMMENDATIONS

5.1

INTRODUCTION

5.2.3

To program the DU11 in the most eff1c1ent manner, the

Detecting the Last Character of the Message

When it is necessary to know when the entire message has

programmer must understand fully the control signal and

been

timing requirements of the device. The following paragraphs discuss DU11 operation from a programming point

~ follows:

of view and describe recommended programming methods.

It is beyond the scope of this manual to provide detailed

transmitted, the

Just prior
to loading the last character of the
message into the TXDBUF, clear the TX DONE

programming information. For more detailed information
~on

programming

general,

refer

Software Programming Handbook,

and the individual program hstlngs

DUll may be programmed as

INTEB bit and set the DNA INTEB bit.

to the Paper-Tape

~b.

DEC-11 XPTSAA-D,

When t{he last character is loaded into the
register, the TX DONE bit will set but will not
cause
an interrupt request.

5.2 PROGRAMMING THE TRANSMITTER IN THE

- C.

'SYNCHRONOUS MODE

After the last character is transmitted, the
transmitter will transmlt the ssynccharacter and

assert DNA whrch causes an 1nterrupt request.
5.2.1

Loading the PARCSR

Once the transmitter is initialized via the BUS INIT pulse or

MSTRST, the PARCSR register must be programmed

The DNA 1nterrupt is notification to the
program

(loaded) to select the mode of operation (synchronous in

that the entrre message has been

transrmtted

this case), character length, and parity. At this point the
Sync register will contain all ones. Before any necessary

5.2.4

handshaking is done with the modem, the program must

Synchronization

Transmitting Initial Sync Characters to Establish

’

load the Sync register with the desired character. When the

The transmission of initial sync characters can be accom-

Sync register is loaded, the character will be used for both

phshedin one of two Ways .

XMTR and RCVR operation.

a.
5.2.2

The program may arrange its data buffer such

Enabling the Transmitter

- that the requlred number of sync characters

Once handshaking is complete, the program can assert the

precede any messages. In this case, the Sync

SEND bit in the TXCSR. When SEND is asserted, the

XMTR
is enabled but will not start transmitting data until

character If the Sync register is not loaded, it

the first character isloaded into the TXDBUF. If SEND is
cleared during transmission, the character currently being

or may not contain the Sync

- will contain all ones subsequent toa BUS INIT |

or MSTRST

transmitted will be completed, the transmit line will go to a
mark hold state, the internal XMTR logic will enter the idle
state, and synchronization with the RCVR will be lost.
When SEND is cleared, there is no guarantee that the TX

)

Assuming that any necessary handshaking has

~been

DONE bit will be asserted when current character trans-

m1ss1on is complete

5-1

completed

and

that

SEND has been

asserted, the program can commence transmission by loading a sync character into the
'TXDBUF. When the first data bit is transferred

If the latter method is chosen, it can be programmed in one

to the communication line, the TX DONE bit
will be asserted. If the TX INTEB bit is set,an
interrupt request will be generated, and the
program must load another sync character into

of two ways. The first way would be to set the DNA.

INTEB bit and clear the TX INTEB bit. The program would
then ignore the TX DONE bit and the XMTR would
transmit a sync character and assert DNA. The program’

the TXDBUF.
0

el synC

would monitor the DNA bit and, when the desired number
character

was

initially

of sync characters are transmitted, set the TX INTEB bit

loaded

synchromzatron

~thereby enabling the TX DONE interrupt. The program

- cannot~be guaranteed ‘unless the program

- would then respond to the TX DONE interrupt by loading

(1/baud rate X bits per “char) seconds- 1/2 (bit

o the transmission of sync characters. The second way would

;;hrntotheSync register,

not

then

.+, responsetime to the TX.DONE bit is less than.

a message character into the TXDBUF, thereby terminating

time). This can be verified by the absence of

be to clear the TX INTEB and DNA INTEB bits for a given

the DNA bit in the TXCSR.

period of time during message transmission thereby
allowing sync characters from the sync register to be

transmitted.

bTheprogramcan.. also enable transmrssron of

— 1n1t1alsynccharacters from the Sync reg1ster
Assummg any necessary handshakrng is. com-

NOTE

plete and SEND is asserted, the program loads

- DNAINTEB bit, and clears the TX INTEB bit.

- for the duration of the message; any on to off

transition will cause the XMTR to enter an idle

The programthen loads async character into
the TXDBUF and transmrssron begins. The TX

... DONE interruptis inhibited so the contents of

,_‘.;‘_'the Sync regrster are- transferred to the XMTR
register upon the completron of transmission of

state after completion of current character

.transmission

PROGRAMMING THE RCVR IN THE [NTERNAL

Once the program has completed any necessary handshakmg, the receiver logic can be enabled. The program
enables the receiver logic by setting the SCH SYNC (Search
Sync) bit in the RXCSR. Assuming a sync character has
been loaded into the Sync register (this must be donein the

, character is then transmitted and a DNA

.f,t.,.,\rnterrupt1s generated notrfyrng the program.

. The program then allows the transmission of

~sync characters to continue by simply monitor-

‘internal synchronous mode), the receiver begins to compare

~_.ingthe DNA until the desired number have

~incoming character bits with the character held iin the Sync

:vfbeentransmrtted‘Notethat DNA is reset each
time the program reads the TXCSR and set

again when the first bit of the next sync

NOTE

“For the receiver to become synchronized wrth

XMTR' either one or two contiguous sync

~ characters must be received. The number of

It is suggested that a mrmmum of f1ve

sync characters required is jumper selectable.

sync characters be transmitted. In Sys-

‘

The standard configuration requires two sync

temsthat are prone to error because of
.lost synchronrzatron as many as twelve

characters.

_synccharacters may. be desrrable |

NOTE

Though the DU11_may be Jumpered to. .

synchronlze on two contlguous sync characters,

When the desrred number of sync characters have been
transmrtted the. program sets the X INTEB bit, thereby
enabling the TX DONE interrupt, and responds to the
1nterrupt by loadrng a message character into the TXDBUF.

5 2 5 Transmlttlng SyncCharacters - to
Synchronization
o
|

NOTE

character is-placed on the c,o;mmunrcatron line.

MODE
SYNCHRONOUS

first sync character. The second sync

the

,The SEND bit in the TXCSR must. remaln set

the Sync registerwith a sync character, sets the

- there is a srtuatlon which, if it develops will
) prevent RCVR synchromzatron on only two
contiguous sync characters. If, while the DU11

. is searching for synchromzatlon it recognizes a

Maintain

After. synchromzatron has been achreved 1t can be main-

tained by the program by inserting sync characters into the
message or by ignoring the TX DONE bit, thereby allowing

sync characters from the Sync register to be transmitted.

5-2

sync . character that is not followed con-

tiguously by a second sync character the- RCVR 1nternal logic resets, thereby 1nh1b1tmg:
the RCVR bit detection logic for two bit times.
Should the first bits of a proper sync character
sequence occur during that two bit time period,
the RCVR will fail to achieve synchronization.

When two contiguous sync characters are received, the REC

5.4 PROGRAMMING THE RCVR IN THE EXTERNAL

ACT (Receiver Active) bit is set and any characters received

SYNCHRONOUS MODE

after that will cause RX DONE interrupt requests, provided

The external synchronous mode enables the RCVR logic to
set to the synchronize state immediately upon the assertion

the RX INTEB bit is set and the STRIP SYNC bit is

cleared.

of the SCH SYNC (1) H input. This mode is designed for
use with communication equipment capable of accom-

plishing synchronization external to the DUI1. When the
program sets the SCH SYNC bit, the REC ACT bit sets and
the RCVR starts framing characters on the very next bit

NOTE

The SCH SYNC bit must remain set for the
duration of the message. If not, the character

received. When the selected number of bits are received, the

being received at the time of the on to off

received character is transferred into the RXDBUF and the

transition will be lost along with synchroni-

RX DONE bit is set causing an interrupt request. All other

zation.

~ features and parameters of the internal synchronous mode
apply to this mode also.

If the programmer wishes the RCVR to discard all sync
characters after synchronization is achieved, the STRIP

5.5 PROGRAMMING THE XMTR IN THE ISOCHRO-

SYNC bit in the RXCSR must be set. The STRIP SYNC bit

NOUS MODE

~ inhibits the RX DONE interrupt whenever a sync character
is received with no errors; however, the sync character is
still

held

the RXDBUF until the next

5.5.1

character is

Loading the PARCSR

Once the XMTR is initialized via BUS INIT or MSTRST,

received.

the PARCSR must be programmed to select the mode of

If the program fails to read the RXDBUF in response to a

parity. It is not necessary to load the sync register in this

operation (isochronous in this case), character length, and

RX DONE interrupt, overrun errors will occur. When the

mode as sync characters are not required to achieve

RXDBUF is not serviced in the time required to receive the

character,

i.e., (1/baud rate X bits

per

synchronization and the transmitter is not

character)

required

transmit continuously.

seconds, the character presently being held in the RXDBUF
is

overwritten

by the next received character and the

5.5.2

OVRN ERR (overrun error) bit is set in the RXCSR.

Enabling the XMTR

When the required handshaking is complete, the program

sets the SEND and TX INTEB bits and loads a character
into the TXDBUF. The XMTR adds the START and STOP

bits and transmits the character to the modem. As soon as

NOTE

The

the first character bit is placed on the communication line

information in the following paragraph

by the XMTR, the TX DONE bit is asserted and remains

must be strictly adhered to or RCVR synchro-

asserted until the XMTR services the TXDBUF or clears the

nization problems will be encountered.

SEND bit.

If the DU11 is configured to achieve synchronization on

5.6

PROGRAMMING THE RCVR IN THE ISOCHRO-

two contiguous sync characters then receiver operation may

NOUS MODE

be terminated (after the entire message is received) by

RCVR operation is initiated by the assertion of SCH SYNC.

simply clearing the SCH SYNC bit in the RXCSR. However,

When the program sets the SCH SYNC bit, the REC ACT

if only one character is required
to achieve synchronization,

bit sets and the RCVR starts framing characters upon

receiver termination is a little more complex. If the SCH

receipt

SYNC bit is cleared while a sync character is present in the

selected number of character bits are received, the RCVR

- RXDBUF, false synchronization will occur when the

of the START bit from the XMTR. When the

‘tests the line for a valid STOP bit, transfers the received

receiver is enabled (SCH SYNC bit set) to receive the next

character into the RXDBUF, and sets the RX DONE bit. If

message. The program must ensure that this does not

the STOP bit is not detected, the FRM ERR (Framing

happen by transmitting a pad character, i.e., a non-sync

Error) bit is also set. If the program fails to service the

character, immediately after the transmission of the termi-

RXDBUF before the next characteris framed, the OVRRN

nating control character.

ERR bit is set.

5-3

CHAPTER
6

MAINTENANCE

6.1 SCOPE

The

This chapter lists fequired test equipment and provides a

preventive

maintenance

schedule

depends

on the

environmental and operating conditions that exist at the

complete description of DU11 prevent1ve and corrective

installation site. Under normal conditions, recommended

mamtenanceprocedures

preventive maintenance consists of inspection and cleaning

62 -MA:II\ITENANCE?PHIL'OSOPHY

occurs first.

Basically, DUl1 maintenance consists of preventive and
corrective maintenance procedures, diagnostic programs,

temperature, humidity,

every 600 hours of operation or every 4 months, whichever
However, relatively extreme

dust,

and/or

conditions of

abnormally heavy

- work loads demand more frequent maintenance. In any

and amaintenance ‘log. The preventive maintenance pro-

case, the diagnostic programs should be run once per week

cedures are performed regularlyin an attempt to detect any
detenoratmndue to aging and any damage caused by

as part of the normal preventive maintenance schedule.

improper handling of the module. The corrective maintenance procedures are performed to-isolate and repair faults

6.4 TEST EQUIPMENT REQUIRED

in module circuitry only after it has been determined that

Maintenance procedures for the DU11 require the standard

the module is faulty. The maintenance log is used to record
all maintenance activities for future reference arnd analysis;

test equipment and diagnostic programs listed in Table 6-1,
in addition to standard hand tools, cleaners, test cables, and

hopefully, the log will facilitate future maintenance action

probes.

and aid in- detectmg any component failure pattern that

- may develop.

6.3

PREVENTIVE MAINTENANCE

6.5

CORRECTIVE MAINTENANCE

Preventive maintenance consists of tasks performed at
periodic’ intervals to ensure proper equipment operation
and ‘minimum unscheduled downtime. These tasks consist

within the DU11 module. Hence, the technician must be

of running

otherwise equipped to determme that the DUll is, in fact

diagnostics, visual

inspection,

The corrective maintenance procedures are designed to aid

the maintenance technician in isolating and repairing faults

operational

checks, and replacement
of marginal components.

at fault.

Table 6-1
Test Equipment Required

Equipment

Manufacturer

Designation .

- Multimeter

Triplett or Simpson

Model 630-NA or 260

Oscilloscope

Tektronix

Type 453

X10 Probes (2)

Tektronix

P6008

Module Extender

DIGITAL

W984 (QUAD Helght)

Modem Test Connector

DIGITAL

H315A

DIGITAL

MAINDEC-11-DZDUA

- Diagnostics (Maindecs)

6-1

RCVRlogic.The technician uses standard test equipment

connecting the interface from the modem. This is made
possible by maintenance mode logic that electrically
inhibits the clock and data channels [MS 00 (0) H cleared]
between the interface and the modem. Note, however, that
the modem control lines are not inhibited; therefore, care
must be taken when this mode is programmed not to

(scope and probe) to further isolate the fault to a specific

activate any of the modem control lines.

The diagnostic programs comnprise the basic tool used by
the technician to isolate faults. The diagnostics exercise the
DUI11

in three distinct maintenance modes and provide

printouts indicating the results. The printouts point the
technician to a particular logic area such as the XMTR or

c1rcu1t component

6.5.1

When the internal loop maintenance mode is programmed,

Maintenance Modes

the maintenance mode select bits (MS 01, MS 00) establish
the required operating conditions as follows (Figure_ 6-1 and

The three maintenance modes are:
-

System Test

'b.

Internal Loop =~

External Loop

6.5.1.1

engineering drawings D5 and

D6)'

~a.

MS 00 (0) H is cleared thus:1nh1b1t1ngthe“

modem clock inputs" (TRS-CLK -and :REC

CLK), the modem input to the RCVR input

System Test Mode — This mode is selected by the

select

logic

(SERIAL DATA IN),

and the

XMTR output tothe modem (SERIAL DATA

system test diagnostic program. The system test diagnostic

exercises all devices and interfaces connected to the Unibus

and is run with the DU11 connected to the modem. The
following operations are performed to exercise the DU11

(Frgure 6-1):

. enablingthe program 1nputto. the RCVR wvia

_,MS Ol (1) H and MS OO (0) Hare. cleared thus

The system test clock located within the DU11
-

is enabled [MS 01 (1) H and MS 00 (1) H
asserted] and provrdes clock pulses to the

:.When programmlng the

RCVR and XMTR

the RCVR input select loglc[MAINT DATA
(1) H] and theRX INP H1nput to the TXCSR

The XMTR and RCVR are enabled [SEND (1)

mternalloop_,._

maintenance mode, ensure
that SERIAL . -

- DATA OUTH is disabled (BREAK bit ..
;.set) Whenever the MAINT DATA. (1) H

H and SCH SYNC (1) H asserted].

input to the RCVR input select logic-is: - .

A character is loaded into the TXDBUF.

active.

d. '_'The XMTR output (SERIAL DATA OUT H) is

routed to the RCVR viathe RCVR input select

¢c.. - MS 00 (1) H isasserted -thus-enabling .the

programmable. srngle step clockinput [SSCLK

(1) H]to drive the RCVR-and XMTR and the

- . XMTR output to the RCVR via the RCVR

The program monitors the RX DONE and the

input select logic (SERIAL DATA OUT H).

RXDBUF for errors.

Once the operating conditions are established, the program

6.5.1.2 Internal Loop Mode — This mode is designed to
o

performs the following operations:
.~ isolate the faults within the DU11 to one of the following.

logic areas:

The single step clock is programmed (by alter

RCVR

DNA

nately setting and clearing the SS CLK bit) to
._provrde clock pulses to theRCVR and XMTR.

XMTR

RX DONE

b, TheRCVRand XMTRareenabled.

TX DONE

. c.._. A character is loaded into ,the. _TXDBUF

Synchronization

" The internal loop maintenance mode 'enables the program
to

exercise

the

interface logic without physically dis-

6-2

| d

.The XMTR then serrallyoutputs the character

to the RCVR via the SERIAL DATA OUT H
lme

DUII-EA

MODULE
.

[CLoCK TCONTROL LOGIC (D5)

SS CLK (@) H

jr—\

CLK EXT

TXCSR DATA

(1)

l
H

RX INP H

SEND (1)
H

(DS)

|
{>

TTL REC CLK

TTL

|
L.

—

TX CLK H

BERG

‘

LEVEL |0NNECTOR
|“¥

CONVERTER

BELL

303

MODEM

‘?

TTL CARRIER

TTL

SEC

REC

— ——

I
_I

MODEM TEST CONNECTOR

(WIRING SHOWN) (SEE NOTE 1)

2aN\EIA_CLK EXT

PARCSR DATA

TXDBUF

DATA

— — a— a—

fRCVR

SEND (1) H
.

| ‘

INPUT

SELECT

RX CLK' H

COMPUTER

DATA

PARCSR DATA

—»{

oLXCSR DATA

|RXDBUF DATA

RX_DONE (1) H

(D5,D6)

TX DONE H
BUS
DRIVERS

DNA H

pata

(A)dllJJ'll';llJI

_CLK EXT

TRS

oLk Exe

CLK

EIA

TRS

REC CLK

EIA REC CLK

SERIAL DATA OUT H

EIA

XMIT

STRIP SYNC (1) H

__RXCSR DATA

SCH SYNC (1) H

SEC TX (0) H

MuLTI-

RTS

(0)

DTR (0)

SERIAL

DATA

SEC TX (0) H\
‘;

RTS

(0)

25>NOT USED

QEIA RING

“1

EIA LEVEL

SEC XMIT
EIA
EIA REQ TO SD

CONVERTER

L
1

EIA DATA TERM RDY

)

I
>

BERG

| CONFIGURATION

}

DUII-DA

(

EIA SERIAL DATA IN

DONE (1) H

_RXDBUF DATA

QEIA CLR TO SD

(D5,D6)
RX

4>EIA REQ TO SD

DTR (O) H

MSOO (0) H
RXCSR

-\__20>EIA DATA TERM_RDY
\EIA CARRIER
8>

DATA

yoNEIA_SEC REC

CLK

SET RODY

J\EIA SEC XMIT

( |

]
! SERIAL DATA OUT H

PDP-11

SEIA DATA_

r RCVR LOGIC

CLK

s\EIA
SERIAL DATA IN
/

_.L|

TRS

|17 E!A_REC CLK

2>(EIA XMIT DATA
e
CONNECTOR]

RXCSR

cincH

XMTR LOGIC
(05)

. (D3)

DFI1 -G
DATA

TTL DATA SET RDY

) RX CLK H

—

gggEhEA

'\ (BCOIW-25)

TTL CLR TO SD

REC CLK

SERIAL

‘
RING 1
TTL

DTR (@) H

TRS CLK

‘

CONNECTOR

TTL TRS CLK

CLK

BURNDY

RTS (@) H

SEC TX (@) H

EXT

SERIAL DATA OUT H

CLK

CONFIGURATION

y5NEIA

'BUS

UNIBUS

,
|

]

‘

RECEIVERSi

(D3)

]

SEND (1) H

MAINT DATA (1) H
BREAK .(1) H _

'SS CLK (1) H
DUP

MSO0 (0) H

HALF

MS00 (1) H

TXCSR

SYS TST CLK

|
MSO{

CINCH
CONNECTOR

)

> CONNECTOR!

‘J

MODEM

|
,

CABLE
(BCO5C-25)

BELL
201

MODEM

—

(D3)

RING

EIA

_ CLR_TO SD
DETECTOR

(D6)

SEC

REC

_ DATA SET RDY

RING 1

EIA CLR TO SD
EIA SEC REC

(DS, D6)

- EIA DATA SET RDY

Mod'ertr; t_estI ?fr:inec':or

mus

Q instalied

wnen

testing in external

loop maintenance mode

$1-2330

Figure 6-1

DU11 Maintenance Diagram

6-3

The program then monitors the RX INP bit, the RX DONE

MS 01 (1) H is asserted thus enabling the

bit, and the RXDBUF for errors. To further isolate any

programmable single step clock input [SS CLK

errors that may be detected, the program sets the BREAK

(0) H] to drive the RCVR and XMTR via CLK

bit and inputs data directly to the RCVR via the MAINT

EXT output to the modem test connector.

" DATA (1) H line.
Once the operating conditions are established, the program

6.5.1.3 External Loop Mode — This mode is designed to
isolate faults occurring in the cabling connecting the DU11
to the modem, as well as faults within the DU11 level
‘converters and data set change detector logic. Before this

performs the following operations to check out the modem
cabling.

mode can be executed the interface must be physically

disconnected from the modem and the modem test

The single step clock is programmed to activate
the EIA CLK EXT output

connector (H315A) installed at the modem end of the

which is looped

back by the modem test connector and applied

BCO5C modem cable. Figure 6-1 illustrates the proper

to the TRS CLK and REC CLK input lines.

FRN

installation of the modem test connector

When the external loop maintenance mode is programmed,
the maintenance mode select bits establish the required

The RCVR and XMTR are enabled.

A character is loaded into the TXDBUF.

operating conditions as follows (Figure 6-1 and engineering
drawings D5 and D6):
a.

MS 00 (0) H is asserted thus enabling the TRS
CLK and REC CLK inputs to the clock control
logic, the

SERIAL DATA IN input to the

~d.

RCVR input select logic and the XMTR output

to the modem test connector (SERIAL DATA

back to the interface where it is applied to the

OUT H).

The XMTR then serially outputs the character
to the modem test connector. which loops it
RCVR via the SERIAL DATA IN line.

MS 01 (1) H and MS 00 (0) H are asserted thus
enabling the program input to the RCVR via
the RCVR input select logic [MAINT DATA
(1) H] and the RX INP H input to the TXCSR.

The program\then monitors the RX INP‘bitv, the RX DONE
bit, and the RXDBUF for errors. To further isolate any
- errors that may be detected, the program sets the BREAK

NOTE

When programming the external loop
maintenance mode, care must be taken to
ensure that SERIAL DATA OUT H is
disabled (Break bit set) whenever the
MAINT DATA (1) H input to the RCVR
input select logic is active.

bit and inputs data dlrectly to the RCVR via the MAINT

DATA (1) Hline.
To

check

out

the

modem

control lines, the program

individually sets and clears the modem control bits (bits 01,
02, and 03 in the RXCSR) and monitors the modem
|

6-5

control lines and the DAT SET CH bit for errors.

APPENDIX
A

'REPRESENTATIVE MODEM

FACILITIES AVAILABLE
Manufacturer .

Model.

- Speed

- (Maximum)

Half or

Syncor | . Type of Line

Full Duplex

‘Comments

Async

Bell System

103A

300 baud

Full Duplex

Async

DDD

Bell System

103E

300 baud

Full Duplex

Async

DDD

Similar to 103A

Bell System

103F

300 baud

Full Duplex

Async

Private

Bell System

113A

300 baud

Full Duplex

Async

DDD

Originate Only

Bell System

113B

300 baud

Full Duplex

Async

DDD

Answer Only

‘Bell System

201A

2000 baud

Either

Sync

DDD

.
Bell System

201B

2400 baud

Either

Sync

Bell System

202B

1800 baud

Either

Async

DDD

202C

1200 baud

Either

Async

DDD

Bell System

Full Duplex on

2 calls

Private
Full Duplex on

2 calls

Bell System

202D

1800 baud

Either

Async

Private

Bell System

205B

600 baud

Full Duplex

Sync

Private

1200 baud

2400 baud

Bell System

202E

Series

1200 baud

Trans Only
|

Bell System

~ 301B

40,800

Bell System

303B,

19,000 to

C,D,E

230,400

baud

Async

Fither

DDD
Private

Sync

Private
Wide Band

Either

Sync

Private

Wide Band

baud
Bell System

811B

110 baud

Western

118-1A

180

Either

Async

- TWX
Network

Union

Telegraph

Western

1601-A

600

Voice

2121-A

1200

Voice

2241-A

2400

Union

Western
Union

Broad Band

Western

Either

Union

Broad Band

Western

- Union

Fither

100

200

Either

A-1

Async

Voice

Manufacturer

Model

Western

100

Union
Western

300

Union

Half or

Sync or

(Maximum)

Full Duplex

Async

2400

Either

18,000

Either

Type of Line

Voice

Async

|
-

40,000

Rixon

FM-12

Rixon =

Sebit 48

General
Electric

- TDM
220

Speed

|
|

Sync
|

Broad Band
|

1200

- Either

Fither

Voice

4.800

‘Either

Sync

Voice

2,400
-

Either

Private
Bell 4B

A-2

Bell 4A
Bell 4C

Comments

APPENDIX B
ADDRESS ASSIGNMENTS
B.1

FLOATING VECTORS

These addresses are assigned in order starting at 760010 and

There is a floating vector convention used for communications (and other) devices that interface with the PDP-11

proceeding upward to 763776. Refer to Table B-2 for
floating address sequence.-

computer. These vector addresses are assigned, in order,

starting at 300 and proceeding upwards to 777. Table B-1

Table B-1

shows the assigned sequence. It can be seen that the first

Priority Ranking
for Floating Vectors

vector address, 300, is assigned to the first DC11 in the

(starting at 300 and proceeding upwards)

system. If another DC11 is used, it would then be assigned

vector address 310, etc. When the vector addresses have

been assigned for all the DC11s (up to a maximum of 32),

Rank

addresses are then assigned consecutively to each unit of

Device

Vector | Max. No.
Size
(in octal)

the next highest ranked device (KL11 or DP11 or DM11,
etc.), then to the other devices in accordance with the

priority ranking (Table B-1).

If any of these devices are not included in a system, the
vector address assignments move up to fill the vacancies. If
a device is added to an existing system, its vector address
‘must be inserted in the normal position and all other

DC11

KL11,DL11-A,DL11-C

DP11

10%*
10%*

32
32

4%
4*

5
6

7
8

addresses must be moved accordingly. If this procedure
is
not followed, DEC software cannot test the system.

9
10

NOTE

The floating vectors range from addresses 300
to 777, but addresses 500 through 534 are
reserved for special bus testers. In addition,
address 1000 is used for the DS11 Synchronous
Serial Line Multiplexer. Refer to Appendix A
of
the
PDP-11
Peripherals
Handbook,
addresses.

FLOATING DEVICE ADDRESS

There is a floating address convention for communication

DM11-A

DNI11
DMI11-BB

DRI11-A
DR11-C

PA611 Reader
PA611 Punch

| DT11

DX11

DL11-C,DL11-D,DL11-E

DJ11

GT40

LPS11

DQ11

DHI11

KW11-W

DU11

|
|

|
|
-

4
4

1973-1974, for a complete discussion of Unibus

B.2

16
16

10%

10*

30%

*The first vector for the first device of this type must always be on a

~(and other) devices interfacing with PDP-11 computers.

(10), boundary.

B-1

Rank | Device

Table B-2

Table B-3

Floating Address Sequence

Floating Device Address Assignments
Device

Address Boundary Starting at 760010

First Address

Number of

DJ11

IOX (N)+2
DJ11 (GAP)

760010

—

DHI1 #0

760020

DHI1 #1

760040

DHI11 (GAP)

760060

—

10 X (N) + 2 (go to next 10, 20, 30,

DQI11 #0

760070

40, 50, 60, 70, or 100 boundary)

DQI1 #1

760100

DQ11 (GAP)

760110

DUI1 #0

760120

DU11 #1

1760130

20 X (N) + 2 (go to next 20, 40, 60, or
100 boundary)
3

4 .

DQ11

DU11

10 X (N) + 2 (go to next 10, 20, 30,
40, 50, 60, 70, or 100 boundary)

N = number of each device

If, for example, a communication system is to contain two

DHI11s, two DQI 1s, two DU11s and no DJ11s, the floating
- addresses would be assigned as shown in Table B-3.

If a DU11 in 'a'systelm is not preéeded by other devices
in the floating vector area, it must have a starting address of 1600 for zero.

B-2

IC SCHEMATICS

The DUI11 1nterface employs six types of integrated circuit

INPUTS

(IC) chips in its design. A detailed schematic of each type

packaging diagram with pin number desig-

Hex D-Type Flip-Flop with Clear
Quad D-Type Flip-Flop with Clear

- 74H74

D-Type Edge-Triggered Flip-Flop

UG CI G
0

OUTPUTS

In the DU11, the 7442 is used as a 3-wire binary to octal
inputs A, B, C are decoded forcing one of eight outputs

(0—7) low (see the truth table and Figure C-1).

Octal Output
INPUT C

012345¢67
01111111

10111111

0010

11011111

0011

11101111

111110711

0110

11111101

0111

11111110

X X X

(12)
: INPUT Do——Dc—A

1110111

0101

[

Vec=PIN
16

GND=PIN
8

00O

(13) | :

Truth Table

DCBA

% L~

o e
4

GND

11-0733

decoder as input D is used as a strobe. When D goes LOW,

7442 4-LINE-to-10-LINE DECODERS

BCD Input

OUTPUT
.0

OUTPUT
1

OUTPUT 2

OUTPUT 3

OUTPUT 4

—~—

74174
74175

T 3 jaaes
3

——

Dual 4-Line-to-1-Line Data Selector

OUTPUT

—

Monostable Multivibrator

74153

——

4-Line-to-10-Line Decoder

74123

\\j:;/ YRR
Y L

7442

)

nations, and a truth table, is given in this appendix.

The followifig IC schematics are included in this appendix:

OUTPUTS
Y

OUTPUT 7

(10)

OUTPUT

Vee

including

APPENDIX C

(11)

OUTPUT

11111111

11-0734

X = Irrelevant

Figure C-1

C-1

7442 Package and Logic Diagrams

74123 MONOSTABLE MULTIVIBRATOR
- Vee

14
1 Rexty
Cext Cext

__l1e

_
2Q

10°

2
CLEAR

9o |

—

CLEAR]

Ql—

—1Q

CLEAR

— T H2HsHsaHsHeseH77Hs
—
tA

1
CLEAR

2 2Rexs GND
Cext
Cext
|

FUNCTIONAL LOGIC/PIN LOCATOR

TRUTH TABLE

INPUTS

| OUTPUTS

sB B

I
NOTE:

H=high level (steady state), L= low level (steady state),

$ = transition from low to high level, t=transition from

high to low level,

low- level pulse,

Figure C-2

_I'L_= one high-level

pulse,

"1 =one

8E-0516

X= irrelevant (any input, including transitions).

DEC 74123 IC Hlustrations

OUTPUT PULSE WIDTH
VS

EXTERNAL TIMING CAPACITANCE

Tp=25°C

T
£

4 000

—

2 000

o TAe
0“
/

°
z

700

400

‘i
-

200

a
=

100

4y 4

‘

v
»> -o‘«g
s

1
L

g
F

Ay ’\0* /
?\,"
p

P
d
T ax
=t

0%
/

—~

A“/

20
10

100200400 1000

Cext-External Timing Capacitance-pF

8E-0524

’

Figure C-3 DEC 74123 IC Output Pulse Width vs External Timing Capacitance
C-2

74153 4-LINE-TO-1-LINE MULTIPLEXER

STROBE 16
[

c{::)>

DATA

INPUTS
!

(

1D
-

’

‘

CONTROL

INPUTS
!

[

_
DATA

NPUTS
INP

:>0

- OUTPUTS

|
»—<{>

STROBE

—

CONTROL.IN?QT STROBE | OUTPUT
-

LOW

H1GH

LOW

| HIGH

LOW

HIGH

LOW

DON'T CARE
TRUTH TABLE

HIGH
|

’

DIAGRAM

LOGIC

—

”c

" Vee

ettt
2D

'
2C

!
2B

v
2Y

LOW

(EACH HALF)

I
.

1C-

) N

PIN LOCATOR

GND

(TOP VIEW OF IC)
B8E-0138

Figure C-4

74153 Package and Logic Diagram

C-3

74174 HEX/74175 QUAD D-TYPE FLIP-FLOPS WITH CLEAR

A o3

TABLE

INPUT

|OUTPUTS

th+1

tn = Bit time before
clock pulse.

(2)

TRUTH

TABLE

INPUT [ OUTPUTS
—O

CLOCK

CLEAR

th+1=Bit time after
clock pulse.

)

fn"l' 1

H
L

Irr | Ol

TRUTH

th=Bit time before

clock pulse.

th+1=Bit time after

clock

pulse.

o CLOCK
CLEAR

c o8

Q¢

(@)

(7)

(,k

CLEAR

(1)

Qaf—=TM

——Qx By

o CLOCK.

D o

CLEAR

(10)

(5)

DB' QB——O
QCLK Qgl—o

o CLOCK

CLEAR

CLEAR
¢

(13)

(12)
Qg —
O Qg

(12)

(10)

Qef—TM®

QOICLK Q¢ f—o

o CLOCK

CLEAR

CLEAR
[

14)

CLOCKC>fl

~QF

(15)

10
(9)

)

0 CLOCK

cLocko—

"\
CLEAR

CLEAR

CLEAR )
1

od b T

Pin (16)= Vo, Pin (8)=GND

Figure C-5

74174 Logic Diagram

Qpf—>2

CLEAR

(1)

Pin (16)= Ve, Pin (8)=GND

Figure C-6

74175 Logic Diagram

74H74 D-TYPE EDGE-TRIGGERED FLIP-FLOPS

complementary Q and Q outputs. Information at input D is

The 74H74 consists of two D-type edge-triggered flip-flops.

transferred to the Q output on the positive-going edge of

Each flip-flop has individual clear and preset inputs and

the clock pulse.

TRUTH TABLE (Each Flip-Flop)

Signal/Pin Designation

tn+1

Signal Name

Circuit #1

Circuit #2

INPUT

OUTPUT

OUT2UT

CLOCK

CLEAR
L

PRESET

H = high level, L = low level
NOTES:

t, = bit time before clock pulse.

th+1 = bit time after clock pulse.

Functional Block Diagram (each flip-flop)

functional block diagram (each flip-flop)

PRESET O—

CLEAR

—~

fiL—

O__I

—®

CLOCK O

Figure C-7

74H74 Logic Diagram

C-5

digital equipment corporation

Printed

U.S.A.