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Document:	DRV11-B General Purpose DMA Interface User's Manual
Order Number:	EK-DRV1B-OP
Revision:	001
Pages:	36
Original Filename:

OCR Text

general

purpose DMA

iy,i

%WMWW

interface user’'s manua

EK-DRV1B-OP-001

;

DRV11-B
~general purpose

DMA

interface user’s manual

PDPII[23 Sysksa

digital equipment corporation - marlborough, massachusetts

1st Edition, August 1976

The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in this
manual.
Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:

DEC
DECCOMM

DECtape
DECUS

DECsystem-10

DIGITAL

DECSYSTEM-20

MASSBUS

PDP

RSTS

TYPESET-8

TYPESET-11
UNIBUS

- CONTENTS

CHAPTER 1

INTRODUCTION

1.1

GENERAL DESCRIPTION

1.2

SPECIFICATIONS

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1.3

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CHAPTER 2

INSTALLATION

2.1

GENERAL

2.2

SYSTEM CONSIDERATIONS

2.2.1

LSI-11 Bus Loading

2.2.2

Power Requirements

2.2.3

Priority Requirements -

2.2.4

Space Requirements

2.3

USERI/OCABLES

“

SRR

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. . . . . . . . .

2.4

DEVICE ADDRESS SELECTION

2.5

INTERRUPT VECTOR ADDRESS SELECTION

2.6

MODULE INSTALLATION

2.7

INITIAL TURN-ON

. . . . . . .. .. ... ... ... ....
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2.8

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CHAPTER 3

BASIC OPERATION |

3.1

GENERAL

3.2

FUNCTIONAL DESCRIPTION

3.2.1

DRVII-BREZIStErS

. . . . e,
iiiiiiiiiiiiiiiiiiiiiiii

. . . . o o oo oo e

3.2.1.1

Word Count Register (WCR)

3.2.1.2

Bus Address Register (BAR)

3.2.1.3

Control/Status Register (CSR)

3.2.1.4

Input and Output Data Buffer Registers (DBRs)

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ttttttttt

3.2.2

User Interface Lines

3.2.3

LSI-1T BusLines

3.2.4

User’s 1/O Device to LSI-1 | Memory Transfer (DATO or DATOB)

3.2.4.1
3.2.5

Interrupts

nnnnnnnnnnnnnnnnnnnnnnnn

nnnn

. . . . . . . . . . . . . .
. . . . .. L

LSI-11 Memory to User’s Device Transfers (DATIO or DATI)

3.3

TIMING

CHAPTER 4

PROGRAMMING

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4.1

GENERAL

PROGRAMMING INSTRUCTIONS

4.3

DRV11-B REGISTERS

4.3.2

4.3.3

4.3.4

WCR

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4.2

4.3.1

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. . . . . . .

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‘‘‘‘‘

}

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0000000000000000000000

00000000000

0000000000000000000000

0000000000

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ii1

CONTENTS (Cont)
Page

4.4

PROGRAM INTERRUPTS

4.4.1

Word Count Overflow

4.4.2

. .. ... ... .. T

4-2

. . . ..

4-2

CSR ERRORBit (Bit15)

4.5

. . . . .. IR

. .. .. .. .. e

FUNCTION AND STATUSBITS

e e e e e

e e e e

. . ... ... ..... T

4-2
4-2

ILLUSTRATIONS

Figure No.

Title

Page

1-1

DRV11-B Simplified Interface Diagram

2-1

DRV11-B Connector and Switch Locations

. . . . .. .. e
. . . . . e

2-2

DRV11-B Device Address Select Format

2-3

DRV11-B Interrupt Vector Address Select Format

2-4

DRV11-B Connector Pin Assignments

3-1

DRVI11-BBlock Diagram

3-2
3-3
34

e e e e e e .

. . . . . . ... ... .......

. . . . . e

e e e

. . . . .. . .. .. e

. . . . . . . . . . . .«

i i i

e e e e e
e

1-2
2-3
2-3

2-4
2-4
3-2

DMA DATO/DATOB Data Flow Diagram . . . . . . .. ... ... .. ...
3-6
DMA DATIO/DATI Data Flow Diagram
. . . . . . ... ... ..... ..
3-8
DRV11-B Single Cycle, User-Initiated, Timing Diagram . . . . . . .. .. .. -39

3-5

DRV11-B Single Cycle, Program-Initiated, Timing Diagram

3-6

DRV11-B Burst Mode, User-Initiated, Timing Diagram

3-7

DRV11-B Burst Mode, Program-Initiated, Timing Diagram

4-1

CSRFormat

. . . . . . . . .. 3-10

. . . . . . . . . . .. 3-11

. .. ... ... ... ......... e

. . . . . . . . .. 3-12
e e e e e e e e

4-2

TABLES

Table No.

2-1
3-1
4-1

Title

Recommended Cable Assemblies

Page

. . . . . . . . . .« .

.. L

222

CO,ClCodes
. . . . . v v v it i e e e e e e e
e
e
e e e
CSR Bit Functions
. . . . . . . . . . .
e e e e e e e e e e e e

4-3

o v oo

CHAPTER 1

INTRODUCTION

1.1
GENERAL DESCRIPTION
The DRV11-B is a general-purpose direct memory access (DMA) interface for transferring 16-bit data
words directly between the LSI-11 memory and a user’s I1/O device. Data Transfer Out (DATO) or
Data Transfer In (DATI) takes place via the LSI-11 bus after a DMA request, where the DRV11-B
becomes bus master. Burst modes, byte addressing, and read-modify-write operation (DATIO) are

possible with the DRV11-B. The DRV11-B features switch-programmable device and vector addresses

and 40-pin connectors which provide for simple interfacing to the user’s

/O device.

Five registers are contained within the DRV11-B:
Word Count Register (WCR)
Bus Address Register (BAR)
Control/Status Register (CSR)
Input and Output Data Buffer Registers (DBRs).

The CSR and DBRs are word- and byte-addressable, whereas the WCR and BAR are only word- addressable.
|

DRV11-B operation
is initialized under progr’am control by:

Loadmg the WCR with the 2’s complcment of the number of tra.nsfers

Loading the BAR with the first address to or fmm which datais to be transferred

Loading the CSR with the desired function bits.

Data transfers may now proceed under the control of the DRV11-B DMA logic.
Figure 1-1 shows the primary interface signals between the DRV11-B and the user’s I/O device. DMA
input (DATI) or output (DATO) data transfers take place when the processor clears READY. For a
DATO cycle (DRV11-B to memory transfer), the user’s I/O device presets the CONTROL BITS
(word count increment enablc, bus address increment enable, C1, CO, A00O, and ATTN), and asserts
CYCLE REQUEST to gain use of the LSI-11 bus. When CYCLE REQUESTis asserted, input datais
latched into the input DBR, the CONTROL BITS are latched into the DRV11-B DMA control, and

BUSY goes low. (A DATI cycle memory to DRV11-B transferis handledin a similar manner, except
that the output datais latched into the output DBR during the bus cycle.)

1-1

PN
16 - OUTPUT DATA BITS

<: " 16 - DATA/ADDRESS BITS

READY

CYCLE REQUEST

BUS

FUNCTION BITS

USER'S

DRVI1-B

LSI-11

DMA

INTERFACE |

STATUS BITS

I/0
~

DEVICE

BUSY

CONTROL BITS

_BUS_CONTROL

16 -INPUT DATA BITS

11- 4155

Figure 1-1

DRYV11-B Simplified Interface Diagram

When the DRV11-B becomes bus master, a DATO or DATI cycle is performed directly to or from the
- LSI-11 memory location specified by the BAR. At the end of each cycle, the WCR and BAR are
incremented and BUSY 8Os high while READY remains low. A second DATO or DATI cycleis
performed when the user’s I/O device again asserts CYCLE REQUEST. DMA transfers will continue
asynchronously until the WCR increments to zero, at which time READY goes high and the DRV11B generates an mterrupt (if interrupt enableis set) to the LSI-11 processor.
If burst modeis selected (SINGLE CYCLE low), only one CYCLE REQUESTis requlred for the
complete synchronous transfer of the specified number of data words.
1.2

SPECIFICATIONS

The following specifications and partlculars are for informational purposes ‘and are subject to change
without notxce

Physical

Quad-—helght smgle w1dth extended length module

Dxmensmns

8-1/2 in. L, 10-1/2in. H, 1/2 in. W
(21.6 cm L, 26.7 cm H, 127cmW)

Weight

13 oz. (370 gr)

1-2

User 1/O Connections

Twa (2) 40-pm connwcwrs

|
Moummg Reqmrements SR
Plugs directly into LSI-11 backplane or LSMI expansion backplane
Electrical

Logic Power Requirements
+5V £ 5% @ 1.9 A (nominal)

LSI-11 Bus Loading
Presents one bus load

User Loading
Input Data Lines
1 TTL unit load each
HIGH = Logic one
LOW = Logic zero
Input Control Lines
1 TTL unit load each
HIGH = Logic one
LOW = Logic zero

Output Data Lines

10 TTL unit loads (drive) each

HIGH = Logic one
LOW = Logic zero
- Output Control Lines
10 TTL unit loads (drive) each
HIGH = Logic one

LOW = Logic zero

Module Type
M7950

Operational
Transfer Mode
DMA or program-controlled with interrupts
Data Transfer Rate

Up to 250,000 16-bit words per secondin smgle cycle mode
Up to 500,000 16-bit words per secondin burst mode

Environmental
Temperature

Storage: —40° to 66° C (-40° to 150° F)
Operating: 5° to 50° C (41° to 122° F)
Relative Humidity
10% to 95% noncondensing

1.3 RELATED LITERATURE
In addition to the M7950 print set, the LSI-11 PDP-11/03 User's Manual and the LSI-J ! PDP~I 1 /03
Processor Handbook contain useful information for installing and operating the DRV11-B generalpurpose DMA interface. Handbeoks may bc ordered fmm thc nearest Dngltal Equipment Corporation
Sales Office.

CHAPTER 2
INSTALLATION

2.1

GENERAL

2.2

SYSTEM CONSIDERATIONS

Installation of the DRV 11-B general-purpose DMA interface consists of selecting
the device and interrupt vector addresses and then inserting the interface into an LSI-11 processor system.

Before installing the DRV11-B into an LSI-11 system, consideration must be given to bus loading,

power, priority, and space requirements.
2.2.1

LSI-11 Bus Loading

The DRV11-B presents one bus load to the LSI-11 bus. Fifteen (15) bus loads can be handled by the
LSI-11 bus; therefore, the user must dctermme the LSI-11 bus load when installing additional LSI 11
modules.

2.2.2

Power Reqmrements

The DRV11-B requires +5 V + 5% @ 1.9 A (nominal). Power for the DRV11-B
LSI-11 system power supply.

2.2.3

is obtained from the

Priority Requirements

Each device on the LSI-11 bus has an interrupt and DMA priority based on its relative position from
the processor. Since the user may install the DRV11-B on the bus along with other devices that use the
‘same interrupt or DMA priority, the user must bear in mind that when more than one device is
requesting service, the device electrically nearest the LSI-11 microprocessor has the highest priority
‘and will be serviced first. In addition, if the REV11 DMA refresh option is used, the REV11 must be at
a priority level higher than that of the DRVI11-B. Refer to the LSI-11 PDP-11/03 User's Manual,
A ppendix G for detailed information on the REV11 options.

:22. 4 Space Reqmremems

‘The DRV11-B requires four module slots. Of the four slots, the A and B module fingers must mterfacc
to the LSI-11 bus. The C and D fingers maintain interrupt and DM A grant continuity as well as power
and ground.
2.3

USER I/0 CABLES

‘The DRV11-B has two 40-pin connectors whlch prowde the mtcrface to the user’s devnce Two cable
assemblies are required. Itis recommended that cable assemblies from Table 2-1 be used to connect the
"DRV11-B to the user’s device. The listed cables are terminated (one or both ends) with H856 40-pin
connectors that mate with the connectors
on the DRV11-B. Cable selection is determined by the type
of connections used on the user’s device. The desired cable length (XX) must be specified when ordering. (Lengths longer than 50 feet are not recommended for use with the DRV11-B.) Cables may be
ordered from the nearest Digital Equipment Corporation Sales Office. Non-standard length cavles
may be ordered at additional cost.

Table 2-1

Cable No.
BCO8R-XX

BC04Z-XX

2.4

Recommended Cable Assemblies

Connectors

Type

- Standard Lengths (ft./m.)

HB856to H856

Shielded flat

H856 to open
end

Shielded flat

1, 6, 10, 12, 20, 25, 50 ft.

0.305, 1.830, 3.050, 3.66,
6.100, 7.625, 15.250 m.

6, 10, 15, 25, 50 ft.
1.830, 3.050, 4.575, 7.625,
15.250 m.

DEVICE ADDRESS SELECTION

The DRVI11-B contains five registers:
the WCR
the BAR
the CSR
the input DBR
the output DBR.

These registers must be addressed for data and status transfers between the DRV11-B and the LSI-11

processor. The two (2) DBRs use the same address. The register addresses are sequential by even
numbers and are as follows:
Register
WCR

BAR
CSR
DB RS

BBS7
1

1
1
1

Octal Address
XXXXXO0

XXXXX2
XXXXX4
XXXXX6

The assrgned DMA interface base addressis 7724103 The user selects a basc address for assignment to
the WCR and sets the device address selection switches on the DRVI11-B module to decode this
address. The remaining BAR, CSR, and DBR addresses are then properly decoded by the module as
they are received from the LSI-11 processor.

Figure 2-1 shows the location of the device address selection switches on the DRV11-B module.
Switches are set to the ON (closed) position for bits to be decoded as ““ONE” bits in the base address.
‘Bits decoded as “ZERQ”’ bits in the address have their switches set to the OFF (open) position. Figure
2-2 shows the address select format and presents the switch-to-bit relationship for the device address
selection switches.

2.5 INTERRUPT VECTOR ADDRESS SELECTION
Vector addresses 0-17743 are reserved for LSI-11 system users. The DRVH B is assngned vector

address 1245. The user selects the interrupt vector address by means of switches on the DRV11-B
‘module. Figure 2-1 shows the location of the vector address selection switches. Vector address selection switches are set to the ON (closed) position for bits to be encoded as “ONE” bits in the vector
address. Bits encoded as “ZERO” bitsin the address have their switches set to the OFF (open) position. Figure 2-3 shows the address select format and presents the switch-to-bit relatmnshlp for the
vector address selection switches.
e

2-2

DEVICE ADDRESS

/ SELECTION SWITCHES

VECTOR ADDRESS

/ SELECTION SWITCHES

—

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o
m——

(4§

S—

(1Y

TOR——

R
LP

smssanmuoner - (R)

sy
T

s 0}

s
o

R —=]

= o

11-4156

Figure 2-1

DRVI11-B Connector and Switch Locations

DEGODEFU‘:GR

DECODED BY BBS7

‘

DEVICE

REGISTERS

‘

[

—F

mTE_J
CONTROL

o
F

07 .

SELEcvwou'”"““mmmmmflu
SWITCHES

SELECTED BY SWITCHES

B
|

‘

OFF="ZERO"
ON= "ONE"

11-4184

- Figure 2-2 DRYV11-B Device Address Select Format
2.6

MODULE INSTALLATION

With the exception of the first four slots (the LSI-11 proccssor always occupies the first slots), the

DRYVI11-B can be installed into any four slots (Paragraph 2.2.4) of the LSI-11 backplane. However, if
"REV11 DMA refresh option is used, the DRV11-B must be at a lower priority than the REV11. When
inserting the module into the backplane, make sure that the deep notch on the module seats against the
connector block rib. Do not insert or remove the module with power applied. After performing the initial
turn-on (Paragraph 2.7), connect the user’s I/O cables to J1 and J2 on the DRV11-B I/O connectors.
Connector locations for the DRV11-B are shown in Figure 2-1. Pin assignments for J1 and J2 are
shownin Figure 2-4 and are specifiedin Paragraph 1.2.

1 ST

;

OCTAL
DIGIT

‘

OCTAL

SELECTION =
SWITCHES

AS ZEROS

OFF = "ZERO"
ON = "ONE"

s
CT

<—

CYCLE REQUEST H
> READY H

H o J

-3

N
MR

» INIT V2 H

SINGLE CYCLE H —»

1-4185

DRV11-B Interrupt Vector Address Select Format

y s

<«—

AA BB

8 INH

<«—

H
9 IN

H
<—10 IN

MM NN
= o
3INH———F

<«—12 IN H

»10 OUT H

% &
4 0UT He—4

NN
3 0UT H e—e" N
M

2 OUT H ¢——1—=

OOUT

He—+}% Tl
o

Juw|

He—1—

»11 OUT H

»12 OUT H

5 INH——t—s

¢
4 IN H——
PP

»13 OUT H

2INH—»—+Fe

-»15 OUT H

ow
fuu
—
O IN Hmww—-—v-&u

»14 OUT H

<—

6 INH——oF—s

7 IN H—>

» 9 OUT H
o

FNCT 2 H

< R

» 8 OUT H

AA BB

FNCT 3 H

«— COH
<«—
Cl H

BA INC ENB
H

6 OUT H «—t—s

<—

AOO H

ATTNH

<—

°«

STATUS
CH

«—

7 oUT H «—-%C B

1 OUT

o}——«— STATUSBH

<«—

o J

» BUSY H

> INIT H
|

<«— STATUS A H

B
D.

<— WC INC ENB H

¢
C<

5 OUT H @———F—=

Q
F

Figure 2-3

;

VECTOR

ADDRESS

PREASSIGNED

DIGIT

OCTAL DIGIT
(OOR 4)

3RD

2 ND

4 TH

‘

{ IN H—»

Figure 2-4 DRVI11-B COnneCtOr Pin Assignments

‘

<«—11 INH

|
H
<—13, IN

«—14 INH

H
<+—15 IN L

11-a159

2.7

INITIAL TURN-ON

After completing the module installation, turn on the LSI-11 and initialize the system. With no I/O
cables connected, and using the LSI-11 terminal and operating procedures, perform the following:
1.

Load the addresses of the WCR, BAR, CSR, and DBRs through the system terminal and
examine the locations. The terminal will indicate the following:
WCR contents will be 000000
BAR contents will be 000001

CSR contents will be 127200
DBR contents will be 177777

The WCR and BAR can be loaded with data from the system terminal and the corresponding data read back on the terminal. BAR bit 0 will read as a one (1) with no I/O cables
connected.

The user’s 1/O device cables can now be connected to the DRV11-B (Figure 2-1).
2.8

DIAGNOSTIC PROGRAM

The check procedure performed in Paragraph 2.7 does not completely verify the operation of the
DRV11-B. Complete module operation can be verified through the use of the diagnostic software
program MAINDEC-MD-11-DVDRA-PB. The program can be loaded into the LSI-11 system by
means of a paper tape reader or a terminal. A BCO8R maintenance cable (not longer than 50 ft) is
required to loop the DBR output to the DBR input for checking the 1/O data path. A complete
description of the diagnostic software program and its implementation is provided in MAINDECMD-11-DVDRA-D.

CHAPTER 3

BASIC OPERATION

3.1
GENERAL
This chapter contains a functional description of the DRV11-B. The DRV11-B registers are described
as well as user device and bus operations necessary to perform DMA transfers. Figure 3-1 is a block
diagram of the DRV11-B. All descriptions are written to this diagram. The chapter ends with a brief
description of the timing associated with DMA transfers.

3.2

FUNCTIONAL DESCRIPTION

3.2.1
DRV11-B Registers
The DRV11-B contains five (5) registers:

Word Count Register (WCR)
Bus Address Register (BAR)
Control Status Register (CSR)
Input and Output Data Buffer Registers (DBRs).

3.2.1.1

Word Count Register (WCR) - The WCR is a 16-bit read/write register that controls the

number of transfers. This register is loaded (under program control) with the 2’s complement of the
number of words to be transferred. At the end of each transfer, the word count register is incremented.
When the contents of the WCR is incremented to zero, transfers are terminated, READY is set, and if
enabled, an interrupt is requested. The WCR is word-addressable only.

3.2.1.2 Bus Address Register (BAR) - The BAR is a 15-bit read/write register. This register is loaded
(under program control) with a bus address (not including address bit 0) which specifies the location to
or from which data is to be transferred. The BAR is incremented after each transfer and can be
~incremented across 32K memory boundaries via the extended address feature of the DRV11-B. Systems with only 16 address bits will “wrap-around” to location zero when the extended address bits are
incremented. The BAR is word-addressable only.
~
3.2.1.3 Control/Status Register (CSR) - The CSR is a 16-bit register used to control the functions
and monitor the status of the interface. Bit 00 is a write-only bit and always reads as a zero. Bits 01-06,
‘and bits 08 and 12 are read/write bits, while bits 07, 09-11, and 13-15 are read-only bits. Bit 14 can be
written to a zero. Bits 04 and 05 are the extended addressing bits. CSR bit functions are fully described
in Chapter 4. The CSR is both byte- and word-addressable.

3-1

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3.2.1.4 Input and Output Data Buffer Registers (DBRs) - The two DBRs are 16-bit registers. The
input DBR is a read-»only register; the output DBRis a write-only register. Datais loaded into the
input DBR by the user’s device and subsequently transferred to memory under DMA control by the
DRV11-B, or under program control by the LSI-11 processor. Conversely, data is written into the
output DBR from memory under DMA control
by the DRV11-B, or under program control by the
LSI-11 processor, and read by the user’s device. The input and output DBRs interface to the user’s
device by means
of two separate 40-pin 1/O connectors. These connectors may be cabled together (for
maintenance purposes) to function as a read/write register. The input and output DBRs share the
same bus address and are byte- and word-addressable.
3.2.2

User Interface Lines

There are 50 interface lines (25 per connector) between the DRV11-B and the user’s I1/O device. Of
these lines, 32 are I/O data lines, 3 are for status, and 15 are fm control. A brief description of these
interface lines follows:

Mnemonic

Descnptmn

00 OUT - 15 OUT

00 IN - 15 IN

16 TTL data output linesfmm the DRVI 1-B. One
= high.

16 TTL data input lines from the user’s device. One = high.

STATUS A, B, C

Three TTL status input lines fmm the user’s devxce Thc func«

tion of these linesis defined by the user.

FUNCT 1, 2,3

INIT
INIT V2

A00

BUSY

READY

Three TTL output lines to the user’s device. The function of
these linesis defined by the user.

~
|

One TTL output line; used to initialize the user’s device.
One TTL output line; present when INITis asserted or when
- FUNCT 2 is written to a one. Used for interprocessor buffer
applications.

One TTL input line from the user’s device. This line is normally
high for word transfers. During byte transfers this line controls
address bit 00.

One TTL output line to the user’s device. BUSY is low when the
DRV11-B DMA control logwis requesting control of the LSI11 bus or when a DMA cycleis in progress. A lowwtmhzgh transition indicates end of cycle.
|
One TTL output line to the user’s device. When the READY
line goes low DMA transfers may be initiated by the user’s

device.

Co, Cl

Two (2) TTL input lines from the user’s device. These lines control the LSI-11 bus cycle for DMA transfers. C0, C1 codes for
the four (4) possible bus cycles are listed in Table 3-1. |

Mnemonic

Description

Table 3-1 CO, C1 Codes

SINGLE CYCLE

Bus Cycle

Cco

DATI
DATIP
DATO
DATOB

0
1
0
1

0
0
1
|

One TTL input line from the user’s dcvvice, This line is intcmally
pulled high for normal DMA transfers. For burst mode operation SINGLE CYCLE is driven low by the user’s device. |
CAUTION
When single cycle is driven low, total system oper‘ation is affected because the LSI-11 bus becomes
dedicated to the DMA device and other devices,
including the MOS memory refresh function, cannot
use the bus.

WC INC ENB

One TTL input line from the user’s device. This line is normally
high to enable incrementing the DRV11-B word counter. Low
inhibits incrementing.

BA INC ENB

One TTL input line from the user’s device. This lineis normally
high to enable incrementing the bus address counter. Low
inhibits incrementing.

CYCLE REQUEST
ATTN

One TTL input line from the user’s device. A low-to-high transi-

tion of this line initiates a DMA request.

One TTL input line from the user’s device. This line is driven

high to terminate DMA transfers, to set READY and request
an interrupt if the interrupt enable bit is set.

3.2.3 LSI-11 Bus Lines
There are 34 LSI-11 bus signal lines used by the DRV11-B; 16 of these are multiplexed and bldlrectlom
al lines which carry data and address bits. Two lines are used for extended address bits, while 16 lines
are used for control signals. A brief description of the 34 bus lines follows:
-

Mnemonic

Description

BDAL
0 - BDAL 15

16 bus data/address lines. An address is first placed on these
lines followed by the data. These lines are asserted when driven
low.

BAD 16, 17
BDOUT

Two (2) bus lines used to address beyond 32K of memory by the
DRYV11-B. These lines are asserted when low.
One bus line; when asserted (low) indicates that data is available
on the BDAL lines and an output transfer (with respect to the
bus master) is taking place.
3-4

Mnemonic

Description

BRPLY

One bus line; asserted (low)in response to BDIN or BDOUT
and in response to BIAK transactions. It is gancmted by the
slave device for address recognition.

BDIN

- One bus line; whcn asserted (low) during BSYNC time,
indicates an input transfer (with respect to the bus master).
Requires a BRPLY response. BDIN is asserted when the bus
master is ready to accept data from the slave. When asserted
without BSYNC, indicates that an interrupt operation is
occurring.

BSYNC

‘One bus line; asserted (low) by the bus master to indicate that it
has placed an address on the BDAL lines. The transfer is in
progress until BSYNC is negated (high).

BWTBT

One bus line; asserted (low) during address time to indicate that
an output sequence (DATO or DATOB)is to follow. BWTBT
is also asserted during data time for byte addressing during a
DATOB.

BIRQ —

One bus line; device asserts (low) this line when its interrupt
enable, interrupt request, and ready flip-flops are set. BIRQ
informs the LSI-11 processor that service is requested.

BIAKI, BIAKO

Two bus lines; one (1) is interrupt acknowledge in, the other is
interrupt acknowledge out. BIAKI is generated by the LSI-11
processor in response to BIRQ. The processor asserts (low)
BIAK
O whichis routed to the BIAKI pin of the first device on
the bus. If the deviceis not requesting an interrupt BIAKOis
passed (as BAIAKI) to the next device.

BBS7

One bus line; asserted (low) by the LSI-11 processor when
addressing a device for program-controlled transfers. The
DRVI11-B can assert BBS7 and address other devices on the
LSI-11 bus without processor intervention.

BDMGi, BDMGO

Two bus lines; one is DMA grant in, the otheris DMA grant
out. The LSI-11 processor generates BDMGO whichis routed
to the BDMGI pin of the first bus device. If the deviceis
requesting the bus, it will inhibit passing BDMGO to the next
bus device. If the device is not requesting the bus, it will pass
BDMGO (as BDMGI) to the next device.

BINIT

One bus line; asserted (low) by the LSI-11 processor to initialize
or clear devices connected to the LSI-11 bus.

BSACK

One bus line; BSACK is asserted (law) by a DMA devicein
response to the LSI-11 processor’s BDMGO signal, indicating
‘that the DMA deviceis bus master.

BDMR

~ One bus line; a device asserts this signal for DMA requests and
to become bus master.

3-5

3.2.4

User’s 1/0 Device to LSI-11 Memory Transfer (DATO or DATOB)

Data transfers from the user’s I/O device to the LSI-11 memory are DMA transfers. Figure 3-2 1llus~
trates the data flow for a DMA DATO or DATOB cycle. Referring to Figure 3-1, DMA transfers are
initialized under program control by loading the DRV11-B WCR (in 2’s complement) with a count
equal to the number of words to be transferred; loading the BAR with the starting memory address for

DRV1I-B

‘

LSI-11 BUS

word storage; and setting the CSR for transfers.

<— DATO OR DATOB <—

k\k——-'& DATA FLOW ——

<::

USERS
DEVICE

]

| MEMORY

LSI-11
| PROCESSOR

11-4187

Figure 3-2

DMA DATO/DATOB Data Flow Diagram

When the GO bit of the CSR is written to a “one,” READY goes low and the user’s I/O device

conditions the A00, BA INC ENB, WC INC ENB, ATTN, SINGLE CYCLE (high for normal DMA
transfers), and the CO, C1 (refer to Table 3-1) lines, and then asserts CYCLE REQUEST. The INPUT
DATA BITS and control bits (CO, Cl1 and SINGLE CYCLE) are latched into the respective DRV11-B
registers. CYCLE REQUEST sets CYCLE and causes the DRV11-B to assert BDMR which makes
an LSI-11bus request and causes BUSY to go low. In response to BDMR, the processor asserts
BDMGO whichis received as BDMGI. The DRV11-B becomes bus master and asserts BSACK and
negates BDMR. The. processor then terminates the bus grant sequence by negating BDMGO.
As bus master, the DRV11-B performs a DATO or DATOB bus cycle by placing the memory address
on BDAL lines, asserting BWTBT, and then asserting BSYNC. The LSI-11 memory decodes the

address; then, the DRV11-B removes the address from the BDAL lines, negates BWTBT (BWTBT will

remain active for a DATOB) and then places the user’s input data on the BDAL lines and asserts
BDOUT. Memory receives the data and asserts BRPLY. In response to BRPLY, the DRVI1I1-B
negates BDOUT and then removes the user’s mput data from the BDAL lines. Memory now negates
BRPLY, the bus cycleis terminated, and the busis released when the DRV11-B negates BSACK and
BSYNC.
|

3-6

;,‘,,,M"”“"“”’W’”%M

At the end of the first transfer, the DRV11-B WCR and BAR are incremented, BUSY goes high, while
READY remains low. With BUSY high and READY low, the user’s 1/O device can initiate another
DATO or DATOB cycle by again asserting CYCLE REQUEST. DMA transfers can continue until
the WCR increments to zero and generates an interrupt request, if the interrupt enable bit is set.
3.2.4.1 Interrupts - When the WCR increments
to zero, READY goes high and the DRV11-B generates an interrupt request (if the interrupt circuits are enabled). The LSI-11 processor responds to the
interrupt request (BIRQ) by asserting BDIN followed by BIAKI (interrupt acknowledge). BIAKI is
received by the DRV11-B andin response places a vector address on the BDAL lines, asserts BRPLY,
and negates BIRQ. The LSI-11 processor receives the vector address and negates BDIN and BIAKI.
The DRV11-B now negates BRPLY, while the processor exits from the main program and enters a
service program for the DRV11-B as indicated by the vector address.
Interrupt requests from the DRV11-B occur for the following conditions:
1.

When the WCR increments to zero - this is a normal interrupt at the end of a designated
number of transfers.

When the user’s I/O device asserts ATTN - thisis a special condition mterrupt whnch may
be defined by the user to override the WCR

When a nonexistent memory locationis addressed by the DRV11-B - this special condition
interrupt is pmduced when no BRPLY is recelvcd fmm the LSI-11 memory.

Interrupts are explamedin greater detailin Chapter 4 of this manual.
3.2.5 LSI-11 Memory to User’s Device Transfers (DATIO or DATI)
DMA transfers from the LSI-11 memory to the user’s 1/O device occur in a manner smmllar to that

described for user’s I/O device to memory transfers. Figure 3-3 illustrates the data flow for aDMA
DATIO or DATI cycle. Under program control, the DRV11-B WCR (Fxgure 3-1) is loaded with a
count equal to the number of transfers, while the BARis loaded with the starting a,ddress from whwh
the first word will come; the CSRis set for transfers.
|

With the CSR set, READY goes low and the user’s | /0 devnce cmndltmm the C0, Cl lines. (refer to

Table 3-1) for a DATI or a DATIO and conditions the WC INC ENB, BA INC ENB, ATTN,
SINGLE CYCLE (high for normal DMA transfers), and asserts CYCLE REQUEST. BUSY from the
DRVI11-B goes low and the user’s control bits are latched into the DRV11-B. The DRV11-B then
asserts BDMR which makes a bus request. When the request is arbitrated as described in Paragraph
3.2.4, the DRV11-B becomes bus master.
When the DRVI11-B becomes bus master,

a DATI or DATIO bus cycle is performed (a DATI is
described). The DRV11-B places the address of the memory location from which the first word is
taken on the BDAL lines and asserts BSYNC. Memory decodes and latches the address. The DRV11B then removes the address from the BDAL lines and asserts BDIN. Input datais now placed on the
BDAL lines by the memory and the memory asserts BRPLY. The input data is accepted by the
DRVI11-B and BDINis negated. Memory negates BRPLY and the DRV11-B negates BSACK and
- BSYNC to terminate the bus cycle and release the bus. The OUTPUT DATA BITS for the user’s I /O
device are stored in the DRV11-B output data buffer register. These bits can be read by the user’s
device at the low-to-high transition of BUSY.

3-7

DATI OR DATIO —»

—=

(

USERS
DEVICE

M orvn-B

LSI-11BUS

]
|

, \L- DATA FLOW <—

MEMORY

<::

/]l

1
LSI-

PROCESSOR

1t-4188

Figure 3-3

DMA DATIO/DATI Data Flow Diagram

At the end of the first transfer, the DRV11-B WCR and BAR are incremented, BUSY goes high, while

READY remains low. The user’s device can initiate another DATI or DATIO cycle by again setting
CYCLE REQUEST. DMA transfers to the user’s device can continue until the WCR increments to
zero and causes an interrupt request to be generated (Paragraph 3.2.4.1).
3.3

TIMING

~ Input and output timing for the DRV11-B is shown in Figures 3-4 through 3-7. The timing diagrams
show user signal timing for single cycle and burst mode operations which can be either program- or
user-initiated.

3-8

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3-12

CHAPTER 4

PROGRAMMING

4.1

GENERAL

This chapter presents basic programming information for the DRV11-B. The types of programming
instructions, the use of the registers, program interrupts, and special program considerations are

presented.

4.2 PROGRAMMING INSTRUCTIONS
|
All programming instructions used for the LSI-11 processor may be used for programming the

DRVI11-B.

DRVI11-B REGISTERS

Five registers are used by the DRV11-B:
Word Count (WCR)
Bus Address (BAR)
Control/Status (CSR)

Input and Output Data Buffers (DBRs).

The input and output data buffer registers share the same bus address while WCR, BAR and CSR
have unique addresses.

4.3.1

WCR

4.3.2

BAR

43.3

CSR

Load the 16-bit WCR with the 2’s complement (negative number) of DMA data transfers. At the end
of each DMA cycle, the WCR is incremented by one. When the last transfer is made, the WCR is
incremented to zero and an interrupt is requested. The WCR is not byte-addressable.

Load the 15-bit BAR with the address that specifies the memory location into which the first word is
written, or from which the first word is read. Following the transfer of each word, the BAR is
incremented by two, to point to the next higher sequential memory word location. If the BAR overflows, it will increment the extended address bits and “‘wrap-around’ to location zero. Address bit
A00, used for byte transfers, is driven by the user’s device. The BAR is not byte-addressable.

- The 16-bit CSR is monitored for interface status and loaded with control bits. The CSR is byteaddressable. Figure 4-1 shows the CSR bit assignments. The function of each bit is described in Table
4-1.

4.3.4

DBRs

The DRBs hold the 16-bit data words for transfer to memory from the user’s I/O device (input DBR),
or from the memory to the user’s I/O device (output DBR). Both DBRs share the same bus address
and are word- and byte-addressable.

4.4 PROGRAM INTERRUPTS
DRV11-B interrupts are enabled by setting bit 06 (IE) of the CSR when the GO bit (bit 00)is 1ssued
(Figure 4-1 and Table 4-1). Interrupts can occur for the following reasons:

Word count overflow (normal interrupt)

4.4.1

CSR ERROR bit (bit 15) set
(special condition)

Word Count Overflow

An interrupt request is generated when the DRV11-B WCR increments to zero and produces WC
OFLO (word count overflow). WC OFLO sets READY in the CSR at the end of the DMA cycle.
4.4.2

CSR ERROR Bit (Bit 15)
The CSR ERROR b1t can set for two possible reasons:

,l.. * when bit 14 (NEX) of the CSRis set, or
2.

when CSR bit 13 (ATTN)is set.

"CSR bit 14 is set when a nonexistent (NEX) memory Iocatmn is addressed and a reply from the
addressed location is not received within 15 us.

Bit 14 will set if a DATO bus cycle does not occur 30 us after performing a DATIO bus cycle.

ATTN bit 13 sets the CSR ERROR bit when the user’s I/O device drives ATTN high. ATTN is a userdefined function which can be utilized to generate an interrupt request.

4.5

FUNCTION AND STATUS BITS

There are three function bits (FNCT 1, 2, 3) and three status bits (STAT A, B, C) which the user can
employ (at his option) to control and mdlcate the status of the DMA transfers and/or the user interface. The function bits (CSR bits 01, 02, and 03) can be used to transfer control data to the user’s
interface via the OUTPUT DATA BIT lines of the DRV11-B. The status bits (CSR bits 09, 10, and 11)
can be used to indicate that status informationis on the DRV11-B INPUT DATA BIT lines.

|rewo|

ERROR

R | R/W|
ATTN

NEX

|rew!|l

STAT A
MAINT

STAT C

STAT B

=+00

| rew |l rRw!rRw!|rRw!|

Rew!|

READY
CYCLE

XAD 17
1E

FNCT 3
XAD 16

FNCT 2

FNCT 1
GO

LEGEND:
R = Read only
R/W =

Read / Write

R/WQO =

Read
/ Write to O

W =

Write only. Always reads as a O.
1~ 4186

Figure 4-1

CSR Format

4-2

Table 4-1
Bit

thction

CSR Bit Functions.

Write-only bit; always,ireads as a zero. T
-

Causes READY to be sent to the user’s devibe, indicating that a

Allows DMAoperation.

command
has been issued.

01, 02, 03

FNCT 1,2, 3: Read/write bits.

04, 05

Cleared by INIT.

XADI6, 17: Read/write bits. Two bits used for extended addressing. Bits

- 04 and 05 increment with the address count when the BAR “wraps-around”

“to zero.
06

Three 0utpi.it bitsfl avaiiéble i"or user-defined functions.

[E:

Read/write bit.

Enables interrupts to occur when READY is set.

Cleared by INIT.

READY:
Read-only bit. Indicates that the DRV11-B is able to accept a
new command. Set by INIT, WCOFLO, ERROR; cleared by GO (bit 00).

CYCLE:
Read/write bit. CYCLE is used to prime a DMA bus cycle; set by
CYCLE REQUEST, cleared during DMA cycle, INIT.

09, 10, 11

STAT A, B, C.
Read-only bits. Three device status input bits that indicate
the state of the DSTAT A, B, and C user signals.

MAINT:
Read/write bit. Maintenance bit for use with the MAINDEC
diagnostic.

ATTN:

NEX:

Read-only bit. Indicates the state of the ATTN user signal; sets
READY, ERROR.
Read/write to zero bit.

Nonexistent memory; indicates that as bus master, the DRV11-B
did not receive BRPLY or that a DATIO cycle was not completed.

Sets ERROR.

Cleared by INIT or by writing it to a zero.

4-3

- Table 4-1 CSR Bit Funrctinns (Cont)
Bit

" ERROR: Read-only bit.

Function

: 1.
Y

Indicates one of the fallgwing special conditions:
a. NEX (bit 14)
b.

ATTN (bit 13)

Sets READY (bit 7) and causes an interrupt if IE (bit 6) is set.

‘3. Cleared by removing the special condition as follows:
a.

'b.

NEX is cleared by writing bit 14 to a zero.

ATTN s cleared by the user device.

DRV11-B GENERAL PURPOSE DMA

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