Digital PDFs

EK-DPV11-UG-001

August 1980

98 pages

Original

31MB

view download

OCR Version

35MB

view download

Document:	DPV11 Serial Synchronous Interface User Guide
Order Number:	EK-DPV11-UG
Revision:	001
Pages:	98
Original Filename:

OCR Text

EK-DPV11-UG-001

DPV 11 serial synchronou
interface user guide

digital equipment corporation ® merrimack, new hampshire

1st Edition, August 1980

The matenal in this manual is for informational purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsi-

bility for any errors which may appear in this manual.

Printed in U.S A.

This document was set on DIGITAL’s DECset~8000 computerized
typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:

DIGITAL

DECsystem-10

MASSBUS

DEC

DECSYSTEM-20

OMNIBUS

PDP

DIBOL

OS/8

DECUS

EduSystem

RSTS

UNIBUS

VAX

RSX

DECLAB

VMS

IAS
MINC-11

CONTENTS
Page

INTRODUCTION
SCOPE.....eeeeeeccreeeen, ieeiineseraiisaianereis SioMisadeessaniisiranteesaresnsteaneenesanssrnnrenases 1-1
DPV11 GENERAL DESCRIPTION .......... eveerssdsnninriesirasastiorainserererararensassrasssarsons 1-1
DPVI1I OPERATION L.ttt
e e st e e e eana s 1-2
DPVI11 FEATURES ..o CedhibanesidaReis i endaben
e bbb e snitesesaesnns ciinieensaerses .1-2
GENERAL SPECIFICATIONS .............................................................................. 1-2
Environmental Specifications ..............ccccceevvvrieennneee.Guaditresknestvbasanesasasinivnbisseses .1-2
Electrical SpecifiCations...........ccoveiiiiiiiiiciiieeeee e 1-3
Performance Parameters.........cccccevveeeeeeeeeen. cererrereeeaaarans raeerretarantaartaaraaaateaarares 1-3
DPV11 CONFIGURATIONS.............. Criesieveiieessesratons Cinbesinanseesessuiaesesanrraressrsasnaane 1-3
EIA STANDARDS OVERVIEW ........ Vi Semenebindestashrndedesine esidumehansaireanserrennnnneereseaes 1-3

CHAPTER 2

INSTALLATION

2.1

2.5

INTRODUCGTION ...ttt
e et s eae et ee e e e e e e e e|
UNPACKING AND INSPECTION............. R SN O S 2-1
PRE-INSTALLATION REQUIREMENTS .......ccoo oo rrrreereeeeeas 2-1
INSTALLATION.........eeeeeeecee, CErsiariearaisasiunnisninsedvanisaatoasisensrsiuvatansisensesane 2-6
Verification of Hardware Operatxon ............................................ cerrreraraaaraaaaaaas 2-7
Connection to External Equipment/Link Testing .............ccccooveiiviviieiiinniinnnnns 2-8
TEST CONNECTORS ..................ennraraes eeeeteeterenratreeeeraa
s annaeteeeeereaarranrtteneeesaens 2-8

CHAPTER 3

helbebeb
st et et et et et atst
LpabbhLLLbbLbb-—
RO
(U - VS I B R

bl
DD

CHAPTER 1

INTRODUCTION ...ttt
e e s e e e aaaeee se 3-1
DPV11 REGISTERS AND DEVICE ADDRESSES...........ccccveee.. rrrrereeeee e 3-1
REGISTER BIT ASSIGNMENTS ..o eereeaeereeaenr—raeeeeeernes 3-2
Receive Control and Status Reglster (RXCSR) eeeerterertenaeeretarrteatatettttartta—e————. 3-2
Receive Data and Status Register (RDSR) .....ovooveoioeiieeeeeeeeeeeeeeeeeeeeee, 3-2
Parameter Control Sync/Address Register (PCSAR)......cccooevvveiiiiiieiineenn. 3-2
Parameter Control and Character Length Register (PCSCR) ........................ 3-2
Transmit Data and Status Register (TDSR) ..... eeeeeereenrtaneteeeaaaearn—ranaaaaeeaaeaaanns 3-2
DATA TRANSFERS ..., eeteeereea——a—aeeeeeaaeaannrrans 3-19

2.2

2.3

2.4
2.4.1
242

Receive Data .......cooovvivviiiniicccccccercceeeeeee
eerbeeueaeerean——————————a———————————_. 3-19
Transmit Data ............cccoeveennnnn. cvareurshrenteaaryrente eheetreeerneetrht————aat——n———a———.n——a——_. 3-20
INTERRUPT VECTORS ...ttt s 3-21

CONTENTS (Cont)
Page

APPENDIX A

DIAGNOSTIC SUPERVISOR SUMMARY

INTRODUCGTION L
e e A-1
VERSIONS OF THE DIAGNOSTIC SUPERVISOR ... A-1

A.2

LOADING AND RUNNING A SUPERVISOR DIAGNOSTIC ................... A-1
SUPERVISOR COMM
AN DS
e e A-3
Command SWItChES ... A-4
Control/Escape Characters Supported ... A-4
THE SETUP UT L LI Y e A-5

APPENDIX B

USYNRT DESCRIPTION

APPENDIX C

IC DESCRIPTIONS

A3
A4

A4l
A4.2

GENE R AL e e C-1
DCOO3 INTERRUPT CHIP ..o e C-1
DC004 PROTOCOL CHIP......................et
eaara s et eree bt
e eeeraaneres C-3
DCO00S BUS TRANSCEIVER CHIP
.. oo
i C-3
261.S32 QUAD DIFFERENTIAL LINE RECEIVER ... C-6
8640 UNIBUS RECEIVER ...l SR UOTPPROI C-6
BB N AN
DD
C-6
9636
A DUAL LINE DRIVER .
e C-6
9638 DUAL DIFFERENTIAL LINE DRIVER ... C-6
APPENDIX D

PROGRAMMING EXAMPLES

GLOSSARY

ILLUSTRATIONS
Figure No.

Title

Page

1-1

DPVI1I System ................................. P

2-1
2-2

DPVI11 Jumper LOCAtions ........ooiiiiiiiiiii
e 2-4
H3259 Turn-Around Test Connector.............. et 2-8

2-3
2-4
3-1
3-2
3-3

RS-423-A with H3259 Test CONNeCctor ..........ooviiiiiiieeeeee e, 2-10
H3260 On-Board Test ConneCtOr.......ooooiiiiii e 2-11

3-4

3-5

3-6
A-1

SO I-1

DPV11 Register Configurations and Bit Assignments........................
. 3-3
Receive Control and Status Register (RXCSR) Format ..., 3-4
Receive Data and Status Register (RDSR) Format.....................
... 3-8
Parameter Control Sync/Address Register (PCSAR) Format ................................ 3-11
Parameter Control and Character Length Register
(PCSCR) FOrmat .
e
e 3-13
Transmit Data and Status Register (TDSR) Format ... 3-17
Typical XXDP+ /Diagnostic Supervisor Memory Layout................................. A-2

ILLUSTRATIONS (Cont)
Figure No.
Terminal Connection Identification Diagram
(2T12517-0-0 VATIAtI0N) ooooiiiiiiieeeee
e
et B-2
5025 Internal Register Bit Map (2112517-0-0 Vanatmn) ........................................ B-3
DCO003 Logic Symbol ..oSO C-1
DC004 Simplified Logic Diagram .............cccccoiiiiiiiiimiiiiie
S C-4
DCO00S Simplified Logic Diagram ............coooviiiiiiiiiieei
e C-7
26L.S32 Terminal Connection Diagram and Terminal
Indentification...............cooocoviiiiiiii ettt
e e
ta e e eaennaas C-9
8640 Equivalent Logic Diagram ................et
aaae e C-10
8881 Pin Identification.......................cocis oot e
aaaee ]C-10
9636A Logic Diagram and Terminal [entification.. ... eooooo C-11
9638 Logic Diagram and Terminal Identification..............e e C-12

OOO0O

0000
S W N - N

B-1

TABLES

S S VS

&:-)u

Do == U

PN
-

wwwr:smmw

Title Page

Page

Configuration SREEt ... ..o 2-1
Vector Address SeleCtion............ooiiiiiiiiiiiiiiie
e 2-5
Device Address Selection ...............ccooooiviiiiiiiiiiiiieeeeee e
————————— 2-6
Voltage ReqQUIr€mMents .............cooiiiiiiiiiiiniiii
e, et 2-7
H3259 Test CONNECIONS. .....c.oooiiiiiiiiieiee
e 2-9
DPVIT REGISTEIS. ....ottt
e
e e 3-1
Receive Control and Status Register (RXCSR) Bit
ASSIZIITIENES L.iiiiiiiiiiiiiiiii
ittt e ete e e e e e aae e e e e areeeesertaeeeseeasaeeeeeeeeaneeeeeeeeaeeesenaaseens 3-5
Receive Data and Status Register (RDSR) Bit Assignments....... s 3-8
Parameter Control Sync/ Addrcss Register (PCSAR)
Bit ASSIZNMENTS ...ooiii
e
iiiiiiii
et
e e ietie
eee e e e e e
, e 3-11
Parameter Control and Character Length Register
(PCSCR) Bit ASSIZNMENLS ........ooiiiiiiiiiiieiiiee
ee 3-14
Transmit Data and Status Register (TDSR) Bit Assignments .............c....oooooooo.... 3-17
DCO003 Pin/Signal DeSCriptions.............cc.oiiviiiieeiieieiieeeceeee e, veeenanealC-2
DCO004 Pin/Signal DesCriptions..............oooiiiiuiiiiiiciiiiieeeeeeee e elC-5
DCO0O0S5 Pin/Signal DeSCriPtioNnS. .......c.ooiiiiiiiiiieiciieceeeeeee eC-8

Gys,

eiy

PREFACE

This manual is intended to provide an introduction to the DPV11 Interface and present the information required by the user for configuration, installation and operation.
It contains the following categories of information.

General description including features, specifications, and configurations

Installation

Programming

The manual also contains four appendixes which include diagnostic information, integrated circuit de-

scriptions, and programming examples.

The DPV11 Field Maintenance Print Set (MP00919) contains useful additional information.

Vil

1.1 SCOPE
This chapter contains introductory information about the DPV11. It includes a general description,
and a brief overview of the DPV11 operation, features, general specifications, and configurations.
1.2 DPV11 GENERAL DESCRIPTION
The DPV11 is a serial synchronous line interface for connecting an LSI-11 bus to a serial synchronous
modem that is compatible with EIA RS-232-C interface staridards and EIA RS-423-A and RS-422-A
electrical standards. EIA RS-422-A compatibility is provided for use in local communications only
(timing and data leads only). The DPV11 is intended for character-oriented protocols such as BISYNC,
byte count-oriemted protocols such as DDCMP, or bit-oriented data communication protocols such as
SDLC. The DPV11 does not provide automatic error generating and checking for BISYNC.
The DPV11 consists of one double-height module and may be connected to an EIA RS-232-C modem
by a BC26L-25 (RS-232-C) cable.

ARV

The DPVII is a bus request device only and must rely on the system software for service. Interrupt
control logic generates requests for the transfer of data between the DPV11 and the LSI-11 memory by
means of the LSI-11 bus. (Figure 1-1 shows the DPV11 system.)

'
l

l
1

l TELEPHONE

MODEM

CPU

MEM

MK- 1320

Figure 1-1

DPV11 System

1.3 DPV11 OPERATION
The DPV11 is a double-buffered program interrupt interface that provides parallel-to-serial conversion
of data to be transmitted and serial-to-parallel conversion of received data. The DPV11 can operate at
speeds up to 56K b/s.* It has five 16-bit registers which can be accessed in word or byte mode. These
registers are assigned a block of four contiguous LSI-11 bus word addresses that start on a boundary

with the low-order three bits being zeros. This block of addresses is jumper-selectable and may be
located anywhere between 160000g and 177776g. Two of these registers share the same address. One is
accessed during a read from the address, the other during a write to the address. For a detailed description of each of the five registers, refer to Chapter 3. These registers are used for status and control
information as well as data buffers for both the transmitter and receiver portions of the DPV11.

1.4 DPVI11 FEATURES
Features of the DPV11 include:

Full-duplex or half-duplex operation

Double-buffered transmitter and receiver
EIA RS-232-C compatibility
All EIA RS-449 Category I modem control

Partial Category II modem control to include incoming call, test mode, remote loopback,
and local loopback

Program interrupt on transitions of modem control signals
Operating speeds up to 56K b/s (may be limited by software or CPU memory)
Software-selectable diagnostic loopback
Operation with bit-, byte count-, or character-oriented protocols

Internal cyclic redundancy check (CRC) character generation and checking (not usable
with BISYNC)

Internal bit-stuff and detection with bit-oriented protocols.
®

Programmable sync character, sync insertion, and sync stripping with byte count-oriented
protocols.

Recognition of secondary station address with bit-oriented protocols.

1.5 GENERAL SPECIFICATIONS
This paragraph contains environmental, electrical, and performance specifications for the DPVI11.
1.5.1
Environmental Specifications
The DPVI11 is designed to operate in a Class C environment as specified by DEC Standard 102 (extended).

Operating Temperature

5° C (41° F) to 60° C (140° F)

Relative Humidity

10% to 90% with a max. wet bulb temperature of 28° C (82°
F) and a min. dew point of 2° C (36° F)

* The actual speed realized may be significantly less because of limitations imposed by the software and/or CPU memory
refresh.

1-2

1.5.2 Electrical Speclficmi@us
The DPV11 requires thé fallowmg voltages from the LSI-11 bus for proper operation.
+12 V at 0.30 A max. (0.15 A typical)

+5Vatl2A max. (0.92 A typical)

The interface includes a chargc pump to generate a negatwc voltage required to power the RS-423-A
drivers.

The DPV11 presents 1 ac load and 1 dc load to the LSI-11 bus.
1.5.3 Performance Parameters
Performance parameters for the DPV11 are listed as follows.

Operating Mode

Full or half-duplex

Data Format

Synchronous BISYNC‘, DDCMP, and SDLC

Character Size

Program-selectable (5-8 bits with character-flfiented

protocols and 1-8 bits with bit-oriented protocols)

Max. Configuration
Max. Distance

16 DPV11 modules per LSI-11 bus
|

15 m (50 ft) for RS-232-C. 61 m (200 ft) for RS-423-

A/RS-422-A (Distanceis directly dependent on speed,
and 200 ft is a suggested average. See RS-449 spccxfication for details.)
Max. Serial Data Rates

56K b/s (May be less because of software and memory
refresh limitations.)

1.6 DPV11 CONFIGURATIONS
There are two DPV11 configurations, the DA and the DB.

DPV11-DA
Unbundled version consists of:
M8020 module
DPV11 Maintenance Reference Card (EK-DPV11-CG)

DPV11-DB
Bundled version consists of:
M8020 module
H3259 turn-around connector
BC26L-25 cable
DPV11 User Manual (EK-DPV11-UG)
DPV11 Maintenance Reference Card (EK-DPV1 1-CG)
LIB kit (ZJ314-RB)
Field Maintenance Print Set (MP00919)
Turn-around connectors, cables and documentation may be purchased separately.
1.7 EIA STANDARDS OVERVIEW (RS-MW RS-232-C)
The most common interface standard used in recent years has been the RS~232~C However, this standard has serious limitations for use in modern data communication systems. The most critical limitations
are in speed and distance.

1-3

For this reason, RS-449 standard has been developed to replace RS-232-C. It maintains a degree of

compatibility with RS-232-C to accommodate an upward transition to RS-449.

The most significant difference between RS-232-C and RS-449 is in the electrical characteristics of
signals used between the data communication equipment (DCE) and the data terminal equipment
(DTE). The RS-232-C standard uses only unbalanced circuits, while the RS-449 uses both balanced
and unbalanced electrical circuits. The specifications for the types of electrical circuits supported by
RS-449 are contained in EIA standards RS-422-A for balanced circuits and RS-423-A for unbalanced
circuits. These new standards permit much greater transmission speed and will allow greater distance
between DTE and DCE. The maximum transmission speeds supported by RS-422-A and RS-423-A
circuits vary with cable length; the normal speed limits are 20K b/s for RS-423-A and 2M b/s for RS422-A, both at 61 m (200 feet).

Another major difference between RS-232-C and RS-449 is that additional leads are needed to support
the balanced interface circuits and some new circuit functions. Two new connectors have been specified
to accommodate these new leads. One connector is a 37-pin Cinch used in applications requiring secondary channel functions. Some of the new circuits added in RS-449 support local and remote loopback
testing, and stand-by channel selection.
|
,

INSTALLATION

2.1
INTRODUCTION
CE
This chapter provides all the information necessary for a successful installation and subsequent check-

out of the DPV11. Included are instructions for unpacking and inspection, pre-installation, installation

and verification of operation.

2.2

UNPACKING
AND INSPECTION

The DPV11 is packaged in accordance with commercial packing practices. Remove all packing mate-

rial and verify that the following are present.

M8020 module

‘
H3259 turn-around connector
BC26L-25 cable
@
DPV11 User Manual (EK-DPV11-UG)
LIB kit (ZJ314-RB)
”
Field Maintenance Print Set (MP00919)

Inspect all parts carefully for cracks, loose components or other obvious damage. Report damages or
shortages to the shipper immediately, and notify the DIGITAL representative.
2.3
PRE-INSTALLATION REQUIREMENTS
|
Table 2-1 (Configuration Sheet) provides a convenient, quick reference for configuring jumpers.

Table 2-1

Configuration Sheet

(W1-W2) Driver Attenuation Jumper

Driver

Normal*
Configuration

Alternate*
Option

Terminal

W1 to W2

Not connected

Timing

Description

Bypasses

attenuation

resistor.

Jumper must be removed for cer-

tain modems to operate properly.

(W3-W11) Interface Selectifln Jumpers
Input

Signals

SQ/TM
(PCSCR-5)

DM (DSR)
(RXCSR-9)

Normal*

Configuration

WS to W6
|

Not connected

- Alternate*

Option

Description

;

Signal quality
o

W7 to W6

Test mode

W10 to W9

Data mode return for RS-422-A
|

*Normal configuration is typically RS-423-A compatible. Alternate option is typi«c:ally R,S~A22~A compatible.

2-1

Table 2-1

Configuration Sheet (Cont)

(W3-W11) Interface Selection Jumpers (Cont)
Output

Normal*

Alternate*

Signals

Configuration

Option

SF/RL
|
(RXCSR-0)

W3 to W4

Select frequency

Local

Description

W5 to W3

Remote loopback

W8 to W9

Not connected

Local loopback

Not connected

W8 toWl1

Local loopback (alternate pin)

Loopback

(W12-W17) Receiver Termination Jumpers
Normal*

Alternate*

Receiver

Configuration

Option

Description

Receive Data

Not connected

W12toWI3

Connects terminating resistor for
RS-422-A compatibility

Send Timing

Not connected

Wlid4to W15

Receive
Timing

|
Not connected

W16 to W17

(W18-W23) Clock Jumpers

Function

NULL MODEM
- CLK

Normal*

Alternate*

Configuration

Option

W20to W18

Description

Sets NULL CLK MODEM CLK

to 2 kHz.

W21 to W18

Sets NULL MODEM CLK to
50 kHz.

Clock Enable

W19 to W21

Always installed except for factory

W22 to W23

testing.

(W24-W28) Data Set Change Jumpers

Modem Signal

Normal*

Name

Configuration

Data Mode (DSR)|

~ Alternate*

Option

Description

Clear to Send

W26 to W24
ot
3
W26 to W25

Not connected
k
Not connected

Connects the DSCNG flip-flop to
the respective modem status signal
for transition detection.

Incoming Call

W26 to W27

Not connected

Note: W26 is input to DSCNG flip-

W26 to W28

Not connected

Receiver Ready
(Carrier Detect)

*Normal configuration is typically RS-423-A compatible. Altzcrgme option is typically RS-422-A compatible.

Table 2-1

Configuration Sheet (Cont)

Device Address Jumpers

GND
W29

Al2
W31

All
W30

Al0 A9
W36
W33

A8
W32

A7
W39

A6
W38

AS
W37

A4
W34

A3
W35

The address to which the DPV11 is to respond is
daisy-chain jumpered to W29 (GND).
Vector Address Jumpers

W43

W42

W4l

W40

W44

W45

Source

W46

NOTE
Vector address to be asserted is daisy-chain jumpered to W46.
NOTE
Table 2-1 shows the recommended normal and alter-

nate jumpering schemes. Any deviation from these
will cause diagnostics to fail and require restrapping
for full testing and verification. It is recommended
that customer configurations that vary from this
scheme :mt be cammctually suppm'ted

Prior to installing the DPV11, perform the follawmg tasks

Verify that the following modem mterfacc wire-wrap jumpers are installed (anure 2-1).
W26 to W25 to W24 to W28 to W27
W22 to W23 and W19 to W21
W18 to W20
WS to Wé
W3 to W4
W8 to W9
W1 to W2

Thisis the normal / RS-423-A shipped configuration. Some of these Jumpers may be changed

- when the moduleis connected to external equipment for a specific application. The NULL

MODEM CLKis set to 2 kHz as shipped.

Based on the LSI-11 bus floating vector scheme or user requirements, determine the vector
address for the specific DPV11 module being installed and configure W40 through W46
accordingly (Table 2-2).

Based on the LSI-11 bus floating address scheme or user requirements, determine the device
address range for the DPV11 module and configure W30 through W39 accordingly (Table
2-3). Devices may be physically addressed starting at 160000 and continuing through
177776; however, there may be some software restrictions. The normal addressing convenin Table 2-3.
tion is as shown

000‘00‘0

W12

TERMINAL/ 012

TIMING

00O

3456

910 11

O13

O14

\ RESISTOR

TERMINATING

O1e |

\INTEHFACE
SELECTION

JUMPERS

FORRS422A

gcdL

W18

Ov
23

CLOCK JUMPERS

25 27
24

26%

DATA SET CHANGE JUMPERS

*W26 IS INPUT TO DSCNG FLIP FLOP

SHIPPED

ADDRESS

VECTOR

160010

300
r\__,/\____/\

W29 30 3234 36 38

O0O000
O

OO0

31 33353739

40 42 44

00O

JUMPERS ARE

O 0O
41

DAISY CHAINED

43 45

|
B

MK-1338

Figure 2-1

DPV11 Jumper Locations

rrrrrrr

Table 2-2

Vector Address Selection

DPV11 (M8020) VECTOR ADDRESSING
MSB__

JUMPERS
JUMPER-

[

__ NUMBER _

]

VECTOR
,
ADDRESS

300

"X INDICATES A CONNECTION
TO W46.

330

340

320

310

;

X X X X

X X X X X X XX

pag

350
360

370

W46 IS THE SOURCE JUMPER FOR THE VECTOR ADDRESS

JUMPERS ARE DAISY CHAINED,

,
MK 1341

2-5

‘Table 2-3

Device Address Selection

DPV11-XX (M8020) DEVICE ADDRESSING
MSB

‘

12 l ool sl7|e]s|als

JUMPERS -

- ' ol

LSB

i
N

DEVICE

W30|W36| W33 §W32| W39|W3BJW37| W34 |W35)

sppRess

760010

760030

760050

760040
X

X X X X

760020

760060

| x

760070

760100
760200
-

760300

760400

x |

X
x

760500

760600

| x

760700
"

761000
-

x |

762000
-

x| x

763000
-

764000

"X INDICATES A CONNECTION TO W29. W29 IS TIED TO

GROUND. JUMPERS ARE DAISY CHAINED.
MK-1339

2.4 INSTALLATION
The DPV11 can be installed in any LSI-11 bus-compatible backplane such as H9270. LSI-11 configuring rules must be followed. Proceed with the installation as follows. For additional information
refer to PDP-11/03 User Manual EK-LSI11-TM or LSI-11 Installation Guide EK-LSI11-IG.

Configure the address and vector jumpers at this time if they have not been previously done
(Paragraph 2.3).
WARNING
Turn all power OFF.
2-6

—

2.
o

Connect the female Berg connector on the BC26L-25 cable to J1 on the

’and plug the modulc into a dual LSI-11 bus slot of the
backplane.

M8020 module
|

CAUTION

Insert and remove modules slowly and carefully to
‘avoid snmagging module components on the card
guides.

Connect the H32597 turn-around connector to the EIA connection on the BC26L-25 cable.

The jumper W1 on the H3259 turn-around connector must be removed.

Perform resistance checks from backplane pin AA2 (+5 V) to ground and from AD2

(+12

V) to ground to ensure that there are no shorts on the M8020 module or backplane.
5.

Turn system power on.

6.
-

Check the voltages
to ensure that they are within the specified tolerances (Table 2-4). If

voltages are not within specified tolerances, replace the associated regulator (H780 P.S.)

Voltage

+5V

+12V

Table 2-4

Voltage Requirements

Max.

Min

+525 |

+475 | AA2

12.75

+11.25 | AD2

2.4.1 Verification of Hardware Operation
|
|
The M8020 module is now ready to be tested by running the CVDPV* diagnostic.
Additional information on the DPV11 diagnostics is contained in Appendix A. Proceed
as follows.
|

The

tic.

NOTE
represents the revision level of the diagnos-

Load and run CVDPV*. Three consecutive error-free passas of this test is the minimum re-

quirement for a successful run. If this cannot be achieved, check the following.
Board seating
Jumper connections
- Cable connection

Test connector
If a successful run is still unachievable, corrective maintenance is required.

Load and run the DEC/X11 System Exerciser configured to test the number of DPV11s in

the system.

Each DEC/X11 CXDPV module will test up to eight consecutively addressed DPV
1 1s.

CXDPV uses a software switch register. Refer to the DE C/X11 Cross-Reference (ASF055C-MC) for switch register utilization.

T If a BC26L-25 cable and H3259 turn-around connector are not available, an on-board test connector
(H3260) can be ordered separately. See Paragraph 2.5.
|
s
B

2-7

TheDEC/X11 System Exerciser is designed to achieve maximum contention with all devices that make up the system configuration. Itis within this environment that the CXDPV
module runs. Its intent is to isolate DPV11s which adversely affect the system operation.

For information on canfiguring and running the DEC/X11 System Exerciser, refer to

DEC/X11 User Manual (AS-FO503B-MC) and DEC-XI1 Cross Reference (AS-FO55CMCQ).

2.4.2

Connection to External Equipment/Link Testing

The DPV11 is now ready for connection to external equipment.

If the DPV11 is being connected to a synchronous modem, remove the H3259 connector and install the

EIA connection of the BC26L-25 cable into the connector on the modem.

Configure jumpers W1-W28 in accordance with operating requirements (Table 2-1).

Load and run DCLT (CVCLH*)
if a full link is available. This will check the final configuration and

isolate failures to the CPU, the communications link, or the modem.

[f the connection to external eqmpment uses RS-422-A, the user must provide the cable and test support.

2.5

TEST CONNECTORS

The only test connector provided with the DPV11 is the H3259 turn-around connector (Figure 2-2).
Table 2-5 and Figure 2-3 show the relationship between pin numbers, signal names and register bits
when the H3259 is connected by means of the BC26L-26 cable to the M8020 module.
2

NULL MODEM

15 @—=

@—

TCP

RCP

—_—

SEC XMIT

14 @
19
@
23 @

ECT FREQ ;
SELECT

12
@

16 @
21 @

SEC REC
REMOTE LOOP

(SIGNAL QUALITY)

TEST MODE

XMIT DATA

2 &
3 @

REC DATA

RTS

4 @

8 @

06 ©

@6 2

©®

@ O

0 ® © 60 © & @ O

CTS
RR

H3259

18 @

LOCAL

LOOP

. DATAMODE '

6 @

20 ®

DTR

27 @—e

CO
GC CAL L
INCOMING

W1 IS CUT FOR TESTING DPV11

Figure 2-2

H3259 Turn-Around Test Connector 2-8

1329

Table 2-§

H3259 Test Connections

From

Pin No.

Signal Name

H3259

H3259 |

Signal Name

SEND DATA

RECEIVE DATA

REQUEST TO SEND

BB&T

5&8

(RTS) (RXCSR-2)

CLEAR TO SEND

(CTSYRXCSR-13),

RECEIVER READY
(RR) (RXCSR-12)
LOCAL LOOPBACK

(LL) (RXCSR-3)

(SF/RL) (RXCSR-0)

- DATA MODE
(DM) (RXCSR-9)

SELECT FREQ/REMOTE |23/21
LOOPBACK

NULL MODEM

RR/MM

MM/‘C

21/25 | SIGNAL QUALITY/
TEST MODE

(SQ/TM) (PCSCR-5)

N&R

15&17

DATA TERMINAL

READY (DTR)
(RXCSR-1)

| RCV CLOCK
TX CLOCK

| X

INCOMING CALL

(IC) (RXCSR-14)

The following accessories are available for interfacing and may be ordered separately.
®

BC26L-X cable. Available in lengths of .3, 1.8, 2.4, 3.0, 3.6, 6.1, and 7.6 meters (1,
6, 8, 10,
12, 20 and 25 feet). When ordering, the dash number indicates the desired cable length in
feet; e.g., BC26L-25 or BC26L-1.
|

@®

H3259 cable turn-around connector

HB856 Berg connector. Includes H856 Berg connector and 40 pins. Crimping tools are available from:
'
|

Berg Electronics, Inc.
New Cumberland, PA

17070

H3260 on-board test connector (includes RS-422-A testing)

The H3260 on-board test connector (Figure 2-4) may be used to test the M8020 circuitry in its entirety.

RS-422-A circuitry is not tested with the H3259 cable turn-around connector. The H3260 on-board test
connector is shipped configured for testing RS-422-A. It may be configured to test RS-422-A or RS423-A as follows.
|

RS-422-A

RS-423-A

W1-W2 out
W3-W6 installed

W1-W2 installed
W3-W6 out

The connector is installed into J1 with the jumper side up.

Since the H3260 on-board test connector does not test the cable, it is recommended that the DPV11 be
tested with a turn-around connector at the modem end of the cable if possible.

2-9

|
SEND
DA TA

E40

—171

—7

H3259

IVE
RECEIVE
D DATA

£
\{

TX CLOCK
TCP

SQ/TM

PCSCR 5

SF/RL

RXCSR-0

DATA SET
READY

LOCAL LOOP BACK

13_"" .

N
3 d £ag

Wil
S

W3,

)

E25

\ 7.

W9
- "=

W10

W?/vw1

-A

DATA TERMINAL
READY

RSCSR-13 (CTS)

250

k;n

! THIS JUMPER

) PP
.

RECEIVER READY

K
K

"‘“/

5
.

\_m

)
15

2 d 45

12/

)

REQUEST TO SEND

RXCSR 12 (RR)

)
.
Y

CLEAR TO SEND

2(RTS)
RSCSR-2

W ~

3 _ cas

’7)
T
[

RXCSR-14 {INCOMING ']
£
CALL)
\ 9
RSCSR-1(DTR)

" NN
N

JJ
)

/ 6

d e39

3,/

£40

COTY

\
-3
(LL
RXCSR-3
(LL)

84
2

E38

RCP

CLK

RCV CLOCK

LOCAL

\ 2

NEGATIVE INPUT TO DIFFERENTIAL

RECEIVERS OMITTED FOR CLARITY

Q\I\

h\[\
ME 1336

Figure 2-3 RS-423-A with H3259 Test Cmmcmr
2-10

MUST BE
REMOVED WHEN
TESTING A DPV11

TEST MODE

C o

SIGN QUAL

MM o

RR o

SF/RL

SEND DATA

RX DATA

SEND DATA

O
AA

TERM TIMING

SEND TIMING

N o

(RS422)

RX TIMING

TERM TIMING

W o

W3
,

& o

)

(RS422)

CLEAR TO SEND

T o

REQ TO SEND

RX RDY

BBO

INCOMING CALL

TERM RDY

‘

RSa22

W6 o}

DATA MODE

Z 0O

DATA MODE RET

W4 o-

W3 ¢

O
DD

5013970A

]

(LOCAL LOOP)
SEND TIM RET

TT ©

RX TIM RET

SS o

TERM TIM RET

EE O

whH

(RS422)

SEND DATA RET
RX DATA RET

,fw,,_‘

KKO
So

H3260 TEST CONNECTOR
NOTE: 1. W1 & W2 IN
W3-W6 OUT
2. W1 & w2 OUT

W3-W6 IN

} RS-423-A TESTING
} RS-422-A TESTING
MY 1464

Figure 2-4

H3260 On-Board Test Connector

2-11

*
EGISTER DESCRIPTIONS
AND PROGRAMMING INFORMATION
3.1

INTRODUCTION

’

This chapter describes the bit assngnmants and programming considerations fm the DPV11. Smmc typical start and receive sequences for both bit- and character-oriented protocols are included.

The five rchsters usedin the DPVII are showninTable 3-1. Nme thattwoof the registers:(P S AR

and RDSR) have the sameaddress. This does not constitutea conflict, however, becausethe PCSAR
1s a write-only register and the RDSRis a read-only register. These five registers occupy eight contiguous byte addresses which begin on a boundary where the low-wder three bits are zero, and can be
located anywhere bctween:0“6‘%1 and 1777763 R
R

;

Receive Control and Status

Mnemonic |

Addrm 1

RXCSR

16xxx0

o
Parameter Control Sync/Address

Parameter Control and Character

Word or byte* addressable.

16xxx2

PCSAR**

Read-only.
Wm'd or bytc addmssablc

-R

Length

PCSCR¥

Transmit Data and Status R

TDSR“ ‘ : 2 16m6 i [ :Wm'd or byte addressable.
5

16xxx4

Word or byte addressable.
Read/write.

Read/write.

* Reading either byte of these registers, cl@am data andcertain statusbitsin mhm bytes. See Paragraphs 3.3.1
and 3.3.2.
|

** Rc:gzswrs contained mthm the USYNRT

11tis notpossible to do bit set or bit clear instructions on this mg;stm
f The high byte of this register is internal to the USYNRT.
|

TheDPV11 uses a unwarsabxynchmmus receiver/ transmltter (USYNRT) ahnp whxch accounts for a
large portionofthe DPV11’s functionality. TheUSYNRT provides complete mmahmtwn, dasermhza~
tion and buffering of data to and from the modem.

3-1

Most of the DPV11 registers are internal to the USYNRT. Only the receiver control and status register (RXCSR) and the low byte of the parameter control and character length register (PCSCR) are

external.

NOTE

When using the special space sequence function, all
registers internal to the USYNRT must be written
in byte mode.

3.3

Bit assignments for the five DPV 11 registers are shown in Figure 3-1. Paragraphs 3.3.1-3.3.5 provide a
description of each register using a bit assignment illustration and an accompanying table with a detailed description of each bit.

3.3.1

Receive Control and Status Register (RXCSR) (Address 16xxx0)

Figure 3-2 shows the format for the receive control and status register (RXCSR). Table 3-2 is a deof the register. This register is external to the USYNRT.
tailed description
NOTE

The RXCSR can be read in either word or byte
mode. However, reading either byte resets certain
status bits in both bytes.

3.3.2

Receive Data and Status Register (RDSR) (Address 16xxx2)

Figure 3-3 show the format for the receive data and status register (RDSR). It is a read-only register
and shares its address with the parameter control sync/address register (PCSAR) which is write-only.
|
‘Table 3-3 is a detailed description of the RDSR.
NOTE

The RDSR can be read in either word or byte mode.
However, reading either byte resets data and certain
status bits in both bytes of this register as well as
bits 7 and 10 of the RXCSR.

3.3.3 Parameter Control Sync/Address Register (PCSAR) (Address 16xxx2)
The parameter control sync/address register (PCSAR) is a write-only register which can be written in
either byte or word mode. Figure 3-4 shows the format and Table 3-4 is a detailed description of the
PCSAR. This register shares its address with the RDSR.

NOTE

Bit set (BIS) and bit clear (BIC) instructions cannot be executed on the PCSCR, since they execute

‘using a read-modify-write sequence.

|
3.3.4 Parameter Control and Character Length Register (PCSCR) (Address 16xxx4)
The parameter control and character length register (PCSCR) can be read from or written into in
either word or byte mode. The low byte of this register is external to the USYNRT and the high byte is
of the PCSCR.
internal. Figure 3-5 shows the format and Table 3-5 is a detailed description
3.3.5

Transmit Data and Status Register (TDSR) (Address 16xxx6)

The format for the transmit data and status register (TDSR) is shown in Figure 3-6 and Table 3-6 is a
or byte
detailed description. The TDSR is a read/write register which can be accessed in either word

mode with no restrictions. All bits can be read from or written into and are reset by Device Reset or
I
ok odE
B
s
|
|
Bus INIT except where noted.
3-2

RXCSR

16 XXX0
READ/WRITE
15

R , R

R I R

R/W l RW | R/W l RW | RW | rw | RoW I

DATA

CLR

SET

RCV

DATA

RCV
DATA

LOCAL

SEND

MOVE

DATA

CHANGE

ACTIVE

SET

READY

(LL)

INTR

TERM

LOOP

RDY

INCOMING

RCVR

CALL

DATA

RCVR

READY

SYNC

STATUS
READY

RCV

INTR

FLAG

REQ

ENA

SF/RL

10
SEND

DETECT

RDSR
|
MK-1504

16 XXX2
READ ONLY
15

13
i

12
I

ASSEMBLED
BIT

COUNT

'RECEIVE

ERROR

" RCVR

CHECK

)

s
DATA

BUFFER

END

OVER

RUN

MESG

RCV

START

ABORT

OF
MESG

PCSAR

16XXX2

"er50s

WRITE ONLY
16

[

09
¥

SELECTION
|

ERROR DETECTION
i

ALL

STRIP

PARTIES

IDLE

SYNC OR

MODE

LOOP

SELECT

ADDR

Q7
i

'secouomv STATION + RECEIVER SYNC
L

MODE

PROTOCOL

SECD

SELECT

ADRS |

MODE

SEL

Figure 3-1

DPVI11 Register Configurations and Bit Assignments

ME- 1508

(Sheet 1 of 2)

PCSCR

READ/WRITE
15
'

1rw

089
i

R/W R/WIRW!IRWIlRW

EXTD

R/W R/W|

TRANSMITTER

| rW ]| R/W| R'W | RW

RECEIVER

CHARACTER LENGTH ADDR

RSVD

CHARACTER LENGTH

SQ/TM

MAINT

XMTR

MODE

FIELD

ACTIVE

SELECT
EXTD
CONT

XMIT

XMTR

INTR

ENAB

FIELD

XMTR
BUFFER

DEVICE

RESET

EMPTY
MK-1507

16XXX6

READ/WRITE

XMIT

13
o

0
]

RESERVED

DATA
LATE

R'W | R'W | R'W | R'W | R/'W
)

R/W

AHEAD

MESG
ABORT

R/W
|

R/W
i

R/W
]

00
R/W

)

TRANSMIT DATA BUFFER

END

XMIT

R/W

—
START

OF
MESG
MK-1508

Figure 3-1

DPVI11 Register Configurations and Bit Assignments (Sheet 2 of 2)

RDAT | RX | DS

rRy** | 1TeENn | ITEN | ENA

15
DS* |
NG

cts |

L | rRts | TR | SF/RL

11
RX
| acr

|RSTA""
lay

| sfFo

* THIS BIT IS RESET BY READING EITHER BYTE OF THIS REGISTER.
** THESE BITS ARE RESET BY READING EITHER BYTE OF RSDR.
MK 1327

Figure 3-2

Receive Control and Status Register (RXCSR) Format

3-4

Table 3-2 Receive Control and Status Register (RXCSR) | Bit Assignments
Bit

Name

Description

Data Set Change
(DSCNG)

This bit is set when a transition occurs on any of the following
modem control lines:

Clear to Send

Data Mode

Receiver Ready
Incoming Call

Transition detectors for each of these four lines can be disabled
by removing the associated jumper.

- Data Set Changa,;is cleared by reading either byte of the
RXCSR or by Device Reset or Bus INIT.

Data Set Change causesa receive interrupt if DSITEN (bit $)
and RXITEN (bit 6) are both set.

Incoming Call

This bit reflects the state of the modem Incoming Call line. Any
transition of this bit causes Data Set Change bit (bit 15) to be
asserted unless the Incoming Call line is disabled by removing
its jumper. This bit is read-only and cannot be cleared by soft-

(IC)

ware.

~ This blt refl@cts the _s,t!alte bf the Clear to Send line of the

Clear
to Send

(CTS)

modem. Any transition of this line causes Data Set Change (bit
15) to be set unless the jumper enabling the Clear to Send signal
is removed.

Clear to Send is a program read-only bit and cannot be cleared
by software.

Receiver Ready

(RR)

This bit is a direct reflection of modem Receiver Ready lead. It
indicates that the modem is receiving a carrier signal. For exter-

nal maintenance loopback, this signal must be high. If the line is
open, RR is pulled high by the circuitry.

Any transition
of this bitrr.causes Data Set Change (bit 15) to be

asserted unless the jumper enabling the Receiver Ready signal
is removed.

.Rcceivar ,,,Ready isa read-only bit and cannot be cleared by software.

Receiver Active
(RXACT)

Thls bit is set when the USYNRT presents the first character of
a message to the DPV11. It remains set until the receive data

path of the USYNRT becomes idle.

Receiver Active is cleared by any of the following conditions: a
terminating control character is received in bit-oriented protocol
mode; an off transition of Receiver Enable (RXENA) occurs: or

Device Reset or Bus INIT is issued.

3-5

Table 3-2 Receive Control and Status Register (RXCSR) Bit Assignments (Cont)
Bit

Name

Descnptmn

Receiver Active is a read-only bit which reflects the state of the

USYNRT output pin 5.
10

Receiver Status
Ready (RSTARY)

This bit indicates the availability of status information in the
upper byte of the receive data and status register (RDSR). It is
set when any of the following bits of the RDSR are set: Receiver
End of Message (REOM); Receiver Overrun (RCV OVRUN);
Receiver Abort or Go Ahead (RABORT); Error Check
(ERRCHK) if VRC is selected.

Receiver Status is cleared by any of the following conditions:
reading either byte of the RDSR; clearing Receiver Enable (bit

4 of RXCSR); Device Reset, or Bus Init.

When set, Receiver Status Ready causes a receive interrupt if
Receive Interrupt Enable (bit 6) is also set.

Receiver Status Ready is a read-only bit which reflects the state

of USYNRT pin 7.

Data Mode (DM)
(Data Set Ready)

This bit reflects the state of the Data Mode signal from the
modem.

When this bit is set it indicates that the modem is powered on
and not in test, talk or dial mode.

Any transition of this bit causes the Data Set Change bit (bit
15) to be asserted unless the Data Mode jumper has been removed.

Data Mode is a read-only bit and cannot be cleared by software.
Sync or Flag
Detect (SFD)

This bit is set for one clock time when a flag character is detected with bit-oriented protocols, or a sync character is detected with character-oriented protocols.

SFD is a read-only bit which reflects the state of USYNRT pin

Receive Data
Ready (RDATRY)

This bit indicates that the USYNRT has assembled a data character and is ready to present it to the processor.

If this bit becomes set while Receiver Interrupt Enable (bit 6) 1s

set, a receive interrupt request will result.

Receive Data Readyis reset when either byte of RDSR is read,
Receiver Enable (bit 4)is cleared or Device Reset or Bus INIT
|

is issued.

RDATRY is a read-only bit which rcflectes the state of US-

YNRT pin 6.

3-6

Table 3-2
Bit

Receive Control and Status Register (RXCSR) Bit Assignments (Cont)

Name

Description

Receiver Interrupt
Enable (RXITEN)

When set, this bit allows interrupt requests to be made to the
receiver vector whenever RDATRY (bit 7) becomes set.

The conditions which cause the interrupt request are the assertion of Receive Data Ready (bit 7), Receive Status Ready (bit
10), or Data Set Change (bit 15) if DSITEN (bit 5) is also set.
RXITEN is a program read/write bit and is cleared by Device
Reset or Bus INIT.
Data Set Interrupt
Enable (DSITEN)

This bit, when set along with RXITEN, allows interrupt .
requests to be made to the receiver vector whenever Data Set
Change (bit 15) becomes set.

DSITEN is a program read/write bit and is cleared by Device
Reset or Bus INIT.
Receiver Enable
(RXENA)

This bit controls the operation of the receive section of the USYNRT.
When this bit is set, the receive section of the USYNRT is enabled. When it is reset the receive section is disabled.
In addition to disabling the receive section of the USYNRT, resetting bit 4 reinitializes all but two of the USYNRT receive
registers. The two registers not reinitialized are the character
length selection buffer and the parameter control register.

Local Loopback

(LL)

Asserting this bit causes the modem connected to the DPV11
establish a data loopback test condition.

Clearing this bit restores normal modem operation.

Local Loopback is program read/write and is cleared by Device
Reset or Bus request to Send is program read/write and is
cleared by Device Reset or Bus INIT.
Request to Send
(RTS)

Setting this bit asserts the Request to Send signal at the modem
interface.
|
|
Request to Send is program read/write and is cleared by Device
Reset or Bus INIT.

Terminal Ready (TR)
(Data Terminal
Ready)

When set, this bit asserts the Terminal Ready signal to the
modem interface.

For auto dial and manual call origination, it maintains the established call. For auto answer, it allows handshaking in response to
a Ring signal.

3-7

Table 3-2
Bit

Receive Control and Status Register (RXCSR) Bit Assignments (Cont)

Name

Description

Select Frequency
or Remote
Loopback (SF/RL)

This bit can be wire-wrap jumpered to function as either select
frequency or remote loopback. When jumpered as select frequency (W3 to W4), setting this bit selects the modem’s higher
frequency band for transmission to the line and the lower frequency band for reception from the line. The clear condition se-

lects the lower frequency for transmission and the higher frequency for reception.

When jumpered for remote loopback (W5 to W3), this bit, when

asserted, causes the modem connected to the DPV11 to signal
when a remote loopback test condition has been established in
the remote modem.
SF/RL is program read/write and is cleared by Device Reset or
Bus INIT.

RECEIVE DATA BUFFER

13
i

12
i

ERR

ASSEMBLED

]REC

CHK

BIT COUNT

OVRUN

]

107

ABORT| REOM | RSOM

Figure 3-3

Table 3-3

Bit
15

1326

Receive Data and Status Register (RDSR) Format

Receive Data and Status Register (RDSR) Bit Assignments

Name

Description

Error Check

This bit when set, indicates a possible error. It is used in conjunction with the error detection selection bits of the parameter
control sync/address register (bits 8-10) to indicate either an
error or an all zeros state of the CRC register.

(ERR CHK)

With bit-oriented protocols, ERR CHK indicates that a CRC
error has occurred. It is set when the Receive End of Message
bit (RDSR bit 9) is set.
With character-oriented protocols ERR CHK is asserted with

each data character if all zeros are in the CRC register. The
processor must then determine if this indicates an error-free

3-8

Table 3-3
Bit

Receive Data and Status Register (RDSR) Bit Assignments (Cont)

Name

Description
message or not. If VRC parity is selected, this bit is set for every
character which has a parity error.

ERR CHK is cleared by reading the RDSR, clearing RXENA
(RXCSR bit 4), Device Reset or Bus INIT.

12
— O OO
— O

Used only with bit-oriented protocols, these bits represent the
number of valid bits in the last character of a message. They are
all zeros unless the message ends on an unstated boundary. The
bits are encoded to represent valid bits as shown below.

——
O - — O O

Assembled Bit
Count (ABC)

—_———
O 00O

14-12

Number of Valid Bits
All bits are valid
One valid bit
Two valid bits
Three valid bits
Four valid bits
Five valid bits

Six valid bits
Seven valid bits

These bits are presented simultaneously with the last bits of
data and are cleared by reading the RDSR or by resetting
RXENA (bit 4 of RXCSR).
11

Receiver Overrun

(RCV OVRUN)

This bit is used to indicate that an overrun situation has occurred. Overrun exists when the data buffer (bits 0-7 of RDSR)
has not been serviced within one character time.
As a general rule, the overrun is indicated when the last bit of
the current character has been received into the shift register of
the USYNRT and the data buffer is not yet available for a new
character.

Two factors exist which modify this general rule and apply only
to bit-oriented protocols.
The first factor is the number of bits inserted into the data
stream for transparency. For each bit inserted during the formatting of the current character, the controller’s maximum response time is increased by one clock cycle.
The second factor is the result of termination of the current
message. When this occurs, the data of the terminated message
which is within the USYNRT is not overrunable. If an attempt
is made to displace this data by the reception of a subsequent
message, the data of the subsequent message is lost until the

data of the prior message has been released.

3-9

Table 3-3
Bit
10

Receive Data and Status Register (RDSR) Bit Assignments (Cont)

Name

Description

Receiver Abort or

This bit 1s used only with bit-oriented protocols and indicates
that either an abort character or a go-ahead character has been
received. This 1s determined by the Loop Mode bit (PCSAR bit
13). If the Loop Mode bit is clear, RABORT indicates reception
of an abort character. If the Loop Mode bit is set, RABORT
indicates a go-ahead character has been received.

Go Ahead (RABORT)

The setting of RABORT causes Receiver Status Ready (bit 10
of RXCSR) to be set.

RABORT is reset when the RDSR 1s read or when Receiver Enable (bit 4 of RXCSR) is reset.
The abort character 1s defined to be seven or more contiguous
one bits appearing in the data stream. Reception of this bit pattern when Loop Mode is clear causes the receive section of the
USYNRT to stop receiving and set RSTARY (bit 10 of
RXCSR). The abort character indicates abnormal termination
of the current message.

The go-ahead character i1s defined as a zero bit followed by seven consecutive one bits. This character is recognized as a normal

terminating control character when the Loop Mode bit is set. If
Loop Mode is cleared this character is interpreted as an abort
character.

Receiver End of
Message (REOM)

This bit is used only with bit-oriented protocols and 1s asserted if
Receiver Active (bit 11 of RXCSR) 15 set and a message 1s terminated either normally or abnormally. When REOM becomes
set, it sets RSTARY (bit 10 of RXCSR).

REOM is cleared when RDSR is read or when Receive Enable
(bit 4 of RXCSR) is reset.
Receiver Start of
Message (RSOM)

Used only with bit-oriented protocols. This bit 1s presented to
the processor along with the first data character of a message
and is synchronized to the last received flag character. Setting
of RSOM does not set RSTARY (RXCSR bit 10).
RSOM is cleared by Device Reset, Bus INIT, resetting Receiver Enable (RXCSR bit 4), or the next transfer into the Receive Data buffer (low byte of RDSR).

Receive Data

The low byte of the RDSR is the Receive Data buffer. The se-

Buffer

rial data input to the USYNRT is assembled and transferred to
the low byte of the RDSR for presentation to the processor.
When the RDSR receives data, Receive Data Ready (bit 7 of

RXCSR) becomes set to indicate that the RDSR has data to be
picked up. If this data is not read within one character time, a
data overrun occurs.
The characters in the Receive Data buffer are right-justified
with bit O being the least significant bit.

3-10

6
i

4
|

SYNC CHARACTER OR
SECONDARY STATION ADDRESS

APA

gng ::,Zf

SEC

]

MDE

ADR | IDLE

ERR DET SEL
MK . 1330

Figure 3-4

Table 3-4

Parameter Control Sync/Address Register (PCSAR) Format

Parameter Control Sync/Address Register (PCSAR) Bit Assignments

Bit

Name

Description

All Parties
Addressed (APA)

This bit is set when automatic recognition of the All Parties Addressed character is desired. The All Parties Addressed character is eight bits of ones with necessary bit stuffing so as not to be

confused with the abort character.

Recognition of this character is done in the same way as the secondary station address (see bit 12 of this register) except that
the broadcast address is essentially hardwired within the receive
data path. The logic inspects the address character of each
frame for the broadcast address. When the broadcast address is
recognized, the USYNRT makes it available and sets Receiver
- Start of Message (bit 8 of RDSR).

If the broadcast address is not recognized, one of two possible
actions occurs.
1.
If the Secondary Address Select mode bit (bit 12) is set, a
test of the secondary station address is made.

2. If bit 12 is not set or the secondary station address is not
recognized, the receive section of the USYNRT renews
its
search for synchronizing control characters.
|
14

Protocol Select
(PROT SEL)

Strip Sync or
Loop Mode
(STRIP SYNC)

This bit is used to select between character- and byte count-ori
ented or bit-oriented protocols. It is set for character- and byte
count-oriented protocols and reset for bit-oriented protocols.

This bit serves the following two functions.
1. Strip Sync (character-oriented protocols) — In character-oriented protocols, all sync characters after the initial synchronization are deleted from the message and not included in
the
CRC computation if this bit is set. If it is cleared, all sync char-

acters rem:in in the message and are included in the CRC

- putation.

com-

Table 3-4
Bit

Parameter Control Sync/Address Register (PCSAR) Bit Assignments (Cont)

Name

Description

2. Loop Mode (bit-oriented protocols) — With bit-oriented protocols, this bit is used to control the method of termination. If it
is set, either a flag or go-ahead character can cause a normal
termination of a message. If it is cleared, only a flag character
can cause a normal termination.

Secondary
Address Mode
(SEC ADR MDE)

This bit is used with bit-oriented protocols when automatic recognition of the secondary station address is desired. If 1t 1s set,
the station address of the incoming message is compared with
the address stored in the low byte of this register. Only messages
prefixed with the correct secondary address are presented to the
processor. If the addresses do not compare, the receive section
of the USYNRT goes back to searching for flag or go-ahead
characters.

When SEC ADR MDE is cleared, the receive section of the
USYNRT recognizes all incoming messages.
11

Idle Mode Select
(IDLE)

This bit is used with both bit- and character-oriented protocols.

With bit-oriented protocols, IDLE is used to select the type of
control character issued when either Transmit Abort (bit 10 of
TDSR) is set or a data underrun error occurs. If IDLE 1s set,
flag characters are issued. If IDLE is clear, abort characters are
issued.

With character-oriented protocols, IDLE is used to control the
method in which initial sync characters are transmitted and the
action of the transmit section of the USYNRT when an underrun error occurs. IDLE is cleared to cause sync characters from
the low byte of PCSAR to be transmitted. When IDLE is set,
the transmit data output is held asserted during an underrun error and at the end of a message.

10-8

Error Detection
Selection
(ERR DEL SEL)

These bits are used to determine the type of error detection used
on received and transmitted messages. In bit-oriented protocols,
the selection is independent of character length. In character-

and byte count-oriented protocols, CRC error detection is usable only with 8-bit character lengths. The maximum character
length for VRC is seven. The bits are encoded as follows.

3-12

CRC Polynomial

x16+x12+x5+1 (CRC CCITT) (Both CRC

data registers in the transmit and receive sections are set to all ones prior to the computation.)

x16+x124+x5+1 (CRC CCITT) (Both CRC

data registers set to all zeros.)

Table 3-4

Bit

Parameter Control Sync/Address Register (PCSAR) Bit Assignments (Cont)

Name

Description
0

Not used

x16+x15+x2+1 (CRC 16) (Both CRC registers set to all zeros.)
|

0
|

Odd VRC Parity (A parity bit is attached to
each transmitted character.) Should be used

only in character-oriented protocols.
1

Even VRC parity (Resembles odd VRC except that an even number of bits are gener-

ated.)

7-0

Sync Character

Not used.

All error detection is inhibited.

The low byte of PCSAR is used as either the sync character for

or Secondary
Address

character-oriented protocols or as the secondary station address
for bit-oriented protocols.

The bits are right-justified with the least significant bit being bit
0.

EXTERNAL TO THE USYNRT
’

‘5

6
X
RSVD | INT
.|

|sa/TM|TxENnA

3
2
MM | TB
SEL | EMTY

o \

TXACT | RESET
|

INTERNAL TO THE USYNRT

(15
14
TRANSMITTER

A’

10
9
RECEIVER

g )

CHARACTER LENGTH |EXADD|EXCON CHARACTER LENGTH
I

MK 1325

Figure 3-5

Parameter Control and Character Length Register (PCSCR) Format

3-13

Table 3-5

Parameter Control and Character Length Register (PCSCR) Bit Assignments

Bit

Name

Description

15-13

Transmitter

These bits can be read or written and are used to determine the
length of the characters to be transmitted.

Character Length

They are encoded to set up character lengths as follows.
15

Character Length

Eight bits per character

Seven bits per character

Six bits per character

Three bits per character (bit-oriented protocol

Two bits per character (bit-oriented protocol

One bit per character (bit-oriented protocol

Five bits per character (bit-oriented protocol
only)

Four bits per character (bit-oriented protocol

only)

These bits can be changed while the transmitter is active, In
which case the new character length is assumed at the completion of the current character. This field is set to a character
length of eight by Device Reset or Bus INIT. When VRC error
detection is selected, the default character length is eight bits
plus parity.

Extended Address
Field (EXADD)

This bit is used with bit-oriented protocols and affects the address portion of a message in receiver operations. When it is set,
each address byte is tested for a one in the least significant bit
position. If the least significant bit is zero, the next character is
an extension of the address field. If the least significant bit i1s
one, the current character terminates the address field and the
next character is a control character.

EXADD is not used with Secondary Address Mode (bit 12 of

PCSAR).

EXADD is read/write and is reset by Device Reset or Bus
INIT.

Extended Control
Field (EXCON)

This bit is used with bit-oriented protocols and affects the control character of a message in receiver operations. When EX3-14

Table 3-5

Bit

Pammetgr Control and Character Length Register (PCSCR)

Name

Bit Assignments (Cont)

Description
CON is set it extends the control field from one 8-bit byte to
two 8-bit bytes.

EXCON is not used with Secondary Address Mode (bit 12 of
PCSAR)
EXCON is read/write and is reset by Device Reset or Bus
INIT.

10-8

Receiver
Character Length

These bits are used to determine the length of the characters to
be received.
They are encoded to set up character lengths as follows.
10

Character Length

Eight bits per character

Seven bits per character

Six bits per character

Five bits per character

Four bits per character (bit-oriented protocols

only)
0O

Three bits per character (bit-oriented protocols only)

Two bits per character (bit-oriented protocols
only)

One bit per character (bit-oriented protocols
only)

Reserved

Not used by the DPV11

Transmit Interrupt
Enable (TXINTEN)

When set, this bit allows a transmitter interrupt request to be
made to the transmitter vector when Transmit Buffer Empty
(TBEMTY) is asserted. Transmit Interrupt Enable (TXINTEN) is read/write and is cleared by Device Reset or Bus
INIT.
|

Signal Quality or
Test Mode (SQ/TM)

This bit can be wire-wrap jumpered to function as either Signal
Quality or Test Mode.

When jumpered for signal quality (W5 to W6), this bit reflects
the state of the signal quality line from the modem. When as- serted, it indicates that there is a low probability of errors
in the
received data. When clear it indicates that there is a high probability of errors in the received data.
3-15

Table 3-5
Bit

Parameter Control and Character Length Register (PCSCR) Bit Assignments (Cont)

Name

Description

When jumpered for the test mode (W6 to W7), this bit indicates
that the modem has been placed in a test condition when asserted. The modem test condition could be established by asserting Local Loopback (bit 3 of RXCSR), Remote Loopback (bit O
of RXCSR) or other means external to the DPV11.
When SQ/TM is clear, it indicates that the modem is not in test
mode and is available for normal operation.
SQ/TM is program read-only and cannot be cleared by software.

Transmitter
Enable (TXENA)

This bit must be set to initiate the transmission of data or control information. When this bit is cleared, the transmitter will
revert back to the mark state once all indicated sequences have
been completed. TXENA should be cleared after the last data
character has been loaded into the transmit data and status register (TDSR). Transmit End of Message (bit 9 of TDSR) should
be asserted when TXENA is reset (if it is to be asserted at all)
and remain asserted until the transmitter enters the idle mode.
TXENA is connected directly to USYNRT pin 37. It is a
read/write bit and is reset by Device Reset or Bus INIT.

Maintenance Mode
Sclect (MM SEL)

When this bit is asserted, it causes the USYNRT’s serial output
to be internally connected to the USYNRT’s serial input. The
serial send data output line from the interface is asserted and
the receive data serial input is disabled. Send timing and receive
timing to the USYNRT are disabled and replaced with a clock
signal generated on the interface. The clock rate is either
49.152K b/s or 1.9661K b/s depending on the position of a
jumper on the interface board.
Maintenance mode allows diagnostics to run in loopback without disconnecting the modem cable.

MM SEL is a read/write bit and is cleared by Device Reset or
Bus INIT. When it is cleared, the interface is set for normal operation.

Transmitter Buffer
Empty (TBEMTY)

This bit is asserted when the transmit data and status register
(TDSR) is available for new data or control information. It is
also set after a Device Reset or Bus INIT.
The TDSR should be loaded only in response to TBEMTY
being set. When the TDSR is written into, TBEMTY is cleared.
If TBEMTY becomes set while Transmit Interrupt Enable (bit

6 of PCSCR) is set, a transmit interrupt request results.
TBEMTY reflects the state of USYNRT pin 35.

3-16

Table 3-5

Parameter Control and Character Length Register (PCSC

R) Bit Assignments (Cont)

Bit

Name

Transmitter
Active (TXACT)

Description
This bit indicates the state of the transmit section

of the USYNRT. It becomes set when the first character of data
or control information is transmitted.

TXACT is cleared when the transmitter has nothin
g to send or
when Device Reset or Bus INIT is issued.
TXACT reflects the state of USYNRT pin 34,
0

Device Reset
(RESET)

When a one is written to this bit all components of the
interface
are initialized. It performs the same function as Bus INIT
with

respect to this interface. Modem Status (Data

Mode, Clear to

Send, Receiver Ready, Incoming Call, Signal Quality

or Test

Mode) is not affected. RESET is write-only; it
cannot be read
by software.

]

TRANSMIT

[

|
RESERVED
{

DATA BUFFER

|
TERR

TGA

X
ABORT

|
9

TEOM | TSOM

MK 1331

Figure 3-6

Table 3-6

Bit

Name

Transmitter
Error (TERR)

Transmit Data and Status Register (TDSR) Format

Transmit Data and Status Register (TDSR) Bit Assignm

ents

Description
This is a read-only bit which becomes asserted when the
Transmitter Buffer Empty (TBEMTY) indication has not
been serviced for more than one character time.

When TERR occurs in bit-oriented protocols, the transmi
t section of the USYNRT generates an abort or flag charac
ter based
on the state of the IDLE bit (PCSAR bit 1 1).
If IDLE is set, a
flag character is sent. If it is reset, an abort character
is sent.
When TERR occurs in character-oriented protocols,
the state of
the IDLE bit again determines the result. If IDLE
is set, the

transmit serial output is held in the MARK conditi

cleared, a sync character is transmitted.

3-17

on. If it is

Table 3-6 Transmit Data and Status Register (TDSR) Bit Assignments (Cont)
Bit

Name

Description

TERR is cleared when TSOM (TDSR bit 8) becomes set or by
Device Reset or Bus INIT.

Clearing Transmitter Enable (PCSCR bit 4) does not clear
TERR and TERR is not set with Transmit End of Message.
14-12

Reserved

Not used by the DPV11

Transmit Go
Ahead (TGA)

This bit, when asserted, modifies the bit pattern of the control
character initiated by either Transmit Start of Message
(TSOM) or Transmit End of Message (TEOM). TSOM or
TEOM normally causes a flag character to be sent. If TGA is
set, a go-ahead character is sent in place of the flag character.
TGA is only used with bit-oriented protocols.

Transmit
Abort (TXABORT)

This bit is used only with bit-oriented protocols to abnormally
terminate a message or to transmit filler information used to establish data link timing.

When TXABORT is asserted, the transmitter automatically
transmits either flag or abort characters depending on the state
of the IDLE mode bit. If IDLE is cleared, abort characters are
sent. If IDLE 1s set, flag characters are sent.
Transmit End of
Message (TEOM)

This control bit is used to normally terminate a message in bitoriented protocol. It also terminates a message in character-oriented protocols when CRC error detection is used. As a secondary function, it is used in conjunction with the Transmit Start of
Message (TSOM)
bit to transmit a SPACE SEQUENCE. Refer to the TSOM bit description (bit 8 of this register) for information regarding this sequence.
With bit-oriented protocols, asserting this bit causes the CRC

information to be transmitted, if CRC is enabied, followed by
flag or go-ahead characters depending on the state of the Transmit Go Ahead (TGA) bit. See bit 11 of this register.
With character-oriented protocols, asserting this bit causes
CRC information, if CRC is enabled, to be transmitted followed
by either sync characters or a MARK condition depending on
the state of the IDLE bit. If IDLE is cleared, sync characters
are transmitted.

The character following the CRC information is repeated until
the transmitter is disabled or the TEOM bit is cleared.
A subsequent message may be initiated while the transmit section of the USYNRT
is active. This is accomplished by clearing
the TEOM bit and supplying new message data without setting

3-18

Table 3-6
Bit

- Name

Transmit Data and Status Register (TDSR) Bit Assignments (Cont)
'

Description
the Transmit Start Of Message bit. However, the CRC character for the prior message must have completed transmission.

Transmit Start
of Message
(TSOM)

This bit is used with either bit- or character-oriented protocols.
As long as it remains asserted, flag characters (bit-oriented protocols) or sync characters (character-oriented protocols) are
transmitted.

With bit-oriented protocols, a space sequence (byte mode only)
of 16 zero bits can be transmitted by asserting TSOM and
TEOM simultaneously provided the transmitter is in the idle
state and Transmit Enable is cleared. This should not be done
during the transfer of data, and must only be done in byte mode.

NOTE
When using the special space sequence function, all registers in-

ternal to the USYNRT must be written in byte mode.

Normally at the completion of each sync, flag, go-ahead or
Abort character, the TBEMTY indication is asserted. This allows the software to count the number of transmitted characters. In certain applications, the software may elect to ignore the
service of the Transmitter Buffer Empty (TBEMTY) indication.
Normally during data transfers, this would cause a transmit
data late error. The TSOM bit asserted suppresses this error
and provides the necessary synchronization to automatically
transmit another flag, go-ahead or sync character.

7-0

Transmit Data
Buffer

Data from the processor to be transmitted on the serial output
line is loaded into this byte of the TDSR when Transmitter Buf-

fer Empty (TBEMTY) is asserted. If the transmitter buffer is
not loaded within one character time, an underrun error occurs.
The characters areright-justified, with bit O being the least significant bit.

3.4 DATA TRANSFERS
|
~
Paragraphs 3.4.1 and 3.4.2 discuss receive and transmit data transfers as they relate to the system
software.

3.4.1

Receive Data

Serial data to be presented to the DPV11 from the modem enters the receiver circuit and is presented
to the USYNRT. Recognition by the USYNRT of a control character initiates the transfer. When
a
transfer has been initiated, a character is assembled by the USYNRT and then placed in the low
byte
of the receive data and status register (RDSR) when it is available. If the RDSR is not available,
the
transfer is delayed until the previous character has been serviced. This must take place before the
next
character is fully assembled
or an overrun error exisis. Refer to the description of bit 11 in Table 3-3
for more details on Receiver Overrun.
|

Servicing of the RDSR is the responsibility of the system software in response to the Receive Data
Ready (RDATRY) signal. This signal is asserted when a character has been transferred to the RDSR.
The setting of RDATRY would also cause a receive interrupt request if Receive Interrupt Enable
(RXITEN) is set. The software’s response to RDATRY is to read the contents of the RDSR. At the
completion of this operation, the new information is loaded into the RDSR and RDATRY 1s reasserted. This operation continues until terminated by some control character. The upper byte of the
RDSR contains status and error indications which the software can also read.

The DPV11 will handle data in bit-, byte count- or character-oriented protocols.

With bit-oriented protocol, only flag characters are used to initiate the transfer of a message. Information inserted into the data stream for transparency or control is deleted before it is presented to the
RDSR. This means that only data characters are available to the software. The first two characters of
every message or frame are defined to be 8-bit characters and the USYNRT will handle them as such
regardless of the programmed character length. All subsequent data is formatted in the selected character length. When CRC error detection is selected, the received CRC check characters are not presented to the software, but the error indication will be presented if an error has been detected.

If the secondary address mode is implemented, the first received data character must be the selected
address. If this is not the case, the USYNRT will renew its search for flag or go-ahead characters.
Refer to the description of bit 12 of the PCSAR in Table 3-4.

With byte count- or character-oriented protocols, two consecutive sync characters are required to synchronize the transfer of data. The sync characters used in the message must be the same as the sync
character loaded by the software into the low byte of the parameter control sync/address register
(PCSAR). If leading sync characters subsequent to the initial two syncs are to be deleted from the
data stream, the Strip Sync bit (bit 13) must also be set in the upper byte of the PCSAR. The character length of the data to be received should also be set in bits 8, 9, and 10 of the parameter control and
character length register (PCSCR). Sync characters and data must have the same character length
and only characters of the selected length will be presented to the receive buffer. Sync characters
following the initial two will be presented to the buffer and included in the CRC computation unless
the Strip Sync bit is set. If vertical redundancy check (VRC) parity checking is selected, the parity bit
itself is deleted from the character before it is presented to the buffer.
3.4.2

Transmit Data

System software loads information to be transmitted to the modem into the transmit data and status

Loading of the TDSR occurs in response to the Transmitter Buffer Empty (TBEMTY) signal from the
USYNRT. The character length of information to be transmitted is established by the software when
it loads the transmit character length register (bits 13, 14, and 15 of the PCSCR). The default length
of eight is assigned when the transmit character length register equals zero. The length of characters
presented to the TDSR should not exceed the assigned character length. When the information in the
TDSR is transmitted, the TBEMTY signal is again asserted to request another character. The setting
of TBEMTY also causes a transmit interrupt request if Transmit Interrupt Enable is set.
Byte count- or character-oriented protocols require the transmission of synchronizing information normally referred to as sync characters. The sync characters can be transmitted when Transmit Start of
Message (TDSR bit 8) is set. This happens in one of two ways depending on the state of the IDLE bit
(PCSAR bit 11). When the IDLE bit is cleared, the sync character is taken directly from the common
sync register (PCSAR bits 7-0). The sync register would have been previously loaded by the software.
If the IDLE bit is set, the sync character must be loaded into the TDSR by the software when it is to
be transmitted. If multiple sync characters are to be transmitted, the TDSR must only be loaded with
the first one of the sequence. This character will be transmitted until data information is loaded into
the TDSR. The TBEMTY signal is asserted at the end of each sync character but the TSOM signal
allows it to be ignored without causing a data late error.
3-20

‘

With bit-oriented protocols, the USYNRT automatically generates control characters as initiated by
the software and inserts necessary information into the data stream to maintain transparency.
Typical programming examples in bit- and byte count-oriented protocols appear in Appendix D.

3.5 INTERRUPT VECTORS
"
The DPV11 generates two vector addresses, one for receive data and modem control and the other for
transmit data.

The receive and modem control interrupt has priority over the transmit interrupt and is enabled by
setting bit 6 (RXITEN) of the receiver control and status register (RXCSR).
If bit 6 of the RXCSR is set, a receiver interrupt may occur when any one of the following signals is
asserted.
®
®
®

Receive Data Ready (RDATRY)
Receive Status Ready (RSTARY)
Data Set Change (DAT SET CH)

The signal DAT SET CH only causes an interrupt if bit 5 (DSITEN) of the RXCSR is also set.
It is possible that a data set change interrupt could be pending while a receiver interrupt is being
serviced, or the opposite could be true. In either case, the hardware ensures that both interrupt
requests are recognized.

NOTE
The modem status change circuit interprets any
pulse of two microseconds or greater duration as a
data set change. This ensures that all legitimate
transitions of modem status will be detected. However, on a poor line, noise may be interpreted as a
data set change. Software written for the DPV11
must account for this possibility.
A transmitter interrupt request occurs if Transmit Interrupt Enable (TXINTEN) is set when Transmit
Buffer Empty (TBEMTY) becomes asserted.

3-21

J—

APPENDIX A
DIAGNOSTIC SUPERVISOR SUMMARY
A.1
INTRODUCTION
The PDP-11 diagnostic supervisor is a software package

that performs the following functions.

Provides run-time support for diagnostic programs running on

Provides a consistent operator interface to load and run a
single diagnostic program or a .
script of programs

Provides a common programmer interface for diagnostic develop

Imposes a common structure upon diagnostic programs

Guarantees compatibility with various load systems such as
APT, ACT, SLIDE, XXDP+,
ABS Loader

Performs nondiagnostic functions for programs, such
as console I /O, data conversion, test
sequencing, program options
|

a PDP-11

in stand-alone mode

ment

VERSIONS‘OF THE DIAGNOSTIC SUPERVISOR

File Name

Environment

HSAA **SYS

XXDP
+

HSAB ** SYS

APT

HSAC **SYS

ACT/SLIDE

HSAD ** SYS

Paper Tape (Absolute Loader)

In the above file names, “**” stands for revision and patch

level, such as “A0Q”.

A.3 LOADING AND RUNNING A SUPERVISOR DIAGNO
STIC
A supervisor-compatible* diagnostic program may be loaded
and started in the normal way, using any
of the supported load systems. Using XXDP+ for example
, the program CVDPVA .BIN is loaded and
started by typing .R CVDPVA.
The diagnostic and the supervisor will automatically be loaded

gram started. The program types the following message

as shown in Figure A-1 and the pro-

DRS LOADED
DIAG.RUN-TIME SERVICES
CVDPV-A-0
*To determine if diagnostics are supervisor-compatible, use

the List command under the Setup utility (see Paragraph A.5.)..

A-1

XXDP+/ DIAGNOSTIC SUPERVISOR MEMORY LAYQUT
ON A 16KW (MIN MEMORY) SYSTEM
ADDRESS

100000 (0)
XXDP+

070000
(0)

DIAGNOSTIC
SUPERVISOR
( BKW)

(0)
040000

DIAGNOSTIC
PROGRAM

( 7.5KW)

002000 (0)
(0)
000000
MK-2216

Figure A-1

Typical XXDP+ /Diagnostic Supervisor Memory Layout

DIAGNOSTIC TESTS
UNIT IS DPVI11
DR>

> is the prompt for the diagnostic supervisor routine. At this point a supervisor command must be
DR

entered (the supervisor commands are listed in Paragraph A.4).
Five Steps to Run a Supervisor Diagnostic
1.

Enter Start command.

When the prompt DR> is issued, type:

STA/PASS:1/FLAGS:HOE <CR>
The switches and flags are optional.

Enter number of units to be tested.

The program responds to the Start command with:
# UNITS?

At this point enter the number of devices to be tested.
A-2

Answer hardware parameter questions.
After the number of devices to be tested has been entered, the program responds by asking a
number of hardware questions. The answers to these questions are used to build hardware
parameter tables in memory. A series of questions is posed for each device to be tested. A
“Hardware P-Table” is built for each device.
Answer software parameter questions.

When all the “Hardware P-Tables’ are built, the program responds with:
CHANGE SW?

If other than the default parameters are desired for the software, type Y. If the default parameters are desired, type N.
If you type Y, a series of software questions will be asked and the answers to these will be
entered into the “Software P-Table” in memory. The software questions will be asked only
once, regardless of the number of units to be tested.
Diagnostic execution.

After the software questions have been answered, the diagnostic begins to run.
What happens next is determined by the switch options selected with the Start command, or
errors occurring during execution of the diagnostic.
A.4 SUPERVISOR COMMANDS
The supervisor commands that may be issuedin response to the DR> prompt are as follows.

Start — Starts a diagnostic program.
Restart — When a diagnostic has stopped and control is given back to the supervisor, this
command restarts the program from the beginning.
Continue — Allows a diagnostic to continue running from where it was stopped.

Proceed — Causes the diagnostic to resume with the next test after the one in which it halted.
Exit — Transfers control to the XXDP+ monitor.
Drop — Drops units specified until an Add or Start command is given.

Add — Adds units specified. These units must have been previously dropped.
Print — Prints out statistics if available.
Display — Displays P-Tables.
Flags — Used to change flags.

ZFLAGS - Clears flags.
All of the supervisor commands except Exit, Print, Flags, and ZFLAGS can be used with switch options.

A-3

‘A.4.1

Command Switches

)

Switch options may be used with most supervisor commands. The available switches and their function

are as follows.

./JTESTS: — Used to specify the tests to be run (the default is all tests). An example of the
tests switch used with the Start command to run tests 1 through 5, 19, and 34 through 38
would be:

DR> START/TESTS : 1-5: 19 : 34-38 <CR>

./PASS: — Used to specify the number of passes for the diagnostic to run. For example:
DR> START/PASS : 1

In this example, the diagnostic would complete one pass and give control back to the superVISOT.

./EOP: — Used to specify how many passes of the diagnostic will occur before the end of pass

message is printed (the default is one).

./JUNITS: — Used to specify the units to be run. This switch is valid only if N was entered in

response to the CHANGE HW? question.

.JFLAGS: — Used to check for conditions and modify program execution accordingly. The

conditions checked for are as follows.

:HOE —Halt an error (transfers control back to the supervisor)
:LOE - Loop on error
:IER — Inhibit error reports

:IBE — Inhibit basic error information

:IXE - Inhibit extended error information
:PRI — Print errors on line printer

‘PNT - Print the number of the test being executed prior to execution
-BOE — Ring bell on error

‘UAM - Run in unattended mode, bypass manual intervention tests
:ISR — Inhibit statistical reports

:IOU - Inhibit dropping of units by program

A.4.2

Control/Escape Characters Supported

The keyboard functions supported by the diagnostic supervisor are as follows.

CONTROL C (JC) - Returns control to the supervisor. The DR> prompt would be typed in
response to CONTROL C. This function can be typed at any time.

CONTROL Z (JZ) - Used during hardware or software dialogue to terminate the dialogue
and select default values.

CONTROL O (10) - Disables all printouts. This is valid only during a printout.

CONTROL S (IS) - Used during a printout to temporarily freeze the printout.

CONTROL Q (JQ) — Resumes a printout after a CONTROL S.

A.5

THE SETUP UTILITY
Setup is a utility program that allows the operator to create parameters for a supervisor
diagnostic
prior to execution. This is valid for either XXDP+ or ACT/SLIDE environments.
Setup asks the
hardware and software questions and builds the P-Tables.

The following commands are available under Setup.
List — list supervisor diagnostics
Setup — create P-Tables
Exit — return control to the supervisor
The format for the List command is:

LIST DDN:FILE.EXT
Its function is to type the file name and creation date of the file specified if it is a revision
C or later
supervisor diagnostic. If no file name is given, all revision C or later supervisor diagnostics
are listed.
The default for the device is the system device, and wild cards are accepted.

The format for the Setup command is:
SETUP DDN:FILE.EXT=DDN:FILE.EXT
It reads the input file specified and prompts the operator for information to build P-Tables.
An output
file is created to run in the environment specified. File names for the output and input files
may be the
same. The output and input device may be the same. The default for the device is the
system device
and wild cards are not accepted.

APPENDIX B
USYNRT DESCRIPTION

5025 Universal Synchronous Receiver/Transmitter (USYNRT)
The data paths of the USYNRT provide complete serialization, deserialization and buffering.
Output
signals are provided to the USYNRT controller to indicate the state of the data paths,
the command
fields or recognition of extended address fields. These tasks must be performed
by the USYNRT controller.

The USYNRT is a 40-pin dual-in-line package (DIP). Figure B-1 is a terminal connection
(identification) diagram.

Data port bits DP07:DPO0O0 are dedicated to service four 8-bit wide registers. Bits
DP15:DPO08 service
either control information or status registers. The PCSCR register is reserved.
(See Figure B-2.)
Purchase Specification 2112517-0-0 provides a detailed description of the 5025 USYNRT.

B-1

TSO|

03 |RSI
02

|RXCLK
TBEMTY | 35

39 | TXCLK
TXACT | 34

37 |TXENA
TERR|

RDATRY | 06
RSTARY | 07
RXACT | 05

08 |RXENA

+| 04
SYNC
ADR COMP

DP 15|17
DP 14|16

23 | DPENA

DP 13115
pP12]|14

DP 1113
DP 10|12

19 | ADR SEL
2

DPO9|

20 | ADR SEL
1

DP O8] 10
5p 07 | 24

DO 061

|ADR SEL
O

22 | BYTE GP

11
BIDIRECTIONAL

> I/O TRI STATE
LINES

DP 05126
DP 04|27

18
| WR TO LS!I
—
40 | MAINT

—

SEL

33 | RESET

DP 03]

DP 02]

DP 00|

DP 0130

GND

Vceo

Vbobp

091

32l

01’

J
NOTE: A) PIN 32 +5V POWER SUPPLY
+10% AT 100mA.

B) PIN 01

+12

+12V POWER SUPPLY

+10% AT 100mA.
C) PIN 9 = GROUND
ME-1411,

Figure B-1

Terminal Connection Identification Diagram (2112517-0-0 Variation)

B-2

DP15

ERR

OVER

ASSY BIT ACCOUNT

10
ABORT
OR

REOM

RSOM

R/O

[

R O

DPOO

RX DATA

R/O

R O

RDSR

TERR

TGA

R/O

R W

R/ W

R W

| TABORT|

R O

ADRO

TeoM |

Tsom

R W

R wW

DATA

R W

R'W

R,W

TDSR

MK-1502

Figure B-2

5025 Internal Register Bit Map (2112517-0-0 Variation) (Sheet 1 of 2)

B-3

cep

LOOP

SEC

ADRS

MODE

STRIP | \10DE

SEL

FRR TYPE SEL—

|«

SYNC

R/O

R/0

R/O

]

R/W

R'W

R/W

. TX RX SYNC
RX SEC ADRS

R/W

ADR4

«—— TS DATA LEN SEL—{

EXADD

EXCON

t#——RX DATA LEN SEL ——n

R/W

R
l

RESERVED

PCSCR

ADR 6

ME-1503

Figure B-2

5025 Internal Register Bit Map (2112517-0-0 Variation) (Sheet 2 of 2)

B-4

APPENDIX C
IC DESCRIPTIONS
C.1
GENERAL
|
This appendix contains data on the LSI-11 chips and some of the unusual ICs used by the DPV11. The
other ICs are common, widely-used logic devices. Detailed specifications on these chips are readily
available, and hence are not included here.
C.2 DCO003 INTERRUPT CHIP
*
|
The interrupt chip is an 18-pin DIP device. It provides the circuits to perform an interrupt transaction

in a computer system that uses a “‘pass-the-pulse” type arbitration scheme. The device provides two
interrupt channels labeled A and B, with the A section at a higher priority than the B section. Bus
signals use high-impedance input circuits or high-drive open-collector outputs, which allow the device
to directly attach to the computer system bus. Maximum current required from the V. supply is 140
mA.

Figure C-1 is a simplified logic diagram of the DC003 IC. Table C-1 describes the signals and pins of

the DC003.

DC003

RQSTA
H

ENA DATA H

ENA ST H

ENA CLK
H

BIROL 1028

%7 o BiaKIL

BIAKO L o208

BINIT L

INITO L

ENB CLK H

VEC RQSTB H

ENB DATA H

RQSTB H

ENB ST H

f—nr

03 j BDIN L
1

VECTOR H 01

MK 0164

Figure C-1

DCO003 Logic Symbol

C-1

Table C-1

DCO003 Pin/Signal Descriptions

Signal

Description

VECTOR H

Interrupt Vector Gating Signal — This signal gates the appropriate vector address onto the bus and forms the bus signal
BRPLY L. Not used in the DPV11.

VEC RQSTB H

Vector Request B Signal — When asserted, this signal indicates
RQST B service vector address is required. When negated, it

indicates RQST A service vector address is required. VECTOR
H is the gating signal for the entire vector address; VEC RQST
B H is normally bit 2 of the address.
BDIN L

Bus Data In — THE BDIN signal always precedes a BIAK signal.

INITO L

BINIT L

BIAKO L

17
10

Initialize Out — This is the buffered BINIT L signal used in the

device interface for general initialization.

Bus Initialize — When asserted, this signal brings all drive lines
to their negated state (except INITO L).

Bus Interrupt Acknowledge — This signal is the daisy-chained

signal that is passed by all devices not requesting interrupt service (see BIAKI L). Once passed by a device, it must remain
passed until a new BAIKI L is generated.

BIAKI L

Bus Interrupt Acknowledge — This signal is the processor’s response to BIRQ L true. This signal is daisy-chained such that
the first requesting device blocks the signal propagation while
nonrequesting devices pass the signal on as BIAKO L to the
next device in the chain. The leading edge of BIAKI L causes
BIRQ L to be unasserted by the requesting device.

BIRQL

Asynchronous Bus Interrupt Request — The request is generated
by a true RQST signal along with the associated true Interrupt
Enable signal. The request is removed after the acceptance of
the BDIN L signal and on the leading edge of the BAIKI L signal, or the removal of the associated interrupt enable, or due to
the removal of the associated request signal.

RQSTA H
RQSTB H

Device Interrupt Request Signal — When asserted with the enable A/B flip-flop asserted, this signal causes the assertion of
BIRQ L on the bus. This signal line normally remains asserted
until the request is serviced.

16
11

ENA ST H
ENB ST H

Interrupt Enable — This signal indicates the state of the interrupt enable A /B internal flip-flop which is controlled by the signal line ENA/B DATA H and the ENA/B CLK H clock line.

Table C-1

Description

Signal

ENA DATA H

DC003 Pin/Signal Descriptions (Cont)

ENB DATA H

ENA CLK H

ENB CLK H
o

Interrupt Enable Data — The level on this line, in conjunction

with the ENA /B CLK H signal, determines the state of the internal interrupt enable A flip-flop. The output of this flip-flop is
monitored by the ENA/B ST H signal.

Interrupt Enable Clock — When asserted (on the positive edge),

interrupt enable A/B flip-flop assumes the state of the ENA/B
DATA H signal line.

C.3 DC004 PROTOCOL CHIP
The protocol chip is a 20-pin DIP device that functions as a register selector, providing the signals
necessary to control data flow into and out of up to four word registers (8 bytes). Bus signals can
directly attach to the device because receivers and drivers are provided on the chip. An RC delay
circuit is provided to slow the response of the peripheral interface to data transfer requests. The circuit
is designed such that if tight tolerance is not required, then only an external 1K X20 percent resistor is
necessary. External RCs can be added to vary the delay. Maximum current required from the Vg
supply is 120 mA.

Figure C-2 is a simplified logic diagram of the DC004 IC. Signal and pin definitions for the DC004
are shown in Table C-2.

C.4 DC005 BUS TRANSCEIVER CHIP
.
The 4-bit transceiver is a 20-pin DIP, low-power Schottky device for primary use in peripheral device
interfaces, functioning as a bidirectional buffer between a data bus and peripheral device logic. In
addition to the isolation function, the device also provides a comparison circuit for address selection
and a constant generator, useful for interrupt vector addresses. The bus I/O port provides high-impedance inputs and high-drive (70 mA) open-collector outputs to allow direct connection to a computer’s
data bus. On the peripheral device side, a bidirectional port is also provided, with standard TTL inputs
and 20 mA tri-state drivers. Data on this port is the logical inversion of the data on the bus side.
Three address jumper inputs are used to compare against three bus inputs and to generate the signal
MATCH. The MATCH output is open-collector, which allows the output of several transceivers to be
wire-ANDed to form a composite address match signal. The address jumpers can also be put into a
third logical state that disconnects that jumper from the address match, allowing for “don’t care” address bits. In addition to the three address jumper inputs, a fourth high-impedance input line is used to
enable/disable the MATCH output.
Three vector jumper inputs are used to generate a constant that can be passed to the computer bus.
The three inputs directly drive three of the bus lines, overriding the action of the control lines.

Two control signals are decoded to give three operational states: receive data, transmit data, and disable.

C-3

VECTOR H []1

20{]Vcc

BDAL2 L[]2

19[JENB H

13
|
L.
BDALO L[4

DC004

BDAL1 L[

18_JRXCX H

17 JSEL6
L

BWTBT L[]5

16[_JSEL4 L

BSYNC L[]6

15 _JSEL2
L

BDINL[}7

14 ]JSELOL

BRPLY L[]8

13[JOUTHB
L

BDOUT L []9

12 JOUTLB L

GND[]10

11 JINWD L

L &
a—
s

ENB H| 19}

'ENB
LATCH

BDAL2 L|02

ENB.

BSYNC L--- G

SYNC

]

GND

01
LATCH
g
0

BDALO LE

DECODER

DAL 1

D 1pb—H }WD

DAL 2

17|{SEL6
L

BDAL1 L|o3}

16|SEL4 L

16|SEL 2 L

LATCH

14|SELOL

13JOUTHB L
ot

E:Z]OUTLB L

BWTBT L

18]RXCX H

J
BRPLY L

BDOUT L

BDIN L

O1}VECTOR H

T1}INWD L
MK-01~

Figure C-2

DC004 Simplified Logic Diagram

C-4

Table C-2

DC004 Pin/Signal Descriptions

Signal

Description

VECTOR H

Vector
— This input causes BRPLY L to be generated through
the delay circuit. Independent of BSYNC L and ENB H.

BDAL2 L

BDALI1 L
BDALO L

Bus Data Address Lines — These signals are latched at the assert
edge of BSYNC L. Lines 2 and 1 are decoded for the select outputs; line O is used for byte selection.

BWTBT L

Bus Write/Byte — While the BDOUT L input is asserted, this
signal indicates a byte or word operation: asserted = byte, unasserted = word. Decoded with BDOUT L and latched BDALO
L, BWTBT L is used to form OUTLB L and OUTHB L.

BSYNC L

Bus Synchronize — At the assert edge of this signal, address information is trapped in four latches. While unasserted, this signal disables all outputs except the vector term of BRPLY L.

BDIN L

Bus Data In - This is a strobing signal to effect a data input

transaction. BDIN L generates BRPLY L through the delay cir-

cuit and INWD L.

BRPLY L

Bus Reply — This signal is generated through an RC delay by
VECTOR H, and strobed by BDIN L or DBOUT L, and
BSYNC L and latched ENB H.

BDOUT L

Bus Data Out - This is a stobing signal to effect a data output
transaction. Decoded with BWTBT L and BDALO, it is used to
form OUTLB L and OUTHB L. BDOUT L generates BRPLY
L through the delay circuit.
»

INWD

In Word - Used to gate (read) data from a selected register ont.

the data bus. It is enabled by BSYNC L and strobed by BDIN
L.
12
13

OUTLB L
OUTHB L

Out Low Byte, Out High Byte — Used to load (write) data into
the lower, higher, or both bytes of a selected register. It is enabled by BSYNC L and the decode of BWTBT L and latched
BDALO L. It is strobed by BDOUT L.
~

SELO L

15
16
17

SEL2 L
SEL4 L
SEL6 L

Select Lines — One of these four signals is true as a function of

RXCX

BDAL2 L and BDALI L if ENB H is asserted at the assert
edge of BYSNC L. They indicate that a word register has been

selected for a data transaction. These signals never become asserted except at the assertion of BSYN L (then only if ENB H
is asserted at that time) and, once asserted, are not negated until
BSYNC L is negated.
H

External Resistor Capacitor Node — This node is provided to
vary the delay between the BDIN L, BDOUT L, and VECTOR
H inputs and BRPLY L output. The external resistor should be

tied to V¢ and the capacitor to ground. As an output, it is the
logical inversion of BRPLY L.

C-5

Table C-2

Signal

ENB H

DC004 Pin/Signal Descriptions (Cont)

Description
Enable — This signal is latched at the asserted edge of BSYNC
L and is used to enable the select outputs and the address term
of BRPLY L.

Maximum current required from the V.. supply is 100 mA.

Figure C-3 is a simplified logic diagram of the DC005 IC. Signal and pin definitions for the DCO005

are shown in Table C-3.

C.5 26LS32 QUAD DIFFERENTIAL LINE RECEIVER
|
The 26L.S32 line receiver is a 16-pin DIP device. Terminal connections are shown in Figure C-4.

C.6 8640 UNIBUS RECEIVER

The 8640 is a quad 2-input NOR. Its equivalent circuit is shown in Figure C-5.
C.7 8881 NAND
The 8881 is a quad 2-input NAND. The schematic and pm identifications are shownin Figure C-6.

C.8 9636A DUAL LINE DRIVER
The 9636Ais an 8-pin DIP device specified to satisfy the reqmrew .nts of ETA standards RS-423-A and

RS-232-C. Additionally, it satisfies the requirements cf CCITT v 28, V.10 and the federal standard
FIPS 1030.

The output slew rates are adjustable by a single external resistor connected from pin 1 to ground.
The logic diagram and terminal identification are sheovn in Figure C-7.
C.9 9638 DUAL DIFFERENTIAL LINE DRIVEK
The 9638 is an 8-pin DIP device specified to satisfy the requirements of EIA RS-422-A and CCITT
V.11 specifications.

The logic diagram and terminal identification are shown in Figure C-8.

DCO05 TRANSCEIVER

JATL

JA2 L

L 20Vee
L 19 JA3 L

MATCH H 3 RECH

17 DAT1 H

XMITH 5 -

DAT3H

6 -

DATZH

BUS3 L

BUS2L

GND

— 16 JV3
H
15 JV2 H

- 14 JV1 H

_ 13 MENB L

12 BUSO
L

10-

r
suso L 2>

J‘g iC 2 DATO
§

Bust L [1}—

JAT L [01) £14[>

BUS2 L (09}
(09

.
T

JA3

L [19 mflm

(08

L
MENB

XMIT

‘

H [0+

REC H [04] - l'

i{1:]7 DAT1

J‘k
1>

—{07)
{07) DAT2

BUS3

VVVYYV A VS

JA2

f{j}'g JV
1

«D“L“

Figure C-3

(ic}— GND

MK 0170

DCO00S5 Simplified Logic Diagram

C-7

Jvs3

DAT3

[03) MATCH

20} Vvce

{ig]

[12}

BUST

18 DATO H

4 -

Table C-3

DC005 Pin/Signal Descriptions

Signal

Description

12
11

BUSOL
BUS 1L

Bus Data — This set of four lines constitutes the bus side of the
transceiver. Open-collector output; high-impedance inputs. Low

9
8

BUS 2 L
BUS 3L

= 1.

18
17
7
6

DATO H
DATI H
DAT2 H
DAT3 H

Peripheral Device Data — These four tri-state lines carry the inverted received data from BUS (3:0) when the transceiver is in
the receive mode. When in transmit data mode, the data carried
on these lines is passed inverted to BUS (3:0). When in the dis-

14
15
16

JV1H
JV2H
JV3IH

Vector Jumpers — These inputs, with internal pull-down resistors, directly drive BUS (3:1). A low or open on the jumper pin
causes an open condition on the corresponding BUS pin if

abled mode, these lines go open (high impedance). High = 1.

XMIT H is low. A high causes a one (low) to be transmitted on
the BUS pin. Note that BUS U L 1s not controlled by any jumpr
input.

MENB L

Match Enable - A low on this linc enables the MATCH output.

MATCH H

1
2
19

JA1L
JA2L

Address Jumpers — A strap to ground on these inputs allows a
match to occur with a one (low) on the corresponding BUS line:

JA3L

an open allows a match with a zero (high); a strap to V. disconnects the corresponding address bit from the comparison.

5
4

XMIT H
REC H

Control Inputs — These lines control the operational of the transceiver as follows.

A high forces MATCH low, overriding the match circuit.

Address Match - When BUS (3:1) matches with the state of JA

(3:1) and MENB L is low, this output is open; otherwisc, 1t is
low.

REC XMIT
0
0
1
]

0
|
0
1

DISABLE: BUS and DAT open
XMIT DATA: DAT to BUS
RECEIVE: BUS to DAT
RECEIVE: BUS to DAT

To avoid tri-state overlap conditions, an internal circuit delays
the change of modes between Transmit data mode, and delays
tri-state drivers on the DAT lines from enabling. This action 1s
independent of the disable mode.

C-8

=t
i

NOTE: PIN
1 IS MARKED FOR ORIENTAT!ON NUMBE
RS INDICATED DENOTE TERMINAL NUMBER

TERMINAL IDENTIFICATION

1. INPUT
A
2. INPUT A

3 OUTPUTA
4 ENABLE

5 OUTPUTC
6 INPUTC
7. INPUT
C

16. POSITIVE SUPPLY VOLTAGE

(Vee)

13. OUTPUT B
11. OUTPUT D

8 GROUND
MK 1340

Figure C-4

26LS32 Terminal Connection Diagram and Terminal

Identification

6
2

7
= PIN 8
Vec
= PIN 1
GND

Figure C-5

ME 1321

8640 Equivalent Logic Diagram

VCC

LECHN

S 20 A

[

3A
BN

XWT

—

4
2Y

| |

7
GND
MK-1322

Figure C-6

8881 Pin Identification

(2)

(3)

\_
NOTE

_/
NUMBERS IN () DENOTE TERMINAL NUMBERS.
TERMINAL IDENTIFICATION

‘1 ) WAVESHAPE CONTROL (RISE AND FALL TIME)

(2 ) INPUT A

(3 ) INPUT B
( 4) POWER AND SIGNAL GROUND

{ 5) NEGATIVE SUPPLY VOLTAGE

(6) OUTPUT B
( 7) OUTPUT A

( 8) POSITIVE SUPPLY VOLTAGE (V¢c)
MK. 1323

Figure C-7

9636A Logic Diagram and Terminal Identification

C-11

(8)

(1)
"

1
CH

[

oUTA

CH 1

(2)

NCH

(7}

e
H

(3)

(6)

INCH 2

CH. 2

SUT A

CH 2

(4)

(5)
OuUT
B

NOTE: NUMBERS IN () DENOTE TERMINAL NUMBERS.

TERMINAL IDENTIFICATION

1. POSITIVE SUPPLY VOLTAGE
2. CHANNEL 1 INPUT
3 CHANNEL2 QUTPUT

4 SUPPLY AND SIGNAL GROUND
5 CHANNEL 2 INVERTED OUTPUT

6 CHANNEL 2 NON INVERTED OQUTPUT
7 CHANNEL 7 INVERTED OUTPUT
8 CHANNEL 1 NON INVERTED OUTPUT
MK 1324

Figure
C-8 9638 Logic Diagram and Terminal Identification

C-12

APPENDIX D
PROGRAMMING

EXAMPLES

Two examples are included in this appendix. The first is an example
for bit-oriented protocols, and the
second is an example for byte count-oriented protocols.

These are only examples and are not intended for any other purpose.

. TITLE

DPV11

. IDENT

/X0,

1920 BY

EQUIPMENT

CORPORATIOCN,

2DM

FOR

BIT

MAYNARD,

ORIENTED

PROTCZ2COLS

MASS,

DIGITAL

CpPV-11

EXAMPLEL

RSX-11M

APPLICATION
-

NOTE

THIS

WOT

BIT

ORIENTED

RUNNING

NDPV-11

DEVICE

DRIVER

k%%

HWDDF3,SINT3X,SINTXT,MDCDFS,CCBDFS,
TMPDFS, ASYRET, SYNRET

+.MCALL

HWDDF
$

CCBDFS
MDCDF$

[
.

TMPDFS

REGISTERS

DEFINE

THE

HARDWARE

DEFINE

THE

CCB

DEFINE
DEFINE

THE MODEM CONTROL SYMBOLS
LINE-TABLE TEMPLATE OPERATORS

OFFSETS

CHARACTERISTICS

DEVICE

guredl

DC.PRT

gouoe’

DALN4C

DC.SPS

cocol3

DC.SSS

Cao633

CC.ADR

0uae29

Ccooela

DC.MPT
DC.SEC

DC.HDX

DEFINED

HHALF-DUPLEX LINE INDICATOR
PROTOCOL SELECTION FIELD

(WORD
(WORD

MULTI-POINT CONFIGURATION
MULTI-POINT SECONDARY MODE
STATION ADDRESS IS 14 BITS
SDLC PRIMARY STATION
SDLC SECCNPDARY STATION

(WORD

¥
-

STATUS

DEVICE

FLAGS

DD. ENE

201

CD.5TR

2
ge

DD.EOM

Cr.EOM

DD.50M

CF.50M

[

DD.ABT

D29

DD.SYN

CEF.S5YN

DD.TRN

CEF.TRN

DD.ACT

200

DD.DIS

DD.ENB!DD.ST

SEL

]

-D.DCHR-

DEFINED

ZERO,
ZERO,

LINE
LINE

#1)
(WORD #1)
(WCRD #1)
(COMPOSITE)
(COMPOSITE)

-D.FLAG-

HAS
HAS

BEEN
BEEN

ENABLED
STARTED

—-=-(UNUSED)
---(UNUSED)

TRANSMIT

ABORTED DUE

TRANSMIT

SYNC-TRAIN

UNDERRUN

REQUIRED

TRANSMIT LINE TURN-AROUND REQUIRED
TRANSMITTENRR READY FOR NEXT FRAME
; INITIAL STATUS = DISABLED, STOPPED

MODEM

CONTROL

BITS

s
WE
Wy
WE
W

0ol

geBen2

CLEAR

CARRIER
MODEM

Pooen4

CHANGE

DATA

00Pv010

INDICATOR

DATA

PeBa40

SET

REQUEST

DSSEL

PP1000

DATA
RING

DATA

DSDTR

DSRTS

DSLOOP

| B

DSITEN

DSMODR

p20000

210000

DSCARY

DSCTS

180200
040060

DSRING

DSCHG

SEND

SELECT FREQUENCY

INDICATOR

READY

SET

INTERRUPT

SET

LOOPBACK
TO

ENABLE

SEND

TERMINAL

READY

OR REMOTE

SEL

]

RECEIVER

CONTROL

BITS

;

Po4000

RECEIVER

ACTIVE

RXSRDY

02000

RECEIVER

STATUS

RXACT

READY

#0)
#1)

LOOPBACK

RXREN

wme

FLAG

000100
000020

RECEIVER
RECEIVER

DONE

RXITEN

PPo400
000200

®E

wuuu

RXFLAG
RXDONE

@01000

RXSTRM

202400

]

(A |

RXENDM

SEL

]

-—-

n
W
[|

RECEIVER

CRC

ASSEMBLED

RECEIVER

BUFFER

RECEIVER

DATA

ERROR

RECEIVED

ABORT

RECEIVED

END

RECEIVED

BIT COUNT
OVERFLOW (SOFTWARE
OVERRUN

ALL

PARTIES

DDCMP

STRIP

SYNC

ADDRESSED

BISYNC

3*40¢

’

000377

PPSTRP!DPCRC

ERROR)

OF MESSAGE
START OF MESSAGE

OPERATION
OR LOOP MODE
SDLC / ADCCP SECONDARY STATION
4
IDLE MODE SELECT
¥ *

004000

]

INPUTS

RECEIVER

210600

ENABLE

MODE CONTROL OUTPUTS

190000
040000
020008

SEL

STATUS

WMy

RXABRT

0B4000
002000

RECEIVER

|I T

RXOVRN

100000

g7000¢
210000

RXERR

-—

]

RXABC
RXBFOV

SEL

RECEIVER INTERRUPT
RECEIVER ENABLE

DETECT

USE

CRC

ERROR

STATION

ADDRESS

INITIAL

STARTUP

TRANSMITTER

SELECT

DETECTION
OR

SYNC CHARACTER
PARAMETERS

STATUS

AND

CONTROL

coecla

TRANSMITTER

ccoo04

MAINTENANCE

godag2

TRANSMITTER

Nd
W

Je01C0

pea020

DEVICE

TXDONE

TXACT

TXMAI

CHARACTER

TXITEN

TXREN

w04000

03400

]

EXCON
RCLEN

TRANSMIT

EXTENDED ADDRESS FIELD
EXTENDED CONTROL FIELD
RECEIVE CHARACTER LENGTH
TRANSMITTER INTERRUPT ENABLE

210000

l15000¢

EXADD

TCLEN

TXRES
Wmg
W

0Ce081
6

]

-—

ENABLE

MODE
DONE

ACTIVE

TRANSMITTER

OUTPUT

Wy
We
Wy

£020009
¢2l100¢

coe4co

TRANSMIT

END

TRANSMIT

START

PROCES S

DISPATCH

CONTROLS

TRANSMITTER DATA LATE
TRANSMITTER GO AHEAD
TRANSMITTER ABORT

TXSTRM

120000
604200

]

TXENDM

TXABKRT

TXLATE

TXGO

SELECT

RESET

SEL

LENGTH

(UNDERRUN)

MESSAGE
OI

MESSAGE

TABLE

«-WORD

TRANSMIT

ENABLE

.WORD

$SDASX
$SDASR
SSDKIL
$SDCTL

RECEIVE

ENABLE

- WORD

-WORD

KILL

ENABLE

SDXPTB:
:

CONTROL

I/0

D-3

ENABLE

(ASSIGN

BUFFER)

-WwORD

SSDTIM

.SBTTL

3SDPRI

;
—--

TIME OUT

RECEIVE

INTERRUPT

SERVICE

ROUTINE

: +

FUNCTION:

;
;

THE DEVICE INTERRUPT IS VECTORED BY THE HARDWARE TO THE
DEVICE LINE TABLE. THE '$SDPRI' LABEL IS ENTERED VIA A

:
;:

CALLING
ON

SEQUENCE

IN THE LINE TABLE AT OFFSET

'D.RXIN'.

ENTRY:

:
:
;

R5
G(SP)
2(SP)
4 (SP)

=
=
=

ADDRESS OF 'D.RDBF'
SAVED RS
INTERRUPTED PC

INTERRUPTED

IN THE

LINE

TABLE

;

OUTPUTS:

;

D.RVAD =

ADDRESS

'D.RDB2'

THE

RECEIVER STATUS BITS

LINE

TABLE

FROM CSER

[SEL

SSDPRI::
MOV

R3,-(SP)

MOV
@ (R5)+,R4
BIC
# RXABC, R4
.IF DF M$S$SMGE
MOV
KISAR6,- (SP)
MOV
(R5)+,KISAR6

SAVE

REGISTERS

;3;
;:;

GET CHARACTER AND FLAGS
DON'T WORRY ABOUT ASSEMBLED BIT COUNT

:::
:;;

SAVE CURRENT MAP
MAP TO DATA BUFFER

.IFTF

DEC

BMI

(RS) +
DPRBOQO

:::;
:;;

DECREMENT BUFFER BYTE COUNT
BUFFER OVERFLOW - POST COMPLETE

MOV
BIT
BNE

2(R5) ,R3
#RXSRDY,~(R3)
DPRCP

;;;
:;;
;:;

GET CSR+2 ADDRESS
ERROR OR END-OF-MESSAGE ?
YES - POST RECEIVE COMPLETE

MOVB

R4 ,@ (R5) +

:::

STORE CHARACTER

MOV

(SP)+,KISARG

; ;;

RESTORE

- (R5)
(SP) +,R4

; ;;

ADVANCE

BUFFER ADDRESS

MOV

:;:;

RESTORE

REGISTERS

MOV

(SP)+,R3

222

;::;

EXIT THE

;;:;
:::;

BUFFER OVERRUN
SET (SOFTWARE)

RECEIVE

BUFFER

.IFT

MAPPING

LIFTF

INC

SINTXT

DPRBO:

BIS

DPRCP:

+IFT

#RXBFOV, R4

INTERRUPT

HAS OCCURRED
ERROR INDICATOR

::;: END-OF-MESSAGE OR ERRQR INDICATION

hed

- §

wmy

(SP) +,KISARS

RECEIVE

COMPLETE,

ADD

#D.RCNT-D.RCCB,R5

SUB

(R5)+,C.CNT1
(R4)

BIC

BEQ

$61777, (R5) +
46S

ASR

- (R5)

60S

BlS
MOV

C.STS(R4)
,R3
R3,-(SP)

CALL

SDDRCP

MOV

(SP)+,R3

MOV

(5P) +,R3

WITH

THE

INTERRUPTS

COMPLETE

FRAMES
SAME

FOR

BUFFER

Wy
my
W

RECEIVER
RE-ENAELE

;

FAILED

ERROR

DISABLE

LEAVE

CSR

RECEIVER

REPORTED

RCVR
ISEL

RESTCRE

THE

ANY

INACTIVE
DLC ?
RE-SYNC

INTERRUPTS

SYSTEM

DRCLKA:

ENTRY:

MOMENTARILY RESET 'RXREN'
FLAC IN GCGRDER TO FORCE RECEI
VER
RE-SYNCHRONIZATION.
THIS IS REQUIRED FOR ANY ERROR
WHICH
TERMINATES THE RECEIVE OPE RATION
IN MID-FRAME.

ADDRESS

'D.RCCB'

THE

D-5

LINE

TABLE

FRAME

DLC

FOR

RECEIVER

EXIT

STATUS,

REPORTED

RETURN

- POST

ABORTED

#RXITEN,- (R3)

O.K.

W My

wWe

TME

-{(R%) ,R3

STATUS

?
COMPLETE

POST RECEIVE COMPLETE
RECOVER COMPLETION STATUS
ASSIGN NEW CCB TO THE RECEIVER

YES

MOV

3IS

RE-SYNC

WAS

DRCLRA

RECEIVED
FOR COMPLETION

ABORTED

STATUS

ms WE

EMI

DUAL COUNT
FRAME BYTE COUNT

INCLUDE

POPPED)

RESI

SAVE

TS84

NOT

NUMBER

RBFSET
CREXIT

FRAME

;COUNT

CALL
BCS

RE-INITIALIZE
RE-ENABLE

W4 e W

RBFUSE

Wma

Mg We Wy

D.RABT-D.RDB2
(RS

R4)

(RS

PLACES RIGHT
'RXABRT' INTO C-BIT
USE INDICATORS AS TABLE INDEX
R3 NOW = CCB STATUS FLAGS

40S

INC

SHIFT

BCC

TWO

BUT NOT

BUFFER

INDICATORS...

(R5)+,R3
RCVERR-2(R,R3
3)

-«

TO THE

RECEIVE

ERROR

NEW

ADDITIONAL

REPORTED

POST

et Wy

MOVB
MOV

SHIFT

ERRORS
--

WMy

- (R5)

(R5)
+

ASRB

ANY

SAVED

COMPUTE
SET

ADDRESS

ASR

DREXIT:

BACK

4CS:

SAVE

CCB

CLR

CALL

(R5) ,R4

R3,-(SP)

MOV

(R5

ASSIGN

POST

ERRORS,

SINTSV

WME

FOR

CHECK

TRICKY

TME

We
Wy

(SP)+,R3

GET

T ]

SINTSX

STATUS FLAGS IN 'D.RVAD®
CSR+2 ADDR + POINT TO 'D.RPRI‘
CLEAR RECEIVER INTERRUPT ENABLE
RESTORE R4 SO 'S$INTSV' IS HAPPY
AND R3

MOV

SAVE

$RXITE
- (R4)
N,
(SP)+,R4

MAPPING

BIC
MOV

PREVIOQUS

R4, (R5) +
(R5)+,R4

MOV

RESTORE

MOV

- ENDGC

R4
;

(SP)=

ADDRESS
SAVED

DRCLRA:

'C.STS'

THE

NEWLY-ASSIGNED

CCB

VALUE

mMov.

BIC

-(R5),R3

;;

RCVR

CSR

#RXREN,-(R3)

RESET

ADDRESS

RCVR

[SEL

FOR

RE-SYNC

ENABLE

BIS

#CS.RSN, (R4)

;;

SET

BIS
BR

# RXREN!RXITEN, (R3)
DREXIT

;3
;;

RE-ENABLE THE RECEIVER
RESTORE R2 AND EXIT

.SBTTL

S$SDPTI

-—--

TRANSMIT

RE-SYNC

INTERRUPT

SERVICE

CCB

'C.STS'

ROUTINE

; t

;

FUNCTION:

;

THE DEVICE INTERRUPT IS VECTORED BY THE HARDWARE TO THE

;

DEVICE

LINE TABLE.

;

CALLING

SEQUENCE

;

ONCE

;

HANDLED

;

FRAME
BY

THE

ROUTINE

LABEL

TABLE

INITIATED,

ADDRESSED

VIA

ENTERED VIA A

OFFSET
EACH
THE

'D.TXIN'.

INTERRUPT

'D.TSPA'

WORD.

ENTRY:

ADDRESS

;

¢ (SP)})

SAVED

;

2(SP)

INTERRUPTED

;

4(SP)

INTERRUPTED

LINE

TRANSMISSION

;

'SSDPTI'

THE

'D.TCSR'

THE

LINE

TABLE

EXIT:

;

ADDRESS

'D.TCCB'

THE

LINE

TARIL

SSDPTI::

MOV

R4,-(SP)

SAVE

MOV

(R5)+,R4

;5;

TST

(R4) +

;::

POINT

JMP

@(R5)+

;::;

CORRECT

CURRENT

STATE

R4
TRANSMITT:- Sk

MONITOR

CSR

[SEL

FOR

ADDRESS

TEST

STATE

'CLEAR

UNDERRUN

PROCESSOR
TO

SEND'

;

TISCTS:

;

BIT

#$DSCTS,-6(R4)

;:;

BNE

TISIFL

;+:

YES

'"CLEAR TO
-

START

SEND'
TO

ACTIVE

SEND

THE

BITB

#DD.SYN,D.FLAG-D.TCNT(RS)

;;;

SYNC-TRAIN

REQUIRED ?

BEQ

TISIFX

;::

FLAGS

MOV

$§ TXSTRM! TXENDM, (R4)

;:;

START +

TISEXT

CURRENT STATE =

SEND INITIAL FRAME

MOV

¥TISTRT,—- (R5)

;:;

STATE

MOV

#TXSTRM, (R4)

;7;

SEND

END

SENDS

"FLAG'

UNTIL

'CTS'

SYNC

STRING

;

TISIFL:

SEND

ADDRESS

BYTE

SDLC

FLAG

CHARACTER

TISIFX:

YET ?

FRAME

;
f

TISEXT

CURRENT

STATE

SEND

ADDR

BYTE

FOLLOWING

'FLAG'

;

TISTRT:

DEC

(R5)

MOV

D.TADC-D.TCNT(RS)
, (R4)

i i;

DECREMENT

;;;

MOV

SEND ADDR,

$TISDAT,- (R5)

CLEAR

;;;

TISEXT

COUNT

STATE

FOR

ADDR

DATA

TRANSFER

;

cuanENT

STATE

mmmmmm

TRANSFER

mmmmmm

FRAME

DATA

mmmmmm

BYTES

mmmmmm

mmm

TISDAT:

.IF

BMI

TISLAT
(R5) +

i i;

UNDERRUN

BMI

; i ;

TISEND

DECREMENT

i;;

ALL

MS$SSMGE

MOV

KISAR6,- (SP)

MOV

i ;;

(R5) +,KISAR6

SAVE

i7;

MAP

MOVB

(R5)
‘
@ (R5) +, (R4)

i;;

ADVANCE

;i7

MOV

(SP)+,KISARS

i ;7

RESTORE

i i;
(SP) +,R4

COMMON

;;;

RESTORE

.IFTF
INC

.IFT
. ENDC

TISEXT:

|
MOV

SINTXT
PTT

;

DONE

777

CURRENT

STATE

DATA

ABORT AND RE-TRANSMIT

DATA
-

BYTE

SEND

CURRENT
TO

EXIT
e

;

mmmmmm

DEC

BYTE

'TXSTRM'

THE

COUNT

END-MSG

SEQUENCE

MAPPING

TRANSMIT

BUFFER

ADDRESS

THE

CHARACTER

LEVEL-7

SENT

MAPPING

INTERRUPT EXIT

INTERRUPT SERVICE
e

e e f f e e 4 BYTE-COUNT EXHAUSTED

oo ;
;

TISEND:
MOV

$TXENDM, (R4)

INC

- (R5)

MOV

#TISFLG,- (RS)

ASLB

;

D.FLAG-D.TSPA(R5)

BPL

TISEXT

MOV

§TISPAD, (R5)

TISEXT

CURRENT

STATE

mmmmmm

SEND

mmmmmm

7;;

TRANSMIT

i ;i

ADJUST

iii

ii;

END-OF-MSG

SEQUENCE

AND CLEAR

STATE

'D.TCNT'

= IDLE

TEST

FOR

iii

—-

IDLE

THE

YES

SEND

PADS,

'ABORT'

PAD

CLRB

$TISCLR, - (R5)

# TXABRT, (R4)

BR
Pm

;

—

i7;

RESET

THE

STATE

;i;

SET

"TXABRT'

DEVICE
=

FLAG

SEND
TO

—

CURRENT STATE

SEND SECOND

BYTE

SECOND

SEND

PAD

'ABORT'

PAD

;

TISEXT
=

FLAGS

DISABLE

'FLAG';
mmm

i ;i

WITH

THEN

mmmmmm

D.FLAG-D.TCNT(RS)

MOV

LINE

AFTER

mmmmmm

TISPAD:

MOV

(ASSUMED)
TURN-AROUND

LINE

ii;

mmmmmm

FLAGS

;
H

TISCLR:
MOV

$TISRTS, - (R5)

i ;i

D-7

STATE

DROP

'REQUEST

SEND'

TISCLX:

;

MOV

#TXABRT, (R4)

;:;

SETUP

BIC

BTXREN, - (R4)

:::

DISABLE

TISEXT

CURRENT

STATE

DROP

SEND

THE

REQUEST

ANOTHER

'ARORT'

CHAR

TRANSMITTER

SEND

EXIT

;

TISRTS
:

;

BIT

#DC.HDX,D.DCHR-D.TCNT(RS)

;;;

HALF-DUPLEX

CHANNEL

BEQ

TISDON

::;;

'RTS'

LEAVE

ACTIVE

BIC

#DSRTS, -5 (R4)

;:;

DROP

'REQUEST

TISDON

ji;

POST

TRANSMIT

COMPLETE

CURRENT

STATE

TRANSMITTER

DATA

SEND'

UNDERRUN

MOV

#TISDON, - (R5)

:;:

STATE

MOVE

$DD.ABT,D.FLAG-D.TSPA(RS)

;;;

THIS

FRAME

WAS

ABORTED

INC

D.TURN-D.TSPA(R5)

:;;

COUNT

THE

ERROR

EVENTS

TISCLX

:;;

SEND

PAD,

CURRENT STATE
=

LINE

RE-TRANSMIT

DISABLE

TRANSMITTER

IDLE FLAGS BETWEEN FRAMES

;

TISFLG:

MOV

#TXSTRM, (R4)

::;

MOVE

#DD.ACT,D.FLAG-D.TCNT (RS)

;;; TRANSMITTER

CURRENT STATE =

CLEAR

'TXENDM',
IS

IDLE

FLAGS

ACTIVE

POST COMPLETE OR RE-TRANSMIT

;

TISDON:

ADD

#D.TPRI-D.TCNT,RS

;;;

ADJUST

BIC

#TXITEN,- (R4)

;:;

DISABLE

MOV

(SP) +, R4

;;;

RESTORE

;:;

'SINTSV'

SINTSX

TABLE

POINTER

'TXDONE'
INTERRUPTS
R4 FOR PRIORITY DROP

W/0 R4

(POPS

R3,- (SP)

;;

SAVE

(R5) , R4

CLR

(R5) +

;;
;;

ACTIVE CCB ADDRESS TO
THIS CCB IS NO LONGER

R4
ACTIVE

BITB

$DD.ABT,D.FLAG-D.TCBQ
(R5)

;;

WAS

THE

BNE

TRSTRT

;;

YES

TST

D.KCCB-D.TCBQ (RS)

;;

TRANSMIT

BNE

CKILLT

YES

CLR

SET

COMPLETION

CALL

$DDXMP

;;

POST TRANSMIT

MOV

(R5) , R4

;;

FIRST

CCB

BEQ

TREXIT

;;

NONE

THERE

MOV

(R4) , (R5)

;;

REMOVE

CURRENT

STATE

CLR

(R4)

TRSTRT :

START

CCB

FRAME

SETUP

ABORTED

KILL

PROGRESS

CCB'S

COMPLETE

TO THE

SECONDARY

CHAIN

DLC

IDLE

SECONDARY

CHAIN

TRANSMISSION

|
;;

CLEAR

CCB

THE

SUCCESS

TRANSMITTER

RE-TRANSMISSION

RETURN

STATUS

FROM

FRAME

ADDITIONAL

RS)

MOV

;;

SAVED

MOV

e
e

;

LINE

LINKAGE

WORD

?
DLC

R4 ,- (R5)

TST

- {R5)

ADD

$C.FLG1,R4

BISB

(R4) ,D.FLAG-D.TP
(RS)
RI

MOV
CLR

- (RS)

MOV

—~(R4)
,- (RS

-(R4) ,D.TCNT-D.TPRI
(RS)

SETUP

SKIP

BACK

THE

POINT

SAVE

FLAGS

;MAKE

SURE

;

SET

;

THE

BYTE

TRANSMIT

SET

TRANSMIT

(R5) +,KISARA

MOV

WTM

-(R4) ,-(R5)
KISAR6,-(SP)

SAVE
MAP

THE

@ (R5)+, (RS)

;;

MOVE

MOV

(SP)+,KISARG

; ;

RESTORE

BACK

MOVB

ADD

#D.TSPA-D.TADC,RS5

: ;

D.FLAG-D.TSPA(RS5)

H ; IS

THE

BPL

20$

; ;

WORD
ADDRESS

TRANSMIT
BYTE

BUFFER

'D.TADC®

APRG6

MAPPING

PROCESSOR

STATE

TRANSMITTER

ENABLE

IT,

READY

THEN

409%

MOV

-2(RS) ,R3

; ;

BISN

TRANSMITTER

#DSRTS,~-4(R3)

- ;

ASSERT

'REQUEST

BIS

#TXREN, (R3) +

: ;

ENABLE

THE

MOV

#TISCTS, (R5S)

;;

INITIAL STATE = WAIT FCR

Bis

BTXITEN,
@~ (R5)

MOV

(SP)+,R3

sTISTRT, (R5)

MOV

INITIAL

ENABLE

CELL

NOW

START

LT B

OFF

COUNT

BUFFER

ADDRESS

TSTB

BUFFER RELOCATION
CURRENT APRG MAPPING

THE
TO

FLAGS

USE

FLAG

'D.TADC'

SET

. ENDC

4335

BUFFER

LEVEL-7

'ABORT'

.IFTF

208

CCB

FOR

TRANSMIT

CCB

'D.TPRI'

MOV

1FT

ACTIVE

OVER

INITIALIZE

MS$SMGE

MOV

.IF

MOV

STATE = SEND ADDR BYTE
INTERRUPTS AND EXIT

RE-ENABLE

CSR

[SEL

SEND!

TRANSMITTER

TRANSMIT

rCTS!

INTERRUPTS

TREXIT:

ASYRET

: ;

RESTORE

;

EXIT

CURRENT STATE =

FROM

WHEREVER
-

TRANSMIT KILL OR TIMEOUT
W

ENTRY

APPROPRIATE,
e

CKILLT:

MQOV

#CS.ERR!CS.ABO,-(SP)

BIC

#TXREN,@D.TCSR-D.TCBQ(RS)

MOV

(R5), (R4)

ADD

CLR

(RS) +

HEH

CLEAR

MOV

(SP) ,R3

COMPLETION

MOV

(R4) ,- (SP)

CCB

ADDRESS

CLR

(R4)

SURE

LINK

SDDXMP

MAKE

CALL

}

MOV

POST
A CCB

(SP)+,R4

CKTTiMO:

2€S:

;

;;

TRANSMIT

COMPLETION

STATUS

~
;i

DISABLE

SECONDARY

CCB

TRANSMITTER

CHAIN

STATUS

TOD
TC

WORD

COMPLETE

ADDRESS

CHAIN

PRIMARY

POINTER
R3

STACK
IS

ZERO

W/ERROR
R4

ASYNC

BNE
TST

MOV

20
(SP) +

;;
;;

(RS) ,R4

;;

BEQ

TREXIT

CLR

CMPB
BNE

CALL
BR

CALL

405 :

KILL CCB ADDRESS TO R4

;;

NONE - RESTORE R3 AND EXIT

STATUS

KILL NO LONGER IN PROGRESS

;;

(R5)

CLR

MORE TO GO - CONTINUE
CLEAN STATUS OFF THE STACK

SUCCESSFUL

AFC.KIL,C.FNC(R4)

;;

KILL-I/O OR CONTROL FUNCTION ?

SDDKCP
TREXIT

;;

;;
;:;

CONTROL -

425S

;;

SDDCCP

TREXIT

.SBTTL

S$SDASX

POST

IT COMPLETE

POST KILL-I/0 COMPLETE
RESTORE R3 AND EXIT

POST CONTROL COMPLETE

RESTORE R3 AND EXIT

TRANSMIT

ENABLE

ENTRY

Hiaa

;

FUNCTION:

'$SSDASX' IS ENTERED (VIA THE DISPATCH TABLE) TO QUEUE A

;

IF THE
CCB CONTAINING AN SDLC FRAME TO BE TRANSMITTED.
TRANSMITTER IS BUSY, THE CCB IS QUEUED TO THE SECONDARY
IF NOT, THE TRANSMITTER IS ENABLED TO START
CCB CHAIN.

;
:
;

TRANSMITTING THE NEW FRAME.

;
;

ENTRY:

R4
RS

:
H

PS = PRIORITY OF CALLING DLC PROCESS

;

= ADDRESS OF TRANSMIT ENABLE CCB
= ADDRESS OF DEVICE LINE TABLE

EXIT:

;

SSDASX: :

ALL REGISTERS ARE UNPREDICTABLE

MOV

;; SAVE R3 FOR EXIT VIA '"TRSTRT'

MOV
BIC

D.TCSR(RS5) ,R3
$TXITEN, (R3)

;; TRANSMIT CSR ADDRESS (SEL 4] TO R3
;; DISABLE TRANSMITTER INTERRUPTS

TST
BEQ
MOV

(R5) +
TRETRT
R4,-(SP)

;; IS THERE AN ACTIVE CCB ?
;3 NO -- START UP THE TRANSMITTER
;; SAVE POINTER TO FIRST CCB

MOV
MOV

RS, R4
(R4) ,RS

;; COPY THE CCB ADDRESS TO R4
;; ADDRESS OF THE NEXT CCB TO R5

MOV
CLR
BIS

(SP)+, (R4)
@(R4) +
$#TXITEN, (R3)

;; LINK NEW CCB TO END OF CHAIN
;; MARK NEW END OF CCB CHAIN
; ; RE-ENABLE TRANSMITTER INTERRUPTS

ADD

20S:

R3,-(SP)

BNE

#D.TCCB, RS

20$

;;

POINT TO ACTIVE CCB ADDRESS CELL

LOOP UNTIL WE FIND THE END

D-10

TREXIT

.SBTTL

$SDASR

;;

RESTORE

RECEIVE

ENABLE

AND

AFTER

EXIT

BUFFER WAIT

FUNCTION:

THIS

ROUTINE

BUFFER

CALLED

ALLOCATION

FAILURE

THE

AND A

BUFFER

CAN

CALL

POOL

MANAGER WHEN

SATISFIED,

FOLLOWING

'SRDBWT'.

ENTRY:
wn

ADDRESS

CCB

ADDRESS

DEVICE

AND

RECEIVE BUFFER
TABLE

LINE

EXIT:
u

'D.RCCB'

(SP)

ADDRESS
ADDRESS

'C.STS'

s
wr

SAVED

VALUE

IN
IN

THE
THE

LINE

TABLE

CCB

RB:”(SP)
DRCLRA

MOV

JMP

#CS.BUF, (R4)

BIS

POINT
ASSIGN

#D.RDB2,RS
RBFUSE

PREV.

AT1

ADD

CALL

:
SSDASR:

PUSH

s
5

ALLOCATION

REQUEST

RESET

SECOND

BUFFER

ALLOC.

FOR

AND

RCVR-CSR WORD
THE RECEIVER

FAILURE

EXIT

ACTIVATE

CCB

'C.STS'

'DREXIT',

ABOVE

THE RECEIVER

;

SSDSTR

START

DEVICE

AND

LINE

ACTIVITY

$SSDSTR::
#DD.ENB,D.FLAG(RS)

;; HAS

6OS

RECEIVE

FAILED

START

;

ENABLE

RECEIVER

FOR

START

BUFFER
CCB

THE

AND

BUFFER

TRANSMITTER

INTERRUPTS

CHECK

CORRECT

ASSERT 'REQUEST
.+« AND

MODE

ADDRESS

RECOVER

D-11

ROUTINE

CTLCMP

TABLE

RECEIVER

#DSRTS, (R3)

BIS

ENABLED
‘'START'

OPERATING

LINE

#DC.HDX,D.DCHR(RYS)
CTLCMP

[SEL

BIT

BNE

ADDR

BYTE

BEEN
THE

wmy

w
W

ASSIGN

THE

LINE

(5P) +,R5
D.FLAG (R5)

CSR

ADDRESS

MOV
CLRB

#RXITEN, (R3)

BIS

205

RBFSET

BCS

ADJUST

wmy

CALL

SAVE

#D.RDB2,R5

R5,-(SP)

ADD

ENABLE

]

MOV

RECEIVER

SET

#RXREN,-(R3)

LINE

REJECT

BIS

THE
--

D.RDBF(RS)
,R3
D.STN(RS(R3)
),

MOV

20$:

BITB
BNE

LINE

HAS

TABLE

BEEN

THAT
-

START

STARTED

ASSUMPTION
STARTUP

POST

START

COMPLETE
SEND'

LINE

COMPLETE

605%:

MOV
BR

4CS.ERR!CS.DIS,R3
CTLERR

DP.NQOP:

;;
;;

CONTROL

STATUS

STATUS = LINE DISABLED
RETURN ERROR W/COMPLETION

FUNCTION

NO-OPERATION

CTLCMP:

CLR

SUCCESSFUL

CTLERR:

MOV

(SP)+,R4

RECOVER

;;

SYNCHRONQOUS

SYNRET

.SBTTL
:

'*'SsS

:
SSDSTP:

TOUP'

STOP DEVICE AND LINE ACTIVITY

ONTR

FUNCTTI

D.RDBF(R5) ,R3

;;

#DSDTR, - (R3)

RECEIVER CSR ADDR
DISABLE RECEIVER,

CLR

4 (R3)

;;

DISABLE

MOV

D.RCCB(R5) ,R4

;;

ACTIVE

BEQ

20S

NONE

VALUE

RETURN

MOV
MOV

CALL

205:

SSDSTPV --

SAVED

SRDBRT

;

[SEL 2] TO R3
LEAVE 'DSDTR'

ACTIVE

TRANSMITTER
RECEIVE

THERE

RETURN

CCB

SKIP

BUFFER TO THE

POOL

CLR

D.RCCB(R5)

NO RECEIVE

CLR

CLEAR

BISB
CALL

D.SLN(R5) ,R4
SRDBQP

;;
; ;

SET SYSTEM LINE NUMBER IN R4
PURGE BUFFER WAIT QUEUE REQUESTS

BISE
TST

$DD.STR,D.FLAG(RS5)
D.TCCB(R5)

;;

LINE

BEQ

CTLCMP

NO -—

MOV
MOVB
ASYRET

(SP)+,D.KCCB (R5)
#1, (R5)

::
;;
:;

SAVE THE CONTROL CCB FOR TIMEOUT
MAKE SURE THE TIMER IS ACTIVE

.SBTTL

SSDENB

THE

PARAMETER

USE

IS NO LONGER STARTED
THERE AN ACTIVE TRANSMIT CCB
POST

RETURN

ENABLE

CCB ASSIGNED

FOR

CONTROL

WITH

COMPLETE

ASYNCHRONOUS

COMPLETION

LINE AND DEVICE
TM

$SDENB:

20$

ENABYULE

:
MOV

D.RDBF(RS) ,R3

RECEIVER

BIS

#TXRSET,2(R3)

;:;

RESET

ADD

#D.DCHR+2,R5

:s POINT

BIT
BEQ

#DC.ADR, (R5) +
20$

;;
:;

SWAB

(R5S)
;; USE THE HIGH-ORDER BYTE IN DPV-11
$# "C<DPADRC>,
(R5) ;;CLEAR HIGH-ORDER BYTE OF 'D.STN' WORD

BIC

BIS
BIC

$#INPRM, (R5)
#DC.ADR,~ (R5)

THE
TO

CSR

ADDRESS

DEVICE

[SEL

(1-US

SINGLE-SHOT)

CHARACTERISTICS

WORD

16-BIT STATION ADDRESS ?
NO -- SHOULD BE ALL SET

: :SETUP INITIAL PARAMETERS
:; ADDRESS~-SIZE NO LONGER SIGNIFICANT

CMPB

#DC.SPS, (R5)
409
#DC.SSS, (R5)

BEQ

CMPB
BNE

60
#DPSECS, 2 (R5)

BIS

40S:

BIS

PRIMARY-STATION MODE ?
YES - FLAGS ARE SETUP AS IS
SDLC SECONDARY-STATION MODE
?
NO -- OPERATING MODE INVALID
ENABLE STATION ADDRESS
CHECKING

#DSDTR, - (R3)
i i ASSERT 'DATA TERMINAL
READY' LINE
#DD.ENB,D.FLAG*D.DCHR*Z(RS)
7 LINE IS ENABLED
CTLCMP
ii POST CONTROL FUNCTION
COMPLETE

BICB
BR

60S:

SDLC

ii
i 7

MOV

#CS.ERR!CS.DEV,R3

CTLERR

.SBTTL

SSDDIS

MOV

#CS.ERR!CS.ENB,R3
#DD.STR,D.FL
(RS)
AG
CTLERR

~--

;7;

ERROR

POST CONTROL COMPLETE WITH ERRO
R

STATUS

INVALID

PROTOCOL

DISABLE THE LINE

MOV

D.RDBF (RS) ,R3
- (R3)

CLR
MOVB

$SDMSN
ORI

D S

ENSE
A_T———- A

o—— DA

ii CLEAR

ADDRESS

#DSDSR,*(RB)

THE

YES

208
#MC.DSR,
R4

#DSRING, (R3)
409

#MC.RNG,
R4

;

CTLCMP

CODE

NOT

STATE

REJECT

THE

ADDRESS

DISABLE

RECEIVER

LINE

CLEAR

STOPPED

CORRECT

THE
--

YES

FOR
OF

RECEIVER
+

CSR

[SEL

TURN

DTR

OFF

LONGER ENABLED
CARRY AND EXIT

THERE

NO --

YES

RETURN

POST

RETURN

CODES
CSR

[SEL

SET

RINGING

INDICATOR

CARRIER

?
IN

PRESENT

INDICATOR

RESULTS

CONTROL

READY
.?

POST COMPLETE

D-13

INDICATOR

PHONE
SET

;77

RECEIVER

(SAVED)

FUNCTION

DISABLE

DATA-SET
SET

#DSCARY, (R3)

R4, (SP)

;;

#MC.CAR,R4

LINE

STATU

D.RDBF (R5) ,R3

6083

ODEWM

20S:

SENSE MODEM STATU

-y

TME

D W

#DD.ENB!DD.STR,D.FLAG (RS)
CTLCMP

ERROR

BEQ

-y

BITB

$SDDIS:
:

R¢4

COMPLETE

DPV - BYTE ORIENTED DPV-11 DEVICE DRIVER MODULE

.IDENT

/XB0/

.TITLE

(C)

1980

w3y

DIGITAL EQUIPMENT CORPORATICN,

EXAMPLE
.MCALL

OF AN APPLICATION RSX-11M BYTE CRIENTED DPV-11 DEVICE DRIVER
,
ENABLS
SINTSX,SINTXT,INHIBS

.MCALL

CCBDFS$, TMPDFS$,SLIBCL

.MCALL

MDCDFS$S
CHADF'S

.MCALL

DEFINE MODEM CONTROL SYMBOLS

TRe

MDCDF$
CCBDF3

MASS.

MAYNARD,

TMPDFS$

CHADFS

DEFINE THE CCB OFFSETS

DEFINE LINE TABLE OFFSET MACROS
DEFINE DEVICE CHARACTERISTICS

LOCAL SYMBOL DEFINITIONS
TRANSMITTER FLAGS
el

ACTIVE

Wy
e

TRANSMIT

TRANSMIT START 7 F MESSAGE
TRANSMIT END OF «ESSAGE

g
e
Ty
WE
Wy
g

ENARLE

INTERRUPT ENABLE

RECEIVE CRC
L ¢NC

CHECK

STRIP

SN
PROTTCOL SELECT'

(BYTE)

INITIAL RECEIVE STATUS
INITIALIZATION FLAGS

FLAGS

PoCo04
Q20€00
POORL2
01000
040000

RTS=
CTS=
DTR=
DSR=
RING=

040000

RXINT!RCVEN!DTR
SSYN!PROSEL!CRC

MODEM STATUS

RECEIVE

REQUEST TO SEND

WTME

RINIT=
[NPRM=

€00020
002100
3*40¢
g20000

CLEAR

PROSEL=

;

TRANSMIT INTERRUPT ENABLE

RECEIVE CSR FLAGS

RCVEN=
RXINT=
CRC=
SSYN=

;

(HALF DUPLEX)

ENABLE

;

INITIAL TRANSMIT STATUS
TRANSMIT

(00020
000120
000002
000400
01820

000010

TXENA=
TXINT=
TXACT=
TSOM=
TEOM=

TINIT=

;

LEAD

SEND

DATA

TERMINAL READY

DATA
RING

SET READY
INDICATOR

DPV1l DEVICE DRIVER DISPATCH TABLE

we
WE

.WORD

DPKIL

ENABLE

DPASR

.WORD

DPCTL

TRANSMIT

DPASX

-.WORD

KILL I/0
CONTROL TINITIATION

-WORD

DPTIM

wwy

:
: .WORD
SDPVTB

TIME

RECEIVE ENABLE
OUT

D-14

(ASSIGN BUFFER)

**-SDPVRI-DPV11l
THE

DEVICE

THE

'JSR

INTERRUPT

HARDWARE

R5,SDPVRI'

; TABLE.
;

RECEIVE

AND

INTERRUPT SERVICE ROUTINE

VECTORED

THE

THIS

ROUTINE

ENTERED

INSTRUCTION

LINE

BEGINNING

TABLE

THE

LINE

INPUTS:

;

STACK :

ADDRESS
OF

DEVICE

LINE

TABLE

;

@(SP)

SAVED

;

2(SP)

INTERRUPTED

;

4 (5P)

INTERRUPTED

;

6 (SP)

INTERRUPTED

;

THE

DEVICE

BIAS

OUTPUTS:

; ETC.

TMy

ERROR

RECEIVER

DATA

BUFFER

OVERRUN

MOV

KISAR6,-(SP)

MOV

(R5)+,KISAR®S

MSS$SMGE
SAVE

-y

OF RECEIVER
CHARACTER AND FLAGS

MAP

b1]

.IF

ANY

DPRHO

BMI

GET

(R4) ,R4

MOV

SAVE R{4
GET ADDRESS

(R5)+,R4

R4,-(SP)

STORE

MOV

et RTM

:
SDPVRI:

RESTORE

CURRENT
TO

DATA

MAP
BUFFER

R4,@ (R5) +

MOVB

. IFTF

CHARACTER

RECEIVE

BUFFER

IFT

(SP)+,KISARS6

b T ]

MOV

MAPPING

-(RS)

MOV

(SP)+,R4

W
e

TME

DECREMENT

REMAINING BYTE
RECEIVE COMPLETE
ADVANCE BUFFER ADDRESS
RESTORE REGISTERS

EXIT THE

EXCEPTIONAL

RECEIVE

SERVICE

ROUTINES

HARDWARE

OVERRUN

SINTXT

INC

(R5)
DPRCP

owmy

DEC
BEQ

« ENDC

D-15

INTERRUPT

COUNT

LSB

. ENABL
DPRHO:

;;;

#<RCNT-RDBF-2>,RS

ADD

#100001,RFLAG-RCNT(RS)

MOV

;;;

POINT TO COUNT CELL

;;;

CLEAR

SET FLAGS TO COMPLETE REQUEST AND

RECEIVE

#CS.ERR+CS.ROV,RSTAT-RCNT(RS)

;;;

ACTIVE

EXIT

SET OVERRUN STATUS

RECEIVE

COUNT

BYTE

RUNOUT

MOV

DPRCP:

;;: SAVE CRC FLAG AND POINT TO PRIORITY
R4, (R5) +
(R5) ,R4 ;;; GET RECEIVE DATA BUFFER ADDRESS
RDBF-RPRI
;:; CLEAR RECEIVER INTERRUPT ENABLE
#RXINT, - (R4)

MOV

MOV
BIC
MOV

(SP) +, R4

SINTSX

R3,- (SP)
(R5) +
(RS) +
20$
(R5) , R4

MOV
TST
ASR
BCS
MOV

.LIST

.
:;
;;
;;
.+

SAVE AN ADDITIONAL REGISTER
POINT TO FLAGS WORD
LOAD C-BIT FROM FLAGS (BIT 0)
IF CS DATA, POST COMPLETION
GET PRIMARY CCB ADDRESS

MEB

$SLIBCL

HDRA-RPRIM,RS5,$DDHAR,SAV

.NLIST

MEB

ROR
TST
BMI
BEQ

-2 (RS)
R3
10$
7%

#2,R3

ADD

79 :

::: RESTORE R4 SO 'SINTSV' IS HAPPY
;;:; DO A TRICKY SINTSV (R5 PRESAVED BUT NOT R4)

::
;;
;;
::

;;

MOV

R3,RPCNT-RPRIM(R5)

MOV

$5,R3

;;

$RCNT-RTHRD,R5
R3, (RS)

;;
;:

INC
ADD

- (R5)
R3,8-(R5)

INC

- (R5)

ADD
MOV

.IF

;3
;;
::

;;

CALL DDHAR THROUGH LINE TABLE

SAVE 'FINAL SEEN' IN FLAGS (BIT 15 SET)
EXAMINE BYTE COUNT FOR THIS MESSAGE
IF MI AN INVALID HEADER RECEIVED
IF EQ SET TO RECEIVE REST OF HEADER

ACCOUNT FOR BCC IN CURRENT COUNT

;;

SAVE DATA COUNT UNTIL HEADER CRC

CHECKED

GET REMAINING HEADER

MARK DATA IN PROGRESS IN FLAGS (BIT @ SET)
INCLUDE CURRENT COUNT IN TOTAL COUNT
POINT TO CURRENT COUNT
SET UP CURRENT BYTE COUNT

MOVE BUFFER ADDRESS PAST BCC

-4(R5),R3

;;

GET ADDRESS OF RECEIVE DATA BUFFER

- (R5) ,R3

;;

GET ADDRESS OF RECEIVE DATA BUFFER

REXT®

;

FINISH

.IFF

MOV

‘mgy

ad]

.ENDC

HEADER

RECEIVED

MS$S$SMGE

MOV

INVALID

D-16

IN COMMON CODE

BIT

$CS.MTL,R3

;

BNE

31$

MESSAGE

;

RECOVER

10$:

SET

MOV

(R5)+,R4

CALL

BUFUSE

MOV

RDBF-RPRIM(RS)
,R3

;;

COMPLETION
ON RECEIVE

COMPLETE

LONG

POST

COMPLETION

PRIMARY

CCB ADDRESS
“
CCB AGAIN (CLEARS 'RSTAT')
POINTE
TO REC.
R DAT. BUFF.

SET

405

TOO

YES,

CLEAR

THIS

RECEIVE

ACTIVE TO FORCE

POST

RESYNC

POINTS

WaE

TST

RCNT-RPRIM(RS5)

BMI

25$

BR
MOV

;;

ADDRESS

CRC

ERROR

RPCNTmRPRIM(RS),RCNT*RPRIM(RS)

BEQ

38$

ADD

RPCNT~RPRIM(RS),@RTHRD*RPRIM(R

SEC
ROL

RFLAG-RPRIM(R5)

NONE

FORCE

RADD-RPRIM(RS)

MOV

RDBF-RPRIM(RS5)
,R3

REXT

CLR

MOV

(R5) +,R4

BIS

(R5) ,R3

SDDRCP

BCS

REXT1

408

CLR

REXT1:

MOV

RPCNT-RPRIM(R5)

(SP) +,R3

RETURN

FORCE

R3
R5

ACTIVE

ADDRESS

RECEIVE

ADDRESS

'RPRIM'

SYNC

BACK

LAST

COUNT

CCB

MARK
IN

NON

HEADER

BUFFER

CCB ADDRESS
UP ADDITIONAL STATUS

POST
;;

GET

SET

RECEIVE COMPLETION
ADDRESS

OF RECEIVE DATA BUFFER
RECEIVE BUFFER
|
BUFFER AVAILABLE TURN OFF RECEI
VER

;;

NE CLEAR RECEIVE ACTIVE

RESET

PARTIAL

ENABLE

;;

RESTORE

RETURN

REF

COUNT

RECEIVER
R3
TO

INTERRUPTS

RESYNC
|

SYSTEM

LABEL

RESYNC

DAT

BUFFER

CLEAR

FLAGS

CLR

RPCNT-RFLAG(RS)

CLEAR

RECEIVE

;;

RESET

FARTIAL

#CS.RSN,RSTAT-RFLAG (RS)
;i
#RINIT, (R3)
ENABLE
REXTI
7
FINISH
LSB

TOTAL

DLC

PRIMARY

PICK

- (R5S)

.DSABL

CHAR

#RCVEN, - (R3)

SET

FOR

CLR

BIS

REMAINING

BIT

BIC

BIS

SET

GET

#RXINT,- (R3)

CSR FOR EXIT
COMMON EXIT
GET GOOD STATUS

BUFSET

BNE

BIS

TAKE

RDBF-RSTAT(R,R3
5)

CALL

;;

CALL

REXT@:

SET

END OF MESSAGE

INCLUDE

; ;
;:

MOV

REXT:

FLAG

;;
. PUT

INC

L W
—~ 2
W\ 4y

CCB

;7
IF MI, YES - CRC IS VALID
#CS.ERR+CS.DCR,R3 ;;
ELSE SET CRC ERROR STATUS
31$
;7 GO RETURN BUFFER

MOV

PRIMARY

WORD
ACTIVE

INDICATE
RECEIVER
IN

FOR

COUNT

CCMMON

RESYNC

CODE

RESYNC

;
;

**-SDPVTI-DPV11l

TRANSMIT

INTERRUPT

SERVICE

THIS ROUTINE IS ENTERED ON A TRANSMITTER INTERRRUPT VIA‘

A
;
;

;

‘
'JSR R5,DPVTI'

DEVICE

WITH RS

CONTAINING

LINE TABLE OFFSET
BY

THE

ADDRESS

INPUTS:

;

R5 = ADDRESS OF DEVICE LINE TABLE +

;

STACK

CONTAINS:

;o
:
:
;

@ (SP)
2(SP)
4(SP)
6 (SP)

=
=
=
=

;

OF THE

'TCSR'.

INTERRUPTED
INTERRUPTED
INTERRUPTED
INTERRUPTED

'TCSR'

RS
BIAS
PC
PS

OUTPUTS:

;

ETC.

SDPVTI::

.ENABL

LSB

MOV
MOV
TST
BMI
DEC
BEQ

R4,-(SP)
:::
(RS) +, R4
;;:
(R4) +
:::;
10$
;;;
;;;
TCNT-TCSR-2(R5)
20S
;:;

.IF DF

MS$$SMGE

MOV

KISAR6,- (SP)

;;;

SAVE

MOV

(R5) +,KISAR6

:::

MAP TO

@ (R5)+, (R4)

;;;

OUTPUT A CHARACTER

(SP)+,KISAR6

;::

RESTORE PREVIOUS MAPPING

- (R5)
(SP)+,R4

;::

.IFTF
MOVB

SAVE R4
|
GET TRANSMITTER CSR ADDRESS
TEST FOR UNDEZRUN
IF MI, UNDERRUN - WAIT FOR TIMEOUT
DECREMENT COUNT
IF

EQ,

BYTE COUNT RUNOUT

CURRENT MAPPING
DATA BUFFER

JIFT

MOV
LIFTF

INC

MOV

;;;

UPDATE BUFFER ADDRESS

RESTORE R4

SINTXT

TRANSMITTER

UNDERRUN

DISABLE TRANSMITTER INTERRUPTS AND WAIT FOR A TIMEOUT

D-18

10s:

BISB

#TSOM/4008,1(R4)

MOV

; i;
C L EAR

UNDERRUN BIT

;:;

SET STATE TO DISABLE TRANSMITTER-

#TUNST, TSTAT-TCSR -2(R 5)

BYTE

COUNT

RUNOUT

TRANSMIT

STATE

PROCESSING

ROUTINES:

ADDRESS
ADDRESS

TRANSMITTER CSR
THREAD WORD CELL

OUTPUT

209 :

ADD

#TPRI-TCSR-2,R5

;;;

POINT TO PRIORITY DATA

BIC

#TXINT,- (R4)

MOV

i7:;

CLEAR

(SP)+,R4

ii;

RESTORE

SINTSX

INTERRUPT

;SAVE WITH

ENABLE

'SINTSV'

STACK

HAPPY

BUT NOT

. IFT
MOV

KISAR6,-(SP)

i i

MOV

R3,-(SP)

MOV

TCSR-TSTAT(R,R3
5)

H ;

SAVE

CURRENT

SAVE

MAPPING

@ (R5) +

.DSABL

LSB

GET

ADDITIONAL

TRANSMITTER

DISPATCH

**-DPASX-ASSIGN

THIS

ENTERED VIA THE
TRANSMISSION.

TRANSMIT

CSR

PROCESSING

ADDRESS

ROUTINE

QUEUE

ROUTINE
A

CCB

IS
FOR

BUFFER

MATRIX

SWITCH

INPUTS:

ADDRESS

CCB

ADDRESS

DEVICE

TRANSMIT
LINE

TABLE

OUTPUTS:
IF

THE

TRANSMITTER
IS

INITIATED;

OTHERWISE,

THE

REGISTERS

R3,

END

IDLE,
THE

SECONDARY

TRANSMISSION

CCB

(OR

CHAIN.

MODIFIED:

R4,

AND

WS We Wg Wy Wy WMs TMy W s g WA WE M We We Wy wa wmgy W ¥

;;

CALLR

"TMe

. IFTF

D-19

CHAIN)

IS
IS

QUEUED

BIC

ADD

GET TRANSMITTER CSR ADDRESS

WN§

,R3 )
TCSR(RS5
$TXINT, (R3)
RS
#TPRIM,

DISABLE TRANSMITTER INTERRUPTS
POINT TO PRIMARY CELL

MOV

DPASX:

IFT

CURRENT MAPPING

KISARG6,-(SP)

MOV

SAVE

R3,-(SP)
(RS) +

;
;

SAVE R3
PRIMARY ASSIGNED ?

$TXACT,(R3)
STSTR

; TRANSMITTER ACTIVE ?
; IF EQ, NO - START IMMEDIATELY

.IFTF
MOV

TST
BNE

CALL
BIT
BEQ

MOV

108S:

MOV

20S:

MOV

#STSTR,~ (RS)

: IF NE, YES - QUEUE TO SECONDARY CHAIN
|
: SET UP PRIMARY
SET STATE FOR STARTUP

;

WAITI

;

R4,-(SP)

;

WAIT FOR INTERRUPT

SAVE POINTER TO FIRST CCB

R5,R4
(R4) ,R5
20%

COPY POINTER TO CCB
GET NEXT CCB
IF NE, KEEP GOING

MOV

(3P) +, (R4)

:
;
;

TEXT?2

FINISH

MOV

BNE

LINK NEW CCB CHAIN TO LAST CCB
IN

COMMON

CODE

** _STSTR-STARTUP

STATE

PROCESSING

MWE

10
TBSET

STSTR:

BIS
BIS

-4

**-STCTS-WAIT

FOR CLEAR TO SEND STATE PROCESSING

wmE

Yes

MOvVB

; ASSERT REQUEST TO SEND
#RTS,-4(R3)
ENABLE TRANSMITTER
;
(R3)
BTXENA,
RS) ; START TIMER
(R5)
, TIME-TTHRD(
TIMS-TTHRD

STCTS:

BIT
BNE
MOV
MOV
MOV

;
;
;
;
;

IS CLEAR TO SEND UP ?
IF NE, YES - START SYNC TRAIN
SET STATE FOR CTS
SET ADDRESS OF PAD BUFFER
SET TSOM, CLEAR TEOM
FINISH IN COMMON CODE

**_STSYN-SYNC

TRAIN REQUIRED STATE PROCESSING

$CTS,-4(R3)
STSYN
#STCTS, - (R5)
# SPADB,R4
#TSOM,- (SP)
TEXT1

STSYN:

MOV

#STDAT, - (RS)

;

SET STATE

D-20

FOR DATA

¥SSYNB, R4
#TSOM,-(SP)

;

SET ADDRESS

;

SET

TEXT@

;

FINISH

TSOM,
IN

SYNC

CLEAR

BUFFER

TEOM

COMMON

CODE

**_-STCRC-SEND

CRC

STATE

PRCCESSING

WMy

TMe

MOV

. ENABL
BIS

SEND

CRC

POST

COMPLETION

TPOST

BNE

19$

MOV

BIT

#STDA
- T,
(R5)
#CF.SYN,C.FLG-C.

mit s My W

#TEOM,2(R3)

CALL

BEQ

205

;

MOV

#STSYN, (RS)

208$

;

ELSE

;

WAIT FOR CRC TO BE SENT

NOTHING

ASSUME

UF(R4)

;

EQ,

AND

SET

SEND

STATE

ARE

SYNC'S

CHANGE

wms

#STID
- (R5)
L,

#¥TXENA, (R3)

NE,

SET

STATE

Yes

MOV

BIC

SHUT

DOWN

SEND

NEXT
SYNC'S

REQUIRED

LEAVE ASSUMED

STATE

SYNC'S

SEND

CCB

IDLE

TRANSMITTER

STCRC:

LSB

FOR

WAITI:

MOV

#1,TCNT-TSTAT(RS5)

MOVB

TIMS-T
(RS5) ,TIME-TS
STA
TAT(RS)
T

TEXT2

**-STIDL-IDLE

STIDL:

STATE

;

WAIT

FOR

ONE
;

;

FINISH

;

DROP

REQUEST

TIMER

INTERRUPT
START

COMMON

TIMER

CODE

PROCESSING

BIC

$RTS,-4 (R3)

TST

- (R5)

38$:

;

TIME-TSTAT(RS)

TEXT?3

.DSABL

LSB

;

CLEAR

;

FINISH

RUN

STATE

SEND

IN COMMON

CODE

CLRB
BR

**-TUNST-TRANSMIT

DATA

UNDER

INTERRUPT

ALL

TRANSMIT

BUFFERS

HIGHER

LEVEL

RETURN

TUNST:

ADD

#-TTHRD, RS

CLRB

(R5)

; ;sTIMEOUT

CALL

DPTIM

MOV

#STIDL,TSEC-TSTAT (R5)

EXPECTS

DDM

; sRESET TIMER
; ;FAKE

TEXT3

¥
-

D-21

;SET
; TAKE

LINE

TIMEOUT

STATE

COMMON

IDLE
EXIT

TABLE

POINTER

RETURN

BUFFERS

**-STDAT-DATA

STATE

PROCESSING

STDAT:

MOV

(R5) ,R4
¥
#C.FLG-C.STS,
(R5

GET

TST

(R4)
+

LAST

BPL

108

ADD

190$:

TPOST

ADDRESS

UPDATE

#STDAT
- (RS)
,

POST

ASSUME

BIT

#CF.EOM,C.FLG-C. B UF(R4)

209

’

MOV

#STCRC, (R5)

CLR

- (5P)

’

FLAGS

WORD

FROM

THREAD

POINTER

THIS

CCB

(BIT

SET)

SET

CCB

COMPLETION
DATA

;

EQ,

SEND
NO

AND

CONTINUES

CRC

FOLLOWING

THIS

LEAVE

ASSUMED

STATE
TO

ELSE

CHANGE

STATE

FOR

CLEAR

TSOM,

CLEAR

TEOM

CRC

THREAD

BUFFER

PL,

BEQ

**_TEXTO-COMMON

CALL

**-TEXT1-

EXIT

ROUTINES

**_TEXT2**-TEXT3i

TMy

;

MOV

205

hod

TEXTO:

MOVB

TEXT1:

TIMS-TSTAT
, TIME-TSTAT(
(RS)
R5)

ADD

#TCSR-TSTAT+2,R5

POINT

START

;

CURRENT

TIMER

BUFFER

CELL

cIFT
MOV

(R&4)+, (R5) +

CCPY

RELOCATI
N

+
(R4)

SKIP

OVER

MOV

(R4)+, (R5) +

COPY

MOV

VIRTUAL

(R4)
, (RS)

BIAS

. IFF
TST

RELOCATION

BIAS

.IFTF

AND

THE

ADDRESS

BYTE

COUNT

.IFT
MOV

-4 (R5) ,KISARS

MAP

DATA

BUFFER

BIS

(SP)+,2(R3)
RTXINT, (R3)

TEXT3:

MQV

(SP)+,R3

MOV

TEXT2:

BUILD

CHARACTER

UPDATE

VIRTUAL

OUTPUT

CHARACTER

ENABLE

TRANSMITTER

RESTORE

LIFT

D-22

OUTPUT

ADDRESS

-2 (R5)

@-2(R5)
, (5P)

INC

BISH

.IFTF

AND

FLAGS

INTERRUPTS

CCB

BUFFER
SENT

MOV

(SP)+,KISARH

;

RESTOREkPREVIOUS‘MAEPING

. ENDC

SEC

;

SET

RETURN

;

RETURN

**_DPSTR-DEVICE

START-UP

THIS

CALLED

ROUTINE

DPSTR:

20%:

DEVICE.

R4,-(SP)

SAVE

RDBF (R5) ,R3

;

GET

MOV
TST

#SSYNC+INPRM
(R3)
,
-(R3)
;i

POINT

RECEIVER

ADD

#RSTAT,RS

;

POINT

CALL

STATUS

BUFSET

;

ASSIGN

BCS

209

;

CLR

A PRIMARY CCB (AND
GO TO TRANSMITTER

-2 (R5)

;

CLEAR

MOV

#RINIT, (R3)

MOV

;

INITIALIZE

#TINIT,4 (R3)

;

TURN

MOVB

DPVCH+3-RPRIM(
, TIMS-RPRIM(RS
RS5)
)

BIT

#1,DPVCH-RPRIM(R5);
-

BIT
BNE
BIS

THE

COMPLETION

CALLER

MOV

BNE

MOV

;

THE

CALLING

RECEIVER

SET

INITIAL

THE

HALF

BUFFER

ADDRESS

PARAMETERS
CSR

WORD

FLAGS

BUFFER)

WORD

RECEIVER

TRANSMITTER
;SET

DDM

TIME

INTERVAL

DUPLEX

30$

#TINIT,4(R3)

;

INDICATE

CCB

DATA

YES,

DONT

FULL

FORCE

FD MODE

DUPLEX

#CH.MDT,DPVCH+2-RPRIM(R5)
;IS THIS A MULTIPOINT SLAVE?
308
; YES - DO NOT SET REQUEST TO SEND
#RTS, (R3)
; ASSERT REQUEST TO SEND FOR FULL DUPLEX

(SP) +,R4

;

RESTORE THE

CALLING

CLC

;

CLEAR

SYNCHRONOUS

RETURN

;

RETURN

C-BIT

CCB
COMPLETION

**-DPSTP-STOP

DEVICE

RETURN

OUTSTANDING

BUFFERS

AND

CLEAR

TIMERS

ACTIVATE

ASYNCHRONOUS

MOV

BIC

30$:

C-BIT

DPSTP:

10S:

MOV

R4,-(SP)

;

SAVE

MOV

RDBF (RS5) ,R3

;

GET

THE

CALLING

MOV

#DTR,-(R3)

;

DISABLE

RECEIVER

CLR

4 (R3)

;

DISABLE

TRANSMITTER

RECEIVE

MOV

RPRIM(RS) ,R4

;

GET

BEQ

10$

;

CALL
CLR

SRDBRT

;

RETURN

RPRIM(R5S)

;

CLEAR

PRIMARY

EQ,

BUFFER
-

ADDRESS

LEAVE

RECEIVER

CCB

NONE

ASSIGNED
BUFFER TO THE

PRIMARY

MOV

LINE(R5) ,R4

;

SRDBQP

;

SET SYSTEM LINE
REMOVE ANY WAIT

MOV

(SP)+,R4

;

RESTORE

TST

TPRIM(R5)

;

BNE

20%

YES,

THE

ANYTHING

SAVE

POOL

POINTER

CALL

D-23

CCB

DATA

NUMBER

REQUESTS

SAVED

CCB

ACTIVE

FOR

TIMEOUT

DTR

SEC
RETURN

R4 ,KICCB(RS)

NO,

SO GIVE
EXIT

THE

MOV

30%

AND

20S:
30S$:

$SDDCCP

SAVE

INDICATE

CALL

AND

CCB

THE

FOR

COMPLETION

NOW

LATER

ASYNC

EXIT

. END

D-24

'GLOSSARY
Asynchronous Transmission

Transmission in which time intervals betwe
en transmitted characters may be of unequ
al length.
Transmission is controlled by start and
stop elements at the beginning and end
of
each
chara
cter.
Also called start-stop transmission.
|

BDIN

Data Input on the LSI-II bus.
BDOUT
Data Output on the LSI-II bus.
BIAKI

Interrupt Acknowledge.

Bit-Stuff Protocol
~
Zero insertion by the transmitter after
any succession of five continuous ones
designed for bitoriented protocols such as IBM’s Synch
ronous Data Link Control (SDLC).
Bits per Second (b/s)

Bit transfer rate per unit of time.

BIRQ

Interrupt Request priority level for LSI-11

bus.

BRPLY

LSI-11 Bus Reply. BRPLY is asserted

in response to BDIN or BDOUT.

BSYNC

Synchronize — asserted by the bus maste
r device to indicate that it has placed
an address on the
bus.
Buffer

Storage device used to compensate for
a difference in the rate of data flow when
transmitting
data from one device to another.
BWTBT
Write Byte.

CCITT
Comite Consultatif Internationale de
Teleg

raphie et Telephonie — An internatio

committee that sets international comm

unications usage standards.

nal consultative

Control and Status Registers (CSRs)

Communication of control and status infor

mation is accomplished through these regist

ers.

Cyclic Redundancy Check (CRCQ)
An error detection scheme in which the check character is generated by taking the remainder
after dividing all the serialized bits in a block of data by a predetermined binary number.
Data Link Escape (DLE)
A control character used exclusively to provide supplementary line control signals (control character sequences or DLE sequences). These are 2-character sequences where the first character is
DLE. The second character varies according to the function desired and the code used.

Data-Phone DIGITAL Service (DDS)
|
A communicaitons service of the Bell System in which data is transmitted in digital rather than
analog form, thus eliminating the need for modems.
DIGITAL Data Communications Protocol (DDCMP)
DIGITAL’s standard communications protocol for character-oriented protocol.
Direct Memory Access (DMA)
Permits 1/O transfer directly into or out of memory without passing through the processor’s general registers.
Electronic Industries Association (EIA)
A standards organization specializing in the electrical and functional characteristics of interface
equipment.
Full-Duplex (FDX)
|
Simultaneous 2-way independent transmission in both directions.

Field-Replaceable Unit (FRU)
- Refers to a faulty unit not to be repaired in the field. Umt is replaced with a good unit and faulty
unit is returned to predetermined location for repair.
Half-Duplex (HDX)

An alternate, one-way-at-a-time independent transmission.
LARS

Field Service Labor Activity Reporting System.
Non-Processor Request (NPR)

Direct memory access-type transfers, (see DMA).

Protocol
|
A formal set of conventions governing the format and relative timing of message exchange between two communicating processes.

RS-232-C
EIA standard single-ended interface levels to modem.

KS-422-A
EIA standard differential interface levels to modem.
RS-423-A
EIA standard single-ended interface levels to modem.

G-2

RS-449

EIA standard connections for RS-422-A and RS-423-A to modem interface.
Synchronous Transmission
Transmission in which the data characters and bits are transmitted at a fixed
rate with the transmitter and receiver synchronized.
V.35

(CCITT Standard) — Differential current mode-type signal interface for high-spee

d modems.

DPV11 Serial Synchronous

Reader’'s Comments

Interface User Guide
EK-DPV11-UG-001

Your comments and suggestions will help us in our continuous effort to improve the quality and useful-

ness of our publications.

What is your general reaction to this manual?
well written, etc?

Is it easy to use?

In your judgement is it complete. accurate. well organized,

What features are most useful?

What faults or errors have you found in the manual?

Does this manual satisfy the need you think it was intended to satisfy?
Does it satisfy your needs?

Why?

Please send me the current copy of the Technical Documentation Catalog. which contains information

on the remainder of DIGITAL's technical documentation.

Name
Title

Company

Department

Additional copies of this document are available from:

Digital Equipment Corporation
Accessories and Supplies Group

Street
~ City

Cotton Road
Nashua, NH 03060

Attention Documentation Products

Telephone 1-800-258-1710

Order No. EK-DPV11-UG

State/Country

Zip

dlilg[tal

Lkl

mmmwmmmmmmwmwmwWWMMWM*FO'C’ Heremmmmmmmmmmmmwmmmmmmw

No Postage
Necessary
if Mailed in the

United States

FIRST CLASS

PERMIT NO

MERRIMACK

POSTAGE WILL BE PAID BY ADDRESSEE

Digital Equipment Corporation

Educational Services Development & Publishing

Continental Blvd. (MK1/2M26)
Merrimack, N.H. 03054

‘

BUSINESS REPLY MAIL