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Document:	DPV11 Serial Synchronous Interface Technical Manual
Order Number:	EK-DPV11-TM
Revision:	002
Pages:	114
Original Filename:

OCR Text

DPV11 serial synchronous
interface technical manual

dlilgliltiall |

EK-DPV11-TM-002

DPV11 serial synchronous
‘interface technical i anual|

digital equipment corporation ® merrimack, new hampshire

1st Edition, July 1980
2nd Printing (Rev), November 1980

The material in this manual is for informational purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsi-

bility for any errors which may appear in this manual.

Printed in U.S.A.

0 computerized
This document was set on DIGITAL’s DECset-800i}
typesetting system.

The following are trademarks of Digital Equipment

Corporation, Maynard, Massachusetts:
DIGITAL

DECsystem-10

MASSBUS

DEC

DECSYSTEM-20

OMNIBUS

PDP

DIBOL

OS/8

DECUS
UNIBUS
DECLAB

EduSystem
VAX
VMS

RSTS
RSX
IAS
MINC-11

CONTENTS
Page

—

CHAPTER 1

CHAPTER 2

INTRODUCTION
SCOPE........rrreveeennn. sihessibritiniosirasesers eeatiaeeb i s iRV GaTebueseesesssnssnanasesresessnesssarnedsarons
.1-1
DPV11 GENERAL DESCRIPTION veesrdrsitedenisrisersTeisisassrrassarsssnsrrennnsensnsarassssasiane . 1-1
DPV11 OPERATION .................. Censievsisibivbianbettnbiesusidisisssennnseeensesenssresssrasessenssanteion 1-2
DPV11 FEATURES ... idrieeiversransertaenecosasssnessrnnnssares v 122
GENERAL SPECIFICATIONS ..........trettetteeeeerteareeeesereneresssssranssssanssseeesseeeneeeeenes 192
Environmental SpecifiCations ...........ccccvviiiiiiiiiiiiiiceecceecee
e 1-2
Electrical Specifications........ Cieeibeertanissebestiniainne
deiib b aba crerararsessnanaassessnnneresnsans 1-3
Performance Parameters.........coouvueiiriiiiinninniiiiiicieeee
et eeeeeeeeeeaeeee
s e e e s 1-3
DPV11 CONFIGURATIONS......... fenesuedseviisinsnns eeeerereeerrennraraeeseeeeressesnrennnnreseseeseases
123
EIA STANDARDS OVERVIEW ...ttt eeeeeeeeeeeseseeeeenaaeaeeens 1-3
INSTALLATION
INTRODUCTION ..o reeniin terenrnnrrranrarrenrraterereeeeeseesseeesnnsseeses
201
UNPACKING AND INSPECTION................... F43ieisiieresnrrsrannectarsasensessnnnsnnnnresnrtns 2-1

INSTALLATION ............................................. deinivheesstteeeeeeernrnrarnerreeeeeessessennnseseenes 270
Verification of Hardware Operatmn......,.....‘;.....m..v........... .................................... 2-7
Connection to External Equipment/Link Testmg
ST ks evbrneneacsesssssnasaessssnnnrreni .. 2-8
TEST CONNECGCTORS ...ttt
ceerre et eeseeee et e e eess e
eeeeeseaseesnnnaeeas 2-8

[ oo

u&izww

WWWLWLWWWWWWWW
LapBRLLLWLWLWN-

REGISTER DESCRIPTIQNS AND PROGRAMMING INFORMATION
INTRODUCGTION ...ttt
eeseast e eeessra e e s e eaeseeesssesnasesessesaneeeeas 3-1

DPV11 REGISTERS AND DEVICE ADDRESSESW ,,,,,edeerreseiesesnnsenseresssrenesie 3-1

REGISTER BIT ASSIGNMENTS............... Gaseusiserbeaieiaeiisntasssennsunnsannressresssssssariie 3-2
Receive Control and Status Register (RXCSR) ........dvieriverseesuraseaserannenee vevrereene 372
Receive Data and Status Register(RDSR) ......cccoivevvvieeeenn... rreeeeeeeeeeeraranna .32
Parameter Control Sync/Address Register (PCSAR)
.............................. vevinees 32
Parameter Control and Character Length Register (PCSCR) ........................ 3-2
Transmit Data and Status Register (TDSR)............ rrvvesieesosasienseenenisnasanisnnasaiei 32
DATA TRANSFEERS ...ttt
e e e e e e e e e e e st eeeeeeeesneneeeas 3-19
ReCeive Data .....ccooeeeeiiieeeeeeeeeeeee
ereeeirerenrrreneeeeesennnen. 3=19
Transmit Data....................... caevhabesesiirbareebersarnaiionnsbis sedeedessatissaeannnsenanssssensssanes3-20
INTERRUPT VECTORS ..., SRSPSERAL JE N SP eee———————— 3-21

CONTENTS (Cont)
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CHAPTER 4
4.1

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R
R

4.2
4.2.1
4 2.1.
1.
1.
1.
1.
1
1.
1.
1.
d.
4.2,2
4.2.2.1
4.2.2.2
4.3

AR EE R

EEE RS

RS R

R R E

R R

RN »

Clock
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1 §i| TP eiceosenboiebuasseseeicesssesherrensnerasnnncanntooannsoes
4-3

EIA Lebel Converters-»vw»«uw»wu«-.»wnfl 0000000000000000 LA R A R RS R R R R R R R R R R R R R R AR R R R S R R RN R R R R R E RN N 4.3
Charge Pump............. ceessesaesiresiossaserresassisansaes sbevelibeseanersenssiencaroncarsrsrseranios 4-3
General 10 Operational
ional Overvi
i
‘
|
Overview ....................
Sseeabiiesinidiiiiennes
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Recelve
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Operation .......e ebievusteenresitsriiautieetnnsterirrensesrevesbvesusnteaessecencncennnnsans 4-5

DETAILED DESCRIPTIONttfitltdfifiiibhfldunhw fififififififififififififififififififififififififififi IR E R E N N NN 2 LR R E SR R R E R R R R E R R R R R R R RN 5
BusT
US ITansSCeIVerS...ccvviennnnnnes
v
teeenereesensannnneeeanteeeeneeeeatnnnnnocnntnnnnnnecencecaserasannnnannnnanns 4-5

B W
—

Add ress Selecti
e cctlon [ EZ SRR RSSEEESEESEEEEENRS (I E R E RS RN SR.
ERERENN] ‘*&‘Ufiffl QQQQQQQQQQQ
o Sreeene ‘flflfid'liowhii| nnnnnnn4~ 5

Addrcss DeCOde [ZE
AR R EEEREE RS SRR RS SRR R RS R R R RS RS R SRR ERE] EREDEERENY Nw«flwwwdwtwwcfiq«n wwwwwwwwwwwwwww LA R R R E 3 ' 6
Bus Data TranSferS e I I T I ITrTTTTTTTT TTITTIETITTNTTYTYTYFIT'T'IT''Tm''m B EEB AR VOB R R R N AR I RE RS R RN -y hw ' 6
VLYo
00 gl € 13113 £- 15 (0] | PUUU RN
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Logi I FE R R R E' R R R R R R E R R R R R R R R R R R R R R R R RN R R R RN R RNi E RN N ) SR
rlte C ontro1 Oglc
I mmMmM T I T T YT Tty N4“6

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eco e’tifiIUIQO'Iwt&v!.ttwi"wtfiiflfi fififififififififi fi‘!‘fi*flfl*&oi‘fid'flW‘flh.'v*fl ''''''''''''''''''''''''''

USYNRT Contr()l FERERBERERD
B ETRROE RS REERBERERANSTEFRER
DR R S LA R RSR R R RN R E R R R R AR R R RN I ZEEEEE
R RN NS EREERE RN I ;

USYNRT RXCSR and PCSCR ttttttt [EEERERE] [ R A R R R R
R R
R R R S R R R SR 2R 2] ' ;
o
|
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4USYNRT iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii 10

Receive Control and Status Re ister ..
4-10
‘Parameter Control and Character Length Reglstcr
SO
|
4-10
Interrupt Loglc.,........,,.........,.,... ....... eerreaannssanns reeeveeaanes eveseeatnsesanentconstiontosaansoccnn 4-10
Data Set Change CirCuit.... ..o
e 4-11
CIOCk ClrcultI E R A E RS SRR R R RNSN] BEE RN IEZE RS TR EENEEE S RS RS TS SN EEEE RN E R NN [ E R R SR EEEE RS AR SR R R EEREESEE RS RS R R REE SRR RS EE RN N NN ] ' l l
USYNRT Tlmlng wwwwwwwwww BREBPEBRE
RS DRSS BRI EBR
ERE DB RARREEBEBT EEREN"i!#i‘flt ttttttttttttttttttttttttttttttt l 12
EIA Reccluers FRBEERBESRD
R RN A BB R E BB RSN R RN SRR ANi.fitt&flt& LR R te«um«wu [ ZEE 2R R R RS EEE SN EEE SRR RS ] 2 R RSRN l 12
EIA Dnvers -wwwu:.wmcmiuuawuwwwwwyuuuwo%uuc«nmuomrwnmuwu«uwu*t‘uwuuqunu"««omuu lllll (I EE R R R Y] [ ZEEEETEE
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4.3.8
4.3.9
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4.3.1

INTRODUCIION iiiiii IR R R R EEEE RN RN ] 000&4&1\‘&’1*‘07‘W*&#fifi*.&td*ifil'fli\llé.ui‘o*»'il'Q&ifl'b‘IOU‘.““W& iiiiiiiiiiiiiiii 4“1
FUNCTIONAL DESCRIPTION wwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwww CERERE A BB DR B R DN - » 4-1
LOZIC DESCIIPLION .....eevviireeiiiiieiiiiieitiieririreertte
et reeeeeeeeeeeeaeeeeeeeesseeeseesssssnnsssssnnssees 4-1
B uS Iranscelvers
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RS EE N R E R R R R R R R R E RN EEREE RN RN NS 4.1
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USYNRT anand Bidi
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uuuuuuuuuuuuuuuuuuuuu
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Receive Control an
tatus Register
4-1
Transmit Control and Status Reglster .....eeeteectenienaneenen treeesaseeenneeeeececeasesens 4-1
Interrupt Logxc ........................... tecnniiasensiesonnianerneses cerenssasessesensescancessnnacaans 4-3
D ata Set det Ch Change Logi
'
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:
’
LogIC .......cocccervivniininnnne.ieieeesViseaststantitiasneseneraanstassnnsrass
4-3

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CHAPTER §

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e e T Bl ATERAE RBRBA L T A Bed ok Rk Bed N Nt Ml B RB SRR
D RN SR CEEEE
GO RN HEEEAES B EAEERBEERRER
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CORRECTIVE MAINTENANCE
5-2
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Mode

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B ESEA R

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meback Conncctors#'fiQQO*QOQfl‘*##‘fl‘fl‘lfifl"flllflIlfiilhil‘idndOOOOG‘&QOO&.'QOG‘D& QQQQQQQQQQQQQQQQQQQQQQQQQQQQQ 5 2
Dlag nostics &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& [ E R EEENRSER [ EEE N E R R EEE R ENEREESEEEE
NS ER] (AR R E R R RS SRR E RS E R ER NN 5-2
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tttttttttttttttttttttttttttttttttttttttttttttttttttttttttttt

DEC/XI l CXDP . MOdule 00000000 [ ESEE RN TR B N [ E R R E R R A R BN S R R R
Data Communications Link Test CVCLH* (DCLT)
-

[

5-3

R R R R R SRR AR SRR E R R R E R R R RN S I
5-4

E S EE R

E RS

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SRR E

SRR SN

LN NN

CONTENTS (Cont)
Page
APPENDIX A

DIAGNOSTIC SUPERVISOR SUMMARY

INTRODUCTION ...t
e et e e s st e e e e eaeaeeessnneeeenns A-1
VERSIONS OF THE DIAGNOSTIC SUPERVISOR..........cooeovvieiieeeeseeeennnn. A-1
LOADING AND RUNNING A SUPERVISOR DIAGNOSTIC ..................... A-1
SUPERVISOR COMMANDS....... civeveeekicibvessesenne Vibieeiivnaeienseaiiisannnasessersesansnsassne A-3
Command SWItCRES.......cccviiiiiiiiiiiiiiieciece ets e e eaes A-4
Control /Escape Characters Supported ..................... rrrreeeennrraeeeessnnaneessennneeeees A=l
THE SETUP UTILITY ...,veiesiiees eeeeer——————— e A-5

APPENDIX B

USYNRT DESCRIPTION

APPENDIX C

IC DESCRIPTIONS

A2
A3
A4
A4l

C.1
C.2
C3

C.5
C.6
C.7
C.8
C. 9

GENERAL ... ettt
e et e et e e e aeeeeseaeeseseesesnes C-1
DCOO3 INTERRUPT CHIP ...ttt
e e e e e C-1
DCO004 PROTOQCOL CHIP ...ttt
e e e e e - C-3
DCO005 BUS TRANSCEIVER CHIP........coouiiiieieeeeeeeeeceeeeeeeeeeee
e e C-3
26L.S32 QUAD DIFFERENTIAL LINE RECEIVER......................................... C-6
8640 UNIBUS RECEIVER ........ccooiiiiieiiicieeeeeeeeeeeeeeeeeeee
e robesersneanneesssraranns C-6
BBBI INAND ..ot
e e e et e s et eeeseennesenesnes C-6
9636
A DUAL LINE DRIVER .........cccoovviiiiiiiieeeeene. eeteeeereteeeeeea
e ran——aaaeenan C-6
9638 DUAL DIFFERENTIAL LINE DRIVER ................................................... C-6

APPENDIX D

PROGRAMMING EXAMPLES

GLOSSARY

ILLUSTRATIONS
Figure No.
1-1
2-1

2-2
2-3
2-4
3-1
3-2
3-3
3-4
3-5

3-6
4-1
4-2
4-3
4-4
4-5
A-1

Title

Page

DPV11 System.................... crvesrisraerens cerressaiins ivresesds ceeisisisteseisirtesesveiitnesnanansansrssererranas 1-1
DPV11 Jumper Locations ................... RS R
P NS 1 P SRR AT R PSR SUPRUNORUPOPOOO .
H3259 Turn-Around Test Connector,..,.. ............. ATATAT
I Cideiiiaiiadsiiisiananannnesensasessssaine 2-8
RS-423-A with H3259 Test Connector.............. PRI Ciaritirisniaeseaiisasensuren ceeerrrenans 2-10
H3260 On-Board Test CONNECLOr............covviiiiiiiiiiiiiiiiiieieiecce eeeeeeeeeeaeeeeas 2-11
DPV11 Register Configurations and Bit Assignments...........cccceeveveiveveveeeeeeeeeennnn. 3-3
Receive Control and Status Register (RXCSR) Format ..........ccooeevvvevveeeeeeeeeennnnn. 3-4
Receive Data and Status Register (RDSR) Format.........ooooivvieiioiiieieoieeeeieeeeeeeeeennns 3-8
Parameter Control Sync/Address Register (PCSAR) FOrmat.......o.oovveoovvoo 3-11
Parameter Control and Character Length Register
(PCSCR) FOIMAL.......oiiiiieiiieeeeieeeieeceteceec
et et eetee e aeeeeneeeeseeeseaessnessneeenees 3-13
Transmit Data and Status Register (TDSR) Format......ccccvveevveeeveoeeeeeeeeeeecennnnnns. 317
DPV11 BIOCK DIaBrami.......coiciiiiiiiiiiiiieeeeccctieeeeeec ettt e s eeaeeee e e e e e e enennaeas 4-2
Simplified Functional Diagram...........ccccccovveercrnnnnnnn.n. ceereerarreaerraaaaaaans ceeeeereeeeenann 4-4
Register Decode................... revereeeeeeaananns ettt e e e ettt ta e et e e e e e s e
nnaratanaaaaeeeeeaanrnnns 4-8
Timing for Read Operation .............cocociiiiiricirieeecceeeecccee
e cvereeaeeeans 4-9
Timing for Write Operation .......... ChreteansrssrsesasabasitssabartEesasetteratsannsenerersestnsessrentianent 4-10
Typical XXDP+ /Diagnostic Supervisor Memory Layout..............cccccveeeuueennnne... A-2
\'4

ILLUSTRATIONS (Cont)
Figfire No.
B-1

B-2
C-1
C-2
C-3
C-4

C-5
C-6
C-7
C-8

Terminal Connection Identification Diagram
AT
£
(2112517-0-0 VATIation) ccocceeeeeieeeeiiiiiiiereeee
e ecceeeeciiiireer e e eeeeesesesssssssssnsseeeseeseens oo B-2
5025 Internal Register Bit Map (21 12517-0-0 Varlatlon),,.,;;.m,,..‘..;,. ................ vveens B-3
DCO003 Logic Symbol ........cccovviiiiiniiiieeniiienenineeeceneeeeennes e C-1
DCO004 Simplified Loglc Dxagram
verebatesabaniserbibiniobuiiarnete bbbt dritbhishrhalensrensersarsossnnnsee C4
DCO005 Simplified Logic Diagram
........ eveerrreeeens C-7
26L.S32 Terminal Connection Diagram and Terminal
|
Ry
Indentification........cccovceeeveierervennnns vienvreeens evansesiidusasieibeeteeisibrihrsivareannnarssessrasnansssanns .. C9
8640 Equivalent Logic Diagram ................ Gedainarinnmieiesivniniribriesiobthobrnnaereesensarnsnaransd >-10
8881 Pin Identification...........cccceevieeiiiiinnneeennnnnes eeereeeeern————— rrererererrrereeraaeeeneesd -10
9636A Logic Diagram and Termmal Identnflcatmn.m.driviieiioiesibiinnsensanniteciiisboniness
Co ]
9638 Logic Diagram and Terminal Identification......................... eeeernens cererernnnns C-12

TABLES

Title

Page

Configuration Sheet..........cccccovvevuennenne s
o s
SO R e e nadhannrssesasessessatsnsas O
Vector Address Selection......... crrveeeeeerrnnans eerere——————
........................ .2-5
Device Address Selection ...........cococevieeecirreenreieniininineseneresteereeseassnesenes e cees 2-6
Voltage Requirements ....................... e
...............2-7
H3259 Test Connections..................
................................................. 2-9
DPV11 Registers................ veeeansenessanssbatadopunsenengesrns
e arhebehob
s dsh ayUy iR ee o iys dip fipieanefid
el
Receive Control and Status Register (RXCSR) Blt
|
|
ASSIZINIMIEIILS .cooviriierereeeeeeeeeereeeeerseesnsraranrsreeseeeesessessessssnssssereseseesssssssssnes N
Receive Data and Status Register (RDSR) Bit Assxgnments ................................... 3-8
Parameter Control Sync/Address Register (PCSAR)
Bit ASSIZNIMENLS ...ovviiiiriiieiiiiiiieeiieeirirrrreeeeeeseriireeseeeeesssabntaeeseaessssstaeesseeessessnnnseeens 3-11
Parameter Control and Chamcter Length Register
(PCSCR) Bit ASSIZNIMENLES ...ccevvverrrrienerriererrirereriereerreererreeeereerereesereeeeeeseeeessssssens e 3-14
3-6
4-1
4-2

5-1
C-1

C-2
C-3

Transmit Data and Status Register (TDSR) Bit Assignments .........cccceeevveerineesinnen 3-17
Register Selection ....... e eetteeeeeeeeeteeenaereraaaerreaaaateeeteeeeeeaeaaaa
e haanttttaeraeaeeeeeaaartrarrrrearararees 4-9
USYNRT Register Select............ eerrrereaens vesverrannsernersrisbrasasteteiskidbioreeessaseseersrassesesas 4-9
Test Equipment Recommended............... caiseseerenanniestssiBFiFssdradedeid i ichnnanenarcenne eeeerens 5-1
DCO003 Pin/Signal Descriptions..........ccccceeiviueciiieeinuncinnn TR R L2 L OC-Z
DCO004 Pin/Signal Descriptions............ccccveu... eC-5
DCOOS Pin/Signal DeSCriptionSQ*#QU‘Ufi*bfi&&'225 KRS *& RN U*fi*@’fl“uii tAAl a2 QUQ ************************C”s

This manual was written to satisfy the needs of Field Service and Educational Service Training personnel.

It contains the following categories of information.
General description including features, specifications, and configurations
Installation
Programming

Technical Description
Maintenance

The manual also contains four appendixes which include diagnostic information, integrated circuit descriptions, and programming examples.

The DPV11 Field Maintenance Print Set (MP00919) cOntains useful additional information.

vii

1.1

SCOPE

This chapter contains mtroductary mfonnatmn about the DPVII It includes a general description,
and a brief overview of the DPV11 operation, features, general specifications,and configurations.
1.2 DPV11 GENERAL DESCRIPTION
The DPV11 is a serial synchronous line interface for connecting anLSI-11 bus to a serial synchronous
modem thatis compatible with EIA RS-232-C interface standards and EIA RS-423-A and RS-422-A
electrical standards. EIA RS-422-A compatnbzhty is provided for use in local communications only
(timing and data leads only). The DPV11 is intended for character-oriented protocols such as BISYNC,
byte count-oriented protocols such as DDCMP, or bit-oriented data communication protocols such as
SDLC. The DPV11 does not provide automatic error generating and checkmg for BISYNC.

The DPV11 consists of one double-height madule and may be cmmectcd to an EIA RS~232~C modcm
by a BC26L-25 (RS-232-C) cable.
The DPV11 is a bus request device only and must rely on the system software for service. Interrupt
control logic generates requests for the transfer of data between the DPV11 and the LSI-11 memory by
means of the LSI-11 bus. (Figure 1-1 shows the DPV11 system.)

l TELEPHONE

LSI -BUS

DPV11

LINE

MQDEM

l +

CPU

MK-1320

- Figure 1-1

DPV11 System

1-1

1.3 DPV11 OPERATION
The DPV11 is a double-buffered program interrupt interface that provides parallel-to-serial conversion
of data to be transmitted and serial-to-parallel conversinn of received data. The DPV11 can operate at
speeds up to S6K b/s.* It has five 16-bit registers which can be accessed in word or byte mode. These
registers are assigned a block of four contiguous LSI-11 bus word addresses that start on a boundary
with the low-order three bits being zeros. This block of addresses is jumper-selectable and may be
located any ,;kwwbetween 160000g and 177776g. Two of these registers share the same address. Oneis

accessed during a read from the address, the other during a write to the address. For a detailed description of each of the five registers, refer to Chapter 3. These reglsters are used for status and control
mformanon as well as data buffcrs for both the transmlttcr and recewer portxons of the
DPVII
|

1.4

DPVI] FEAT TRES

Features of the DPV11 mclude
o

Full-duplex or half«duplex 0pemtwn
| Doubw«buffered tmnsmntter and receiver

EIA RS-232-C wmpmlblllty

All EIA RS-449 Category I modem control
Partml Category 11 modem control to mclude1ncommg cafl te&t m‘“e, mmme impback
and local 100pback
- Program interrupt on tranmtmns of modem cantml sngnals

Operating speeds up to 56K b/ s (may be limited by snftware or CPU memory)
Software-selectable dlagnostlc loopback
Operation with bit-, byte count-, or chamcterwomnted protocals

Internal cyclic redundancy check (CRC) character gemmtmn and checking (not usable

with BISYNC)

Internal bit-stuff and detection with bit-oriented protocols.

Programmable sync character, sync insertion, and sync fltrlppmg ‘withbytc count-oriented
|

protocols.

Recognition of secondary station address with bit-oriented protocols.

1.5 GENERAL SPECIFICATIONS
'
This paragraph contains environmental, electrical, and performance sp@cifwatwm fm: the DPV11.
1.5.1 Environmental Specificafions
The DPV11 is designed to operate in a Class C environment as sffseclfwd by DEC Stmdard 102 (extended).

Operating Temperature
Relative Humidity

5° C (41° F) to 60° C (140° F)
- 10% to 90% with a max. wet bulb temperature of 28° C (82°
F) and a min. dew point of 2° C (36° F)

* The actual speed realized may be significantly less because of limitations imposed by the software and/or CPU memory
refresh.

The DPV]I mqmres the follmwmg mltages from the LSI~11 bus for proper operation.

412 V at 0.30 A max. (0.15 A typical)
+5Vat 1.2 A max. (092 A tymcal)

Tha mwrface maludes a ahargc pump to genemte a negative vmlm ge mqmwd to power the RSW423~A
drivers.
The DPVII prescnts 1 ac laad and 1 dc lwad to the LSMI bus

1.5..3 Performance Pammeters
Performance parameters for the DPV11 are listed as follows.

Operating Mode

| Data Format

Fuu or half«dupiax

'Synchmmus BISYNC DDCMP and SDLC

Character Size

Program-selectable (5-8 bits with character-oriented
protocols and 1-8 bits with bit-oriented protocols)

Max. Configuration

16 DPV11 modules per LSI-11 bus

Max. Distance

15 m (50 ft) for RS-232-C. 61 m (200 ft) for RS-423A/RS-422-A (Distance is directly dependent on speed,
and 200 ft is a suggested average. See RS-449 specification for details.)

Max. Serial Data Rates

56K b/s (May be less because of software and memory

refresh limitations.)

1.6 DPV11 CONFIGURATIONS
There are two DPV11 configurations, the DA and the DB.
DPV11-DA
Unbundled version consists of:
M8020 module
Module Configuration Sheet (EK-DPV11-CG)

"DPV11-DB

Bundled version consists of:
M8020 module
H3259 turn-around connector
BC26L-25 cable
DPV11 User Manual (EK-DPV11-UG)
LIB kit (ZJ314-RB)
Field Maintenance Print Set (MP00919)
Turn-around connectors, cables and documentation may be purchased separately.
1.7 EIA STANDARDS OVERVIEW (RS-449/RS-232-C)
The most common interface standard used in recent years has been the RS-232-C. However, this standard has serious limitations for use in modern data communication systems. The most critical limitations
are in speed and distance.
v

For this reason, RS-449 standard has been developed to replace RS-232-C. It maintain . degme ;f
compatibility with RS-232-C to accommodate an upward transition to
RS-449.
The most significant difference between RS-232-C and RS-449 is in the electrical characteristics of
signals used between the data communication equipment (DCE) and the data terminal equipment
(DTE). The RS-232-C standard uses only unbalanced circuits, while the RS-449 uses both balance

and unbalanced electrical circuits. The specifications for the types of electrical circuits supported y
RS-449 are contained in EIA standards RS-422-A for balanced circuits and RS-423-A for unbalanced
circuits. These new standards permit much greater transmission speed and will allow greater distance
between DTE and DCE. The maximum transmission speeds supported by RS-422-A and RS-423-A
circuits vary with cable length; the normal speed limits are 20K b/s for RS-423-A and 2M b/s for RS422-A, both at 61 m (200 feet).
swstameseTM emgoranTM
LG
Another major difference between RS-232-C and RS-449 is that additional leads are needed to support
the balanced interface circuits and some new circuit functions. Two new connectors have been specified
to accommodate these new leads. One connector is a 37-pin Cinch used in applications requiring secondary channel functions. Some of the new circuits added in RS-449 support local and remote loopback
testing, and stand-by channel selection.
"

1-4

TR2
INSTALLA TION
2.1 INTRODUCTION
This chapter provides all the information necessary for a successful installation and subsequent checkout of the DPV11. Included are instructions for unpackmg and inspection, pre-installation, msmllatwn
and vemfication of operatmn
2.2

UNPACKING AND INSPECTION

The DPV11is packaged in accordance with commercial pac:kmg practices. Rcmmre all packmg mate~
rial and verify that the following are present.

M8020 module
H3259 turn-around connector
BC26L-25 cable
DPV11 User Manual (EK~DPV1 1-UG)
LIB kit (ZJ314-RB)
Field Maintenance Print Set (MPOOQIQ)

Inspect all parts carefully for cracks, loose components or other obvious damage. Report damages or
shortages to the shipper immediately, and notify the DIGITAL representative.
o
2.3 PRE-INSTALLATION REQUIREMENTS

Table 2-1 (Configuration Shcet) pmwdes a canvemem qmck refcrence for cunfiguring ]umpers
Table 2-1

Ctmfigumtinn Sheet

(Wl«-WZ) Dmer Attenmtian Jumper
Nmmal*

Driver

Configuration

Terminal

W1 to W2

Timing

Alternate*

Option

Description

Not connected

Bypasses
~

attenuation

resistor.

Jumper must be removed for certain modems to mwmtcproperly.

(W3-W11) Interface Selection Jumpers

Input .

]

SQ/TTM _

Signals

DM (DSR)

(RXCSR-9)

Alternate*

N@rmul*

Configuration

Wwstows
Not connected

Option

;

Description

Signal quality
W7 to W6

Test mode

W10to W9

Data mode return f()r RS-422-A

*Normal configurationis typwally RS-423-A compatible. Alwmaw a::aptwn is typmafly RS-422-A mmpmzbm
2-1

Table 2-1

Configuration Sheet (Cont)

(W3-W11) Interface Selection Jumpers (Cont)
Output

Normal*
Configuration

Signals
SF/RL
(RXCSR-0)

Alternate*
Option

Description

W3 to W4

Select frequency
Remote loopback

W5toW3

Local

| WB‘w W9

Loopback

Not connected

W8 toWll1

(W12-W17) Receiver Termination Jumpers

Receiver

Normal*
Configuration

Option

Receive Data

Not connected

Wi12toW13

Alternate*

Send Timing

Not connected

W14
to W15

Receive
Timing

Not connected

W16to W17

Description

Connects termmatmg msmw for

- RS-422-A ce, pambnhty

(W18-W23) Clock Jumpers
Normal*
Configuration

Function
NULL MODEM
CLK

Alternate* |

Option

Description
Sets NULL CLK MODEM CLK

W20to W18

to 2 kHz
W21 to W18

Clock Enable

W19 to W21

W22to W23

W19 to W21

- Always ~ ifnsztall@d except for factory

| (W24-W28) Data Set Change Jumpers
Modem Signal
Name

Normal*

Configuration

Alternate*
Option

Data Mode (DSR)

W26
to W24

Not connected

Clear to Send

W26 to W25

‘Not connected

Incoming Call

W26
to W27

Not connected

W26 to W28

Not connected

Receiver Ready
(Carrier Detect)

Connectsthe DSCNG flip-flop to

the respec: ive modem statussignal
- for. tmrwnm detection.

Note W26is input to DSCN» ipflop

*Normal configuration is fiypically RS-423-A compatible. Alzt;oxé-naw option is typically RS-422-A compatible.

GND Al2
W29

W3l

All Al0

W30

W36

W33

W32

W39

W38

W37

D3
W45

Source
W46

W34

W3S

Vector Address Jumpers
D8
W43

D7
W42

D6
W4l

D5
W40

D4
W44

NOTE
Vector address to be asserted is daisy-chain jump-

ered to W46.

NOTE
Table 2-1 shows the recommended normal and altering schemes. Any deviation from these
will cause diag nostics to fail and require restrapping
for full testing and verification. It is recommended
that customer configurations that vary from this
scheme not be contractually wpported

Prior to installing the DPV11, perform the following tasks.
1.

Verify that the following modem interface wire~wrap jumpers are installed (Figure 2-1).
W26 to W25 to W24 to W28 to W27
W22 to W23 and W19 to W21
W18 to W20
W5 to Wé
W3 to W4
W8 to W9
W1 to W2

Thisis the shlppcd configumtwn Some of thesejumpers may be changed when the moduleis
connected to external equipment for a specific application. The RS-423-A NULL MODEM
CLKis set to 2 kHz as shipped.

Based on the LSI-11 bus floating vector scheme or user requirements, determine the vector

address for the specific DPV11 module being installed and configure W40 through W46
accordingly (Table 2-2). The floating vector ranki

Based on the LSI-11 bus floatmg address scheme or user requirements, determine the device

address range for the DPV11module and configure W30 thmugh W39 accordingly (Table
2-3). Devices may be physically addressed starting at 160000 and continuing through
177776; howevcm', there may be some software restrictions. The normal addressing convention is as shown in Table 2-3. The floating address rankingis 44.

2-3

O12

TERMINALZ

013

TIMING

O14
Q15
Q16

~\ INTERFACE
~ TERMINATING
RESISTOR

SELECTION
JUMPERS

JUMPERS

FOR RS-422-A

017

i9 i

24 26% 28
DATA SET CHANGE JUMPERS -

*W26 IS INPUT TO DSCNG FLIP FLOP

SHIPPED

ADDRESS

VECTOR

160010

300
40 42 44 46

JUMPERS ARE
DAISY CHAINED

e m’“’%w

2-4

‘Table 2-2

Vector Address Selecti

DPV11 (M8020) VECTOR ADDRESSING

[ iomeer

VEC

“X" INDICATES A CONNECTION TO W46,

320

330

340

300
310

X X X X

.
X
X

X X X X X X X X

ADDRESS

X X X X X X X X

”

X
X

|
|

| |

350
360
370

400

W46 IS THE SOURCE JUMPER FOR THE VECTOR ADDRESS

JUMPERS ARE DAISY CHAINED.

|
-

2-5

MK-1341

Table 2-3

Device Address Selection

DPV11-XX (M8020) DEVICE ADDRESSING

MSB__

| 13

12'11

JUMPERS
'

{

W36 W33 w32 | was|wasfwa7|w

'NUMBER

DEVICE
ADDRESS
760010

760020
X X X X

760030
760040

760050
760060
760070
760100
-

760200
-

760300
X
X

760500

760600

760400

760700

761000
762000
W

763000
-

764000

“X" INDICATES A CONNECTION TO W29. W29 IS TIED TO

GROUND. JUMPERS ARE DAISY CHAINED.
MK-1339

2.4 INSTALLATION
The DPV11 can be installed in any LSI-11 bus-compatible backplane such as H9270. LSI-11 configuring rules must be followed. Proceed with the installation as follows. For additional information
refer to PDP-11/03 User Manual EK-LSI11-TM or LSI-11 Installation Guide EK-LSI11-1G.
1.

Configure the address and vector jumpers at this time if they have not been previously done
(Paragraph 2.3).
WARNING
Turn all power OFF.
2-6

Connect the female Berg connector on the BC26L-25 cable to J1 on the M8020 module T
and plug the module into a dual LSI-11 bus slot of the backplanc

Insert and remove mod

avoid snagging mod #
guides.

Connect the H3259T turn-around connector to the EIA connection on the BC26L-25 cable.

The jumper W1 on the H3259 turn-around connector must be removed.

Perform resistance checks from backplane pin AA2 (+5 V) to ground and from AD2 (+ 12
V) to ground to ensure that there are no shorts on the M8020 module or backplane.
Turn system power on.

‘Check the voltages to ensure that they are within the specified tolerances (Table 2-4). If
voltages are not within specified tolerances, replace the associated regulator (H780 P.S.)

Table 2-4

Voltage
+5V

Max.
|

+12V

Voltage Requirements

+5.25
12.75

Ba kmam Pin
+4.75

AAZ

+11.25 |

AD2

2.4.1 \Verification of Hardware Operation
The M8020 moduleis now ready to be tested by running the CVDFV* diagnostic. Additional information on the DPV11 diagnosticsis containedin Appendix A and C apter 5. Proceed as follows.

The
tic.

NOTE
represents the revision level of the diagnos-

Load and run CVDPV*. Three consecutive error-free passes of this test is the minimum re-

quirement for a successful run. If this cannot be achieved, check the following.
Board seating
Jumper connections
Cable connection
Test connector

If a successful run is still unachievable, corrective maintenance is required (see Chapter 5).

Load and run the DEC/X11 System Exercmer cmflgumd to test the number of DPV11s
the system.

Each DEC/X11 CXDPV module will test up to eight consecutively addressed DPV11s.
CXDPV uses a software switch register. Refer to the DEC/X1I Cross-Reference (ASF055C-MC) for switch register utilization.
+If a BC26L-25 cable and H3259 turn-around
connector are not available, an on-bos rd test connector (H3260) can be ordered separately. See Paragraph 2.5.

The DEC/X11 System Exerciseris designed to achieve maximum
¢
ion with all devices that make up the system configuration. It is within this environn fizant that the CXDPV
module runs. Its intent is to isolate DPV11s which adversely affect the system operation.

For information on configuring and running the DEC/X11 § ystem Exerciser, refer to
DEC/X11 User Manual (AS-F0503B-MC) and DEC-XI11
Cross Reference (AS-F055CMOQ).

2.4.2

Connection to External Equipment/Link Testing

The DPV11is now ready for connection to external cqmpmem
If the DPV11 is being connected to a synchronous modem, remove the H3259 conmcmrand install the
EIA connection of the BC26L-25 cable into the connector on the modem.
X
Configure jumpers W1-W28 in accordance with operating requirements (Table 2-1).
Load andrun DCLT (CVCLH?*) if a full linkis available. This will check the fmm cwnfxgumtton and
isolatefailures to the CPU,the communications link, or the modem.

If the connection to external equipment uses RS-422-A, the user must pmvxde the cable and test sup-

port.

2.5 TEST CONNECTORS
The only test connectorprovidedwith the DPVII is the H3259 turnwar'und connector (Figure 2-2).
Table 2-5 and Figure 2- 3 show the relationship between pin numbers, signal names and register bits
when the H3259is connected bymeans of the BC26L-26 cable to the '»’?8020 module.
i

TCP

RCP

17.

15 @

NULL MODEM

24 @

19
@
SELECT FREQ

23
@

12@

16 @—=
9

SEC REC

REMOTE LOOP

(SIGNAL QUALI

25 &~ rsTmobt
2 @&
3@

XMIT DATA

REC DATA

R.T.S.

18 @

TS,

H3259

LOC AL o]0 LOOP

DATA MODE

"WI IS CUT FOR TESTING DPV11

22 @—e

NCOM NG CALL

Figure 2-2

,
mwvw.sfifl

H3259 Turn-Around Test Connector °H
b

2-8

sidgo

L8~ 005 )

Table 2-5

H3259 Test Connections

From

Signal Name

PinNo. | PinNo. | PinNo.

Pin No. |

H3259

SEND DATA

REQUESTTOSEND

BB&T | 5&8

(RTS) (RXCSR-2)

|
|

LOCAL LOOPBACK

(LL) (RXCSR-3)

SELECT FREQ/REMOTE |23/21
LOOPBACK

DATA TERMINAL

READY (DTR)

H3259 | Signal Name

RECEIVE DATA
CLEAR TO SEND

(CTS)(RXCSR-13),
RECEIVER READY

- DATA MODE

(RR) (RXCSR-12)

(DM) (RXCSR-9)

RR/MM | MM/C | 21/25 | SIGNAL QUALITY/
TEST MODE

(SF/RL) (RXCSR-0)

NULL MODEM

(SQ/TM) (PCSCR-5)

N&R

| 15&17 | RCV CLOCK
TX CLOCK

(RXCSR-1)

INCOMING CALL
(IC) (RXCSR-14)
|

The following accessories are available for interfacing and may be ordered separately.

BC26L-X cable. Availablein lengths of .3, 1.8, 2.4, 3.0, 3.6, 6.1, and 7.6 meters (1, 6, 8, 10,

12, 20 and 25 feet). When ordering, the dash number mdwatea the desired cable lcngthin
feet; e.g., B026L~25 or BC26L-1.

H3259 cable turn-around connector

HB856 Berg connector. Includes H856 Berg connector and 40 pms Cmmpmg tools are available from:
Berg Electronics, Inc.
New Cumberland, PA

®
-

17070

H3260 on~board test connector (mcludes RS-422-A testing)

The H3260 on-board test connector (Figure 2-4) may bc used to test the M8020 circuitry in its entirety.
RS-422-A circuitry is not tested with the H3259 cable turn-around connector. The H3260 on-board test
connector is shipped configured for testing RS-422-A. It may be amfligured to test RS-422-A or RS423-A as follows.

RS-422-A

W1-W2 out

W3-W6 installed

RS-423-A

W1-W2 installed

W3-W6 out

The connectot is installed into J1 with the jumper side up.
Since the H3260 on-board test connector does not test the cable, it is recommended that the DPV11 be
tested with a turn-around connector at the
modem end of the cable if possible.
2-9

SEND DATA

& T

(

L B

E40

SQ/TM
m

we,” W5 |
p

w37

3 _

MM|

" FF

Wi1

21 | T THIS JUMPER

12/

11 | |

MUST BE

REMOVED WHEN

©w

RXCSR-3 (LL)

~ LOCAL LOOP BACK

N
o,

READY

RAAA
~

($2)

DATA SET

//A\[/N \

RXCSR-0

/‘r

)

PCSCR-5

SF/RL

& r—

LOCAL CLK

{

TX CLOCK
TCP.

RECEIVE DATA

RXCSR-14 (INCOMING 11

READY

RSCSR-13 (CTS)

CLEAR TO SEND

RSCSR-2 (RTS)

jius*‘a

& —i

REQUEST TO SEND

a E 45

RSCSR-1 (DTR)

DATA TERMINAL

(o)

& ~<

CALL)

E25

NEGATIVE INPUT TO DIFFERENTIAL

RECEIVERS OMITTED FOR CLARITY

Figure 2-3

RS-423-A with H3259 Test Connector =~

2-10

TEST MODE

Cco

SIGN QUAL

MM
o

SF/RL

RR o
Wi

SEND DATA
RX DATA

SEND DATA

4 \b-T—[\.,

O
AA

(RS422)

TERM TIMING

SEND TIMING

RX TIMING

TERM TIMING

W o

(RS422)

CLEAR TO SEND
REQ TO SEND

RX RDY

V o

RS422

BBO
O
DD

DATA MODE

H3260

DATA MODE RET
(LOCAL LOOP)

RS423

WS o3

INCOMING CALL

TERM RDY

|
W5

SEND TIM RET

TT o

RX TIM RET

SSo

TERM TIM RET

EEO

P—;

(RS422)
W6

SEND DATA RET
RX DATA RET

So
H3260 TEST CONNECTOR

NOTE: 1. W1 & W2 IN

W3-WE OUT

}

-4233T
RS-423-A
TESTING

2. W1 & W2 ouT } RS-422-A TESTING
W3-W6 IN

Figure 2-4

H3260 On-Board Test Connector

2-11

MK-1464

)

3.1 INTRODUCTION
This chapter describes the bit assignments and pmgrammmg considerations for the DPV11. Some typical start and receive sequences for both bit- and character-oriented protocols are included.

The fwe mgxsters usedin thc DPVII are sho»wnin Table 3»1 Note that two of the registers (PCSAR

and RDSR) have the same address. This does not constitute a conflict, however, because the PCSAR
is a write-only register and the RDSRis a read-only register. These five registers occupy eight contiguous byte addresses which begin on a boundarywhere the low*rdcr three bits are zero, and can be
located anywhere between 160000g and 17 7776g.

Tahle 3-1

DPVll R 20jnters

RXCSR
|

Addm&

16xxx0
R

Word or byte* addressable.
§Read/writc.

Word or byte* addressable.
Read-only.

Receive Data and Status

RDSR**

16xxx2
|

Parameter Control Sync/Address

PCSAR**

16xxx2

Word or byte addressable.

PCSCR}

16xxx4

Word or byte addressable.

Parameter Control and Character

Length

Read/write.

Transmit Data and Status

TDSR**

16xxx6

Word or byte addressable.
‘Read/write.

* Reading either byte of thme wgmtem, clears data and certain status bitsin mhur bytes. See Paragraphs 3.3.1
and 3.3.2.
** Registers contained within the USYNRT.
It is not possible to do bit set or bit clear instructions on this register.
1 The high byte of this register is internal to the USYNRT.

The DPVM uses a umvamabsymhmmw receiver/transmitter (USYNRT) chip which accounts for a
large portion of the DPV11’s functionality. The USYNRT provides complete serialization, deserialization and buffering of data to and from the modem.

3-1

Most of the DPV11 registers are internal to the USYNRT. Only the receiver control and status register (RXCSR) and the low byte of the parameter control and character length register (PCSCR) are
external.

o
|
PR
et ol

NOTE
When using the special space sequence function, all
registers intemal to the USYNRT must be written
:byw m e.

Blt assignments for the flve DPVl 1 reglsters are shownin Figure 3-1. Paragraphs 3.3.1-3.3.5 provide a
description of each register usmg a b1t assxgnment 1Mustratmn and an accompanymg table wzth a de»
tailed descmptwn of aach blt
3.3.1 Receive Cmtml and Status Regmer (RXCSR) (Address16xxx0)
Figure 3-2 shows the format for the receive control and status register (RXCSR) Table 3 2is a detmled dwcmptmn of the register T’hm register is external to the USYNRT
)
-

The RXCSR can be read in either word or byte
mode. However, reading either byte resets certain
status bits in both bytes.
3.3.2 Receive Data and Status Register (RDSR) (Address 16xxx2)
Figure 3-3 show the format for the receive data and status register (RDSR). Itis a read—»only register
and shares its address with the parameter control sync/address register (PCSAR) whichis wnte-—wmly
Table 3-3 is a detaileddeamptwn of the RDSR.
L

NOTE

The RDSR can be readin either word or byte mode.

However, readmg either byte resets data and certain
~status bitsin both bytes of thismm&ter as well as
_bits 7 and 10 of the RXCSR.

3.3.3 Parameter ControlSync/Address Register (PCSAR) (Address 16xxx2)
,
The parameter control sync/address register (PCSAR)is a write-only reglster which can be wr1tten in
either byte or word mode. Figure 3-4 shows the format and Table 3-4is a detailed description of the
PCSAR. This register shares its address with the RDSR
,
»
,

NOTE

Blt set (BIS) and bit clear (BIC) instructions can-not be executed on the PCSCR, since they execute
~ using a read-modify-write sequence.
,

id Character Leumth Register (PCSCR) (Address 16xxx4)

The parameter control and character length register (PCSCR) can be read from or written into in

either word or byte mode. The low byte of this regnster is external to the USYNRT and the high byte is
internal. Figure 3-5 shows the format and Table 3-5 is a dmmled descmptwnmf thePCSCR. "+

3.3.5 Transmit Data and Status Register (TDSR) (Address 16xxx6)
The format for the transmit data and status regmter (TDSR)is shownin Figure 3-6 and Table 3-6is a
detailed descmptwn The TDSRis a read/write register which can be accessedin either word or byte
mode with no restrictions. Allbits can beread fmm or wmtwn mm andare resetby I'W1m csetm',
Bus INIT exceptwhere noted.
L
-

RXCSR
16XXX0

READ/WRITE

R | R
DATA

CLR

CHANGE

SEND

INCOMING
CALL

w | rw | Rw| RW | AW |

RCV

RCVR
READY

RCVR
STATUS

DATA

LOCAL

READY

INTR

LOOP

DATA

TERM

(LL)

SET

RDY

SYNC
OR

RCV
INTR

RX
ENA

FLAG

READY

RCV

DATA

ACTIVE

SET

DETECT

REQ
TO

SF/RL

SEND

RDSR

MK-1504

16XXX2
READ ONLY

BLED
ASSEM
BIT COUNT

l
'

‘

JSIEAE
i

]

!‘

meve DATA BUFFER
1

G IS,
i

]

RCVR
OVER

ERROR
CHECK

RUN

START

RCV

ABORT

MESG

PCSAR

16XXX2

WRITE ONLY

ALL
PARTIES
ADDR

DETECTION
ERROR
SELECTION
i

’
’
”
’SECONDARY
STATION <+
. |

_’!

RECEIVER SYNC
}

~ IDLE
MODE

STRIP
SYNC OR
LOOP

SELECT

MODE

PROTOCOL
SELECT

SECD
ADRS
MODE

SEL
MK-1508

Figure 3-1

DPVII1 Register Configurations and Bit Assignments (Sheet 1 of 2)

3-3

PCSAR
16XXX4

READ/WRITE
15

08
|

- R/W

R/W

J ‘

TRANSMITTER

CHARACTER LENGTH
b

EXTD

" RECEIVER

ADDR

R/W

]

RSVD

CHARACTER LENGTH

FIELD

MAINT

XMTR

MODE

ACTIVE

SELECT
EXTD

CONT

XMIT

XMTR

~ DEVICE

INTR

ENAB

BUFFER

RESET

FIELD

EMPTY
MK-1507

TDSR

16XXX6
READ/WRITE
13

lR
XMIT

RESERVED

R/W

R/W |RW

XMIT

END

DATA

LATE

AHEAD

MESG

ABORT

R'W R/W

R/W |
)

TRANSMIT DATA BUFFER

START
OF
MESG
MK-1508

Figure 3-1

DPVI11 Register Configurations and Bit Assignments (Sheet 2 of 2)

RDAT

DS*
-

CNG

ITEN

ENA

CTS

RTS

RSTA"*

ACT

SF/RL

SFD

E THIS BIT IS RESET BY READING EITHER BYTE OF fH!S REGISTER.
** THESE BITS ARE RESET BY READING EITHER BYTE OF RSDR.
MK-1327

Figure 3-2

Receive Control and Status Register (RXCSR) Format

3-4

‘“@%~4

ter (RXCSR) Bit Assignmer

Table 3-2 Receive Cor
Bit

Name

Description

Data Set Change
(DSCNG)

‘This bit is set when a transition occurs on any of the following
modem control lines:

Clear to Send

Data Mode
Receiver Ready
Incoming Call

Transition detectors for each of these four lines can be disabled
by removing the associated jumper.
Data Set Change is cleared by reading either byte of the
RXCSR or by Device Reset or Bus INIT.

Data Set Change causes a receive interrupt if DSITEN (bit 5)

and RXITEN (bit 6) are both set.
14

Incoming Call

(IC)

This bit reflects the state of the modem Incoming Call line. Any
transition of this bit causes Data Set Change bit (bit 15) to be
asserted unless the Incoming Call line is disabled by removing
its jumper. This bit is read-only and cannot be cleared by software.

Clear to Send
(CTS)

This bit reflects the state of the Clear to Send line of the
modem. Any transition of this line causes Data Set Change (bit
15) to be set unless the jumper enabling the Clear to Send signal

“is removed.

Clear to Send is a program read-only bit and cannot be cleared |

by software.
12

Receiver Ready

(RR)

This bit is a direct reflection of modem Receiver Ready lead. It
indicates that the modem is receiving a carrier signal. For external maintenance loopback, this signal must be high. If the line is
open, RR is pulled high by the circuitry.

Any transition of this bit causes Data Set Change (bit 15) to be
asserted unless the jumper enabling the Receiver Ready signal
is removed.

Receiver Ready is a read-only bit and cannot be cleared by software.

Receiver Active
(RXACT)

This bit is set when the USYNRT presents the first character of
a message to the DPV11. It remains set until the receive data
path of the USYNRT becomes idle.
Receiver Active is cleared by any of the following conditions: a
terminating control character is received in bit-oriented protocol
mode; an off transition of Receiver Enable (RXENA) occurs; or
Device Reset or Bus INIT is issued.

3-5

Table 3-2

Bit

Receive Control and Status Register (RXCSR) Bit Assignments (Cont)

Name

Description
Receiver Active is a read-only bit which reflects the state of the
USYNRT output pin 5.

Receiver Status
Ready (RSTARY)

This bit indicates the availability of status information in the
upper byte of the receive data and status register (RDSR). It is
set when any of the following bits of the RDSR are set: Receiver
End of Message (REOM); Receiver Overrun (RCV OVRUN);
Receiver Abort or Go Ahead (RABORT); Error Check
(ERRCHK) if VRC is selected.

Receiver Status is cleared by any of the following conditions:
reading either byte of the RDSR; clearing Receiver Enable (bit
4 of RXCSR); Device Reset, or Bus Init.
When set, Receiver Status Ready causes a receive interrupt if
Receive Interrupt Enable (bit 6) is also set.

Receiver Status Ready is a read-only bit which reflects the state
of USYNRT pin 7.

Data Mode (DM)
(Data Set Ready)

This bit reflects the state of the Data Mode signal from the
modem.
When this bit is set it indicates that the modem is powered on
and not in test, talk or dial mode.
Any transition of this bit causes the Data Set Change bit (bit
15) to be asserted unless the Data Mode jumper has been removed.

Data Mode is a read-only bit and cannot be cleared by software.

Sync or Flag
Detect (SFD)

This bit is set for one clock time when a flag character is detected with bit-oriented protocols, or a sync character is detected with character-oriented protocols.
SFD is a read-only bit which reflects the state of USYNRT pin
4.

Receive Data
Ready (RDATRY)

This bit indicates that the USYNRT has assembled a data character and is ready to present it to the processor.
If this bit becomes set while Receiver Interrupt Enable (bit 6) is
set, a receive interrupt request will result.
Receive Data Ready is reset when either byte of RDSR is read,
Receiver Enable (bit 4) is cleared, or Device Reset or Bus INIT
is issued.

RDATRY is a read-only bit which reflectes the state of USYNRT pin 6.
V

3-6

Table 3-2
Bit

Receive Control and Status Register (RXCSR) Bit Assignments (Cont)

Name

Description

Receiver Intempt

When set, this bit allows interrupt requests to be made to the
receiver vector whenever RDATRY (bit 7) becomes set.

Enable (RXITEN)

The conditions which cause the interrupt request are the assertion of Receive Data Ready (bit 7), Receive Status Ready (bit
10), or Data Set Change (bit 15) if DSITEN (bit 5) is also set.

RXITEN is a program read/write bit and is cleared by Device
Reset or Bus INIT.

Data Set Intermpt
Enable (DSITEN)

This bit, when set along with RXITEN, allows interrupt
requests to be made to the receiver vector whenever Data Set
Change (bit 15) becomes set.

DSITEN is a program read/write bit and is cleared by Device
Reset or Bus INIT.
Receiver Enable
(RXENA)

This bit controls the operation of the receive section of the USYNRT.

When this bit is set, the receive section of the USYNRT is enabled. When it is reset the receive section is disabled.
In addition to disabling the receive section of the USYNRT, re-

setting bit 4 reinitializes all but two of the USYNRT receive

registers. The two registers not reinitialized are the character
length selectmn buffer and the parameter control register.
Local Loopback

(LL)

Asserting this bit causes the modem connected to the DPV11 to
establish a data loopback test condition.
Clearing this bit restores normal modem operation.

Local Loopbackis program read / write andis cleared by Device
Reset or Bus request to Send is program read / write and is
cleared by Device R.e&ct or Bus INIT.
v

Request to Send
(RTS)

Setting this bit asserts the Request to Send sxgml at the modem
interface.

Request to Send is pmgram read /write and is cleared by Device

Reset or Bus INIT.

Terminal Ready (TR)
(Data Terminal
Ready)

When set, this bit asserts the Terminal Ready signal to the
modem interface.

For auto dial and manual call origination, it maintains the established call. For auto answer, it allows handshaking in response to
a Ring signal.

3-7

Table 3-2

Bit

Receive Control and Status Register (RXCSR) Bit Assignments (Cont)

Name

Description

Select Frequency
or Remote
Loopback (SF/RL)

This bit can be wire-wrap jumpered to function as either select
frequency or remote loopback. When jumpered as select frequency (W3 to W4), setting this bit selects the modem’s higher

frequency band for transmission to the line and the lower fre-

quency band for reception from the line. The clear condition selects the lower frequency for transmission and the higher frequency for reception.

When jumpered for remote loopback (W5 to W3), this bit, when
asserted, causes the modem connected to the DPV11 to signal
when a remote loopback test condition has been established in
the remote modem.

SF/RL is program read/write and is cleared by Device Reset or
Bus INIT.

ERR

CHK

RECEIVE DATA BUFFER

L
15

]

ASSEMBLED
BIT COUNT

lF?EC
'OVRUN ABORT| REOM |RSOM|
MK-1326

Figure 3-3

Table 3-3

Receive Data and Status Register (RDSR) Format

Receive Data and Status Register (RDSR) Bit Assignments

Bit

Name

Description

Error Check
(ERR CHK)

This bit when set, indicates a possible error. It is used in conjunction with the error detection selection bits of the parameter
control sync/address register (bits 8—10) to indicate either an
error or an all zeros state of the CRC register.

With bit-oriented protocols, ERR CHK indicates that a CRC
error has occurred. It is set when the Receive End of Message
bit (RDSR bit 9) is set.
With character-oriented protocols ERR CHK is asserted with
each data character if all zeros are in the CRC register. The

processor must then determine if this indicates an error-free

3-8

Table 3-3 Receive Data and Status Register (RDSR) Bit Assign ments (Cont)
Bit

Name

Description

message or not. If VRC parity is selected, this bit is set for every
character which has a parity error.

ERR CHK is cleared by reading the RDSR, clearing RXENA
(RXCSR bit 4), Device Reset or Bus INIT.

All bits are valid
One valid bit
Two valid bits
Three valid bits
Four valid bits
Five valid bits
Six valid bits
Seven valid bits

O = O

Number of Valid Bits

D e
N

pd et

—O

et O
e e

Used only with bit-oriented protocols, these bits represent the
number of valid bits in the last character of a message. They are
all zeros unless the message ends on an unstated boundary. The
bits are encoded to represent valid bits as shown below.

ek OO

Assembled Bit
Count (ABC)

14-12

These bits are presented simultaneously with the last bits of
data and are cleared by reading the RDSR or by resetting
RXENA (bit 4 of RXCSR).

Receiver Overrun

(RCV OVRUN)

This bit is used to indicate that an overrun situation has occurred. Overrun exists when the data buffer (bits 0—7 of RDSR)
has not been serviced within one character time.

As a general rule, the overrun is indicated when the last bit of
the current character has been received into the shift register of
the USYNRT and the data buffer is not yet available for a new
character.

Two factors exist which modify this general rule and apply only
to bit-oriented protocols.

The first factor is the number of bits inserted into the data
stream for transparency. For each bit inserted during the formatting of the current character, the controller’s maximum response time is increased by one clock cycle.

The second factor is the result of termination of the current
message. When this occurs, the data of the terminated message
which is within the USYNRT is not overrunable. If an attempt
is made to displace this data by the reception of a subsequent
message, the data of the subsequent message is lost until the
data of the prior message has been released.

3-9

Table 3-3

Receive Data and Status Register (RDSR) Bit Assignments (Cont)

Bit

Name

Description

Receiver Abort or
Go Ahead (RABORT)

This bit is used only with bit-oriented protocols and indicates
that either an abort character or a go-ahead character has been
received. This is determined by the Loop Mode bit (PCSAR bit
13). If the Loop Mode bit is clear, RABORT indicates reception
of an abort character. If the Loop Mode bit is set, RABORT
indicates a go-ahead character has been received.
The setting of RABORT causes Receiver Status Ready (bit 10
of RXCSR) to be set.
RABORT is reset when the RDSR is read or when Receiver Enable (bit 4 of RXCSR) is reset.

The abort character is defined to be seven or more contiguous
one bits appearing in the data stream. Reception of this bit pattern when Loop Mode is clear causes the receive section of the
USYNRT to stop receiving and set RSTARY (bit 10 of
RXCSR). The abort character indicates abnormal termination
of the current message.

The go-ahead character is defined as a zero bit followed by sev-

en consecutive one bits. This character is recognized as a normal
terminating control character when the Loop Mode bit is set. If
Loop Mode is cleared this character is interpreted as an abort

character.
Receiver End of
Message (REOM)

This bit is used only with bit-oriented protocols and is asserted if
Receiver Active (bit 11 of RXCSR) is set and a message is terminated either normally or abnormally. When REOM becomes
set, it sets RSTARY (bit 10 of RXCSR).
REOM is cleared when RDSR is read or when Receive Enable
(bit 4 of RXCSR) is reset.

Receiver Start of
Message (RSOM)

7-0

Used only with bit-oriented protocols. This bit is presented to
the processor along with the first data character of a message
and is synchronized to the last received flag character. Setting
of RSOM does not set RSTARY (RXCSR bit 10).

RSOM is cleared by Device Reset, Bus INIT, resetting Receiver Enable (RXCSR bit 4), or the next transfer into the Receive Data buffer (low byte of RDSR).
Receive Data
Buffer

The low byte of the RDSR is the Receive Data buffer. The
serial data input to the USYNRT is assembled and transferred
to
the low byte of the RDSR for presentation to the processo
r.
When the RDSR receives data, Receive Data Ready (bit 7 of
RXCSR) becomes set to indicate that the RDSR has data to be
picked up. If this data is not read within one character time,
a

data overrun occurs.

The characters in the Receive Data buffer are right-justified
with bit O being the least significant bit.
|
3-10

APA

|
|

SECONDARY STATIRON ADIDRESSl

SYNC CHARACTER OR

SEC

SEST gz’g ADR | IDLE
|

ERR DET SEL

MDE

MK-1330

Figure 3-4

Table 3-4

Bit

Parameter Control Sync/Address Register (PCSAR) Format

Parameter Control Sync/Address Register (PCSAR) Bit Assignments

Name

All Parties

Description

‘

Addressed (APA)

This bit is set when automatic recognition of the All Parties Ad-

dressed character is desired. The All Parties Addressed character is eight bits of ones with necessary bit stuffing so as not to be
confused with the abort character.
Recognition of this character is done in the same way as the sec-

ondary station address (see bit 12 of this register) except that
the broadcast address is essentially hardwired within the receive
data path. The logic inspects the address character of each
frame for the broadcast address. When the broadcast address is
recognized, the USYNRT makes it available and sets Receiver
Start of Message (bit 8 of RDSR).

If the broadcast addwss is not recognized, one of two possible

actions occurs.

1. If the Secondary Address Select mode bit (bit 12) is set, a
test of the secondary station address is made.

If bit 12 is not set or the secondary station address is not

recognized, the receive section of the USYNRT renews its
search for synchronizing control characters.

)

Protocol Select

(PROT SEL)

This bit is used to select between character- and byte count-ori-

ented or bit-oriented protocols. It is set for character- and byte
count-oriented protocols and reset for bit-oriented protocols.

Strip Sync or
Loop Mode
(STRIP SYNC)

This bit serves the following two functions.

1. Strip Sync (character-oriented protocols) — In character-oriented protocols, all sync characters after the initial synchronization are deleted from the message and not included in the

CRC computation if this bit is set. If it is cleared, all sync characters remain in the message and are included in the CRC com-

putation.

3-11

Table 3-4
Bit

Parameter Control Sync/ Address Register (PCSAR) Bit Assignments (Cont)

Name

Description
2. Loop Mode (bit-oriented protocols)— With bit-oriented protocols, this bitis used to control the method of termination. If it
is set, either a flag or go-ahead character can cause a normal
termination of a message. If it is cleared, only a flag character
can cause a normal termination.

Secondary
Address Mode
(SEC ADR MDE)

This bit is used with bit-oriented protocols when automatic recognition of the secondary station address is desired. If it is set,
the station address of the incoming message is compared with
the address stored in the low byte of this register. Only messages
prefixed with the correct secondary address are presented to the
processor. If the addresses do not compare, the receive section
of the USYNRT goes back to searching for flag or go-ahead
characters.

When SEC ADR MDE is cleared, the receive section of the
USYNRT recognizes all incoming messages.

Idle Mode Select

This bit is used with both bit- and characteréoriented protocols.

(IDLE)

With bit-oriented protocols, IDLE is used to select the type of
control character issued when either Transmit Abort (bit 10 of
'TDSR) is set or a data underrun error occurs. If IDLE is set,
flag characters are issued. If IDLE is clear, abort characters are
issued.

With character-oriented protocols, IDLE is used to control the
method in which initial sync characters are transmitted and the
action of the transmit section of the USYNRT when an underrun error occurs. IDLE is cleared to cause sync characters from
the low byte of PCSAR to be transmitted. When IDLE is set,
the transmit data output is held asserted during an underrun error and at the end of a message.

10-8

Error Detection
Selection
(ERR DEL SEL)

These bits are used to determine the type of error detection used
on received and transmitted messages. In bit-oriented protocols,
the selection is independent of character length. In characterand byte count-oriented protocols, CRC error detection is usable only with 8-bit character lengths. The maximum character
length for VRC is seven. The bits are encoded as follows.
10

CRC Polynomial

x16+x12+4+x5+1 (CRC CCITT) (Both CRC
data registers in the transmit and receive sections are set to all ones prior to the computation.)

x164-x12+4x5+1 (CRC CCITT) (Both CRC
data registers set to all zeros.)
|

3-12

Table 3-4
Bit

Parameter Control Sync/Address Register (PCSAR) Bit Assignments

Description

Name

Not used

x164+x15+x2+1 (CRC 16) (Both CRC regis-

Odd VRC Parity (A parity bit is attached to
each transmitted character.) Should be used

ters set to all zeros.)

only in character-oriented protocols.

Even VRC parity (Resembles odd VRC ex-

cept that an even number of bits are generated.)

7-0

Not used.

All error detection is inhibited.

The low byte of PCSAR is used as either the sync character for

Sync Character

character-oriented protocols or as the secondary station address
for bit-oriented protocols.

or Secondary
Address

The bits are right-justified with the least significant bit being bit
0.

EXTERNAL TO THE USYNRT
..

(7
I| rsvo|

6
o
IN
NT

2
|
o )
|18
[TXACT|RESET |
- |8
TE

INTERNAL TO THE USYNRT

(15

TRANSMITTER

8 \

RECEIVER

CHARACTER LENGTH EXADD|EXCON] CHARACTER LENGTH
MK-1325

Figure 3-5

Pammetzr Control and Character Length Register (PCSCR) Format
3-13

Table 3-5 Parameter Control and Character Length Register (PCSCR) Bit Assignments

Bit
15-13

Name

Description

Transmitter

These bits can be read or written and are used to determine the
length of the characters to be transmitted.

Character Length

They are encoded to set up character lengths as follows.

Character Length

Eight bits per character

Seven bits per character

Six bits per character

Five bits per character (bit-oriented protocol

only)
1

Four bits per character (bit-oriented protocol

only)

Three bits per character (bit-oriented protocol
only)

Two bits per character (bit-oriented protocol
only)

One bit per character (bit-oriented protocol
only)

These bits can be changed while the transmitter is active, in
which case the new character length is assumed at the completion of the current character. This field is set to a character
length of eight by Device Reset or Bus INIT. When VRC error
detection is selected, the default character length is eight bits
plus parity.
12

Extended Address
Field (EXADD)

This bit is used with bit-oriented protocols and affects the address portion of a message in receiver operations. When it is set,
each address byte is tested for a one in the least significant bit
position. If the least significant bit is zero, the next character is

an extension of the address field. If the least significant bit is
one, the current character terminates the address field and the

next character is a control character.

EXADD is not used with Secondary Address Mode (bit 12 of
PCSAR).

EXADD is read/write and is reset by Device Reset or Bus

INIT.
11

Extended Control
Field (EXCON)

This bit is used with bit-oriented protocols and affects the control character of a message in receiver operations. When EX3-14

Table 3-5
Bit

Parameter Control and Characte:

Name

signments (Cont)

Description
CON is set it extends the control field from one 8-bit byte to
two 8-bit bytes.

EXCON is not used with Secondary Address Mode (bit 12 of

PCSAR)

EXCON is read/write and is reset by Device Reset or Bus
INIT.

10-8

Receiver

Character Length

These bits are used to determine the length of the characters to
be received.
They are encoded to set up character lengths as follows.
10

Character Length

Eight bits per character

Seven bits per character

Six bits per character

Five bits per character

Four bits per character (bit-oriented protocols
only)

Three bits per character (bit-oriented protocols only)

Two bits per character (bit-oriented protocols

One bit per character (bit-oriented protocols

only)

Reserved

Not used by the DPV11

Transmit Interrupt
Enable (TXINTEN)

When set, this bit allows a transmitter interrupt request to be
made to the transmitter vector when Transmit Buffer Empty
(TBEMTY) is asserted. Transmit Interrupt Enable (TXIN-

TEN) is read/write and is cleared by Device Reset or Bus
INIT.

Signal Quality or
Test Mode (SQ/TM)

This bit can be wire-wrap jumpered to function as either Signal
Quality or Test Mode.
When jumpered for signal quality (W5 to W6), this bit reflects

the state of the signal quality line from the modem. When asserted, it indicates that there is a low probability of errors in the
received data. When clear it indicates that there is a high probability of errors in the received data.
3-15

Table 3-5
Bit

Parameter Control and Character Length fiegmwr (PCSCR) Bit Assignments (Cont)

Name

Description
When jumpered for the test mode (W6 to W7), this bit indicates
that the modem has been placed in a test condition when asserted. The modem test condition could be established by asserting Local Loopback (bit 3 of RXCSR), Remote Loopback (bit 0
of RXCSR) or other means external to the DPV11.

When SQ/TM is clear, it indicates that the modem is not in test
mode and is available for normal operation.

SQ/TM is program read-only and cannot be cleared by soft-

ware.

Transmitter
Enable (TXENA)

This bit must be set to initiate the transmission of data or control information. When this bit is cleared, the transmitter will
~revert back to the mark state once all indicated sequences have
been completed. TXENA should be cleared after the last data
character has been loaded into the transmit data and status register (TDSR). Transmit End of Message (bit 9 of TDSR) should
be asserted when TXENA is reset (if it is to be asserted at all)
and remain asserted until the transmitter enters the idle mode.
TXENA is connected directly to USYNRT pin 37. It is a
read/write bit and is reset by Device Reset or Bus INIT.

Maintenance Mode
Select (MM SEL)

When this bit is asserted, it causes the USYNRT’s serial output
to be internally connected to the USYNRTs serial input. The
serial send data output line from the interface is asserted and
the receive data serial input is disabled. Send timing and receive
timing to the USYNRT are disabled and replaced with a clock
signal generated on the interface. The clock rate is either
49.152K b/s or 1.9661K b/s depending on the position of a
jumper on the interface board.

Maintenance mode allows diagnostics to run in loopback without disconnecting the modem cable.
MM SEL is a read/write bit and is cleared by Device Reset or
Bus INIT. When it is cleared, the interface is set for normal operation.

Transmitter Buffer
Empty (TBEMTY)

This bit is asserted when the transmit data and status register
(TDSR) is available for new data or control information. It is
also set after a Device Reset or Bus INIT.

The TDSR should be loaded only in response to TBEMTY
being set. When the TDSR is written into, TBEMTY is cleared.

If TBEMTY becomes set while Transmit Interrupt Enable (bit
6 of PCSCR) is set, a transmit interrupt request results.

TBEMTY reflects the state of USYNRT pin 35.
3-16

Table 3-5

Parameter Control and Character

Description

Bit

Name

Transmitter

This bit indicates the state of the transmit section of the US-

YNRT. It becomes set when the first character of data or con-

Active (TXACT)

trol information is transmitted.

TXACT is cleared when the transmitter has nothing to send or
when Device Reset or Bus INIT is issued.

TXACT reflects the state of USYNRT pin 34.

When a one is written to this bit all components of the interface
are initialized. It performs the same function as Bus INIT with

Device Reset
(RESET)

respect to this interface. Modem Status (Data Mode, Clear to
Send, Receiver Ready, Incoming Call, Signal Quality or Test
Mode) is not affected. RESET is write-only; it cannot be read
by software.

i‘

—

T
T

TRANSMIT DATA BUFFER

lI,lVlIIl
11

TERR

RESERVED
l
!

TGA

ABORT

TEOM| TSOM
MK-1331

Figure 3-6 Transmit Data and Status Register (TDSR) Format
Table 3-6 Transmit Data and Status Register (TDSR) Bit Assignments

‘

Bit

Name

Description

Transmitter

This is a read-only bit which becomes asserted when the Trans-

mitter Buffer Empty (TBEMTY) indication has not been serviced for more than one character time.

Error (TERR)

When TERR occurs in bit-oriented protocols, the transmit sec-

tion of the USYNRT generates an abort or flag character based
on the state of the IDLE bit (PCSAR bit 11). If IDLE is set, a
flag character is sent. If it is reset, an abort character is sent.

When TERR occurs in character-oriented protocols, the state of
the IDLE bit again determines the result. If IDLE is set, the
transmit serial output is held in the MARK condition. If it is
cleared, a sync character is transmitted.

3-17

Table 3-6
Bit

Transmit Data and Status Register (TDSR) Bit Assignments (Cont)

Name

Description
- TERR is cleared when TSOM (TDSR bit 8) becomes set or by

Device Reset or Bus INIT.

Clearing Transmitter Enable (PCSCR bit 4) does not clear
TERR and TERR is not set with Transmit End of Message.
14-12

Reserved

Not used by the DPV11

Transmit Go
Ahead (TGA)

This bit, when asserted, modifies the bit pattern of the control
character initiated by either Transmit Start of Message
(TSOM) or Transmit End of Message (TEOM). TSOM or
TEOM normally causes a flag character to be sent. If TGA is
set, a go-ahead character is sent in place of the flag character.

TGA is only used with bit-oriented protocols.
10

Transmit
Abort (TXABORT)

This bit is used only with bit-oriented protocols to abnormally
terminate a message or to transmit filler information used to establish data link timing.
When TXABORT is asserted, the transmitter automatically
transmits either flag or abort characters depending on the state
of the IDLE mode bit. If IDLE is cleared, abort characters are
sent. If IDLE is set, flag characters are sent.

Transmit End of
Message (TEOM)

This control bit is used to normally terminate a message in bitoriented protocol. It also terminatesa message in character-oriented protocols when CRC error detection is used. As a secondary function, it is used in conjunction with the Transmit Start of
Message (TSOM) bit to transmit a SPACE SEQUENCE. Refer to the TSOM bit description (bit 8 of this register) for information regarding this sequence.

With bit-oriented protocols, asserting this bit causes the CRC
information to be transmitted, if CRC is enabled, followed by
flag or go-ahead characters depending on the state of the Transmit Go Ahead (TGA) bit. See bit 11 of this register.

With character-oriented protocols, asserting this bit causes
CRC information, if CRC is enabled, to be transmitted followed
by either sync characters or a MARK condition depending on
the state of the IDLE bit. If IDLE"s cleared, sync characters
are transmitted.
The character following the CRC information is repeated until
the transmitter is disabled or the TEOM bit is cleared.
A subsequent message may be initiated while the transmit section of the USYNRT is active. This is accomplished by clearing
the TEOM bit and supplying new message data without setting

3-18

Table 3-6

Transmit Data and Status Register (TDSR) Bit Assignments (Cont)
Description

Name

the Transmit Start Of Message bit. However, the CRC character for the prior message must have completed transmission.

Transmit Start

This bit is used with either bit- or character-oriented protocols.
As long as it remains asserted, flag characters (bit-oriented protocols) or sync characters (character-oriented protocols) are
transmitted.

of Message
(TSOM)

- With bit-oriented protocols, a space sequence (byte mode only)

of 16 zero bits can be transmitted by asserting TSOM and
TEOM simultaneously provided the transmitter is in the idle
state and Transmit Enable is cleared. This should not be done
during the transfer of data, and must only be done in byte mode.
NOTE

When using the special space sequence function, all registers internal to the USYNRT must be written in byte mode.

Normally at the completion of each sync, flag, go-ahead or
Abort character, the TBEMTY indication is asserted. This allows the software to count the number of transmitted characters. In certain applications, the software may elect to ignore the
service of the Transmitter Buffer Empty (TBEMTY) indication.
Normally during data transfers, this would cause a transmit
data late error. The TSOM bit asserted suppresses this error
and provides the necessary synchronization to automatically
transmit another flag, go-ahead or sync character.

Transmit Data

7-0

Buffer

Data from the processor to be transmitted on the serial output
line is loaded into this byte of the TDSR when Transmitter Buffer Empty (TBEMTY) is asserted. If the transmitter buffer is
not loaded within one character time, an underrun error occurs.
The characters are right-justified, with bit 0 being the least significant bit.

3.4

DATA TRANSFERS

Paragraphs 3.4.1 and 3.4.2 discuss receive and transmit data transfers as they relate to the system
software.

3.4.1

Receive Data

Serial data to be presented to the DPV11 from the modem enters the receiver circuit and is presented
to the USYNRT. Recognition by the USYNRT of a control character initiates the transfer. When a
transfer has been initiated, a character
is assembled by the USYNRT and then placed in the low byte
of the receive data and status register (RDSR) when it is available. If the RDSR is not available, the
transfer is delayed until the previous character has been serviced. This must take place before the next
character is fully assembled or an overrun error exists. Refer to the description of bit 11 in Table 3-3
for more details on Receiver Overrun.

3-19

Servicing of the RDSRis the rcsponmbxhty of the system softwarein response to the Receive Data
Ready (RDATRY) signal. This signalis asserted when a character has been transferred to the RDSR.
The setting of RDATRY would also cause a receive mterrupt request if Receive Interrupt Enable
(RXITEN)is set. The software’s response to RDATRYis to read the contents of the RDSR. At the
completion of this Operatlon the new information is loaded into the RDSR and RDATRY is reasserted. This operation continues until terminated by some control character. The upper byte of the
RDSR contains status and error indications Wthh the software can also read.
The DPV11 will handle datain bit-, byte count- or character-oriented protocols.

With bit-oriented protocol, only flag characters are used to initiate the transfer of a message. Information inserted into the data stream for transparency or control is deleted before it is presented to the
RDSR. This means that only data characters are available to the software. The first two characters of

every message or frame are defined to be 8-bit characters and the USYNRT will handle them as such

regardless of the programmed character length. All subsequent data is formatted in the selected character length. When CRC error detection is selected, the received CRC check characters are not presented
to the software, but the error indication will be presented if an error has been detected.

If the secondary address modeis implemented, the first received data character must be the selected
address. If this is not the case, the USYNRT will renew its search for flag or go-ahead characters.

Refer to the description of bit 12 of the PCSARin Table 3-4.

With byte count- or character-oriented protocols, two consecutive sync characters are required to synchronize the transfer of data. The sync characters usedin the message must be the same as the sync
character loaded by the software into the low byte of the parameter control sync/address register
(PCSAR). If leading sync characters subsequent to the initial two syncs are to be deleted from the
data stream, the Strip Sync bit (bit 13) must also be set in the upper byte of the PCSAR. The character length of the data to be received should also be set in bits 8, 9, and 10 of the parameter control and

character length register (PCSCR). Sync characters and data must have the same character length
and only characters of the selected length will be presented to the receive buffer. Sync characters
following the initial two will be presented to the buffer and includedin the CRC computation unless

the Strlp Sync bitis set. If vertical redundancy check (VRC) parity checkingis selected the parity bit
xtselfis deletcd from the character before it is presented to the buffer.
3.4.2 Transmit Data
System software loads information to be transmitted to the modem into the transmit data and status

register (TDSR). This does not ordinarily include error detection or control character information.
Loading of the TDSR occurs in response to the Transmitter Buffer Empty (TBEMTY) signal from the
USYNRT. The character length of information to be transmitted is established by the software when
it loads the transmit character length register (bits 13, 14, and 15 of the PCSCR). The default length
of eight is assigned when the transmit character length register equals zero. The length of characters
presented to the TDSR should not exceed the assigned character length. When the informationin the
TDSRis transmitted, the TBEMTY signalis again asserted to request another character. The setting
of TBEMTY also causes a transmit interrupt request if Transmit Interrupt Enableis set.
Byte count- or character-oriented protocols require the transmission of synchronizing information normally referred to as sync characters. The sync characters can be transmitted when Transmit Start of

Message (TDSR bit 8) is set. This happensin one of two ways dependmg on the state of the IDLE bit
(PCSAR bit 11). When the IDLE bitis cleared, the sync characteris taken directly from the common
'sync register (PCSAR bits 7-0). The sync register would have been previously loaded by the software.
If the IDLE bitis set, the sync character must be loaded into the TDSR by the software when it is to

be transmitted. If multiple sync characters are to be transmitted, the TDSR must only be loaded with

the first one of the sequence. This character will be transmitted until data information is loaded into
the TDSR. The TBEMTY signal is asserted at the end of each sync character but the TSOM signal
allows it to be ignored without causing a data late error.
3-20

With bit-oriented protocols, the USYNRT automatically generates control characters as initiated by
the software and inserts necessary information into the data stream to maintain transparency.

Typical programming examples in bit- and byte count-oriented protocols appear in Appendix D.
3.5

INTERRUPT VECTORS

The DPV11 generates two vector addresses, one for receive data and modem control and the other for
transmit data.

The receive and modem control interrupt has priority over the transmit interrupt and is enabled by
setting bit 6 (RXITEN) of the receiver control and status register (RXCSR).
If bit 6 of the RXCSR is set, a receiver interrupt may occur when any one of the following signals is

asserted.

®
®
®

Receive Data Ready (RDATRY)
Receive Status Ready (RSTARY)
Data Set Change (DAT SET CH)

The signal DAT SET CH only causes an interrupt if bit 5 (DSITEN) of the RXCSR is also set.

It is possible that a data set change interrupt could be pending while a receiver interrupt is being
serviced, or the opposite could be true. In either case, the hardware ensures that both interrupt
requests are recognized.

NOTE

The modem status change circuit interprets any
pulse of two microseconds or greater duration as a
data set change. This ensures that all legitimate
transitions of modem status will be detected. However, on a poor line, noise may be interpreted as a
data set change. Software written for the DPV11
must account for this possibility.

A transmitter interrupt request occurs if Transmit Interrupt Enable (TXINTEN) is set when Transmit
Buffer Empty (TBEMTY) becomes asserted.

3-21

CHAPTER 4

TECHNICAL DESCRIPTION
4.1

INTRODUCTION

This chapter provides a 2-level discussion of the DPV11. Paragraph 4.2 includes a description of the
DPV11 logic in functional groups at the block diagram level. At this level, a general operational overview is also discussed. The second level of discussion is the detailed description, which covers the complete DPV11 logic at the circuit schematic level, as shown in the DPV11 print set.
4.2
4.2.1

FUNCTIONAL DESCRIPTION
Logic Description

For discussion purposes, the DPV11 logic is divided into the ten sections shown in Figure 4-1. The

sections are described in Paragraphs 4.2.1.1 through 4.2.1.10.

4.2.1.1 Bus Transceivers — The interface for data, and address on the LSI-11 bus consists of four bus
transceiver chips (DC005). These function as bidirectional buffers between the LSI-11 bus and the
DPV11 Logic. These transceivers provide isolation, address comparison, and vector generation.

4.2.1.2 Read/Write Control — The read/write control logic consists of a DC004 protocol chip and its
associated logic. It provides the control signals for accessing registers and strobing data. It controls
reading from and writing into registers in both word and byte mode, and provides the deskew delays for
these operations. When data has been placed on or picked up from the LSI-11 bus or when vector
information has been placed on the LSI-11 bus, the read/write control logic notifies the processor by
asserting BRPLY.

4.2.1.3 USYNRT and Bidirectional Buffer - The USYNRT provides a large portion of the functionality of the DPV11. The USYNRT is installed in a socket for ease of replacement. It provides complete serialization, deserialization and buffering of data between the modem and the LSI-11 bus. The
USYNRT also provides logic support, via program parameter registers, for basic protocol handling and
error detection.

The tri-state bidirectional buffer provides the fan-out drive to accommodate the number of circuits the
USYNRT feeds.

4.2.1.4 Receive Control And Status Register (RXCSR) - This register contains most of the control
and status information pertaining to receiver operation, including the status of the lines to and from the
data set. The receive and data set interrupt enable bits are also contained in this register, but the receive interrupt enable is actually generated by the interrupt logic. The high byte of the RXCSR is
read-only and the low byte is read/write. RXCSR is both word- and byte-addressable.
4.2.1.5 Transmit Control And Status Register — This register is the low byte of the parameter control
and character length register (PCSCR). (The high byte is internal to the USYNRT). It contains most
of the control and status information pertaining to transmit operations. The maintenance mode bit is
also a part of this register. The register is read/write and can be accessed separately as the low byte of
the PCSCR or in word mode when the entire PCSCR is accessed.

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chip. The chip contains two interrupt channels: one for receive and one for transmit interrupts. The
circuit generates a receive interrupt when the Receiver Interrupt Enable bit (RXITEN) is set and one
of the following signals becomes asserted.
Receive Status Ready (RSTARY)
Receive Data Ready (RDATRY)
Modem Control Interrupt Request (MCINT)
MCINT requires that DSITEN (RXCSR bit 5) also be set.
If the Transmit Interrupt Enable bit (PCSCR bit 6) is set, a transmit interrupt is generated when the
Transmit Buffer Empty signal (TBEMTY) is asserted.
Receive interrupts have priority over transmit interrupts.

4.2.1.7 Data Set Change Logic — This logic is used to determine if the modem had a change in status.
Jumpers can be removed or installed to allow any or all of the following signals to set the Data Set
Change bit (RXCSR bit 15).

RS-232-C

RS-449

Clear to Send (CTS)

Carrier Detect (CD)

Receiver Ready (RR)

Data Set Ready (DSR)

Data Mode (DM)

Ring Indicator (RI)

Incoming Call (IC)

If the Data Set Interrupt Enable bit and Receiver Interrupt Enable (RXCSR bits 5 and 6) are both
set, Data Set Change causes the interrupt logic to generate an interrupt request.
4.2.1.8 Clock Circuit - The clock circuit consists of a 19.6608 MHz off-the-shelf oscillator and two
741.S390 dividers to provide the clock signals for the DPV11.

4.2.1.9 EIA Level Converters — These circuits contain drivers and receivers necessary for converting
from TTL levels to EIA levels and from EIA levels to TTL levels. There are drivers and receivers to
accommodate both RS-422-A (RS-449 compatible: limited to clock and data) and RS-423-A (RS-232C compatible) electrical standards. Selection of RS-422-A or RS-423-A interface standard is provided
by wire-wrap jumpers.
4.2.1.10 Charge Pump - This circuit converts the + 12 volts to a negative voltage to power the RS423-A drivers.
|

4.2.2 General Operational Overview
This discussion describes the relationships between the different sections of the block diagram from a
simplified operational viewpoint. It is assumed for the purpose of this discussion that the DPV11 will
be operated with the interrupts enabled. A simplified diagram which emphasizes the functions of the
USYNRT (Figure 4-2) is referenced for both the receive and transmit operations. Bit-oriented protocol
(BOP) and byte count-or character-oriented protocols (BCP) are not discussed in detail here.
4.2.2.1 Receive Operation — Serial data from the modem enters the EIA receiver where it is converted from EIA to TTL level. This TTL data is then presented directly to the receive serial input of

4-3

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the USYNRT. At the same time the EIA receiver converts the receive timing signal from the modem
to TTL level and presents it to the USYNRT. The USYNRT uses the timing signal to control the
assembling of the incoming data characters. As the information enters the USYNRT, sync-detect and
flag-detect circuits check for FLAG (BOP) or SYNC (BCP) until there is a match. When a match
occurs, assembling of data characters begins. Error circuits check for errors while the data is being
assembled. When a character is assembled in the receive data shift register, it is then transferred to the
receive data buffer, and the USYNRT timing and control logic generates the signal receive data ready
(RDATRY). Interrupt logic uses this signal to produce an interrupt request to the processor. When the
processor responds to the interrupt request, the interrupt logic causes the bus transceiver circuits to
assert the associated vector and the interrupt sequence takes place.
The processor now retrieves the data from the receive data buffer which resets the interrupt condition.
To do this the processor asserts the address of the buffer and the necessary control signals on the bus.
The bus transceivers recognize the address and enable the read/write control logic. The read/write
control logic then generates the necessary control signals to select and read from the receive data buffer (low byte of RDSR). Data in the buffer is sent through the bidirectional tri-state buffer to the LSI11 bus transceivers where it is enabled onto the LSI-11 bus and picked up by the processor. The USYNRT is double-buffered so that while the processor is picking up the character from the receive data
buffer, the receive data shift register is already assembling a second character. This process is repeated
until the entire message is received.

4.2.2.2 Transmit Operation - When the processor wishes to send data to the modem, it first places
the address of the transmit buffer (low byte of TDSR) and the necessary control signals on the LSI-11
bus.

The bus transceivers recognize the address and enable the read/write control logic which selects the
register. The processor then places the parallel data on the LSI-11 bus and the read /write control logic
gates it through the bus transceivers and writes it into the transmit buffer. When a character is written
into the transmit data buffer, the USYNRT transfers it to its transmit shift register and asserts
TBEMTY. Once the character is in the shift register, the USYNRT begins to serialize and send it by
means of the serial output line to the EIA drivers. Here it is converted from TTL to EIA level and sent
to the modem.

TBEMTY causes the interrupt logic to generate an interrupt request to the processor. At the completion of the interrupt sequence, the processor repeats the process of addressing the transmit buffer
and sending another character. This operation continues until the entire message has been sent.
4.3 DETAILED DESCRIPTION
The circuit operation is described in Paragraphs 4.3.1 through 4.3.9.
4.3.1

Bus Transceivers

Data, address and control signals move between the LSI-11 bus and the DPV11 by means of a group of
bus transceivers. The bus transceivers are contained in four DCO0O0S5 transceiver chips and perform the
following functions.
®
®
®

Address selection/decode
Data transfers to and from the LSI-11 bus
Vector generation

4.3.1.1 Address Selection - Each DPV11 is assigned four consecutive addresses that are decoded to
generate control signals to enable five registers in the DPV11. Four addresses are able to access five
registers because two of the registers (RDSR and PCSAR) share the same address. RDSR is a readonly register and PCSAR is a write-only register. Refer to Chapter 2 for address assignments.

4-5

When the software communicates with the DPV11, it does so by placing the address of the register it
wishes to access and the necessary control signals on the LSI-11 bus. The DPV11 checks the address to
see if it is within the range assigned to it. If so, access to the register is allowed. Paragraphs 4.3.1.2
through 4.3.1.4 describe the decoding of the address.

4.3.1.2 Address Decode — Address decoding is accomplished in the DC005 chips where a comparison
is made of the BDALO3 through BDALI12 lines wi:h the states selected by the address jumpers W29
through W39. (Refer to Chapter 2 for address selection and jumper connections). Each DC005 chip
looks at three address lines and compares each of them against a corresponding jumper connection.
When each address line agrees with its jumper input, the DC005 asserts pin 3 high. If all four DC005
chips have pin 3 asserted, the address on the bus is within the range assigned to this DPV11. When this
condition exists, the register decode circuit is enabled to allow access to the specific register being
addressed. Notice that BDALOO through BDALO2 are not used in the address compare. Line zero is
used in byte selection and lines one and two are used to select a particular register. Register selection
and byte operation are discussed in Paragraph 4.3.2.
4.3.1.3 Bus Data Transfers - Once the address has been accepted and access to the selected register
has been granted, data transfers can take place on the bus. The DC005 chips handle this function too.
Consider first the operation in which the processor is sending data to a register in the DPV11. In this
case, the DC005s would be placed in receive mode by a high on pin 4. This is a result of control signals
placed on the bus by the processor. In the receive mode, data on the BDALO through BDALI1S5 lines is
passed through the DC00S5 and made available to the register on the DAO through DA15 lines.

When the processor is requesting information from one of the DPV11 registers, the DC005s are placed
in transmit mode by a high on pin 5. In the transmit mode, data from the selected register is presented
to the DCO05s on the DAO through DA15 lines. The DCO005s then pass this data to the bus on the
BDALO through BDAL1S5 lines.
|
4.3.1.4 Vector Generation — A third function of the DCO005 chips is vector generation. This is accomplished by daisy-chain strapping W40 through W45 to W46 in the proper configuration for the vector
address desired. Refer to Chapter 2 for information on vector assignments and jumper connections.
W46 is high when the vector is to be sent to the processor. The signal VECTOR H is asserted by the
interrupt logic during an interrupt sequence. W45 corresponds to BDAL3 and W43 corresponds to
BDALS.
4.3.2 Read/Write Control Logic
|
The read/write control logic contains circuits for controlling register decoding, USYNRT operations,
and BRPLY. A description of each follows.
4.3.2.1
Register Decode (Figure 4-3) — The selection of individual registers within the DPV11 is accomplished by a DC004 protocol chip and its associated logic. This circuit is enabled by an address
match from the DC005s. When enabled, the DC004 decodes address lines 1 and 2 to produce one of
four select signals. These select lines, however, do not directly select the registers. Two registers share
the same address, one being a read-only and the other, a write-only register. One entire register and the
low byte of another are external to the USYNRT. For these reasons, additional gates are used with the
select lines to properly select the one register in five to be accessed. These gates use byte and write
signals to aid in the register selection. Table 4-1 shows the register selection based on the three loworder address bits.

NOTE
All registers can be accessed in either word or byte
mode. However, reading either byte of the RXCSR
resets certain status bits in both bytes.

4-6

Reading either byte of the RDSR resets data and
certain status bits in both bytes of this register as
well as bits 7 and 10 of the RXCSR.
NOTE

The address inputs to the DCO004 are inverted,
thereby causing a reverse order on the select lines.
Pin 17 corresponds to select 0 and pin 14 corresponds to select 6. This applies also to the OUTLB
(pin 13) and OUTHB (pin 12).

4.3.2.2 USYNRT Control - Most of the control signals for the USYNRT are generated by the
DCO004 and its associated logic. This paragraph describes the control signals and their functions.

ADRO, ADR1, and ADR?2 are used to select a register within the USYNRT. They are encoded as
shown in Table 4-2. ADRO is used in conjunction with BYTE OP to select a byte.

WRITE USYNRT is used to control writing into or reading from registers within the USYNRT.
When it is asserted, a write operation is indicated. When it is not asserted, a read operation is indicated. WRITE USYNRT is generated by ORing the OUTLB and OUTHB signals from the DC004.
OUTLB and OUTHB are used to write data into the low byte, high byte or both bytes of a selected
register. They are generated by the DC004 in response to the bus signals BWTBT, BDOUT, and
BDALO. OUTLB and OUTHB do not directly control byte selection for the USYNRT but are used to
generate ADRO and BYTE OP.

BYTE OP is used to indicate to the USYNRT that a byte operation is to be performed on the selected
register. It is generated during a write operation when either OUTLB or OUTHB but not both are
asserted.

DPENA (Data Port Enabled) is used to enable the tri-state data bus of the USYNRT and supply the
necessary timing for transactions between the USYNRT and the external circuits. DPENA strobes the
data for write or read operations. It is generated from the register select signals and the output of pin 8
of the DC004 chip which results directly from BDIN or BDOUT. Deskew delay is accomplished by
using a 74L.S164 serial to parallel shift register. Pin 8 of the DC004 is used as the serial input to the
shift register which is clocked by a 100 ns clock. Initially the serial input is high and the shift register
outputs are all high. 100 to 200 ns after the serial in goes low, DPENA becomes asserted to strobe the
USYNRT. DPENA remains asserted for at least 300 ns as determined by pin 10 of the shift register.
For read operations, DPENA will remain asserted until BDIN becomes not asserted. This is to ensure
that the data is on the bus when the processor strobes it. For write operations DPENA will be asserted
for 300 ns.

BRPLY (Bus Reply) indicates to the processor that the DPV11 has placed data on the bus or has
received data from the bus. It is generated from the same circuit as DPENA and is asserted 300 ns
after DPENA. BRPLY remains asserted until the processor responds by negating BDIN or BDOUT.
Figure 4-4 shows the timing for the generation of DPENA and BRPLY for a read operation. Figure 4-5
shows the timing for a write operation.
4.3.3

USYNRT, RXCSR, and PCSCR

Most of the registers used in the DPV11 are contained within the USYNRT. The receive control and
status register (RXCSR) and the low byte of the parameter control and character length register
(PCSCR) are external to the USYNRT. The USYNRT and the external registers are discussed in
Paragraphs 4.3.3.1 through 4.3.3.3.

4-7

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4-8

Table 4-1

0
0
0
0
1

0
0
1
1
0

0
1
0
1
0

RXCSR (word or low byte)
RXCSR (high byte)
RDSR (read) or PCSAR (write)
RDSR or PCSAR (high byte)
PCSCR (word or low byte)

1
1

0
1

TDSR (word or low byte)
TDSR (high byte)

Table 4-2

B SYNCL
REGISTER

SELE CTE

PCSCR (high byte)

USYNRT Register Select

ADR2

ADR1

0
0
1
1

0
1
0
1

RDSR (read only)
TDSR
PCSAR (write only)
PCSCR (high byte)

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4-9

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4.3.3.1
USYNRT - The universal synchronous receiver/transmitter (USYNRT) functions as a large
scale integration (LSI) subsystem for synchronous communications. The USYNRT provides the
logic
support, via program parameter registers, for basic protocol handling and error detection.
Protocol
handling by the USYNRT conforms to standards imposed by these protocols, but is slightly different

in each version of the USYNRT. The 5025 (2112517-00) is implemented in the DPV11. For
more
details on the USYNRT, refer to Appendix B or to A-PS-2112517-0-0 Purchase Specification.
4.3.3.2 Receive Control and Status Register (RXCSR) - The RXCSR is described in detail in Chapter 3. It is a buffer and line driver consisting of two 74L.S244 chips and one 74L.S174 hex D
flip-flop.
The low byte can be read or written into but the high byte can only be read. The write operation
occurs
on the positive transition of WREGQO. The register can be read when RREGO is asserted low.

4.3.3.3 Parameter Control and Character Length Register (PCSCR) - This register is described in
Chapter 3. Its upper byte is internal to the USYNRT and its low byte is external. Three bits (0, 3, and
4) of the low byte of this register are directly program-writable with bit zero being write-only. Bit 6 is

program writable but is a function of the interrupt circuit.

4.3.4 Interrupt Logic
Most of the logic for interrupts is contained in a single DC003 interrupt chip. The chip contains two
interrupt channels: one for receiver and modem control interrupts and one for transmitter interrupts.
The receive and modem control interrupt has the higher priority and may occur when receive interrupt
enable (RX INT ENA) is set and any of the following signals become asserted.
Receive Data Ready (RDATRY)
Receive Status Ready (RSTARY)
Data Set Change (DAT SET CH)

Notice that DAT SET CH requires that MC INT ENA (RXCSR bit 5) also be asserted.

4-10

When a register in the receive section (RXCSR or RDSR) is accessed; i.e., when servicing a receive
interrupt request, the receive interrupt request is disabled for 600 ns by the output on pin 5 of the
741.S74 flip-flop. This is done to ensure that any modem control interrupt request that might have
occurred while servicing the receive interrupt request,
is recognized. When the flip-flop is reset by the
600 ns signal, a negative to positive transition is recognized on pin 17 of the DC003 if a modem control
interrupt request is present.

A transmitter interrupt is generated by the DC003 if the TBEMTY
interrupt enable (bit 6 of PCSCR) is set.

signal is asserted when transmitter

Both the TX INT ENA and RX INT ENA bits are located physically in the DCO003 interrupt chip
although they are functionally part of the PCSCR and RXCSR respectively.
The bus interrupt request (BIRQ) is asserted by the DCO003 for either a receive or transmit interrupt
request. The processor responds to BIRQ by asserting BIAKI and BDIN. BIAKI is the interrupt acknowledge signal. It is passed down the priority chain until it reaches the section of the interrupt chip
that initiated the request.
When the interrupt logic receives both BDIN and BIAKI, it asserts the signal VECTOR. VECTOR
enables the assertion of the vector address by the DS005s. If the interrupt is a transmitter interrupt,
the RQSTB signal would assert vector address bit 2.
4.3.5

Data Set Change Circuit (Transition Detector)

The data set change circuit consists of a 74L.S273 D-register, exclusive NOR gates and two flip-flops.
Setting of the Data Set Change bit (DAT SET CH) is determined by the configuration of jumpers
W24 through W28. Any or all of the following modem signals can set DAT SET CH if its associated

jumper is installed.

RS-232-C

RS-449

Clear to Send (CTS)

Carrier Detect (CD)

Receiver Ready (RR)

Data Set Ready (DSR)

Data Mode (DM)

Ring Indicator (RI)

Incoming Call (IC)

The modem change circuit interprets any pulse of
two microseconds or greater duration as a modem
status change. This ensures that all legitimate
modem status changes will be detected. However, on
a poor line, noise may be interpreted as a modem
status change. Software written for the DPV11
must account for this possibility.
4.3.6

Clock Circuit

The clock circuit consists of an off-the-shelf 19.6608 MHz crystal oscillator, and two 74L.S390

counters. The 19.6608 MHz signal is divided by the counter circuits to produce the following four

clock signals.

LOCAL CLK (49.152 kHz) — Normally jumpered to NULL MODEM CLK (W18 and

W21) and used as the data clock.

4-11

DIAG CLK (1.9661 kHz) — Nonsymmetrical clock available for diagnostic purposes (not
recommended for local communications). It becomes the transmit clock when the DPV11 is
placed in diagnostic mode. DIAG CLK can also be jumpered to LOCAL CLK for 50 kHz

operation but some of the tests must be omitted.

SR CLK (9.8304 MHz) — Used to clock the shift register to establish delays for DPENA
and BRPLY.

Charge PUMP CLK (491.52 kHz) — Used by the charge pump circuit and transition detector.

4.3.7 USYNRT Timing - USYNRT timing for the transmit and receive sections originates with the
modem and is gated through the AND-OR inverter to the USYNRT.
During normal receive data transfers, the 74LS51 gates receiver timing from the modem as receive
clock pulse (RCP) to the USYNRT. If the modem clock stops with the last valid data bit, Receiver
Ready becomes not asserted. The next positive transition of the NULL MODEM CLK causes 74L.S74
pin 8 to go high, thus substituting NULL MODEM CLK for modem receive timing. In this way, the
USYNRT receives the necessary 16 clock pulses to complete its operation after the modem has
stopped sending.

During normal transmit data transfers, timing for the USYNRT is gated from the modem through the
74LS51 pin 6 to the USYNRT.

In maintenance mode, the signal MSEL disables the modem timing and enables the DIAG CLK as the

clock for the USYNRT.

4.3.8 EIA Receivers
26L.S32 quad differential line receivers are used to accept signals and data from the modem. Jumpers
W12 through W17 are terminating resistors which may be connected for RS-422-A but must be disconnected for RS-423-A.
4.3.9

EIA Drivers

Two types of drivers are used to send signals and data to the modem. 9638 drivers are used for RS-422A and 9636 drivers are used for RS-423-A.
4.3.10 Maintenance Mode
The USYNRT is placed in maintenance mode by setting Maintenance Mode Select (bit 3 of the
PCSCR). When this happens, the serial output of the transmit section is internally looped back as
serial input and the transmit serial output is held asserted. All clocking of both the receive and transmit sections is controlled by the transmitter clock input. This signal is derived from the 2 kHz clock as
determined by the 74L.S51 AND-OR inverter.

4-12

CHAPTER 5
MAINTENANCE
5.1

SCOPE

This chapter provides a complete maintenance procedure for the DPV11 and includes a list of required
test equipment and diagnostics. The maintenance philosophy and procedures for preventive and corrective maintenance are discussed.

5.2 TEST EQUIPMENT RECOMMENDED
Maintenance procedures for the DPV11 require the test equipment and diagnostic programs listed in
Table 5-1.

Table 5-1

Test Equipment Recommended

Equipment

Manufacturer

Designation

Multimeter

Triplett or Simpson

Model 630-NA or 260 or
equivalent

Oscilloscope

Tektronix

Type 453 or equivalent

X10 Probes (2)

Tektronix

P6008 or equivalent

Module extenders

DIGITAL

Cable turn-around

DIGITAL

H3259

DIGITAL

H3260

W984 (double)

connector

On-board test
connector

Breakout box

IDS

LIB kit

DIGITAL

ZJ314-RB

Document only

ZJ314-RZ

Document and
paper tape

ZJ314-RB

Paper tape only
Fiche

ZJ314-PB
ZJ314-FR

5.3 MAINTENANCE PHILOSOPHY
The basic approach to DPV11 fault isolation is the use of stand-alone diagnostic programs and maintenance mode features supported by the hardware.
Typical applications of the DPV11 do not allow lengthy troubleshooting sessions; therefore, the maintenance philosophy in the field is module swapping. The defective module is returned to the factory for repair.

5.4

PREVENTIVE MAINTENANCE

5.5

CORRECTIVE MAINTENANCE

There is no scheduled preventive maintenance for the DPV11. Preventive maintenance for the DPV11
is integrated into its corresponding system preventive maintenance and consists of checking the power
supply voltage. Whenever the module or cables have been disturbed, diagnostics (specifically
DEC/X11 and DCLT) should be run to verify proper operation.

Since the field replaceable units are the M8020 and the cables, all diagnosis should be directed to
isolation of one of these components.

NOTE
The operating jumper configuration of the DPV11
module being serviced should be recorded prior to
any changes for maintenance purposes. This will facilitate reconfiguring the module when the service activity is complete.

5.5.1

Maintenance Mode

To aid in troubleshooting, the DPV11 has a software-selectable maintenance mode which causes the
serial output of the USYNRT to be internally connected to its serial input. When in maintenance
mode, serial data from the modem is disabled and the send and receive timing from the modem are
replaced with a clock signal generated on the M8020 module. The clock rate is 2K b/s.

The diagnostics normally operate with and without the Maintenance Mode Select (MSEL)’ bit set. In
this way the USYNRT chip can be isolated from the remainder of the circuitry.
5.5.2

Loopback Connectors

The cable loopback connector shipped with the DPV11-DB (bundled version) is the H3259. This connector is connected to the modem end of the BC26L cable when it is used. No cables or test connectors
are shipped with the DPV11-DA (unbundled versions). An on-board connector (H3260) can be purchased separately (see Paragraph 2.5 and Figure 2-4) for connecting to J1 on the M8020 module. It

provides for testing of all M8020 logic.
5.5.3

Diagnostics

DPV11 diagnostics aid in the isolation process and should be run when a malfunction is indicated.
Diagnostics should also be run to verify operation after repair.

NOTE
To ensure that all M8020 logic circuits are checked, on-board test connector H3260 must be used.
However, the DPV11 system cannot be assumed to
be thoroughly checked unmless the DIGITAL-supplied cable is also tested.

Diagnostics must be run with a cable turn-around
connector (H3259) at the modem end of the
BC26L-25 cable.
5-2

The following diagnostics are available to aid in the isolation and verification process.

3.5.3.1 CVDPV* Functional Diagnostic - CYDPV* is designed to verify the functionali
ty of the
DPV11. No resolution to the chip is intended. CVDPV* is a stand-alone program that
must be executed under control of the PDP-11 diagnostic supervisor (DS). Errors are reported as they
occur in the
program, unless they are inhibited, and conform to the DS error report format. For
information on
loading and running of the DS, see Appendix A.

CVDPV* is campatiblé: with XXDP+, ACT/SLIDE, APT or ABS. It consists of a number of tests

which function as follows.

Test No.

Description

Verificsfi that addressing the RXCSR does not cause a nonexistent memory trap.

V:rifics that the DPV11 may be properly initialized by a Master Clear or LSI-11 Re-

set.

Writes and reads data pattcrns into all writable bits to verify bit validity and address-

ing paths.

Enables and ensures @hat the transmitter is activated.

Verifies that TBEMTY is asserted and cleared properly for all possible conditions.

Verifies proper operation of the transmit interrupt.

Enables and ensures that the receiver is activated, and RDATRY is asserted properly.

Verifies proper operation of the receive interrrupt for the reception of data.

Verifies proper operation of RSTARY for all possible conditions.

Verifies proper operaticm of the receive interrupt for status.

Ensures that both transmit and receive interrupts are recognized.

Verific§ proper operation of all modem status bits and ensures that DSCNG is set when

a transition occurs.

Verifies that an interrupt is received when DSCNG is set.

Verifies that if a DSCNG occurs during a receive interrupt, it will be recognized
.

15-20

Verifies proper operation with bit-oriented protocols (BOP).

21-23

Verifies proper operation with byte count-oriented protocols (BCP).

24-28

Verifies CRC and VRC functions.

Verifies maintenance mode noninterrupt data operations.

30-36

Verifies BOP data operation.

37-40

Verifies BCP data operation.

Verifies DDCMP message protocol and message transmission.

Verifies high-speed BCP data operation.

Verifies high-speed BOP data operation.

5.5.3.2

DEC/ X11 CXDPV Module - CXDPV exercises up to six consecutwely addressed DPVII

synchronous interfaces as they relate to the total system configuration. It is very usefulin determining
whether a DPV11 is the failing component among other system components in a system environment.
Itis a system exerciser and does not operate as a stand-alone test. It must be configured and run as
part of a total system exerciser.

The DEC/X11 System Exerciser must be run after the stand-alone diagnostic CVDPV* has been run.
It determines if the DPV11 or another device adversely affects the total system operation. For more
information on DEC/X11, refer to the DEC/X11 User Manual (AC-FOSBB-MC) and DEC/X1I

Cross-Reference (9AC-F055C-MC)

5.5.3.3 Data Communications Link TestCVCLH* (DCLT) - DCLT is a communications equipment
maintenance tool designed to isolate failures to either the interface, the telephone communication line,

or the modem. It exercises DPV11 to DPV11 links.

DCLTis XXDP+ or APT compatible and runs under control of the diagnostic supervisor (DS) (see
Appendix A). It requires 24K of memory. For more information on DCLT refer to CVCLH* document AC-F582A-MC.

APPENDIX A
DIAGNOSTIC SUPERVISOR SUMMARY

‘A1 INTRODUCTION

The PDP-11 diagnostic supervisor is a software package that performs the following functions.

A.2

Provides run-time support for diagnostic programs running on a PDP-11 in stand-alone mode

Provides a consistent operator interface to load and run a single diagnostic program or a
script of programs

Provides a common programmer interface for diagnostic development

Imposes a common structure upon diagnostic programs

Guarantees compatibility with various load systems such as APT, ACT, SLIDE, XXDP+,
ABS Loader

Performs nondiagnostic functions for programs, such as console 1/0, data conversion, test
sequencing, program options

VERSIONS OF THE DIAGNOSTIC SUPERVISOR

File Name

Environment

HSAA **SYS

XXDP+

HSAB **.SYS

APT

HSAC **.SYS

ACT/SLIDE

HSAD **.SYS

Paper Tape (Absolute Loader)

In the above file names, “**” stands for revision and patch level, such as “A0”.
A.3 LOADING AND RUNNING A SUPERVISOR DIAGNOSTIC
A supervisor-compatible* diagnostic program may be loaded and startedin the normal way, using any
of the supported load systems. Using XXDP+ for example, the program CVDPVA.BINis loaded and
started by typing .R CVDPVA.

The diagnostic and the supervisor will automatically be loaded as shown in Figure A-1 and the program started. The program types the following message.

DRS LOADED
DIAG.RUN-TIME SERVICES
CVDPV-A-0
* To determine if diagnostics are supervisor-compatible, use the List command under the Setup utility (see Paragraph A.5.).

A-1

XXDP+/ DIAGNOSTIC SUPERVISOR MEMORY LAYOUT

ON A 16KW (MIN MEMORY) SYSTEM
ADDRESS

100000 (0)
XXDP+

070000 (0)

DIAGNOSTIC
SUPERVISOR
( 6KW)

040000 (0)

DIAGNOSTIC
PROGRAM

( 7.5KW)

002000 (0)

000000 (0)
MK-2216

Figure A-1

Typical XXDP+ /Diagnostic Supervisor Memory Layout

DIAGNOSTIC TESTS
UNIT IS DPV11
DR>
DR> is the prompt for the diagnostic supervisor routine. At this point a supervisor command must be
entered (the supervisor commands are listed in Paragraph A.4).
Five Steps to Run a Supervisor Diagnostic
1.

Enter Start command.

When the prompt DR> is issued, type:
STA/PASS:1/FLAGS:HOE <CR>
The switches and flags are optional.
2.

Enter number of units to be tested.

The program responds to the Start command with:

# UNITS?
At this point enter the number of devices to be tested.
A-2

Answer hardware parameter questions.

After the number of devices to be tested has been entered, the program responds by asking a

number of hardware questions. The answers to these questions are used to build hardware
parameter tables in memory. A series of questions is posed for each device to be tested. A
“Hardware P-Table” is built for each device.
Answer software parameter questions.

When all the “Hardware P-Tables’ are built, the program responds with:
CHANGE SW?

If other than the default parameters are desired for the software, type Y. If the default parameters are desired, type N.

If you type Y, a series of software questions will be asked and the answers to these will be
entered into the “Software P-Table” in memory. The software questions will be asked only
once, regardless of the number of units to be tested.
Diagnostic execution.

After the software questions have been answered, the diagnostic begins to run.
What happens next is determined by the switch options selected with the Start command, or
errors occurring during execution of the diagnostic.
A.4

SUPERVISOR COMMANDS

The supervisor commands that may be issued in response to the DR> prompt are as follows.
Start — Starts a diagnostic program.

Restart — When a diagnostic has stopped and control is given back to the supervisor, this
command restarts the program from the beginning.

Cantinué — Allows a diagnostic to continue running from where it was stopped.
Proceed — Causes the diagnostic to resume with the next test after the one in which it halted.

Exit — Transfers cohtml to the XXDP-+ monitor.
Drop — Drops units specified until an Add or Start command is given.

Add - Adds finits specified. These units must have been previously dropped.
Print — Prints out statistics if available.
Display — Displays P-Tables.

Flags — Used to change flags.
ZFLAGS - Clears-flags.

All of the supervisor comma‘nds except Exit, Print, Flags, and ZFLAGS can be used with switch options.

A-3

A.4.1 Command Switches
Switch options may be used with most supervisor commands. The available sw1tches and their function
)
are as follows.

./TESTS:
— Used to specify the tests to be run (the defaultis all tests) An example of the
tests switch used with the Start command to run tests 1 through 5, 19, and 34 through 38
would be:

DR> START/TESTS : 1-5 : 19 : 34-38 <CR>
./PASS: — Used to specify the number of passes for the diagnostic to run. For example:
DR> START/PASS : 1
In this example, the diagnostic would complete one pass and give control back to the superVISOr.

./EOP:
— Used to specify how many passes of the diagnostic will occur before the end of pass
message is printed (the defaultis one).
|
|
./UNITS: — Used to specify the units to be run. This switch is valid only if N was entered in
response to the CHANGE HW? question.

./FLAGS:
— Used to check for conditions and modify program execution accordmgly The
conditions checked for are as follows.

:HOE —Halt an error (transfcrs control back to‘ the supervisof)
:LOE - Loop on error
:IER — Inhibit error reports

:IBE — Inhibit basic error information

:IXE — Inhibit extended error infofniation

:PRI{-_ Print crrbrs on li’ne printer
:PNT - Print the number of the test being executed prior to cxecutibn
:BOE - Ring bell on error

:UAM - Run in unattended mode, by‘pass manual intervention tests

:ISR - Inhibit statistical reports

:IOU - Inhibit dropping of units by program

A.4.2 Control /Escape Characters Supported

The keyboard functions supported by the diagnostic supervisor are as follows.
®

CONTROL C (TC) — Returns control to the supervisor. The DR> prompt would be typed in
response to CONTROL C. This function can be typed at any time.

CONTROL Z (]Z) - Used during hardware or software dialogue to terminate the dialogue

CONTROL O (JO) - Disables all printouts. This is valid only during a printout.

CONTROL S (IS) — Used during a printout to temporarily freeze the printout.

CONTROL Q (JQ) — Resumes a printout after a CONTROL S.

and select default values.

A.5 THE SETUP UTILITY
Setup is a utility program that allows the operator to create parameters for a supervisor diagnostic
prior to execution. This is valid for either XXDP+ or ACT/SLIDE environments. Setup asks the
hardware and software questions and builds the P-Tables.

The following commands are available under Setup.
List — list supervisor diagnostics
Setup — create P-Tables
Exit — return control to the supervisor
The format for the List command is:

LIST DDN:FILE.EXT

Its function is to type the file name and creation date of the file specified if it is a revision C or later

supervisor diagnostic. If no file name is given, all revision C or later supervisor diagnostics are listed.
The default for the device is the system device, and wild cards are accepted.

The format for the Setup command is:

SETUP DDN:FILE.EXT=DDN:FILE.EXT
It reads the input file specified and prompts the operator for information to build P-Tables. An output
file is created to run in the environment specified. File names for the output and input files may be the
same. The output and input device may be the same. The default for the device is the system device
and wild cards are not accepted.

APPENDIX B

USYNRT DESCRIPTION

5025 Universal Synchronous Receiver/Transmitter (USYNRT)
The data paths of the USYNRT provide complete serialization, deserialization and buffering. Output
signals are provided to the USYNRT controller to indicate the state of the data paths, the command
fields or recognition of extended address fields. These tasks must be performed by the USYNRT controller.

The USYNRT is a 40-pin dual-in-line package (DIP). Figure B-1 is a terminal connection (identification) diagram.
|

Data port bits DP07:DPO0O are dedicated to service four 8-bit wide registers. Bits DP15:DP08 service
either control information or status registers. The PCSCR register is reserved. (See Figure B-2.)

Purchase Specification 2112517-0-0 provides a detailed description of the 5025 USYNRT.

B-1

RSI

RXCLK

TXCLK

TXENA

TSO| 38

TBEMTY

TXACT

TERR

RDATRY

RSTARY

RXACT

SYNC +

RXENA
ADR COMP

DP 15

DP 14
23

DP 13

DPENA

DP 12
DP 11

DP 10
19

ADR SEL 2

ADR SEL 1

ADR SEL O

BYTE GP

WR TO LSI

MAINT SEL

RESET

DP 09

DP 08|

BIDIRECTIONAL

DP 07

/O TRI STATE

LINES

DO 06
DP 05

DP 04
DP 03
DP 02

DP O1
DP OO

GND

Vcc

VpD

09‘

32‘

01‘

+12

_)
NOTE: A) PIN 32 +5V POWER SUPPLY
*+10% AT 100mA.

B) PIN 01 +12V POWER SUPPLY
+10% AT 100mA.

C) PIN 9 = GROUND
MK-1415

Figure B-1

Terminal Connection Identification Diagram (2112517-0-0 Variation)

DP15

FhA

ASSY BIT ACCOUNT

CHK

| rRo

R/O

ABORT

OVER
1
RUN

"or | Reom | msom

RO | RO | RO

R/IO

mo | RO

R/O

DPOO

DATA

R/O

R/IO

R/O

RDSR

TERR

TGA

R/O

R/W

R'W

rRw |

| TABORT|

DATA.

R/O
ADRO

TEOM |

TSom

R/W

RwW

TDsR

| RW |

MK-1502

Figure B-2

5025 Internal Register Bit Map (2112517-0-0 Variation) (Sheet 1 of 2)

viooe | STRIP |

ADRS

mope |

SEL

l«——ERR TYPE SEL—»

SYNC

R/O

- OR"—
TX RX SYNC

RX SEC ADRS

R/W

R'W

R/W

RIW

R/W

ADR4

|«— TS DATA LEN SEL—»| EXADD | EXCON {«——RX DATA LEN SEL——»
02
R'W

01
|

R/W

00
|

R/W

RESERVED

PCSCR

ADR 6
MK-1503

Figure B-2

5025 Internal Register Bit Map (2112517-0-0 Variation) (Sheet 2 of 2)

APPENDIX C
IC DESCRIPTIONS
C.1

GENERAL

This appendix contains data on the LSI-11 chips and some of the unusual ICs used by the DPV11. The
other ICs are common, widely-used logic devices. Detailed specifications on these chips are readily
available, and hence are not included here.
The interrupt chip is an 18-pin DIP device. It provides the circuits to perform an interrupt transaction
in a computer system that uses a “pass-the-pulse” type arbitration scheme. The device provides two
interrupt channels labeled A and B, with the A section at a higher priority than the B section. Bus
signals use high-impedance input circuits or high-drive open-collector outputs, which allow the device
to directly attach to the computer system bus. Maximum current required from the V¢ supply is 140
mA.

Figure C-1 is a simplified logic diagram of the DC003 IC. Table C-1 describes the signals and pins of
the DCO003.

DC003

17|

RasTAH

ENA DATA H

ENASTH

sira L 10-28

141 ENACLKH
— 97 o BiakiL
9

o BINITL

03 ] BDIN L

ENB DATAH

—

RQSTB H

BIAKO L

INTO L

VEC RQSTB H

|—22

ENB ST H

f——

VECTORH Y

131 ENBCLKH
12_|

|—18

MK 0164

Figure C-1

DCO003 Logic Symbol
C-1

Table C-1

DCO003 Pin/Signal Descriptions

Signal

Description

VECTOR H

Interrupt Vector Gating Signal — This signal gates the appropriate vector address onto the bus and forms the bus signal
BRPLY L. Not used in the DPV11.

VEC RQSTB H

Vector Request B Signal — When asserted, this signal indicates
RQST B service vector address is required. ‘When negated, it
indicates RQST A service vector addressis required. VECTOR
H is the gating signal for the entire vector address VEC RQST
B H is normally bit 2 of the address.
@~

BDIN L

Bus Data In— THE BDIN sngnal always precedes a BIAK signal.

INITOL

Initialize Out — This is the buffered BINIT L signal used in the
device interface for general initialization.

BINIT L

Bus Initialize — When asserted, this signal brings all drive lines
to their negated state (except INITO L).

BIAKO L

Bus Interrupt Acknowledge — This signal is the daisy-chained
sngnal thatis passed by all devices not requesting interrupt service (see BIAKI L). Once passcd by a device, it must remain
passed until a new BAIKI L is generated.

BIAKI L

Bus Interrupt Acknowledge — This mgnalis the processor’s response to BIRQ L true. This signal is daisy-chained such that
the first requesting device blocks the signal propagation while
nonrequesting devices pass the signal on as BIAKO L to the
next device in the chain. The leading edge of BIAKI L causes
BIRQ L to be unasserted by the requesting device.

BIRQL

Asynchronous Bus Interrupt Request — The request is generated
by a true RQST signal along with the associated true Interrupt
Enable signal. The request is removed after the acceptance of
the BDIN L signal and on the leading edge of the BAIKI L signal, or the removal of the associated interrupt enable, or due to
the removal of the associated request signal.

17
10

RQSTA H
RQSTB H

Device Interrupt Request Signal — When asserted with the enable A/B flip-flop asserted, this signal causes the assertion of
BIRQ L on the bus. This signal line normally remains asserted
until the request is serviced.

16
11

ENA ST H
ENB ST H

Interrupt Enable — This signal indicates the state of the inter-

rupt enable A/B internal flip-flop whichis controlled by the signal line ENA/B DATA H and the ENA/B CLK H clock line.

C-2

Table C-1

DCO003 Pin/Signal Descriptions (Cont)

Signal

Description

15
12

ENA DATA H
ENB DATA

Interrupt Enable Data — The level on this line, in conjunction
with the ENA/B CLK H signal, determines the state of the internal interrupt enable A flip-flop. The output of this flip-flop is
monitored by the ENA/B ST H signal.

14
13

ENA CLK H
ENB CLK H

Interrupt Enable Clock — When asserted (on the positive edge),
interrupt enable A/B flip-flop assumes the state of the ENA/B
DATA H signal line.

C.3 DC004 PROTOCOL CHIP
The protocol chip is a 20-pin DIP device that functions as a register selector, providing the signals
necessary to control data flow into and out of up to four word registers (8 bytes). Bus signals can
directly attach to the device because receivers and drivers are provided on the chip. An RC delay
circuit is provided to slow the response of the peripheral interface to data transfer requests. The circuit
is designed such that if tight tolerance is not required, then only an external 1K X 20 percent resistor is

necessary. External RCs can be added to vary the delay. Maximum current required from the V¢ supply
is 120 mA.

Figure C-2 is a simplified logic diagram of the DC004 IC. Signal and pin definitions for the DC004
are shown in Table C-2.

C.4 DC005 BUS TRANSCEIVER CHIP
The 4-bit transceiver is a 20-pin DIP, low-power Schottky device for primary use in peripheral device
interfaces, functioning as a bidirectional buffer between a data bus and peripheral device logic. In
addition to the isolation function, the device also provides a comparison circuit for address selection
and a constant generator, useful for interrupt vector addresses. The bus I/O port provides high-impedance inputs and high-drive (70 mA) open-collector outputs to allow direct connection to a computer’s
data bus. On the peripheral device side, a bidirectional port is also provided, with standard TTL inputs
and 20 mA tri-state drivers. Data on this port is the logical inversion of the data on the bus side.

Three address jumper inputs are used to compare against three bus inputs and to generate the signal
MATCH. The MATCH output is open-collector, which allows the output of several transceivers to be
wire-ANDed to form a composite address match signal. The address jumpers can also be put into a
third logical state that disconnects that jumper from the address match, allowing for “don’t care” address bits. In addition to the three address jumper inputs, a fourth high-impedance input line is used to
enable/disable the MATCH output.
Three vector jumper inputs are used to generate a constant that can be passed to the computer bus.
The three inputs directly drive three of the bus lines, overriding the action of the control lines.
Two control signals are decoded to give three operational states: receive data, transmit data, and disable.

VECTOR H []1

20[J Vce

BDAL2[C]2

BDAL 1[]3

5C004

BDALO[]4

18[_JRXCX H
17JSEL6 L

BWTBT L[]5

16 JSEL4 L

BSYNC L[]6

15[JSEL2
L

BDINL[]7

14 JSELO
L

BRPLY L[]8

13[JOUTHB L

BDOUT L[]9

12[JOUTLB L

GND []10
e AAA
ENB H|19

JENB H

11[JINWD L

e +V O C
1

D
ENB

LATCH

BDAL2 L}02

ENB

SYNC D

| GND

DECODER

17|SEL6 L

16|SEL
4 L

15|SEL2 L

—{14|SELO
L

LATCH
s
0

BDALO L}04

DAL 2

0O
BDAL1 L}03

LATCH

DAL
1

— [P
00

L
LATCH

BWTBT L

13JOUTHB L

12]OUTLB L

18]RXCX H

),
BDOUT L

BDIN L

T1INWD L
MK-0171

Figure C-2

DC004 Simplified Logic Diagram

C-4

ignal Descriptions

Signal

VECTOR H

Vector — This input causes BRPLY L to be generated through
the delay circuit. Independent of BSYNC L and ENB H.

2
3
4

BDAL2 L
BDALI1 L
BDALO L

Bus Data Address Lines — These signals are latched at the assert
edge of BSYNC L. Lines 2 and 1 are decoded for the select outputs; line 0 is used for byte selection.

BWTBT L

Bus Write/Byte — While the BDOUT L input is asserted, this
signal indicates a byte or word operation: asserted = byte, unas-

serted = word. Decoded with BDOUT L and latched BDALO
L, BWTBT L is used to form OUTLB L and OUTHB L.
6

BSYNC L

Bus Synchronize — At the assert edge of this signal, address information is trapped in four latches. While unasserted, this signal disables all outputs except the vector term of BRPLY L.

BDIN L

Bus Data In — This is a strobing $ignal to effect a data input

BRPLY L

Bus Reply — This signal is generated through an RC delay by
VECTOR H, and strobed by BDIN L or DBOUT L, and
BSYNC L and latched ENB H.

BDOUT L

Bus Data Out — This is a stobing signal to effect a data output
transaction. Decoded with BWTBT L and BDALO, it is used to
form OUTLB L and OUTHB L. BDOUT L generates BRPLY
L through the delay circuit.

INWDL

transaction. BDIN L generates BRPLY L through the delay circuit and INWD L.

In Word — Used to gate (read) data from a selected register onto

the data bus. It is enabled by BSYNC L and strobed by BDIN
L.

OUTLB L

Out Low Byte, Out High Byte — Used to load (wriie) data into

OUTHB L

the lower, higher, or both bytes of a selected register. It is enabled by BSYNC L and the decode of BWTBT L and latched
BDALO L. It is strobed by BDOUT L.

14
15
16
17

SELO L
SEL2 L
SEL4 L
SEL6 L

Select Lines — One of these four signals is true as a function of
BDAL2 L and BDAL1 L if ENB H is asserted at the assert
edge of BYSNC L. They indicate that a word register has been
selected for a data transaction. These signals never become as-

serted except at the assertion of BSYN L (then only if ENB H
is asserted at that time) and, once asserted, are not negated until
BSYNC L is negated.

RXCX

External Resistor Capacitor Node — This node is provided to
vary the delay between the BDIN L, BDOUT L, and VECTOR
H inputs and BRPLY L output. The external resistor should be
tied to V¢ and the capacitor to ground. As an output, it is the
logical inversion of BRPLY L.

C-5

Table C-2

Signal

ENB H

DC004 Pin/Signal Descriptions (Cont)

Description
"

Enable — This signal is latched at the asserted edge of BSYNC
L and is used to enable the select outputs and the address term
of BRPLY L.

Maximum current required from the V. supply is 100 mA.
Figure C-3is a simplified logic diagram of the DCOOS IC. Signal and pin definitions for the DCO005
are shownin Table C-3.

C.5 26LS32 QUAD DIFFERENTIAL LINE RECEIVER
The 26L.S32 line receiver is a 16-pin DIP device. Terminal connections are shownin Fxgure C-4.
C.6 8640 UNIBUS RECEIVER
The 8640 is a quad 2-input NOR. Its equivalent circuit is shown in Figure C-5.
C.7 8881 NAND
The 8881 is a quad 2-input NAND. The schematic and pin ldentlficatlons are shownin Figure C-6.

C.8 9636A DUAL LINE DRIVER
The 9636Ais an 8-pin DIP device specified to satisfy the requirements of EIA standards RS-423-A and
RS-232-C. Additionally, it satisfies the requirements of CCITT V.28, V.10 and the federal standard
FIPS 1030.
|
The output slew rates are adjustable by a single external resistor connected from pin 1 to ground.

The logic diagram and terminal identification are shown in Figure C-7.
C.9 9638 DUAL DIFFERENTIAL LINE DRIVER
The 9638is an 8-pin DIP device specified to satisfy the requirements of EIA RS-422-A and CCITT
V.11 specifications.

The logic diagram and terminal identification are shown in Figure C-8.

C-6

DC005 TRANSCEIVER

JATL

JA2L

- 20 Ve

19 JA3 L

— 18 DATO H

MATCH H 3 -

- 17 DAT1 H

4 -

RECH

DAT3H

XMITH 56--

JV3H
16
_ 15 Jv2 H

BUS3L 8-

| 13 MENB L

- 14 V1 H

DAT2H 7

)

12 BUSO L

BUSZL 9-

GND

Buso

L [12}

Bust

L [11]

11 BUST L

10—

JA1

BUS2

JA2

:{\m DAT3

BUS3
JA3

“

Mol

il ‘

MATCH

)

= ‘D
MENB L @T—

[20}— vee
Figure C-3

(10— GND

MK-0170

DCO005 Simplified Logic Diagram

C-7

Table C-3

DCO005 Pin/Signal Descriptions

Signal

Description

12
11
9
8

BUSOL
BUS 1L
BUS2L
BUS 3 L

Bus Data
— This set of four lines constitutes the bus side of the
transceiver. Open-collector output high-impedance inputs. Low
= 1.

18
17
7
6

DATO H

Peripheral Device Data — These four tri-state lines carry the inverted received data from BUS (3:0) when the transceiver is in
the receive mode. Whenin transmit data mode, the data carried
on these linesis passed inverted to BUS (3:0). Whenin the dis-

14
15
16

JV1H
JV2H
JV3IH

DAT1 H
DAT2 H
DAT3 H

abled mode, these lines go open (high impedance). High
= 1.

Vector Jumpers — These inputs, with internal pull-down resistors, directly drive BUS (3:1). A low or open on the jumper pin
causes an open condition on the corresponding BUS pin if
XMIT H is low. A high causes a one (low) to be transmitted on
the BUS pin. Note that BUS 0 L is not controlled by any jumpr
input.

MENB L

Match Enable — A low on this line enables the MATCH output.

MATCH H

Address Match—When BUS (3:1) matches Wlth the state of JA

1
2
19

JA1L
JA2L
JA3L

Address Jumpers — A strap to ground on these inputs allows a
match to occur with a one (low) on the corresponding BUS line;
an open allows a match with a zero (high); a strap to Vm disconnects the corresponding address bit from the comparison.

5
4

XMIT H
REC H

Control Inputs — These lines control the operational of the transceiver as follows.

A high forces MATCH low, overriding the match circuit.

(3:1) and MENB L is low, this output is opcn otherwise, it is
low.

REC XMIT

0
0
1
1

0
1
0
1

DISABLE: BUS and DAT open
XMIT DATA: DAT to BUS
RECEIVE: BUS to DAT
RECEIVE: BUS to DAT

To avoid tri-state overlap conditions, an internal circuit delays
the change of modes between Transmit data mode, and dclays
tri-state drivers on the DAT lines from enablmg This actmn is
independent of the disable mode.

fiWWW_L+

:jn

NOTE: PIN 1 IS MARKED FOR ORIENTATION. NUMBERS INDICATED DENOTE TERMINAL NUMBERS.

TERMINAL IDENTIFICATION
1.INPUT A

16. POSITIVE SUPPLY VOLTAGE (Vce)

2. INPUTA

15. INPUT B

3. 0UTPUTA
4. ENABLE

14 INPUT B
13.OUTPUT B

5. QUTPUTC

12. ENABLE

6. INPUTC

7.INPUTC

8. GROUND

11. OUTPUT D

10. INPUTD

9. INPUTD
MK-1340

Figure C-4

26LS32 Terminal Connection Diagram and Terminal Identification

C-9

)

Vee = PIN 8
GND = PIN 1
MK-1321

Figure C-5

VCC

8640 Equivalent Logic Diagram

]

3A
||

Iy,

1 l‘—

2 [1 3

[]| 5

6 [| 7
2B

GND
MK-1322

Figure C-6

8881 Pin Identification

C-10

(1)

(5)

(2)

(6}

(3)

NOTE: NUMBERS IN () DENOTE TERMINAL NUMBERS.
TERMINAL IDENTIFICATION

{1) WAVESHAPE CONTROL (RISE AND FALL TIME)
(2) INPUT A
(3) INPUT B
(4) POWER AND SIGNAL GROUND

(5) NEGATIVE SUPPLY VOLTAGE
(6) OUTPUT B

(7) OUTPUT A
(8) POSITIVE SUPPLY VOLTAGE (V)
MK-1323

Figure C-7

9636A Logic Diagram and Terminal Identification

C-11

V+

CH. 1

A
OUT

CH.1

CH. 2

A
OUT

INCH.
2

ouTB

CH.2

(4)

CH. 2

GND

ouT B

)

\.
NOTE: NUMBERS IN ()

DENOTE TERMINAL NUMBERS.

TERMINAL IDENTIFICATION

1. POSITIVE SUPPLY VOLTAGE
2. CHANNEL 1 INPUT
3. CHANNEL
2 OUTPUT

4. SUPPLY AND SIGNAL GROUND
5. CHANNEL 2 INVERTED OUTPUT
6. CHANNEL 2 NON INVERTED OUTPUT

7. CHANNEL 1 INVERTED OUTPUT

8. CHANNEL 1 NON INVERTED OUTPUT
MK-1324

Figure C-8

9638 Logic Diagram and Terminal Identification

C-12

APPENDIX D
PROGRAMMING EXAMPLES

Two examples érc included in this appendix. The first is an example for bit-oriented protocols, and the
second is an example for byte count-oriented protocols.

These are only examples and are not intended for any other purpose.

D-1

DPV1l

/X00/

DPV-11]

=--

DDM

FOR

BIT

ORIENTED

PROTOCOLS

.TITLE

.IDENT

DIGITAL

(C)

198¢

BY
CORPORATION,

MAYNARD,

MASS.

EXAMELE

APPLICATION

NOTE

THIS

RSX-11M

NOT

BIT

ORIENTED

RUNNING

DPV-11

DEVICE

DRIVER

s WE

EQUIPMENT

HWDDFS SINTSX $INTXT MDCDF$,CCBDFS$, TMPDFS$ ,ASYRET, SYNRET
DEFINE

THE

HARDWARE

'DEFINE THE CCB

REGISTERS

®E

OFFSETS"

DEFINE

THE

TMy

DEFINE

LINE-TABLE

MODEM

COMTROL SYMBOLS
TEMPLATE OPERATORS

DEVICE CHARACTERISTICS DEFINED
IN -D.DCHR-

FL O

.MCALL
HWDDF$
CCBDF$
MDCDFS$
TMPDF$

my
ws

PoOEC1A

PRRB33

DC.SSS

(WORD

#0)

(WORD

#1)

WTME

0PvP13

FIELD

MULTI-POINT

CONFIGURATION

(WORD

#1)

WTMy

pecpdd

INDICATOR

MULTI-POINT

SECONDARY

(WORD
(WCRD

#1)
#1)

MWE

DC.ADR
DC.SPS

LINE

SELECTION

STATION

PO0B209

[

PROTOCOL

]

HALF-DUPLEX

goeRa7

SDLC

PRIMARY

DC.MPT

DC.SEC

00e0a1

DC.HDX
DC.PRT

ADDRESS

SDLC

SECONDARY

MODE

BITS

STATION

(COMPOSITE)

STATION

(COMPOSITE)

’

DEVICE

STATUS

FLAGS

DEFINED

I:bq

*'r). I?I#Z\(;'”

DD.TRN
DD.ACT

DD.DIS

|B
|

CF.EOM

CF.SOM

ZERO,

LINE

HAS

BEEN

ENABLED

ZERO,

LINE

HAS

BEEN

STARTED

--(UNUSED)
-~
-— (UNUSED)
-~

DD.ABT

DD.SYN

'
¥

g20

nu
il
(L

DD.EOM
DD.SOM

Pa1
002

CF.SYN

CF.TRN

o
o

DD.ENB

DD.STR

200
¥
DD.ENB!DD.ST

TRANSMIT

ABORTED

TRANSMIT

SYNC-TRAIN

TRANSMIT

LINE

TRANSMITTER

;

INITIAL

DUE

UNDERRUN

REQUIRED

TURN~-AROUND

READY

STATUS

FOR

REQUIRED
FRAME

DISABLED,

STOPPED

r
.

’

[

SEL

]

MODEM

CONTROL

BITS

wWs
ws
ey
ms
wy

Poooel

00RRR2

MODEM
DATA

YWs

DSSEL

PoPoo4

CLEAR

CARRIER

DATA

DSDTR

DSRTS

PPYo1e

DSLOQOP

DSITEN

SET

INDICATOR

REQUEST

Wma

DSMODR

DATA
RING

DATA

020000

210000
01000
Poo240

| O

DSCTS

DSCARY

| I

100000
P40000

| O

DSCHG
DSRING

SELECT

CHANGE

SEND

INDICATOR

READY
SET

INTERRUPT

SET

LOOPBACK
TO

ENABLE

SEND

TERMINAL

READY

FREQUENCY

REMOTE

LOOPBACK

;

—

;

SEL

]

RECEIVER

CONTROL

BITS

e
W

000020

000200
0Pe100

RECEIVER

RXREN

oeo4a0

RECEIVER

RECEIVER
RECEIVER

RXDONE
RXITEN

P04000
PR2000

RECEIVER

INTERRUPT

RXFLAG

RXSRDY

RXACT

Wonouwu

‘

RECEIVER

ENABLE

ACTIVE

STATUS
FLAG

DONE

READY

DETECT

ENABLE

SEL

]

RECEIVER

STATUS

INPUTS

CRC

004000

0100080

RECEIVER
RECEIVER

ASSEMBLED

RXOVRN

wouu

RXBFOV

100000
g7000@

RXERR
RXABC

RECEIVER

BUFFER

ERROR

RECEIVER

DATA

BIT COUNT
OVERFLOW (SOFTWARE

OVERRUN

D-2

ERROR)

RXABRT

002000

RXENDM

001000

RXSTRM

(00044d0

;

[

SEL

i
;
;

]

RECEIVED ABORT
RECEIVED
RECEIVED

END OF MESSAGE
START OF MESSAGE

MODE CONTROL OUTPUTS

;

DPAPA

190000

;

ALL

DPDECM

040000

;

DDCMP /

DPSTRP

(0200080

;

STRIP

DPSECS

010000

;

SDLC /

DPIDLE

(004000

;

IDLE

DPCRC
DPADRC

=
=

3%400
@00377

;
;

USE CRC
STATION

16 ERROR DETECTION
ADDRESS OR SYNC CHARACTER

INPRM

DPSTRPIDPCRC

;

INITIAL

STARTUP

;

[ SEL 4 ]

PARTIES

ADDRESSED

BISYNC

SYNC

OPERATION

LOOP

MODE

ADCCP SECONDARY

MODE

STATION

SELECT

PARAMETERS

TRANSMITTER STATUS AND CONTROL

TCLEN
EXADD
EXCON
RCLEN

=
=
.=
=

003400

TXITEN

000100

;
;

RECEIVE CHARACTER LENGTH
TRANSMITTER INTERRUPT ENABLE

TXREN

(000020

;

TRANSMITTER

TXMAI

(000€10

;

MAINTENANCE
MODE SELECT

TXDONE

@20004

;

TRANSMITTER

DONE

TXACT

000002

;

TRANSMITTER

ACTIVE

TXRES

000001

;

DEVICE

;

[

TXLATE

140000

~; TRANSMIT CHARACTER LENGTH
; EXTENDED ADDRESS FIELD
; EXTENDED CONTROL FIELD

(l0000

004000

SEL

]

ENABLE

RESET

TRANSMITTER

OUTPUT CONTROLS

(04000

100000

; TRANSMITTER DATA LATE (UNDERRUN)

TXABRT

002000

TXENDM

(¢010080

;

TRANSMIT

TXSTRM

(000400

;

TRANSMIT

TXGO

;

PROCESS

éDXPTB:

;

TRANSMITTER GO AHEAD

TRANSMITTER ABORT

END

OF MESSAGE

START OF MESSAGE
)

DISPATCH TABLE

+WORD
« WORD
+«WORD
+«WORD
-WORD

$SDASX
$SDASR
$SDKIL
$SDCTL
$SDTIM

.SBTTL

$SDPRI
|

; +

;

;
;
;

TRANSMIT ENABLE
RECEIVE
ENABLE
KILL I/0 ENABLE

; CONTROL
;i

TIME

(ASSIGN BUFFER)

ENABLE

OUT

-- RECEIVE INTERRUPT SERVICE ROUTINE

FUNCTION:

THE DEVICE INTERRUPT
IS VECTORED BY THE HARDWARE TO THE

DEVIC
LINE TABLE.
E THE '$SDPRI' LABEL
CALLING SEQUENCE IN THE LINE TABLE AT

;

ENTERED VIA

;

;
;

@ (SP)
2(SP)

= SAVED RS
= INTERRUPTED

;

4 (SP)

= INTERRUPTED PS

ADDRESS

'D.RDBF'

THE

LINE

TABLE

OUTPUTS:

= ADDRESS OF 'D.RDB2' IN THE | LINE TABLE
= RE( CEIVER STATUS BITS FROM CSR [SEL

D.RVAD

-y

n‘v’

D-3

'D.RXIN'.

ENTRY:

;

’

OFFSET

MOV

i SAVE

R3,-(SP)

MOV
@(R5)+,R4
BIC
#RXABC,R4
.IF DF MS$SS$MGE
MOV
KISARG6,—- (SP)
MOV
(R5) +,KISARb

HEHF
;;:

:::;
:;:

"3 :;: DECREMENT BUFFER BYTE COUNT
.
;;; BUFFER OVERFLOW - POST COMPLETE

MOV
BIT
BNE

2(R5) ,R3
g
#RXSRDY, - (R3)
DPRCP

:::; GET CSR+2 ADDRESS
;;: ERROR OR END-OF-MESSAGE
7
;:: YES - POST RECEIVE COMPLETE

MOVB

R4 ,@ (R5)+

STORE

MOV

(SP)+,KISARG

HEIH

RESTORE ‘PREVIOUS MAPPING

INC

- (RS)

:;+

ADVANCE BUFFER ADDRESS

MOV

(SP)+,R4

RESTORE REGISTERS

MOV

(SP)+,R3

238

EXIT THE

DPRBO:
BIS

MOV
.ENDC
MOV
MOV
BIC
MOV
MOV

SINTSX

CHARACTER

RECEIVE BUFFER

INTERRUPT

;;;

BUFFER OVERRUN HAS

:::;

SET

;::;

END-OF-MESSAGE OR ERROR

(SP)+,KISARS

; ++

RESTORE PREVIOUS MAPPING

R4, (R5)+

;33 SAVE STATUS FLAGS IN

#RXBFOV, R4

DPRCP:

(R5)+,R4
#RXITEN,- (R4)

(SP)+,R4
(sp)+,R3

:3:
;:;
;:;
;+:

;:;

(SOFTWARE)

OCCURRED

ERROR

INDICATOR

INDICATION

'D.RVAD'

GET CSR+2 ADDR + POINT TO 'D.RPRI'
CLEAR RECEIVER INTERRUPT ENABLE
RESTORE R4 S0 'SINTSV' IS HAPPY
AND R3

DO A TRICKY SINTSV

(R5

SAVED BUT NOT R4)
|

;

40$:

GET CHARACTER AND FLAGS
DON'T WORRY ABOUT ASSEMBLED BIT COUNT
|
SAVE CURRENT MAP
MAP TO DATA BUFFER

(R5) +
DPRBO

SINTXT

REGISTERS

DEC
BMI

.IFTF

$SDPRI::

CHECK

FOR ERRORS,

POST RECEIVE

COMPLETE,

MOV
MOV

R3,-(SP)
(R5) ,R4

ADD

SuB
CLR
BIC

#61777,(R5)+

; ;+ ANY

BEQ

40$

:; NO --

POST

ASR

- (R5)

SHIFT

ERROR

ASSIGN NEW BUFFER

;;
;;

SAVE AN ADDITIONAL REGISTER
CCB ADDRESS TO R4 (R5 POPPED)

#D.RCNT-D.RCCB,R5

;;

BACK

(R5)+,C.CNT1(R4)
R3

;3 COMPUTE RECEIVED: FRAME BYTE COUNT
;3 SET R3 FOR COMPLETION STATUS
ERRORS

TO THE

REPORTED

RECEIVE

RESI

DUAL COUNT

COMPLETE

0.K.

INDICATORS...

ASR

(R5) +

+..TWO PLACES RIGHT

ASRB

- (R5)

;;

SHIFT

'RXABRT'

INDICATORS

INTO

MOVB

(R5)+,R3

;;

USE

MOV

RCVERR”Z(R3) R3

;;

BCC
INC
CALL
BR

409
;; FRAME NOT ABORTED - POST COMPLETE
D.RABT-D.RDB2(R5) ;COUNT NUMBER OF ABORTED FRAMES
3
RBFUSE
;; RE-INITIALIZE WITH THE SAME BUFFER
609
;; RE-ENABLE INTERRUPTS FOR NEXT FRAME

BIS

C.STS(R4) ,R3

;;

INCLUDE RE-SYNC

MOV
CALL
MOV
CALL

R3,-(SP)
SDDRCP
(SP)+,R3
RBFSET

;;
;;
;;
;;

SAVE STATUS REPORTED TO DLC
POST RECEIVE COMPLETE
‘
RECOVER COMPLETION STATUS ~
2
ASSIGN NEW CCB TO THE RECEIVER

NOW
=

- D-4

CCB

=
C-BIT

TABLE

STATUS

INDEX

FLAGS

STATUS,

IF ANY

60S:

BCS

DREXIT

TST

FAILED

BMI

DRCLRA

MOV

-(R5) ,R3

;;

RECEIVER CSR

BIS

#RKITEN,“(RB)

;:;

RE-ENABLE

MOV

(SP)+,R3

RESTORE

EXIT TO THE

RECEIVER

INACTIVE

;;

YES

DISABLE

RCVR

FOR

[SEL 2]

RECEIVER

RETURN

RE-SYNC

TO R3

INTERRUPTS

DRCLRA:

MOMENTARILY

;

TERMINATES
THE

RESET

'RXREN'

RE-SYNCHRONIZATION.

FLAG

ORDER

FORCE

RECEIVER

THIS IS REQUIRED FOR ANY ERROR WHICH

RECEIVE

OPERATION

MID-~-FRAME.

ENTRY:

LEAVE

WAS AN ERROR REPORTED TO DLC ?

DREXIT:

;

;;

H
;

ADDRESS

DRCLRA:

'D.RCCB'

THE

LINE

TABLE

|
MOV
BIC

;

R4 = ADDRESS OF 'C.STS'
IN THE NEWLY-ASSIGNED CCB
(SP)= SAVED R3 VALUE

-{R5) ,R3
#RXREN,w(RB)

;;
::

RCVR CSR ADDRESS [SEL 2] TO R3
RESET RCVR ENABLE FOR RE-SYNC

BIS
BIS

#CS.RSN, (R4)
#RMREN*RXITEN (RB)

;:;

SET RE-SYNC IN CCB 'C.STS!
RE~ENABLE THE RECEIVER

DREXIT

RESTORE

.SBTTL

S$SDPTI

~--

AND

~TRANSMIT INTERRUPT SERVICE

EXIT

ROUTINE

FUNCTION:

THE DEVICE INTERRUPT IS VECTORED BY THE HARDWARE TO THE

DEVICE

LINE TABLE.

CALLING

SEQUENCE

;

ONCE

HANDLED

FRAME

THE

'SSDPTI'

THE LINE

TRANSMISSION

THE

LABEL

TABLE

INITIATED,

ROUTINE ADDRESSED

VIA

EACH
THE

'D.TXIN'.

INTERRUPT

'D.TSPA'

;

ENTERED VIA A

OFFSET

WORD.

ENTRY:

ADDRESS

g(SP)

H
H

=
=

2(SP)
4(89)‘%

SAVED R5
IMTERRUPTEP PC

;

'D.TCSR'

THE

LINE

TABLE

INTERRUPTED PS
|

EXIT:

R5 = ADDRESS OF

'D.TCCB'

IN THE

LINE TABLE

S$SDPTI
.

R4 ,- (SP)

:::;

SAVE

(R5)+,R4

:::;

GET

TST

(R4)+

;:;

POINT TO

JMP

@(R5)+

:::

GO TO CORRECT STATE

TRANSMITTER

CSR

[SEL 6]

ADDRESS

TEST UNDERRUN

PROCEQSOR

et
E
e
T
;

CURRENT

ST&TE

: mmmmmmmmmmmm

TISCTS:

|
Cw

wes

MONITOR
we

whes

CSR
e

FOR
e

'CLEAR TO
e

wee

SEND'
e

;
e -

'"CLEAR TO SEND'

’

BIT

#DSCTS,*6(R4)

::;

BNE

TISIFL

;:3;

YES

BITB

#DQfiSYN,D,FLAGmD.TCNT(RS)

:::

SYNC-TRAIN

REQUIRED

BEQ

TISIFX

$:;

NO --

FLAGS

MOV

START TO

SEND

ACTIVE

SEND THE

YET ?

FRAME

UNTIL

'CTS®

#TXSTRM! TXENDM, (R4)

;7;

START +

END

SENDS

SYNC STRING

TISEXT
‘

SEND
TISIFL.

’

INITIAL

FRAME

'FLAG'

;

#TISTRT,- (RS)

;;: NEXT STATE = SEND ADDRESS BYTE

#TXSTRM, (R4)

;3; SEND AN SDLC FLAG CHARACTER

TISIFX:
TISEXT

SEND ADDR

D.TADC-D. TCNT(RS),(R4)

MOV

$#TISDAT,-(R5S)

TISEXT

FOLLOWING

'FLAG'

;

:s: DECREMENT COUNT FOR ADDR BYTE

(R5)

DEC
MOV

BYTE

;::
:::

SEND ADDR,
NEXT STATE

CLEAR 'TXSTRM'
= DATA TRANSFER

TRANSFER FRAME DATA BYTES

TISDAT:

BMI

TISLAT

;::

UNDERRUN

DEC

+
(R5)

:;:

DECREMENT

BMI

TISEND

:::

ALL

.IF DF M$SMGE

DONE

ABORT

DATA
-

AND

BYTE

SEND

RE-TRANSMIT

COUNT

END-MSG

SEQUENCE

MOV

KISAR6
,~- (SP)

;

SAVE CURRENT MAPPING

MOV

(R5) +,KISARG

MAP

MOVB

(R5)
@ (R5)
+, (R4)

;
;

ADVANCE THE BUFFER ADDRESS
NEXT CHARACTER TO BE SENT

MOV

(SP)+,KISAR6

; 7+

RESTORE

(SP)+,R4

;;;
;;;

COMMON LEVEL-7
RESTORE R4
EXIT INTERRUPT

THE

TRANSMIT

BUFFER

.IFTF

INC

LIFT

MAPPING

-« ENDC

TISEXT:
MOV

SINTXT

77:
DATA

BYTE-COUNT

INTERRUPT

EXIT

SERVICE

EXHAUSTED

;

w—

TISEXT

—

a—

—

Wy
Ng

ME
Wy

WS
—

—

]

—-—

TISCLR:

——-—

a—”

——

—

#TISRTS,
- (R5)

——-

—-—

PAD AFTER

ESET

]

SEND SECOND
o

THE

DEVICE

FLAG

BYTE

SEND SECOND PAD
TO SEND A PAD

—-—

—

'ABORT'
wo—

'FLAG';

EXT STATE =
ET 'TXABRT'

#TXABRT, (R4)

MOV

$#TISCLR,-(R5)

TMME

D.FLAG-D.TCNT(R5)

CLRB
MOV

'ABORT'

‘mgp

SEND

TISEXT

#TISPAD, (R5)

TRANSMIT END-OF-MSG SEQUENCE
ADJUST R5 AND CLEAR 'D.TCNT'
NEXT STATE = IDLE FLAGS (ASSUMED)
TEST FOR LINE TURN-AROUND
NO -- IDLE THE LINE WITH FLAGS
YES - SEND PADS, THEN DISABLE

TISEXT

BPL
MOV

D.FLAG-D.TSPA(R5)

#TISFLG,- (R5)

MOV

ASLB

= (R5)

TMy

#TXENDM, (R4)

INC

MOV

TISEND:

—

a——

AS
-

—-

—

——

]

PAD
w—

;

::;3; NEXT STATE = DROP 'REQUEST
TO SEND'

D-6

TISCLX:

# TXABRT, (R4)

MOV
BIC

STATE

DISABLE

'ABORT'

THE TRANSMITTER

CHAR

DROP

REQUEST

SEND

EXIT

;

mmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmm ;

BIT

#DC.HDX,D.DCHR-D.TCNT (R5)

;;;

HALF-DUPLEX CHANNEL ?

BEQ

TISDON

NO —— LEAVE

;;;

POST TRANSMIT COMPLETE

$DSRTS,-6 (R4)

TISDON

—-

—

—-—-

w—-

COUNT

THE

SEND

PAD,

BETWEEN

STATE

FRAME WAS

CLEAR

TRANSMITTER

—-—

——

a—

—

——-

——

—

—-—

w—

—

IS
—-

-3
X

il
e

TRANSMITTER
;

'TXENDM',

(g3

O
e

-3

—

EVENTS

FRAMES

;:;

A——

ABORTED

DISABLE

;;;

— ;

RE-TRANSMIT

ERROR

#DU ACT, D.FLAG-D.TCNT(RS)
m

—-

LINE

;

IDLE FLAGS
ACTIVE

—-

Wy
s

THIS

#TXSTRM, (R4)
-

w——-

—

-3

—

o
=

FLAGS

O
O

R d

IDLE

-3

—-

192

TISCLX

——-—

—

I)ayTrljf%fi@"”f}-uflpfal?lgn(fafa)

STATE
——

—-

INC

#TISDON,- (R5)
#DD.ABT,D.FLAG-D.TSPA(RS)

STATE

——

MOVB

MOV

—

ACTIVE

TRANSMITTER DATA UNDERRUN

STATE =

mmmmmmmmmmmm

-y

'RTS'

;:: DROP 'REQUEST TO SEND'

(o3

BIC

SETUP TO SEND ANOTHER

;i;;

TISEXT

;:;

#TXREN,W(R4)

]

MOV

R3,-(SP)

(RS5) ,R4

Wy
NEF
ey

RESTORE

TME

'SINTSV'

;;

TABLE

POINTER

INTERRUPTS

FOR

PRIORITY

W/0 R4

SAVED

DROP

(POPS

RS5S)

SAVE AN ADDITIONAL REGISTER
ACTIVE CCB ADDRESS TO R4

(R5)+

BNE

THIS CCB IS NO LONGER ACTIVE

CALL

$DDXMP

;: POST TRANSMIT COMPLETE TO THE DLC

MOV

(R5) ,R4

;;

FIRST CCB

BEQ
MOV

TREXIT

NONE

(R4) , (RS)

REMOVE

STATE
e

'TXDONE'

;;
;7

LINE

#$DD.ABT,D.FLAG-D. TCBQ(R5) ; ; WAS THE FRAME ABORTED ?
TRSTRT
;7 YES - SETUP RE-TRANSMISSION
D.KCCB-D.TCBQ
(R5)
;7 TRANSMIT KILL IN PROGRESS ?
CKILLT
%
;; YES - RETURN CCB'S TO THE DLC
R3
;7 SET COM?LETION STATUS = SUCCESS

CLR

DISABLE

CLR
BNE

ADJUST

BITB

TST

SINTSX

MOV

(SP)+,R4

MOV

#D.TPRI-D.TCNT,R5
#TXITEN,- (R4)

BIC

ADD

TISDON:

=
o

START
e

THERE

SECONDARY CHAIN

CCB

TRANSMITTER

FROM

FRAME

TRANSMISSION

dee

IDLE

SECONDARY

CHAIN

;
o

;

TRSTRT:
CLR

(R4)

CLEAR CCB

MOV

R4 ,-(R5)

;;

SETUP

TST

BICB

- (R5)
;; SKIP BACK OVER 'D.TPRI'
$C.FLG1,R4
;; POINT TO THE CCB BUFFER FLAGS
(R4) ,D.FLAG-D.TPRI(R5)
;; SAVE FLAGS FOR LEVEL-7 USE
$DD.ABT,D.FLAG-D.TPRI
(R5) ;MAKE SURE 'ABORT' FLAG IS OFF

ADD
BISB

MOV

w(Ré),D.TCNTwD TPRI(RS)

CLR

- (R5)

MOV

- (R4) ,- (R5)

P
P

D-7

SET

LINKAGE WORD
THE

TRANSMIT

INITIALIZE
SET

ACTIVE

BYTE

COUNT

'D.TADC'

TRANSMIT

CCB

BUFFER

WORD
ADDRESS

.IF DF M$SMGE
MOV
- (R4) ,- (R5)

SET TRANSMIT BUFFER RELOCATION
THE CURRENT APR6 MAPPING

MOV

KISAR6,- (SP)

;;

SAVE

MOV

(R5) +,KISARG

MAP

THE

TRANSMIT

.IFTF

BUFFER

MOVB

@ (R5) +, (R5)

;;

MOVE

ADDRESS

MOV

(SP)+,KISARG

:»

RESTORE

BACK

;;

NO --

BYTE

'D.TADC'

APR6

MAPPING

PROCESSOR CELL

IFT
.ENDC

ADD

#D.TSPA-D.TADC,R5

TSTB

495 :

STATE

BPL

20$

;; IS THE TRANSMITTER READY NOW ?

MOV

$#TISTRT, (RS)

;; INITIAL STATE = SEND ADDR BYTE

MOV

-2(R5),R3

;; TRANSMITTER CSR

BIS
BIS

#DSRTS , -4 (R3)
$TXREN, (R3) +

;:
;;

ASSERT 'REQUEST TO SEND'
ENABLE THE TRANSMITTER

MOV

$TISCTS, (RS)

INITIAL

BIS

$TXITEN,@- (R5)

;;

RE-ENABLE TRANSMIT

MOV

(SP)+,R3

:;;

RESTORE

;;

EXIT

208 :

D.FLAG-D.TSPA (RS5)

40$

ENABLE

IT,

THEN

INTERRUPTS

STATE

AND

[SEL

START

WAIT

EXIT

TO R3

FOR

'CTS'

INTERRUPTS

TREXIT:

ASYRET
R

;

CURRENT

STATE

CKILLT:

FROM

WHEREVER

ENTRY

APPROPRIATE,

TRANSMIT

;

KILL

TIMEOUT

;

T
i
;

MOV

|
|
#CS.ERR!CS.ABO,-(SP)

;;

TRANSMIT

COMPLETION

STATUS

CKTTMO
:

20$:

405

BIC

#TXREN,@D.TCSR-D.TCBQ(R5)

MOV

(R5) , (R4)

;;

ADD

CLR

(R5) +

CLEAR

MOV

(SP) ,R3

;; COMPLETION

MOV

(R4) ,- (SP)

;;

CCB

CLR

(R4)

;;

MAKE

SURE

CALL

SDDXMP

;;

DISABLE

CCB

TRANSMITTER

CHAIN

SECONDARY

CHAIN

PRIMARY

POINTER

STATUS TO R3

ADDRESS

STACK

LINK WORD

IS ZERO
POST A CCB COMPLETE W/ERROR

MOV

(SP) +, R4

s ;

BNE

20$

MORE TO GO -

CONTINUE

TST

(SP) +

CLEAN

OFF

MOV
BEQ

(R5) , R4
TREXIT

;:
;;

KILL
NONE

CCB ADDRESS TO R4
- RESTORE R3 AND EXIT
NO

CLR

(R5)

;;

KILL

STATUS

CMPB
BNE

$FC.KIL,C.FNC(R4)
493

;;
;;

ADDRESS

STATUS

CLR

$DDKCP

POST KILL-I/O

TREXIT

RESTORE

CALL

$DDCCP

THE

STACK

COMPLETE

AND

EXIT

:: POST CONTROL COMPLETE

TREXIT

$SDASX

KILL-I/0O OR CONTROL FUNCTION
CONTROL - POST IT COMPLETE

LONGER IN PROGRESS
SUCCESSFUL

CALL

.SBTTL

RESTORE

TRANSMIT ENABLE

AND

EXIT

ENTRY

FUNCTION:

WMe

;;

SECONDARY

'SSDASX'

ENTERED

(VIA THE

DISPATCH TABLE)

D-8

TO QUEUE

ASYNC

WTMy

CCB

TRANSMITTER

CCB CHAIN.

IF NOT,

CONTAINING

SDLC

TRANSMITTING

BUSY,

TRANSMITTED.

TS QUEUED TO THE

THE TRANSMITTER IS

NEW

1IF

THE

SECONDARY

ENABLED TO START

FRAME.

WME

THE

FRAME

THE CCB

ENTRY:

= ADDRESS OF

WME

ADDRESS

TRANSMIT ENABLE CCB
LINE TABLE

DEVICE

CALLING DLC

REGISTERS

ARE

PROCESS

PRIORITY

EXIT:

UNPREDICTABLE

WMy

ALL

$SDASX: :
R3,- (SP)

;;

SAVE

MOV

D.TCSR(R5)
,R3

;;

TRANSMIT

BIC

#TXITEN, (R3)

;;

DISABLE

ADD

#D.TCCB, RS

;;

POINT TO ACTIVE

TST

20 :

MOV

(R5) +

FOR

EXIT

CSR

VIA

'TRSTRT'

ADDRESS

TRANSMITTER

[SEL

CCB ADDRESS

TRSTRT

;;

MOV

R4 ,- (SP)

;;

SAVE

MOV

R5, R4

;; COPY THE CCB ADDRESS TO R4

(R4) ,R5

BNE

CELL

;; IS THERE AN ACTIVE CCB ?

BEQ

MOV

INTERRUPTS

20%

——

START

POINTER

;;

ADDRESS

;;

LOOP

THE

UNTIL WE

TRANSMITTER

FIRST

CCB

FIND THE

MOV

(SP) +, (R4)

;;

LINK

CLR

NEW

CCB

@ (R4) +

END

;;

MARK

BIS

NEW

END

$TXITEN, (R3)

CCB

CHAIN

; ;

RE-ENABLE

TREXIT

RESTORE

.SBTTL

$SDASR

RECEIVE

TRANSMITTER

END
CHAIN

INTERRUPTS

R3 AND EXIT

ENABLE

AFTER

: +

BUFFER WAIT

i’

;

FUNCTION:

;

THIS

;

ROUTINE

BUFFER

CALLED

ALLOCATION

THE

REQUEST

FAILURE

AND

BUFFER

CAN

CALL

POOL

MANAGER WHEN

SATISFIED,

FOLLOWING

'$RDBWT'.

;

ENTRY:

;

ADDRESS

CCB

;

ADDRESS

DEVICE

AND

RECEIVE
LINE

BUFFER

TABLE

EXIT:

;

ADDRESS

'D.RCCB'

ADDRESS

'C.STS'

;

(SP)=

SAVED

VALUE

THE

LINE

TABLE

CCB

;‘m

$SDASR::
ADD

#D.RDB2, RS

;;

CALL

POINT
TO SECOND

RBFUSE

;;

ASSIGN

MOV

R3,- (SP)

;;

PUSH

JMP

DRCLRA

;;

RESET

BIS

#CS.BUF, (R4)

BUFFER

$SDSTR

RCVR-CSR

WORD

THE

RECEIVER

'DREXIT',

;; PREV. ALLOC. FAILURE TO CCB 'C.STS'
R3

FOR

AND

START UP DEVICE AND LINE ACTIVITY

;“

D-9

EXIT

ACTIVATE

; +

;

THE

ABOVE

RECEIVER

SSDSTR:
:

20S:

60S:

BITB

$DD.ENB,D.FLAG
(R5)

BNE

60$

J
HAS THE LINE BEEN ENABLED
?

NO --

REJECT THE

MOV

D.RDBF(R5) ,R3

RECEIVER CSR ADDR

MOV

D.STN(R5) , (R3)

;::

SET

BIS

#RXREN,~-(R3)

ENABLE THE RECEIVER

MOV

R5,~-(SP)

SAVE

ADD

#D.RDB2,R5

ADJUST R5

CALL

RBFSET

ASSIGN

BCS

20$

;;

FAILED -

BIS

#RXITEN, (R3)

: ;7 ENABLE

ADDRESS

BYTE

[SEL
+

'START'

FOR

BUFFER

RECEIVE

CCB

ROUTINE
AND

BUFFER

START THE TRANSMITTER

RECEIVER

INTERRUPTS

MOV

(SP)+,R5

RECOVER

D.FLAG (R5)

;;

LINE

HAS

TABLE

BEEN

BIT

#DC.HDX,D.DCHR(R5)

CHECK

CTLCMP

CORRECT

BIS

#DSRTS, (R3)

ASSERT

'REQUEST TO

CTLCMP

«+«AND

POST

CTLERR

#CS.ERR!CS.DIS,R3

DP.NOP:

;;

CONTROL

STATUS

START

STARTED

BNE

MODE

LINE TABLE START ADDRESS

CLRB

MOV

OPERATING

THAT ASSUMPTION
-

STARTUP
START

COMPLETE

SEND'

LINE

COMPLETE

STATUS = LINE DISABLED
ERROR W/COMPLETION

RETURN

FUNCTION

NO-OPERATION

CTLCMP:

CLR

MOV

(SP)+,R4

=
:

CTLERR:

; ;3 RECOVER

SYNRET

.SBTTL
§

;
;

;;

$SDSTP

SAVED

SYNCHRONOUS

STOP DEVICE AND

TOP'®

SUCCESSFUL

VALUE

RETURN

LINE ACTIVITY

CONTROL

FUNCTTION

mmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmm

:
SSDSTP:

20S$:

;

D.RDBF(R5) ,R3

;;3 RECEIVER

#DSDTR,- (R3)

;;

DISABLE

RECEIVER,

CLR

4 (R3)

;;

DISABLE

TRANSMITTER

MOV

D.RCCB(R5) ,R4

ACTIVE

BEQ
CALL

208
SRDBRT

;;
:»

NONE THERE - SKIP IT
RETURN BUFFER TO THE POOL

‘

CSR

ADDR

RECEIVE

[SEL

LEAVE

CCB

CLR

D.RCCB(R5)

NO RECEIVE CCB ASSIGNED

R4
D.SLN(R5) ,R4

;;
;;

CLEAR R4 FOR PARAMETER USE
SET SYSTEM LINE NUMBER IN R4

CALL

SRDBQP

;;

PURGE

BUFFER WAIT QUEUE
LONGER

REQUESTS

BISE

$DD.STR,D.FLAG(R5)
D.TCCB(R5)

;;
13

LINE

TST
BEQ

CTLCMP

;;

NO --

MOV
MOVB
ASYRET

(SP)+,D.KCCB(R5)
#1, (R5)

;:+ SAVE THE CONTROL CCB FOR TIMEOUT
;; MAKE SURE THE TIMER IS ACTIVE
:; RETURN WITH ASYNCHRONOQUS COMPLETION

.SBTTL

S$SDENB

ACTIVE

CLR
BISB

'DSDTR'

STARTED

IS THERE AN ACTIVE TRANSMIT CCB

ENABLE THE

POST CONTROL

ENABTULE

LINE AND DEVICE

DEVICE

mmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmm

SSDENB:
:
MOV

D.RDBF(R5) ,R3

#TXRSET, 2 (R3)

RECEIVER

RESET

THE

D-10

CSR ADDRESS
DEVICE

COMPLETE

mmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmm

;
;‘

MOV
MOV

[SEL

(1-US

SINGLE-SHOT)

IN DPV-11

;CLEAR HIGH-ORDER BYTE OF

'D.STN'

$BINPRM, (R5)

BIC

SETUP INITIAL
ADDRESS-SIZE

WORD

PARAMETERS
NO LONGER SIGNIFICANT

ENABLE

#DSDTR,- (R3)
;; ASSERT 'DATA TERMINAL READY' LINE
#DD.ENB,D.FLAG-D.DCHR-2(R5) ;; LINE IS ENABLED
CTLCMP
;; POST CONTROL FUNCTION COMPLETE

BIS
BICB

#DPSECS, 2 (R5)

BIS

CMPB

SDLC PRIMARY-STATION MODE ?
YES - FLAGS ARE SETUP AS IS
SDLC SECONDARY-STATION MODE ?
NO -- OPERATING MODE INVALID

BNE

#DC.ADR,- (R5)
#DC.SPS, (R5)
409
#DC.SSS, (RS)
60

BEQ

60S:

BIS

CMPB

40%:

#~C<DPADRC>,
(R5)

BIC

POINT TO CHARACTERISTICS WORD #1
16-BIT STATION ADDRESS ?
NO -- SHOULD BE ALL SET
USE THE HIGH-ORDER BYTE

(R5)

20$

20S$:

BEQ

SWAB

BIT

#D.DCHR+2,R5
+
(R5),
#DC.ADR

ADD

#CS.ERR!CS.DEV,R3 ;;

MOV
BR

CTLERR

.SBTTL

$SDDIS

;;

STATION

ADDRESS

CHECKING

ERROR STATUS - INVALID PROTOCOL

POST CONTROL COMPLETE WITH ERROR

DISABLE THE LINE

MOVB

- (R3)
#$DD.ENB!DD.STR,D.FLAG
(R5)

CTLCMP

$SSDMSN
ENSE

ew
“was
W
W
ey

D.RDBF (R5) ,R3

CLR

wmy

MOV

CTLERR

BEQ

ERROR CODE
NO

#DD.STR,D.FLAG
(R5)

ADDRESS

$CS.ERR!CS.ENB,R3

DISABLE

RECEIVER + TURN

MOV

BITB

$SDDIS::

LINE

LONGER

-y

[

CLEAR CARRY AND

LINE
--

IF NOT STOPPED

STATE

CORRECT

REJECT THE

RECEIVER CSR
ENABLED

EXIT

SENSE MODEM STATUS

MODEM

STATUS

;

mmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmm ;

(2]

FOR RETURN

CODES

ADDRESS OF RECEIVER CSR

$DSDSR, - (R3)
208
#MC.DSR, R4

;3
i;
;:;

IS THE DATA-SET READY ?
NO -YES - SET INDICATOR IN R4

#DSRING, (R3)
40$
#MC .RNG, R4

;7
:;

IS THE PHONE RINGING ?
NO —YES - SET INDICATOR IN R4

BIS

#DSCARY, (R3)
608
#MC.CAR,R4

;;
+3
;:

IS THERE CARRIER PRESENT ?
NO -- POST COMPLETE
YES - SET INDICATOR IN R4

MOV

R4, (SP)

RETURN

CTLCMP

;;

POST CONTROL

BIS

BIT
BEQ
BIS

BIT
BEQ

60S:

BIT

40S:

CLEAR

D.RDBF (R5) ,R3

BEQ

208

;;

«END

DIGITAL

(C)

[SEL 2]

(SAVED)

FUNCTION

COMPLETE

DPV - BYTE ORIENTED DPV-11 DEVICE DRIVER MODULE
/X00/

. TITLE
.IDENT

RESULTS

1980

BY
MAYNARD,

EQUIPMENT CORPORATION,

D-11

MASS.

DISABLE

([SEL

DTR OFF

DEVICE DRIVER

EXAMPLE OF AN APPLICATION RSX-11M BYTE ORIENTED DPV-11

DEFINE

MODEM

DEFINE

THE

CONTROL

CCB

MDCDFS$
CCBDF$
TMPDF$
CHADFS

DEFINE

LINE

.MCALL

SINTSX,$INTXT,INHIBS,
ENABLS
CCBDF$, TMPDF$,SLIBCL
MDCDF$
CHADFS

.MCALL

DEFINE

DEVICE

SYMBOLS

OFFSETS

TABLE

OFFSET

MACROS

CHARACTERISTICS

;

LOCAL

SYMBOL

DEFINITIONS

;

TRANSMITTER

FLAGS

TINIT=

goPal1g

INITIAL TRANSMIT

TXENA=

0PoB20

TRANSMIT

TXINT=

PeO1a0

TXACT=

goene2

TSOM=

gpR4go0

TRANSMIT

TEOM=

001020

TRANSMIT

;

RECEIVE

CSR

STATUS

(HALF

TRANSMIT

INTERRUPT

ENABLE

TRANSMIT

ACTIVE

ENABLE

START OF MESSAGE
OF MESSAGE

END

FLAGS

3*40¢

SSYN=

PROSEL=

020000
040000

RINIT=

RXINT!RCVEN!DTR

INPRM=

SSYN!PROSEL!CRC

CRC=

RECEIVE

ENABLE

PPR100

RECEIVE

INTERRUPT

POA020

RXINT=

RECEIVE

CRC

STRIP

RCVEN=

TME

ENABLE

CHECK

SYNC

PROTOCOL SELECTION (BYTE)
INITIAL RECEIVE STATUS
INITIALIZATION FLAGS

;

MODEM

STATUS

FLAGS

RING=

Wms

PUOBL2
001009
P40o0Y

DSR=

SEND

LEAD

SEND

DTR=

REQUEST

CLEAR TO
DATA

TERMINAL READY

WmE

peoecd
220200

DATA

SET

RTS=

CTS=

RING

INDICATOR

READY

;

DPV11l

DEVICE

DRIVER

DISPATCH

TABLE

DPCTL

. WORD

DPTIM

KILL

CONTROL
TIME

ENABLE

(ASSIGN

I/0

BUFFER)

|
INITIATION

OUT

**-.SDPVRI-DPV11

RECEIVE

INTERRUPT

SERVICE

ROUTINE

%Ws

THE DEVICE

*JSR R5,$DPVRI'

.WORD

DPKIL

RECEIVE

«WORD

TRANSMIT

WME

DPASR

DPASX

.WORD

B:
: .WORD
SDPVT

WwE

TABLE.

INTERRUPT

HARDWARE

AND

IS VECTORED TO THE DEVICE LINE TABLE
THIS

ROUTINE IS ENTERED BY A
AT THE BEGINNING OF THE

INSTRUCTION

INPUTS:

2(SP)
4 (SP)
6 (SP)

SAVED

DEVICE

LINE TABLE +

INTERRUPTED BIAS
INTERRUPTED PC
INTERRUPTED

= ADDRESS

WS
e

@(SP)

STACK:

WeE

WMy

THE

OQUTPUTS:

D-12

LINE

DUPLEX)

we
wWe
e

ETC.

$DPVRI::
MOV

R4 ,-(SP)

;77

MOV

(R5)+,R4

;+:; GET ADDRESS

MOV

(R4) ,R4

;:;

OF RECEIVER DATA BUFFER
GET CHARACTER AND FLAGS

BMI

DPRHO

;7:

ANY

ERROR

RECEIVER

OVERRUN

MS$SMGE

MOV

KISARG6,~- (SP)

::+;

SAVE

MOV

(R5)+ ,KISARG

;:;

MAP

R4,@ (R5)+

STORE

.IF

SAVE

CURRENT MAP

RESTORE

DATA

BUFFER

.IFTF
MOVB

CHARACTER

RECEIVE

BUFFER

(SP)+,KISAR6

MOV

e 1

LIFT

MAPPING

DEC

(RS)

- BEQ

DECREMENT

DPRCP

INC

-(R5)

: ;+

EQ RECEIVE COMPLETE
ADVANCE BUFFER ADDRESS

MOV

(SP)+,R4

RESTORE

« ENDC

EXIT

BYTE

COUNT

REGISTERS

THE

INTERRUPT

EXCEPTIONAL

RECEIVE

SERVICE

ROUTINES

HARDWARE

OVERRUN

$INTXT

REMAINING

.ENABL
DPRHO:

LSB

ADD

#<RCNT-RDBF-2>,R5

MOV

#100001,RFLAG-RCNT(R5)
|

;77

POINT TO COUNT

;;;

CLEAR

CELL

SET FLAGS
RECEIVE

#CS.ERR+CS.ROV,RSTAT-RCNT
(R5)

TO COMPLETE

ACTIVE

;;;

REQUEST AND

EXIT

SET OVERRUN

STATUS

RECEIVE

BYTE COUNT

RUNOUT

MOV

;;;

DPRCP:

MOV

BIC
MOV

R4, (R5) +
;i SAVE CRC FLAG AND POINT TO PRIORITY
RDBF-RPRI
(R5) ,R4 ;;; GET RECEIVE DATA BUFFER ADDRESS
#RXINT,-(R4)
;77 CLEAR RECEIVER INTERRUPT ENABLE
(SP)+,R4

SINTSX

;7:;

RESTORE

DO A TRICKY

MOV

R3,-(SP)

SAVE

TST

(R5) +

POINT

ASR

(R5) +

;;

LOAD

C-BIT

BCS

209

(R5) ,R4

GET

MOV
.LIST

FLAGS

HAPPY

(R5 PRESAVED BUT NOT R4)

ADDITIONAL

WORD

FROM

DATA,

PRIMARY

FLAGS (BIT 0)
POST COMPLETION

CCB

ADDRESS

MEB

SLIBCL

HDRA-RPRIM,R5,$DDHAR,SAV
;; CALL

.NLIST

MEB

ROR

-2 (R5)

SAVE

TST

EXAMINE

BMI
BEQ

19$
7%

7
;7

IF
IF

ADD

#2,R3
7
R3,RPCNT-RPRIM(R5)

MOV

'SINTSV'

SINTSV

'FINAL

MI
EQ

SEEN'

COUNT

FLAGS

FOR

THIS

LINE TABLE
(BIT

MESSAGE

AN INVALID HEADER RECEIVED
SET TO RECEIVE REST OF HEADER

ACCOUNT

;;

BYTE

DDHAR THROUGH

SAVE

D-13

FOR

DATA

BCC

COUNT

CURRENT

UNTIL

COUNT

HEADER

CRC

SET)

]

$5,R3

INC

-~ (R5)

;;

ADD

R3,@-(R5)

MOV

CHECKED

GET REMAINING

HEADER

MARK DATA IN PROGRESS IN FLAGS
INCLUDE

CURRENT COUNT

(BIT @ SET)

TOTAL COUNT

ADD

#RCNT-RTHRD,R5

;;

POINT TO CURRENT COUNT

MOV

R3, (R5)

SET

INC

- (R5)

;;

MOVE

-4(R5) ,R3

;;

GET ADDRESS

RECEIVE

DATA BUFFER

- (R5) ,R3

GET

RECEIVE

DATA

REXTQ

;;

FINISH

CURRENT BYTE COUNT
BUFFER ADDRESS PAST BCC

MSSMGE

.IF

MOV

.IFF
MOV

ADDRESS

BUFFER

« ENDC

ot e WS Wy

COMMON

CODE
g

INVALID

gsS:

HEADER

RECEIVED

$#CS.MTL,R3
31%
(RS)+,R4

BIT
BNE
MOV

;;
;;
;;

MESSAGE TOO LONG ?
IF NE YES, POST COMPLETION
RECOVER PRIMARY CCB ADDRESS

CALL

BUFUSE

MOV

RDBF-RPRIM(RS5)
,R3 ;; SET POINTER TO REC. DAT. BUFF.
409
;;
CLEAR RECEIVE ACTIVE TO FORCE RESYNC

SET UP THIS CCB AGAIN

(CLEARS

'RSTAT')

POST

COMPLETION

RECEIVE

COMPLETE

POINTS

PRIMARY

CCB ADDRESS

#CS,ERR+CS.DCR,R3

MOV

MI,

;;

FORCE

;;

PUT

INC

RADD-RPRIM(RS5)

;;

INCLUDE

MOV

RDBF-RPRIM(R5)
,R3

REXT

CLR

MOV

(R5) +,R4

#RXINT,~- (R3)
(SP)+,R3

MOV
RETURN

GET CSR FOR
COMMON

s
WH

;

ACTIVE

= ADDRESS

FORCE

RECEIVE

MARK NON HEADER
IN

BUFFER

EXIT

GET ADDRESS OF RECEIVE DATA BUFFER
SET UP NEXT RECEIVE BUFFER
IF CS NO BUFFER AVAILABLE TURN OFF RECEIVER
IF NE CLEAR RECEIVE ACTIVE TO RESYNC

RESET PARTIAL COUNT
ENABLE RECEIVER INTERRUPTS
RESTORE R3
RETURN TO SYSTEM

REF

LABEL

;;

RECEIVE

LAST CHAR

PRIMARY CCB ADDRESS
PICK UP ADDITIONAL STATUS
POST RECEIVE COMPLETION

W wme N

RPCNT-RPRIM(RS)

VALID

GET

(L)
s we

CLR

BIS

BIT

SYNC BACK

GET GOOD STATUS

REXT:

TAKE

;
(R5) ,R3
;
SDDRCP
;
RDBF-RSTAT(RS)
,R
BUFSET
REXTI1
409

REXT®:

wy ws

SET ?

CRC

;

BCS

BNE

;

CALL

;;

CALL

YES

RFLAG-RPRIM(RS5)

MOV

ROL

BIS

CLEAR

FLAG

ELSE SET CRC ERROR STATUS FOR DLC
319
;:; GO RETURN BUFFER
RPCNT-RPRIM(R5) ,RCNT-RPRIM(R5) ;; SET REMAINING COUNT
;3 NONE SO END OF MESSAGE
308
RPCNT-RPRIM(RS5) ,@RTHRD-RPRIM(R5) ;; SET TOTAL COUNT IN CCB

;;

SEC

Jfu

ERROR

MOV

BEQ

REXT1:

CRC

25%

ADD

30$:
31$:

RCNT-RPRIM(RS)

258$:

;

TST
BMI

e Wy WE W ws wa Wa

20S:

RESYNC
DAT

BUFFER

D-14

ADDRESS

'RPRIM'

DPCRA:

CLR

- (R5)

BIC

CLEAR

#RCVEN, - (R3)

CLEAR

FOR RESYNC
RPCNT-RFLAG(R5)
;; RESET PARTIAL COUNT
#CS.RSN,RSTAT-RFLAG(R5)
;;
INDICATE A RESYNC
#RINIT, (R3)
;7
ENABLE RECEIVER
REXTI1
;7
FINISH IN COMMON CODE

CLR
BIS
BIS
BR

ws ‘mg e W WME

LSB

W e ey W e e

.DSABL

TE M WE WS W s Ws Ws TMe es

FLAGS WORD
RECEIVE ACTIVE

**-SDPVTI-DPV11

TRANSMIT

INTERRUPT SERVICE

THIS ROUTINE IS ENTERED ON A TRANSMITTER INTERRRUPT VIA
A 'JSR R5,DPVTI' WITH R5 CONTAINING THE ADDRESS OF THE

DEVICE

LINE

TABLE OFFSET

BY 'TCSR'.

INPUTS:

ADDRESS

STACK

DEVICE

LINE

TABLE

'TCSR'

CONTAINS:

@(SP)

INTERRUPTED

2(SP)

INTERRUPTED

BIAS

4 (SP)
6 (SP)

INTERRUPTED

OUTPUTS:

ETC.
. ENABL

LSB

SDPVTI::
MOV

R4 ,-(SP)

:::;

SAVE

MOV

(R5)+,R4

TST

;77

GET

(R4) +

BMI

TEST

108

;;;

DEC

TCNT-TCSR-2(RS)

BEQ

;;;

DECREMENT

208

;:;

.IF

MOV

TRANSMITTER
FOR

MI,

UNDERRUN

EQ,

CSR

ADDRESS

UNDERRUN
-

WAIT

FOR

COUNT

BYTE

COUNT

RUNOUT

MS$SMGE
KISARG,- (SP)

(R5) +,KISAR6G

;:; MAP TO DATA BUFFER

;::

SAVE

@ (R5) +, (R4)

;:;

OUTPUT

(SP) +,KISARG

; ;;

RESTORE

CURRENT

MAPPING

.IFTF
MOVB

’

CHARACTER

LIFT
MOV

MAPPING

.IFTF

INC

- (RS)

MOV

; ;;

UPDATE

(SP) +, R4

;;;

RESTORE

SINTXT
TRANSMITTER
DISABLE

BUFFER

ADDRESS

UNDERRUN

TRANSMITTER

INTERRUPTS

AND WAIT

FOR A

D-15

TIMEOUT

195:

BISB

#TSOM/400,1
(R4)

CLEAR UNDERRUN BIT

;+;
¥

#TUNST, TSTAT-TCSR~- 2(R5)

;;;

SET STATE TO DISABLE TRANSMITTER

MOV

TRANSMIT BYTE COUNT RUNOUT
STATE

PROCESSING

ROUTINES:

‘s

OUTPUT TO

= ADDRESS OF TRANSMITTER CSR
= ADDRESS OF THREAD WORD CELL

WMy

R3
R5

20$:

ADD
BIC

$TPRI-TCSR-2,R5
#TXINT,- (R4)

MOV

SINTSX

(SP) +,R4

;;;
;:;

;3;

POINT TO PRIORITY DATA
CLEAR INTERRUPT ENABLE

RESTORE R4 SO 'SINTSV'

IS HAPPY

;SAVE WITH R5 ON STACK BUT NOT R4

LIFT

MOV

KISAR6,- (SP)

SAVE CURRENT MAPPING

R3,- (SP)

;;

SAVE AN ADDITIONAL REGISTER

.IFTF

MOV

TCSR-TSTAT
(RS) ,R3 ;;
GET TRANSMITTER CSR ADDRESS
@ (R5)+
;:
DISPATCH TO PROCESSING ROUTINE

.DSABL

LSB

**-DPASX-ASSIGN

A TRANSMIT

BUFFER

THIS ROUTINE IS ENTERED VIA THE MATRIX SWITCH TO
QUEUE A CCB FOR TRANSMISSION.
INPUTS:

Ws Wy

MOV
CALLR

= ADDRESS
= ADDRESS

OF CCB TO TRANSMIT
OF DEVICE LINE TABLE

OUTPUTS :

IF THE TRANSMITTER

Wy Ws

R4
RS

INITIATED;

IDLE,

TRANSMISSION

END OF THE

SECONDARY

(OR CHAIN)

IS QUEUED TO

CHAIN.

REGISTERS

R3,

MODIFIED:

R4,

AND R5

Wa We

THE

OTHERWISE, THE CCB

DPASX:

MOV

BIC
ADD

TCSR(R5) ,R3

;

GET TRANSMITTER CSR ADDRESS

KISAR6,- (SP)

;

SAVE CURRENT MAPPING

$TXINT, (R3)
#TPRIM,R5

;
;

DISABLE TRANSMITTER INTERRUPTS
POINT TO PRIMARY CELL

JIFT

MOV
.IFTF

MOV

TST

R3,-(SP)

(RS) +

;

SAVE R3

; PRIMARY ASSIGNED ?
D-16

BNE

109

IF NE,

YES -

CALL

TBSET

;

SET

PRIMARY

BIT

#TXACT, (R3)
STSTR

;
;

TRANSMITTER ACTIVE ?
IF EQ, NO - START IMMEDIATELY

BEQ

10$:
20$:

#STSTR,~ (R5)

WAITI

MOV
MOV

R4,- (SP)

;

SAVE

POINTER TO

R5,R4

;

COPY

POINTER

MOV

(R4) ,R5

;

GET

BNE

208$

;

IF NE,

MOV

(SP)+, (R4)
TEXT?2

;

LINK

FINISH

FOR

STARTUP

INTERRUPT

FIRST CCB

TO CCB

CCB

KEEP GOING

NEW CCB
IN

CHAIN

COMMON

LAST CCB

CODE

WAIT FOR

**-.STSTR-STARTUP
STATE

PROCESSING

Wwe

STATE

QUEUE TO SECONDARY CHAIN

MOV

; SET

STSTR:

BIS

#RTS,-4(R3)

BIS

#TXENA, (R3)
; ENABLE TRANSMITTER
TIMS-TTHRD(RS5)
, TIME-TTHRD(R5) ; START TIMER

MOVB

;

ASSERT

REQUEST TO

SEND

;

**-STCTS-WAIT

FOR

CLEAR

TO SEND

STATE

PROCESSING

H
r

BIT

#CTS,-4(R3)

’

IS CLEAR TO

BNE

STSYN

;

IF NE,

MOV

#STCTS, - (R5)

;

SET

MOV

# SPADB, R4
#TSOM,-(SP)

;
;

SET ADDRESS OF PAD BUFFER
SET TSOM, CLEAR TEOM

TEXT1

;

FINISH

***STSYN*SYMC

MOV
MOV
MOV
BR

**-STCRC-SEND

. ENABL

SEND UP

START

SYNC

TRAIN

FOR CTS

COMMON

CODE

TRAIN REQUIRED STATE PROCESSING

#STDAT,- (R5)
#SSYNB,R4

#TSOM,-(SP)
TEXT®

CRC

STATE

: SET STATE FOR DATA
; SET ADDRESS OF SYNC BUFFER

;

SET TSOM,

; FINISH

CLEAR TEOM

IN COMMON CODE

PROCESSING

LSB

BIS

#TEOM,2(R3)

CALL

TPOST

BNE

198

;

IF NE,

NOTHING

MOV

#STDAT, - (R5)

;

ASSUME

BIT

#CF.SYN,C.FLG-C.BUF(R4) ; ARE SYNC'S REQUIRED ?
209
; IF EQ, NO - LEAVE ASSUMED STATE

BEQ

190$:

;

SEND CRC
POST

COMPLETION

CHANGE

AND

STATE

#STSYN, (R5)

;

ELSE

2089

;

WAIT FOR CRC TO BE

MOV

#STIDL,- (R5)

BIC

BTXENA, (R3)

SET

STATE

SHUT

DOWN

D-17

SET

MORE TO SEND

MOV

STCRC:

STATE

STSYN:

YES

STCTS:

STATE

IS SEND

SEND

SENT

IDLE

TRANSMITTER

SYNC'S

CCB

FOR

INTERRUPT

**-WAITI-WAIT

MOV

#1, TCNT-TSTAT(RS5)

MOVB

TIMS-TSTAT
(R5) ,TIME-TSTAT(RS5)

TEXT?2

; WAIT FOR ONE INTERRUPT

;

FINISH

;

START

TIMER

IN COMMON CODE

**-STIDL-IDLE

STATE PROCESSING

WAITI:

BIC

$RTS, -4 (R3)

: DROP REQUEST TO SEND

TST

- (R5)

STIDL:

305

;

CLRB

TIME-TSTAT(R5)

;

CLEAR

TEXT3

;

FINISH

.DSABL

LSB

TIMER
IN COMMON

CODE

**_TUNST-TRANSMIT DATA UNDER RUN STATE

;
;

RETURN

’

ALL

TRANSMIT

BUFFERS

HIGHER

LEVEL

ADD

#-TTHRD, RS

CLRB

(R5)

; ;TIMEOUT

EXPECTS

; ;RESET

CALL

DPTIM

; ;FAKE

MOV

#STIDL,TSEC-TSTAT (R5)

; ;SET

TEXT3

**-STDAT-DATA

STATE

TIMEOUT

STATE

;:;TAKE

LINE

TABLE

POINTER

COMMON

RETURN

BUFFERS

IDLE

EXIT

DDM

TIMER

PROCESSING

TUNST:

STDAT:

10s:

20%:

GET ADDRESS OF FLAGS WORD
; UPDATE THREAD POINTER

TST

(R5) ,R4
;
$C.FLG-C.STS,
(R5)
(R4) +
;

BPL

10$

;

IF PL,

CALL

TPOST

;

MOV

#STDAT ,- (R5)

’

POST COMPLETION AND SET
ASSUME
DATA CONTINUES

MOV
ADD

LAST

BUFFER

THIS

CCB

THREAD

(BIT

SET)

CCB

FOLLOWING

THIS

BUFFER

BIT

$CF.EOM,C.FLG-C.BUF(R4)

BEQ

209

;

MOV

#STCRC, (R5)

;

ELSE

CHANGE

STATE

FOR CRC

CLR

- (SP)

;

CLEAR

TSOM,

CLEAR

TEOM

IF EQ,

FROM

SEND CRC

NO - LEAVE ASSUMED STATE
TO

;+
;

**-TEXT@P-COMMON

;

**_TEXT1-

;
;

**-TEXT2**-TEXT3-

EXIT

ROUTINES

;

TEXT@:

MOVB

TIMS-TSTAT(R5) ,TIME-TSTAT(R5)

TEXT1l:

ADD

#TCSR-TSTAT+2,R5

;

START TIMER

POINT TO CURRENT BUFFER CELL

.IFT
MOV

(R4)+, (R5)+

;

COPY RELOCATION BIAS

(R4) +

;

SKIP

. IFF
TST

OVER

D-18

RELOCATION

BIAS

CCB

SENT

. IFTF
(R4)+, (R5) +

(R4) , (R5)

COPY
e&

MOV
MOV

VIRTUAL

AND

THE

ADDRESS

BYTE

COUNT

-4 (R5) ,KISAR6

BISB

@-2(R5) , (SP)

BUILD

INC

-2 (R5)

. IFT

UPDATE

MOV

MAP

DATA

BUFFER

. IFTF

TEXT3:

MOV

(SP)+,R3

(SP)+,2(R3)
#TXINT, (R3)

OUTPUT

CHARACTER

BIS

OUTPUT

VIRTUAL ADDRESS

ENABLE

TRANSMITTER

TEXT2:

CHARACTER

RESTORE

LIFT

D-19

AND

FLAGS

INTERRUPTS

GLOSSARY
Asynchronous Transmission
Transmissionin which time intervals between transmitted characters may be of unequal length.
- Transmissionis controlled by start and stop elemcnm at the beginning and end of each character.
Also called start-stop transmission.
;
BDIN

Data Input on the LSI-II bus.
BDOUT
Data Output on the LSI-II bus.
BIAKI
Interrupt Acknawledgc

| Blt-Stllff Protocol

Zero insertion by the transmitter after any succession of five continuous ones deslgned for bm
oriented protocols such as IBM’s Synchmnous Data Link Control (SDLC)

Bits per Second (b/s)
Bit transfer rate per unit of time.

BIRQ

Interrupt Request priority level for LSI-11 bus.

BRPLY
LSI-11 Bus Reply. BRPLYis assertedin response to BDIN or BDOUT
BSYNC
Synchronize
— asserted by the bus master device to indicate that it has placed an address on the
bus.

Buffer
Storage device used to compensate for a dlffercncein the rate of data flow whfm transmitting
~data from one device to another.
BWTBT
Write Byte.

CCITT
Comite Consultatif Internationale de Telegraphle et Telephonie — An international mnsultatwe
committee that sets international communications usage standards.

Control and Status Registers (CSRs)
Communication of control and status information is accomplished through these registers.

Cyclic Redundancy Check (CRC)

An error detection schemein which the check character is generated by taking the remainder
after dividing all the serialized bitsin a block of data by a predetermined binary number.

Data Link Escape (DLE)

A control character used exclusively to provide supplementary line control signals (control character sequences or DLE sequences) These are 2-character sequences where the first characteris
DLE. The second character varies according to the function desired and the code used
|

' Data-Phone DIGITAL Service (DDS)

A communicaitons service of the Bell Systemin which data
iis tmnsmlttedin dlgttal rather than
analog form, thus eliminating the need for modems.

DIGITAL Data Communications Protocol (DDCMP)

DIGITAL’s standard communications protocol for character-oriented protocol.

Direct Memory Access (DMA)

Permits I/O transfer directly into or out of memory without passing through the processor’s general registers.

Electronic Industries Association (EIA)

A standards organization specializingin the electrical and functional characteristics of interface
eqmpment

Full«-Duplex (FDX)

Simultaneous 2-way independent transmission in both dlrectmns

Field-Replaceable Unit (FRU)

‘

Refers to a faulty unit not to be repairedin the field. Unitis replaced thh a good unit and faulty

unit is returned to predetermined location for repair.
Half-Duplex (HDX)

An alternate, one-way-at-a-time independent transmission.

LARS
Fleld Serv1ce Labor Actmty chortlng System
Non-Pmcessor Request (NPR)

Direct memory access-type transfers, (see DMA).

-~ Protocol

A formal set of conventions governing the format and relative timing of message exchange between two communicating processes.

RS-232-C

EIA standard single-ended interface levels to modem.

|
RS-422-A
EIA standa.rd dlfferential mterface levalg to modem.

|
RS-423-A
interface levels to modem.
single-ended
EIA standard

G-2

RS-449

EIA standard connections for RS-422-A and RS-423-A to modem interface.
Synchronous Transi

Transmission in which the data characters and bits are transmitted at a fixed rate with the transmitter and receiver synchronized.

V.35

(CCITT Standard) — Differential current mode-type signal interface for high-speed modems.

G-3

DPV11 SERIAL SYNCHRONOUS

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EK-DPV11-TM-002

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