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EK-DCT11-UG-003

October 1982

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Document:	μ/T-11 User's Guide
Order Number:	EK-DCT11-UG
Revision:	003
Pages:	242
Original Filename:	http://bitsavers.org/pdf/dec/pdp11/t11/T11_UsersMan.pdf

OCR Text

EK-DCT11-UG-003

T-11

USER'S GUIDE

1st Edition, October 1980
2nd Edition, January 1982
3rd Edition, June 1982

The material in this manual is for informational purposes and is
subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any
errors which may appear in this manual.

Printed in U.S.A.

The manuscript for this book was created on a DIGITAL Word
Processing System and, via a translation program, was
automatically typeset on DIGITAL's DECset-8000 Typesetting
System. Book production was done by Educatioria:I Services
Development and Publishing in Marlboro, MA.
The following are trademarks of Digital ~quipment Corporation:
DEC
DECnet
DECUS
DECsystem-IO
DECSYSTEM-20
DECwriter
DIBOL

EduSystem
lAS
MASSBUS
MINt-II
OMNIBUS
OS/8
PDP
PDT

RSTS
RSX
TOPS-I 0
TO~20

U~IBUS

VAX
VMS
VT

CONTENTS
Page
PREFACE
CHAPTER 1

ARCHITECTURE

1.1
1.2
1.2.1
1.2.2
1.2.3
1.3
1.4
1.5
1.5.1
1.5.2
1.5.3
1.5.4
1.5.4.1
1.5.4.2
1.5.5
1.5.5.1
1.5.5.2
1.6

INTRODUCTION.................................................................................................
REGISTERS .............................................................. ,...........................................
General-Purpose Registers .............................................................................
Status Register ...............................................................................................
Mode Register ....... ......... ........ ....... .................... ....... ......................................
ARITHMETIC LOGIC UNIT (ALU) .................................................................
DCTII-A HARDWARE STACK .........................................................................
INTERRUPTS.......................................................................................................
Interrupt Mechanism......................................................................................
Interrupt Posting.............................................................................................
Interrupt Request (IRQ) ................................................................................
Vectors............................................................................................................
Internal Vector Address .........................................................................
External Vector Address.. .............. ...... .............. ...... ..............................
Priority ............................................................................................................
Maskable Interrupts ...............................................................................
Nonmaskable Interrupts.........................................................................
DIRECT MEMORY ACCESS (DMA) MECHANISM .....................................

CHAPTER 2

BUS TRANSACTIONS

2.1
2.2
2.2.1
2.2.2
2.2.3
2.3
2.3.1
2.3.2
2.3.3
2.4
2.4.1
2.4.2
2.5
2.S.1
2.5.1.1
2.5.1.2
2.5.1.3
2.S.2

INTRODUCTION.................................................................................................
BUS TRANSACTION ..........................................................................................
Transaction .....................................................................................................
Microcycle ......................................................................................................
Clock Phase ....................................................................................................
16-BIT STATIC READ TRANSACTION ...........................................................
Output of Address ..........................................................................................
Input of Data ..................................................................................................
Instruction Fetch ....... ,................... ,................................................................
16-BIT STATIC WRITE TRANSACTION .........................................................
Output of Address ..........................................................................................
Output of Data...................................................... ................... ............ ....... ....
16-BIT DYNAMIC READ TRANSACTION .....................................................
O\,ltput of Address ..........................................................................................
Dynamic Address ........ ...........................................................................
Static Address ........................................................................................
Address Control......................................................................................
Input of Data ..................................................................................................

III

I-I
I-I
I-I
1-3
1-4
1-4
1-4
1-5
I-S
1-5
I-S
1-6
1-7
1-7
1-7
1-7
1-8
1-8

2-1
2-1
2-2
2-2
2-2
2-2
2-2
2-2
2-4
2-4
2-4
2-4
2-6
2-6
2-6
2-6
2-6
2-6

CONTENTS (Cont)
Page
2.5.3
2.5.3.1
2.5.3.2
2.6
2.6.1
2.6.1.1
2.6,1.2
2.6.1.3
2.6.2
2.7
2.7.1
2.7.2
2.7.3
2.8
2.8.1
2.8.2
2.9
2.9.1
2.9.1.1
2.9.1.2
2.9.1.3
2.9.2
2.9.3
2.9.3.1
2.9.3.2
2.10
2.10.1
2.10.1.1
2.10.1.2
2.10.1.3
2.10.2
2.11
2.11.1
2.11.2
2.11.3
2.12
2.12.1
2.12.2
2.13
2.14
2.14.1
2.14.2
2.14.3
2.14.4
2.15

Instruction Fetch ............................................................................................. 2-9
4K/16K Mode........................................................................................ 2-9
64K Mode............................................................................................... 2-9
16-BIT DYNAMIC WRITE TRANSACTION ................................................... 2-10
Output 'of Address .......................................................................................... 2-10
Dynamic Address................................................................................... 2-10
Static Address ........................................................................................ 2-10
Address Control.............. ....... ............................ ....... .............................. 2-12
Output of Data................................................................................................ 2-12
8-BIT STATIC READ TRANSACTION ............................................................. 2-13
Output of Address ........................................................................................... 2-13
Input of Data ............................................. ,.................................................... 2-13
Instruction Fetch ............................................................................................ 2-14
8-BIT STATIC WRITE TRANSACTION ........................................................... 2-14
Output of Address .......................................................................................... 2-16
Output of Data...... ....... ....... ........ ......... ....... ....... ...... ..... ......... ......................... 2-16
8-BIT DYNAMIC READ TRANSACTION ....................................................... 2-16
Output of Address .......................................................................................... 2-18
Dynamic Address .... ........ ............. .................... ...... ........ ....... ........ ......... 2-18
Static Address .... ....... ....... ........ ........ ....... ............ ........ ........................... 2-18
Address Control ...................................................................................... 2-20
Input of Data .................................................................................................. 2-20
Instruction Fetch ............................................................................................ 2-21
4K/16K Mode ........................................................................................ 2-21
64K Mode ............................................................................................... 2-21
8-BIT DYNAMIC WRITE TRANSACTION ..................................................... 2-21
Output of Address .......................................................................................... 2-21
Dynamic Address ................................................................................... 2-21
Static Address ..... ........ ........ ....... ....... ...... ............... ...... ....... ....... ............ 2-21
Address Control ...................................................................................... 2-24
Output of Data................................................................................................ 2-24
REFRESH TRANSACTION ............................................................................... 2-25
Output of Refresh Address ............................................................................. 2-25
Address Control .............................................................................................. 2-25
Output of SEL<O> and SEL< 1> ........ ~ ..................................................... 2-27
lACK (INTERRUPT ACKNOWLEDGE) TRANSACTION ............................ 2-27
Output of Interrupt Acknowledge Data ......................................................... 2-27
Input of Vector Address ................................................................................. 2-28
BUSNOP (NO OPERATION) TRANSACTION ............................................... 2-29
DMA (DIRECT MEMORY ACCESS) TRANSACTION ................................. 2-29
Three-State of DAL< 15:0> ......................................................................... 2-29
Output of - RAS, - CAS, and Pl ................................................................. 2-31
Output of Direct Memory Grant (DMG) ....................................................... 2-31
READY Input ................................................................................................ 2-31
ASPI (ASSERT PRIORITY IN) TRANSACTION ............................................ 2-31

CONTENTS (Coot)
Page
CHAPTER 3

PIN DESCRIPTIONS

3.1
3.2
3.2.1
3.2.2
3.2.3
3.3
3.3.1
3.3.2
3.3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.4.1
3.4.4.2
3.4.5
3.4.6
3.5
3.5.1
3.5.2
3.5.2.1
3.5.2.2
3.5.2.3
3.5.2.4
3.5.2.5
3.5.2.6
3.5.3
3.5.4
3.6
3.6.1
3.6.2

INTRODUCTION................................................................................................. 3-1
DATA ADDRESS LINES (DAL<15:0> ).......................................................... 3-4
16-Bit Mode - DAL<15:0> ......................................................................... 3-5
8-Bit Mode - DAL< 15:8> ........................................................................... 3-6
8-Bit Mode - DAL<7:0> ............................................................................. 3-6
ADDRESS INTERRUPT (AI <7:0> )................................................................. 3-7
AI<7:0> at -RAS and -CAS Time (Static Mode) .................................. 3-7
AI<7:0> at -RAS and -CAS Time (Dynamic Mode) ............................. 3-7
AI <7:0> at Priority In (PI) Time
(Dynamic and Static Modes).......................................................................... 3-8
CONTROL LINES................................................................................................ 3-9
-RAS (Row Address Strobe) ........................................................................ 3-10
-CAS (Column Address Strobe) .................................................................. 3-10
PI (Priority In) ................................................................................................ 3-11
Rj - WHB and Rj - WLB ............................................................................. 3-11
Rj - WHB and Rj - WLB (l6-Bit Mode) ............................................. 3-11
Rj - WHB (-RD) and Rj - WLB (- WT) (8-Bit Mode) .................... 3-11
SEL< 1> and SEL<O> .............................................................................. 3-11
READY .......................................................................................................... 3-11
MISCELLANEOUS SIGNALS ........................................................................... 3-13
- BCLR (Bus Clear) ........... ........ ...... ......... ........ ..... ........ ....... ............... ......... 3-13
PUP (Power-Up) ............................................................................................. 3-13
Power-Up (PUP) Input ........................................................................... 3-14
Bus Clear (-BCLR) .............................................................................. 3-14
Mode Register Load. ........ ...... ........ ........ ...... ..... ......... ....... ....... ......... ..... 3-14
Refresh or Busnop Transaction .............................................................. 3-14
Loading the SP, PC, and PSW ............................................................... 3-14
ASPI Transaction.... ....... ......... ........ ....... ....... ....... ............... ....... ....... ..... 3-15
COUT (Clock Output) ................................................................................... 3-15
XTLl and XTLO (Crystal Inputs) .................................................................. 3-15
POWER PINS ........................................................................................................ 3-16
GND and BGND ............................................................................................ 3-16
Vee ................................................................................................................. 3-16

CHAPTER 4

MODE SELECTION

4.1
4.2
4.2.1
4.2.1.1
4.2.1.2
4.2.2
4.2.2.1
4.2.2.2

INTRODUCTION.................................................................................................
MODES RELATED TO FUNCTION .................................................................
16-Bit or 8-Bit Mode (MR < 11 > ) ................................................. ................
16-Bit Mode............................................................................................
8-Bit Mode..............................................................................................
Dynamic or Static Mode (MR<9> ).............................................................
Dynamic Mode .......................................................................................
Static Mode ............................................................................................

4-1
4-1
4-1
4-1
4-2
4-3
4-3
4-3

CONTENTS (Cont)
Page
4.2.3
4.2.4
4.2.5
4.3
4.3.1
4.3.2
4.3.3
4.4
4.5
4.5.1
4.5.1.1
4.5.1.2
4.5.1.3
4.5.2
4.5.2.1
4.5.2.2
4.5.2.3
4.5.3
4.5.3.1
4.5.3.2
4.5.4
4.5.4.1
4.5.4.2

64K or 4K/ 16K Mode (MR < 10> ) ..............................................................
Tester or User Mode (MR < 12» .................................................................
Start and Restart Address (MR<15:13» ....................................................
MODES RELATED TO TIMING .......................................................................
Constant or Processor Clock (MR <0> ) .......................................................
Long or Standard Microcycle (MR < 1> ) .....................................................
Normal or Delayed Read/Write (MR<8> ).................................................
MODE REGISTER BIT SETTING .....................................................................
MODE REGISTER SELECTION GUIDELINES .............................................
Minimum Cost ................................................................................................
8-Bit Mode..............................................................................................
Dynamic Mode .......................................................................................
Long Microcycle Mode ..........................................................................
Maximum Speed.............................................................................................
16-Bit Mode ............................................ ,...............................................
Static Mode ............................................................................................
Standard Microcycle .... ....... ........ .................... .......................................
Minimum Size (Chip Count) ..........................................................................
8-Bit Mode..............................................................................................
Static Mode ............................................................................................
Minimum Development Time.........................................................................
16-Bit Mode............................................................................................
Static Mode ............................................................................................

CHAPTERS

INTERF ACING

5.1
5.2
5.3
5.4
5.4.1
5.4.2
5.5
5.6
5.6.1
5.6.2
5.7
5.7.1
5.7.2
5.7.3
5.7.4
5.7.5
5.8
5.8.1
5.8.1.1

INTRODUCTION................................................................................................. 5-1
POWER-UP............................................................................................................ 5-1
LOADING THE MODE REGISTER.................................................................. 5-1
CLOCK................................................................................................................... 5-2
Crystal-Based Clock ....................................................................................... 5-3
TTL Oscillator-Based Clock........................................................................... 5-4
ADDRESS LATCH AND DECODE ........... :....................................................... 5-4
MEMORY SUBSYSTEMS .................................................................................. 5-5
16-Bit Mode Memory System......................................................................... 5-5
8-Bit Mode Memory System........................................................................... 5-8
INTERRUPTS ....................................................................................................... 5-11
Posting Interrupts ........................................................................................... 5-11
Decoding lACK Information .......................................................................... 5-11
External Vectors........................... .................................................................. 5-11
Using a Priority Encoder Chip ........................................................................ 5-11
Direct CP Encoding........................................................................................ 5-16
DMA ....................................................................................................................... 5-16
Single-Channel DMA Controller (16-Bit Mode) ............................................ 5-17
Address Latches
(Single-Channel DMA Controller) ......................................................... 5-17
Pulse Mode Clock
(Single-Channel DMA Controller) ......................................................... 5-17

5.8.1.2

4-3
4-3
4-4
4-4
4-4
4-4
4-4
4-4
4-5
4-5
4-5
4-5
4-5
4-5
4-5
4-5
4-5
4-5
4-6
4-6
4-6
4-6
4-6

CONTENTS (Cont)
Page

5.8.2
5.9
5.9.1
5.9.2
5.9.3

Address Decode Structures .................................................................... 5-17
Operation Sequence
(Single-Channel DMA Controller) ......................................................... 5-17
Software DMA Requests ................................................................................ 5-19
WORKING WITH PERIPHERAL CHIPS ......................................................... 5-20
8155 - RAM, Three Ports, and Timer ............................................................ 5-20
2651-PUSART ............................................................................................. 5-20
DC003 - Interrupt Logic ................................................................................ 5-21

CHAPTER 6

ADDRESSING MODES AND INSTRUCTION SET

6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.3.1
6.2.3.2
6.2.3.3
6.2.3.4
6.2.4
6.2.5
6.2.5.1
6.2.5.2
6.2.5.3
6.2.5.4

INTRODUCTION................................................................................................. 6-1
ADDRESSING MODES....................................................................................... 6-1
Single-Operand Addressing ............................................................ ....... ......... 6-3
Double-Operand Addressing .......................................... ............. ................... 6-3
Direct Addressing...................... ...... ............................................................... 6-4
Register Mode........... ............................................................................. 6-6
Autoincrement Mode [OPR (Rn) + ] ..................................................... 6-7
Autodecrement Mode [OPR-(Rn)]...................................................... 6-9
Index Mode [OPR X(Rn)] ..................................................................... 6-10
Deferred (Indirect) Addressing ...................................................................... 6-12
Use of the PC as a General-Purpose Register ................................................. 6-16
Immediate Mode [OPR #n,OO] ............................................................. 6-16
Absolute Addressing [OPR @#A] .......................................................... 6-17
Relative Addressing [OPR A or OPR X(PC)] ....................................... 6-18
Relative-Deferred Addressing
[OPR @A or OPR @X(PC)] .................................................................. 6-19
Use of the Stack Pointer as a
General-Purpose Register ............................................................................... 6-20
INSTRUCTION SET ............................................................................................ 6-20
Instruction Formats ........................................................................................ 6-21
List of Instructions .......................................................................................... 6-24
Single-Operand Instructions ........................................................................... 6-27
General................. ......... .............................................................. ........... 6-27
Shifts and Rotates .................................................................................. 6-31
Multiple-Precision .................................................................................. 6-35
PS Word Operators ................................................................................ 6-37
Double-Operand Instructions ......................................................................... 6-39
General ................................................................................................... 6-39
Logical .................................................................................................... 6-42
Program Control Instructions ......................................................................... 6-45
Branches... ................................ ...... ........ ................................................ 6-45
Signed Conditional Branches ................................................................. 6-49
Unsigned Conditional Branches ............................................................. 6-51
Jump and Subroutine Instructions ......................................................... 6-52
Traps ....................................................................................................... 6-57
Reserved Instruction Traps .................................................................... 6-61

5.8.1.3
5.8.1.4

6.2.6
6.3
6.3.1
6.3.2
6.3.3
6.3.3.1
6.3.3.2
6.3.3.3
6.3.3.4
6.3.4
6.3.4.1
6.3.4.2
6.3.5
6.3.5.1
6.3.5.2
6.3.5.3
6.3.5.4
6.3.5.5
6.3.5.6

vii

CONTENTS (Cont)
Page
6.3.5.7
6.3.S.8
6.3.S.9
6.3.S.10
6.3.S.11
6.3.6
6.3.7

Halt Interrupt ......................................................................................... 6-61
Trace Trap .............................................................................................. 6-61
Power Failure Interrupt .......................................................................... 6-61
CP<3:0> Interrupts ............................................................................. 6-61
Special Cases of the T Bit ...................................................................... 6-61
Miscellaneous Instructions ............................................................................. 6-62
Condition Code Operators .............................................................................. 6-63

APPENDIX A

T A8LES AND TIMING DIAGRAMS

APPENDIX 8

SOFTWARE DIFFERENCES

B.I
B.2
B.2.1
B.2.2
B.2.3
B.2.4

INTRODUCTION................................................................................................. B-1
ADDRESSING MODES....................................................................................... 8-1
Modes 2 and 4................................................................................................. 8-1
Modes 3 and S ............................................................................. .................... B-2
Using the PC Contents as the Source Operand .............................................. B-2
Jump (JMP) and Jump to Subroutine (JSR)
Instructions ..................................................................................................... 8-3
PDP-II INSTRUCTION SET .............................................................................. B-3
Instructions Not Common to All PDP-lIs ..................................................... B-3
MFPT Instruction................................................................................... 8-4
MFPS Instruction.............................................................. ....... ....... ....... B-4
MTPS Instruction ......... :......................................................................... B-S
Basic Instruction Execution............................................................................ B-S
Halt Instruction...................................................................................... 8-6
Reset Instruction .................................................................................... 8-6
Instructions Not Executed.............................................................................. B-7
Effect of the T Bit (Instruction Trace Trap) .................................................. B-7
DCTlI-AA INSTRUCTION EXECUTION SEQUENCE
ON THE DATA BUS ............................................................................................ B-8
EXCEPTIONS AND INTERRUPTS .................................................................. B-8
Bus Errors............. ........................ .................................................................. B-9
Internal Register Access ................................................................................. B-I0
POWER-UP ............................................................................................................ B-IO

B.3
B.3.1
B.3.1.1
B.3.1.2
B.3.1.3
B.3.2
8.3.2.1
B.3.2.2
B.3.3
8.3.4
B.4
B.5
B.S.I
B.S.2
8.6

FIGURES
Figure No.
1-1

1-2
1-3

1-4
1-5
1-6

Title
DCTII-AA, Block Diagram ...................................................................................
General-Purpose Registers ......................................................... ........ ...... ....... ........
Processor Status Word .............................................................................. ........ ......
Mode Register.........................................................................................................
Interrupt Request....................................................................................................
I nterrupt Timing .....................................................................................................

viii

Page
1-2
1-3
1-3
1-4
I-S
1-6

FIGURES (Cont)
Figure No.
1-7
\-8

2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-\ 0

2-\1
2-\2

2-13
2-14
2-\5
2-16
2-\7
2-18
2-\9
2-20
2-2\

2-22
2-23
2-24
3-1
3-2
3-3
3-4
3-5
3-6
4-\

5-\
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-\3
5-\4
5-15

Title

Page

DMA Timing .......................................................................................................... 1-9
DMA, Block Diagram............................................................................................. 1-9
Parts of a Transaction .......... ......................... ........ ........................... ........ ....... ........ 2-1
16-Bit Static Read, Block Diagram ........................................................................ 2-3
16-Bit Static Read Timing ...................................................................................... 2-3
16-Bit Static Write, Block Diagram........................................................................ 2-5
16-Bit Static Write Timing ..................................................................................... 2-5
16-Bit Dynamic Read, Block Diagram ................................................................... 2-7
16-Bit Dynamic Read Timing ................................................................................. 2-8
16-Bit Dynamic Write, Block Diagram .................................................................. 2-10
16-Bit Dynamic Write Timing ................................................................................ 2-11
8-Bit Static Read, Block Diagram .......................................................................... 2-14
8-Bit Static Read Timing ........................................................................................ 2-15
8-Bit Static Write, Block Diagram ......................................................................... 2-16
8-Bit Static Write Timing ....................................................................................... 2-17
8-Bit Dynamic Read, Block Diagram ..................................................................... 2-18
8-Bit Dynamic Read Timing ........ : .......................................................................... 2-19
8-Bit Dynamic Write, Block Diagram .................................................................... 2-22
8-Bit Dynamic Write Timing .................................................................................. 2-23
Refresh Transaction, Block Diagram ...................................................................... 2-26
Refresh Transaction Timing ................................................................................... 2-26
lACK Transaction, Block Diagram ........................................................................ 2-27
lACK Transaction Timing ...................................................................................... 2-28
DMA Timing .......................................................................................................... 2-30
ASPI Transaction, Block Diagram ......................................................................... 2-32
ASPI Transaction Timing ....................................................................................... 2-32
DCTI1-AA Pin Layout........................................................................................... 3-2
Leading and Trailing Edge..................................................................................... 3-10
READY Timing ...................................................................................................... 3-12
Power-Up Sequence, Block Diagram ...................................................................... 3-14
Power-Up Sequence Timing .................................................................................... 3-15
COUT Timing ......................................................................................................... 3-16
Mode Register......................................................................................................... 4-2
Power-Up Circuit .................................................................................................... 5-2
Mode Register Loading .......................................................................................... 5-2
Crystal Oscillator Clock........................................................................... ....... ........ 5-3
TTL Oscillator Clock ............................. ........ ........ .............. ............................ ....... 5-4
TTL Oscillator Waveform ...................................................................................... 5-4
Gating XTL1 .......................................................................................................... 5-4
16-Bit Address Latch and Decode .......................................................................... 5-5
8-Bit Address Latch and Decode ...................................................................... ...... 5-5
16-Bit ROM (4K) and Dynamic RAM (32K) Subsystem ...................................... 5-6
16-Bit System Memory Map................................................................................... 5-7
Column Address Setup and Hold-Time Calculations ............................................. 5-8
16-Bit/8-Bit Memory Organization ........................................................................ 5-9
8-Bit System Memory Map ..................................................................................... 5-10
8-Bit ROM (2K) and Dynamic RAM (16K) Subsystem ........................................ 5-10
General Interrupt .................................................................................................... 5-11

FIGURES (Coot)
Figure No.
5-16
5-17
5-18
5-19
5-20
5-21
5-22
5-23
5-24
5-25
5-26
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-33
6-34
6-35
6-36
6-37

Title

Page

Decoding lACK Information for 16 CP Devices .................................................... 5-12
Interrupt System ..................................................................................................... 5-13
Driving an External Vector During lACK ............................................................. 5-14
Interrupt Request Circuit (Priority Encoder) ......................................................... 5-15
Direct CP Encoding Interrupt System .................................................................... 5-16
Single-Channel DMA ............................................................................................. 5-18
Software DMR Control .......................................................................................... 5-19
8155 RAM .............................................................................................................. 5-20
2651 PUSART ........................................................................................................ 5-21
DC003 Interrupt Logic ........................................................................................... 5-22
DC003 at Different Priority Levels ........................................................................ 5-23
Single-Operand Addressing .................................................................................... 6-3
Double-Operand Addressing................................................................................... 6-3
Mode 0 Register....... ......... ........ ........ ........ ....... ........ .............. ................................. 6-4
Mode 2 Autoincrement ..................................................... ...................................... 6-5
Mode 4 Autodecrement .......................................................................... ................ 6-5
Mode 6 Index .......................................................................................................... 6-5
INC R3 Increment.................................................................................................. 6-6
ADD R2, R4 Add ................................................................................................... 6-7
COMB R4 Complement Byte................................................................................. 6-7
CLR (R5)+ Clear .................................................................................................. 6-8
CLRB (R5) + Clear Byte ....................................................................................... 6-8
ADD (R2) + R4 Add............................................................................................. 6-8
INC -(RO) Increment ........................................................................................... 6-9
INCB -(RO) Increment Byte ................................................................................ 6-9
ADD -(R3), RO Add ............................................................................................. 6-10
CLR 200 (R4) Clear ............................................................................................... 6-11
COMB 200 (Rl) Complement Byte ....................................................................... 6-11
ADD 30 (R2), 20 (R5) Add .................................................................................... 6-12
Mode 1 Register-Deferred ...................................................................................... 6-12
Mode 3 Autoincrement-Deferred ............................................................................ 6-13
Mode 5 Autodecrement-Deferred ........................................................................... 6-13
Mode 7 Index-Deferred ........................................................................................... 6-14
CLR @ R5 Clear ..................................................................................................... 6-14
INC @ (R2) + Increment ...................................................................................... 6-14
COM @ (RO) Complement ..................................................................................... 6-15
ADD @ 1000 (R2), Rl Add .................................................................................... 6-15
ADD # 10, RO Add ................................................................................................. 6-17
CLR@#1100Clear ............................................................................................... 6-17
ADD @ # 2000 Add ................................................................................................ 6-18
INC A Increment. ................................................................................................... 6-19
CLR @ A Clear ....................................................................................................... 6-19
Single-Operand Group ............................................................................................ 6-21
Double-Operand Group .......................................................................................... 6-21
Program Control Group Branch .............................................................................. 6-21
Program Control Group JSR .................................................................................. 6-21
Program Control Group RTS .................................................................................. 6-22
Program Control Group Traps ................................................................................ 6-22

FIGURES (Coot)
Figure No.

6-38
6-39
6-40
6-41
A-I
A-2
A-3
A-4
A-S
A-6
A-7
A-8
A-9
A-IO
A-II
A-12
A-13
A-14
A-IS
A-16
A-17
A-18
A-19
A-20
A-21
A-22

Title

Page

Program Control Group Subtract ........................................................................... 6-22
Operate Group ........................................................................................................ 6-22
Condition Group ..................................................................................................... 6-22
Byte Instructions ..................................................................................................... 6-23
DCTlI-AA, Block Diagram ................................................................................... A-23
16-Bit Static Read ................................................................................................... A-24
16-Bit Static Write .................................................................................................. A-26
16-Bit Dynamic Read .............................................................................................. A-28
16-Bit Dynamic Write ............................................................................................. A-30
8-.Bit Static Read ..................................................................................................... A-32
8-Bit Static Write .................................................................................................... A-34
8-Bit Dynamic Read ................................................................................................ A-36
8-Bit Dynamic Write ............................................................................................... A-38
Refresh .................................................................................................................... A-40
lACK Transaction .................................................................................................. A-42
Busnop Transaction ................................................................................................. A-44
D MA Transaction ................................................................................................... A-46
ASPI Transaction ................................................................................................... A-48
Ready ...................................................................................................................... A-SO
Power-Up ................................................................................................................ A-S2
XTAL and COUT ................................................................................................... A-S4
DCTII-AA Pin Layout ........................................................................................... A-S6
Mode Register ......................................................................................................... A-S7
Processor Status Word ............................................................................................ A-S7
16-Bit Application ................................................................................................... A-S8
8-Bit Application ..................................................................................................... A-S9

TABLES
Table No.
1-\

1-2
2-1
2-2
2-3
2-4
2-S
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13

Title

Page

I nterrupt Signals ..................................................................................................... 1-6
Interrupt Decode..................................................................................................... 1-7
16-Bit Static Write Conditions................................................................................ 2-6
16-Bit Static Write Data Strobes ............................................................................ 2-6
16-Bit Dynamic Read Addressing Scheme .................................................... ......... 2-8
16-Bit Dynamic Read AI Addressing ..................................................................... 2-9
16-Bit Dynamic Read Address Strobes................................................................... 2-9
16-Bit Dynamic Write Addressing ~cheme ............................................................ 2-11
16-Bit Dynamic Write AI Addressing .................................................................... 2-12
16-Bit Dynamic Write Address Strobes .................................................................. 2-12
16-Bit Dynamic Write Data Strobes ....................................................................... 2-12
16-Bit Dynamic Write Conditions ........................................................................... 2-13
16-Bit Dynamic Write Control Timing ................................................................... 2-13
8-Bit Static Read Control Timing ........................................................................... 2-1S
8-Bit Static Read Data Strobes ............................................................................... 2-18

TABLES (Coot)
Table No.

2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
4-1
4-2
5-1
5-2
A-I
A-2
A-3
A-4
A-5
A-6
A-7
A-8
A-9
A-IO
A-II
A-I2
A-I3
A-14
A-I5
A-I6
A-I7
A-I8
A-I9
A-20
A-21
A-22

Title

Page

8-Bit Static Write Control Timing .......................................................................... 2-18
8-Bit Dynamic Read Addressing Scheme ............................................................... 2-20
8-Bit Dynamic AI Addressing ................................................................................. 2-20
8-Bit Dynamic Read Address Strobes .................................................................... 2-20
8-Bit Dynamic Read Control Timing ...................................................................... 2-20
8-Bit Dynamic Write Addressing Scheme .............................................................. 2-24
8-Bit Dynamic Write AI Addressing ...................................................................... 2-24
8-Bit Dynamic Write Address Strobes .................................................................... 2-24
8-Blt Dynamic Write Data Strobes ......................................................................... 2-24
8-Bit Dynamic Write Control Timing ..................................................................... 2-25
Interrupt Acknowledge Data .................................................................................. 2-28
Mapping of AI onto DAL in an lACK Transaction ............................................... 3-1
Signal and Pin Utilization, 16-Bit Mode ................................................................. 3-3
Signal and Pin Utilization, 8-Bit Mode................................................................... 3-4
SEL< 1:0> Functions in Static Mode
or Dynamic 64K Mode............................................................................................ 3-5
SEL< 1:0> Functions in Dynamic 4K/ 16K Mode ............................................... 3-5
AI Functions................ ............................... ...... ........ ..... ............... ...... .................... 3-8
Control Signal Usage .............................................................................................. 3-9
Refresh and Busnop ................................................................................................ 3-15
Mode Register Bit Settings..................................................................................... 4-2
DCTII-AA Modes.................................................................................................. 4-3
Control Signals for Each Transaction.... ............... ...... ...... ...... ........ ........................ 5-8
Data Bus for Each Transaction............................................................................... 5-9
Interrupt Decode................................................................................................ ..... A-I
DC Characteristics ................................................................................................. A-2
Sequences of Transactions ..... ....... ....... ....... ......... ...... .................................. ........... A-4
Signal and Pin Utilization, 16-Bit Mode ................................................................. A-5
Signal and Pin Utilization, 8-Bit Mode ................................................................... A-6
I6-Bit Dynamic Write Addressing Scheme ............................................................ A-7
SEL< 1:0> Functions in Static Mode
or Dynamic 64K Mode ............................................................................................ A-7
SEL<I:O> Functions in Dynamic 4K/I6K Mode ............................................... A-7
AI Functions... ......... ........ .......... ....... ....... ....... ............... ....... ....... ........................... A-7
Control Signals for Each Transaction.. ...... ...... ........ ...... ........ .............. ................... A-8
Data Bus for Each Transaction.. ........ ........ ...... ........ ............. ......... ...... ................... A-8
Summary of DCTII-AA Instructions ..................................................................... A-9
Numerical Op Code List.. ....................................................................................... A-II
Reserved Trap and Interrupt Vectors ..................................................................... A-II
7-Bit ASCII Code ................................................................................................... A-12
Octal, Hex, Decimal Memory Addresses ............................................................... A-13
XOR and Single-Operand Instructions ................................................................... A-I5
Double-Operand Instructions .................................................................................. A-I6
Jump and Subroutine Instructions .......................................................................... A-17
Branch, Trap, and Interrupt Instructions ................................................................ A-I8
Miscellaneous and Condition Code Instructions ..................................................... A-I9
Maximum Latencies ............................................................................................... A-20

xii

TABLES (Cont)
Table No.

B-1
B-2
B-3
B-4
B-5
B-6

Title

Page

Processor Codes...................................................................................................... B-4
PDP-II Instructions Not Executed by the DCTII-AA .......................................... B-7
Interrupt Priority Codes .......................................................................................... B-I0
Start/Restart Addresses ......................................................................................... B-ll
Software Differences and Compatibilities .............................................................. B-12
Hardware Differences - Traps
(Transparent to Software) ....................................................................................... B-21

xiii

PRELIMINARY

PREFACE

This user's guide is designed for engineers familiar with PDP-II architecture. Chapters I through 6
offer a tutorial on DCTII-AA architecture and operation. (Chapter 5 includes some design examples.)
Appendix A contains reference material (instruction set tables and timing diagrams). Appendix B
briefly describes the software differences and compatibilities among the DCT1I-AA and other members of the PDP-II family.
This guide can be used by both hardware and software specialists. The hardware specialist should especially become familiar with Chapters I through 5, whereas the software specialist should become familiar with Chapters I, 4, and 6.
One of the characteristics of the DCTlI-AA is that it can be user-programmed to operate in a variety
of modes, which affect both its functionality and timing. Chapter 2 (Bus Transactions) and Chapter 3
(Pin Descriptions) are arranged by mode. This allows the user to find, in one place, all the information
relevant to a selected mode. A user not knowing which mode to use for a given application should first
read Chapter 4 (Mode Selection).

PRELIMINARY

-CHAPTER 1
ARCHITECTURE

1.1 INTRODUCTION
This chapter describes the internal architecture of the DCTII-AA microprocessor. The chapter is divided into five sections covering all aspects of the architecture:

•
•
•
•
•

Registers
Arithmetic and logic unit (ALU)
DCTII-AA hardware stack
Interrupts
DMA mechanism

1.2 REGISTERS
The DCTII-AA contains a number of internal registers used for various purposes (refer to Figure 1-1).
The registers are divided into three groups:

---

•
•
•

General-Purpose
Status
Mode

1.2.1 General-Purpose Registers
The DCTII-AA microprocessor contains eight 16-bit general-purpose registers that can perform a variety of functions. These registers can serve as accumulators, index registers, autoincrement registers,
autodecrement registers, or stack pointers for temporary storage of data. Arithmetic operations can be
performed between one general-purpose register and another, one memory location or device register
and another, between memory locations, or between a device register and a general register. The eight
16-bit general-purpose registers (RO-R 7) are identified in Figure 1-2.

1-1

::JJ

-3:r-

-Z

INTERRUPTS

DATAl
ADDRESS
BUFFER
liN/OUT)

::JJ

RO-R7, PS
REGISTER

ADDRESS/
INTERRUPT
BUFFER
DYNAMIC
MEMORY
SUPPORT

SEL <0>, SEL <1>
-RAS
BUS
CONTROL
SIGNAL
BUFFERS

OPERATING
MODE REGISTER

PUP

-CAS
R/-WLB
R/-WHB
PI
READY

-BCLR
CLOCK
GENERATOR

VCC

GND

BGND -

XTLO

XTLI

COUT
MR 5759

Figure I-I

DCTII-AA, Block Diagram

PRELIMINARY
HI

STACK POINTER

PROGRAM COUNTER

GENERAL REGISTERS

MR-5272

Figure 1-2

General-Purpose Registers

Registers R6 and R 7 in the OCT ll-AA are dedicated. R6 serves as the stack pointer (SP) and contains
the location (address) of the last entry in the stack. Register R7 serves as the processor program
counter (PC) and contains the address of the next instruction to be executed. The PC is normally used
for addressing purposes only and not as an accumulator.

1.2.2 Status Register
The processor status word (PSW) contains information on the current processor status. This information includes the current processor priority, the condition codes describing the arithmetic or logic results of the last instruction, and an indicator for detecting the execution of an instruction to be trapped
during program debugging. This indicator (the T bit) cannot be directly set or cleared. The T bit can
only be set or cleared when entering or exiting an interrupt routine.
The PSW format is shown in Figure 1-3. Certain instructions allow programmed manipulation of condition code bits and loading and storing (moving) the processor status.
PROCESSOR STATUS
15

<15:8> READ AS ZEROS
03 NEGATIVE
MR-5273

Figure 1-3

Processor Status Word

1-3

PRELIMINARY
1.2.3 Mode Register
The DCTII-AA incorporates a user-loadable mode register (refer to Figure 1-4). The mode register is
loaded at power-up or when a reset instruction is issued. Access to the mode register is not possible at
any other time. The user has the option of selecting any combination of the following modes.
•
•
•
•
•
•
•
•

l6-bit or 8-bit data bus
Dynamic or static memory support
64K or 4K/ 16K dynamic memory support
Constant or processor clock
Long or standard microcycle
Normal or delayed read/write timing
Tester or user operation
One of eight start/restart address pairs

A complete discussion of the mode register is contained in Chapter 4.
15

01
LONG

STD
<15:13>
12
11
10
09

START/RESTART ADDRESS
TESTER/U.SER MODE
16·BIT/8·BIT BUS
64K/4K OR i6K MEMORY
DYNAMIC/STATIC MEMORY

08
<7:2>
01
00

ADDRESS BITS
<15:13>

START
ADDRESS

RESTART
ADDRESS

7
6
5
4
3
2
1
0

172000
173000
000000
010000
020000
040000
100000
140000

172004
173004
000004
010004
020004
040004
100004
140004

NORMAL/DELAYED RIW
RESERVED
LONG/STANDARD MICROCYCLE
CONSTANT/PROCESSOR MODE CLOCK

MR 4843

Figure \-4

Mode Register

1.3 ARITHMETIC LOGIC UNIT (ALU)
Arithmetic and logical instructions of the 16-bit CPU are executed in the ALU. The ALU internally
communicates with registers and buffers in order to execute instructions.
1.4 DCTll-AA HARDWARE STACK
The hardware stack is part of the basic design architecture of the DCT II-AA. It is an area of memory
set aside by the programmer or by the operating system for temporary storage and linkage. It is handled
on a LI FO (last in/first out) basis, where items are retrieved in the reverse of the order in which they
were stored. On the DCTll-AA the stack starts at the highest location reserved for it (3768 at powerup) and expands linearly downward to a lower address as items are added to the stack. There is no stack
overflow warning.
I t is not necessary to keep track of the actual locations into which data is being stacked. This is done
automatically through the use of the stack pointer (SP). Register six (R6) always contains the memory

1-4

PRELIMINARY
address of the last item stored in the stack. Instructions associated with subroutine linkage and interrupt service automatically use register six as the hardware stack pointer. For this reason, R6 is frequently referred to as the system SP. The hardware stack is organized in full-word units only.

1.5

INTERRUPTS

Interrupts are requests (made by peripheral devices) that cause the processor to temporarily suspend its
present program execution to service the requesting device. A device can interrupt the processor only
when its priority is higher than the processor priority indicated by PSW <7:5>.
The DCTII-AA supports a vectored interrupt structure (with optional internally generated vector addresses) with priority on four levels encoded on four lines. In addition, on separate pins it supports two
nonmaskable interrupts, power fail ( - PF) and - HALT.

1.5.1

Interrupt Mechanism

When the DCT II-AA receives an interrupt, no action is taken until the end of the current instruction
(refer to Figure 1-5). Interrupts are only read during a read transaction or assert priority in (ASP!)
transaction. Before fetching the next instruction, the DCTII-AA arbitrates the interrupt priority. If the
interrupt request has a higher priority than the processor's, it initiates an interrupt acknowledge
(lACK) transaction (refer to Paragraph 2.12). Following the lACK transaction, the current PC and
PSW are saved on the stack and the new PC and PSW are loaded from the vector address.

1.5.2

Interrupt Posting

With the assertion of the priority in (PI) signal, interrupts are read into the DCTII-AA during any read
transaction and ASPI transaction. Interrupts are read in only at the occurrence of PI.

1.5.3

Interrupt Request (IRQ)

During the assertion of PI the interrupt request is read by the DCTII-AA (refer to Figures 1-5 and 16). Refer to Table I-I for signal names. Interrupt requests are implemented from the following seven
different signals.
LAST
INSTRUCTION

I
I
I

IRQ L

lACK

FIRST INSTRUCTION OF
SERVICE ROUTINE

B
I
I
I

1 . ___. . ;. :__
I
I
I

PI H

SEL<l>H

n-------

--------~

A.
B.

INTERRUPT REQUEST
INTERRUPT REQUEST LATCHED INTO DCTll·AA
MR-4997

Figure 1-5

Interrupt Request

1-5

PRELIMINARY
AI<7:0> ({{{{(({{{{{{{({((INTERRUPTREQUEST )))))
PI

--.l

\_MR·4996

Figure 1-6

Interrupt Timing

Maskable interrupts:
(coded priority)

• -CP<3:0>
Nonmaskable interrupt:
• -PF
• -HALT

(power fail)
(halt)

Control (internal or external) vector:

• -VEC

(vector)
Table 1-1

Interrupt Signals

Interrupt
Signals

Pin
Name

Pin
Number

-CP<3>
-CP<2>
-CP
-CP<O>
-VEC
-PF
-HALT

AI
AI<2>
AI<3>
AI<4>
AI<5>
AI<6>
AI<7>

33
34
35
36
37
38
39

The DCT I J-AA detects an interrupt request if during the assertion of PI at least one of the following
signals is asserted low.
•
•
•
•
•
•

-CP<3>
-CP<2>
-CP
-CP<O>
-PF
-HALT

(AI<1 »
(AI<2> )
(AI<3> )
(AI<4»
(AI<6»
(AI<7»

1.5.4 Vectors
Every interrupt except - HALT is associated with an interrupt vector. An interrupt vector consists of
two words: the next PC and next PSW. The PC is the address of the routine to service an interrupt
device. The PSW has new information to load into the processor status register. After the lACK transaction, the current PC and PSW are saved on the stack and the new PC and PSW are loaded from the
vector address.

1-6

PRELIMINARY
Up to 64 vectors may reside in the first 256 memory locations (3748 is the highest vector location). The
vector address is provided by the interrupting device (external vector address) or by a fixed table stored
in the DCT ll-AA (internal vector address).
NOTE
The power fail (- PF) interrupt uses interrupt vector address 24 and is not acknowledged with an
lACK transaction. (Refer to Paragraph 2.12.) The
- HALT interrupt is not associated with a vector; it
pushes the PC and PSW onto the stack and immediately goes to the restart address with PSW (3408)'
- HALT is not acknowledged.
1.5.4.1 Internal Vector Address - If - VEt (AI <5» is not asserted (high) during the assertion of
PI, the DCTII-AA gets the vector address from an internal fixed table by decoding the inputs
- HALT, - PF, and -CP<3:0>. Refer to Table 1-2.
Table 1-2

-HALT*
-PF

Interrupt Decode

-CP<3>
(AI<I»

-CP<2>
(AI<2»

-CP
(AI<3»

-CP<O>
(AI<4»

Priority
Level

Vector
Address

X
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

X
X
L
L

X
X
L

X
X

8
8

H
L
H

7
7
7
7
6
6
6
6
5
5
5
5
4
4
4

L
H
H
H
H
L
L
L
L
H
H
H
H

H
H
L
L
H
H
L
L
H
H

H
L
H
L
H
L
H

L
H
H

H
L
H

24
140
144
150
154
100
104
110
114
120
124
130
134
60
64
70

No action

*PC is loaded with the restart address; PSW = 340.

1.5.4.2 External Vector Address - If during the assertion of PI (- PF or - HALT not asserted)
- VEC (AI<5» is asserted (low), the DCTII-AA obtains the vector from the external device during
an lACK transaction. Asserting READY causes the DCTII-AA to wait for the vector.
1.5.5 Priority
Each interrupt is assigned a priority level (refer to Table 1-2). The DCTII-AA divides interrupts into
two groups:
•
•

Maskable
Nonmaskable

1.5.5.1 Maskable Interrupts - Interrupts on -CP<3:0> are maskable. The interrupts are serviced
according to their priority level (refer to Table 1-2).

1-7

PRELIMINARY
NOTE
As in any multilevel priority structure, the PSW of
the service routine must contain a priority level as
high or higher than that of the interrupt request.
Otherwise, the interrupt request continues to cause
lACK transactions until the stack is full. (Refer to
Paragraph 2.12.)
1.5.5.2 Nonmaskable Interrupts - The - HALT interrupt has the highest priority; it interrupts the
processor whatever the processor's status.
NOTE
The - HALT interrupt or execution of the - HALT
instruction results in an interrupt, not in a stopping
of the processor.
1.6 DIRECT MEMORY ACCESS (DMA) MECHANISM
During a DMA transaction the only lines that are three-stated are DAL<15:0>. Low current pull-ups
are placed on:
•
•
•

AI<7:0>
Rj-WHB
Rj-WLB

The processor maintains control of - RAS, - CAS, and PI.
A device requests control of the DMA bus (DAL<15:0>, AI<7:0>, Rj-WHB, and Rj-WLB) by
asserting direct memory request [(DMR (AI<O»] during the assertion of PI (refer to Figure 1-7).
DMR is read during any assertion of PI, unlike interrupts that are read only during a read or ASPI
transaction. The processor waits for the end of the current transaction (read, write, DMG, or ASPI)
and then releases the DMA bus. The requesting device is signaled (by the processor) when it asserts the
two signals:
•
•

SEL<O> (high)
SEL< 1> (high)

SEL<O> and SEL< 1> indicate a direct memory grant (DMG).
The requesting device, having received DMG, performs the DMA by controlling the DMA bus. The
processor continues to output PI in order to allow the negation of DMR. The device holds control of the
DMA bus until DMR is negated during PI. Multiple DMA devices can be implemented using a daisychain structure, as shown in Figure 1-8.

1-8

PRELIMINARY

AI<O>

SEL<O>

SEL<1>

DMA BUS

MA·5275

Figure 1-7

DMA Timing

DEVICE 1

DEVICE 2

SEL<1 :0> (DMG)
DCT11-AA

MR-5276

Figure 1-8

DMA, Block Diagram

1-9

PRELIMINARY

CHAPTER 2
BUS TRANSACTIONS

2.1 INTRODUCTION
This chapter provides a basic discussion of each bus transaction. Paragraphs 2.3 through 2.10 pertain to
the read and write transactions. The details of the read and write transactions change considerably in
each of the following modes.
•
•
•
•

8-bit static
8-bit dynamic
16-bit static
16-bit dynamic

Therefore, a separate discussion of each read and write transaction is presented. All other transactions
.
are described as they apply to the DCTl1-AA bus.
2.2 BUS TRANSACTION
Refer to Figure 2-l. Each PDP-II instruction is composed of a number of transactions.

PDP-11 INSTRUCTION
TRANSACTION

TRANSACTION

I
-.~.:.:: .. : ... ::.-..: ..:.:.;'...::.,.:.:
. .. :............ ::.:
....... ..:.
MICRO
CYCLE

MICRO
CYCLE

TRANSACTION
MICRO
CYCLE

MICRO
CYCLE

TRANSACTION
MICRO
CYCLE

~
~'.::

TRANSACTION
MICRO
CYCLE

:-:.:.~.

TRANSACTION

MICRO
CYCLE

01
FETCH

REFRESH
MR-4842

Figure 2-1

Parts of a Transaction

2-1

PRELIMINARY
2.2.1

Transaction

A transaction is defined as an activity that takes place on the DCTII-AA bus in order to perform a
function such as:
•
•
•
•
•
•
•

2.2.2

Read
\\Zrite
Refresh
lACK (interrupt acknowledge)
DMA (direct memory access)
ASPI (assert priority in)
NOP (no operation)

Microcycle

Each transaction is made up of either one or two microcycles. A microcycle is defined as the activity
required for one microinstruction to be executed. The microcycle performs the functions necessary to
transfer information to and from the DCTII-AA bus, move data internally, and calculate values.

2.2.3 Clock Phase
The basic building block of the DCTlI-AA timing is the clock phase. Each microcycle is normally
constructed of three clock phases: ¢ I, ¢ 2, and ¢ W. During an ASPI transaction, lACK transaction,
DMA transaction, or when operating in long microcycle mode, it is necessary to add a fourth phase,
phase D ( ¢ D), between ¢ 2 and ¢ W. All clock phases have the same duration between assertions.

2.3

16-BIT STATIC READ TRANSACTION

A read transaction consists of three distinct processes:
•
•
•

Output of address
Input of data
Input of interrupt and DMA request (refer to Paragraphs 1.5 and 2.14)

Detailed timing of a 16-bit static read transaction is found in Figure A-2 in Appendix A.

NOTE
All references to input or output are to the processor.
2.3.1

Output of Address

Refer to Figures 2-2 and 2-3. The address is output on the data address lines (DALs) 15-0 « 15:0».
The condition of DAL<O> indicates the address of a word, high byte, or low byte. Data address lines
are time multiplexed and are used for both address and data.

Address Control - Refer to Figures 2-2 and 2-3. Address strobe, which is used to latch the address into
the memory system or register, is accomplished by means of row address strobe ( - RAS). The address
is latched upon the assertion (leading edge) of - RAS.
2.3.2

Input of Data

The input data should be valid on DAL< 15:0> during the period that priority in (PI) is asserted (refer
to Figure 2-3).

2-2

PRELIMINARY
MEMORY
SYSTEM

;-1-

DAL<15:0>
-RAS
-CAS

DCTll·AA

DATA
ADDRESS

ADDRESS
STROBE

WRITE
CONTROL

RI -WHB

RI -WLB

i
MR·4844

Figure 2-2

l6-Bit Static Read, Block Diagram

DAL<15:0>

DATA IN

AI<7:0>

INT & DMA
REQUEST

-RAS

-CAS

RI -WHB

RI -WLB

ADDRESS STROBE
MA-4845

Figure 2-3

l6-Bit Static Read Timing

2-3

PRELIMINARY
Data Control - The data strobe, which the processor uses to latch the input data, is accomplished by
means of column address strobe (-CAS). The data is latched upon the negation (trailing edge) of
-CAS. Read/write control is accomplished through the use of two signals:
•
•

Read/ - Write High Byte (R/ - WHB)
Read/ - Write Low Byte (Rj - WLB)

Both these signals remain high during a read transaction.
2.3.3 Instruction Fetch
An instruction fetch is indicated by two signals:
•
•

SEL<O> high
SEL low

Refer to Figure A-2 in Appendix A.
2.4 16-BIT STATIC WRITE TRANSACTION
A write transaction is composed of three distinct processes:
•
•
•

Output of address
Output of data
Input of DMA request (refer to Paragraph 2.14)

Detailed timing of a 16-bit static write transaction is found in Figure A-3 of Appendix A.
NOTE
All references to input or output are to the processor.
A write transaction is always preceded by a read
transaction (the two are indivisible) except when
writing the stack during an interrupt or trap.
2.4.1 Output of Address
Refer to Figures 2-4 and 2-5. The address is output on DAL<15:0>. The condition of DAL<O>
indicates the addressing of a word, high byte, or low byte. Refer to Table 2-1. DAL< 15:0> are time
multiplexed and used for both address and data.
Address Control - Address strobe, which is used to latch the address into the memory system or register, is accomplished by means of - RAS. The address is latched upon the assertion (leading edge) of
-RAS.
2.4.2 Output of Data
Refer to Figure 2-5. The data is output on DAL< 15:0> before the assertion (leading edge) of PI.
Data Control - The signal used to latch the data into the memory system or register and the edge required is found in Table 2-2. Write control is accomplished through the use of two signals:
•
•

R/-WHB
R/-WLB

Table 2-1 indicates the conditions necessary to address and write a memory.

2-4

PRELIMINARY
MEMORY
SYSTEM

/'"f

DAL<15:0>
-RAS
-CAS

DCT11-AA

)

DATA
ADDRESS
ADDRESS
AND
DATA
STROBES
WRITE
CONTROL

R/ -WHB

R/ -WLB

J
MA4846

Figure 2-4

16-Bit Static Write, Block Diagram

DAL<15:0>

DATA

AI<O>

DMA REQUEST

-RAS

-CAS

R/ -WHB
R/ -WLB
NORMAL

R/ -WHB
RI -WLB
DELAYED

'--v------'
ADDRESS STROBE

DATA STROBES
MR-48.7

Figure 2-5

16-Bit Static Write Timing

2-5

PRELIMINARY
Table 2-1

I6-Bit Static Write Conditions

Addressed Memory

Address

Rj-WHB

Rj-WLB

Word
Low byte
High byte

Even (DAL<O> =0)
Even (DAL<O> =0)
Odd (DAL<O> = I)

0
0
1

Table 2-2

I6-Bit Static Write Data Strobes

Signal

Edge

-RAS
-CAS
PI
PI

Negation (trailing)
Negation (trailing)
Assertion (leading)
Negation (trailing)

2.5 16-BIT DYNAMIC READ TRANSACTION
A read transaction consists of three distinct processes:
•
•
•

Output of address
Input of data
Input of interrupt and DMA request (refer to Paragraphs l.5 and 2.14)

Detailed timing of a 16-bit dynamic read transaction is found in Figure A-4 in Appendix A.
NOTE
All references to input or output are to the processor.
2.5.1 Output of Address
Both static and dynamic addresses are output concurrently while in dynamic mode.
2.5.1.1 Dynamic Address - Refer to Figures 2-6 and 2-7. The address is output on the address interrupt (AI) lines 7-0 «7:0». The AI lines output the row address first and the column address second.
Table 2-3 lists the address bits required in 4Kj 16K mode and 64K mode.
NOTE
The AI lines are not in order. Refer to Table 2-4.
2.5.1.2 Static Address - The addressing of a static ROM, RAM, or register in a system supporting
dynamic devices is accomplished by outputs concurrent with the AI<7:0>. The concurrent address is
output on DAL<15:0>.
2.5.1.3 Address Control - Table 2-5 indicates the signals and edges required to latch each portion of
the address into the memory system or register.
2.5.2 Input of Data
Refer to Figure 2-7. The input data should be valid on DAL< 15:0> during the period of time that PI
is asserted. The negation of -CAS strobes the data into the DCTI1-AA.

2-6

PRELIMINARY

MEMORY
SYSTEM

DAL<15:0>

)

DATA
ADDRESS

AI<7:0>

)

ADDRESS

DCT11-AA
-RAS
-CAS
PI

ADDRESS
STROBES
WRITE
CONTROL

R/-WHB

R/-WLB

MR-4848

Figure 2-6

16-Bit Dynamic Read, Block Diagram

2-7

PRELIMINARY

DAL<15:0>

AI<7:0>

-RAS

-CAS

R/ -WHB

R/ -WLB

'----.r----'
ADDRESS STROBES
MR-4849

Figure 2-7

Table 2-3

16-Bit Dynamic Read Timing

16-Bit Dynamic Read Addressing Scheme

Mode

Memory Chip

Address

AI Used

4K/16K
4K/16K
64K

4K X 1
16K Xl
64K X 1

AI-Al2
AI-A14
AI-A15

<6:1>
<7:1>
<7:0>

2-8

PRELIMINARY
Table 2-4

16-Bit Dynamic Read AI Addressing

Address
AI

4K/16K
-RAS

-CAS

64K
-RAS

<0>
<1>
<2>
<3>
<4>
<5>
<6>
<7>

FET
Al
A3
A5
A7
A9
All
A13

AI4
A2
A4
A6
AS
AID
AI2
AI4

AI5
Al
A3
A5
A7
A9
All
AI3

Table 2-5

-CAS
A14
A2
A4
A6

AS
AIO
AI2
AI2

16-Bit Dynamic Read Address Strobes

Address

Signal

Edge

Device

Rj-WHB

Rj-WLB

Row
Column
DAL

-RAS
-CAS
-RAS

Assertion (leading)
Assertion (leading)
Assertion (leading)

Dynamic
Dynamic
Dynamic or static

I
I
I

Data Control - The data strobe, which the processor uses to latch the input data, is accomplished by
means of -CAS. The data is latched upon the negation (trailing edge) of -CAS. Write control is
accomplished through the use of two signals:
•
•

Rj-WHB
Rj-WLB

Both these signals remain high during a read transaction.

2.5.3 Instruction Fetch
An instruction fetch is indicated by different signals, depending on the mode. Refer to Tables A-4, A-7,
and Figure A-4 in Appendix A.
2.5.3.1 4K/16K Mode - In 4Kj16K 16-bit dynamic mode, AI<O> is asserted at the leading edge of
- RAS to indicate a fetch operation. AI <0> is three-stated before the leading edge of PI. Fetch is
indicated by AI <0> high during - RAS.
NOTE
During refresh the AI lines have the refresh counter
address on them.

2.5.3.2 64K Mode - Static modes and 64K use SEL<O> high and SEL< 1> low to indicate a fetch
condition. When SEL<O> signifies a fetch, it is asserted only during the read cycle. Fetch is indicated
by SEL<O> high and SEL< 1> low.

2-9

PRELIMINARY
2.6 16-BIT DYNAMIC WRITE TRANSACTION
A write transaction consists of three distinct processes:
•
•
•

Output of address
Output of data
Input of DMA request (refer to Paragraph 2.14)

Detailed timing of a 16-bit dynamic write transaction is found in Figure A-5 of Appendix A.

NOTE
All references to input or output are to the processor.
A write transaction is always preceded by a read
transaction (the two are indivisible) except when
writing the stack during an interrupt or trap.
2.6.1 Output of Address
Both static and dynamic addresses are output concurrently while in dynamic mode.
2.6.1.1 Dynamic Address - Refer to Figures 2-8 and 2-9. The address is output on AI<7:0>. The AI
lines output the row address first and the column address second. Table 2-6 indicates the address bits
required by memories in 4Kj 16K mode and 64K mode.
NOTE
The AI lines are not in order. Refer to Table 2-7.
2.6.1.2 Static Address - The addressing of a static ROM, RAM, or register in a system supporting
dynamic devices is accomplished by outputs concurrent with the AI <7:0>. The concurrent address is
output on DAL< 15:0>.

MEMORY
SYSTEM

DAL<15:0>

)

DATA
ADDRESS

AI<7:0>

ADDRESS

DCTll-AA
-RAS
-CAS
PI

DATA
AND
ADDRESS
STROBES
WRITE
CONTROL

R/-WHB

R/-WLB

MA·4850

Figure 2-8

16-Bit Dynamic Write, Block Diagram

2-10

PRELIMINARY

DATA OUT

DAL<15:0>

AI<7:0>

-RAS

-CAS

R/-WHB
R/-WLB
NORMAL

R/-WHB
R/-WLB
DELAYED

"--y-----'

'--_----..y,--_--J

ADDRESS
STROBES

DATA STROBES
MR-4851

Figure 2-9

Table 2-6

16-Bit Dynamic Write Timing

16-Bit Dynamic Write Addressing Scheme

Mode

Memory Chip

Address*

AI Used

4Kjl6K
4Kjl6K
64K

4K X I
16K X I
64K X I

AI-A12
AI-AI4
AI-AI5

<6:1>
<7:1>
<7:0>

*Address lines necessary to address all bits in each chip.

2-11

PRELIMINARY
Table 2-7

16-Bit Dynamic Write AI Addressing

Address

4K/16K
-RAS

-CAS

64K
-RAS

-CAS

<0>

<2>
<3>
<4>
<5>
<6>
<7>

FET
Al
A3
A5
A7
A9
All
AI3

AI4
A2
A4
A6
AS
AlO
AI2
AI4

AI5
AI
A3
A5
A7
A9
All
A13

AI4
A2
A4
A6
AS
AIO
AI2
AI2

2.6.1.3 Address Control - Table 2-8 indicates the signals and edges required to latch each portion of
the address into the memory system or register.
2.6.2 Output of Data
Refer to Figure 2-9. The data is output on DAL<15:0>.
Data Control - The signals used to latch the data into the memory system or register and the edges
required are found in Table 2-9. Write control is accomplished through the use of two signals:
•
•

Rj-WHB
Rj-WLB

Table 2-10 indicates the conditions necessary to address and write a memory system or register. The
timing of Rj - WHB and Rj - WLB is found in Table 2-11.

Table 2-8

16-Bit Dynamic Write Address Strobes

Address

Signal

Edge

Device

Row
Column
DAL

-RAS
-CAS
-RAS

Assertion (leading)
Assertion (leading)
Assertion (leading)

Dynamic
Dynamic
Dynamic or static

Table 2-9

16-Bit Dynamic Write Data Strobes

Signal

Edge

-RAS
-CAS
PI
PI

Negation (trailing)
Negation (trailing)
Assertion (leading)
Negation (trailing)

2-12

PRELIMINARY
Table 2-10

16-Bit Dynamic Write Conditions

Addressed Memory

Address

Rj-WHB

Rj-WLB

Word
Low byte
High byte

Even (DAL<O> =0)
Even (DAL<O> =0)
Odd (DAL<O> = I)

0
I
0

Table 2-11

0
I

16-Bit Dynamic Write Control Timing

Signal

Mode

Parameter

Rj-WHB
Rj-WLB
Rj-WHB
Rj-WLB

Normal
Normal
Delayed
Delayed

Write control before -CAS assertion
Write control before -CAS assertion
Write control at or after -CAS assertion
Write control at or after -CAS assertion

2.7 8-BIT STATIC READ TRANSACTION
A read transaction consists of three distinct processes:
•
•
•

Output of address
Input of data
Input of interrupt and DMA request (refer to Paragraphs 1.5 and 2.14)

Detailed timing of an 8-bit static read transaction is found in Figure A-6 of Appendix A.

When a word read or a word write is being executed. the transaction is repeated twice and the two
transactions are indivisible. For example, the MOV (move word) instruction first does a read transaction and addresses the low-byte data. The address is then incremented by one and the second read transaction addresses the high byte data. In the case of the MOVB (move byte) instruction, the transaction
occurs only once.
NOTE
All references to input or output are to the processor.
2.7.1 Output of Address
Refer to Figures 2-10 and 2-11. The high byte address is output on the static address lines (SALs) 15-8
« 15:8». The low byte of the address is output on DAL<7:0>. Data address lines are time multiplexed and used for both address and data.
Address Control - Address strobe, which is used to latch the address into the memory system or register, is accomplished by means of - RAS. The address is latched upon the assertion (leading edge) of
-RAS.
2.7.2 Input of Data
Refer to Figure 2-11. The input data should be valid on DAL<7:0> during the period PI is asserted.
Data Control - The data strobe, which the processor uses to latch the input data, is accomplished by
means of - CAS. The data is latched upon the negation (trailing edge) of - CAS. Read control is accomplished through the use of the signal - Read (Rj - WHB). The timing of - Read is found in Table
2-12.

2-13

PRELIMINARY
MEMORY
SYSTEM

SAL(DAL)<15:8> )

DCT11-AA

DAL<7:0>
-RAS

ADDRESS

DATA
~ ADDRESS

-CAS

ADDRESS
STROBE

WRITE CONTROL
-RD (RI -WHB)

i
MR-4852

Figure 2- \0

2.7.3

8-Bit Static Read, Block Diagram

Instruction Fetch

An instruction fetch is indicated by two signals:

•
•

SEL<O> high
SEL low

Refer to Figure A-6 in Appendix A.

2.8 8-BIT STATIC WRITE TRANSACTION
A write transaction consists of three distinct processes:
•
•
•

Output of address
Output of data
Input of DMA request (refer to Paragraph 2.14)

Detailed timing of an 8-bit static write transaction is found in Figure A-7 in Appendix A.

When a word read or a word write is being executed, the transaction is repeated twice and the two
transactions are indivisible. For example, the MOY (move word) instruction first does a read transaction and addresses the low byte data. The address is then incremented by one and the second read transaction addresses the high byte data. In the case of the MOYB (move byte) instruction, the transaction
occurs only once.

2-14

PRELIMINARY

SAL<15:8>
(DAL)

DAL<7:0>

HI BYTE OF ADDRESS

La BYTE OF
ADDRESS

DATA IN

INT & DMA
REQUEST

AI<7:0>

-RAS

-CAS

-RD (R/ -WHB)
NORMAL

-RD (R/ -WHB)
DELAYED

-WT (R/ -WLB)

ADDRESS STROBE
MR-4853

Figure 2-11

Table 2-12

8-Bit Static Read Timing

8-Bit Static Read Control Timing

Signal

Mode

Parameter

- RD (Rj - WHB)
- RD (Rj - WHB)

Normal
Delayed

Read control before -CAS assertion
Read control at or after - CAS assertion

2-15

PRELIMINARY
2.8.1 Output of Address
Refer to Figures 2-12 and 2-13. The high byte address is output on the static address lines (SALs) 15-8
«15:8». The low byte of the address is output on DAL<7:0>. Data address lines are time multiplexed and used for both address and data.
Address Control - Address strobe, which is used to latch the address into the memory system or register, is accomplished by means of - RAS. The address is latched upon the assertion (leading edge) of
-RAS.
2.8.2 Output of Data
Refer to Figure 2-13. The data is output on DAL<7:0> before the assertion (leading edge) of PI.
Data Control - The signals used to latch the data into the memory system or register and the edges
required are found in Table 2-13. Write control is accomplished through the use of the signal - Write
(Rj - WLB). The timing of - Write is found in Table 2-14.
2.9 8-BIT DYNAMIC READ TRANSACTION
A read transaction consists of three distinct processes:
•
•
•

Output of address
Input of data
Input of interrupt and DMA request (refer to Paragraphs 1.5 and 2.14)

Detailed timing of a 8-bit dynamic read transaction is found in Figure A-8 of Appendix A.

When a word read or a word write is being executed, the transaction is repeated twice and the two
transactions ate indivisible. For example, the MOV (move word) instruction first does a read transaction and addresses the low byte data. The address is then incremented by one and the second read transaction addresses the high byte data. In the case of the MOVB (move byte) instruction, the transaction
occurs only once.
NOTE
All references to input or output are to the processor.

MEMORY
SYSTEM

....
SAL(DAL)<15:8>

)

ADDRESS

If'

DCT11-AA

V
i'r

DAL<7:0>

DATA
"\ ADDRESS

-RAS
-CAS
PI

DATA
AND
ADDRESS
STROBES
WRITE CONTROL

-WT (RI -WLB)

r
MR·4854

Figure 2-12

8-Bit Static Write, Block Diagram

2-16

PRELIMINARY

SAL<15:8>
(DAL)

DAL<7:0>

HI SYTE OF ADDRESS

LO 8YTE OF
ADDRESS

DATA OUT

AI<O>

-RAS

-CAS

-RD (R/ -WHS)

-WT (R/ oWLS)
NORMAL

-WT (R/ oWLS)
DELAYED

'--v----'
ADDRESS STROBE

DATA STROBES
MR~855

Figure 2-13

8-Bit Static Write Timing

2-17

PRELIMINARY
Table 2-13 8-Bit Static Read Data Strobes
Signal

Edge

-RAS
-CAS
PI
PI

Negation (trailing)
Negation (trailing)

Assertion (leading)
Negation (trailing)

Table 2-14 8-Bit Static Write Control Timing
Signal

Mode

Parameter

- WT (Rj - WLB)
- WT (Rj - WLB)

Normal
Delayed

Write control before -CAS assertion
Write control at or after -CAS assertion

2.9.1 Output of Address
Both static and dynamic addresses are output concurrently while in dynamic mode.
2.9.1.1 Dynamic Address - Refer to Figures 2-14 and 2-15. The address is output on AI <7:0>. The
AI lines output the row address first and the column address second. Table 2-15 lists the address bits
required in 4K/ 16K mode and 64K mode.
NOTE
The AI lines are not in order. Refer to Table 2-16.
2.9.1.2 Static Address - Addressing of a static ROM, RAM, or register in a system supporting dynamic devices is accomplished by outputs concurrent with the AI < 7 :0>. The high byte of the address
is output on the static address lines (SALs) 15-8 « 15:8». The low byte of the address is output on
DAL<7~>.
.

SAL(DAl\<15,a>

/'
~

DCT"·AA

DAL<7:0>

AI<7:0>
-RAS

::>
~
::>

-CAS
PI

MEMORY
SYSTEM
ADDRESS

DATA
ADDRESS

ADDRESS

ADDRESS
STROBES

WRITE CONTROL

-RD (RI -WHB)

i
MR-4856

Figure 2-14

8-Bit Dynamic Read, Block Diagram

2-18

PRELIMINARY

SAL<15:B>
(DAL)

DAL<7:0>

HI BYTE OF ADDRESS

LO BYTE OF
ADDRESS

DATA IN

INT& DMA
REQUEST

AI<7:0>

-RAS

-CAS

-RD (R/-WHB)
NORMAL

-RD (R/-WHB)
DELAYED

-WT (R/-WLB)

ADDRESS STROBES
MR-4857

Figure 2-15

8-Bit Dynamic Read Timing

2-19

PRELIMINARY
Table 2-15 8-Bit Dynamic Read Addressing Scheme
Mode

Memory Chip

Address

AI Used

4K/16K
4K/16K
64K

4K X I
16K X I
64K X I

AO--AII
AO--AI3
AO--AI5

<6:1>
<7:1>
<7:0>

Table 2-16 8-Bit Dynamic AI Addressing
Address
AI

4K/16K
-RAS

-CAS

64K
-RAS

-CAS

<0>

<2>
<3>
<4>
<5>
<6>
<7>

FET
Al
A3
A5
A7
A9
All
AI3

AI4
A2
A4
A6
A8
AIO
AO
AI2

AI5
AI
A3
A5
A7
A9
All
AI3

AI4
A2
A4
A6
A8
AIO
AO
AI2

2.9.1.3 Address Control - Table 2-17 indicates the signals and edges required to latch each portion of
the address into the memory system or register.
2.9.2 Input of Data
Refer to Figure 2-15. The input data should be valid on DAL<7:0> during the period PI is asserted .

•

Data Control - The data strobe, which the processor uses to latch the input data, is accomplished by
means of -CAS. The data is latched upon the negation (trailing edge) of -CAS. Read control is accomplished through the use of one signal - Read (Rj - WHB). The timing of - Read is found in Table

2-18.
Table 2-17 8-Bit Dynamic Read Address Strobes
Address

Signal

Edge

Device

Row
Column
SAL
DAL

-RAS
-CAS
-RAS
-RAS

Assertion (leading)
Assertion (leading)
Assertion (leading)
Assertion (leading)

Dynamic
Dynamic
Dynamic or static
Dynamic or static

Table 2-18 8-Bit Dynamic Read Control Timing
Signal

Mode

Parameter

- RD (R/ - WHB)
- RD (R/ - WHB)

Normal
Delayed

Read control before -CAS assertion
Read control at or after -CAS assertion

2-20

PRELIMINARY
2.9.3 Instruction Fetch
An instruction fetch is indicated by different signals, depending on the mode. Refer to Figure A-8 in
Appendix A.

2.9.3.1

4Kj16K Mode - In 4Kjl6K 8-bit dynamic mode, AI<O> is asserted at the leading edge of
- RAS to indicate a fetch operation. AI <0> is three-stated before the leading edge PI. Fetch is indicated by AI <0> high.
NOTE
During refresh the AI lines have the refresh counter
address on them.

2.9.3.2 64K Mode - Static modes and 64K use SEL<O> high and SEL< 1> low to indicate a fetch
condition. When SEL<O> signifies a fetch, it is asserted only during the low-byte read cycle. Fetch is
indicated by SEL<O> high and SEL< 1> low.
2.10 8-BIT DYNAMIC WRITE TRANSACTION
A write transaction consists of three distinct processes:
•
•
•

Output of addresses
Output of data
Input of DMA request (refer to Paragraph 2.14)

Detailed timing of an 8-bit dynamic write transaction is found in Figure A-9 in Appendix A. .

When a word read or a word write is being executed, the transaction is repeated twice and the two
transactions are indivisible. For example, the MOV (move word) instruction first does a read transaction and addresses the low-byte data. The address is then incremented by one and the second read transaction addresses the high-byte data. In the case of the MOVB (move byte) instruction, the transaction
occurs only once.
NOTE
All references to input or output are to the processor.
A write transaction is always preceded by a read
transaction (the two are indivisible) except when
writing the stack during an interrupt or trap.

2.10.1 Output of Address
Both static and dynamic addresses are output concurrently while in dynamic mode.
2.10.1.1 Dynamic Address - Refer to Figures 2-16 and 2-17. The address is output on AI<7:0>. The
AI lines output the row address first and the column address second. Table 2-19 lists the address bits
required in 4Kj16K mode and 64K mode.
NOTE
The AI lines are not in order. Refer to Table 2-20.

2.10.1.2 Static Address - Addressing of a static ROM, RAM, or register in a system which is supporting dynamic devices is accomplished by outputs concurrent with AI<7:0>. The high byte of the address is output on SAL<15:8>. The low byte of the address is output on DAL<7:0>.

2-21

PRELIMINARY

MEMORY
SYSTEM
SAL(DAL)<15:8>. ) ADDRESS

Vt
~

DCT11-AA

DAL<7:0>

)

AI<7:0>

"\ ADDRESS
./

-RAS
-CAS
PI

DATA
ADDRESS

DATA
AND
ADDRESS
STROBES
WRITE CONTROL

-WT (RI -WLB)

i
MR·4858

Figure 2-16

8-Bit Dynamic Write, Block Diagram

2-22

PRELIMINARY

SAL<15:8>
(DAL)

HI BYTE OF ADDRESS

DATA OUT

DAL<7:0>

AI<7:0>

-RAS

-CAS

-RD (R/ -WHB)

-WT (R/ -WLB)
DELAYED

-WT (R/ -WLB)
NORMAL

'----y---J

ADDRESS STROBES

DATA STROBES
MR-4859

Figure 2-17

8-Bit Dynamic Write Timing

2-23

PRELIMINARY
Table 2-19 8-Bit Dynamic Write Addressing Scheme
Mode

Memory Chip

Address

AI Used

4Kj16K
4Kjl6K
64K

4K X 1
16K X I
64K X 1

AO-AII
AO-AI3
AO-AlS

<6:1>
<7:1>
<7:0>

Table 2-20 8-Bit Dynamic Write AI Addressing
Address
4Kj16K

-RAS

-CAS

<0>

<2>
<3>
<4>
<5>
<6>
<7>

FET
Al
A3
AS
A7
A9
All
A13

A14
A2
A4
A6
A8
AIO

AD
AI2

64K
-RAS

-CAS

AIS
Al
A3
AS
A7
A9
All
AI3

Al4
A2
A4
A6
A8
AIO
AO
Al2

2.10.1.3 Address Control - Table 2-21 indicates the signals and edges required to latch each portion of
the address into the memory system or register.
2.10.2 Output of Data
Refer to Figure 2-17. The data is output on DAL<7:0>.
Data Control - The signals used to latch the data into a memory system or register and the edge required are found in Table 2-22. Write control is accomplished through the use of one signal, -Write
(Rj - WLB). The timing of - Write is found in Table 2-23.
Table 2-21

8-Bit Dynamic Write Address Strobes

Address

Signal

Edge

Device

Row
Column
SAL
DAL

-RAS
-CAS
-RAS
-RAS

Assertion (leading)
Assertion (leading)
Assertion (leading)
Assertion (leading)

Dynamic
Dynamic
Dynamic or static
Dynamic or static

Table 2-22 8-Bit Dynamic Write Data Strobes
Signal

Edge

-RAS
-CAS

Negation (trailing)
Negation (trailing)
Assertion (leading)
Negation (trailing)

PI
PI

2-24

PRELIMINARY
Table 2-23 8-Bit Dynamic Write Control Timing
Signal

Mode

Parameter

- WT (R/ - WLB)
- WT (R/ - WLB)

Normal
Delayed

Write control before -CAS assertion
Write control at or after -CAS assertion

2.11 REFRESH TRANSACTION
A refresh transaction consists of three distinct processes:
•
•
•

Output of refresh address
Address control
Output of SEL<O> and SEL< 1> (in 4Kj 16K mode only)

Detailed timing of a refresh transaction is found in Figure A-I0 in Appendix A.
NOTE
All references to input or output are to the processor.
2.11.1 Output of Refresh Address
Refer to Figures 2-18 and 2-19. The refresh address is output on AI <7:0>. Refresh occurs at different
times:
•

After an instruction fetch:
8-bit mode - every instruction
16-bit mode - after every other instruction

•

After addressing modes 5, 6, and 7:
Index
Index-deferred
Au todecrement-deferred

•

During the following instructions:
HALT
TRAP
BPT
lOT

•

During all interrupts and traps.

2.11.2 Address Control
Address strobe, which is used to latch the address' into the memory, is accomplished by means of
- RAS. The address is latched upon the assertion (leading edge) of - RAS.

2-25

PRELIMINARY

AI<7:0>
-RAS

DYNAMIC
MEMORY
SYSTEM

DCT11-AA

MR-4864

Figure 2-18

DAL <15:0>

Refresh Transaction, Block Diagram

««<<<<<<<<<<»»>»»)))))))))))))

AI<7:0>

REFRESH ADDRESS

-RAS

-CAS

SEL<O>
4K/16K
MODE

j
------

SEL <1>

MA-4865

Figure 2-19

Refresh Transaction Timing

2-26

PRELIMINARY
2.11.3 Output of SEL<O> and SEL<l>
Refer to Figure 2-19. If mode register bit 10 is not set (MR<10>
refresh transaction:
•
•

1, 4Kj16K mode) during the

SEL<O> high
SEL low

If MR<IO> is set (MR<10> = 0, 64K mode) during the refresh transaction:
•
•

SEL<O> low
SEL low

SEL are low for other transactions (refer to Table A-lOin Appendix A).
2.12 lACK (INTERRUPT ACKNOWLEDGE) TRANSACTION
An lACK transaction, which clears the interrupt request, consists of two distinct processes:
•
•

Output of interrupt acknowledge data
Input of vector address [if - VEC (AI <5» was asserted]

Detailed timing of an lACK transaction is found in Figure A-II in Appendix A.
NOTE
All references to input or output are to the processor.

2.12.1 Output of Interrupt Acknowledge Data
Refer to Figures 2-20 and 2-21. The processor first outputs the interrupt acknowledge data on
DAL< 12:8> with the same polarity as the received data. The acknowledge data consists of the coded
priority of the interrupting device. This coded priority was first received on Al<5:1> at the time of
the interrupt request. Refer to Table 2-24. The strobe, which is provided for the interrupting device to
use, is - RAS. The interrupt acknowledge is valid upon the assertion (leading edge) of - RAS.

DAL<12:8>

DCT11·AA

DAL<7:1>
DEVICE
SEL 0
SEL 1
-RAS

MA-4860

Figure 2-20

lACK Transaction, Block Diagram

2-27

PRELIMINARY

DAL<12:8>

INTERRUPT ACKNOWLEDGE DATA

DAL<7:1>

VECTOR DATA

-RAS

-CAS

SEL<O>

SEL <1>

MA-4861

lACK Transaction Timing

Table 2-24

Interrupt Acknowledge Data

Interrupt Request

Acknowledge

-CP<3>
-CP<2>
-CP
-CP<O>

DAL<8>
DAL<9>
DAL<10>
DAL<II>
DAL<12>

-VEC

2.12.2

Figure 2-21

AI
AI<2>
AI<3>
AI<4>
AI<5>

Input of Vector Address

If vector ( - VEC) AI < 5 > was asserted at the time of the interrupt request, the input of an external
vector address should be driven by the user on DAL<7:2>. If - VEC was not asserted at the time of
the interrupt request, 1 of the 15 vector addresses internal to the processor is used.
Refer to Figure 2-21. Select (SEL) output flag 1 « 1» is used by the processor to input the vector.
The vector address is latched upon the negation (trailing edge) of SEL < 1>. If the READY input is
asserted, the latching of the vector address into the DCTI1-AA is delayed by one microcycle. (Depending on the pulsing of READY, more microcycles may be added.)

2-28

PRELIMINARY
2.13 BUSNOP (NO OPERATION) TRANSACTION
A busnop transaction is a specific processor state in which no processes occur at the outputs. The following is a list of the states found at the outputs.
•
•
•
•
•
•
•
•
•

DAL<15:0>
AI<7:0>
-RAS
-CAS
PI
Rj-WHB
Rj-WLB
SEL<O>
SEL

Previously latched data
Three-state (static mode) invalid output (dynamic mode)
High
High
Low
High
High
Low
Low

A busnop transaction occurs, for example, during an instruction decode cycle and internal processor
computations. Detailed timing of a busnop transaction is found in Figure A-12 in Appendix A.

2.14 DMA (DIRECT MEMORY ACCESS) TRANSACTION
A DMA transaction consists of three processes:
•
•
•

Three-state of DAL< 15:0> and internal pull-ups on AI<7:0>, Rj - WHB, Rj - WLB
Output of -RAS, -CAS, and PI
Output of DMG

Detailed timing of a DMA transaction is found in Figure A-13 in Appendix A.

NOTE
All references to input or output are to the processor.

Upon receiving a DMA request on AI<O>, the processor (at the end of the current transaction) initiates a DMA transaction. The DCTII-AA provides - RAS, -CAS, PI, and COUT signals. The external circuitry is responsible for controlling the Rj - WHB and Rj - WLB lines, providing the address, and providing or accepting data.
During DMA transfers, system circuity goes through the following sequence.
1.

A DMA request (DMR) to the DCTII-AA is made by driving AI<O> low during PI.

The request is latched into the DCTII-AA during PI and shortly thereafter a DMA grant is
issued.

The processor relinquishes control of the bus to the device requesting the DMA.

If the bus is required for a longer period of time, the requesting device must insure that AI <0> is low
at the negation (trailing edge) of each PI.

2.14.1 Three-State of DAL<15:0>
Refer to Figure 2-22. The processor three-states DAL< 15:0>. This is required to free the bus for the
requesting device. AI <7:0>, Rj - WHB, and Rj - WLB have internal pull-ups.

2-29

PRELIMINARY

....- - - - - - - - SINGLE DMA TRANSACTION - - - - - - - -......

COUP

DAL<15:0>

J~-----

AI<O>

-RAS

-CAS

RI -WHB
RI -WLB

J~-----

DMG
(SEL<O»

DMG
(SEL<l»
'PULSE MODE CLOCK (MODE REGISTER<O> = 1).
MA-4867

Figure 2-22

DMA Timing

2-30

PRELIMINARY
2.14.2 Output of -RAS, -CAS, and PI
The -RAS and -CAS signals are generated during the DMA transaction for use by the dynamic
memory system as timing strobes. Refer to Figure 2-22. The output of PI is continued for the purpose of
strobing the input of another DMA request on AI <0>. The DMA request is latched into the processor
upon the negation (trailing edge) of PI.
2.14.3 Output of Direct Memory Grant (DMG)
Refer to Figure 2-22. When the grant is issued the DCTII-AA takes the following actions.
•

SEL<O> and SEL< 1> are asserted (high), informing the system that the grant has been
issued and both signals are valid at the assertion (leading edge) of - RAS.

•

-RAS, -CAS, PI, and COUT are driven with the timings specified in the DMA transaction timing diagram (refer to Figure A-14 in Appendix A).

•

The DALs are three-stated.

•

AI <7:0>, Rj - WHB, and Rj - WLB are implemented by internal pull-ups.

When the grant is issued, external circuitry must drive the Rj - WHB and Rj - WLB lines and initially
drive the DALs with the address. In dynamic memory systems the address must be multiplexed on
AI <7:0> so that the memory chips are provided with row and column addresses at the appropriate
times. Later in the transaction the data transfer on the DALs takes place in a direction controlled by
the state of the Rj - WHB and Rj - WLB lines.

2.14.4 READY Input
If the READY input is activated (refer to Paragraph 3.4.6), the DMA transaction is extended by one
microcycle. (Depending on the pulsing of READY, more microcycles may be added.)
2.15 ASPI (ASSERT PRIORITY IN) TRANSACTION
An ASPI transaction consists of two processes:
•
•

Input of interrupt and DMA request
-CAS without -RAS

Detailed timing of an ASPI transaction is found in Figure A-14 in Appendix A.

NOTE
All references to input or output are to the processor.
Refer to Figures 2-23 and 2-24. The processor reads AI<7:0>. If any line is asserted, the processor
acts on the interrupt (depending on the priority); if not, no action takes place. For information concerning the interrupt structure, refer to Paragraph l.5. The ASPI transaction generates a -CAS without generating a - RAS. ASPI transactions occur only during a reset instruction, halt instructionjinterrupt, wait instruction, or during the power-u'p sequence.

Input Control
The interrupt strobe, which the processor uses to latch the interrupt and DMA request data, is accomplished by means of PI. The interrupt is latched by the processor upon the negation (trailing edge) of
PI.

2-31

PRELIMINARY

DCT11-AA

/''\r

DAL<15:0>

(....

AI<7:0>

)

DEVICE

-RAS
-CAS
PI

MR-4862

Figure 2-23

ASP! Transaction, Block Diagram

INT& DMA
REQUEST

AI<7:0>

-RAS

-CAS

PI
MA-4863

Figure 2-24

ASP! Transaction Timing

2-32

PRELIMINARY

CHAPTER 3
PIN DESCRIPTIONS

3.1 INTRODUCTION
This chapter describes the functions performed by each DCTII-AA pin. The pins, and thus, the chapter, are divided into five groups:
•
•
•
•
•

Datajaddress lines (DAL<15:0»
Addressjinterrupt (AI <7:0»
Control lines (SEL<I:0>, Rj-WHB, Rj-WLB, -RAS, -CAS, PI, Ready)
Miscellaneous signals ( - BCLR, PUP, COUT, XTLl, XtLO)
Power pim. (BGND, GND, Vce)

Refer to Figure 3-1 and Tables 3-1 through 3-5. Several DCTII-AA pins perform different functions
depending on the mode. Therefore, signal names vary from pin names. The mode-dependent pins are
•
•
•
•
•
•

DAL<15:0>
AI<7:0>
Select (SEL )
Readj - Write High Byte (Rj - WHB)
Readj - Write Low Byte (Rj - WLB)
Clock Output (COUT)

Each pin function is described under the pin name. If the pin is mode-dependent, a description of each
mode is found under the pin name.
Table 3-1

Mapping of AI onto DAL during an lACK Transaction*
lACK Transaction

Interrupt Request Time
-CP<3>
-CP<2>
-CP
-CP<O>
-VEC

DAL<8>
DAL<9>
DAL<IO>
DAL<II>
DAL<12>

AI
AI<2>
AI<3>
AI<4>
AI<5>
AI <0> (not mapped)
AI <6> (not mapped)
AI<7> (not mapped)

DAL<7:0> ("don't care")
DAL<15:13> ("don't care")
*The logic level is maintained in the AI-to-DAL mapping. For example, if
AI is high at interrupt request time, DAL<8> is high at lACK time.

3-1

PRELIMINARY

DATA/ADDRESS LINES

DAL15

VCC

+5V

DAL14

AI7

-HLT

DAL13

AI6

-PF

DAL12

AI5

-VEC

DALll

AI4

-CPO

DAL10

AI3

-CPl

DAL9

AI2

-CP2

BGND

All

-CP3

INPUT ONLY

DALB

AIO

-DMR

ADDRESS/INTERRUPT

DAL7

PRIORITY IN STROBE

DAL6

-CAS

COLUMN ADDRESS STROBE

DAL5

-RAS

ROW ADDRESS STROBE

DAL4

R/-WL8

DAL3

R/-WHB

DAL2

READY

READIWRITE LOW BYTE (16)
WRITE (8)
READ/WRITE HIGH BYTE (16)
READ (B)
EXTEND TRANSACTION

DALl

SELO

DATA/ADDRESS LINES

DALO

SELl

BUS CLEAR

-BCLR

XTLO

CRYSTAL

POWER-UP

PUP

XTLl

CRYSTAL /EXT OSC

1ST GROUND

GND

COUT

CLOCK OUTPUT

2ND GROUND

DCT11-AA

}

ADDRESS/INTERRUPT
DYNAMIC MODE
OUTPUT
ROW ADDRESS
COLUMN ADDRESS
INPUT
INTERRUPT & DMR
DURING PI TIME
STATIC MODE

SELECT OUTPUT FLAGS
SEE BELOW

SELECT OUTPUT FLAGS
SEL<l>
L
L
H
H

SEL<O>
L
H
L
H

FUNCTION
READIWRITE
REFRESH/FETCH
lACK
DMG
MlA·5211

Figure 3-1

DCTlI-AA Pin Layout

3-2

PRELIMINARY

Table 3-2 Signal and Pin Utilization, 16-Bit Mode

Pin(s)

Signal Names
Pin Name

4Kj16K Dynamic

64K Dynamic

DAL<IS:8>
DAL<7:0>

-RAS

-CAS PI

-RAS

-CAS

-DMR
-CP<3>
-CP<2>
-CP
-CP<O>
-VEC
-PF
-HALT

FET*
Al
A3
AS
A7
A9
All
AI3

AI4
A2
A4
A6
A8
AIO
AI2
AI4

AIS
Al
A3
AS
A7
A9
All
AI3

AI4
A2

-DMR
-CP<3>
-CP<2>
-CP
-CP<O>
-VEC
-PF
-HALT

lACK + DMG
FET + DMG
READY
Rj-WHB
Rj-WLB
-RAS
-CAS
PI

lACK + DMG
REF + DMG
READY
Rj-WHB
Rj-WLB
-RAS
-CAS
PI

lACK + DMG
FET + DMG
READY
Rj-WHB
Rj-WLB
-RAS
-CAS
PI

-BCLR
PUP
COUT
XTLI
XTLO

BGND
GND
VCC

Static

Data Address Lines
1-7,9
10-17

DAL<IS:8> DAL<IS:8>
DAL<7:0> DAL<7:0>

Address Interrupt Lines

32
33
34
3S
36
37
38
39

AI<O>
AI
AI<2>
AI<3>
AI<4>
AI<S>
AI<6>
AI<7>

-DMR
-CP<3>
-CP<2>
-CP
-CP<O>
-VEC
-PF
-HALT

A6
A8
AIO
AI2
AI4

Control Signals
24
2S
26
27
28
29
30
31

SELlt
SELot
READY
Rj-WHB
Rj-WLB
-RAS
-CAS
PI

Miscellaneous Signals
18
19
21
22
23

-BCLR
PUP
COUT
XTLI
XTLO

Power Pins
8
20
40

BGND
GND
VCC

NOTES
* During - RAS, AI <0> is used to indicate a fetch operation in progress. During refresh, AI <0> is the output of the refresh counter at - RAS time.
tSEL and SEL<O> are encoded; refer to Tables 3-4 and 3-S.

3-3

PRELIMINARY
Table 3-3 Signal and Pin Utilization, 8-Bit Mode
Signal Names
Pin(s)

Pin Name

4Kj16K Dynamic

64K Dynamic

SAL<15:8>
DAL<7:0>

-RAS

-CAS PI

-RAS

-CAS

-DMR
-CP<3>
-CP<2>
-CP
-CP<O>
-VEC
-PF
-HALT

FET*
Al
A3
A5
A7
A9
All
AI3

AI4
A2
A4

AI5
Al
A3
A5
A7
A9
All
AI3

AI4
A2

-DMR
-CP<3>
-CP<2>
-CP
-CP<O>
-VEC
-PF
-HALT

lACK + DMG
FET + DMG
READY
-RD
-WT
-RAS
-CAS
PI

lACK + DMG
REF + DMG
READY
-RD
-WT
-RAS
-CAS
PI

lACK + DMG
FET + DMG
READY
-RD
-WT
-RAS
-CAS
PI

-BCLR
PUP
COUT
XTLI
XTLO

-BeLR
PUP
eOUT
XTLI
XTLO

BGND
GND
Vce

BGND
GND
Vee

Static

Data Address Lines
1-7,9
10--17

DAL<15:8> SAL<15:8>
DAL<7:0> DAJ-,<7:0>

Address Interrupt Lines

32
33
34
35
36
37
38
39

AI<O>
AI
AI<2>
AI<3>
AI<4>
AI<5>
AI<6>
AI<7>

A8
AIO
AO
AI2

-DMR
-CP<3>
-CP<2>
-CP
-CP<O>
-VEC
-PF
-HALT

A6
A8
AIO
AO
AI2

Control Signals
24
25
26
27
28
29
30
31

SELlt
SELOt
READY
Rj-WHB
Rj-WLB
-RAS
-CAS
PI

Miscellaneous Signals
18
19
21
22
23

-BCLR
PUP
eOUT
XTLI
XTLO

Power Pins
8
20
40

BGND
GND
Vec

NOTES
* During - RAS, AI <0> is used to indicate a fetch operation in progress. During refresh, AI <0> is the output of the refresh counter at - RAS time.
tSEL and SEL<O> are encoded; refer to Tables 3-4 and 3-5.

3.2

DATA ADDRESS LINES (DAL< 15:0»

DAL< 15:0> functions depend upon the selection of 8-bit or 16-bit mode. During read/write transactions (refer to Paragraph 2.2.1) the DALs are time multiplexed in two ways. In 16-bit mode, they multiplex the address, then the data. In 8-bit mode, in addition to the address/data multiplexing, there is low
byte/high byte multiplexing.

3-4

PRELIMINARY
Table 3-4

SEL<1:0> Functions in Static Mode or Dynamic 64K Mode

SEL<l>

SEL<O>

Function

L
L
H
H

L
H
L
H

Read, write, ASPI, or busnop
Fetch (PDP-II instruction fetch)
lACK (interrupt acknowledge)
DMG (direct memory grant)

Table 3-5 SEL<1:0> Functions in Dynamic 4Kj16K Mode
SEL<l>

SEL<O>

Function

L
L
H
H

L
H
L
H

Read, write, ASPI, or busnop
Refresh
lACK (interrupt acknowledge)
DMG (direct memory grant)

3.2.1 16-Bit Mode - DAL<15:0>
DAL< 15:0> are used in six cases.
1.

During a read/write transaction:
DAL< 15:0> are time multiplexed and used for the address and the data. Read/write transactions are defined in Paragraphs 2.3 through 2.10.

During an lACK transaction:
The information present on AI<5:1> at the time of the interrupt request is output on
DAL<12:8>. Refer to Table 3-1. Paragraph 2.12 defines the lACK (interrupt acknowledge) transaction.

During a DMA transaction:
DAL< 15:0> are three-stated. The DMA (direct memory access) transaction is defined in
Paragraph 2.14.

During a busnop and refresh transaction:
DAL< 15:0> contain previously latched data.

During an ASPI transaction:
DAL< 15:0> are three-stated.

During the power-up sequence or a reset instruction:
The mode register bits are read in from DAL< 15:8, 1:0>. Low-current internal pull-ups are
enabled on these lines when - BCLR is asserted. This avoids the need to drive the bits that
are to be high.

3-5

PRELIMINARY
3.2.2 8-Bit Mode - DAL<15:8>
The signal name for DAL<15:8> in 8-bit mode is static address lines (SAL<15:8», which are used
in six cases.
I.

During a read/write transaction:
SAL< 15:8> contains the high byte of the address throughout the transaction. In 8-bit mode
two transactions (one data byte per transaction) are required for a word read or write.
Read/write transactions are defined in Paragraphs 2.3 through 2.10.

During an lACK transaction:
The information present on AI <5: 1> at the time of the interrupt request is output on
DAL<12:8>. Refer to Table 3-1. Paragraph 2.12 defines the lACK (interrupt acknowledge) transaction.

During a DMA transaction:
DAL< 15:8> are three-stated. The DMA (direct memory access) transaction is defined in
Paragraph 2.14.
.

During a busnop and refresh transaction:
DAL< 15:0> contain previously latched data.

During an ASPI transaction:
DAL< 15:0> are three-stated.

During the power-up sequence or a reset instruction:
The mode register bits are read in from DAL<15:8>. Low-current internal pull-ups are enabled on these lines when - BCLR is asserted. This avoids the need to drive the bits that are
to be high.

3.2.3 8-Bit Mode - DAL<7:0>
DAL<7:0> are used in six cases.
1.

During a read/write transaction:
DAL<7:0> are time multiplexed and used for the low byte of address and data. In 8-bit
mode the data is either the low byte or the high byte. Refer to Figure 3-1. Read/write transactions are defined in Paragraphs 2.3 through 2.10.

During an lACK transaction:
DAL<7:2> are used for the input of an external vector address (if - VEC was asserted
during the interrupt request). DAL<I:0> are irrelevant because the DCTII-AA replaces
them with a 0 after reading them in. This is due to the fact that vectors use two words: PC
and PSW. Paragraph 2.12 defines the lACK (interrupt acknowledge) transaction.

3-6

PRELIMINARY
3.

During a DMA transaction:
DAL<7:0> are three-stated. The DMA (direct memory access) transaction is defined in
Paragraph 2.14.

During a busnop and refresh transaction:
DAL< 15:0> contain previously latched data.

During an ASPI transaction:
DAL< 15:0> are three-stated.

During the power-up sequence or a reset instruction:
The mode register bits are read in from DAL< 1:0>. Low-current internal pull-ups are enabled on these lines when - BCLR is asserted. This avoids the need to drive the bits that are
to be high.

3.3 ADDRESS INTERRUPT (AI <7:0> )
During read, write, refresh, DMA, and ASPI transactions the AI lines (AI <7:0» perform various
functions. The function of AI <7:0> depends upon the selection of one of the following modes: static,
dynamic 4K/16K, or dynamic 64K. Three functions are time multiplexed on AI<7:0>:
•
•
•

Output of row address
Output of column address
Input of interrupts and/or DMA requests

During busnop and lACK transactions, AI <7:0> act as inputs in static modes and contain previously
latched data in dynamic modes. The AI lines are described in three parts:
•
•
•

At - RAS and -CAS time (static mode)
At -RAS and -CAS time (dynamic mode)
At PI time (static or dynamic mode)

3.3.1 AI<7:0> at -RAS and -CAS Time (Static Mode)
While in static mode the address interrupt lines are used as inputs for interrupts and/or DMA requests
during all transactions. AI <7:0> are implemented by internal active low-current pull-ups.
3.3.2 AI<7:0> at -RAS and -CAS Time (Dynamic Mode)
During read/write transactions the address interrupt lines are used as outputs at - RAS and - CAS
time only. The AIs are time multiplexed in two ways:
•

Prior to the assertion (leading edge) of row address strobe (- RAS), the Al lines output the
row address for a dynamic RAM. At the occurrence of - RAS, the data on the AI lines is
valid.

•

Prior to the assertion (leading edge) of column address strobe ( - CAS), the AI lines output
the column address for a dynamic RAM. At the occurrence of - CAS, the data on the AI
lines is valid.

3-7

PRELIMINARY
During refresh transactions· AI <7:0> are used to output the row address at - RAS time. During
DMA and ASPI transactions AI <7:0> have internal low-current pull-ups and are used as inputs.

NOTE
The dynamic address on AI<7:0> available at
- RAS and - CAS time is duplicated on
DAL<15:0> at -RAS time.
3.3.3 AI<7:0> at Priority In (PI) Time (Dynamic and Static Modes)
During read/write, DMA, and ASPI transactions at PI time, AI <7:0> are used as inputs. These lines
are implemented by internal low-current pull-ups. The AI lines input interrupt and DMA requests at
the negation (trailing. edge) of PI. Refer to Table 3-6.

NOTE
The DCTll-AA does not react to interrupt requests
posted during write and DMA transactions.
Table 3-6 AI Functions
@ -RAS (L.E.)

@ -CAS (L.E.)

Transaction

Output

@PI (T.E.)
Input

Read (static)

Interrupt/DMR

Write (static)

DMR

Read (dynamic)

Row address

Column address

Interrupt/DMR

Write (dynamic)

Row address

Column address

DMR

Refresh

Row address

N/A

DMA

DMR

ASPI

N/A

Interrupt/DMR

* - Internal low-current passive pull-ups.
N/ A - Not applicable.
Interrupt and DMA requests are implemented by the following signals.
-DMR

(Direct Memory Request) AI<O>. When the processor reads a DMA request asserted, it (upon termination of almost any current bus transaction) frees the bus for the
DMA device. Refer to Paragraph 2.14 for the definition of a DMA transaction.

-CP<3:0>

(Coded Priority) AI<I:4>. Logic internal to the processor decodes these inputs as an
interrupt request on one of four maskable levels. Refer to Paragraph 1.5 for the definition of the DCTII-AA interrupt structure.

- VEC

(Vector) AI<5>. The signal has meaning only if one or more of -CP<3:0> are
asserted. - VEe signals the processor to ignore the internal vector address indicated
by -CP<3:0> and instead uses the vector address to be provided by the user. The
priority of the -CP lines is not ignored. The user-provided vector address is read during the lACK transaction.

3-8

PRELIMINARY
-PF

(Power Fail) AI<6>. -PF has the highest priority on level seven. If -PF and a level
seven request from CP<3:0> are both present at PI time, the DCTlI-AA services the
- PF first by stacking the PC and PS and jumping to vector address 24. The input
circuit requires no data setup time. Internal logic samples the - PF and then pauses
for up to one instruction before recognizing a request. The - PF input is pseudo-edge
sensitive. It must be read as a negation before another assertion is recognized.

-HALT

(Halt) AI<7>. -HALT is an unmaskable interrupt. It always causes a jump, after
stacking the PS and PC, to the restart address with PS = 3408. The - HALT input is
pseudo-edge sensitive. It must be read as a negation before another assertion is recognized.

3.4 CONTROL LINES
The control lines are composed of signals the DCTII-AA uses to control the normal operation of the
system. The lines are

•
•
•
•
•
•
•
•

-RAS
-CAS
PI
Rj-WHB
Rj-WLB
SEL<l>
SEL<O>
READY

Table 3-7 indicates the transactions in which each of these signals is used. During all transactions not
mentioned in the following description, the control lines remain in their unasserted state (except
READY, which is an input).
Table 3-7 Control Signal Usage
Transaction

-RAS

-CAS

R/-WHB

R/-WLB

Read/write

Refresh

lACK

DMG

ASPI

SEL<O>

SEL<l>

READY

*
2

X - Asserted.
* - Causes one or more microcycle slips.
I - Asserted in static mode and dynamic 64K mode when read as a PDP-II instruction fetch; in 8-bit mode, asserted only in
the low-byte transaction of a fetch.
2 - Asserted in dynamic 4K/I6K mode.
3 - Three-stated.

The - RAS, - CAS, and PI signals are control strobes and act on a iogic transition. Rj - WHB,
Rj - WLB, SEL< 1>, SEL<O>, and READY are static control lines and act on a logic level. Figure
3-2 shows the leading and trailing edges. The leading edge is the edge that changes the signal from the
unasserted state to the asserted state.

3-9

PRELIMINARY
-RAS
-CAS

LEADING EDGE

~~-

-JP

______
ASSERTED
ASSERTED

LEADING EDGE

TRAILING EDGE

MA·5274

Figure 3-2

Leading and Trailing Edge

3.4.1 -RAS (Row Address Strobe)
The - RAS signal is the system address strobe. Table 3-7 indicates the transactions in which - RAS is
asserted. During read/write transactions the assertion (leading edge) of -RAS is used to strobe the
address present on the DALs (for memories not using the - RAS / - CAS multiplexing) and the row
address present on the AIs (for the dynamic memories that use it). During a write transaction the negation (trailing edge) of - RAS may be used as the data output strobe.
During a refresh transaction (dynamic mode only) the assertion (leading edge) of -RAS is used to
strobe the row address present on the AI lines.
During an lACK transaction the assertion (leading edge) of - RAS strobes the lACK information,
which is present on DAL< 12:8>, to the system. The negation (trailing edge) of - RAS strobes the
vector address (user-supplied) into the DCTII-AA.
During a DMA transaction - RAS provides the DMA device with the same function and timing as
used in read/write transactions.

3.4.2 -CAS (Column Address Strobe)
The -CAS signal is an address and chip select strobe. Table 3-7 indicates the transactions in which
-CAS is asserted. During read/write transactions -CAS provides various functions:
•

The assertion (leading edge) of - CAS provides an early warning of the impending occurrence of PI, and therefore, may be used to latch interrupt and DMA requests before they are
strobed onto the AI lines.

•

In dynamic read/write transactions the assertion (leading edge) of -CAS strobes the column address present on the AI lines.

•

In read transactions the negation (trailing edge) of -CAS is used to strobe the data (usersupplied) from the DALs into the DCTII-AA.

•

In write transactions the negation (trailing edge) of -CAS may be used as the data output
strobe.

During a DMA transaction the assertion (leading edge) of -CAS provides the DMA device with the
same function and timing used in read/write transactions.
During ASPI transactions the assertion (leading edge) of -CAS may be used to latch interrupt and
DMA requests before they are strobed onto the AI lines.

3-10

PRELIMINARY
3.4.3 PI (Priority In)
PI is the system interrupt request strobe. PI is used in read, write, DMA, and ASPI transactions. Refer
to Tables 3-6 and 3-7. The function and timing of PI are the same in all four transactions.
Whenever PI is asserted the AI lines are used as inputs. These lines are implemented by internal lowcurrent pull-ups. Therefore, the assertion (leading edge) of PI can be used to strobe the signals
- HAL T, PF, - VEC, -CP<3:0>, and DMR onto the AI lines. (Refer to Paragraph 3.3.)
During write transactions both the assertion (leading edge) and the negation (trailing edge) of PI can be
used as data output strobes.
During write transactions PI can be used to gate the write enable signals (R/ - WHB and R/ - WLB)
for memories and peripherals requiring write enable after the assertion of -CAS.
3.4.4 Rj - WHB and Rj - WLB
The signal names for pin 27 (Rj - WHB) and pin 28 (R/ - WLB) change according to the selection of
8-bit or 16-bit data bus mode.
3.4.4.1 Rj - WHB and Rj - WLB (l6-Bit Mode) - The write enable signals Read/ - Write High
Byte (R/ - WHB) and Read/ - Write Low Byte (Rj- WLB) are used exclusively in read/write transactions. R/ - WHB and R/ - WLB are asserted (low) when the transaction is a write to a high byte or a
low byte.

Normal or delayed mode affects the timing of R/ - WHB and R/ - WLB. In normal mode the
read/write timing is compatible with that of the Motorola 6800 bus peripherals. In delayed mode the
timing is compatible with that of the Intel™ 8080 bus peripherals. During a DMA transaction both pins
are internal low-current pull-ups.
3.4.4.2 R/ - WHB (- RD) and R/ - WLB (- WT) (8-Bit Mode) - The mutually exclusive signals
- RD (read enable) and - WT (write enable) are used only in read/write transactions. The - RD signal is asserted low during a read transaction and - WT is asserted low during a write transaction.

----

Normal or delayed mode affects the timing of - RD and - WT. In normal mode the read/write timing
is compatible with that of the Motorola 6800 bus peripherals. In delayed mode the timing is compatible
with that of the Intel 8080 bus peripherals. During a DMA transaction both pins are internal low-current pull-ups.
3.4.5 SEL< 1 > and SEL<O>
Select I (SEL< I» and Select 0 (SEL<O» are encoded lines and indicate which transaction is
being performed. Refer to Tables 3-4 and 3-5.
3.4.6 READY
Through the use of the READY signal, I/0 devices or memory of any speed may be synchronized with
the DCTII-AA. The READY signal is not generated by the DCT11-AA but by some peripheral device.
The signal is input to the DCTII-AA via the READY input. The signal is used to place the DCTII-AA
into an idle state while the peripheral device finishes its operation.
Refer to Figure 3-3. A single assertion of READY causes a single microcycle slip. An additional cycle
slip requires the READY signal to be pulsed again. The assertion of READY has no effect unless
- RAS is also asserted. The microcycle slip starts after the assertion of - RAS, - CAS, and PI leading
edges. A single microcycle slip occurs during every bus transaction if the READY input is connected to
ground.
TMlntel is a trademark of the Intel Corporation.

3-11

COUT

READY NOTE 2
NOTE 5
NOTE 6

r-,

,--,___

AI<7:0>

-RAS

\\S\~\\\\\\\\ ~t~~ 07//7

~_~~t;~ 111111111111111111111111111111111771//1/
I.
'I'
·1

_---'XrTTT(
(

((TTTT(
( ((TTTT(
(('7TT1(
( ( 'T'TT1(
( ( "TTT1(
((("'TTT1(
(( rTrr{(
((rrrT(
((

MICROCYCLE SLIP 2

-----'r««fC({(f{[~ ~ _-~~~~~ ~ ~ ~ ]I

(rTTT""(((- D - A
TA N I

((""T'T"T"1(
( ( (rrT"r(
((

TT
( -r1(

I.
X(((( (( (( (( (( (( (( (( (( (( ((( (( (( (( (( ((( ((

.1.

MICROCYCLE SLIP 1

'---'x

MICROCYCLE SLIP 2

xr ~IT(QUIIQ ~ ~t~E~~~ ~ ~ ILK

~NETQ~E~~A

MICROCYCLE SLIP 1

,---------------7

·1

MICROCYCLE SLIP 2

______________ -J

\,U

I'
PI

NOTE 1:
NOTE 2:
NOTE 3:
NOTE 4:
NOTE 5:
NOTE 6:

_____---.JI

MICROCYCLE SLIP 1

\L__________

WAVEFORMS ARE DRAWN FOR IS-BIT DYNAMIC READ
READY WAVEFORM IS VALID FOR ANY CASE
R/-WLB R/-WHB ARE ASSERTED HI THROUGHOUT THE TRANSACTION
SEL 0 SEL 1 ARE ASSERTED LO THROUGHOUT THE TRANSACTION
THE READY PULSE MAY BE OBTAINED BY GATING COUT WITH A READY ENABLE SIGNAL
HOLDING READY PERMANENTLY LOW RESULTS IN ONE MICROCYCLE SLIP PER BUS TRANSACTION

VALID
OUTPUT

_ _ _ _ _ _ _ _ _ _ _ _ -1

'1'

\ ---r::::::I

I N V A LID "iV'T'TT'1\'Cr
OUTPUT ~

MICROCYCLE SLIP 2

IGNORED
INPUT

------\\
1XillillXI
- ..... - - -_ •• ., r -

I ______ I
CONDITIONAL _J'-

r--- -------7

-I

MICROCYCLE SLIP 2

·1·

MICROCYCLE SLIP 1

-CAS

-r-

MICROCYCLE SLIP 1

DAL<15:O>

VA LID -y-----yINPUT ..A-----A...
MR-4869

Figure 3-3

READY Timing

-Z

l>
:D

PRELIMINARY
The READY signal extends the following transactions.
•
•

Read
Write

•

lACK

•

DMA

Detailed timing of READY is found in Figure A-15 in Appendix A.

3.5

MISCELLANEOUS SIGNALS

This group of signals includes the following.
•
•
•
•
•

-BCLR
PUP
COUT
XTLI
XTLO

3.5.1 - BCLR ( Bus Clear)
The signal - BCLR on pin 18 is asserted low by the processor during the power-up sequence and during
the execution of a PDP-II reset instruction. The -BCLR signal asserted (low) enables the mode register pull-ups on DAL<I5:8,I:0>. The -BCLR pin must be connected to ground through a lK fl, 1%
resistor. The signal's characterisitics are given in Table A-2 in Appendix A.
3.5.2

PUP (Power-Up)

PUP is a Schmitt-triggered input having a low-current internal pull-down that is always enabled. When
PUP is forced high, the Schmitt-trigger senses the transition. When the processor detects a change
from high back to low, the power-up sequence begins.
If PUP is asserted high during a DCTII-AA operation, the current transaction is terminated and all
internal registers go to an undefined state. The DALs and AI lines output undefined data and the control and miscellaneous signals are in an unasserted state. As soon as PUP is asserted low the power-up
sequence begins.

The power-up sequence is a series of events that initializes the DCTlI-AA. The power-up sequence
occurs in. two cases.
1.

When Vee is applied:
•
•
•
•
•
•
•
•

PUP changes state (low to high).
The - BCLR output is asserted.
PUP changes state (high to low).
The mode register is loaded.
The - BCLR output is cleared.
20 refresh transactions (8-bit dynamic) and 10 refresh transactions (l6-bit dynamic) or
20 busnop transactions (8-bit static) and 10 busnop transactions (l6-bit dynamic) occur.
The stack pointer is loaded to 3768, the program counter is loaded to the start address,
and the processor status word is loaded to 3408.
An ASPI transaction occurs.

3-13

PRELIMINARY
2.

When a reset instruction is executed:
•
•
•
•

The - BCLR output is asserted.
The mode register is loaded.
The - BCLR output is cleared.
An ASPI transaction occurs.

Detailed timing of power-up is found in Figure A-16 in Appendix A.
3.5.2.1 Power-Up (PUP) Input - Refer to Figures 3-4 and 3-5. The processor detects a transition from
low to high on the PUP input. The transition is sensed by an internal Schmitt trigger, which provides a
clean, fast edge when the input reaches a predetermined level (TTL VIL = 0.8 V). When the processor
detects a change from high back to low, the mode register load begins.
-BCLR

J MODE
-I BUFFER

i<lAL<15:a.1:0>

MEMORY
SYSTEM
(DYNAMIC)

-RAS
DCT11·AA

AI<7:0>

PUP

,/
~

V
-CAS

DEVICE

PI
~A-4870

Figure 3-4

Power-Up Sequence, Block Diagram

3.5.2.2 Bus Clear (- BCLR) - As a result of PUP being high, the processor is forced to an initial
condition with undefined register states. It is at this time (PUP high) that - BCLR is asserted. The
- BCLR signal is also asserted as a result of a program reset instruction. The - BCLR signal is a
strobe used by the user to enable pull-downs on data address lines (DALs) < 15:8>,< 1:0> at mode
register read time. The mode register is loaded through DAL<15:0>. However, DAL<7:2> are reserved. The - BCLR signal may also be used to initialize the rest of the system.
3.5.2.3 Mode Register Load - The mode register input begins after - BCLR is asserted and PUP is
low. The load process continues until the microcode returns - BCLR to a high.
3.5.2.4 Refresh or Busnop Transaction - Depending on the condition of the mode register the processor generates either refresh or busnop transactions. Refer to Table 3-8 for the conditions and the number of transactions generated.
3.5.2.5 Loading the SP, PC, and PSW - After the completion of the refresh or busnop transactions
the processor loads the stack pointer (SP) with 3768. The program counter (PC) is loaded with the start
address and, finally, the processor status word (PSW) is loaded with 3408.

3-14

PRELIMINARY

PUP

\~\~~~s~s------~s~s--I

-BelR \ \ \ \ \ \ \ \ \
MODE REGISTER
LOAD

OAl<15 0>

MODE REGISTER

~rAD

==1((((( ((m ((c }}~R---A- ==== ===X
==l(((mmmmm : m))))m}~~\
REFRESH 1

Al<70>

ltD10

REFRESH 20 (8-BIT MODE)

- - - r--------~55r------_r_--~1H \
-RAS __

L_..J

!16"T MOOEI

L_-'

MR-4871

Figure 3-5

Power-Up Sequence Timing

Table 3-8
Mode
8-bit/dynamic
16-bit/dynamic
8-bit/static
16-bit/static

Refresh and Busnop
Busnop

Refresh
20
10

20
10

3.5.2.6 ASPI Transaction - The last process in the power-up sequence is an ASPI transaction to check
for interrupts and DMA. At the completion of the ASPI transaction, normal operation begins. Refer to
Paragraph 2.15 for details on the ASPI transaction.
3.5.3 COUT (Clock Output)
COUT outputs a TTL-level clock that is a function of mode register bit 0 (MR <0». MR <0> determines if the output is to be processor mode clock (MR <0> = 1) or constant clock (MR <0> = 0).
Refer to Figure 3-6. In constant clock mode the output is at a frequency half that of the operating
frequency (the frequency of XTLO and XTLl). In processor clock mode a clock pulse is asserted once
every microcycle (every three or four oscillator periods). Detailed timing of COUT is found in Figure
A-17 in Appendix A.
3.5.4 XTLI and XTLO (Crystal Inputs)
These two pins (22 and 23) are the external crystal connections to the internal clock generator. If an
external TTL clock is used, it must be applied to XTLl (pin 22), and XTLO (pin 23) must be grounded.
Detailed timing of XT AL is found in Figure A-17 in Appendix A.

3-15

PRELIMINARY
XTLO

COUT
CONSTANT
(MRO = 0)"

COUT
PMC
(MRO= 1)

"MAY BE EITHER POLARITY DEPENDING ON THE OCCURRENCE OF PHASE D.
MA-4868

Figure 3-6

eOUT Timing

3.6 POWER PINS
The following are pins associated with the power source of the DCTlI-AA.
•
•

BGND
GND

•

Vee

3.6.1 GND and BGND
BGND and GND should be connected together. They provide the reference ground for all lines of the
DCTII-AA.
3.6.2 Vee
Pin 40 is the + 5 V supply for the DCTII-AA. This voltage must be maintained to within ± 5% of 5 V.

3-16

PRELIMINARY

CHAPTER 4
MODE SELECTION

4.1 INTRODUCTION
Most DCTII-AA features are programmable through the use of an internal 16-bit mode register (MR).
The DCTII-AA must be programmed during the power-up sequence and may be reprogrammed when
the PDP-II reset instruction is executed.
The four sections of this chapter describe:
•
•
•
•

Modes related to function
Modes related to timing
Mode register bit settings
Mode register selection guidelines

4.2 MODES RELATED TO FUNCTION
Refer to Figure 4-1 and Table 4-1. The modes related to function effect the functionality of the processor. These modes are
•
•
•
•
•

16-bit or 8-bit data bus MR< II >
Dynamic or static memory MR<9>
64K or 4K/16K memory chip size MR<10>
Tester or user MR<12>
Start/restart address MR<15:13>

4.2.1 16-Bit or 8-Bit Mode (MR<l1»
Mode register bit II determines if the processor operates the data bus in 8-bit mode or 16-bit mode.
The selection of either 8-bit or 16-bit data bus effects the DAL< 15:0>, R/ - WHB, R/WLB, and
AI <7:6> lines during read/write transactions. It also determines the number of transactions needed to
read or write a word.
4.2.1.1 16-Bit Mode - I f mode register bit II is asserted low (MR < II> = 0), 16-bit data bus mode
is selected and the following occurs in a read or write transaction (refer to Figures 2-2 through 2-9).
Data address lines:
DAL<15:0> -

Output of the 16-bit address before the assertion (leading edge) of - RAS.

DAL<15:0> -

Input or output of 16-bit data at read/write time.

Read/write control:
Each byte of a PDP-II 16-bit word is assigned a separate write control signal (R/ - WHB and
R/-WLB).

4-1

PRELIMINARY
07

<15:13>
12
11
10

START/RESTART ADDRESS
TESTER/USER MODE
16-BIT/8-BIT BUS
64K/4K OR 16K MEMORY
DYNAMIC/STATIC MEMORY

08
<7:2>
01
00

ADDRESS BITS
<15:13>

START
ADDRESS

RESTART
ADDRESS

7
6
5
4
3
2
1
0

172000
173000
000000
010000
020000
040000
100000
140000

172004
173004
000004
010004
020004
040004
100004
140004

NORMAL/DELAYED R/W
RESERVED
LONG/STANDARD MICROCYCLE
CONSTANT/PROCESSOR MODE CLOCK

MR 4843

Figure 4-1

Table 4-1
Mode Register Bit

Mode Register

Mode Register Bit Settings
State

Mode

Processor clock
Constant clock
Standard microcycle
Long microcycle
Delayed read/write
Normal read/write
Static memory
Dynamic memory
4K/ 16K memory
64K memory
8-bit bus
16-bit bus
User
Tester

o
I

o
8

9
10
II

o
I

4.2.1.2 8-Bit Mode - If mode register bit 11 is not asserted (MR < 11 > = 1), 8-bit data bus mode is
selected. Two transactions are required to perform a word read or word write. The following occurs
during a word read or word write operation (refer to Figures 2-10 through 2-17).
Data address lines:
DAL<I5:0>

Output of the 16-bit address before the assertion (leading edge) of - RAS.

DAL< 15:8> - The signal names for these pins are static address lines (SAL< 15:8:;»;
they hold the high byte of the address throughout the. two transactions.
DAL<7:0> -

Contains the low byte of the address during the read/write time of the first
transaction and the data during the read/write time of the second transaction.

4-2

PRELIMINARY
Read/write control:
A separate read/write control signal is provided for a read and for a write. The read/write control
signals are Read (- RD, pin name R/ - WHB) and Write ( - WT, pin name R/ - WLB). These
signals are mutually exclusive.
4.2.2 Dynamic or Static Mode (MR <9> )
Mode register bit 9 determines if the processor supports dynamic or static memories. This mode affects
the operation of the AI lines and SEL< 1:0> during read/write transactions, and the occurrence of the
refresh transaction (which adds time to the instruction execution time).
4.2.2.1 Dynamic Mode - If mode register bit 9 is asserted low (MR<9> = 0), dynamic mode is
selected and dynamic memories are directly supported. Besides outputting the address on
DAL < 15:0> before the assertion of - RAS, the DCTII-AA also outputs row and column addresses
on A 1< 7 :0>. The row address is output before the assertion (leading edge) of - RAS, which strobes it
into the memory chips. The column address is output before the assertion (leading edge) of -CAS,
which strobes it into the memory chips. In addition, automatic refresh is provided by means of the
refresh transaction (refer to Paragraph 2.11).
4.2.2.2 Static Mode - If mode register bit 9 is not asserted (MR<9> = 1), static mode is selected.
The memory is addressed using DAL< 15:0> at - RAS time and no refresh is provided. AI <7:0>
are used only for inputting interrupt and/or DMA information.
4.2.3 64K or 4K/16K Mode (MR<10»
Mode register bit 10 applies to dynamic mode only (in static mode it has no effect) and is used for
selecting the dynamic memory chip type. In 64K mode (MR < 10> = 0), memory chips such as 64K
X I-bit are supported.
In 4K/16K mode (MR<IO>
Refer to Table 4-2.

1), memory chips such as 4K X I-bit or 16K X I-bit are supported.

4.2.4 Tester or User Mode (MR<12»
Tester mode is for Digital Equipment Corporation's use only. If mode register bit 12
(MR<12> = 1), user mode is selected.

Table 4-2

DCTlI-AA Modes

Class

Bit

Mode Name

Function

Modes related
to function.

MR<9>
MR<IO>
MR<II>
MR<12>
MR<15:13>

Static or dynamic
4K/ 16K or 64K
8-bit or 16-bit bus
Tester or user
Start/restart

Dynamic RAM support
RAM chip type
Data bus width
Tester or user
Start/restart address

Modes related
to timing.

MR<O>

Processor clock or
constant clock
Long or standard
microcycle
Normal or delayed
read/write

COUT timing

MR
MR<8>

4-3

Microcode length
Read/write timing

high

PRELIMINARY
4.2.5 Start and Restart Address (MR<15:13»
Mode register bits 15-13 are used to specify one of eight start/restart addresses. The start address is
internally loaded into the program counter (PC) during the power-up sequence. For details on the power-up sequence refer to Paragraph 3.5.2. The restart address is loaded into the PC when a halt interrupt
is received or during the execution of a PDP-II halt instruction. Figure 4-1 indicates the available
start / restart addresses.
4.3 MODES RELATED TO TIMING
The following modes related to timing affect the timing of the processor but not its functionality.
•
•
•

Constant or processor clock MR<O>
Long or standard microcycle MR 
Normal or delayed read/write MR<8>

4.3.1 Constant or Processor Clock (MR<O»
If mode register bit 0 is asserted low (MR<O> = 0), constant clock mode is selected. The output of
COUT (pin 21) is a continuous clock waveform at a frequency half that of the operating frequency (the
frequency at XTLO and XTLl).
If mode register bit 0 is high (MR<O> = 1), processor clock mode is selected. In processor clock
mode, COUT outputs a clock pulse once every microcycle at phase W. This will occur every three or
four clock phases, depending on the presence of phase D.

4.3.2 Long or Standard Microcycle (MR < 1> )
Mode register bit 1 allows for the selection of a long or standard microcycle. If the bit is low (MR < 1>
= 0), long microcycle mode is selected. Long microcycle mode is used in conjunction with memory or
peripherial chips that require a long access time. When long microcycle mode is selected, all microcycles are made up of four operating frequency periods (they all contain OD).
If mode register bit I is high (MR < 1 > = I), a standard microcycle takes place. A standard microcycle is three or four operating frequency periods long, depending on the type of transaction.

4.3.3 Normal or Delayed Read/Write (MR <8»
If mode register bit 8 is low (MR<8> = 0), the DCTII-AA is in the normal read/write mode. In
normal read/write mode, the read/write control lines (R/ - WHB and R/ - WLB) become valid before
the assertion (leading edge) of - RAS and remain valid after its negation (trailing edge).
If mode register bit 8 is not asserted (MR<8> = 1), the DCTII-AA is in the delayed read/write
mode and the read/write control signals have the same timing as -CAS.

4.4 MODE REGISTER BIT SETTING
The mode register is set during the power-up sequence, or when the reset instruction is executed. At
either of these times the DCTII-AA asserts (low) the bus clear (- BCLR) signal, which may be used to
enable external drivers. The external drivers assert specific bits on the DALs to load the desired mode
in the mode register. The data on the DALs must be stable throughout the duration of the - BCLR
pulse.
NOTE
The assertion of - BCLR enables active internal
pull-ups on DAL<lS:8,1:0>. Only those mode register bits that must be driven low need be asserted.

4-4

PRELIMINARY
4.5 MODE REGISTER SELECTION GUIDELINES
The general guidelines below presume the DCTII-AA user has one or more of the following goals in
mind.
•
•
•
•

Minimum cost
Maximum speed
Minimum size (chip count)
Minimum development time

The suggested user modes are listed in the order of their influence upon the desired goal.
4.5.1 Minimum Cost
In order to minimize the cost of a system, the implementation of the following modes is suggested.
•
•
•

8-bit
Dynamic
Long microcycle

4.5.1.1 8-Bit Mode - This mode allow.s the use of 8-bit-wide device registers, data bus, and memories.
In this mode the minimum memory (typically n X 1 organization) uses eight chips.
4.5.1.2 Dynamic Mode - Although dynamic RAMs require refresh logic (provided by the DCT 11AA) they provide greater memory capacity at less cost.
4.5.1.3
chips.

Long Microcycle Mode - Long microcycle mode allows for the use of slower (less expensive)

4.5.2 Maximum Speed
In order to maximize the speed of a system, the implementation of the following modes is suggested.
•
•
•

16-bit
Static
Standard microcycle

4.5.2.1 16-Bit Mode - Every word read or word write operation is performed in a single transaction
rather than in two (8-bit mode). The 16-bit mode is typically 50% to 70% faster than 8-bit mode.
4.5.2.2 Static Mode - In static mode no refresh transactions occur. Without refresh transactions a
10% time saving for computational code is possible.
4.5.2.3 Standard Microcycle - A minor saving in time is possible through the use of this mode because
of the use of faster chips.
4.5.3 Mimimum Size (Chip Count)
In order to minimize the size (chip count) of a system, the implementation of the following modes is
suggested.
•
•

8-bit
Static

4-5

PRELIMINARY
4.5.3.1

8-Bit Mode - This mode allows the use of 8-bit-wide device registers, data bus, and memories.
In this mode the minimum memory (typically n X 1 organization) uses eight chips.

4.5.3.2 Static Mode - Static mode can take advantage of n X 4 and n X 8 static RAMs in order to
minimize chip count.

4.5.4

Minimum Development Time

I n order to minimize the development time of a system, the implementation of the following modes is
suggested.
•
•

16-bit
Static

4.5.4.1

16-Bit Mode - A 16-bit system is simpler to develop than an 8-bit system because in 16-bit
mode a single transaction performs a word read and a word write. Also, a 16-bit system is easier to
debug.
4.5.4.2

Static Mode - A static mode system is simpler to develop because no refresh transactions are
needed. Also, in a static system the AI lines are inputs at all times.

4-6

PRELIMINARY

CHAPTER 5
INTERFACING

5.1

INTRODUCTION

This chapter contains information that is useful for interfacing the DCTll-AA to most systems. The
chapter does not provide answers to all possible questions, but offers a few examples and solutions that
will enable the reader to get started. Interfacing information is presented on the following areas.
•
•
•
•
•
•
•
•

Power-up
Loading the mode register
System clock
Address latch and decode
Memory subsystems
Interrupts
DMA
Working with peripheral chips

NOTE
This chapter assumes that the reader is familiar with
the material presented in the previous chapters.
5.2

POWER-UP

Refer to Figure 5-1. A simple circuit can be constructed from a single ceramic capacitor C. The capacitor must satisfy the following conditions:
•
•

C;;;;' 0.04 /iF
C (/iF) ;;;;. 0.05 tR (ms)

where tR is the rise time of Vee.

NOTE
The DCTII-AA powers up in an undefined state (regardless of the state of PUP) until Vee is stable at
Vee minimum.
5.3

LOADING THE MODE REGISTER

Figure 5-2 shows how to program the mode register. On power-up, or when executing a reset instruction, the - BCLR pin is asserted low; this enables the desired bits onto the data address lines (DALs).
While - BCLR is asserted the DALs map one-for-one onto the internal mode register. When - BCLR
is negated the mode register is write-protected and the LS244 (buffer) shows a three-state load onto the
DALs. Unasserted bits may be left floating since they are pulled up internally by the DCTII-AA when
- BCLR is low. The - BCLR signal is buffered to provide enough drive for system initialization. All

5-1

PRELIMINARY
Vcc

DCT11-AA

L . . - - - - - - t pUP

MR-5501

Figure 5-\

Power-Up Circuit

Vcc

DAl <15:8.

lS244

1:0>
DCT11-A

-BClR u---.-----c~
1Kn
1%

-PUP
MR-5502

Figure 5-2

Mode Register Loading

devices in the system (except the buffer containing data for the mode register) should three-state their
outputs connected to DAL<15:0> at -BCLR time. This is done to prevent the mode register from
being loaded with questionable data.

NOTE
The pull-down resistor on - BCLR must be 1K 1"2 @
1% to guarantee timing specifications. The - BCLR
signal can sink up to 3.2 rnA and source 80 /-LA (can
drive two TTL loads in addition to the IK 1"2 load).
S.4 CLOCK
The DCTII-AA clock is generated by an internal clock circuit. This circuit uses as an input one of two
sources:
•
•

A crystal
A TTL oscillator

5-2

PRELIMINARY
5.4.1 Crystal-Based Clock
The DCTII-AA oscillator circuit is a quasi-linear wide-band amplifier. Refer to Figure 5-3. Three components and proper layout are required to use a crystal with the DCTII-AA. The three components are
•
•
•

A crystal, with loss resistance (RS) at various resonancies
An input capacitor (CA) connected to XTLO (pin 23)
An output capacitor (CB) connected to XTLl (pin 22)

cA
I---r----i XTL 1

D
CB

c::J

DCTll-AA
XTLO

'::'

MR-550B

Figure 5-3

Crystal Oscillator Clock

A fourth component (caused by stray effects of crystal and layout) is a strong input-output capacitance
(CD) between XTLO and XTL 1. Other stray components, such as high frequency inductance of the
connections, have only minor effects at frequencies « 7.5 MHz) when connection paths are less than
two inches_
The capacitors CA and CB are needed to adjust the load to the crystal. The inputs XTLO and XTLl
load the crystal to more than 30 pF (which is the nominal load for most crystals), thus pulling it off
frequency.
The recommended circuit values for the crystal oscillator clock in Figure 5-3 are
Crystal:
Cut at fundamental (At)
Load 30 pF
Rs < 200 Q -7- fMHz (fundamental; i.e., 27 Q @ 7.5 MHz)
Rs > 4000 Q -7- fMHz (spurious)
Rs > 400 Q -7- fMHz (harmonic)
Co < 4 pF
Capacitors:
Type mica
Nominal value (± 10%)
CA (XTLO) 500 pF -7- fMHz (example: 67 pF @ 7.5 MHz)
C B (XTLl) 200 pF -7- fMHz (example: 27 pF @ 7.5 MHz)
These specifications guarantee against third harmonic and spurious start-ups. If such guarantees are
not necessary and only a steady oscillation is required, most crystals can be used. Detailed timing of
XT AL is found in Figure A-I7 in Appendix A.

5-3

PRELIMINARY
5.4.2 TTL Oscillator-Based Clock
Refer to Figures 5-4 and 5-5. A TTL signal may be used to drive XTLl (pin 22) while XTLO (pin 23) is
grounded. The XTL 1 TTL signal must satisfy the following criteria.
•
•
•
•
•

Period T > 133 ns
Rise time tR < 80 ns
Fall time tF < 80 ns
Low time tL > 60 ns
High time tH > 60 ns

t - - - - - - i XTL 1
DCTll-AA

XTLO
MR-5509

Figure 5-4

TTL Oscillator Clock

MR-5503

Figure 5-5

TTL Oscillator Waveform

Refer to Figure 5-6. The XTLl signal may be gated to stop operation of the DCTII-AA as long as the
signal at the XTL 1 pin meets or exceeds the above criteria. XTL 1 may be left high or low indefinitely.
STOP L
XTLl
DCT11-AA

XTLO
MR-5504

Figure 5-6

Gating XTL 1

5.5 ADDRESS LATCH AND DECODE
Refer to Figure 5-7. In 16-bit mode the 16 bits of address can be conveniently latched by a transparent
latch (such as an LS373) enabled by the row address strobe (- RAS) leading edge.
Refer to Figure 5-8. In 8-bit mode only the low byte of the address needs to be latched since the high
byte remains stable on the static address lines (SAL< 15:8» throughout the whole read or write transaction.
Address decoding can be done in a number of traditional ways. In Figures 5-7 and 5-8 PLAs are used to

5-4

PRELIMINARY
provide direct strobing of several registers. Because the circuit uses a transparent latch, the PLA inputs
are stable before - RAS; therefore, some of the strobes have - RAS timing, whereas others have column address strobe (-CAS) timing. The CAS signal should be ANDed with RAS to prevent the enabling of strobes during an ASP! transaction.

DAL <15:0>

RAS

LS373 t--.,...~ 82S101

TIMING

STROBES
DCTll-AA

-RAS ~,,----~----~--~
VCC
-CAS ~--a._~

CAS
TIMING

STROBES

MR·5SQ7

Figure 5-7

16-Bit Address Latch and Decode

SAL < 15:8 >~8~_ _ _......

VCC

8
DAL < 7:0 > ~8"""""-t LS373 t--+-...8+--t 82S101

RAS
TIMING

STROBES
DCT11-AA

-RAS~,-----~--~~--~

Vec

-CASD--<LJ

CAS
TIMING

STROBES

MR-5506

Figure 5-8

8-Bit Address Latch and Decode

5.6 MEMORY SUBSYSTEMS
Two examples of memory subsystems are described below, one using 16-bit mode and the other using 8bit mode.
5.6.1 16-Bit Mode Memory System
An example of a 16-bit mode dynamic memory system is shown in Figure 5-9. The memory map is
shown in Figure 5-10. The address is latched in the LS373 chips by -RAS. The address is then decoded in the LS138 into eight sectors in the upper half of the memory. The sector 140000 to 147776

5-5

ADDR.DECODE

ADDR. LATCH

r--"------.
AI<7:1>1
DAL<15:0:;: I

ROM

"'tJ
:ll

RAM

r---------------~A~

________________

.-3C
r-

7(
;

(

) 16

LDAL<i5:0> H
LDAL<II:I>H

n---01----....IA 10:
10

ADDR
LATCH
LS373
(X2)

ROM
2716-1
(X2)

•

z
»

,L
7

RAM LB
4116-3
(XB)

.-<

LS244
(X2)

ADDR
DECODE

DCTll-AA

A
B

LS138

RD L

Gl
Vo
I

-RASO~--------~--------~

RAM HB
4116-3
(X8)

-CAS~

Plt-~--~

DIN _

R/-WLBO

R/-WHB 0

177776
170000
160000
140000

Y7
Y6

64KB
60KB
56KB
48KB

WLB L

~;""jj;;;;;';;»>;;;;",j 32 K B

RD L
RAMCAS L
RAMCAS L
NOTE'

16KB
0

MODE' REGISTER = MR<150> = 11 1 0 1 0 1 1 1011 101 0 IX I X I Xix IX IX 11 11

X = DON'T CARE

Wff/P/L«////ff/ffPpA OKB
MR 5"17

Figure 5-9

16-Bit ROM (4K) and Dynamic RAM (32K) Subsystem

PRELIMINARY
maps into the ROM. This is implemented by selecting the ROM ( - CE) with the output Y 4 and selecting -OE with -CAS (refer to Figure 5-10). The fast variation ROM (2716-1) must be used, if running at more than 6.9 MHz, in order to meet the DCT11-AA specification of tRRD (405 ns at 7.5
MHz).
177776 . - - - - - - . . . . . . , 64KB
170000
160000

60KB
56KB

140000 f""=..:..................="1 48KB

100000

='?777'7~

32KB

40000

16KB

OKB

Figure 5-10

16-Bit System Memory Map

The RAM is made of high-byte and low-byte sections that have everything in common except the
- WE strobe. The whole RAM is chip selected by controlling - CAS and sending - RAS to all chips
at all times. Using -CAS as chip select has the advantage of refreshing a row at every occurrence of
-RAS.
Although -CAS drives 160 pF (10 pF per RAM chip), it does not require buffering. The DCT11-AA
output timings are specified for a purely capacitive load of 80 pF. For loading other than 80 pF use the
following correction factors.

•
•

80 pF < CL < 200 pF
25 pF < CL < 80 pF

+0.3 nsjpF
-0.3 nsjpF

This results in a -CAS delay of 80 X 0.3 = 24 ns with respect to the nominal timing specifications.
Such a delay still meets the RAM chip specifications for -RAS and -CAS hold time (55 ns minimum for 4116-3). Refer to Figure 5-11.
The DALs drive the DIN inputs of the RAMs directly. The DOUT lines cannot be connected directly
to the DAL bus and must be buffered. This is required because the DCTII-AA does not drive the data
on the DALs soon enough (before the -CAS leading edge) to perform an early write on the RAMs.
Thus, the system only performs a read-modify-writet which would result in contention on the DALs.
The contention would occur between the data driven by the DCTI1-AA and the DOUT driven by the
RAM chips.

5-7

PRELIMINARY
AI AT DCT11-AA
PIN NOMINAL

(

COLUMN ADDRESS
tAHC = 90 ns MIN

CAS AT DCTll-AA
PIN NOMINAL
i--tCD = 2 4 - 1--90-24 = 66 ns MINCAS AT RAM
PIN ACTUAL

~\\\\\ \ \\\'

tCD = CAS DELAY CAUSED BY 160 pF LOAD (160-80) X.3 = 24ns
ALL TIMINGS IN ns
MA-5511

Figure 5-11

Column Address Setup and Hold-Time Calculations

The buffer is enabled only when the DCTII-AA is performing a read from RAM (signal RD L). Tables
5-1 and 5-2 list the control signals and the states of the data bus for each transaction, respectively.
Table 5-1

Control Signals for Each Transaction

Transaction

-RAS

-CAS

Rj-WHB

Read

Fetch

Write

Refresh

lACK

DMA

ASPI

Rj-WLB

SELO

SELl

*
2

Busnop

* - Signal asserted during the transaction.
I - Static modes and dynamic 64K.
2 - Dynamic modes 4Kj16K.
X - Signal asserted during 8-bit mode only.
- Signal asserted during 16-bit mode only.
3S - Three-state.

5.6.2

8-Bit Mode Memory System

Refer to Figure 5-12. Since the data bus is 8 bits wide and the memory organization is different from
that of a 16-bit system, an 8-bit minimum system can be implemented using only half as many memory
chips as a 16-bit minimum system. The memory map implemented is shown in Figure 5-13 and the
circuit schematic in Figure 5-14. The signals WT Land RD L are easily generated in this configuration.

5-8

PRELIMINARY

Table 5-2

Data Bus for Each Transaction

DALLow Byte

Transaction

DAL High Byte

Read

Fetch

Write

Refresh

•

lACK
DMA
ASPI
Busnop

X - Lines driven after address portion of transaction (8-bit mode only).
* - Lines driven after address portion of transaction (8-bit and 16-bit modes).
- Dynamic modes only.
3S - Three-state.

3
ADDR.

4
ADDR.

HB b

LB b

HB b

LB b

HB a

LB a

B 7
16 BIT

7
8 BIT

MR·5513

Figure 5-12

16-Bit/8-Bit Memory Organization

5-9

PRELIMINARY

177777 . - - - - - - - . . . . . . . , 64KB
160000 I---~---I
140000 ""'='""'""'""=~ 48KB

100000 1---...:...::.----1 32KB

16KB

OKB
MR-5514

Figure 5-13

AI<7:1>

8-Bit System Memory Map

ADDR.LATCH

ADDR.DECODE

ROM

RAM

DAL<7:0>
8

SAL<15:8>

SAL<10:8>H

8
LDAL<7:0>H
ADDR
LATCH
LS373

8
Al0:A8

ROM
2716·1
A7:AO

ADDR
DECODE

DCT11·AA

RAM
4116·3
(x8)

LS244

LS138

WT L

RD L

R/-WLBn-_ _ _ _ _--<::J
(-WT)

WTL

SAL <15> L

R/-WHB~--------------------------<l
(-RD)
MR·!)515

Figure 5-14

8-Bit ROM (2K) and Dynamic RAM (16K) Subsystem

5-10

PRELI.MINARY
5.7

INTERRUPTS

The examples of interrupts cover the following areas.
•
•
•
•
•

5.7.1

Posting interrupts
Decoding lACK information
External vectors
Using a priority encoder chip
Direct CP (coded priority) encoding

Posting Interrupts

Refer to Figure 5-15. To avoid propagation of metastable states, it is necessary to drive stable signals as
interrupt requests. A latch can be used for this purpose. The delay between - CAS and PI (tcsp = 105
ns @ 7.5 MHz) is long enough to settle any metastable states on the output of the flip-flop.
INIT L

~.--

lACK L'
ANY AI

DCTll-AA
IRQ L

-CAS D-~(l

Vcc
______________________

'lACK L; (SEL Q·SEL 1) + (-RAS)
MA·5519

Figure 5-15

General Interrupt

5.7.2

Decoding lACK Information
Figure 5-16 shows an example of how to decode lACK information for 15 CP devices. An LS 138 can
be used instead of an LS 154 when fewer interrupts are needed. The LS 138 can also be used if care is
taken to pick CP codes such that one of the CP lines is always low for all CP codes (3-line encoding).

Figure 5-17 shows an example of a complete interrupt system (interrupt request and interrupt acknowledge) for six CP devices.

5.7.3 External Vectors
If - VEC (AI <5» is asserted (low) during the interrupt request, the DCTI1-AA obtains the vector
on DAL<7:2> from the device during the lACK transaction. Figure 5-18 shows an example of such a
circuit.

5.7.4

Using a Priority Encoder Chip

Refer to Figure 5-19. Six devices can generate an interrupt using the internal vectors of the DCTllAA.
In order to handle more than 15 CP interrupts, each of the 15 prioritized lines can be made up of a
daisy chain of several devices. All devices on the same daisy chain have the same CP code, but they are
distinguished from one another by different external vectors during the lACK transaction.

5-11

PRELIMINARY

INCREASING
PRIORITY
(CPO)

DAL<ll>

(CP1)

DAL<lO>

(CP2)

DAL<9>

(CP3)

DAL<8>

DCT11-AA

0
G1 G2

-RAS

lACK 1 L

154
1

lACK 15 L

lACK L

SEL 1
SEL 0
NOTE:
lACK 1 CORRESPONDS TO ALL CPs ASSERTED
AT IRQ TIME (I.E., INTERNAL VECTOR 140).
lACK 15 CORRESPONDS TO ONLY CPO ASSERTED
(I.E., INTERRUPT VECTOR 70)_

MR-5518

Figure 5-16

Decoding lACK Information for 16 CP Devices

5-12

PRELIMINARY

INTERRUPT REOUEST CIRCUIT
LS148
7 EN6 CODER

VCC
LS273
LATCH

LS244
BUFFER

DMR L

AI<O> (-DMRI

AI<l> (-CP31

DEV51ROL

AI<2>

(-CP21

DEV 4 IRO L

AI<3>

(-CP1)

DEV31ROL

AI<4>

(-CPO)

DEV21ROL

AI<5>

(-VEOI

DEV1IROL

AI<6>

(-PFI

AI<7>

(-HLTI

DEV61ROL

VCC

CAS L
GND
PI H

INITL

-LS138
LS148
DURING lACK
DURING IRO{

A
AO

DAL11 DAL10

Y2 Y3 Y4 Y5 Y6
0

345

DAL9 DAL8

-CPO

-CPl

-CP2

-CP3

AI4

AI3

AI2

All

L
H
L
H
L
H

L
L
L
L
L
L

H
H
L
L
H
H

L
L
H
H
H
H

INTERNAL
VECTORS
H
H
H
H
H
L

H
H
H
H
L
H

H
H
H
L
H
H

H
H
L
H
H
H

H
L
H
H
H
H

L L
H H
H H
H H
H H
H H

H
L
H
H
H
H

H
H
L
H
H
H

H
H
H
L
H
H

H
H
H
H
L
H

H DEV6
H DEV5
H DEV4
H DEV3
H DEV2
L DEVl

100
104
120
124
60
64

lACK CIRCUIT

(CPO
(CP21
(CP31

DAL<ll>
DAL<9>

LS138
Y7

DEV 1 lACK L

DEV 2 lACK L

DAL<8>

VCC

DEV 3 lACK L

DEV 4 lACK L

DEV 5 lACK L
DEV 6 lACK L

SELl H----------~
SELO H
'SIGNAL IS GENERATED BY THE USER AND MUST BE STABLE AT PI TIME.
MR 5520

Figure 5-17

Interrupt System

5-13

PRELIMINARY

GND
RESUL TlNG
VECTOR"
(34)
DEV 3 lACK L
(54)

LS244
DAL<7>
DAL<6>
DAL<5>

DEV 2 lACK L

DAL<4>

(64)

DEV 1 lACK L

DAL<3>

(70)

DEV 0 lACK L

DAL<2>

lACK L •
DAL<12> -~_~

'lACK L = (SE L O·SE L 1) + (-RAS)
"CAN BE HARDWI RED I F A SI NG LE EXTERNAL VECTOR INTER RUPT IS USED
'··USED ONLY WITH BOTH EXTERNAL AND INTERNAL VECTOR
(IF EXTERNAL ONLY, USE lACK L)
MR-5521

Figure 5-18

Driving an External Vector During lACK

5-14

PRELIMINARY

DMR L*

AI<O> (-DMR)

7
IRO 6 L

AI<l> (-CP3)

IR05 L

AI<2> (-CP2)

IR04 L

IRO 3 L

LS374

IRO 2 L

LS147
B

LS244

AI<3> (-CP1)
AI<4> (-CPO)

2
AI<5> (-VEC)

VEC L*

IRO 1 L
PF I RO L

AI<6> (-PF)

HLTIROL

AI<7> (-HLT)

CAS L

PI H

'SIGNALS ARE GENERATED BY THE USER AND MUST BE STABLE AT PI TIME (L.E.).

-CP<3> -CP<2>
(AI<l» (AI<2»

INTERNAL
-CP<l> -CP<O> PRIORITY VECTOR
(AI<3» (AI<4» LEVEL
ADDRESS

X
X

L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H
L
H
L

H
L
H
L
H

B
B
7
7
7
7
6
6
6
6
5
5
5
5
4
4
4
NO ACTION

DEVICES
IMPLEMENTED

24
140
144
150
154
100
104
110
114
120
124
130
134
60
64
70

HLT IRO
PF IRO

IR06
IR05
IR04
IR03
IR02
IROl

MR·5522

Figure 5-19

Interrupt Request Circuit (Priority Encoder)

5-15

PRELIMINARY
5.7.5 Direct CP Encoding
Direct CP encoding (refer to Figure 5-20) can be accomplished only when there are four or less CP
devices (one device per CP line). The highest priority device D3 will connect directly to CP<3> and
the lowest to CP<O>. If internal vectors are used, locations 140-154 and 100-114 must be loaded
with the vector address relative to D3. Locations 120-134 must be loaded with the vector address relative to D2. Locations 60 and 64 must be loaded with the vector address relative to D1 and 70 to DO.
AI<7:5,0> do not need to be driven high because the DCTII-AA has internal pull-ups on those lines
at PI time. Refer again to Figure 5-20. A higher device lACK will clear a lower device interrupt
request before the request is serviced.

LS173

AI<1>

(CP3)

DEV2 IRO L

AI<2>

(CP2)

DEV1 IRO L

AI<3>

(CP1)

DEVO IRO L

AI<4>

(CPO)

DEV3 IRO L

DAL<8> ---(:JI

DAL<9> --i--CJl
DAL <10> -r--<T-""

CAS H
DAL<11>-r--«-""
lACK L* - -___./

PI L

DEV3 lACK

DEV2 lACK

DEV1 lACK

DEVO lACK L

GND

'lACK L = (SEL O·SEL 1) + (-RAS)

-CP<3>
(AI<1»

-CP<2>
(AI<2»

-CP<l>
(AI<3»

-CP<O>
(AI<4»

PRIORITY
LEVEL

VECTOR
ADDRESS

x
x

8
8

L
L
L
L
L
L
L
L

L
L
L
L
H
H
H
H
L
L
L
L

L
L
H
H
L
L
H

L
H
L
H
L
H
L

L
L

H
H

L
L

7
7
7
7
6
6
6
6
5
5
5
5
4
4
4

140
144
150
154
100
104
110
114
llU
124
130
134
60
64
70

NO ACTION

H
H
H

H
H
H
H
H

H
H
H
H

H
H

L
L
L

-HALT
-PF

"
DEVICE 3

}

DEVICE 2

)

DEVICE 1
DEVICE 0

MA·5523

Figure 5-20

Direct CP Encoding Interrupt System

5.8 DMA
During DMA the DCTII-AA provides -RAS, -CAS, PI, and COUT signals. The external circuitry
has the responsiblity for controlling the Rj - WHB and Rj - WLB lines, providing the address, and
supplying or accepting data.
During DMA transfers, system circuitry goes through the following sequence.
1.

A DMA request (DMR) to the DCTII-AA is made by driving AI<O> low during PI.

5-16

PRELIMINARY
2.

The request is latched into the DCTll-AA during PI and shortly thereafter a DMA grant is
issued.

The maximum time from the request's origination to the grant's issuance is a function of the DCTllAA mode. This time is specified in Table A-22 in Appendix A. When the grant is issued the DCTllAA takes the following actions.
•

SELO and SEL 1 become high, thus informing the system that the grant has been issued.

•

- RAS, - CAS, PI, and COUT are driven with the timings specified in the DMA transaction timing diagram (Appendix A, Figure A-l3).

•

The DALs are three-stated.

•

AI<7:0>, Rj-WHB, and Rj-WLB have low-current pull-ups.

When the grant is issued, external circuitry must drive the Rj - WHB and Rj - WLB lines, and initially drive the DALs with the address. In dynamic memory systems the address must be multiplexed
on AI <7:0> so that the memory chips are provided with row and column addresses at the appropriate
times. Later in the transaction the data transfer on the DALs takes place in a direction controlled by
the state of the Rj - WHB and Rj - WLB lines. The DCTII-AA continues issuing grants for DMA
transactions until DMR L is no longer asserted low on AI <0> during PI. When this happens the current sequence of DMA transactions finishes and the DCTII-AA resumes normal operation.

5.8.1 Single-Channel DMA Controller (16-Bit Mode)
This section describes a single-channel DMA controller for use with dynamic or static memory systems.
Refer to Figure 5-21.
5.8.1.1

Address Latches (Single-Channel DMA Controller) - Address latches can be shared with the
rest of the system. In a static memory system, if address latches are not necessary for the rest of the
system, the four chips E3-E6 may be eliminated. In a dynamic memory system, if address latches are
not necessary for the rest of the system, the two chips E3 and E4 may be replaced by one latch that will
save the appropriate AI bits for the -CAS strobe.

5.8.1.2 Pulse Mode Clock (Single-Channel DMA Controller) - Refer to Figure 5-21. The pulse mode
clock is used in this circuit. If this is not possible, a delay line or RC combination can be used for the
generation of an edge between -RAS assertion (low) and -CAS assertion (low). This edge switches
the Al multiplexer from row address to column address in dynamic memory systems. In a static memory system this switching is not needed. Pulse mode clock also produces a convenient edge in the middle
of PI that is useful when writing to peripherals.
5.8.1.3 Address Decode Structures - A PLA or any other address decode structure provides the following register selects.
S-A L
S-C L
DMACR L

Select address counter in the DC006s (DEC DMA chip)
Select word counter in the DC006s
DMACR (DMA control register) is an optional register that may specify DMA
direction and make DMA requests under software control.

5.8.1.4

Operation Sequence (Single-Channel DMA Controller) - The DCTII-AA software loads the
DC006s with the 2's complement of the word count and then with the bus address. After the loading the
peripheral is signaled that the DMA setup is complete.

5-17

DAL BUS

,
I'EAD l

RI -WLB

" A D l b elKA

RI -WHB

,.,

.... CLKC

~ CNTIA

':' LD
S-AL-< S-A
S-CL--c SoC

PIH

64D/F
32D/F
16D/F
8D/F
E1 4D/F

2D/F
DALB H
1D/F
MAX-A I-MAX-C I-- WD CNT H
DCOO6

S74
E7A

-yO

ROWADHR-

eASl

>-~

PMCCO~T-~

DAL 15 H

DAL 15 HU

(: RD
RD-A

o I--ROWAD L

DMGH-

""1'

DAL8 H

'"0

::u

ADDRESS LATCH

D1
D2
D3
D4
D5
D6
D7
D8

LS
373
E3

R1
R2
R3
R4
R5
R6
R7
RB

ENB

CLR

RAl L

VCC

DAL LAT
15 H

m
r-

-s::

LS257

}A"-'

MUX
E5

>
::u
-<

ALLATBH

ROWAD L

DAL BUS
SEL 0 ~==r->
SEL 1 H
------'

VI
I

DAL7H'11
CLK A
CLK C
CNTIA
XFER
LD
S-A
E2
~ S:-C
RD
RD-A

WO~

S-A~~):>
S-C L-

IRE~

•
DAL 7 H

DALO H

ADDRESS LATCH

D1
D2
D3
D4
D5
D6
D7
D8

LS
373
E4

R1
R2
R3
R4
R5
R6
R7
RB

f-DC006

ENB

CLR

Vee

DAL LAT
7H

MUX
E6

} " B-3

AL LAT 0 H

RAS L

LS257

ROW AD L
DMG H
PI H

N DATA FROM PERIPHERAL H

DMG H

CAS H

EN DATA INTO PERIPHERAL H

r--------------------------------------~

CAS H

DMG L

I PERIPHERAL

I DMA REO H

PERIPH. IN HB L

PMCCOUT H

I
I

CONNECTED TO R/ -WHB I
AND RI -WLB DCT11-AA I

I
I

RI -WHB L

DMR L
PERIPH. IN LB L
WDCNTH

RI -WLB L

I
I
I

• WIRE MUX INPUTS WITH DAL LATOUTPUTS FOR EITHER BYTE
BCLR H
I
ORWORD TRANSFER AND FOR TYPE OF DYNAMIC MEMORY
L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ...J
MA·5561

Figure 5-21

Single-Channel DMA

PRELIMINARY
The peripheral device makes a DMA request by asserting the upper DMA REQ H, which in turn
causes the assertion of DMR L. The DCTII-AA issues a DMG and drives -RAS, -CAS, PI, and
COUTo The peripheral drives Rj - WHB and Rj-WLB and negates the signal, upper DMA REQ H.
The signal ROW AD H is already asserted high when the DMG cycle starts. ROW AD Hand DMG H
send the output of AND gate E8A high, which asserts the read input to the DC006s. The DC006s drive
the address onto the DALs, where it is input by the address latches. These in turn drive the AI multiplexer inputs. During this period the AI multiplexer is pointing to the row address inputs.
Between - RAS assertion (low) and -CAS assertion (low) the trailing edge of the PMC COUT signal
clocks latch E7 A, driving ROW AD H to a low state. When ROW AD L goes high the Al multiplexer
inputs switch to the column address and the output of AND gate E8A goes low, which affects the
DC006s in two ways:
•

The DC006s' inputs become three-stated, so they stop driving the address onto the DALs.

•

The word count and bus address registers of the low-byte DC006 are incremented. The word
count increments by one if the CNTIA input to E2 (WORD XFER) is low and increments
by two if it is high.

I f the count in E2 reaches a maximum, the next count edge will also increment E I. When the word
count overflows, WDCNT H is asserted, which sets the DMR latch E7B; no further DMA requests are
made.

5.8.2 Software DMA Requests
A small modification to the hardware permits software DMA requests and software specification of the
transfer direction. Substitution of the schematic in Figure 5-22 for the enclosed section of Figure 5-21
results in the necessary hardware modification.
R200 SOFTWARE DMR CONTROL

CAS H
PERIPHERAL DMA REO H

VCC

BUF DAL 1 H

BUF DAL 0 H

S74
DMACR L
PI L

WRITE CR H

DMR L

R/ WLB L
VCC
DMG L

WDCNT H

MA-5562

INIT H

Figure 5-22

Software DMR Control

The transfer direction is specified by writing to bit 0 of the DMACR (DMA control register). Writing a
1 to bit 0 of the DMACR specifies DMA transfers from memory to the peripheral. Writing a 0 to bit a
of the DMACR specifies DMA transfers from the peripheral to memory. Writing a 1 to bit 1 of the
DMACR makes an immediate DMA request. The request will be latched into the DCTII-AA during
the same transaction that wrote the DMACR.

5-19

PRELIMINARY
5.9 WORKING WITH PERIPHERAL CHIPS
Though almost all peripheral chips will work with the DCT l1-AA, this section discusses only these
three selected ones:
•
•
•

8155 RAM, three ports, and timer
2651 PUSART
DC003 interrupt logic

5.9.1 8155 - RAM, Three Ports, and Timer
Refer to Figure 5-23. This example uses 8-bit mode, delayed read/write mode. If normal read/write is
desired, it is necessary to gate the read/write lines with -CAS. Chip enable and IO/M control is accomplished by static addresses, which remain valid throughout the transaction.
8155

SAL < 8 >

10/M

SAL <15>

DCT11-AA
-RAS

~ I/O PORT A

I 8

DAL <7:0>

1"'1

....

AD 7:0
CE

.... ALE

....

-....

R/-WHB
..,
(-RDI

~ I/O PORT B

~ I/O PORT C

.... WT

R/-WLB
(-WTI
I'""

MR-5524

Figure 5-23

8155 RAM

5.9.2 2651 - PUSART
Refer to Figure 5-24. Two facts must be understood when interfacing the 2651 PUSART to the
DCT II-AA. Compatibility depends on these two facts:
•

Every DCTII-AA write is preceded by a read from the same location (except in stack operations, traps, interrupts, and subroutines).

•

The 2651 PUSART's receive data buffer and transmit data buffer have the same address
inside the chip. The buffers are selected by the R/W input.

An involuntary read from the receive buffer clears the receive ready pin, and may result in the resetting
of the receiver interrupt. To avoid this it is necessary to assign separate addresses to the receive and
transmit buffers and disable read transactions from the transmit buffer.
For the same reason, the 2651 mode registers must be accessed by a proper sequence of reads and
writes. For example, in 16-bit mode:
•

To write mode register I: disable transmit and receive, read the mode register, and write the
mode register.

•

To write mode register 2: disable transmit and receive, and write the mode register.

In 8-bit mode the same operation takes place but byte instructions must be used. If word instructions
are used, the same 2651 register is accessed twice, thus incrementing the mode register pointer.

5-20

PRELIMINARY
READY L

VCC

...L
I-------+--+-----IR ESET
-t-'--I(J CE
2651CE L
(-CAS TIMING)

07:00

OAL <2>

-I---~AO

OAL <3>

-1---~A1

2651 RO L

-L..-~(JRO/WT

2651

RX ROY D---'------<(l

RXIRO L

TX ROY D-~-+---1:l

TXIRO L

MR-5525

Figure 5-24

2651 PUSART

The 2651 's access time is 250 ns. A REAOY slip should be used when the OCTII-AA is running at
frequencies greater than 7 MHz.
If the DCTll-AA is running at a frequency greater than 6 MHz, <00:07> require buffering to the
DALs. The buffering is necessary because the 2651 's turn-off time is 150 ns (maximum) with a 100 pF
load. The tCDE for the OCTII-AA at 6 MHz is 148 ns (maximum).

5.9.3 DC003 - Interrupt Logic
Refer to Figures 5-25 and 5-26. The interrupt chip is an 18-pin, dual in-line package device that provides the circuits for handling interrupts. The chip can be used in any externally vectored interrupt scheme
and the system does not have to be daisy-chained. The device is used in peripheral interfaces to provide
two interrupt channels, labeled A and B, with the A section at a higher priority than the B section.
DC003s may be daisy-chained at any priority level.
Daisy-chaining multiple DC003s may cause an error condition. If the requesting device receives the
signal IAK L too late, it will not be able to assert its vector during the lACK transaction.

5-21

PRELIMINARY

RD OA CONTROL STATUS REGISTER (CSR) H - . . . - - - - - ,

DAL < 7 >

DAL < 6 >

DC 003
+5

DEV OA IRQ H

RQSTA

ENAST

IAK L

BIAKI

BIRQ

BCLR L

BINIT

BIAKO

BDIN

INITO

- DEV OB IRQ H
DAL<6>

470 n
TO AI DRIVER

TO NEXT DC 003 IN DAISY CHAIN

RQSTB

VECTOR

ENA DAT

VEC RQST

ENB DAT

ENB ST

}USED TO GENERATE EXTERNAL VECTORS
DAL < 6 >

ENA
CLK

ENB
CLK

LOAD OA
CSR H

LOAD OB
CSR H

DEV OB IRQ H -+-~

RD OB CSR.H

Figure 5-25

DC003 Interrupt Logic

5-22

DAL < 7 >

PRELIMINARY

+5V
470.11

+5
DEV OA
IRQ H

DC 003
RQST A
ENA ST
BIRQ

BIAKI
BCLR L
CAS L
DEV OB
IRQ H
B DAL
<6>

470 .11
DEVIA
IRQ H

AI < 2 > (CP2)
LS173

BINIT
BDIN

INITO

RQSTB
ENA DAT VEC RQS
ENB DAT

ENB ST

ENA

ENB

AI <3> (CP1)

BCLR L

AI < 4 > (CPO)

CAS L
DEVIB
IRQ H

AI < 5 > (·VEC)

IAK H
B DAL<6>

GND
LOAD OA CSR H
READ DRIVERS FOR
INTERRUPT ENABLE
AND DONE BITS ARE
NOT SHOWN IN THIS
DIAGRAM.

LOAD OB CSR H

DEV 2A
IRQ H
IAK L

DC 003
BIAKI

BCLR L

BIRQ
BIAKO I ( } - - - - - - - - - - - - - - '
LS 244

CAS L
DEV2BIRQH

DEV 21AK H
DEV 2B IAK H

B DAL <6>

LOAD 2A
CSR H
INTERRUPT
DEVICE CHANNEL
0
0
1
1
2
2

A
B
A
B
A
B

LOAD 2B
CSR H

GND

DAL < 7 >

GND

DAL < 6 >

DEV 2 IAK H

DAL < 5 >

DEV 1 IAK H

DAL < 4 >

DEV 0 IAK H

DAL < 3 >
DAL < 2 >

PRIORITY EXTERNAL
VECTOR
10
4
4
14
DEV 1B IAK H
4
;~ DEV 2B IAK H
4
40
5
44
5

DCT11·AA
IAK L - - - - - READY
PIN

THIS SECTION CAN BE REPLACED
WITH A ROM FOR BETTER SELECTION
OF EXTERNAL VECTORS.
MR 5526

Figure 5-26

De003 at Different Priority Levels

5-23

PRELIMINARY

CHAPTER 6
ADDRESSING MODES AND
INSTRUCTION SET

6.1 INTRODUCTION
This chapter is divided into six major sections:
•

Single-Operand Addressing - One part of the instruction word specifies the registers; the other part provides information for locating the operand.

•

Double-Operand Addressing - One part of the instruction word specifies the registers; the
remaining parts provide information for locating two operands.

•

Direct Addressing - The operand is the content of the selected register.

•

Deferred (Indirect) Addressing - The contents of the selected register is the address of the
operand.

•

Use of the PC as a General-Purpose Register - The PC is different from other general-purpose registers in one important respect. Whenever the processor retrieves an instruction, it
automatically advances the PC by 2. By combining this automatic advancement of the PC
with four of the basic addressing modes, we produce the four special PC modes - immediate,
absolute, relative, and relative-deferred.

•

Use of the Stack Pointer as a General-Purpose Register - General-purpose registers can be
used for stack operations.

6.2 ADDRESSING MODES
Data stored in memory must be accessed and manipulated. Data handling is specified by a DCTII-AA
instruction (MOY, ADD, etc.), which usually indicates:

•

The function (operation code).

•

A general-purpose register is to be used when locating the source operand, and/or a generalpurpose register is to be used when locating the destination operand.

•

An addressing mode (for specifying how the selected register(s) is/are to be used).

A large portion of the data handled by a computer is structured (in character strings, arrays, lists, etc.).
The DCTII-AA addressing modes provide for efficient and flexible handling of structured data.

6-1

PRELIMINARY
A general-purpose register may be used with an instruction in any of the following ways.
•

As an accumulator - The data to be manipulated resides in the register.

•

As a pointer - The contents of the register is the address of an operand, rather than the operand itself.

•

As a pointer that automatically steps through memory locations - Automatically stepping
forward through consecutive locations is known as autoincrement addressing; automatically
stepping backwards is known as autodecrement addressing. These modes are particularly useful for processing tabular or array data.

•

As an index register - In this instance, the contents of the register and the word following the
instruction are summed to produce the address of the operand. This allows easy access to
variable entries in a list.

An important DCTII-AA feature, which should be considered with the addressing modes, is the register arrangement.
•
•
•

Six general-purpose registers (RO-RS)
A hardware stack pointer (SP) register (R6)
A program counter (PC) register (R 7)

Registers RO-RS are not dedicated to any specific function; their use is determined by the instruction
that is decoded.
•

They can be used for operand storage. For example, the contents of two registers can be
added and stored in another register.

•

They can contain the address of an operand or serve as pointers to the address of an operand.

•

They can be used for the autoincrement or autodecrement features.

•

They can be used as index registers for convenient data and program access.

The DCTII-AA also has instruction addressing mode combinations that facilitate temporary data storage structures. These can be used for convenient handling of data that must be accessed frequently.
This is known as stack manipulation. The register that keeps track of stack manipulation is known as
the stack pointer (SP). Any register can be used as a stack pointer under program control; however,
certain instructions associated with subroutine linkage and interrupt service automatically use register
R6 as a "hardware stack pointer." For this reason, R6 is frequently referred to as the SP.
•

The stack pointer (SP) keeps track of the latest entry on the stack.

•

The stack pointer moves down as items are added to the stack and moves up as items are
removed. Therefore, the stack pointer always points to the top of the stack.

•

The hardware stack is used during trap or interrupt handling to store information, allowing
the processor to return to the main program.

Register R7 is used by the processor as its program counter (PC). It is recommended that R7 not be
used as a stack pointer or accumulator. Whenever an instruction is fetched from memory, the program
counter is automatically incremented by two to point to the next instruction word.

6-2

PRELIMINARY
6.2.1 Single-Operand Addressing
The instruction format for all single-operand instructions (such as clear, increment, test) is shown in
Figure 6-1.
06

00
Rn

__________________

~A~

__________

OP CODE

DESTINATION ADDRESS
MR-5458

Figure 6-1

Single-Operand Addressing

Bits 15-6 specify the operation code that defines the type of instruction to be executed.
Bits 5-0 form a 6-bit field called the destination address field. The destination address field consists of
two subfields:
•

Bits 0-2 specify which of the 8 general-purpose registers is to be referenced by this instruction word.

•

Bits 3-5 specify how the selected register will be used (in address mode). Bit 3 is set to indicate deferred (indirect) addressing.

6.2.2 Double-Operand Addressing
Operations that imply two operands (such as add, subtract, move, and compare) are handled by instructions that specify two addresses. The first operand is called the source operand; the second is called the
destination operand. Bit assignments in the source and destination address fields may specify different
modes and different registers. The instruction format for the double operand instruction is shown in
Figure 6-2.
15
OP

~ODE

: MODE:

SOURCE ADDRESS

02
Rn

:MODE:
J.

DESTINATION ADDRESS
MR-5459

Figure 6-2

Double-Operand Addressing

The source address field is used to select the source operand (the first operand). The destination is used
similarly, and locates the second operand and the result. For example, the instruction ADD A, B adds
the contents (source operand) of location A to the contents (destination operand) of location B. After
execution, B will contain the result of the addition and the contents of A will be unchanged.

6-3

PRELIMINARY
Examples in this paragraph and the rest of the chapter use the following sample OCTII-AA instructions. (A complete listing of the OCTII-AA instructions appears in Paragraph 6.3.)
Mnemonic

Description

Octal Code

CLR

Clear. (Zero the specified destination.)

005000

CLRB

Clear byte. (Zero the byte in the specified
destination.)

105000

INC

Increment. (Add one to contents of the
destination.)

005200

INCB

Increment byte. (Add one to the contents of
the destination byte.)

105200

COM

Complement. (Replace the contents of the
destination by its logical complement;
each 0 bit is set and each one bit is
cleared.)

005100

COMB

Complement byte. (Replace the contents of
the destination byte by its logical
complement; each 0 bit is set and each
1 bit is cleared.)

105100

AOO

Add. (Add the source operand to the
destination operand and store the result
at the destination a·ddress.)

06SS00

DD = destination field (six bits)
SS = source field (six bits)
= contents of

6.2.3 Direct Addressing
The following summarizes the four basic modes used with direct addressing.
Direct Modes (Figures 6-3 to 6-6)

Mode

Name

Assembler
Syntax

Function

INSTRUCTION

OPERAND
MR-5460

Figure 6-3

Mode 0 Register

6-4

PRELIMINARY

Mode

Name

Assembler
Syntax

Autoincrement

(Rn)+

INSTRUCTION

Function

OPERAND

ADDRESS

L...-_ _ _ _ _~

+2 FOR WORD,
+1 FOR BYTE

MA-5461

Figure 6-4

Mode 2 Autoincrement

Function

Mode

Name

Assembler
Syntax

Autodecrement

-(Rn)

-2 FOR WORD,
-1 FOR BYTE

INSTRUCTION

OPERAND

MA-5462

Figure 6-5

Mode

Name

Assembler
Syntax

Index

X(Rn)

INSTRUCTION

Mode 4 Autodecrement

Function

Value X is added to (Rn) to produce
address of operand. Neither X nor
(Rn) is modified.

ADDRESS
OPERAND

x
MR·5463

Figure 6-6

Mode 6 Index

6-5

PRELIMINARY
6.2.3.1 Register Mode - With register mode any of the general registers may be used as simple accumulators, with the operand contained in the selected register. Since they are hardware registers (within
the processor), the general registers operate at high speeds and provide speed advantages when used for
operating on frequently accessed variables. The assembler interprets and assembles instructions of the
form OPR Rn as register mode operations. Rn represents a general register name or number and OPR
is used to represent a general instruction mnemonic. Assembler syntax requires that a general register
be defined as follows.
RO = %0 (% sign indicates register definition)
Rt"= %1
R2 = %2, etc.
Registers are typically referred to by name as RO, Rl, R2, R3, R4, R5, R6, and R7. However, R6 and
R 7 are also referred to as SP and PC, respectively.
OPRRn
Register Mode Examples (Figures 6-7 to 6-9)
1.

Symbolic

Octal Code

Instruction Name

INCR3

005203

Increment

Operation:

Add one to the contents of general-purpose register R3.
06

15
0

: 0 : 1 : 0 : 1 : 0 : 1 :0 I0

o 1 0

I :
0

00
1

~ -, SELECT

I REGISTER

I
I

DESTINATION FIELD

OP CODE (INC(0052))

RO
R1
R2
R3
R4
R5
R6 (SP)
R7 (PC)

Figure 6-7

INC R3 Increment

6-6

I
-+- J

PRELIMINARY
2.

Symbolic

Octal Code

Instruction Name

ADD R2, R4

060204

Add

Operation:

Add the contents of R2 to the contents of R4.
BEFORE

AFTER

R21

000002

R21

000002

R41

000004

R41

000006
MR-5468

Figure 6-8

ADD R2, R4 Add

Symbolic

Octal Code

Instruction Name

COMBR4

105104

Complement byte

Operation:

1's complement bits 0-7 (byte) in R4. (When general registers are used, byte instructions
operate only on bits 0-7; i.e., byte 0 of the register.)

AFTER

BEFORE
022222

R41

022155
MA-5469

Figure 6-9

COMB R4 Complement Byte

6.2.3.2 Autoincrement Mode [OPR (Rn) + ] - This mode (mode 2) provides for automatic stepping of a
pointer through sequential elements of a table of operands. It assumes the contents of the selected general-purpose register to be the address of the operand. Contents of registers are stepped (by one for
bytes, by two for words, always by two for R6 and R 7) to address the next sequential location. The
autoincrement mode is especially useful for array processing and stack processing. It will access an
element of a table and then step the pointer to address the next operand in the table. Although most
useful for table handling, this mode is completely general and may be used for a variety of purposes.
OPR (Rn)+
Autoincrement Mode Examples (Figures 6-10 to 6-12)

Symbolic

Octal Code

Instruction'Name

CLR (R5)+

005025

Clear

Operation:

Use contents of R5 as the address of the operand. Clear selected operand and then increment the contents of R5 by two.

6-7

PRELIMINARY
AFTE~

BEFORE

20000

ADDRESS SPACE

005025

R5 L--_-.-_..J

ADDRESS SPACE

20000

30000

005025

R5 1

030002

000000
MR-5464

Figure 6-10

CLR (RS)+ Clear

Symbolic

Octal Code

Instruction Name

CLRB (R5)+

105025

Clear byte

Operation:

Use contents of R5 as the address of the operand. Clear selected byte operand and then
increment the contents of R5 by one.
BEFORE

AFTER

ADDRESS SPACE

20000

105025

R51

030000

ADDRESS SPACE

20000 1

105025

030001

I
t
30000111116

30000~

30002

30002~
MR-5465

Figure 6-11

CLRB (R5)+ Clear Byte

Symbolic

Octal Code

Instruction Name

ADD (R2)+,R4

062204

Add

Operation:

The contents of R2 are used as the address of the operand, which is added to the contents
of R4. R2 is then incremented by two.
BEFORE

AFTER

ADDRESS SPACE

10000 1

062204

ADDRESS SPACES
R2 L--_-.-_..J

1000021

10000 1

062204

010000

100002 1

Figure 6-12

010000

ADD (R2)+ R4 Add

6-8

REGISTERS

R2 1

100004

R41

020000

PRELIMINARY
6.2.3.3 Autodecrement Mode [OPR-(Rn)] - This mode (mode 4) is useful for processing data in a list
in reverse direction. The contents of the selected general-purpose register are decremented (by two for
word instructions, by one for byte instructions) and then used as the address of the operand. The choice
of postincrement, predecrement features for the DCTII-AA were not arbitrary decisions, but were intended to facilitate hardware/software stack operations.

OPR-(Rn)
Autodecrement Mode Examples (Figures 6-13 to 6-15)
1.

Symbolic

Octal Code

Instruction Name

INC -(RO)

005240

Increment

Operation:

The contents of RO are decremented by two and used as the address of the operand. The
operand is incremented by one.
AFTER

BEFORE
ADDRESS SPACE

1000

17774

ADDRESS SPACE

REGISTERS

005240

017776

000000

1000

17774

I.
I

005240

'---r----'

000001
MR-5466

Figure 6-13

INC -(RO) Increment

Symbolic

Octal Code

Instruction Name

INCB -(RO)

105240

Increment byte

Operation:

The contents of RO are decremented by one and then used as the address of the operand.
The operand byte is increased by one.
BEFORE

AFTER

ADDRESS SPACE

1000

105240

ADDRESS SPACE

017776

1000

105240

+
17774E8

17774

17776

o=J

017775

001 I 000

MA·5471

Figure 6-14

INCB -(RO) Increment Byte

6-9

PRELIMINARY
3.

Symbolic

Octal Code

Instruction Name

ADD -(R3),RO

064300

Add

Operation:

The contents of R3 are decremented by two and then used as a pointer to an operand
(source), which is added to the contents of RO (destination operand).
BEFORE

AFTER
REGISTER

ADDRESS SPACE

10020

064300

R31

ADDRESS SPACE

000020

10020

064300

077776

R31

0000070

077774

.t=j

77774~

77774

77776

c=J

000050

MR·5472

Figure 6-15

ADD -(R3), RO Add

6.2.3.4 Index Mode [OPR X(Rn)] - In this mode (mode 6) the contents of the selected general-purpose
register, and an index word following the instruction word, are summed to form the address of the operand. The contents of the selected register may be used as a base for calculating a series of addresses,
thus allowing random access to elements of data structures. The selected register can then be modified
by program to access data in the table. Index addressing instructions are of the form OPR X(Rn),
where X is the indexed word located in the memory location following the instruction word and Rn is
the selected general-purpose register.
OPR X(Rn)
Index Mode Examples (Figures 6-16 to 6-18)
1.

Symbolic

Octal Code

Instruction Name

CLR 200(R4)

005064
000200

Clear

Operation:

The address of the operand is determined by adding 200 to the contents of R4. The operand location is then cleared.

6-10

PRELIMINARY
BEFORE
ADDRESS SPACE
1020

005064

1022

000200

001000

1024

1200
1202

1000
+200
1200

005064

1022

000200

001000

MA·5473

CLR 200 (R4) Clear

Octal Code

Instruction Name

COMB 200(Rl)

105161
000200

Complement byte

The contents of a location, which are determined by adding 200 to the contents of Rl, are
l's complemented (i.e., logically complemented).
BEFORE
ADDRESS SPACE
1020

105161

1022

000200

20176
20200

AFTER
ADDRESS SPACE

IO~, !~ I
Figure 6-17

017777

1020

105161

1022

000200

017777

017777
+200
020177
20176
20200

ffi

MR-5474

COMB 200 (Rl) Complement Byte

Symbolic

Octal Code

Instruction Name

ADD 30(R2),20(R5)

066265
000030
000020

Add

Operation:

1024

Symbolic

Operation:

1020

1200

Figure 6-16

AFTER
ADDRESS SPACE

The contents of a location, which are determined by adding 30 to the contents of R2, are
added to the contents of a location that is determined by adding 20 to the contents of R5.
The result is stored at the destination address, that is, 20(R5).

6-11

PRELI~INARY
BEFORE
ADDRESS SPACE
R2

AFTER
ADDRESS SPACE

001100

1020

066265

1022

000030

1024

000020

1020

066265

1022

000030

1024

000020

1130

000001

1130

000001

2020

000001

2020

000002

002000

001100

002000

1100 2000
+30 +20
1130 2020
MR-5475

Figure 6-18

ADD 30 (R2), 20 (R5) Add

6.2.4 Deferred (Indirect) Addressing
The four basic modes may also be used with deferred addressing. Whereas in register mode the operand
is the contents of the selected register, in register-deferred mode the contents of the selected register is
the address of the operand.
In the three other deferred modes, the contents of the register select the address of the operand rather
than the operand itself. These modes are therefore used when a table consists of addresses rather than
operands. The assembler syntax for indicating deferred addressing is ® [or 0 when this is not ambiguous]. The following summarizes the deferred versions of the basic modes.

Deferred Modes (Figures 6-19 to 6-22)

Mode

Name

Assembler
Syntax

Registerdeferred

@Rn or (Rn)

INSTRUCTION

Function

ADDRESS

OPERAND
MA-5476

Figure 6-19

Mode 1 Register-Deferred

6-12

PRELIMINARY

Mode

Name

Assembler
Syntax

AutoincrementDeferred

@(Rn) +

INSTRUCTION

Function

Register is first used as a pointer to a
word containing the address of the operand and then incremented (always
by two, even for byte instructions).

ADDRESS

OPERAND

MR-5477

Figure 6-20

Mode 3 Autoincrement-Deferred

Mode

Name

Assembler
Syntax

Autodecrementdeferred

@-(Rn)

Function

Register is decremented (always by
two, even for byte instructions) and
then used as a pointer to a word containing the address of the operand.

-2

INSTRUCTION

ADDRESS

OPERAND

MR-5478

Figure 6-21

Mode 5 Autodecrement-Deferred

Mode

Name

Assembler
Syntax

Index-deferred

@X(Rn)

Function
Value X (stored in a word following
the instruction) and (Rn) are added;
the sum is used as a pointer to a word
containing the address of the operand.
Neither X nor (Rn) is modified.

6-13

PRELIMINARY
INSTRUCTION

ADDRESS
ADDRESS

OPERAND

x
MR-5479

Figure 6-22

Mode 7 Index-Deferred

The following examples illustrate the deferred modes.
Register-Deferred Mode Example (Figure 6-23)
Symbolic

Octal Code

Instruction Name

CLR@R5

005015

Clear

Operation:

The contents of location specified in R5 are cleared.
BEFORE

AFTER

ADDRESS SPACE
1677
1700

001700

ADDRESS SPACE
1677
1700

Figure 6-23

001700

MR·6480

CLR @ R5 Clear

Autoincrement-Deferred Mode Example (Mode 3) (Figure 6-24)
Symbolic

Octal Code

Instruction Name

INC@(R2)+

005232

Increment

Operation:

The contents of R2 are used as the address of the address of the operand. The operand is
increased by one; the contents of R2 are incremented by two.
AFTER

BEFORE

1010
1012

10000

§g

ADDRESS SPACE

ADDRESS SPACE
R2
1010
1012

§3

010302

~
MA·5481

Figure 6-24

INC @ (R2) + Increment

6-14

PRELIMINARY
Autodecrement-Deferred Mode Example (Mode 5) (Figure 6-25)
Symbolic

Octal Code

COM@-(RO)

005150

Operation:

The contents of RO are decremented by two and then used as the address of the address
of the operand. The operand is 1's complemented (i.e., logically complemented).
BEFORE

AFTER

ADDRESS SPACE
10100
10102

10774
10776

ADDRESS SPACE

B
t=J

010776

10100
10102

10774
10776

MR-5482

Figure 6-25

COM @ (RO) Complement

Index-Deferred Mode Example (Mode 7) (Figure 6-26)
Symbolic

Octal Code

Instruction Name

ADD @1000(R2),Rl

067201
001000

Add

Operation:

1000 and the contents of R2 are summed to produce the address of the address of the
source operand, the contents of which are added to the contents of R 1; the result is stored
in Rl.
BEFORE
ADDRESS SPACE
1020

067201

1022

001000

AFTER
REGISTER

001234

000100

1024

'"
1050

1020

067201

1022

001000

r=g

R2
1024

1050

1100

ADDRESS SPACE

1100
1000
+100
1100

001236

000100

B
B
MR·5483

Figure 6-26

ADD @ 1000 (R2), Rl Add

6-15

PRELIMINARY
6.2.5 Use of the PC as a General-Purpose Register
Although register 7 is a general-purpose register, it doubles in function as the program counter for the
DCTII-AA. Whenever the processor uses the program counter to acquire a word from memory, the
program counter is automatically incremented by two to contain the address of the next word of the
instruction being executed or the address of the next instruction to be executed. (When the program
uses the PC to locate byte data, the PC is still incremented by two.)
The PC responds to ail the standard DCTlI-AA addressing modes. However, with four of these modes
the PC can provide advantages for handling position-independent code and unstructured data. When
utilizing the PC, these modes are termed immediate, absolute (or immediate-deferred), relative, and
relative-deferred. The modes are summarized below.

Mode

Name

Assembler
Syntax

Function

Immediate

Operand follows instruction.

Absolute

@#A

Absolute address of operand follows
instruction.

Relative

Relative address (index value) follows
the instruction.

Relativedeferred

Index value (stored in the word after
the instruction) is the relative address
for the address of the operand.

When a standard program is available for different users, it is often helpful to be able to load it into
different areas of memory and run it in those areas. The DCTII-AA can accomplish the relocation of a
program very efficiently through the use of position-independent code (PIC), which is written by using
the PC addressing modes. If an instruction and its operands are moved in such a way that the relative
distance between them is not altered, the same offset relative to the PC can be used in all positions in
memory. Thus, PIC usually references locations relative to the current location.
The PC also greatly facilitates the handling of unstructured data. This is particularly true of the immediate and relative modes.
6.2.5.1 Immediate Mode [OPR #n,DD] - Immediate mode (mode 2) is equivalent in use to the autoincrement mode with the Pc. It provides time improvements for accessing constant operands by including the constant in the memory location immediately following the instruction word.
OPR #n.DD
Immediate Mode Example (Figure 6-27)
Symbolic

Octal Code

Instruction Name

ADD #IO,RO

062700
000010

Add

6-16

PRELIMINARY
Operation:

The value lOis located in the second word of the instruction and is added to the contents
of RO. Just before this instruction is fetched and executed, the PC points to the first word
of the instruction. The processor fetches the first word and increments the PC by two.
The source operand mode is 27 (autoincrement the PC). Thus, the PC is used as a pointer
to fetch the operand (the second word of the instruction) before it is incremented by two
.
to point to the next instruction.
AFTER

BEFORE
ADDRESS SPACE
1020
1022

1--_06_2_70_0--1' RO
000010

ADDRESS SPACE

000020

""-pc

1024

1020

062700

1022

000010

1024

000030

MR·5484

Figure 6~27

ADD # 10, RO Add

6.2.5.2 Absolute Addressing [OPR @#A] - This mode (mode 3) is the equivalent of immediate-deferred or autoincrement-deferred using the Pc. The contents of the location following the instruction
are taken as the address of the operand. Immediate data is interpreted as an absolute address (i.e., an
address that remains constant no matter where in memory the assembled' instruction is executed).
OPR@#A
Absolute Mode Examples (Figures 6-28 and 6-29)
1.

Symbolic

Octal Code

Instruction Name

CLR @#IIOO

005037
001100

Clear

Operation:

Clear the contents of location 1100.
AFTER

BEFORE

ADDRESS SPACE

ADDRESS SPACE
20

005037

001100

005037

20
PC

1--_00_1_10_°--iVPC

1100

1102

1102
MA-5485

Figure 6-28

CLR ® # 1100 Clear

6-17

PRELIMINARY
2.

Symbolic

Octal Code

Instruction Name

ADD @#2000,R3

063703
002000

Add

Operation:

Add contents of location 2000 to R3.
AFTER

BEFORE
ADDRESS SPACE
20

063703

002000

ADDRESS SPACE

000500

•

063703

002000

001000

MR-5486

Figure 6-29

ADD @ # 2000 Add

6.2.5.3 Relative Addressing [OPR A or OPR X(PC)] - This mode (mode 6) is assembled as index mode
using R 7. The base of the address calculation, which is stored in the second or third word of the instruction, is not the address of the operand, but the number which, when added to the (PC), becomes the
address of the operand. This mode is useful for writing position-independent code since the location
referenced is always fixed relative to the PC. When instructions are to be relocated, the operand is
moved by the same amount.
.
OPR A or OPR X(PC) (X is the location of A relative to the instruction)
Relative Addressing Example (Figure 6-30)
Symbolic

Octal Code

Instruction Name

INC A

005267
000054

Increment

Operation:

To increment location A, contents of memory location immediately following instruction
word are added to (PC) to produce address A. Contents of A are increased by one.

6-18

PRELIMINARY
BEFORE
ADDRESS SPACE
1020

005267

1022

000054

AFTER
ADDRESS SPACE

1020

0005267

1022

000054

1024

1026

1100

000000

1100

1024

~ PC

000001

ffi4

~-------------------1100
MR-5481

Figure 6-30

INC A Increment

6.2.5.4 Relative-Deferred Addressing [OPR @A or OPR @X(PC)] - This mode (mode 7) is similar to
relative mode, except that the second word of the instruction, when added to the PC, contains the address of the address of the operand, rather than the address of the operand.
OPR @A or OPR @X(PC) (X is the location containing the address of A, relative to the instruction)
Relative-Deferred Mode Example (Figure 6-31)
Symbolic

Octal Code

Instruction Name

CLR@A

005077
000020

Clear

Operation:

Add second word of instruction to updated PC to produce address of address of operand.
Clear operand.
BEFORE
ADDRESS SPACE
(PC = 1020) 1020
1022

005077

AFTER
ADDRESS SPACE
1020

'-"-00-0-02-0--1

1022
1024
+20

(PC = 1022) 1024

005077
t--_000
__
02_°---iVC

1024

,~------------------1~4

'~
10100

100001

1~4

010100

10100

000000 ]
MR-5488

Figure 6-31

CLR @ A Clear

6-19

PRELIMINARY
6.2.6

Use of the Stack Pointer as a General-Purpose Register

The processor stack pointer (SP, register 6) is in most cases the general register used for the stack
operations related to program nesting. Autodecrement with register 6 "pushes" data onto the stack and
autoincrement with register 6 "pops" data off the stack. Since the SP is used by the processor for interrupt handling, it has a special attribute: autoincrements and autodecrements are always done in steps of
two. Byte operations using the SP in this way leave odd addresses unmodified.

6.3

INSTRUCTION SET

Thc rcst of this chapter describes the DCTII-AA's instruction set. Each instruction's explanation includes the instruction's mnemonic, octal code, binary code, a diagram showing the format of the instruction, a symbolic notation describing its execution and effect on the condition codes, a description,
special comments, and examples.
Each instruction's explanation is headed by its mnemonic. When the word instruction has a byte equivalent, the byte mnemonic also appears.
The diagram that accompanies each instruction shows the octal op code, binary op code, and bit assignments. [Notc that in byte instructions the most significant bit (bit 15) is always a one.]
Symbols:

o = contents of
SS or src = source address
DD or dst = destination address
loc = location
<-

= becomes
"is popped from stack"

1 = "is pushed onto stack"
1\

boolean AND

boolean OR

exclusive OR
boolean not

REG or R = register
B = Byte

• = 0 for word, I for byte
, = concatenated

6-20

PRELIMINARY
6.3.1 Instruction Formats
The following formats include all instructions used in the DCT II-AA. Refer to individual instructions
for more detailed information.

Single-Operand Group:
(Figure 6-32)

CLR, CLRB, COM, COMB, INC, INCB, DEC, DECB, NEG,
NEGB, ADC, ADCB, SBC, SBCB, TST, TSTB, ROR, RORB,
ROL, ROLB, ASR, ASRB, ASL, ASLB, JMP, SWAB, MFPS,
MTPS, SXT, XOR
06

MA-5191

Figure 6-32

Double-Operand Group:
(Figure 6-33)
15

Single-Operand Group

BIT, BITB, BIC, BICB, BIS, BISB, ADD, SUB, MOV, MOVB,
CMP, CMPB
06

: : ~D

:
MR-5192

Figure 6-33

Double-Operand Group

Program Control Group:
a.

Branch (all branch instructions) (Figure 6-34)
08

MR·5193

Figure 6-34

b.
15

Program Control Group Branch

Jump to Subroutine (JSR) (Figure 6-35)
09

05
:

00
:
MR-5194

Figure 6-35

Program Control Group JSR

6-21

PRELIMINARY
c.

Subroutine Return (RTS) (Figure 6-36)
03

02
R

MA-5195

Figure 6-36

Program Control Group RTS

Traps (breakpoint, lOT, EMT, TRAP, BPT) (Figure 6-37)

15
OP

C~DE

MR-5196

Figure 6-37

Program Control Group Traps

Subtract 1 and Branch (if = 0) (SOB) (Figure 6-38)
09

MR-5197

Figure 6-38

Program Control Group Subtract

Operate Group: HALT, WAIT, RTI, RESET, RTT, NOP, MFPT (Figure 6-39)
00

MA-5198

Figur.e 6-39

Operate Group

Condition Code Operators (all condition code instructions) (Figure 6-40)
06

011

I I I Iz I I
N

MR·5199

Figure 6-40

Condition Group

6-22

PRELIMINARY
Byte Instructions
The OCTII-AA includes a full complement of instructions that manipulate byte operands. Since all
OCT I I-AA addressing is byte-oriented, byte manipulation addressing is straightforward. Byte instructions with autoincrement or autodecrement direct addressing cause the specified register to be modified
by one to point to the next byte of data. Byte operations in register mode access the low-order byte of
the specified register. These provisions enable the OCTII-AA to perform as either a word or byte processor. The numbering scheme for word and byte addresses in memory is shown in Figure 6-41.
WORD OR BYTE
ADDRESS

HIGH BYTE
ADDRESS

002001

BYTE 1

BYTE 0

002000

002003

BYTE 3

BYTE 2

002002

MR-5201

Figure 6-41

Byte Instructions

The most significant bit (bit IS) of the instruction word is set to indicate a byte instruction.

Example:

Symbolic

Octal Code

Instruction Name

CLR
CLRB

0050DO
l050DD

Clear word
Clear byte

6-23

PRELIMINARY
6.3.2 List of Instructions
The following is a list of the OCT 1 I-AA instruction set.
SINGLE-OPERAND
General
Mnemonic

Instruction

OpCode

CLR(B)
COM(B)
INC(B)
OEC(B)
NEG(B)
TST(B)

Clear destination
Complement destination
Increment destination
Oecrement destination
Negate destination
Test destination

.05000
.05100
.05200
.05300
.05400
.05700

Mnemonic

Instruction

Op Code

ASR(B)
ASL(B)
ROR(B)
ROL(B)
SWAB

Arithmetic shift right
Arithmetic shift left
Rotate right
Rotate left
Swap bytes

.06200
.06300
.06000
.06100
000300

Mnemonic

Instruction

Op Code

AOC(B)
SBC(B)
SXT

Add carry
Subtract carry
Sign extend

.05500
.05600
006700

Mnemonic

Instruction

OpCode

MFPS
MTPS

Move byte from PS
Move byte to PS

Shift and Rotate

M ultiple-Precision

PS Word Operators

106700
1064SS

DOUBLE-OPERAND
General
Mnemonic

Instruction

Op Code

MOY(B)
CMP(B)
AOO
SUB

Move source to destination
Compare source to destination
Add source to destination
Subtract source from destination

.ISSOO
.2SS00
06SS00
16SS00

6-24

PRELIMINARY
Logical
Mnemonic

Instruction

OpCode

BIT(B)
BIC(B)
BIS(B)
XOR

Bit test
Bit clear
Bit set
Exclusive OR

.3SSDD
.4SSDD
.5SSDD
074RDD

PROGRAM CONTROL
Branch
Mnemonic

Instruction

BR
BNE
BEQ
BPL
BMI

Branch (unconditional)
Branch if not equal (to zero)
Branch if equal (to zero)
Branch if plus
Branch if minus
Branch if overflow is clear
Branch if overflow is set
Branch if carry is clear
Branch if carry is set

Bye
BYS

Bee
Bes

Op Code or Base Code

000400
001000
001400
100000
100400
102000
102400
103000
103400

Signed Conditional Branch
Mnemonic

Instruction

BGE
BLT
BGT
BLE

Branch if greater than or equal (to zero)
Branch if less than (zero)
Branch if greater than (zero)
Branch if less than or equal (to zero)

Op Code or Base Code

002000
002400
003000
003400

Unsigned Conditional Branch
Mnemonic

Instruction

BHI
BLOS
BHIS
BLO

Branch if higher
Branch if lower or same
Branch if higher or same
Branch if lower

Op Code or Base Code

101000
101400
103000
103400

Jump and Subroutine
Op Code or Base Code

Mnemonic

Instruction

JMP
JSR

Jump
Jump to subroutine
Return from subroutine
Subtract one and branch (if =1= 0)

RTS
SOB

6-25

0001DD
004RDD
00020R
077 ROO

PRELIMINARY
Trap and Interrupt
Mnemonic

Instruction

EMT
TRAP
BPT
lOT
RTI
RTT

Emulator trap
Trap
Breakpoint trap
Input/output trap
Return from interrupt
Return from interrupt

Op Code or Base Code
104000-104377
104400-104777
000003
000004
000002
000006

MISCELLANEOUS
Mnemonic

Instruction

HALT
WAIT
RESET
MFPT

Halt
Wait for interrupt
Reset external bus
Move processor type

Op Code or Base Code
000000
000001
000005
000007

RESERVED INSTRUCTIONS
00021R
00022R

CONDITION CODE OPERATORS
Mnemonic

Instruction

CLC
CLY
CLZ
CLN
CCC
SEC
SEV
SEZ
SEN
SCC
NOP

Clear C
Clear Y
Clear Z
Clear N
Clear all CC bits
Set C
Set Y
Set Z
Set N
Set all CC bits
No operation

Op Code or Base Code
000241
000242
000244
000250
000257
000261
000262
000264
000270
000277
000240

6-26

PRELIMINARY
6.3.3

Single-Operand Instructions
NOTE
In all DCTll-AA instructions a write operation
(which in 8-bit mode consists of two adjacent and indivisible write transactions) to a memory location or
register is always preceded by a read operation from
the same location. The exceptions are when writing
the PC and PSW to the stack in two cases:

6.3.3.1

During the execution of the microcode preceding an interrupt or trap service routine.

In interrupt and trap instructions (HLT,
TRAP, BPT, lOT).

General

CLR
CLRB
CLEAR DESTINATION

-05000
06

MR·5202

Operation:

(dst) <- 0

Condition Codes:

N: cleared
Z: set
V: cleared
C: cleared

Description:

Word: The contents of the specified destination are replaced with Os.
Byte: Same.

Example:

CLR RI
Before

After

(RI) = 177777

(RI) = 000000

NZVC
1111

NZVC
0100

6-27

PRELIMINARY

COM
COMB
COMPLEMENT OST

-051 DO

15
011 :

o : o : o :

:o:

:o: o: I

:d : d : d : d : d

MR-5203

Operation:

(dst) < - - - (dst)

Condition Codes:

N: set if most significant bit of result is set; cleared otherwise
Z: set if result is 0; cleared otherwise
V: cleared
C: set

Description:

Word: Replaces the contents of the destination address by their logical complement. (Each bit equal to 0 is set and each bit equal to 1 is cleared.)
Byte: Same.

Example:

COM RO
Before

After

(RO) = 013333

(RO) =

NZVC
0110

NZVC
1001

164444

INC
INCB
-05200

INCREMENT OST

15
011:

MA-5204

Operation:

(dst) < - (dst) +

Condition Codes:

N: set if result is < 0; cleared otherwise
Z: set if result is 0; cleared otherwise
V: set if (dst) held 077777; cleared otherwise
C: not affected

Description:

Word: Add I to the contents of the destination.
Byte: Same.

6-28

PRELIMINARY
INC R2

Example:

Before

After

(R2) = 000333

(R2) = 000334

NZVC

0000

DEC
DECB
DECREMENT DST
15

MR-S205

Operation:

(dst) <- (dst) -

Condition Codes:

N: set if result is < 0; cleared otherwise
Z: set if result is 0; cleared otherwise
V: set if (dst) was 100000; cleared otherwise
C: not affected

Description:

Word: Subtract 1 from the contents of the destination.
Byte: Same.

Example:

DEC R5
Before

After

(R5) = 000001

(R5) = 000000

NZVC

1000

0100

NEG
NEGB
NEGATE DST

-054DD

0/1 :

o : o : o :

: o :

: :

: : :
d

MR·5206

6-29

PRELIMINARY
(dst)

Operation:

(dst) <- -

Condition Codes:

N: set if result is < 0; cleared otherwise
Z: set if result is 0; cleared otherwise
V: set if result is 100000; cleared otherwise
C: cleared if result is 0; set otherwise

Description:

Word: Replaces the contents of the destination address by its 2's complement.
Note that 100000 is replaced by itself. (In 2's complement notation the most negative number has no positive counterpart.)
Byte: Same.

Example:

NEG RO
Before

After

(RO) = 000010

(RO) = 177770

NZVC
0000

NZVC
1001

TST
TSTB
TEST OST

-05700
06

0/1 :

o : o : o :

1 :

o :

1 :

05
d

00
:

d :

MR-S207

Operation:

(dst) <- (dst)

Condition Codes:

N: set if result is < 0; cleared otherwise
Z: set if result is 0; cleared otherwise
V: cleared
C: cleared

Description:

Word: Sets the condition codes Nand Z according to the contents of the destination address; the contents of dst remain unmodified.
Byte: Same.

Example:

TST Rl
Before

After

(RI) = 012340

NZVC
0011

NZVC
0000

6-30

PRELIMINARY
6.3.3.2

Shifts and Rotates - Scaling data by factors of two is accomplished by the shift instructions:

ASR - Arithmetic shift right
ASL - Arithmetic shift left
The sign bit (bit 15) of the operand is reproduced in shifts to the right. The low-order bit is filled with
Os in shifts to the left. Bits shifted out of the C bit, as shown in the following instructions, are lost.
The rotate instructions operate on the destination word and the C bit as though they formed a 17-bit
"circular buffer." These instructions facilitate sequential bit testing and detailed bit manipulation.

ASR
ASRB
ARITHMETIC SHIFT RIGHT

-06200

0/<

06
0

0
MR·5208

Operation:

(dst) +- (dst) shifted one place to the right

Condition Codes:

N: set if high-order bit of result is set (result < 0); cleared otherwise
Z: set if result = 0; cleared otherwise
V: loaded from exclusive OR of N bit and C bit (as set by the completion of the
shift operation)
C: loaded from low-order bit of destination

Description:

Word: Shifts all bits of the destination right one place. Bit 15 is reproduced. The
C bit is loaded from bit 0 of the destination. ASR performs signed division of the
destination by 2.
Byte: Same.

Example:

BYTE:

ODD ADDRESS

: rD L.r-'--T:-----,---,.:----.:-.,..---,~I__D
08

' - 07

6-31

EVEN ADDRESS

PRELIMINARY

ASL
ASLB
ARITHMETIC SHIFT LEFT

-063DD
06

15
0/1:

05
d

MA·5210

Operation:

(dst) <- (dst) shifted one place to the left

Condition Codes:

N: set if high-order bit of result is set (result < 0); cleared otherwise
Z: set if result = 0; cleared otherwise
V: loaded with exclusive OR of N bit and C bit (as set by the completion of the
shift operation)
C: loaded with high-order bit of destination

Description:

Word: Shifts all bits of the destination left one place. Bit 0 is loaded with a O. The
C bit of the status word is loaded from the most significant bit of the destination.
ASL performs a signed multiplication of the destination by 2 with overflow indication.
Byte: Same.

Example:
WORD:

BYTE:

MR·5211

ROR
RORB
ROTATE RIGHT

-060DD
06

15
0/1

: 0

: 1

: 0

: d

MR-5212

6-32

PRELIMINARY
Operation:

(dst) <- (dst) rotate right one place

Condition Codes:

N: set if high-order bit of result is set (result < 0); cleared otherwise
Z: set if all bits of result = 0; cleared otherwise
V: loaded with exclusive OR of N bit and C bit (as set by the completion of the
rotate operation)
C: loaded with low-order bit of destination

Description:

Word: Rotates all bits of the destination right one place. Bit 0 is loaded into the C
bit and the previous contents of the C bit are loaded into bit 15 of the destination.
Byte: Same.

Example:
WORD:

BYTE:

+r------1D~-----,

EV:EN

MR~5213

ROL
ROLB
ROTATE LEFT

-061DD

0/1:

15
0

: a

: 0

: 1

: 0

: a

: 0

: 1

00
:

MA·5214

Operation:

(dst) <- (dst) rotate left one place

Condition Codes:

N: set if high-order bit of result word is set (result < 0); cleared otherwise
Z: set if all bits of result word = 0; cleared otherwise
V: loaded with exclusive OR of the N bit and C bit (as set by the completion of
the rotate operation)
C: loaded with high-order bit of destination

6-33

PRELIMINARY
Word: Rotates all bits of the destination left one place. Bit 15 is loaded into the C
bit of the status word and the previous contents of the C bit are loaded into bit 0
of the destination.
Byte: Same.

Description:

Example:

WORD:

OST

~I~~~~~~~~~
BYTE:

r---------~~~----------~

~[]
07

) I

E~EN
MR·5215

SWAB
SWAP BYTES

000300

MA-5216

Operation:

byte l/byte 0 <- byte O/byte 1

Condition Codes:

N: set if high-order bit of low-order byte (bit 7) of result is set; cleared otherwise
Z: set if low-order byte of result = 0; cleared otherwise
V: cleared
C: cleared

Description:

Exchanges high-order byte and low-order byte of the destination word. (The destination must be a word address.)

Example:

SWAB R 1
Before

After

(Rl) = 077777

(Rl) = 177577

NZVC
1111

NZVC
0000

6-34

PRELIMINARY
6.3.3.3 Multiple-Precision - It is sometimes necessary to do arithmetic operations on operands considered as multiple words or bytes. The DCTII-AA makes special provision for such operations with the
instructions ADC (add carry) and SBC (subtract carry) and their byte equivalents.
For example, two 16-bit words may be combined into a 32-bit double-precision word and added or subtracted as shown below.
32-BIT WORD

.-.

(
31

)

I I

OPERANDI

(~------------------------------~-----------------------------~1
31

OPERANDI~

_ _ _ _ _ _ _ _ _B_1____________

~15~

~1 ~I

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---;;O

_____________

BO___________

RESULTI

I
MR-5217

Example:
The addition of - 1 and - 1 could be performed as follows.
- 1 = 37777777777
(R I) = 177777
ADD
ADC
ADD
l.
2.
3.
4.

(R2) = 177777

(R3) = 177777

(R4) = 177777

Rl,R2
R3
R4,R3

After (R 1) and (R2) are added, 1 is loaded into the C bit.
The ADC instruction adds the C bit to (R3); (R3) = O.
The (R3) and (R4) are added.
The result is 37777777776, or - 2.

6-35

PRELIMINARY

ADC
ADCB
ADD CARRY

-05500

15
0/1:

06
0

05
d

00
:

MR·5218

Operation:

(dst) < - (dst) + (C bit)

Condition Codes:

N: set if result < 0; cleared otherwise
Z: set if result = 0; cleared otherwise
V: set if (dst) was 077777 and (C) was I; cleared otherwise
C: set if (dst) was 177777 and (C) was I; cleared otherwise

Description:

Word: Adds the contents of the C bit to the destination. This permits the carry
from the addition of the low-order words to be carried to the high-order result.
Byte: Same.

Example:

Double-precision addition may be done with the following instruction sequence.
ADD
ADC
ADD

AO,BO
BI
AI,Bl

;add low-order parts
;add carry into high-order
;add high-order parts

SBC
SBCB
SUBTRACT CARRY

-05600
12

Operation:

(dst) <- (dst) - (C)

Condition Codes:

N: set if result < 0; cleared otherwise
Z: set if result = 0; cleared otherwise
V: set if (dst) was 100000; cleared otherwise
C: set if (dst) was 0 and C was 1; cleared otherwise

Description:

Word: Subtracts the contents of the C bit from the destination. This permits the
carry from the subtraction of two low-order words to be subtracted from the highorder part of the result.
Byte: Same.

6-36

PRELIMINARY
Example:

Double-precision subtraction is done by:
SUB
SBC
SUB

AO,BO
B1
AI,BI

SXT
006700

SIGN EXTENO

MR-5220

Operation:

(dst) <- 0 if N bit is clear
(dst) ~ I if N bit is set

Condition Codes:

N: not affected
Z: set if N bit is clear
V: cleared
C: not affected

Description:

If the condition code bit N is set, a - I is placed in the destination operand; if the
N bit is clear, a 0 is placed in the destination operand. This instruction is particularly useful in multiple-precision arithmetic because it permits the sign to be extended through multiple words.

Example:

SXT A

6.3.3.4

Before

After

(A) = 012345

(A) = 177777

NZVC
1000

PS Word Operators

MFPS
MOVE BYTE FROM PROCESSOR STATUSWORO

106700
08

I : : : : : :
1

MA-5221

6-37

PRELIMINARY
Operation:

(dst) <- PS
dst lower 8 bits

Condition Codes:

N: set if PS <7> = 1; cleared otherwise
Z: set if PS <7:0> = 0; cleared otherwise
V: cleared
C: not affected

Description:

The 8-bitcontents of the PS are moved to the effective destination. If the destination is mode 0, PS bit 7 is sign-extended through the upper byte of the register.
The destination operand address is treated as a byte address.

Example:

MFPS RO
Before

After

RO [0]
PS [000014]

RO [000014]
PS [000000]

MTPS
1064SS

MOVE BYTE TO PROCESSOR STATUS WORD
08

I :
1

MR-5222

Operation:

PS <- (src)

Condition Codes:

Set according to effective SRC operand bits <3:0>

Description:

The eight bits of the effective operand replace the current contents of the PS. The
source operand address is treated as a byte address. Note: The T bit (PS bit 4)
cannot be set with this instruction. The SRC operand remains unchanged. This
instruction can be used to change the priority bits (PS bits <7:5» in the PS.

Example:

MTPS Rl
Before

After

(R 1) = 000777
(PS) = XXXOOO

(Rl) = 000777
(PS) = XXX357

NZVC
0000

NZVC
1111

6-38

PRELIMINARY
6.3.4 Double-Operand Instructions
Double-operand instructions save instructions (and time) since they eliminate the need for "load" and
"save" sequences such as those used in accumulator-oriented machines.

6.3.4.1

General

MOV
MOVB
.1SSDD

MOVE SOURCE TO DESTINATION
15
011:

12
0

I : :
5

5
:

00
:

MR-5223

Operation:

(dst) <- (src)

Condition Codes:

N: set if (src) < 0; cleared otherwise
Z: set if (src) = 0; cleared otherwise
Y: cleared
C: not affected

Description:

Word: Moves the source operand to the destination location. The previous contents of the destination are lost. Contents of the source address are not affected.
Byte: Same as MOY. The MOYB to a register (unique among byte instructions)
extends the most significant bit of the low-order byte (sign extension). Otherwise,
MOYB operates on bytes exactly as MOV operates on words.

Example:

MOY XXX,Rl

;loads register 1 with the contents of memory location; XXX represents a programmer-defined
mnemonic used to represent a memory location

MOY #20,RO

;loads the number 20 into register 0; # indicates
that the value 20 is the operand

MOY @#20, - (R6)

;pushes the operand contained in location 20 onto
the stack

MOY (R6) + ,@#177566

;pops the operand off a stack and moves it into
memory location 177566 (terminal print buffer)

MOY RI,R3

;performs an inter-register transfer

MOYB @#177562,@#177566

;moves a character from the terminal keyboard
buffer to the terminal printer buffer

6-39

PRELIMINARY

CMP
CMPB
COMPARE SRC TO DST
12

011:

-2SSDD
11

MR·5224

Operation:

(src) - (dst)

Condition Codes:

N: set if result < 0; cleared otherwise
Z: set if result = 0; cleared otherwise
V: set if there was arithmetic overflow; that is, operands were of opposite signs
and the sign of the destination was the same as the sign of the result; cleared
otherwise
C: cleared if there was a carry from the result's most significant bit; set otherwise

Descri ption:

Compares the source and destination operands and sets the condition codes, which
may then be used for arithmetic and logical conditional branches. Both operands
are not affected. The only action is to set the condition codes. The compare is
customarily followed by a conditional branch instruction. Note: Unlike the subtract instruction, the order of operation is (src) - (dst), not (dst) - (src).

ADD
ADD SRC TO DST

06SSDD

o :

:oI

: : : I

: :
d

MR-5225

Operation:

(dst) <-- (src) + (dst)

Condition Codes:

N: set if result < 0; cleared otherwise
Z: set if result = 0; cleared otherwise
V: set if there was arithmetic overflow as a result of the operation; that is, both
operands were of the same sign and the result was of the opposite sign; cleared
otherwise
C: set if there was a carry from the result's most significant bit; cleared otherwise

Description:

Adds the source operand to the destination operand and stores the result at the
destination address. The original contents of the destination are lost. The contents
of the source are not affected. Two's complement addition is performed. Note:
There is no equivalent byte mode.

6-40

PRELIMINARY
Example:

Add to register:

ADD 20,RO

Add to memory:

ADD R1,XXX

Add register to register:

ADD Rl,R2

Add memory to memory:

ADD @#17750,XXX

XXX is a programmer-defined mnemonic for a memory location.

SUB
16SSDD

SUBTRACT SRC FROM DST
15
1

: oI

: :

: d : d

MR-5226

Operation:

(dst) <- (dst) - (src)

Condition Codes:

N: set if result < 0; cleared otherwise
Z: set if result = 0; cleared otherwise
V: set if there was arithmetic overflow as a result of the operation; that is, if operands were of opposite signs and the sign of the source was the same as the sign
of the result; cleared otherwise
C: cleared if there was a carry from the result's most significant bit; set otherwise

Description:

Subtracts the source operand from the destination operand and leaves the result at
the destination address. The original contents of the destination are lost. The contents of the source are not affected. In double-precision arithmetic the C bit, when
set, indicates a "borrow." Note: There is no equivalent byte mode.

Example:

SUB R 1,R2
Before

After

(Rl) = 011111
(R2) = 012345

(R1) = 011111
(R2) = 001234

NZVC
1111

NZVC
0000

•

6-41

PRELIMINARY
6.3.4.2 Logical - These instructions have the same format as those in the double-operand arithmetic
group. They permit operations on data at the bit level.

BIT
BITB
BIT TEST

15
0/1:

a : 1

06
:

s
MR-5227

Operation:

(src) 1\ (dst)

Condition Codes:

N: set if high-order bit of result set; cleared otherwise
Z: set if result = 0; cleared otherwise
V: cleared
C: not affected

Description:

Performs logical AND comparison of the source and destination operands and
modifies condition codes accordingly. Neither the source nor the destination is affected. The BIT instruction may be used to test whether any of the corresponding
bits set in the destination are also set in the source, or whether all corresponding
bits set in the destination are clear in the source.

Example:

BIT #30,R3

;test bits three and four of R3 to see if both are off.

R3 = 0000000 000 011 000
Before

After

NZVC
11 11

NZVC
0001

BIC
BICB
BIT CLEAR

15
0/1 :

-4SSDD

: a : a

06
:

: s

05
d

MA-5228

Operation:

(dst) <- - - (src) 1\ (dst)

Condition Codes:

N: set if high-order bit of result set; cleared otherwise
Z: set if result = 0; cleared otherwise
V: cleared
C: not affected

6-42

PRELIMINARY
Description:

Clears each bit in the destination that corresponds to a set bit in the source. The
original contents of the destination are lost. The contents of the source are not
affected.

Example:

BIC R3,R4
Before

After

(R3) = 001234
(R4) = 001111

(R3) = 001234
(R4) = 000101

NZVC

1111

0001

Before:

(R3) = 0 000001 010011 100
(R4) = 0 000 001 001 001 001

After:

(R4) = 0 000000001 000001

HIS
HISH
BIT SET

-~--

-5SSDD

15
0/1:

: a

MR·5229

Operation:

(dst) <- (src) V (dst)

Condition Codes:

N: set if high-order bit of result set; cleared otherwise
Z: set if result = 0; cleared otherwise
V: cleared
C: not affected

Description:

Performs an inclusive OR operation between the source and destination operands
and leaves the result at the destination address; that is, corresponding bits set in
the source are set in the destination. The contents of the destination are lost.

Example:

BIS RO,R 1
Before

After

(RO) = 001234
( R I) = 00 1 11 1

(RO) = 001234
(Rl) = 001335

NZVC

0000

Before:

(RO) = 0000001 010011 100
(Rl) = 0000001 001 001 001

After:

(R1) = 0000001 011 011 101

6-43

PRELIMINARY

XOR
074RDD

EXCLUSIVE OR

MR-5230

Operation:

(dst) <- (reg) V (dst)

Condition Codes:

N: set if result < 0; cleared otherwise
Z: set if result = 0; cleared otherwise
V: cleared
C: not affected

Description:

The exclusive OR of the register and destination operand is stored in the destination address. The contents of the register are not affected. The assembler format
is XOR R,D.

Example:

XOR RO,R2

6.3.5

Before

After

(RO) = 001234
(R2) = 001111

(RO) = 001234
(R2) = 000325

NZVC
I111

NZVC
0001

Before:

(RO) = 0000001 010011 100
(R2) = 0000001 001 001 001

After:

(R2) = 0000000011 010 101

Program Control Instructions

Branches - These instructions cause a branch to a location defined by the sum of the offset
(multiplied by 2) and the current contents of the program counter if:

6.3.5.1

I.
2.

The branch instruction is unconditional.
It is conditional and the conditions are met after testing the condition codes (NZVC).

The offset is the number of words from the current contents of the PC, forward or backward. Note that
the current contents of the PC point to the word following the branch instruction.
Although the offset expresses a byte address, the PC is expressed in words. The offset is automatically
multiplied by 2 and sign-extended to express words before it is added to the Pc. Bit 7 is the sign of the
offset. If it is set, the offset is negative and the branch is done in the backward direction. If it is not set,
the offset is positive and the branch is done in the forward direction.

6-44

PRELIMINARY
The 8-bit offset allows branching in the backward direction by 2008 words ( 4008 bytes) from the current PC, and in the forward direction by 1778 words (3768 bytes) from the current Pc.
The DCTII-AA assembler handles address arithmetic for the user and computes and assembles the
proper offset field for branch instructions in the form:
Bxx loc
Bxx is the branch instruction and loc is the address to which the branch is to be made. The assembler
gives an error indication in the instruction if the permissible branch range is exceeded. Branch instructions have no effect on condition codes. Conditional branch instructions where the branch condition is
not met are treated as NOPs.

DR
000400 PLUS OFFSET

BRANCH (UNCONDITIONAL)

o :

Operation:

PC +- PC + (2 X offset)

Condition Codes:

Not affected

Description:

Provides a way of transferring program control within a range of - 12810 to
+ 12710 words with a one word instruction.
New PC address = updated PC + (2 X offset)
Updated PC = address of branch instruction + 2

Example:

With the branch instruction at location 500, the following offsets apply.
New PC Address

Offset Code

Offset (decimal)

474
476
500
502
504
506

375
376
377
000
001
002

-3
-2
-1
0
+1
+2

--6-45

PRELIMINARY

8NE
001000 PLUS OFFSET

BRANCH IF NOT EQUAL (TO ZERO)
08

15
0

: : :o: o: : I
0

00
OFF:SET

MR-5232

Operation:

PC .-- PC + (2 X offset) if Z = 0

Condition Codes:

Not affected

Description:

Tests the state of the Z bit and causes a branch if the Z bit is clear. BNE is the
complementary operation of BEQ. It is used to test: (1) inequality following a
CMP, (2) that some bits set in the destination were also in the source following a
BIT operation, and (3) generally, that the result of the previous operation was not

Branch to C if A.=I= B

Example:

CMPA,B
BNE C

;compare A and B
;branch if they are not equal

Branch to C if A + B =1= 0
ADD A,B
BNE C

;add A to B
;branch if the result is not equal to 0

BEQ
001400 PLUS OFFSET

BRANCH IF EQUAL (TO ZERO)

MA-5233

Operation:

PC .-- PC + (2 X offset) if Z = 1

Condition Codes:

Not affected

Description:

Tests the state of the Z bit and causes a branch if Z is set. It is used to test: (1)
equality following a CMP operation, (2) that no bits set in the destination were
also set in the source following a BIT operation, and (3) generally, that the result
of the previous operation was O.

Example:

Branch to C if A = B (A - B = 0)
CMPA,B
BEQ C

;compare A and B
;branch if they are equal

6-46

PRELIMINARY
Branch to C if A + B = 0
ADD A,B
BEQ C

;add A to B
;branch if the result = 0

BPL
100000 PLUS OFFSET

BRANCH IF PLUS

: : : :o: o: : I
0

00
OFF:SET

MR-5234

Operation:

PC <-- PC + (2 X offset) if N = 0

Condition Codes:

Not affected

Description:

Tests the state of the N bit and causes a branch if N is clear (positive result). BPL
is the complementary operation of BMI.

BMI
BRANCH IF MINUS
08

15
1

100400 PLUS OFFSET

: o: o: o: o: o: o: I
1

OFF~ET
MA-5235

Operation:

PC <-- PC + (2 X offset) if N = 1

Condition Codes:

Not affected

Description:

Tests the state of the N bit and causes a branch if N is set. It is used to test the
sign (most significant bit) of the result of the previous operation), branching if
negative. BMI is the complementary function of BPL.

Bve
BRANCH IF OVERFLOW IS CLEAR

102000 PLUS OFFSET

MR·5236

6-47

PRELIMINARY
Operation:

PC <- PC + (2 X offset) if V = 0

Condition Codes:

Not affected

Description:

Tests the state of the V bit and causes a branch if the V bit is clear. BVC is complementary operation to BVS.

BVS
BRANCH IF OVERFLOW IS SET

102400 PLUS OFFSET

MR-5237

Operation:

PC <- PC + (2 X offset) if V = 1

Condition Codes:

Not affected

Description:

Tests the state of the V bit (overflow) and causes a branch if V is set. BVS is used
to detect arithmetic overflow in the previous operation.

Bee
103000 PLUS OFFSET

BRANCH IF CARRY IS CLEAR

MR·5238

Operation:

PC <- PC + (2 X offset) if C = 0

Condition Codes:

Not affected

Description:

Tests the state of the C bit and causes a branch if C is clear. BCC is the complementary operation of BCS.

Bes
103400 PLUS OFFSET

BRANCH IF CARRY IS SET

MR·5239

6-48

Operation:

PC <- PC + (2 X offset) if C = 1

Condition Codes:

Not affected

Description:

Tests the state of the C bit and causes a branch if C is set. It is used to test for a
carry in the result of a previous operation.

6.3.5.2

Signed Conditional Branches - Particular combinations of the condition code bits are tested
with the signed conditional branches. These instructions are used to test the results of instructions in
which the operands were considered as signed (2's complement) values.
Note that the sense of signed comparisons differs from that of unsigned comparisons in that in signed,
16-bit, 2's complement arithmetic the sequence of values is as follows.

077777
077776

largest
positive

000001
000000
177777
177776

smallest
negative

100001
100000

Whereas, in unsigned, 16-bit arithmetic, the sequence is considered to be:
highest

177777

lowest

000002
000001
000000

BGE
BRANCH IF GREATER THAN OR EQUAL
(TO ZERO)
15

a : a : a : a : a :

002000 PLUS OFFSET
07

OFF~ET
MA-5240

6-49

PRELIMINARY
Operation:

PC <- PC + (2 X offset) if N \f V = 0

Condition Codes:

Not affected

Description:

Causes a branch if N and V are either both clear or both set. BGE is the complementary operation of BLT. Thus, BGE will always cause a branch when it follows an operation that caused addition of two positive numbers. BGE will also
cause a br~nch on a 0 result.

BLT
BRANCH IF LESS THAN (ZERO)

002400 PLUS OFFSET
08

MR-5241

Operation:

PC <- PC + (2 X offset) if N, \f V = I

Condition Codes:

Not affected

Description:

Causes a branch if the exclusive OR of the N and V bits is one. Thus, BLTwill
always branch following an operation that added two negative numbers, even if
overflow occurred. In particular, BLT will always cause a branch if it follows a
CMP instruction operating on a negative source and a positive destination (even if
overflow occurred). Further, BLT will never cause a branch when it follows a
CMP instruction operating on a positive source and negative destination. BLT will
not cause a branch if the result of the previous operation was 0 (without overflow).

BGT
BRANCH IF GREATER THAN (ZERO)

003000 PLUS OFFSET
08

MA-5242

Operation:

PC <- PC + (2 X offset) if Z V (N \f V) = 0

Condition Codes:

Not affected

Description:

Operation of BGT is similar to BGE, except that BGT will not cause a branch on
a 0 result.

6-50

PRELIMINARY

BLE
003400 PLUS OFFSET

BRANCH IF LESS THAN OR EQUAL (TO ZERO)
08

MR-5243

Operation:

PC +- PC + (2 X offset) if Z V (N V V) = 1

Condition Codes:

Not affected

Description:

Operation is similar to BLT, but in addition will cause a branch if the result of the
previous operation was O.

6.3.5.3 Unsigned Conditional Branches - The unsigned conditional branches provide a means for testing the result of comparison operations in which the operands are considered as unsigned values.

BHI
BRANCH IF HIGHER

101000 PLUS OFFSET

15
1

: o: o:

OFF~ET
MR-5244

Operation:

PC +- PC + (2 X offset) if C = 0 and Z = 0

Condition Codes:

Not affected

Description:

Causes a branch if the previous operation caused neither a carry nor a 0 result.
This will happen in comparison (CMP) operations as long as the source has a higher unsigned value than the destination.

BLOS
BRANCH IF LOWER OR SAME

101400 PLUS OFFSET
08

MA-5245

6-51

PRELIMINARY
Operation:

PC <- PC + (2 X offset) if C V Z = I

Condition Codes:

Not affected

Description:

Causes a branch if the previous operation caused either a carry or a 0 result.
BLOS is the complementary operation of BHI. The branch will occur in comparison operations as long as the source is equal to or has a lower unsigned value
than the destination.

BHIS
103000 PLUS OFFSET

BRANCH IF HIGHER OR SAME
08

MA·5246

Operation:

PC <- PC + (2 X offset) if C = 0

Condition Codes:

Not affected

Descri ption:

BHIS is the same instruction as BCe. This mnemonic is included for convenience
only.

BLO
103400 PLUS OFFSET

BRANCH IF LOWER
08

MA-5247

Operation:

PC <- PC + (2 X offset) if C =

Condition Codes:

Not affected

Descri ption:

BLO is the same instruction as BCS. This mnemonic is included for convenience
only.

6.3.5.4 Jump and Subroutine Instructions - The subroutine call in the DCTII-AA provides for tlutomatic nesting of subroutines, reentrancy, and multiple entry points. Subroutines may call other subroutines (or indeed themselves) to any level of nesting without making special provision for storage of
return addresses at each level of subroutine call. The subroutine calling mechanism does not modify
any fixed location in memory, and thus provides for reentrancy. This allows one copy of a subroutine to
be shared among several interrupting processes.

6-52

PRELIMINARY

JMP
JUMP

0001 DD
05

o : o : o : o : o : o :

00
d

MR·5248

Operation:

PC .- (dst)

Condition Codes:

Not affected

Description:

JMP provides more flexible program branching than the branch instructions do.
Control may be transferred to any location in memory (no range limitation) and
can be accomplished with the full flexibility of the addressing modes, with the
exception of register mode o. Execution of a jump with mode 0 will cause an "illegal instruction" condition, and will cause the CPU to trap to vector address four.
(Program control cannot be transferred to a register.) Register-deferred mode is
legal and will cause program control to be transferred to the address held in the
specified register. Note that instructions are word data and must therefore be fetched from an even-numbered address.
Deferred-index mode JMP instructions permit transfer of control to the address
contained in a selectable element of a table of dispatch vectors.

Example:

First:
JMP FIRST

;transfers to FIRST

JMP @LlST

;transfers to location pointed to at LIST

List:
FIRST

;pointer to FIRST

JMP @(SP)+

;transfer to location pointed to by the top of the stack,
and remove the pointer from the stack

JSR
JUMP TO SUBROUTINE

004RDD
09

o : o : o : o :

05
I

:o:

d
\

MR-5249

6-53

PRELIMINARY
Operation:

(tmp) ~ (dst) (tmp is an internal processor register)

1 (SP) ~ reg (Push reg contents onto processor stack)
reg ~ PC (PC holds location following JSR; this address now put in reg)
PC ~ (dst) (PC now points to subroutine destination)
Description:

In execution of the JSR, the old contents of the specified register (the "linkage
pointer") are automatically pushed onto the processor stack and new linkage information is placed in the register. Thus, subroutines nested within subroutines to
any depth may all be called with the same linkage register. There is no need either
to plan the maximum depth at which any particular subroutine will be called or to
include instructions in each routine to save and restore the linkage pointer. Further, since all linkages are saved in a reentrant manner on the processor stack,
execution of a subroutine may be interrupted. The same subroutine may be reentered and executed by an interrupt service routine. Execution of the initial subroutine can then be resumed when other requests are satisfied. This process
(called "nesting") can proceed to any level.
A subroutine called with a JSR reg,dst instruction can access the arguments following the call with either autoincrement addressing, (reg) +, if arguments are
accessed sequentially, or by indexed addressing, X(reg), if accessed in random order. These addressing modes may also be deferred, @(reg)+ and @X(reg), if the
parameters are operand addresses rather than the operands themselves.
JSR PC, dst is a special case of the DCTII-AA subroutine call suitable for subroutine calls that transmit parameters through the general registers. The SP and
the PC are the only registers that may be modified by this call.
Another special case of the JSR instruction is JSR PC,@(SP) +, which exchanges the top element of the processor stack with the contents of the program
counter. This instruction allows two routines to swap program control and resume
operation from where they left off when they are recalled. Such routines are
called "coroutines."
Return from a subroutine is done by the RTS instruction. RTS reg loads the contents of reg into the PC and pops the top element of the processor stack into the
specified register.

Example:
SBCALL:
SBCALL+4:

JSR R5,SBR
ARG 1
ARG2

SBCALL+2+2M:
CONT:

ARGM
Next Instruction

6-54

R7
SBCALL

CONT

PRELIMINARY
SBR:

EXIT:

MOY (R5) + ,dst 1
MOY (R5)+,dst 2

SBCALL+4

n-2

SBR

MOY (R5) + ,dst M
Other Instructions
RTSR5

SBCALL+2+2M
CONT
CONT

n-2

EXIT

JSR R5, SBR

BEFORE:

STACK

DATA 0

(SP)

SBR

AFTER:

(PC)

DATA 0
R6

n-2

I
I

PC+2

JSR PC, SBR

BEFORE:

AFTER:

(PC)

(SP)

SBR

R61

STACK

DATA 0

n-2

6-55

DATA 0
PC+2
MA·6250

PRELIMINARY

RTS
00020R

RETURN FROM SUBROUTINE

o :

0 :

o
MA-5251

Operation:

PC <- (reg)
(reg) < - (SP) T

Description:

Loads the contents of the register into PC and pops the top element of the processor stack into the specified register.
Return from a nonreentrant subroutine is typically made through the same register that was used in its call. Thus, a subroutine called with a JSR PC, dst exits
with a RTS PC and a subroutine called with a JSR R5, dst, may pick up parameters with addressing modes (R5) +, X(R5), or @X(R5) and finally exits, with an
RTS R5.
.

Example:

RTS R5
RTS R5
BEFORE:

(PC)

STACK

SBR

I
DATA 0

(SP)

PC _......
R51L.._ _

AFTER:

R71.

n+2

DATA 0

I
MA-5252

6-56

PRELIMINARY

SOB
SUBTRACT ONE AND BRANCH (IF *- 0)

077RNN
09

o :

I :

OFF~ET
MR-5253

PC - (2 X offset); if (R) =

Operation:

(R) - (R) - 1; if this result =1= 0, then PC PC -PC

Condition Codes:

Not affected

Descri ption:

The register is decremented. If the contents does not equal 0, twice the offset is
subtracted from the PC (now pointing to the following word). The offset is interpreted as a 6-bit positive number. This instruction provides a fast, efficient method of loop control. The assembler syntax is SOB R,A where A is the address to
which transfer is to be made if the decremented R is not equal to 0. Note: the
SOB instruction cannot be used to transfer control in the forward direction.

then

6.3.5.5 Traps - Trap instructions provide for calls to emulators, I/O monitors, debugging packages,
and user-defined interpreters. A trap is effectively an interrupt generated by software. When a trap
occurs, the contents of the current program counter (PC) and processor status word (PS) are pushed
onto the processor stack and replaced by the contents of a 2-word trap vector containing a new PC and
new PS. The return sequence from a trap involves executing an RTI or RTT instruction, which restores
the old PC and old PS by popping them from the stack. Trap instruction vectors are located at permanently assigned fixed addresses.

EMT
104000- 104377

EMULATOR TRAP
08

MR-5254

Operation:

1(SP) - PS
1(SP) <--- PC
PC <--- (30)
PS + - (32)

Condition Codes:

N: loaded from trap vector
Z: loaded from trap vector
V: loaded from trap vector
C: loaded from trap vector

6-57

PRELIMINARY
Description:

All operation codes from 104000 to 104377 are EMT instructions and may be
used to transmit information to the emulating routine (e.g., function to be performed). The trap vector for EMT is at address 30. The new PC is taken from the
word at address 30; the new processor status (PS) is taken from the word at address 32.
CAUTION: EMT is used frequently by DIGITAL system software and is therefore not recommended for general use~

PC 1

STACK

BEFORE:
SP

AFTER:

DATA 1

(32)

(30)

DATA 1
PS 1

n-4

PC 1

MR-5255

TRAP
104400-104777

TRAP

MA-5256

Operation:

1(SP) -- PS
1(SP) -- PC
PC -- (34)
PS +- (36)

6-58

PRELIMINARY
Condition Codes:

N: loaded from trap vector
Z: loaded from trap vector
V: loaded from trap vector
C: loaded from trap vector

Description:

Operation codes from 104400 to 104777 are TRAP instructions. TRAPs and
EMTs are identical in operation, except that the trap vector for TRAP is at address 34.
NOTE: Since DIGITAL software makes frequent use of EMT, the TRAP instruction is recommended for general use.

BPT
000003

BREAKPOINT TRAP

MR-5257

1 (SP) <- PS

Operation:

1 (SP) <- PC
PC <- (14)
PS <- (16)

Condition Codes:

N: loaded from trap vector
Z: loaded from trap vector
V: "loaded from trap vector
C: loaded from trap vector

Description:

Performs a trap sequence with a trap vector address of 14. Used to call debugging
aids. The user is cautioned against employing code 000003 in programs run under
these debugging aids. (No information is transmitted in the low byte.)

lOT
000004

INPUT/OUTPUT TRAP

o :

MR·5258

Operation:

1(SP) <- PS

1(SP) <- PC
PC <- (20)
PS <- (22)

6-59

PRELIMINARY
Condition Codes:

N: loaded from trap vector
Z: loaded from trap vector
V: loaded from trap vector
C: loaded from trap vector

Description:

Performs a trap sequence with a trap vector address of 20. (No information is
transmitted in the low byte.)

RTI
RETURN FROM INTERRUPT

000002

MR-5259

Operation:

PC <- (SP) T
PS < - (SP) T

Condition Codes:

N: loaded from processor stack
Z: loaded from processor stack
V: loaded from processor stack
C: loaded from processor stack

Description:

Used to exit from an interrupt or TRAP service routine. The PC and PS are restored (popped) from the processor stack. If a trace trap is pending, the first instruction after RTI will not be executed prior to the next T trap.

RTT
RETURN FROM INTERRUPT

000006
00

o
MR-5260

Operation:

PC <- (SP) T
PS <- (SP) T

Condition Codes:

N: loaded from processor stack
Z: loaded from processor stack
V: loaded from processor stack
C: loaded from processor stack

Descri ption:

Operation is the same as RTI except that it inhibits a trace trap whereas RTI
permits trace trap. If the new PS has the T bit set, a trap will occur after execution of the first instruction after R TT.
.

6-60

PRELIMINARY
6.3.5.6 Reserved Instruction Traps - These are caused by attempts to execute instruction codes reserved for future processor expansion (reserved instructions) or instructions with illegal addressing
modes (illegal instructions). Order codes not corresponding to any of the instructions described are considered to be reserved instructions. JMP and JSR with register mode destinations are illegal instructions; they trap to vector address 4. Reserved instructions trap to the vector addresses as listed in Table
A-14 in Appendix A.
6.3.5.7 Halt Interrupt - This is caused by the - HALT line (AI <7». The - HALT interrupt saves
the PC and PS and goes to the restart address with PS = 3408.
6.3.5.8 Trace Trap - Trace trap is enabled by bit 4 of the PS and causes processor traps at the end of
instruction execution. The instruction that is executed after the instruction that set the T bit will proceed to completion and then trap through the trap vector at address 14. Note that the trace trap is a
system debugging aid and is transparent to the general programmer.
NOTE
Bit 4 of the PS can only be set indirectly by executing a RTI or RTT instruction with the desired PS
on the stack.
6.3.5.9 Power Failure Interrupt - Occurs when the - PF line (AI <6» is asserted. The vector for
power failure is in locations 24 and 26. A trap will occur if an RTI instruction is executed in a powerfail service routine.
6.3.5.10 CP<3:0> Interrupts - Refer to Paragraph 1.5.3.
6.3.5.11 Special Cases of the T Bit - The following are special cases of the T bit.
NOTE
The traced instruction is the instruction after the
one that set the T bit.
I.

An instruction that cleared the T bit - Upon fetching the traced instruction, an internal flag,
the trace flag, was set. The trap will still occur at the end of this instruction's execution. The
status word on the stack, however, will have a clear T bit.

An instruction that set the T bit - Since the T bit was already set, setting it again has no
effect. The trap will occur.

An instruction that caused an instruction trap - The instruction trap is performed and the
entire routine for the service trap is executed. If the service routine exits with an RTI, or in
any other way restores the stacked status word, the T bit is set again, the instruction following the traced instruction is executed, and, unless it is one of the special cases noted previously, a trace trap occurs.

Interrupt trap priorities - In the case of multiple processor trap and interrupt conditions occurring simultaneously, the following order of priorities is observed (from high to low).
Halt Line
Trace Trap
Power-Fail Trap
CP<3:0> Interrupt Request
Instruction Traps

6-61

PRELIMINARY

6.3.6

Miscellaneous Instructions

HALT
000000

HALT

o :

0 :

~ : 0 : 0

MA·5261

1(SP) <- PS
1 (SP) <- PC

Operation:

PC <- restart address
PS <- 340
Condition Codes:

Not affected

Description:

The processor goes to the restart address after placing the current PC and PS on
the stack. PS is initialized to 340.

WAIT
WAIT FOR INTERRUPT

OOpOOl

o : o : o : o : o : o : o : o : o : o : o : o : o : o : o :

MA-5262

Condition Codes:

Not affected

Description:

In WAIT, as in all instructions, the PC points to the next instruction following the
WAIT instruction. Thus, when an interrupt causes the PC and PS to be pushed
onto the processor stack, the address of the next instruction following the WAIT is
saved. The exit from the interrupt routine (i.e., execution of an RTI instruction)
will cause resumption of the interrupted process at the instruction following the
WAIT.

RESET
RESET EXTERNAL BUS

000005

o :

00
0:

0 :

0: 0 : 0.: 0 : 0 : 0 : 0: 0 : 1 : 0 : 1

MA-5263

6-62

PRELIMINARY
Condition Codes:

Not affected

Description:

The - BCLR line is asserted and the mode register is loaded. The - BCLR line is
negated and an ASPI transaction takes place. PC, PS, and RO-R5 are not affect-

ed.

MFPT
000007

MOVE FROM PROCESSOR TYPE WORD

MA-7198

Operation:

RO.- 4

Condition Codes:

Not affected

Description:

The number 4 is placed in RO, indicating to the system software that the processor
type is DCTII-AA.

6.3.7

Condition Code Operators

CLN SEN
CLZ SEZ
CLV SEV
CLC SEC
CCC SCC
CONDITION CODE OPERATORS

0002XX

15
0

011

I Iz I I I
N

MR-5266

Description:

Set and clear condition code bits. Selectable combinations of these bits may be
cleared or set together. Condition code bits corresponding to bits in the condition
code operator (bits 0-3) are modified according to the sense of bit 4, the set/clear
bit of the operator; i.e., set the bit specified by bit 0, I, 2, or 3, if bit 4 = l. Clear
corresponding bits if bit 4 = o.

6-63

PRELIMINARY
Mnemonic

Operation

OPCode

CLC
CLV
CLZ
CLN
SEC
SEV
SEZ
SEN
SCC
CCC

Clear C
Clear V
Clear Z
Clear N
SetC
Set V
Set Z
Set N
Set all CCs
Clear all CCs
Clear V and C
No operation

000241

NOP

000242
000244

000250
000261
000262
000264
000270
000277
000257
000243
000240

Combinations of the above set or clear operations may be ORed together to form
combined instructions.

6-64

PRELIMINARY

APPENDIX A
TABLES AND TIMING DIAGRAMS

Table A-I

-HALT*

-PF

Interrupt Decode

-CP<3>
(AI<I»

-CP<2>
(AI<2»

-CP<l>
(AI<3»

-CP<O>
(AI<4> )

Priority
Level

Vector
Address

X
X

8
8

L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

L
L
H
H

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

7
7
7
7
6
6
6
6
5
5
5
5
4
4
4
No action

L
L
H
H
L
L
H
H
L
L
H
H

*PC is loaded with the restart address; PSW = 340.

A-I

24
140
144
150
154
100
104
110
114
120
124
130
134
60
64
70

PRELIMINARY
Table A-2

DC Characteristics

Absolute Maximum Ratings
-0.5 V to +7 V
-55 0 C to + 125° C
(-67 0 F to 257 0 F)
l.lW
0° C to 70° C
(32° F to 158 0 F)

Pin voltages
Storage temperature range
Maximum power dissipation
Chip ambient temperature operating range

NOTE
Stresses greater than those listed may cause permanent damage
to the device. Exposure to absolute maximum rating conditions
for extended periods may affect the device's reliability.
Static Characteristics
TA = 0° C to 70° C (32° F to 158° F), VCC = 5.0 V ± 5%, VSS = 0 V
Symbol

Parameter jPins

IlL

(Low input) Three-state
leakage current on
DAL<15:0>
(High input) Three-state
leakage current on
DAL<15:0>
(Min.) Input current
for internal pull-ups
on AI<7:0>, READY,
DAL< 15:7,2:0>
(Max.) Input current
for internal pull-ups
on AI <7:0>, READY,
DAL< 15:7,2:0>
Power supply current
on VCC
Input high current on
XTLI
Input low current on
XTLI
Input high voltage on
READY, DAL<15:0>, AI<7:0>
Input low voltage
on READY, DAL<15:0>,
AI<7:0>
Output high voltage
for DAL<15:0>, COUT,
PI, SELl, SELO
Output high voltage for
AI<7:0>
Output high voltage for
BCLR

IlL
IIH

IIH

ICC
IXLIH
IXLIL
VIH
VIL
VOH
VOHA
VOHB

VOHC

Output high voltage for
- RAS, - CAS, Rj - WLB,
Rj-WHB

Max.

Units

Comments and
Conditions

-50

J.lA

VIN = 0.4 V

+10

J.lA

VIN = VCC max.

rnA

VIN = 2.4 V

-0.1

rnA

VIN = 0.4 V

190

rnA

TCYC = 400 ns

+700

J.lA

-6.4

rnA

2.4 < VIN < VCe.
XTLO grounded
-0.5 < VIN < +0.8 V,
XTLO grounded

VCC

-0.5*

+0.8

Min.

-0.1

2.4

IOH = 700J.lA

2.6

IOH = -700J.lA

2.2

IOH = -700J.lA
terminated with
I K resistor to VSS

2.8

IOH = -700J.lA

A-2

Table A-2

DC Characteristics (Cont)

Symbol

Parameter j Pins

Min.

Max.

Units

Comments and
Conditions

VOL

Output low voltage
for DAL<15:0>. AI<7:0>.
COUTo PI. SEll. SELO.
-BCLR. -RAS. -CAS.
Rj - WLB. Rj - WHB
Input low level for PUP
I nput high level for PU P
Hysteresis. PUP
I nput capacitance
for READY. DAL< 15:0>.
AI<7:0>
Output capacitance
for three-state load
calculation on DAL< 15:0>.
AI<7:0>. COUTo PI. SELl.
SELO. - BCLR. - RAS. -CAS.
Rj - WHB. Rj - WLB

0.0

0.4

IOL = 3,2 rnA

-0.5*
1.6
0.6

+0,8
VCC
10

V
V
V
pF

VILPUP
VIHPUP
VHY
CIN

("OUT

* -0.5 Von input pins allows for ringing on unterrninated lines,

A-3

PRELIMINARY
,~

Table A-3 Sequences of Transactions
I - lACK

R- Read
W - Write
Ref - Refresh
(replaced by N in
static modes)
Instruction

I6-Bit

CLRRO

CLR (RO) or
MOY RO, (Rl)
or MOY RO, (RI)+

MOY RO, -(R!)

MOY RO, @X(R!)
MTPS RO
JMP (RO)
JSR RO, (R!)
WAIT
HLT
EMT
RESET
Interrupt sequence

D-DMA
A-ASPI
N - Busnop
8-Bit

Sequence of Transaction

RRefN
R-RRefN

R RefR-W
R-R Ref R-R-W-W

RRefN R-W
R-R Ref N R-R-W-W

R Ref R N R-W Ref!
R-R Ref R-R N R-R-W-W Refl

RRefNN NNN
R-RRefNN N N N

R RefN N
R-R RefN N

RRefNNNNN
R-R RefN N W-W N N

R [RefN A)2
R-R [Ref N A)2

R Ref NNW Ref N W N NAN
R-R RefN N W-W RefN W-W N NAN

R Ref NNW Ref N W R R N
R-R Ref N N W-W Ref N W-W R-R R N

R Ref N N N N [N N N)3 N N NAN
R-RRefNN N N [N N N)3 N N NAN

X
X
X
X

X
X

... R-W4[I N N5 N W RefN W R R N) R6 ...
... R-R-W-W 5 [I N N5 N W-W Ref N
W-W R-R R N) R-R6 ...

X
X

DMA sequence

NOTE: R-W means
read-modify-write
( - indicates
indivisible)

... R-W7 DR ...
... R-R-W_W7 D R-R ...

! Missing transaction in static mode.
2 Sequence repeated until interrupt request.
3 Sequence repeated nine times. (- BCLR is low during this time.)
4 Last transactions of instruction in which interrupt is posted.
5 Transaction missing if internal vector is used.
6 Fetch of first instruction of interrupt service routine.
7 R-W (R-R-W-W) are indivisible.

A-4

PRELIMINARY
Table A-4

Signal and Pin Utilization, 16-Bit Mode

Signal Names
Pin(s)

Pin Name

Static

4K/16K Dynamic

64K Dynamic

DAL<IS:8>
DAL<7:0>

-RAS

-CAS PI

-RAS

-CAS

-DMR
-CP<3>
-CP<2>
-CP
-CP<O>
-VEC
-PF
-HALT

FET*
Al
A3
AS
A7
A9
All
AI3

AI4
A2
A4
A6
A8
AlO
Al2
Al4

AI)
AI
A3
AS
A7
A9
All
AI3

AI4
A2
A4
A6
A8
AIO
AI2
AI4

-DMR
-CP<3>
-CP<2>
-CP
-CP<O>
-VEC
-PF
-HALT

lACK + DMG
FET + DMG
READY
R/-WHB
R/-WLB
-RAS
-CAS
PI

lACK + DMG
REF + DMG
READY
R/-WHB
R/-WLB
-RAS
-CAS
PI

lACK + DMG
FET + DMG
READY
R/-WHB
R/-WLB
-RAS
-CAS
PI

-BCLR
PUP
COUT
XTLI
XTLO

BGND
GND
VCC

Data Address Lines
1-7,9
10-17

DAL<IS:8> DAL<IS:8>
DAL<7:0> DAL<7:0>

Address Interrupt Lines

32
33
34
3S
36
37
38
39

AI<O>
AI
AI<2>
AI<3>
AI<4>
AI<S>
AI<6>
AI<7>

-DMR
-CP<3>
-CP<2>
-CP
-CP<O>
-VEC
-PF
-HALT

Control Signals
24
25
26
27

28
29
30
31

SELlt
SELOt
READY
R/-WHB
R/-WLB
-RAS
-CAS
PI

Miscellaneous Signals
18
19
21
22
23

-BCLR
PUP
COUT
XTLI
XTLO

Power Pins
8
20
40

BGND
GND
VCC

NOTES
*During -RAS, AI<O> is used to indicate a fetch operation in progress. During refresh, AI<O> is the output of the refresh counter at - RAS time.
tSEL and SEL<O> are encoded; refer to Tables 3-4 and 3-S.

A-5

PRELIMINARY
Table A-5

Signal and Pin Utilization, 8-Bit Mode

Signal Names
Pin(s)

Pin Name

Static

4Kj16K Dynamic

64K Dynamic

SAL<15:8>
DAL<7:0>

Data Address Lines
1-7,9
10-\7

DAL<15:8> SAL<15:8>
DAL<7:0> DAL<7:0>

Address Interrupt Lines

32
33
34
35
36
37
38
39

AI<O>
AI
AI<2>
AI<3>
AI<4>
AI<5>
AI<6>
AI<7>

-RAS -CAS

-DMR
-CP<3>
-CP<2>
-CP
-CP<O>
-VEC
-PF
-HALT

FET*
Al
A3
AS
A7
A9
All
AI3

-DMR
-CP<3>
-CP<2>
-CP
-CP<O>
-VEC
-PF
-HALT

AI5
Al
A3
AS
A7
A9
All
AI3

-DMR
-CP<3>
-CP<2>
-CP
-CP<O>
-VEC
-PF
-HALT

lACK + DMG
FET + DMG
READY
-RD
-WT
-RAS
-CAS
PI

lACK + DMG
REF + DMG
READY
-RD
-WT
-RAS
-CAS
PI

lACK + DMG
FET + DMG
READY
-RD
-WT
-RAS
-CAS
PI

-BCLR
PUP
COUT
XTLI
XTLO

BGND
GND
VCC

AI4
A2
A4
A6
A8
AIO
AO
AI2

Control Signals
24
25
26
27
28
29
30
31

SELlt
SELOt
READY
Rj-WHB
Rj-WLB
-RAS
-CAS
PI

Miscellaneous Signals
18
19
21
22
23

-BCLR
PUP
COUT
XTLI
XTLO

Power Pins
8
20
40

BGND
GND
VCC

NOTES
"'During -RAS, AI<O> is used to indicate a fetch operation in progress. During refresh, AI<O> is the output of the refresh counter at - RAS time.
tSEL and SEL<O> are encoded; refer to Table.!' 3-4 and 3-5.

A-6

PRELIMINARY
Table A-6

16-Bit Dynamic Write Addressing Scheme

Mode

Memory Chip

Address*

AI Used

4K/16K
4K/16K
64K

4K X I
16K X I
64K X I

AI-Al2
AI-AI4
AI-A15

<6:1>
<7:1>
<7:0>

*Address lines necessary to address all bits in each chip.
Table A-7

SEL<1:0> Functions in Static Mode or Dynamic 64K Mode

SEL<l>

SEL<O>

Function

L
L
H
H

L
H
L
H

Read, write, ASPI, or busnop
Fetch (PDP-II instruction fetch)
lACK (interrupt acknowledge)
DMG (direct memory grant)

Table A-8

SEL<l:O> Functions in Dynamic 4Kj16K Mode

SEL<l>

SEL<O>

Function

L
L
H
H

L
H
L
H

Read, write, ASPI, or busnop
Refresh
lACK (interrupt acknowledge)
DMG (direct memory grant)

Table A-9

AI Functions

@ - RAS (L.E.)
Output

@ -CAS (L.E.)
Output

@PI (T.E.)
Input

•

InterruptjDMR

Write (static)

•
•

DMR

Read (dynamic)

Row address

Column address

InterruptjDMR

Write (dynamic)

Row address

Column address

DMR

Refresh

Row address

NjA

DMA

•

DMR

ASPI

NjA

•
•

Transaction
Read (static)

• - Internal low-current passive pull-ups.
N/A - Not applicable.

A-7

InterruptjDMR

PRELIMINARY
Table A-tO

Control Signals for Each Transaction

Transaction

-RAS

-CAS

Rj-WHB

Read

Fetch

Write

Refresh

'"
'"

lACK

DMA

ASPI

Rj-WLB

SELO

*
2

'"
'"
'"

'"
'"

Busnop

* - Signal asserted during the transaction.
1 - Static modes and dynamic 64K.
2 - Dynamic modes 4Kj 16K.
X - Signal asserted during 8-bit mode only.
- Signal asserted during 16-bit mode only.
3S - Three-state.

Table A-ll
Transaction

Data Bus for Each Transaction

DALLow Byte

DAL High Byte

Read

Fetch

Write

Refresh

'"
'"

lACK
DMA

ASPI
Busnop

SELl

X - Lines driven after address portion of transaction (8-bit mode only).
'" - Lines driven after address portion of transaction (8-bit and 16-bit modes).
1 - Dynamic modes only.
.
3S - Three-state.

A-8

PRELIMINARY
Table A-12

Summary of DCTll-AA Instructions

SINGLE OPERAND
Mnemonic

Instruction

dst Result

NZVC

Clear
Complement (1 's)
Increment
Decrement
Negate (2's complement)
Test

0
-d
d+!
d-l
-d
d

0 I o0
* * o I

Rotate right
Rotate left
Arithmetic shift right
Arithmetic shift left
Swap bytes

-C,d
C, d +-d/2
2d

* * * *
* * * *
* * * *
* * * *
* * o0

Add carry
Subtract carry
Sign extend

d+c
d-c
o or -I

* * * *
- * 0 -

Move byte from PS
Move byte to PS

d +-- PS
PS +-- s

* * 0 * * * *

.ISSOO
.2SS00
06SS00
16SS00

Move
Compare
Add
Subtract

d+--s
s- d
d+--s+d
d+--d-s

* * * *
* * * *
* * * *

.3SS00
.4SS00
.5SS00
074ROO

Bit test (AND)
Bit clear
Bit set (OR)
Exclusive (OR)

sAd
d +-- (-s) V d
d+--sVd
d+--r'v'd

* * 0 * * 0 * * 0 * * 0 -

Base
Code

Instruction

000400
001000
001400
100000
100400
102000
102400

Branch (unconditional)
Branch if not equal (to 0)
Branch if equal (to 0)
Branch if plus
Branch if minus
Branch if overflow is clear
Branch if overflow is set

General
CLR(B)
COM(B)
INC(B)
OEC(B)
NEG(B)
TST(B)

.05000
.05IDO
.05200
.05300
.05400
.05700

* * * * * * * * * *
* * o0

Rotate and Shift
ROR(B)
ROL(B)
ASR(B)
ASL(B)
SWAB

.06000
.06100
.06200
.06300
000300

Multiple-Precision
AOC(B)
SBC(B)
SXT

.05500
.05600
006700

* * * *

Processor Status (PS) Operators
MFPS
MTPS

106700
1064SS

DOUBLE OPERAND
General
MOV(B)
CMP(B)
ADD
SUB

* * 0 -

Logical
BIT(B)
BIC(B)
BIS(B)
XOR
BRANCH
Mnemonic

Branch Condition

Branches
BR
BNE
BEQ
BPL
BMI
BVC
BVS

A-9

(always)
*0
=0
+
-

Z=O
Z=I
N = 0
N = 1
V=O
V=!

•

PRELIMINARY

C = 0
C=I

Branch if carry is clear
Branch if carry is set

BCC
BCS

Signed Conditional Branches
BGE
BLT
BGT
BLE

002000
002400
003000
003400

Branch if greater or equal
Branch if less than (0)
Branch if greater than (0)
Branch if less or equal

<0
>0

Unsigned Conditional Branches

.;;;

BHI
BLOS
BHIS
BLO

>
.;;;

101000
101400
103000
103400

Branch if higher
Branch if lower or same
Branch if higher or same
Branch if lower

NVV=O
N 'lfV= 1
Z V (N 'If V) = 0
Z V (N 'If V) = 1

C VZ = 0
C VZ = 1
C=O
C=I

JUMP and SUBROUTINE
Mnemonic

OpCode

Instruction

Notes

JMP
JSR
RTS
SOB

OOOIDD
004RDD
00020R
077RNN

Jump
Jump to subroutine
Return from subroutine
Subtract I and branch
(if =1= 0)

PC +- dst
Use same R
Use same R
R - I, then if R =1= 0:
PC +-- Updated PC - (2 X NN)

Emulator trap
(not for general use)
Trap

PC at 30, PS at 32

TRAP and INTERRUPT
EMT
TRAP
BPT
lOT
RTI

RTI

104000 to
104377
104400 to
104777
000003
000004
000002
000006

Breakpoint trap
Input/output trap
Return from interrupt
Return from interrupt

PC at 34, PS at 36
PC at 14, PS at 16
PC at 20, PS at 22
Inhibit T bit trap

MISCELLANEOUS
Mnemonic

OpCode

Instruction

HALT
WAIT
RESET
MFPT
NOP

000000
000001
000005
000007
000240

Halt
Wait for interrupt
Reset external bus
Move from processor type
(No operation)

CONDITION CODE OPERATORS
Mnemonic

OpCode

Instruction

NZVC

CLC
CLV
CLZ
CLN
CCC
SEC
SEV
SEZ
SEN
SCC

000241
000242
000244
000250
000257
000261
000262
000264
000270
000277

Clear C
Clear V
Clear Z
ClearN
Clear all CC bits
Set C
Set V
Set Z
Set N
Set all CC bits

---0
--0 -0 - -

o --o0 0 0

-- -I
- -I -1 - -

1 --1 1 I 1

A-1O

PRELIMINARY
Table A-13

Numerical Op Code List

OpCode

Mnemonic

OpCode

Mnemonic

OpCode

Mnemonic

000000
000001
000002
000003
000004
000005
000006
000007
000077
000] DD
0002 OR
000210
through
000227
000240
000241
through
000277
0003 DD
0004 XXX
0010 XXX
0014XXX
0020 XXX
0024 XXX
0030 XXX
0034 XXX
004R DD
0050 DD
0051 DD
0052 DD

HALT
WAIT
RTI
BPT
lOT
RESET
RTT
MFPT
Unused
JMP
RST
Reserved

0053 DD
0054 DD
0055 DD
0056 DD
0057 DD
0060 DD
0061 DD
0062 DD
0063 DD
0067 DD
007000
through
007777
01 SS DD
02 SS DD
03 SS DD
04 SS DD
05 SS DD
06 SS DD
075040
through
076777
077RNN
1000 XXX
1004 XXX
10 10 XXX
1014 XXX
10 20 XXX
10 24 XXX
10 30 XXX

DEC
NEG
ADC
SBC
TST
ROR
ROL
ASR

10 34 XXX
10 40 00
through
10 4377
104400
through
]04777
]050 DD
10 51 DD
10 52 DD
10 53 DD
1054 DD
10 55 DD
10 56 DD
1057 DD
10 60 DD
1061 DD
10 62 DD
1063 DD
10 64 SS
10 67 DD
11 SS DD
12 SS DD
13 SS DD
14SS DD
15 SS DD
16 SS DD
170000
through
177777

BCS, BLO
EMT

NOP
Condition
codes
SWAB
BR
BNE
BEQ
BGE
BLT
BGT
BLE
JSR
CLR
COM
INC

Table A-14
Vector
000
004
010
014
020
024
030
034

SXT
Unused
MOV
CMP
BIT
BIC
BIS
ADD
Unused
SOB
BPL
BMI
BHI
BLOS
BVC
BVS
BCC, BHIS

TRAP
CLRB
COMB
INCB
DECB
NEGB
ADCB
SBCB
TSTB
RORB
ROLB
ASRB
ASLB
MTPS
MFPS
MOVB
CMPB
BITB
BICB
BISB
SUB
Reserved

Reserved Trap and Interrupt Vectors

Description
Default vector = 0 for interrupting device failing to put vector out on DALs.
If mode 0 is the destination address in a JMP or JSR instruction, a trap will occur to vector location 4.

Illegal and reserved instruction.
BPT instruction and T bit.
lOT instruction.
Power fail.
EMT instruction.
TRAP instruction.

A-II

PRELIMINARY
Table A-IS

7~Bit ASCII Code

Octal

Char.

Octal

Char.

Octal

Char.

Octal

000
001
002
003
004
005
006
007
010
011
012
013
014
015
016
017
020
021
022
023
024
025
026
027
030
031
032
033
034
035
036
037

NUL
SOH
STX
ETX
EOT
ENQ
ACK
BEL
BS
HT
LF
VT
FF
CR
SO
SI
DLE
DCI
DC2
DC3
DC4
NAK
SYN
ETB
CAN
EM
SUB
ESC
FS
GS
RS
US

040
041
042
043
044
045
046
047
050
051
052
053
054
055
056
057
060
061
062
063
064
065
066
067
070
071
072
073
074
075
076
077

100
101
102
103
104
105
106
107
110
III
112
113
114
115
116
117
120
121
122
123
124
125
126
127
130
131
132
133
134
135
136
137

140
141
142
143
144
145
146
147
150
151
152
153
154
155
156
157
160
161
162
163
164
165
166
167
170
171
172
173
174
175
176
177

.
!

#
$
%

.&
(
)

.+
-

0
1
2
3
4
5
6
7
8
9
,

<
=

>
?

A-12

A
B

C
D
E
F
G
H
I
J '

K
L
M
N
0

P
Q
R
S
T
U
V
W

X
Y
Z
[

\
1
/\

Char.
0

a
b
c
d
e
f

g
h
i
j
k
I
m
n
0

P
q
r

s
t
u
v
w

x
y
z

{

DEL

PRELIMINARY
Table A-16

Octal, Hex, Decimal Memory Addresses

Octal

K bytes

Hex

Decimal

Octal of High Byte
8-Bit Mode

200 000
177 000
176 000
175 000
174 000
173 000
172 000
171000
170 000
167 000
166 000
165 000
164 000
163 000
162 000
161000
160 000

10000
FEOO
FCOO
FAOO
F 800
F600
F400
F 200
FOOO
EEOO
ECOO
EAOO
E 800
E600
E400
E 200
EOOO

65536
65024
64512
64 000
63488
62976
62464
61952
61440
60 928
60 416
59904
59392
58880
58368
57856
57344

N/A
376
374
372
370
366
364
362
360
356
354
352
350
346
344
342
340

52
48
44
40
36
32
28
24
20
16
12
8
4

0000
C 000
BOOO
A 000
9 000
8 000
7 000
6 000
5 000
4000
3 000
2000
1000

53248
49152
45 056
40 960
36864
32768
28672
24576
20480
16384
12288
8 192
4 096

320
300
260
240
220
200
160
140
120
100
60
40
20

EOO
COO
AOO
800
600
400
200

3584
3 072
2560
2 048
1 536
1024
512

16
14
12
IO
6
4
2

150 000
140 000
130 000
120 000
110 000
100 000
70 000
60 000
50 000
40 000
30 000
20 000
IO 000
7 000
6 000
5 000
4 000
3 000
2 000
1000

63
62
61
60
59
58
57

3
2
1

A-13

PRELIMINARY
DCTll-AA Instruction Execution Times at Maximum Operating Frequency
Tables A-I7 to A-22 list the execution times for all instructions executable by the DCT Il-AA. The
tables are organized so as to help you calculate program execution times. To do such computations, you
must first choose a system configuration and then find the columns in the tables that apply to it. Only
those execution times listed may be used. The possible system configurations are
•
•
•
•

I 6-bit mode - REFRESH on
I6-bit mode - REFRESH off
8-bit mode - REFRESH on
8-bit mode - REFRESH off

It is possible for an instruction to have varying execution times when REFRESH is on. In 8-bit mode
REFRESH is done every instruction cycle; in 16-bit mode it is done every other cycle. The refresh
cycle adds a small increment of time to the machine cycle. Addressing modes 5, 6, and 7, I/O, and trap
(two occurrences) also add time. Therefore, minimum and maximum execution times are given in REFRESH ON configurations. The program execution time is computed for REFRESH ON configurations by totaling the average execution times of the instructions used.
The following notes apply to Tables A-17 through A-22.
•

All times are in microseconds.

•

Add 0.4 j.LS for every - READY pulse that occurs during an I/O transaction.

•

Operating frequency is 7.5 MHz. Use the following formula to compute instruction execution
times (lETs) for different operating frequencies.
IET(fOP) = (7.5 MHz/fOP) * IET(7.5)
where:
IET(fOP) = Instruction Execution Time for the new frequency, fOP.
fOP = The operating frequency at which the instruction execution times are needed.
IET(7.5) = Instruction Execution Times with an operating frequency of 7.5 MHz.
These times are listed in the tables.

•

NA = Not applicable.
NOTE
The times calculated are those using revision 5.18 of
the microcode.

A-14

PRELIMINARY
Table A-17

XOR and Single-Operand Instructions
8-Bit Mode

16-Bit Mode
REFRESH

OFF

Word
lostr.

Byte
lostr.

Word
lostr.

Byte
lostr.

Instructions

Dest.
Mode

Min.

Max.

CLR(B), COM(B),
lNC(B), DEC(B),
NEG(B), ROR(B),
ROL(B), ASR(B),
ASL(B), SWAB,
ADC(B), SBC(B),
SXT, MFPS,
XOR

0
1
2
3
4
5
6
7

1.60
2.80
2.80
3.60
3.20
4.13
4.13
4.93

1.73
2.93
2.93
3.73
3.33
4.26
4.26
5.06

1.6
2.8
2.8
3.6
3.2
4.0
4.0
4.8

2.53
5.33
5.33
6.93
5.73
7.46
7.46
9.06

2.53
3.73
3.73
5.33
4.13
5.86
5.86
7.46

2.4
5.2
5.2
6.8
5.6
7.2
7.2
8.8

2.4
3.6
3.6
5.2
4.0
5.6
5.6
7.2

TST (B)

0
1
2
3
4
5
6
7

1.60
2.40
2.40
3.20
2.80
3.73
3.73
4.53

1.73
2.53
2.53
3.33
2.93
3.86
3.86
4.66

1.6
2.4
2.4
3.2
2.8
3.6
3.6
4.4

2.53
4.13
4.13
5.73
5.33
6.26
6.26
7.86

2.53
3.33
3.33
4.93
3.73
5.46
5.46
7.06

2.4
4.0
4.0
5.6
5.2
6.0
6.0
7.6

2.4
3.2
3.2
4.8
3.6
5.2
5.2
6.8

MTPS

0
1
2
3
4
5
6
7

3.20
4.00
4.00
4.80
4.40
5.33
5.33
6.13

3.33
4.13
4.13
4.93
4.53
5.46
5.46
6.26

3.2
4.0
4.0
4.8
4.4
5.2
5.2
6.0

4.13
4.93
4.93
6.53
5.33
7.06
7.06
8.66

4.0
4.8
4.8
6.4
5.2
6.8
6.8
8.4

NOTE:
XOR and single-operand instruction execution times include instruction fetch, instruction decode, operand fetch, instruction
operation, and result output (except in mode 0 and the TST(B) instruction, where there is no output).

A-IS

PRELIMINARY
Table A-18

Double-Operand Instructions

NOTE
Double Operand Execution Time = Source Mode Time + Destination Mode Time.
Source Mode Time*
16-Bit Mode
ON

REFRESH

Instructions
MOY(B), CMP(B),
ADD, SUB, BIT(B),
BIC(B), BIS(B)
BIT(B), BIC(B),
BIS(B)

Src.
Mode
0
I

2
3
4
5
6
7

8-Bit Mode
ON

Ost. Mode (0-4)

Dst. Mode (5-7)

Min.

Max.

Min.

Max.

1.20
2.00
2.00
2.80
2.40
3.33
3.33
4.13

1.33
2.13
2.13
2.93
2.53
3.33
3.33
4.13

1.33
2.13
2.13
2.93
2.53
3.46
3.46
4.26

OFF

1.2
2.0
2.0
2.8
2.4
3.2
3.2
4.0

OFF

Word
Instr.

Byte
Instr.

Word
Instr.

Byte
Instr.

2.13
3.73
3.73
5.33
4.13
5.86
5.86
7.46

2.13
2.93
2.93
4.53
3.33
5.06
5.06
6.66

2.0
3.6
3.6
5.2
4.0
5.6
5.6
7.2

2.0
2.8
2.8
4.4
3.2
4.8
4.8
6.4

*Source mode times include instruction fetch, instruction decode, and source operand fetch.

Destination Mode Timet
16-Bit Mode
REFRESH

Instructions
MOY(B), ADD,
SUB, BIC(B)
BlS(B)

CMP(B), BIT(B)

Dest.
Mode
0
I

2
3
4
5
6
7
0
I

2
3
4
5
6
7

Min.

Max.

0.4
\.6
\.6
2.4
2.0
2.8
2.8
3.6

0.4
\.6
1.6
2.4
2.0
2.8
2.8
3.6

0.4
1.2
1.2
2.0
\.6
2.4
2.4
3.2

0.4
1.2
1.2
2.0
1.6
2.4
2.4
3.2

8-Bit Mode
OFF

OFF

Word
Instr.

Byte
Instr.

Word
Instr.

Byte
Instr.

0.4
\.6
1.6
2.4
2.0
2.8
2.8
3.6

0.40
2.40
2.40
4.00
2.80
4.53
4.53
6.13

0.40
\.60
1.60
3.20
2.00
3.73
3.73
5.33

0.4
2.4
2.4
4.0
2.8
4.4
4.4
6.0

0.4
\.6
1.6
3.2
2.0
3.6
3.6
5.2

0.4
\,2
1.2
2.0
1.6
2.4
2.4
3.2

0.40
2.00
2.00
3.60
2.40
4.13
4.13
5.73

0.40
\.20
1.20
2.80
1.60
3.33
3.33
4.93

0.4
2.0
2.0
3.6
2.4
4.0
4.0
5.6

0.4
1.2
1.2
2.8
1.6
3.2
3.2
4.8

tDestination mode times include destination operand fetch, instruction operation, and result output (except in destination
mode 0 and the CMP(B) and BIT(B) instructions, where there are no outputs).

A-16

PRELIMINARY
Table A-19 Jump and Subroutine Instructions
16-Bit Mode
REFRESH

Dest.
Mode

Min.

Max.

JMP

1
2
3
4
5
6
7

2.00
2.40
2.40
2.40
2.93
2.93
3.73

2.13
2.53
2.53
2.53
2.93
2.93
3.73

JSR

1
2
3
4
5
6
7

3.60
4.00
4.00
4.00
4.53
4.53
5.33

RTS

SOB

Instructions

8-Bit Mode
OFF

OFF

Word
Instr.

Byte
Instr.

Word
Instr.

Byte
Instr.

2.0
2.4
2.4
2.4
2.8
2.8
3.6

2.93
3.33
4.13
3.33
4.53
4.53
6.13

NA
NA
NA
NA
NA
NA
NA

2.8
3.2
4.0
3.2
4.4
4.4
6.0

NA
NA
NA
NA
NA
NA
NA

3.73
4.13
4.13
4.13
4.53
4.53
5.33

3.6
4.0
4.0
4.0
4.4
4.4
5.2

5.33
5.73
6.53
5.73
6.93
6.93
8.53

NA
NA
NA
NA
NA
NA
NA

5.2
5.6
6.4
5.6
6.8
6.8
8.4

NA
NA
NA
NA
NA
NA
NA

2.80

2.93

2.8

4.53

4.4

2.40

2.53

2.4

3.33

3.2

NOTES:
I.

JMP / JSR destination mode 0 is an illegal instruction that traps to vector location 10.

JMP execution times include instruction fetch, instruction decode, operand fetch, and loading the Pc.

JSR execution times include instruction fetch, instruction decode, operand fetch, pushing the linkage register onto the
stack, and loading the Pc.

RTS execution times include instruction fetch, instruction decode, loading the PC, popping the stack, and loading the
linkage register.

SOB execution times include instruction fetch, instruction decode, decrementing the count register, testing for zero, and
branching, if necessary. (NOTE: Whether or not a branch is taken does not affect the execution time.)

A-17

PRELIMINARY
Table A-20

Branch, Trap, and Interrupt Instructions
8-Bit Mode

16-Bit Mode

OFF

Word
Instr.

Byte
Instr.

Word
Instr.

Byte
Instr.

1.6

2.53

2.4

6.66

6.4

9.73

9.6

3.20

3.33

3.2

4.93

4.8

4.40

4.53

4.4

7.13

7.0

OFF

Dest.
Mode

Min.

Max.

BR, BNE, BEQ,
BPL, BMI, BYC,
BYS, BCC, BCS,
BGE, BLT, BGT,
BLE, BHI, BLOS,
BHIS, BLO

1.60

1.73

EMT,TRAP,
BPT,IOT

6.53

RTI

RTT

REFRESH

Instructions

NOTES:
I.

Branch instruction execution times include instruction fetch, instruction decoding, doubling the offset, testing the conditions, and adding the offset to the PC if the conditions are met. (NOTE: Whether or not a branch is taken does not
affect the execution times.)

Trap instruction execution times include instruction fetch, instruction decode, pushing the PS and PC onto the stack,
loading the PC with the contents of the vector location, and loading the PS with the contents of the vector location plus
two.

Return from interrupt instruction execution times include instruction fetch, instruction decode, and popping the PC and
PS from the stack.

A-I8

PRELIMINARY
Table A-21

Miscellaneous and Condition Code Instructions
16-Bit Mode

REFRESH

8-Bit Mode
OFF

OFF

Word
Instr.

Byte
Instr.

Word
Instr.

Byte
Instr.

Instructions

Dest.
Mode

Min.

Max.

HALT

5.73

5.86

5.6

8.4

8.0

WAIT

1.60

1.73

1.6

2.43

2.4

RESET

14.60

14.73

14.6

16.53

16.4

NOP

2.40

2.53

2.4

3.33

3.2

CLC, CLY, CLZ,
CLN, CCC, SEC,
SEY, SEZ, SEN,
SCC

2.40

2.53

2.4

3.33

3.2

MFPT

2.00

2.13

2.0

2.93

2.8

NOTES:
I.
HAL T execution times include instruction fetch, instruction decode, writing the PC and PS onto stack, then loading the
PS with 340, and loading the PC with the RESTART address.
2.

WAIT execution times include instruction fetch, instruction decode, pulsing PI to sample the interrupt lines, and doing
a REFRESH cycle if REFRESH is on. [NOTE: If no interrupt lines were asserted during the PI pulse, the WAIT
instruction will cycle in a 1.2 f.ts loop pulsing PI. (If REFRESH is on the loop will be 1.33 f.ts maximum). The looping
will continue until an interrupt line is asserted and sensed by the DCT11-AAj

RESET execution times include instruction fetch, instruction decode, the assertion of - BCLR, and the writing of
DAL< 15:0> into the mode register.

NOP execution times include instruction fetch, instruction decode, and idle time.

Condition code instruction execution times include instruction fetch, instruction decode, and the setting or resetting of
the appropriate status flags in the PS.

A-19

PRELIMINARY
Table A-22

Maximum Latencies
16-Bit Mode

8-Bit Mode

Dest.
Mode

Dynamic

Static

Dynamic

Static

-CP<3:0>, -PF
(Internal vector)

15.47

15.20

22.13

21.60

- VEC, -CP<3:0>
(External vector)

15.87

15.60

22.53

22.00

DMR

3.66

3.52

4.46

4.32

WAIT Instruction
Internal vector

7.87

7.73

10.53

10.13

External vector

8.27

8.13

10.93

10.53

DMR

1.66

1.79

1.66

Active Inputs

NOTES:
These timings are given in microseconds and assume a clock frequency of 7.5 MHz.
I.

Interrupt latency is measured from the time the interrupt request is asserted either on the AI lines (in static modes) or
on the input of the AI line driver (in dynamic modes) to the time the DCTll-AA is ready to fetch the first instruction in
the interrupt's service routine. During this time the DCT1I-AA:
a)

Keeps going until a PI latches the request. (This could happen in the instruction following the request.)

Finishes the instruction that latched the request.

Executes the lACK microcode (which involves priority arbitration), issuing lACK, generating the interrupt vector
(or in the case of - VEC being asserted, reading in the external vector), pushing PSW and PC onto the stack, and
loading PC and PSW from vector and vector + 2.
I
LAST
INSTRUCTION

lACK
MICROCODE

I
I

I
I
__ A _ - I - _ B - . . . . , - - - C ----I

I:
I
I

I
I

I
~
I
I

---.
IRQ

I
I

_ _.....J'

FIRST INSTRUCTION
OF SERVICE
ROUTINE

I
I
I

L.-:

f---,
I
I
,

- _____

lACK

______

Note that the time to synchronize the IRQ and perform any external priority arbitration is not included in the interrupt
latency.
2.

DMG latency is calculated from the time DMR is valid on the input of the AI line driver to the time the DCTII-AA
asserts DMG.

WAIT instruction latencies are the maximum encountered in the instruction's execution state. These times do not include the instruction fetch or the instruction decode.

A-20

PRELIMINARY
4.

Times refer to IRQ occurring during a JSR (mode 2 or 4) EMT sequence, which is the worst case.

Times refer to DMR occurring during a MTPS (mode 0) instruction, which is the worst case.

Timings assume the DCTlI-AA is not in long bus cycle (mode register bit 1) and there are no ready slips.

A-21

16·BIT INTERNAL BUS

, , - Yo,
20-

GND

8 _ BGND
19_ PUP

~ POWER

INSTRUCTION REGISTER

CONTROL

ALU

STATUS REGISTER

1 8 - -BCLR

R6(SP)

INTERNAL
CONTROL

>
I

CONTROL

COUT

XTL 1

XTLO

AI<7:0>

{}
32-39

SEL <0>
READY SEL <1>

-RAS
-CAS

1 ~

24-25

.t}

29-31

RI -WHB
RI -WLB

DAL<15:8>

DAL <7:0>

1-7,9

10-17

27-28

MA 5577

Figure A-I

DCTII-AA, Block Diagram

"r-

:xl

--3:

z
»
:xl
-<

."
•

~
READ ADDRESS

COUT

_I_

::%J

m
r-

CPU READ TRANSACTION

s--:

READ INPUT

,'----_

z
>
::u
-<

OAL<15.0>

AI<7:0>

"RAS

-CAS

:>
I

N
+;.
PI
MODE REGISTER
11

101 X 11 1x 1X 11 I
R/-WLB
R/-WHB
NORMAL

1 = HIGH

o ~ LOW
X -=

R/-WLB
R/-WHB
DELAYED

SE L 0 IFETI
NOTE 1
NOTE 2

VAliD
OUTPUT

SFR--i

I r

_______

IRRELEVANT

~~VT~~I~

t~F- - - - - - - {

mrmmxr

~N~~~~
\

NOTE 1 ASSERTED DNLY IF READ TRANSACTION IS AN INSTRUCTION FETCH
NOTE 2 SEL 1 IS NEGATED LOW THROUGHOUT THE TRANSACTION
• THE PREVIOUS AND FOLLOWING TRANSACTIONS ARE ASSUMED TO BE READ TRANSACTIONS

Figure A-2

16-Bit Static Read

IGNORED
INPUT

IXTIID1XI

CONDITIONAL

~)=~-_~-_-_-_~I~~
MR-4703

SYMBOL

PARAMETER

FUNCTION OF tCYC

MIN/MAX

tCDE

-CAS (T.E.I to next DAL<15:0>
Address Enable
-CAS (L.E.I or Delayed Mode RM
(L.E.I to Read Data Valid
-CAS (L.E.I Set Up Time to PI (L.E.I
XTL 1, XTLO Operating Period
DAL<15:0> Address Float to
-CAS (L.E.I
DAL<15:0> Address Hold Time
from -RAS (L.E.I
DAL<15:0> Address Set Up Time
to Read Data Valid
DAL<15:0> Address Set Up Time
to -CAS (L.E.)
DAL<15:0> Address Set Up Time
to PI (L.E.I
DAL<15:0> Address Set Up Time
to -RAS (L.E.I
Input on AI<7:0> Hold Time from
PI (T.E.I
PI (L.E.I to Input on AI<7:0> Valid
PI Hold Time from -CAS (T.E.I
PI Pulse Width
PI Precharge Time
PI (L.E.I to Read Data Valid
PI (L.E.I Set Up Time to -CAS (T.E.I
PI (L.E.I Set Up Time to -RAS (T.E.I
-RAS Pulse Width
Read Data Hold Time from -CAS (T.E.)
-RAS (T.E.I to next DAL<15:0>
Address Enable
-RAS (T.E.I Hold Time from -CAS
(T.E.I
-RAS (T.E.) Hold Time from PI (T.E.I
-RAS Pre charge Time
-RAS (L.E.I to Read Data Valid
-RAS (L.E.I Set Up Time to -CAS
(L.E.I
-RAS (L.E.I Set Up Time to PI (L.E.I
DMA on SEL<O> (L.E.I Set Up Time to
-RAS (L.E.I
Fetch SE L<0> Pulse Width

(T -181 = 115 ns

min

(3T -1801 = 220 ns

max

(T -281 = 105 ns
T=133ns
o ns

min
min

(T -121 = 121 ns

min

(5T -1571 = 510 ns

max

(2T -221 = 245 ns

min

(3T -201 = 380 ns

min

(T -481 = 85 ns

min

o ns

min

(2T -1671 = 100 ns
10 ns
(2T -471 = 220 ns
(4T -331 = 500 ns
(2T -1761 = 91 ns
(2T -751 = 192 ns
(2T -141 = 281 ns
(4T -351 = 568 ns
o ns
(T -1181 = 15 ns

max
min
min
min

tCRD
tcsp
tCYC
tDFC
tDHR
tDRD
tDSC
tDSP
tDSR
tlHP

:>
I

tlSP
tPHC
tPIP
tpPR
tpRD
tpsc
tpSR
tRAS
tRDC
tRDE
tRHC
tRHP
tRPR
tRRD
tRSC
tRSP
tSFR
tSSF

min

max
min
min
min
min

min

50 ns

min

10 ns
(2T -1201 = 147 ns
(4T -1281 = 405 ns
(T+ 101 = 143ns

min

min
max
min

(2T + 101 = 277 ns
(2T -231 = 243 ns

min
min

(3T -381 = 362 ns

min

"'D
::xJ

1: Add T ns if in long bus cycle mode, then if RDY slips are initiated, add H*T ns, where:
T = l/fop, H = number of RDY pulses times 3 if mode = normal, times 4 if mode = long bus cycle.
MR-5581

»
::xJ
-<

"tJ

:xl

'I:

.+.

DAL<lS,O>

•

ADDRESS

I---'DHN
AI<7,O>

r---

I---tWHR-

'RAS
tRHC_
tRHP
tpSR

~'RSC~
'DSC~

~) XI)
I-

'IH~

tRSP

'CSR
tCAS

'CPR

-'CSP

(

DMA REDUEST

-tDHR-

RAS

:xl

'WSR

-'RWD

-tNSR ....

tRPA

DATA OUT

)))))))))))): :(((((((I~ ((((((((( ((((((( ((( (( (((((;
-tDSR~

WRITE OUTPUT

J '-J

CDUT

-s:
-l>Z

CPU WRITE TRANSACTION
WRITE ADDRESS

f---

CAS

t~'NHR.

I-

-'WHC--

tpsc_

I+-'ISP~

-tNHC-'WHP-r-

IV
0\

tDSP

>--'WDP

tNM]

tpHC-

tCWD I---

twsp

>tNSP
t

HIGH
LOW
X

NMP

twsc

SEL<l"O> NOTE 1
NOTE L

MODE REGISTER

[OJYEP1!B

tNSC

R/-WHB
R/-WLB
DELAYED

tpSN

tpPR

R/-WHB
R/-WLB
NORMAL

-'NHP~

tplP

SEL 0 AND SEL 1 ARE ASSERTED LD THROUGHOUT THE TRANSACTION.
, THE PREVIOUS AND FOLLOWING TRANSACTIONS ARE ASSUMED TO BE WRITE TRANSACTIONS.

IRRELEVANT

VALID
OUTPUT

x:::::::r.

~UVT~~'~

mrmmxr

VALID
INPUT

IGNORED
INPUT

lXITIDlXI

CONOI llONAL

~): ~-_-_-_-_-_~.~~
MR 4704

Figure A-3

16-Bit Static Write

SYMBOL

PARAMETER

FUNCTION OF tCYC

MINIMAX

SYM80L

PARAMETER

FUNCTION OF tCye

MINIMAX

tCAS
tCPR
tcsp

-CAS Pulse Width
-CAS Precharge Ti me
-CAS IL.E.) or Delayed Mode RM
IL.E.) Set Up Time to PI IL.E.)
-CAS IL.E.! Set Up Time to
-RAS IT.E.)
-CAS IL.E.) or Delayed Mode RNi
I L.E.) to Write Data Valid
XTL 1, XTLO Operating Period
DAL<15:0> Address Hold Time
from Normal Mode RiW I L.E.)
DAL<15:0> Address Hold Time
from -RAS I L.E.)
DAL<15:0> Address Set Up Time to
-CAS IL.E.! or Delayed Mode
RiW IL.E.)
DAL <15:0> Address Set Up Time
to PI IL.E.)
DAL<15:0> Address Set Up Time to
-RAS IL.E.)
Input on AI<7:0> Hold Time from
PIIT.E.!
PI IL.E.) to Input on AI<7:0> Valid
Normal Mode RM Hold Time from
-CAS IT.E.)
Normal Mode RM Hold Time from
PI IT E.)
Normal Mode RM Hold Time from
RAS IT.E.)
Normal Mode RM Pulse Width
Normal Mode RM Reoovery Time
Normal Mode RM Set Up Time to
-CAS IL.E.!
Normal Mode RM Set Up Time to
PI IL.E.)
Normal Mode RNi Set Up Time to
-RAS IL.E.!
PI Hold Time from -CAS IT.E.) or
Delayed Mode RM IT.E.)
PI Pulse Width
PI Precharge Time
PI IL.E.! Set Up Time to -CAS IT.E.)
or Delayed Mode RM IT.E.)
PI IL.E.)2,et Up Time to Normal
Mode RfW IT.E.!
PI IL.E.) Set Up Time to -RAS IT.E.!

13T -90) = 310 ns
13T -5) = 395 ns
IT -28) = 105 ns

min
min
min

tRAS
tRHC

14T + 35) = 568 ns
50 ns

min
min

13T -40) = 360 ns

min

10 ns
12T -120) = 147 ns
IT + 10) = 143 ns

min
min
min

80 ns

max
min
min

12T + 10) = 277 ns
12T + 4) = 270 ns
IT -83) = 50 ns
IT -28) = 105 ns

min

T = 133 ns
12T -20) = 247 ns
IT-12) = 121 ns

min

12T -22) = 245 ns

min

tWHP
tWHR

IT -88) = 45 ns
IT -118) = 15 ns

min
min

13T -20) = 380 ns

min

twsc
twsp
tWSR

-RAS Pulse Width
-RAS IT.E.) Hold Time from -CAS
IT.E.) or Delayed Mode RM IT.E.)
-RAS IT. E.) Hold Time from PI IT.E.)
-RAS Precharge Time
-RAS IL.E.) Set Up Time to -CAS
IL.E.) or Delayed Mode RfW IL.E.)
-RAS IL.E.) Set Up Time to PI IL.E.!
-RAS IL.E.) to Write Data Valid
Write Data Set Up Time to PI IL.E.)
Write Data or SAL<15:8> Hold Time
from -CAS IT.E.) or Delayed Mode
RNi ITE.)
Write Data Hold Time from PI IT.E.)
Write Data or SAL<15:B> Hold Time
from -RAS IT.E.)
Write Data Set Up Time to -CAS IT.E.!
Write Data Set Up Time to PI IT.E.)
Write Data Set Up Time to -RAS IT.E.)

13T -150) = 250 ns
(3T -110) 7'J0 ns
13T -55) = 345 ns

min
min
min

tCSR
tCWD
tCYC
tDHN
tDHR
tDSC

tDSP
tDSR
tlHP
tlSP
tNHC

N
-...I

tNHP
tNHR
tNMP
tNMR
tNSC
tNSP
tNSR
tPHC
tplP
tpPR
tpsc
tPSN
tPSR

IT -48) = 85 ns

min

o ns

min

12T -167) = 100 ns
IT -32) = 101 ns

min

IT -43) = 90 ns

min

IT -108) = 25 ns

min

16T -66) = 734 ns
12T -37) = 230 ns

min
min
min

13T -45) = 355 ns

min

IT -78) = 55 ns

min

10 ns

min

12T -47) = 220 ns
14T -33) = 500 ns
12T -75) = 192 ns

min
min
min

13T -90) = 310 ns

min

12T -14) = 281 ns

min

o ns

tRHP
tRPR
tRSC
tRSP
tRWD
tWDP
tWHC

max
min
min

max

."
:Jl

r3:-

-z

1: Add T ns if in long bus cycle mode, then if RDY slips are initiated, add HOT ns, where:
T = l/fop, H = number of RDY pulses times 3 if mode = normal, times 4 if mode = long bus cycle.
MR-5582

:Jl

"'tJ
::0

I:
•

COUT

DAL<150>

_I"

/\~_

:\ :\\(( :\\ \( \\ \1:(

ADDRESS

tRAS

))))))))))'f/J. ~

ROW ADDRESS

COL ADDR

I-----

t--t

... tASR~
tAHR_
""':'tDSR--<O t---tDHRRPR

I----tRSCi---tRSP

-RAS

tose

\\\((((;

tASC

::0

): OC

0) @

-tCDE~

II
tRRD

r---

Z
l>

tADC 1--

INT. & DMA
REOUEST

I--'DFC

DATA IN

tORO

AI<7co>

-3-C

READ INPUT

)'j)'J))))00

m
r-

CPU READ TRANSACTION
READ ADDRESS

fADE

1--'-

tCSA
tpSR

r_tpRD_ ~

tCPR

tCRD-

fo-fo--

tRHC_
tRHP tCAS--------I

-CAS

--1

.tIHPO

tpHC~

t PSC

--<0

_tISP_

tAHC

tosp

IV
00

tPIP

tpAE_

-tAFP

--0

tpPR

I-tCSP.
MODE REGISTER
11

R/-WLB
R/-WHB
NORMAL

SEL 0 (FETI
(NOTE II
(NOTE 21
NOTE I
NOTE 2

1 '" HIGH
LOW
0

X '"

R/-WLB
R/-WHB
DELAYED

lolxlolxlxTiJ
o

~'~'m ~
____

IRRELEVANT

~~~~~T

~:VT~~t~ lXillIDITXr

~N~~I~

-r=:r

IGNORED
INPUT

IillID1XI

CONDITIONAL

~): ~ ----~-_-_~I~~

ASSERTED ONLY IN 64K MODES IF READ TRANSACTION IS AN INSTRUCTION FETCH.
SEL 1 IS ASSERTED LO THROUGH THE TRANSACTION.
• THE PREVIOUS AND FOLLOWING TRANSACTIONS ARE ASSUMED TO BE READ TRANSACTIONS.

x::::::r. -

MR-4701

Figure ;\-4

16-Bit Dynamic Read

SYMBOL

PARAMETER

tAFP

Column Address on AI<7:0>
Float to PI I L.E.I
Column Address on AI<7:0>
Hold Time from -CAS IL.E.I
Row Address on AI<7:0>
Hold Time from -RAS IL.E.I
Column Address on AI<7:0>
Set Up Time to -CAS I L.E.I
Row Address on AI<7:0>
Set Up T,me to -RAS IL.E.I
-CAS Pulse Width
-CAS IT.E.I to next DAL<15:0>
Address Enable
-CAS Precharge Time
-CAS IL.E.I to Read Data Valid
-CAS IL.E.! Set Up Time to PI IL.E.I
-CAS IL.E.I Set Up Time to -RAS
IT.E.I
XTLI, XTLO Operating Period
DAL<15:O>Address Float to
-CAS IL.E.I
DAL<15:0> Address Hold Time
from -RAS Il.E.1
DAL<15:0> Address Set Up Time
to Read Data Valid
DAL<15:0> Address Set Up Time
to -CAS IL.E.I
DAL<15:0> Address Set Up Time
to PI IL.E.I
DAL<15:0> Address Set Up Time
to -RAS IL.E.!
Input on AI<7:0> Hold T,me from
PI IT.E.I

tAHC
tAHR
tASC
tASR
tCAS
tCDE
tCPR
tCRD
tcsp
tCSR
tCYC
tDFC
tDHR
tDRD

>
I

1.0

tDSC
tDSP
tDSR
tlHP
tlSP
tpAE
tPHC
tplP
tpPR
tpRD
tpsc
tpSR
tRAS
tRDC
tRDE
tRHC

PI IL.E.I to Input on AI<7:0> Valid
PI IT.E.! to next AI<7:0> Address
Enable
PI Hold Time from -CAS IT.E.I
PI Pulse Width
PI Precharge Time
PI IL.E.! to Read Data Valid
PI IL.E.I Set Up Time to -CAS IT.E.I
PI IL.E.I Set Up T,me to -RAS IT.E.I
-RAS Pulse Width
Read Data Hold Time from -CAS IT.E.I
-RAS IT.E.I to Next DAL<15:0>
Address Enable
-RAS IT.E.I Hold Time from
-CAS IT.E.I

FUNCTION OF tCYC

o ns

MINIMAX
mon

IT -431 0 90 ns

mIn

IT -601 0 73 ns

mon

20 ns

mon

IT -681 065 nsl

mon

13T -901 0310 ns
IT-1Bl o 115ns

min
mon

13T -51 0 395 ns
13T -1801 0220 ns
IT -281 0 105 ns
13T -401 0 360 ns

min

T o 133ns

o ns

min
min

IT -121 0 121 ns

mon

15T -1571 0 510 ns

max

12T -221 0 245 ns

min

13T -201 0 380 ns

mon

IT -481 0 85 ns

min

o ns

min

12T -1671 0 100 ns
IT -401 0 93 ns

max

10 ns
12T -371 0 230 ns
14T -331 0 500 ns
12T -1761 0 91 ns
12T -751 0 192 ns
12T + 241 0291 ns
14T + 351 0568 ns
o ns
IT -l1BI 0 15 ns

min
mm
mIn
max
min

50 ns

mon

SYMBOL

PARAMETER

tRHP

-RAS IT.E.! Hold T,me from
PI ITE.I
-AAS Precharge Time
-RAS IL.E.I to Read Data Valid
-RAS IL.E.I Set Up Time to
-CASILEI
-RAS IL.E.I Set Up T,me to PI IL.E.I
Fetch SEL<O> IL.E.I Set Up Time
to -RAS IL.E.I
Fetch SEL<O> Pulse W,dth

tRPR
tRRD
tRSC
tRSP
tSFR
tSSF

FUNCTION OF tCYC

MINIMAX

10 ns

mon

12T -1201 0 147 ns
14T -1281 0 405 ns
IT + 101 0 143 ns

min
max
mon

12T I 101 0277 ns
IT -231 0 110 ns

min

13T -381 0 362 ns

mon

max
min
mIn

min

mon
mon

"'0

:J:J

min

mon

-3C

-----

1: Add T ns if In long bus cycle mode, then if ROY slips are initiated, add H·T ns, where:
To llfop, H 0 number of ROY pulses times 3 if mode 0 normal, times 4 if mode 0 long bus cycle.
MA·5579

-:t>Z

:J:J

"tJ
::D

*1:
COUT

.1.

L_ ___ _J\

DAL<150>

-------'x
)))))))'j

AI<70>

WRITE OUTPUT

ADDRESS.

CPU WRITE TRANSACTION
WRITE ADDRESS

m
r3:
Z
l>

,'---_

::D

DATA OUT

ROW ADDRESS

+RAS
'OSC----+-!

~I----+--++H--

'CPR

H+'WHC-t=!

I•

Jr...!-.:-

V-J

R/-WHB
R/-WLB
NORMAL

:E'NHP~

II ____

~I---_ ,
•

:Jf

'OSP
'ASC

'wHP-t---

'N:;R----+if-----1- -'.

'NS?

tewD ~

twsp

'wsc

tPHc1.

113M?

R/-WHB
R/-WLB
DELAYED

SEl <1.0> NOTE 1 .
NOTE 1,

-\--4

NHC

CAS

MODE REGISTER
11

HIGH

LOW

X -=- IRRELEVANT

VALID
OUTPUT

r=:r.

~:V~~I~

mrrmxr

VALID
INPUT

IGNORED

mm:m

INPUT

SEL 0 AND SEL 1 ARE ASSERTED LO THROUGHOUT THE TRANSACTION
• THE PREVIOUS AND FOLLOWING TRANSACTIONS ARE ASSUMED TO BE WRITE TRANSACTIONS.

\olxlolxlxll\

CONDITIONAL

~~(~·_-_-_-_-_~I~~
MA 4702

Figure A-5

16-Bit Dynamic Write

SYMBOL

PARAMETER

FUNCTION OF tCYC

MIN/MAX

SYMBOL

tCAS
tCDE

-CAS Pulse Width
-CAS (T.E.) or Delayed Mode Riiii
(T.E.) to next DAL<15:0> Address
Enable
-CAS Precharge Time
-CAS (L.E.) or Delayed Mode Riiii
(L.E.) to Read Data Valid
-CAS (L.E.) or Delayed Mode Riiii
(L.E.) Set Up Time to PI (L.E.)
-CAS (L.E.) Set Up Time to
-RAS (T.E.)
XTL 1. XTLO Operating Period
DAL<15:0> Address Float to -CAS
(L.E.) or Delayed Mode Riiii (L.E.)
DAL<15:0> Address Hold Time from
Normal Mode Riiii (L.E.)
DAL<15:0> Address Hold Time from
-RAS (L.E.)
DAL<15:0> Address Set Up Time to
Read Data Valid
DAL<15:0> Address Set Up Time to
-CAS (L.E.) or Delayed Mode
Riiii (L.E.)
DAL<15:0> Address Set Up Time to
PI (L.E.)
DAL<15:0> Address Set Up Time to
-RAS (L.E.)
Input on AI<7:0> Hold Time from
PI (T.E.)
PI (L.E.) to Input on AI<7:0> Valid
Normal Mode Riiii Hold Time from
-CAS (T.E.)
Normal Mode RiW Hold Time from
PIIT.E.)
Normal Mode RiW Hold Time from
-RAS IT.E.)
Normal Mode RiW Pulse Width
Normal Mode Riff. Recovery Time
Normal Mode R/W Set Up Time to
Read Data Valid
Normal Mode RiW Set Up Time to
-CAS IL.E.)
Normal Mode Riiii Set Up Time to
PI IL.E.)
Normal Mode Riiii Set Up Time to
-RAS (L.E.)
PI Hold Time from -CAS IT.E.) or
Delayed Mode RiW IT.E.)

(3T -90) ~ 310 ns

min
min

tPIP
tpPR
tpRD
tpsc

tCPR
tCRD
tcsp
tCSR
tCYC
tDFC
tDHN
tDHR
tDRD
tDSC

tDSP

>
I

W
W

tDSR
tlHP
tlSP
tNHC
tNHP
tNHR
tNMP
tNMR
tNRD
tNSC
tNSP
tNSR
tpHC

(T-18)~115ns

PARAMETER

PI Pulse Width
PI Precharge Time

PI I L.E.} to Read Data Valid
PI (L.E.) Set Up Time to -CAS IT.E.}
or Delayed Mode Rffl IT.E.}
PI I L.E.} Set Up Time to Normal Mode
Rffl IT.E.)
PI IL.E.) Set Up Time to -RAS IT.E.}
-RAS Pulse Width

FUNCTION OF tCYC

MIN/MAX

12T -47} = 220 ns
14T -33) ~ 500 ns
12T -176) ~ 91 ns
(2T -75) ~ 192 ns

min

max
min

13T -gO} ~ 310 I1S

min

12T --14} = 281 ns
14T + 35} ~ 568 ns

min
min

min

(3T -5) ~ 395 ns
(3T -180) ~ 220 ns

max

tpSN

(T -28) ~ 105 ns

min

tpSR
tRAS

(3T -40) ~ 360 ns

min

tRDC

Read Data Hold Time from -CAS
IT.E.) or Delayed Mode RiW IT. E.}

o ns

min

T ~ 133 ns
o ns

min
min

tRDE

IT-118)~15ns

min

50 ns

(2T -201 ~ 247 ns

min

(T -12) ~ 121 ns
(5T-157) ~510ns

max

tRHP
tRPR
tRRD
tRSC

10 ns
12T -120} ~ 147 ns
(4T -128) ~ 405 ns
(T + 10) ~ 143 ns

mIn

min

(2T -22) ~ 245 ns

min

tRSP

-RAS IT.E.) to next DAL<15:0>
Address Enable
-RAS IT.E.) Hold Time from -CAS
IT.E.) or Delayed Mode Rffl (T.E.)
-RAS IT.E.) Hold Time from PI IT.E.)
-RAS Precharge Time
-RAS IL.E.) to Read Data Valid
-RAS IL.E.) Set Up Time to -CAS
(L.E.) or Delayed Mode Rffl IL.E.}
-RAS IL.E.) Set Up Time to PI IL.E.)

(2T + 10) ~ 277 ns

min

tSFR

DMA on SE L <0> I L.E.) Set Up

12T -23) ~ 243 ns

min

tRHC

(3T -20) ~ 380 ns

min

(T -48) ~ 85 ns

min

o ns

min

(2T -167) ~ 100 ns
IT -32) ~ 101 ns

max

IT -43) ~ gO ns

min

IT -108) ~ 2511s

min

16T -66) ~ 734 ns

min

o ns

min

(5T -148) ~ 519 ns

max

12T -37) ~ 230 ns

min

13T -45) ~ 355 ns

min

(T -78) ~ 55 ns

min

10 ns

min

max
min

Time to -RAS I L.E.)

tSSF
tWHC

SE L<0> Pulse Width
Write Data or SAL<15:8> Hold Time
from -CAS (T.E.) or Delayed Mode
Rffl (T.E.)

13T -38) ~ 362 ns
IT -28) ~ 105 ns

min
min

tWHR

Write Data or SAL<15:8> Hold Time
from -RAS (T.E.)

(T -118) ~ 15 ns

min

::u
m'
r-.

1: Add T ns if in long bus cycle mode, then if RDY slips are initiated, add H*r ns, where:
T ~ l/fop. H ~ number of RDY pulses times 3 if mode ~ normal. times 4 if mode ~ long bus cycle.
MA·5585

-»3:z
::u
-<

.rr.

CPU WRITE TRANSACTION (LO B Y T E I : r

_I_

o----WRITE ADDRESS

COUT

DAL<IS,S>
SAL<IS,S>

DAL<7,0>

]

(((I )))

!\L.....-_ _
C

LOBYTEDATA

HI BYTE OF ADDRESS

LO BYTE OF ADDRESS

---I

r--

HI BYTE DATA

............

1_
_

AI<7,O>

))))): ((((((((((((((((((

((( ((((((

~(((((((

DMAREQUEST ) ) ) ) ) ) )

I--'DHR---O

-RAS

-CAS

'RWD

i-'WHR-

f.'NHR'
' C S R - - - - + - I I r - _ - + + -_ __

I--

'RHP -

'RHC~

I--

'wsc

I-'WHC -

'DSC

I+I--'NHC~

'PSN ___~~_____~

'PIP

'~'WHP-

I- 'WDP

rI-- 'NHP-

1-------- 'PPR

'CWD-

t--

-4..+-___

' P S C - - - - I I r......_ _

'CAS

t--

'PHC -

R/-WLB (-WTI
NORMAL

--lJ ~ 'D~~SC
p . . .----

Ir\

'WSP

f '---

'NSP - - - - - - - - + - - - - 1

1------------------1--- 'NMP

~ _ _ _ _ II

SEL<1-0> NOTE 2
NOTE 1
NOTE 2·
NOTE 3
NOTE 4.

~)))))\:((((((

DMAREQUEST
'WSR

\~------~--~-4------------------__~
' ~----------+_~---H::::::~:-'P-S-R~--~~
---4---------.....,j
__~~d:::H:::::::~~::~!t~----~----. . . tCPR------l--1\~l...-l-------~
1 - - - - - - - - - 'DSP -

R/-WLB (-WTI
DELAYED

'--'IHP

I----'RSC~

i--'csp-

I..;.J
..j::..

~(((((((((([(((((((K( (((((((

I-'NSR~

I--

I-- 'ISP~

:((((((
'RPR

f.-'DSR--q."""'RSP 'DFC-,pl.-------I-----+--+-'RAS

__-+___'""

m
r-

WRITE OUTPUT------.!-·

HI BYTE OF ADDRESS

LO BYTE OF ADDRESS

"I-

WRITE ADDRESS

CPU WRITE TRANSACTION (HI BYTEI

WRITE OUTPUT

."
:ll

11
MODE
REGISTER

RI -WHB IS ASSERTED HI THROUGHOUT THE TRANSACTION
SELO AND SEll ARE ASSERTED LO THROUGHOUT THE TRANSACTION
ASSERTED ONLY IN 64K MODE, IF THE WRITE TRANSACTION IS AN INSTRUCTION FETCH
SHOWN IS A WORD WRITE (2 TRANSACTIONSI.

* THE PREVIOUS AND FOLLOWING TRANSACTIONS ARE ASSUMED TO BE WRITE TRANSACTIONS

Figure A-7

[}IX 11 I X I X I 1I
, '" HIGH

0" LOW
X-= IRRELEVANT

8-Bit Static Write

VALID
OUTPUT

r=J.

I N V A LID TVTTf'1\\rrVT
OUTPUT ~

~N~~I~~

IGNORED
INPUT

rfJ1JillJJ.

- ....... ------ ..... -

CONDITIONAL _ ... JL

______ } ' - _

-Z

:ll

SYMBOL

PARAMETER

FUNCTION OF tCYC

MIN/MAX

tCAS
tCPR
tcsp

-CAS Pulse Width
-CAS Precharge Time
-CAS Il.E.) or Delayed Mode R/W
Il.E.) Set Up Time to PI IL.E.)
-CAS IL.E.) Set Up Time to
-RAS IT.E.!
-CAS IL.E.) or Delayed Mode Rm
IL.E. to Write Data Valid
XTL 1. XTLO Operating Period
DAL<15:0> Address Float to -CAS
IL.E.) or Delayed Mode Rm Il.E.)
DAL<15:0> Address Hold Time
from Normal Mode RNi Il.E.)
DAL<15:0> Address Hold Time
from -liAS Il.E.)
DAL<15:0> Address Set Up Time to
-CAS I L.E.) or Delayed Mode
RNi IL.E.)
DAL<15:0> Address Set Up Time to
PI IL.E.)
DAL<15:0> Address Set Up Time to
-RAS Il.E.)
Input on AI<7:0> Hold Time from
PIIT.E.)
PI Il.E.) to Input on AI<7:0> Valid
Normal Mode RNi Hold Time from
-CAS IT.E.)
Normal Mode RNi Hold Time from
PI IT.E.)
Normal Mode RNi Hold Time from
-RAS IT.E.)
Normal Mode RNi Pulse Width
Normal Mode Rm Recovery Time
Normal Mode Rm Set Up Time to
-CAS IL.E.)
Normal Mode RNi Set Up Time to
PI Il.E.)
Normal Mode Rm Set Up Time to
-RAS Il.E.)
PI Hold Time from -CAS IT.E.) or
Delayed Mode RNi IT.E.)
PI Pulse Width
PI Precharge Time
PI Il.E.) Set Up Time to -CAS IT.E.)
or Delayed Mode RNi IT.E.)

13T -90) = 310 ns
13T -5) = 395 ns
IT -28) = 105 ns

min

13T -40) = 360 ns

min

80 ns

max

T = 133 ns
o ns

min
min

12T -20) = 247 ns

min

IT -12) = 121 ns

min

12T -22) = 245 ns

min

tCSR
tCWD
tCYC
tDFC
tDHN
tDHR
tDSC

tDSP
tDSR
tlHP

:>
I

tlSP
tNHC

W
Vl

tNHP
tNHR
tNMP
tNMR
tNSC
tNSP
tNSR
tpHC
tplP
tpPR
tpsc

mIn

SYMBOL

PARAMETER

FUNCTION OF tCYC

MIN/MAX

tpSN

13T -90) = 310 ns

min

tpSR
tRAS
tRHC

PI IL.E.) Set Up Time to Normal
Mode RNV IT. E.)
PI I L.E.) Set Up Time to -RAS IT.E.)
-RAS Pulse Width
-RAS IT.E.) Hold Time from -CAS
IT.E.) or Delayed Mode RNV IT.E.)
-RAS IT.E.) Hold Time from PI IT.E.)
-RAS Pre charge Time
-RAS Il.E.) Set Up Time to -CAS
Il.E.) or Delayed Mode RmlL.E.)
-RAS IL.E.) Set Up Time to PI IL.E.)
-RAS I L.E.) to Write Data Valid
Write Data Set Up Time to PI Il.E.)
Write Data or SAL<15:8> Hold Time
from -CAS IT.E.) or Delayed Mode
Rm IT.E.)
Write Data Hold Time from PI IT.E.)
Write Data or SAL<15:8> Hold Time
from -RAS IT.E.)
Write Data Set Up Time to -CAS IT.E.)
Write Data Set Up Time to PI (T.E.)
Write Data Set Up Time to -RAS (T.E.)

12T -14) = 281 ns
14T + 35) = 568 ns
50 ns

min
min
min

10 ns
12T -120) = 147 ns
IT+ 10) = 143ns

min

12T + 101 = 277 ns
12T + 4) = 270ns
IT -83) = 50 ns
IT -28) = 105 ns

min

tRHP
tRPR
tRSC
tRSP
tRWD
tWDP
tWHC

tWHP
tWHR
13T -20) = 380 ns

min

IT -48) = 85 ns

min

o ns

min

12T -167) = 100 ns
IT -32) = 101 ns

max

IT -43) = 90 ns

min

IT --108) = 25 ns

min

16T -66) = 734 ns

o ns

min
min

12T -37) = 230 ns

min

13T -45) = 355 ns

min

IT -78) = 55 ns

min

10 ns

min

12T -471 = 220 ns
14T -33) = 500 ns
12T -75) = 192 ns

min

2
2
2

twsc
twsp
tWSR

min
min

max
min

min
!

IT -88) = 45 ns
IT -118) = 15 "s

min
min

(3T - 150) = 250 ns
(3T - 110) = 290 ns
(3T -55) = 345 ns

min
min

min

""0

::D

min

-r-3:
-z

1: Add T n5 If in long bus cycle mode, then if ROY slips are initiated, add H·r ns, where:
T:::: 1 ffop. H = number of RDY pulses times 3 if mode:::: normal, times 4 if mode:::: long bus cycle.

2: Add 4T for each READY pulse.
MR 5586

::D

*t
__~I\
r

COUT

DAL<158>
SAL<158>

+
+

CPU READ TRANSACTION (LO BYTEI

_I_

READ ADDRESS

READ INPUT

)

'"'0

CPU READ TRANSACTION (HI B Y T E ' : I

_I_

READ ADDRESS

I\~

HI BYTE OF ADDRESS

:::0

READ INPUT------4-"l·

____

x..-

HI BYTE OF ADDRESS

I'WHC~

r((( ~((( :(((((((((

LO BYTE OF ADDRESS

LO BYTE DATA

))j~

INT & DMA
REOUEST

LO BYTE OF ADDRESS

K(C(((((:(((((((((

1):

HI BYTE DATA

'ORO

AI<70>

JJJ1. ~

ROW ADDRESS

I"'"

i---tASR4

COL ADDR

)

:((((((((

I--tAH~~
i---'DHR-r-

tRRD

I----tRSC Ir----'RSP
tOFC

r----

t--

'~;oei's~A

) f))'

'eSR

tRHC~

tAHC ~
!""-'CSP

t--

-CAS

tDSP

tRHP

'CRDI-'PRDI--t,SP-

IpSC

rJ- 'CDE
t'HP '--

f--tAFP

-1-

tosc

tpPR

tPIP

'PSN
tCAS

I-tPAE-

'CPA

-tNSRtNRD

R/-WHB I-RDI
NORMAL

: ( ( ( ( ( ( ( ( ( ((

tRDE

tpSR

I-

COL ADDR

tRAS

Io-tASC.

W
0\

ROW ADDRESS

tRPR_

I--tDSR··RAS

'PHC-

I-

-'DHN
tNMR

tNHP_
I--tNHR4

tNMP

R/-WHBI-RDI
DELAYED

r-tSFR~
SEL 0

trr ....
!;:----oo
r

"t---------------

i I\,

NOTE 2
NOTE 3

NOTE ,NOTE 2
NOTE 3
NOTE 4

R/-WLB IS ASSERTED HI THROUGHOUT THE TRANSACTION
SEL' IS ASSERTED LO THROUGHOUT THE TRANSACTION
ASSERTED DNL YIN 64K MODES, IF READ TRANSACTION IS AN INSTRUCTION FETCH
SHOWN IS A WORD READ (2 READ TRANSACTIONSI
THE PREVIOUS AND FOLLOWING TRANSACTIONS ARE ASSUMED TO BE READ TRANSACTIONS

~~g'~TER I ' I X I 0 I X I X I' I
1 = HIGH
OoLOW
X= IRRELEVANT

-r=r..

IGNORED
INPUT

INVALID
OUTPUT ~

CONDITIONAL

VALID
OUTPUT

lfJJIilljJ
_,,.. ______ 'r_
J,- ______ ~I .... -

_ .i

~N~~I~~
MR 4705

Figure ;\-H

H-Bit Dynamic Read

-Z

l>
:::0

.tWHR~

DAL<70>

m
r3:

SYMBOL

PARAMETER

tAFP

Column Address on AI<7:0>
Float to PI Il.E.1
Column Address on AI<7:0>
Hold Time from ~CAS Il.E.1
Row Address on AI<7:0>
Hold Time from ~RAS Il.E.1
Column Address on AI<7:0>
Set Up Time to ~CAS Il.E.1
Row Address on AI<7:0>
Set Up Time to ~RAS Il.E.1
~CAS Pulse Width
~CAS IT.E.I or Delayed Mode RiW
IT.E.I to next DAl<15:0>
Address Enable
-CAS Precharge Time
~CAS I l.E.! or Delayed Mode RiW
Il.E.1 to Read Data Valid
~CAS I l.E.1 or Delayed Mode RiW
Il.E.1 Set Up Time to PI Il.E.1
~CAS Il.E.1 Set Up Time to
~RAS IT.E.!
XTll, XTlO Operating Period
DAl<15:0> Address Float to ~CAS
Il.E.1 or Delayed Mode RiW Il.E.1
DAl<15:0> Address Hold Time from
Normal Mode RIW Il.E.1
DAl<15:0> Address Hold Time from
~RAS IL.E.I
DAl<15:0> Address Set Up Time to
Read Data Valid
DAl<15:0> Address Set Up Time to
~CAS Il.E.1 or Delayed Mode
RiW Il.E.1
DAl<15:0> Address Set Up Time to
PlllE.1
DAl<15:0> Address Set Up T,me to
~RAS IL.E.I
Input on AI <7:0>Hold Time from
PI ITEI
PI IL.E.I to Input on AI<7:0> Valid
Normal Mode RiW Hold T,me from
PI IT.E.I
Normal Mode RiW Hold Time from
~RAS IT.E.I
Normal Mode RiW Pulse Width

tAHC
tAHR
tASC
tASR
tCAS
tCDE

tCPR
tCRD
tcsp
tCSR
tCYC
tDFC
tDHN

tDHR

-.J

tDRD
tDSC

tDSP
tDSR
tlHP
tlSP
tNHP
tNHR

tNMP
tNMR
tNRD

Normal Mode RiW.... Recovery Time

Normal Mode RIW Set Up Time to
Read Data Valid

FUNCTION OF tCYC

MINIMAX

SYMBOL

PARAMETER

o ns

min

tNSR

Normal Mode RIW Set Up Time to
~RAS Il.E.1

IT ~781 = 55 m

m,n

IT ~431 c 90 ns

min

tpAE

IT ~401 = 93 ns

mIn

IT ~601 = 73 ns

min

tpHC

10 ns

m,n

20 ns

mIn

tPIP
tpPR
tpRD
tpsc

PI IT.E.I to next AI<7:0>
Address Enable
PI Hold Time from ~CAS IT.E.I or
Delayed Mode RM IT.E.I
PI Pulse Width

12T -471 - 2201ls
14T ~331 = 500 ns
12T --1761 = 91 ns
12T ~751 = 192 ns

min

13T -901 - 310 ns

min

12T 14) - 281 ns
14T + 351 = 568 ns
o ns

mIn
min
mIn

IT ~ 1181 = 15 ns

mIn

50 ns

min

10 ns
12T ~1201 = 147 ns
14T ~ 1281 = 405 ns
IT + 101 = 143 ns

min
min
max
min

12T + 101 = 277 ns
12T ~231 = 243 ns

mIn

13T ~381 = 362 ns
IT ~281 - 105 ns

mIn
min

IT ~1181 = 15 ns

m,n

IT -831 - 50 ns

mIn

13T ~901 = 310 ns
IT~181=115ns

mIn
min

13T ~51 = 395 ns
13T ~1801 = 220 ns

min
max

tpSR
tRAS
tRDC

IT ~281 = 105 ns

min

tRDE

13T ~401 = 360 ns

min

tRHC
tRHP
tRPR
tRRD
tRSC

tpSN

T = 133 ns

mIn

o ns

min

12T ~201 = 247 ns

min

IT~121=121ns

mIn

15T ~1571 = 510 ns

max

12T ~221 = 245 ns

m,n

tSSF
tWHC

13T ~201 = 380 ns

min

tWHR

IT ~481 = 85 ns

min

o ns

min

tRSP
tSFR

12T ~ 1671 = 100 ns
IT ~211 = 112 ns

max
TIln

IT ~1081 = 25 ns

min

16T -661 = 734 ns

min

o ns

min
max

15T ~ 1481 = 519 ns
-_ .. _.. _ - - - -

PI Precharge Time

PI Il.E.1 to Read Data ValId
PI Il.E.1 Set Up T,me to ~CAS IT.EI
or Delayed Mode R/W IT.E.I
PI~.E.I Set Up Time to Normal Mode
RIW IT.E.I
PI Il.E.1 Set Up Time to ~RAS ITE.I
~RAS Pulse W,dth
Read Data Hold Time from ~CAS
IT.E.I or Delayed Mode RiW IT.E.I
~RAS IT.E.I to next DAl<15:0>
Address Enable
~RAS IT.E.I Hold Time from ~CAS
IT.E.lor Delayed Mode RiW IT.E.I
~RAS IT.E.I Hold Time from PI IT.E.I
-RAS Precharge Time
~RAS Il.E.1 to Read Data Valid
~RAS Il.E.1 Set Up Time to ~CAS
Il.E.1 or Delayed Mode RiWlL.E.1
~RAS Il.E.1 Set Up Time to PI Il.E.1
DMA on SEl<O> Il.E.1 Set Up Time
to~RAS Il.E.1
SEl<O> Pulse Width
Write Data or SAl<15:8> Hold Time
from ~CAS IT.E.I or Delayed Mode
RiW ITE.I
Write Data or SAl<15:8> Hold Time
from ~RAS IT.E.I

FUNCTION OF tCYC

MINIMAX

min
max
min

min

"'tJ
::%J

m
r-

-31:
-z

---

Add T ns if in long bus cycle mode, then If RDY slips are initiated, add H*T ns, where:

»
::%J

T == l/fop, H = number of RDY pulses times 3 if mode = normal, times 4 if mode = long bus cycle.
2: Add 4T for each READY pulse.
3: Add 3T if multiple DMA cycles are granted.
MA 5583

'"tJ

.r
COUT

DAL<15,B>

:1:

CPU WRITE TRANSACTION (LO BYTE)

-I-

"r-----WRTE ADDRESS

WRITE OUTPUT

--l

DAL<7,O>

~
I

AI<7,O> _

HI BYTE OF ADDRESS

LOBYTEOFADDRESS

ROWADDRESS

(((O))X
~~~R

-RAS

____
L

X ~~~R

ROW ADDRESS

HI BYTE DATA

~\\\\(\\((

'RPR_ ~'RWD

DMAREQUEST

I--'RSC
'DFC -

'ASC _

'AFP~

'CSR - - - - - . . . . ; ir---+-I----

I 'PSR - - - -.....

I---"SP~

___+-__________,I--'csP-

I-'NHR.

'RAS
-

'RHP'RHC_

'CWD

'IHP-~

f)>»)X~
I--'WHR~

'WSR

_'NSR_

I""'AHC~

LO BYTE OF ADDRESS

'WSC

I--

I--'WHC-

I+___

'DSC

'PSC-----lir-_ _ _ _

W
00

~+---_+-f----'CPR

-CAS

'CAS

1-------'DSP---++::::::::t1:::::::::'i;'P~,P;:::::::::.~ I--'PAE~,
----PPR

'NHCPSN

-----11+------1

f- 'WDP

1l:::::WHP{
'NHP-

'PHC-

R/-WLB (-WTI
NORMAL

R/-WLB (-WTI
DELAYED

~-----+------------~~-+~
t-_'DHN----ooj

---u

[00-----' NSC

~----~---'WSP----+t-.,

>-- 'NMR

/1111-----'NSP

~1::::::::::::::::~::~'~N~M;P:::::::::::::::t::::::~,

SEL<l :0> NOTE 2
NOTE 1,
NOTE 2NOTE 3,
NOTE 4

R/-WHB IS ASSERTED HI THROUGHOUT THE TRANSACTION
SEL 0 AND SEL 1 ARE ASSERTED LO THROUGHOUT THE TRANSACTION
ASSERTED ONLY IN 64K MODES IF THE WRITE TRANSACTION ISAN INSTRUCTION FETCH
SHOWN IS A WORD WRITE (2 TRANSACTIONS)
• THE PREVIOUS AND FOLLOWING TRANSACTIONS ARE ASSUMED TO BE WRITE TRANSACTIONS

MODE
REGISTER

1, I xI IxI xi' I
0

HIGH
LOW

X '" IRRELEVANT

Figure A-9

8-Bit Dynamic Write

~~~~~T -r::::::£

:~~~TREO lXillillXI

- .. ,....------ ..... ~NUVT~~I~ ~ CONDITIONAL _.}L _____ .}.... _

~N~~I~~

-l>Z
r-

f))))): ,X

DMAREQUEST

I\~
HI BYTE OF ADDRESS

[.o-'ASR_ I - - ' D H R I--'AHRI--'DSR_ I--'RSP

OUTPUT-------t~

LOBYTEDATA

~((((((((i

WRITE

SAL<15,B>

_I.

WRITE ADDRESS

__~I\

CPU WRITE TRANSACTION (HI BYTE)

-.-

(
SYMBOL
tAFP
tAHC
tAHR
tASC
tASR
tCAS
tCPR
tcsP
tCSR
tewD
tCYC
tDFC

tDHN
tDHR

:>
I

\,0.)

tosc

\0
tDSP
tDSR
tlHP
tlSP
tNHC
tNHP
tNHR
tNMP

PARAMETER
Column Address on AI<7:0>
Float to PI (L.E.)
Column Address on AI<7:0>
Hold Time from -CAS (L.E.)
Row Address on AI<7:0>
Hold Time from -RAS (L.E.)
Column Address on AI<7:0>
Set Up Time to -CAS (L.E.)
Row Address on AI<7:0>
Set Up Time to -RAS (L.E.)
-CAS Pulse Width
-CAS Precharge Time
-CAS (L.E.) or Delayed Mode
Rm (L.E.! Set Up Time to PI (L.E.)
-CAS (L.E.! Set Up Time to
-RAS (T.E.)
-CAS (L.E.) or Delayed Mode
RNi (L.E.) to Write Data Valid
XTL 1, XTLO Operating Period
DAL<15:O>Address Float to
-CAS (L.E.) or Delayed Mode
RNi (L.E.)
DAL<15:0> Address Hold Time
from Normal Mode Rm (L.E.)
DAL<15:0> Address Hold Time
from -RAS (L.E.)
DAL<15:0> Address Set Up
Time to -CAS (L.E.) or
Delayed Mode RNi (L.E.)
DAL <15:0> Address Set Up
Time to PI (L.E.)
DAL <15:0> Address Set Up
Time to -RAS (L.E.)
Input on AI <7:0> Hold Time
from PI (T.E.)
PI (L.E.) to Input on
AI <7:0> Valid
Normal Mode RNi Hold Time
from -CAS (T.E.)
Normal Mode RNi Hold Time
from PI (T.E.!
Normal Mode RNi Hold Time
from -RAS (T.E.)
Normal Mode RNi Pulse Width

FUNCTION OF tCYC

o ns

MINIMAX
min

(T -43) = 90 ns

min

(T -60) = 73 ns

min

20 ns

min

(T -83) = 50 ns

min

(3T -90) = 310 ns
(3T -5) = 395 ns
(T -28) = 105 ns

min
min
min

(3T -40) = 360 ns

min

80 ns

max

SYMBOL
tNMR
tNSC
tNSP
tNSR
tpAE
tPHC
tplP
tpPR
tpsc
tPSN
tpSR

T = 133 ns
o ns

min
min

(21 -20) = 247 ns

min

tRHP

(T -12) = 121 ns

min

tRPR
tRSC

(2T -22) = 245 ns

min

tRAS
tRHC

tRSP
(3T -201 = 380 ns

min

tRWD
tWDP

(T -48) = 85 ns

min

o ns

min

(2T -167) = 100 ns

max

tWHP

IT -32) = 101 ns

min

tWHR

(T -43) = 90 ns

min

twsc

(T -108) = 25 ns

min

twsp
tWSR

(6T -66) = 734 ns

min

tWHC

PARAMETER
Normal Mode RNi Recovery Time
Normal Mode RNi Set Up Time
to -CAS (L.E.)
Normal Mode RIW Set Up Time
to PI (L.E.)
Normal Mode RIW Set Up Time
to -RAS (L.E.)
PI (T.E.) to Next AI <7:0>
Address Enable
PI Hold Time from -CRS (T.E.)
or Delayed Mode RNi (T.E.)
PI Pulse Width
PI Precharge Time

PI (L.E.) Set Up Time to -CAS
(T.E.) or Delayed Mode RNJ (T.E.)
PI (L.E.!~et Up Time to Normal
Mode RIW (T.E.)
PI (L.E.) Set Up Time to
-RAS (T.E.)
-RAS Pulse Width
-RAS ("t.E.) Hold Time from -CAS
(T.E.) or Delayed Mode RNi (T.E.)
-RAS (T.E.) Hold Time from
PI (T.E.!
-RAS Precharge Time
-RAS (L.E.) Set Up Time to -CAS
(L.E.) or Delayed Mode RNJ (L.E.)
-RAS (L.E.) Set Up Time to
PI (L.E.)
-RAS (L.E.) to Write Data Valid
Write Data Set Up Time to
to PI (L.E.)
Write Data or SA L <15:8> Hold
Time from -CAS (T.E.) or
Delayed Mode RNi (T.E.)
Write Data Hold Time from
PI IT.E.)
Write Data or SAL <15:8> Hold
Time from -RAS (T.E.!
Write Data Set Up Time to -CAS
(T.E.!
Write Data Set Up Time to PI (T.E.)
Write Data Set Up Time to -RAS
(T.E.)

FUNCTION OF tCYC

MINIMAX

o ns

min

(2T -37) = 230 ns

min

(3T -45) = 355 ns

min

IT -78) = 55 ns

min

IT -40) = 93 ns

min

10 ns

min

(2T -47) = 220 ns

min

(4 T -33) = 500 ns
(2T -75) = 192 ns

min
min

(3T -90) c 310 ns

min

(2T --14) = 281 ns

min

(4T + 35) = 568 ns
50 ns

min
min

10 ns

min

(2T -120) = 147 ns
(T+ 10) = 143ns

min
min

(2T + 10) = 277 ns

min

(2T + 4) = 270 ns
(T -83) = 50 ns

max

(T -28) = 105 ns

min

(T -88) = 45 ns

min

(T-118)=15ns

min

(3T -1!~0) = 250 ns

min

(3T -110) = 290 ns
(3T -55) = 345 ns

min
min

min

"tJ

::Jl

-r-~
-z

1: Add T ns if in long bus cYcle mode, then if RDY slips are initiated, add HOT ns, where:
T = llfop, H = number of RDY pulses times 3 if mode = normal, times 4 if mode = long bus cycle.
MR-5584

»
:n
-<

"tJ
:ll

r3C

COUT ,

DAL<150> NOTE 3

-z

»
:ll

REFRESH TRANSACTION

, ' -_ _ _ _ _ _ _ __

))))))))))X((((((((((((((((((O))))))))))))))))))))C
t ASR

tAHR

-rr'.,-'M",.,.."iM'~'

AI<7,O>

REFRESH ADDRESS

tFFR

.1.

tFRP

MODE REGISTER
11 10 9 8

-RAS

IxI I0 I xlXJ!l
X

.j:::.

-CAS
PI
R/-WHB
R/-WLB

NOTE 1
NOTE 2
NOTE 1
NOTE 1

HIGH

LOW

'FSP

IRRELEVANT

VALID
OUTPUT

SEL 0

r::::r..

I N VA II 0 \'VTTT'1f:mVT
OUTPUT ~

SEL 1 NOTE 2

NOTE 1,
NOTE 2,
NOTE 3,
NOTE 4:
NOTE 5,
NOTE 6·

X '"

~N~~~~

ASSERTED HI THROUGHOUT THE TRANSACTION
ASSERTED LO THROUGHOUT THE TRANSACTION.
CONTAINS THE LAST LATCHED DATA.
SEL 0 ASSERTED HI IN 4/16K MODE. ASSERTED LO IN 64K MODE
READY HAS NO EFFECT
EXTRA TIMING PHASE (ODI ALWAYS PRESENT.

Figure A-IO

IGNORED

Refresh

INPUT

IXillJlXI

CONDITIONAL

~)=~-_~-_-_-_~.~~

SYMBOL

PARAMETER

tASR

Refresh Address on AI<7:0>
Set Up Time to -RAS (L.E.)
Refresh Address on AI<7:0>
Hold Time from -RAS (L.E.)
XTL 1, XTLO Operating Period
Refresh -RAS Pulse Width
Refresh Select on SE L<0>
Pulse Width
Refresh Select on SEL<O> (L.E.)
Set Up Time to -RAS (L.E.)
Refresh Select on SEL<O> (T.E.)
Hold Time from -RAS (T.E.)

tAHR
tCYC
tFRP
tFSP
tFFR
tSHF

FUNCTION OF tCYC

MINIMAX

(T -83) " 50 ns

min

(T -60) "73

min

T" 133 ns
(2T + 35) " 302 ns
(4T -20) " 513 ns

min
min
min

(T -23) " 110 ns

min

(T-123) "10

min

:>
I

."
2J

-ir-:
MR-5587

-»
z

::D

"tJ
:XI

m
r-

ICOUT

lACK TRANSACTION

<NOTE]> /

-3:
z-

»
:XI

DAL<12:8> NOTE 3

INTERRUPT REOUEST DATA

DAL<7:1> NOTE 4

AI<7:O> NOTE 6

=-t=tDSR~'~"U--'
tKAP

-RAS

:>
I

-CAS
PI
RI -WHB
RI -WLB
SEL 0

NOTE 1
NOTE 2
NOTE 1
NOTE 1
NOTE 2

tv
SEL 1
ClACKI

MODE REGISTER
11

[XTXlx] X I XIQ

I-

1" HIGH
0" LOW
X" IRRELEVANT

tKSP

VALID
OUTPUT

DAL<15:13> NOTE 6
DAL<O>
NOTE 5

~:VT~~'~

NOTE 1:
NOTE 2:
NOTE 3:
NOTE 4:
NOTE 5:
NOTE 6:

ASSERTED HI THROUGHOUT THE TRANSACTION
ASSERTED LO THROUGHOUT THE TRANSACTION
DAL<12:8> OUTPUTS THE IRO DATA LATCHED FROM AI<5:1> DURING IRO ACKNOWLEDGE
DAL<7:1> READS VECTOR DATA IF AI<5> WAS ASSERTED
TRISTATED AND IGNORED THROUGHOUT THE TRANSACTION
CONTAINS PREVIOUSLY LATCHED DATA (OUTPUTI

NOTE 7:

EXTRA TIMING PHASE (ODI ALWAYS PRESENT

r:::::r.

romoo:

~N~~I~~

:~~~;ED IXillillXr
CONDITIONAL

::(~-_-_-_-_-_~.~:
MR-4710

Figure A-II

lACK Transaction

SYMBOL

FUNCTION OF tCYC

MINIMAX

tCYC

XTL I, XTLO Operating Period

T=133ns

min

tDSR
tKDS

lACK Data Set Up Time
Vector Data on DAL<7:2> Hold
Time from lACK Select on SEL
(T.E.)
lACK info on DAL<15:8> Hold
Time from -RAS (T.E.)
lACK info on DAL<15:8> Hold
Time from lACK Select on SEL
(T.E.)
lACK Select on SEL<l> (l.E.) Set
Up Time to -RAS (l.E.)
lACK -RAS (l.E.) to Vector Data
on DAL<7:0> Valid
lACK -RAS Pulse Width
lACK Select on SEL<l> (l.E.) to
Vector Data on DAL<7:2> Valid
lACK Select on SEL Pulse Width
-RAS <T.E.) to next DAL<15:0>
Addre .. Enable
-RAS (T.E.) Hold Time from lACK
Select on SEL <T.E.)
lACK or DMA Select on SEL

(T -48) = 85 ns
Ons

min

(T-118)=15ns

min

(T -50) = 83 ns

min

(T -63) = 70 ns

min

(2T -148) = 119 ns

max

(2T + 35) = 302 ns
(3T -155) = 245 ns

max

(3T -66) = 334 ns
(T -118) = 15 ns

min
min

45 ns

min

(T) = 133 ns

min

tKHR
tKHS

tKKR
tKRD
tKRP
tKSD
tKSP
tRDE
tRHS
tSPR

>
~

PARAMETER

min

Recovery Time

r
3C

1: Add T ns if in long bus cycle mode, then if RDY slips are initiated. add H*T ns, where:
T = llfop, H = number of RDY pulses times 3 if mode = normal, times 4 if mode = long bus cycle.
MR-5588

-z

>
:D
-<

"'C

:xl

rfo---BUS NOP TRANSACTION------l

COUT\

Z
l>
:xl

)((((((((((((+~~}I)))))))))))'( - - - -

OAL<15:O>

)((((((((((((1oj~~I)))))))))))X= - - - -

AI<7:O>

-RAS

_ _ _ -1

,
-CAS

I
_ _ oJ

---,

\
\

~
I

-------;

~
~

RI -WHB
RI -WLB _ _ _ _ _ _

\-----

--1

L ___ _

r---I

SEL 0

MODE REGISTER

111098

Ixlxlxlxlxl'l
1 "
X "

SEL 1

NOTE 1
NOTE 2
NOTE 3

HIGH

o " LOW
IRRELEVANT

~~~~~T
~NUVT~~I~

PREVIOUSLY LATCHED DATA
THREE-STATE IN STATIC MODES
LONG BUS CYCLE MODE AND READY HAVE NO EFFECT

-:r:::::r.

mImIDXI

~N~~~ r=::L
IGNORED
INPUT

m:nrnxr

- ... ,..------ ...... CONDITIONAL _~J..... ______ } .... .
MA-4715

Figure A-12

Busnop Transaction

•

••

(A Busnop transaction is a specific state; therefore, no timings are provided.)

>
I

:JJ

-z

r3:

:JJ

r---J

COUT

:%J

DYNAMIC OMA TRANSACTION

'ORO

r--

DAL<'5:O>

AI<O>
NOTE 4

\ \ \ \ \ \ \\ \

DMA REOUEST

tMOR-

tOFS

-f

I--

'IHP'AFs--II------'sKR

-RAS

r'DSE=K=~ ~

jt=

I--'MRO
l---'ISP--1

___

~+-----

tMAREOUESTt

_N::T~ ~ -

'MOC ---.l

fl.

'MRC:---

"\I.

RDE -

'MRP

'~'CDEl

'CAS

-CAS

;J>

J,..

!-'CSP-!

'PIP

~ i--'PAF-

'rJ-

0\
R/-WHR

'RSD--j

R/-WLR

'MSF=======___-------l---~~ - - - -

II'

'-N~TE 1

SEL 0

SEL 1

NOTE 1NOTE 2:
NOTE 3:
NOTE 4
NOTE 5-

jr'OPW-l

Io----=='SF=R==I====~'M~S:.K-=_=_=_=_=__-_-_-_-_-_-_-~..::--=-=-.,J - - - - t7 __ _
'~-1fL=
'SPR---<

NOTE 2

IF THE NEXT RRANSACTION IS REFRESH OR A SECOND DMA SELO REMAINS SET
IF THE NEXT TRANSACTION IS ANOTHER DMA OR AN lACK SEL 1 REMAINS SET
DMA TRANSACTION IS TERMINATED IF AI<O> IS ASSERTED HI
AI<7:11> HAVE INTERNAL PASSIVE PULLUP THRU THE TRANSACTION_ DURING
THIS TIME INTERRUPT REOUESTS ARE INHIBITED
EXTRA TIMING PHASE 100) ALWAYS PRESENT

Figure A-13

~~gl~TER I X I X I 0 I X I X l' I
1 '"

HIGH

LOW

X = IRRELEVANT

DMA Transaction

r::::=r.

INPUT

m:rrnxr

I N V A LID TVTTr'1\rr\VT
OUTPUT ~

CONDITIONAL

~:( ~--~-_-_-_~I~~

~N~~~ ~

THREE-STATE

J---C

VALID
OUTPUT

IGNORED

-3:
Z

(

SYMBOL

PARAMETER

tAFS

AI<7:0> Float to DMA Select on
SEL<O>
-CAS Pulse Width
-CAS IT.E.) to next DAL<15:0>
Address Enable
-CAS (L.E.J Set Up Time to PI (L.E.)
XTL I, XTLO Operating Period
DAL<15:0> Float to DMA Select On
SEL<O> (L.E.J
DAL<15:0> Enable from DMA
Select on SEL IT.E.)
Input on AI<7:0> Hold Time from
PI (T.E.)
PI (L.E.) to Interrupt or DMA Input
on AI<7:0> Valid
Pulse Mode COUT (T.E.) Set Up Time
to -CAS (L.E.)
Pulse Mode COUT
(L.E.) Set Up Time to -RAS (L.E.)
DMA Select -RAS
(L.E.) Set Up Time to -CAS (L.E.)
DMA Pulse Mode COUT
(T.E.) Hold Time from -RAS (L.E.)
DMA Select -RAS
Pulse Width
DMA Select on SE L <0>
Pulse Width
DMA Select on SEL
Pulse Width
Pulse Mode COUT Pulse Width
Pulse Mode COUT Recovery Time
when OD is present
PI IT.E.) to next AI<7:0> Address
Enable
PI Pulse Width
-RAS (T.E.) to next DAL<15:0>
Address Enable
RNI Drivers disabled and
Passive Pull Up Enabled Set Up Time to
DMA Select on SE L <0> (L.E.)
PtiW driver enable from
DMA Select on SEL<l> (T.E.)
DMA Select on SEL<O>
(L.E.) Set Up Time to -RAS (L.E.)
DMA Select on SEL
(L.E.) Set Up Time to-RAS (L.E.)

tCAS
tCDE
tcsP
tCYC
tDFS
tDSE
tlHP
tlSP
tMOC
tMOR
tMRC
tMRO
tMRP

-.I

tMSF

tMSK

2,3

tOPW
tORD

2,3
tpAE
tPIP
tRDE
tRSD

tRSE
tSFR
tSKR
tSPR

lACK or DMA Select on SEL

FUNCTION OF tCYC

MINIMAX

o ns

min

(3T -90) = 310 ns
(T-18)=115ns

min
min

(T -28) = 105 ns
T = 133 ns
ns

min
min
min

IT -27) = 106 ns

min

Ons

min

(2T -167) = 100 ns

max

(T+l0) = 143 ns

min

Ons

min

(2T + 10) = 277 ns

min

IT -51) = 82 ns

min

(5T + 35) = 702 ns

min

(8T -38) = 1029 ns

min

(7T -68) = 865 ns

min

(T -33) = 100 ns
(3T -37) = 363 ns

min
min

(T -40) = 93 ns

min

(2T -47) = 220 ns
IT -118) = 15 ns

min
min

o ns

min

(T -27) = 106 ns

min

(2T -23) = 243 ns

min

(2T -63) = 203 ns

min

IT) = 133 ns

min

o ns

min

Recovery Time

tsss

SEL<O> (L.E.) Set Up Time to
SEL (L.E.)

1: Add T ns if in long bus cycle mode, then if RDY slips are initiated, add HOT ns, where:
T = l/fop, H = number of RDY pulses times 3 if mode = normal, times 4 if mode = long bus cycle.
2: Add 4T for each READY pulse.
3: Add aT if multiple DMA cycles are granted
MA 5590

"1!!
:JJ

:-sc

::Z
:»
;:JJ
-<

"tJ

-~.

r3:.

I.
COUT /

DAL<15:O>

ASPI TRANSACTION

<NOTE 6> /

:u.

, - \

-('

NOTE 3

AI<7:O>

-RAS

NOTE 1
MODE REGISTER

11109810

-CAS

Ixl xl xlxl xiII

HIGH

o " LOW

X '" IRRELEVANT

~~~~~T

R/-WHB NOTE 1
R/-WLB NOTE 1
SEL 0 NOTE 2
SEL 1 NOTE 2
NOTE I:
NOTE 2
NOTE 3
NOTE 4:
NOTE 5.
NOTE 6

x::=r.

INVALID~

OUTPUT ~

ASSERTED HI THROUGHOUT THE TRANSACTION
ASSERTED LO THROUGHOUT THE TRANSACTION
THREE·STATED
ASPI OCCURS AT THE END OF A HL T. PUP TRANSACTION. AND DURING A WAIT INSTRUCTION
READY HAS NO EFFECT
EXTRA TIMING PHASE IDOl ALWAYS PRESENT

Figure A-14

ASPI Transaction

~N~~~ :x-:=I.
IGNORED
INPUT

lXillillXI

CONDITIONAL

..}\..- ----~ .......

......

~ ~.-

-- .. ,.-

SYMBOL

PARAMETER

FUNCTION OF tCYC

MINIMAX

tCAS
tCOE

-CAS Pulse Width
-CAS (T.E.) to next OAL<15:0>
Address Enable
-CAS (L.E.) Set Up Time to PI (L.E.)
XTL 1, XTLO Operating Period
Input on AI<7:0> Hold Time from
PI (T.E.)

(3T -90) = 310 ns
(T -18) = 115 ns

min
min

(T -28) = 105 ns
T=133ns
ns

min
min
min

(2T -167) = 100 ns
10 ns
(2T -37) = 230 ns

max
min
min

tcsP
tCYC
tlHP
tlSP
tpHC
tplP

PI (L.E.) to Input on AI<7:0> Valid
PI Hold Time from -CAS (T.E.)
PI Pulse Width

+:>.

m
C
J:
1: Add T ns if in long bus cycle mode, then if ROY slips are initiated, add H*T ns, where:
T = l/fop, H = number of ROY pulses times 3 if mode = normal, times 4 if mode = long bus cycle.
MA·5592

-Z

"tJ

::r:J

r3:'

-_.

lySO

z
>
::D-

COUT

READY NOTE 2
NOTE 5
NOTE 6

+ GfCWJ{[ _-

--MICROCYCLE SLIP 2---~

,rl,"T,T,T"ljj"T,+J..",""',""-,T,'"","',T,.",,'"",T",'"","T,T",'""' "' '...,-, ,,",,,""T,-'-,""",""',""T,-'-,,""',""T,-'-,.",''"'''...,-,-.-,''"'''---------,'~«
T"",

DATA IN

DAL<15,0>

------+~----MICROCYCLE SLIP 2

{~CutuIC~1~~~t~~~ILL[

INT. & DMA
REOUEST

AI<7:D>

~ ~~~~ ~ ~ ~ ~

MICROCVCLE SLIP 1

·1

MtCRQCYCLE SLIP 2

r - - - - - - - - - - - - - - - -,
-RAS

;I>
I

I·

-------------MICROCYCLE SLIP 1

r---CAS

r
PI

NOTE l'
NOTE 2'
NOTE 3,
NOTE 4,
NOTE 5,
NOTE 6,

_ _ _--.J!

·1·

MICROCYCLE SLIP 2

I
~

--------,
I

I·

------------ -1

·1·

MtCROCVCLE SLIP 1

'L _ _ _ _ _ _ _ _ _ _ _ _ _

WAVEFORMS ARE DRAWN FOR 16-BIT DYNAMIC READ
READY WAVEFORM IS VALID FOR ANY CASE
RI-WLB RI-WHB ARE ASSERTED HI THROUGHOUT THE TRANSACTION
SEL 0 SEL 1 ARE ASSERTED LO THROUGHOUT THE T8ANSACTION
THE READY PULSE MAY BE OBTAINED BY GATING COUT WITH A READY ENABLE SIGNAL
HOLDING READY PERMANENTLY LOW RESULTS IN ONE MICROCYCLE SLIP PER BUS TRANSACTION

Figure A-IS

MICROCYCLE SLIP 2

~
11

---10

~~gl~TE R I X I X I X I X I X I 1 I
1 = HIGH
0= LOW
X'" IRRELEVANT

Ready

-I

-',
I

OUTPUT

r::::::x.

INVALID
OUTPUT

~ CONDITIONAL ~ =-= ~-_-_-_-_-_~J~~

VALID

:N~~I~~

IGNORED
INPUT

liilliJJJl

,\'

SYMBOL

PARAMETER

tCYC
tYHC

XTL I, XTLO Operating Period
Ready (L.E.) Hold Time from
COUT (T.E.)
Ready Unassorted Pulse Width
Ready Recovery Time
Ready (T.E.) Delay from -CAS (L.E.)
Ready (L.E.) Delay from Pulsed Mode
COUT (T.E.)
Ready (T.E.) Delay from -RAS (L.E.)

2
2

typw
tYRT
tySC
tySO

tYSR

2
1

FUNCTION OF tCYC

MINIMAX

T= 133ns

max

o ns

min

60ns
60 ns
(2T -135) = 132 ns
(2T -127) = 140 ns

min

(3T -100) = 300 ns

max

min

max
max

:>
I

"lJ
::0:

m,
r-

E:
Z
»
::0

1: These timing parameters apply only to cases where multiple READY pulses are required;
i.e., multiple microcycle slips.

2: READY is an edge-triggered input that is usually activated by asserting a low on its pin.
However, READY is internally activated by the leading edge of -RAS if its pin has been
asserted low before these edges.

MR·5593

"tJ

I-

tpFF _
PUP

-BClR

tupp--------I

tpBU

"\\\\\\

------!..

~:.u.:----<o

DAl<15.0>

----------------Al<7'O>
----------

lilli J
( ( \\ (

(

MOOt

NO\E 3 NOT{ 8

(

NO,T~' (

INPUT I

((

1)))))1)))

----------CAS

I---

_____ _____ J

----------,

SEL r

SEll

COUT

,NOTE "

4,NOTE 1,'

L __ J

\... __ J

'I',

r--

- - - - ------,
--------- - - - -----,

I---_+___--'1...:.,'_...I.'"";fi \

------------

------,

-- -----

tpco ~

T OSC.
WITH MODE
REG 101 " 1

OSC. PE R MODE
BIT 1
- ....J

I-I--

ASSERTION DEPENDS ON MODE
LOW CURRENT PULLUP ON DAL <158,1-0> UNTIL -BelA NEGATION

NOTE 9

DURING BelR ASSERTION AT POWER UP THERE MAY BE CONTROL SIGNAL ASSERTIONS
PRIOR TO THE POINT WHERE THE OCT-11 READS IN THE MODE REGISTER
ON THE LEADING EDGE OF PUP THE OUTPUT SIGNALS ARE INVALID UNTIL !PUT. THIS
CONDITION EXISTS ON POWER UP AND IF PUP IS ISSUED DURING EXECUTION OF A RESET

~~gl~TE RI x I x I x I x I x Ix I

LOW CURRENT PULLUP
INTERRUPTS AND DMA REQUEST ARE SERVICED BEFORE THE FIRST FETCH
ASSERTED IN DYNAMIC MODE ONLY, REFLECTS CONTENTS OF THE MODE REGISTER

L-,

~
L ______ _

r------

~~~
J

OSC. PER MODE BIT 9

_l~

ASSERTED IN DYNAMIC MODES ONLY

NOTE 2
NOTE 3
NOTE 4
NOTE 5
NOTE 6
NOTE 7
NOTE 8

HIGH

lOW
X

IRRELEVANT

VALID

IGNORED
INPUT

liIJ§JJJl
- ....... ------"'\ ... ~:\~~I~ lXillIDTI:XI CONDITIONAL ..} ..... _---_ ......... OUTPUT

~N~~~~

20 REFRESH TRANSACTIONS IN 8 81T MODE 10 REFRESH TRANSACTIONS IN 16 BIT MODE
DAL S ALWAYS DRIVING EXCEPT DURING DMA AND DATA PORTION OF READ TRANSACTION

INSTRUCTION

MR.4711

Figure A-16

Power-Up

Z
l>

:lJ

FIRST FETCH
ADDRESS

~~~

NOTE 1

NOTE 10

r-----I

----------

RI -WlB _ _ _ _ _ _ _ _ _ ..J

---+---

:,1--1

r---+-_ _ _....;\\
r----~--------------~\ ,

----------

--------RI -WHB __________ J

I---

--3:

, - - - --j \ - - - - - - - - - - - - -

))Jill ~,~~; , Illi~

_____ _____ J

---------·1

-l

---------RAS

:lJ

~n--n-l

_tpMU~

tpBC

\lli \ \\\

____

-I

POWER UP SEQUENCE

SYMBOL

PARAMETER

tCYC
tpBC
tpBU

XTl1. XTLO Operating Period
Power Up to -BCLR Il.E.1
Set Up Time
Power Up IT.E.I to -·BCLR IT.E.I

tpco
tpFF

Power Up IT.E.I to COUT Il.E.1
Power Up IT .E.I to Beginning of

tpMU

Power Up IT.E.I to Mode Bits on
DAL<15:00> Valid
Power Up Il.E.1 to Output Pins Preset

First I nstruction Fetch

tpUT
tupp

Power Up Time

FUNCTION OF tCYC
T = 133 ns
100 ns
99T = 13200 ns
lOOT = 13333 ns
IT + 601 193 ns
295T = 39333 ns
315T = 42000 ns
18T = 2400 ns
19T = 2533 ns
250 ns
100"s

MINIMAX
min

max
min

max
max
min

max
min

max
max
min

;I>
I

VI
VJ

."
::0

..m
r

MR-5589

»::0

"'tJ

::u

z-;

r
3:

»
::u

XTALO

XTAL 1 NOTE 1

__-....,..1.

'ORO

'1t='OPW=11

'CRT

1.,.._--..

COUT

'Cap

,r-,r-=x
-1"__""- __

COUT NOTE 2

MODE REG ISTE R
11

[1] X IYEl xEJ
1 '" HIGH

o • LOW

X '"

-RAS

IRRELEVANT

~~~~~T x::::::::::L
~NUVT~~I~~

-CAS

~N~~~~
NOTE 1:
NOTE 2:

NOTE 3:

XTAL1 MAY BE USED ASAN OUTPUT
BUS MODE CLOCK (MODE REG <0>'0) PHASE DEPENDS ON MODE AND CODE
EXECUTED AS SHOWN WITH CONDITIONAL OUTPUT. FOR LONG MICROCYCLE
MODE AND BUS MODE CLOCK, THE VAll 0 OUTPUT IS SHOWN (PHASE IS UNCONDITIONAL)
EXTRA TIMING PHASE 1001 PRESENT. 00 IS PRESENT ONLY DURING ASPI, DMA,
REFRESH AND lACK IN STANDARD MICROCYCLE MODE MR<1 >'1. 00 IS PRESENT
IN ALL MICROCYCLES IN LONG MICROCYCLE MODE MR<1 >. O.

IGNORED
INPUT

mIIDIXI

CONDITIONAL

~:-: ~----------~.~~

MR·.?1.

Figure A-I?

XT AL and COUT

(
SYMBOL

tCYC
tMOC
tMOR

tMRO

tOPW
tORD

PARAMETER

XTL I, XTLO Operating Period
Pulse Mode COUT (T.E.) Set Up Time
to -CAS (L.E.)
Read/Write or DMA
Pulse Mode COUT (L.E.) Set Up
Time to -RAS (L.E.)
Read/Write or DMA
Pulse Mode COUT (T.E.) Hold
Time to -RAS (L.E.)
Pulse Mode COUT Pulse Width
Pulse Mode COUT Reoovery Time

FUNCTION OF tCYC

MINIMAX

T=133ns
(T+l0) = 143 ns

min

10 ns

min

(T -51) = 82 ns

min

(T -33) = 100 ns
(3T -37) = 363 ns

min
min

(2T -37) = 230 ns

min

when Phase 0 is Present
tORT

Pulse Mode COUT Recovery Time

:>
I

Vl
Vl

",r-3-:.
."

~~--

MA-5591

"-<

PRELIMINARY

DATA/ADDRESS LINES

DALl5

vee

+5V

DALl4

AI7

-HLT

DALl3

AI6

-PF

DAL12

AI5

-VEC

DALl1

AI4

-CPO

DALlO

AI3

-CP1

DAL9

AI2

-CP2

BGND

AI1

-CP3

INPUT ONLY

DAL8

AIO

-DMR

ADDRESS/INTERRUPT

DAL7

PRIORITY IN STROBE

DAL6

-CAS

COLUMN ADDRESS STROBE

DAL5

-RAS

ROW ADDRESS STROBE

DAL4

R/-WLB

DAL3

R/-WHB

DAL2

READY

READ/WRITE LOW BYTE (16)
WRITE (8)
READ/WRITE HIGH BYTE (16)
READ (8)
EXTEND TRANSACTION

DAL1

SELO

DATA/ADDRESS LINES

DALO

SEL1

BUS CLEAR

-BCLR

XTLO

CRYSTAL

POWER-UP

PUP

XTL1

CRYSTAL /EXT OSC

1STGROUND

GND

COUT

CLOCK OUTPUT

2ND GROUND

DCT11-AA

}

ADDRESS/INTERRUPT
DYNAMIC MODE
OUTPUT
ROW ADDRESS
COLUMN ADDRESS
INPUT
INTERRUPT & DMR
DURING PI TIME
STATIC MODE

SELECT OUTPUT FLAGS
SEE BELOW

SELECT OUTPUT FLAGS
SEL<1>
L
L
H
H

SEL<O>
L
H
L
H

FUNCTION
READ/WRITE
REFRESH/FETCH
lACK
DMG
MR·6271

Figure A-18

DCTII-AA Pin Layout

A-56

PRELtMlNARY

01
LONG
STD

<15:13>
12
11
10
09

START/RESTART ADDRESS
TESTER/USER MODE
16-81T /8-BIT BUS
64K/4K OR 16K MEMORY
DYNAMIC/STATIC MEMORY

NORMAL/DE LAYED RNJ
RESERVED
LONG/STANDARD MICROCYCLE
CONSTANT/PROCESSOR MODE CLOCK

<7:2>
01
00

ADDRESS BITS
<15:13>

START
ADDRESS

RESTART
ADDRESS

7
6
5
4
3
2
1
0

172000
173000
000000
010000
020000
040000
100000
140000

172004
173004
000004
010004
020004
040004
100004
140004
MR 4843

Figure A-19

Mode Register

PROCESSOR STATUS
15

<15:8> READ AS ZEROS
03 NEGATIVE

Figure A-20

Processor Status Word

A-57

PRELIMINARY
R/-WLB~
R/-\NH~
LS32
WLB L
LS32
WHB L
CAS L

R!-WLB=8LSOO
-RD H
R/-WHB

CAS L

LS368A

~INITH
G2
GND

LDAL <15,14> 2

A, B

CC
VCC- IC

::::GT

-H-

40~
5.0688

1J-

AI
PUP
DCT11-AA
HIDAL

~L'm)--< 2C
1G

L DAL <2:1>
2
8

P-- 2716 SEL L

XTLO

P-

B255SELL

A1:0
07:0

8 ~I/O PORT

RD L -(l RD

R/-WLB

C ~I/OPORT

WL8 L-<l -WT

'-R/-WHB

1Y1

411BSEL L

8
A +1/0 PORT

CAS L
COUT

100pF

P-- 2651 SE L L

RAS L

XTL1

MHZ c::J
XTAL

2Y3

2G
IY2
74LS155

CTRLi

P-

CAS L-C

DAL <15:8>

LO DAL

1YO

MODE
3Y BUFFER
(16 BIT,
11
NORMAL
BMCI

BCLR
VCC

L DAL<1>

1/2 LS36BA

RD L

IOSEL L-a

INTEL
8255A

INITH- RESET
74LS373
MOSTEK

~ 0

L DAL

LDAL<15:8>

<10:8>

--c

1/0
6E 4118
'"
1K x 8
RAM SEL L-C CS STATIC
WLB L~ WE RAM
WHB L-Oj"WE
VCC

LS32
EN

RAMSEL L
RAS L

74LS373
LO

~ 0

L DAL<7:0>

OUT
CTRL

:t,

LRAS L

8{
2

CO
PORT (RIWI
C

5
5

B PORT (RIWI
A PORT (RIWI

2{~~

MMAND (WI

1/0

LDAL <118>
LDAL <7:1>

A10:7
A6:0

-C CE

OUT

ROM SEL L--o OE

8
OUT

INTEL
2716
2K X 8
EPROM

VALID ADDRESS

()()()()-3776
RA M (RIWI
100000-107776
RO M (RI
MMAND (RIWI 177016
177012
DE (RIWI
177006
ST ATUS (RI
177002
RB UF (RI
177000
XB UF (WI

6
5

I--8

RAS L

I--

A9:7

8 A6:0

RD L
OUT
CTRL

I
8
LDAL <3.2>

-RWL8 H

LS368A
_-RWLB L

07:0

RX ~
AO,A1 ROY
_
TX
RDIWT ROY

40006
40004
40002
40000

2651 SEL L~ CE
INITH- RESET
BRCLK

SIGNETICS
2651
PUSART
MR 5601

Figure A-21

16-Bit Application

A-58

PRELIMINARY

LS368A

~INITH

V C

Gl
GND

C G2

1/2 LS368A

8CLR

C-H- PUP
p

5.0688
MHz
XTAL

DCTllAA

74LS155

HIDAL

40~

MODE BUFFER
INORMAL,BMCI

2
SAL <15,14>

La DAL

A,8

VCC
4

XTLl CTRL

I RAS,CAS,RD,wTI

XTL 0 COUT

CAS L

lC
lG

RD L

2Y3 p-2651 SEL L

;:JLS02}--< -2C

lYl P-2716 SEL L

LDAL <1>

INTEL
8155
AD7:0

8
SAL <14>
RAS L

101M
_ ALE

A ~I/OPORT

B ~ 1/0 PORT

RD L
~

CAS L :::JLS3r
~
./'

SAL <15> ,..
CAS L __
WT L

;:JLS3~

INITH- RESET

SAL <10:8> 3
8 LDAL<7:0>

"TI

INTEL
2716
2K X 8
EPROM

RAS L
8
VALID ADDRESS

ROM IRI

100000- 103777

i{~T

177016
177012
177006
177002
177000

8{~T

0-377
40000
40000
40001
40002
40003

A7:0

ROM SEL L--o OE

R EGISTER
OMMANDI RIW)
ODE IRIWI
ATUS IRI
R BUF IRI
XBUF IWI

Al0:8

OUT

RAS L
OUT
CTRL

6
+1/0 PORT

~WT

74LS373

~ D

DAL<3,2>
RD L

D7:0
AO,Al

" RDIWT ~Y
'"
TX
BRCLK RDY

... 2

2651 SEL L--<:J CE

1
5
5

AM (R/WI
ATUS IRI
CO MMAND (WI
A PORT IRIWI
8 PORT IRIWI
C PORT IRIWI

INITH- RESET
SIGNETICS
2651
PUSART

NOTE:
2651 MUST BE ACCESSED BY BYTE
INSTRUCTIONS ONLY.

Figure A-22

MA 5600

8-Bit Application

A-59

PRELIMINARY

APPENDIX B
SOFTW ARE DIFFERENCES

B.l INTRODUCTION
This appendix is meant to make the reader aware of the variations between the DCTII-AA and other
members of the PDP-II family. These variations fall into the following major categories.
•
•
•
•
•

Addressing modes
PD P-I I instruction set
DCTII-AA instruction execution sequence on the data bus
Exceptions and interrupts
Power-up

The processors that are compared with the DCTII-AA in this appendix are
PDP-I 1/03
PDP-I 1/04
PDP-I 1/23

PDP-I 1/24
PDP-II/34A
PDP-I 1/40

PDP-I 1/44
PDP-II/45
PDP-I 1/70

Table 8-5 (found at the end of this appendix) describes the software differences and compatibilities
among the DCTII-AA and other members of the PDP-II family.
B.2 ADDRESSING MODES
Most basic instructions operate in the same way from one PDP-II processor to another. However, there
are variations in the wayan address is computed, depending on the addressing mode being used. This
section covers the variations in the addressing modes that are implemented by the DCTII-AA. An explanation of the symbols used in this section is found in Paragraph 6.3.
When executing a double-operand instruction, the same general-purpose register may be used for both
the source and destination fields of the instruction. Note that when the same registers are used in the
DCTII-AA, PDP-I 1/23, PDP-I 1/24, and PDP-I 1/40, the results vary from o~her PDP-II processors.
B.2.1 Modes 2 and 4
If the addressing mode of the destination operand is autoincrement (mode 2), the contents of the register are incremented by 2 before being used as the source operand. If the addressing mode of the destination operand is autodecrement (mode 4), the contents of the register are decremented by 2 before
being used as the source operand.

8-1

PRE;LIMINARY
In the other processors covered in this appendix, the initial content of the source register is not modified
and is used as the source operand.
The following is an example of an autoincrement (mode 2). Register 0 contains 10008.
MOY RO, (RO)+

In the DCTII-AA, the quantity 1002 is moved to location 1000.
In the other processors, the quantity 1000 is moved to location 1000.

The following is an example of an autodecrement (mode 4). Register 0 contains 10008.
MOY RO, -(RO)

In the DCTII-AA, the quantity 776 is moved to location 776.
In the other processors, the quantity 1000 is moved to location 776.

8.2.2 Modes 3 and 5
If the addressing mode of the destination operand is autoincrement-deferred (mode 3), the contents of
the register are incremented by 2 before being used as the source operand. If the addressing mode of
the destination operand is autodecrement-deferred (mode 5), the contents of the register are decremented by 2 before being used as the source operand.
In the other processors covered in this appendix, the initial content of the source register is not modified
and is used as the source operand.
The following is an example of an autoincrement-deferred (mode 3). Register 0 contains 10008 and
location 1000 contains 20008.
MOY RO, @(RO)+

In the DCTII-AA, the quantity 1002 is moved to location 2000.
In the other processors, the quantity 1000 is moved to location 2000.

The following is an example of an autodecrement-deferred (mode 5). Register 0 contains 10008 and
location 776 contains 20008.
MOY RO, @-(RO)

In the DCTII-AA, the quantity 776 is moved to location 2000.
In the other processors, the quantity 1000 is moved to location 2000.

B.2.3

Using the PC Contents as the Source Operand
Op Code PC, X(R)
Op Code PC, @X(R)
Op Code PC, @A
Op Code PC, A

In the operations above, the resulting source operand is the value of the location of the op code plus 4.
This is true for the DCTlI-AA, PDP-11/23, PDP-11/24, and PDP-I 1/40. This varies from other PDPI I processors covered in this appendix, where the source operand is the value of the location of the op
code plus 2.
In the following example, the PC contains the value 10008. Location 1002 contains the offset value 2.
RO contains the value 20008.

B-2

PRELIMINARY
MOY pc, 2(RO)

In the DCTII-AA, the value 1004 is moved to location 2002.
In the other processors, the value 1002 is moved to location 2002.

The final source operand is the same (I004) for all the addressing modes explained above.
NOTE
The use of the above forms of addressing should be
avoided. The MACRO-ll assembler generates an
error code (Z), which is printed in the listing. This
occurs in each instruction when the addressing mode
is found not to be compatible among all members of
the PDP-ll family.
B.2.4

Jump (JMP) and Jump to Subroutine (JSR) Instructions
JMP %R
JSR reg, %R

When programming JMP and JSR instructions, take care in selecting the destination mode of the instruction. When mode 0 is selected, an error condition is created and the DCTII-AA traps through
location 4 of the trap vectors (refer to Paragraph B.5). This is true of all PDP-II processors except the
PDP-I 1/45.
The PDP-II /45 causes a trap through memory location 10 when executing this instruction.
B.3 PDP-II INSTRUCTION SET
The DCTII-AA implements the basic PDP-II instruction set. This instruction set offers a wide choice
of operations, and often a single instruction will do a task that would need many in other computers.
PDP-II instructions allow byte and word addressing in both single- and double-operand formats. This
saves memory space and simplifies the implementation of control and communications applications.
I nstruction set variations fall into these categories:
•
•
•
•

Instructions not common to all PDP-lIs
Basic instruction execution
Instructions not executed
Effect of the T bit (instruction trace trap)

B.3.1 Instructions Not Common to All PDP-lIs
As the number of PDP-II processor types increased, instructions were added to the basic instruction
set. The OCT II-AA includes the following instructions.
MFPT (move from processor type)
MFPS (move byte from processor status)
MTPS (move byte to processor status)

B-3

PRELIMINARY
8.3.1.1

MFPT Instruction
MOVE FROM PROCESSOR TYPE

000007

00
:

: 0

: : I
1

MA-5969

Operation:

Condition Codes:

Not affected

processor type

The DCTII-AA, PDP-I 1/23, PDP-I 1/24, and PDP-I 1/44 are the only processors that execute the
MFPT instruction. The model code is placed in the low byte of register RO, indicating to the system
software the processor type. Table B-1 shows the codes assigned to identify the processor in use.

NOTE
The PDP-llj23 and PDP-llj24 are controlled by
the same processor and have the same model code.
Table B-1 Processor Codes
Model Code

Processor Type

4
3

DCTlI-AA
PDP-l 1/23 or PDP-l 1/24
PDP-l 1/44

8.3.1.2

MFPS Instruction
106700

MOVE BYTE FROM PROCESSOR STATUS WORD

MA-5221

Operation:

(dst)

Condition Codes:

N: set if PS bit 7 = I; cleared otherwise
Z: set if PS bits <7:0> = 0; cleared otherwise
V: cleared
C: not affected

The low byte of the PS is used as the source operand. The destination operand is treated as a byte.
The DCTII-AA, PDP-I 1/03, PDP-I 1/23, PDP-I 1/24, and PDP-I 1/34 implement this instruction to
save the processor status register (PS) without directly accessing the PS on the data/address bus.

B-4

NOTE
The DCT11-AA is not restricted from having memory or a device at the PS address 177776. In addition,
the DCTll-AA does not recognize that an error has
occurred when addressing a nonexistent memory location. (Refer to Paragraph B.5.) Attempting to
read or write data at address 177776 and expecting·
the PS will cause unpredictable results.
B.3.1.3

MTPS Instruction
MOVE BYTE TO PROCESSOR STATUS WORD

1064SS

MR-S222

Operation:

PS < - (src)

Condition Codes:

N: set according to effective source operand
Z: set according to effective source operand
V: set according to effective source operand
C: set according to effective source operand

The source operand is treated as a byte and the destination operand is always the low byte of the PS.
The source operand is not affected by the MTPS instruction.
NOTE
The T bit (bit 4 of the PS) cannot be set with the
MTPS instruction.
The DCTII-AA, PDP-I 1/03, PDP-I 1/23, PDP-I 1/24, and PDP-I 1/34 implement this instruction in
order to load the low byte of the processor status register without directly addressing the PS on the
data/address bus.
NOTE
When developing software for the DCT11-AA on
PDP-ll systems that have memory management,
the priority bits of the PS (bits <7:5» may not be
affected. Refer to the appropriate processor handbook.
B.3.2 Basic Instruction Execution
The OCT II-AA executes all basic PDP-II instructions except MARK. Some instructions vary in execution from other PDP-II processors. These instructions are covered in this section.

B-5

PR,ELIMINARY
8.3.2.1

Halt Instruction
000000

HALT

o :

o : o : o : o :

:oI
MA-5261

Condition Codes:

Not affected

When the other PDP-II processors covered in this appendix execute the halt instruction, their operations cease. Control goes to the console (if one is present) or to a console microprogram within the
processor. The DCTII-AA has neither console nor console microprogram; it executes a halt instruction
the way it would a trap.
The DCTII-AA pushes the current PS and PC onto the stack. The PC is loaded with the value of the
restart address (power-up address + 4), and the PS is loaded with a value of 340 to inhibit interrupts.
The power-up and restart addresses are explained in Paragraph B.6.
NOTE

When developing software for the DCTII-AA on
PDP-ll systems that have memory management, be
aware that the trap sequence is different when executing a halt instruction. Refer to the appropriate
processor handbook.
8.3.2.2

Reset Instruction
RESET EXTERNAL BUS

000005
00

o : o : o : o : o : o : o : o : o : o : o : o : o :

:o:

MA-5263

Condition Codes:

Not affected

The OCT I I-AA reset instruction causes the assertion of the bus clear ( - BCLR) signal. An assert priority in (ASP)) transaction takes place to input interrupt and DMA information. The condition codes
and general-purpose registers RO-RS, SP, and PC are not affected. The - BCLR signal is asserted low
for a minimum of 8.4 /-LS followed by a minimum ISO ns pause. No processor operations are performed
during this pause. The next programmed instruction is executed after the pause. Timing for the
- BCLR signal is a function of the processor clock or crystal frequency.
If the power-fail interrupt is asserted during the reset instruction, it is not recognized until the instruction has completed the -BCLR sequence. This is also true with the PDP-I 1/03, PDP-I 1/23, and PDP11/24.
A power-fail interrupt occurring during a reset instruction in the PDP-II /04 and PDP-II /34 is a fatal
error, and no power-down sequence occurs. PDP-I 1/44, PDP-II/4S, and PDP-l 1/70 reset instructions
are aborted in the event of a power-fail.

B-6

PRELIMINARY
B.3.3 Instructions Not Executed
The DCT II-AA does not execute the PDP-II instructions and op codes listed in Table B-2. An attempt
to execute these instructions causes the processor to trap through location 10.
Table B-2

PDP-Il Instructions Not Executed by the DCTIl-AA

OpCode

Mnemonic

OpCode

Mnemonic

000010
through
000077
0002 10
through
000227
00023N
0064 NN
0065 SS
0066 DD
007000
through
007777

Reserved

0704 SS
07 IR SS
07 2R SS
07 3R SS
0750 OR
0750lR
07502R
07503R
075040
through
076777
10 65 SS
1066 DD
170000
through
177777

MUL
DIY
ASH
ASHC
FADD
FSUB
FMUL
FDIY
Unused

Reserved
SPL
MARK
MFPI
MTPI
Reserved

MFPD
MTPD
FPP Instructions

B.3.4 Effect of the T Bit (Instruction Trace Trap)
The processor status register contains information on the current status of the CPU. This information
includes:
•
•
•

The current processor priority for interrupts.
The condition codes describing the result of the last instruction.
A bit that indicates a trap will occur after the execution of the current instruction.

The DCTII-AA does not allow the T bit to be set directly. This is true of all processors covered in this
appendix, except the PDP-II /04. Only indirect references to the PS can cause the T bit to be set. Such
references occur when executing:
•
•
•
•

RTI (return from interrupt) instruction
RTT (return from trap) instruction
Trap instructions
Exceptions or interrupts

If the RTI instruction causes the T bit to be set, the T bit trap is taken through location 14 before the
execution of the next instruction. If the RTT instruction causes the T bit to be set, the T bit trap is
taken after the execution of the next instruction. The above is true for all processors covered in this
appendix.

The DCTII-AA and all processors (except the PDP-I 1/45 and PDP-I 1/70) acknowledge the T bit trap
before they acknowledge an interrupt that occurs during instruction execution. The PDP-II /45 and
PO P-I 1/70 give the pending interrupt priority over the T bit trap.

---

I f a wait instruction is executed and the T bit is set, the OCT II-AA sequences out of the wait. After the
T bit is serviced the instruction following the wait is executed. This is true of all processors except the
PDP-II /03, PDP-II /45 and PDP-II /70. These processors return to the wait until an interrupt occurs.

B-7

PRELIMINARY
B.4 DCTll-AA INSTRUCTION EXECUTION SEQUENCE ON THE DATA BUS
Each PDP-II instruction executed by the DCTII-AA performs a number of transactions on the
datal address bus. The number and type of transaction is determined by the instruction being executed.
Every instruction that ends in a write transaction to a memory location is always preceded by a read
transaction from the same location.
Using the Move (MOV) Instruction
I n all other processors covered in this appendix, the MOY instruction consists of the following bus
transactions.
•
•
•
•

The processor fetches the op code of the instruction.
The processor then obtains the source operand.
The destination operand is computed.
The source operand is written into the destination address.

The MOY instruction operates similarly in the DCTII-AA and the other processors, except for the last
bus transaction. After the destination address has been computed, the DCTII-AA reads from the destination address before it writes to that address. Clear (CLR) and sign extend (SXT) follow a similar bus
sequence.
This bus sequence is important when connecting the DCTII-AA directly to interface devices. For example, the I ntel'M 8251 A serial interface contains data input and output registers at the same bus address. When the data has been assembled in the input register, the signal (RxRDY) is generated to
indicate the receiver is ready. The RxRDY signal is cleared when the processor reads the input register.
During a write operation to the Intel 8251A data registers, the DCTII-AA first reads the input register
and then writes to the output register. This may result in the RxRDY signal's being cleared. Data may
be lost when RxRDY is cleared in this manner.

NOTE
When connecting interface devices to the DCT 11AA that do not have DEC standard bus addresses
and status registers, it is important to know the device addresses and bit patterns in the status register.
B.5 EXCEPTIONS AND INTERRUPTS
The DCT Il-AA has a flexible hardware and software interrupt structure. Hardware interrupts cause
the DCT II-AA to temporarily suspend program operation in order to execute a service routine. Software interrupts call service routines required by the program. They occur when executing trap instructions or when the trace bit is set in the processor status register. Program execution is resumed when the
service routine is completed.
The DCTII-AA services calls and interrupts in the following order of priority.
I.
2.
3.
4.
5.
6.
7.
8.

HALT (nonmaskable interrupt or instruction)
Power-fail (nonmaskable interrupt)
Trace trap (T bit)
CP<3:0> priority 7 (interrupt)
CP<3:0> priority 6 (interrupt)
CP<3:0> priority 5 (interrupt)
CP<3:0> priority 4 (interrupt)
Trap instruction call

TMlntel is a trademark of the Intel Corporation.

B-8

PREliMINARY
The DCT J J-AA supports a vectored interrupt structure with four priority levels. Interrupts are input on
four coded priority lines (CP<3:0». The value encoded on these lines indicates an interrupt request is
pending from I of 15 devices on I of 4 priority levels. Interrupts are maskable in that the priority code
of the interrupting device must exceed the value in the PS (bits <7:5»; otherwise the interrupts are
not acknowledged.
The DCT ll-AA also has two nonmaskable interrupt lines, HALT and Power-fail (PF). Assertion of
either of these lines interrupts the processor regardless of the priority level in the PS. HALT and PF
have individual input lines. The nonmaskable interrupt HALT is not associated with an interrupt vector. When a HALT interrupt occurs, the current PS and PC are pushed onto the stack, the PC is loaded
with the restart address, and the PS is loaded with 340.
A device requests service by asserting one or more of the CP lines (CP<3:0». If the priority of the
requesting device is higher than that of the processor, the interrupt is acknowledged and the device is
serviced at the completion of the current instruction.
NOTE
If the T bit is set in the PS, the trace trap is taken
before the interrupt is serviced. The T bit must not
be set in the PS word of the T bit trap vector. If it is,
continuous T bit trapping will result.
The current state of the machine is saved so that program execution may continue after completion of
the service routine. The contents of the program counter (address of the next instruction) and the PS
are pushed onto the system stack. The new contents of the PS and PC are loaded from two consecutive
memory locations called "vector locations." The first location contains the address of the service routine and the second contains the new PS value. All information in the vector locations must be loaded
under program control.
NOTE
The device requesting an interrupt must remove the
request when it receives an interrupt acknowledge
(lACK) from the DCTII-AA. If the request is not
removed and the PS word of the service vector does
not contain a prority level as high or higher than that
of the interrupt request, the request continues to be
serviced until the stack is full. This causes a loss of
program and data.
During an interrupt acknowledge transaction, the vector address is provided by either a fixed table
stored in the DCTll-AA (internal vector address) or by the interrupting device (external vector address). Table 8-3 lists the internal vectors assigned to interrupt priority codes.
8.5.1 Bus Errors
The DCTll-AA does not support bus errors. Most PDP-II processors indicate that an error has occurred and interrupt program execution when:
•
•
•

A word instruction executes with an odd address (odd address error).
A nonexistent memory location is accessed (nonexistent memory (NXM) error).
The stack value approaches the vector location area (stack overflow error).

8-9

PRELIMINARY
Table 8-3

Interrupt Priority Codes
Vector Address

Priority Level

New PC at:

New PS at:

Nonmaskable HALT
Nonmaskable PF

Restart address

340
26

7
7
7
7
6
6
6
6
5
5
5
5
4
4
4

140
144
150
154
100
104
110
114
120
124
130
134
60
64
70

142
146
152
156
102
106
112
116
122
126
132
136
62
66
72

If a word instruction is executed and the source or destination address is odd, the least significant address bit is ignored and a word operation is performed at the even address.
If the DCTII-AA attempts to read or write a nonexistent memory location, the transaction is completed and program execution continues. If the transaction is a read, undefined data is received. A write
to a nonexistent memory location outputs data onto the data address lines as if memory is present and
the data is lost.
No warning is given by the DCTII-AA if the hardware stack pointer (SP) decrements below 3778. If it
does, unpredictable results may occur when the contents of the vector addresses are changed.

NOTE
It is important to leave enough room for the stack

area so the vector locations will not be destroyed.
B.5.2 Internal Register Access
None of the internal registers of the DCTII-AA are directly accessible to the programmer as memory
locations. All transactions involving these registers are done internally by the DCT 11-AA. The addresses assigned to these registers by other PDP-II processors are within the 16-bit address space of the
DCTII-AA. These addresses can be used as memory locations or as peripheral device registers.

NOTE
The PS, general-purpose registers RO-R5, SP, and
PC are examples of registers that cannot be directly
accessed by the programmer as memory locations.
B.6

POWER-UP

The DCTII-AA is a flexible microprocessor that can be adapted to many different applications. The
power-up process is used to set one of eight different start/restart addresses. The instruction in the start
address is always the first executed after power is applied to the DCTII-AA. During power-up, or when
executing a reset instruction, the DCTl1-AA loads an internal register with a 3-bit code that represents
one of the eight start/restart addresses. Table B-4 lists the start/restart addresses.

B-I0

PRELIMINARY
Table B-4 Start/Restart Addresses
Start Address
(Used at Power-Up)

Restart Address
(Used for HALT)

000000
010000
020000
040000
100000
140000
172000
173000

000004
010004
020004
040004
100004
140004
172004
173004

NOTE
The start address is used only at the time power is
applied to the DCTll-AA. The reset instruction
loads the mode register; it does not cause the start
address to be loaded into the Pc.

When a halt instruction is executed, or a hardware halt interrupt is asserted, the values of the PS and
PC are placed on the hardware stack. The DCTII-AA loads the PC with the restart address and sets
the PS to 340.
SYMBOLS AND NOTATION
The following symbols are used in the explanations of the various modes described in Table ~-5.

Mode 0 addressing. The contents of the register are to be used as the source operand.

(R)+

Mode 2 addressing. The register contents are to be used as the address of the destination
operand and then incremented by 2 (autoincrement).

-(R)

Mode 4 addressing. The register contents are to be decremented by 2 and then used as the
address of the destination operand (autodecrement).

@(R)+

Mode 3 addressing. The contents of the register are to be used as the address of the address
of the destination operand. The contents of R are incremented by 2 (autoincrement-deferred).

@-(R)

Mode 5 addressing. The contents of the register are to be decremented by 2 and then used
as the address of the address of the destination operand (autodecrement-deferred).

Program counter mode 0 addressing. The contents of the program counter are to be used as
the source operand.

X(R)

Indexed addressing (register mode 6). The value of X is added to the contents of register R
to form the address of the destination operand.

@X(R)

Index-deferred addressing (register mode 7). The value of X is added to the contents of
register R to form the address of the address of the destination operand.

Program counter relative addressing. Relative addressing uses the contents of the location
following the op code as the address of the destination operand.

Program counter relative-deferred addressing. Relative-deferred addressing uses the contents of the location following the op code as the address of the address of the destination
operand.

B-ll

Table 8-5

Software Differences and Compatibilities

:ll

PDP-Ill

Activity

OCT I I LSI-II I 23

aPR %R,(R)+ or aPR %R,-(R) using the same register
as both source and destination: contents of Rare
incremented (or decremented) by 2 before being used as
the source operand.

aPR %R,@,(R)+ or aPR %R,@-(R) using the same register
as both source and destination: contents of Rare
incremented (or decremented) by 2 before being used as
the source operand.

05,10

15,20

35,40

aPR %R,@(R)+ or aPR %R,@-(R) using the same
register as both source and destination: initial
contents of R are used as the source operand.

I X

t:c
,
N

aPR PC,X(R); aPR PC,@X(R); aPR PC,@A; aPR PC,A:
Location A will contain the PC of aPR + 4.

aPR PC.X(R); aPR PC,@,X(R); aPR PC,A; aPR PC,@,A:
Location A will contain the PC or aPR + 2.
4.

IX
X

X
X

JMP (R)+ or JSR reg,(R)+: Contents of Rare
incremented by 2, then used as the new PC address.

X
X

JMP (R)+ or JSR reg,(R)+: Initial contents of R
are used as the new pc.

JMP %R or JSR reg,%R traps to 4 (illegal
instruction).

X
X
X

SWAB does not change V.
SW AB clears V.
Register addresses 177700-177717 are valid
program addresses when used by the CPU.

JMP %R or JSR reg,%R traps to 10 (illegal
instruction).
6.

-.-r-3:
Z
':Jl

aPR %R,(R)+ or aPR %R,-(R) using the same register
as both register and destination: initial contents
of R are used as the source operand.
2.

X
X

Table 8-5

Software Differences and Compatibilities (Cont)
PDP-It I

ocrll LSI-It

Activity
Register addresses 177700-177717 timeout when
used as a program address by the CPU. Can be
addressed under console operation. NOTE:
Addresses cannot be addressed under console for LSI-II
or PDP-II 123.

05,10

15,20

35,40

MARK instruction.

ASH, ASHC, DIY, MUL instructions.

Register addresses 177700-177717 are handled as
regular memory addresses (in the BSIO page). No
internal registers are addressable from either the
bus or the console.

Basic Instructions noted in PDP-II Processor
Handbook.

MFPT (move from processor type).

SOB, RTT, SXT instructions.

O:f
I
w

XOR instruction.

The external option KEII-A provides MUL, DIY and
SHIFT operations in the same data format.

. X

'The KEII-E (expansion instruction set) provides the
instructions MUL, DIY, ASH, and ASHe. These new
instructions are PDP-II 145-compatible.
The KE II-F adds unique, stack-ordered, floating-point
instructions: FADD, FSUB, FMUL, FDIV.
The KEV-II adds EIS/FIS instructions.

mi.

A power-fail during a RESET instruction is not recognized until after the instruction is finished (70 ms).
A RESET instruction consists of a 70 ms pause with INIT
occurring during the first 20 ms.

-.3::_c

SPL instruction.

"'0

::JJ!

»
::JJc

Table 8-5

"'0

Software Differences and Compatibilities (Cont)

::D

PDP-Ill
Activity

DCfIl LSI-Il

05,10

15,20

35,40

A power-fail immediately ends the RESET instruction
and traps if an INIT is in progress. A minimum INIT
of I jLS occurs if instructions aborted.
X

A power-fail acts the same as in the PDP-I 1/45 (22 ms
with about 300 ns minimum). A power-fail during a RESET
fetch is fatal with no power-down sequence.
X

The RESET instruction consists of 10 jLS of INIT
followed by a 90 jLS pause. A power-fail is not
recognized until the instruction is complete.

10.

I I.

12.

If RTI sets the T bit, the T bit trap is acknowledged
after the instruction following RTI.

. I
X

When operating with the T bit set (e.g., when
single-stepping), no interrupt requests will be
serviced. At the end of instruction execution, the
T bit has higher priority than interrupt requests.
Once in the T bit service routine, other interrupts
are blocked to ensure no unexpected occurrences.
When the RTT instruction is executed to leave
the service routine, interrupts will not be
serviced if the T bit is set in the new PS
popped off the stack. The user will, therefore,
not see any interrupt requests he is expecting.

If an interrupt occurs during an instruction that
has the T bit set, the T bit trap is acknowledged
before the interrupt.

I X

X
X

If RTI sets the T bit, the T bit trap is acknowledged
immediately following RTI.

-l>
Z

No RTT instruction.
If RTT sets the T bit, the T bit trap occurs after
the instruction following RTT.

.::D

The RESET instruction consists of a minimum 8.4 jLS
followed by a minimum 150 ns pause. A power-fail is
not recognized until the instruction is complete.

OJ
I

m
r-

Table 8-5

Software Differences and Compatibilities (Cont)
PDP· 11 I

18.

Activity

OCTII LSI· 11

PSW address 177776 not implemented; must use new
instructions, MTPS (move to PS) and MFPS (move from
PS).

Four interrupt levels exist encoded in four lines.

Stack overflow not implemented.

Odd address trap not implemented.

FMUL and FDIV instructions implicitly use R6 (one
push and pop); hence R6 must be set up correctly.

FMUL and FDIV instructions do not implicitly use R6.
23.

Due to their execution time, EIS instructions can
abort because of a device interrupt.

EIS instructions do not abort because of a device
interrupt.

24.

Due to their execution time, FIS instructions can
abort because of a device interrupt.

25.

EIS instructions do a DATI P and DATa bus sequence
when fetching a source operand.

EIS instructions do a DATI bus sequence when
fetching a source operand.

Odd address trap implemented.
22.

35,40

Some sort of stack overflow implemented.
21.

15,20

Only one interrupt level (BR4) exists.
Four interrupt levels exist.

0::1
I

05,10

Z
l>

PSW address and MTPS and MFPS implemented.

20.

PSW address implemented; MTPS and MFPS not implemented.

19.

::u
m
r-

:u
-<

Table B-S

Software Differences and Compatibilities (Cont)
PDP-III

Activity
26.

ocrtl LSI-II

MaV instruction does only a DATa bus sequence for
the last memory cycle.

May instruction does a DATI P and DATa bus sequence
for the last memory cycle.
MaV instruction does a READ (DATI) and a WRITE (DATa)
bus sequence for the last memory cycle.
27.

05,10

15,20

28.

-.l

'If a register contains an odd value in mode 2 and a
bus error occurs, the register will be unchanged.

30.

I
.1

"'tJ'

I X

Condition codes restored to original values after
.,FIS interrupt abort. (EIS does not abort on the
PDP-I 1/35 and PDP-l 1/40.)
Condition codes that are restored after EIS/FIS
interrupt abort are indeterminate.

If a register contains an odd value in mode 2 and a
bus error occurs, the register will be incremented.

Does not support bus errors.

If a register contains nonexistent memory address
in mode 2 and a bus error occurs, the register will
be unchanged.

29.

If a register contains a nonexistent memory address
in mode 2 and a bus error occurs, the register will
be incremented.

Does not support bus errors.

If the PC contains a nonexistent memory address and a
bus error occurs, the PC will be unchanged.

CO
,

If the PC contains a nonexistent memory address and a
bus error occurs, the PC will have been incremented.

Does not support bus errors.

35,40

r
3:,

-'Z

::1'J

Table B-S

Software Differences and Compatibilities (Cont)

"'0

PDP-HI
Activity

3l. Op codes 075040-075377 unconditionally trap
to 10 as reserved op codes.

OCTll LSI-ll

05,10

15,20

35,40

If the KEV-II option is present, op codes 075040075377 perform a memory read using as a pointer
the register specified by the low-order 3 bits.
I f the register contents is a nonexistent address,
a trap-to-4 occurs. I f the register contents is
an existent address, a trap-to-I 0 occurs (if user
microcode is not present). If no KEV-II option is
present, a trap-to-I 0 occurs.

32.

Op codes 210-217 trap to 10 as reserved op codes.

33.

Op codes 75040-75777 trap to 10 as reserved
op codes.

I X

X
X

Op codes 75040-75377 can be used as escapes
to user microcode only if the KEV-II option is
present. Op codes 75400-75777 can also be used
as escapes to user microcode and the KEV-II
option need not be present. If no user microcode
exists, a trap-to-I 0 occurs.
34.

Op codes 170000-177777 trap to 10 as reserved
instructions.

Op codes 170000-177777 are implemented as
floating-point instructions.
Op codes 170000-177777 can be used as escapes
to user microcode. If no user mocrocode exists,
a trap-to-I 0 occurs.
35.

X
X

CLR and SXT do only a DATO sequence for the last
bus cycle.
CLR and SXT do a DATIP-DATO sequence for the last
bus cycle.

-~
-<

Op codes 210-2 I 7 are used as a maintenance
instruction.
t:x:I
I

r3:

IX
X

.,'

Table 8-5 Software Differences and Compatibilities (Cont)
PDP-II/

36.

37.

Activity

0Cf1l LSI-II I 23

CLR and SXT do a READ (DATI) and a WRITE (DATO)
sequence for the last bus cycle.

MEM. MGT. maintenance mode SRO bit 8 is implemented.
MEM. MGT. maintenance mode SRO bit 8 is not
implemented.

PS< 15:12>. user mode. user stack pointer. and the

05,10

15,20

35,40

MTPX and MFPX instructions exist even when MEM. MGT.
is not configured.

PS< 15: 12>. user mode. user stack pointer. and the
MTPX and MFPX instructions exist only when
MEM. MGT. is configured.
t:::tl
I
\0

38. Current mode PS bit < 15: 14> set to 01 or JO
will cause a MEM. MGT. trap upon any memory
reference.

39.

40.

Current mode PS bits < 15:14> set to 01 or 10
will be treated as kernel mode (00) and not cause
a MEM. MGT. trap.

MTPS in user mode will cause a MEM. MGT. trap if PS
address 177776 is not mapped. If mapped. PS<7:5>
and <3:0> are affected.

MTPS in user mode will only affect PS<3:0>.
regardless of whether PS address 177776 is mapped.

MFPS in user mode will cause a MEM. MGT. trap if PS
address 177776 not mapped. If mapped. PS<7:0>
are addressed.

MRPS in user mode will access PS<7:0>. regardless
of whether PS address 177776 is mapped.

,"'0

m
r-

'3C

»
2J
-<

"tJ

Table 8-5 Software Differences and Compatibilities (Cont)

PDP-Ill
Acthity

41.

0Cf1l LSI-Il I 23

05,10

15,20

35,40

x
x

A HALT instruction in user mode traps to 10.

~
I
IV

A HALT instruction in user mode traps to 4.

A HALT instruction pushes the PS and PSW to the
stack, loads the PS with 340, and loads the
PC with power-up address + 4 (restart address).

43.

Resident ODT microcode.

44.

All data outs (DATOs) are preceded by a data in
(DATI).

45.

Instruction execution runs to completion regardless
of bus errors.

46.

Vector address range limited to 4 to 374.

Z
l>
:xJ

42.

:u
m
r-

Table 8-6 Hardware Differences - Traps
(Transparent to Software)

ttl
I
IV

DCTll

PDP-ll/23

PDP-ll/04

PDP-ll/34

Priority of internal
processor traps, external interrupts,
HALT and WAIT:

TRAP instructions
HALT interrupt
TRACE trap
External vector
interrupt
I nternal vector
interrupt
Power-fail trap
WAIT loop
Test mode request

Memory parity errors
Memory management
Fault
Bus error traps
TRAP instructions
TRACE trap
OVFL trap
Power-fail trap
Console bus request
QBus bus request
WAIT loop

Bus error trap
TRAP intructions
TRACE trap
OVFL trap
Power-fail trap
Unibus bus request
Console HALT
WAIT loop

Memory parity errors
Memory management
Fault
Bus error traps
TRAP instructions
TRACE trap
OVFL trap
Power-fail trap
Console bus req uest
Unibus bus request
WAIT loop

LSI-ll

PDP-ll/05,IO

PDP-ll/15,20

PDP-II /35,40

Priority of internal
processor traps, external interrupts,
HALT and WAIT:

Priority of internal
processor traps, external interrupts,
HAL T and WAIT:

Bus error trap

Memory parity errors

"tJ

"-m
-»z

r
3C

"-<

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I1IT-ll User's Guide

EK-DCTII-UG-003

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