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EK-DMR11-TM-002
May 1981
162 pages
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Document:
DMR11 Synchronous Controller Technical Manual
Order Number:
EK-DMR11-TM
Revision:
002
Pages:
162
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OCR Text
EK-DMR11-TM-002 DMR11 synchronous controller technical manual digital equipment corporation ¢ merrimack, new hampshire 1st Edition, May 1980 2nd Printing, September 1980 2nd Edition, January 1981 Copyright © 1980, 1981 by Digital Equipment Corporation The material in this manual is for informational purposes and is subject to change without notice. Digital Equipment Corporation assumes no responsibility for any errors which may appear in this manual. Printed in U.S.A. This document was set on DIGITAL’s DECset-8000 computerized typesetting system. The following are trademarks of Digital Equipment Corporation, Maynard, Massachusetts: DIGITAL DEC PDP DECUS UNIBUS DECsystem-10 DECSYSTEM-20 DIBOL EDUSYSTEM VAX VMS MASSBUS OMNIBUS 0S/8 RSTS RSX IAS CONTENTS Page PREFACE — B o DN — e e et e e 1-1 s GENERAL SPECIFICATIONS ..ottt 1-5 POWer REQUITEIMENTS .. ..eveiiiiiiiieiiieeeiiiie ettt e e e e e nee e s eaaee e neen s 1-5 Environmental Requirements ~ A1l DMRI1s ..o 1-7 EIA STANDARDS OVERVIEW (RS-449 vs RS-232-C) ..o, 1-7 NY ek Mt bd e et et et met e e DMRI11 GENERAL DESCRIPTION ...ooiiii e, 1-1 DMRI11ISYSTEM OPERATION .....ooiiiiiie et 1-3 Command SETUCLUTE.....oee et eeee et e eeeeneeeesessraeeaaneeeeee e s 1-4 INPUt COMMANGS ...uviiiieiiiie ettt eee e e 1-4 OUtPUL COMMEANAS....iiiieiee ettt ecteee e e rirre e e arat e e e an e e e e s 1-4 DMRI11 Operation SEQUENCING ...ceeeieiieeieereceeeiiieeeeeeeee e eeeeetes e eee s 1-5 Maintenance Mode Operation.............ucieesirreereneeieieiiieiieiii e 1-5 INSTALLATION e e 2-1 S O PE .o UNPACKING AND INSPECTION . ..o 2-1 — — . . —— N |\ I = e o b — R B RO RN RN BN N D o el CHAPTER 2 N b DB LW W INTRODUCTION SCOPE . ek s CHAPTER 1 I [\ W W W W NN RN — CHAPTER 3 INSTALLATION CONSIDERATIONS ... 2-1 PREINSTALLATION CONSIDERATIONS ...t 2-1 System and Device Placement...........ccooviiiiiiiiiiiiiii 2-2 System Placement........ooocuiiiiiiiiiiiiiii 2-2 Device PlaCement ....ouiiiiiieieiiiiee e 2-3 SYStEmM REQUITEMENTS ...vovveeeeieieeieeeeveeie e este et sae e ene e, 2-3 MICROPROCESSOR INSTALLATION ...t 2-4 Backplane Considerations ...........ooeeueeuerireemeniioiiaieseesee e 2-4 eeeiiiiieeesee 2-4 e siesierreeeeeeeeseaanneenans M8207-RA ConSIAErations......ccoeurrrueeieiee eieee 2-6 e eeenae e e s eesebee e s eebeeeeeaeeseaaeeanneas etttiieieiieiee MB207-RA INSEIION c..vveiiiee ettt ettt e e ee e 2-7 LINE UNITINSTALLATION L..ootiii ee 2-17 e ee e eee ettt M 8203 ConSIAETATIONS ..evieeeeiieiiiiiiie anraaae e e e 2-23 eeeeee e e e e eaeaeeee e e e e s e e et e iiiieeeeeeee MB203 TNSEITIOM .eeveveiiiie DMRITSYSTEM TESTING ...ttt 2-28 eirice 2-29 e e Functional Diagnostic TeStINE......couvirriiiiiiiieeieeiicee 11 System EXErCISer ....ccoiiuiiiiriiiiiiiiie et 2-29 DECX s 2-32 rnnaneeee e e eeeiiieiiieeeee Final Cable CONNECIONS ....cvviiiii ce s e ea e 2-32 ee e e DMRIT LINK TSN ettt DMRI11I-XX INSTALLATION CHECK-OFF LIST ..o 2-37 PROGRAMMING s e eeeeeseeaneeeesennnaaaeaanas 3-1 e e s e e e e et eett INTRODUCGCTION...ot 3-1 tt st ... STRUCTURE. COMMAND Control and Status REZISTETS .. ...uuuiiiiiiieiieeeiiiiiieeeeeeeeeseniereeeeesenreeeesseeeeees 3-1 | Bs VAR T Y V4213 o) AP OO P PP 3-4 iii CONTENTS (CONT) v I — V) N SOV i R B SR DU N L [PV B I Receive Buffer Address;/Character Count Out (RBA CCO)........ccvieennnnon. 3-22 Transmit Buffer Addresfl/Chamuer Count Out (TBA/CCO).covvvveee 3-23 Control QUL oo e e 3-24 imio | I e th ' i sd Tad ad et sd Tt Cad ad T | D IOV NTG — — — N IR [ ) NI I I ad 1D Td "D ' PROGRAMMING TECHNIQUES ... e 3-25 Input Command SEQUENCE ........ovviiiiiiiiiiiiiiee e 3-27 Base In Command with Resume Feature ..o 3-27 Distinguishing DMRI1T from DMCHI1 ..., 3-30 DDC P Maintenance Mode Operation .............ooooeeiiiiiiiiiiiiiiieiiiieeee, 3-30 Data Transler. ..o 3-30 Unattended System Control ........ccocoooiiiiiiiiiiie e3-30 BASE TABLE COUNTERS...., 3-31 e R R D T Modem Status Read.........ooooiiiiiee e, 3-8 Output Commands OVETVIEW ......ocueieeeieeee e 3-13 Output Command Handshaking ..............cccooiiiiiiiie 3-14 INPUT COMM AN S L e 3-14 Base In ..., TR 3-16 Control IN ..o 3-17 MODEM CONTROL ... e 3-34 Modem Control Implemented in M8203.................ccciiiiiiiii i3-34 Modem Ready Lockout of RTS ..., 3-34 Half-Duplex Mode..........ccooiiiiiiece e 3-34 Modem Control Implemented in DMR 1 Microprogram...............ccceee 3-34 A ULO-ATISWET ..ottt e e e et e e e e e e e e e e e e e eeeeneaans3-34 Data Set Ready Glitch.......oooiiiiiiiiee e 3-35 RTS —CTS Dl uueeiiiiiiiiec e 3-35 Loss of Carrier Detect .......... e 3-35 Receiver Inactive Check ... 3-35 o ~N I R 1ot 0 Tad 1d Input Commands OVEIVIEW ......uuueiiieiieiieeeee e, 3-6 Input Command Handshaking .....cccoceeriiiiiiiii e 3-7 Receive Buffer Address/Character Count In(RBA,/CCD.....ccvieeeiii 3-18 Transmit Buffer Address/Character Count In(TBA CCly....ooeeeeeeeiee. 3-19 Halt Request Command ... 3-20 OUT PUT COMMANNDS e, 3-22 ad ) et M 9 00 10D ) 'Jn;Jl ;Jl.-‘—-‘d-‘--‘-'.hl'ad'.fl o) 0 ' d 0 e T DI I 1D 9 [N Page Modem Status Read During Input Command ...........cccocon, 3-35 Data Terminal Ready Control.........ooeiiiiim e, 3-36 DMRI1I DATA LINK FUNCTIONS L. 3-36 SERVICE N L0 ] 34 S PRSP4-1 MAINTENANCE PHILOSOPHY ..o4-1 MAINTENANCE FUNCTIONS/MAINTENANCEMODES..........o.4-1 Maintenance Register (BSEL 1) ..oviiiiiiioe oo -1 Maintenance Modes...........oooevviivrieeennnn.. e B Maintenance Modes..........ooovviiviviieiieeieeeeeeeeeeeeeeeeeeeeeene e A2 SYSEM TESL..ueiiiiiieiieeeieee e e B2 Single Step Internal Maintenance Mode ... 42 System Test Internal Maintenance Mode.. -2 External Maintenance Mode ......oooooiiiiiiiiiiiie SR 2 iv CONTENTS (CONT) APPENDIXD MICROCODE OVERVIEW D.1 INTRODUCTION . .ot D.2 D.3 D.3.1 D.3.2 D.3.3 FUNCTIONAL HARDWARE ... DMRI11I MICROPROGRAM ... Microprogram Message Processing .........coooooiviiniinnen, e e e e e e e neee s e s eiree e s e e e e e et trbeeii T AN PrOCESS .. eteeeiiiieee r ee e ite e enee eei e ee s b iee e e e eeeetinin R ECEIVE PrOCESS .. eieeei APPENDIXE BOOTSTRAP TEST UNDER ITEP E.l REMOTE LOAD DETECT ... e E.2 E.2.1 E.2.2 E.3 E.4 DMR11SETUP FOR REMOTE LOAD DETECT ..., ............. DMRIT AdAreSSing ..uvvvieeieiieeeer i DMRIT LN Unit SELUP ..vvveiiiieieiiiiiiirieieee e PROCEDURE TO TEST REMOTE LOAD DETECT UNDER ITEP PROCEDURE TO TEST DOWN-LINE LOAD UNDER ITEP GLOSSARY FIGURES Figure No. Title 1-1 1-2 1-3 c e Typical PDP-11 ApplCations ......coooeiiiiiniii e iiniee iiiiii .ooovi ...... ions AppHCat /780 Typical VAX-11 tsis s iiimiii ieriiii vivriir ......o INE SEGUENC on DMR11 Operati 2-2 2-3 e M 8203 Switch/Jumper LOCations.......ooocveiiiiiiiiiiii . . . ion Installat Unit ine cessor/L Micropro 2-1 2-4 2-5 2-6 2-7 2-8 3-1 3-2 3-3 3-4 3-5 MB8207-RA Microprocessor Switch/Jumper LOCations.........cooevrenen. DMRI11 Cable Drawings.....ccovereeiiiiumiiriiiirree i iiiis sareeeeees DMR11 Turnaround Test CONNECLOTS ....cuviviimuieeenvircnirin DMRI11 Remote System Cabling Diagram............coooviiinninne DMCI11 to DMRI11 Integral (Local) Modem Cabling Diagram............. DMR11 to DMRI11 Integral (Local) Modem Cabling Diagram.............. UNIBUS Control and Status Registers Format Overview ...................... Programming Example for Input Commands.........oooeiii e Input Command SETVICING ...coverveirminriiiiini i Modem Status Read FOrmat....c..c.eevvieeiiiiiimiiiiiii iii s Summary of Control Out Status ......coooeeniii 3-6 ss s Output ComMand SETVICINZ.......ovrrumiirirererresiieiemss 3-9 Start/Stack Sequence TIMeT ........coooviiiiiieniii 3-7 3-8 e Base In Command FOrmat ......o.oooeveieiriiiiiimiii Control In Command FOrmat .......eueeiiiininiier vi CONTENTS (CONT) Page Maintenance (LED) INAICators. ..o ueeeeeeeeeee e e e 4-3 PREVENTIVE MAINTENANCE (PM)...oooiiiiiie e, 4-5 CORRECTIVE MAINTENANCE ON A PDP-11 PROCESSOR....................... 4-5 CZDMPH*/CZDMQ¥ ...t 4-6 CZDMR¥*/CZDMS¥ et 4-8 CZDMI¥e e e e et e e e 4-9 DMRI11 Microdiagnostic Error Reporting ..........ccoocoiiiiniiinn 4-11 ZDMO** - DMC11/DMRI11 Overlay for Interprocessor Test Program (ITEP).....coo oot4-12 DEC/XT1I DMCTTI MOAUI€...oiiiiiiiiiiiiiec ettt4-13 Soft Error Reports Under DEC /X 1 1...ccoiiiiiiiiiiiiiccieee e4-16 Examination of DMR11 Internal Components.......ccccooeveeeiieeneeeceeieennenns4-16 CORRECTIVE MAINTENANCE ON A VAX-11/780 ... ..cueiieiieiiiiceee4-18 EVDXA COMM Microprocessor Repair Level DAZNOSTICS e eeeeiiiiee e e e e e et ee e e e e e e ee e e e e e et e e tetareeraan 4-19 EVDMA Repair Level Diagnostics ......cecceerieeeriiiceiiieieeiieiceiee e, 4-23 EVDCA REV *.* VAX-11/780 Synchronous Link Level Two DEAZNOSTICS ..ttt et a e e eanaeas 4-24 Examination of DMRI1 Internal COmMpONents........c.ooovevveeveevienieiceneennes 4-24 FLOATING DEVICEADDRESSES. ... A-1 FLOATING VECTOR ADDRESSES ..o A-2 EXAMPLESOF DEVICE AND VECTOR ADDRESS ASSIGNMENT ......... A-4 APPENDIX B DDCMP IN A NUTSHELL 15 1 B @01 U UPPTURPPPPPUPIR B-1 Controlling Data Transfers .........cooooiiiiiiiiii e B-1 Error Checking and RECOVETY ......cvvviiiiiiiiiiieii e B-1 Character COAINE . ... .uueeee e eaee e B-3 Data TranSParenCy ......cooooiiiiiiiiiiiiee e eeeeeeee ettt e eeeaeeeee e enseeeeeeanns B-3 Data Channel UtIHZation .........ocoooiiiiiiiiiiieeee e B-3 PROTOCOL DESCRIPTION....ttt B-3 MESSAGE FORM AT L e B-6 DIAGNOSTIC SUPERVISOR SUMMARY VERSIONS OF THE DIAGNOSTIC SUPERVISOR ..ot C-1 LOADING AND RUNNING A SUPERVISOR DIAGNOSTIC..........ccoee. C-1 Five Steps to Run a Supervisor Diagnostic .........ccoeeeiiiiiiiiiiiiiiiiee i C-2 SUPERVISOR COMMANDS ..o C-3 Command SWILCRES ... .. C4 Control/Escape Characters Supported..........ooooiiiiiiiiiiiiiiiereeeeee C-5 WHAT IS THE SETUP UTILIT Y e C-5 — INTRODUCTION .. C-1 N — u\:b-.-b-b':uwt\)-—- APPENDIX C NOONANNAN ) R e e N BN — > > > o — FLOATING DEVICE ADDRESSES AND VECTORS Twoowmww APPENDIX A FIGURES (CONT) Title Page S I VS S UV SR UV R VS SN RN W LI Receive Buffer Address/Character Count In Command Format ........................ 3-20 Transmit Buffer Address/Character Count In Command Format...................... 3-21 Halt Request Command FOrmat........cccooeiiniiiiiiiiniciiiiiii e 3-22 Receive Buffer Address/Character Count Out Command Format....................~3-23 Transmit Buffer Address/Character Count Out Command Format................... 3-24 e 3-25 Control Out Command FOrMAL .......ooviiiiiiiiiiiecc e3-28 DMR11 Protocol State Diagram .......ccooiveeiiiiiiiiiciiiiininirii Down-Line Load Procedure to Remote Station......ccoocceeerimiiiiiiiniiiiineeineeeennenn 3-32 e 3-33 1 Base Table Error COUNTETS ....cceiiiiiiieeiieeeeeiieeniie DMR S M 8203 Maintenance LED Locations/Heartbeat Waveform ..., (@R M- Recing IS DMR11 Base Table Layout.........cccoovrevivecenecnenn Heeteerteeteereaaeesaeenevasestanaeensanns4-20 e et UNIBUS Address Map .. .coooieee oot DDCMP Data Message FOrmat... ... DDCMP Sample Handshaking Procedure ... DDCMP Message Format in Detail........oooooiiis XXDP+ /Diagnostic Supervisor Memory Layout on a (Min Memory) D mm == b Gt — wlvlwiwlw W SYSTEIM Luiiiiiieiiieiiiieees e e e e FOK es s s e e s e sttt s D-2 eeeeie ettt sie et Data and Control FIOW = BASIC .uveiiiiiieeiieeci eenas D-5 s ene e ean e e eieeeeeee esaea e secees et iiieeiieii ..ooiviiii Executive FIOW DIAZIAM . D-6 e niniieseieesiecsie ccoivueiiiiiinimimi ProCessing........c Typical DMR 1 Message D-7 e eiiiceeicc ........cccooiiiiiiiiiie Diagram Transmit Process FIow Receive Process FIOW DIagram . .c..oooiiiiiiiiiiie e D-8 Down-Line Load to Remote End Using Remote Load Detect......................... Remote End Request for Down-Line Load ...........oooo TABLES N DN — BRI BN BN N MO RO DD MO ] 1] ] [] 1 ] ] [) ] ] _——— \D 00~ ON BN o — O ] ' B — e Title Page et e s e et DMRIT OPUONS ..eeeeiiitee ettt i, DMR11] Performance Parameters .......ooouiiiiiiiiiiiii DMR 11 Option Packing List ......cccooiiiiiiiiiiiiiiiiii e DMR11 Voltage Chart....coooiiiiiiiiiiiiiiiiiiiiiiie M8207-RA DMRIT Jumper Chart... ...t SwitCh Pack E127 SeleCtionS. ..uuiiiiiieiiii ettt eieee t iiiiii e e e e e e e ee e Switch Pack E28 SEleCtiONS ..oooiiiiiii e 2-10 Switch Selectable FEAtUTESs ...cooovviiiiiiiiiiiiiiieie Normal M8203 Configuration (Bootstrap Not Selected)............oocoiiiiiiiinnns 2-11 M 8203 Jumper FUNCHOMNS. ..coiiiiiiiiii it 2-12 ieic 2-13 eeiree e et iiiiii Switch Pack E39 (Z) SElECtIONS .. .uvvviereiii iieeeae 2-14 e eiiiiiii Switch Pack E121 (Y) SeleCtiONS. .....uuvueiiiiiee Switch Pack E134 (X) SEIECtiONS. ..uuveieeriiiieieeiiieeieeiiiteeeeeeiieeeeessereiesseennesanas 2-16 ecre 2-18 tt eeeti ettt et et ettteeeit Cable DESCTIPHON .. vviiieteei vii z ) 4 (8] s W — — OO SN Wi e o "W R OO ~I O B — oo W PEEPE e e £ - = TABLES (CONT) Title Page Modem Option Jumper FUNCIONS .........vvuemiiiiiiiieeieeeeeeeerereere e 2-27 SEL O Bit FUNCHONS ..coecoiieiiciieeee ettt s A 3-2 BSEL 2 Bit FUNCHIONS.....eoiiiiiiieieieiie ettt e e eetee e e etee e s s s e s saseee e 3-5 INPUL COMMEANAS ....coiiiiiieiiiiiiiiece et e e e ee ettt e e e e e e e e ee s anareaeeeeeeenes 3-7 Modem Status Bit Descriptions..........ccooocviiiiieieeeeeeererernereeeeeee e——————————— 3-11 Data Port Descriptions with Control In.........ccccoeiiiiiiniiiiii e 3-18 Data Port Bit Descriptions with Control OUut...........ccccvieeiiieeniiiee e 3-26 DMRI1 Command SEQUENCE........ceeeeiueieeeiiieeeiireeeeieeeesereee e e esneeeeseeeeesnans 3-29 Invalid Enter MOP Message RESPONSE.......c..ccveeueieiieienieeieneenee e e 3-31 BSEL [ Bit DESCIIPLIONS. ...vveieveeeieeeieiireeetieeireeieeeseeesaeeesseeeiaesareesnee e nessassasaseenns 4-4 Maintenance INAICALOTS .....ocuviiiieieeeeeeeeieeeeeteeeeereeeeiteeereeesneeesateesbreeseneeseeaeseanes 4-6 CZDMP* Diagnostic SUMIMATY .....ceerverrieeeieeniteeniie et nteeseeesie s siss e ene s4-8 DZDMQ* Diagnostic SUMMATY .......eeeviierirniiree e eeeesiis e sree e re 4-9 eeseeeeeree 4-10 CZDMR* Diagnostic SUMMATY......ooeieuiieieieecerieeeiereeeseeessnaessanees ee4-11 sec e saes s srne s eaae CZDMS* Diagnostic SUMMATY ..c..oeiiiieeeiieeniienr CZDMI* Diagostic SUMMATY ....cccuiieiuieeiieeerireeeite sttt e e e siae s saeeseaae 4-12 DDCMP Message Decode for DMRITT** i 4-14 Major FUNCtional ATEas.......c.occeveeieiiiiiiieiiin et D-3 VIii PREFACE This manual describes in detail the installation requirements, programming considerations, and servicing procedures, including diagnostic support, for the DMR11 Synchronous Controller. A variety of appendices are also provided to supplement the above. Other publications which support the DMR11 Synchronous Controller are: M8207 Microprocessor Technical Manual (EK-M8207-TM-001) M8203 Line Unit Technical Manual (EK-M8203-TM-001) DMRI1 Print Set (MP-00911) Electronic Industries Association (EIA) Specifications ' CHAPTER 1 INTRODUCTION 1.1 SCOPE This chapter contains a brief introduction to DMR11 operation. The term DMRI1, as used throughout this manual, denotes the communication subsystem which consists of a microprocessor module and a line unit module. 1.2 - DMRI11 GENERAL DESCRIPTION The DMRI11 is designed to be used in a network link for high performance interconnection of VAX11/780 or PDP-11 computers. It is a microprocessor-based, intelligent synchronous communications controller which employs the DIGITAL Data Communications Message Protocol (DDCMP). The DMRI1 is program compatible with DMC11 and line compatible with either DMCI1 or any device that uses DDCMP version 4.0. Features of the DMRI11 include: e Extensive error reporting, e Down-line and remote load detect to attended or unattended PDP-11 processors (requires bootstrap option), e Modem control. e Auto-answering capabilities, e DMCI1I program compatibility. e Switch selection of DMC11 e Comprehensive diagnostic tests. e Support for local or remote. full-duplex or half-duplex configurations, e 16-bit non-processor request (NPR), direct memory access (DMA) transfers, and e line compatibility mode or DDCMP V4.0 compatibility mode, DDCMP implementation which handles message sequencing and error correction by auto' matic retransmission. The DMR 1 basic unit consists of the M8207-RA microprocessor and the M8203 line unit. The microprocessor serves as a parallel data interface between the central processor (VAX-11/780 or PDP-11) and the M8203 line unit. This line unit/microprocessor combination permits either remote or local computer applications. (For remote operations, computers are connected through external modems that use common carrier facilities.) See Figure 1-1 for PDP-11 applications and Figure 1-2 for VAX11/780 applications. 1-1 (REMOTE) SIS | | SYNCHRONOUS BCO8S-1 | COMMUNI- | BCO5Z-25 MICROPROCESSOR CATIONS (M8207-RA) ncCcow-—2«C BC55B-10 pieec.10 MODE LINE ODEM UNIT 8-BIT (M8203) SERIAL DATA | SYNCHRO- TO REMOTE STATION DATA NOUS VIA TELEPHONE LINES (BIDIREC- SERIAL TIONAL) DATA (LOCAL) COMMUNI- | MICROPROCESSOR <:f"> ffl;o”s { M8207-RA ) UNIT | '(';’;:L MODEM 8c08s1 | (M8203) BC55A-10 SYNCHRONOUS s'ERIAL DATA * TO LOCAL STATION VIA TWINAX OR TRIAXIAL CABLES PDP11 MEM N MK-2241 Figure 1-1 Typical PDP-11 Applications The DMRI11 system consists of a basic subsystem and four options which allow it to accommodate standard and special interface configurations. With these options, DMR 1 systems can operate with speeds ranging from 2.4K bits per second (b/s) to IM b/s (see Table 1-1). Table 1-1 Option DMRI11-AA DMRI11 Options Interface Line Speed EIA RS-232-C* EIA RS-423-A/ Upto 19.2K b/s Up to 56K b/st CCITT V.10 DMRI11-AB 1SO2593/CCITTV.35¢ Upto IMb/s DMRI11-AC Integral Modem 56K, 250K, 500K, IM b/s DMRI11-AE EIA RS-422-A/ UptoIMb/s CCITT V.11 *EIA - Electronic Industries Association +1SO - International Standards Organization CCITT - Comite Consultatif Internationale de Telegraphic et Telephone 1 Limited to 20K b/s by RS-449 and 9600 b/s by ISO 4902 1-2 VAX CPU (REMOTE) UNIBUS —| ADAPTER | MEM PROCESSOR CONT. M8203 M8207-RA ' OMR11 LINE UNIT MICRO- B MEM VAX DMR11 BCO8S-1 BC55B-10 nCcw-—-2c«C MASSBUS | MASSBUSS | ADAPTER BC55C-10 |— BCO52-25 MODEM 7 TELE. v <:> DMR11 PR MICROOCESSOR M8207-RA BCO8S-1 < v > (LOCAL) T DMR11 UINE UNH.:INTEGRAL Ma203 | | MODEM ACSSA SYNCHRONOUS SERIAL DATA TO LOCAL STATION VIA TWINAX OR TRIAXAL CABLE MK-2240 Figure 1-2 Typical VAX-11/780 Applications The basic subsystem is designated DMR11-AD and consists of an M8203 line unit, an M8207-RA microprocessor. a BC0O8S-1 interconnect cable, an H3254 interface module test connector, and an H3255 interface module test connector. The M8203 line unit has an Integral Modem which is switch selectable to operate at speeds of 56K, 250K, 500K, and IM b/s. For local operations through Integral Modems, systems are interconnected by twinax or triaxial cables in either half-duplex (one cable) or full-duplex (two cables) configurations. The DMR11-AC option is used for local operations. A maximum distance of 6 km (18K feet) at 56K b/s can be obtained using recommended cables. For information on recommended cables, data rates/distance, and fabrication techniques for twinax/triaxial cables, refer to the M8203 Line Unit Technical Manual, EK-M8203-TM-001, Appendix B. For specific information on the installation of the DMRI1 basic subsystem and its options, refer to Chapter 2. 1.3 DMRI11 SYSTEM OPERATION Operation of the DMRI11 is initiated and directed by a user program residing in the central processing unit’s (CPU) memory. A user program consists of an application program and a device driver routine 1-3 that interfaces with the DMR11. Communication between the user program and the DMRI11 is accomplished by four 16-bit control and status registers (CSR) integrated to the microprocessor. These CSRs are used for initializing, selecting the mode of operation. assigning receive or transmit buffers to the DMR 11, obtaining receive and transmit buffer returns from the DMR 11, and error reporting. The first two registers in the group have a fixed format and serve as a command header for the second two registers. The second two registers form a two-word data port for the exchange of unigue con- trol /status information between the DMR11 and the user program. Data port contents are specified by an identification field in the command header. Other fields in this header control interrupt enabling and status bits for command transfer handshakes between the main CPU and the DMRII. A user program issues a command to the DMRI1 by setting up the input command header and requesting the use of the data port. When the DMR 1 grants permission to use the data port. the user program passes the command to the DMRI11 in the pertinent CSRs. The DMR11 interprets the command and performs the specified actions. The DMRI1 issues error or status information to the user program by storing the command in the pertinent CSRs and by notifying the user program that the status is available for retrieval and processing. Message data received or transmitted by the DMR11 is written into or read from the user program assigned buffers in the main CPU memory. The DMRI11 accesses these buffers through NPRs to a UNIBUS address. A UNIBUS address is an 18-bit address used by an NPR device to access a device on the UNIBUS or a location in main CPU memory. Command Structure 1.3.1 As previously stated, communication between the main CPU resident user program and the DMRI11s accomplished through a set of four 16-bit UNIBUS CSRs. This is accomplished by using these CSRs to implement an input and output command structure. There are five input and three output commands. Their functions are discussed in Chapter 3. Input 1.3.2 Commands Input commands are issued by the user program to initialize, select the mode of operation, and assign receive or transmit buffers to the DMRI11I. Output Commands 1.3.3 Output commands provide a means for the DMR1 to report various normal and abnormal (error) conditions concerning the data transfer operation. Two basic commands are provided: . Receive or Transmit Buffer Address/Character Count Out and 2. Control Out The Buffer Address/Character Count Out command is used to report a successful, error free completion of a receive or transmit buffer and it indicates the actual number of bvtes transferred. This command utilizes both Select 4 (SEL 4) and SEL 6 to identify the address of the completed buffer and the actual character count of the transfer. 1-4 The Control Out command is used to report specific conditions concerning the DDCMP, the user program, the hardware. or the modem. Control Out utilizes SEL 6 to inform the user program as to the nature of the report (refer to the following). e Error Status Identifies the reason for the error condition (errors can be associated with the DDCMP. the user program, the modem, or other hardware limitations). In some cases the error condition is non-fatal and normal operations can continue. Other errors are fatal, causing the DMR1 1 to shut down. 1. 3.4 DMRI11 Operation Sequencing h o The e nor normal sequence of operation }) is represenied in the flow chart in Figure i-3. The user program initializes the DMR11 by issuing the Initialize command with the Master Clear bit set. When the DMRI11 has completed the initialization. it sets the Run bit. At this point the user program assigns a 128-byte Base Table in CPU memory to the DMR11 for maintaining error counters and storage of vital information on shut-down. This is done using the Base In command. The user program via the Control In command then sets the DMR 11 for either half-duplex or full-duplex and either DDCMP Normal or DDCMP Maintenance Mode. If Normal DDCMP Mode is selected. DMRI1 initiates protocol start up. The user program should now assign transmit and receive buffers to the DMR11 via the Buffer Address/Character Count In command. When a transmit buffer is assigned. the DMR11 issues an NPR to retrieve the data from CPU memory for transmission on the serial line. If there are receive buffers assigned when the DMR11 receives data over the serial line, it issues an NPR to transfer the data to the CPU memory. The DMRI1 performs message sequencing, link management, cyclic redundancy check (CRC) error checking, error connection via retransmission, and some error reporting to the CPU. 1.3.5 Maintenance Mode Operation A special DDCMP message format, the maintenance message. is used for down-line loading. restart- ing, or otherwise maintaining satellite computer systems. Messages in this format are subject to error checking but are unsequenced, unacknowledged, and not retransmitted automatically by the microprocessor. The user program must initialize the DMR11, give it a Base In with the Resume bit clear, and then give a Control In to put the DMRI11 in Maintenance Mode. 1.4 GENERAL SPECIFICATIONS The following paragraphs contain performance, electrical, and environmental specifications for all DMRI11 configurations. Table 1-2 lists the performance parameters of the DMRI!. 1.4.1 Power Requirements The M8207-RA and M8203 line unit power requirements are listed below: Module Voltage Rating (Approximate Values) M8207-RA + 5 volts @ 5.0 amperes M8203 + 5 volts @ 3.0 amperes +15volts @ .11 amperes -15volts @ .2 amperes 1-5 VAX/PDP-11 PROGRAM VIA MASTER CLEAR ASSIGN 128- BYTE BASE TABLE - VIA M MAND BASE | IN COM SET UP PROPER MODE HALF-OR FULL-DUPLEX AND NORMAL DDCMP OR VIA CONTROL IN COMMAND DDCMP MAINTENANCE DMR11 INITIATES THE v PROTOCOL START UP SEQUENCE VIA BUFFER ADDRESS/CHARACTER COUNT IN COMMANDS ASSIGN TRANSMIT & RECEIVE BUFFERS DMR11 IN DDCMP RUNNING MODE AFTER COMPLETION OF DDCMP START SEQUENCE RECEIVE TRANSMIT DMR11 (1) PROCESSES DMR11 (1) GENERATES DDCMP THE RECEIVED HEADER, (2) PROTOCOL HEADER, (2) GEN- CHECKS CRC CHARACTERS, (3) ERATES AND TRANSMITS CYCLIC REDUNDANCY CHECK (CRC) CONTROLS ACKNOWLEDGEMENTS (ACKS) OF CHARACTERS SAGES AND NEGATIVE ACKS (NAKS) FOR PROPERLY RECEIVED DATA MESERROR MSGS. THE DMR11 PERFORMS MESSAGE SEQUENCING, CRC ERROR CHECKING, RETRANSMISSION, SOME ERROR REPORTING TO THE PDP-11, AND LINK MANAGEMENT MK-2323 Figure 1-3 DMRI11 Operation Sequencing 1-6 Table 1-2 DMRI11 Performance Parameters Parameter Description Operating Mode Full-Duplex or Half-Duplex Data Format Synchronous DDCMP Special Data Rates Up to IM b/s Cable Length Refer to M8203 Line Unit Technical Manual, EK-M8203-TM- 001, Appendix B Environmental Requirements - All DMR11s 1.4.2 The DMRI1 is designed to operate in a Class C environment as outlined in DEC Standard 102. 1.5 e Operating temperature range - 5°C to 50°C (41°F to 120°F) e Relative humidity - 10 to 90 percent with a maximum wet bulb of 28°C (82°F) and a minimum dewpoint of 2°C (36°F) EIA STANDARDS OVERVIEW (RS-449 vs RS-232-C) The most common interface standard used in recent years has been the RS-232-C. It does. however, have serious limitations for use in modern data communications systems: the most critical being speed and distance. For this reason. the RS-449 standard has been developed to replace the RS-232-C. It maintains a degree of compatibility with RS-232-C to accommodate an upward transition to RS-449. The most significant difference between RS-449 and RS-232-C is the electrical characteristics of signals used between the data communication equipment (DCE) and the data terminal equipment (DTE). The RS-232-C standard uses only unbalanced circuits while the RS-449 uses both balanced and unbalanced electrical circuits. The specifications for these different types ofelectrical circuits supported by RS-449 are contained in EIA Standards RS-422-A for balanced circuits and RS-423-A for unbalanced circuits. These new standards permit much greater transmission speeds and will allow greater distances between the DTE and DCE. The maximum transmission speeds supported by RS-422-A and RS-423-A circuits vary with circuit length: the normal speed limits being 20K b/s for RS-423-A at 200 feet and 2M b/s for RS-422-A at 200 feet. These normal speeds can be exceeded in special applications by trading speed for distance, or vice-versa. Another major difference between RS-232-C and RS-449 is that two new connectors have been specified to allow for the additional leads needed to support new circuit functions and the balanced interface circuits. One connector is a 37 pin cinch used to accommodate the majority of data communications applications. The other is a nine pin cinch used in applications requiring secondary channel functions. Some of the new circuits that have been added in RS-449 support local and remote loopback testing. and standby channel selection. The transition from RS-232-C to RS-449 will take some time. Therefore. any applications that are interconnected between RS-232-C and RS-449 must adhere to the limitations of RS-232-C. which has a normal speed of 20K b/s at a maximum distance of 50 feet. CHAPTER 2 INSTALLATION SCOPE DMRI1I microation for installing and testing the This chapter provides all the necessarycaninform also included. is s. proces lation instal the processor subsystem. A checklist, which be used to verify 2.1 unpacking. remove all to commercial packing practices. When The DMRI11 is packaged according e 2-1 contains a list of supment against the shipping list (Tablthe packing material and check the equip e for cracks, loose t all parts and carefully inspect modul plied items for each configuration). Inspec er and components, and separations in the etched paths. Report damages or shortages to the shipp 2.2 UNPACKING AND INSPECTION notify the DIGITAL representative. 2.3 INSTALLATION CONSIDERATIONS Installation of the DMR11 microprocessor/line unit subsystem should be done in e Phase I - Preinstallation Considerations e Phase 11 - Microprocessor Installation e Phase 111 - Line Unit Installation four phases: ts. Verify system requirements, system placement, and configuration requiremen ostics. Configure, install, and verify microprocessor module via the appropriate diagn Configure the line unit module for the customer application and install, cable, and verify it via appropriate diagnostics. e Phase IV - DMRI11 System Testing Verify the DMR11 microprocessor subsystem operation with the functional diagnostics and system exercise programs. NS 2.4 PREINSTALLATION CONSIDERATIOprior to ordering a DMRI11 communications interface d be considered The following (Table 2-1) shoul 11 and that it can be installed correctly. These steps t the DMR accep can em syst the to insure that installation time. should also be verified at Table 2-1 Option DMRI11 Option Packing List Parts List Description DMRI11-AD DMRI11 basic subsystem unit containing: M8203 Line unit module - Mg8207-RA Microprocessor module with DMRI11 microcode ROMS BCO08S-1 Module interconnect cable H3254 V.35 and integral module test connector H3255 RS-232-C/RS-422-A /RS-423-A module test connector EK-DMRI11-UG-001 DMRII User's Guide MP-00911 Customer print set Z])-306-RB Diagnostic set DMRI1I-AA RS-232-C/RS-423-A interface configuration con- taining: DMRI11-AD Basic DMRI11 unit BCS5C-10 H3251 H325 EIA RS-232-C/RS-423-A cable Cable turnaround test connector Cable turnaround test connector DMRI11-AB CCITT V.35 interface configuration containing: DMRI11-AD Basic DMRI11 unit: BC05Z-25 H3250 CCITT V.35 cable Cable turnaround test connector DMRI1I-AC Integral Modem interface configuration containing: DMRI11-AD BC55A-10 H3257 Basic DMRI1 unit Integral Modem cable BCS55A terminators H3258 DMRI1I1-AE 2.4.1 “a 4 9 RS-422-A interface configuration containing: DMRI11-AD Basic DMR11 unit BC55B-10 H3251 RS-422-A cable Cable turnaround test connector System and Device Placement 12 &4.1.1 . 4 DySsie o d o e - SLCLHID devices, there is a probability of advers A - Lildl bus 2-2 physical placement of the DMRI11 to the processor, the higher the DMA device priority. A single DMR11 at 1M b/s and in full-duplex mode is capable of transferring 125,000 bytes/second/channel X 2 channels (Transmit and Receive). Because the DMR11 performs 16-bit word transfers via nonprocessor request (NPR) transactions to memory, approximately 125,000 NPRs per second at the rate of 8 microseconds/NPR are generated. Customer applications using speeds greater than 250K bits per second (b/s) require UNIBUS placement before all UNIBUS repeaters and before all devices that have a lower NPR rate on the UNIBUS. 2.4.1.2 Device Placement - The DMR11 requires two hex-height, small peripheral controller (SPC) backplane slots (preferably two adjacent slots). Any SPC backplane [DD] 1-B(REV E) or later] can accept the DMR11. The DD11-D can accommodate a maximum configuration of three DMRI11s. CAUTION Each DMRI11 requires approximately 8 amperes from the +5 volt source. Check to ensure that the supply is capable of providing a total of 24 amperes if a maximum configuration is installed. System Requirements 2.4.2 1. UNIBUS Loading M8207-RA microprocessor M8203 line unit 2. 1 UNIBUS dc load 5 UNIBUS ac loads No UNIBUS loads Power Requirements Check the power supply before and after installation to ensure against overloading. The8 microprocessor/line unit total current requirement for the +5 volt supply is approximately amperes. Additionally, the unit requires +15 volts for the silos. level conversion logic, and Integral Modem. Power requirements for the microprocessor/line units are listed in Table 22. Table 2-2 DMRI11 Voltage Chart Maximum Voltage Minimum Voltage Back Plane Pin M8207-RA | + 5Volts @ 5.0A + 5.25 + 5.0 ClA2 + 5Volts @ 3.0A + 5.25 + 5.0 ClA2 +15Volts @ .1A +15.75 +14.25 Ci1Ul @ .2A -15.75 -14.25 C1B2 Module M8203 Voltage Rating (Approximate Values) -15Volts Interrupt Priority The interrupt priority is selected by priority plug E77 on the M8207-RA microprocessor module. This plug is preset to select priority five (BRS5). Refer to Figure 2-1 for the priority plug location. Device Address Assignment The DMRI1 resides in the floating address space of the Input/Output (1/0) page of memory. The ranking assignment of the DMR11 is equal to the DMC11 ranking number seven. The selection of the device address is accomplished by Switch Pack E127 on the M8207-RA microprocessor module. Refer to Figure 2-1 for the switch pack placement. Since the DMR11 will reside at the same ranking as the DMCI 1, the operating system can determine what type of device resides at that address location by reading the second control and status register (CSR) of the device and examining the high byte. If the bootstrapping feature of the DMR11 or DMCI1 is to be used, only the devices that reside at unit zero and/or unit one address location can implement this feature, unless bootstrap is designed to accept more units. N Refer to Appendix A if more information is needed on the floating address allocation, Device Vector Address Assignment The DMRI11 resides in the floating vector space ofthe reserved vector area of memory. The ranking assignment of the DMR11 is equal to the DMCI1 ranking number 27. The selection of the device vector address is accomplished by Switch Pack E28 on the M8207-RA microprocessor module. Refer to Figure 2-1 for the location of the switch pack. Appendix A contains more information on floating vector allocation. 2.5 MICROPROCESSOR INSTALLATION Backplane Considerations 2.5.1 Perform the following on the SPC slot that will contain the DMRI11, M8207-RA microprocessor module (selected at preinstallation). 1. Verify that the backplane voltages are within the specified tolerances listed in Table 2-2. 2. Turn system power off and remove the NPR Grant (NPG) wire that runs between CA|l and CBI1 on that backplane slot for the M8207-RA module. NOTE Be sure to replace this jumper if the microprocessor is removed from the system. Perform resistance checks on the backplane voitage sources to ground to ensure that no short circuit conditions exist. Refer to Table 2-2 for backplane pin assignments. 2.5.2 M8207-RA Considerations Perform the following on the DMR11 M8207-RA microprocessor module. 1. Ensure that the module version number is an M8207-RA., which indicates DMR 1 microcode. 2-4 SWITCH PACK E127 DEVICE ADDRESS SELECTION - e A12 1 2 4 : \ 5 6 7 8 9 10 SWITCH OFF = LOGICAL 1 (REFER TO TABLE 2-4) DJ13 /—\ 1 rJ'l SWITCH PACK E85 20 PRIORITY SWITCH PACK E28 PLUG mmo -V8 V3-mmmmmmmm o 2 3 4 5 6 7 8 |=] )F SPARES BSEL 1 0 1 LOCKOUT VECTOR ADDRESS SELECTION SWITCH CN = LOGICAL 1 (REFER TO TABLE 2-5) RUN INHIBIT — CSR DISABLE— MK-2120 Figure 2-1 M8207-RA Microprocessor Switch/Jumper Locations 2-3 Verify that M8207-RA jumpers W1 and W2 are installed correctly (refer to Jumper Table 23). Asswas determined from the floating address allocation. Refer to Table 2-4 for the correlation between switch number and address bit. A switch OFF (open) responds to logical one on the UNIBUS. Refer to Appendix A for additional information on floating address allocation. Configure Switch Pack E28 to implement the correct vector address for the DMRI1 as determined from the floating vector allocation. Refer to Table 2-5 for the correlation between switch number and vector bit. A switch ON (closed) responds to a logical one on the UNIBUS. Refer to Appendix A for additional information on floating vector allocation. Verify that the switch selectable features of the M8207-RA are configured as follows (Table 2-6 provides a summary of switch selectable features): e Run Inhibit - Switch Pack E28, switch 7: always ON. * CSR Inhibit - Switch Pack E28, switch 8: always OFF. e Byte Select/Lockout (BST) - Switch Pack E85, switch I, normally ON (allows all functions in Byte Select 1 to be used). If the switch is OFF. the Run bit is always asserted and will not allow diagnostic testing. NOTE Switch Pack E8S, switches 2, 3, and 4 are not used. Verify that the priority plug is a BRS5 and is installed correctly in location E77. 6. Table 2-3 M8207-RA DMR11 Jumper Chart Jumper Normal Number Configuration Function Wi Always In Microprocessor Clock Enable - When removed it disables the microprocessor clock. Removed only for automatic module testing at the factory. W2 Always In Bus ac Low Enable - When removed it disables a program asserted ac low signal passed onto the UNIBUS. 2.5.3 MB8207-RA Insertion Carefully insert the M8207-RA microprocessor module into the selected SPC slot and perform the following tasks: l. Perform resistance checks on the backplane voltage sources to ground to ensure that no short circuit conditions exist on the module. Refer to Table 2-2 for backplane pin assign- - ~ all 3 8 ST U MNNT L UL DYdLICH] pUWLL UiN L [ ] ments. ances listed in Table 2-2. 2-6 3. Load and execute the M8207 static diagnostics, parts one and two (no test connectors are required). A. PDP-11 System CZDMP* M8207 Static Test 1 CZDMQ* M8207 Static Test 2 B. VAX-11/780 Systems EVDXA COMM Microprocessor Repair Level Diagnostics REV *.* Chapter 4 provides additional information on these diagnostics. Upon obtaining a minimum of five error free end passes, proceed to the M8203 line unit installation section. 2.6 LINE UNIT INSTALLATION The M8203 line unit is a universal module with various types ofinterface capabilities. The M8203 line unit does not present any ac or dc loads to the UNIBUS and only draws power from the backplane slot in which it resides. All data and control signals flow into and out of the line unit via a berg port to the microprocessor. Because of the various M8203 applications, the configurations for each may be differ- ent and are selected via switches, jumpers, and different cables. To provide a better understanding of these variations, a number of tables describing each switch pack, jumper, and cable function (as listed below) has been created for reference. Table 2-7 lists the normal M8203 line unit configurations for the 1 options without the bootstrap feature selected. Also, refer to the following: different types of DMR Table 2-8 Jumper Functions - These jumpers are used to select various interface standard parameters and modem interface signals, depending on application and modem type. Additional jumpers are available on the BC55C (panel) cable for additional interface signal selection. e Table 2-9 Switch Pack E39 Functions - This switch pack allows proper selection of interface e Table2-10 Switch Pack E121 Functions — This switch pack is provided for the selection of the bootstrap offset address for the remote load detect feature (if used) and for various microcode driver and receiver control logic and different line speeds for various applications. switch features. e Table 2-11 Switch Pack E134 Functions - This switch pack is provided for the selection of the bootstrap password for the remote load detect feature (if used) and for various microcode switch features. e Table 2-12 Cable Description - This table lists the functions and uses of each cable used with o Figure 2-2 shows the jumper and switch pack placements on the M8203 line unit. e Figure 2-3 shows the microprocessor and line unit installation. * Figure 2-4 shows the outline drawings of DMRI1 cables. the DMRI11. 2-7 Table 2-4 Switches Function 1-10 Device Address Selection: Switch Pack E127 Selections LSB * | MSB 1s[1a]13]12]11J10] o8 [7[6]s|a]3]2 lojo]o SWITCH PACK E127 11]1 || | I i 1 i ] | i | | I ] | ] ' ] | ’ [ 1 [] SWITCH SWITCH Is10fso[s8|s7|se[ss|sa|s3|s2|s1] OFF OFF OFF | OFF OFF OFF OFF OFF | OFF i OFF OFF | OFF | OFF DEVICE DoRess 760010 760020 760030 760040 760050 760060 760070 760100 OFF 760200 OFF | OFF 760300 OFF 760400 OFF OFF 760500 OFF | OFF 760600 OFF | OFF | OFF 760700 OFF 761000 OFF 762000 OFF| OFF 76.3-600 OFF 764000 NOTE: SWITCH OFF RESPONDS TO LOGICAL ONE ON THE UNIBUS. SWITCH PACK E127 DEVICE ADDRESS SELECTION /- S g g A12 01 N o F F 2 3 4 5 6 7 8 9 10 Switch Pack E127 Table 2-5 Switches Switch Pack E28 Selections Function NOTE Switch ON equals a logical one (1) on the UNIBUS. 1-6 Vector Address Selection: MSB | LSB isf1a]13]12[11]10] o8 7|e]s|a|a3]2[1]o0 ojojlofofo|o|o] switchpacke2s 14| o t | | | ] ] ! | | t | | s | [ | { 1 ] ] ] SWITCH NUMBER | S6|S5|S4]S3[S2|S1| VECTOR ApDRESS 300 ON|ON ON ON|ON 310 ON|ON ON 320 ON|ON ON|ON 330 oN|oN]oN 340 oN|oN|oN ON 350 oN|oNJON|ON 360 oN|oN]ON|ON|ON 370 ON 400 ON ON 500 ON | ON 600 ON|ON|ON 700 NOTE: SWITCH ON PRODUCES LOGICAL ONE ON THE UNIBUS. mmno =20 SWITCH PACK E28 1 2 3 4 5 6 7 i L 1 M 8 VECTOR ADDRESS SELECTION RUN INHIBIT* CSR DISABLE*— *Refer to Table 2-6 for switch functions. Table 2-6 Switch Location and Number Normal Switch Selectable Features Configuration Function ON Run Inhibit - Under normal conditions, switch ON. The initialization of the microprocessor directly sets the run flip-flop E28 Switch 7 which allows the microcode to be executed immediately. Because of an internal malfunction or execution of erroneous microcode during power up, it is possible for the microprocessor to hang the UNIBUS. Placing the Run Inhibit switch in the OFF position clears the Run flip-flop and allows the diagnostics to be loaded to determine the fault. Once diagnostics have been executed and the problem corrected, return the Run switch to the ON position. E28 Switch 8 OFF CSR Inhibit - When the switch is ON it keeps the device from responding to its address. Used in special applications on other options. ON BSEL 1 Lockout (BST) - When the switch is OFF, it inhibits the use of all maintenance test features and keeps the Run bit asserted at all times. This allows the DMR11 microcode to run with the ability to detect a boot request message at all times. This is used at unattended computer sites. This switch must be ON to execute all diagnostics. E8S Switch 1 NOTE Although BSEL 1 Maintenance functions are inhibited, Master Clear (bit 6) is still functional. E8S OFF Not Used Switches 2,3,and 4 2-10 M8203 Configuration Table 2-7 Normal M8203 Configuration (Bootstrap Not Selected) Option Type: | DMRII1-AA DMRI11-AB | DMRII-AE | DMRI1-AC EIA RS-232-C | CCITT V.35| EIA Integral or RS-423-A Jumper Configuration®* WI1-W6, Wil | OUT Wi4-W17 Modem DMRI11-AA Null Modem Modem Clock 56K b/s 1 MEG b/s 9.6K b/s ouT ouUT ouT ouT ouT (refer to Table 2-8) "o W0 IN IN IN IN N N Switch Pack E39 Si-4 S5 | S6 OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ON OFF OFF OFF OFF OFF S7 S8 S9 S10 OFF ON ON OFF OFF ON ON OFF ON ON ON OFF OFF OFF OFF ON OFF ON ON ON OFF OFF ON OFF ON ON WIi2, W13 (refer to Table 2-9) Switch Pack E121 1 | S1-8 11-C RS-422-A DMRI11-AC Integral (refer to Table 2-10) [Fqg S10 Switch Pack E134%1 | S1-8 ~ (refer to Table 2-11) | S9 S10 ON OFF | DMRII ON to OFF ‘DMCII-AL to OFF OFF OFF OFF OFF OFF OFF ON = Disables Microdiagnostics At Master Clear Time OFF = Enables Microdiagnostics At Master Clear Time NOTE: Switch selections for BSEL 1, Bit 13 = 0 at Master Clear Time. H3254 IN J2 IN J1 H3250 _ to OFF ) DMRII@ 1M b/s | ON | DMRII OFF H3255 t+ Customer application variable ON ON ] DMRI1 OFF Module Tumaround *Modem variable ON DMRI1 OFF Test Connector (refer to Figure 2-5) Test Connector to DMCI11-AR ON OFF BCS55C-10* and (refer to Figure 2-5) ON DMRII OFF Cables Required (refer to Figure 2-4) Cable Turnarouna OFF | BCO5Z-25 BCOSD-25 EIA RS-423-A H3251 BC55A-10 . and Twinax Cables BC55A-10 and Triax Cables | H3255 H3254 H3254 H3254 IN J2 _ IN JI IN J1 IN J2 H3251 Half-duplex Half-duplex H325 BC55D-33 ‘ EIA RS-232-C H325 BC55B-10 and BCS55C-10* and Null Modem EIA RS-232-C Switch ON and | Switch ON and Cables Removed Cables Removed _ EIA RS-423-A H3251 Table 2-8 M8203 Jumper Functions Jumper Normal Configuration Function Wi ouT Clearto Send EIA/V .35 w2 ouT Data Mode EIA/V.35 W3 ouT Receive Data EIA w4 ouT Receive Clock EIA WS OuUT Receive Ready EIA W6 OouT Transmit Clock EIA Wi IN Signal Rate Indicate — When removed, opens signal to interface in RS-422-A and RS-232-C configurations. Remove when an BCO5SC-XX* cable is used as this signal is presented to cinch pin nine, which has a positive test voltage on some modems. W8 IN w9 IN w10 IN Data Mode (Data Set Ready) - When removed, opens signal to interface in RS-422-A/423-A configurations. It has no effect in RS-232-C. Remove when a BCO5CXX* cable is used, as the signal is presented to cinch pin 18, which is dibit clock on some modems. Null Modem Clock - When removed the signal ampli- tude is lowered below the interface standards so as not to create interference in some modems. Terminal Ready - When removed, it opens the signal to modem in RS-422-A/423-A configurations. Remove when a BCO5C-XX* cable is used, as this signal is presented to cinch pin 10, which is negative test voltage on some modems. Wil ouT Receiver Ready (Carrier Detect) - When installed, it allows this signal to be on at all times. This could cause a problem with the microcode since the Universal Synchronous Receiver/Transmitter (USYRT) will be enabled all the time. W12 IN Terminal in Service (Make Busy) - When removed, it opens this signal to the modem. Some modems will not answer the phone and will be put in Analog Loopback when this signal is asserted. When a BCOSC-XX* cable is used, this signal is presented at cinch pin 25. *DMRI11 does not support the use of a BCOSC-XX cable. 2-12 Table 2-8 Jumper W13 M8203 Jumper Functions (Cont) Normal Configuration Function IN Oscillator Enable - To be removed only for factory automatic testing. Jumper should always be installed in the field. W14 and WIS ouUT ouT 56K Bandpass Filter Enable — With these jumpers in- stalled. the bandpass filter is limited to 36K b/s. Used in special applications only. W16 OouUT Switched RTS-CTS Enable - When this jumper is installed, it enables the request to send and clear to send interlock in the M8203 line unit which inhibits asserting RTS. until CTS is dropped. This jumper should never be installed when the DMR11 is operating with a modem that has the constant CTS option installed. W17 OUT Half-Duplex Lockout Enable - When this jumper is installed, it enables the M8203 line unit half-duplex lockout feature when half-duplex mode is selected. The lockout feature disables the transmitter or receiver when the other is active. This jumper applies only to half-duplex applications. It must not be installed for full-duplex applications. NOTE Jumpers W16 and W17 are mutually exclusive. Only one or the other may be installed, not both. Also, these jumpers are provided only on M8203 modules REYV E or higher. For modules up to REV D, refer to ECO-M8203-MK-007 for details of similar jumpers. *DMRI1 does not support the use of a BCOSC-XX cable. Table 2-9 Switches Switch Pack E39 (Z) Selections Function NOTE Switch off equals a logical one (1). 1-4 Not used inDMRI11. 5-7 Interface Selection - Selects proper drivers and receivers for eachinterface type: 2-13 Table 2-9 Switch Pack E39 (Z) Selections (Cont) Function Switches SW5 SWé SW7 Integral Modem* OFF OFF OFF V.35 ON OFF - OFF RS-422-A OFF OFF ON Interface Type RS-232-C, RS-423-A, * Integral modem is selected by BC55A cable when installed in J1 of the M 8203 line unit. Module connector J2 must not have a cable or test connector installed. (Switches 8-10) Line Speed Selection - Selects modem speed for Integral Modem applications, Null Modem applications, and diagnostic testing. Speed 1 MEG 500K 250K 56K Switch Switch Speed 10 9 8 19.2K¥ ON | ON | ON OFF | ON | ON | 9.6K ON | OFF| ON | 438K OFF | OFF| ON | 24K 10 9 8 ON | ON | OFF OFF | ON | OFF ON | OFF| OFF OFF | OFF | OFF + Normal switch setting unless the Integral Modem or Null Modem clock features are used. Table 2-10 Switches Switch Pack E121 (Y) Selections Function NOTE Switch OFF equals a logical one (1). 1-8 Bootstrap Offset Address Selection - These switches are physically connected to IBUS Register 16 with switch 1 being the least significant bit (LSB) and switch 8 the most significant bit (MSB). When the remote load detect (RLD) feature is used, Switch Pack E121 (switches 1-8) must contain the appropriate offset entry address in the bootstrap program. The address formed by the DMR11 is 173XXX, where XXX is the content of E121, switches 1-8. Variations in bootstrap ROMs may require different entry addresses to boot the DMC11/DMRI1. If the remote load detect, feature is not used, the offset must be set to octal 000, switches 1-8 all ON (closed). NOTE When the RLD feature is used, the microdiagnostics in the bootstrap ROM musi be disabied. 2-14 Table 2-10 Switches | Switch Pack E121 (Y) Selections (Cont) Function The following examples are for the M9301-YJ bootstrap module. Depending on the bootstrap module used, reference should be made to the appropriate manual for specific details. 1. M9301-YJ Bootstrap Technical Manual EK-M9301-TM-001 2. M9312 Technical Manual. EK-M9312-TM-002 To boot DMR11 unit 0 without CPU diagnostics, address 356 must be selected: Switch # ] LSB 5 3 L 4 2 1 |ON OFF OFF|OFFJ | ON , MSB 8 | =356 6 |7 OFFJOFF|OFF To boot DMRI11 unit 1 without CPU diagnostics, address 374 must be selected: Switch # LSB ] , 2 T 3 V4 , 5 (16 )7 MSB 8§ |=374 ON | ON |OFFJOFF|OFF| OFFJOFF|OFF To boot DMR11 unit 0 with CPU diagnostics, address 354 must be selected: Switch # MSB LSB J7 18 ]=34 3041516 I T 21 OFF OFFJOFF| | ON OFFJOFF| ON | ON | To boot DMR11 unit 1 with CPU diagnostics, address 372 must be selected: Switch # 9 LSB 1 2 [3F4 MSB |5 16 F7 |8 |=372 ON | OFF|ON [ OFF |OFF OFFJOFF|OFF DMC Line Compatable - Switch is physically connected to IBUS Register 11. bit 2. The DMRI11 microcode uses this bit to determine whether to implement DIGITAL Data Communications Message Protocol (DDCMP) version 4.0 or DMC Line Compatible Mode. e OFF = DMC11 Line Compatible Mode. ¢ ON = DDCMP version 4.0, DMR11 Operating Mode. 10 High Speed Select - Switch is physically connected to IBUS Register 11, bit 1. NOTE The combination of switches 9 and 10 must be appropriately selected to satisfy the configuration requirements as listed below. 2-135 Table 2-10 Switch Pack E121 (Y) Selections (Cont) Switches | Function SW9 | SW10 | Configuration ON ON ON OFF DDCMP version 4.0 (not connected to DMC11) with line speed less than IM b/s. DDCMP version 4.0 (not connected to DMC11) with line speed at |M b/s. OFF | ON Connected to low speed DMCI11-DA (M8200-YA) OFF | OFF Connected to high speed DMCI11-AL (M8200-YB) Table 2-11 Switch Pack E134 (X) Selections Switches | Function NOTE Switch OFF equals a logical one (1). 1-8 Bootstrap Password Selection - These switches are physically connected to IBUS Register 15 with switch 1 being the least significant bit and switch 8 the most significant bit. In the DMRI11, this switch will contain the bootstrap password if the bootstrap feature is being used. Otherwise, it will contain an octal 377 [switches | through 8 OFF (open)]. NOTE A password of 377 will disable the RLD feature. Also, if the DMRI11 is connected to a modem and the user program has not assigned Base In/Control In to the DMRI11, when the DMR11 detects Ring Detect it will drop DTR to disable answering the call. Example of a password of octal 012: Switches LSB ] 2 3 ON | OFF|ON 4 5 JOFF|ON ] 6 § 7 |ONJON MSB 8 |ON Auto-Answer Enable - When the switch is in the ON positon, auto-answer is disabled. The DMRI11, following a power up or master clear, assests DTR allowing the DMRI11 to answer an incoming call for remote load. The call terminates only when the user program issues a Halt Request or the remote end terminates the call. When the switch is in the OFF position, auto-answer is enabled. This allows the DMR11 to monitor ring indicator (RI) and data set ready (DSR) to answer and control incoming calls. Control is established using a 20 second call set up timer. Refer to section 3.7.2.1 for additional information. 2-16 Table 2-11 ~ Switches Switch Pack E134 (X) Selections (Cont) Function NOTE If a DMRI11 is installed on a switched line, this switch must be placed in the OFF position to allow the DMR11 to effectively control incoming calls. 10 bit 5. MicroMicrodiagnostic — Switch is physically connected to IBUS Register 11, met. diagnostic testing is executed when the conditions indicated below are SELO BIT 13 SW10 AT E134 ON M8203 Execution of Microdiagnostics Clear ON No Microdiagnostics Run Clear OFF Run Microdiagnostics Set ON Run Microdiagnostics Set OFF NO Microdiagnostics Run NOTE When installing a DMR11 to run under DMC11 software, it is advisable to place this switch in the ON position. This is necessary where DMC11 software is not designed to wait 6.4 ms for microdiagnostic testing to be completed. * At Master Clear time M8203 Considerations Configure all appropriate switch settings and jumpers on the M8203 line unit module according to the 2.6.1 recommendations in Table 2-7. NOTE If the customer has additional requirements because of modem restrictions or a bootstrapping feature, be sure to configure the line unit to his requirements using the information contained in Tables 2-8 through 2-11. Table 2-12 Interface Cable Description Description RS-232-C o Cable Assembly: BC55C-10 (Refer to Figure 2-4A) o MZ8203 Connector: J2 o Test Connector: H325 A 3 m (10 feet) cable with a 40 pin, berg connector at one end which is installed into J2 of the M8203 so that the ribbed side of the cable faces out. This creates a half twist in the cable and is required for proper pin connections. The other end has a panel bracket that includes three different cinch connectors, J1, J2, and J3. Connector J2 is used for RS-232-C and is connected to the modem with external cable BCO5SD-25. The bracket must be mounted on the rear mounting rail of the cabinet to ensure proper grounding and for easy access to external cable connections. The BCS55C panel contains several jumpers. Depending on the modem option selected, certain jumpers must be installed. Refer to Table 2-13 for detailed jumper configurations. External Cable * BCO5D-25 (Refer to Figure 2-4E) * Test Connector: H325 A 7.5 m (25 feet) external cable that connects J2 of the BC55C panel to an RS-232-C modem. RS-422-A * Cable Assembly: BC55B-10 (Refer to Figure 2-4B) ¢ MS8203 Connector: J2 * Test Connector: H3251 A 3 m (10 feet) cable with a 40 pin, berg connector at one end which is installed into J2 of the M8203 so that the ribbed side of the cable faces out. This creates a half twist in the cable and is required for proper pin connections. This cable is similar to the BC55C in that it has a panel bracket at the other end. There is, however, only one connector on the panél (J2) that is used with cable BC55D-33 for external connection to the modem. The bracket must be mounted on the rear mounting rail of the cabinet to ensure proper grounding and easy access to external cable connections. The BC55B panel has two jumpers (W1 & W2) for shield grounding connections. Normally, W1 is always out (special application only) and W2 normally in. For RS-449 applications, W2 can be removed to place a 100 ohm resistor between circuit ground and frame ground to dissipate ground currents. External Cable e BC55D-33 (Refer to Figure 2-4F) A 10 m (33 feet) external cable that connects J2 of the BC55B panel to an RS-422-A modem. 2-18 Table 2-12 Cable Description (Cont) Description Interface RS-423-A e Cable Assembly: BC55C-10 (Refer to Figure 2-4A) o M8203 Connector: J2 ¢ Test Connector: H3251 Same cable as used for RS-232-C except that panel connector J1 is used with external cable BC55D-33 for connection to the modem. The bracket must be mounted on the rear mounting rail of the cabinet to ensure proper grounding and easy access to external cable connections. The BC55C panel contains several jumpers. Depending on the modem option selected, certain jumpers must be installed. Refer to Table 2-13 for detailed jumper configurations. External Cable BC55D-33 (Refer to Figure 2-4F) e A 10 m (33 feet) external cable that connects J1 of the BC55C panel to an RS-423-A modem. Test Connector: H3251 V.35 * Cable Assembly: BCO5Z-25 (Refer to Figure 2-4G A 7.5 m (25 feet) modem cable with a 40 pin, berg connector at one end that connects to J1 of the M8203. A 37 pin, Data- e M8203 Connector: J1 er end and connects to the modem. e Test Connector: H3250 Phone Digital Service (DDS) connector is installed at the oth- Integral Modem ¢ Cable Assembly: BC55A-10 (Refer to Figure 2-4C) ¢ J1 M8203 Connector: e Test Connector: NONE (Place panel switch to HDX Position for turnaround) A 3 m (10 feet) cable with a 40 pin, berg connector at one end that plugs into J1 of the M8203 with the cable strain relief tab facing out. A BC35A connector panel is installed at the other end. This panel contains four connectors, two female and two male. The panel also includes a toggle switch to select either full-duplex or half-duplex. The panel is mounted on the rear mounting rail of the cabinet to ensure easy access to external connections and for proper grounding. Appropriate terminator connectors H3257 or H3258 must be used. See Figures 2-7 and 2-8. NOTE Ensure that all cables mounted in the M8207 and M8203 are properly installed and seated in the berg connectors. 2-19 Table 2-12 Interface Cable Description (Cont) Description External Cables e BCS55N-98 (Refer to Figure 2-4D) o Test Connector: NONE o BC55M-98 (Refer to Figure 2-4D) e Test Connector: NONE A 29.4 m (98 feet) external twinax cable used to interconnect a DMCI11 to a DMRI11 or a DMRI11 to a DMRI11 for a selected data rate of 56K b/s. A 29.4 m (98 feet) external triaxial cable used for the same purpose as the BC55N, but for data rates above 56K b/s. 2-20 AUTO ANSWER BOOTSTRAP PASSWORD N 2 3 7 ¢ 4 4 BiT 13 | E134 ON | EXECUTION OF MICRODIAGNOSTICS M8203 T 1 o1 | SWI0 AT sELo \ MICRODIAGNOSTIC Jj (1BUS REGISTER 15) T T 8 910 Y SWITCH ON =0 ~ SWITCH OFF = 1 ,’ sB M5B SWITCH PACK E134 CLEAR ON NO MICRODIAGNOSTICS 1S RUN CLEAR OFF RUN MICRODIAGNOSTICS SET ON RUN MICRODIAGNOSTICS SET OFF NO MICRODIAGNOSTICS 1S RUN DMC LINE COMPATIBILITY BOOTSTRAP OFFSET (IBUS REGISTER 16) [ sSW 9 ] SW10 l - HIGH SPEED SELECT ON 1§ O 1 2 3 4 5 6 7 8B ¢ CONFIGURATION DDCMP VERSION 4.0 (NOT CONNECTED 10 ON TO DMC11) WITH LINE SPEED LESS THAN 1M 8/S. DOCMP VERSION 4.0 (NOT CONNECTED ON 158 TO DMC11) WITH LINE SPEED AT 1M on CONNECTED TO LOW SPEED DMC11-DA B/S. MSB SWITCH PACK E121 w7 W3 w4 N 4 w6 OFF p) OFF (I (M8200 YA) OFF CONNECTED TO HIGH SPEED DMC11-AL (M8200 YB) / I f\ w9 g wiz Wl o w8 W17 | . e 'l ol il SWITCH W10 wis] wi4]) { L) wi3 'l I ul [ 20 SWITCH PACK £39 o 1 OFF 1 4 2 3 4 5 6 7 8 I ] = [| RESERVED 9 10 =| ] -\ SPEED 8 9 10 MEG ON ON ON 500K OFF ON ON 250K ON OFF ON 56K OFF OFF ON *19.2K ON ON OFF 9.6K OFF ON OFF 4.8K ON OFF OFF 1 2.4K J OFF % NORMAL SWITCH SETTING UNLESS THE INTEGRAL MODEM OR NULL MODEM CLOCK FEATURES ARE USED. SW5 | SW6 ; sw7 RS-232-C OR RS-423-A OFF | OFF OR INTEGRAL* [SELECTS DATA RATE V.35 RS-422 (SEE TABLE 2) SELECTS RS-422 INTERFACE L LRESER\/ED SELECTS V-35 INTERFACE / *% OFF | OFF | OFF ON OFF | OFF OFF | OFF ON INTEGRAL MODEM 1S SELECTED BY BCS5A CABLE WHEN INSTALLED IN J1 OF THE M8203 LINE UNIT. MODULE CONNECTOR J2 MUST NOT HAVE ANY CABLE OR TEST CONNECTOR INSTALLED. MK 2119 Figure 2-2 ME&203 Switch/Jumper Locations CONNECT CABLE BCO5Z FOR V.35 INTERFACE OR BC55A FOR INTEGRAL MODEM. H3254 @ TEST CONNECTOR | = H3255 [JTM—_ ~ = T\ T f -y | {) B M8203 j M8207 / CONNECT CABLE BC55C-10 FOR RS-232-C OR RS-423-A INTERFACE, OR BC55B-10 FOR RS-422-A INTERFACE MICROPROCESSOR G~ LINE UNIT TEST CONNECTOR |$, . i IE | cJ L E i MAINTENANCE LED'S n ] TRANSMIT DATA (D13) S - J3 RECEIVER DATA (D12) REQUEST TO SEND (D14) CARRIER (D11) : 1 B——— HEARTBEAT (D15) | SIGNAL QUALITY (D10) SEE TABLE BELOW FOR DESCRIPTION / BCO8S __— -d hu |' - hi -1 | g i’::: D E_ "'I: C ] —_—— ——— DESIGNATION | DESCRIPTION D13 ON INDICATES DMR11 IS TRANSMITTING A STEADY STREAM OF 1's. D12 ON INDICATES DMR11 IS RECEIVING A STEADY STREAM OF 1's. D14 ON INDICATES THE USYRT IS READY TO TRANSMIT WHEN CTS IS DETECTED. D11 ON INDICATES CARRIER IS PRESENT AT THE RECEIVER. D15 THE HEARTBEAT SEQUENCE IS GRAPHICALLY SHOWN IN THE WAVEFORM BELOW. D10 ON INDICATES CARRIER PRESENCE AND OFF INDICATES CARRIER ABSENCE. EXECUTION OF BASE IN/ MICRODIAGNOSTICS CONTROL IN IF ENABLED ON OFF - ~ =~ 200 ms y—" 1 BLINK RATE 5 TIMES/SECOND {(APPROXIMATE) MASTER CLEAR RUN BIT ASSERTED REMAINS ON IF HALT OR HEARTBEAT WAVEFORM FATAL ERROR MK-1570 Figure 2-3 Microprocessor/Line Unit Installation 2-22 2.6.2 MB8203 Insertion With system power OFF, carefully insert the M8203 line unit module into the proper backplane slot (usually adjacent to the microprocessor) and perform the following: Interconnect the line unit and the microprocessor using the BC08S-1 cable. One end of the cable is connected to J1 of the M8207-RA microprocessor module and the other end to J3 of the M8203 line unit module. Carefully fold the cable back to the right, tightly against the component side of either the microprocessor or line unit module, so as to fit it into the 1. mounting box. Refer to Figure 2-3 for connector layouts. Insert the appropriate module test connector into the correct line unit connector as specified 2. in Table 2-7. Be sure to insert with “SIDE 1" (etched on the test connector) visible from the component side of the line unit. See Figure 2-3 for test connector orientation. Schematics and outline drawings of each test connector used with the DMRI11 are provided in Figure 2-5. Turn System power ON and perform voltage checks on the line unit backplane slot. Ensure 3. that the voltages are within the specified tolerances as listed in Table 2-2. VIEW A NOT USED RS-423-A RS-232-C IN DMR11 W8 W e/ J2 ) o > o] J3 © 3 W10 ffi own W12 CoOW2 W3 J01 o W9 I W13 | — W14 — W15 o W16 W4 2 - < N W1 = | — W17 o W5 = W6 W18 — =wr LS) W19 —=weo [— o = w21 BC55C-10(RS-232-C/RS-423-A) INTERFACE PANEL CABLE MK-15871 Figure 2-4 DMRI11 Cable Drawings (Sheet 1 of 4) 2-23 VIEW B I © ng OU@ E@ '@ © - J1 = _ = B S0l e |e U =1 BC55B-10 {RS-422-A INTERFACE) PANEL CABLE MK-2136 VIEW FEMALE CONNECTORS C HDX RECEIVE@ TRANSMIT iIN FDX N O ) TN\7& MALE CONNECTORS BC55A-10 (INTEG RAL MODEM) PANEL CABLE CONNECTOR PANEL (FRONT VIEW) MK-2137 X — m—) — — H3257 TERMINATOR H3258 TERMINATOR MK-2244 Figure 2-4 DMRI11 Cable Drawings (Sheet 2 of 4) 2-24 __________ ad [, WUl VIEW D — s 000 BC55N TWINAX CABLE BC55M TRIAX CABLE MK-2168 VIEW E ® ® @ 25 PIN BCO5D-25 (RS-232-C INTERFACE) MODEM CABLE CINCH MK-2139 VIEW F 37 PIN 37 PIN BC55D-33 (RS-422-A/RS423-A INTERFACE) MODEM CABLE CINCH Figure 2-4 DMRI11 Cable Drawings (Sheet 3 of 4) 2-25 CINCH MK.2187 VIEW G 5 s 5 o i~ I W JNoN N J | [ l O 00 'Y 20 _©° e 03¢ T 3 T o O oo o @ e (e3(~) S I} T M 0 o m 1 % 8 n BCO52-25 (V.35 INTERFACE) MODEM CABLE (i - MK-2138 Figure 2-4 4. DMRI11 Cable Drawings (Sheet 4 of 4) Load and execute the M8203 static diagnostics, parts one and two, with external maintenance mode selected. A. PDP-11 System CZDMR* M8203 Static Diagnostic | CZDMS* M8203 Static Diagnostic 2 B. VAX-11/780 Systems EVDMA M8203 Repair Level Diagnostics REV * * Chapter 4 provides detailed information on these diagnostic routines. Upon obtaining a minimum of five error free end passes, with the module turnaround test connector installed, proceed with step 5. 5. Remove the module turnaround test connector and connect the appropriate cable (see Table 2- 7) to the proper berg connector for the DMR11 option selected. Refer to Table 2-12 for detailed information on cable requirements and to Figures 2-6 through 2-8 for system cabling configurations. NOTE When installing panel cables BC55A, BCSSB, or BC55C, it is important that the panel be properly mounted to the rear mounting rail of the cabinet to ensure adequate grounding. When connecting the BC55C connector panel, verify that the appropriate modem jumpers on the panel are properly configured for the option selected. Table 2-13 lists each of these options and required jumper configurations. Integral Modem options require that a 75 ohm terminator be connected to each receive line (BC55A panel) at each end of a full-duplex and a half-duplex network. These terminators are available in both male (H3257) and female (H3258) types to accommodate different Integral Modem cabling. Selection of the appropriate terminator type is dependent upon which type of unused panel connector is available on the receive line at the BC55A-10 panel. Refer to Figure 2-7 for DMRI1 to DMCII cabling and to Figure 2-8 for DMRII to DMRI11 cabling. 2-26 Modem Option Jumper Functions Table 2-13 /& & /S /e o ) $/8/)e )&/ S /L) Rijumper Pin 1 Wi /S /&' /S /R /ST /S ¥ /S /5 /) /0 /S /L /8 /8 /O /O SEE /8 O |IN|IN|IN|IN|IN /85 [ Sy ¥ /& /& [/ < Y IN AA Sy e E /S /S /R C 101 W7 2 BA 3 BB 3 WI9[IN | IN |IN |[IN | IN |IN |IN |IN | IN |[SD |103 | RD | 104 CA |RS |105 5 CB |CS |106 6 CC 7 AB [SG [102 8 CF_|RR | 109 SF | 126 | DM | 107 9 10 11 | W4 12 INt W3 |IN IN |IN |IN |IN |IN | IN SCF | SRR | 122 137 w2 |IN IN IN |IN [ IN | IN SCB | SCS | 121 14 W6 |IN IN | IN |IN |IN | IN | IN SBA | SSD | 110 | IN |IN | IN [IN |IN [ IN | IN DB | IN | IN |IN [IN IN | IN SBB | SRD | 119 (IN 'IN "IN |IN |IN 'IN | IN DD = 15 16 W20/IN | W5 | IN WIS IN 17 18 | 19 . W4 | IN |IN W17 | IN IN IN [IN |IN IN | IN |114 |RT | 115 LL 20 21 |ST | 141 SCA | SRS | 120 CD | TR | 108 | WI16 | IN IN CG W13 | 24 | W15 25 | WIl W21 | IN* w12 | WI0O 110 RL | 140 22 23 | SQ IN | IN |IN | IN | IN = | IN CE |IC | 125 CH | SR | 111 Cl |SF |112 SS | 116 IN /IN | IN | IN IN IN IN W9 W8 | IN DA |TT |113 SB | 117 TM |142 Make Busy *RS-232-C defines both signals for this pin + CCITT modem A only 2-27 Refer to Insert the appropriate cable turnaround test connector in the end of the cable.diagnost ics static M8203 the Table 2-7 for the specific test connector. Load and execute and module the verify to specified in step 4 using the external maintenance mode selected cable. Upon obtaining a minimum of five error free passes, proceed to the DMR11 System Test Procedures, Section 2.7. Figure 2-5 illustrates the various test connectors used in the DMRI11. J1 PP NULL CLK + ——P—-———':H RECCLK + —-‘——C% TXCLK + < NULLCLK - > RECCLK - < TXCLK - < EE SS — , TT @ > o R DATA - < KtK TX DATA + —> -o— ® R DATA + < V RTS > ?' CTS < REC RDY < —— TER RDY gl Z TX INT > REC INT < NN TX INT > TX DATA DATA MODE REC INT > ¢ J + ] + J SIDE 1 — BB —1 o < J1 H3254 FF o— MM —-‘—-G l VIEWA H3254 MODULE TEST CONNECTOR (J1 ON M8203) MK-2143 Figure 2-5 DMRI11 Tumaround Test Connectors (Sheet 1 of 5) M TESTING 2.7 DMRI11 SYSTE and line unit, The final step in the installation ofaDMR11 subsystem is to exercise the microprocessor testing that first the is This link. ations communic the over as one complete unit, on the UNIBUS and 11 microcode. will use the DMR 2-28 AUX CLK - ——] TX CLK DIFF = —e— RX CLK DIFF - . - TX DATA DIFF + . - RX DATA DIFF + —_— TX DATA DIFF — SN RX DATA DIFF — - RTS CTS CDET VIEW B SGu—— <l - D S—— e S——— DTR DSR - - il -y L RX CLK DIFF + Omd:r:lmlc OQ—|+m+mp-uq><Lm l20< -<¢CD AUX CLK + TX CLK DIFF + H3250 MK-2123 Figure 2-5 DMRI1 Turnaround Test Connectors (Sheet 2 of 5) Functional Diagnostic Testing 2.7.1 Ensure that the specific cable turnaround test connector for the selected DMR11 option is still installed at the end of the cable. Load and execute the DMR11 functional diagnostics with the External Mode selected. See Chapter 4 for details on this diagnostic test. A. PDP-11 Systems CZDMI* DMRI11 Functional Diagnostics B. VAX-11/780 Systems EVDCA REV ** . VAX Synchronous Link Level 2 Diagnostics Upon obtaining a minimum of five error free end passes, proceed to section 2.7.2. 2.7.2 DECXI11 System Exerciser 11 system exerciser for the DMR11 can be run in two different operating modes, Internal The DECX and External. The External Mode selects faster UNIBUS activity. This mode also requires that the specific modem test connector is installed at the end of the cable and is the preferred mode of operation. Refer to Chapter 4 for additional details. 2-29 J2 (A ¢ SEND COMMON 8 REC COMMON TER IN SER > INCOMING CALL < % TER RDY + —» —— DATA MODE + - g SEND DATA + —» ¢ X || z || REC DATA + — K? SEND DATA - > st REC DATA - - t ** NULL CLK + —» g SEND TIMING + - g REC TIMING + — EtE ** NULL CLK — —» - SEND TIMING — - % REC TIMING — —a— v RTS + CTS + 1 J m + < .o > MM < SEL SIGNAL RATE > SIGNAL RATE IND < LtL * SEC SEND DA TA > ® > % SEC REC DATA -~ J v > -0— D ¥ Sec cTS - ¢ LOCAL LOOP + SIDE 1 + > EF SEL STAND BY > o STAND BY IND < K | o+ o+ * TH2 TH1 3055 l J VIEW C TEST MODE —4——Coc———-| l —v-——'g CTS — < HF REC RDY - - T - > - TER RDY - s, & RR * SECRT C S DATA MODE EI + -_-.___% SIGNAL QUALITY RTS — J2 H3255 MODULE TEST CONNECTOR (J2 ON M8203) MK-2122 J —e—1—0— % NOT REQUIRED FOR DMR11 ** RS-449 SIGNAL = TERMINAL TIMING Figure 2-5 DMRI11 Turnaround Test Connectors (Sheet 3 of 5) 2-30 J1 SHIELD GROUND SIGNAL RATE INDICATION ) g 1 — " —»——5» _-‘——_T 47 - SEND DATA + SEND TIMING + REC DATA + > : - ;F - e LOCAL LOOP > * RECEIVER READY + - t REQ TO SEND + REC TIMING + + CLEAR TO SEND DATA MODE + TERMINAL READY + REMOTE LOOP INCOMING CALL SIGNAL RATE SEL - —1 SIGNAL GROUND RECEIVE COMMON % > fi . ; -—»—-—zeg REC DATA - —— . REQ TO SEND- - —— > - REC TIMING - -- CLEAR TO SEND - - TERMINAL IN SERVICE > DATA MODE - - RECEIVER READY - TERMINAL READY- —1 SELECT STANDBY > SIGNAL QUALITY - NEW SIGNAL — TERMINAL TIMING - > STANDBY INDICATION - SEND COMMON 20 - . SEND DATA- SEND TIMING - §§ ® 1% - 1 r\ | 1+2 _l - TERMINAL TIMING + TEST MODE o : 0 / 37 O 26 . zz % . -] H3251 J VIEW D : A v H3251 CABLE TEST CONNNECTOR (BC558B, BC55C AND BC55D) Figure 2-5 DMRI11 Turnaround Test Connectors (Sheet 4 of 5) 2-31 MK-2121 H325 SCE SCT SCR ; —e——24 12 ——at——L SEC XMIT——e] SEC RCV—e XMIT DATA CUT TO TEST 12 NEW =l o@...........}]o 3 RCV DATA—e ® RS——=2t CS SYNC SIDE 10—i—-o e 000600 00660 ‘ 5 = 0 0 o CO—e NEW SYNC—e—ouo>94 H325 DATA SET RDY —a—-0 CUT TO TEST* NEW SYNC VIEW E oTR—e—22| Rl ———22 H325 CABLE TEST CONNECTOR (BC55C AND BCO5D) Figure 2-5 MK-2124 DMRI11 Turnaround Test Connectors (Sheet 5 of 5) 2.7.3 Final Cable Connections The final step in the installation process is to return the DMR1 to its normal cable connections, either to the appropriate modem or to the distribution panel. The DMR11 system cabling diagrams in Fig- ures 2-6, 2-7, and 2-8, have been included to help show overall cabling for the various DMR11-XX options. References to specified locations of the various test connector s during diagnostic testing are also included. After the cables are connected to the appropriate modem or distributio n panel, it is suggested that the Link Test Program ITEP be exercised. 2.7.4 DMRI1 Link Testing The DMRI11 can be exercised over a communications link by the Interproc essor Test Program (ITEP). It is suggested that ITEP be configured to run first on a cable test connector and then on a modem with the modem Analog Loopback test feature selected, if the modem includes this feature. Next, the overall communications link should be exercised with the remote computer system that contains a DMRII1 or a DMCI1. 2-32 RS-232-C INTERFACE J2 BCO8S-1 [ S . ] J3 J1 BC55C-10 g O MODEM BCO5D-25 BC55C (= JZN M8203 LINE UNIT M8207 MICROPROCESSOR RS-232-C o] PANEL H325 - J2 TEST CONNECTOR CABLE TEST CONNECTOR H325 H3255 L(___rfl__r"L__r"l__r'L——f'\—-—-r £e-C MK-2131 RS-422-A |NT52RFACE RS-422-A BCO8S-1 f A ) J3 J1 BC558B-10 (=] JN M8203 LINE UNIT M8207 MICROPROCESSOR ff (I S e, I, B O, , T “BCS5B PANEL TM~ H3255 MODEM BC55D-33 H3251 H3251 Y. T, B R, , U MK-2132 Figure 2-6 DMRI1 Remote System Cabling Diagram (Sheet 1 of 2) BCO8S-1 j &= " t=h J BC55C-10 S J2%w fl-fl | R5-423-A MODEM BC55D-33 BC55C =he= J3 M8207 MICROPROCESSOR > PANEL U1 M8203 LINE UNIT H3251 H32561 J2 TEST CONNECTOR T, ba ) T, T, e, { (I | | i T, T, T, e, ,J e, H3255 ve-T MK-2133 BCO8S-1 f V.35 INTERFACE j) ( :L—;bt:a J1 J 20 M8203 LINE UNIT M8207 MICROPROCESSOR BC052-25 J1 TEST CONNECTOR H3254 i DDS MODEM CABLE TEST CONNECTOR H3250 O3 T, e, ., Fod Yo Y ) D o Ny | MK-2134 Figure 2-8 Figure 2-6 DMR-11 REMOTE SYSTEM CABLING DMRI11 Remote System Cabling Diagram (Sheet 2 of 2) FULL-DUPLEX - BCO8S-1 INSTALL 75Q TERMINATOR re M8202-YD LINE UNIT cm ) CONNECTOR (H3257) PLACE HDX/FDX SWITCH | m8207 MICROPROCESSOR N IN FDX (down) POSITION J1 M8200-XX M8203 LINE UNIT MICROPROCESSOR ‘W = J3 J2 == P BCO8S-1 ¢e-¢C - MK-2129 HALF-DUPLEX BCO8S-1 INSTALL 758 s TERMINATOR r—— M8202-YD LINE UNIT )| CONNECTOR (H3257) PLACE HDX/FDX SWITCH | m8207 MICROPROCESSOR =] J1 ,QD MICROPROCESSOR M8200-XX M8203 LINE UNIT 2 J1 ';J___a J3 — BC55N-98 BCO8S-1 MK-2130 Figure 2-7 DMCI11 to DMR11 Integral (Local) Modem Cabling Diagram [ FULL-DUPLEX BCO8S-1 INSTALL 750 M8203 LINE UNIT TERMINATOR CONNECTOR (H3257) BC55A-10 &= ; L HDX/FDX SWITCH O O M8207 MICROPROCESSOR J1 =\ MUST BE IN THE FDX J1 M8207 MICROPROCESSOR M8203 LINE UNIT J1 .JiZ. w0 BCO8S-1 BC55A-10 INSTALL 759 TERMINATOR CONNECTOR (H3258) * FOR 56K bps USE CABLE BC55N-98 FOR 250K bps to 1M bps USE CABLE BC55M-98 MK-2127 9¢-T HALF-DUPLEX ( BCO8S-1 ‘ INSTALL 759 = TERMINATOR CONNECTOR (H3257) BCEEA-10 M8203 LINE UNIT 2 2~ || = M8207 MICROPROCESSOR o= wo, S8\ \ J1 = T ()| musT BE IN THE ot 0@ HDX (up) POSITION ON BOTH PANELS M8203 LINE UNIT . £ & e BC55A-10 INSTALL 759 TERMINATOR CONNECTOR o m M8207 MICROPROCESSOR | HDX/FDX SWITCH “@ . T | BCO8S-1 Y, * FOR 56K bps USE CABLE BC55N-98 FOR 250K bps to 1M bps USE CABLE BC55M-98 (H3258) MK-2128 Figure 2-8 DMRI1 to DMR11 Integral (Local) Modem Cabling Diagram 2.8 DMRI11-XX INSTALLATION CHECK-OFF LIST Date Completed PHASE-1 - Preinstallation Considerations: System placement (2.4.1.1) Device placement (2.4.1.2) 000 O System requirements (2.4.2) UNIBUS loading Power requirements Interrupt priority level DMRI11 device address determination DMRI11 vector address determination PHASE 11 - Microprocessor Installation 1. Unpack DMRI11 option and verify that all components were shipped (2.2 and Table 2-1). With power ON, verify selected SPC backplane voltages (2.5.1 and Table 2-2). Turn power OFF and remove NPR Grant (NPG) wire on selected SPC backplane slot (2.5.1). Perform resistance checks to ensure that there are no shorts to ground on the backplane (2.5.1 and Table 2-2). Ensure that the module is an M8207-RA and that W1 and W2 are correctly installed (2.5.2 and Table 2-3). Install correct device address as determined in Phase I (2.5.2 and Table 2-4). Install correct vector address as determined in Phase 1 (2.5.2 and Table 2.5). - Install correct switch selectable features (2.5.2 and Table 2-6). Ensure that Priority Plug E77 is a BR5S and that it is properly installed (2.5.2). 2-37 Date Completed 10. Install microprocessor module M8207-RA into selected SPC slot (2.5.3). Perform resistance checks on backplane to ensure that no shorts to ground exist on the module. Turn power ON and verify voltages (2.5.3 and Table 2-2). 12. Load and execute M8207 Static Diagnostics (2.5.3 and Chapter 4). PHASE III - Line Unit Installation l. Install the correct jumpers and switch selections for the appropriate DMRI11 option. Use Table 2-7 to initially set up line unit and if additional features are required, refer to Tables 2-8 through 2-11 (2.6.1, Figure 2-2, and Table 2-7). Also refer to: Table 2-8 Table 2-9 Table 2-10 Table 2-11 Jumper Functions Switch Pack E39 Functions Switch Pack E121 Functions Switch Pack E134 Functions Important switch/jumper verifications: a. If DMRI11 is used with a DMCI11, make sure Switch Pack E121, switch 9 is OFF (Table 2-10). b. If DMRII is operating at a speed of IM b/s, make sure Switch Pack E121, switch 10 is OFF (Table 2-10). c. If microdiagnostics are desired on initialization of the device, ensure that Switch Pack E134, switch 10 is in the appropriate position (Table 2-11). d. If down-line load or remote load detect feature is used, install the appropriate boot offset address in Switch Pack E121, switches 1-8, and the system password in Switch Pack E134, switches 1-8, at the remote end (Table 2-10 and Table 2-11). 2-38 NOTE M9301-YJ or M9312 bootstrap module must be installed at the remote end. With power OFF, carefully install the M8203 line unit adjacent to the microprocessor with interconnecting cable BCO8S-1 in J3. The other end is installed in J1 of the M8207-RA microprocessor (2.6.2 and Figure 2-3). Correctly insert the proper module test connector in J1 and/or J2 of the M8203 line unit (2.6.2, Figure 2-3 and Figure 2-6). Turn Power ON, perform voltage checks, and adjust if necessary (2.6.2 and Table 2-2). Load and execute the M8203 static diagnostics selecting module test connectors H3254 or H3255 (2.6.2 and Chapter 4). Remove module test connector(s) and install the appropriate option cable to either J1 or J2, as required. When installing cables BC55A, BC55B, or BC55C, it 1s necessary to mount the connector panel on the rear mounting rail of the cabinet. It is important that the panel be properly mounted to ensure adequate grounding. Insert the appropriate turnaround test connector at the end of the cable. Load and execute the M8203 static diagnostics in External Mode to verify cable connections (2.6.2, Table 2-7 and 2-12, and Figure 2-4 and 2-93). NOTE On Integral Modem options, ensure that the 75 ohm receive line terminators are installed on the BCS5A10 panel as shown in Figure 2-7 or Figure 2-8. PHASE IV - DMR11 System Testing 1. With cable turnaround test connectors still installed, load and execute the DMRI11 functional diagnostic test (2.7.1 and Chapter 4). 2-39 Date Completed Date Completed Configure and execute the DECX11 system exerciser to include the DMR11 option (2.7.2 and Chapter 4). Using ITEP, perform DMRI1 link testing on the following (if possible): a. b. c. Cable test connectors installed Modem Analog Loopback test Link testing over network (2.7.4). Remove all cable test connectors, if installed, and connect appropriate cables to the modem or distribution panels (2.7.3, Figures 2-6, 2-7, and 2-3). 2-40 CHAPTER 3 PROGRAMMING 3.1 INTRODUCTION The information in this chapter is essential when developing a user program that will properly interface to the DMRI1. The command structure and format of input and output commands, as well as data port descriptions, are described in detail. Some examples of instruction sequences are also provided to demonstrate a typical method of user program implementation. Other discussions include special programming techniques, user access to maintenance mode, and user interpretation of status/error reporting. 3.2 COMMAND STRUCTURE The command set for the DMR11 is structured into two categories; input commands and output commands. Brief descriptions of Input/Output commands, including command codes and the hand- ~ shaking requirements, are provided in this section. Transfer of control and status information between the main central processing unit (CPU) resident user program and the DMRI11 is accomplished through four 16-bit UNIBUS control and status registers (CSR). Input commands are issued to the DMR11 by the user program and output commands are issued to the user program by the DMRI11. 3.2.1 Control and Status Registers Four 16-bit CSRs are used to transfer control and status information. These registers are both byte and word addressable. The eight bytes are assigned addresses in the floating address space in the 1/O page as follows: X X0, 76X XX1, 76XXX2, 76XXX3, 76XXX4, 76XXX5, 76XXX6 and 76XXX7. 76X For discussion, these byte addresses are designated Byte Select O through 7 (BSEL 0 through BSEL 7). The four word addresses are the even numbered locations and are designated Select 0, 2,4, and 6 (SEL 0, SEL 2, SEL 4, and SEL 6). It is recommended that the CSR address be assigned to the floating address space. Refer to Appendix A if detailed information on floating address space is required. Figure 3-1 provides an overview of the CSR register format. Detailed bit descriptions of SEL 0 and BSEL 2 are contained in Tables 3-1 and 3-2 respectively. 3-1 Table 3-1 Bits 0-3 Name Input Command Codes SEL 0 Bit Functions Description Bits 0-2 define the type of input command issued by the user program to the microprocessor (see Table 3-3). Bit 3 is reserved for future expansion of the input command set. 4 Reserved > Request In (RQI) Serves as an interlock bit when requesting the use of the data port - set by the user program to request the data port. It is cleared by the program when the data port has been loaded. 6 Interrupt Enable In (IET) 7 Ready In (RDI) : When set, allows the DMRI11 to interrupt to vector address XX0, when RDI (bit 7 of BSEL 0) is set. RDI is a DMRI11 response to RQI, indicating to the program that it may load the data ports (SEL 4, SEL 6). It is cleared by the DMR11 indicating that the data port has been read and the input command transfer is complete. 8 9 10 Step Microprocessor (Step uP) When set, this bit steps the microprocessor through one instruction cycle. The Run flip-flop should be cleared before executing this control function. ROM Input When set, directs the contents of SEL 6 as the next (ROM IN) ROM Output (ROM OUT) microinstruction to be executed by the micro- processor when Step uP or Run is asserted. When set, modifies the source paths for SEL 6 to be the contents of the addressed control read only memory (CROM) or the next microinstruction ex- ecuted when Step uP is asserted. 11 Line Unit (LU LOOP) When asserted, connects the line unit serial line out back into the serial line in. This is done at the TTL level, before level conversion. When the Line Unit Loop bit is set and Run is cleared, the STEP LU clock is the only clock available for shifting data out or in. When LU Loop and Run are set, data is clocked at the maintenance clock rate (approximately 48K b/s). 3-2 Table 3-1 Bits | 12 SEL 0 Bit Functions (Cont) Name Description Step Line Unit Used in conjunction with LU Loop. When asserted, the transmitter shifts. When cleared, the receiver shifts. 13 Microdiagnostics (MICRO DIAG) This bit controls automatic execution of internal microdiagnostics at Master Clear time. Depending on the position of switch 10 of Switch Pack E134 (MS8203 line unit) either the Set or Cleared condition of this bit can enable this feature. Refer to the chart below for specific conditioning. SELO BIT 13* ‘ SW I10AT E134 ON M8203 Execution of Microdiagnostics Clear ON - No Microdiagnostics Run Clear OFF Run Microdiagnostics Set ON Run Microdiagnostics Set OFF No Microdiagnostics Run 14 Master Clear When set, Master Clear initializes both the microprocessor and the line unit. This bit is selfclearing. The microprocessor clock is enabled, and the Run flip-flop is asserted. The microprocessor’s program counter is also temporarily cleared by Master Clear. 15 Run On power up reset or device Master Clear, this bit is set by the DMR11 microcode to inform the user program that the DMRI11 is ready to accept input commands. Run can be cleared for maintenance states. *At Master Clear time. ROl RUN '| | 1Bl i i] '| ' ORI i r | DIAG | 'MASTRl MICRO| STEP CLR l L INPUT COMMAND : 1 LW , | LU 1 ¥ RDO ! o || || | } ; : { | ROM | LOOP I ‘ l BSEL CODE o 1T | I OUT z = i | ROM | 1 ]T 0 — STEP | MP | T | COM | OUTPUT | RCY | : COMMAND ‘ . 2 y P SEL 2 MICRODIAGNOSTIC STATUS * 1 L ] 3 1 / 1 1 1 i 1 1 2 1 ] ] . DATA PORT } } ) } 4 % + { } SEL 4 DATA PORT 5 s ! 1 1 N ! 1 1 ] || ¥ ! 1 1 1 ] 6 DATA PORT SEL6 } 4 % : + + : 7 DATA PORT { 7 , 6 ; 4 5 4 4, 3 2 | ) ’ 1 | i 1 1 N 1 + SELO 1 1 4,3 O MmK-2221 *Valid only immediately after Master Clear or Reset. Figure 3-1 UNIBUS Control and Status Registers Format Overview. Initialization 3.2.2 Initialization places both the DMR11 hardware and firmware in the initialized (operational) state. In the initialized state, the DMR11 does not send or receive messages, but it does check for Enter MOP messages and for remote load detect (RLD). Initialization is accomplished by one of the following methods: 1. 2. System Initialization e System Reset e Power-up/shut-down sequence By the user program - Set Master Clear bit (BSEL 1) Initialization of the DMR11 by the user program is done in two steps. The Master Clear bit is set, and then waits for the DMRI11 to set the Run bit. Once the Run bit is set the DMRI11 is ready to accept Base In. 3-4 Table 3-2 BSEL 2 Bit Functions Bit Name Description 0.1,2 Output Command These bits define the type of data transfer from the microprocessor to the user program: Bit 2 0 Bit 1 Bit 0 Description 0 0 Transmit ' Buffer Address/ Character Count Out (TBA/CCO) 1 0 0 Receive Buffer Address Character Count Out (RBA/CCO) 0 0 1 Control Out 0 1 0 Reserved 0 ] 1 Reserved 3-5 Reserved 6 Interrupt When set. enables the DMRI1I1, upon asserting Enable Out RDO.to generate an interrupt to vector address (IEO) XX4. Ready Output Asserted by the DMRI1 to indicate that the data (RDO) ports (SEL 4 and SEL 6) contain data for the out- 7 put command defined by bits 0-2 of BSEL 2. Bit 7 must be cleared by the user program after the data port is read. 3-5 Internal microdiagnostic testing is automatically executed at this time (during power-up/initialization) providing that this feature is appropriately enabled as described below: SEL 0 BIT 13* SW10 AT E134 ON M8203 Execution of Microdiagnostics Clear ON No Microdiagnostics Run Clear OFF Run Microdiagnostics Set ON Run Microdiagnostics Set OFF No Microdiagnostics Run * At Master Clear time. 240 microIf microdiagnostic testing is disabled, the Run bit will be asserted by the DMR11 in about nds. milliseco 6.4 about in pass) tests (if asserted seconds. However, if enabled, the Run bit will be must check BSEL Test results (listed below) are available to the user program in BSEL 3. The programRun bit and further the assert not will 11 DMR the 3 before proceeding with Base In. If the tests fail, required. For is l personne Service Field ed authoriz by operations are prohibited. Corrective action additional information on microdiagnostic test, refer to section 4.5.4. BSELI1 BSEL3 Indication Run bit Run bit no Run bit no Run bit 2003 100g 001g or XXX 002g Test Complete Test Inhibited M 8207 Test Failed M 8203 Test Failed Programming Example: 1$: MOV #40000,SELO :SET MASTER CLEAR BIT SELO ;TEST RUN BIT BPL 1$ ‘BRANCH IF NOT READY YET :CHECK BSEL3 FOR MICRODIAGNOSTIC :STATUS -PROCEED WITH BASE IN NOTE If the Run bit is not asserted within 6.4 milliseconds, either the M 8207 or the M 8203 test may have failed and the user should check BSEL 3. 3.2.3 Input Commands Overview to assign In general, input commands provide the means for the user program operational modes cominput each of formats and ons descripti receive of transmit buffers to the DMR11. Detailed field mand are provided in section 3.3. Input commands are executed by the user program by requesting service and by setting the appropriate bits of the command code in bits 0-3 of BSEL 0. Specific handshake requirements to implement command transfers are explained in section 3.2.3.1. Input commands are listed in Table 3-3. The Base In command is the only command that the program can issue, without causing a procedural error, following intialization. Table 3-3 Input Commands Input Commands BSELO Bit 3 Bit 2 Bit 1 Bit 0 Character Count In 0 0 0 0 Control In 0 0. 0 ] Halt 0 0 ] 0 Base In 0 0 ] 1 0 1 0 0 Transmit Buffer Address/ Receive Buffer Address/ Character Count In The Base In command must be followed by Control In. then Receive Buffer Address/Character Count In (RBA/CCI), and then Transmit Buffer Address/Character Count In (TBA/CCI). Section 3.5, Programming Techniques, further defines proper command sequencing. 3.2.3.1 Input Command Handshaking At start up time, before the user program can execute any input command, it must initialize the DMRI11!. This is accomplished by the program setting the Master Clear bit in BSEL | and waiting for | the DMRI11 to set the Run bit. Input command sequencing requires that Base In be the only input command used following initialization. This command must be followed by Control In, Receive Buffer Address/Character Count In, and Transmit Buffer Address/Character Count In, respectively. All input commands are issued by the user program in two successive steps. The first step requests the use of the data ports. The second step identifies the command type and the data port information for the appropriate command. The specific content of each data port is further defined under each command description in section 3.3. The handshaking procedure for input commands is as follows. (A typical programming example for an input command assignment is provided in Figure 3-2. The flow chart in Figure 3-3 further defines this process.) The user program: e Requests the use of the data port to issue an input command by setting Request In (RQI) bit 5 of BSEL 0. The user may also set bit 6 of BSEL 0, Interrupt Enable In (IEI), at the same time (using the same instruction) to allow the DMRI1 to interrupt the CPU when the data port is available. 3-7 1. NOTE Because of interrupt and service time, it is most efficient for the user program to have input interrupts disabled and to simply scan RDI a few times (for less than S50 us). If RDI is not set by the DMRI11 in 50 us, the user should set the IEI bit twice and wait for an interrupt. 2. When setting the IEI bit, the user program must use two consecutive bit set byte (BISB) instructions. 3. e If interrupt mode is not used, the user must. scan for Ready Out (bit 7 of BSEL 2) while waiting for RDI to set. The user program must be prepared to accept an output transfer from the DMRI11 while it is waiting for RDI. When the Data Port is available, the DMR 11 informs the user by setting Ready In (bit 7 of BSEL 0) and, if IEI was previously set, the DMR 11 generates an interrupt to vector XXO0. e If modem status is desired, the user can, at this time, read SEL 4 and SEL 6 for modem status. * On detecting RDI bit set, the user can load the input command code into bit 0-3 of BSEL O and also load the appropriate information into SEL 4 and SEL 6. e The user must then clear RQI (bit 5 of BSEL 0) to inform the DMRI11 to decode the input command. e When the DMRI11 has read and decoded the input command, it clears RDI (BSEL 0, bit 7). This completes input command handshaking. 3.2.3.2 Modem Status Read - This feature provides the user program with the option of reading (monitoring) modem status during an input command. Modem status is updated by the DMRI11 to SEL 4 and SEL 6 each time RDI is asserted in response to RQI. Modem status is not guaranteed to be accurate prior to asserting RDI or after the program clears RQI. Sensing RDI set, the user program can read the status before loading the data port(s) for the particular command being executed. Figure 3-4 shows the format for the modem status read feature. Table 3-4 lists the bit descriptions of modem status read for all four data ports. 3-8 INPUT COMMAND ASSIGNMENT ROUTINE: THIS ROUTINE COULD BE ENTERED VIA THE FOLLOWING CONDITIONS: 1. APPLICATION PROGRAM ISSUES AN INPUT COMMAND. 2. AT THE COMPLETION OF THE INPUT COMMAND OR OUTPUT COMMAND PROCESSING BY THE DMR11 DRIVER, THERE ARE SOME OUTSTANDING INPUT COMMANDS WAITING TO BE ISSUED TO THE DMR11. ASSUMPTIONS: - : R4 = CONTAINS DMR11 CSR ADDRESS {SEL 0}. - : R6 = SCRATCH REGISTER. - : ICMD: .WORD ; ICMD10 -- INPUT COMMAND CODE .WORD ;ICMD12 -- INFORMATION FOR SEL4. .WORD ; ICMD14 -- INFORMATION FOR SELS6. - : MDMS: .WORD ; MODEM STATUS 1. .WORD ; MODEM STATUS 2. - : OUTPUT INTERRUPT IS ENABLED AT ALL TIMES. INPUT: 10$: 208: 308: BITB # RQI,0(R4) ; IS RQI ALREADY SET? DNE EXIT ; YES - PREVIOUS INPUT IS NOT DONE YET MOV #4,R5 ; SET UP THE WAIT LOOP COUNT BITB # RD!,0(R4) . IS RDI CLEARED ? BEQ 208 : YES - CONTINUE WITH THE INPUT DEC R5 ; SOME MORE WAITING ? BNE 10% ; YES - BR EXIT ; MoV #4,R5 ; SET UP THE WAIT LOOP COUNT BISB #RQI,0(R4) . NOW - SET THE RQL BITB # RDI,0(R4) ; IS RDI SET ? BNE SETINP . YES - GO ISSUE THE INPUT NOW DEC R5 ; SOME MORE WAITING ? -BNE 308 ; YES ; RDI WAIT LOOP EXPIRED 408: EXIT: BISB #1EI'RQL0(R4) ; SET INTERRUPT ENABLE BISB #1EI'RQL,0(R4) ; AGAIN RETURN ; CAN ALSO BE ENTERED FROM AN INPUT INTERRUPT ROUTINE AFTER VERIFYING THAT RQl AND RDI ARE BOTH SET. SETINP: MOV 4(R4), MDMS+0 ; GET MODEM, STATUS NOW MOV 6(R4), MDMS+2 ; BISB ICMD+0.0(R4) ; SET THE INPUT COMMAND CODE MOV ICMD+2,4(R4) ; LOAD DATA PORT SEL4 MOV ICMD+4,6(R4) : LOAD DATA PORT SEL6 BICB # RQIIEI O(R4) ; CLEAR RQI AND IE! RETURN Figure 3-2 MK-2245 Programming Example for Input Commands 3-9 ( INPUT Y ENTER HERE TOISSUE AN INPUT COMMAND RQl ASSUMPTION SET (1) IEO SET AT ALL TIMES. N RDI Y SET N | N SET RQl 50 ps T/0 Y SET (SOFTWARE FLAG FOR) INPUT COMMAND \ RDI PENDING. ( EXIT SEV N T/0 Y Y ) N 50 us SET IEI TWICE (CONSECUTIVELY) INPUT INTERRUPT EXIT SERVICE ROUTINE SETINP ) RaQl & RDI SET | B SAVE MODEM STATUS FROM SEL4 & 6 PROBLEM @ SET INPUT CODE INTO BSEL O B LOAD SEL 4,6 B CLEAR RQl & IE| =D Figure 3-3 Input Command Servicing 3-10 MK-2230 ! 1 : INPUT COMMAND CODE , + } i I | ] : : | t t t | | I | l| 11 | : T I l I | I | : | % | RING | | % l l | 4 | | + sic t | D TR sig | | RTS : , l : | % ! ; DS R I | % | | | 1 | | RTS | HOLD [ INTGL | | I PROG 3 4 | } SEL 6 ! ] v ) 2 ‘ 6 | SELECT | 1 ] ] 7 } t t } SEL 4 . 1 l ’ ) 4 | || | } 4 | STND | CARR | DET By | | mopE | | SEL2 3 | 1 t V3% imopem! 5 2 I t ] l | ! I' 1gsT | ! / . : I CTS ! i | | | l | ] 6 + + I RS-232 | , 4 | | | HPX RS-422 | ps.423| 7 + i I } ! HDX 1 i i | DTR | t l | l § L | I | t | l | b SELO ] | T o | | | 1T \ BSEL I | I | | RATE | auaL | ., ' I O ’ | MK-2247 Figure 3-4 Modem Status Read Format Table 3-4 Modem Status Bit Descriptions Port ~ Bit(s) Name Description (If Bit is Set) BSEL 4 0 Carrier Valid for both the Integral Modem and the modem interfaces. Indicates that the receiver is active. ] 2 3 References the Standby indication from the Standby modem (refer to EIA specification RS-449). Clear to This is a reply from the modem indicating that Send data can be transmitted. Modem Indicates that the modem is in service. : .. i Ready 4 This indicates that the line unit is set in half- Half- duplex mode. Duplex 3-11 Table 3-4 Port Bit(s) 5 Modem Status Bit Descriptions (Cont) Name Description (If Bit is Set) Request to This indicates that the Universal Synchronous Receiver/Transmitter (USYRT) is ready to start Send transmitting data as soon as Clear to Send is true. 6 Data Terminal Ready 7 BSEL 5 ~ Ring Test Mode 15 BSEL 6* 0 Indicates that the modem has just been dialed up. | Indicates that the modem is in the test mode (refer to EIA specifications). Reserved — Bit condition, don’t care. 11-13 14 o . eis available availe . on-line. and unit the line dicating Reserved - Bit Condition, don’t care. 8.9 10 A signal from the line unit to the modem in- Signal Quality A signal from the modem that indicates the presence or absence of the carrier. Usually, when this Signal A signal from the modem that indicates a data Rate RTS Hold signal is ON it indicates the presence of a carrier and OFF indicates an absence of a carrier. rate. Usually a negative level indicates a lower rate while a positive level indicates a higher rate. This bit is set for FDX at speeds less than IM b/s in DDCMP normal mode. When set, RTS (EIA CA/CCITT 105) will be held asserted while the communications link is idle (except during error recovery). Reserved; Bit condition, don't care. 1,2&3 4 HDX half-duplex mode. Reserved; Bit condition, don’t care. 5 6 When set, indicates that the line unit is set in DTR When set indicates that the line unit is available and on-line. *BSEL 6 contains data written to the modem register by the DMRI11, as opposed to SEL 4 which contains what was read. Modem Status Bit Descriptions (Cont) Table 3-4 Name Bit(s) Port Reserved: Bit condition, don’t care. Program Selected - Used for diagnostic purposes. When set, the modem interface is defined by other bits in BSEL 7. Used for test purposes 7 8 BSEL 7 (applies only after Description (If Bit is Set) when clear. Base Table is assigned) 5 & i0 Reserved; Bit condition, don't care. 11 When set, indicates Integral Modem selected. When set, il;ldiC’dICS V.35 interface selected. | 12 13 Reserved: Bit condition, don’t care. 14 When set. indicates RS-232-C or RS-423-A interface selected. . ' When set, indicates RS-422-A interface selected. 15 Output 3.2.4 Commands Overview Output commands provide a means for the DMR11 to report various normal and abnormal (error) conditions concerning the data transfer operation. Two basic commands are provided: 1. Receive or Transmit Buffer Addresss/Character Count Out and 2. Control Out The Buffer Address/Character Count Out command is used to report a successful, error free. completion of a receive or transmit buffer and indicates the actual number of bytes transferred. This command utilizes both SEL 4 and SEL 6 to identify the address of the completed buffer and the actual character count of the transfer. The Control Out command is used to report specific conditions concerning the DIGITAL Data Communications Message Protocol (DDCMP), the user program, the hardware, or the modem. Control Out utilizes SEL 6. as shown in Figure 3-5. to inform the user program as to the nature of the report. The various conditions are shown below. e FError Status Identifies the reason for the error condition; that is, errors can be associated with the DDCMP, the user program, modem, or other hardware limitations. In some cases the error condition is non-fatal and normal operations can continue. Other errors are fatal, causing the DMRI1 to shut-down. - 3-13 SEL 6 START i '\ RCVD * . 7 | | l L ., MSGTOO| MAINT | B LONG * T ' 4 e 5 4 T 4 W A . 3 4 ) TIME OUT oA NAK THRES ' HALT * | NON * l | 2 ' * = FATAL ERRORS Figure 3-5 | | | COMPLETE| EX-MEM | | 4 ! | NO | | | | l RCVD * =~ BUF | | l €& | [ [ (yscon ., 0O | MK-2238 Summary of Control Out Status Detailed bit descriptions of SEL 6 for Control QOut are contained in section 3.4.3. 3.2.4.1 Output Command Handshaking The DMR11 issues output commands in two steps. The data pertinent to the command being issued is loaded into SEL 4 and 6. Once this is complete, the DMR11 sets the Ready Out (RDO) bit and the command code in BSEL 2, and generates an interrupt through vector XX4 if the IEO bit is set. Generally, processing an output command involves the following steps: e The user program checks for RDO set. This can be done through periodic checking or by waiting for an interrupt, assuming that interrupts are enabled. NOTE It is strongely recommended that the output interrupt capability be used to avoid unnecessary delay on the M8207-RA processor when CSRs are constantly scanned. e To use the output interrupt capability, the user program must set the output interrupt enable bit in BSEL 2 immediately after it detects that Run bit has been set following Master Clear. After Base In, IEO must never be changed unless RDI or RDO is set. e When a RDO set condition is detected, the user program should read SEL 2, SEL 4, and SEL 6 into three registers or a storage area and clear RDO in BSEL 2. When RDO is cleared, the data port (SEL 4 and 6) will be released for more input or output command processing. The flow chart in Figure 3-6 illustrates a typical procedure for the user program to implement output command servicing. The example shown is for interrupts enabled. It also demonstrates user requirements to process each command. This procedure is provided as an example only and should not be considered as the only method to implement output command servicing. 3.3 . INPUT COMMANDS This section provides detailed descriptions of each input command. Command formats and data port usages are illustrated and defined in terms of user program execution requirements, command variables, and action taken by the DMRI11 in response to the command. 3-14 OUTPUT INTERRUPT SERVICE ROUTINE NOTE: THIS FLOW CHART ASSUMES: 1) IEO IS SET AFTER MASTER CLEAR. 2) R3, R4, RS ARE AVAILABLE FOR USE. LOG SUPRIOUS INTERRUPT ERROR R3<-(SEL 2) R4--(SEL 4) R5=(SEL 6) CLEAR RDO IN BSEL 2 INTERRUPT EXIT 000 TRANSMIT BA/CC O __0o1 CONTROL OUT BIT2-0 IN R3 (BSEL2) 100 RECEIVE BA/CC 0 A HANDLE THE SUCCESSFULLY TRANSMITTED BUFFER LOG ERROR TYPE HANDLE THE SUCCESSFULLY RECEIVED BUFFER BUFFER ADDR (R4) - BUFFER ADDR. (R6) CHAR.COUNT/ (R5) - CHAR COUNT/ IS ‘BA16, 17 IT FATAL (R4) BA16, 17 © | ERROR? (R5 = ) (R5 =10, 20, 200, 400, 1000) TAKE APPROPRIATE ACTION TO CORRECT ERROR CONDITIONS ANY INPUT COMMAND TO BE ISSUED - TAKE CORRECTIVE ACTION - MASTER CLEAR DMR11 - RESTART DMR11 INTERRUPT EXIT MK-2231 Figure 3-6 Output Command Servicing 3-1 5 3.3.1 BaseIn The Base In command is the only command allowed after initialization. It performs two basic func- tions: I. 2. Assigns a Base Table to the DMRI11 and Implements the Resume feature The command format for Base In is shown in Figure 3-7. Base In assigns a Base Table of 128 bytes to the DMRI11, beginning at the address specifiedin SEL 4. This table remains dSslgned to the DMRI1 until it is initialized or shut-down by the Halt command. If the Resume bit (SEL 6, bit 12) is asserted by the user program, the DMR 1 immediately reads the contents of the Base Table into its random access memory (RAM). At this time, the DMRI11 also examines the Base Table for non-existent memory (NXM). If there is a NXM error, the DMR11 will report the error by Control Out/NXM. For additional material concerning Base In with the Resume feature, refer to section 3.5.2. NOTE The user program should not assign the Base Table at an odd address boundary. | T I T | I | | ! : ! | I I | I I | ] 1 | | 1 | | I [ } } + |l H 1 l | ! | | | | | | T BSEL i | | | | | L 1 } | } | i 1 i | | } t : 2 b SEL 2 | 1 3 / { | 4 t } t | I 1 1 1 1 | | | l | b SEL 4 BASE ADDRESS HIGH BYTE | BA 17 I BA 16 { . 7 | 6 1 [} 1 i | | -+ + } | { I 'RESUME| | | | | | | | 5 4 | 1 4 4 3 5 | } | } | I | 1 { 4 J . : I 1 1 BASE ADDRESS LOW BYTE + \ 0 1 T 1 1 | | 1 | 1 1 | | T i T 0 I | | 1 T o | | L T BASE IN | | | 1 1 T 2 4 / \ ] L SEL 6 ! 7 ] 1 4 / 0O MK-2222 Figure 3-7 Base in Command Format 3-16 1t provides further definition of the operation by This command must be executed following Base In. nd In performs three major functions. Control In 3.3.2 making specific mode selections in BSEL 7. Comma e Selects DDCMP Normal or Maintenance Mode, e Selects the Start Timer Selects half-duplex of full-duplex, and e The command format is shown in Figure 3-8. Table 3-5 lists data port (BSEL 7) bit descriptions for this command. I I]; 1 | }i I| 0 T4 0 fTl 0 i1 1 | | I | | T i 1 l ¥ T | T | | | I [ l '. | T | I I I | ! I I | I I ‘ I I I i | | T1 T I | I | t : I {1 [l1 I + | } I 4 4, 6 | 5 , || ]1 I ) | } | } | } 3 4 Figure 3-8 | | 3 I MAINT | 2 7 | DDCMP | | | 1 | } SEL4 \ | | | ] | | 1 1 | TIMER | | l | 1 | START | HDX I | | | | | i / 5 | ] | I | | } | | | | | I | 1 | p SEL 2 ) 4 | } | | I I } } } } l I I I | } 5 : | I | | I 2 | | | , R § T T T T| 1 } SELO 1 . { | ! 0 | | : 7 ]1 | : I, | ( I IN CONTROL . BSEL T ] : | i I 0 | } SEL 6 . / MK-2223 Control In Command Format e a protocol Control In causes the DMRI11 to initiatsendin If selected for DDCMP Normal Mode, the first g Start e Stack messages. The interval for start-up sequence and send Start and acknowledg s and is selected by the user program in Bit 3 of BSEL 7.The messages can be either one or three secondvalue. one second timer interval is the default collisions on the line ion is not critical because Start messaisgeslight. In full-duplex mode. the timer value select Start messages even though the possibility are not possible. In half-duplex mode, however. would never could be issued by both devices at the same time. With identical time intervals., Stack occur. second timer at one end to the user program can select thegethree To eliminate this remote possibility, the coincident Start messa would not return a Stack. The offset the interval. In this case, only first y. This condition is illustrated in Figure 3-9. device set at one second will have priorit 3-17 Table 3-5 Data Port Descriptions with Control In Port Bit(s) Function Description BSEL 7 (Write) 0 DDCMP Maintenance DDCMP Maintenance - When set by the user program, it causes the microprocessor to enter the DDCMP Maintenance Mode. It will remain in this mode until initialized. When this bit is “0” the microprocessor will enter DDCMP Normal Mode. 2 Half-Duplex HDX — When set, half-duplex mode is selected. When cleared by the program, full-duplex mode is selected. 3 Long Start Timer When set, a three second Start timer is selected; when clear, a one second Start timer is selected (the Start timer is the interval for sending Start/Stack). 1 & 4-7 Reserved; Bit condition, set to 0. If selected for DDCMP Maintenance Mode, a special DDCMP message format, the maintenance message, is used for down-line loading, restarting, or otherwise maintaining satellite computer systems. Messages in this format are subject to error checking but are unsequenced, unacknowledged, and not automatically retransmitted by the microprocessor. To set the DMRI11 into Maintenance Mode, the user program must initialize the DMRI1I, give it a Base In with the Resume bit clear, a Control In with the maintenance bit set, and set the half-duplex bit for HDX or clear for FDX. In Maintenance Mode the DMRI11 provides the following functions: . Message framing. 2. Bit error detection - The header and data block check character (BCC) is checked by the DMRL11. If the BCC is bad, the message is discarded with no notification given to the user program. 3. Link management - The DMRI11 provides proper line turn-around in half-duplex mode. 4. Some errors are recorded in the DMRI11’s internal RAM memory and are reported to the user program by updating the Base Table. It is the responsibility of the user program to recover from any error via software time outs, since there is no retransmission attempted in maintenance mode. 3.3.3 Receive Buffer Address/Character Count In (RBA / CCI) The RBA/CCI allows thc user program to a551gn a receive buffer by giving the DMRI1 the starting address of the buffer and the character count in SEL 4 and SEL 6. The DMR11 can accept up to 64 receive buffers. 3-18 DMR TART .o | START TIMER _ |START (HDX) 1 SEC START w <+«—START START -« . START DMR (HDX) 1 SEC TIMER NO STACK RETURNED DMR (HDX) 156 TIMER START > START . | _ - START DMR (HDX) _ _ _ _ _ _] “\ 3 SEC : ___ sTACK | ! TIMER MK-2232 Figure 3-9 Start/Stack Sequence Timer NOTE DMC11 can only accept a maximum of 7 buffers. If the Resume feature is to be used, the maximum number of receive buffers is limited to eight. If the DMR11 has more than eight buffers, it will only save up to eight after Resume. For example, if DMRI11 has BUF 1, BUF 2,....BUF 20 after a Shutdown/Resume operation, the DMRI11 will only retain BUF 1, BUF 2,....BUF 8. The format for RBA/CCI is shown in Figure 3-10. The starting address of the receive buffer is contained in SEL 4 and the two most significant bits of SEL 6. The buffer size is contained in the remaining bits of SEL 6. Buffers range from 1 to 16,383 bytes. The buffer size should be limited to a practical size large enough to accommodate the longest message expected. Each buffer corresponds to one DDCMP data message. NOTE The user program should give a higher priority to assigning all receive buffers before it assigns any transmit buffers. For example, if seven receive and seven transmit buffers are to be assigned, the program should assign all seven receive buffers before assigning any transmit buffers. 3.3.4 Transmit Buffer Address/Character Count In (TBA/CCI) The TBA/CCI allows the user program to assign a transmit buffer by giving the DMR 1] the starting address of the buffer and the character count in SEL 4 and SEL 6. The DMR11 can accept up to 64 transmit buffers. NOTE DMC11 can only accept a maximum of seven buffers. If the Resume feature is to be used, the maximum number of transmit buffers is limited to eight. If the DMRI11 has more than eight buffers, it will only save up to eight after Resume. For example, if DMRI11 has BUF 1, BUF 2,....BUF 20 after a Shutdown/Resume operation, the DMR11 will only retain BUF 1, BUF 2.....BUF 8. Buffers range from 1 to 16,383 bytes. 3-19 1 T l : : I 1 | 1 1 I. ]1 } I | | | ] | ! | v s 1 l| 1 I | || T I T | l } % ! | : — | | O 1 | | ' T I 1] O ] | ] ] L | I | ! } : 1 | | | z T | — 0 2 | ; } } 1 + | L 1 Ll 1 1 { } SEL 4 5 1 1 i T 7 T \ 6 CHARACTER COUNT LOW BYTE BA17 | | BA16 1 \ 7 ¢ | 4 7 CHARACTER COUNT HIGH SIX BITS | 1 6 } SEL 6 } } } } } f t 1 5 4 1 4 4 | 3 4 1 2 : 4 t L 7 l SEL2 3 : BUFFER ADDRESS HIGH BYTE ¥ ’ \ BUFFER ADDRESS LOW BYTE + } SELO 1 l | : 0 . ; | ! BSEL | | | I } 1 - 1 | | | ' RECEIVE BA/CC IN 3 | 4 v / 0 | MK-2224 Figure 3-10 Receive Buffer Address/Character Count In Command Format The maximum size of the transmit buffer is a factor of the line speed and the reply or selection timer value. The time (T) required to transmit each buffer should be less than either the reply timer value (FDX) or the selection timer value (HDX). The user can optimize the buffer size using the following formula: T = (Character Count + 20) X 8 or Character = (T X Line Speed) - 20 Line Speed 8 Count Where: T = Seconds (should be less than the 3 second REP/Select Timer) Line Speed = Bits per second (b/s) Character Count = Number of bytes Each buffer corresponds to one DDCMP data message. The format for this command is shown in Figure 3-11. 3.3.5 Halt Request Command The Halt Request command format is shown in Figure 3-12. 3-20 T l l ] y ' : : | TRANSMIT BA/CC IN T T ] ] T 1 T | | |i I | | | i l 1 1 ) T | | I g | ' | I | } 1 i | ] | I T l | 1 1 i 7 | } T ] 1 / 1 7 1 \ 4 BUFFER ADDRESS HIGH BYTE | | T i i | T 1 1 ‘ 1 ] | SEL 4 + } } } 1 } + } | | 1 BA 17 : BA 16 : ¢ 7 4 6 4, 85 / T . \ $ } } } It 1 1 | CHARACTER COUNT HIGH SIX BITS 4 4 4 3 | 2 5 i i CHARACTER COUNT LOW BYTE -+ b SEL 2 ; BUFFER ADDRESS LOW BYTE + ) 2 | | 1 . b SELO l | | ! | | BSEL | | | + I | 1 T T t | ' T | ' 1 | | t | l | | - 4 1 , 6 } SEL 6 7 / 0 j MK-2225 Figure 3-11 Transmit Buffer Address/Character Count In Command Format Halt Request allows the user to request a controlled DMR11 shut down: that is, in the proper order. Halt Request is the only formal method used to shut down the DMR. CAUTION If the Halt Request command is issued with outstanding transmit buffers, the DMR11 will abort a transmission in progress. The DMR11 shutdown sequence is as follows: 1. Clear data terminal ready (DTR). This condition is performed only when a Halt Request 2. Return all queued up Control Outs. 3. Dump the Base Table to local CPU Memory. The DMR11 will wait up to three seconds for 4. command is issued. It does not occur during a fatal error shut-down. data set ready (DSR) to clear, before issuing Control Out with Halt Complete. Initialize the scratch pads and RAM location 0-400, and reset the M8203 line unit. Data ports are not used for the Halt Request command. 3-21 I i T l T i T 1 T I | | | | : - | 1 T | T | 1 ' I 1 | T 1 ] I I | | | | | | I | | | r | | | : : | | | — I '| 1 i : ] | | ; | | | 4 | } | + | 1 ] 1 T 1 ] 1 } | L} i | | ] | | | | | | | | | | i | | + | | } | I 4 | I } | I + | | } | | 4, 6 4 5 | 4 4 3 4 2 4 \ 5 ' 4 } SEL 6 ; ’ | | 1 1 / | i 1 } SEL 4 5 | | ) 4 I L) 1 . | T { | SEL 2 3 % | | 2 | } i | / \ l } I z 1 | | : | i + } SELO I | | } | I | I HALT REQUEST I | ! | | | } ' ! 7 T I T : | ( T T : . BSEL y T | T 0O ] MK-2226 Figure 3-12 34 Halt Request Command Format OUTPUT COMMANDS Output Commands provide a means for the DMRI1 to report various normal or abnormal (error) conditions pertaining to the data transfer process. There are two basic commands: 1. 2. Buffer Address/Character Count Out, which is further categorized into receive or transmit buffers, and Control Out. The Buffer Address/Character Count Out command is used to report normal transfer completions to the user program. Control Out is used to report abnormal (error) conditions. In either case, if the Interrupt Enable Out (IEO) bit is set, the DMRI11 will interrupt the CPU to vector XX4. If the I[EO bit is disabled (0), the user program, by sensing Ready Out (RDO), assumes the responsibility of recognizing that an output command is pending. When the output command is complete, the user program can execute an Input Command. However, the DMRI11 will not recognize an input request until output command servicing is completed. 3.4.1 Receive Buffer Address/Character Count Out (RBA /CCO) This commandis used by the DMRI11 to report successful completnons of receive buffers to the user program. The format for this command 1s shown in Figire 3-13. 3-22 T T T . y T T BSEL | i ' % | { | , | % ! i | : 0 | : l | I | : RECEIVE BA/CC OUT | ! : l ; 1 | | | | I | | | | | : | ; i | i | 1 | / 0 : ’ i 11 I 11 1 ] | | / {! 11 } } } } } 5 ‘ ACTUAL RECEIVED CHARACTER COUNT LOW BYTE } } SEL4 { } BUFFER ADDRESS HIGHBYTE {i \ 6 } BA 17 I BA 16 lACTUAL RECEIVED CHARACTER COUNT HIGH SIX BITS | } | ] ] { { ( 7 6 | 5 4 4 4 2 % ’ N 4 } } } } | SEL2 | BUFFER ADDRESS LOW BYTE } 9 II { H 1 1 . | | ] 1 |T § ) T 0 : b SELO : % + I l | I | | | { | I | l T I I | | | | 1 | } SEL 6 7 / 0 | MK-2227 Figure 3-13 Receive Buffer Address/Character Count Out Command Format The address of the completed buffer is contained in SEL 4 and the two most significant bits (MSB) of SEL 6. while the actual received character count is contained in the remaining bits of SEL 6. In the normal DDCMP mode, this command indicates that: Cyclic redundancy checks (CRC) are good, The sequence number is correct, The protocol requirement checks are good, and The data is stored in memory (DMAed). In DDCMP Maintenance mode, the following is valid: CRCs are good, e Protocol requirement checks are good, Data is stored in memory (DMAed). 3.4.2 Transmit Buffer Address/Character Count Out (TBA/C CO) buffers to the user This command is used by the DMR11 to report successful completions of transmit 4 and SEL 6. SEL in d containe are count r characte and buffer program. The address of the completed 3-23 In normal DDCMP mode, this command indicates: ® The data was successfully transmitted and ®* An acknowiedgement for that message has been received from the remote station. This command when issued in DDCMP Maintenance mode only indicates: ¢ Data was transmitted. Figure 3-14 illustrates the format for this command. 3.4.3 Control Out The DMRI11 informs the user program of unusual or error conditions involving the microprocessor hardware, user program, physical link, or remote station by means of the Control Out command. Some error conditions are non-fatal; that is, after taking the appropriate action, such as assigning more buffers for No Buffer Available, normal data transfer operations may continue. Other error conditions are fatal, causing the DMRI11 to shut down. Fatal errors require the user program to reinitialize the DMR11. The format for this command is shown in Figure 3-15. The port (SEL 6) bit descriptions for Control Out are listed in Table 3-6. | { | | | i | | v ¥ I | ¥ BSEL 0 | ] | | I | | | i t ! , t t t | ] , [ I | | | l 1 | L} ' | | : : l I | i } + + F 1 1 1 L H T T T T BUFFER ADDRESS } 4 1 L { T ! o} 2 0] b SEL 2 | | | | L) : 3 i Il 7 T L} \ LOW BYTE } -+ 4 2 } | ! L SEL 4 BUFFER ADDRESS HIGH BYTE L) 1 ) L T 1 T | ’ . TRANSMIT BA/CC OUT 0 b SELO 1 | 1 I | I | I | l | | { ' : | | | | l | | N 5 ¥ 7 T \ CHARACTER COUNT LOW BYTE } } } BA 17 : BA 16 | (. 7 4 1 6 4 + } } L SEL 6 CHARACTER COUNT HIGH SIX BITS I L + 6 { 5 4 1 4 4 ] 3 | | 2 4 7 ] v 4 ’ 0 4 MK-2228 Figure 3-14 Transmit Buffer Address/Character Count Out Command Format 3-24 T T ] T T ‘ | f f I , I t I | l I i I I I 1 ] 11 | ] 1 : | I I | | I ' I I I I I | | l : } ! I | | ' | | ! | I 4 I I . { -t | I l I } I I } | I i | START | I | | | | | } | + I } + I | 7 , 6 | } I } 3 T 1 t | I | } | NO | SEL2 | N I } | : I } ) . 4 | } | I } | TIME ! } SEL4 5 NAK | I 5 4 | coMP |EX-MEM | 3 4 4 1 i 1 | 4 | HALT | NON l 2 4 1 4 0O 3 6 } + + I ) | L 2 1 I | | MAINT! } ' l | T { | I MSG 0 | A 9 I LOONOG | revD | BUF | ouT | THRES rovp |PISCON, t 0 + I } / 1 CONTROL OUT I - + 1 { 11 | -+ b SELO | | I . BSEL ' T } SEL 6 , ’ | MK-2228 Figure 3-15 3.5 Control Out Command Format PROGRAMMING TECHNIQUES This section provides various recommendations and considerations necessary for the user program to properly interface to the DMRI11 microprogram. These considerations are further defined in terms of DDCMP Normal Mode and DDCMP Maintenance Mode. The state diagram in Figure 3-16 shows the relationship of each command to the DDCMP states. Specific areas for consideration are summarized below and are explained in detail in subsequent para- graphs. Proper command sequence Execution of input commands with the Resume feature How to distinguish DMR11 from DMCl1 Implementation of DDCMP Maintenance Mode Execution of remote load detect Error detection 3-25 Table 3-6 SEL 6 Bit 0 Data Port Bit Descriptions With Control Out Name Status Type Description NAK Error/Non- This error is reported when persistent line errors (Protocol) received. When consecutive NAK transmissions or NAK receptions occur, they are counted in their respective threshold counter. When the threshold value of seven is reached, this error is reported. Each threshold counter is cleared Threshold Fatal occur, resulting in protocol NAK to be sent or when the threshold is reached or when the oper- ation it is monitoring is performed correctly. l Time Out Error/NonFatal (Protocol) When consecutive REP transmissions occur, they are counted in the threshold counter. This error is reported when the threshold value of seven is reached. Each threshold counter is cleared when the threshold value is reached or when the operation it is monitoring is correctly performed. 2 No Buffer Error/Non- This error is reported for the following condi- Fatal (User Program) tions: DMRI1 has received seven NAKs because of No Receive Buffer Available at the remote end. There were seven attempts to receive a message with No Buffer Available. 3 Maintenace Received Error Fatal (Protocol) A DDCMP Maintenance message format was received while the DMRI! was in DDCMP Run/Start or ASTRT mode. The message caus- ing this condition is lost and the DMRII is forced to shut down. 4 Message Too Long 5 Not Used 6 Disconnect Error Fatal (Program) Error Non-Fatal A received message or transmitted message is larger than the assigned buffer (incluuding main- tenance messages). The DMRI11 will have shut down by the time this error is reported. Indicates that an unexpected drop in DSR (EIA Interface CCITT-107) was detected. (Modem) NOTE On applications using a switched network via dial-up modems, the ON-to-OFF transition of DSR could indicate that the connection has been terminated and a redial or call set up may be required. Table 3-6 SEL 6 Data Port Bit Descriptions With Control Out (Cont) Name Bit Status Description Type 7 Start Error Fatal A protocol Start message was received while the Received (Protocol) DMRI11 was in the DDCMP Run state. The DMRI11 will complete shut-down by the time this error is reported. This error is not reported when the DMRI11 is in DDCMP Maintenance Mode. 8 _ Non- Error Fatal A non-existent memory (UNIBUS address time Existent (Program/ out) condition has occurred on a receive or Memory Hardware) transmit data operation, or a Base Table up- (NXM date/read operation. The DMRI11 has completed the shut-down by the time this error is reported. 9 Halt Complete This condition is reported following completion of the Halt Request Command or programming error: that is, a character count of zero on Transmit or Receive BA/CC In, or assigning Control In or BA/CC In before Base In. Refer to section 3.3.5 for the proper shutdown sequence. 10-15 3.5.1 Not Used Reserved. Input Command Sequence The sequence in which the user program issues input commands is critical. The following identifies the proper sequences. The command sequence is listed in Table 3-7. They are shown in the correct order of program execution. Initialization is the first function that the program must perform. This action is required to reset both the DMRI11 hardware and firmware to the initialized (operational) state. Base In 1s the only command that the user can issue following initialization. Any other commands issued before Base In will cause a procedure error, resulting in a DMR 11 shut-down. This will require the program to reinitialize the DMRI11. Control In should be issued following Base In. After issuing Control In, the user program can assign either receive or transmit buffers to the DMRI11. The sequence of issuing one or the other is not critical, however, the program should give priority to assigning all receive buffers before any transmit buffers. Halt Request can be issued at any time. 3.5.2 Base In Command with Resume Feature The Resume feature can be implemented during a Base In by the program setting SEL 6 bit 12. 3-27 MASTER CLEAR BASE IN/CONT IN l HALT ISTRT RECEIVESTRT RECEIVE STACK RECEIVE STRT ASTRT RECEIVE STACK ACK/RESP=0 DATA MSG/RESP=0 RUN BASE IN/CONT IN/MAINT MAINTENANCE NXM MESSAGE TOO LONG HALT COMMAND NXM ERROR, STRT RCVD, DLE RCVD, MSG TOO LONG, HALT COMMAND SHUT-DOWN DLE RCVD MK-2237 Figure 3-16 DMRI11 Protocol State Diagram The proper command sequence to implement a shut-down and then resume, is as follows: Input Commands Halt Request :shutdown DMRI11 Master Clear ;optional (initialized internally by Halt Request) Base in with Resumeset ;resume DMRI11 Control In :To select half-duplex or full-duplex 3-28 Table 3-7 DMRI11 Command Sequence Command Description Initialization Master Clears the DMR 1 and places it in the operational state. Base In Only command allowed after Master Clear. Assigns the Base Control In Sets DMR11 in either half-duplex or fullduplex mode and either Table to the DMR11 and prepares for protocol startup. DDCMP Normal (Run) or Maintenance Mode. Also establishes a one or three second Start timer. Buffer Address/ Assigns receive or transmit buffers. Can assign up to 64 buffers. Halt Request The Halt Request command can be issued by the user program All receive buffers should be assigned first. Character Count In at any time to formally shut down the DMRI1. and The Resume feature causes the DMRI11 to read the Base table content from the CPU memory resulting Table Base updated the be should ion informat This store that data in the DMR11 RAM. the from the previous shut-down. The information contained in the Base Table will determine whether protocol is, that State; nce Maintena or ASTRT ISTRT, Run, the DMRI11 will Resume operation in start up is not required. However, if the remote end has abandoned the process due to protocol time out, it will be necessary to reinitialize. m of eight receive and eight Buffers assigned to the DMR11 prior to shut-down (up to a maximu transmit buffers) will still be assigned when the operation resumes. If there are more than eight outstanding receive or transmit buffers, they will be lost. 1. NOTE : During shut-down and subsequent Base In with Resume, the Base Table must NOT be altered. If modified, the DMR11 could resume in an undefined state. 2. To use this feature, the number of transmit or receive buffers must be less than eight each. 3. Whenever the Base Table is written to or read from main memory, resulting from a shutdown or Resume operation, 64 back to back DMAs (5-10 microseconds apart) are execued to. transfer the Base Table. Therefore the user must be aware of the effect of the high rate of DMAs on the rest of the system. 3-29 Distinguishing DMR11 from DMCl11 3.5.3 If the user program needs to determine if it is interfacing with a DMCI1 or a DMRII. The user program can execute the procedure listed below as part of the initialization sequence. 1. Load any number (except lg, 28, 100g or 200g) into BSEL 3, 2. Set Master Clear bit (with or without microdiagnostics enabled), 3. Wait for the RUN bit (maximum of 6.4 ms), and 4. Check BSEL 3. The unit is a DMRI11 if BSEL 3 contains either 1g, 2g, 100g, or 200g. NOTE If the microdiagnostic is disabled, BSEL 3 will contain 100g (Test Inhibited). If enabled, BSEL 3 will contain lg, 2g, or 200g. The unit is a DMCI1 if BSEL 3 contains the same number that was written in step 1. 3.5.4 DDCMP Maintenance Mode Operation Maintenance Mode provides the mechanism to implement down-line program loading or restarting/maintaining satellite computer systems via remote load detect (RLD). In this mode, a special message format (maintenance message) is used to execute this feature. Messages in this format are subject to error checking but are unsequenced (not numbered), unacknowledged, and not automatically retransmitted by the microprocessor. Because of this, it is necessary for the user program to recover from any error conditions by utilizing time outs to retransmit the message. To enter the DDCMP Maintenance Mode, the DMR 1 must be initialized and issue a Base In with the Resume bit cleared, followed by the Control In with the Maintenance bit (SEL 6, bit 8) set. 3.5.4.1 Data Transfer — Once in DDCMP maintenance mode, maintenance messages can be sent and received like data messages. On transmission, the data portion of the message is taken from the assigned buffer with the DMR11 generating the header and CRCs. On reception, only the data portion is placed in the available assigned buffer. Messages not in DDCMP maintenance format, having incorrect CRCs orno receive buffers are simply discarded. When operating in conformance with MOP, the DMR 1 must be operated in a single buffered manner, causing a line turnaround after each message is transmitted. When a host computer wishes to restart a satellite computer system, it must send the appropriate MOP messages as described in section 3.54.2. 3.5.4.2 Unattended System Control- Unattended system control (down-line load/remote load detect) is accomplished using the maintenance operation protocol (MOP), version 2.0. There are two basic considerations when using MOP: down-line load (originating station) to remote end and remote (boot station) request for down-line load. The Enter MOP Mode message is used to control an unattended satellite system. This message, to- gether with the appropriately configured hardware, causes the DMRI11 to stop current operations, forcing the computer to transfer control to a resident MOP program or bootstrap. 3-30 Whenever the microprocessor is running, it constantly scans the line for a DDCMP maintenace mes- sage (DLE) containing an Enter MOP Mode data field. The data portion of this message contains five bytes. The first byte contains the number code six. The remaining four bytes contain the password, which must match the password assigned to the line unit. All four passwords must be the same. In order to execute down-line load to the remote station, the following conditions must be true: 1. The password Switch Pack (E134 on the line unit) is NOT set to 377s. 2. All four passwords in the Enter MOP Mode message match the password selected by Switch 3. The data CRC for the ENTER MOP message is good. Pack Ei34 on the M8203 line unit (except 377). Once these conditions are satisfied, the DMR 11 will write via direct memory access (DMA) 173XXX into memory location 24 and zero to location 26 followed by pulling AC LO to initiate a power up recovery. The power up recovery causes the CPU to transfer control to a primary MOP program residing in a boot module such as the M9312 with the DECNET boot ROM at location 173XXX. The designation XXX is the content of the boot offset which is selected by the offset Switch Pack E121 on the M8203 line unit. (switches 1-8). If any of the three conditions are not satisfied, the DMR11 will treat the Enter MOP mode message as specified in Table 3-8. Figure 3-17 illustrates the procedure for remote load detect and the required handshakes to execute this feature. This procedure assumes that the remote device is configured for the appropriate password and offset to implement the bootstrap feature. Appendix E provides a detailed description for executing and testing the bootstrap. Table 3-8 Invalid Enter MOP Message Response Condition Action DMRI11 in Halt or No action taken. Initialized mode DMRI11 in Run, ISTART 1 will enter the Halt state and notify the program that DMR or ASTART mode a maintenance message (DLE) was received. DMRI11 in Maintenance Mode If a receive buffer is available and the message contains a CRC error, the message will be discarded and the error 3.6 counter incremented. BASE TABLE COUNTERS After Base In and Control In are issued by the software, DMR 1 will periodically update the internal counters from its RAM location 2 through 42 (see Figure 3-18) to the Base Table assigned. These cumulative error counters start at 0 and wrap around back to 0 when the maximum count is reached. These counters are updated approximately every second. 3-31 DMR1t1 #2 RECEIVED WITH PWD SELEC- 5-8A/CCI FOR TRANSMIT WITH CHARACTER COUNT OF 5. TRANSMIT BUFFER (N PDP-11 0 0 0 O 1-TRANSMIT ENTER MOP DLE MOP 6 MESSAGE 2-DO A BA/CCO ON TRANSMIT (4 PASSWORD THAT = 0) THE FOLLOWING TO PDP-11 XXX = LINE UNIT. SW PACK E121 4-PULL AC LO ON UNIBUS SEE NOTE 2 DMR11 BOOT CODE IN BOOT ROM (M9301-YJ4/M9O312) PROGRAM CONTROL IS PASSED TO DMR1 1t BOOT CODE WHICH DOES THE FOLLOWING. 1-INITIALIZE DMR11 2-BASE IN TO DMR11 3-CONTROL IN TO DMR11 WITH SEL6 = 2400 4-BA/CCI FOR RECEIVE WITH A CHARACTER COUNT OF 4092 5-BA/CCI FOR TRANSMIT WITH CHARACTER COUNT OF 4. TRANSMIT BUFFER IN PDP-11 MEMORY SHOULD BE 10, 14, 1,0 (MOP 8: REQUEST SECONDARY BOOT) 6-SEE NOTE 1 1-CHECK VALIDITY OF REQUEST SECONDARY . . e e SEE NOTE 1 TED IN LINE UNIT SWITCH PACK E134 3-IF ALL 4 PWD's MATCH, DMA MEMORY 24/174 XXX, 26/0 DONE e MMEMORY SHOULD LOOK LIKE6 | COUNT OF 256 i 4-BA/CCI FOR RECEIVE WITH CHARACTER e 3-CONTROL IN TO DMR11 WITH SEL 6 = 2400 —— e 2-COMPARE PASSWORD (PWD) — 1-CHECK FIRST BYTE = 6 1-INITIALIZE DMR11 2-BASE IN TO DMRARI11 _— e — LINE — SERIAL DMR11 #1 SOFTWARE AT HOST BOOT MESSAGE RECEIVED COUNT OF (X + 12). THE TRANSMIT DO A 8A/CCO RECEIVE TO PDP-11 MOFP 8 1-TRANSMIT REQUEST SECONDARY BOOT MESSAGE (MOP 8) 2-DO A BA/CCO TRANSMIT IMAGE DATA LOADED = X BYTES c——— el LOAD ADDRESS (4 BYTES) =0 e LOAD NUMBER (1 BYTE} =0 e CODE (1 BYTE) =0 —— BUFFER CONTAINS MOP O MEMORY LOAD WITH TRANSFER ADDRESS AS FOLLOWS: [ ] TRANSFER ADDRESS (4 BYTES) =0 TRANSFER ADDRESS (4 BYTES) =0 4-5EE NOTE 1 WITH TRANSFER ADDRESS) 1-VERIFY MOP CODE = O AT LOCATION O DLE MOP O DO A BA/CCO RECEIVE TO PDP-11 2-DO A BA/CCO TRANSMIT THEN DO A SYSTEM RESET 2-JUMP TO LOCATION 6 TO PASS PROGRAM CONTROL TO NEWLY LOADED PROGRAM e TRANSFER ADDRESS (4 BYTES) =0 1-TRANSMIT MOP 0 (MEMORY LOAD TEANSFER ADDRESS (4 BYTES) =6 — (A% 3-DO A BA/CCI TRANSMIT WITH CHARACTER DLE e COUNT OF 256. — 2-DO A BA/CCI RECEIVE WITH CHARACTER NOTES: 1) IN DDCMP MAINTENANCE, THERE IS NO RETRANSMISSION: BA/CCO FOR A TRANSMIT OPERATION DOES NOT ASSURE SUCCESSFUL RECEPTION AT THE REMOTE END. THE SOFTWARE MUST KEEP A REPLY TIMER OF 3 SECONDS TO RETRANSMIT THE MESSAGE WHEN NO REPLY IS RECEIVED WITHIN THAT TIME 2) XXX MUST BE THE OFFSET FROM 173000 OF THE DMR11 BOOT CODE IN M9301-YJ/M9312 MK 2246 Figure 3-17 Down-Line Load Procedure to Remote Station BASE TABLE BASE ADDRESS TABLE ALLOCATION ; NAME O o - e TMo we TMo %e e T YT RRCV peee13 NRREP peopBl4 NRROV TMe pooe15 NRHFM TMe gp0B16 NRMTL “e goea17 NSREP go0020 NSROV TMo wo Wb we e RST pooP12 pPep21 NSHFM 000022 XUNDR 200023 CFAIL 000024 CTSCNT PooB25 CDLCNT NAKS RCVD - DATA BCC ERROR ** ___ (ALWAYS = 0060) (REASON = 8.) (REASON = 1.) {REASON = NAKS ARE SENT. NAKS SENT - BUFFER TEMP. UNAVAILABLE (REASON = NAKS SENT - HEADER BCC ERROR (REASON = 1,) ** NAKS SENT - DATA BCC ERROR (REASON = 2.) (REASON = 3.) NAKS RCVD - MSG HDR FORMAT (REASON = 17.) NAKS SENT - REP RESPONSE (REASON = SENT REPS RCVD - CUMUL REP RCVD. NAKS RCVD - REP RESPONSE - CUMUL REP NAKS RCVD - RCV OVERRUN (REASON = “e He o ~e H= XMIT -e == CALL = CTS FAILURE COUNT. = A CARRIER DETECT = RECEIVER STREAMING TIME-OUT COUNTER TOTAL NUMBER OF BYTES TRANSMITTED. INCOMPLETE SELECTION COUNTER NO REPLY TO SELECTION COUNTER pooo4e ICSEL wo NRSEL e we NE Wy N me N -e ~e ~e we -e NAKS SENT - RCV OVERRUN NAKS SENT - MSG HDR FORMAT SET UP COUNT. LOST COUNT (WHILE RECEIVING) INACTIVE COUNT. ¢INCLUDING RETRANSMISSION, 32 BIT COUNTER) TOTAL OF BYTES RECEIVED. #NOT INCLUDING DUPLICATE OR OUT OF SEQUENCE, 32 BIT COUNTER) Figure 3-18 DMRI11 Base Table Error Counters 3-33 3.) (REASON = 9.) (REASON = 17.) COUNT. FAILURE 9.) (REASON = 16.) NAKS RCVD - MSG TOO LONG UNDERRUN ** SENT. = o W REPS ppeB41 2.) IN DDCMP MAINTENANCE MODE e eo o e e RCBYT ERROR He = gpo@34 RCVD - HEADER BCC TM poe211 XMBYT NAKS RCVD - BUFFER TEMP UNAVAILABLE NAKS m NSDCE goo030 BEGINNING OF BASE TABLE DATA e 000010 STRCNT LIMIT = He e e NSNBF pooB27 INDEX POINTER UDPATE NO NSHCE RCVIDL UPDATE TABLE THESE IN-BOUND ERRORS ARE RECORDED BUT Poo0B6 oe0007 poBR26 (L K-> . voyovyo s NRNBF NRHCE TABLE BASE wg 0000083 PoooB4 BASE ~e UPLMT BASTBL Do UPINDX 2008021 000002 e 200000 e o 0 14 ** ** 8.) 3.7 MODEM CONTROL There are two levels of modem control available in the DMRI11. The first level is provided by the M 8203 hardware and the second is provided by the DMR 11 microcode. 3.7.1 Modem Control Implemented in M8203 3.7.1.1 Modem Ready Lockout of RTS - Bit 3 of line unit Register 13 is data mode (modem ready) or data set ready (Circuit EIA CC/CCITT-107). Unless modem ready is asserted by the modem, M8203 will not present request to send (Circuit EIA CA/CCITT-105) to the modem. 3.7.1.2 Half Duplex Mode - Bit 4 of line unit Register 13 is the half-duplex bit; if set, it indicates that the fine unit is set in the half-duplex mode. In half-duplex mode, there is hardware interlock to prevent the line unit from transmitting and receiving simultaneously. While the receiver is actively receiving or carrier detect is asserted, the data loaded into the transmit silo will not be loaded into the USYRT for transmission and therefore RTS will not be presented to the modem. Similarly, while the transmitter is transmitting, the receiver is disabled from receiving data. NOTE This hardware interlock will prevent the M8203 line unit from being used in half-duplex mode on a fullduplex modem, with the continuous carrier option installed. 3.7.2 Modem Control Implemented in DMR11 Microprogram 3.7.2.1 Auto-Answer - When the DMRI11 is installed on a switched line, Switch Pack E134 switch 9 should be placed in the OFF position. This enables the DMR 11 to monitor RI and DSR, utilizing a 20 second timer to answer and control incoming calls. With the switch in the ON (auto-answer disable) position, the DMR11 asserts DTR immediately following system initialization or Master Clear, allowing the DMRI11 to answer an incoming call. The call, however, is not terminated until the user program issues a Halt Request or the remote end terminates the call. 1. 2. NOTE The ON to OFF transition of RI starts the DMR11 20 second timer. For the auto-answer feature to be affective, the “Ring Indicator Constantly ON after Call’’ option on the modem must not be installed. Asserting DTR after Master Clear is required to maintain compatibility with DMC11. When the auto-answer feature is enabled, and when RI is detected, the DMR11 takes the appropriate action as described below: 1. Before Base In/Control In (Remote Load Detect Enabled) Remote load detect is enabled when the bootstrap password is not 377. When the DMRI11 detects the ON to OFF transition of RI, it starts a 20 second timer. If a valid Enter MOP message is not recieved before the timer expires, the DMR11 drops DTR and waits up to two seconds for DSR to clear before asserting DTR again for the next call. The number of call set up failures are counted in the CFAIL error counter. 3-34 NOTE If RI is not asserted by the modem on an incoming call and the modem sets DSR, the DMR11 starts the 20 second call set up timer. 2. Before Base In/Control In (Remote Load Detect Disabled) Remote load detect is disabled when the bootstrap password is 377. When the DMR11 detects RI, it drops DTR to disconnect the incoming call. 3. After Base In/Control In When the DMR11 detects RI, it asserts DTR and starts a 20 second timer. If the DMRI11 does not receive a valid DDCMP header and DSR before the timer expires, it drops DTR and waits up to two seconds for DSR to clear before asserting DTR again for the next call. The number of call set up failures are counted in the CFAIL error counter. 3.7.2.2 Data Set Ready Glitch - In ISTRT, ASTRT, Run, or Maintenance Mode, once the DMR11 has received data set ready (Circuit CC/107), any DSR drop is reported by the DMR11 to the user program via a Control Out/Disconnect Error. It is not a fatal error. When the DMR11 drops DTR on a call set up time out, the DSR drop is not reported by Control Out. 3.7.2.3 RTS - CTS Delay - Any time the DMR11 attempts to transmit by presenting RTS (Circuit CC/105) to the modem, it will wait up to two seconds for CTS (Circuit CB/106) to be returned. If the two second time out occurs, the DMR 1 will increment a CTS Fail Counter in its memory. if DMR11 is not in the Halt state, this counter will be updated to the Base Table in PDP-11 and VAX-11/780 memory. NOTE DMRI11 exits from the HALT state after the user program has issued Base In and Control In. 3.7.2.4 Loss of Carrier Detect - Whenever Carrier Detect (Circuit CF/109) is dropped by the modem for greater than 500 ms while the DMRI1 is still receiving, the carrier detect lost counter in DMR11 memory will be incremented. If DMR11 is not in the Halt state, then the error counter in the Base Table will also be updated. 3.7.2.5 Receiver Inactive Check - In ISTRT, ASTRT, Run, or Maintenance states, the following e In full-duplex mode, if a valid message header, including SOH, ENQ or DLE. has not been receiver inactive checks are made: e received in 20 seconds, a receiver inactive counter is incremented. In half-duplex mode, if the total selection interval time, before a valid DDCMP header 1S received, is about 20 seconds, the receiver inactive counter is incremented. 3.7.2.6 Modem Status Read During Input Command - This feature provides the user program with the option of reading (monitoring) modem status. Modem status is updated by the DMR11 to SEL 4 and BSEL 6 each time RDI is asserted in response to RQI. Refer to section 3.2.3.2 for details on this feature. 3-35 3.7.2.7 Data Terminal Ready Control - The DMR11 microcode controls the data terminal ready signal as follows: DTR is set when: 1. a. Master clear is performed, b. Auto-Answer (E134 switch 9 OFF) is enabled and the DMRI1 detects RI, or c. The user issues Control In. DTR is cleared when: 2. a. The system powers down, b. The user issues Halt Request, or c. The 20 second call set up timer expires. NOTE If the link is established (DSR asserted) and auto-answer is enabled, the DMR11 drops DTR 20 seconds after a Master Clear (provided that Base In/Control In are not issued). 3.8 DMRI11 DATA LINK FUNCTIONS The DMRI11 implements DDCMP and provides a number of functions to the user during what is referred to as a session. A session is defined as that period beginning immediately after the user assigns Base In and Control In and ending when the user issues a Halt Request or a fatal error occurs, forcing the DMRI11 to shut down. The functions that are provided during each of these sessions are listed below: 1. Creates an error-free data path. DMR 1 transfers data between protocol users over a physical link, while maintaining data integrity within some small undetected error probability. Transfers messages in proper sequence. Messages will be delivered from one user to the 11 may require the use of other in the same order as they are sent, even though the DMR retransmission for error recovery. Manages the characteristics of the channel. If the channel requires arbitration of transmis- sion requests, the DMR11 is responsible for that management. Interfaces to modem control signals. The DMRI11 interfaces with signals necessary for the operation of the physical channel. Accesses data in blocks consisting of byte quantities. The DMR11 accepts data in blocks consisting of 8-bit bytes. All 256 8-bit combinations are transmittable and transparent to DDCMP. However, the CRC-16 error detection polynomial used is most effective with blocks up to 4093 bytes long. 3-36 Provides restart or initialization notification. If the other end ofthe link resets or initializes. the DMR11 will notify the user. Provides start and stop control. The user controls the protocol and can start (or reinitialize), and stop (or halt) the operation of the DMRI11. Provides notification of channel error. When a persistent error is detected, the user is notified of such a condition. Such errors might be (a) a high bit error rate; (b) outages: (c) nonexistent: communications; or (d) modem failure. Provides a maintenance mode. The DMR11 creates a data envelope with bit error-detectiononly capability for use in diagnostic testing and system bootstrapping functions. NOTE In order to recover from the premature termination of a session, forcing DMRI11 to shut down, by a hardware or modem failure, the user should implement higher level protocols to ensure synchronization of the two communicating devices between sessions. Since the DMR11 or DDCMP guarantees these functions within each session only, it is the user’s responsibility to implement a higher level protocol in order to provide an additional level of error recovery, guaranteed delivery, and sequentiality. 3-37 CHAPTER 4 SERVICE 4.1 SCOPE This chapter provides information for servicing the DMR11. It includes the maintenance philosophy, maintenance functions, preventive maintenance, and corrective maintenance. The section on corrective maintenance contains brief descriptions of the diagnostics associated with the DMRI1. 4.2 MAINTENANCE PHILOSOPHY The field replaceable unit (FRU) for the DMRI11 is either a faulty module or cable. Training of field service personnelis directed to functional and application troubleshooting, using diagnostics, for fault isolation to the FRU. Spare parts for module repair are not stocked in the field. Typical applications of the DMR11 do not permit lengthy troubleshooting sessions and component troubleshooting/repair requires, at least, a 16-channel logic analyzer. CAUTION When inserting or removing the M8207-RA microprocessor module, be sure not to dislodge the priority plug or control read only memories (CROMs). Ensure that the CROM is seated firmly and in the proper socket; otherwise erratic operation of the DMRI11 may result. 4.3 MAINTENANCE FU\NCTIONS/MAINTENANCE MODES The maintenance functions are available to the DMR11 via the maintenance control and status register (CSR) (BSEL 1). Maintenance and system tests constitute the Maintenance Modes. 4.3.1 Maintenance Register (BSEL 1) This reglster contains the high byte of address 76XXXO0. A brief descr:ptlon of the CSR byteis providedin Chapter 3. The byte format and bit descriptions are providedin detailin this section. 15 14 13 12 RUN | MCLR | MICRO | STEP DIAG LU 11 LU LOOP 10 ROM OUT 9 ROM IN 8 STEP UP BSEL 1 BSEL 1 contains all maintenance functions, including Master Clear, and is not intended for normal user communications between the PDP-11 program and the microprocessor. These functions override all other control functions. All bits are read/write; only Master Clear is functional if the BSEL 1 Lock Out switch is set (refer to Chapter 2). Table 4-1 describes the bit functions of BSEL 1. 4.3.2 Maintenance Modes The DMR11 microprocessor can be tested by two basic modes: Maintenance and System Test (free-running). 4-1 The DMRI11 line unit can be tested by three basic modes: * Single Step Internal Maintenance, e System Test Internal Maintenance, and e External Maintenance. 4.3.2.1 Maintenance Mode - The Maintenance Mode can be invoked using selected bits of BSEL 1. These can be used to halt the microprocessor (clear bit 15), step the microprocessor (set bit 8), examine the current CROM location (assert bit 10 and examine SEL 6), and override the current CROM instruction with a different instruction and execute the new instruction (load SEL 6 with the new instruction, assert bits 8 and 9, then clear bit 8). NOTE 1. Be sure that BSEL 1 Lock Out BST Switch 1, E85 is ON to allow access to the maintenance bits in BSEL 1. 2. With the BST switch OFF, it is still possible to Master Clear the microprocessor by setting bit 14 of BSEL 1. 4.3.2.2 System Test - System Test Mode tests the functionality of the microprocessor and line unit running at full speed and utilizing the control ROM. NOTE Run Inhibit Switch 7, E28 must be ON to use this mode and ensure normal operating conditions. 4.3.2.3 Single Step Internal Maintenance Mode - This mode is selected by the user program setting LU Loop and clearing Run bits 11 and 15 of SEL 0. This mode allows for checking most of the line unit without disconnecting the M8203 from the modem or from the triaxial cable. Line unit signal D8 LPBKL is set to keep the transmitter output active, looping the output back at TTL levels to become the receiver input. Line unit Request to Send (RTS) and Data Terminal Ready (DTR) signals are held cleared. The clocking source is the D16 Step LU signal from the microprocessor which becomes D1 Step LU at the line unit. The user program generates the clock signal which sets Step Line Unit bit 12 of SEL 0. 4.3.2.4 System Test Internal Maintenance Mode - This mode is selected by the user program setting Line Unit Loop bit 11 and bit 15 (Run) of BSEL 1. This mode allows the program to perform an offline system test by free-running the DMR11 and checking the line unit without disconnecting the M 8203 from the modem or from the triaxial cable. The transmitter output is looped back at TTL level to become the receiver input. The clock source is the DMR11 maintenance clock which is 48K b/s. 4.3.2.5 FExternal Maintenance Mode - External Maintenance Mode is selected by the user program placing the DMR11 in normal running mode (bit 11 clear and bit 15 set) and terminating the cables with a test connector. 4-2 The M8203 options are configured as follows: 1. DMRI11-AA (for RS-232-C; RS-423-A) The modem must be disconnected and the H325 test connector must be attached to the BCO05D-25 cable. Data rate switches (switches 8, 9, and 10 of E39) select the clock rate. This clock signal is looped back in the H325 to simulate modem transmit and receive clocks. The data rate for this application must not exceed 56K b/s. Modem control signals are tested for proper level conversion and cable p‘aths. These signals are looped back in the H325 as shown in the signal flow of Figure 2-5E. 2. DMRII-AB (CCITT V.35/DDS) The modem must be disconnected and the H3250 test connector must be attached to the BC05Z-25 cable. Data rate switches (8, 9, and 10 of E39) select the clock rate. This clock signal is looped back in H3250 to simulate modem transmit and receive clocks. Modem control signals are tested for proper level conversion and cable paths. These signals are looped in the H3250 as shown in the signal flow of Figure 2-3B. 3. DMRI11-AC (for Integral Modem local use) The local link connections of the BC55A connector panel are disconnected at the local panel and the FDX switch on the BC55A connector panel is switched to half-duplex to accomplish the external loopback. CAUTION If DMRI11 is connected to another running DMR11, disconnect the cable at the BCS5A connector panel during diagnostic execution. Data rate switches (8, 9, and 10 of E39) select the clock rate. This data is looped back through the BC55A connector panel to test, transmit, and receive data. The data rate for this application must not be less than 50K b/s. 4. DMRI1-AE (for RS-422-A interface) The modem is disconnected and a H3251 test connector is attached to the BC55D-33 cable. Data rate switches (8, 9, and 10 of E39) select the clock rate. This signal 1s looped back through the H3251 to simulate modem transmit and receive clocks. Modem control signals are tested for proper level conversion and cable paths. These signals are looped in the H3251 as shown in the signal flow of Figure 2-5D. 4.3.3 Maintenance (LED) Indicators Six light emitting diodes (LEDs) are installed on the M8203 line unit to permit visual observation of certain conditions. Five of these pertain specifically to modem conditions. The remaining LED (D15) reflects operational conditions of the DMR11. Table 4-2 provides a description of each LED, while Figure 4-1 identifies the physical locations. 4-3 Table 4-1 BSEL 1 Bit Descriptions Bit Name Description 8 Step uP When set, it steps the microprocessor through one instruction (Step Microprocessor) 9 ROM In cycle which is typically composed of three, 60 ns pulses. The Run bit should be cleared before executing this control function. When set, it directs the contents of BSEL 6 and 7 as the next microinstruction to be executed by the microprocessor when Step uP is set. 10 I ROM Out When set, it modifies the source paths for BSEL 6 and 7 to contain the contents of the addressed CROM. If ROM Out and Step uP are set, then the content of the next CROM address will be output to BSEL 6 and 7. LU Loop When set, it connects the line unit’s serial line OUT, back to its (Line Unit Loop) serial line IN. This loop back is done at the TTL level before level conversion. When the LU Loop bit is set and the Run bit (bit 15) is cleared, the Step LU clock is the only one available for shifting data in or out. When the LU Loop bit is set and the Run bit is set, data is clocked at 48K b/s by the maintenance clock. If the LU Loop bit is cleared and the Run bit set, the loop back test connector is required. LU loop Run Clock Source Set Clear | Step LU(bit 12 via Pro gram Mode Single -Step Internal Maintenance Set Set Maintenance System Clock @ 48K b/s Test Internal Maintenance Clear Set 4-4 Maintenance External Clock determined by rate select SWs Maintenance Table 4-1 Bit Name BSEL 1 Bit Descriptions (Cont) Description NOTE The DMR11 must be set up in full-duplex mode to run in any loopback maintenance mode. For External Loopback Mode, cable test connectors H3235, H3250 or H3251, or modaule test connectors H3254 or H3255 are required. 12 Step LU With the Run bit cleared and bit 12 set, the transmitter shifts: (Step Line Receiver) when bit 12 is cleared, the receiver shifts. This control function is used in conjunction with LU Loop bit 11 to simulate transmit and receive clocks for line unit maintenance in Single Step Maintenance Mode. - 13 MICRO DIAG This bit, in addition to the position of Switch 10 on Switch Pack (Micro Diagnostics) E134, enables automatic execution of internal microdiagnostics. Refer to Table 2-11 for further conditioning information. 14 15 MCLR When bit 14 is set, MCLR initializes both the microprocessor (Master Clear) and the line unit. This bit is self clearing. The microprocessor clock is enabled and the Run bit is set, placing the DMR11 in the initialized state. Run Run controls the microprocessor clock: bit 15 is set by BUS initialization or Master Clear, which enables the micro- processor clock. Run can be cleared for maintenance by the Run Inhibit switch (E28). See D16 of the M8207-RA Print Set. The BST switch is provided to prevent Run from being cleared by a runaway microcode program when the microprocessor malfunctions. Further discussion of the Run Inhibit switch is contained in Chapter 2. 4.4 PREVENTIVE MAINTENANCE (PM) There is no specific DMR11 PM schedule. A general check of voltages and connections should be done when system PM is performed. After handling DMR 11 modules or cables, a complete checkout of the device, by running all diagnostics and, if possible, the interprocessor test, is required. Special care must be exercised for the following reasons: e The DMRII is susceptible to seating problems and ¢ CROM (control ROM) chips installed in sockets are easily dislodged during removal and replacement of the M8207-RA module or adjacent modules. The CROM chips may accidentally come in contact with the etch side of the adjacent module. 4.5 CORRECTIVE MAINTENANCE ON A PDP-11 PROCESSOR Since the FRU is either a module or cable, all corrective diagnosis should be directed towards isolating the failing FRU. DMRI11 diagnostics are designed to aid in the isolation process and should be run 45 Table 4-2 Maintenance Indicators Designation Name Description D10 Signal Quality A signal from the modem that indicates the presence or absence of the carrier. Usually, when this signal is ON it indicates the presence of the carrier and OFF indicates an absence of the carrier. D1l Carrier Indicates that the carrier is present at the receiver. D12 Receiver Data When ON, indicates that a steady stream of Is are D13 Transmit Data D14 Request to Send being received. When ON, indicates that a steady stream of Is are being transmitted. When ON, indicates that the USYRT is ready to start transmitting as soon as Clear to Send is detected. Heartbeat D15 At Master Clear time, this indicator is OFF. When the DMRI11 asserts the Run bit, this indicator will go ON and remain ON until the completion of Base In and Control In. Following Control In, this indicator will blink at the rate of five times per second until a Halt or fatal error condition occurs, at which time it will remain ON. This sequence is graphically represented in Figure 4-1. starting with the basic microprocessor test and continuing to the interprocessor test. The proper se~ quence of diagnostics is as follows: Diagnostic Description CZDMP* M 8207 Static Diagnostic | CZDMQ* M 8207 Static Diagnostic 2 CZDMR* M 8203 Static Diagnostic | CZDMS* M8203 Static Diagnostic 2 CZDMI* DMRI11 Functional Diagnostic ZITAD*/ZDMO** DMCI1 11/DMRI11 ITEP-OVERLAY Interprocessor Test 4.5.1 CZDMP*/CZDMQ* These diagnostics test the M8207-RA microprocessor in two parts and by using the diagnostic supervisor (DS). Through dialogue with the operator, the program allows modification of device parameters, such as the UNIBUS address, vector address, and processor type. *Indicates current revision level of diagnostics. 4-6 EXECUTION OF MICRODIAGNOSTICS g:?: O"C'/I Y IF ENABLED ON oFF ~ 200 ms I | I Ly yys |-——— 5 TIMES/SECOND ————I I MASTER RUN BIT CLEAR ASSERTED BLINK RATE (APPROXIMATE) REMAINS ON IF HALT OR FATAL ERROR HEARTBEAT WAVEFORM MK-2189 SIGNAL QUALITY (D10) HEARTBEAT (D15) CARRIER (D11) REQUEST TO SEND (D14) RECEIVER DATA (D12) l — TRANSMIT DATA (D13) MAINTENANCE LED'S (TN e T L N—] jfli r Nn—1 N— T MK-2188 Figure 4-1 M8203 Maintenance LED Locations/Heartbeat Waveform This program is compatible with the stand-alone diagnostic supervisor. It must be loaded co-resident with the DS. or be previously combined with the DS and loaded as a single file. In either case, the combined program will not exceed 16K of memory. Refer to Appendix C for details on the diagnostic SUPETVISOT. 4-7 The total time required to run M8207 static tests is approximately from 30 seconds to 2 minutes per pass, depending on the CPU type. CZDMP* and CZDMQ* are compatible with XXDP+, ACT/SLIDE. and APT. XXDP+ and ACT/SLIDE may be run in dump or chain modes. APT can be run in program or script modes. Memory management is not used in this program and, if installed, it is disabled. If parity memory is installed, memory parity traps are disabled. An error log retains the number of errors which have occurred on each device under test since the last start or restart command. The log may be printed by using the print command. A summary of the tests performed are listed in Tables 4-3 and 4-4. All tests support the DMCl1, KMCl1I-A, B, and DMRI11. However, some tests listed in Table 4-4 are not executed on certain devices. Refer to Table 4-4 for these exceptions. For greater detail, refer to the diagnostic listings. Table 4-3 CZDMP* Diagnostic Summary Test Number Description | Verify that referencing UNIBUS device registers does not cause a T/O trap. 2 3 4-8 9 10 11 12 K Verify that Run can be cleared. UNIBUS register word, dual addressing test Control status register write/read tests Port 4 register write/read test Port 6 register write/read test UNIBUS register byte, dual addressing test Maintenance instruction register test Microprocessor test 14-27 28 Microprocessor IBUS/IBUS* register write/read tests Microprocessor IBUS/IBUS* dual address test 29 Microprocessor BR register test 30 31 32,33 34,35 Scratchpad test Scratchpad dual addressing test Interrupt tests Priority interrupt tests 36-38 NPR tests 39,40 Test of extended address (EA) bits 16 and 17 41,42 NPR non-existent memory test 43 44 45-76 NPR test ALU C-bit test ALU tests 4.5.2 CZDMR*/CZDMS* These diagnostics perform static tests of all M8203 logic. These include - line unit register addressing, USYRT addressing, static bit interaction and read/write logic tests, basic transmitter, receiver sequencing and data buffering, and static operations in character and bit-stuffing modes. In addition, data messages are sent on the line unit at TTL level, or through an external test connector with a specific modem interface selected. Static logic tests provide troubleshooting capabilities such as tight scope loops, switch options, and the . [P R G A Al e~ abilily to lock on intermiiient errors. Additionai test of the smallest field replaceable unit. 4-8 S ——rre. provi + . | P tn Familitat | 28] Uit 13G1ation 1o rachiiaid Ffip.acen.e H Table 4-4 DZDMQ* Diagnostic Summary DMC 11 |[KMC11-A} KMC11 |DMR Test -B Number Description 11 Verify that referencing UNIBUS device registers 1 does not cause a timeout. 2 34 BR right shift test IOP CRAM write/read test S S IOP CRAM dual addressing test 9 10 11 12-24 S S S S S IOP MAR test (4K Main Memory) IOP (CRAM) ODT bits test CRAM tests of Jump(i) CRAM tests of Jump(i) 26 S S 5 6,7 8 IOP main memory test IOP main memory dualaddressing test S 4K Main memory page dual address test S S 27,28 S S 35 36 S S S S S S S S S S S S S 25 S S 29 30 31 32 33 34 37 38 39 40 41 42 43 S Jump Field, page test Jump test S S S S Z bit test C bit test Program clock bit test Force Power Fail test Microprocessor noise test NODST instruction test Extended CRAM test (M8206 only) Microcode test (M8206 only) Negative address test Byte addressing test PC register test Branch Field H test Scratchpad 0 (SPO) selection test MOV INST H signal test Master Clear test S = Test Skipped These programs conform to the stand-alone version of the diagnostic supervisor and are compatible with ACT, APT. XXDP+, and SLIDE. Through dialogue with the operator, the programs permit modifications of device parameters such as the UNIBUS address, vector addresses, and device priority. The operator can specify particular tests to be run and a variety of looping, running, and reporting modes. Refer to Appendix C for details on the diagnostic supervisor. Device errors are reported as they occur. The report includes the test number and error description, good and bad test data, and applicable device register contents. A summary of the tests performed are listed in Tables 4-5 and 4-6. For greater detail, refer to the diagnostic listings. 4.5.3 CZDMI* The CZDMI* diagnostic performs testing on the DMR11 option in a functional manner to verify 1ts proper operation under microcode controlled use of the DDCMP. This includes a ROM CRC/CCITT check, microdiagnostis, command utilization, error generation, interrupt testing, and interrupt driven exercising. CZDMR* Diagnostic Summary Description Microprocessor CSR addressing test (SEL 0) Inbus/Outbus register 14 initialization test Inbus/Outbus register 14 read/write bit test Register 14 Master Clear test Register 14 UNIBUS reset (INIT) test Line unit false selection test Inbus register Master Clear test Register 10-17 addressing test Register 11 read/write bit test Register 12 read/write bit test Register 13 read/write bit test — b bAEWWWWWLWLWWLWWUWNNNNN N = OOV EWN— OO0~ £ 9 Lo N OV ~-1\WV £ b o Dttt ot bt b et b et WK _— O 00~ Test Number ONWV BN — Table 4-5 Register 17 read/write bit test Maintenance clock bit test Extended register Master Clear test Extended register addressing test Registers 15, 16/AX2-15, AX2-16 read/write bit test AXO0-15, AX0-16 read/write bit test AXI1-15, AX1-16 read/write bit test AX3-15, AX3-16 read/write bit test Register 17 AX2-16 read/write, Master Clear test Transmitter buffer data test Transmitter buffer sequencing test TX MSG timing test, character mode with CRC TX MSG timing test, bit mode with CRC TX MSG timing test, character mode with no CRC TX UNDERRUN set and clear test, character mode TX character length timing test, character mode with CRC TX character length timing test, bit mode with CRC TXDATA bit test, character mode with no CRC USYRT RCV MSG test, character mode with CRC USYRT RCV MSQG test, bit mode with CRC USYRT RCV MSQG test, character mode with no CRC USYRT RCV MSG test, bit mode with no CRC Silo-disabled transmitter load test Silo-disabled MSG test, bit mode with no CRC RCYV buffer test, character mode with CRC RCV character length timing test, character mode with no CRC RCYV character length timing test, bit mode with no CRC TX UNDERRUN error, idle marking character mode with no CRC MSG termination with Go Ahead (GA) characters. bit mode with no CRC Idle SYNC test, character mode STRIP SYNC test This functional test provides troubleshooting capabilities such as tight scope loops, switch options, and the ability to lock on intermittant errors. Additionally this program conforms to the standalone version of ihe diagnostic supervisor and is compatibie with APT, ACT, XXDPT, and SLIDE. Refer to Y Appendix C for details on the diagnostic supervisor. 4-10 TIIT Table 4-6 Test Number Description 1 Bit stuffing test 3 Abort sequence test CZDMS* Diagnostic Summary RCV OVERRUN error, set and clear test 2 4 Abort and idle flags test 6 7 RCYV disable test Assembled bit count test TX underrun error, idle abort characters, bit mode 5 Secondary station address bit test All parties address bit (RDALL) test 8 9 Insert error bit (IERR) test, character mode with no CRC 10 Switch PACK printout and test Register AX3-15 printout CRC generation test CRC error detection test VRC parity generation test VRC error detection test 11 12 13 14 15 16 Integral modem interface test, character mode with CRC V.35 modem interface test, character mode with CRC 17 18 RS-232-C and RS-423-A modem interface test, character mode with CRC RS-422-A modem interface test, character mode with CRC 19 20 Half-duplex bit (HALF DUPX) test 21 Half-duplex RCV disabled test, with silos disabled 22 Interaction of modem control bits 23 Data test, bit mode with no error detection Data test, character mode with no error detection 24 25 Data test, bit mode with CRC-CCITT-1 error detection Data test, bit mode with CRC-CCITT-0 error detection Data test, character mode with CRC-16 error detection Data test, character mode with ODD VRC error detection Data test, character mode with EVEN VRC error detection Contiguous ones in secondary station address mode, bit mode 26 27 28 29 30 31 DDCMP MSG test, character mode 32 as Through dialogue with the operator, the program permits modification of device parameters such tests r particula specify can operator The priority. device and , the UNIBUS address, vector addresses to be run and a variety of looping, running, and reporting modes. A summary of the tests performed are listed in Table 4-7. For greater detail, refer to the diagnostics listings. DMRI11 Microdiagnostic Error Reporting 4.5.4 When the microdiagnostic is run on the DMRI11 (during power-up/initialize), status indications take the following form (see table below): 1. contains Upon completion of the microdiagnostic, if BSEL 1 has the Run bit set and BSELed3 healthy. consider is 11 DMR the and lly successfu on completi 2003, then the test has run to 4-11 2. After attempting the microdiagnostic, if BSEL 1 has the Run bit set and BSEL 3 equals 100g, then the microdiagnostic tests were inhibited. 3. A failure in the microprocessor module is indicated by no Run bit in BSEL 1 and a 0013 (or any other indication other than 2003, 100g, or 002g)in BSEL 3 after initiation of the micro- diagnostic. 4. - The line unit is the suspect module when no Run bit is set in BSEL 1 and a 0023 is present in BSEL 3 after the microdiagnostic. BSEL 1 BSEL 3 Indication Run bit Run bit no Run bit 200g 100g 001g or XXX Test complete Test inhibited M8207 test failed no Run bit 002g M8203 test failed CZDMI* Diagnostic Summary Description Verify all CSR addresses ROM CRC/CCITT check Master Clear/Microdiagnostics Initialize /Base In DMR Commands Control In commands Modem test ‘ No Buffer test NXM (Base In, BA/CC IN RCV & XMT) Time Out MSG Too Long oW — O el e e Test Number OO0~ AW — Table 4-7 Procedure Errors Free Running Flag Mode Extended Addressing Interrupt/Base In Resume (124 bytes to 2K bytes depending on memory availability) Interrupt Driven Exercise (64 Buffers — 16 bytes to 256 bytes depending on memory availability) Interrupt Large Message (2K bytes to 16K bytes depending on memory availability) Interrupt Maintenance Mode (2K bytes to 16K bytes depending on memory avail- 15-16 i7 18 19 ability) 4.5.5 ZDMO** - DMCI11/ DMRI11 Overlay for Interprocessor Test Program (ITEP) This test is used to isolate various interconnect problems between systems. Through a series of tests, failures are identified in level converters, cables and connections, modems, lines between modems, and modem incompatibilities. ITEP has been useful in identifying new or modified software problems In this role, ITEP is used to ienlate fkn !nnpr‘jora Fram thae lllllllll IRlAYTQl v llUlll LIIV cta o'yo;\.«ul enfturar [4 DURLYY ul\i Tunir\q"\r F ITED k1L A X l—tl wrirme 181104 tha cuctarm cnfturnr o chAanld Lllw OJOC\IIII IVILYYAL W J1IVUIJ run. ITEP provides a controlled environment for test purposes often unavailable in operating systems. 4-12 ITEP can be used for loop testing, providing the ability to incrementally test larger (or smaller) segments of the communications link. For instance, if a failure occurs when running in Modem Analog Loop Mode rather than in Cable Loop Mode (with an H325 connector), the probability ofa modem or modem option fault is increased. ITEP is more of a confidence test than a true diagnostic, and provides a GO/NO-GO indication ofthe integrity of the communications link. ITEP is often used for installation acceptance, as well as confirmation of a corrective action. An ITEP feature not provided in any of the stand-alone diagnostics is the capability of checking out the remote load detect (RLD). The DMC11/DMRI1 overlay for the Interprocessor Test program is designed to verify the proper operation of a complete communications link (DMC11 or DMRI11) from one PDP-11 system to another, or to a communications test center. The program must be used in conjunction with the Interprocessor Test Monitor program (ZITAD*) on a PDP-11 system. Two tests for the DMRI11 are selectable by the parameter locations provided in ITEP. To aid in Link Test analysis, refer to Table 4-8. TEST 1 is a link test which provides a GO/NO-GO test (a confidence check) on the communications link (could be either half-duplex or full-duplex). TEST 2 is a bootstrap test which checks the ability of a DMR11 to boot another DMRI1 using maintenance operation protocol (MOP) messages. The bootstrap test requires an M9301-YJ/M9312 (UNIBUS terminator with bootstrap) or equivalent boot module at one station. The RLD feature of the DMR11 is checked out: the host sends an Enter MOP message to a remote station to initialize the entire system and cause program control to be transferred to a boot ROM program (or in true on-line application, a secondary boot program) to be down-line loaded and evenually execute that program. Only the down-line load feature of the DMRI11 can be checked: a remote station sends a program Request MOP Message and the host, with its DMR11 running ITEP, will down-line load a special program to the remote station, which prints out a message indicating a successful BOOT has been completed. NOTE 1. Refer to Appendix E for detailed operating procedures for bootstrap testing under the ITEP program. 2. 4.5.6 Refer to the diagnostic listings for detailed operating procedures of CZDMP*, CZDMQ*, CZDMR*, CZDMS*, and CZDMI*. DEC/X11 DMC11 Module The DEC/X11 DMC11 module, DMC*, is designed to exercise up to and including two consecutively addressed DMR11 synchronous interfaces. One pass of the DMC* module consists of transmitting and receiving seven buffers of 100 characters, 100 times for each selected device. It is recommended that bit 0 of the DMC* Switch Register 1 (SR1) be set to | and that a test connector be installed (H325, H3250, or H3251 for M8203) when running DEC/X11 (as indicated in the checkout procedures in Chapter 2). Installing the test connector and setting bit 0 of SR1 allows the DMC11/DMRI11 to run in External Loopback Mode and, therefore, generate more activity on the UNIBUS. 4-13 Table 4-8 . Type of Message Start Message Code Bits DDCMP Message Decode for DMRI11** Count Bits 7-0 Class 00000101 | 00000110 0 5 Hex ASCI11 | ENQ 0 6 ACK 00000101 | 00000111 Start Acknowledge- | Bits 0 7 0 5 Hex ment BEL ASCI11 | ENQ 00000101 | 00000001 Bits Acknowledgement vi-v Data Message 0 5 Hex ASCI1 | ENQ glzhg“s Count S 1 S 0 1 SOH Bits 100000071 | No. of Char.| S Hex 8 1 ASCI11 | SOH ” ” 00000101 | 00000010 Negative Acknow- Bits 0 2 0 5 Hex ledgement BCC STX ASCI11 | ENQ Header Error 00000101 | 00000010 Negative Acknow- Bits 0 2 0 5 Hex ledgement BCC STX ENQ | ASC11 Error Data 00000101 | 00000010 Negative Acknow- Bits 0o 2 0 5 Hex ledgement ButfSTX ASCI11 | ENQ fer Unavailable 00000010 | 00000101 Bits Negative Acknow0o 2 0 5 ledgement Recei- | Hex STX ASCI11 | ENQ ver Overrun 00000101 | 00000010 Negative Acknow- Bits 0 2 0 5§ Hex ledgement MesSTX ENQ | ASCI1 sage Too Long 00000101 | 00000011 Negative Acknow- Bits 0o 2 0 5§ ledgement Header | Hex STX ENQ ASC11 Format Error *Assumes that both S and Q are asserted Response 00000000 Sequence 00000000 To Point 00000001 1000000 C 0 00000000 0O 0 00000000 00 00000001 0 1 cC o0 @ @ Q000000 * C 0 * @ Q]No. of Char. 00 NUL NUL > » 0O 0 NUL 0 | SOH Msg. Revd. ” QJ[000001 * ] * A S Q000010 *C 2 * B S QJ001000 * C 8 * H S QJ001001 * C 9 S S S * ] Q010000 * D O * p Q[01000l * D 1 * Q SOH 00000001 ” ” ” ” ’ ”? ” ” " > ” Q7 NUL 0 1 SOH 00000000 ” S 00 NUL No. Last Good Q7 S Address Point Q Bit 13-8 1 000000 ” 7 ” ” ” ” ’ ”? No. Msg. Sent 00000001 ” 0 1 00000000 0O O NUL 00000000 00 NUL 00000000 0 0 NUL 00000000 (V) NUL 00000000 00 NUL 00000000 0 0 NUL 00000001 0 1 SOH 00000001 0o | SOH 00000001 o 1 SOH 00000001 0 1 ” SOH SOH 00000001 0o 1 SOH 00000001 0 1 SOH Siv Table 4-8 DDCMP Message Decode for DMRI1** (Cont) Count Bits 7-0 Type of Message Code Class Reply Message Bits 00000101 | 00000011 Negative Acknow- ledgement Reply Response Maintenance Message 0 5 Hex ASC11 | ENQ Bits 0 3 ETX 00000101 | 00000010 0 2 0O S5 Hex STX ASCI11 | ENQ 10010000 | No. of Char. Bits ” 9 0 Hex ASCI11 | DLE * Assumes that both S and Q are asserted Flag | count Address Point to Point % B'g Bit 13-8 Response Sequence Q00000000 00000000 No. Last 00000001 * C 0 (@ 0 0 NUL No. Last Good ! > 00000000 0 1 SOH v ” 00000000. 0 0 NUL 0 0 NUL 00000000 0 0 NUL 0 1 SOH 00000001 0 1 SOH S S Q000011 {1 * C 3 C 1 |No. of Char. ” v Msg. Revd Msg. Sent 00000001 External loopback connector options are: DMRI11-AA DMRii-AB - H325 or H3251 H3250 DMRII-AE - H3251 DMRI11-AC - HDX switch selected on the BC55A panel implements turnaround Speed is selected by switches 8, 9, and 10 on E39, (refer to Table 2-9). 4.5.7 Soft Error Reports Under DEC/X11 Soft errors indicate errors which occurred causing a message retransmission. A cumulative count of soft errors is kept in DMR11 random access memory (RAM) memory. The RAM memory is written to PDP-11 memory (beginning at the assigned base address) whenever a fatal DMRI11 error occurs at the end of each pass. DEC/X11 checks the error counters in the Base Table at the end of each pass. If any errors are counted, they are reported as soft errors. The soft error report may be used in the isolation of certain DMR11 failures from UNIBUS loading or data late problems. The DMR has no data late bit or capabilities for detecting the fact that it did not obtain Bus mastership in time to service the synchronous line. The DMRI1 sees such a condition as an error in the synchronous data stream (a BCC error transmitter underrun or receiver overrun) and DDCMP causes the message to be retransmitted. This occurrence causes incrementation of the cumulative error counters in DMR11 RAM memory. A process of elimination must be used to determine whether soft errors (BCC) are caused by BUS latency or failing DMRI11 hardware. Typically, the DMR11 should show no errors when running in a local loopback mode. This is nor- mally a noise-free circuit. Therefore, any soft error reports should be examined and the cause isolated. If soft errors are reported while running a DMRI11 on a fully loaded system (other devices being exercised simultaneously), they may be due to Bus latency. This may be verified by running only the DMC* DEC/X11 module with only one DMR11 enabled. If the soft errors cease, a latency condition is indicated. If soft errors persist while running only the DMC* DEC/X11 module, the DMRI1 should be run. The problem could be a faulty DMRI11 or cable. device diagnostics SR1 (bit 0) may be used in the isolation process. If bit 0 is set, DEC/X11 does not set line unit loopback but it uses an external turnaround. By running with bit O clear, a TTL loopback is performed, eliminating the possibility of the cable/turnaround connector being faulty. With the M8203, bit 0 clear eliminates the level converters and the Integral Modem. The bit rate selected is 48K b/s using the maintenance clock. 4.5.8 Examination of DMR11 Internal Components The following are some examples for examining DMR 11 memory and scratchpad registers. 4-16 Example 1: Examine DMR11 Memory Procedures Comments 1. Load OgSELO :To clear Run bit and stop the 2. Load 010XXXgtoSEL 6 :Microinstruction 3. O Load 1400gto SEL :Set ROM In and Step uP bits 4. Load 055224gto SEL 6 :Load microinstruction to SEL6 to read :memory content pointed to by MAR to ;MICTOProcessor :is loaded into SEL 0 where XXX is an -eight bit memory address which is :loaded into MAR :SEL4. MAR is incremen;ed. 5. Load 1400gto SEL 0 :Set ROM 1In and Step uP bits 6. Examine BSEL 4 low byte for memory -BSEL 4 contains content of memory :location under examination. content 7. GotoStepS5for examination of consecutive memory locations Example 2: Examine DMR11 Scratchpad Registers Procedures Comments I. Load SEL 0 with Og :To clear Run bit 2. Load SEL 6 with . :SEL 6 is loaded with microinstruc:tions, where XX is 0-17, Scratchpad :Register content of SP is loaded into 0606XXg :the Branch Register. 3. Load SEL 0 with 1400g :Set ROM In and Step pp bits the micro;processor. 0612243 ‘Load microinstruction, where content :0f SPX (from BR) is loaded into BSEL 5. Load SEL 0 with 14003 :Set ROM 1In and Step pP bits. 6. Examine BSEL4 for :BSEL 4 contains contents of scratchpad 4, [Load SEL 6 with 4. content of SPX 4-17 Example 3: DMR11 Base Table Dump Comments Procedures 1. Load 43g to BSEL 0 To perform an RQI for Base I type input. 2. Examine BSEL O for bit 7 (RDYI) set. To indicate the microprocessors release ofthe port. Load 10003 to SEL 4 Giving base address to microprocessor. Load 0 to SEL 6 Clearing high order address bits and Resume bit. Load 203g to BSEL 0 To relinquish port back to microprocessor. Load 423 to BSEL 0 To force a Halt Function with RQI. Examine BSEL 0O for bit To indicate the microprocessors release of the port. 7 (RDI) set. Load 202g to BSEL 0 To relinquish port back to microprocessor. Examine 128 memory To see counters, buffers, and other Base Table data. (Refer to the DMR 11 Base Table layout of Figure 4-2.) locations starting at 1000 to see Base Table NOTE This procedure provides a Base Table dump from a DMRI11 in the DDCMP Halt state. If the DMR11 is in the DDCMP Run state and a Base Table dump is desired, only perform steps 6 through 9. 4.6 CORRECTIVE MAINTENANCE ON A VAX-11/780 Since the FRU is either a module or cable, all corrective diagnosis should be directed to isolating the faulty FRU. DMR11 diagnostics are designed to aid in the isolation process and should be run starting with the basic microprocessor test. The proper diagnostics sequence is as follows. Diagnostic Description EVDXA REV ** COMM Microprocessor Repair Level Diagnostics EVDMA REV ** M8203 Repair Level Diagnostics EVDCA VAX Synchronous Link Level 2 Diagnostics REV ** 4-18 4.6.1 EVDXA COMM Microprocessor Repair Level Diagnostics This diagnostic performs tests on the M8207-RA microprocessor. It includes device initialization, register and RAM addressing, READ/WRITE testing, interrupt generation and priority, NPR operNBUS* ation and addressing, ALU functions and the microprocessor instruction set, and INBUS/IMode by nce Maintena in tests the of many and OUTBUS/OUTBUS* testing. This program performs VAX at run be will program This . sequences n stepping the microprocessor through various instructio Level 3, which is a stand-alone repair level. 4-19 BASE TABLE ADDRESS BASE TABLE ALLOCATION ; NAME ’ Poo0O17 NSREP 000020 PP0B21 NSROV NSHFM Poea22 XUNDR pooo23 CFAIL 000024 CTSCNT 2000825 CDLCNT RCVIDL 0oeB27 STRCNT 000030 XMBYT RCBYT PO0040 poeG4l W Ws e W wme DD e TEMP HEADER BCC NAKS RCVD - DATA BCC UNAVAILABLE ERROR ERROR IN DDCMP MAINTENANCE MODE we we WO poPB34 WE WP W P0PB26 BUFFER - e TMo NRMTL D DD 000216 DD NRROV NRHFM g NRREP peool4 200015 We p00B13 wms RRCV - **k —__ pthae ke RST pPoo12 RCVD RCVD NO e Pogo11 NAKS NAKS NAKS ERRORS ARE ARE NAKS SENT - BUFFER TEMP. SENT - HEADER BCC NAKS SENT - DATA REPS SENT - CUMUL REP SENT. REPS RCVD - CUMUL REP RCVD. NAKS RCVD - REP NAKS RCVD - RCV OVERRUN NAKS RCVD - MSG HDR NAKS RCVD - MSG TOO SENT - REP NAKS SENT - RCV OVERRUN NAKS SENT - MSG (REASON = 8.) = 1.) (REASON = 2.) BUT (REASON = (REASON = 1,) ** (REASON = 2,) ** (REASON = 3.) (REASON = 9.) FORMAT (REASON = 17.) LONG (REASON = 16.) RESPONSE (REASON = 3.) (REASON = 9,) ** (REASON = 17.) ** UNDERRUN SET BCC ERROR RESPONSE XMIT CALL CTS CARRIER RECEIVER STREAMING TIME-OUT COUNTER HDR FORMAT COUNT. FAILURE COUNT. COUNT. FAILURE DETECT LOST COUNT RECEIVING) INACTIVE TOTAL NUMBER OF COUNT. BYTES TRANSMITTED. tINCLUDING RETRANSMISSION, 32 BIT COUNTER) TOTAL OF BYTES RECEIVED. #NOT INCLUDING DUPLICATE OR OUT OF SEQUENCE, 32 BIT COUNTER) INCOMPLETE NO REPLY Figure 4-2 SELECTION TO @208) (REASON UNAVAILABLE ERROR NAKS (WHILE = SENT. NAKS UP (ALWAYS THESE RECORDED th gk e NSDCE DATA M 000010 BEGINNING A NSNBF NSHCE POINTER LIMIT TABLE IN-BOUND W goooe6 o00087 INDEX UDPATE OF BASE 3 NRDCE UPDATE TABLE Wtk 200005 NRNBF TABLE BASE Sh NRHCE BASE s 0000063 poP004 Sk gk 3k 020002 UPLMT BASTBL Wi UPINDX Hee= o= ; po0000 po0001 COUNTER SELECTION COUNTER DMRI11 Base Table Layout (Sheet | of 4) 4-20 8.) ** BASE TABLE ADDRESS BASE TABLE ALLOCATION : NAME pepB42 ;S R fi HIGHEST MSG N A T X ;S ;S ;S ;S : S T EMPX XEC XBQ ;S ;S TRANSMIT END TRANSMIT BEGINNING REQ RBQ ;S ;S RECEIVE END goBOB53 RECEIVE BEGINNING eoee54 NREAS ;$ LATEST peee43 poeB44 Po0045 gpoo46 0geea7 Po0250 pgee51 PoeB52 TEMPX A - NEXT T X —-- SUCCESSFULLY RECEIVED HIGHEST MSG TRANSMITTED HIGHEST MSG ACKNOWLEDGED N MSG TO TRANSMIT LAST MSG TO COMPLETE TRANSMISSION CURRENT MSG BEING TRANSMITTED -- NAK OF OF QUEUE OF QUEUE QUEUE OF QUEUE REASON 0@BB55 PRETIM ;$ PROGRAMMABLE REP/SELECT-TIMER PRESET VALUE Po0O56 RSTIM ;$ ISTRT/ASTRT/REP/SELECT-TIMER epee5s57 TIMER ;$ ACTIVE gooP60 THIL TIME COMPARE LEVEL COUNTER THRESHOLD LEVEL TH1 ;S ggoeel ;S THRESHOLD COUNT - 'NAK' 'NAK' RCVD RCVD P00062 TH2L pP0oOB63 TH2 ;S THRESHOLD LEVEL — : S THRESHOLD COUNT - 'NAK' 'NAK' SEND EXCEPT NO BUF SEND EXCEPT NO BUF peoo64d TH23L ;S THRESHOLD LEVEL PoOO6S TH3 : S THRESHOLD COUNT - 'REP' 'REP' SENT SENT poo066 TH4L ;S THRESHOLD LEVEL - 'NO-BUF' 000067 TH4 : S THRESHOLD COUNT - 'NO-BUF' pooe70 IM.SP ;S IMAGE OF SP.@4 i$ S ;S iS i$ IMAGE OF SP.@5 IMAGE OF SP.87 IMAGE OF SrP.16 IMAGE OF SP.11 IMAGE IMAGE OF OF SP. IMAGE OF MODEM ;S i$ Figure 4-2 SP.13 AVAILABLE AVAILABLE ISP.XMS) ¢SP.RCS) ISP.PST) ¢SP.XFL) ¢SP.GBL) ¢SP.RFL) SP.TFL) STATUS REGISTER DMRI11 Base Table Layout (Sheet 2 of 4) 4-21 BASE TABLE ADDRESS BASE TABLE ALLOCATION ; NAME p00106 gp@l164 g0gl1@ XBF@ XBF1 XBF2 gPel14 XBF3 pP@l28 XBF4 ;$ XBF@: (BSEL 4) :S S IBSEL 7) (BSEL 6) ;S (BSEL 5) ;$ XBFl: :$ ;S i $ (BSEL ¢BSEL (BSEL ¢BSEL :$ XBF2: ;S ;S ;S (BSEL 4) $BSEL 5) (BSEL 7) ({BSEL 6) ;$ XBF3: (BSEL 4) 4) 5) 7) 6) ;S ;S : S $BSEL 5) (BSEL 7) IBSEL 6) ;$ XBF4: (BSEL 4) ;S ;S (BSEL 7) $BSEL 6) : S ¢BSEL 5) gepP124 XBFS ;$ XBFS: (BSEL 4) : S ;S :S ¢BSEL 5) (BSEL 7) ¢BSEL 6) geP130@ XBF6 ;$ XBF6: . ) (BSEL 4) #BSEL 5) gP@134 XBF7 ;S : S (BSEL 7) ¢BSEL 6) ;$ XBF7: (BSEL 4) ;S (BSEL 7) ;S :S Figure 4-2 ¢BSEL 5) (BSEL 6) DMRI11 Base Table Layout (Sheet 3 of 4) 4-22 BASE TABLE BASE TABLE ALLOCATION ADDRESS — RBFO X o) ] \b Ib | Y () = g00140 $ RBF@: (BSEL 4) $ (BSEL 6) $ $ $ RBF1l: (BSEL 4) ;S ¢BSEL 5) ;S ¢BSEL 6) ;$ RBF2: (BSEL 4) ;8 ;S (BSEL 7) (BSEL 6) (BSEL 7) ;S @@@158 gP@154 RBF2 RBF3 ;S ) :S RBF4 RBF5S gPP178 RBF6 $ $ RBF7 4.6.2 ({BSEL 5) (BSEL 7) ¢BSEL 6) (BSEL 4) ;$ RBF6: ;S (BSEL 4) (BSEL 5) : 8 ¢BSEL 6) $ RBF7: $ $ $ Figure 4-2 (BSEL 6) ;% RBF5: ;S :$ ;S :$ gP@174 ¢BSEL 5) (BSEL 7) $ RBF4: (BSEL 4) $ g@r164 (BSEL 5) ;$ RBF3: (BSEL 4) ;S gpP168 (BSEL 5) ¢BSEL .7) ¢BSEL 5) (BSEL 7) (BSEL 6) (BSEL 7) (BSEL 4) ¢BSEL 5) (BSEL 7) ¢BSEL 6) DMRI1 Base Table Layout (Sheet 4 of 4) EVDMA Repair Level Diagnostics action and read/write This diagnostic performs register and USYRT addressing tests, static bit-inter on in character and bitlogic tests, basic transmitter and receiver sequencing tests, and static operati stuffing modes tests. This program performs many of the tests in Internal Loopback Mode using the 4-23 USYRT maintenance bit and the line unit loopback features. In external loopback mode it uses a turnaround connector. This program is implemented as a separate VAX diagnostic, which runs at Level 3. 4.6.3 EVDCA REV** VAX-11/780 Synchronous Link Level Two Diagnostics The VAX network diagnosticis intended to provnde a means to verify a communications link with VAX-11/780 hardware, and to provide a VAX exerciser for the DUP11, DMCI11, DMRI11, and future synchronous communications options on a link. The diagnostic runs at Level 2, which will eventually support either VMS or stand-alone operation. The DMC11/DMRI1 tests allow operation with internal or external data loopback and will be able to communicate with another VAX-11/780, or a PDP11 node running Data Communication Link Test-11/780. The PDP-11. DCLT programs will provide Field Service with a standalone tool to be used to maintain communications equipment by providing the test coverage necessary to isolate failures to the computer equipment, the communications line, or the modem. The DMRI11 can be run using this diagnostic, in DMC11 compatibility mode only, using the VMS DMC-11 driver. These will all run under the VAX supervisor. 4.6.4 Examination of DMRI11 Internal Components Example 1: Examine DMR11 memory Procedures Comments 1. Load 0 SEL O (to clear Run bit and stop the microprocessor). Done with “D/W” command to reference “word” rather than a “Longword” deposit. To specify the DMR address, prefix the floating address with 040043 to assemble the 32-bit physical address and then convert to HEX (that s, address 760100g becomes 040047601005, which is 2013E040;¢). This procedure assumes the DMRI11 to be installed on UBA 0 of the VAX. 2. Load 10XX6 to SEL 6 using word command reference. Microinstruction is loaded into SEL 6 where XX is an eight bit memory address which is loaded into MAR. 3. Load 30015to SEL O using word command reference. Set ROM In and Step uP bits. 4. Load 5A94¢to SEL 6 Load microinstruction to SEL 6 to read memory content using word command reference. pointed to by MAR to SEL 4. MAR is incremented. 5. Load 3006 to SEL O using word command reference. Set ROM In and STEP uP bits. 6. Examine SEL 4 Low byte for memory content using word command reference. Low byte of SEL 4 contains content of memory location under examination. 7. Go to step S for exam- ination of consecutiive memory locations. 4-24 Example 2: Examine DMR11 Scratchpad Registers Procedures 1. Load 0 to SEL 0 using word command refer- . Comments To clear Run bit. [N ence. (See example 1 above for procedure to form register addressing on a VAX.) Load 618X ;4 to SEL 6 using word command reference. SEL 6 is loaded with microinstructions, where X is O-Fg Scratchpad Register and the content of SP is loaded into the Load 3004 to SEL 6 Set ROM In and Step uP bits. Branch Register. using word command reference. Load 62944 to SEL 6 Load microinstruction, where content of SPX (from BR) is using word command reference. loaded into SEL 4 low byte. Load SEL 0 with 3004¢ Set ROM In and Step uP bits. , using word command reference. Examine BSEL 4 for content of SPX. BSEL 4 contains contents of scratchpad X. 4-25 Example 3: DMRI11 Base Table Dump Comments Procedure NOTE The UBA Mapping register must be loaded as follows: Load address 20006804 with 80000001. 1. Load 23;¢to BSEL O using word command To perform an RQI for Base I type input. reference. 2. 3. Examine BSEL O for bit To indicate the microprocessors release of the port. Load 2006 to SEL 4 Giving base address to Microprocessor. 7 (RDY]) set. using word command reference. 4. 5. Load O to SEL 6 using Clearing high order address bits and Resume bit. Load 83;4to BSELO To relinquish port back to microprocessor. word command reference. using word command reference. 6. Load 22,4to BSEL O To force a Halt Function with RQI. using word command reference. 7. 8. 9. Examine BSEL O for bit To indicate the microprocessors release of the port, Load FF4to SEL 4 & Force Procedural Error. Load 82,4to BSEL O To relinquish port back to microprocessor. 7 (RDI) set. SEL 6 using word command reference. using word command reference. 10. Examine 128 memory To see counters, buffers, and other Base Table data. locations starting at 2006 to see Base Table. 4-26 APPENDIX A FLOATING DEVICE ADDRESSES AND VECTORS A.1 FLOATING DEVICE ADDRESSES UNIBUS addresses starting at 760010 and continuing through 763776 are designated as floating device addresses (see Figure A-1). These are used as register addresses for communications (and other) devices interfacing with the PDP-11 and VAX-11/780. NOTE Some devices are not supported by VAX-11/780, however, the same scheme applies; that is, gaps are provided as appropriate. The convention for assigning these addresses is as follows: Floating CSR Address Devices Rank Option Decimal Size Octal Modulus 1 2 4 8 4 10 20 3 IDAND DHI1 DQl1 4 DUII 4 10 5 6 7 8 9 10 11 12 13 14 DUPI1 LKI1IA DMC11/DMRI11 DZ11* and DZV11 KMClI1 LPP11 VMV2] VMV3] DWR70 RL11 and RLV]] 4 4 4 4 4 4 4 8 4 4 10 10 10 10 10 10 10 20 10 10 (extra only) 10 A gap of 10g must be left between the last address of one device type and the first address of the next device type. The first address of the next device type must start on a module 10g boundary. The gap of 10g must also be left for devices that are not installed but are skipped over in the priority ranking list. Multiple devices of the same type must be assigned contiguous addresses. Reassignment of device types already in the system may be required to make room for additional ones. * DZI11E and DZ11F are dual DZ11s and are treated by the algorithm as two DZ11s. A-1 777 777 DIGITAL EQUIPMENT 2K WORDS CORPQORATION (FIXED ADDRESSES) 770 000 DR11-C 1K + WORDS 1. USER ADDRESSES 767 777 764 000 763 777 T 1K WORDS FLOATING ADDRESSES 760 010 DIGITAL EQUIP CORP (DIAGNOSTICS) 760 006 760 000 757 777 001 000 000 777 T 80 VECTORS FLOATING VECTORS 000 300 000 277 48 TRAP & INTERRUPT VECTORS VECTORS 000 000 MK-2190 Figure A-1 UNIBUS Address Map A.2 FLOATING VECTOR ADDRESSES Vector addresses, starting at 300 and proceeding upward to 777, are designated as floating vectors. These are used for communications (and other) devices that interface with the PDP-11 and VAX11/780. NOTE Some devices are not supported by VAX-11/780, however, the same scheme applies. Vector size is determined by the device type. There are no gaps in floating vectors unless required by physical hardware restrictions (in data communications devices, the receive vector must be on a zero boundary and the transmit vector must be on a 43 boundary). Multiple devices of the same type would be assigned vectors sequentially. The following chart shows the assignment sequence. Floating Interrupt Vector Devices Rank Option Decimal Size Octal Modulus 1 DCl11 4 10 2 2 2 KL1I(extra) DL11-A(extra) DL11-B(extra) 4 4 4 10* 10* 10 3 4 5 DPI11 DMI11-A DNI11 4 4 2 10 10* 4 6 6 7 DMI11-BB DH11 modem control DR11-A 2. 2 4 4 4 10* 8 9 10 DR11-C 4 10* PA611(reader) PA611(punch) 2 2 10* 10* 11 12 LPDI11 DTI11 4 4 10 10* 13 14 14 14 15 DX11 DL11-C DLI11-D DL11-E DJI1 4 4 4 4 4 10* 10* 10* 10* 10* 16 17 DH11 GT40 4 8 10F 10 18 LPSI11 12 30* 19 20 DQ11 KWI1-W 4 4 10% 10 21 DUI1I 4 10* 22 23 24 25 26 DUPI1 DV1] DV modem control LKI1I-A DWUN 4 4 2 4 4 10* 10* 4 10 10 27 DMC11/DMRI11 4 10* 28 DZ11 4 10* 29 30 KMCl11 LPPI11 4 4 10 10 31 VMV2] 4 10 32 VMV3l 4 10 33 VTVO0I K T 34 DWR70 4 10* 35 RL11/RLVI] 2 4 36 37 38 39 RX02 TS11 2 2 LPAIl-K IP11/1P300 4 4 4 (after the first) 10 4 2 * The vector for the device of this type must always be on a 10g boundary. + These devices can have either a M7820 or M7821 interrupt control module. However. it should always be on a 10g boundary. i To be determined. A.3 EXAMPLES OF DEVICE AND VECTOR ADDRESS ASSIGNMENT Example | The first device requiring address assignment in this example is a DH11 (Number two in the device address assignment sequence; Number 16 in the vector address assignment sequence). The only devices used are: 2 2 1 1 Device (Option) DHlls DQlls DUPII DMRI1I Device Address Vector Address Comment Gap left for DJ11 (one on device address assign- 760010 ment sequence) which is not used DHI11 760020 300 First DHI11 DHI11 760040 310 Second DHI1 1 Gap between the last DHI1 used and the next 760060 device DQI1 760070 320 First DQI 1 DQI11 760100 330 Second DQ11 DUPI1 DMRI11 760110 Gap between the last DQI1 used and the next 760120 Gap left for DU Is not used 760130 device 340 Only one DUPII 760140 Gap left between DUPI11 and next device 760150 Gap left for LK11-As not used 760160 760170 350 Only one DMRI1 Gap left after the last device (in this case, the DMRI1) to indicate that none follow Example 2 The only devices used in this example are: 1 DJ11 1 DHI1 2 DQlls 2 DUPlIs DMRI1Is 2 Device Device Vector (Option) Address Address Comment IDARD 760010 300 Only one DJ11 DHI11 760020 Gap left between DJ11 and the next device 760030 Gap -The next device, DHI11, must start on an address boundary that is a multiple of 20 760040 310 Only one DH11 760060 Gap left between DH11 and next device DQI 760070 First DQ11 DQI 1 760100 Second DQI11 760110 Gap left between DQI11 and next device 760120 Gap left for DU11s not used DUPII 760130 340 First DUPI1 DUPII 760140 350 Second DUPI 1 Gap left between the last DUPII and next de- 760150 vice Gap left for LK11-As not used 760160 DMRI11 760170 360 First DMR11 DMRI1 760200 370 Second DMR11 760210 Gap left after the last device (in this case the DMRI11) to indicate that none follow Example 3 Only one of each of the following devices are used in this example: DCI1 DJ11 DHI1l1 GT40 DQI1 DUPII DMRI1 DMCl11 Device (Option) Device Address DCI1 DJil DHI1 760010 Vector Address Comment 300 DC11 has a fixed device address 310 Only one DJ11 760020 Gap left between DJ11 and the next device 760030 Gap - The next device, DH11, must start on an address boundary that is a multiple of 20 760040 320 Gap left between DHI1 and next device 760060 GT40 DQIlI DUPII 760070 Only one DH11 | 330 GT40 has a fixed device address 340 Only one DQI11 760100 Gap left between DQI1 and next device 760110 Gap left for DU11s not used 760120 350 Only one DUP11 760130 Gap left between DUP11 and the next device 760140 Gap left for LK 11-As not used DMRI1 760150 360 Only one DMRI11 DMCI1 760160 370 Only one DMC11 760170 Gap left after the last device (DMCl1) to indicate that none follow APPENDIX B DDCMP IN A NUTSHELL B.1 DDCMP DDCMP (DIGITAL Data Communications Message Protocol) was developed to provide full-duplex message transfers over existing standard hardware. B.1.1 Controlling Data Transfers The DDCMP message format is shown in Figure B-1. A single control character is used ina DDCMP message and is the first character in the message. Three control characters are provided in DDCMP to differentiate between the three possible types of messages: SOH - data message follows ENQ - control message follows DLE - bootstrap message follows Note that the use of a fixed-length header and message size declaration obviates the requirement for extensive message and header delimiter codes. syn| {synl |son COUNT | FLAG DATA |RESPONSE | SEQUENCE |ADDRESS|CRC-1 BIT Tslg 14 BITS|2 BITS|8 BITS 8BTS |8 BITS |16 8ITS (ANY NUMBER OF 8-BIT CHARACTERS UP TO 214) CRC-2 16 BITS MK-2248 Figure B-1 DDCMP Data Message Format Figure B-2 shows an example of a data exchange. B.1.2 Error Checking and Recovery DDCMP uses a 16-bit cycle redundency check (CRC-16) for detecting transmission errors. When an error occurs, DDCMP sends a separate negative acknowlege (NAK) message. DDCMP does not require an acknowledgement message for all data messages. The number in the response field of a normal header or in either the special NAK or acknowledge (ACK) message specifies the sequence number of the last good message received. For example, if messages 4, 5, and 6 have been received since the last time an acknowledgement was sent and message 6 is bad, the NAK message specifies number 5 which says “‘messages 4 and 5 are good and 6 is bad.” When DDCMP operates in full-duplex mode, the line does not have to be turned around: the NAK is simply added to the sequence of messages for the transmitter. B-1 DMR #2 DMR #1 SENDS A STRT (START) MESSAGE WHICH MEANS: “| WANT TO BEGIN SENDING DATA TO YOU AND THE SEQUENCE NUMBER OF MY &~~~ SENDS A STRT (START) MESSAGE WHICH MEANS: “I WANT TO BEGIN SENDING DATA _ TO YOU AND THE SEQUENCE NUMBER OF MY FIRST MESSAGE WILL BE 1.” FIRST MESSAGE WILL BE 1.” @ RECEIVES STRT MESSAGE. SENDS A STACK (START_ ACKNOWLEDGE) MESSAGE WHICH MEANS: “OK WITH ME.” @ RECEIVES STACK. 6 ) SENDS DATA MESSAGES WITH A RESPONSE FIELD SET TO O AND THE SEQUENCE FIELD SET TO 1. WHICH MEANS: “1 AM LOOKING FOR YOUR MESSAGE 1.” OTHER MESSAGES MAY BE SENT / AT THIS TIME (I.E., MESSAGES 2, 3, ETC)) WITHOUT WAITING FOR A RESPONSE. 1 AND CHECKS IT FOR \ @ RECEIVES DATA MESSAGE ERRORS. IF THERE IS A SEQUENCE AND CRC SEQUENCE ERROR, GO TO 12. IF THERE IS NO ERROR, GO TO 9. o A CRC ERROR WAS DETECTED. COMPUTER B SENDS A NAK MESSAGE WITH THE RESPONSE FIELD SET TO 0. WHICH MEANS: “ALL MESSAGES UP TO O (MODULO 256) HAVE BEEN ACCEPTED AND MESSAGE 1 IS IN ERROR.” COMPUTER A RECEIVES NAK, RETRANSMITS. MESSAGE 1 AND ANY OTHER MESSAGES SENT SINCE (L.E., 2, 3, ETC.) IF ALREADY SENT. ( ) T~ @ SENDS ACK RESPONSE OF 1 EITHER IN A / @ RECEIVES ACK AND RELEASES MESSAGE 1. @CONT'NUES SENDING MESSAGES. \’ SEPARATE ACK MESSAGE OR IN THE RESPONSE FIELD OF A DATA MESSAGE. DISCARD MESSAGE AND WAIT FOR PROPER TIMES OUT DUE TO LACK OF RESPONSE FOR MESSAGE 2. SENDS A REPLY FOR @ SEND NACK RESPONSE OF 1 IN THE @ RETRANSMITS MESSAGE 2 AND FOLLOWING MESSAGES MK 2250 When a sequence error occurs in DDCMP, the receiving station does not respond to the message. The transmitting station detects, from the response field of the messages it receives (or via timeout), that the receiving station is still looking for a certain message and sends it again. For example, if the next message the receiver expects to receive is 5, but receives 6 instead, the receiver will not change the response field (which contains a 4) of its data messages. The receiver will say, *I accept all messages up through message 4 and I'm still looking for message 5. B.1.3 Character Coding DDCMP uses ASCII control characters for SYN, SOH, ENQ and DLE. The remainder of the mes- sage, including the header, is transparent. _ Data Transparency B.1.4 DDCMP defines transparency by use of a count field in the header. The header is of a fixed length. The count in the header determines the length of the transparent information field, which can be from 0 to 16,383 bytes long. To validate the header and count field, it is followed by a CRC-16 field: all header characters are included in the CRC calculation. Once validated, the count is used to receive the data and to locate the second CRC-16, which is calculated on the data field. Thus, character stuffing is avoided. Data Channel Utilization B.1.5 DDCMP uses either full-duplex or half-duplex circuits at optimum efficiency. In the full-duplex mode, DDCMP operates as two independent one-way channels, each containing its own data stream. The only dependency is the acknowledgements which must be sent in the data stream in the opposite direction. Separate ACK messages are unnecessary, reducing the control overhead. Acknowledgements are simply placed in the response field of the next message for the opposite direction. If several messages are received correctly before the terminal is able to send a message. all of them can be acknowledged by one response. Only when a transmission error occurs, or when traffic in the opposite direction 1s light (no data message to send), is it necessary to send a special NAK or ACK message, respectively. In summary, DDCMP data channel utilization features include: 1. The ability to run on full-duplex or half-duplex data channel facilities, 2. Low control character overhead, 3. No character stuffing, 4. No separate ACKs when traffic is heavy: this saves on extra SYN characters and intermessage gaps, B.2 5. Multiple acknowledgements (up to 255) with one ACK, and 6. The ability to support point-to-point and multipoint lines. PROTOCOL DESCRIPTION DDCMP is a very general protocol: it can be used on synchronous or asynchronous. half-duplex or full-duplex, serial or parallel, and point-to-point or multipoint systems. Most applications involving protocols are half-duplex or full-duplex transmission in a serial synchronous mode: that operating environment will therefore be emphasized in this description. B-3 The header is the most important part of the message because it contains the message sequence num- bering information and the character count, the two most important features of DDCMP. Because of the importance of the header information, it merits its own CRC block check, indicated in Figure B-3 as CRC-1. Messages that contain data, rather than just control information, have a second section which contains any number of 8-bit characters (up to a maximum of 16,363) and a second CRC (indicated in Figure B-3 as CRC-2). Before the message format is discussed in greater detail, the message sequencing system should be explained because most of the header information is directly or indirectly related to the sequencing operation. In the DDCMP, any pair of stations that exchange messages with each other number those messages sequentially starting with message number one. Each successive data message is numbered using the next number in sequence, modulo 256. Thus, a long sequence of messages would be numbered |1, 2, 3,...254, 255, 0, 1,... The numbering applies to each direction separately. For example, station A might be sending its messages 6, 7, and 8 to station B, while station B is sending its messages 5, 6, and 7 to station A. Thus, in a multipoint configuration where a control station is engaged in two-way communication with 10 tributary stations, there are 20 different message number sequences involved - one sequence for messages from each of the 10 tributaries to the control station and one sequence for messages from the control station to each of the 10 tributaries. Whenever a station transmits a message to another station, it assigns its next sequential message number to that message and places that number in the sequence field of the message header. In addi- tion to maintaining a counter for the sequentially numbered messages which it sends, the station also maintains a counter of the message numbers received from the other station. It updates that counter whenever a message is received with a message number exactly one higher than the previously received message number. The contents of the received message counter are included in the response field ofthe message being sent, to indicate to the other station the highest sequenced message that has been received. ‘ When a station receives a message containing an error, that station sends a negative acknowledge (NAK) message back to the transmitting station. DDCMP does not require an acknowledgement for each message, as the number in the response field ofa normal header (or in either the special NAK or positive acknowledgement message ACK), specifies the sequence number of the last good message received. For example, if messages 4, 5, and 6 have been received since the last time an acknowledgement was sent, but message 6 is bad, the NAK message specifies number 5 which says ““messages 4 and 5 are good and 6 is bad.”” When DDCMP operates in the full-duplex mode, the line does not have to be turned around; the NAK is simply added to the messages for the transmitter. When a station receives a message that is out of sequence, it does not respond to that message. The transmitting station will detect this from the response field of the messages which it receives: if the reply wait timer expires before the transmitting station receives an acknowledgement, the transmitting station will send a REP message. The REP message contains the sequence number of the most recent unacknowledged message sent to the distant station. If the receiving station has correctly received the message referred to in the REP message (as well as the messages preceding it), it replies to the REP by sending an ACK. If it has not received the message referred to in sequence, it sends a NAK containing the number of the last message that it did receive correctly. The transmitting station will then retransmit all data messages after the message specified in the NAK. The numbering system for DDCMP messages permits up to 255 unacknowledged messages outstanding, a useful feature when working on high delay circuits such as those using satellites. B-4 NOTE 1 INFORMATION SYN SYN cLass |COUNT FLAG 14 BITS| 2 BITS| |RESPONSE | SEQUENCE|ADDRESS | CRC1 | ANY NUMBER | CRC 2 8 BITS 8 BITS 8 BITS |16 BITS OF 8-BIT 16 BITS CHARACTERS \\ NOTES NOTg N,OTES NOTEs MOOOKKOXXX XX XOOOKXXX XOOOOKXX SOr - DATA MIESSAGES 10000001 CHARACTER COUNT QS RESP # MESSAGE# ADDRES ENG {ACKNOWLEDGEMENT 00000101 00000001 000000 QS RESP # 00000000 ADDRESS 00000101 00000010----==--- QS RESP # 00000000 ADDRESS 00000000 00000000 00000000 LSTMESS# 00000000 00000000 ADDRESS ADDRESS ADDRESS NEGATIVE ACKNOWLEDGE REASONS: BCC HEADER ERROR 000001 BCC DATA ERROR 000010 REP RESPONSE 000011 BUFFER UNAVAILABLE 001000 RECEIVER OVERRUN 001001 MESSAGE TOO LONG 010000 HEADER FORMAT ERROR 010001 REPLY MESSAGE 00000101 ENQ { START MESSAGE 00000101 START ACKNOWLEDGEMENT 00000101 DLE MAINTENANCE MESSAGE 10010000 0000001 1000000 000001 10000000 000001 11000000 CHARACTER COUNT QS 11 11 11 00000000 00000000 XOXKXXXXX ADDRESS NOTES: . ONLY THE DATA MESSAGE AND THE MAINTENANCE MESSAGE HAVE CHARACTER COUNTS, SO ONLY THESE MESSAGES HAVE THE INFORMATION AND CRC2 FIELDS SHOWN IN THE MESSAGE FORMAT DIAGRAM ABOVE. “RESP #~ REFERS TO RESPONSE NUMBER. THIS IS THE NUMBER OF THE LAST MESSAGE RECEIVED CORRECTLY. WHEN USED IN A NEGATIVE ACKNOWLEDGE MESSAGE, IT IS ASSUMED THAT THE NEXT HIGHER NUMBERED MESSAGE WAS NOT RECEIVED, WAS RECEIVED WITH ERRORS, OR WAS UNACCEPTED FOR SOME OTHER REASON. SEE “REASONS.” “MESSAGE#" IS THE SEQUENTIALLY ASSIGNED NUMBER OF THIS MESSAGE. NUMBERS ARE ASSIGNED BY THE TRANSMITTING STATION MODULO 256; |.E.,, MESSAGE 000 FOLLOWS 255. “LSTMESS#"~ IS THE NUMBER OF THE LAST MESSAGE TRANSMITTED BY THE STATION. SEE THE TEXT DISCUSSION OF REP MESSAGES. ~ ADDRESS" IS THE ADDRESS OF THE TRIBUTARY STATION IN MULTIPOINT SYSTEMS AND IS USED IN MESSAGES BOTH TO AND FROM THE TRIBUTARY. IN POINT TO POINT OPERATION, A STATION SENDS THE ADDRESS 1" BUT IGNORES THE ADDRESS FIELD ON RECEPTION. 6. “Q" AND "S” REFER TO THE QUICK SYNC FLAG BIT AND THE SELECT BIT. SEE TEXT. MK- 2249 Figure B-3 DDCMP Message Format in Detail B-5 B.3 MESSAGE FORMAT With the above background, it is now time to explore the various DDCMP message formats in full detail, as shown in Figure B-3. The first character of the message is the class of message indicator, represented in ASCII with even parity. There are three classes of messages: data, control, and maintenance. These are indicated by class of message indicators SOH, ENQ, and DLE respectively. The next two characters of the message are broken into a 14-bit field and a 2-bit field. The 14-bit field is used in data and maintenance messages to indicate the number of characters that will follow the header and form the information part of the message. In control messages, the first 8 bits of the 14-bit field are used to designate what type of control message it is: the last 6 bits are generally filled up with zeros. The exception is in NAK messages where the last six bits are used to specify the reason for the NAK. The 2-bit field contains the quick sync and select flags. The quick sync flag is used to inform the receiving station that the message will be followed by sync characters; the receiver may wish to set its associated synchronous receiver hardware into sync search mode and sync strip mode. This will re-establish synchronization and syncs will be discarded until the first character of the next message arrives. The purpose of this is to permit the receiving station to engage any hardware sync-stripping logic it might have and prevent it from filling its buffers with sync characters. The select flag is used to indicate that this is the last message which the transmitting station is going to transmit and that the addressed station is now permitted to begin transmitting. This flag is useful in half-duplex or multipoint configurations, where transmitters need to get turned on and off. The response field contains the number ofthe last message correctly received. This field is used in data messages and in the positive and negative acknowledge types of control message. Its function should be evident from the preceding discussion of sequence control. The sequence field is used in data messages and in the REP type of control message. In a data message, it contains the sequence number of the message as assigned by the transmitting station. In a REP message, it is used as part of the question, “Have you received all messages up through message number (specify) correctly?” The address field is used to identify the tributary station in multipoint systems and is used in messages both to and from the tributary. In point-to-point operation, a station sends address |, but ignores the address field on reception. In addition to the positive and negative acknowledgement and REP types of control message, there are also start and start acknowledge control messages. These are used to place the station which receives them in a known state. In particular, they initialize the message counters, timers, and other counters. The start acknowledge message indicates that this has been accomplished. Figure B-3 also shows the maintenance message. This is typically a bootstrap message containing load programs in the information field. A complete treatment of bootstrap messages and start up procedures is beyond the scope of this book. NOTE Refer to the DDCMP Specification Order (AAD599A-TC) for a complete detailed description of DDCMP. APPENDIX C DIAGNOSTIC SUPERVISOR SUMMARY 7 1 Cel INTDNMNANITIATINN lNlRUUU\,llUl The PDP-11 diagnostic supervisor is a software package which: e Provides run-time support for diagnostic programs running on a PDP-11 in Stand-alone Mode, e Provides a consistent operator interface to load and run a single diagnostic program or a script of programs, e Provides a common programmer interface for diagnostic development, e Imposes a common structure upon diagnostic programs, e Guarantees compatibility with various load systems such as APT, ACT, SLIDE. XXUP+, ABS Loader, and e Performs non-diagnostic functions for programs, such as console 1/0, data conversion, test sequencing, program options. C.2 VERSIONS OF THE DIAGNOSTIC SUPERVISOR File Name Environment HSAA **SYS XXDP+ HSAB **.SYS APT HSAC **S5YS ACT/SLIDE HSAD **S8YS Paper Tape (Absolute Loader) In the above file names, ** ** * is for REV and patch level, such as “AOTM. C.3 LOADING AND RUNNING A SUPERVISOR DIAGNOSTIC A supervisor-compatible* diagnostic program may be loaded and started in the normal way, using any of the supported load systems. Using XXDP+ for example, the program “*“CZDMRB.BINTM is loaded and started by typing .R CZDMRB. *To determine if diagnostics are supervisor-compatible. use the List command under the Setup Utility (see section C.5.). XXDP+/ DIAGNOSTIC SUPERVISOR MEMORY LAYOUT ON A 16KW (MIN MEMORY) SYSTEM ADDRESS 100000 (0) XXDP+ 070000 (0) DIAGNOSTIC SUPERVISOR ( 6KW) 040000 (0) DIAGNOSTIC PROGRAM ( 7.5KW) 002000 (0) 000000 (0) MK-2216 Figure C-1 XXDP+ /Diagnostic Supervisor Memory Layout on a 16Kw (Min Memory) System The diagnostic and the supervisor are automatically loaded to the memory location (as shown in Figure C-1) and the program is started. The following message is typed by the program: DRS LOADED DIAG.RUN-TIME SERVICES CZDMR-B-0 M8203 STATIC LOGIC TESTS - PART | OF 2 UNIT IS M8203 DR> DR > is the prompt for the diagnostic supervisor routine. At this point a supervisor command must be entered (the supervisor commands are listed in section C.4). C.3.1 Five Steps to Run a Supervisor Diagnostic e STEP | - Enter start command. When the prompt “DR>" is issued, type: STA /PASS:1/FLAGS:HOE <CR> The switches and flags are optional. STEP 2 - Enter number of units to be tested. The program will respond to the Start command with: # UNITS? At this point the number of devices to be tested must be entered. STEP 3 - Answer hardware parameter questions. After the number of devices to be tested has been entered, the program will respond by asking a number of “‘Hardware Questions.”” The answers to these questions are used to build hardware parameter tables in memory. One of these ““Hardware P-TablesTM will be built for each device to be tested and the series of. questions will be posed for each device. STEP 4 - Answer software parameter questions. When all the “Hardware P-TablesTM are built, the program will respond with: CHANGE SW? If other than the default parameters are desired for the software, type *'Y.” If the default parameters are desired, type “N.” If “YTM is typed, a series of “Software QuestionsTM will be asked and the answers to these will be entered into the *“Software P-TableTM in memory. The software questions will be asked only once, regardless of the number of units to be tested. STEP 5 - Diagnostic execution. After the software questions have been answered, the diagnostic will begin to run. What happens next will be determined by the switch options selected with the Start command, or errors occurring during execution of the diagnostic. C.4 SUPERVISOR COMMANDS The supervisor commands that may be issued in response to the “DR>" prompt are as follows: Start Command - Used to start a diagnostic program. Restart Command - When a diagnostic has stopped and control is given back to the super- visor, this command may be used to restart the program from the beginning. Continue Command - Used to allow a diagnostic to continue running from where it was : stopped. Proceed Command - Causes the diagnostic to resume with the next test after the one in which it halted. Exit Command - Transfers control to the XXDP+ monitor. C-3 is given. Drop Command - Drops units specified until an Add or Start Command ed. Add Command - Adds units specified. These units must have been previously dropp Print Command - Prints out statistics if available. Display Command - Displays P-Tables. Flags Command - Used to change flags. ZFLAGS - Clears flags. All of the supervisor commands except Exit, Print, Flags, and ZFLAGS can be used with switch options. Command Switches ns may be used with most supervisor commands. The available switches and their funcoptio h Switc tion are as follows: of the lt is all tests). An example ugh the tests to be run (the defau| thro .JTESTS: - Used to specifyStart ugh 5, 19, and 34 thro 38 command to run tests tests switch used with the C4.1 would be: DR> START/TESTS : 1-5: 19 34-38 <CR> ple: ./PASS: - Used to specify the number of passes for the diagnostic to run. For exam DR> START/PASS: 1 In this example, the diagnostic would complete one pass and give control back to the super- VisOr. how many passes of the diagnostic will occur before the end of pass ./EOP: - Used to specifydefau lt is one). message is printed (the entered ./JUNITS: - Used to specify the units to be run. This switch is valid only if **NTM" was in response to “CHANGE HW?” dingly. The k for conditions and modify program execution accor ./FLAGS: - Used to chec are: conditions checked for .HOE -Halt an error (transfers control back to the supervisor) ‘LOE - Loop on error -JER - Inhibit error reports .IBE - Inhibit basic error information ‘IXE - Inhibit extended error information PRI - Print errors on line printer .PNT - Print the number of the test being executed prior to execution C-4 :BOE - Ring bell on error :UAM - Run in unattended mode, bypass manual_intervention tests :ISR - Inhibit statistical reports :IOU - Inhibit dropping of units by program C.4.2 Control/Escape Characters Supported The keyboard functions supported by the diagnostic supervisor are as follows: ¢ - CONTROL C (1C) - Used to return control to the supervisor. The “*DR>" prompt would be typed in response to CONTROL C. This function can be typed at any time. LMNAAANTT DN Iy ra - 4 — == o PRy | sl Tha oTD N chensnrsad 2ynes e CONTROL Z (1Z) - Used during hardware or software dlalogue to terminate the dialogue and select default values. C.S e CONTROL O (10) - Used to disable all printouts. This is valid only during a printout. e CONTROL S (1S) - Used during a printout to temporarily freeze the printout. ¢ CONTROL-Q (1Q) - Used to resume a printout after a CONTROL S. WHAT IS THE SETUP UTILITY? Setup is a utility program that allows the operator to parameterize a supervisor diagnostic prior to execution. This is valid for either XXDP+ or ACT/SLIDE environments. Setup asks the hardware and software questions and builds the P-Tables. The commands available under Setup are: List - list supervisor diagnostics Setup - create P-Tables Exit - return control to the supervisor The format for the List command is: LIST DDN:FILE.EXT Its function is to type the file name and creation date of the file specified if it is a revision C or later supervisor diagnostic. If no file name is given, all revision C or later supervisor diagnostics will be listed. The default for the device is the system device and wildcards are accepted. The format for the Setup command is: SETUP DDN:FILE.EXT=DDN:FILE.EXT It will read the input file specified and prompt the operator for information to build P-Tables. An output file will be created to run in the environment specified. File names for the output and input files may be the same. The output and input device may be the same. The default for the device is the system device and wildcards are not accepted. C-5 APPENDIX D MICROCODE OVERVIEW D.1 INTRODUCTION This section contains an overview of the major functional hardware areas and the microprogr am ofthe DMRI1. For detailed descriptions of the hardware components, refer to the list of related documents in Chapter 1. Chapter 3 contains detailed programming descriptions. D.2 FUNCTIONAL HARDWARE The basic flow of data and control signals of the DMR11] system 1s shown in Figure D-1. Some registers and control logic have been omitted for simplicity. Table D-1 contains brief descriptions of the major functional areas. D.3 DMRI11 MICROPROGRAM The DMRI11 microprogram determines the functions that the M8207-RA microprocessor will perform. This program is stored within the control read only memory (CROM) of the M8207-RA. The microinstruction set contains branch and move instructions. Branch instructions perform conditional and unconditional program jumps, and subroutine entry and return. Move instructions provide interregister and inter-memory transfers and perform logical and arithmetic operations on the transferred data. D.3.1 Microprogram Message Processing The microprogram performs four internal processes to implement data transfers between an external source (modem) and the central computer. As shown in the Executive Flow Diagram. Figure D-2, these processes are: transmit, receive, port service, and timer service. Each process operates independently of the other and is time-shared by the microprocessor. Activity levels within a process are called states. A typical flow diagram of microprogram message processing is shown in Figure D-3. Two examples of message processing are shown in the figure (solid lines and dotted lines). In the first example, the microprogram flow starts at state XM.A of a transmit process. When the activity within this state is completed, the program proceeds to the receive process at state RCV_ A, During the receive process a determination is made as to what action is required (see Figure D-2). In this example, nothing was done in the receive process and the program sequences through a timeservice routine if the program clock time-out occurs. When the timer service state (T.1) has been completed, the program returns to the transmit process. This cycle of activity repeats until the message has been processed completely. Although the processing cycle requires the flow to sequence through each process, there may be state levels entered where no action will take place. D-1 <fi — ADDRESS | M8207-RA MICROPROCESSOR R 4 3 ] |] || 1 i | oaTa UNIBUS TRANSCEIVERS I l I UNIBUS DATA RAM DATA SG'STER MUX MUX ELECT | MULTIPORT RAM NPR REG|CSR REG] SELECT SROM " 8x32 UNIBUS ] A B [ MAR 8:1 FROM — 32 X8 |- ALU 1 p.P M‘SC 8-BIT FUNCTION DMR INTERNAL MEM 4K X 8 - BRG - 1 & CROM INSTRUCTION REGISTER B 8-BITS | ALU T PROGRAM e A Sp | 16 X 8 BALU COUNTER 14-BIT MAR DATA IN CROM BERG DATA PORT DATA ouT 1 [ 1 1 BERG DATA PORT OUTBUS REGISTER REG -9 : ; TRANSMIT SILO SELECT {_ - | | EXT REG | | EXT REG| | RECEIVE SILO INBUS OUTBUS/INB L] & USYRT M8203 LINE UNIT MK-2200 Figure D-1 Data and Control Flow - Basic D-2 Table D-1 Major Functional Areas Function Description ALU Performs the microprocessor arithmetic and logic operations. Arithmetic Logic Unit BRG Branch Register Temporary 8-bit data register for branch determination and rotate right operations. There are three operating modes: load, shift right, and hold. Control Read Only Memory Instruction memory. Contains the microprogram (2K, 4K, or 6K X 16-bit). DMUX 8-bit line multiplexer: 8 to 1 CROM o e T. Data Multiplexer DROM Destination ROM Controls the destination location of data in a move instruction. FROM Controls up to 16 functions to be performed by the ALU (32 X 8 bits). INBUS Input Bus Register Reads incoming data and status into the receive silo (8bit register). IR Output register of the CROM. Instruction Register MAR Set up by microprocessor to address MEM. Memory Address Register MEM Main Memory MIR Maintenance Instruction Register MP RAM Multipart Random Access Memory Used for loading a single microinstruction from the CPU and providing various maintenance functions. Outputs are wire-ORed with IR outputs. Contains the control and status registers that are accessible both internally and by the CPU program. Also contains NPR IN/OUT address and data registers. NPR Nonprocessor Request and Control PC Program Counter Allows microprocessor to initiate an NPR under microprogram control and gain the UNIBUS to transfer data to or from the CPU memory. Provides the addressing for the CROM. PC control is derived from branch and move instructions. Table D-1 Major Functional Areas (Cont) Function REGISTER SELECT Description Decodes selected register address and type of UNIBUS operation requested. SILO Transmit or Receive First in, first out register. Receive silo is loaded from the USYRT. transmit silo in the microprocessor (64 SP Temporary storage register for data (16 X 8 bits). SROM Source Read Only Memory Controls input selection for the DMUX. Also determines if a move instruction is to be executed (32 X 8 System Clock Provides clock pulses for the microprocessor. Scratch Pad Memory USYRT Universal Synchronous X 12). bits) Handles input or output data to the modem, and the basic protocol framing and error detection. Receiver/Transmitter enter successive process states The second example (dotted flow lines) shows that the program flow canwithin each process during the at any state level. However, it must go through a defined sequence cycle. Transmit Process lines indicate is a macroflow diagram of the transmit process. Areas within the dotted D-4 Figure in the flow tions Designa D-3). Figure microprogram state levels of the message processing cycle (see flow detailed the and listing de microco paths are actual program names and may be referred to in the D.3.2 charts included in the engineering print set. sion is possible or When a message is ready to be sent, the transmitter must determine whether transmis sent and sets up the to be not. If transmission is possible, the program determines the type of message negative acknowledge include: , priority of order in types, Message it. proper subroutines to process (NAK), reply (REP), data, and acknowledge (ACK). enters the When the transmitter is ready to send, all the sync signals are transmitted. Theg program d message by selectin the type field, subappropriate subroutine to set up the header of the specifie type field, message field, and response field. It then sets the selection flag in the header storage location, and sends the header out. If a REP, Start, or Stack message is in progress, the program resets the reply timer and if there is no data to be transmitted, continues toward the shutdown state. When a data message is being transmitted, the program initiates the first non-processor request (NPR) right after transmitting the header CRC (block check character). Receive Process a message. At When the microprogram is at the start of the receive process, it is expecting tos receive (see Figure D-5). If it D.3.3 this point, the program is either in the idle state or prepared to receivenesmessage is idle, an attempt is made to update the Base Table. If niot, it determi what type of message is being received. D-4 TRANSMIT PROCESS XM,* RECEIVE || proOCESS _____ RCV.* ANYTHING TO DO ? TIMER SERVICE PROCESS PORT SERVICE PROCESS| P.* MK-2201 Figure D-2 Executive Flow Diagram iately Data fetched from the host memory via NPRs are transmitted on the serial line, followed immed by CRCs. The program s ms error checking. When an error 1S tores the bytes that make up the header and perfor the receiver is cleared. returning it to the led and detected, a negative ac knowledge (NAK) is schedu the program sequences through a header veriidle state. After header storage has been completed, fication routine. RCV.B XM.C RCv.C XM.D RCV.D XM.E RCV.E b e Z e — RCV.A XM.B e XM.A e A —_— MICROPROGRAM STATES N TA P.A T.2 P.O T.3 P.P T4 P.OUT T.5 P.IN MK-2202 Figure D-3 Typical DMRI11 Message Processing TRANSMIT DATA MESSAGE/ CONTROL MESSAGE MAINTENANCE MESSAGE SMA -‘t SYNS + HDR BYTE 1 DECIDE TO TRANSMIT, WHAT TO TRANSMIT, AND SET UP BYTE 1 SEND ALL SYNS. ’i“‘?e & HEADER 1.D. XM.C DISPATCH TO SET UP HEADER HOR BYTE 2 l xm‘ CR l XM.CN (REp. START X,‘\AA;SA | l XM.CD SET UP DATA MESSAGE HEADER AND SEND CC . sTACK HEADER) (NAK) | ) {ACK HEADER) SEND TYPE FIELD HANDLE SELECTION XM.D FLAGS SET SELECT FLAG IN HEADER STORAGE XM.E SEND HEADER OUT +BCC ) - RESET REPLY TIMER FOR CONTROL MESSAGE o o XM.F XM.F1 - SEND UP TO HDR CRC | R == PREPARE TO START NPR FOR DATA MESSAGE e = = = — I ] DATA BYTES DATA ] OBTAIN DATA FROM XNF XM.G | TRANSMIT PREPARE TO SEND START NPR XNS [ DATA MESSAGE B | T (XM.C 1/2) HDR BYTE 3-6 SET UP HEADER STORAGE FOR CONTROL/ + v ] NPR e XM.H ] l TRANSMIT DATA BYTES ON THE LINE XNS START TRANSMITTING NPRs + DATA BCC TRANSMIT DATA BCC XM.| SEND DATA CRC DECIDE TO ABUT NEXT MESSAGE OR ' XM.J SHUT THE TRANSMITTER HANDLE SELECT FLAGS SEND PADS AND SHUT DOWN TRANSMITTER l L& XM. A e DOWN XM.K1 } XM.K2 SHUT DOWN THE TRANSMITTER J MK-2213 Figure D-4 Transmit Process Flow Diagram D-7 — —— — ct——— SYNCH | RECEIVER IDLE, GET FIRST RCV(A) SEARCH | BYTE OF NEW HEADER. BYTE 2 RECEIVER IDLE, BASE TABLE UPDATE | STORE HEADER RCV(B) WAIT FOR HEADER BYTES CONTROL DATA MESSAGE MAINTENANCE MESSAGE MESSAGE RCV(BD) RCV(BM) ] BYTE 5 | VERIFY HEADER FIELDS J BYTE 6 RCV(BC) o S ] S S BCC 1 (BYTE 7) v PROCSSCS\,’((?CC):I)\ITROL —— —- I RCV‘('CM) RCVICA) Rcvice) PROCESS MAINTENANCE L | MESSAGE HEADER MESSAGE BCC 1 (BYTE 8) RCV(CD) SET UP RECEIVE BUFFER FOR NPR SERVICE RECEIVE DATA i RCVI(DA) DETERMINE DATA RECEPTION STATE DATA (N) ¢ l RCV(DE) PROCESS EVEN BYTES | BCC 2 —« RCV(DM) [ TEST FOR BOOT RCV(DO) PROCESS ODD BYTES ] MESSAGE # END OF MESSAGE RCV(MA) (N+1) WAIT FOR BOOT MESSAGE -+ RCV(E) DATA BYTES - ——— WAIT FOR SECOND CRC BYTE BCC 2 HEADER OR DATA ( (N+2) ) l BOOT _.J;_______.___—_—__-_—_——__.____ MK-2214 Figure D-5 Receive Process Flow Diagram D-8 The program then performs the specified operation contained in the message. For a control type message, once the operation is complete, the program sequences to the end of message state. For data messages, the implied acknowledge field is processed. If the header is contained in a data message and there is a receive data buffer for storing the incoming data, the DMRI1 sets up the buffer for NPR service. When the incoming message is data, appropriate receiver registers are set up to accept the data from the communication line. The program initiates NPRs to transfer the data to the CPU memory (receive buffers). End of message processing is then performed where checks are made for overrun conditions, block check characters (BCC), and non-existant memory (NXM). After the data has been received and processed properly, the receive buffers are turned to the driver. If the incoming data is a boot message, control is transferred to a boot message subroutine to process the incoming boot data bytes. A boot password check is made to determine if the message is an Enter _MOP (for remote load detect). D-9 APPENDIX E BOOTSTRAP TEST UNDER ITEP Interprocessor test programs DZITA* ITEP monitor and DZDMO* ITEP DMCI l/DMRI | overlay, provide the capabilities to check out the communications link and to test the ability of the DMR11 to perform both remote load detect and down-line load. E.1 REMOTE LOAD DETECT Remote load detect (RLD) is also referred to as unattended system control in Maintenance Operation (MOP) Mode specifications (AA-D60ZA-TC). Unattended system control is defined as follows. The Enter MOP Mode message is used to control an unattended system. This message, together with the appropriate hardware, enables a satellite computer to halt current operation and begin operating in either the MOP primary or secondary mode. This is accomplished by transferring control to a resident MOP program or bootstrap. The hardware is used to recognize this message and force the computer system to transfer control to the MOP program, usually residing in a read only memory. The password in this message protects the system from being controlled and loaded by an unauthorized host. Only messages with a matching password will cause the system to enter MOP mode. E.2 DMRI11 SETUP FOR REMOTE LOAD DETECT DMRI11 Addressing E.2.1 When using the DMR11 with a bootstrap module (M9301-YJ or M9312), the DMR11 must be addressed according to the rules for floating address assignment. These rules are outlined in the installaand tion section of this manual. If the address is not set correctly, the module will not find the DMR11 neither manual booting of the DMR11 nor an RLD works. DMRI11 Line Unit Set up E.2.2 DMRIlisto The DMRI11 line unit (M8203), Switch Packs E134 and E121, must be properly set when in appliused is ion combinat be used with a bootstrap module such as the M9301-YJ or M9312. This cations where RLD and subsequent down line loading are required. The set-up of Switch Packs E134 and E121 is only required at the end of the link (satellite station) where the boot module is installed. Switch Pack E134 (M8203) is configured to contain the 8-bit password specified by the operating system. e Switch 1 is the LSB, switch 8 is the MSB e Set switches OFF for a | e All switches OFF (SP2=377) inhibits RLD operation E-1 Switch Pack E121 (M8203) is configured to the low order 8 bits of the bootstrap entry point (offset). Switch 1 is the LSB, switch 8 is the MSB NOTE Switch 1 represents bit 0 of the boot address and should be set to 0. Set switches OFF for a | Setting for current M9301-YJ code should be 356 (octal) for booting unit 0 and 374 (octal) for booting unit | ' NOTE The bootstrap entry point (offset) may be different for bootstrap ROM modules other than the M9301YJ. E.3 PROCEDURE TO TEST REMOTE LOAD DETECT UNDER ITEP Down-line load should not be attemped unless the DMRI11 link has been checked out successfully using the link test under DMR11 ITEP. The following switch settings are required on the M9301-YJ and DMRI11 line unit (M8203) when using ITEP. NOTE The M9301-YJ must have both the power-up boot and diagnostics disabled. Module/Switch SWI SWwW2 SwW3 Sw4 SW5 SwWé6 SW7 SW8 Switch Pack E134 ON ON ON ON ON ON ON ON ON OFF OFF OFF ON OFF OFF OFF SW9- SWI0 Switch Pack El121 In this mode, the originating station (the one running ITEP) will send an Enter MOP message to the boot station (the one with M9301-YJ) and initiate a down-line load. Successfully down-line loaded, the boot station will print out a boot complete message. See events for RLD under ITEP which follow the set-up requirements below. - Set the Enable/Halt switch on the console of the boot station to the enable position. If the boot station is a PDP-11/34 or PDP-11/04, press INIT (followed by CNTL Halt when using KY11-LB). Under ITEP at the originating station: ¢ Modify parameter one to 400, ¢ Modify paramter two to O, ¢ Deposit 1004 to console Switch register, and e Type <CR>. The automatic mode Bootstrap test should then complete and print out end pass message. E-2 Events for RLD Under ITEP (See Figure E-1) 1. At CPU one, ITEP steps up DMRI11, then assigns Enter MOP Mode (MOP6) 2. a. AtCPU two, DMRI1I1 compares MOP6 message received to password setup in line unit Switch Pack at E134. b. If all passwords match, DMRI11 two writes 173000 plus the contents of Switch Pack at E121 on line unit to location 24, clears location 26, and asserts AC LO on the UNIBUS. NOTE Load 125252 into locations 24 and 26. These two locations should be modified if 2b is occuring. Scope AC LO on CPU two to see if it is pulsing because 2b is occuring. c. CPU two program control is transferred to DMR11 boot code in the ROM boot (M9301-YJ type). The correct entry into boot code must be set up in line unit Switch Pack at E121 which contains offset added to 17300. d. The DMRI1! boot code sets up the DMRI11 and sends a Request Secondary Boot (MOPS8) message. 3. At CPU one, ITEP checks receipt of MOP8 message and transmits a memory load with transfer address (MOPO0) message. 4 a. AtCPU two, ROM boot receives MOPO and transfers program control to location 6. b. The down-line loaded program is then executed and a boot complete message is printed at the console terminal. NOTE 1. The above procedure will set the password for down-line load to 0. This password is determined by the switch E134 settings on M8203 at the boot station or remote station. When doing down-line load with software, the password used by software must match the password selected on the DMRI11 line unit at the remote station; in this case the password is 0. 2. For automatic boot (RLD) on successful recognition of the Enter MOP message the remote DMRI11 will NPR PC and PS to locations 24 and 26 respectively and then it will assert AC LO. Switch at E121 in the events sequence sets the Bootstrap entry point (offset) to 356 for booting DMR11 unit 0. 3. On PDP-11/40, 45, and 70, the AC LO asserted by the DMR11 will cause the CPU to assert DC LO. The setting of M9301-YJ SW2 to OFF, prevents the M9301 from attempting to take control of the address bits during the simulated power-up. 4. In order to verify switches at E134 and E121 on the line unit, run any DMRI11 diagnostics. The STAT2 under the Map of DMRI11 Status will give the actual setup of the switches. STAT2: Low byte (bits 7-0) = E134 (PASSWORD) High byte (bits 15-8) = E121 (BOOT OFFSET) E.4 PROCEDURE TO TEST DOWN-LINE LOAD UNDER ITEP The down-line load should not be attempted unless the DMRI11 link has been checked out successfully, using the link test under DMR11 ITEP. In this mode, the operator at the boot station has to do a boot to M9301-YJ at the entry point for DMRI11 Boot code which sends a request secondary boot message to the originating station (see Figure E-2). The originating station running ITEP in bootstrap mode then replies with a memory load with transfer address message. The boot station executes that program and prints out a boot complete message. Procedure: 1. 2. Under ITEP at the originating station: a. Modify parameter one to 2400, b. Modify parameter two to 0, c. Deposit 1004 in the console switch register, and d. Type <CR>. At the boot station, boot the M9301-YJ via one of the following methods: a. Type XM under the console emulator, b. Load address 7773356 and start, or c. On the PDP-11/04 and PDP-11/34, when switch setting on the M9301-YJ is set up to boot the DMRI1, a control boot to KY11-LB initiates the boot to the DMRI11. This may take two control boots to occur with KY11-LC (CNTRL BOOT/CNTRL HALT/CNTRL BOOT). NOTE Refer to the M9301-YJ manual for proper switch setting in each case. Upon successful completion of a down-line load, the terminal at the boot station prints out a boot complete message. E-4 HOST LINK ACTION REMOTE END HOST INITIATES DOWN-LINE LOAD BY SETTING DMR INTO MAINTENANCE MODE WITH CNTL IN AND SENDS A MOP 6 MESSAGE. THE PASSWORD IN MOP 6 MESSAGE MUST 470,06, EQUAL THAT OF THE REMOTE END. DMR11 RECEIVES MOP 6 MESSAGE AND CHECKS PASSWORD. IF EQUAL, DMR11 TRIES TO DO AN NPR TO LOCATION 24 WITH BOOT ADDRESS FROM THE SWITCH PACK ON THE 4,Ls LINE UNIT.(ADDRESS = DMR11 CODE IN 8406‘ M9301-YJ OR M8312 BOOTSTRAP MODULE) DMR11 ALSO CLEARS LOCATION 26. NOW DMR11 ASSERTS AC LO TO TRAP CPU TO LOCATION 24 TO JUMP TO THE BOOTSTRAP [SN) MODULE CODE. THE BOOTSTRAP MODULE INITIALIZES THE DMR TO MAINTENANCE MODE AND ASSIGNS A RECEIVE BUFFER AT LOCATION O WITH CHARACTER COUNT EQUAL TO 7774. THE BOOTSTRAP MODULE THEN TRANSMITS A MOP 8 MESSAGE TO THE HOST. IF NPR WAS ¢ é,s!*c’ Y N UNSUCCESSFUL, THEN WHEN AC LO WAS ASSERTED, THE CPU SHOULD HAVE TRIED TO EXECUTE WHATEVER WAS IN LOCATION 24 AND SHOULD START RUNNING. &%iLC:EECCET\?EEOR. MOP 8 MESSAGE A SECOND NPR TO LOCATION 24 & 26 ' OCCURS FOLLOWED BY A TRANSMITS A MOP O MESSAGE TO SECOND ASSERTION OF AC LO. THE REMOTE END. THIS SECOND SEQUENCE WILL NOTE: MOP O MESSAGE MUST BE START THE CPU IF THERE IS NO HARDWARE A SELF STARTING MESSAGE AT FAILURE. "o LOCATION 6. IF MORE THAN ONE LOAD IS REQUIRED, Po e IT MUST ALSO BE ABLE TO SSAGE SEND A REQUEST FOR A MOP O MESSAGE RECEIVED. SAME TERTIARY BOOT MESSAGE BACK TO SEQUENCE AS FOR REMOTE THE HOST CPU FOR MULTIPLE END REQUEST, SEE MOP O LOADS. ON THE FLOW CHART (FIGURE E-2). MOP 6 MESSAGE = CODE | 4 BYTES EQUAL TO SYSTEM PASSWORD(PASSWORD=0 FOR ITEP) | 6 | PASSWORD [ PASSWORD ] PASSWORD TPASSWORD MOP 8 MESSAGE = CODE | DEVICE TYPE | MOP VERIFY | PROGRAM TYPE 8 = O MESSAGE MOP DMC= 12 l 1 | | | O SECONDARY LOADER ] 4 BYTES | PROGRAM IMAGE | TRANSFER ADDRESS | CODE | LOAD# | LOAD ADDRESS MEMORY ADDRESS 0 o o]l o]l o] o 0 1 2 | 3| & 5 DATA 0 I 0 [ 6 l 0 | 6 MK-2252 Figure E-1 Down-Line Load to Remote End Using Remote Load Detect E-5 REMOTE END LINK ACTION HOST INITIATE REQUEST FOR SECONDARY BOOT MESSAGE. 1. 2. TYPE XM, LOAD ADDRESS 773356 or 773374 UNIT 1. 3. PRESS CONSOLE BOOT SWITCH IF M9301-YJ SWITCH PACK IS SET TO ADDRESS 773356 OR 773374 UNIT 1. DMR11 RECEIVES SECONDARY NOTE: ADDRESSES ABOVE SELECT DMR11 UNITO & 1 BOOT MESSAGE AND INFORMS CPU THAT A MAINTENANCE MESSAGE RESPECTIVELY WITHOUT WAS RECEIVED. DMR11 MUST NOW BE INITIALIZED AND DIAGNOSTICS ENABLED. IF ONLY DOING BOOT REQUEST THE CNTRL IN FORMAT MUST SET MAINTENANCE MODE AND TRANSMIT THE MOP O MESSAGE THEN DIAGNOSTICS ENABLE TO THE REMOTE END. (773354 & 773372) FROM THIS REMOTE END ADDRESS CAN BE USED. NOTE: MOP MESSAGE O MUST BE A SELF STARTING MESSAGE AT LOCATION 6 AND IF MORE THAN ONE LOAD IS REQUIRED, ANY OF THE ABOVE CAUSES THE M9301-YJ CODE TO SEND A MOP 8 MESSAGE VIA THE DMR11 LINK. IT MUST ALSO BE ABLE TO SEND A REQUEST FOR A TERTIARY BOOT MESSAGE BACK M9301-YJ CHECKS FOR MOP O MESSAGE AND STARTS LOADING TO THE HOST CPU FOR MULTIPLE LOADS. AT LOCATION O.WHEN DONE LOADING, THE M9301-YJ TRANSFERS STARTING ADDRESS OF 6 FROM MS301-YJ TO START MOP O MESSAGE (SECONDARY BOOT REQUEST MESSAGE COMPLETED.) MOP 0 MESSAGE MUST NOW REQUEST TERTIARY LOADER, IF NECESSARY FOR MORE DATA TO BE LOADED. NOTE: MAX DATA/MESSAGE IS 8K WORDS OR 16K BYTES. MOP 8 MESSAGE = —CO0F DEVICE TYPE l MOP VERIFY | DMC= 12 | 1 I PROGRAM TYPE |0 SECONDARY LOADER | MOP 0 MESSAGE = CODE | LOAD# | LOAD ADDRESS 4 BYTES| PROGRAM IMAGE | TRANSFER ADDRESS | MEMORY ADDRESS 0 o |ololo] o O 1 2 4| 5 { 31 DATA Iololeloi |6 MK-2251 Figure E-2 Remote End Request for Down-Line Load GLOSSARY ACKNOWLEDGE (ACK): Indicates that the previous transmission block was accepted by the receiver and it is ready to accept the next block of the transmission. ARITHMETIC LOGIC UNIT (ALU): Allows the microprocessor to perform arithmetic and logic operations. A PORT: Read/write input to the multiport RAM. ASYNCHRONOUS TRANSMISSION: Transmission in which time intervals between transmitted characters may be of unequal length. Transmission is controlled by start and stop elements at the beginning and end of each character. Also called Start-Stop transmission. BUFFERED ARITHMETIC LOGIC UNIT (BALU): Operations performed by the ALU are buffered by the BALU and directed to data memory, respective registers, and the Berg Port. BERG PORT: An 8-bit port that allows the microprocessor to communicate with other devices without using the UNIBUS. BIT-STUFF PROTOCOL.: Zero insertion by the transmitter after any succession of five continuous ones designed for bitoriented protocols such as IBM’s Synchronous Data Link Control (SDLC). BITS PER SECOND: Bit transfer rate per unit of time. B PORT: Read Address input of the multiport RAM (Read Only Port). BRANCH REGISTER (BRG): Temporary card storage register used for branch determination and shifting right. BUFFER: Storage device used to compensate for a difference in the rate of data flow when transmitting data from one device to another. GLOSSARY-1 Comite Consultatif Internationale de Telegraphie et Telephonie - An international consultative CCITT: committee that sets international communications usage standards. CONTROL AND STATUS REGISTERS (CSRs): Communication of control and status information is accomplished through these registers. CRC (CYCLIC REDUNDANCY CHECK): An error scheme in which the check character is generated by taking the remainder after dividing : all the serialized bits in a block of data by a predefined number. CROM: Plug-in control read only memory used as the instruction memory for the processor. CYCLIC REDUNDANCY CHECK (CRC): | An error detection scheme in which the check character is generated by taking the remainder after dividing all the serialized bits in a block of data by a predetermined binary number. DATA LINK ESCAPE (DLE): (control charA control character used exclusively to provide supplementary line control signals character is first the where s sequence acter two-char acter sequences or DLE sequences). These are used. code the and desired function the to g DLE. The second character varies accordin DATA MULTIPLEXER (DMUX): An 8-bit wide, 8-to-1 multiplexer used to select data for the B input of the ALU. DATA-PHONE DIGITAL SERVICE (DDS): A communications service of the Bell System in which data is transmitted in digital rather than analog form, thus eliminating the need for modems. DESTINATION ROM (DROM): Controls the operand as defined by the destination of the instruction in the instruction register. DIGITAL DATA COMMUNICATIONS PROTOCOL (DDCMP): DIGITAL's standard communications protocol for character oriented protocol. DIRECT MEMORY ACCESS (DMA): Permits 1/O transfers directly into or out of memory without passing through the processor’s general registers. ELECTRONIC INDUSTRIES ASSOCIATION (EIA): A standards organization specializing in the electrical and functional characteristics of interface equipment. FROM: Function ROM - Controls up to 16 functions performed by the ALU. FULL-DUPLEX (FDX): Simultaneous two-way independent transmission in both directions. FIELD REPLACEABLE UNIT (FRU): Refers to a fauity unit not to be repaired in ihe fieid. Unit is replaced with a good unit and the faulty unit is returned to a predetermined location for repair. GLOSSARY-2 FIFO: First In/First Out characteristic of the silo hardware buffer. HALF-DUPLEX (HDX): An alternate, one-way-at-a-time independent transmission. IBUS/OBUS: Microprocessor NPR control, miscellaneous registers, and CSRs. IBUS*/OBUS*: Microprocessor NPR control. miscellaneous registers, and CSRs. INSTRUCTION REGISTER (IR): Contains the instruction that is being executed. Outputs are used to control the microprocessor. LINK MANAGEMENT: | ~ The link management component resolves the transmission and reception on links that are con- nected to two or more transmitters and/or receivers in a given direction. LU IBUS: The line unit input data bus provides a path to the DMUX via the berg connector. MEMORY ADDRESS REGISTER (MAR): Controls the data memory for buffered arithmetic and logic operations to main memory. MAIN MEMORY (MEM): Data storage area for the microprocessor 4K X 8 RAM: cannot be accessed directly by the CPU. MAINTENANCE INSTRUCTION REGISTER (MIR): Provides a destination for an instruction that can be loaded by the CPU during maintenance. MOP: Maintenance operation protocol. MULTIPORT RAM: Contains all M8207 control and status registers between the microprocessor and the CPU procesSOT. NEGATIVE ACKNOWLEDGMENT (NAK): Indicates that the previous transmission block was in error and that the receiver is ready to accept a retransmission of the erroneous block (also a Not Ready Reply to a station selection in multiport). NON-PROCESSOR REQUEST (NPR): Direct memory access type transfers, see DMA. PROGRAM COUNTER (PC): A 14-bit counter used to control the address of the control ROM directly. PC is derived from Branch and Move instructions. PROTOCOL: A formal set of conventions governing the format and relative timing of message exchange between two communicating processes. GLOSSARY-3 RANDOM ACCESS MEMORY (RAM) READ ONLY MEMORY (ROM) RS232-C: EIA standard single-ended interface levels to modem. RS-422-A: EIA standard differential interface levels to modem. RS-423-A: EIA standard single-ended interface levels to modem. RS-449: EIA standard connections for RS-422-A and RS-423-A to modem interfgce. SILO: First in. first out register. Receive silo is loaded from the USYRT, transmit silo from the micro- processor (64 X 12). SCRATCHPAD MEMORY (SP): Read/write memory used for temporary storage of data (16 X 8 bits). SCROM: Source ROM - Controls input selection for the DMUX. Also determines ifa move instruction is to be executed (32 X 8 bits). SYNCHRONOUS TRANSMISSION: Transmission in which the data characters and bits are transmitted at a fixed rate with the transmitter and receiver synchronized. SYSTEM CLOCK: Basic timing providing clock pulses for microprocessor timing functions. UNIBUS: A single high speed bus on which system components connect and communicate with each other. Addresses, data, and control information are transmitted via 56 available lines of the bus. USYRT: Universal Synchronous Receiver/Transmitter - Handles input or output data to the modem, and the basic protocol framing and error detection. GLOSSARY-4 DMR11 SYNCHRONOUS CONTROLLER TECHNICAL MANUAL Reader’'s Comments EK-DMR11-TM-002 Your comments and suggestions will help us in our continuous effort to improve the quality and usefulness of our publications. What is your general reaction to this manual? weli written, etc? In your judgement is it complete, accurate, well organized, s it easy to use? What features are most useful? What faults or errors have you found in the manual? Does this manual satisfy the need you think it was intended to satisfy? Does it satisfy your needs? O Why? Please send me the current copy of the Technical Documentation Catalog. which contains information on the remainder of DIGITAL's technical documentation. Name Street Title City Company Department Zip State/Country Additional copies of this document are available from: Digital Equipment Corporation 444 Whitney Street Northboro, MA 01532 Attention: Communications Services {(NR2/M15) Customer Services Section Order ‘No. EK-DMR11-TM-002 e DO NOt Tear — Fold Here and Staple-——-——————————-——-— ————————— —— —— ———— I BH50020 No Postage Necessary if Mailed in the United States BUSINESS REPLY MAIL FIRST CLASS PERMIT NO. 33 MERRIMACK, NH POSTAGE WILL BE PAID BY ADDRESSEE Digital Equipment Corporation Educational Services Development & Publishing Continental Bivd. (MK1/2M26) Merrimack, N.H. 03054
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