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Document:	DMC11 IPL Microprocessor Maintenance Manual
Order Number:	EK-DMCMP-MM
Revision:	001
Pages:	200
Original Filename:

OCR Text

DMC11 IPL microprocessor
maintenance manual

dlifgliltiall

EK-DMCMP-MM-001

DMC11 IPL microprocessor

maintenance manual

digital equipment corporation ¢ maynard, massachusetts
e

A
A ——_
e ————————————

Preliminary Printing, May 1976

The material in this manual is for informational

purposes and is subject to change without notice.

Digital Equipment Corporation assumes no responsibility for any errors which may appear in this
manual.
Printed in US.A.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

DECtape

DECCOMM

DECUS

DECsystem-10

RSTS

DIGITAL

TYPESET-8

DECSYSTEM-20

MASSBUS

PDP

TYPESET-11

UNIBUS

CONTENTS
Page

CHAPTER 1

INTRODUCTION

1.1

MICROPROCESSOR GENERAL DESCRIPTION

CHAPTER 2

INSTALLATION

2.1

SCOPE

UNPACKING AND INSPECTION

2-1

2.2

OPTION DESIGNATIONS

2-2

2.3

MECHANICAL PACKAGING

2=2

2.4
2.5

PREINSTALLATION PROCEDURES

2-5

General Information

2-5

Preinstallation Checkout Procedures

2-6

2.5. 1
2.5. 2

2-1

2-9

2.6

INSTALLATION

2.7

DEVICE ADDRESSES

2.7. 1

2.7. 2
2.7. 3
2.8
2.8. 1

2.8. 2

2.8. 3

Introduction

2-12

Device Address Selection

2-15

VECTOR ADDRESSES
Introduction

2-18
2-18

vector Address Selection

2-19

CHAPTER 3

PROGRAMMING INFORMATION

3.1

INTRODUCTION

3.2

INTERRUPT VECTORS

3.3

PRIORITY SELECTION

3.4.

2-18

Floating Vector Address Assignment
INSTALLATION CHECKLIST

3.4.

2-12

Floating Device Address Assignments

2.9

3.4

2—-12

2-20

3-1

3-2
3-2

PDP-11 PROGRAMMING INFORMATION
Introduction

Unibus Control and Status Registers
Input Transfers

Output Transfers

Initialization
DDCMP Start Up

Data Transmission

0.‘

3-3
3-3

3-20

3-22

3-24
3-26

3-26

CONTENTS

(Cont)
Page

3. 4.8

Data Reception

3. 4.9

Control Out Transfers
Maintenance Messages

-4.11

Remote

.4.12

Power Fall

.4.13

Data

wwwwwwwwwwwwwwwww

.4.10

Set

Load

Recovery

3-35
REGISTERS

N
w

NPR Control

Microprocessor Miscellaneou
s Register

NPR Bus

Registers

0-7

Address

and

Data

Registers

G
OV B

Control

3-46

Modem Control
Sync

3-50

3=-53

3-55

Switch Selectable Registers

Maintenance
DETAILED

3-56

DESCRIPTION

SCOPE

4-1

MICROPROCESSOR DESCRIPTION

4-1

Introduction

N
W

CROM,

Main Memory

CROM and

the

DMUX

SROM

4-1

Microinstruction Word Formats

ALU

3-45

3-46

Y N

3-43

3-46

In/Out Data Silo Registers
Control

3=37
3=-37

UNIT REGISTERS

Out

3-36

OUT BUS*/IN BUS*

LINE

3-33

3-35

Control

Introduction

U
O
O
SR
SR
- S -N
R
T

3=-32

MICROPROCESSOR CONTROL AND
STATUS

CHAPTER 4

NNN!\)NNNNNN}—'

3-29

Load Detect and Down Line

i S ©) B O

mo\mmmmmmmmmmm

3-28

MAR,

and

BR,

BRANCH

4-1
MUX

4-14

4-17
Maintenance

and Associated

Scratch

and

Pad Memory

Multiport RAM

REG

4-20

4-21
Logic

4-22

4-27
4-28

CONTENTS

(Cont)
Page

4.2.10

Maintenance CSR

4-34

4.2.11

Microprocessor Clock

4-37

4.2.12

Address Selection Logic

4-41

4.2.13

NPR Control Logic

4-41

4.2.14

Interrupt Control Logic

4-44

4.2.15

Line Unit Interface

4-46

4.2.16

Typical System Timing

4-49

CHAPTER 5

MAINTENANCE

5.1

SCOPE

5.2

MAINTENANCE PHILOSOPHY

5.3

PREVENTIVE MAINTENANCE

5.4

TEST EQUIPMENT REQUIRED

5.5

CORRECTIVE MAINTENANCE

5.5.1

APPENDIX A

Diagnostic Modes

PDP-11 MEMORY ORGANIZATION AND
ADDRESSING CONVENTIONS

CHAPTER

INTRODUCTION

1.1

MICROPROCESSOR GENERAL DESCRIPTION

operate,
This manual provides the information necessary to install,
covers
and maintain the DMC11 Microprocessor. Specifically, it
to
the DMC11-AD Microprocessor which has its ROMs configured

operate under the discipline of the DDCMP protocol.

It is organized

into five chapters and two appendices as follows.

Chapter

Introduction

Chapter

Installation

Chapter 3 - Device Registers and Programming Information
Chapter 4 - Detailed Description
Chapter

Maintence

Appendix A - PDP-11 Memory Organization and Addressing
Conventions

Appendix B - Integrated Circuit Descriptions

In this manual, the term DMC11 denotes the DMC11 Network Link
which consists of a microprocessor module and a line unit module.

Explicit references to these modules may Or may not be prefixed
by

the

term

DMC11.

The DMC11-AD Microprocessor module 1is designated M8200.

Where

the

carrier

computers

facilities,

synchronous

The

DMC11

DDCMP

line

the

systems
are

number

interfaces
to

transmission

using

speed

Extensive

firmware

detects

16-bit

are

protocol.

offered

with

instructions

result

throughput

speeds

and

delayed

PDP-11

the

interconnecting

Check

(CRC-16).

retransmissions.

messages

DMC11

over

hardware

greatly

longer

and

software

simplified.
required
time

implementing

the

protocol.

the

DMC11

the

processor

are

conventional

processor

when

duplications.

and

because

the

microprocessor.

memory

enhanced

implementing

automatic

omissions

common

209.

channel

that

combination

expertise

wasted

DMC11.

high

ensure

Programming

the

tasks.

with

and

Redundancy

headers

programming

priority

Cyclic

message

order

a
the

necessary,

require

not

when

communications

errors

208

via

interface

data

advantates

reliable

proper

implement

configured

connected

models

which

and

Bell

corrected,

can

remotely

using

numbers

delivered

such

protocol

located

DMC11s

protocol

DDCMP

Sequence

modems

ensures

The

Errors

are

has

operates
to

when
are

not

direct
at

high

perform

high

There are two versions of the line unit.

The M8202 high speed

line unit is intended for local network applications using coaxial cables.
at

bps

The M8201

The M8202 contains an integral modem that operates
56K

bps.

low speed line unit has no integral modem but contains

level conversion logic to interface with EIA/CCITT V24 or CCITT
V35 compatible modems at speeds up to

19.2K bps and 56K bps,

respectively.
2

The M8201
Stuff

and M8202

line units can operate with DDCMP and Bit

protocols.

The line unit is not a stand alone device.
a

DMC11

Microprocessor.

A separate manual
line

It must be used with

(EK-DMCLU-MM-001)

covers the M8201

and M8202

units.

The Microprocessor is a general purpose control unit providing

a full duplex parallel data interface between any PDP-11

central processor and a given DMC11 Line Unit.

processor/line unit combination,

family

With the micro-

computers can be configured in

many different network applications.

Where

the

computers

are

located at the same facility, DMC11s can be configured for high
speed operation

(56,000 or 1,000,000 bits-per-second)

inexpensive coaxial cable.

over

The necessary modems are built-in.

——
o
e, A+

Other

DMC11

Down-line

Ability

computer

(M8200)

features

system

include:

satellite

initialize

o—
S
53 s

computer

incorrectly

command

over

the

systems.

functioning
link

satellite

(Remote

Load

remote,

full

Detect).
®

Same

PDP-11

software

half

duplex

configurations.

Recovery

link

the

DMC11-DA

binary

NPR

serial

speed

modem

The

other

line

system

case

interfaces

M8201

failures

unit

directly

interface

the
is

because
to

used

both

Figure

1-1.

for

with

ends

data
the

the

from

data

the

Electronic
used

Shown

1is

commun-

DMC11

Industries
nearly

all

standard.

with

identical

local

synchronous

specification,

M8202

converts

compatible

function

however,

either

illustrated

interface

data.

manufacturers

unit

local

transfers.

line

format

RS-232C

low

this

losss

(DMA)

(M8201)

The

Association

overall

power

configuration

ications.
a

without

16-bit

typical

from

supporting

an
to

integral
that

built-in

coaxial

the

modem,

cable.

modem.

The

M8201.

the

M8202

w7075

(1028W)

~QDV

This

configuration

operation

(Figure

Figure
tween

two

1-2
the

coaxial

tain

full

defines

bit

output

dQuplex

addressed

The

unit

for

cable

for

half

duplex

full

duplex

operation.

the

general

interface

contains

bits.

The

most

unit

being

unit

INPUT

line

buses;

unit.

First,

input

one

separate

eight

the

buses

line

are

unit,

using

the

there

bus

used

the

beare

and

data

the

sus-

source

INPUT/OUTPUT

the

bits

Simultaneous

During

microprocessor

bit

read.

The

registers.

the

significant

bits.

three

any

Two

bus,

addressing

data

detail

bus.

the

into.

coaxial

microprocessor

uses

OUTPUT

and

operation.

which

other

greater

bus.

the

address

line

parallel

the

single
cables

microprocessor

eight

the

1-2).

other

uses

The

During

held

other
a

write

select

significant

the

addressing

line

the

operation,

uses

four

addressing

show

bits

that

bit

four

and

line

the

which

1line

uses

different
enabling

INPUT

select

operation,

uses

unit

read

three

microprocessor

most

low

OUTPUT

bit

and

written

buses

1is

possible.

The

remaining

and

control

data

strobe

bus,

the

information

signals.

control
to

the

signal
1line

interface,

unit

such

delivers
clock

timing

sync

and

L/IM

A.TAYOWTW
|

(0026W)
WIGOW

WOS04 O0Y
v
!
|

—~ @Q D W

1-7

Data

transfers

the

form

bus

cycle,

writing

UNIBUS

and

are

device
0-7

the

three

common

the

interrupt

(DATO)

The

between

CSR's

composed

accessed

addresses

are

indicating
consists

word

BSEL2

and

handshaking

CSR's

which

port.

data

This

the

port

program

(through

BSELO)

the

READY

BSEL4-7

1IN.

RQI.

completes

setting

4-7.

should

The

the

Similarly,

the

READY

The

data

etc...).

sets

and

addresses
These

Select

(BSEL)

SEL

BSELO

and

BSEL1,

BSELO

and

BSEL2

are

through

for

common

BSEL4-7

(SEL

4,6).

transfer

data

the

DMC11,

REQUEST

(RQI)

and

the

The
by

DMC11

the

data

responds

PDP-11

and

drops

NPR

(CSR's).

device

Byte

the

(DATI)

76XXX7.

are

through

loaded

takes

transfers

passed.

then

are

Registers

through

and

They

reading

bytes

consists

accessed

DMC11

bytes,

wishes

processor

program,

RDYI

SEL2

data

the

function

setting
and

which

exchange.

DMC11
OUT

PDP-11

then

eight

interlock

PDP-11

describing

clears

BSEL3,

the

referred

(SELO

PDP-11

Status

76XXX0

individual

transfers

and

henceforth

program

Control

the

transactions.

sequence,

DMC11

indicating

and

bus

are

for

When

DMC11

clear

transfers

(RDYO)

with

program,

RDYO,

data
a

after

the

function

reading

releasing

the

PDP-11

after

the

port

program

having

required

for

loaded

BSEL

registers,

further

use.

g mrn”

The DMC11-AD (M8200) is referenced as a microprocessor throughout
this manual as well as in other related documentation.

nts.
This is due to the fact that ROMs are used as controlling eleme
The ROMs act as compact logic arrays that replace a large amount

of distributive logic.

For example, a 2048 bit ROM is organized

as 512 words of 4-bits each.

512 words of 16-bits each.
and in unalterable.
same

the

produces

Combining four of these ROMs produces

Fach word in the ROM is pre-programmed

When addressed, a specific word always

output.

The information stored in the ROMs at the word level can be called / /
microsteps. Executing an appropriate series of microsteps 1is

—

called a microroutine.

It can represent a particular instruction

The combination of microroutines is called a

or function.

i
§

microprogram.
——
S
o

As the microroutine is being executed, the ROM output signals
are sent to the appropriate circuits 1in the microprocessor to

perform the instruction or function that is represented by the
microroutine.
5 @ MWEEFAT
.

WIS

o pen

St 1

As illustrated in Figure 1-3, the DMC11 essentially connects the
UNIBUS to the line unit interface through internal registers.

This allows the data to be processed by the microprocessor as it
passes between the two buses.

The processing is dependent on

the microprogram residing 1in the microprocessor.

Currently, a

microprogram is available to accommodate the DDCMP line protocol.
1-9

\
|

PROGRAM
COUNTER
T

CAOM

FUNCTION

SOURCE

ROM

UN/BUS

INTERFACE

Figure

1-3

ALY AND DATA

REG! S TERS

OESTINATION |
ROM

LINE UNMIT

INTERFACE

Microprocessor Simplified Block Diagram

The

block

hence

the

diagram

Figure

the

microprogram

microinstruction

then

which

perform on

control
the

registers

The

and

DMC11

microprocessor

are

available:

19.2K bps,
up

The

56K

local

The

DMC11-MA

feet

The

18,000

one

flow

address
and

1K of

ROM.

Certain
bits

for

determine
4

a processor,

a program counter

word.

Chapter

consist

foot

version

covers

and

with

two

cable.

(PC)

Each

bits
three

the

additional

what

operation

these

internal

1is

modules

ordered

synchronous
1M bps,

EIA/CCITT

operation

separate

Each

four

operation

remote

microprocessor

pad

line

local

with

V24

line

local

V35

unit

versions

operation

compatible

CCITT

separately.

modems

compatible

56K

modems

module

(hex SPC)

ROM

implementing

memory,

and

unit

module

operation

UNIBUS

(notched
1M bps

includes

the

DDCMP

300

nsec

protocol,

interface.

hex)

over

includes

coaxial

cable

built-in
up

6,000

length.

DMC11-MD

modem

microprocessor,

for

bit

resembles

bps.

scratch

modem

unit

operation

DMC11-AD

bipolar

residing

serve

local

and

It has

sixteen

data

much

detail.

line

One

remote

operands.

interconnected

bps,

very

term microprocessor.

addressing

ROM's

1-3

for

line

local

feet

unit

module

operation

(notched hex)
56K

bps

length.
1-11

over

includes

coaxial

a built-in

cable

Coaxial

cables

BCO3N-AO0

are

coaxial

One

for

full-duplex

required

not

included

cable

for

two

versions

use

the

same

conversion

cable

that

logic

V35

DMC11-DA

EIA/CCITT

V24

modems

their

DMC11-FA

V35

interface.

e <

100

operation

and

unit.

Optional

lengths

only.

two

required

are

Wttt
4 mtmr i o .

remote

line

Both

interface.

O
A

9 AW v ———

shipped

The

match

it SR

W TP

with

unit,

DMC11-DA

versions

accommodates

interface

The

o s

(M8201).

supplied
A
S
WISV

the

that

European

line

operation.

module

CCITT

[IRRPE——

The

either

——

The

the

available

half-duplex

EER—

and

with

contain

EIA/CCITT

V24

only

difference

specified

DMC11-FA,

level

the

and

interface

the

modem

interface.

]

foot

accommodate

BCO5C

cable

for

the

209

synchronous

cable

for

the

used

Digital

Data

Service

Bell

208

equivalent.

shipped
This

networks

and

with

synchronous
in

the

foot

BC05Z

interface

domestic

1-12

CCITT

certain
(DDS).

CHAPTER

INSTALLATION

2.1

SCOPE

This chapter provides all necessary information for a successful
installation and subsequent checkout of the DMC11 micro-processor
subsystem.

2.2

AND

UNPACKING

INSPECTION

The microprocessor/line unit system combination arrives at the
customer site in one of two ways, either as a part of a complete
computer system or as an add-on option.

When it arrives as an

add-on option, the microprocessor module, line unit module, and
associated mounting hardware and cables arrive packaged in a
Inspect the carton visually for any signs of

single carton.

Included in the contents of the carton are the

physical damage.
following.

M8200-YA Microprocessor

M8201

BCO08S-1

M8202

Cable

Line

Unit

Module

(Interconnects microprocessor and line

unit)

BCO5C-25 Cable

(M8201 EIA/CCITT V24 interface only)

BCO5Z-25 Cable

(M8201

H325 Test

12-12528 Coaxial Cable Test Connector

MAINDEC-11

Connector

CCITT V35 interface only)

(M8201

only)

(M8202 only)

DZDMC Microprocessor Basic W/R and Up Test

MAINDEC-11

DZDME

Line

Unit

DDCMP

10.

MAINDEC-11

DZDMF

Line

Unit

Bit

11.

MAINDEC-11

DZDMG

Jump

and

Free

12.

--=--

DEC/XII

13.

==--

ITEP

14.

EK-DMCUP-MM-001

Microprocessor

15.

EK-DMCLU-MM-001

Line

2.3

OPTION

There

only

one

and

protocol

only.

various

its

line

ROMs

2.4

MECHANICAL

unit
E

The

microprocessor

later,

the

installed
be

into

slot

Test

Unit

Manual

available.

configured

and

cables

are

implement

listed

any
a

microprocessor

hex).

DD11-C,

DD11-B

into

installed

(notched

Rev

Running

designated
the

Table

DDCMP

2-1

and

PACKAGING

consists

module

are

units

respectively.

DMC11

Line

Test

microprocessor

2-2,

The

One

Stuff

DESIGNATIONS

DMC11-AD

The

System

Test

These

DD11-D

module

must

DD11-C.

the

single

modules

The

remaining

plug

line

then

the

and

into

any

DD11-B

SPC

into

unit

slots.

(hex)

plug

equivalent

always

DD11-B,

module

system

either

module

Should
line

unit

may

two

line

unit.

slot

DMC11's

module

plugs

Table

2-1

Line Unit Option Designations
Option

Description

DMC11-DA

M8201 Line Unit Module with cable for EIA/CCITT v24
interface

DMC11-FA

M8201 Line Unit Module with cable for CCITT V35
interface

/"\

DMC11-MA

M8202-YA Line Unit Module with 1 Mbps integral modem
and

DMC11-MD

cable

M8202-YD Line Unit Module with 56 Kbps integral
modem

and

cable

Table

Line

2-2

Unit

Cables

Option
BCO3N-AO

Description

100

ft.

M8202

BC05C-25

BC05z-25

Line

ft.

Line

Unit

EIA/CCITT

cable

with

connectors.

Used

for

use

DMC11-DA

use

with

Module.

V24

cable

with

Unit.

ft.

Unit.

coaxial

CCITT

V35

cable

for

DMC11-FA

Line

The

the

slots

vicinity

DD11-B,

the

and

System

E,and

module

plugs

into

Unibus

cable

connector

and

short

that

are

installed

Unibus terminator
and

The

two modules

and

2.5

one-foot

are

BC(08S-1

General

Installation
done

installed

this manner

apart

from

the

line

also

both

(approximately
slot

the

in.)

2-1/2

connectors

A and

connector

40-pin

provides

Next,

with

third

checked

the

line

additional

and

combination

final

unit

and

DZDMC.

module

DZDME

and

confidence

1In

installed

MAINDEC-11

factor

for

the

involves

installation phase

the

stand-alone module

DZDMG which verifies

microprocessor

should

physically

MAINDEC-11

with MAINDEC-11

MAINDEC-11

the

unit

microprocessor

verified

unit.

The

execution of

status
v,

and

the

microprocessor

microprocessor.
the

over

PROCEDURES

operationally verified

DZDMR which

fits

cable.

First

checked

the

and

a BERG

microprocessor/line

phases.

then

in end

The

Interfacing Units.

Information

three

length

interconnected

PRE-INSTALLATION

2.5.1

and

connectors

in the

installed

and M8202

been

has

connectors

and

the

the M8201

allows

This

removed.

end

the

module

the corner of

a result,

not required.

B are

connectors A and

edge

so module

interface with the Unibus

not

line unit does

the operational

line unit

free

running

test.

Additionally,

this

test

checks

the

contents

the
—

ROMs

(microcode)

minimum

MAINDEC

Check

and

BRANCH

memory

instructions.

necessary

for

execution

the

diagnostics.

the

power

supply

microprocessor/line
+5

the

volt

supply

unit

insure

total

against

current

approximately

overloading.

requirements

Amperes.

The

for

the

Additionally,

the

;
—

line

unit

logic

and

requires
the

Installation

integral

requires

can

are

2-1/2

in.

hex

slot

while

either

backplane.
Rev
an

*15V

the

two

less.

silos

line

adjacent

input

DD11-C,

backplane

The

DMC11

unit

fits

microprocessor

higher,

equivalent

the

and

the

level

conversion

modem.

UNIBUS

the

The

for

that

SPC

slots,

terminator

slot

microprocessor

into

can

DD11-D

Hex

any

the

which

modules

requires

the

DD11

installed

the

DD11-B

the

backplanes.

PDP-11/04

Such
PDP-11/34

Computers.

2.5.2

Preinstallation

Before
must

installing
performed.

the

Checkout

Procedures

microprocessor

module,

the

—

full

slot

equivalent

used

one

following

functions

Verify

that

not

removed

factory

The

the

installed.

field.

automated
the

with

Verify

with

module

device

paragraph

BRS5

priority

that

switch

numbers

jumper

removed

testing
clock

address

only

should
at

inhibit

the

logic.

must

selected

must

selected

2.7.

address

paragraph

that

This

microprocessor

microprocessor vector

accordance

microprocessor

accordance

during

oscillator

jumper

2.8.

card

installed

position

E75,.

Verify
package

located

package,

and

Switch

switches

the

Run

and

Inhibit

position

and
E76

9
are

1-6

are

used

are

not used.

(RI)

for

the

both OFF.
the

switch which

vector

ground and the CLEAR input of the RUN flip-flop.
OFF

and

normal

sets

the

RUN

flip-flop

conditions,

the

RUN

immediately.
malicious

cannot

initialization of

flip-flop
Because

directly

internal

microcode during power

up,

switch
1In

this

address

connected

between

Normally,

cleared.

it 1is

Under

the microprocessor directly

which allows the microcode
of

DIP

to be

executed

malfunction or

execution

for

is possible

the

microprocessor
load

the

Inhibit

Switch
the

Switch

program

line

all

line

the

Byte

loaded.

the

maintenance

When

the

Processor

via

not

possible

Placing

the

RUN

the

flip-flop

Run
and

loaded.

(BS1)

application

set,

fault.

clears

Lockout

closet"

operation

Now,

position

Sel

PDP-11

Unibus.

determine

diagnostics

"computer

down

hang

diagnostics

allows

the

BS1

switch.

where

switch

from

all

link.

programs

prevents

preventing

DMC11

This

are

runaway

boot

switch

down

inhibits

functions.

NOTE

The

M8200

M8201

and

| \

Before

installing the microprocessor

remove

the

NPR

Grant

pins

CA1

and

CB1

that

going

the

wire

for

the

line

unit

M8202

Line

power

requirements.

The

local

DMC11

DMC11-MD

Line

that

M8200.

slot

that

the

Do
is

slot

not

going

M8202).

one

load

the

Unibus

and

load

the

Unibus

except

(DMC11-AD
bus

between

for

the

(M8201

requires

runs

backplane

present

configuration
Unit)

the

presents

Units

for

the

remove

Microprocessbr

wire

(M8200) ,

Microprocessor

placement

nearest

and
to

the

DMC11-MA

the

NPR transactions
of
te
ra
gh
hi
e
th
to
e
du
is
is
Th
r.
so
es
oc
PDP-11 Pr
it (1 Mbps)
Un
ne
Li
-MA
3%1
DMC
e
th
e,
pl
am
ex
r
Fo
.
ed
ir
qu
re
that are
ery 8us .

requires an average of one NPR ev
INSTALLATION

edures in

ut proc
After completing the pre—installation checko

2.6

ion
paragraph 2.5.2, proceed with the installat

as follows.

per backplane

pro
1. Insert the microprocessor module in the
slot.

ion of the

operat
2. Run MAINDEC-11 DZDMC to verify correct
microprocessor.

DIAGNOSTIC NOTE

ng a

1f the installation is in a system usi

t does
PDP-11/04 or other PDP-11 Processor tha
switch
not have a switch register, a software
r the same

er is
switch options. If a switch regist
7), the
available but contains all 1s (17777
Refer to
software switch register 1is used.
nt for

the appropriate diagnostic docume
further details.

Check

all

appropriate

the

line

Chapter

unit

module

switch

settings

accordance

INSTALLATION

the

and

with

line

jumpers

the

unit

recommendations

manual

(EK-DMC11LU-MM-001)
.

Insert

the

line

Interconnect

BC08S-1

cable

mating
an

the

which

with

unit

line

H856

male

connector

unit

the

and

one-foot

female

connector

H854

module

long

the

M8202

the

M8201,

install

the

other

end

the

this

the

and

M8201

Line

BCO5C-25

cable,

end.

mylar

The

this

J1.

flat

cable

microprocessor,

designated

and

each

using

unit

the

slot.

line

designated

conductor

microprocessor

connector.

backplane

microprocessor

connectors

the

proper

Unit

cable

connect

Line

Unit,

H325

J1.

connector

the

J1.

test

connector.

the

which
two

M8202,

ties

3-foot

the

within

the

install

two

cables

M8202,

the

12-12528

coaxial
are

check

pigtails

soldered

that

specifications.

the

Refer

2-10

coaxial

together.

the

integral

the

test

connector

These

M8202.

modem

line

clock

unit

manual.

ly voltages are

pp
Oon the backplane, check that the su
s.
within the following tolerance

Backplane

Voltage

Min
+4.75
-14.25
+14.25

Pin
C1A2
C1B2
C1U1

Max
+5.25
-15.75
+15.75

Nominal
+5.0
-15.0
+15.0

/""\A

rect line

Run MAINDEC-11 DZDME and DZDMF to verify cor
unit operation.

—~

10.

e unit/
Run MAINDEC-11 DZDMG to verify correct lin
also tests
microprocessor operation. This diagnostic
.

the microcode and BRANCH instructions

11.

Remove the test connector.

25 cable

For the M8201, connect the BCO05C-25 or BC05Zto the customer supplied modem.
CAUTION

The maximum allowable length for the
BC05C and BCO052 cables is 50 feet.

2-11

For

the

M8202,

connect

coaxial

cables

the

pigtails

optional

100

the

foot

customer

BCO3N-AD0

cable.

2.7

DEVICE

2.7 .1

ADDRESSES

Introduction

Starting

with

assigned

floating

devices

are

used

2.7.2
Floating

the

DJ11,

new

communications

addresses.

The

devices

addresses

for

are

current

production

retained.

system.

Floating

Device

device

addresses

The

floating
extends

The

devices

are

DuU11,

introduced
Same

type

are

address

and

DQ11,

Address

must

assigned

Space

location

DMC11,

assigned

follows:

location

(octal

order

and

production.

starts

764000

assigned

DUP11,

into

Assignments

then

designations).

type:

the

Multiple
contiguous

760010

DJ11,

DH11,

device

devices

addresses.

the

The

first

modulo

address

108

modulo

left

the
be

left

that

any

left

type

contains

device

10_

one

list

that

the

last

The

device

the

DH11

type

the

has

must

gap

not

and

must

used,

equivalent
assigned

DH11

device

bus-

boundary,

device.

used.

four

the

type

start

address

because

modulo

address

must

one

starting

boundary

the

after

device

if
a

gap

indicate

follows.

devices

can

inserted

ahead

device

list.

additional

system,

they

original

devices

must

devices

type

devices

make

room

The

type

The

last

following

nothing

new

the

for

208

the

address

device

should

starting

8’

between

first

the

registers.

new

registers.

eight

gap

boundary,

addressable
must

already

for

following

assignments

the

list

assigned

are

contiguously

the

same

type.

the

system

added

after

Reassignment

may

show

typical

required

communications

2-13

floating

devices

the

additions.

examples

for

the

device
system.

other

Example

DJ11s,

DH11s,

DQ11s,

DUP11,

and

1DMC1.

j
“M——

760010

DJ11

gap

760020

DH1
1

first

address

760040

DH11

first

address

760060

DH1
1

gap

760070

DQO11

first

address

760100

DO11

first

address

760110

DO11

gap

760120

DU1
1

gap

760130

DUP1
1

760140

DUP11

gap

760150

DMC11

760160

Indicates

first

address

first

address

DMC11s

and

other

DUP11s,

devices

follow.

Example

760010

DJ11

760020

DJ11

gap

760040

DH11

760060

DH11

gap

760070

DQO11

760100

DJ11,

DH11,

first

address

first

address

first

address

DQO11

first

address

760110

DQ11

gap

760120

DU11

gap

760130

DUP11

first

address

2-14

DQ11s,

and

DMC11s

Example

(Cont.)

760140

DUP11

760150

DUP11

gap

760160

DMC11

760170

DMC11

760200

Indicates

first

address

first

address

first

address

DMC11s

and

other

devices

following.

2.7.3
In

Device

the

floating

always

PDP-11

memory

are
With

the

The

device

switch

address

located

are

used.

address

bit

numbers

are

(Figure

2-1).

the
the

address

bits

13-17

Appendix

addressing

line.

selection

package

switches

processor).

and

(closed),

address

and

PDP-11

switches
on

(760010-764000),

shows

conventions.

decoding

logic

decoder

looks

for

Bits

and

are

the

Bits

3-12

(Table
on

2-3).

the

decoded

registers.

package

positions

Unibus

space

organization

switch

associated

Selection

address

(function

selected

select

Address

the

The
is

position

correlation
shown

switch

rocker

switches

type

are

E113.

contained
All

between

numbers

and

switch
The

numbers

are

marked

the

and

pushed

the

DIP
in

2-3.

one

switches

Table

are

and

OFF

package.

desired

the

The

position

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Table

Guide

Switch
Bit

No.

2-3

for

Setting

Switches

Select

Device

Address

Device

Address

760010
760020

760030

760040

Vg
X

760050

760060

760070
760100

760200

'
X

760300

760400

760500

760600

760700

761000

762000

763000

764000

NOTES
:

means

Switch

switch

off

(open)

numbers

are

physical

respond

positions

2-17

logical

switch

the

package

Unibus.
1.

2.8

VECTOR

2.8.1

ADDRESSES

Introduction

Communications

This
for

devices

eliminates
the

the

maximum

are

assigned

necessity

number

each

floating

assigning

device

vector

address

that

can

addresses.

absolutely
used

the

system,

2.8.2

Floating

Vector

vector

addresses

The

floating

proceeds

Address

are

assigned

address

upward

Assignment

space

777.

follows:

starts

Addresses

location

500-534

300

and

are

reserved.

The

devices

DL11-A,

are

assigned

DP11;

DM11-A;

PA611

Reader;

DJ11;

DH11;

GT40;

DUP11;

DV11;

type

any

must

move

type:

DM11-BB;

DT11;

VT20;

DX11;

DQ11;

DC11;

DR11-A;

DL11-C,

KW11-W;

KL11/
DR11-C;

DU11;

DMC11.

additional

they

order

DN11;

Punch;

LPS11;

device

assignments

PA611

not

devices

already

the

same
in

fill

are

assigned

used

the

added

address

the

systenm,

after

the

original

Reassignment

system

2-18

system,

vacancies.

contiguously

type.

may

other

required.

type

2.8.3

Vector

Each

drive

(two

words)

Address

interrupt

which
is

The

address

octal

number

end

and

bit

vector

seven

or
2

that

using

(2-8)

only

specified

Unibus

addresses

data

and

least

4).

The

bits

are

the

four

address

even-numbered

vector

determines
(0

requires

all

bits

address

bits

vector

implies

constraint
vector

Selection

0-8.

not

end

octal

the

(they

control

processor

further

binary-coded,

Because

specified

interrupt

digit,

significant

PDP-11

addresses.

must

three

locations

vector

are

digit
logic

represent

must

always
of

the

send

only

the

vector

address.

The
in

DMC11
the

shipped

interrupt

addresses:

RDY

form

XX0,

and

XX4.

For

this

the

digits
3-8
on

The

logic

(Table

the

control

I
RDY

not

2-4).

vector

generated

address
in

the

This

generate

the

The

are

associated

selection
position

vector

addresses

two

line;

E76

vector

state
most

are

(Figure

the

switches
a

switch

data

2-1).

lines

generated
ON

(closed),

one

line.

contained
Only

form

selected

octal

switches in the package are used for the vector address.

2-19

significant

the

Unibus

bit

vector
the

addresses

(open),

with

switches

installed

two

the

OFF

card

generates

determined

switch

data

selection

logic

generate

operation,

address

Unibus

priority

logic.

switch.

With

located

BRS5

interrupts

method

associated

package

interrupts

the

vector

with

DIP

the

The

correlation

between

Table

2-4.

The

marked

the

package.

pushed

the

desired

2.9

The

and

INSTALLATION

following

features

Power

numbers

the

switches

are

rocker

The

switch

type

shown

numbers

are

and

are

the

important

position.

concise

checklist

installation.

Requirements
+5V

4.0

M8201

+5V

3.0

+15v

0.03

-15v

0.31

+5v

3.0

+15Vv

0.18

-15vVv

0.46

Unibus

M8200

presents

one

Unibus

loads.

present

Special

Installation

bit

and

M8200

The

and

positions

represent

DMC11

M8202

OFF

numbers

CHECKLIST

items

the

switch

Unibus

Microprocessor

Before

installing,

that

runs

The

M8301

and

M8202

Requirements

M8200

wire

load.

remove

between

the

pins

NPR

CA1

Grant

and

CB1

continuity

the

backplane
-—

Guide

Switch

Bit

for

Switch

Setting

No.

Table

2-4

Switches

Select

Vector

Address

Vector

Address

300

310

320

330

340
350

360
370

400

500

600

700

Notes:

means

switch

off

(open)

numbers

are

physical

produce

logical

the

Unibus.
2.

Switch

positions

switch

package

for

the

system

wire

must

M8200
or

slot

that

change

going

requires

removal

the

M8200.

the

M8200,

replaced.

Microprocessor

configuration

closest

with

Local

Line

Units

(DMC11-MA

the

must

PDP-11

placed

Processor

the

because

Unibus
of

the

rate of NPR transactions that are required.

M8200

the

DMC11-MD)

This

placed

before

Microprocessor

Address

Switch

DB11-A

Switch

Selection

Bus

Repeater

high

It must alsuu/

one

used.

Settings

(E113)

No.

Address

Bit

_
6

Switch

OFF

(open)

Switch

(closed)

to
to

respond
respond

to
to

logical
logical

on
0

Unibus.
Unibus.

Vector

Selection

Switch

No.

Vector

OFF

(open)

Switch

(closed)

produce

Remaining

Switches

E76

Switch

RUN

Switch

BYTE

Unit

Shipped

Switch

(2)

and

Switch

(1)

Bit

Switch

Switches

Line

(E76)

produce

INHIBIT

SEL

(RI)

logical

and

should

LOCKOUT

(BS1)

are

not

used

and

Settings

and

Jumper

and

should

the

Pack

M8202)

Switch

Pack

M8202)

All

No.

(E87

switches

No.

(E88

switches

should
be

should

M8201

should

and

E90

E91

OFF.

and
OFF.

OFF.

Configuration

M8201

Unibus.

OFF.

Settings

Switch

Unibus.

OFF.

(3)

The
2-2.

Switch

Pack

M8202)

shown

jumpers

No.

The

(E26

switches

Figure

should

M8201

should

and

E29

positioned

2-2.

configured

shown

Figure

Switch

DMC11-DA

DMC11-MA/MD

M8201

M8202

OFF

ourT

ouT

ourT

Jumper

No.

DMC11-FA

No.

Not

Present

Not

Present

OUT

(FD)

(HD)

and

E29

NOTES
:

Switch

pack

no.

located

E26

M8201

M8202.

Full

Duplex

Half

Duplex

Figure

2-2
Switch

Configuration

Pack

Line

No.

2-25

Jumpers
Unit

and

\.,./

CHAPTER

PROGRAMMING

3.1

INFORMATION

INTRODUCTION

This

chapter

programming
is

contains
of

presented

the

DMC11

transfers,

Unibus

control

status

registers,

etc.

and

information

categories

Also

status
and

line

this

information

Microprocessor.

operational

output

The

general

included

registers,
unit

chapter

such
are

input

and

status

follows.
Para.

Vectors

3.2

Priority

Selection

3.3
Information

3.4

Introduction

3.4.1

Unibus

Control

Input

Transfers

and

Status

Transfers

Registers

3.4.2
3.4.3
3.4.4

Initialization

3.4.5

DDCMP

3.4.6

Start

Data

Transmission

3.4.7

Data

Reception

3.4.8

Control

Out

Transfers

the

and

registers.

Interrupt

Output

control

3.1

Programming

information

transfers,

Introduction

PDP-11

the

descriptions

arranged

Description

for

general,

microprocessor

control

necessary

3.4.9

No.

Description
Maintenance

Messages

Remote

Detect

Power

Load

Fail

Microprocessor

Line

Unit

3.2

The

Para.

3.4.10

and

Down

DMC11

and

Status

generates

two

vector

addresses:

(microprocessor

output

addresses

the

interrupts

XX0

port

and

3.3

priority

via

plug-in

PDP-11)

XX4.

The

address

XX0

occurs

and

the

SEL6)

(RDYI)

address

data,

Interrupt

PRIORITY

vector

form

Ready

with

The

that

(SEL4

interrupt

port

the

generate

input

(BDP-11

addresses

interrupts

conditions

to
the

form

generate

that

initiate

are:

asserting

interrupt

the

3.5

VECTORS

XX0;

XX4

Registers

3.6

interrupts

3.4.11

3.4.12

microprocessor)

vector

Load

Registers

INTERRUPT

and

Line

Recovery

Cnontrol

No.

the

and

XX4

Out

the

PDP-11

microprocessor

Interrupt

occurs

microprocessor

Enable

when

when,

Enable

after

asserts

requests

responds
In.

(IEI).

charging

Ready

Out

the

(RDYO)

(IEO).

SELECTION

for

the

interrupts

priority

establishes

BR5

selection

the

selectable

card.

priority

level.

the

shipped

microprocessor

with

card

3.4

PDP-11

3.4.1

PROGRAMMING

Introduction

Programming

the

DMC11

describes

how

registers

together

and

status

PDP-11

order

familiar

are

handled

with
by

the

protocol

the

communicate

implementation

should

DDCMP,

for

and

transfer

describes

details

these

formats,

details

and

program

unusual

the

DDCMP

useful

error

different

the

not

protocol

necessary

some

provided
computers.
which

programming

the

protocol

These

familiarity

interpreting

two

DDCMP

and

DMC11

operation.

However,

interface,

person

consult

protocol

counters
the

device

control

cases.

DMC11,

microprogram.

level

status

level

connecting

with

system

control

first

the

various

circuit

DMC11

The

and

operation

the

levels.

program

details

DMC11

the

interrupt

transfer

the

two

PDP-11

second

data

uses

between

successfully

significance
quality

the

including

initialization,

described

program

with

The

transactions,

the

information

microprogram.

with

INFORMATION

the

assess

uses

the

DMC11
a

software

standard

document.

3.4.2

Unibus

Control

Communication

and

uses

the

(CSR's).
76XXX4,

DMC11

These
76XXX5,

and

control

are

eight

Status

and

status

bytes

addressed

76XXX6,

and

Registers

information

control

76XXX0,

76XXX7.

and

between

status

76XXX1,

These

device

the

PDP-11

registers

76XXX2,

76XXX3,

addresses

are

subsequently

for

referred

indicating

SEL6

for

individual

indicating

Byte

bytes

Select

and

SELO,

(BSELO

SEL2,

BSEL7)

SEL4,

and

—

words.

NOTE

The

Control

and

implemented

(RAM) .
up

Status

with

Thus,
random

Registers

Random

power

states.

Access

on,
As

Memory

the

part

CSR's
of

microprocessor initialization,
(SEL0-6)
of

bit

lower

cleared

order

cleared
the

are

SELO

(RUN)

bits

first,

Due

microprocessor,

cleared

before

with

the

come

the

the CSR's

set.

(BSELO)
high

The

are

speed

registers

are

access

data

port

that

and

the

PDP-11.

the

microprocessor

the

exception

which

SELO

are

PDP-11

possible.

BSEL4-7

comprise

between

the

information
Input

Output

which

from

Transfer,

confused
are

reception.

bit

microprocessor

Transfer,

information

the
often

abbreviated

the

microprocessor

often

with

called

PDP-11

abbreviated

sending

and

used

The

the

PDP-11

OUT

receiving

transmission,

data
and

informationuwj

transfer

1I.

pass

called

transfer

These

called
terms

the

are

serial

receiving

not

line

BSELO

controls

input

BSEL1

contains

bits

concern

which

can

not

PDP-11

the

program

functions

from

BSEL1

initialize

reference

for

each

are

3.4.2.1
This

CSRs

controls

output

maintenance

purposes

which

the

clearing

which

the

also

shown

RUN

PDP-11

Input

comprises

3-1.

are

MASTER

module

CLEAR

prevents

other

no
bit

BSEL?2

the

maintenance

microprocessor's

computer

bit

transfers.

microprocessor.

the

tabular

the

performing

disable

Figure

DMC11

microprocessor

would

contains

the

programmer,

shown

BSEL2

unattended

BSELO

for

and

initialize

switch

Unibus

used

programmer.

used

used.

transfers

ability

system.

assignments

detailed

for

the

description

form.

low

byte

address

76XXX0

(Figure

3-1).

Bit
0,

Name
TYPE

(TYPE

INPUT

Description
These

bits

transfer
Bit
0

define

Bit
0

the

type

input

follows.
0

Buffer

Address/

Character

(BA/CC

Control

Reserved

Base

Count

(CNTL

(BASE

1I)

o69y9/|1/°2/B)o\e|7DQ058|iAt0g|W/‘iItmS|He2T77o5N08e|VTL1TINT|D0|S8LTYW)FNOESV/)).|Tk|2O42
\|&A99gswm9_1rq%\i9w//emH5\E-\],/\\A.,0\\\Nw//\\&.\>S\@iQ&\xSg\k9nAg\mN_SVSWi\ITsa&Y.Y0\qRoaY¢\\y0A\1S|Y\\I\NmY0\2/7\7wS\Smb7Ij\>Y\~Oi\H\%:\\Lo\z\aSd\N|@R|N292*
N\ — N

SN/EIN/DTIOyLNIODNTONYDSNdLVOLSSLSUHW¥YIOFSLS/OTY
A1R AAR7 A, es-e ATNAN
9

w's

3-6
JJ

a—

77777777
Ro

SE, AND CNTL F

E————

DDDDDDDDD

1111111

Figure
3 -1

©Unibus Cont
andr
Stao
tus l
Reg isters

3.4.2.4

BSEL3

Reserved
."
f«";‘

3.4.2.5

»."’"

Data gd}t Message Formats - The dagx'port is representeé/fl

by addressi§/76xxx4 and 76XXX6.

The firnghalf of the port is

76XXX4"}KECh includes BSEL4 and BSEL?X”

The second half of/the

port isx76XXXG, which includes BSE%K/and BSEL7.
,’

The port is loaded by the Pbgf{i/on input transfersg‘nd by the
/

type

(TYPE

TYPE

0).

In discussing/éhe data port messagelfibrmats,

it is

sometimes more

convenient/yé use word designatii?‘ (SEL4 and SEL6) than byzé
!

designatigns (BSEL4-7).
/

;r.

/
/

)

There¢ are four formats:
/’

///

Buffer Address/cgflgacter Count Input and O&tput (BA/CC I and
BA/CC O) Formapf;
The formatsalgr BA/CC I and BA/CC O are the same (Figure 3-1).
SEL4

contains

18-bit

this

buffer

the

least

address.

address

are

significant
The

two

ccntaiqéd

most

bits

(0-15)

significant

and

the

bits

(16

SEL6.

and

17)

The

remaining 14 bits (0-13);5f SEL6 contain the character count in
/

ppsitive notation, not 4'8 complement notation.
Lo

Bit

Name

TYPE

(Cont.)

(TYPE

Description

INPUT

1I)

Each

(Cont.)

these

detail.

Buffer

Utilized

the

with

PDP11
to

use

18-bit

for
bus

character

The

the

Control

(BSEL

the

4-7)

the

protocol

use

from

purpose
and/or

This

transferring
a

14-bit

microprocessor.

used

the

expressed

number.

When

must

port

and

the

binary

positive

Count

(RQI).

data

address

count

requests

explained

microprocessor

character
a

purposes

count

for

REQUEST

4-7)

Address/Character

request

(BSEL
an

transfers

with

data

RQOI,

port

microprocessor
transferring

process

control

information.
10

Reserved

Base

address

which,

requests

from

the

when
the

provides

used

with

ROTI,

microprocessor

use

data

purpose

transferring

18-Bit

Base

Address

(power

fail)

bit.

port

(BSEL

and

4-7)
to

RESUME

base

the

for

the

Bit
02

Name

Description

I/0

Defines
Input

the

Flags

(receive)

For

example,

new

BA/CC,

need

etc.)

Output

BSEL

4-7

buffer

for

Set

the

PDP-11

message

would

this

out,

contained

whether

transferred

for

(transmit).

microprocessor

knowledge

block

the

(BA/CC

was

received.

RESERV ED

REQUES T

(RQI)

transfer.

the

data

serves

Cleared

has

used

port

(BSEL

been

request

interlock

request

4-7)

use

order

data

program.

The

RQI

bit

transfer

from
is

input

PDP-11

bit

the

bits

type

the

loaded.

when

This

bit

which

the

data

transfer
the

PDP11

accompanied

defined

bits

2:0.

INTERRUPT

ENABLE

When

set,

allows

the

microprocessor
L]

INPUT

(IEI)

vector
RDY

interrupts

XX0

having

set

Bit

Name

READY

Description

(RDY

1I)

This

RQI.

the

microprocessor

When

PDP11

This

asserted,

program

the

bit

data

indicates

proceed

with

port

(BSEL

4-7).

cleared

microprocessor

response

the

the
end

input

MASTER

CLEAR

transfer.

3.4.2.2

This
and

CSR
is

PDP-11

all

BSEL

only

and

control

MASTER

CLEAR

for

normal

user

All

functional

the

functions

high

byte

These

bits

MICRO-

are

BSEL

between

functions

LOCK

OUT

76XXX0

the

override

however,
set.

This

(Figure

3-1).

Description

This

bit

when

set

PROCESSOR

processor

(STEP

cycle,

composed

pulses.

The

cleared

before

MP)

than

read/write;

address

Name

STEP

other

communications

microprocessor.

functions.

maintenance

the

comprises

Bit

all

intended

program

Maintenance

contains

not

other

function.

steps

through

one

RUN

the

micro-

instruction

five

flip-flop

executing

nsec

clock

should

this

control

Bit
9

Name
ROM

INPUT

Description
(ROM

When

set,

BSEL

6-7

ROM

(ROM

OUTPUT

directs
as

the

executed

STEP

When

Set,

modifies

for

BSEL

the

addressed

4-7

LINE

(LU

UNIT

LOOP)

LOOP

This

out

back

done

its

source

the

contents

paths

executed

when

LOOP

STEP

and

shifted

approximately

RUN

the

Kbps

the

EIA

LOOP

before

level

UNIT

LOOP

the

clock

data

out

in.

RUN

set

data

rate.

connector

free

This

cleared,
only

line

in.

LINE

and

the

set

serial

level,

back

not

TTL

asserted

line

shifting

end

serial

for

when

units

When

clock

loop

the

set

the

line

and

clocked

H325

microprocessor

CROM

the

set

available
When

microinstruction

function

conversion.

STEP

asserted.

control
the

bit

asserted.

connects

contents

the

when

microinstruction

the

cable
mode,

running

the

installed

with

RUN

data

clock

1is

Kbps.

;
N

3-10

Bit

Name

LINE

(Cont.)

(LU

UNIT

LOOP)

Description

LOOP

The

(Cont.)

require

cables

STEP

LINE

(STEP

UNIT

LU)

unit

the

This

RESERVED

MASTER

CLEAR

the

loop

back.

operates

the

set,

both

the

this

case.

function

used

RUN

the

MASTER

enter

This

CLEAR

bit

the

controls

bit

also

CLEAR

set

and

shifts.

and

the

line

cleaning.

enabled

asserted.

temporarily

allowing

idle

the

shifts,

initializes

self

clock

flip-flop
PC

When

receiver

microprocessor

RUN

LOOP.

tranmistter

microprocessor

MASTER

This

rate

the

When

clock

The

modem

with

negated,

CROM's

adapter

provide

when

RUN

coaxial

units

pig-tail

conjunction

the

line

unit

control

unit.

Kbps

line

integral

asserted,

12-12528
at

and

installed

line

—

Mbps

the

The

and
The

cleared

microcode

state.

microprocessor

BUS

clock.

initialization

Bit

Name

(Cont.)RUN

Description

(Cont.)

MASTER

CLEAR

microprocessor
cleared

for

switch

(BS1)

RUN

from

which

enables

clock.

RUN

maintenance

being

program

processor

malfunctions.

Chapter

INSTALLATION

information

when

concerning

which

microcode

can

states.

provided
cleared

the

prevents

runaway

micro-

Refer

for

the

BS1

switch.

3.4.2.3

This

BSEL

transfers

contains

from

the

comprises

Bit
0,

Output

control

information

microprocessor

the

low

byte

the

TYPE

(TYPE

OUTPUT

PDP11

address

Name

relative

output

program.

76XXX2

This

(Figure

3-1).

Description
These

bits

are

data

the

Bus

Control

Reserved

3-12

encoded

transfer

PDP11

from

for

the

type

—’

microprocessor

program.

Address

and

Output

Character

Count

Out

Bit

Name

ouT

I/0

Description

OUT

I/O

for

Input

For

example,

BA/CC,
to

defines

(receive)

the

know

received.

bit

Flags

BSEL4-7

contained

would

was

block

Input

indicated

and

output

this

bit

indicated

when

When

the

want

set

etc.)

(transmit,.

output

this

(BA/CC

Output

PDP111program

whether

completed

this

the

message

when

cleared.

RESERVED

INTERRUPT

OUTPUT

ENABLE

(IEO)

asserting
to

READY

(RDYO)

OUTPUT

set,

RDYO,

vectors

when

asserted,

bit,

that

BSEL4-7

bits

cleared

the

upon

interrupt

XX4.

This

microprocessor,

port

contain

0-2.
by

the

data

This

bit

PDP11

has

data

indicates
as

must

program

been

defined

be
after

sampled.

3.4.2.4

BSEL3

the DMC11

is used
data

Line

Number/Priority

is used

to designate

a multiple

line controllerfffhis

line numbers

and to assign,fifiority for bldéck

transfers.

This register comprises the high byte of address 76XXX2/1Figure
3-1).

S
ffi.f

Bit

Name

8-13

LINE NUMBER

_//

| ’

’

A’
‘fi

\V/

afe designated for line

during

format

transfers.

used

line

controller.

These

bits

of data

{i/// o

assign

priority

blocks

for transfer via the DMC11

microprocessor when it is used as a

multiple line controller.
-

The

smultiple

PRIORITY

-i

.
o
.
\
, DMG11 microprocessor is

/./

line number bits are required when the

14,

]

gfieficziption

Thege bits
numbédrs

/f'"

)

especially

‘

useful

when

This 1is

lines

fivj

different speed are used.
/,

3.4.2.5

The

data

first

The

Data

port

half

second

Port

1i1s

represented

the

half

Message

port

the

Formats

addresses

76XXX4

port

which

76XXX6

BSEL7.

76XXX4

includes

which

and
BSEL4

includes

76XXX6.

The

and

BSELS.

BSEL6

and

._/j
3-14

1.4.2.4

BSEL3

1.4.2.5

Dhata

- nfiserved

Port

Message

Formats

Ly addresses 75xxx§ and 76XXX6.

The

data

port

represented

The first half of the port {is

715XXX4, which incl&dén BSEL4 and BSELS;

The lecon@ half of the

port is 76XXX6, which includes BSEL6 and BSEL7.

The

port

loaded

the

microporcessor

The

format

contents

tyope

(TYPE

and

discussing

convenient

designations

There

are

BA/CC

The

the

data

the

port

depend

the

transfer

’

port

use

word

designations

message

formats,
(SEL4

and

sometimes

SEL6)

than

byte

formats:

Count

Input

and

Output

(BA/CC

and

Format

for

contains

buffer

BA/CC

the

and

least

are

bits

notation,

BA/CC

The

two

contained

(0-13)
not

significant

address.

address

remaining
positive

(BSEL4-7).

this

and

O).

Address/Character

18-bit

transfers

transfers.

data

formats

SEL4

TYPE

on' input

the

four

Buffer

éutput

PDP-11

‘

2's

SEL6

are

the

bits

most
bits

(Figure

(0-15)

significant

the

bits

(16

and

contain

the

character

complement

same

notation.

SEL6.

3-1).

andl?)
The

éount

stack a maximum of seven BA/CCs each for

The microprocessor can

This number is based on the size of the core tables

and output.
(BASE)

For

the

input

PDP-11

which

memory,

BA/CC

operations,

limited

supplies

256

bytes.

new message

buffers

the

microprocessor.

For

output

that were

operations,

successfully

BA/CC

returns

transferred

buffers

the

PDP-11

the microprocessor.

Base Input (BASE I) Format
SEL4

and

bits

and

SEL6 provide

reserved block of addresses
block

size

256

within

the

Bit

PDP-1l1

assigned

block.

SEL6

microprocessor

the
of

called

the

base

functions

shown

base

the

address

(Figure

3-1).

BASE

address

not modify

any

bit

table

and

protocol.

cleared,

specified

The

the

locations

this

operation

the

the
If

set,

contents

table.

Input

CNTL

resumes

first

PDP-11 memory

program must

the

assigning

RESUME.

initializes

microprocessor

Control
The

in the

Upon

bytes.

the

mioroprocessor,

(CNTL

format
(Figure

Format

provides
3-1).

The

means

control

implementing
bits

are

located

below.

Name

Description

Reserved

certain
in

control

SEL6

DDCMP

Maintenance

(DDCMP

MAINT)

With

this

sor

enters

the

DDCMP

mode

where

remains

bit

subsequently

set,

the

microproces-

maintenance
until

initialized.

Reserved

DDCMP

Half

(DDCMP

Duplex

With

HD)

DDCMP

Secondary

(DDCMP

SEC)

cleared,

DDCMP

with

bit

With

this

DDCMP

selected.

full

half

With

duplex

This

bit

set,

DDCMP

duplex

this

bit

operation

must

used

1l1.

bit

half

secondary

station

operation

selected.

With

bit

DDCMP

duplex

full

set,

half

operation

12,

bit

operation

this

cleared,

primary

selected.

duplex

station

Not

used

for

duplex.

Reserved

Control

The

Output

CNTL

program
PDP-11

SEL4

(CNTL

Format

format

provides

error

conditions

program,

and

bits

format.

The

(Figure

3-1).

means

involving

communications

and

control

bits

SEL6
are

informing

the

hardware,

DMC1ll

channel,

contain

the

located

the

remote

address

SEL6

PDP-11

shown

station.

this
below

—

Description

Name

—Bit
Data

When

Check

(DATA

this bit

set,

that

has

been

indicates

that

threshold

retransmission

CK)

indicates

exceeded.

Time

when

Out

bit

this

set,

received

microprocessor has

PaammaN

Overrun

(OCRUN)

for

When

set,

remote

end of

the

seconds.

link

message

the

from

response

the

this

was

bit

indicates

received

but

receive

1it.

available

When

this

that

buffer

DDCMP

Maintenance

Received
MAINT

(DDCMP

RECD)

set,

message

the

format

has

been

device

must

the

Lost

Data

Wnen

this

set,

received
supplied
and

Reserved

the

and

that

reinitialized
state.

bit

message
buffer.
device

that

The

messacge

indicates

that

longer
is

the

enter

lost.

1is

set

This

must

maintenance

received

bit

this

indicates

DDCMP

maintenance

caused

bit

than

fatal

that

the

the
error

reinitialized.

Disconnect

When

set,

this

on-to-off

Data

DDCMP

Start

Received
START

(DDCMP

Set

indicates

transition

the

modem

lead

has

been

detected

has

been

started.

the

data

link

When

set,

this

bit

the

that

Ready

after

DDCMP

RECD)

bit

Start

indicates

messacge

protocol

was

This

must

initialized

fatal

that

was

received

when

the

running

state.

error

and

the

device

following

its

occurence.

Nonexistent
Memory

(NON

When
EX

set,

Unibus

MEM)

this

bit

address

indicates

timeout

This

must

initialized

When

set,

fatal

error

has

and

that

occurred.

the

device
7

PROCEDURE

(PROC

ERROR

ERR)

PDP-11

bit

indicates

that

progoram

has

verformed

This

fatal

the

Input

Whenever
by

the

PDP-1ll1

the

port

its

must

occurence.

the

error

initialized

occurence.

Transfers

data

port

microprocessor

the

error.

device

following

3.4.3

its

this

procedural

and

following

—

program

before

not

use,

for

use

must

request

proceeding

with

the
an

output

subject
transfer.

microprocessor
input

transfer.

being

seized

Therefore,

to
It

assign

must

also

specify the type of input transfer

(a transmit buffer, a receive

buffer, control information, etc.) so the microprocessor can make
appropriate preparations.

The PDP-11 program should set bits fg-2 of BSELF to indicate the

the port.

(RDYI), when the

Ready In

When RDYI has been

port has been assigned to the PDP-1l1l program.

the PDP-1l1 program should load the desired data into the

data port

(BSEL4-7);

which completes the transfer.

microprocessor has
program to have

The microprocessor

cannot

immediately.

1In

program

The PDP-11l

these

interrupts

service

cases,
finds

should ensure

the setting of

set it.

While

the PDP-11l

it must be prepared to accept an output

the microprocessor may have

enable

PDP-1ll

for the

is most efficient

the microprocessor has

program is waiting,

PDP-1l1

when the

interrupts disabled and simply scan RDYI one or

more times until

the

set RDYI.

controls whether the

(to Vector XXf)

PDP-11 program receives an interrupt

because

(IEI),

Interrupt Enable Input

Bit 6 of BSEL@,

The microproOcessor

then it should clear RQI.

takes the data and clears RDYI,

can

The

These bits may be set by a single instruction.

microprocessor responds by setting bit 7,

set,

to regquest

(RQI),

type of transfer and then set bit 5, Request In

RDYI

setting

that

seized the port

certain types of
is

convenient

clear

IEI

IEI was

IEI while waiting

successful, it should try again.
A9

after

with

several

BIS

the meanwhile.

input
use

transfer

transfers

interrupts.
scans,

or MOV

instruction.

successfully set following

for RDYI.

If the PDP-11

WwWas un-=

The DMCll interrupts the PDP-11

(to

Vector

program

XXf@)

gets

when

the

already

can

bypass

any

The

PDP-11

program

awaiting

microprocessor

interrupt

had

set

the

RDYI

scanning

may

the
if

all

time
IEI

clear

cases,

the

IEI

has

even

program

set

when

any

RDYI.

the

sets

the

time

The

microprocessor_
_-

IEI.

The

progr-m

sets

other

PDP-11

than

program
RQI.

when

RDYI.

NOTE

The

PDP-11

input
has

program

transfer

been

program

wishes

begin

should

check

new

transfer
by

new

the

PDP-11

transfer

that

RDYI

This

can

has

done

Output

wishes

PDP-1ll1l
more

RDYI

until

not

attempt

program
than

must

seven

data

buffers

integrity

for

may

transmission

lost.

Transfers

error

scanning

F//

cleared.

microprocessor
or

the

has been cleared before settinag ROI.

reception,

buffer

indicated

RDYI.

queue

begin

clearing

The

status

the

not

microprocessor

been

The

until

completed,

immediately,

3.4.4

should

initiates

information

return

full

transmission.

an
to

output
transfer

buffer

The

transfer
to

the

reception

microprocessor

can

when
PDP-11

has

program

empty

initiate

output

g
-

AlO

transfer
PEP-1ll
I
2

any

time

program

the

data

input

for

't transfer.

Kowever,

port

free;

transfer

the

that

and

not

PDP-11 has

is,
in

not

use

assigned

for

the

out-

initialized the DMC1l1 by

setting

MASTER CLEAR or generating the INIT signal on the Unibus, the microprocessor
does

not

the

PDP-11

The

microprocessor

generate

(BSEL4-7)

any

outrut

and

loads

sets

bits

the

data.

the

PDP-1l1

programs

PDP-11

then

program

f#-2

program

has

sampled

the

PDP-11

setting

the

DMCll

has

set

’/Qutput

-n

BSEL2

RDYO.

frees

Since

transfer

will

PDP-11

error

has

been

information
indicate

BSEL2,

data

available.

read
the

BSEL2

note

the

type

data

Ready

data

data,

wishes,

BSEL2,

RDYO.

of
bit

that

all

interruprts

efficient

sets

program
6

fg-2

and

This

bit

status

should

bits

clearing

until

initialized

progran.

transfer

must

port

(RDYO),

response
transfer

port.
the

can

enable

interrupts

Interrupt

Enable

Output

(to

the

PDP-11

Program

usually

example,

when

(for

Vector

ordinarily

XX4)

enables

does

the
not

message

PDP-1ll

Peing
RDYO.

port

set

progranm

reading

Failure

from

must

being

respond

the

data

this

freed.

and

prevents

the

All

RDYO

clearing
the

PDP-11

data

port

significance
indicate
RDYO

setting,

specified

the

PDP-11

transfer

transaction.

output
If

transfers

IEO

set,

microprocessor
know

will

interrupts

NOTE

The

output

(IEO).

after

When

subsequent

PDP-11

progran

Out

data

the

occur

and

1In

data

format

complete

for

the

output

the

into

when
be

received),

cutput

transfers

program

has8 requested

setting

RQI,

output

RDYI.

respond

PDP-11

loop

the

level

3.4.5

powerup

The

PDP-11l

MASTER

state,

not

output

not

also

DMCll

respond

being

given

gets

RDYI.

spin

test

fails

interrupt

unless

are

lower

The

RDYI

RDYO

transfers

executes

the

sequence
program

CLEAR

the

The

PDP-1ll

program

perform
l128-word

PDP-1l1l

enabled,

priority

level.

1In

achieve
Each

INIT
the

generate

should

same

these

beginning
does

signal

effect

procecures

its

not

send

output

initialize

DMC1l.

setting
restarts

microprogram.
or

the

receive

the

this

messages

transfers.

not

access

wishes

the

CSRs

for

CLEAR.

program

input

table

PDP-1l1l
11.

MASTER

Unibus

microprocessor

line

the

can

the

serial

following

and

BSELl.

the

should

does

than

microprocessor

The

never

1Initialization

The

When

program

transfer

prepared

PDP-1l1l

RDYO,

loop

prior

program

that

must

input

transfer

the

interrupts
and

transfer

that

PDP-11

memory,

program
response

requests
to

RDYI,

specifies

the
the

Al2

DMCll

which

BASEI

the

function,

base

called

transfer

program

loads

addresé
the

by
the

base

setting

must

table.

TYPEI

low-order

If the DDCMP protocol

address into bits 15 and 14 of SEL6.

must

(bit 12 of SEL®6)

the RESUME bit

operation is to be initialized,

the

2 bits of

and the high-order

SEL4

into

bits of the address

clear.

the 1l28-word base

Once the PDP-11 has specified a base address,

table belongs to the microprocessor until the DMCll is master

The PDP-ll program may examine

cleared by INIT or MASTER CLEAR.
the contents of

the base

(for example,

table

error counters

but must not alter its contents.

relating to protocol operation)

..y supplying a base address with the RESUME bit clear,

conditioned to enter the DDCMP start-up state.

microprocessor

The PDP-11 program must perform an input transfer,
Control
if

In format by setting the Half Duplex bit

the channel

whether

the

station

(long

by
A

setting
half

half duplex or by

DMCll

duplex

operate

timer)

clearing
link

secondary

station.

length

time

duplex

operation

accommodate

channel.

The

spent
may

The

switching

DMC1ll

only

before
be

Secondary
have

one

half

options

bit

duplex

half

any

Al3

(bit

start

the

backup

10)

the

specify

(short

SEL6

(bit

and

one

station

time

duplex

containing

between

retransmitting

in SEL6

secondary

station

(SEC)

primary

difference

specified

(HD)

the program must

half duplex primary

the

should

using the

leaving this bit clear if

addition,

1In

duplex.

full

channel

the

two

timer)
11).

sequences.
a

Control

the
Half

transfer

communications

integral

modem

must

specifically

strapped

for

operation

addition

3.4.6

DDCMP

Start-Up

Before

data

start-up

messages

sequence

the

link

the

running

within

The

one

state.

may

property

local

DMCll

has

entered

error

the

fact

Sequence.

transfer

the

with

PDP-11

begin

again.

3.4.7

Data
the

clears
ter

SEL6

The

Count

and

requests

input

SEL4
and

PDP-11

that

program

make

certain

both

ends

place

the

protocol

will

initiated

assignment

the

end

has

program

should

start

sequence.

detects‘and

receives

set.

end

BASE.

Once

initiated

RECD)

other

the

significant.

state,

START

the

DDCMP

details

other

(DDCMP

knows

transfer

this

bit

program

that

bits

the

PDP-11

specify

loads

that

the

running

transfer.

received,

and

sequence

cable

the

initialize

flags

the

start

Control

this

link

the

Out

happens,

has

DMCll

and

Transmission

PDP-1ll1l

bits

the

result,

program

restarted.

When

the

single

procedure

following

ignore
of

start-up

using

Control

transmitted

initialized

The

when

the

completed

interval

program

one

correctly

timer

PDP-11l

However,

are

duplex

requiring

may

must

half

wishes

BSELf
and

the

SEL6

full

bit

buffer
by

setting

low-order
with

transmit

indicate

clears

transfer

with

the

Buffer

data,

Address/Charac-

(IN

I/0)

transmitted.

RQI.

bits

buffer

BSELZ

high-order

Al4

then

response

the

buffer

address,

bits

the

RDYI,

Buffers

and bits 13-0 of SEL6 with the 14-bit character count.

For

from 1 to 16,383 bytes long may be used for local operation.

remote operation, buffers should be limited to a practical maximum
depending on the error rate of the communications

of about 512 bytes,

Each buffer corresponds to a single DDCMP data message.

facilites.

When the messace has been successfully transmitted and an

the microprocessor initiates an output

acknowledgement received,
transfer with bits

and 2 of

Address/Character Count
is

clear

been

indicate

returned

The

PDP-11

supplying

the

program

Out

that

BRSEL2

clear to

(BA/CC O)

indicate

the

Buffer

Bit

(OoUT

1I/0)

format.

successfully

transmitted buffer

has

progranm.

may

buffers

gueue

the

seven

buffers

microprocessor

for

faster

transmission

than

returns

fill

them.

NOTE

The

PDP-11

transfer
seven

that

are

integrity

3.4.8

Data

the

with

received

BA/CC

that

PDP-11

supplies

already
may

must

not
a

regquest

transmit

outstanding,

input

buffer

data

lost.

Reception

When

program

rrogram

data,

transfer

and

has

clears

empty

bits

sets bit

empty buffer has

been made

AlS

buffer

and

# of

BSELZ

(IN

available

wishes

BSELf#

indicate

I/0)

specify

for reception.

then

requests

RDYI,

loads

count

the

input

SEL4

same

and

SEL6

format

must

large

enough

When

message

has

buffer,

the

and

BSEL2

I/0)

SEL4

and

SEL6

contain

informed

program

The

PDP-1ll

may
them

the

buffer

1In

the

initiates

that

The

longest

received

the

BA/CC

buffer

and

when

the

and

the

format.

Bit

been

the

buffer

and

receive

buffer

PDP-11

set.

The

means

other

automatically
suprly

seven

that

are

integrity

the

bits
2

received,
the

actual

empty

end

available,

Control

the

retransmits

buffer

microprocessor

program

transfer

seven

with

has

count

expected.

transfer

soon

buffers

the

for

may

must

supplies

already

not
a

request

input

outstanding,

lost.

Al6

—

message.

returns

reception

data

transfer

1is

reception

than

for

the

possible.

faster

buffer

Out

link

NOTE

PDP~-11

character

stored

buffers.

The

character

message

and

output

response

address

transmission.

address

should

queue

RQI.

received.

error

PDP-11

the

indicate

(ORUN)

The

supplying

informs

the

for

setting

successfully

received

SEL6

with

indicate

characters

message

bit

accommodate

been

clear

set

microprocessor

with

microprocessor

(OUT

number

transfer

3.4.9

Control Out Transfers

or error
The microprocessor informs the PDP-11 program of unusual
end of
conditions involving the communications channel, remote
output
the link, DMCll hardware, OTr PDP-11 program by means of an
ng a
transfer with bit 1 of BSEL2 clear and bit # set, indicati
Control Out (CNTL ©O) transfer. SEL6 contains bits that indicate
l
the error condition. Some errors are advisory in nature and norma

operation may continue.

Others are fatal and require the PDP~-11

program to initialize the DMC1ll.

Bit # (DATA CK) indicates that a retransmission threshold has
been exceeded (more than eight consecutive retransmissions have

occurred for transmission or reception). This indicates a defective
communications channel or that the other end of the link has failed
to supply a buffer for reception.

The PDP-11 can examine error

counters in the base table for more details of the error. This is
a non-fatal error. When the cause of the error is corrected, normal

operation continues with no messages lost in either direction. This
error may appear repeatedly until the condition is corrected or until
the DMCll is initialized.

Transient errors corrected before eight

retransmissions are not reported to the PDP-11 program but are
counted in the base table.

Bit 1

(TIME OUT)

indicates that the microprocessor has received no

response from the remote end of the link for a specified period
(24 seconds).

This indicates a broken communications channel or a

failure at the other end of the link

Like DATA CK,

(possibly a power failure).

this is a non-fatal error which can occur repeatedly.
Al?

Bit

(ORUN)

indicates

was

available.

can

prevent

This

this

that

error

message

non-fatal

from

was

received

error.

The

recurring

but

PDP-1l1l

repeatedly

buffer

program

supplyingc

buffer.

Bit

(DDCMP

maintenance
was

lost,

MAINT

RECD)

format

and

the

was

indicates

received.

PDP-1l1l

that

The

message

must

reinitialize

fatal

maintenance

state.

This

Bit

(LOST

DATA)

indicates

than

the

causina

DDCMP

the

DMCll

was

received

contition

enter

the

error.

longer

fatal

Bit

Data

program

Set

must

the

Bit

was

received

(DDCMP

DMCll

Bit

(NON

occurred.

lead

message

when

the

wishes

been

For

PDP-1l1l

program.

on-to-off

detected

dial-up

required

indicates

protocol

that

This

error.
to

have

was

that

been

the

new

———®

operation

caller

has

only).

connected

considerations.

Start

program
complete

address
the

the

PDP-11

running

Unibus

the

initialized

and

caused

AlS8

DDCMP

PDP-1l1

over

(remote

security

has

The

start

that

transition

operation,

that

computer

indicates

could

possibility

remote

fatal

MEM)

This

RECD)
the

the

the
is

that

has

error.

this

START

that

This

the

Ready

consider

DMCll,

indicates

non-fatal

link.

supplied

error.

(DISCONNECT)

modem

This

buffer

that

message

state.

This

its

end

should
the

initialize

start-up

timeout

PDP-1ll1l

the

has

program

sequence.

specifying an invalid base address, buffer address, or count that
1
was stored illegally in the base table or that by a defective PDP-1
This

memory.

fatal

error.

Bit 9 (PROC ERR) indicates a procedure error on the part of the
PDP-11 program. The requested input transfer cannot be honored

This error can be caused by requesting

due to a programming error.

a BA/CC before supplying a base address, requesting a base address

a second time, or specifying an invalid code in BSELZ bits 1 and #.
This is a fatal error. The PDP-11 program may create this condition
as a means of shutting down the DMCll in an orderly manner (see
Data Terminal Ready will be cleared as a result

Paragraph 3.4.13).
of

this

3.4.10

error

condition.

Maintenance

Messages

A special DDCMP message format, the maintenance message, is used

for down-line loading, restarting, or otherwise maintaining satellite
Messages in this format are subject to error

computer systems.

checking but are unsequenced, unacknowledged, and not retransmitted
automatically by the DMCll1l.

Maintenance messages

processor

the

can

the microprocessor

bit

SEL6

(DDCMP

maintenance

microprocessor

only be

sent

DDCMP maintenance

cause
8

Transmission is always half duplex.

MAINT)

message

performs

enter this

and

received while

state.

state

The

the

micro-

PDP-1l1l program may

a CNTL

transfer with

set.

received while

CNTL O

transfer with

AlC

the

running

DDCMP MAINT

state,

RECD

the

set

SEL6.

The

PDP-1ll

maintenance

Once
and

state

DDCMP

received

portion

program

must

transfer

maintenance
similarly

then

initialize

messages

mode,

data

messages.

the

message

taken

from

generating

the

header

and

CRCs.

placed

having

incorrect

The

data

Operation

the

line

Whenever

Remote

Load

MOP

MODE

base

line

for

the
the

sent
the

data

DMC11
data

portion

maintenance

format

the

contain

data

Digital

operating

single

btuffered

transmitted.
computer

described

mode,

may

any

that

Maintenance
conformance
manner,

When

system,

with

causing

host

must

send

below.

the

PDP-11

with

the

program

RESUME

must

bit

initialize

clear.

Detect

field.

depends

address

microprocessor

data

received

satellite

only,

DDCMP

message

nessage

maintenance

supply

serial

with

the

discarded.

When

buffer

conforms

each

messages

and

the

operated

restart

MOP

simply

formats.

after

leave

the

are

not

can

transmission,

reception

maintenance

(MOP)

must

wishes

DMCll

3.4.11

the

Messages

ordinarily

turn-around

order

CRCs

Protocol

appropriate

the

but

DMCll

computer

the

buffer.

portion

desired,

MOP,

the

format.

messages

the

device

maintenance

the

DDCMP

unit.

Depending

will

either

trigger

running,

maintenance

What

happens

when

the

setting

line

the

setting

PDP-11

constantly

message
this

two

begin

A20

containing

particular

switch

these

scanning

packs

switches,

executing

ENTER

message

the

program

DMC11

DMC1ll

readwa

only memory (ROM) bootstrap (DM873, M93¢1l, etc.) or simply pass the
data to the PDP-11 as an ordinary maintenance message.

In case a

ROM bootstrap is triggered, switches on the line unit specify an
8-bit

the

offset

word

bootstrap

address

space.

The data portion of the ENTER MOP MODE message is 5 bytes 1long.
The remaining 4

The first byte contains the decimal number 6.

This value is specified by

bytes contain the same 8-bit value.
a

rack

switch

DMCll

the

line

and

unit

serves

protect against inadvertent recognition of

a password to

the ENTER MOP MODE

ENTER MOP MODE messages with an invalid password are

message.

discarded if the switch settings specify remote load defect.

;

/" e

Recovery

Fail

Power

3.4.12

The DMCll keeps all data necessary to attempt recovery from a power
failure

its base

table.

it should cease

failure,

Wwhen the PDP-1l1l program detects

requesting input transfers

a power

1 and 2.

procedure error by specifying an invalid code in BSELf@ bits
At this

point,

already

sent

code

appears

the DMCll will

and

acknowledged or

a CNTL O transfer.

PDP-11 power

recovery

recover

the

RESUME

from
bit

contents
was

lost;

the

set.

The

program can

the

base

table

1is

original
table

the

tell

MOS

the

a BASE

address
the

program must

within

and receive messages

until

the procedure

error

When power has been restored,

base

must

send

received,

error by performing

otherwise,

base

cease

and create

same

start

DMCll
I

transfer with

must be
as

over

were

(RESUME

the

specified

they

or bipolar memory

A2l

microprocessor

the

and

the

when

power

bit

clear).

(without

battery

backup),
been

lost.

11/58,
by

recovery
the

not

PDP-~1l1l

11/55,

11/78,

loss,

and

the

data

the

will

DMCll

using

3.4.13

Shutdown

program

may

specifying

acknowledged
CNTL

Set

3.4.15

Data

the

DMC1ll

Cumulative

order

invalid
output

table

11/48,

recovery

may

designed

information

the

code

DMC1l1
in

the

BSEL@

transfers

until

help

will

have

11/45,

accompanied

reinitialize

about

transmit

for

creating
bits

error

and

messages

procedure

Ready

Error

encounters.

the

base

and

procedure
#.

The

already

code

PDP-11

sent

appears

and

these

provides

component

Eight

counters.

transition

(PROC

given

Ready
of

ERR).

continuously,
Data

Data

cleared.

base

Ready,

Terminal

master
CNTL

Set

transfer

Ready

on-to-off

described

address.

Counts

provides

table.

Terminal

device

been

localize

DMC11

error

Set

has

Data

on-to-off

the

error

when

the

Table

down

maintains

channel,

provide

shut

procedure

reasserted

transition

within

PDP-11/35,

fail

should

base

Control

following

result

above,

the

DMC1l1

received

microprocessor

will

process

Data

dropping
as

power

since

transfer.

3.4.14

The

the

program

should

software-maintained

pending.

error

processor

software

messages

PDP-11

successful

DMC1ll1

receive

The

The
The

record

failures

each

bit

counters

base

table

format

3-1,
A22

for

the

recoverable
these

updated

these

communications

errors

communications
are

periodically

counters

provided

detailed

3.4.16

The

Optimizing

DMCll

overhead

implements
of

ten

synchronization
performance
maximum

vided

Performance

that

with

the

sequence

each

whenever

will

approached

mray

transmitted

bidirectional.
link

efficiency.

poor

link

numbers

Applications

Table

3-1

the

which

line

the

buffers,
using

result

Cumulative

has

error,

and

line

Error

the

error

Recd

BASE+4

NAKS

Recd

Bad

Header

BASE+5

NAKS

Recd

Bad

Data

BASE+6

NAKS

Sent

Buffer

BASE+7

NAKS

Sent

Bad

Header

BASE+10

NAKS

Sent

Bad

Data

BASE+11

REPS

Sent

BASE+12

REPS

Recd

A23

Buffer

Available

RCC

ECC
Available
BCC

BCC

yield

messages

Condition

NAKS

Optimal

transfer

rates.

approach

DMCll

Counters

BASE+3

fixed

idle.

messages

large

requires

sizes

message

small

very

and
gone

message

very

using

imposes

message

without

Location

data

when

Applications

efficiency

DMCll

DDCMP protocol,

characters

maximal

the

may

the

pro-

is
poor
yield

Once

this

message

the

PDP-11

has

been

the

program

successfully

specified

received,

transfer

DMC11

add@ress.

starts

The

DMC11
y

must

1initialized

subsequent

3.4.12

ENTER

before

MOP

MODE

does

anything

maintenance

Power Fail Recovery

except

regLognize

mefSsage.

///

in its base table. When the sz/y Xééram detects a power

The

DMC11

keeps

all

data

necessary/

recover

frpm

power

failure

failure, it should cease requestlng 1n§ut’t ansfers and not
respond to output transfers.

Wh@n power

PDP-11 power recovery pp@gram:‘n tell

AAas been restored, the

£he DMC11 microprocessor

to recover from the eféor by perSormyng a BASE I transfer with

the RESUME bit set:fijThe original

PYase address must be specified

and the contentsgfi% the%bas? tab)e must be the same as they were
when power was
(RESUME

bit

program

mus

?»ear).
/

IEFO

'ost; othe?%ise
As

paiylof

‘

desired.j

’

13A~~Qata Sethontrol

The

If’thé\SW1 ches’on the DMC11

microprocessor

Ready

the

PDP-11

It must set

repeats

uncompleted

line unit specify bootstrap ROM

or/down line loading,
1

recovery,

3.4

Termin

power

and

Data

the

repeat an uiyémpleted input transfer.

IET

/trlggerfig

the program must start over.

continuously,

the microprocessor maintains
dropping

for

one

second

period fofiowing an on to off transition of Data Set Ready.
Otherwifii, the DMC11 does not turn Data Terminal Ready on until
¢

it has;received a base address.

It drops Data Terminal Ready

when initialized by INI

AST?§;CLEAand
R 1t‘g;ops”T€¢g:;fl:;e

secoEg,fie&ISWI;% an o?éto of{ tgflns&tion of Data Set Ready.
e

on tigakfliiransafl;gawfifflData Set Ready provides a CNTL O transfer
et

»»»»»»»

described

above,

the

DMC11

has

been
s

3.5

MICROPROCESSOR

3.5.1

The

CONTROL

AND

A
ok

given
i

base

address.

STATUS

REGISTERS

REgisters

described

Introduction

Unibus

3.4.2

are

Control

and

physically

Status

located

the

multiport

RAM.

paragraph

The

RAM

capacity is 128 bits arranged as 16 8-bit bytes, which is equivalent
—
to
two

16-bit

words.

sources.

One

microprocessor.
are

viewed

Control

The

OUTBUS*/INBUS*

contains
called

the

can

source

the

Unibus

when

these

the

Status

remaining

RAM

Therefore,

from

and

The

microprocessor,
Registers.

registers

multiport

NPR

Data

Microprocessor

and
CSRs

registers

0-7

(octal).

There

are

two

additional

listed

the

OUT

(108)

and

BUS*/IN
the

the

Unibus

they

are

which

registers.

and

byte

BUS*

other

CSRS

the

(BSEL1-BSEL7)

called
they

from

Microprocessor

are

identified

(octal).

capacity,

and

simultaneously

Specifically,

0-7

RAM

accessed

These

are

specified

sized

hardware

category.

Microprocessor

8-bit

registers
OUT

are

Miscellaneous

are

BUS/IN

registers

They

bytes,

the

BUS

that

NPR

also

are

Control

(118).

~—

The

microprocessor

registers.

assigned
and

OUT

(octal)
not

BUS/IN

are

have been

listed

each
a

under

has

result,

the

located
two

line

six

line

the

unit

line

and

there

are

nine

registers

The

detailed

the

that

the

use

Out

Line

is,

OUT

These

registers,

the

108

same

the

line

unit.

Unit

registers
is

write

shown

CSRs

12-17

listed

address.

BUS*

108-—178

These

Silo

CSRs

registers

Address

sized

BUS*/IN

Data

byte

registers

category.

Microprocessor

discussion

show

device

only

decided

unit.

read

arrangement

undefined

BUS

The

been

addressing

OUT BUS*/IN BUS*.

OUT BUS/IN

category;

added

Therefore,

The

only.

Figure

contained

3-2.

1in

3.6.

3.5.2

OUT

These

eight

BUS*/IN

BUS*

registers

3.4.2.1

through

3.5.3

NPR Control

Bit

The

Silo

paragraph

capability

physically.

because

Data

under

BUS.

are physically

the

convention,

addresses

exist

twice

has

are

Registers

0-7

identical

(NPR

described

paragraphs

3.4.2.5.

(OUT

BUS*/IN

Name

NPR

those

REQUEST
RQ)

BUS*

10)

Description

This

bit

can

automatically

set

only.

cleared

It
the

1is
hardware

R 4 1l

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REE TS TELS

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Unibvs CSRs

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3-2

Microprocessor Registers

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Figure

3-2

Microprocessor Registers

Bit

(Cont.)

Name

NPR

REQUEST

Description

(Cont.)

when

the

When

set,

via

the

NPR

has

this

bit

Unibus

OUT

transferred

NPR

memory.

the

NPR

Bit

XFER)

(BYTE

the

NPR

memory.

cleared,

the

OUT

PDP-11

from

transferred

completed.

requests

(bit

been

data

PDP-11
set,

PDP-11

data

memory.

controls

word/byte

selection.

For

address

NPR,

the

OUT

PDP-11

BUS/IN

memory

BUS

registers

and

For

QOUT

NPR,

OUT

BUS/IN

BUS

registers

the

address

and

The data that is associated.with the
transaction

comes

from

registers

and

for

from

OUT

BUS/IN

BUS

Unibus

Control

(bit

line

and

BYTE

XFER

line

CO.

state

cant

bit

(0)

byte.

The

When

truth

the

used

and

NPR

the

DATA

BUS

OUT

set,

OUT

BUS/IN

registers

for

Control

OUT

BYTE
BA

table

XFER

least

select
for

and

the

Unibus
is

signifi-

the
type

Bit

(Cont.)

Description

Name

NPR

REQUEST

(NPR

RQ)

transaction,

(Cont.)

bits,
OUT

NPR

shown
BYTE

selected

these

below.
XFER

UNIBUS

(c1)

(CO)

BAO

TRANSACTION

DATI

Illegal

DATO

DATOB

(Low

Byte)

DATOB

(High

Byte)

READ/WRITE

(R/W)

This

read/write

function

and

microcode

may
a

bit

provides

treated

flag

no
in

the

state

indicator.

and

These

are

bits

used

the

PDP-11

during

transaction.

memory
IN

NPR

extension
(C1

Bit

Name

OUT

NPR

Description

This
NPR

bit
RQ

(bit

used

0).

The

association
details

inter-relationship

between

are

covered

description

NPR

0).

(bit

the

with
the

these

bits

RESERVED

BYTE

XFER

This
OUT

bit
NPR

is
to

used

the

PDP-11

set,

the

for

byte

DATA

the

DATA

byte

BYTE

the

PDP-11

byte

uses

7-0

stored

memory.
is

stored

bit

the

low

the

PDP-11

memory.

cleared

during

PDP-11

this

address

the

OUT

with

transfer

When

selection.

7-0

operation,

memory.

PDP-11

OUT

association

indicate

OUT

DATA

15-0

memory

O,
byte

high

OUT

NPR

transferred

word.

5.4

Microprocessor

Bit

Miscellaneous

Name

BUS*/IN

BUS*

11)

Description

NON-EXISTENT

(NON-EX

(OUT

MEM)

MEMORY

During

mately

ZO/us

memory

location

NPR,

this

after

NPR

logic

This

bit

microprocessor.

bit

set

non-existent

addressed

releases

approxi-

this
the

time,

the

Unibus.

—~

LOW

set

triggers

1-shot

duration
to

the

fail

only

0.5s.

Unibus

recovery

bit.

with

This

and

When

pulse

initiates

procedure

set,

goes

power

the

PDP-11

Processor.

OUT

ouT

PROGRAM

(PGM

and

CLOCK

CLK)

These

are

bits

used

This

bit

the

PDP-11

during

acts

OUT

timer

microprocessor.

determine

time

lapse

flag

testing,

This

bit

triggerable

memory

can

NPR

extension

transfer.

for

the

read

time

out,

re-

etc.

the

1-shot

output

with

pulse

Bit
4

(Cont.)

Name
PROGRAM

(PGM

Description

duration.

CLOCK

CLK)

(Cont.)

pulses

come

intervals,

and

this

1-shot

long

along
the

bit

times

read

out,

this

bit

set,

vector

the

triggering

less

1-shot

than

remains

this

second

asserted

the

bit

read

(bit

XX4

generated.

RESERVED

VECTOR

XX4

vector

REQUEST

(BR

RQ)

XX0

and

address

When

set,

Request

shipped

this

with

installed.

when

XX0

cleared

the

has

been

bit

initiates

Unibus

BR5

RDYI
with

priority

the

can

level

B s«ij

card

set

hardware

completed.

RDY).

Bus

microprocessor

bit

set,

with

associated

The

generated.

This

and

associated

the

when

address

XX4

via

set

cleared

address

Address

only
after

3.5. 5

NPR

Bus

Address

and

Data

Registers

Name

DATA

OUT

DATA

Low

byte

(register

from

the

Low

byte

the

PDP-11

Contains
during

BUS

memory.

BUS

0-7)

and

high

byte

transferred

memory.

data

and

high

byte

transferred

memory.

Address

NPR
Bit

data

(register

BUS/IN

Description

(register

(OUT

(BA)

transfer
0

bits

from

0-16

the
4

PDP-11

bit 0 ahd bit 7 of register 5 is BA
bit

OUT

16.

Contains

during

memory.

bit

Bus

Address

NPR
Bit

and
16.

bit

(BA)

transfer
0

bits

0-16

the

PDP-11

3.6

LINE

3.6.1

The

UNIT

In/Out

Data

operation

Physically,

The

Data

Silo

Receiver

silo.

REGISTERS

Silo

Registers

loaded

the

When

other

with

Data

four

bits

the

Silo

(10)

received

microprocessor

data

the

considered

from

performs

presented

form

data

the

word

part

the

read

IBUS.

bit

Control

When

the

Silo,
data

to
The

microprocessor

nothing
to

the

transmitted

input

other

happens

four

performs

this

write

operation

However,

the

OBUS

and

which

word

part

the

Out

taken

from

the

Out

Data

bits

are

considered

Silo,

the

the
8

bits

Data
of

presented

bit

silo.

Control

3.6.2

Out

Bit
0

Control

(11)

Name

Description

TSOM

(Transmit

Start

This

bit

new

message.

used

initiate

the

start

Message)

DDCMP

Mode:

loaded

with

TSOM

The

into

bit.

transmitted

Sync

the

Out

This

the

character

Data

Silo

character

Sync

must

along

character

until

Bit
0

(Cont.)

Name

Description

TSOM

(Transmit

Start

Message)

(Cont.)

cleared.

Until

the

characters

CRC

accumulation.

the

present

are

Sync

not

All

included

accumulation,

TSOM

set,

has

cannot

been

unit

Bit

Stuff

flag

Mode:

with

the
of

data

All

Out

and

Data

cleared,

data.

enabled.
CRC

unless

the

CRC

Once

accumulation
the

1line

character

TSOM

long
be

data

flag

transmission

information

function

the
is

TSOM

set,

automatically

Silo.

current

included
CRC

The

cleared

actual

the

characters
are

the

When
is

the

transmitted
When

CRC

cleared,

initialized.

transmitted.

Flag

followed

inhibited

character

loaded

TSOM

character

and

included

When

transmitted
data

CRC

bit

that

lost.

automatically

TSOM

set.

transmitted,

loaded

the

data

into

completion

character,
of

TSOM

the

begins.

transmitted

accumulation,

enabled.

the

Bit
0

(Cont.)

Name

Description

TSOM

This

(Transmit

Start

Message)

(Cont.)

TEOM

(Transmit
Message)

End

bit

cleared
and

program

the

fact

write

only.

initialization
that

data

loaded

into

the

Out

Data

Silo.

into

the

Silo

and

passed

the

through

the

This

used

terminate

bit

message

progress

transmission

the

CRC

DDCMP

the

function

Mode:

character

messages

are

When

Silo.

and

control

CRC

character,

enabled.

TEOM

set,

the

CRC

cleared),

Stuff

(TSOM

shut

When

TEOM

loaded

with

character

messages

are

pending,

shut

down

second

the

silo.

closing

set,

lost.

transmitted.

transmitter

down.

Mode:

CRC

single

the

pending

Bit

the

transmitter

TEOM

loaded

transmitted.

the

character

logic

was

transmitter

the
The

the

having

This

generates

intermessage

flag.

Description

Name

Bit

(cont.)

(Transmit

End

Message)

(Cont.)

Reserved

Data

Silo.

These

bits

are

and

are

cleared by

and

set

whenever

through
is

must

bits
10

OUT

(Out

RDY

Ready)

initialization

logic

loaded

These

bits

the

sent,

into.

asserted,

this

bit

informs

microprocessor

that

the

transmitter

ready

the

indicates

data.

these

written

When

the

before

written

the

therefore,

into

transmitter

into;

and bits

everytime

format

They

silo

the

CONTROL

only.

data

passed

written

write

flip-flop which

Silo.

are

the

TSIP

the

Out Data
and

program

Out

the

into

loaded

data

whenever

set

flip-flop which

TSIP

the

and

logic

initialization

by the

cleared

1is

only.

is program write

bit

This

TEOM

that

space is available in the Out Data Silo.
microprocessor

The

Silo

and

the

then

reads

loads

the

OUT

RDY.

microprocessor
read

and

allows

interpreted

Out

Data

speed

The
OUT

RDY

true

Bit
4

(Cont.)

Name
OUT

RDY

(Out

Description

(Cont.)

Ready)

before

the

Therefore,
loading

Reserved

silo

has

loaded

the

one

cycle

must

elapse

the

silo

and

read

only.

This

bit

Read

only.

reading

Physically,

this

data.

between

OUT

RDY.

bit

switch.

OUT

ACTIVE

OUT

ACTIVE

the

This

informs

status

set,

bit

hardware

the

is
and

(OUT

This

CLEAR)

bit

transmitted
write

Control

Check

Character

only.

cleared

When

active.

set

all

the.

the

logic.

used

clear

functions.

OCLRP

program

(12)

Description

MATCH

(Block

transmitter.

only.

Name
BBC

the

microprocessor

transmitter

read

initialization

OCLRP

the

Match)

BBC

MATCH

CRC

error

logic

contents

the

output

the

that

monitors

CRC

receiver

the
With

Bit
0

(Cont.)

Description

Name

BBC

MATCH

(Block

(Cont.)

Check

Character

Match)

the

CRC

function

asserted

message.

been

This

BLOCK

END

the

bit

read

BLOCK

END

used

microprocessor,

terminating
This

flag

may

loaded

with

read.

mode,

leading

that

received.
flag

for

bit

The

BLOCK

END

high

byte

the

CRC

BLOCK

END

bit

the

BCC

updated

the

indicate

been

along

Receiver

has

therefore,

used

the

inform

character;
with

SDLC

and

SDLC

message.

the

message

016417,

only

everytime

the

CRC

the

contents

errorless

protocol,

equal

MATCH

errorless

when

BBC

DDCMP

received.

protocol,
CRC

Receiver

the

zero

equals

end

the

contents

has

the

enabled,

the

MATCH

bit

reception

should
a

good

message.

This
in

bit

the

time

read

only

DDCMP

mode.

and
is

read.

not

updated

used
every-

Name

e et
v,

———
e

5= oo S oma—

Description

Reserved

When

this

bit

microprocessor

that

received

ready

for

that

data

the

This

LOOP

(Alternate
Unit

Loop)

bit

During

Line

asserted,

ALT

s g

informs

the

data

processing.

indicates

the

available

Data

output

Silo.

read

only.

maintenance,

loop

the

receiver

with

connection

this

bit

the

set

transmitter

the

modem

control

lines.

ACTIVE

This

bit

When

asserted,

this

bit

informs

the

microprocessor

that

the

receiver

the

data

program

reception

receiving

DDCMP

Mode:

mode;

CRC

ACTIVE

the

first

Mode:

ACTIVE

the

first

data

receipt

SDLC

data

read/write.

receipt

that

is,

characters.

asserted

non-sync

upon

character.

asserted

upon

character.

Bit

Description

Name

(In

Clear)

Modem

bit

This

ICLRP

Control

receiver

functions.

ICLRP

program

Description

SECURE

only.

(13)

Name

(Clear

write

the

all

clear

used

Send)

The

function

for

future

use.

asserted

when

The

function

for

future

switch

the

line.
must

bit

read

reserved

only

(open).

OFF

bit

reserved

This

read
SW

only
is

bit

asserted

OFF

(open).

informs

the

microprocessor

the

modem

Clear

This

bit

and

MODEM

RDY

asserted

generate

SEND

enabling

signal.

This

bit

1is

state

bit

1is

SECURE

switch.

when

switch

this

use.

This

the

selected

The

bit

switch.

selected

the

this

read

(bit

simulteneously

which

only,

the

Send

transmitter

A
1

A
R
o
b

Bit

Name
MODEM

Description

RDY

(Modem

The

Ready)

MODEM

RDY

bit

microprocessor

informs

the

Ready

line.

the

this

signal

can

through

jumper.

the

signal

turned

on.

M8201

the

Line

Modem

Unit,

asserted

the

M8202

asserted

state

held

permanently

the

use

Line

when

Unit,

power

this

1is

[

Nu-—/j

This

HDX

(Half

The

Duplex)

bit

HDX

the

read

bit

only.

used

half-duplex

and

the

receiver

Request

clock

blinds

the

half-duplex

the

put

mode.
Send

receiver

the

line

unit

When

this

bit

are

asserted,

inhibited

during

which

operation

mode.

S—_

This
be

program

read/write

directly

cleared

from

(Request

Send)

bit

the

The

the

Send

the

informs

state

line.

line

the

and

clear

can

signal

microprocessor.

bit

of
This

unit

the

the
bit

logic

microprocessor

modem
is

and

Request

controlled

not

the

to
by

7’

Bit

Name

(Cont.)

Description

microprocessor.

(Cont.)

(Request

Send)

absence

data

is
by

cleared
the

initialization

logic.

This

6
'z

DTR

The

(Data Terminal

Data

Ready)

bit

DTR

read

bit

enables

Terminal

program

only.

the

Ready

line.

read/write.

set

the

can

cleared

into

it.

The

RING

modem

only

This

initialization

via

the

bit

directly
logic

writing

but
a

//“\
7

RING

the

RING

bit

state

informs
of

the

inhibited

the

microprocessor

modem

Ring

line.

the

M8202

Line

Unit.

This

3.6.5
The

Sync

DDCMP

—

Sync

Mode:

character.

The

bit

read

only.

(14)
an

8-bit

program

loaded

read/write

with

program

selectable

sync

Bit

Stuff:

secondary

flag

3.6.6
Both

The

station

the

these

program

3.6.7

secondary
address.

message

registers

determines

mode,
This

this

bit

character

loaded

follows

with

the

initial

format.

Selectable

Maintenance

Bit
0

SDLC

Switch
of

the

Registers

are

the

DIPs

(15

containing

function

and

both

16)
eight

switches

each.

registers.

(17)

Name

Description

MODE

The

MODE

bit

Bit

selected;

selects

Stuff

the

families).

when

protocol

(DDCMP

When

DDCMP

cleared,

set

Bit

Stuff

selected.

During
from

ECS

(Internal

the

DDCMP.

(SDLC

selected)

into

it.

This

bit

clock

1is

the

This

only

bit

CLEAR

sets
can

signal

this
be

bit

cleared

writing

read/write.

output

(approximately

read

the

microprocessor

select

ECS

Clock)

initialization,

only.

the

internal

KHz).

This

bit

Bit

Description

Name

Reserved

Read

only.

ICIR

When

asserted,

(In

Composite

Input

the

Data

this

bit

Silo

read

only,

indicates

ready

that

data.

Ready)

OCOR

(Out

Composite

Output

Ready)

bit

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asserted,

data

1is

Out

Data

This

bit

(Serial

This

Input)

(Quotient

In)

(Quotient

Out)

the

bit

indicates

output

that

the

Silo.

read

only.

serial

input

bit

the

CRC

This

bit

CRC

This

3-57

the

read

least

Receiver

Q0O

ready

this

data

from

the

modem.

This

only.

significant

read

least

the

bit

the

only.

significant

bit

read

only.

CHAPTER

DETAILED

DESCRIPTION

4.1

SCOPE

This

chapter

Included

word

general

MICROPROCESSOR

4.2.1
The

and

internal

diagram

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includes

logic

general

paths.

all

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4.2.2

the

DMC11

this

different

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These

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can

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and

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and

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DMC11

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to

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Formats

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microprocessor.

chapter,

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with

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the

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microprocessor.

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ALU

4-3

Function

Code

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COMP

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(A-B)

1110

(A-B-1)

1111

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0000

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W/C

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0001

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0010

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0101

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Notes:

W/C
C

Carry

and

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Z

are

Carry
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with

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address

the

Branch

4.2.2.2

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Address

Bits

BRANCH

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4-7).

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result

bits
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Scratch

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The

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Move Microinstruction Word Format

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Figure
MOV

ALU

Function

(Cont.)

Functions

Code

SUB
2

4-4

COMP

SUB

AD D

(A-B)

1110

(A-B-1)

1111

(A,B)

0000

MOV

AD D

wW/C

(A,B,C)

0001

INST

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W/C

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0010

CLOCK

INC

(A+1)

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0100

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2A

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(A)

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1100

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1101

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function,

set

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function,

cleared

MOV

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indicate

carry

indicate

when

Carry

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Arithmetic
Logic

C
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ALU

set

with

out

all

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scratch

pad

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all

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FIELD

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the

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The

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loop.
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4-16

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edge

memory
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to

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locations

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previously

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and

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microword

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address

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the

microinstruction.

addressed
the

PC,

the

eight

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can

incremented

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the

and

always

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edge

clock

outputs

signal

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during

the

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execution

DESTINATION

perform

the

ROM

MAR

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(MAR

L).

discussed,

the

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also

has

four

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Pad

memory,

*OUT

BUS.

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DESTINATION

signal,

when

parallel

always

clock

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from

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it.

with

Address

the

4-6.

additional
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the

field

Figure

microword

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and

4-7

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and

bits
Pad

bits

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control

memory
8-12

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FUNCTION

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map

shown

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writing

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form

MAR

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sheet

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4.2.4

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chips

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one

such

comprise
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message

messages.

4-17

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REG

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is

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unique

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stored

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total

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chip

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second

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four

Addressing

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microprogram

discussed

memory

stores

necessary

read

microword

the

storage

use

bits

the

with

from

for

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which

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the

two

powerful

beginning

this

chapter.

eight

are

available

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the

through

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locations

the

system

ten

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bit

become

within

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the

three

for

circuit
in

512

the

chips.
storage

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address

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for

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addition,

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chip

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low

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tri-state

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memory

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selected

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enable

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1024

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locations.

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must

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high

be
chips

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memory

outputs

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control

microprocessor.

13)

chip.

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words)

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DMUX

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4.2.6

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When the microprocessor executes NPR cycles, the bus address will
be fetched from the RAM through the B PORT and clocked into the
The two RAM locations where the bus

bus drivers by NPR MASTER.

address is stored is defined by the B PORT address multiplexer
with MP READ CYCLE low.

This results 1in addressing either

location two or three, as determined by OUT NPR.

The remaining input to the B port address multiplexer becomes

active during a particular MOVE microinstruction (X01) and in
turn gates the addressed data either to the high byte or to the
low byte input on the DMUX.

Bits 5, 6, and 15 determine the RAM

Bit 15 determines which group is to be addressed, the
IBUS or *IBUS. The location within the selected group is addressed
by bits 5 and 6. The appropriate byte is selected by the DMUX.

address.
!/"\

With the A PORT, both reading and writing must be considered.
The A PORT output bus feeds a 2:1 multiplexer which feeds the

UNIBUS data bus drivers.

Data is written into the RAM through

another 2:1 multiplexer which selects either the UNIBUS data
receivers or the ALU output as the data to be written.

There are three conditions under which data 1is written into the
(1) an output NPR cycle, (2) loading a CSR by the
MULTIPORT RAM:
PDP-11, and (3) writing by the microprocessor.

MP WRITE CYCLE

is asserted when the microprocessor executes a write cycle.

This condition then selects the ALU output to be written into the

RAM

data

illustrated

receivers

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MULTIPORT

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4.2.10

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two

write

fixed

and

NPR

and

determine

multiplexer

During

addressing

A0O2,

and

always

for

the

DMC-11

addresses.

(BSEL

features

are

available

(location

addressed

CSR

MASTER.

locations

direction.
AO0O1

microprocessor

location

bits

levels

bits

when

input

under

transfer

RAM

written

determines

through

multiplexer

addressed.

the

When

position.

into

instruction

byte

written

determined

data

the

AO.

multiplexer

desired

into

and

always

cycles,

written

HBWL

1is

The

PDP-11

first

NPR

can

determines

are

determined

number

controlled

the

shown

always

4-14.

byte

with

another

function

CSR,

execution
1)

low

addressing

multiplexing

the

words

into

(CROMO)

writing

The

byte

output,

high

cycles

selected

This

microinstruction
NPR

Figure

RAM.

the

a
is

through

the

use

address

76xxx1

transfer.

read

the

With

the

and

this

contents

step

either

loop

transmitted

both

microprocessor

The

logic

shown

CSR

each

executed.

D09-D12

the

SEL

all

diagnostic

LOCK

prevents

must
two

the

off

remaining

instruction

The

referenced
the

CROM,

via

PDP-11

write

MAINTENANCE

word

diagnostic

CSR

byte

program

into

the

MAINTENANCE

substituting

the

CROM

microprocessor

through

byte

the

D17.

time
are

format

line

and

the

unit

back

can

microword,

line

flop

enable
D14

execution.

from

the
and

illustrated

the

MAINTENANCE

stored

edge

Five

the

features.

bits

CSR.

unit,

and

the

verification.

switch

RUN

the

leading

OUT

thereby

drawing

microprocessor

74S74

the

data

for

MAINTENANCE

can

feature,

INSTRUCTION

MAINTENANCE

off.

74174

BSEL

This

Another

pulse

are

instruction

D15

must

the

BYTE

off

this

enter

the

stored

INHIBIT,

Obviously,

the

provided

RUN

with

stored

while

switch

microprocessor
D08

CSR

01L

switch,

setting.

bits

above

RUN

when

enable

switch

mode.

microprocessor

The

4.2.10.1

Step

This

signal,

unit
set,

function

bit

12,

interface

controlling

the

stepping

the

line

unit

the

line

unit

receiver.

Loop

clocks

4.2.10.2

This

signal,

unit

enabling

function
the

loopback

feeds

bit

11,

feature.

transmit

then

back

the

microprocessor

program

then

data

determine

4.2.10.3

Under

performs

CROM

control

contents

comparison

any

errors

bit

10,

the

CROM

order

CROM

OUT

the

known

cycling.

The

microword

through

had

line

unit.

When

cleared

directly

the

line

this

feature,

which

the

received

transmitted

the

line

data.
data

unit
The

and

received

occurred.

functions

line

the

data
as

when

With

can

the

and

feeds

program
to

transmitter

diagnostic
sends

directly

diagnostic

multiplexer

program

can

determine

the

select

and

then

A2H

drive

read

validity

the

the
of

the

CROM

UNIBUS

data

machine

lines.

What this meéns is that a second instruction, a DATI with an
address

xxxxx48

instruction
on

UNIBUS

D11

data

which
to

must

executed

set

CROM

OUT

select

the

CROM

lines.

following
This

the

enables

microword

and

MAINTENANCE

the

feed

CSR

multiplexer
it

the

4.2.11

The

basic

clock

shift

time
to

Microprocessor

unique

overall

consists

interval

asserted
four

period

T60

throughout

system

Mhz

33.33

shift
of

flop

CLOCK).

WAIT

accessed

SYNC
and

RAM

becomes

WAIT

SYNC

CLOCK

Both outputs

These

microprocessor

See

intervals.

nsec.

the

Each

However,

resulting

expected

360

Note

clock

the
the

the

reset

with

SYSTEM

being

D14

clock

the

clock

due
an
nsec.

overlap

signals

used

are

registers

applied
output

and

the

when

the

multiport

This

clock

hold

state

But

with

WAIT

SYNC

CLOCK

continue

Low

only

transition

and 5)

first

set.

are

when

used

its

flop
control

the

being
multiport

effect

set,

inputs

passes

The
RAM

the

clock

a divide—by;two

clock

the

(CK)

clock

state.

each

timing

oscillator

drawing

stops

the

(WAIT SYNC)

available.

toggles

sequencing.

T210.

before

the

flop

allows

time

overlap

instead

generates

Hofiever,

through a control
(SYSTEM

the

oscillator

shift

with

interconnected

timing.

the

T240

intervals

clock

with

discrete

period

the

provide

time

flip-flops

six

nsec

illustrates
and

for

300

4-15

distributed

six

Figure
T90

generating

clocking,

clock

Clock

with

SYSTEM

clock

shift

input.

clocks.

Refer

drawing

flip-flops

D14

through

for

the

T240

following

are

wired

logic

analysis.

right

shifting

Note

the

shift

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4-38

with

T240's

inputs

are

TO's

T60,

T90,

the

shift

T150,

positions.
SYSTEM

T90,

CLOCK,

CLOCK's

toggle

T210

are

all

does

T150,

while

output.

dropping

wired

and

output

not
and

TO,

The

off

and

the

shift

both

the

The

initial

four

flip-flops

reset

and

RUN

SYNC

same

T210

are

clocked

T240

aforementioned

and

time

input

occurring

point,
reaches

The

clock
a

flop

reset,

STEP

complete

0".

See

later,

functions
new

clock

bit

RUN

each

cycling

done

clock

MODE,

T60

SYNC

are

STEP

(T0O

can

the

pulse

T240)

4-39

all

output

intervals

SYNC

the

toggle

With

the

resets.

the

RUN

the

sets

occur.

time

the

SYSTEM

CLOCK

this

the
to

bit

TO.

the

SYSTEM

the

SYNC

toggle

From

When

set,

the

stopping

shift

RUN

TO0

When

flop.

set,

mode.

point

inputs

shift

both

condition

This

4-16.

clock

with

Note

SYSTEM

time

WAIT

set.

halted
the

for

"Q"
by

simultaneously

and

will

shift

stop

and

regenerated

allows
and

cycle

the

set.

180O out of phase.

Therefore,
sets

overlap

Figure

while

source

clocked

results

resetting

cycle

clock

SYNC

placing

sets,

asserted.

This

remains
nsec

RUN

zeroes,

qualified

T240,

current

CLOCK.

the

CLOCK

"time

microprocessor

all

inputs

T60

the

SYSTEM

referenced

set

conditions

bucket.

the

and

bit

when

use

T60,

the

is generated by using these two clocks

Given

into

RUN

allowing

complete

cleared.

one

_ _ __ _ .|
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otcl

4-40

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4.2.12

Address

Drawing

D16

Selection

illustrates

the

microprocéssor address.
recognition.

switches,

The

each

Address

bits

allowing

logic

address

associated

through

addressing

used

recognize

DMC-11

The JK flop OSSYN sets upon address

assigned

switch

Logic

A12

are

range

configured

with

unique

available

four

for

words

with

ten

address

bit.

configuration,

within

the

DMC-11

microprocessor.

The

logic

bits

compares

using

two

connected.
outputs

all

condition
sets.

the

high.

which

the

BOSSYN

are

remaining

true

inputs

code

chips

inputs

The

must

switch

comparator

When

the

are

asserted

with

the

respective

whose

outputs

are

wire

equal

bit

bit,

the

hi-order

ANDed

OSSYN.

with
On

130

nsec

cycle

under

initiate

NPR

for

address
"OR"
comparator

address

bits,

MSYN

produce

the

later,

clock

A13-A17,

(CK)

acknowledging

set
OSSYN

bus

master.

4.2.13

NPR

Initiation

Control

microprogram.
referencing
address
NPR

ROQ.

Logic

NPR

the

OUT*BUS

108.

This

Once

asynchronously

NPR

with

complete

cycle,

executed

the

respect

logic

the

MOVE

specifying

microinstruction
sets,

control

along

then

the

microinstruction
a

unique

with

executes

microprogram.

output

BALUO(1)
the

NPR

sets
cycle

Figure

4-17

illustrates

cycle.

The

requirements

(2)

data

and

(4)

gated

address

logic.

and

the

The

bus,

and

generates

the

responds

with

DATA

the

microprocessor

queued

all

sets

central

point,

the

further

processor

monitors

for

resets

selection

current

BUS

simply

the

master

busy

L
of

The

NPGC

when

The

take

The

turn

device

the

arrive
of
to

grant

signal.

bus

The

situation,

acknowledging

master

at
70

the
ns.

other

signal
to

the

this

soon

microprocessor

control.

processor

delay

the

discussion.

other

signal

grant

data

the

which

the

place.

does

grant

contains

data

such

c1,

gating

priority

and

its

central

address,

recognizes

following

control.
to

D15

NPR

takes

provided

its

following

RQ (1)

(SACK),

becomes

relinquishes

determine

the

microprocessor.

reception

microprocessor

BUS

then

receipt

until

NPR

acknowledge

the

NPR

UNIBUS

via

After

mastership.

When

control

NPR

stalls

BUS

for

bus

BUS

NPG

bus

lines.

propagation

prevented

the

DATA

requesters.

microprocessor,
addition,

for

(1)

output

Drawing

(slave)

D15

defined

acknowledges

assertion

signal

already

the

DATO

unit

for

are:

(MSYNC).

drawing

handshake

bus

was

also

slave

4-17

with

control

Figure

begins

devices

the

standard

(3)

addressed

the

sequence

execution

sync

(SSYN).

timing

master

sync

the

highest

for

slave

First,

then

timing

UNIBUS,

interprets

data

asserting

Refer

the

assertion

relevant

from

the

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The

actual

the

microprocessor

NPR

relinquishes
up

asserting

MASTER

The
CO0

under

C1.

bus

BUS

and

BBSY

gated

control

the

begins.

UNIBUS

with

other

DATA
—> BUS

hand,

OUTPUT

NPR

a A50

nsec

delay

which

INPUT

NPR

most

part

MSYN

cycle

the

and

BUS

multiport

terminating

4.2.14

The

then

the

RAM

and

NPR

bus

three

queued

reset

the

triggered,

the
at

control
and

well
data

conditions

master

takes

MASTER

gated

NPR

as
bus

occur

leading

the

time

edge

conclusion

OUTPUT

the

NPR

addressed

microprocessor

acknowledges

Figure

cycle.

4-18

slave

then

loads

receipt

and

this

case

respond
the

dropping

for

the

with

data

into

BUS

MSYN

cycle.

Control

operation.
actual

SACK

cycle,

illustrated

the

for
The

Interrupt

waits

the

execution

two-phase

timing

SSYN.

then

the

asserted.

similar

microprocessor
data

NPR

These

during

microprocessor

now

during

BUS

the

Simultaneously,
cycle

place

microprocessor

simultaneously
MASTER,

takes

Once

provided

NPR

transfer

master.

H],

The

Data,

data

bus

[SACK(1)

set.

address
and

the

1is

cycle

Logic

interrupt
First,

INTERRUPT

cycle
bus

cycle

accomplished

mastership
execution.

must

through

gained

and

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Figure
an

4-19

illustrates

INTERRUPT

assertion

cycle.

The

RQ.

with

bit

address

sets

RQ.

With

both

MASTER

satisfied

generate

Card
to

the

grant
this

again
When

turn

central

awaiting

bus

058,

which

point,

this

cycle.

the

until

INTR

4.2.15

Line

Interconnection

done

via

signal
the

the

lines

LINE

UNIT

IN),

asserted

interrupt

from

the

(1)

equal

condition

feeds

the

bus

logic

PDP-11

and

resets

becomes

the

bus

sets

while

begins

simultaneously

interrupt

vector

operation

concluded

when

the

interrupt

BUS

bus

the

and

control."“j

INTERRUPT

the

address

the

When

master

relinquishes

which

\j/

stalls,

SACK

master

signal

Processor.

the

Priority

request

then

one,

sets

bus

the

output

places

onto

central

with

BUS

SSYN.

microprocessor

and

the

processor

Interface

UNIT

between
and

The

with

the

appropriate

current

between

LINE

reset,

having

operand

the

MASTER

receipt

Unit

the

execution

initiated

BUS

The

for

signal

the

acknowledges

microprocessor

logic

bus.

process

still

generates

microprocessor
data

SACK

sequence

microinstruction

seven

BUS

(BUS

happens,

BUS

MOVE

and

grant

arrives

timing

entire

processor.

bus

stalls

the

interface.

the

two

units,

remaining

The

of
in

interface

which
the

line

cable

eight

unit

carries

originate

microprocessor.

BR RQ #

BUS BR
L

1L A

8G IN H

._____{

BUS SACK /

BUS BSSY L

BRMASTER () H
BUS INTR

SSYNV H

NN,

BUS VECTOR AOKS

OR DONVE

Figure

4-19

Interrupt

4-47

Timing

Diagram

4.2.15.1

These

IBUS

eight

lines

line

unit

the

and

addressed

4.2.15.2

BALUOL

eight

goes

line

unit.

the

4.2.15.3

This
is

signal

asserted

4.2.15.4
BT240

IBUS

Line

delivers
the

unit

data

input

microword

bus.

the

This

bus

originates

microprocessor

(CROM

CROM

from

the

2).

BALU7L

are

buffered

the
ALU

microprocessor
register

then

output

the

bus.

The

interface

data

the

L/IBR*H

acknowledges
during

used

OBW

signal

the

line

unit

receipt

data,

and

T240.

BT240

4.2.15.4
This

the

lines

IBR

are

These

synchronize

the

line

unit

with

the

microprocessor.

the

output

data

strobe.

clock

strobe

the

output

asserted

low

indicates

The

data

line

into

unit

uses

this

internal

4.2.15.5

This
the

signal
output

OUT

when
data

the

*OUT

BUS

instead

the

line

the

OUT

unit
BUS.

direct

4.2.15.6

CROM

These

bits

are

CROM

address

CROM

0-3

and

CROM

the

internal

4.2.15.7

This

input/output

registers.

the

input

The

address
output

registers

with

used

the

line

registers

are

addressed

bits

CROM

unit

4-7.

Clear

signal

initializes

the

line

unit

placing

reset

state.

4.2.15.8

With

this

diagnostic

transmitter

4.2.15.9

This

its

Step

signal

4.2.16

Loop

Typical

Figure

system

timing

shows

with

typical

line

from

T90

valid

strobed

OBW

through

from

line

unit

loops

data

advance

one

cycle.

from

its

line

T300

illustrated

applicable
unit

unit

Timing

while

internal

signals

logic.

approximately

into

the

System

4-20

the

receiver.

commands

Typical

function,

Note

the

T270

used

4-20

the

address

for

the

cycle

through
with

the
the

next
low

and

output

that

data

Figures

T240.
to

cycle

high

4-21.

along

wvalid

question

1is

The

1is

data

transition

@
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(CROM @-3)

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240NS

300NS

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Figure

4-20

GONS

Typical Output Bus Timing

JEONS

/BONS

P40NS

FOONS

IN ADRS

(CROM 4-7)
.

/N DATA

(IBUS @-7)

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IN DATA

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Figure

4-21

Typical

4-50

Input Bus

Timing

_/”\

Input bus
address

(T90
bus
T160

timing

valid

for

T300).

during
-

T240

illustrated
the

same

The

line

unit

its

time,

which

the

in Figure

period

then

places

4-21.

data

approximately

microprocessor.

the

Again,
output

cycle

the

coincides

the

input

with

—

CHAPTER

MAINTENANCE

5.1

SCOPE

This

chapter

lists

required

description

maintenance

procedures.

5.2

Maintenance

Basically,
and

DMC11

corrective

maintenance
performed

DMC11

aging

The

regularly

conditions

procedures,

damage

attempt

caused

handling

corrective

maintenance

isolate

the

failure

the

failure

primarily

maintenance

for

future

5.3

intervals

log

component

reference

complete

corrective

the

programs,

procedures
any

preventive

deterioration

the

procedures

are

performed

module

isolation

due

environmental
and

level

and

Only
and

interconnect

correct

under

to
the

unusual

component

corrective

maintenance

procedure.

record

maintenance

activities

all

analysis.

ensure

consists

proper

tasks

equipment

performed

operation

are

module

replacement.

and

Maintenance

maintenance

used

and

detect

microprocessor

module

considered

Preventive

through

should

The

diagnostic

extremes

The

and

consists

maintenance

cable.

replacement

provides

preventive

maintenance

preventive

improper

circumstances

and

Philosophy

maintenance

any

equipment

microprocessor

log.

and

test

and

periodic

minimum

unscheduled

down-time.

operational

checks

The

preventive

and

operating

Under

normal

every

and

conditions

visual

the

inspection,

diagnostics.

depends

exist

preventive

and

consist

schedule

that

However,

humidity

tasks

running

maintenance

months.

temperature

These

the

installation

maintenance

relatively

mechanical

extreme

shock

environmental

should

site.

conditions

may

demand

performed
of

frequent

maintenance.

5.4

Test

Maintenance
standard

Equipment

Required

procedures

test

for

equipment

the

and

DMC11

microprocessor

diagnostic

programs

regquire

listed

the

Table

5-1.

5.5
The

Corrective
corrective

service

Maintenance

maintenance

technician

DMC11

microprocessor

module

replacement.

microprocessor

determining
module

For

those

situations

the

basic

microprocessor

into

140g

and

where

and

that

this

designed

aid

failure

the

through

involves

running

the

any

1level

test

the

failure

error

repalr

MAINDEC-11-DZDMC

sequentially

the

observing

component

test

are

correcting

Essentially

diagnostics

subtest

procedures

each

messages.
is

has

section

required,

been

divided

logic.

The

free-running

corrective

functions

5.5.1
The

test

maintenance

correctly

Diagnostic

DMC11

during

MAINDEC-11-DZDMG
to

using

can

These

Maintenance

Mode

System

(free

Test

Maintenance

mode

current

bit

15),

CROM

current

can

step

location

CROM

that

the

microprocessor

control

ROM

(CROM),

full

that

the

instruction).

tested

invoked

using

two

basic

using

selected

bits

the

microprocessor

(assert

bit

with

(assert

(set

OFF

that

bits

With

this

SEL1

allow

the

and

setting

bit

upper

8),

examine

CSR

6),

different

bits

LOCK

access

and

load

OUT

(switch

the

E76)

maintenance

ON,

however,

clear

the

microprocessor

the

first

5-3

CSR.

still
by

the

override

instruction

CSR.

switch

possible

the

bit

NOTE

sure

modes

These can be used to halt the microprocessor

instruction

speed.

running)

instruction

execute

new

after

Mode

byte of the first CSR.
(clear

used

are:

5.5.1.1

the

its

Modes

microprocessor

servicing.

ensure

should

CSR

and
6

with

T
T

5.5.1.2

System

This

tests

mode

full

speed

ERTNAEENTEC
W

Test
the

and

functionality

utilizing

the

control

microprocessor

running

ROM.

NOTE

sure

OFF

the

operating

RUN

INHIBIT

utilize

this

switch

mode

and

(switch

for

E76)

normal

conditions.

Table
Test

Equipment

5-1

Equipment

Required

Manufacturer

Designation

Multimeter

Triplett

Oscilloscope

Tektronix

Type

X10

Tektronix

P6008

DEC

W984

(Double)

W987

(Quad)

Probes

Module

(2)

Extenders

Simpson

Model

630-NA

260

453

NOTE

For
a

Diagnostic

Tapes

DEC

hex

double

DZDMC,

board
and

DZDMG

us
guad.

APPENDIX

PDP-11

MEMORY

ORGANIZATION

AND

ADDRESSING

The

PDP-11

8-bit

memory

bytes.

location;

low

numbered.
and

the

organized

Each

byte

bytes

are

Words

high

provide

CONVENTIONS

are

(odd)

16-bit

word.

addresses.

even

location

Eighteen

bits

locations

select

address

each

128K

16-bit

1024

word

provide

256K

A
an

byte

this

high

own

bytes

words

are

two

address

are

odd

locations

automatically

only

included

therefore

addresses

found

odd

byte.

bits

8-bit

identified
addressing

byte.

discussion,

represents

its

numbered

capability

and

consisting

has

operation

contains

the

words

and

even

word

8-bit

which

words.

that

the

Consecutive

numbered

Unibus

numbered

addressed

byte

16-bit

addressable

even

The

262,144

This

the

A(17:00).

256K

memory

also

represents

multipler

locations

equals

and

238K

represents

used

only

f/-\

131,072
PDP-11

locations.
processor

address

bits.

The

with

maximum
memory

Without

this

memory

size

management

unit,

the

can

unit

that

processor

utilizes

provides

all

address bits which iimits the maximum memory size to 64K (65,536)
bytes

Figure

32K

A-1

256K bytes.
262,144

(32,768)

shows

the

words.

organization

for

the

maximum

memory

size

In the binary system, 18 bits can specify 218 or

(256K)

locations.

The

octal

A-1

numbering

system

used

designate

the

address

shown

The

address.

the

address

binary

provides

system

convenience

that

the

highest

general

physical

memory

reserved.

for

result,

this

area;

words

program.

PDP-11

these

locations

registers

assigned

processor

and

(760000-77777)

peripheral

addresses;

only

programmable

therefore,

without

the

memory

the

memory

(32K)

A(17:16)

master

with

only

maximum

converting

uses

words.
1s

bits

allow

16-bit

Logic

processor

A(15:13)

generation

are

all

There

cannot

(64K)

forces

addresses

124K

provides

locations

65,536

when

are

bytes

unit

(64K)

the

248

management

for

numbers

has

size

reserved

locations

user

memory

address

the

bytes

bits

processor

reserved

area

control.

17|16 |1511¢]13102]11 /0|9

32,768

The

A-2).

(Figure

are

devices.

16 address bits that specify 216 or 65,536

below.

internal

This

4|3 (2|l

|O|AVLRESS BIT

01010|/ 0|

B/INARY

JCTAL

08|07

le— 16 BIT DATA WORD —|
HIGH BYTE

LOW

BYTE

000001

000000

000003

000002

USER ADDRESS SPACE
AVAILABLE

USING 18

ADDRESS BITS ON
e

g___./

POP-11 PROCESSOR
WITH

MEMORY

MANAGEMENT

OPTION,

INCLUDES 248K (253,952)

BYTES OR 124K (126,976)
WORDS.
757777

757776

760001

760000

HIGHEST 8K (8192)

BYTES

4K (4096)

WORDS RESERVED FOR

DEVICE REGISTER

ADDRESSES.

*217777

777776

LAST ADDRESS IS BYTE

NUMBER 262.14310

MAXIMUM SIZE

WITH 18 ADDRESS BITS IS

256K(262,144) BYTES OR 128K (131,072) WORDS.
11-1690

Figure

A-1

Memory

Organization
18

Address

A-3

for
Bits

Maximum

Size

Using

1s
oslo7
00
le— 16 BIT DATA WORD —
HIGH BYTE

LOW BYTE

000001

000000

000003

000002

USER ADDRESS SPACE

AVAILABLE

—T

USING 16

ADDRESS BITS ON
POP-11

PROCESSOR

WITHOUT MEMORY
MANAGEMENT OPTION.

INCLUDES 56K (57,344)
BYTES OR 28K (28,672)
WORDS.

187777

187776

160000

160001

w
ADDRESSES 160000177777 ARE CONVERTED
TO 760000-777777 BY
"

——/fl’—fi

THE PROCESSOR. THUS,
THEY BECOME THE
HIGHEST 8K (8192) BYTES

OR 4K(4096) WORDS

177776

*177777

LLAST ADDRESS 1S BYTE NUMBER 65,535,
MAXIMUM SIZE WITH 16 ADDRESS BITS IS

RESERVED FOR DEVICE
REGISTER ADDRESSES.

64K (65,536) BYTES OR 32K(32.768) WORDS.
I1-1689

Figure

A-2

Memory

Organization
16

Address

A-4

for
Bits

Maximum

Size

Bit

becomes

(56K) .
byte

This

memory.

highest

locations

bytes

Memory

the

are

28,672

problem

less

are

addresses

memory

locations

PDP-11

core

highest

location

words

56K

than

interfering

Memory
K-Words

(28K

Size
K-Bytes

8K bytes

last

the

bus.

the

64K

160000-177777

bytes

(4K

These

general

the

57,344

user

are

the

has

words)

and

57,344

words)

under

the

reserved

area,

because

not

have

there

with

the

available

various

decimal

(56K)

progranm.

and

locations

internal

with

160000

are

which

last

therefore,

bytes

converted

these

for

addresses;

memories

the

accessible

reserved

160000

converts

interference

designations

relocates

(28K)

capacities

octal

processor

locations

device

beginning

which

that

peripheral

first

the

The

760000-777777

the

size

core

binary

not

possibility

bit
of

space.

increments.

memories

Highest

are

shown

Location

(Octal)

017777

037777
057777

077777

117777

137777

157777

A13.

physical

reserved

have

The

below.

ADDENDUM

DMC11

IPL

MICROPROCESSOR

MAINTENANCE

(EK-DMCMP~-MM~001)
October

1976

MANUAL

Changing

the

Option

Designations

’g/"“w .

This

manual

that

refers

with

all

used

the

DMC11-AD

versions

Microprocessor
the

local

and

(M8200-YA

remote

module)

DMC11

line

units.

The

DMC11-AD

(M8200~-YA
other

unit.

The

option

module),
DMC11-AL

line

has

been

which

replaced

used

(M8200-Y@),

unit

option

only

which

two

with

the

used

designations

options.

have

remote

One

line

DMC11-AR

unit.

only

with

the

not

been

changed.

local

The
1line

o
The

following

table

describes

the

mircoprocessor

and

line

unit

options.

Option

Module

Description

DMC11-AR

M8200~YA

Microprocessor

; /-\*.

microcode

Prerequisite

for

applications

with

DDCMP

PDP-11

remote
(M8201

Line

Unit)

I/\
DMC11-AL

M8200-YB

Microprocessor
microcode

for

applications

with

DDCMP

PDP-11

local
(M8202

Line

Unit)

DMC11-DA

M8201

Line
for

unit
EIA

/""“*-:,

A1l

with

cable

interface

for

DMC11-AR

DMC

11-FA

M8201

Line

unit

V35/DDS

DMCl1l-MA

M8202-YA

Line

M8202-Y0O

Line

unit

Sections
and

the

with

for

DMCl1l-AR

bps

DMCll-AL

modem

unit

integral

Programming

cable

interface

integral

DMC11-MD

with

56K

bps

DMCll-AL

modem

Sections

3.4.2.1

through

corrected

version

Replace

page

3-6

Retain

pages

3-7

3.4.2.15
is

have

been

substantially

revised

attached:

through

3-13
S

\—/

Replace

Retain

pages

the

3-14

rest

through

the

3-37

chapter.

The

port

loaded

the

microprocessor

The

format

contents

type

(TYPE

and

output

TYPE

PDP-11

input

transfers

and

the

transfers.

the

data

port

Qépend

the

transfer

O0).

In discussing the data port me;égg; formats, it is segmetimes more
convenient

use

word

desighations

(SEL4

and

SEW6)

rather

than

byte designations (BSEL4/{).
There

are

four

foryéts.
&4

1. Buffi!fi address/character /count input and output (BA/CC I
/

%?fi

BA/CC

0).

2.//%ase input (BASE I)//
/

/7( Control input (CN%L 1I)
4.

Control

output

ALCONL

O0)

1. BA/CC I andfé;/cc O Format

The formafi; for BA/CC I and BA/CC O are the same (Figure
/

3-1). /g£L4 contains the least significant 16 bits (0-15)
of

the

bits
14

(16

and

bit

and
of

buffer

17)

SEL6.

SEL6

contain

2's

complement

the

address.

The

two

this

address

are

The

remaining

character

notation.

3-15

count

most

significant

contained
bits

(0-13)

positive

bits
of

notation

not

The

microprocessor

each

for

size

which

For

input

the

For

core

stack

output.

(BASE)

bytes.

256

maximum

This

tables

operations,

BA/CC

number

the

seven

BA/CCs

based

PDP-11

the

memory

supplies

new

message

buffers

returns

the

buffers

microprocessor.

output

PDP-11

and

limited

input

can

operations,

that

were

BA/CC

successfully

transferred

the

microprocessor.

BASE

SEL4

and

reserved

Format

(Figure
the

bits

and

The

block

address
must

block

3-1).

BASE

program

not

SEL6é

provide

addresses

the

size

the

256

any

locations

first

PDP-11

bytes.

microprocessor,

modify

the

address

memory

Upon

assigning

the

PDP-11

within

the

assigned

cleared,

block.

Bit

the

microprocessor

set,

the

SEL6

the

called

RESUME.

initializes

microprocessor

contents

the

base

the

resumes

table.

3-16

this

base

bit

table

operation

and

protocol.

specified

’

I-S

WS«.t

x- .

- .

r“

CNTL

The

CNTL

Format

control

shown

format

functions

(Figure

means

implementing

certain

3-1).

Name
SECONDARY

ADDRESS

(SEC ADRS)

provides

below.

Bit
0-7

DDCMP

’//

M%ZNTENANCE
/

(DDCMg/MAINT)
|

/With

this

‘fl
/

set,

the

microprocessor

enters the DDCMP maintenance mode
where

quently

bit

remains

until

subse-

initialized.

/
9

RESERVED

DDCMP!AALF

(DqgéP HD)

DUPLEX

With this bit

set,

DDCMP half duplex

operation is selected.
cleared,

DDCMP

selected.

with bit
—

3-17

11.

full

This

With this bit

duplex

bit

must

operation

used

Bit

Name

Description

DDCMP

(SECONDARY

With

DDCMP

SEC)

secondary

station

operation

selected.

With

bit

DDCMP

duplex

this

half

operation

full

12,

set,

DDCMP

this

half
is

cleared,

primary

selected.

duplex

station

Not

used

for

duplex.

RESERVED

CNTL

The

CNTL

PDP-11

Format
O

format

program

hardware,

PDP-11

provides
error

remote

station.

SEL4

and

this

format.

The

shown

below

(Figure

bits

and

means

conditions

program,

the

Bit
0

bit

control

(DATA

CHECK

CK)

informing

involving

communications

SEL6

bits

contain

are

the

DMC11

channel,

the

located

address

SEL6

3-1).

Name
DATA

Description
When

set,

this

retransmission

bit

indicates

threshold

that

has

been

that

exceeded.

TIME

OUT

When

this

bit

indicates

microprocessor

has

received

3-18

set,

the

Bit
1

(Cont.)

Name
TIME

OUT

OVERRUN

Description

(Cont.)

(ORUN)

response

from

link

for

When

set,

message

the

end

the

seconds.

this

was

availabl

remote

indicates

xeceived

but

receive

1it.

that

buffer

d
DDCMP

MAINTENANCE

RECEIVED
MAINT

Whén

(DDCMP

RECD)

set,

// message

format

has

protocol

this

bit

the

DDC

inddcates

maintenange

maintenance

been/received

opeyation

that

has

and

that

entered

the

state.

LOST,bATA

Whegfiset,

this

bit

indicates

that

the

r?éeived message

longer

than

the

Jéupplied buffer.

RESERVED

DISOONNECT

When

set,

this

bit

indicates

off

Set

Ready

lead

has

been

DDCMP START

When

set,

this

bit

indicates

RECEIVED

DDCMP

START

(DDCMP

RECD)

the

transition

Start

protocol

Maintenance

3-19

message

was

state.

the

that

modem

Data

detected.

that

was

received

the

Running

a
when

Bit

Name

NON

Description

EXISTANT

MEMORY

(NON

When

set,

Unibus

this

address

bit

indicates

time

out

has

that

occurred.

MEM)

PROCESSOR

(PROC

3.4.3

Input

Whenever

seized

the

assign
must

ERR)

data

port

the

PDP-11

port

before

specify

the

receive

buffer,

control

The

PDP-11

appropriate

type

the

port.

program

transfer

These

microprocessor

the

port

has

this

bit

indicates

that

program

has

performed

procedural

error.

use,

for

use

not

program

also

make

set,

PDP-11

microprocessor

the

can

When

the

Transfers

the

Therefore,

ERROR

set

bits
bit

bits

may

responds

data

port

(BSEL4-7).

takes

the

and

output
the

transfer

program

Then,

clears

set

0-2
5

etc.)

the

being

transfer.

microprocessor

input

transfer.

transmit

the

RDYI

BSELO

single

bit

PDP-11

should

Request

setting

assigned

PDP-11

input

with

subject

buffer,

microprocessor

preparations.

set

the

request

information,

then

set,

data

type

should

been

proceeding

and

been

must

load

should
which

(RQI)

program.

clear

(RDYI)

When

desired

RQI.

completes

the

The

the

request

instruction.

Ready

the

indicate

The
when

RDY1

data

has

into

the

microprocessor

transfer.

Bit

the

PDP-11

the

microprocessor

RQI

immediately

below

BSELO,

have

program

megabit

receiver

Interrupt

Enable

receives

has

set

(within

idle.

interrupts

Input

interrupt

RDYI.

The

megabit

most

disabled

waiting

must

(to

when

Vector

when

either

efficient

and

controls

fogr

simply/scan

Set it.

prepared

whether

XX0)

microprocessor

microseconds)

times until the microprocessor has
program

(IEI),

responds

operating

when

speeds

transmitter

the

PDP-11

program

RDYI

one

While the PD€f11
accept

oufput

transfer because the microprogessor may have seizig/{;e
port in
the

meanwhile.

The

microprocessor

immediately.

For

canhot

exXample,

service

the

certain

PDP-11

P§pes

padbram

//'

may

input

transfers

attempt

queue

than

buffers

convenient to use

for

transmission.//In

interrupts.

these

1If Eyé PDP-11

cases,

program finds RDYI

clear afteré;veral scans, it caq/énable interrupts by setti
ng IEI
with

(to

BI%/or

Vec%%r

MOV

XX0)

1nstruct10n.l/The

when

the

DMC11

mlcgfiprocessor

interrupts

has

set

the

RDYI.

PDP-11

The

PDP-11

program/gets the interrupt ih all cases, even if the
microprocessor
had already set RDYI at tpé time the program sets IEI.
The program
can

bypass

any

scanning

IEI

set

when

the

program

NOTE

The

PDP-11

input

program

transfer

should

until

the

not

begin

new

transfer

sets

RQI.

until

the

indicated

RDYI.

The
or

PDP-11

transfer
has

been

This

can

has

been

the

data

initiates

until

full
The

time

format

and

before

scanning

the

this

within

has

cleared
to

begin

should

check

setting

RQI.

RDYI

output

transfer

buffer

until

that

the

data

port

input

for

CLEAR

microprocessor

has

(BSEL4-7)

been

loads

and

significance

sets

bits

the

PDP-11

program

can

transfer
if

the

not

error

data.

that

and

has
or

not

has

BSEL2

then

sets

use

for

initialized

any

information

assigned

INIT

PDP-11

buffer

not

the

status

output

is,

generate

the

empty

PDP-11

generating

does

0-2

initiate

free;

initialized

status

when

reception

However,

MASTER

transfer

the

microprocessor

transfer.

microprocessor

port

setting

UNIBUS,

transfer

The

clearing

wishes

completed,

cleared.

program

output

DMC11
the

any

PDP-11

program

cleared

done

been

Transfers

return

the

does

immediately,

RDYI

transmission.

the

information

transfer

has

microprocessor

ROI.

microprocessor
error

the

after

Output

wishes
on

The

transfer

microseconds

new

3.4.4

signal
output

progranm.

into

the

indicate

bit

the

BSEL2,

Ready

Out

(RDYO)

available.

1In

response

note

the

type

and

read

the

data

sampled

all

clearing

indicate

the

RDYO.

output
in

the

RDYO

PDP-11

setting,

transfer

data

port.

data,

must

complete

This

frees

data

the

When

port

II/

the

PDP-11

transfers

program

wishes,

setting bit

usually does not know whip/an output ¢tr
a messagy/will

interrupts

program

ordinarily

/
. The
sef

Output

will

occur

efficient

interrupfs

output

transfers.

reading

NoTE

gfle

data

and

clearing

RDYO.

Fdilure to do}%is prevents the data port from

being freed.//If the PDP-11 program has

requested ?5 input transfer by setting RQI,
it

must

transfer
PDP-11

never

prepared

prior

program
gets

(for

PDP-11

PDP-11 prografl/hust respond to RDYO being
by

output

%Aables
I

respond

being

given

RDYI.

fails

RDYI.

The

respond

PDP-11

(IEO).

(to Vector XX4)

sfer

receiy'ed)

has

Sipce the PDP-11 program

when

transfer

BSEL?2

subsequent

If TEO is set, the DMC11 interffi;ts the PDP-1

example,

program

Interrupt Efléble

after the microprocessor has/get RDYO.

should

canfenable

6 of Bssyé,

0-2

1is

PDP-11

data

program

bits

output

for

transaction.

the

that

PDP-11

specified

the

programs

output
If

the

RDYO,

program

should

not

spin

test
are

RDYO

unless

enabled,

priority

3.4.5

RDYI

loop

that

interrupts

and

level

the

than

loop

the

doesn't
output

executes

DMC-11

also

transfers

lower

interrupts

level.

Initialization

The

power

The

PDP-11

MASTER

sequence

program

CLEAR

and

can

UNIBUS

INIT

accomplish

BSEL1.

Each

the

signal
same

these

initialize

effect

procedures

the

DMC11.

setting

restart

the
—

microprocessor
state,

the

serial

When

the

perform

The

PDP-11
11.

bits

address

Once

the

table

beginning

program

its

not

send

output

that

PDP-11

memory,

requests

response

the

address

into

bits

and

DMC11

which

BASEI

the

SEL4

specifies

the

RDYI,

microprogram.

the

to
the

this

messages

loads

high
If

RESUME

initialized,

the

has

specified

base

called

SEL6.

function,

transfer

program

and

receive

transfers.

the

transfer

whiches

does

generate

program

the

Base

the

TYPEI

low

order

bits

the

protocol

(bit

PDP-11

INIT

the

microprocessor

MASTER

CLEAR.

address,
until

The

the

PDP-11

the

128

DMC11

program

SEL6)

word

base

master

may

)

Table.

setting

DDCMP

bit

must

address

order

clear.

belongs

cleared

input

table

operation
must

line

word

the

microprocessor

PDP-11

128

examine

the

contents

relating

base

protocol

supplying

microprocessor
sequence

the

base

received

microprocessor

table

operation)

address

from

the

not

but

with

conditioned

does

(for

example,

error

counters

must

alter

its

the

not

RESUME

respond

remote

initiate

system.f

the

bit

clear,

the

DDCMP

However,

start-up

contents.

the

start-up

the

sequerce

microproce

its

accord unless the PDP-11

own

program sugpiies a buffér of data to be

transmitted.

//!

If the DMC11 is connected Bdfa half-du
Y

channel, the PDP-11

program must now performxén input trdAnsfer using the Control 1In
A//.‘\

format

and

set

the

Ha}f

Duplex

(HD)

SEL6

(bit

10).

addition, the proggd; must speglify whether the DMC11 is to operate
as a hélf duple%/éécondary aflgtion (3 second timer) or a half
duplex

the

primary/station

Secondarxf

bit

(SECb,in

ASecond

timer)

SEL6

(bit

11).

setting

half

clearing

duplex

link

must have %he primar;/gtation and one secondary station.

The only

difference between/éhe two is in the length of time spent before

retransmitting i)/gase of errors.

Half duplex operation may be

specified at ap§ time by a Control In transfer to accomodate
switching
DMC-11

options

strapped

Control

for

half

duplex

containing

half

duplex

back
the

integral

operation

transfer.

—

communications

modem

must

addition

channel.
be

The

specifically

requiring

the

3.4.6

DDCMP

Before

data

Start

messages

may

transmitted

start-up

sequence

the

link

are

the

running

state.

both

ends

simultaneously.

data

buffer

start

The

completed

initialized

Either

end

and

may

received,

the

DDCMP

make

certain

both

ends

place

initiate
If

transmitted,

the

start

PDP-11

local

protocol

sequence

program

DMC11

supplies

initiates

the

sequence.

PDP-11

program

may

However,

one

Once

the

local

and

flags

the

start

sequence.

Control

Out

has

begin

Data

the

Character

PDP-11
The

the

that

result,

with

the

SEL6

the

sequence

running
the

the

bit

(DDCMP

program

knows

PDP-11

program

end

that

has

program
START

the

should

sequence.

significant.

state,

other

PDP-11

start

detects
initiated

receives

REC'D)

other

set.

end

initialize

the

again.

Transmission

PDP-11

bits

fact

details

entered

the

restarted.

and

clears

the

property

has

error

transfer

link

3.4.7

DMC11

happens,

DMC11

ignore

important

this

When

correctly

may
of

must

program

and

Count

specify

that

this

requests

input

wishes
BSELO

transfer

full

transfer

and

indicate

clears

buffer
by

transmit

setting

bit

buffer

Buffer

data,

Address/

BSELO

(INI/O)

transmitted.

RQI.

response

It
to

then
RDYI,

loads

SEL4

with

the

low

order

SEL6

with

the

high

bits

and

bits

from

remote

16,383

operation

about

SEL6

bytes

with

long

buffers

the

bits

order

bit

the

bits

buffer

address,

character

may

used

should

1limité€d

for

local
to

the

count.

operation.

practical
~

512

bytes,

facilities,

Each

depending

buffer

the

error

correspopds

rate

Buffers

For

maximum

communications

single/DDCMP

data

message.

When the message has beep/;uccessfull

transmitted

and

rocessor

initiates

output

clear

indicate

the

Buffer

Bit

(OoUT

I/0)

acknowledgement rece%yéa, the micr
/

transfer

with

bits/4

Address/CharacteX

and

Count

Out

BSEL2

g?%/CC O)

format.

is clear to

ipgdicate that ?/successfully transmitted buffer has

been returngd to the prog{;m.
/

The

PDPA11

program

supplying

them.

m@y

buffeys

attemp

queue

the

queue

than

/to

delay

granting

until

has

been

returned.

buffegr

buffers

microprocessor

microprocessor
a

seven

the

for

faster

seven

than

buffers

request

for

transmission

forces

the

input

NOTE

The

PDP-11

transfer
are

program

that

already

should

supplies

outstanding,

not

request

transmit
unless

buffer
is

input
if

certain

returns

the

transfer

that

the

enough

buffers

two

PDP-11's

queue

buffers
and

3.4.8

Data

When

the

with

received

BA/CC

then

requests

loads

count

the

and

SEL4

same

message

has

BSEL2

SEL4

and

SEL6

set

DMC11's
no

microprocessor

made

attempt

receive

deadlocked

BSELO

setting
the

indicate

the

indicate

(IN

I/0O)

specify

for

ROI.

full

address

buffer
of

the

The

response

has

and

character

message

and

output
BA/CC

reception.

address

received

the

fill

BSELO

longest

buffer

the

initiates

wishes

transmission.

successfully

available

for

and

with

indicate

contains

characters

message

particular,

buffer

accommodate

been

transfer

clear

bits

been

microprocessor

I/0)

supply

DMC11's.

empty

bit

When

number

sets

format

enough

(OUT

can

become

their

clears

SEL6

large

while

they

and

connected

has

input

must

and

link

reception.

queued,

buffer

the

buffers,

program

data,

RDYI,

the

for

Reception

empty

buffer,

end

initialize

transfer

that

are

must

PDP-11

other

stored

expected,

transfer

with

format.

Bit

been

buffer

count

the
bits
2

received,

and

the

actual

received.

received

informs

when

the

PDP-11

receive

buffer

means

available,

Control

Out

the

transfer

with

bit

informed

SEL6

the

error

The

PDP-11

program

The

PDP-11

may

supplying

them

buffers.

(O'RUN
and

the

attempt

set,

The

automatically

should

queue

ERR)

supply

seven

other

queue

morf£

than

soon

buffers

microprocessor/faster

retransmits

buffer

empty

end

than

seven

the

for

the

link

message,

possible,

reception

returns

buffers

forces

the

microprocessor to delay grantiyé the reques$t for input transfer
until a full buffer has beep/returned.

)

The PDP-11/$rogram shiould not request an input
,

transfey'than sup?{ies a buffer for reception
/

cepytain

already
that

upplying

outstanding,

unless

other

the

buffers

for

end

link

is
1is

transmission.

Control

Transfers

icroprocessoy
conditions
the

link,

transfer
Control

the

Out

the

hardware

with/bit

operation
program

involfing
DMC1

error

informs

(CNTL

))

condition.
may

PDP-11

BSEL2

clear

transfer.

Some

the

program

communications
or

continue.

initialize

the

errors

Others
DMC11.

and

bit

set

advisory

fatal

and

unusual

remote

end

means

contains

are

channel,

program

SEL6

that

nature

require

output

indicating

bits

error

indicate

the

and

normal

PDP-11

Bit

been

(DATA

CK)

exceeded.

occurred

for

(More

supply

counters
a

the

non-fatal

normal

This

corrected

corrected
program

Bit

are

(TIME

from

failure
Like

DATA

CK,

consecutive

reception.)

that

the

other

reception.

The

Should

the

cause

continues

with

error

appear

may
the

DMC11

counted

indicates
remote

this

detalls

lost

are

not

the

link

the

condition

the

errors
PDP-11

table.

broken
link

non-fatal

either

the

reported

corrected,

Transient

microprocessor

failed

This

until

the

has

error.
be

that
of

link

defective

error

initialized.

examine

the

error

repeatedly

can

the

base

end

has
have

indicates

the

indicates

other

This

PDP-11

threshold

retransmissions

messages

retransmissions

This

the

seconds).

retransmission

for

OUT)

table

until

before

but

response

(21

base

operation

for

error.

direction.

than

channel

buffer

that

transmission

communications
to

indicates

for

has

specified

communications

(possibly

error

which

received

a
can

period

channel

power

failure).

occur

repeatedly.

Bit

(O'RUN)

indicates

was

available.

This

can

prevent

this

error

that
a

message

non-fatal

from

was

received

error.

recurring

The

repeatedly

but

PDP-11
by

buffer

program

supplying

buffer.

Bit

(DDCMP

MAINT

Maintenance

format

has

the

entered

REC'D)
was

indicates

received

Maintenance

and

state.
3-30

that

message

that

the

protocol

the

DDCMP

operation
“'\.../

Bit

(LOST

longer
a

than

fatal

Bit

DATA)

the

indicates

buffer

that

supplied

message

the

was

PDP-11

received

program.

that

This

error.

(DISCONNECT)

indicates

that

off

transitiog

the

modem

Data

Set

only).

This

PDP-11

program

has

Ready

connected

has

non-fatal

must

lead

detegted

error.

consider

the

been

the

DMC11,

considerations.

(remote

dial-up

ssibility

X£his

op€ration

opgeration,

thAt

requiXed

new

the

caller

security

/
Bit

(DDCMP

START

REC'P)

indicates

£Ahat

DDCMP

Start

message

was received when téy/;rotocol wag in the Running or Maintenance
states.
its

This

end

ind}éates

ink.

the

may initializé
the

start-

Bit

(NON

that thé

remote

computer has

This fi7/a fatal error.

the DMC11

initialized

The PDP-11

program

ifl/it wishes to start over and complete

sequence.

MEM)

indicates

that

UNIBUS

address

time

out

occurred.

This co;i; have been caused by the PDP-11 program

specifying

was

illegmlly

stored

inva&lid

base
in

the

defective.

Thys

Bit

ERR)

indicates

(PROC

PDP-11

program.

due

The

programming

address,
base

fatal

table

address,
the

PDP-11

count,

memory

that

1is

error.

procedure

requested

error.

buffer

has

input

This

error

transfer

error

can

the

can

part

the

not

honored

caused

requesting

BA/CC

before

second

time,

This

3.4.10

down

line

error

computer

half

requesting

invalid

code

base

address

BSELO

bits

and

format,

restarting,

systems.
but

the

are

Maintenance
or

otherwise

Messages

unsequenced,

automatically

the

message,

this

used

maintaining

format

are

unacknowledged,

DMC11.

subject

and

Transmission

not

always

duplex.

Maintenance

messages

microprocessor
program

CNTL

may

transfer

message
CNTL

is
O

state

Once

can

only

the

DDCMP

the

with

bit

the

received.

change

DDCMP

and

received

data

portion

1In

with

and

generating

the

sent

and

SEL6é

case,
MAINT

mode,
data

message

header

and

set

taken

the

from
On

PDP-11
by

The

maintenance

SEL6

performs

indicate

message.

messages

messages.

data portion is'placed in the buffer.

set.

maintenance

CRC's.

the

state

microprocessor

REC'D

while
The

this

MAINT)

state

the

state.

enter

(DDCMP

Maintenance
this

received

maintenance

availability

similarly

the

DDCMP

maintenance

microprocessor

enters

transfer

the

DMC11

cause

microprocessor

address,

Messages

loading,

retransmitted

base

error.

message

checking

specifying

fatal

DDCMP

satellite
to

Maintenance

special

for

supplying

can

transmission,

buffer

reception

with
only,

sent
the

the
the

Messages not in DDCMP

maintenance

format

having

incorrect

CRC's

are

simply

discarded.

The

data

portion

that is desired,

the

maintenance

message

may

contain

any

data

but ordinarily it conforms to,{he Digital

Maintenance Operation Protocol (MOP) forma;si

When a host ///’

computer wishes to restart a satellite gofiputer system}/{é/;ust
send

the

appropriate

MOP messages

as/déscribed

belo

order

initialize
bit

leave

Maintenance mgée,

the DMC11

and

supel& a

clear.

3.4.11

Remote

Whenever

the

Load

v} ’

DEtect
f/}v

micropyocessor
4

base

program

must

address with the

and
L]

Dgwn

Line

fLunning,

MOP MODE data @&;ld.
i

RESUME

.-V' ’

the serial 1line gfi} a DDCMP

P
e
N

PDP-

the

[

Load
]

constantly

scanning

intenance message containing an ENTER

What/Aappens when this particular message

is received ?épends on th vsetting of two switch packs on the

DMC11 line fnit.

Depending on the setting of these switches,

the DMC11/will either ¢ommence down line loading in MOP mode,
trigger/the

PDP-11

tf6

begin

executing

program

read

only

memory (ROM) bOOti%&ap (BM873, M9301, etc.) or simply pass the
data to the PDP-1/ as an ordinary maintenance message.

In case

ROM

specify

bootstrap

bit

word

triggered,

offset

the

switches

bootstrap

the

address

line

unit

space.

The

data

portion

The

first

byte

bytes

contain

switch

protect

ENTER

contains
the

pack

the

against

same

the

the
8

message

bytes

long.

number

The

remaining

value.

This

value

specified

and

serves

line

inadvertant

MODE

decimal

bit

DMC11

MOP

unit

recognition

the

ENTER

recognized

and

the

password
MOP

MODE

message.

ENTER

MOP

MODE

to commence down line
over

are

PDP-11

tight

program

MODE

The

followed
address.

down

data

ENTER

This

was

end

the

and

remains

until

MOP

MODE

the

processor

control

message,

message

three

bytes

informs

system

placed

transferred

the

DDCMP

long

sends

maintenance

that

remote

DMC11

contains

format

the

end

that

the

LOAD

WITH

TRANSFER

decimal

ENTER

MOP

received.

should

now

send

DDCMP

maintenance

bytes

are

specify

micropr&cessor takes

periperals

sequence

All

switches

line.

MODE

field

the DMC11

system.

INIT

where

the

8.12,1.

remote

SECONDARY

message

the

MOP

containing
numbers

loop

loaded

response

REQUEST

loading,

computer

initialized

into
a

the

message

memory

image

MEMORY

format.

bit

memory

The

first

address

loaded

and

two

right

four

bytes

ADDRESS
are

zero,

justified,

bytes

transfer

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digital equipment corporation

Printed

U.S.A.