DMC11 IPL Microprocessor Maintenance Manual

This document is a maintenance manual for the DMC11 IPL Microprocessor (M8200-YA/M8200-AD), designed for PDP-11 computer systems. Published by Digital Equipment Corporation in May 1976, with an October 1976 addendum, it provides comprehensive information for the installation, operation, and maintenance of the DMC11.

Core Functionality: The DMC11's primary purpose is to ensure reliable data transmission by implementing the DDCMP (Digital Data Communications Message Protocol) line protocol in firmware using a high-speed microprocessor. This firmware-based approach offers significant advantages over software-implemented protocols, including simplified programming, reduced PDP-11 processor overhead and memory usage, and enhanced data throughput.

Key Components and Features:

• DMC11 Network Link: Comprises two modules: the microprocessor module (M8200-AD) and a line unit module.

  • Line Unit Modules:
    • M8201 (low-speed): For remote network applications, interfacing with external synchronous modems (e.g., Bell 208/209 via EIA/CCITT V24 or CCITT V35).
    • M8202 (high-speed): For local network applications using coaxial cables, featuring an integral modem operating at 1 Mbps or 56 Kbps.

• Microprocessor (M8200-AD): A general-purpose control unit containing a bipolar microprocessor, Read-Only Memory (ROMs) configured with the DDCMP protocol, scratchpad memory, and a UNIBUS interface.

• Key Features: Support for down-line loading of satellite computer systems, remote initialization of systems over the link (Remote Load Detect), consistent PDP-11 software support for various configurations (local/remote, full/half duplex), power failure recovery without data loss, and 16-bit NPR (DMA) transfers.

Installation Procedures: The manual outlines a three-phase installation and checkout process. It specifies:

• Components: M8200-YA Microprocessor Module, M8201 or M8202 Line Unit Module, interconnecting cables, and various test connectors.
• Physical Setup: Both microprocessor (hex) and line unit (notched hex) modules plug into specific slots in DD11 backplanes and are interconnected by a one-foot cable.
• Pre-installation Checks: Emphasizes verifying jumper W1, selecting microprocessor device and vector addresses using DIP switches (E113 and E76), and confirming the presence of a BR5 priority card.
• Critical Step: The NPR Grant wire on the backplane for the M8200 slot must be removed before installation.
• Diagnostics: Installation is verified using specific MAINDEC-11 diagnostic programs (DZDMC for the microprocessor, DZDME/DZDMF for the line unit, and DZDMG for overall system verification).
• Power: Details power requirements for both modules (+5V and +/-15V).

Programming Information: This section provides details for PDP-11 programming of the DMC11. While the DDCMP protocol is handled by firmware, the manual explains the interface:

• UNIBUS Control and Status Registers (CSRs): Eight bytes of device addresses (76XXX0-76XXX7) are used for communication.
• Data Transfers: Data is exchanged between the PDP-11 and the microprocessor via a 32-bit data port (BSEL4-7) using handshaking signals (REQUEST IN/READY IN for input, READY OUT for output).
• Interrupts: The DMC11 generates interrupts to the PDP-11 at specified vector addresses (XX0 for input, XX4 for output).
• Initialization: The PDP-11 initializes the DMC11 by providing a "Base Table" address in its memory, which the DMC11 uses for protocol and error tracking.
• Control Functions: The PDP-11 can set operating modes (e.g., half duplex, primary/secondary station) and receive error/status information from the DMC11 (e.g., data check, timeout, overrun, disconnect, procedure errors). Some reported errors are fatal and require re-initialization.
• Maintenance Messages: Special DDCMP messages are used for down-line loading and restarting satellite systems.
• Power Fail Recovery: The DMC11 stores necessary data in its base table to attempt recovery from power failures.
• Error Counters: Eight-bit counters track recoverable communication errors.
• Performance Optimization: Suggestions for maximizing throughput, primarily by optimizing message sizes and buffer management.

Detailed Description: This chapter delves into the internal logic and architecture of the DMC11 microprocessor, including:

• Microinstruction Formats: Explains the MOVE and BRANCH microinstructions (16-bit words) stored in the Control ROM (CROM).
• Component Details: Describes the functions of the CROM, Memory Address Register (MAR), Program Counter (PC), Arithmetic Logic Unit (ALU), Scratch Pad Memory, and Multiport RAM.
• Timing: Provides timing diagrams for various operations (e.g., output/input bus timing, NPR cycles, interrupt cycles).
• Control Logic: Details the address selection logic, NPR (DMA) control logic, and interrupt control logic.

Maintenance Procedures: The manual outlines both preventive and corrective maintenance:

• Preventive Maintenance: Recommends regular visual inspections, operational checks, and running diagnostics (typically every 3 months).
• Corrective Maintenance: Focuses on isolating failures to the microprocessor module for replacement. Component-level repair is generally discouraged unless unusual circumstances dictate.
• Diagnostic Modes: Describes "Maintenance Mode" (for halting, stepping through, and examining the microprocessor's internal state) and "System Test" (for full-speed operational testing). Both modes require specific switch settings to enable.
• Test Equipment: Lists standard equipment required, such as multimeters, oscilloscopes, probes, module extenders, and specific diagnostic tapes.

Appendix A (PDP-11 Memory Organization): Explains how PDP-11 memory is organized (16-bit words, 8-bit bytes) and the UNIBUS addressing scheme (18 address bits for 256KB, with the highest 8KB reserved for device registers).

Addendum (October 1976): The addendum notes that the DMC11-AD option has been replaced by two new microprocessor options: DMC11-AR (for remote applications) and DMC11-AL (for local applications), though line unit designations remain unchanged. It also indicates substantial revisions to sections 3.4.2.1 through 3.4.2.15 of the Programming Information chapter, which supersede the original content.