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Document:	DMB32 User Guide
Order Number:	EK-DMB32-UG
Revision:	001
Pages:	158
Original Filename:

OCR Text

EK-DMB32-UG-001

DMB32

User Guide

EK-DMB32-UG-001

'DMB32
User Guide

Prepared by Educational Services
of

Digital Equipment Corporation

First Edition, May 1986

The information in this document is subject to change without
notice and should not be construed as a commitment by Digital

Equipment Corporation, Digital Equipment Corporation assumes

no responsibility for any errors that may appear in this document.

Using Digital’s networked computer systems, this book was
produced electronically by the Media, Publishing and Design
Services department in Reading, England.

Printed in U.S.A.

The following are trademarks of Digital Equipment Corporat

ion.

lijoliltal]
DEC

PDP

DECmate

P/0OS

UNIBUS

DECUS

Professional

DECwriter

VAX

Rainbow

VMS

DIBOL

RSTS

MASSBUS

RSX

Work Processor

CONTENTS

I
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*

CHAPTER 2
2.1
2.2
2.3

SENESESESESESRS g

2.4

INTRODUCTION

SCOPE. ... eenans eeeeireeeeennnnaaas Ceeiesesasesnsensnassasosssnarunes
OVERVIEW ..iiiiiiiiiiiiiiiiiiieiiieieinnienns ereeenn ereieeeeeeeeaes e eeeeeearnaaas
FUNCTIONAL DESCRIPTION....cciiiiiiiiiiiiiiiiiiaeanes PP
Data Transfer................ ceeeens Cereeeeraneeaaees e eeeereeeeaeteereanraeaeranaaaaaes
8 201 0) 1 TN t et eesesantteeasaaeereearaeaeseerrataerarraiaeas
|§910=3
Device RegiSters....ccovveriiiiiieiinniainnennns. PP

Lh Lbh Lh Lh

B
s PRARWLWWLLWWWWN
Lo L) L B

CHAPTER 1

1-1
1-1
1-2
1-4
1-6
£

VAXBI Registers.......... eerreeeerennens e eaeseeeeeannnaaaaaeeeaeeaannas e 1-6
DMB32 RegiSters...ccureeeeeererrereenaennns eaenn reeaeeeeeans errrereeeaeeenns. 1-6
PHYSICAL DESCRIPTION..... evens e eeeerereeeearereeeeaaaneae e ereereeeeennnnes 1-7
The DMB32 Option............. e eeeereressennnneeseataans ereeeeees eteeeereeeeeeannes 1-7
The T1012 Module.................. PPN 1-8
The H3033 Distribution Panel............. eeeeereeeannanes e Cerereereeeeenans 1-9
Communications Interfaces.........cccceeeiiiiianen e eereeeeenannaraaaaeresaaaes 1-9
Asynchronous Interface........ ereeaeeeeeeaaanas Ceeessasecessennanaceeatoesanans 1-10
The Synchronous Interface.................. ceeeeeans erererreaneean ereeaeneaes 1-12
The Printer Interface....... ceeens orreeeeaee ceeenn erreieeeees eeeereeereannnaas 1-13
SPECIFICATIONS ...ciiiiiiiiiiiiiinnnns ereneeeen e eteeerereteetearearaeaeennanaes 1-13
Electrical Requirements........oovevveereeeeieainnnns e eeteeeeesannnraaaaaaaes eveeen 1-13
Functional Parameters...............cvvaeee. erneeeeeeaes ceennas eerrireeeeennnaas eeen 1-13
Synchronous Functional Parameters“m... ..... et teeeteeerenneeesaeaeaaeas 1-13
Asynchronous Functional Parameters............... e eeeeeannreeeeeanaaaas 1-14
Printer Port Functional Parameters.............. e eeennreeaaaaaaaneierienns 1-14
Throughput ...ooieiiiiiiiiiiiiiiiiiieea PP 1-14
Environmental Specifications............... e enneeeiaeaeeaann e eeeererteaaaeaes 1-15
eeeneaaerreeeaae e 1-15
Operating Environment............. eeeeaenees et t
eaeananraans 1-15
e
eaeeaeeeee
eeeeeereeeee
e
.
Environment.......
Storage
INSTALLATION

SCOPE....ccceeeeeeettn eeeneeeeeaes e eeereeaetereeeearaes N
INSTALLATION TASK LIST ..............................................................
e
SITE PLANNING......ccccviiiiiiiiannnnn. eereeen ereeaen eeinann e eeeeeeeee
a
eerrereeeeeraaaa
t
e
iancs
teeerreseanrasnrenna
KITS............
ON
DMB32 INSTALLATI
es
aseasnnsrsasnnnasso
eeeieiiteetieeteter
iiiiiiiiiiiiiiieiie
..o
INSTALLATION CHECKS.
CONFIGURATION RULES. .. itiiiiiiiiiiiiiieiiiiiiiietrnnssiasienseaeens erreaeeeee
MECHANICAL INSTALLATION....cciiiiiiiiiiiiiiiiinnnn, PP
Electro-Static Discharge Precautions.......c.ccveeveiiiiiiiiiiiiiiiiiiiiiiiiinennanes
Anti-Static Wrist Strap........... PP ..
Conductive Module ContainerS.......ueeiererneeeeeereieieeraiessesnaaeaseaes
T1012 Module INStallation. . .coveeeeiieieereeenreiaaiereeeeeeannirieeeennssnonaseneens
Transition Header Assembly Installation......... PPN
Ribbon Cable Installation.......... e eeeeennieeesanaaareearaaans e teeeenrieeeaeaas

2-1
2-1
2-2
2-2
2-3
2-3
2-3
2-3
2-3
2-4
2-4
2-6
2-6

=
Un
b

L X0
W

B W RN —

—
B W

0 X0 10 0 00 0 0 0

H3033 Distribution Panel................. ettt e, 2-10
AdapPLer Cables. . ..ouiiiiit i 2-12
V.35 Adapter Cable......o.oviniiniiiie e 2-13
V.24 Adapter Cable.......c.o
e
oouiiiiiiii 2-14

RS-422 Adapter Cable.......oouvuiiniiieieee
e 2-15
RS-423-A Adapter Cable........oooiniieiiie e 2-16
Loopback ConNectOrS
.. ..uuieinii
. it 2-16
H3196 50-Way Balanced Loopback Connector.......ovouvemveeoeeennnn.. 2-17

H3195 50-Way Unbalanced Loopback Connector........oeeevmvenvnnnn.... 2-17
H3197 25-Way Loopback Connector (Async Channels)................... 2-18

H3250 34-Way Loopback Connector (V.35).....eueeiie 2-19

H3248 37-Way Loopback Connector (V.24).......oovuieeeeeeie 2-20
H3198 37-Way Loopback Connector (RS- 422/423) ........................ 2-21
OPERATION AND PROGRAMMING

SCOPE ...
OPERATION ...
DMB32 Register Map ...................................

B BB B B B B et et et it et et et et bt et D OO0 ~d O\ U

LD B e

CHAPTER 3

pguyuppb@hwh&;bwbawiu@@@*mmmiybhb’wbbb;—a

ACCEPTANCE TESTING......ccovveeoeeooooooo 2-8
POWer-Up And Self-Test.....couuirieiniiiee
e 2-9
DIagNOSLICS. ..ottt e, 2-10
CABLI.NG
.. e 2-10

REZISEET ACCESS. o uenintitit ittt e e
REGISTER BIT DEFINITIONS .............................................................

Device Type Register (DTYPE)....ouuuiiuiniiae
e
VAXBI Control and Status Register (VAXBICSR)......; ........................

3-1
3-1
3-1
3-4
3-5

3-6
3-6

Bus Error Register (BER)....oovivviuiieiniiniieieiieianinnn et ieeaean, 3-8
- Error Interrupt Control Register (EINTRCSR)....... i eieeeeeeeann.. 3210
Interrupt Destination Register (INTRDES).......c.ouiuviiivininiiniiiaiiin 3-11

Starting Address Register (SADR)....cuouirinieeieee e 3-11
Ending Address Register (EADR).....couviriiee
e 3-12

User Interface Interrupt Control Register (UINTRCSR)........ccvvennnennenn, 3-12
General Purpose Register 0 (GPRO).....o.oouinieee
e 3-13
Maintenance Register (MAINT)........ ett
er ettt
t et a e rae e 3-14
Async Control And Status Register (ACSR)...ouueninineeiee 3-16
Sync Control And Status Register (SCSR). . vviveeeeeieie e 3-17
Printer Control And Status Register (PCSR).......vuverieiniee 3-17
- Device Configuration Register (CONFIG)......c.voeerinii 3-18
Second Async Control And Status Register (ACSR2).....ovvvuivivnininiinin, 3-19
Second Sync Control And Status Register (SCSR2)...uovnvninininininiiinin. 3-20
Second Printer Control And Status Register (PCSR2)..... e
ere et reaaas 3-20
System Page Table Register (SPT
. .uciuirie
E) e 3-21
System Page Table Size Register (SPTS)........ett
et
et
eeannan 3-21
Global Page Table Register (GPTE)......ccoiiurieiie e 3-22
Global Page Table Size Register (GPTS).c.uoueineeiee
e . 3-22
Printer Prefix/Suffix Control Register (PFIX)..... et
tetee ett
eeeeeenans 3-23
Printer Buffer Address Register (PBUFFAD).......couviuiiie 3-24
Printer Buffer Count Register (PBUFFCT)...o.vvniieiiiei
e 3-24
Printer Control Register (PCTRL).......ooiuiriniiae
e 3-25
Printer Carriage Counter Register (PCAR)......oouirinm 3-28

3.3.27
3.3.28
- 3.3.29
3.3.30
3.3.31
3.3.32
3.3.33
3.3.34
3.3.35
3.3.36
3.3.37
3.3.38
3.3.39
3.3.40

3.3.41
3.3.42
3.3.43
3.3.44
3.3.45
3.3.46
3.3.47
3.3.48
3.3.49
3.3.50
3.3.51
3.3.52
3.3.53
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.6.1
3.4.6.2
3.4.6.3
3.4.7
3.4.8
3.4.8.1
3.4.8.2
3.4.8.3
3.4.8.4
3.4.8.5
3.4.8.6
3.4.8.7
3.4.8.8
3.4.8.9
3.4.9
3.4.9.1
3.4.9.2
3.4.9.3

~ Printer Page Size Descriptor Register (PSIZE)........ccooooiiiiiiiiiiniiin. 3-29
Sync Transmit Buffer 1 Address Register (TBUFFAD1)........................ 3-29
Sync Transmit Buffer 1 Count/Offset Register (TBUFFCT]I).................. 3-30
Sync Receive Buffer 1 Address Register (RBUFFADI)...........teereeraennnas 3-30
Sync Receive Buffer 1 Count/Offset Register (RBUFFCT1).................... 3-31
Sync Transmit Buffer 1 Control Register (TLNCTRLI1)....................c.... 3-31
Sync Receive Buffer 1 Control Register (RLNCTRLI1)..............c.coiiin. 3-33
Sync Line Parameters Register 1 (LPR1).......ccooiiiiiiin 3-35
Sync Line Parameters Register 2 (LPR2)......coooiiiiiiiiiin, 3-37
Sync Transmit Buffer 2 Address Register (TBUFFAD2)......................... 3-39
Sync Transmit Buffer 2 Count/Offset Register (TBUFFCT2).................. 3-40
Sync Receive Buffer 2 Address Register (RBUFFAD2)...............c..oo.i. 3-40
Sync Receive Buffer 2 Count/Offset Register (RBUFFCT2).................... 3-41
Sync Transmit Buffer 2 Control Register (TLNCTRL2)...............c......... 3-41

Sync Receive Buffer 2 Control Register (RLNCTRL2)............ooooiiiiiiis 3-43
Sync Line Parameters Register 3 (LPR3).........oooiiiiin, 3-44
Sync Buffer Control Register (BUFCTRL).......ccooiiiiiiiiiiiiiiii, 3-45
Async Transmission Preempt Buffer (PREEMPT)............cooins 3-47
Async Transmit Buffer Address Register (TBUFFAD).......................... 3-47
Async Transmit Buffer Count/Offset Register (TBUFFCT).................... 3-48
Async Line Parameters Register (LPR)................. eteenteereraeaenraearanas 3-48
- Async Line Control Register (LNCTRL).....ccooviiiiiiiiiiie 3-54
Async Line Status Register (LSTAT).............. Mt eeteanaeteeaararaeaerenaaaaaaas 3-56
Async Flow Control Characters (FLOWC)............eneeasearerenstcasrerosnsers 3-57
Async Transmit Completion FIFO (TBUF).......coooiiiiiiii, 3-58
Sync Line Completion FIFO (SBUF).................... e eeeeraraeeeeeaaaaeeeaaas 3-59
Async Receive Buffer (RBUF)..........cooooiiiiiniiin, et 3-61
PROGRAMMING FEATURES. ..o iiiiiiiiiiiiiiiiiaiiteieceittenanenns 3-63
) s W 3-63
| G1 LB P 107221010
15 o) s PP e eeeeeeeeenaanenn .... 3-64
@6 s 31400
Using the FIFOS.....oviuiiiiiiiiiiiiiiiiiiii i cereeaes 3-64
erea 3-64
e raaas
Receiving via the RX FIFO........cccooiviiiiiinnieetererreennrt
Preempt Transfers....oocovneeiieiiiiiiiii i 3-64
DMA OperationsS....occeeeeueeiiieiiiiieieiineriiisrreineesieannno erneeeteeaieaaaas 3-64
Address Translation.......eeeeeverrirereerietereeeaereeeaarsssiaianssssssesnnnnns 3-65
Transmitting Data........ccvviiiiiiiiiiiiiiiiiiiiiiiiienn. etreeeeeeeeaaaaas 3-66
Receiving Data......ccccoevvviiiiiiiinnnnnn. et teetetereetteeeereeiaaaanrraeaaaans 3-66
eaneiaeeaaas 3-66
e
Interrupt Control......SO,e taeeeeeerereteeeraea
3-67
araaaas
teeeeennareeaaer
t
e
| 253 £0)G 070 16 (= T
3-68
s
eranttotoananctessse
secarnntrstatenneese
evsanaesissessasases
W
No Error..........c.0s
3-68
P
DY V2N 25 5 o )S
3-69
P
)P
Y FSSRT: T 2 6 (6
3-69
iiier
e
iiiiiiiiiiiiii
.iiiiieriiiiii
Incomplete....
Last Character
3-69
T
S
o)
5
5
=) g =1
133008
Y (e Te 1= s (I =R 5 n'e )P 3-69
Aborted BY HoOSt...uuiiii i e 3-69
eeee e e 3-70
Printer Offline......covvvieiriiiiiiiiiiiiiiiieenenn. ett
3-70
O
)O
0
4
8
25
BB
:1
80
oRT=
|D
3-70
saaananens
iieriiiiieitiiieeeea
oiiieiiiiiiiiiiieiii
...
Flow-Control.
Automatic
eeeeie i 3-71
IAUTO.FLOW..oviiiiiiiiiiiiiiaennnseereereeenn et
AN D10 2 D 3-72
N0Y-N 01 O 2 510 )AP 3-72

Flow-Control Characters........ouvuiiiiiiiiise
a2
eeseaaa 3274
Async Modem Control....... el unesetee s et ttanieeenonaiieriotresasaennteterceennnnne 3-74

N — O

Pk
o
ok

O © ©
e VN

W W W W W w

fooanck

B
- n B

g9y

W W W W R

CHAPTER 4

Sync Modem Control.......o.viiiiniiiiiiii
e
e 3-74
Selecting Protocols......coccvevenann.... et
eeeeeeeee e et et et —n...n 3-75
TROUBLESHOOTING

SCOPE.....cccovvvvivviiinnnn. e £36ababnanateceionereseanssssssnsansnocsassnnn
DIAGNOSTICS............... ceiveess et
ee e e e e et e e eee et eeaaeaaaaaan
ON-BOARD SELF-TEST DIAGNOSTIC........... et
e et eee et
Starting the Self-Test........... ceveesesans b eeerrrreaaeeas e
aeeiaaeaan

Self-Test Indications and Error Codes.................... O
Self-Test Error Codesin the RX FIFO......covvvuiiieiiiaiiii

Test Summary Register Bit Definitions........... e
EVDAK STANDALONE DIAGNOSTIC.,.................,....;..‘ ......................

Starting EVDAK........... veieiiavans Geeerianeinsrreeeaaas e tteeseenansetestonnninnos

)

*®

DISCARD‘FLO‘“flflfi‘*%m@l’biflfiifi‘ llllllllllllllllllll LRR R N NN O R
Y R R ) 3”;2
Flow-Control State Diagrams..........cccovveennnn.... . S )9,

(RN

ALk L b

PhRERELBA ;&&&;&:&:&b&&k
iy NN
*

W B G R
DN e
B U

4-3
4-4
4-5
4-6

4-8

SectionsS.................vreeaenns ceeeranes errereeeeea. ettt
eaaan, 4-11
Error Messages................. Ceeierneniiesennes ereeeeenea ettt
et iaeeaaan 4-11
EVDAJ ONLINE DIAGNOSTIC (Async).‘.......,...;..‘.,..; ......................... 3-11

Starting EVDAIJ...... e neeeteaesa
it aeeeeeteneinteceseso
seeate
rorarannns e eeeeeerreeea 4-13

Optlons.......,......,.,.....;.;...;....,,........,....; ...... eavee T 4-14
EVENT Flags.....cc...cc......... et teesieeie
e reere
teeraa
et rareeseraranennsannss 4-14

]

NN
G
I

—

— e \D QO ~]

APPENDIX A

4-2
4-3

OptionS....ccvvviiinniiiiinnnennn. O
S
TP 4-9
EVENT Flags....ccccoviiiiiiiiiiiinnnnnnn. ceivesannen e e aeaaaas 4-10

4.4.3

4-1
4-1

R1Tw
8 (0] o L Ceadasavenciateseinenenos ettt 4-14
Error Messages.................... ereereereae. Ceeeiiearnnnans et
e eeeeeeraraeeeenaa. 4-15
EVDAL ONLINE DIAGNOSTIC (Sync) ........................ P 4-15
Starting EVDAL..........ettt Cehetetteiseneeaeeaerneraesnannareenns 4-16
EVENT Flags....... eneeee eeareeeeen Ceeteereeerenrraaaan e teieneeetetrraaaeaaa 4-16
SectionsS......c.evvvennnnn. eeeeas P cerens 4-17

Error Messages...... e ereeenrrreeraaaaeen R
. 4-17
EVAAA ONLINE DIAGNOSTIC (Prmter)...; ..... O SO 4-17
Starting EVAAA........cooovveeiinn... e eeetssearsheanecaeeeenresansaniiesnannsnrnees 4-18
128 ¢ (o)g\ (e T
4-19
USER ENVIRONMENT TEST PROGRAM (UETP) .................................. 4-19

DATA COMMUNICATIONS LINK TEST (DCLT)........ teeiittreceetennereccerens 4-19
FIELD REPLACEABLE UNITS (FRUs)................ e e raeraeiriiaaaaen ... 4-19

TROUBLESHOOTING FLOW CHART..ttt
eeeane
e . 4-21

GLOSSARY

Title
DMB32 Typical Configuratmnm.m.....” ...... Hiteeieaeteeseetareraneetanonrocestnnnenennns - 1-3
DMB32 Functional Block Diagram........ccoveveviiieneiiinnennnnnnns Cheevevensnnnseneans
1-5

T1012 Module........ e eteetenreeeeennireeaeen Ceenn P e eeteetetareenaraeeaaas
H3033 Distribution Panel.” ...................... Feeettestecaeinrereeeteattatrenannnnnnencnnes

1-8
1-9

JOto J7 Async Connector Detail......oouveieeeeeineie e e 1-10
Sync Connector Detalil.......... e veetetsesasaniansssesescainnnne et
etee e, 1-12

1-7
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11

Printer Connector Detail........ e eeeeeeeeeeannereeeteaenaraaaaaeeeeeeeanariretaeeannaran 1-13
DM B3 2 INStAllAtiON . et ereeeeeeeeeesaeesneesuaaasssesansrassossseesnsessssssnssessassssssss 2-5
The VAXBI Backplane (Rear VIEW).....couiiiiiiiiiiiiiiiiiiiiiiiiiiiiieeee, 2-7
The H3033 Distribution Panel (Rear VIEW).....coviviiiiiiiiiiiiiiiiiiiieieens 2-8
H3033 Distribution Panel (Front VIeW)......cooiiiiiiiiiiiiiiiiiiiiiiiiiiiiiieens 2-11
Sync Channel CONNECtOT.......ouiieiniiiiiiiiiiiiiiiiiiiiieiraeeaaaeas 2-12
50-Way
BC19F-02 (17-01112-01) Adapter Cable Detail..........c.oooiiiiiiiii. 2-13
BC19D-02 (17-01110-01) Adapter Cable Detail...........ccooiiiiieiiiiiiii. 2-14
BC19B-02 (17-01108-01) Adapter Cable Detail.........c.ccoooiiiiiiiiiiiiiii. 2-15
BCI19E-02 (17-01111-01) Adapter Cable Detail......... PP PPPPT 2-16
H3197 Loopback Connector........ e eeererereeteeeeeeaeeiaaens enenes e erereeeeeeeeaeaon 2-18
H3250 Loopback CONMMECLOT ... cuuivreeenerieeinrianeirneraneernersnessiensnreereeneenees 2719

2-13
3-1
3-2

H3198 LoOpback CONMMECIOT. . euuiutintiiniiitiatiaaneitteieaieieatiiteittieeiianaanaas 2-21
DMB32 Register Map.......covvvennnnnn. erereiieeaaans e etnaeaeeanannarearaanaaaaaaaaneas 3-2
Handling an Unaligned DMA Buffer...........ooooiiiii 3-65

2-12

3-3
3-4
3-5

3-6

H3248 Loopback Connector......ocevviiiiiiniiiiiieiiiinnns e eeeeerae i 2-20

DMB32 Interrupt VectorsS.......coovvvvvvniiiniiinnnnan.. e aeeeeteeeeeneeeraneiieeeatanaas 3-67
Automatic Flow-Control of Transmitted Characters..............ooooiiiinnne. ereeenn 3-72
Automatic Flow-Control of Received Characters......ccoovevvviiiiiiniiiiiiinieian.. 3-73

Program Initiated Flow-Control................... e eeaaeebeaeeeraeteeareraaaaareraaaaees 3-73

TABLES

Table No.

1-1
1-2
1-3
1-4
1-5
2-1
2-2
2-3
2-4
3-1
4-1
4-2
4-3
4-4

Title

EIA/CCITT Signal Relationships.................... eeeeen eereeeees R ... 1-11
Synchronous Functional Parameters............cooiiiiiiiiiiiiiiiii. 1-13
Asynchronous Functional Parameters.........c.ooiviiiiiiiiiiiii 1-14
Printer Port Functional Parameters..........coovvvieiiiinnn. eeenenennes errerreiaanas .. 1-14
Maximum Sensible Speeds (Sync Port).....coooviiiiiiiiiiiii 1-15
DMB32 Installation Kit Details.......ccccoviviiiiiiiiiiiiiiiia... PP 2-2
Ribbon Cable Connections........cceevveeveveen.. e anenenneaneaes e ereireeeeeeenanaaaas 2-6
H3196 Balanced Loopback Interconnections........ccevvviuieiiiiiiiaiinieiiiiineninne. 2-17
H3195 Unbalanced Loopback Interconnections.........ccocevvveiinannn.e. Cererreeaann 2-17
DMB32 RegiSters....ccceeuvevineeneneennnn. et eeeererereranaeeaaaaes e ratreeeeeeennnanas 3-3
Scope and Duration of Self-Test...........cooiiiiiiiiiine. P .. 4-2
Self-Test Error Codes in the RX FIFO................... PP 4-4
D VN (G KoL T PPNST eeerternreeeaaaeaaaes 4-7
|DAY
Ribbon Cable Signal Distribution..................... eteeeserenanraaeeaeeeeeaeanaas 4-20

vii

PREFACE

This document describes the installation, use, programming, and service requirements of the DMB32
asynchronous/synchronous multiplexer. It contains information for first-line service, field service support,
and for customer engineers and programmers.

The manual is organized into four chapters plus an appendix.
Chapter 1
Chapter 2

Appendix A

Chapter 3
Chapter 4

Introduction
Installation

Operation and Programming
Troubleshooting
Glossary

The following is a list of related titles.

Document

Number

DMB32 Technical Description

EK-DMB32-TD

DMB32 Field Maintenance Print Set

MP-01797-01

CHAPTER 1

" INTRODUCTION

1.1

SCOPE

This chapter describes the functmns vcrsmns phys;cal featums and spemfwatmns of thc DMBBZ communications adapter.
1.2

OVERVIEW

The DMB32 is an intelligent synchmnous/ asynchromus muluplexer whmh pmvxdes enght full-duplex
asynchronous serial data channels, one synchmnous data channel, and one line printer interface on VAXBI
systems.

The main features of the I)MBBZ are:

Smgle VAXBI module (T1012) and dlStI‘lbutIOIl panel (H3033)

Eight full-duplex asynchronous (async) data channels

One synChronous (sync) data channel

One line-printer port. The DMB32 printer port supports the LP32 generic printer specification.
This includes the LNO1, LNO1-B, LNO1-S, LP25, LP26, LP27, LXY 12, and LXY22 printers.

Direct Memory Access (DMA) or ;s“inglewhamcter ,programmed transfers to and from host
memory

Onboard virtual-to-physical address translation allows the DMB32 to handle data buffers in

Large 512-entry First-In First-Out (FIFO) buffer on the async channels, for received characters,

Async ports are electrically and mechanically compliant with RS-232-C, and compatible with

The sync port is electrically and mechanically compliant with RS-232-C, RS-422-A /RS-449,

their virtual address format

dataset status changes, and diagnostic information

V.28/V.24 (T1012 is also compatible with RS-423-A, V.10, and X.26, but the H3033 is not,
due to pin limitations on the 25-pin D-type connectors).

V.11, X.27, and V.35, and compatible with RS-423-A/RS-449, V.28/V.24, V.10, and X.26.

IBM Bisync, SDLC/HDLC, and DDCMP protocols are supported on the sync port. NRZI

support is also provided.

General Byte (GEN BYTE) protocol provides basic framing and data transfer facilities to
implement other byte-oriented protocols on the sync channel

Full-duplex point-to-point or auto-answer dial-up operation
1-1

Programmable split-speed operation

Total module throughput 21000 characters per second

@ugqmatic flow-control of transmitted and received data on the async channels

e ;\;Self}testdiagnostics

Programmable loopback modes and test facilities

There are no switches on the module or the distribution panel. Each external cable for the sync
channelis electrically coded to select a specific CCITT/EIA standard. Other line charactenstncs
are set under program control.
)

Enough modem controlis provided on all synchronous and asynchronous channels to allow auto-answer
dial-up operation over the public switched telephonenetwork (PSTN). The DMB32 can also be used for
point-to-point operation over private lines. Modem controlis implemented by softwarein the host.
An integral microprocessor releases the host from many of the datawhandhng tasks
The DMB32 has an on-board self-test dlagmstlc thatis executed mdependently of the host Onlme and

standalone diagnostics are also available.

Two yellow LEDs on the T1012 module give the GO/NOGO status of the option. The self-test also
provides more detailed error and/or status information thmugh the RX FIFO and some 0f the devnce

registers.

1.3 ' FUNCTIONAL DESCRIPTION
The DMB32is a communications adapter of the VAXBI famlly It has elght asynchronous channels one
synchronous channel, and a printer channel. The function of the DMB32is to transfer data bctween a
VAXBI node and the asynchronous, synchronous, and printer ports.

Figure 1-1 shows a DMB32 in a typical configuration.

UP TO SIXTEEN VAXBI NODES
A

(’

VAXBI
PROCESSOR

VAXBI
NODE

SO U Ul

" omes2

—

T1012 MODULE

sync|

o
Lprinter ||
PRINTER
: SR 1| | CRANNELT

SN
i )S
,

.|
/

—

| EQUIPMENT

CHANNEL | MODEM

}

——

| REMOTE

EQUIPMENT

r—

Loea

EEERRE
|
|

NODE

i i

? % ? ? ra
Coro!

VAXBI

(

VAXBI BUS

HOST

*1
|

ASYNC

mODEM
-

[

: |

—

TELEPHONEOR |
:
|
ASYNC
DATA COMMS

MODEM
|

[

REMOTE

| TERMINAL

L.pmmmmmflmmmmmmw_l

Figure 1-1

DMB32 Typical Configuration

Figure 1-2 is a functional block diagram that shows the data routes through the option. Data is transferred
between a VAXBI node on the host and the communications lines via registers and DMA files in the
Common Address Store RAM (CASRAM). Also in the CASRAM are Control and Status Registers
(CSRs) which configure and program the option. The information which is written to and read from the
CSRs is used to support and control the communications functions.

Data can be transferred between the VAXBI and CASRAM by programmed Read or Write commands,
or by the DMB32’s DMA logic. Data is transferred between the communications interface and the
CASRAM under the control of a 68000 microprocessor.

The maximum data transfer rate on the VAXBI is 13.3 Mbytes per second. Such a high rate makes the
design of the VAXBI interface critical, so a standard VAXBI interface (VAXBI corner) has been designed
for all VAXBI options. The VAXBI corner is based on a specially designed VAXBI integrated circuit
(BIIC), which handles all the VAXBI commands and protocols.
The intelligence of the DMB32 is supplied by the 68000 microprocessor driven by ROM-based firmware.
The microprocessor controls and configures the communications interface, and manages both DMA and
communications functions. The firmware also includes self-test routines which run automatically at powerup or reset.

1.3.1
Data Transfer
The function of the DMB32 is to transfer data between the VAXBI host and the data lines connected to
the communications interface. There are several methods of transfer.
DMA

Sync RX and TX data is transferred between host memory buffers and CASRAM files by
DMA. The microprocessor keeps track of the buffers, and initiates further DMA transfers as
needed. Transfers between CASRAM and the sync port are initiated by an interrupt to the

MiCroprocessor.

Printer data is also transferred across the VAXBI by DMA. Transfers of data from CASRAM
to the printer port are done by the microprocessor. Printer status is polled by the microprocessor, which also makes the status information available in the CSRs. 1
:

Async TX data can be transferred by DMA or by programmed transfer. DMA transfers to

CASRAM are controlled in the same way as sync data transfers. The MiCroprocessor monitors
the async ports to check if they are ready to accept data.
[

RX FIFO
The microprocessor transfers async RX data to a 512-character RX FIFO in CASRAM. The
host reads the data, together with error status information, from a single location (RBUF). The
RX FIFO is also used to send diagnostic reports to the host.
:

Programmed (Preempt) Transfer
-

Async TX data may be transferred to CASRAM by DMA, or it can be written to a single-

character ‘preempt’ register (one exists in each async channel). From there the transfer is
completed by the microprocessor. A character written to the preempt register of a channel
which is transmitting a DMA buffer will be transferred to the async port before any remaining
DMA data.

1-4

MEMORY
NODE

EeS

g UP TO SIXTEEN

VAXBI BUS

)

VAXBI NODES

VAXBI INTERFACE

(PART OF VAXBI CORNER)

VAXBI REQUIRED REGISTERS
BIC

AND BIIC SPECIFIC
REGISTERS

ADDRESS
DATA

NODE

mcorflnofli“ mmmmm —— M ———— H— ———— - I—— A A T—— m A ——

A A %LEQEP“ A

CONTROL LOGIC

GATE ARRAYS|

USER

LATCHES AND|

INTERFAC; E

TE
READ/WRI
REOIOTERS

TRANSFERs ADDRESS
AND

INFORMATION

“

ouT

MOVE DATA
STATUS AND
CONFIGURATION

CRINTER

»! CASRAM | AND

DMA FILES

DMA LOGIC

DATA

CONTROL

READ/WRITE

| AND

REGISTERS

INITIATE
DMA

Rty

| ARBITRATION

Rx FIFO

gw:mss

”””””””PRINTER SYNCHRONOUS

SERVICE THE PORTS
SYNC

DATA

INTERRUPT

clo

| CHANNEL
DATA

8000

‘

PROCESSOR

—

FOUR DUARTS

\
e

NMICRO-

USART

INTERRUPT

AND

COMMUNICATIONS
INTERFACE

SYNCHRONOUS
CHANNEL

PRINTER
STATUS

— I T TT
1TM
ASYNCHRONOUS DATA

PRINTER

ADDRESS: |
A

DATA

EIGHT ASYNCHRONOUS CHANNELS

ROM AND
RAM

Y
RE182

Figure 1-2 DMB32 Functional Block Diagram

1.3.2 Interrupts
The DMB32 can be programmed to interrupt a VAXBI hcst under the fcllcwmg conditions.
e

When a channelis rcady for ancthcr preemptcharacter

. When transfer of a DMA buffcrfmm system memory to an I/O channel has:

- bcen ;aicoi‘fcd
-

been terminated due to an crrcf

—

completed successfully

When a received character has been placedin a previously empty RX FIFO (thc DMB32 can be
programmed to delay this interrupt so that several characters can be placedin the FIFO before
“the interrupt is raised)

When modem status mfcrmatlon has bccn placedin thc RX FIFO This action overrides any
programmed interrupt delay.
|
|

1.3.3 Device Registers
The DMB32 is a microprocessor-controlled device and consequently the host does not havc to perform
many data-handling tasks directly. The DMB32 appears to the host to be a set of device registers which
can be loaded with commands or data to produce a certain action. When this action has been completed
the DMB32 loads appropriate registers with status information. The complctmn of a taskis signaled to the
host either by an mtcrrupt or by status informationin a register thatis polled by thc host. Device registers
can be ccnsxdcrcdin two groups.
|
.

_VAXB;I regiswtcr;s,

*‘DMBBZ-registcfs

1.3.3.1 VAXBI Registers - Scme cf thcse rcglsters must cxzst on any devrce (ncdc) thatis connected on
the VAXBE: These “required” registers hold status and ccmml information which defines how the DMB32
will respond to commands on thc VAXBI.

Other VAXBI registers are not rcqulred by the VAXBI specification, but thcy support spccmc functions
implemented by the BIIC. Features selected by the BIIC registers mcludc the commands to be implemented by thxs nodc |

The VAXBI registers, ‘Wthh are all in the BIIC, areconsidered in detail in Chaptcr 3, Operation and
Programming.
1.3.3.2 DMB32 Registers — These are the registers through which the DMB32 specific features are
controlled. They can be further subdivided into four groups.
e

General registers — Used to control paramctcrs and functmns common to all parts of the
communications interface
|

Async registers — Used to control and monitor the async ports

1-6

Sync regxsters — Used to control and monitor the sync ports

Prmter regzsters Used to control and mamtor the prmter port

A register map, together with full details of all reglster functlons, is gwen in Chapter 3, Operatmn and
-

Programming.

1.4

PHYSICAL DESCRIPTION

The DMB32 Optmn

1.4. 1

The DMB32 option is made up of the following major items:

A single VAXBI module (TIOIZ)

A distribution panel (H3033)

Six ribbon cables (17-00740-xx, where xx defines the length)

A 50-pin unbalanced loopback connector (H3195)

A 50-pin balanced 1oop'back connector (H3196)

An async line loopback connector (H3197)

In addition to the above, the following adapter cables are available to match the synchronous channel
connector (50-pin subminiature D-type) to the standard used by the connected equipment. Appropriate
loopback connectors, not supplied with the option, are also indicated.
|
Cable

DIGITAL
Part Number

BC19F-02
BC19D-02
BC19B-02
BCI19E-02

17-01112-01
17-01110-01
17-01108-01
17-01111-01

Standard

Loopback
Connector

V.35
V.24
RS-422
RS-423-A

H3250
H3248
H3198
H3198

Details of the adapter cables and all loopback connectors are given in Chapter 2, Section 2.9.

1-7

1.4.2 The T1012 Module
The DMB32is based on a standard VAXBI--Slzc module (T1012) The layout of this moduleis shownin
Figure 1-3. The dimensions are 23.3 c¢cm (9.18 in) by 20.3 cm (8.00 in).

The moduleis connected to the VAXBI via connector segments A and B. Connector segments C, D, and E

are connected to the communications lines via the ribbon cables and the H3033 distribution panel.

The T1012 module connects dlrcctly to any slot (except number K1J1; see Chapter 2, Installation)in the

VAXBI backplane. The bus addressis determined by the ‘Node ID’ plug Wthhis fltted to the back of the
backplane (there are no switches on the module itself).

DIAGNOSTIC
LED

68000

MICROPROCESSOR

SCC

DUART

DUART
L

ClO

CASRAM

DUART

CGA

ATGA

o BI CORNER
|
i

.
l
|

BIIC

DIAGNOSTIC

‘:]

CONNECTOR E

CONNECTOR D

CONNECTOR C

CONNECTOR B

CONNECTOR A
-

RE225

Figure 1-3

T1012 Module

1-8

The H3033 Distribution Panel

1.4.3

Figure 1-4 shows the H3033 distribution panel. This 1dent1fles the sync, async and printer connectors, and
the connectors to which the ribbon cable headers are connected.

p——

J14

37-WAY

CONNECTOR —}__|

(PRINTER

CHANNEL)
S

—

o . o i Sy, o M OO B S Y0 S

LN
\

J10

I
X

CONNECTS TO

BACKPLANE C1

Ja1

e S

I
\
S

CONNECTSTO

BACKPLANE D1

CONNECTORS

>(ASYMC

EIGHT 25-WAY

J6
©

J15

Ja
<

—

[

n ]
-

]

J13

CONNECTS TO
BACKPLANE E2

CONNECTS TO
BACKPLANE D2

CONNECTSTO
BACKPLANEC2

CHANNELS

J9
iS

O SO U S S S

J12

oAy

50<1| CONNECTOR
_—

(SYNC

CHANNEL)

CONNECTS TO

BACKPLANE E1

Figure 1-4 H3033 Distribution Panel
Communications Interfaces

1.4.4

Electrically and mechanically, the T1012/H3033 async ports are:
e

Compliant with RS-232-C

Compatible with V. 28/V 24

The T1012 moduleis also comphant with RS-423A V. 10 and X.26, but the H3033is not, because of pin
limitations on the 25-pin D-type connector..

Electrit;ally and mechanically, the TIO;l 2/H3()w3,3‘ sync port is:
.

Compliant with RS-232-C, RS-422-A/RS-449, V.11, X.27, and V.35

Compatible with RS-423-A/RS-449, V.28/V.24, V.10, and x,:m

1.4.4.1
Asynchronous Interface — Connection to external equipment, for each
of the eight async interfaces, is made via a 25-pin subminiature D-type connector. Figure 1-5 shows
the pin configuration of the

connector.

;

CONNECTOR FOR
EARTH STRAP

FROM PIN 1

OF OTHER

ASYNC

CHANNELS

PIN 1
PROTECTIVE GROUND
Tx DATA

REQUEST TO SEND
CLEAR TO SEND

o
o

DATA SET READY

-0

DATA CARRIER DETECT

o
0

| : \
o>

—

SIGNAL GROUND

_(SEE TEXT)

LNKws

9
|

OHM

LINK Wn (n =0 to 7)

O
O

O
O
O

O
«

DATA TERMINAL READY

RING INDICATOR

0
ol

25-PIN

D-TYPE

CONNECTOR

Q
Q

\/
PIN 25
RE144

Figure 1-5

JO to J7 Async Connector Detail

- As supplied by DIGITAL, each async connector has Signal Ground (pin 7) connected
to Protective
Ground (pin 1) by a resistor. Provision is made on the circuit board for a wire link to connect pin
7 directly
to pin 1. There are places for eight such links designated WO to W7.

The Protective Grounds of all eight channels are joined‘ together, and are connected (via wire link W8) to a
plated hole suitable for connection to a grounding strap. This allows the Protective
Grounds to be

connected to the chassis of the equipment in which the DMB32 is installed.

Table 1-1 shows the EIA/CCITT signal relatiohships and the pin connections for equivalent signals.

1-10

EIA/CCITT Signal Relationships

Table 1-1

EIA RS-449

Signal Name
-

Shield

EIA RS-232-C

Signal Name

Signal Ground

Send Common

Terminal Ready (+)

Terminal Ready (-)

Data Mode (-)

Send Data (+)

Send Data (-)

RD
RD
TT

Received Data (+)
Received Data (-)
Terminal Timing (+)

6
6
17

BB
DA

Terminal Timing (-)

Send Timing (+)

Terminal Timing (-)

Receive Timing (+)

Receive Timing (-)

Request To Send (+)

Request To Send (-)

Clear To Send (+)

Clear To Send (-)

Receiver Ready (+)

Receiver Ready (-)

Signal Quality

LL
RL
TM

Signaling Rate Selector
Signaling
Indicator

New Signal

Rate

Local Loopback
Remote Loopback
Test Mode

Signal Ground

102

Terminal In Service

Data Mode (+)

Signal Ground

Signal Name

Receive Common

Incoming Call

Protective Ground

CCITT V.24

10
14
18

Ring Indicator

Data Terminal Ready
Data Set Ready
Transmitted Data
|

Received Data
Transmitter Signal
Element Timing
(DTR Source)

Transmitter Signal
Element Timing
(DCE Source)

Signal

Receiver

Element Timing

Request To Send

Clear To Send
Received Line Signal

Detector

125

108/2

Calling Indicator

Data Terminal Ready 20
-

107

Data Set Ready

Transmitted Data

103

3
24

104
113

114

Transmitter Signal 15

115

105

106

109

3
Transmitter Signal 24

Received Data

Timing
Element
(DTR Source)

Timing
Element
(DCE Source)

Signal 17

Receiver

Element Timing

Request To Send

4
-

Clear To Send

Data

Channel 8

Received Line Signal
Detector

Signal Quality Detector

Data Signal Rate

Selector (DTE Source)

Data Signal Rate
Selector (DCE Source)

1-11

110

Data Signal Quality 21

111

Detector

Data Signaling Rate 23

Selector

(DCE

Source)

141
140
142

Local Loopback
Remote Loopback
Test Indicator

18
21
25

Table 1-1
EIA RS-449

Signal Name

EIA/CCITT Signal Relationships (continued)

EIA RS-232-C

Signal Name

CCITT V.24

Signal Name

Select Standby

Standby Indicator

—~

Pin
~

1.4.4.2 The Synchronous Interface — Connection to external equipment is made via
a 50-pin subminiature D-type connector. Figure 1-6 shows the pin configuration of the connector. Different
adapter cables
are used to select only those signals needed to implement a specific interface standard. These
adapter
cables are fully described in Chapter 2, Section 2.8, Cabling.
V
50-WAY
PIN

SIGNAL

CODE GROUND

NAME

CODE
0
CODE 1

3
4

CODE 2

CODE 3
Tx DATA (A)
Tx DATA (B)

6
7
8

Tx DATA

RTS/C (B)

TEST |

REM.LOOP

Rx CLOCK (A)
Rx CLOCK (B)

19
20
21
22
23
24

25
26
27
28
29

35
36
7

Tx CLOCK (A)
Tx CLOCK (B)
CLOCK
V.35 Tx CLOCK (A)
V.35 Tx CLOCK (B)
V.35 CLOCK (A)
V.35 CLOCK (B)
V.35 Rx DATA (A)
V.35 Rx DATA (B)
V.35 Tx DATA (A)
V.35 Tx DATA (B)
V.35 Rx CLOCK (A}

(A}

47
48
49

gggfi: 53)’
CTS (B)

S
g
g

O
O

g
S

o g
995

o
o

2
g

o
0

05
0 g

O
o

O
8

5
o

O
8

DSR (B)
RTS

40
42

0
0

PINSO | PIN17

DTR

CTS (A)

43
44

PIN 1

V.35 Rx CLOCK (B)
DSR

PIN 34

Rx DATA (A)

LOCAL LOOP
SPEED INDICATE

FIN18

Rx DATA (B)

30
31

RTS/C (A)

50-WAY D-TYPE CONNECTOR
{MALE PLUG)

DCE GROUND
TEST 1
TEST 2
DTE GROUND

DTR (A)
DTR (B)
CLOCK (A)
CLOCK (B

TEST 3

SPEED

(A).(B) WIRES A(+ve) AND B(-ve) OF A TWISTED PAIR
RE146

Figure 1-6

Sync Connector Detail

1-12

1.4.4.3 The Printer Interface — The printer port is a parallel interface at TTL levels. Connection to the
printer is made via a 37-pin subminiature D-type connector. Figure 1-7 shows the pin configuration of the
connector.

The T1012/H3033 line printer port supports the LP32 generic printer specification. This includes the
|
LNO1, LNO1-B, LNO1-S, LP25, LP26, LP27, LXY12, and LXY22 printers.
(PIN 19)

(PIN 37)

o—
O o
g o

MODULE
GROUND

DEMAND
DAVFU

CONN

g»—-

ONLINE

0 O

DAT<0>

-0 g‘“

STROBE

AT<4>

DAT<7>

o o
~—g g

gm{g}
DAT<2>

DAT<1>

(PIN 20)

Figure 1-7
1.5

DAT<6>

DAT<3>

1)
(PIN

Printer Connector Detail

SPECIFICATIONS

1.5.1

Electrical Requirements

+5Vdc+or-5%at6.75A

+12 V dc + or = 3% at 300 mA
~-12 V.dc + or - 3% at 425 mA
1.5.2 VFunctitmal Parameters

1.5.2.1

Synchronous Functional Parameters — Table 1-2 lists the functional parameters for the synchro-

nous line of the DMB32.

Table 1-2

Synchronous Functional Parameters

Parameter

Description

DMA transfer

Double buffered

Protocols supported

DDCMP, SDLC, HDLC, IBM BISYNC, GEN BYTE

Data rates (bits/s)

600, 1200, 1800, 2000, 2400, 4800, 9600, 19200, 48000, 56000, 64000

1-13

1.5.2.2 Asynchronous Functional Parameters
- Table 1-3 lists the functional parameters for the asynchronous line of the DMB32.
|
S
|
Table 1-3

Parameter

Asynchronous Functional Parameters

Description

Operating mode

Full-duplex or half-duplex*

Data format

One start bit; 1, 1.5, or 2 stop bits

Character size

5, 6, 7, or 8 bits (Does not include the parity bit)

Parity

Odd, even or no parity

Data rates (bits/s)

50, 75, 110, 134.5, 150, 300, 600, 1800, 2000, 2400, 4800, 7200, 9600,
19200, 38400

Split-speed

When using split-speed operation the transmit and receive speeds of both

channels sharing a DUART must be in the same group (A or B). Channels
are paired (use the same DUART) as follows: channels 0 and 1, 2 and 3, 4
and 5, 6 and 7. Speeds are grouped as follows:

Speeds (bits/s)

Group

50, 7200, 38400

75, 150, 1800 2000, 19200

110, 134.5, 300, 600, 1200, 2400,
4800, 9600
|
|

A and B

* Half-duplex is only supported on systems using coded link-control as the DMB32 does not support
the
secondary transmit and receive signals.

1.5.2.3 Printer Port Functional Parameters — Table 1-4 lists the functional parameters
for the printer
port of the DMB32.

Table 1-4

Printer Port Functional Parameters

Parameter

Description

Formatting capabilities

Prefix characters, suffix characters, CR insertion, FF to LF conversion,
lower-case to upper-case conversion, line wrapping, carriage position
tracking, line truncate.

1.5.2.4 Throughput - Each asynchronous channel is capable of full-duplex operation at data rates
of up
to 38400 bits/s. However, the DMB32 cannot support eight channels operating at 38400 bits/s
at the
same time. The total maximum throughput of the DMB32 is around 21000 characters per second
(eight

data bits with start and one stop bit), including all characters transmitted and received on the synchronous

line and the printer port.

If congestion occurs, the DMB32 will give priority to the synchronous line, followed by the reception
of
async characters.
|

1-14

The individual maximum througputs for each port are:
e

Sync - 16000 char/s

Async - 10000 char/s

Printer — 4000 chars/s (equivalent to 1800 lines/min)

on the protocol and electrical
The maximum sensible speed that can be used on the sync port dependsfor
interface standard selected. Table 1-5 lists the maximum sensible speeds all the supported protocols.
Table 1-5 Maximum Sensible Speeds (Sync Port)
Electrical Interface Standard

Protocol

RS-232

RS-423

RS-422

V.35

DDCMP
HDLC

19200
19200

19200
64000

19200
48000

BISYNC
GEN BYTE

9600
9600

1.5.3

Environmental Specifications

1.5.3.1

Operating Environment

9600
9600

Data rate
(Bits/s)

Temperature:

5°C to 50°C (41°F to 122°F)

Relative humidity:

10% to 95% non-condensing, with a maximum wet bulb of 32°C (90°F)

Altitude:

1.5.3.2

and a minimum dew point of 2°C (36°F)
Up to 2.4 km (8000 feet)

Storage Environment

Temperature:

~40°C to 66°C (-40°F to 151°F)

Relative Humidity:

Up to 95% non-condensing

Altitude:

Up to 9.0 km (30000 feet)

1-15

CHAPTER 2
INSTALLATION

2.1

SCOPE

The procedures for installing and testing the DMB32 option are described in this chapter.
WARNING
|
The procedures described in this chapter involve the
removal of the system covers, and should be performed only by trained personnel.
CAUTION

You must wear an anti-static wrist strap connected
to an active ground whenever you work on a system
with the covers removed, or handle the T1012
module.

The T1012 module is supplied in protective antistatic packaging. Do not remove the module from its
packaging until you are about to install it.
NOTE

The complete equipment and documentation should
be present before installation begins. Any missing
items must be identified and the discrepancy
corrected.

2.2

INSTALLATION TASK LIST

The installation of the DMB32 consists of a number of steps:
Unpacking and inspection (see Section 2.4)
Installation checks (Section 2.5)
VAXBI Configuration checks (Section 2.6)

Installing the T1012 module (Section 2.7.2)

Installing the transition header assembly on the VAXBI backplane (Section 2.7.3)

Installing the ribbon cables into the transition header (Section 2.7.4)
Installing the H3033 distribution panel and ribbon cables (Section 2.7.5)
Installing the external adapter cables (Sections 2.7.5 and 2.9)
Installation testing (Section 2.8)

2.3 SITE PLANNING
|
No special site planning is required for the DMB32 option. Your System documentation will define any
site-planning considerations. The environmental conditions required by the DMB32 option are specified
in
Chapter 1, Section 1.5.3.

2.4 DMB32 INSTALLATION KITS
|
The DMB32 option is supplied in a kit that contains the parts needed to install the option, but you may
also need the torque wrench (29-17381-00) from the VAXBI installation kit. Check the contents of your

DMB32 installation kit against the list given in this section. Examine all parts for physical damage. Report
damaged or missing items to the shipper immediately, and inform the local DIGITAL office.

The T1012 module is supplied in protective antistatic packaging. Do not remove the module from its
packaging unless you are wearing an anti-static
_wrist strap.
|
o

There are three different versions of the installation kit, tailored to three different system configurations.
These are:

DMB32-LJ for the VAX-8800 and VAX-8500 systems

DMB32-LM for fhe VAX-8200 and VAX-8300 systems

DMB32-LN for the VAX-8800 system with an expander cabinet

The only difference betwe‘e‘n'thé thféé versions is the léngtfi of the six ribbéfi cables that go between the

- VAXBI backplane and the H3033 distribution panel. The contents of the three kits are given in Table 2-1.

" Table 2.1 DMB32 Installation Kit Details
Part Number

Description

T1012

DMB32 module

H3033

DMB32-LJ

-LM

-LN

Distribution panel

12-22246-01

Transition header assembly

17-00740-02

5 ft ribbon cable assembly

17-00740-04

8 ft ribbon cable assembly

17-00740-05

15 ft ribbon cable assembly

-0

12-24866-01

H3195 unbalanced sync loopback

H3196 balanced sync loopback

12-24867-01

12-15336-07

H3197 async loopback

EK-DMB32-UG

DMB32 User Guide

2-2

1
1

When the DMB32 hardware has been installed, the DMB32 synchronous device driver must be installed
before the sync port can be used. The DMB32 synchronous driver is a layered product that must be
ordered separately from DIGITAL, it is not part of the DMB32 hardware kits described in section 2.4.

The procedure for installing the DMB32 Sync Driver is fully described in the DMB32 Sync Driver
Installation Guide supplied in the software installation Kit.
NOTE

VAX/VMS requires that an adapter cable is connected to the sync port before it will configure the
sync device (SIx0).

2.6

CONFIGURATION RULES

In VAXBI systems the base address of each node is defined by the node ID plug fitted to the backplane.
At the base address, the node must identify its device type and its revision level. Therefore, there is no
need for complex fixed, or floating, address schemes, such as are required on UNIBUS and Q-bus systems.

There are, however, two VAXBI configuration rules which do apply to the DMB32.

The DMB32 must have a unique node ID (set by the node ID plug). The DWBUA UNIBUS
adapter is always assigned a node ID of zero; therefore, if the host system has a DWBUA
installed, the DMB32 cannot be node zero.

The DMB32 must not be installed in slot 1 of the first backplane. This is also called slot K1J1
and is reserved for the node which supplies the BI TIME and BI PHASE clock signals.

There may also be system-dependent configuration restrictions, such as those imposed by backplane
capacity, and physical mounting limitations within the cabinet. These limitations will be described in the
host system documentation.

2.7

MECHANICAL INSTALLATION

Figure 2-1 shows how the parts of the DMB32 option fit together. This figure should be used together with
the installation instructions given in this section.

WARNING

Shut off the system power and disconnect the main
system power cord before performing any procedure
in this chapter.

2.7.1

Electro-Static Discharge Precautions

CAUTION

You must wear an anti-static wrist strap connected
to an active ground whenever you work on a system
with the covers removed, or handle the T1012
module.

2.7.1.1 Anti-Static Wrist Strap - The anti-static wrist strap is located within the system cabinet of the
host system (refer to the host system documentation for a description of where to find the wrist strap), and
is connected to ground. Place this wrist strap on your wrist before performing any of the following
procedures.

2-3

2.7.1.2 Conductive Module Containers - Do not remove the T1012 module from
its conductive
container until you are ready to install it into the cardcage. Whenever you remove a VAXBI
module from

the cardcage, place it in a conductive container.
2.7.2

T1012 Module Installation
1.

Insert the T1012 into a slot in the VAXBI cardcagc:,

The module may be installed in any empty slot except slot K1J1 (that is, the first slot in the
first
backplane). The module is keyed
to prevent incorrect installation.

Fit an appropriate node ID plug to the reverse side of the backplane at the position corresponding with the slot where the T1012 module is inserted.
|

Take care not to bcnd the pins of the node ID plug.

VAXBI BACKPLANE (REAR VIEW)

RIB SIDE |
T1012
MODULE

coLoren

N/
|

17-00740-xx

CABLE

STRIPE

TRANSITION

HEADER

ASSEMBLY

H3033

DISTRIBUTION PANEL
KEY

SLOT

REAZY

Figure 2-1

DMB32 Installation

2-5

2.7.3

Transition Header Assembly Installation
1.

Check the VAXBI backplane to see if a transition header assembly (12-22246-01) is already
installed on the backplane at the correct position. If it is, you will not need to continue with the
procedure described in this section. Continue with the installation of the ribbon cables (Section

2.7.4).

NOTE

You will need the torque wrench (29-17381-00) from
the VAXBI installation kit to complete the installation of the transition header assembly.
Fit the transition header assembly to the reverse of the VAXBI backplane at the position
corresponding with the slot where the T1012 module is inserted.
Tighten the screws gradually and alternately to prevent the header assembly from skewing. Use
the torque wrench to tighten the screws to a torque of 5 inch.Ibf (+ or — 1 inch.Ibf).
|

2.7.4 Ribbon Cable Installation
1.

Connect the six ribbon cables (17-00740-xx) into the transition header assembly. Make sure
that the ribbed side of the cables faces towards slot 1 (see Figure 2-1).

Route the six ribbon cables to the I/O panel where the H3033 distribution panel is to be
installed. Refer to the host system documentation for routing details.

2.7.5 Distribution Panel Installation
1.

Connect the six ribbon cables to the distribution panel.

Table 2-2 and Figures 2-2 and 2-3 will help you identify which connector on the transition

header connects to which socket on the H3033 distribution panel. The cable header plugs are

keyed to prevent incorrect installation.

An electrical key signal passes through all six ribbon cables. If any cable is incorrectly installed,
the path of the key signal will be broken and the DMB32 will fail its self-test (see Sections 2.8.1
and 4.3.2).
|

Table 2-2

Ribbon Cable Connections

Transition

H3033
Distribution
Panel Socket

Header
Connector
C-1
C-2

J10
J13

D-1
D-2

J11
J14

E-1
E-2

J15

J12

2-6

Install the H3033 distribution panel into the appropriate position on the system cabinet.

Fit the adapter cable, line printer cable, and async cables (as appropriate) to the distribution
panel. Adapter cables are fully described in Section 2.9, Cabling.

A
z20NE

ZONE B

<)
®

®
®

1O}
®

®
®

® L‘éfi’gm
51

ZONE C

ZONE D

ZONE E

RE427

Figure 2-2

The VAXBI Backplane (Rear View)

"PLATED
EARTH
CONNECTION

J15

213

412

J11

J10

|
RE428

Figure 2-3

The H3033 Distribution Panel (Rear View)

NOTE
VAX/VMS requires that an adapter cable is
connected to the sync port before it will configure
the sync device (SIx0). It also requires that a line
printer cable is connected to the printer port before
it will configure the printer device (LIxO0).
2.8 ACCEPTANCE TESTING
When you have installed the DMB32, run the following tests.
1.

Self-test (runs on power-up)

EVDAK, EVDAJ, EVDAL, EVAAA diagnostics

UETP

The sequence used to test the DMB32 is described in the following sections.

2-8

Power-Up and Self-Test

2.8.1

1. ~ Power-up the host system.
2.

Check that the yellow LED on the T1012 module lights after about four seconds, and stays lit.
This indicates a successful self-test.

On the VAX-8200 and VAX-8300, check the printout from the system console. Immediately
after its own CPU self-test, the host system prints a sequence of numbers and periods, for
example:

o.2....7..

.BCD.

This example indicates that the host has detected modules with node IDs of 0, 2, 7, 11, 12, and
13, and that they have passed their self-test diagnostics. If a module fails its self-test, it is not
configured by the host and the host puts a minus sign in front of the node ID, for example:
o

.2....7..

.-BCD.

This example indicates that the option with a node ID of B4 has not passed its self-test.

The host should recognize that a module is present at the node ID with which you have installed
the T1012 module.

If the DMB32 self-test fails, type the following at the console prompti
»>>

E/P/W 200xx000

<RET>

(where xx is twice the node ID)

The console should respond with 0109,¢, the valid DMB32 device type.

If the console reports an error, check that you have the entered the correct address for the node
ID.

If the console responds with FFFF ¢, try reseating the T1012 module.

If the console gave the correct device type (0109,¢), type the following at the console prompt:
»>>>

E/P/L 200xx0F0

(where xx is twice the node ID)

The console will print out the contents of the GPRO register in the DMB32 which contains bits
that indicate the reason for the self-test failing (see Section 3.3.9 for an interpretation of these
bits).

2-9

2.8.2 Diagnostics
After a successful self-test, use the following diagnostic sequence to make sure that the DMB32 is fully
functional. Full details of these diagnostics and how to run them are given in Chapter 4, Maintenance. Run
each diagnostic for at least one error-free pass.
1.

Load the VAX Diagnostic Supervisor (VDS).
“Load and run EVDAK, the DMB32 level 3 diagnostic.

Boot the VAX/VMS system.
Load and run EVDAJ, the DMB32 level 2R async diagnostic.

Load and run EVDAL, the DMB32 level 2R sync diagnostic.
6.

Load and run EVAAA, the DMB32 level 2R printer diagnostic.

Run UETP.

2.9 CABLING
This section contains details of the distribution panel and adapter cables referred to in Section 2.7. These

adapter cables are not supplied as part of the DMB32 option, but must be ordered separately. Section 2.7
also describes the loopback connectors, both those supplied with the DMB32 option, and those which are
not supplied but are needed to test the adapter cables.
2.9.1

H3033 Distribution Panel
Figure 2-4 shows a front view of the H3033 distribution panel.

2-10

PIN 1

REA29

Figure 2-4 H3033 Distribution Panel (Front View)

2.9.2 Adapter Cables
Adapter cables for V.35, V.24, RS-422, and RS-423-A are available for use on the 50-way sync connector
of the distribution panel. Pinout information of the sync connector is repeated here for reference.
Interconnection and pinout detail for each adapter cable follows.
50-WAY
PIN

SIGNAL
NAME

CODE GROUND

CODE 0

1
CODE
CODE 2
CODE 3
Tx DATA (A
Tx DATA (B)

Tx DATA

PIN 18

RTS/C (A)
RTS/C (B)

LOCAL LOOP

0000000000000
00

SPEED INDICATE

TEST |
REM.LOOP

RI
Rx CLOCK (A)

Rx CLOCK (B)
Tx CLOCK (A)

Tx CLOCK (B)

CLOCK
V.35 Tx CLOCK (A)

V.35 Tx CLOCK (B)
V.35 CLOCK (A)
V.35 CLOCK (B)

V.35 Rx DATA (A)
V.35 Rx DATA (B)

0000000000000
O

Rx DATA (B)

0000000000000
000

)

PIN 34

Rx DATA (A)

V.35 Tx DATA (A)
V.35 Tx DATA (B)

V.35 Rx CLOCK (A)

PIN 50

V.35 Rx CLOCK (B)

DTR

PIN 17

PIN 33

DSR (A)

DSR (B)
RTS

DCD/I (A)

50-WAY D-TYPE CONNECTOR
(MALE PLUG)

DCD/I (B

CTS (A)

CTS (B)
DCE GROUND
TEST 1
TEST 2

DTE GROUND
DTR (A)
DTR (B)

CLOCK (A)
CLOCK (B)
TEST 3
SPEED
(A),(B) WIRES A(+ve) AND B(- ve) OF A TWISTED PAIR
RE1486

Figure 2-5

50-Way Sync Channel Connector

2-12

2.9.2.1

V.35 Adapter Cable
34-WAY

50-WAY SIGNAL
PINS

CODE GROUND
0
CODE
1
CODE
CODE 2
CODE 3

PIN 34

PIN 1

)

—

V.35 Tx CLOCK (A)
V.35 Tx CLOCK (B)
V.35 CLOCK (A)
V35 CLOCK (B)
V.35 Rx DATA (A)
V.35 Rx DATA (B)
V.35 Tx DATA (A)
V.35 Tx DATA (B)
V.35 Rx CLOCK (A)
V.35 Rx CLOCK (B)
DTR

PIN 18

PINS

NAME

o 3o

Y
a

o
O O
O
O

o O

%0
®© 0 ©

\Y}

o O
O

]

PIN 17

PIN 50

PIN 33

\_
50-WAY D-TYPE CONNECTOR

* CONNECTED TOGETHER

0 5 ©

AH#

%o
®© o. °,

DTE GROUND

o) o @)
o © o

®) g O

%06
©°%
o
®

o Qo

R
T

DSR (A)
DSR (B)
RTS
DCD/I (A)
DCD/! (B)
CTS (A)
CTS (B)
DCE GROUND

(FEMALE)

Yy,

34-WAY SQUARE

CONNECTOR (MALE)

# CONNECTED TO DCE GROUND
(A),(B) WIRES A(+ve) AND B(-ve) OF A TWISTED PAIR
RE147

Figure 2-6

BCI19F-02 (17-011 125-01) Adapter Cable Detail

2-13

50-WAY

SIGNAL

PINS

25-WAY

NAME

WN -

V.24 Adapter Cable

PINS

CODE GROUND

CODE 2
CODE 3

TEST |

REM.LOOP

Rx CLOCK (A)

Rx CLOCK (B)
Tx CLOCK (A)

20
21
22
33

34
35
36
37
38
39
40
41

)

Tx CLOCK (B)

CLOCK
DTR
DSR (A)
DSR (B)

PIN 1

0000000000

LOCAL LOOP

RTS

O0000000000

0000000000000
00

Rx DATA (A)
Rx DATA (B}

PIN 34

0000000000000
00

Tx DATA

PIN 1

0000000000000
00

8
12

PIN 18

CODE O
CODE 1

2.9.2.2

DCD/I (A)
DCD/! (B)

CTS (A)

PIN 17

CTS (B)
DCE GROUND

DTE GROUND

SPEED

PIN 50

PIN 14

PIN 13

PIN 33

50-WAY D-TYPE CONNECTOR
(FEMALE)

25-WAY D-TYPE

CONNECTOR (MALE)

* — CONNECTED TOGETHER
# — CONNECTED TO DCE GROUND

(A).(B) = WIRES A(+ve) AND B(- ve) OF A TWISTED PAIR
RE149

Figure 2-7

BC19D-02 (17-01110-01)Adapter Cable Detail

2-14

2.9.2.3

RS-422 Adapter Cable
37-WAY
PINS

50-WAY SIGNAL
NAME
PINS

CODE GROUND

CODE 1

CODE 2

(A)
TxTx DATA
DATA (B)

a22

| go S50

o 3

RTS/C (B)

o 5 ©

S o

Rx DATA (B)

CODE O

Rx DATA (A)

LOCAL LOOP

TEST |

16
18

RTS/C (A)

DSR (B)
DCD/! (A)

29
13

CTS (A)

40
41

45
46

o 9%

DSR (A)

DCD/I (B)

CTS(B)

DCE GROUND

19, 37

DTE GROUND

DTR (A)
DTR (B)

12
30
17

CLOCK (A)

CLOCK (B}

SPEED

o ©

Tx CLOCK (A}

O 5 ©

g o g

Tx CLOCK (B}

g o

35
37

0 3o

0 o O

Rx CLOCK (B)

o
9
o 8
o 3

o 9o

) g o

o ©

o 9%

Rx CLOCK (A)

o 35

3 03

REM.LOOP

PIN 1

0O 5 O

> 906

SPEED INDICATE 2

PIN 20

PIN 34

PIN 1

CODE 3

PIN 18

PIN 17

o 5

o ©

o g

oIN 37

o 3

—

o 3
o

PIN 19

PIN 50

PIN 33

50-WAY D-TYPE CONNECTOR
(FEMALE)

37-WAY D-TYPE
CONNECTOR (MALE)

* — CONNECTED TOGETHER

(A).(B) — WIRES A(+ve) AND Bf-ve) OF A TWISTED PAIR
REYB0

Figure 2-8

BC19B-02 (17-01108-01) Adapter Cable Detail

2-15

2.9.2.4

RS-423-A Adapter Cable

50-WAY

SIGNAL

37-WAY

CODE GROUND ~

PINS

NAME

PINS

CODE 0

CODE 1

Tx DATA

Rx DATA (B)

4
5

Rx DATA (A)

SPEED INDICATE

33
34
35

1S o

S o8

o ©

5 O

g o

S o

O 5 O
S o3

o ©
o g

o 35
O 5

S 9%

DCD/1 (A)
DCD/1 (B)

23
32

PIN 33

39
40

CTS (A)
CTS (B)

9
27

50-WAY D-TYPE CONNECTOR
(FEMALE)

DTE GROUND

|
SPEED

PIN17

o g

37
38

DCE GROUND

©o
9 o0

12
11
29

996

o
o

26
5

RTS

18
14

DTR
DSR (A)
DSR (B)

Tx CLOCK (B)
CLOCK

o g

5 O

Rx CLOCK
(A)

Rx CLOCK (B)
TxCLOCK (A)

PIN1

| PIN34

o 30

TEST |
REM.LOOP

19
20

PIN1

LOCAL LOOP

PIN20
S

CODE
2
CODE
3

15
16

PIN 18

PIN 37 W%m PIN 19
PIN50

37-WAY D-TYPE
CONNECTOR (MALE)

19, 22, 25,

30, 35, 37
16

* - CONNECTED TOGETHER
(A). (B) — WIRES A(+ve) AND B(-ve) OF A TWISTED PAIR
RE151

Figure 2-9

BCI19E-02 (17-01111-01) Adapter Cable Detail

2.9.3 Loopback Connectors
— A range of loopback connectors is available for testing the DMB32. Three are supplied with the option:
H3197 1s used to test a single async channel, H3195 and H3196 are used to test the sync channel. The
other loopback connectors are used to test the adapter cables and modem cables, and are not supplied with
the DMB32 option. The full list of loopback connectors is:
H3196 50-way balanced (sync channel)

H3195 50-way unbalanced (sync channel)

)

Supplied
with the
option

H3197 25-way (async channel)

H3250 34-way V.35 (sync channel)

H3248 25-way V.24 (sync channel)

H3198 37-way RS-422 and RS-423-A (sync channel)

2-16

2.9.3.1 H3196 50-Way Balanced Loopback Connector — This loopback connector is used to test all the
balanced, and many of the unbalanced, drivers and receivers. (DTR, CTS, RTS, and DCD are tested with
»

both the unbalanced and balanced loopbacks.)

The balanced loopback is a 50-way D-type connector that plugs into the sync port on the distribution
,

panel, and is wired as given in Table 2-3.

Table 2-3 H3196 Balanced Loopback Interconnections
Pins Connected Together

Signals

1,3,4,5

Connector identity code

6,11
7,12

Data A
Data B

47.18,20
48.19,21

Clock A
Clock B

29,27
30,28
25,23,31
26,24,32

V.35 data A
V.35 data B
V.35 clock A
V.35 clock B

Ground and receiver inputs

35,41,44

RTS/C A, DCD/T A
RTS/C B, DCD/I B
Local loop, Test indicator
Speed, Ring indicator, and Speed indicator
Remote loop, DSR A

- 9,37
10,38
13,15
50,17,14
16,34

DTR A, CTS A
DTR B, CTS B

45,39
46,40

2.9.3.2 H3195 50-Way Unbalanced Loopback Connector — This loopback connector is used to test all
the unbalanced drivers and receivers. It is a 50-way D-type connector that plugs into the sync port on the
distribution panel, and is wired as given in Table 2-4.

Table 2-4

H3195 Unbalanced Loopback Interconnections

Pins Connected Together

Signals

1,2,5
12,19,21,35,38,40,41,44

Connector identity code
Ground and receiver B inputs

13,15
16,34
50,17,14

Local loopback, Test indicator
Remote loop, DSR
Speed, Ring indicator, and Speed indicator

8,11

Data

22,18,20
33,39

Clock
DTR, CTS

36,37

RTS, DCD

2-17

2.9.3.3 H3197 25-Way Loopback Connector (Async Channels) - This connector is used to test a single
asynchronous channel. (Eight H3197s will be needed to test all the async channels simultaneously.) It is a
25-way D-type connector that plugs into an async port on the distribution panel, and is wired as shown in
Figure 2-10.

The wiring of the H3197 loopback is similar to that in the H325 async loopback (used with most other
async communications options), and the H325 connector can be used to test the DMB32. However,

because of the physical layout of the distribution panel, it is not possible to connect H325 loopbacks to all

eight ports at the same time, nor to connect them to JS, J6, or J7 without first removing the sync port
cable.

CCITT No.

NAME

NOT USED

NOT USED
NOT USED
103

TXD

104

RXD

105

RTS

106

CTS

»
17

PIN
1
12

DCD

107

DSR

90
o 4

3
4

S
O
5 O
o 3

DTR

125

O
O

108.2

109

PIN 25

PIN14
|
R

PIN13

25-WAY D-TYPE

CONNECTOR (MALE)

22
RE152

Figure 2-10

H3197 Loopback Connector

2.9.3.4 H3250 34-Way Loopback Connector (V.35) — This connector is used to test the V.35 interface

AUX CLK +

:;;

TX CLK DIFF +

-t

RX CLK DIFF +

——

AUX CLK -

of the sync channel and the V.35 adapter cable. It is a 34-way square connector that attaches to the end of
the V.35 adapter cable, and is wired as shown in Figure 2-11.

—>—1—®

TX CLK DIFF-

—e

a
°

RX CLK DIFF -

TX DATA DIFF +

RX DATA DIFF +

—=

®S

RX DATA DIFF -

—e

0‘ 09 Oh o°

RTS

—>—1—e

o ° on©

T
CTS

®
-

CDET

—e

DTR

—»

TX DATA DIFF -

DSR

—»

——e

X
P

.
|

FO-

p O

4,0

ot o of o
QO

- OP

c»‘d ob o) o0

0¥zO
%y oVO
Ow
[

° D °
34-WAY SQUARE
CONNECTOR

(FEMALE)
RE434

Figure 2-11

H3250 Loopback Connector

2.9.3.5 H3248 37-Way Loopback Connector (V.24) — This connector is used to test the V.24 interface
of the sync channel and the V.24 adapter cable. It is a 37-way D-type connector, and is wired as shown in
Figure 2-12.
)

Tx DATA

Rx DATA(A)

RTS

CTS(A)

;

—ee—{—2
o
°

DSR(A)

DCD/I(A)

-l

o
L

N
)

PIN1

14
*

Tx CLOCK (A) —t—2

PIN 25

S o

Rx CLOCK (A)

—at{—s

LOCAL LOOP

—»—{—

DTR
RI

SPEED
CLOCK
TEST |

()

o
o 3

'fg
A

|22

i
o
—

O o
° 3
O o

]

-l

./
PIN 13

PIN 14

25-WAY D-TYPE

CONNECTOR
(FEMALE)

RE430

Figure 2-12

H3248 Loopback Connector

2-20

2.9.3.6 H3198 37-Way Loopback Connector (RS-422/423) — This connector is used to test the RS-422
and RS-423 interfaces of the sync channel and the RS-422 and RS-423 adapter cables. It 1s a 37-way Dtype connector, and is wired as shown in Figure 2-13.
RS-422

RS-423

SPEED INDICATE ~ SPEED INDICATE

—={—

Tx DATA (A)

Tx CLOCK (A)
Rx DATA (A)

Tx DATA (A)

Tx CLOCK (A)
Rx DATA (A)

——s

RTS/C (A)

RTS

Rx CLOCK (A)
CTS (A)

Rx CLOCK (A
CTS (A)

-1
“f-e

DSR (A)

LOCAL LOOP
DTR (A)

DCD/1 (A)
RI

A
<t

PIN1

PIN 20

LOCAL LOOP

o ©

DTR (A)

-t

CLOCK (A)

—t-e

“t-e

DCD/I (A)

SPEED

TEST |

CLOCK (A)

“t-e
%

1o
-

o 3

8 o
o ©

o ©

o) ’g

DCE GROUND

S o

Tx DATA (B)

Tx CLOCK (B)

DTE GROUND

Tx CLOCK (B)

—1—=

S o

Rx DATA (B)
RTS/C (B)
Rx CLOCK (B)
CTS (B)

Rx DATA (B)
DTE GROUND
Rx CLOCK (B)
CTS (B)

———=
«t-e
-~
.

DSR (B)
DTR (B}

DSR (B)
DTE GROUND

-~
———=

DCD/I (B)
NC
NC
NC
CLOCK (B)

DCD/! (B)
NC
NC
NC
DTE GROUND

1=
.
-t
-1
—>1—=

-t

DTE GROUND

-t

o @

PIN19

PIN 37

37-WAY D-TYPE
CONNECTOR
(FEMALE)

RE153

Figure 2-13

H3198 Loopback Connector

2-21

CHAPTER 3

OPERATION AND PROGRAMMING

3.1

SCOPE

This chapter describes the device registers, and how they are used to control and monitor the DMB32. The
chapter covers:

3.2

‘~

The register map

The bit functions and format of each register

Programming features available to the host

OPERATION

The host system controls and monitors the DMB32 option by using registers in the BIIC and CASRAM.
Command longwords, words, or bytes are written to the registers by the VAXBI host, and are interpreted
and executed by the DMB32 firmware. Status reports and data to the host are also transferred using the
registers.

3.2.1

DMB32 Register Map

The DMB32 occupies 8 Kbytes of VAXBI memory-mapped 1/O space. During normal operation, all
commands to the DMB32 are made through the device registers in this address space.

The ‘Base’ address of the 8 Kbytes within the VAXBI bus I/O space is determined by the ‘Node ID’ plug
which is fitted to the VAXBI backplane. There are no option switches on the module itself.
The set of DMB32 device registers is composed of two major groups. The first group includes the VAXBI
registers and the second includes all the DMB32-specific registers. These can be further subdivided by
function, as shown in Figure 3-1.

Table 3-1 lists each DMB32 device register and gives its type and address offset from the ‘Base’ address of
the node. This address is the lowest I/O address to which the option responds (address bits <11:0> are
|
zero), and is determined by the Node ID plug.
The designation ‘I’ (for ‘Indexed’) in the ‘Address Offset’ column indicates that a set of identical indexed
registers (one for each channel) are accessed at that location (see Section 3.2.2).

3-1

VAXBI ADDRESS

(HEX)
)

BASE

VAXBI REQUIRED REGISTERS
BASE + 20
BIIC SPECIFIC DEVICE REGISTERS

IN BIIC <

BASE + 44

NOT USED

BASE + FO

GENERAL PURPOSE REGISTERS
.

BASE + 100
PRIMARY SCRS
AT

BASE + 120

BASE + 150

DMA TRANSLATION REGISTERS
BASE + 160

PRINTER CHANNEL REGISTERS

BASE + 180

N CASRAM <

SYNC CHANNEL REGISTERS

BASE +1CO

ASYNC CHANNEL REGISTERS

NOT USED

‘

NOMINAL FIFO LOCATIONS,

AND RESERVED REGISTERS
g

BASE + 200

BASE + 204
|

BASE + 210

USED BY DMB32 FOR FIFOS,
MANAGEMENT
OF DMA,
,

IN CASRA

ASRAM <

AND CONTROL, STATUS

AND BUFFERING OF PORTS

J BASE + 1FFC

RE154

Figure 3-1

DMB32 Register Map

3-2

The register type is given as R/W (Read/Write), R (Read Only) or NU (Not Used).
Table 3-1

DMB32 Registers
Address Offset

Name

Device type register
VAXBI control and status register
Bus error register
Error interrupt control register
Interrupt destination register
IPINTR mask register
Force-Bit IPINTR/STOP destination
IPINTR source register
Starting address register
Ending address register

DTYPE
VAXBICSR
BER
EINTRCSR
INTRDES
IPINTRMSK
FIPSDES
IPINTRSRC
SADR
EADR

BCI control register
Write status register
Force-Bit IPINTR /STOP command register
User interface interrupt control
General-purpose register 0
General-purpose register 1
General-purpose register 2
General-purpose register 3
Maintenance register
Async control and status
Sync control and status
Printer control and status
Device configuration
2nd async control and status
2nd sync control and status
2nd printer control and status
System page table register
System page table size
Global page table register
Global page table size
Printer prefix/suffix control
Printer buffer address
Printer buffer count
Printer control
Printer carriage counter
Printer page size descriptor
Transmit buffer address
Transmit buffer count/offset 1
Receive buffer address 1
Receive buffer count/offset 1
Buffer 1 transmit control
Buffer 1 receive control
Sync line parameters 1
Sync line parameters 2
Transmit buffer address 2

BCICSR
WSTAT
FIPSCMD
UINTRCSR
GPRO
GPR1
GPR2
GPR3
MAINT
ACSR
ACSR
PCSR
CONFIG
ACSR2
SCSR2
PCSR2
SPTE
SPTS
GPTE
GPTS
PFIX
PBUFFAD
PBUFFCT
PCTRL
PCAR
PSIZE
TBUFFADI1
TBUFFCT1
RBUFFADI
RBUFFCT1
TLNCTRLI1
RLNCTRLI1
LPRI1
LPR2
TBUFFAD?2

3-3

(Hexadecimal)
0
5
8
C
10
14
18
1C
20
24

28
2C
30
40
FO
F4
F8
FC
100
104
108
10C
114
118
11C
120
150
154
158
15C
160
164
168
16C
170
174
180 (I)
184 (I)
188 (I)
18C (I)
190 (I)
194 (I)
198 (I)
19C (I)
1A0 (I)

Type
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W

- NU
NU
NU
R/W
R/W
NU
NU
NU
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Table 3-1

DMB32 Registers (continued)
Address Offset
(Hexadecimal)

Name

Type

Transmit buffer count/offset 2

TBUFFCT?2

1A4 (D)

R/W

Receive buffer address 2

RBUFFAD?2

1A8 (I)

R/W

Receive buffer count/offset 2

RBUFFCT?2

1AC (D)

R/W

Buffer 2 transmit control

TLNCTRL2

1BO (I)

R/W

Buffer 2 receive control

RLNCTRL2

1B4 (I)

R/W

Sync line parameters 3

LPR3

1B8 (I)

R/W

Sync buffer control bits

BUFCTRL

1BC (I)

R/W

Transmission preempt buffer

PREEMPT

1CO (I)

R/W

Transmit buffer address

TBUFFADD

1C4 (1)

R/W

Transmit buffer count/offset

TBUFFCT

1C8 (I)

R/W

Line parameter register

LPR

1CC (I)

R/W

Line control register

LNCTRL

1D0 (1)

R/W

Line status register

LSTAT

1D4 (1)

R/W

Flow control characters

FLOWC

1D8 ()

R/W

Reserved

1DC to IFC

Receive console data register

200

Transmit completion FIFO

TBUF

204

Sync line completion FIFO

SBUF

208

Receive buffer

RBUF

20C

3.2.2

Registers marked (I) are implemented as a set of indexed registers, one for each channel. When

an (I) register is accessed, the address is internally indexed by the ASYNC.IND.ADD parameter in the async CSR (for async registers), or by the SYNC.IND.ADD parameter in the sync
CSR (for sync registers), the value of the index parameter being the channel number. Therefore, before (I) registers are accessed, the channel number must be written to the corresponding
CSR, as shown in the following example.
To read the async line parameter register for channel 3, the following commands would be
executed:

MOVB #CHAN,
MOVL

@#BASE+~X104

@#BASE+”X1CC,

sWRITE CHANNEL NUMBER TO ACSR
;s READ

THE

LPR

where CHAN (the channel number) = 3.
Not all register bits are specified. In a write action, any unspecified bit must normally be
written as a 0. In a read action, unspecified bits are undefined. However, if an unspecified bit is
read as a 1, it can be written as a 1 or 0. This allows read-modify-write operations to work
correctly.
|
|

3-4

The VAXBI architecture requires that all registers on the VAXBI bus are capable of being read
without the contents of the register changing. This means that FIFOs which are ‘popped’ by a
read from the host are not allowed. To overcome this restriction, the registers that are FIFOs
are read by the host without removing the FIFO entry (if there is one). To remove the top FIFO
entry, the host must write to the location of the FIFO. However, a write must not be done when
the FIFO 1s empty.

The register at ‘Base + 200’is reserved for the VAXBI console. The DMB32 does not support
console functions, therefore this register does not exist (thatis, the DMB32 wfll respond to an
access to this address with a NO ACK).
Many registers have read-only fields (or fields that may not be written to under some circumstances). The host should make sure that it does not accidentally write to these registers.

Register locations between ‘Base + 0218’ and ‘Base + 1FFC’ are used as register, FIFO, and
buffer space by the DMB32. These locations can only be accessed by the host when the DMB32
is in maintenance mode (MAINT<4> or <5> set).
The host should avoid writing to registers unnecessarily. This is because writing to some
registers (for example, the parameter registers) causes the on-board microprocessor to examine
the registers to determine what action it must take. Such writes, if unnecessary, will degrade the
performance of the option.

3.3

The following abbreviations are usedin the illustration of the registers and the definition of the register
bits:

Blank

= Not defined

0
1

= Read only and always read as 0
= Read only and always read as 1

R
w
R/W
WIC

= Read only
= Write only
= Read/write

= Write ‘1’ to clear
= Special case, refer to the text

A
B
C
D

= Cleared by Bus Reset only
= Cleared by Bus Reset and Programmed Reset
= Cleared by Bus Reset, Programmed Reset and Initialization
= Cleared by Bus Reset, Programmed Reset, Initialization and Selective Line Reset

= Set

Ec
El

= Cleared

by deassertion of BL_DC_LO.L after a successful self-test

= Loaded

== Cleared by a STOP command to the DMB32

where:

Bus Reset includes power-up

Programmed Reset is MAINT<1>

Imtlahzatmnis ACSR2«:10>~ SCSR2<10> and PCSRZ«*:IO‘:»

)

Selectlve Line Resetis LPR1<31>

3.3.1

Device Type Register (DTYPE)
DTYPE (BASE)

30 29

26 25 24

2120

17 16

12 11

10 09

08 07

04 03

02 01

lJlW”W%W”lMWlMWIMN%W%IIW%W%%%%W%
: REVCODE

Bit

Name

<15:0>

DEVTYPE

Description

(Device Type)
(R, El)
<31:16>

DE\;TVYF‘E

This field contains 0109, which identifies the device as a

DMB32.

REVCODE

This field contains a value that identifies the revision level of

(Revision Code)
(R, El)
3.3.2

the DMB32.

VAXBI Control and Status Register (VAXBICSR)
VAXBICSR (BASE + 4)

R]Rlfllnla Rlflln

RIR|R|R|R a!n

IREV

ITYPE

<3:0>

Name
NODE.ID

(Node ID)

(R)

08 07

04 03

Rlfl R| R RWW*IO %WWWW%WWIR RIR|R
SES
HES

Bit

|BROKE| NRST
INIT

STS

UWP | SEIE
~

HEEE

NODE ID
ARB

Description
This field contains the node ID of the DMB32. It is loaded from

the <3:0> lines at power-up (from the node ID plug).

Bit

Name

Description

<5:4>

ARB

These two bits control the mode of arbitration.

(R/W, Ec)

00 - Round robin

SEIE

Determines whether an error interrupt is generated when SES is

<6>

(Arbitration Control Bits)

01 - High priority
10 — Low priority
11 — No arbitration

asserted.

(Soft Error Interrupt
Enable)

(R/W, Ec, F)
<7>

HEIE
(Hard Error Interrupt

Determines whether an error interrupt is generated when HES
is asserted.

Enable)

(R/W, Ec, F)

<8>

<10>
<l1>

<12>
<13>
<14>

UwpP

(Unlock Write Pending)
(W1C, Ec, F)

NRST

This bit indicates that a Read Lock transaction has successfully

completed, but there has not yet been a Write Unlock
command. If a Write Unlock is attempted while this bit is clear,
the ISE bit (BUSERR<26>) will be set.

Setting this bit starts the BIIC and DMB32 self-test sequence.

(Node Reset)
(*)

This will initialize the DMB32 firmware. This bit will always
read as 0.

STS

This bit is cleared when BIIC self-test is started. It is set when

BROKE

When this bit is sct,‘ the DMB32 has not passed the self-test. No

INIT

When set, this bit indicates that the DMB32 has not completed

'SES

- This bit indicates that one or more soft error bits in the bus

(Self-Test Status)

(Broke)
(WI1C, Ec)
(W1C, Es)
(Soft Error Summary)

the test is passed. If it stays clear, the test has failed.

other register should be written to when this bit is set. The
contents of other registers may not be valid when this bit 1s set.
its initialization.

error register are set.

(R)

<15>

HES

~ (Hard Error Summary)

This bit indicates that one or more hard error bits in the bus
error register are set.

(R)

<23:16>
|

ITYPE

(Interface Type)

This field indicates the primary interface to the VAXBI. This
field reads as 01,4 in the DMB32.

3-7

Bit

Name

Description

<31:24>

JREV
(Interface Revision)

This field contains the revision level of the device that provides

the primary interface to the VAXBI.

(R)
3.3.3

Bus Error Register (BER)

BER (BASE + 8)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11

LT T

10 09 08 07 06 05 04 03 02 01 00

L
olo
[e[o[o e [e[
[T

NMR

| CTE

MTCE

Bit
<0>

MPE

ISE

IVE

TDF

| SPE

CPE

| RTO |

RDS

<2>

<17>

NEX

UPEN

]

NPE

CRD

Odd parity was detected on the bus during the second cycle of a

two-cycle sequence durmg which NOARB and BUSY were
unasserted.
,

CRD

(Corrected Read Data)
(W1C, Ec)

transaction initiated by the master port.

UPEN

CRD status

code

was

received

during

READ-type

IPE

A parity error was detected on the encoded master ID during an

Imbedded ARB cycle.

Indicates the BIIC parity mode:

I — User-generated
0 - BIIC-generated
It is always zero in the DMB32.

ICE

A RESERVED or Illegal Confirmation code was received

(Illegal Confirmation
Error)
(W1C, Ec)

during a transaction in which the BIIC was involved.

NEX

Set when a NO ACK response is received for a READ-type or

(Non-Existent Address)
(WIC, Ec)

<18>

IPE

NPE

(User Parity Enable)
(R)

<16>

ICE

Description

(ID Parity Error)
(WI1C, Ec)
<3>

STO

Name

(Null Bus Parity Error)
(WI1C, Ec)
<l>

BTO

BTO
(Bus Timeout)
(WIC, Ec)

WRITE-type command sent by the BIIC.
|

Set if the BIICis unable to start at least one pendmg transaction
before 4096 cycles have elapsed.

3-8

Bit

Name

Description

<19>

STO
(Stall Timeout)

Set if the slave port asserts the STALL code on the RS<1:0>
lines for 128 consecutive cycles.

(W1C, Ec)
<20>

<21>

<22>

RTO

Set if the master receives 128 consecutive RETRY responses

(Retry Timeout)
(W1C, Ec)

from the selected slave for the same master port transaction.

RDS

Set if an RDS or RESERVED Status Code is received during a

(Read Data Substitute)
(W1C, Ec)

READ-type or IDENT (for vector status) transaction.

SPE

Set if the slave port detects a parity error on the bus during a

(Slave Parity Error)

non-ARB cycle of a transaction for which it was selected.

(W1C, Ec)
<23>

<24>

<25>

CPE

Set when the BIIC detects a parity error in a command/address

(Command Parity Error)
(WI1C, Ec)

cycle.

IVE

Set by the selected slave if it receives anything but an ACK

(IDENT Vector Error)
(W1C, Ec)

confirmation from the IDENTing master for the Interrupt
Vector. |

| TDF |

(Transmitter During
Fault)

Set if the BIIC was driving the VAXBI DAL and I lines (I lines

only during the Imbedded ARB cycle) during a cycle that
resulted in setting the SPE, MPE, CPE or IPE error bits.

(W1C, Ec)

<26>

ISE

Set if the DMB32 successfully completes a Write Unlock

<27>

MPE

Set if the master detects a parity error on the bus during a

<28>

CTE

Set if the DMB32 detects that its attempt to assert the NO

(Interlock Sequence
Error)
(WI1C, Ec)

(Master Parity Error)
(WI1C, Ec)

(Control Transmitter

Error)

transaction when the UWP bit (BICSR<8>) is clear.
~
|

READ-type or vector ACK data cycle.

ARB, BSY, or CNF<2:0> lines has failed.

(WI1C, Ec¢)
<29>

MTCE

Set if the master’s transmitted data on the DAL, I and P lines

(Master Transmit

does not match the received data.

Check Error)
(WI1C, ED

Bit

Name

Description

<30>

NMR
(NO ACK to MultiResponder Command
Received)
(W1C, Ec)

Set if the master receives a NO ACK response for an INVAL,
STOP, IPINTR, BDCST, or RESERVED command.

3.3.4

Error Interrupt Control Register (EINTRCSR)

EINTRCSR (BASE + C)

30 29

[ofofo]efe]o]o L

Lo |

INTR

10 09

08 07

06 05

04 03

02 O1

R Rl o | TPl
o
,

NTRC

LEVEL

VECTOR

SENT

INTRAB

Bit
<13:2>

Name
VECTOR

(Error Interrupt Vector)
- (R/W, Ec)

<19:16>

LEVEL
(Error Interrupt Level)
(R/W, Ec)
|

Description
Vector used during error interrupts. It is transmitted when the

DMB32 wins an IDENT ARB cycle on an IDENT that
matches the conditions in this control register.

Determines the level at which interrupts are transmitted.
Also helps to determine whether this register will respond to

IDENT commands. If any level bits in the IDENT command

match this field (and there is a match in the destination mask),
this register will arbitrate for the IDENT.
<20>

INTR.FORCE

(Force Error Interrupt)
(R/W, Ec, F)
<2i>

INTR.SENT
(Error Interrupt Sent)
(R/W, Ec, F, *)

<22>

INTRC
(Error Interrupt

Complete)

(R/W,
Ec, *)

When set, this bit causes an error interrupt request.

The

DMB32 will set this bit when a DMB32 error has occurred and
the error interrupt enable bit is set.

Indicates that an INTR command has been sent for this
interrupt and that an IDENT command is expected. Cleared
~during an IDENT command after a Level and Master ID
match is detected. Also cleared if the error interrupt request is
deasserted.
|

Set when the vector for the error interrupt has been transmitted

successfully, or has been aborted. Cleared when the error

interrupt request is removed.

Bit

Name

Description

<23>

INTRAB
(Error Interrupt Abort)

Set if the error interrupt has aborted. It can only be cleared by
the user and has no effect on the BIIC to send further INTR or
respond to IDENT cammands

(R/W, Ec, *)

3.3.5 Interrupt Destination Register (INTRDES)
INTRDES (BASE + 10)

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11

lolololololololojo}jolojOo]|lO]O]O

Bit

<15:0>

10 09 08 07 06 05 04 03 02 01 0O

O,WW%%%%%WW%%WWWW%%«%WWWW

INTRDES

’

Name

Description

INTRDES

This field is sent out during an INTR command and is used by
other nodes to determine whether they should respond.

(INTR Destination)
(R/W, Ec)

During an IDENT command, the decoded master’s ID is
compared with this word. If there is a match, the BIIC will
respond to the IDENT, provided that there is an interrupt
pending that matches the level transmitted in the IDENT
command.

Starting Address Register (SADR)

3.3.6

SADR (BASE + 20)

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11

o|o R R

R TR
,

10 09 08 07 06 05 04 03 02 01 00

TR PR PR i p'v olofofofofofolofo|olojofo|o]o]oo]

STARTING

ADDRESS

Bit

Name

Description

<29:18>

STARTING. ADDRESS Bits <29:18> of the start address of a block of addresses to be
recognized by the BIIC as node window space (note that the
(Starting Address)
DMB32 uses window space only for maintenance). The lowest
(R/W, Ec)
|

address recognized has bits <17:0> equal to 0.

3-11

3.3.7

Ending Address Register (EADR)

' EADR (BASE + 24)

30 29

08 07

04 03

Lo Lo Poftofa PlPoult
o]ao [ o[ e[ o[ o[ e JeJ o e o] e JoTo o e oo o]
ENDING
ADDRESS

~ RE94

Bit

Name

Description

<29:18>

ENDING. ADDRESS

Bits <29:18> of the address of the first location after the block

(Ending Address)
(R/W)

of addresses to be recognized by the BIIC as node window
space. The lowest address recognized has bits <17:0> equal to

3.3.8 User Interface Interrupt Control Register (VINTRCSR)
UINTRCSR (BASE + 40)

30 29

FiN

INTRAB

—~——

INTRC

INT.
SENT

14 13

INT.
FORCE

10 09

08 07

04 03

VECTOR
(NOT USED)

EX.

VECTOR

RESS

NOTE
When EX.VECTOR (bit <15>) is set, the other
fieldsin this register do not need to be used. Since
the DMB32 always has EX.VECTOR set, the host
would not normally use this register. However, the
information in bits <16:31> is still valid as described
here.

Bit
<13:2>

Name

Description

VECTOR

The DMB32 does not use this field.

(Interrupt Vector)
<15>

EX.VECTOR

(External Vector)

(R/W, Ec)

This bit is always set on the DMB32. This allows the firmware

to specify the interrupt vector directly.

Bit

Name

Description

<19:16>

FORCE
(INTR Force)

The four bits correspond to the four interrupt levels. When a bit
is set the BIIC generates an interrupt at the specified level.

(R/W, Ec, F)
<23:20>

<27:24>

SENT

- The four bits correspond to the four interrupt levels. When an

(INTR Sent)
(WIC, Ec, F, *)

INTR command has been successfully transmitted, the
corresponding bit is set. The bit is cleared during an IDENT

INTRC

The four bits correspond to the four interrupt levels. When the

(W1C, Ec, *)

an INTR command sent under the control of this register is
aborted, the corresponding bit is set. Removing the interrupt
request clears the corresponding bit. While an INTRC bit is set,
no further interrupts at that level are generated by this register,
nor will this register respond to any IDENTS when the INTRC

command following the detection of a level and Master ID
match. Clearing the bit allows the interrupt to be resent if the
node loses the IDENT arbitration or if the node wins but the
vector transmission fails. The bit is cleared by removing the
interrupt request.
|

(INTR Complete)

vector for an interrupt has been successfully transmitted, or if

bit is set at IDENT level.

<31:28>

3.3.9

INTRAB

The four bits correspond to the four interrupt levels. If an

(INTR Abort)
(W1C, Ec, *)

INTR command sent under the control of this register is
aborted, the corresponding bit is set. These are status bits only
and have no effect on the ability of the BIIC to send or respond
to further INTR or IDENT commands.

General Purpose Register 0 (GPRO)

Talwl[w]alalaa
=] [=]=]=]*]]~]

o¢

15 14

10 09 08 07 06 05 04 03 02 01

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S
wox
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L2 v auacgt§
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€«

4«

€«

€&
2

g
2

«©

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€&
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§F

S EEFEEEE
<oEQF
V
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x Q9 O

sEEEEEEECZEZ
Y2 EsE g2
gwmwuxwgmfiggg@amg@mfi
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2
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[

222 22 =200% g Y8EE5ZQ28E
3
555523882283S6
S5
2 2 << << E&ES3ISIFFQ9E
o
[

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2h

SYNC INTERNAL Rx/Tx ERROR

SYNC EXTERNAL Rx/Tx ERROR

SYNC EXTERNAL MODEM ERROR

13 12

?‘
&

EX
B

PRINTER PORT ERROR

18 17

BIIC LOOPBACK/SELF-TEST ERROR

BIHC INTRA-NODE TRANSACTION ERROR ——|

ossomme—,

30 29 28 27 26 25 24 23 22 21 20 19

BIIC INTRA-NODE MASK TRANS ERROR ——|

o¢

GPRO (BASE + FO)

Bit

Name

Description

<31:0>

TSMR

This register is used as the self-test status register TSRO. It
provides for redundancy in DMB32 self-test error reporting
should the RX FIFO be defective.

(R, Ec)

After a self-test sequence, any errors that were found are
reported here by setting the corresponding bit. Bit <31> is set
to indicate that the contents of this register are valid.

See also Section 4.3,2.
3.3.10 Maintenance Register (MAINT)
MAINT (BASE + 100)

30 29 28 27 26 25 24

23 22 21 20

18 17

13 12

RESERVED

CABLE
KEY

10 09

08 Q07 06 05 04 03 02 01

PHWT SYNC

LEVEL

SELF | RESET

TEST
RESERVED

<0>

RV Ry

MA NT. SK PROG.

AG ASYNC

Bit

PTE

FORCE

VALID

FAIL

Name

Description

FORCE.FAIL

When this bit is set, the DMB32 will act as if the self-test has

(Force Failure)

failed. This allows the self-test failure logic to be tested.

(R/W, D)
<l>

PROGRAMMED.RESET

(Programmed Reset)
(R/W, B)

Set by the host to request a programmed reset. This causes the

DMB32 to run self-test and initialize itself. Programmed reset is
the only way to use the Skip Self-Test and Forced Failure
features.
This bit is set by any reset operation. It stays set until the reset
is complete. The host should not access any registers, other than
MAINT and BIIC registers, while this bit is set.

<2>

PTE.VALID

(Page Tables Valid)
(R/W, A)

This bit is set by the host to indicate that it has set up the

SPTE, SPTS, GPTE and GPTS registers. This bit should be

cleared by the host when a programmed reset is requested,
otherwise it may stay set (thatis, it may not be automatically
cleared by reset).

3-14

Bit

Name

Description

<3>

SKIP.SELF.TEST
(Skip Self Test)

When this bit is set, the DMB32 will bypass normal self-test
operations. This results in a faster reset and allows diagnostics

MAINT.LEVEL
(Maintenance Level)

These bits are used to determine the mode in which the DMB32
is to run. The bits have the following meaning:

(R/W, D)

<5:4>

to testa board that fails self-test.

<5>

<4>

0
0
1
1

0
1
0
1

Normal operation
Maintenance level 1
Maintenance level 2
Reserved

In maintenance level 1, the Node window address space can be
used to access the privileged registers contained on the board,
and the host can directly access the CASRAM which is used to
hold the registers and FIFOs.
In maintenance level 2, the features at maintenance level 1 are
still available, but in addition the DMB32’s microprocessor is
disabled. This allows the host to interrogate the microprocessor
bus.

<8> -

SYNC

(Sync Line Present)
(R, B)

This bit is set to indicate that an adapter cable or loopback

connector is installed on the sync line at the distribution panel.
This bit may be used by auto-configuration programs. If this bit
is not set then the sync CSRs do not respond when they are
addressed. This bit may be clear if certain self-test functions on
the sync channels do not work.

<9>

ASYNC
(Async Lines Present)
(R, B)

This bit is set to indicate that the async channels are configured
on the DMB32. This bit may be used by auto-configuration
programs. If this bit is not set then the async CSRs do not
respond when they are addressed. This bit may be clear if
certain self-test functions on the async channels do not work.

<10>

PRINT
(Printer Present)
(R, B)

This bit is set to indicate that a suitable printer cable is
connected to the the distribution panel. This bit may be used by
auto-configuration programs. If this bit is not set then the

printer CSRs do not respond when they are addressed. This bit
may be clear if certain self-test functions on the printer
interface do not work.

<l1>

DIAG.FAIL

(Diagnostic Error)

(R, B)

If this bit remains set after PROGRAMMED.RESET has
cleared then the self-test diagnostic has failed.

Bit

Name

Description

<13>

CABLE.KEY

This bit is set to indicate that the self-test has detected the

<31:14>

3.3.11

(Electrical Cable Key
Signal Present)
(R, B)

presence of the electrical-cable-key signal. This signal verifies
that all six internal ribbon cables (17-00740-xx) are correctly
connected between the module and the the distribution panel.
This bit can be updated without a Reset occurring.

Not Used

These bits are reserved to DIGITAL.

Async Control And Status Register (ACSR)

ACSR (BASE + 104)

30 29

26 25

08 07

AR L

TxIE

04 03

Y W W A L e

Qfiifi%o
RxIE
REGT

Bit

Name

Description

<7:.0>

ASYNC.IND.ADD
(Indirect Address Register

This byte should contain the channel number when accessing

Pointer)

(R/W, B)

the following registers:

LNCTRL,
FLOWC.

TBUFFAD,

LPR,

FIFOSIZE,

TBUFFCT,

FIFODATA.,

PREEMPT,

LSTAT,

Each of these registers controls a single channel. An access to
any of them is indexed internally by the value of this field to
~access the register for the particular channel.
<8>

<9>

RX.ILE

When set, this bit allows the DMB32 to interrupt the CPU at

(Receive Interrupt
Enable)
(R/W, B)

the async interrupt vector when DATA.VALID (RBUF<31>)
is set. Receive interrupts may be delayed by using the
RX.TIMER, so that several characters can be processed during
one interrupt.
U

TX.ILE
(Transmit Interrupt
Enable)

When set, this bit allows mterrupts to occur at the async
interrupt vector when TX.ACTis set.

(R/W, B)

3-16

3.3.12

Sync Control And Status Register (SCSR)

SCSR (BASE + 108)

30 29 28 27

26 25 24

23 22 21 20

| |

10 09

08 07

06 05

04 03

02 01

R PR
RV i [y
b

SYNC.
IND.ADD

SYNC.LE
RESH

Bit

Name

Description

<7.0>

SYNC.IND.ADD

This byte defines the sync channel number when accéssing the

(Indirect Address Register
Pointer)
(R/W, B)

following registers: TBUFFAD1, TBUFFCT1, RBUFFADI,
RBUFFCT1, TLNCTRL1, RLNCTRLI1, LPR1, LPR2,
LPR3, BUFCTRL, TBUFFAD2, TBUFFCT2, RBUFFAD?2,
RBUFFCT2, TLNCTRLI1, RLNCTRL2.

Although the DMB32 has only one sync channel, and this byte
is ignored, it is reccommended that the driver use this register as
if multiple sync channels are supported.

<11>

SYNC.LE
(R/W, B)

3.3.13

When set, this bit allows the DMB32 to interrupt the CPU at
the sync interrupt vector.

(Sync Interrupt Enable)

Printer Control And Status Register (PCSR)

+ 10C)
PCSR (BASE
31

30 29 28 27 26 25 24

23 22 21 20

13 12

R|R|R

PROFFLINE | PR.DAVFU.

PFJLE

READY

10 09

08 07 06 05 04 03 02 01

PR.CONNECT
VERIFY

Bit

Name

Description

<l1>

PR.LLE
(Printer Interrupt Vector)

When set, this bit allows the DMB32 to interrupt the CPU at
the printer interrupt vector.

(R/W, B)
<16>

PR.DAVFU.READY

This bit indicates the state of the DAVFU Ready control line

(R, B)

DAVFU characters.

(DAVFU Ready)

from the printer. When set the printer is ready to receive

3-17

Bit

Name

<17>

Description

PR.CONNECT.
READY
(Connect Verify)
(R, B)

<18>

This bit indicates the state of the Connect Verify control line
from the printer. When set a printer is connected to the printer
port.

PR.OFFLINE
(Line Printer Error)

This bit indicates the state of the Error control line from the
printer. When set it indicates the printer is offline.

(R, B)
3.3.14

Device Configuration Register (CONFIG)

CONFIG (BASE + 114)

30 29

27 26 25

10 09

08 07

06 05

04 03

02 01

R|{R|R|R|R|R|[R|R|R|R|R|R|R|R|[R|R|R|R[R|R|R|R|R]|R

)

PRINTER.
LINES

’

" svie

LINES

’

ASYNC.
LINES

Bit

Name

Description

<7:0>

ASYNC.LINES

This byte normally contains the value 08¢, the number of
async channels supported by the DMB32. If the async channels

(Number of Async Lines)
(R, B)

<15:8>

<23:16>

are not configured (for example, self-test has falled) then this
byte will read as zero.
|

SYNC.LINES
(Number of Sync Lines)
(R, B)
|

This byte normally contains the value 01 ¢, the number of sync
channels supported by the DMB32. If there is no adapter cable
connected, or if self-test has detected a hardware fault on the
sync channel, then this byte will read as zero.

PRINTER.LINES

This byte normally contains the value 01, the number of

(Number of Printer Ports)

(R, B)

printer ports supported by the DMB32. If no printer cable is
connected to the distribution panel, or if self-test has detected a
hardware fault in the printer port, then this byte will read as
Zero.

3-18

3.3.15 Second Async Control And Status Register (ACSR2)
ACSR2 (BASE + 118)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 O1 00

[P v

Rx. TIMER

ASYNC.
RESET
RET2Y

Bit

Name

Description

<10>

ASYNC.RESET

The host may set this bit to request a reset of the async
channels. When the bit is set, the DMB32 will abort all async
DMA operations and initialize all the async channels. When it
has finished, it will clear the bit. After setting this bit, the host
must not alter any registers associated with the async channels
until this bit has been cleared. This process will not take longer
than 10 ms. During the reset operation, activity on other
channels may be affected (for example, overrun or underrun
conditions may occur on the sync channels or the printer
operation may be delayed). When the operation completes there

(Async Port Reset)

(R/W, C)

will be no entries in RBUF or TBUF.

<23:16>

RX. TIMER

(Receive Interrupt Delay
Timer)

(R/W, C)

This byte is used to delay a receive interrupt. This allows data
to accumulate in the FIFO, and thus places less overhead on the
host interrupt service routines. The delay may be selected from
a number of values as indicated below. If the FIFO becomes so
full that an XOFF code would be generated, then the delay is
canceled and the interrupt signaled immediately. If the host
empties the receive FIFO before the interrupt is signaled then
the interrupt may or may not be requested. Any modem statuschange entry causes an immediate interrupt, and any
outstanding delay is canceled.
Values for the timer:

An infinite delay is used. A receive interrupt

No delay is used. The interrupt is delivered as

2 to 255

Time in milliseconds.

will only be given if the FIFO gets 3/4 full or a
modem status change entry is put in the FIFO.
soon as possible.

3-19

3.3.16

Second Sync Control And Status Register (SCSR2)
",

SCSR2 (BASE +11C)

30 29

10 09

08 07

04 03

HEERRREERT
SYNC
RESET

Bit

Name

<10>

Description

SYNC.RESET
(Sync Port Reset)
(R/W)
-

This bit may be set by the host to request a reset of the sync

channel. When this bit is set, the DMB32 will abort sync DMA
operations and initialize the sync channel. When it has finished,
it will clear this bit. Once the host has set this bit it must not
alter any registers associated with the sync channel until the bit
has been cleared. This process will not take longer than 10 ms.

During the reset operation, activity on other channels may be

affected (for example, overrun or underrun conditions may
occur on the async channels or the printer operation may be
delayed). When this operation completes there will be no entries
in SBUF.
3.3.17

Second Printer Control And Status Register (PCSR2)

PCSR2 (BASE + 120)
31

30 29

26 25

10 09

ENREEENRENENENEREREED

08 07

06 05

04 03

PRINTER
RESET
RE102

3-20

Bit

Name

Description

<10>

PRINTER.RESET

This bit may be set by the host to request a reset of the printer
port. When this bit is set, the DMB32 will abort DMA
operations and initialize the printer port. When it has finished,
it will clear this bit. Once the host has set this bit it must not
alter any registers associated with the printer port until the bit
has been cleared. This will not take longer than 10 ms. During
the reset operation, activity on other channels may be affected
(for example, overrun or underrun conditions may occur on the
sync or async channels).

(Printer Port Reset)

(R/W)

3.3.18

System Page Table Register (SPTE)

SPTE (BASE
+ 150)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11

10 09 08 07 06 05 04 03 02 01 00

[leflcvl% R [P P

e e e e i PP i P e

i i [ [ i PP v [
A

SPTE
RE103

Bit

Name

Description

<31:0>

SPTE

This register is loaded with the physical address of the system
page table. It is shared between all ports on the DMB32. It is
recommended that each driver for each port load this register so
that it will be valid whatever combination of ports are in use.
The host should set PTE.VALID (MAINT<2>) only after
loading the page table registers (this register together with
SPTS, GPTE, and GPTS); if PTE.VALID is not set the
contents of this register are not valid.

(System Page Table
Register)

(R/W)

3.3.19

System Page Table Size Register (SPTS)

+ 154)
SPTS (BASE

30 29 28 27 26 25 24 23 22 21 20 19

18 17

13 12

10 09

08 07 06 05 04 03 02 01

M@Mml%l%l%l%l%lflfwl%l%l%lwwlmI%]Rcvl%l% A A A A A A A e A A
J

SPTS
RE104

3-21

Bit

Name

<31:0>

SPTS

Description

(System Pagé Table Size)
(R/W)

3.3.20

This register is loaded with the number of entries in the system
page table. It is shared between all ports on the DMB32. It is
recommended that each driver for each port load this register so
that it will be valid whatever combination of ports are in use.
The host should set PTE.VALID (MAINT<2>) only after
~ loading the page table registers (this register together with
SPTE, GPTE, and GPTS); if PTE.VALID is not set the
contents of this register are not valid.

Global Page Table Register (GPTE)

GPTE (BASE
+ 158)

30 29

10 09

08 07

04 03

R L
e e o o o M A o O O A
k

GPTE

Bit
<31:0>

’

Name

Description

GPTE

This register is loaded with the system virtual address of the

(Global Page Table

global page table. It is shared between all ports on the DMB32.

It is recommended that each driver for each port load this

(R/W)

register so that it will be valid whatever combination of ports
- are in use. The host should set PTE.VALID (MAINT<2>) only

after loading the page table registers (this register together with
SPTE, SPTS, and GPTS); if PTE.VALID is not set the
contents of this register are not valid.
3.3.21

Global Page Table Size Register (GPTS)

GPTS (PAGE + 15C)

30 29

R/
w

a7 R [Rev R

[P R [ "W

R/
W

[P o

i X

08 07

[ P | P

04 03

[

P P

AN
Y

GPTS
RE108

3-22

Bit

Name

Description

<31:0>

GPTS
(Global Page Table Size)
(R/W)

This register is loaded with the number of entries in the global
page table. It is shared between all ports on the DMB32. It is
recommended that each driver for each port load this register so
that it will be valid whatever combination of ports are in use.
The host should set PTE.VALID (MAINT<2>) only after
loading the page table registers (this register together with
SPTE, SPTS, and GPTE); if PTE.VALID is not set the
contents of this register are not valid.

3.3.22

Printer Prefix/Suffix Control Register (PFIX)

PFIX (BASE + 160)

30 29 28 27 26 25 24 23 22 21 20 19

18 17

13 12 11

= 4

A L LA L A L L L L v L L0 v A L A L L

{

SUFFIX.

~ CHAR

SUFFIX.

COUNT

10 09 08 07 06 05 04 03 02 01

A v ) LAY W A L LV i Y W Y

PREFIX.

CHAR

PREFIX.

COUNT

’

Bit

Name

Description

<7:0>

PREFIX.COUNT

Cleared by initialization.

(R/W)

This byte is loaded by the host with the number of prefix
characters to be inserted at the beginning of the buffer.

PREFIX.CHAR
(Prefix Character)

Cleared by initialization.

<15:8>
|

(Prefix Count)

(R/W)

This byte is loaded by the host with the type of prefix character
to be inserted at the beginning of the buffer. If the prefix
character count is zero then no prefix characters are sent.

A zero value for this prefix character is interpreted as a “‘new
line” character. A “new line”’ character is a carriage return
followed by a line feed. The carriage return precedes the line
feed only if the automatic carriage return insert bit
(PR.AUTO.RETURN) is 1.
<23:16>

SUFFIX.COUNT
(Suffix Count)

(R/W)

Cleared by initialization.

This byte is loaded by the host with the number of suffix
characters to be inserted at the end of the buffer.

3-23

Bit

Name

<31:24>

SUFFIX.CHAR

Description
Cleared by initialization.

(Suffix Character)
(R/W)

This byte is loaded by the host with the type of suffix character
to be inserted at the end of the buffer. If the suffix character
count is zero then no suffix characters are sent.
A zero value for this suffix character is interpreted as a “new
line” character. A “new line” character is a carriage return
followed by a line feed. The carriage return precedes the line
feed only if the automatic carriage return insert bit
(PR.AUTO.RETURN) is 1.

3.3.23

Printer Buffer Address Register (PBUFFAD)

PBUFFAD (BASE + 164)

30 29

MW R

08 07

04 03

02 01

A s S A A A A AL
o

PBUFFAD

Bit

Name

<31:0>

PBUFFAD

Description
-

(Printer Buffer Address)
(R/W)

Cleared by initialization.

This longword is loaded by the host with the start address of the
buffer to be sent by DMA transfer.
This register must not be written to between setting
TX.DMA .START and the respective interrupt being returned.
During this period, the contents of the register are undefined.

The interpretation of this address is controlled by the DMA
register.

3.3.24 Printer Buffer C(junt Register (PBUFFCT)
PBUFFCT (BASE + 168)

30 29

ool

08 07

04 03

tafafaPolfta] [ [ [ [ ] [ FefuRePofolafaale

PR.CHAR.CT

PR. BUFF OFF
RE109

3-24

Bit

Name

Description

<8:0>

PR.BUFF.OFF
(Printer Buffer Offset)

These bits contain the offset of the first character of the buffer
within the first page containing the buffer. This is only used

PR.CHAR.CT

Cleared by initialization.

(R/W)

This word defines the length of the Transmit DMA buffer. It is
initially loaded by the host and is updated by the DMB32 on
termination of a transfer so that it contains the number of
characters still to be sent. The number of characters is specified

when PR.DMA PTE is set.

(R/W)

<31:16>

(Transmit DMA
Character Count)

as a 16-bit unsigned integer.

This register must not be written to between setting
PR.DMA.START and the respective interrupt being returned.
During this period, the contents of this register are undefined.
3.3.25

Printer Control Register (PCTRL)

PCTRL (BASE + 16C)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

R P R RRG P P P R ]

R R [P P

Pfl.l PR. F’FLl PR. l

WRAP

NON.

AUTO.

RETURN

PR. EVRQR

PR. l

FORMAT
|
|
PR.

DMA

TAB

ABORT

Bit

Name

Description

<0>

PR.DMA.START
(Start a DMA Transfer)

Cleared by initialization.

(R/W)

RalRal | ] 1 Rl

L PR! PF&!,

DMA
DMA.
PHYS | START
PR.
o

DMA.
PTE

This bit is set by the host to start a printer port DMA transfer.

‘Having set this bit, the host must not write to PBUFFCT or
PBUFFAD until the interrupt has been received to say that this
transfer has finished. This bit will be reset before the interrupt
is returned.

3-25

Bit

<1>

Name

Description :

PR.DMA.PTE
(PTE Address)
(R/W)

Cleared by initialization.
|

This bitis set by the host to mdncate that the DMA addressis
the address of the first PTE for the buffer.
|

If the bit is clear, the DMB32 assumes that the address is the
address of the first byte of the buffer.
If the bit is set, the DMB32 assumes that the address is the
address of a PTE which describes the page which contains the
first byte of the buffer. This address must be longword aligned.
The offset of the first byte is contained in PR.BUFF.OFF.

This bit may not be modified by the host while a DMA is in
progress.
<2>

PR.DMA.PHYS

Cleared by initialization.

(Physical Address)
(R/W)

”
This bit is set by the host to indicate that the DMA address is a
physical address. If this bit is clear, the DMB32 assumes the
addrcss1s a system virtual address.

- This bit may not be mod1fled by the host whlle a DMAis in
progress.

<8>

PR.DMA.ABORT
(Abort a DMA Transfer)
(R/W)

<9>

PR.FORMAT
(Format Control)
(R/W)

Cleared by initialization.

SRR
|
This bit is set by the host to abort a DMA transfer. The host
may set it at any time. If this bit is set while a print operation is
in progress the DMB32 will abort the operation and generate an
interrupt. (It may not be possible to determine at what point the
operation was aborted; for example, if prefix or suffix
characters were bemg transmitted when the abort was
detected).
|

Cleared by Master Reset.
|
|
If this bit is set, the DMB32 examines the characters being

transferred from the DMA buffer to the printer. Characters
may be acted upon as indicated by the formatting control bits.
If this bit is clear, all characters are transferred without being
examined. The DMB32 is unable to keep track of the carriage
position, and the PR.AUTO.RETURN, PR. AUTO.FORM,
PR.NON.PRINT, PR.DAVFU, PR.WRAP, PR.UPPER,
PR.TAB and PR.TRUNC bits have no effect.

3-26

Bit

<23:16>

Name

Description

PR.ERROR

Cleared by initialization.

(Error Code)

(R/W)

If it contains a value other than zero, this field indicates that

errors were detected during a DMA operation.

Error codes are described in Section 3.4.8.
<24>

PR.TAB
(Tab Expansion)

(R/W)

Cleared by initialization.

If this bit is set the DMB32 will convert any TAB characters to
the appropriate number of spaces while formatting output data.
Tabs are set every eighth character position.

<25>

<26>

PR.TRUNC

Cleared by initialization.

(R/W)

When this bit is set the DMB32 will truncate overlong lines

PR.AUTO.RETURN
(Auto Carriage Return

Cleared by initialization.

(Truncation of Data)

Insert)
(R/W)

while formatting output data.

If this bit is set, the DMB32 will insert carriage returns before
any form feed or line feed in the data stream that is not
preceded by a carriage return. It will also strip out any
redundant carriage returns.

<27>

PR.AUTO.FORM

(Auto Form Feed to Line

Feed Convert)
(R/W)

Cleared by initialization.

If this bit is set the DMB32 will convert a form feed to the
appropriate number of line feeds in order to position the paper
to the top of the form. The page size is specified in PR. The

DMB32 assumes that the paper is positioned at top-of-form
when the printer port is initialized.

<28>

PR.NON.PRINT
(Non-Printing Character

Accept)
(R/W)

Cleared by initialization.

This bit allows non-printing characters to be included in the
data stream. Non-printing characters are those with the MSB
set, and also unknown control codes.

If formatting is enabled and this bit is clear, then non-printing
characters are discarded.

If formatting is enabled and this bit is set, then these characters
are sent to the printer. Unknown control codes are assumed to
have no effect on the carriage position. Other non-printing
are assumed tc take one print position.
characters

3-27

Bit
<29>

Name

Description

PR.DAVFU

Cleared by initialization.

(DAVFU)
(R/W)

<30>

This bit allows DAVFU control codes (2005 to 237g) to be
transferred to the printer. The DMB32 keeps track of the
carriage position as it is affected by these codes. If this bit is not
set then these codes are considered non-printing codes and are
dealt with as indicated by the PR.NON.PRINT bit.

PR.WRAP

Cleared by initialization.

(Line Wrap)
(R/W)

If this bit is set, a new-line sequence is sent to the printer if the
current character would be printed at a position beyond the end
of the line, as indicated by the line size in PR.WIDTH.

If this bit is clear, the rest of the line will either be sent to the

printer or truncated, as specified by the PR.TRUNC bit.
<31>

PR.UPPER

Cleared by initialization.

(Convert to Upper Case)
(R/W)
-

|
»
This bit causes the DMB32 to translate all lower-case characters
to the corresponding upper-case character (this includes some

non-alphabetic characters that do not appear on upper-case-only
printers).

3.3.26

Printer Carriage Counter Register (PCAR)

PCAR (BASE + 170)
31

30 29

10 09

08 07

04 03

‘
/ R/
S/
/
R/ i
7
P
¢
lR/W]R/WlR/WlR/W[% I% MIR/WI% lfi/wlfl/w
RGo Ry IROIRG, R/WlflfW; l&Wl
ARG
R
W[R/W R,
R/W!R/WIR/W]R/W[%
IR/W% R,
L

PR.CHAR

PR.LINE
RE111

Bit
<15:0>

Name

Description

PR.LINE

Cleared by initialization.

(Lines Printed)

(R/W)

This word contains the number of lines of paper that have been
~used during the previous DMA (that is, the number of line feed
characters and the number of line feeds that a form feed would
have been converted to). It is only valid when
PR.DMA.START is zero. It is not valid if DAVFU is set, or if
formatting is not enabled.

3-28

Bit
<31:16>

Name

Description

PR.CHAR

Cleared by initialization.

(Characters Transmitted)

(R/W)

3.3.27

This word indicates the number of characters transferred to the

line printer during the previous DMA operation. This includes
all prefix and suffix characters and all inserted characters. It is
only valid when PR.DMA.START is zero.

Printer Page Size Descriptor Register (PSIZE)

PSIZE (BASE + 174)

30 29 28 27 26 25 24 23 22 21 20 19

PP
PR.PAGE

R
k

18 17

P o P vP

16 15 14 13 12 11

o vi P

o i e P i

o iR

PRWIDTH

Bit

Name

Description

<15:0>

PR.WIDTH
(Line Width)
(R/W)

Cleared by initialization.

PR
(Page Size)
(R/W)

Cleared by initialization.

<31:16>

10 09 08 07 06 05 04 03 02 01 00

’

This word contains the number of printing positions on a line.
Zero indicates no limit to the number of printing positions. It is
used to determine when a new-line should be inserted when
auto-wrap operation is selected.

This word contains -the number of lines which may be printed
on a page. It is used when converting form feeds to line feeds
and when accounting for the number of lines used during a
DMA.

3.3.28

Sync Transmit Buffer 1 Address Register (TBUFFADI1)

TBUFAD1 (BASE + 180 (MODIFIED BY SYNC.IND.ADD))

30 29 28 27 26 25 24 23 22 21 20 19

R e

18 17

16 15

13 12 11

10 09 08 07 06 05 04 03 02 01

e PP i i i o P P P P o P P i e [ i iR i ]
~

TBUFFAD1
RE114

3-29

Bit

Name

Description

<31:0>

TBUFFADI

Cleared by initialization.

(Buffer Address)
(R/W)

This longword is loaded by the host with the start address of the

3.3.29

buffer to be sent on the sync channel by DMA transfer.

Sync Transmit Buffer 1 Count/Offset Register (TBUFFCT1)

TBUFFCT1 (BASE + 184 (MODIFIED BY SYNC.IND.ADD))

30 29

eI
k

Tx.CHXH.CT?

’

08 07

I A
)

06 05

04 03

2R R
Tx.BU;’F'OFF}

’

Bit

Name

Description

<8:0>

TX.BUFF.OFF1

These bits contain the offset of the first character of the buffer

(Transmit Buffer Offset)
(R/W)

within the first page containing the buffer. This is only used
when TX.DMA.PTE is set.

TX.CHAR.CT]I
(Transmit DMA

Cleared by initialization.

<31:16>

Character Count)
(R/W)

These bits define the length of the Transmit DMA buffer for
the selected channel. They are initially loaded by the host and
are updated by the DMB32 after a transfer so that they contain
the number of characters still to be sent. The number of
characters is specified as a 16-bit unsigned integer.

3.3.30 Sync Receive Buffer 1 Address Register (RBUFFAD1)
RBUFFAD1 (BASE + 188 (MODIFIEDBY SYNC.IND.ADD)}

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 156 14 13 12 11 10 09 08 07 OG 05 04 03 02 01 00

Te
YR e R R A R R R R A
N

RBUFFAD!1
RE116

3-30

Bit
<31:0>

Name

Description

RBUFFADI

Cleared by initialization.

(Buffer Address)

This longword is loaded by the host, with the start address of

(R/W)

the buffer to receive data from the sync channel by DMA
transfer.

3.3.31

Sync Receive Buffer 1 Count/Offset Register (RBUFFCT1)

RBUFFCT1 (BASE + 18C (MODIFIED BY SYNC.IND.ADD))

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11

10 09 08 07 06 05 04 03 02 O1 OO

FoJraralaFalafalafaFalfafalofalfalfal | 1 1 1 1 1

’

Rx.CHAR.CT1

el o ool

Rx.BUFF.OFF1

Bit

Name

Description

<8:0>

RX.BUFF.OFF1
(Receive Buffer Offset)

These bits contain the offset of the first character of the buffer
within the first page containing the buffer. This is only used
when TX.DMA.PTE is set.

RX.CHAR.CTI
(Receive DMA Character

Cleared by initialization.

(R/W)
<31:16>

- Count)
(R/W)

3.3.32

These bits define the length of the Receive DMA buffer for the
selected channel. They are initially loaded by the host and are

updated by the DMB32 after a transfer so that they contain the
number of characters actually received. The number of
characters is specified as a 16-bit unsigned integer.

Sync Transmit Buffer 1 Control Register (TLNCTRLI1)

TLNCTRL1 (BASE + 190 (MODIFIED BY SYNC.IND.ADD))

31 30 29 28 27 26 25 24 23 22 2120 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 O1 0O

R [P [ [P
‘

Pl R/[

Tx1.ERROR
g

Tx1.
DMA.
ABORT

R || R/v |

l | '

Tx1.
|Tx1.
|
PAR. |DMA
Tx1. PHYS Tx1
X21.

Tx1.
DMA.
START

DMA.
PTE
RE118

3-31

Bit

Name

Description

<0>

TX1.DMA.START
(Start a DMA Transfer)

Cleared by initialization.

(R/W)

This bit is set by the host to start a sync port DMA transfer
from buffer 1. Having set this bit, the host must not write to
TBUFFCT1 or TBUFFADI until this bit is cleared by the
DMB32 at the end of transmission.

TX1.DMA.PTE
(PTE Address)

Cleared by initialization.

(R/W)

This bit is set by the host to indicate that the DMA address is
the address of the first PTE for the buffer.

<]>

If this bitis clear, the DMB32 assumes that the addressis the
address of the first byte of the buffer.
If this bit is set, the DMB32 assumes that the address is the
address of a PTE describing the page containing the first byte
of the buffer. This address must be longword aligned and the
offset of the first byteis containedin TX1.BUFF.OFF.

This bit may not be modified by the host while a DMAis in
progress.

<2>

TX1.DMA.PHYS
(Physical Address)

Cleared by initialization.

(R/W)

This bit is set by the host to indicate that the DMA addressis a
physical address. If this bitis clear, the DMB32 assumes the the
addressis a system virtual address.

This bit may not be modified by the host while a DMA is in
progress.

<3>

TX1.X21

(R/W)
<4>

TX1.PAR

(R/W)
<8>

TX1.DMA.ABORT

(Transmit DMA Abort)

(R/W)

Reserved to DIGITAL.

Cleared by initialization.
This bit is set by the host, to abort transmission of data from
buffer 1 of the sync channel. On seeing this bit set, the DMB32
stops transmitting data on this channel. If a DMA was in
progress, it updates the DMA address/count registers and
generates an interrupt.

This bit should be clear before a transferis started otherwise the
new transfer will be aborted without transmitting any
characters.

3-32

Bit

Name

Description

<23:16>

TX1.ERROR

Cleared by initialization.

(R/W)

If this byte contains a value other than zero, this indicates that
errors were detected during an operation on the transmitter.

(Transmitter Error Bits)

Error codes are described in Section 3.4.8.

3.3.33

Sync Receive Buffer 1 Control Register (RLNCTRL1)

RLNCTRL1 (BASE + 194 (MODIFIED BY SYNC.IND.ADD))

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

ROV | v | v v [P | P [

Rx1.ERROR

’

Rx.
DMA.
ABORT1

Rév (v [Rv|
v
-

Rx1.
DMA,
Rx1. PHYS gy1.
X21

Rx1.
DMA.
START

DMA.
PTE

Bit
<0>

Name

Description

RX1.DMA.START

Cleared by initialization.

(Start a DMA Transfer)

<l>

(R/W)

This bit is set by the host to start a sync port DMA transfer to

RX1.DMA.PTE
(PTE Address)

Cleared by initialization.

(R/W)

buffer 1. Having set this bit, the host must not write to
RBUFFCT1 or RBUFFADI1 until this bit is cleared by the
DMB32 at the end of transmission.

This bit is set by the host to indicate that the DMA address is
the address of the first PTE for the buffer.

If this bit is clear, the DMB32 assumes that the address is the
address of the first byte of the buffer.
If this bit is set, the DMB32 assumes that the address is the
address of a PTE which describes the page which contains the
first byte of the buffer. This address must be longword aligned.
The offset of the first byte is contained in RX1.BUFF.OFF.
This bit may not be modified by the host while a DMA is in
progress.

3-33

Bit

Name

Description

<2>

RX1.DMA.PHYS
(Physical Address)

Cleared by initialization.

(R/W)

This bit is set by the host to indicate that the DMA address is a
physical address. If this bit is clear, the DMB32 assumes the the
address is a system virtual address.
|

This bit must not be modified by the host while a DMA is in
progress.

<3>

RX1.X21

Reserved to DIGITAL.

(R/W)
<8>

RX.DMA.ABORT1

- Cleared by initialization.

(Receiver DMA Abort)

(R/W)

This bit is set by the host, to abort reception of data to buffer 1
of the sync channel. On seeing this bit set, the DMB32 stops
receiving data on this channel. If a DMA was in progress it
updates the DMA address/count registers and generates an
interrupt.
This bit should be clear before a transfer is started otherwise the
new transfer will be aborted without receiving any characters.

<23:16>

RX1.ERROR
(Receiver Error
Bits)

(R/W)

Cleared by initialization.
If this byte contains any value other than zero, this field
indicates that errors were detected during an operation on the
receiver.
Error codes are described in Section 3.4.8.

3-34

3.3.34

Sync Line Parameters Register 1 (LPR1)

LPR1 (BASE + 198 (MODIFIED BY SYNC.IND.ADD))

31 30 29 28 27 26 25 24 23 22 2120 19 18 17 16 15 14 13 12 11

i
LINE.
RESET

i S R A R T

NUMBER,

SYNC

V35.
MODEM
SUPPRESS |SELECT
V10.

SELECT

LOOP

10 09 08 07 06 05 04 03 02 01 OO

eaup
RATE

Rx.
CLOCK
CONTROL [PRIMARY
CODING.

TYPE

X21.

Rx.
ENABLE

ENABLE MATCH
ENA

Bit

Name

Description

<0>

RX.ENABLE

When set, this bit enables processing of the receiver serial input

(Receiver Enable)

data.

(R/W)

<2>

RX.MATCH.ENA

(Receive Match Character

This bit is used‘by the GEN BYTE protocol. It enables the
matching of characters using the MATCH character.

Enable)

(R/W)
<3>

<4>

RX.PRIMARY
(Primary/Secondary
Station)

This bit controls whether the device acts as a primary station or
as a secondary station. When set the DMB32 acts as a

(R/W)

secondary station, when clear as a primary station.
|

X21.ENABLE

Reserved to DIGITAL.

(R/W)
<6>

CLOCK.CONTROL
(Clock Control Bits)
(R/W)

When this bit is set, it indicates that the internal clock should be
used, rather than the DTE clock from the interface. This would
normally be used for internal loop.

<7>

CODING.TYPE
(Data Coding Type)
(R/W)

If this bit is set then the data transmitted and received will be
encoded using NRZI encoding. If this bit is clear then the data
will be transmitted and received normally.

3-35

Bit

Name

Description

<11:8>

BAUD.RATE<3:0>
(Internal Baud Rate
Generator)

This field selects the speed of the internal baud rate generator.
(The baud rate clock is passed to the DTE clock signal of the

(R/W)

indicates that the internal clock should be used). Possible values

sync connector. It is also used when the clock control bit

are:

01 2 3 4 —

600
1200

1800
2000

2400
5 - 4800
6 - 9600
7 - 19200
8 — 48000
9 - 56000
10 - 64000
11 - reserved
12 - reserved

13 - reserved
14 — no clock (DTE clock off)
15 — maximum sensible speed

‘Maximum sensible speed’ is the highest speed that the device
- supports for the selected protocol. These speeds are given in the
following table (speeds are given in bits/s).

Electrical Interface Standard

<12>

<]3>

Protocol

RS-232

RS-423

RS-422

V.35

DDCMP

19200

HDLC

19200

64000

48000

BISYNC

9600

GEN BYTE

9600

LOOP
|
(Maintenance Loopback)

Cleared by master reset.

(R/W)

This bit controls the internal loopback of the sync channel. If it
is set then data is internally looped back.

V35.SELECT
(V.35 Select)

This bit is used by the host when some maintenance mode
connectors are being used. When the bit is set, the DMB32 uses

(R/W)

the V.35 receivers instead of the V.11 receivers. This bit is only
used for maintenance; in normal use the type of sync cable
connected will select the appropriate receivers.

3-36

Bit

Name

Description

<14>

V10.SELECT
(V.10 Select)

This bit is used by the host when some maintenance mode
connectors are being used. When this bit is set, the DMB32 uses
the V.10 receivers instead of the V.11 receivers. This bit is only
used for maintenance; in normal use the type of sync cable
connected will select the appropriate receivers.

(R/W)

MODEM.SUPPRESS
FIFO
Modem
(Inhibit
Entries)

<15>

‘This bit is set by the host to suppress the normal action of
putting modem status change entries into the FIFO.

(R/W)
This field indicates the number of sync characters that should
be transmitted before a message. This field should normally be
set to 3 for BISYNC and 2 for DDCMP.

NUMBER.SYNC
(Number of Sync
Characters)

<23:16>

(R/W)

If this bit is set then the DMB32 will abort all DMA operwations

|
LINE.RESET
(Line Reset Request)

<31>

and initialize the channel. When it has finished, it will clear this
bit. Once the host has set this bit it must not alter any registers
~ associated with this channel until this bit has been cleared. This
will not take longer than 10 ms. During the reset operation
activity on other channels may be affected (for example,
overrun or underrun conditions may occur on other sync
channels and received characters may be lost on async
channels). If there are DMA operations in progress on the
channel then the FIFO entries for these may be present in
SBUF, or they may be lost.

(R/W)

Sync Line Parameters Register 2 (LPR2)

3.3.35

LPR2 (BASE + 19C (MODIFIED BY SYNC.IND.ADD))

30 29 28 27 26 25 24

R
MODEM.

| |

|[EBCDIC.

OVERRIDE |CODE

IDLE.
SYNC

Toie

Tx.BPc

23 22 21 20 19

18 17

13 12

10 09

08 07 06 05 04 03 02 01

TYPE

‘

DSR
,

~ Rl

STRIP.

SYNC

DCD

CTS

| SYNC.

Rx.CLOCK

SYNC.
Tx.CLOCK

L Pl
NN
|

RTS

DRS

ML2

ML1

DTR
RE122

3-37

Bit
<4:0>

Name

Description

(Modem Control Outputs)

These bits are used to directly control the modem status

(R/W)

outputs. Each bit corresponds to one control line as follows:

Bit

Control Line

—O

ML1 (Modem Loop (Local))
DTR (Data Terminal Ready)
DRS (Data Rate Select)
ML2 (Modem Loop (Remote))
RTS (Request To Send)

<]15:8>

(Modem Status Inputs)

(R)

‘These bits are used to monitor the received modem status input.
Each bit corresponds to one line as follows:
Bit

Status Line

8
9
10
11
12
13

Rx Clock running
Tx Clock running
TI (Test Indicator)
(Not used)
CTS (Clear To Send)
DCD (Data Carrier Detect)

14
15
<18:16>

<21:19>

PROTOCOL
(Protocol Type)

0 - DDCMP
1 - SDLC

(R/W)

2 - HDLC
3 - IBM BISYNC
4 — Spare
|
5 - Spare
6 — Spare
7 - GEN BYTE

ERROR.TYPE
(Error Control Type)

0 - CRC-CCITT preset to 1s
1 - CRC-CCITT preset to Os
2 - LRC/VRC odd

(R/W)

<24:22>

RI (Ring Indicator)
DSR (Data Set )

RX.BPC
(Number of Receive Bits
per Character)

(R/W)

3 - CRC-16
4 - LRC odd
5 —= LRC even
6 - LRC/VRC even
7 — no error control
0 - 8 bits

6 — 6 bits
7 — 7 bits

GEN BYTE only

The DMB32 does not support character sizes less than 6 bits per
character.

3-38

Bit

Name

Description

<27:25>

TX.BPC

0 - 8 bits

per Character)
(R/W)

GEN BYTE only
|
The DMB32 does not support character sizes less than 6 bits per

(Number of Transmit Bits

6 — 6 bits

7 - 7 bits

character.

<28>

<29>

STRIP.SYNC

This bit indicates whether sync characters should be stripped

EBCDIC.CODE

This bit indicates whether the character code used for IBM

(Character Code)
(R/W)

<30>

for the GEN BYTE protocol.

(Strip Sync)
(R/W)

BISYNC is EBCDIC (bit <29> set) or ASCII (bit <29> clear).

IDLE.SYNC
(Idle Sync)

This bit indicates whether the DMB32 should send sync
characters while idle (if set) or MARK (if clear).

MODEM.OVERRIDE
(Modem Control
Override)

If this bit is set, the DMB32 will ignore modem control signals.
If the bit is clear, the DMB32 will not allow transmission or
reception to proceed if the modem control bits are set

(R/W)

<31>

incorrectly (see Section 3.4.11).

3.3.36 Sync Transmit Buffer 2 Address Register (TBUFFAD?2)
TBUFAD2 (BASE + 1A0 (MODIFIED BY SYNC.IND.ADD))

31 30 29 28 27 26 25 24 23 22 2120 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

O N

Ae e e e i

)

i B i i

i e i

A A R e A T T AT

TBUFFAD2

Bit

Name

Description

<31:0>

TBUFFAD?2

Cleared by initialization.

(R/W)

This longword is loaded by the host with the start address of the

(Buffer Address)

buffer to be sent on the sync channel by DMA transfer.

3-39

3.3.37

Sync Transmit Buffer 2 Count/Offset Register (TBUFFCT2)

TBUFFCT2 (BASE + 1A4 (MODIFIED BY SYNC.IND.ADD))

30 29

08 07

04 03

TP
| Tl
T T T |
PPl

)

Tx.CHAR.CT2

’

T BUFF.OFF2

Bit

Name

Description

<8:0>

TX.BUFF.OFF2

These bits contain the offset of the first character of the buffer

(Transmit Buffer Offset)
(R/W)
<31:16>

TX.CHAR.CT?2

Cleared by initialization.

(Transmit DMA
Character Count)

(R/W)

3.3.38

within the first page containing the buffer. This is only used
when TX.DMA.PTE is set.

Sync Receive Buffer 2 Address Register (RBUFFAD2)

RBUFFAD2 (BASE + 1A8 (MODIFIED BY SYNC.IND.ADD))

30 29

RBUFFAD2

08 07

04 03

ee Y R eRR

’

Bit

Name

Description

<31:0>

RBUFFAD?2
(Buffer Address)
(R/W)

Cleared by initialization.
|
This longword is loaded by the host, with the start address of
the buffer to receive data from the sync channel by DMA
transfer.

3-40

3.3.39

Sync Receive Buffer 2 Count/Offset Register (RBUFFCT2)

RBUFFCT2 (BASE + 1AC (MODIFIED BY SYNC.IND.ADD})

30 29 28 27 26 25 24 23 22 21 20 19 18 17

P [ [

Rx.CHAR.CT2

’

Description

- Name

<8:0>

[ [P

Rx BUFF.OFF2

’

RX.BUFF.OFF2

These bits contain the offset of the first character of the buffer

(R/W)

when TX.DMA.PTE is set.

RX.CHAR.CT2
(Receive DMA Character

Cleared by initialization.
|

(Receive Buffer Offset)

<31:16>

10 08 08 07 06 05 04 03 02 01 00

R R R

Bit

16 15 14 13 12 11

Count)
(R/W)

within the first page containing the buffer. This is only used

These bits define the length of the Receive DMA buffer for the
selected channel. They are initially loaded by the host and are
updated by the DMB32 after a transfer so that they contain the

number of characters actually received. The number of
characters is specified as a 16-bit unsigned integer.

3.3.40

Sync Transmit Buffer 2 Control Register (TLNCTRL2)

TLNCTRL2 (BASE + 1B0O (MODIFIED BY SYNC.IND.ADD]})

30 29 28 27 26 25 24 23 22 21 20 19

[TTTTT

18 17

16 15 14 13 12 11

T elaralalalaParal [ [ [ 1]
‘

T2 BRROR

’

10 09 08 07 06 05 04 03 02 01 00

| I%lvl || PolaPe ol
|

Tx2.

PAR

Bit

<0>

Name

Tx2.

DMA.
PHYS

Tx2.

DMA
START

Description

TX2.DMA.START

Cleared by initialization.

(R/W)

This bit is set by the host to start a sync port DMA transfer

(Start a DMA Transfer)

from buffer 2. Having set this bit, the host must not write to
TBUFFCT2 or TBUFFAD2 until this bit is cleared by the
DMB32 at the end of transmission.

3-41

Bit

Name

Description

<l>

TX2.DMA.PTE

Cleared by initialization.

(PTE Address)
(R/W)

This bit is set by the host to indicate that the DMA address is
the address of the first PTE for the buffer.
If this bit is clear, the DMB32 assumes that the address is the
address of the first byte of the buffer.

If this bit is set, the DMB32 assumes that the address is the
address of a PTE which describes the page which contains the
first byte of the buffer. This address must be longword aligned
and the offset of the first byte is contained in TX2.BUFF.OFF.

~ This bit may not be modified by the host while a DMA is in
progress.

<2>

TX2.DMA.PHYS

Cleared by initialization.

(Physical Address)
(R/W)

This bit is set by the host to indicate that the DMA address is a

physical address.

If this bit is clear, the DMB32 assumes the the address is a
system virtual address.
This bit may not be modified by the host while a DMA is in
progress.

<3>

TX2.X21

Reserved to DIGITAL.

(R/W)
<4>

TX2.PAR

Reserved to DIGITAL.

(R/W)
<8>

TX2.DMA.ABORT

|
Cleared by initialization.

(Transmit DMA Abort)

(R/W)

This bit is set by the host, to abort transmission of data on
buffer 1 of the sync channel. On seeing this bit set, the DMB32
stops transmitting data on this channel. If a DMA was in
progress, it updates the DMA address/count registers and
generates an interrupt.
This bit should be clear before a transfer is started otherwise the

new transfer will
characters.

3-42

be aborted

without transmitting any

Bit

Name

Description

<23:16>

TX2.ERROR
(Transmitter Error Bits)

Cleared by initialization.

(R/W)

If this byte contains a value other than zero, this indicates that
errors were detected during an operation on the transmitter.
Error codes are described in Section 3.4.8.

3.3.41

Sync Receive Buffer 2 Control Register (RLNCTRL2)

RLNCTRL2 (BASE + 1B4 (MODIFIED BY SYNC.IND.ADD))

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11

LT T T

P oo
PP

Rx2.ERROR

10 09 08 07 06 05 04 03 02 01 0O

Ax.

R)j.?, RXLW

DMA. | DMA.
PHYS | START

DMA.
ABORTZ
Rx2.

X21

Rx1.

DMA,
PTE

Bit

Name

Description

<0>

RX2.DMA.START
(Start a DMA Transfer)

Cleared by initialization.

<1>

(R/W)

This bit is set by the host to start a sync port DMA transfer to

RX2.DMA.PTE

Cleared by initialization.

(PTE Address)

(R/W)

buffer 2. Having set this bit, the host must not write to
RBUFFCT!1 or RBUFFADI until this bit is cleared by the
DMB32 at the end of transmission.

This bit is set by the host to indicate that the DMA address is

the address of the first PTE for the buffer.

If this bit is clear, the DMB32 assumes that the address is the

address of the first byte of the buffer.

If this bit is set, the DMB32 assumes that the address is the
address of a PTE describing the page containing the first byte
of the buffer. This address must be longword aligned. The
offset of the first byte is contained in RX2.BUFF.OFF.
This bit may not be modified by the host while a DMA is in
progress.

3-43

Bit
<2>

Name

Description

RX2.DMA.PHYS

Cleared by initialization.

(Physical Address)
(R/W)

This bit is set by the host to indicate that the DMA address is a
physical address.
If this bit is clear, the DMB32 assumes the the address is a
system virtual address.

This bit must not be modified by the host while2 DMA is in
progress.

<3>

RX2.X21

Reserved to DIGITAL.

(R/W)
<8>

RX.DMA.ABORT?2

Cleared by initialization.

(Receiver DMA Abort)
(R/W)

|
This bit is set by the host, to abort reception of data on buffer 1
of the sync channel. On seeing this bit set, the DMB32 stops
receiving data on this channel. If a DMA was in progress it
updates the DMA address/count registers and generates an
interrupt.
This bit should be clear before a transfer is started otherwise the
new transfer will be aborted without receiving any characters.

<23:16>

RX2.ERROR

Cleared by initialization.

(Receiver Error Bits)

(R/W)

If this byte contains any value other than zero, this field
indicates that errors were detected during an operation on the
receiver.
Error codes are described in Section 3.4.8.

3.3.42

Syncr Line Parameters Register 3 (LPR3)

LPR3 (BASE + 1B8 (MODIFIED BY SYNC.IND.ADD))

[ ol
L

08 07

] v ] ] R i i P i PP P P o P [P P

ADDRESS?

FAN

ADDRESS

04 03

Rx. MATCH

P
J

SYNC.CHAR
RE129

3-44

Bit

Name

<7:0>

SYNC.CHAR

Description
This character is the sync character used by byte oriented

(Sync Character)

protocols.

(R/W)
<15:8>

RX.MATCH
(Receive Match
Character)

- This 1s the ‘match’ character used by the GEN BYTE protocol.

(R/W)
<23:16>

ADDRESSI

The first byte used in address matching.

(First Address Character)

(R/W)

<3 I:24>¢ - ADDRESS2

- The second byte used in address matching.

(Second Address
Character)

(R/W)
3.3.43

Sync Buffer Control Register (BUFCTRL)

BUFCTRL (BASE + 1BC (MODIFIED BY SYNC.IND.ADD))

30 29

26 25 24

10 09

08 07

06 05

04 03

02 01

lefel Jelelnfelefefafajefafefa] [ [ [ [ [ [ R [T TTTT I
|

SYNC. | SYNC.
X21
LOOP

SYNC.

CABLE

SYNC.

TEST.
INPUT

Rx.
BUFF.

PRIO

SYNC.
VALID

Tx.
BUFF.

PRIO

‘

Bit

Name

Description

<0>

TX.BUFF.PRIO

This bit controls which of the two buffers the device will use if

(Transmitter Buffer

both are valid for DMA when a message is transmitted. If this

Priority)

bit is clear then buffer 1 is used; if it is set then buffer 2 is used.

(R/W)

The host should set this bit before it sets up a DMA on buffer 1

and clear it before it sets up a DMA on buffer 2. This makes
sure that the ‘oldest’ buffer is always used when there is a
choice.

3-45

Bit

Name

Description

<8>

RX.BUFF.PRIO

This bit controls which of the two buffers the device will use if

(Receiver Buffer Priority)
(R/W)

both are valid for DMA at the start of a received message. If
this bit is clear then buffer 1 is used; if it is set then buffer 2 is
used. The host should set this bit before it sets up a DMA on
buffer 1 and clear it before it sets up a DMA on buffer 2. This
makes sure that the ‘oldest’ buffer is always used when there is
a choice.

<23:16>

SYNC.TEST. INPUT

(Test Inputs)

This byte is used during manufacturing testing only.

(R)
<27:24>

SYNC.CABLE

These bits indicate the type of adapter cable or loopback

(Cable Type)
(R)

connected at the distribution panel. Bit <27> is the MSB. The
meanings of the numerical values are:
0 - no cable present
1 — V.35 cable
2 — V.24 cable
3 - reserved
4 - V.36/RS-422 cable
o
5 - reserved
6 — reserved
7 — reserved
8 — reserved
9 — unbalanced loopback connector
10 - reserved
11 - reserved
12 - reserved

13 - reserved
14 — balanced loopback connector
15 - reserved

<29>

SYNC.LOOP
(Loopback Present)

(R)
<30>

SYNC.VALID
(Valid Cable)

This bit is used for manufacturing testing only.
|

|
This bit indicates that a valid cable is connected to the sync line
connector.

(R)
<31>

SYNC.X21

Reserved to DIGITAL.

(R)

3-46

Async Transmission Preempt Buffer (PREEMPT)

3.3.44

PREEMPT (BASE + 1CO (MODIFIED BY ASYNC.IND.ADD))

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11

R R R Y R RAY

PREEMPT.GO

Bit

<7:0>

10 09 08 07 06 05 04 03 02 01 00

PREEMPT.CHAR

Name

Description

PREEMPT.CHAR

This byte contains the character to be transmitted.

(Character to Transmit)

’

(R/W)
<15>

PREEMPT.GO
(Start Preempt)
(R/W)

This bit is set by the host when it loads the character to be
transmitted. It is cleared by the DMB32 when the character has
been read from the register. A TX action is also generated when
this bit is cleared.

Characters loaded into the register may be transmitted before
characters in the transmit FIFO or characters in a current
DMA operation.

3.3.45

Async Transmit Buffer Address Register (TBUFFAD)

TBUFFADD (BASE + 1C4 (MODIFIED BY ASYNC.IND.ADD))

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11

10 09 08 07 06 05 04 03 02 01 0O

MWWNNW%N%%NW%MM%MNWMM%%%M%WMN%%M
A

TBUFFAD

Bit

Name

Description

<31:0>

TBUFFAD

Cleared by initialization.

(Transmit Buffer
Address)

This longword is loaded by the host, with the start address of

(R/W)

the buffer to be sent by DMA transfer.

This register must not be written to between setting
TX.DMA.START and the respective TX.ACT being returned.
During this period, the contents of this register are undefined.

The interpretation of this address is controlled by
TX.DMA.PTE AND TX.DMA.PHYS.

3-47

3.3.46

Async Transmit Buffer Count/Offset Register (TBUFFCT)

TBUFFCT (BASE + 1C8 (MODIFIED BY ASYNC.IND.ADD))

30 29

08 07

04 03

oo
Pll falofalalalofal [ [ T [T ] FefoloFafalalalulol
Tx.C}:;R.CT

Tx.BUFF.OFF

’

Bit

Name

Description

<8:0>

TX.BUFF.OFF

These bits contain the offset of the first character of the buffer

(Transmit Buffer Offset)
(R/W)
<31:16>

within the first page contammg the buffer. This is only used
when TX.DMA.PTEis set.

TX.CHAR.CT

Cleared by initialization.

(Transmit DMA
Character Count)

These bits define the length of the Transmit DMA buffer for

(R/W)

the selected channel. They are initially loaded by the host and
are updated by the DMB32 after a transfer so that they contain
the number of characters still to be sent. The number of
characters is specified as a 16-bit unsigned integer.

This register must not be written to between setting
TX.DMA .START and the respective TX.ACT being returned.
During this period, the contents of this register are undefined.

3.3.47

Async Line Parameters Register (LPR)

LPR (BASE + 1CC (MODIFIED BY ASYNC.IND.ADD))

30 29

v o] v
60 P B P P
R/

Tx.

SPEED

Rx.

SPEED

]

OAUTO.|

USE

FLOW

CTS

08 07

04 03

P PP PP Palraliolia] | T T T%] T T

IR/

| EVEN
PARITY|

CHAR.

REPORT.

LENGTH

BREAK | Tx.INT.

|MODEM

IAUTO.

STOP

PARITY

DISCARD.

FLOW

CODE

ENABLE

FLOW

MAINT

RTS

DELAY

Rx.ENA

DTR

RE134

3-48

Bit

Name

Description

<l>

DTR
(Data Terminal Ready)
(R/W)

Cleared by initialization.

This bit controls the Data Terminal Ready signal (CCITT
Circuit Number 108). When the bit is set, the Data Terminal
Ready line goes to the ON state.

<4>

RTS

(Request to Send)

<9>

Cleared by initialization.

(R/W)

This bit controls the Request to Send signal (CCITT Circuit

TX.INT.DELAY
(Transmit Interrupt

Cleared by initialization.

Control)
(R/W)

When this bit is clear, the interrupt can take place when the
final character has been transferred from host memory. The
interrupt indicates that the host can release its buffers and start

Number 105). When the bit is set, the Request to Send line
goes to the ON state.

a new transfer. However, changes made to the line parameter
register after this interrupt may affect the last few characters of
the buffer.

When this bit is set the transmit interrupt for a DMA operation
will not take place until the final character has been
transmitted. The host can then change the line parameter
register (for example, change modem control) knowing that all
of the message has been transmitted.
<10>

RX.ENA
(Receiver Enable)

(R/W)

Cleared by initialization.
|

When this bit is set, the receiver for the selected line is enabled.
If RX.ENA is cleared while a character is being assembled, the
character is lost.

<l1>

'BREAK

Cleared by initialization.

(Break Control)

(R/W)

This bit forces the selected line to the Spacing state after the
current character has been sent. Transmission continues after
the break has been cleared.

3-49

Bit
<13:12>

Name

Description

MAINT

Cleared by initialization.

(Maintenance Mode)
(R/W)

|
|
|
These two maintenance bits have the following meaning:
00

Normal Operation

Automatic echo mode. Received data is
retransmitted (regardless of the state of TX.ENA) at
the same speed as the receiver. RX. ENA must be set
for this mode to work. Received characters are
placed in the receiver FIFO

Local loopback. The transmitter output is internally

connected to the receiver. Normal received data is

ignored and the transmitter data line is held at the
Marking state.
11

Remote Loopback. In this mode received data is
retransmitted at a clock rate equal to the received
clock rate. The data is not placed in the receiver

FIFO. The state of TX.ENA is ignored.
<14>

REPORT.MODEM

Cleared by initialization.

(Report Modem Changes)
(R/W)

When this bit is clear, Data Set change information is prevented
from being passed to the CPU via the received character FIFO,
but the line status register will continue to be updated with the
current Data Set status information. This allows these inputs to
be used for other control functions. When this bit is set Data
Set change information is passed normally.

<15>

DISCARD.FLOW

(Discard

Flow

Characters)

Cleared by initialization.

Control

(R/W)

When this bit is set received flow control characters (XON,
XOFF) will not be placed in the received-character FIFO
buffer. If OAUTO.FLOW is clear then this bit has no effect.

<17:16>

CHAR.LGTH

Set by initialization.

(Character Length)
(R/W)

|
These two bits define the character length, excluding the start,
stop, and parity bits as follows:
00 - 5 bits per character
01 - 6 bits per character
10 — 7 bits per character
11 — 8 bits per character

3-50

Bit

Name

Description

<18>

PARITY.ENAB
(Parity Enable)

Cleared by initialization.

(R/W)

When set, this bit causes a parity bit to be generated and added
on transmission, and checked and stripped on reception for the
selected line.

<19>

EVEN.PARITY
(Even Parity)

(R/W)

Cleared by initialization.

When PARITY.ENAB is set, this bit controls the sense of the
parity according to the following table:
0 — Odd parity
1 — Even Parity

<20>

STOP.CODE
(Stop Code)

(R/W)

Cleared by initialization.

This bit defines the length of the Stop Code at the end of the
character.

Clear

1 stop bit for 5-, 6-, 7- or 8-bit characters

Set

<21>

USE.CTS
(CTS Controls Output)

(R/W)

2 stop bits for 6-, 7-, or 8-bit characters; 1.5

stop bits for 5-bit characters.

Cleared by initialization.
When this bit is set, it indicates that a modem should be
connected to the port and that the DMB32 should obey the
CTS protocol. This is important when the card is sending a
DMA buffer without CPU intervention.

When the bit is clear, it indicates that a Data-Leads-only type
terminal is connected to the port and transmission is to take
place irrespective of the state of CTS.

3-51

Bit

Name

Description

<22>

IAUTO.FLOW
(Automatic Flow Control
of Incoming Data)

Cleared by initialization.

(R/W)

by requesting lines that are sending characters to stop
transmitting. When the Received Character FIFO becomes
critically full, the DMB32 will send an XOFF to each line that
sends it a character. Thereafter it will send an XOFF to a line in
reply to every alternate character received. When the
congestion has been removed by the host taking characters
from the received character FIFO, an XON will be sent to
those lines that have been sent one or more XOFFs. If this bit is
clear, NO characters will be sent to this line other than those
written to it by the host.

When set, this bit allows the DMB32 to stop internal congestion

Either the DMB32 or the CPU can send flow control characters
to any one channel, but not both together. Unpredictable results
will occur if the CPU tries to send flow control characters
during any time when the DMB32 has been enabled to send
flow control characters. However, the CPU can force the
DMB32 to send an XOFF or XON by using the SNDOFF bit.
<23>

OAUTO.FLOW
(Automatic Flow Control
of Outgoing Data)

(R/W)

Cleared by initialization.
This bit enables the DMB32 to respond automatically to
received XON/XOFF characters. When set, this bit causes the
DMB32 to update the TX.ENA bit in LNCTRL after receiving
flow control characters. A received XOFF causes TX.ENA to

be reset and a received XON causes it to be set.
The host may also write to TX.ENA while incoming flow
control is enabled (for example, to override an XOFF), but care
must be taken not to lose any incoming XON characters. The
DMB32 may write to the TX.ENA bit for up to 20
microseconds after OAUTO has been cleared by the host.
The XONs and XOFFs will still be passed to the host when this
feature is enabled. This allows the host to keep track of the line
state.

3-52

Bit

Name

Description

<27:24>

RX.SPEED
(Receive Data Rate)

This field is set to 1101 (9600 bits/s) by initialization.

(R/W)

These four bits select the async receiver line speed on a line-byline basis, as specified in the following table.

Data Rate

Max Error

Value

(bit/s)

(%)

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101

50
75
110
134.5
150
300
600
1200
1800
2000
2400
4800
7200
9600
19200

1110
1111
<31:28>

TX.SPEED

38400

0.01
0.01
0.08
0.07
0.01
0.01
0.01
0.01
0.01
0.19
0.01
0.01
0.01
0.01
0.01
0.01

Group
A

A
A
A
A
A

A
A
A
A

B
and B
and B
B
and B
and B
and B
B
B
and B
and B
and B
B

This field is set to 1101 (9600 bits/s) by initialization.

(Transmit Data Rate)

(R/W)

These four bits select the async transmitter line speed according
to the same table as given for RX.SPEED.
When selecting split-speed operation the transmit and receive
speeds of both channels sharing a DUART must be contained
in the same group (A or B). If a channels transmitter and
receiver are configured in conflicting groups, the group of the
receiver will be used; if two channels sharing a DUART are
configured in conflicting groups, the group of the most recently

configured channel will be used.

3-53

Bit

Name

- Description
If the speed group of a port is changed implicitly (that is, by
configuring a partner port in a conflicting group), the new speed
of that port is given by:
Previously Selected

New Speed
(bits/s)

Speed (bits/s)
50

150

200
7200

1800
2000

1050
1800

7200
19200

38400
19200

38400

The ports are implemented using Dual UARTs and are
associated in the following manner:
Ports 0 and 1 use the same DUART
Ports 2 and 3 use the same DUART
Ports 4 and 5 use the same DUART
Ports 6 and 7 use the same DUART

3.3.48

Async Line Control Register (LNCTRL)

LNCTRL (BASE + 1DO (MODIFIED BY ASYNC.IND.ADD))

30 29

HER

‘

08 07

| Falarafafalolalol | |1 [ ] Pl [
L

Tx.ERROR

04 03

ABORT

[ ] Fefalo
Tx.

Tx.OUT.

Tx.

DMA.
PHYSTX,

DMA.
START

:
DMA.
PTE
RE135

3-54

Bit

Name

Description

<0>

TX.DMA.START

Cleared by initialization.

(Start DMA Transfer)
(R/W)
|

<1>

TX.DMA.PTE

(PTE Address)
(R/W)

This bit is set by the host to start an async DMA transfer.
Having set this bit, the host must not write to TBUFFCT or
TBUFFAD, or the byte containing this bit until the TX.ACT
has been received to say that this transfer has finished. This bit
will be reset before the TX.ACT is returned.
|
Cleared by initialization.

This bit is set by the host to indicate that the DMA address is
the address of the first PTE for the buffer.
If this bit 1s clear, then the DMB32 assumes that the address is
the address of the first byte of the buffer.
If this bit is set, the DMB32 assumes that the address is the
address of a PTE which describes the page which contains the
first byte of the buffer. This address must be long-word aligned
and the offset of the first byte is contained in TX.BUFF.OFF.

This bit may not be modified by the host while a DMA is in
progress.

<2>

TX.DMA.PHYS

(Physical Address)
(R/W)

<8>

TX,OUT*ABORT

Cleared by initialization.

This bit is set by the host to indicate that the DMA address is a
physical address. If this bit is clear then the DMB32 assumes
that the address is a system virtual address. This bit may not be
modified by the host while a DMA is in progress.

Cleared by initialization.

(Transmitter Output

Abort)
(R/W)

This bit is set by the CPU to abort transmission of data. On
seeing this bit set, the DMB32 stops transmitting data on this
channel. If a DMA was in progress it updates the DMA
address/count register.
After a DMA has been aborted, the parameters in the DMA
address and count registers will be in a suitable form to continue
the transfer by clearing the TX.DMA.ABORT bit and setting
the TX.DMA.START bit.

<23:16>

TX.ERROR
(Transmitter Error Bits)

Cleared by initialization.

(R/W)

If this byte contains any value other than zero, this indicates
that errors have have occurred in the transmitter during the
DMA operation.

Error codes are described in Section 3.4.8.

3-55

3.3.49

Async Line Status Register (LSTAT)

LSTAT (BASE + 1 D4 (MODIFIED BY ASYNC.IND.ADD))

30 29

26 25

Pl L L L LRl [

Tx.EINA

<10>

10 09

08 07

04 03

fnfnfefef ol LTI

DSR DCD

SNDOFF

Bit

MILZ’

CTS

Name

Description

ML2

Indicates the current status of the second modem loopback

(Spare Modem Control

signal (Test Indicator) from the modem.

Lead)

®)
<12>

CTS

(Clear to Send)
(R)
|

Indicates the current status of the CTS signal from the modem.

The host should not write to the byte containing this and the
other modem control bits. If it does, then it may read incorrect
modem status until the correct status is made available.

<13>

DCD

(Data Carrier Detected)

Indicates the current status of the DCD signal from the modem.

(R)
<14>

(Ring Indicator)
(R)

<15>

DSR

(Data Set Ready)

Indicates the current status of the Ring Indicator signal from

the modem. The Ring Indicator signal is monitored over a

period of 30 ms, and the state is not updated until all the
samples taken over this period are in agreement.
Indicates the current status of the DSR signal from the modem.

(R)
<23>

SNDOFF

(Send XOFF)
(R/W)

Cleared by initialization.

When this bit is set, the DMB32 will behave as if its internal
FIFO alarm condition has been reached. That is, it will transmit
XOFF characters to every other received character. It will
transmit an XON character when this bit is cleared if it has sent
an XOFF character. It does this regardless of the state of
IAUTO.

3-56

Bit

Name

Description

<31>

TX.ENA

Set by initialization.

(R/W)

When set, the DMB32 will transmit characters as requested.
When clear, the DMB32 will only transmit internally generated
flow control characters and preempt characters. This bit will be
updated by the DMB32 on receiving of flow control characters

(Transmitter Enable)

if the OAUTO bit in LPR 1s set.

3.3.50

Async Flow Control Characters (FLOWC)

FLOWC (BASE + 1D8 (MODIFIED BY ASYNC.IND.ADD))

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11

ool enn [
k

Bit
<7:.0>

<15:8>

RECEIVED.

XON

<31:24>

oo i o o P o o

RECEIVED.

XOFF

SENT.
XON

v v v
SENT.
XOFF

’

Name

Description

SENT.XOFF

This field is set to CTRL/S by Master Reset.

(R/W)

This byte contains the character that the DMB32 will use when

(Transmitted XOFF)

SENT.XON

(Transmitted XON)

(R/W)

<23:16>

10 09 08 07 06 05 04 03 02 01 0O

RECEIVED.XOFF
(Received XOFF)

it sends an XOFF.

This field is set to CTRL/Q by Master Reset.

This byte contains the character that the DMB32 will use when
it sends an XON.

This field is set to CTRL/S by Master Reset.

(R/W)

This byte contains the character that the DMB32 will treat as

RECEIVED.XON

This field is set to CTRL/Q by Master Reset.

(R/W)

This byte contains the character that the DMB32 will treat as

(Received XON)

an XOFF when it is received.

an XON when it is received.

3-57

3.3.51

Async Transmit Completion FIFO (TBUF)

TBUF(BASE
+ 204)

30 29

L L L]

Iefnlefnfafefafe]

)

DMA.

ACT

04 03

[ [ [ [ [ ] [a]a]e][n][r]e]n]a]s]

Tx.v

Tx.

08 07

Tx.PREEMPT

TX.[.TNE

}

ERROR

NOTE
~
The host must not write to this FIFO when TX.ACT

(bit <31> is clear. If TX.ACT is set, the host must
acknowledge a read from this FIFO by writing to it,
which will clear TX.ACT.

Bit

Name

Description

<7:.0>

TX.LINE

Undefined if TX.ACT is clear.

(Transmit Line Number)
(R)

If TX.ACT is set then this byte contains the number of the line
on which one of the following has just occurred:
e

The preempt character register has been emptied.

e A DMA transfer has completed normally.
e

A DMA abort sequence has been completed

An error has been detected during a DMA transfer.

TX.PREEMPT
(Preempt Completed)
(R)
|

This bit indicates that the action is because a single character
(preempt) output has completed. It is clear if a DMA has
completed.

<23:16>

TX.DMA.ERROR

This byte will contain a non-zero error code if an error is

(Transmit Error Code)
(R)

detected while performing output. The same value is in

TX.ERROR

3-58

Bit

Name

Description

<31>

TX.ACT

Cleared by initialization.

(Transmitter Action)

(R)

This bit is set by DMB32 to report one of the following events
concerning the channel specified in TX.LINE:

The preempt character register has been emptied.

A DMA buffer previously passed to the DMB32 has been
completed (last character transmitted).

A DMA abort sequence has been completed.

Transmission of a DMA buffer has been terminated by
DMB32 because a nonexistent memory location was
specified, or the read data had a parity error.

The host must not write to this FIFO when this bit is clear. If
this bit is set, the host must acknowledge a read from this FIFO
by writing to it to clear this bit.

3.3.52

Sync Line Completion FIFO (SBUF)

SBUF (BASE + 208)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

lR]

l I

l l

!R{RRRRH‘R Rl
L

SYNC.
ACT

—

SYNC.
ERROR

! l

‘

HRRRR‘R!RRR!HR
‘

SYNC.
SYNC.
SECOND. | MODEM

SYNC.
LINE

BUFFER

SYNC.
Tx.
ACT
RE138

NOTE

The host must not write to this FIFO when
SYNC.ACT (bit <31> is clear. If SYNC.ACT is set,
the host must acknowledge a read from this FIFO by
writing to it, which will clear SYNC.ACT.

3-59

Bit
<7:0>

Name

Description

SYNC.LINE

Undefined if SYNC.ACT is clear.

(Sync Line Number)

(R)

<8>

SYNC.MODEM

If SYNC.ACT is set then this byte contains the number of the
line on which one of the following has just occurred:
e

A DMA transfer has completed normally, or with an error

‘o

A modem change has been detected.

This bit is set if the FIFO entry is due to a modem change.

(Modem Change)

<9>

SYNC.TX.ACT

This bit is set if the FIFO entry is due to completion of a

(Sync Transmit

transmission. If this bit is clear and SYNC.MODEM is clear

Complete)

then the FIFO entry is due to completion of a receive operation.

R) -~
<10>

SYNC.SECOND.

This bit is set if the FIFO entry is due to completion of a DMA

BUFFER
(Buffer Number)

operation on the second receive or transmit buffer.
T

(R)

<23:16>
|

SYNC.ERROR
(Sync Line Error Code)

This byte contains the error code for the opératian (see
@

TXI1.ERROR, RX1.ERROR).

(R)

<31>

SYNC.MODEM

(Sync Line New Modem
Status)
(R)

When ‘the FIFO entry reiates to a modem status change

operation, this byte contains the new modem status rather than
an error code. This status is of the same format as
LPR2<15:8>.

SYNC.ACT

Cleared by initialization or when the sync Action FIFO is

(Sync Action)

empty.

(R)

This bit 1s set by DMB32 to report one of the following events
concerning the channel specified by sync line number:

A DMA operation has completed

A modem status change has been detected

The host must not write to this FIFO when this bit is clear. If
this bit is set, the host must acknowledge a read from this FIFO
by writing to it to clear this bit.

3-60

3.3.53

Async Receive Buffer (RBUF)

RBUF (BASE + 20C)

30 29

28 27

26 25 24

23 22

21 20

10 09

08 07 06 05 04 03 02 01

FLL LT T LT Pofopalaolalolnfnfafa] | [ | [nfefs]nfs]e]n]n]

O‘V!EF{* PALHW,

ReLINE

DATA.

VALID

RUN. | ERR

Rx CHAR

ERR

NON.

FRAME.

CHAR

ERR

NOTE
The host must not write to this FIFO when
DATA.VALID (bit <31> is clear. If DATA.VALID
is set, the host must acknowledge a read from this
FIFO by writing to it, which will clear
DATA.VALID.

Bit
<7:0>

Name

Description

RXCHAR

If the NON.CHAR

(Received Character)
(R)

contain the oldest received character on the line defined by
RX.LINE<7:0>. Characters are received least significant bit
first and this bit is placed in RBUF<0>. Characters of less than
8 bits are right justified with the high-order bits set to zero.

bit (RBUF<15>) is clear, these bits

DMB32 does not contain a break-detect bit. Line breaks are
passed to the CPU as a single null character with the framingerror bit (RBUF<13>) set.
If the NON.CHAR bit is set, these bits contain either the
current Data Set status following a recent change in status
(RBUF<0> = 0), or a diagnostic code (RBUF<0> = 1).

RBUF<0> = 0 (indicates Data Set change)
RBUF<1> = Undefined
RBUF<2> = Spare modem control input (Test Indicator)
RBUF<3> = Undefined
RBUF<4> = Clear To Send
RBUF<5> = Data Carrier Detected
RBUF<6> = Ring Indicator (integrated over 30 ms)
RBUF<7> = Data Set Ready

The meaning of the bits in RBUF<7:1> during a diagnostic
report is described in Chapter 4, Section 4.3.2.1. After
initialization of the DMB32 there will be diagnostic reports in
the received character FIFO if it has failed self-test.

3-61

Bit

Name

Description

<]2>

PARITY.ERR
(Parity Error)

This bit is set if parity was enabled for the line on which a
character was received with incorrect parity.

(R)
<13>

FRAME.ERR

(Framing Error)

This bit is set if the line on which a character was received was
in the spacing state at the time the first stop bit was sampled.

(R)
<l14>

OVERRUN.ERR
(Overrun Error)

(R)

This bit is set if one or more characters on the line are lost
because the FIFO is full or the DMB32 fails to service the
DUARTsS.
In the event of an overrun, the DUART’s three-character FIFO
is cleared, and a null character with an overrun error is placed
in the received character FIFO. This is a dummy character and
was not in the original character stream. Subsequent characters

will be as read from the DUART.
<15>

NON.CHAR
(Non Character Data)

(R)
<23:16>

RX.LINE

(Receive Line Number)

(R/W)
<31>

DATA.VALID
(Data Valid)

(R)

This bit is set when the data read from the FIFO is not a
character. The data may be either a modem change indication
or a diagnostic message.
This byte contains the line number on which data has been
received, or a Data Set change or a diagnostic report has
occurred.

This bit is cleared by master reset or by the FIFO becoming
empty. It is set when the first character is loaded into the FIFO,
and remains set as long as there is valid data in the FIFO.
The host must not write to this FIFO when this bit is clear. If
this bit is set, the host must acknowledge a read from this FIFO
by writing to it to clear this bit.

3-62

3.4

PROGRAMMING FEATURES

3.4.1

[Initialization

The DMB32 is initialized by its on-board firmware. Initialization takes place after a bus reset sequence, or
when the host sets MAINT<1> (PROG.RESET).

Before starting initialization, the on-board diagnostics run a self-test program. The results of this test are
reported by diagnostic codes placed in the Received Character FIFO (RBUF) and the General Purpose
Register 0 (GPRO) which, in the DMB32, is also designated the Test Summary Register (TSMR).
NOTE

This self-test diagnostic can be skipped on command
from the program. This is covered in Chapter 4,
Section 4.3.

The state of the DMB32 after a successful self-test is as follows:
The self-test status (STS) bit (BICSR<11>) is set.

The BROKE bit (BICSR<12>) is cleared.

All async channels are set for:

OB grRTIER SO AL o

Send and receive 9600 bits/s
Eight data bits
One stop bit

One start bit (cannot be altered)

Parity disabled
Parity odd
Auto-flow off
RX disabled
TX enabled
No break on line
No UART loopback
Data-leads-only circuit
DTR and RTS off
TX.DMA.START cleared
TX.DMA.ABORT cleared.

All sync channel fields (except BUFCTRL<31:16>) set to 0.

All printer port fields set to 0.

The DMB32 clears the PROG.RESET bit (MAINT<1>) and the INIT bit (BICSR <13>) when initialization and self-test are complete.

3-63

3.4.2

Configuration

After the DMB32 self-initialization, the driver program can configure the DMB32 as needed. This is done

using the line parameter registers.

By writing to the associated LPR the program can select data rate, character length, parity and stop bit
length for each async channel. Individual receivers and transmitters can be enabled and auto-flow selected.

By writing to LPRI, LPR2, and LPR3 the
program can select the protocol, mode,
and individual
|
|
characteristics for the sync channel.

There is no equivalent of LPR for the printer port, although there are the registers PFIX, PCTRL and
PCAR. Control and formatting commands
are embedded in the data stream by host software.

3.4.3 Using the FIFOs
|
The contents of TBUF, SBUF, and RBUF are not cleared by a READ action from the FIFO register.
Therefore, after each READ the host should write to the FIFO (the data associated with the WRITE
action is not used). This action will remove the top entry of the FIFO.
The data in the FIFOs will only be valid if bit <31> is set. The host must not write to any of these FIFOs if

bit <31> is clear.

3.4.4 Receiving via the RX FIFO
Characters received on the async channels are merged with the channel number and any error status, and
are put in the received character FIFO (RBUF). The FIFO can be read by any processor connected on the
VAXBI.
If a character is put into an empty RBUF, the DMB32 sets DATA.VALID. This bit will remain set as long
as there is valid data in RBUF. If RXIE is also set, the host will be interrupted at the async vector. The
host’s interrupt routine should then remove data from RBUF until DATA.VALID is clear.
If RXIE is not set, the host must poll RBUF often enough to prevent data loss.
3.4.5

Preempt Transfers
Async channels can transmit single characters by using the Preempt register. The host has only to make

sure that the correct line number is loaded in ASYNC.IND.ADD and then write the character and the
PREEMPT.GO bit to the preempt register. The character will be transmitted before any outstanding
DMA transfers are serviced on that channel.
After the DMB32 transfers the character from PREEMPT, it writes the channel number, and sets
TX.ACT and TX.PREEMPT in TBUF. This adds the TX action report to any queue in TBUF. If TXIE is
set, and the TX interrupt is not already raised to report previous entries, the host will be interrupted at the
transmit vector. Further interrupts will not be produced until TBUF is cleared.

3.4.6

DMA Operations

DMA access to host memory is essentially the same for sync, async, and printer channels (however, only
the sync channel uses DMA transfer on received data).

The DMB32 always attempts to transfer DMA buffers an octaword at a time. Figure 3-2 shows how the
DMB32 handles buffers that are not octaword aligned.
During a DMA WRITE to host memory, that part of the octaword that is outside the buffer will be
masked out by a Write Mask transaction.

3-64

During a DMA READ from host memory, the full octaword at each end of the buffer is read by the
DMB32, but that part of the octaword that is outside the buffer will be discarded.

2°% |3

BUFFER
ADDRESS LOCATION

OCTAWORD
BOUNDARY

BUFFER
ADDRESS + COUNT

ONE

LONGWORD

—

a—

m—

LAST
LONGWORD
TRANSFERRED

ONE
OCTAWORD

FIRST
LONGWORD
TRANSFERRED

MASKED ON WRITE,
DISCARDED ON READ
RE155

Figure 3-2

Handling an Unaligned DMA Buffer

3.4.6.1 Address Translation - DMA buffer information supplied by the host must define the location of
the buffer, and its size. The buffer can be defined in one of four ways, in accordance with VAX
architecture.

Physical address and size (no translation)

Physical address of the first PTE for the buffer, the offset within the first page, and the size.

System virtual address and size

System virtual address of the first Process PTE for the buffer, the offset within the first page,
and the size.

When TXn.DMA.PHYS is O the address is virtual and the DMB32 uses the contents of the SPTE, SPTS,
GPTE and GPTS registers to access the appropriate page tables in host memory. Using these, and any
offsets supplied by the host, the option constructs the physical addresses of the pages. Address translation
of each page is performed separately and continues during the transfer. Accesses to page tables are done
by longword DMA transfers.

3-65

3.4.6.2 Transmitting Data — In this description the registers for the sync channel buffer number one will
be used as examples. The async and printer channels have register names that are recognizable as
equivalents. For example, TBUFFADD and PBUFFAD are equivalent to TBUFFADI.
The host should make sure that TX1.DMA.START is clear before setting up the transfer of a DMA
buffer. If not, there is a DMA transfer in progress. The start address and size of the buffer, and the
address offset if relevant, can then be written to TBUFFAD1 and TBUFFCT
1. The transfer is initiated by
TX1.DMA.START, so it must always be written last. Therefore it is logical to write TX1.DMA.PHYS,
TX1.DMA.PTE and TX1.DMA.START at the same time.

The contents of TBUFFCT1 and TBUFFADI are invalid While TXI.DMA.START 1s set. These will not

be updated until the transfer is completed, stopped by an error or aborted. The host must not write to
TBUFFCT1 or TBUFFADI until the DMB32 clears TX1.DMA.START at the end of transmission.

After TX1.DMA.START is set, the DMB32 will perform the transaction and will report via SBUF. If
SYNC.LE is set, the host will be interrupted at the sync vector.
To abort

a DMA transmission, the host must set TX1.DMA.ABORT. The DMB32 will then stop
transmission and update TBUFFCT1 and TBUFFADI to reflect the number of characters still to be

transmitted. TX1.DMA.START will be cleared and a sync action report placed in SBUF. The host will be
interrupted if SYNC.LE is set.

3.4.6.3 Receiving Data — Reception of a DMA buffer is much the same as transmission. In this case
however, the relevant registers and fields are:

Field(s)

RBUFFADI1

RBUFFCT1

RX.BUFF.CT1
RX.BUFF.OFF1

RLNCTRLI

RX1.DMA.PHYS
RX1.DMA.PTE
RX1.DMA.START
RX1.DMA.ABORT

When the DMA has been completed, stopped by an error or aborted, the DMB32 will place a sync action
report in SBUF. If SYNC.LE is set, the host will be interrupted at the sync vector.

3.4.7 Interrupt Control
In addition to the bus error interrupt vector generated by the BIIC, the DMB32 can provide three interrupt
vectors. These vectors are constructed as shown by Figure 3-3. Bits <31:9> are always zero, bit <8>
indicates that the interrupts are type 1 VAXBI interrupts.
The three DMB32 vectors report several different events, therefore host interrupt routines must check the
DMB3?2 registers to find the precise reason for the interrupt. (See Error Codes, Section 3.4.8)

3-66

10 09 08 07 06 05 04 03 02 01 OO

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11

[o]o]o]o]o]o]olo]o]o]o]o]o]o]o]o]ofo]ofofofo]of+| | | [ [ | [e]°]
zleizzpriinls;

DMB32

VECTOR CODE
BITS 7, 6

0
D
1
1

D
1
0
1

VECTOR
CODE

NODE
D

INTERRUPT

BIIC ERROR
SYNC CHANNEL
ASYNC CHANNEL
PRINTER CHANNEL

PRINTER CHANNEL
ASYNC CHANNELS
SYNC CHANNEL

Figure 3-3

RE140

DMB32 Interrupt Vectors

Interrupts are raised to report the following conditions.

Async channels

—

A character has just been transferred from a preempt register

An async DMA transfer has been stopped by an error, aborted or
completed with or without an error

Sync channel

Printer channel

—

A character has just been placed in an empty RX FIFO The interrupt may
be delayed by RX. TIMER. If REPORT.MODEM is set, the delay will be
overridden by any change of modem status on an async channel.

—

The interrupt is not already raised, and async modem change information

A sync DMA transfer has been stopped by an error, aborted or has

—~

Sync modem change information has been placed in SBUF

—

is placed in the RX FIFO

completed with or without error

A printer DMA transfer has been stopped by an error, aborted or has

completed with or without error

Interrupts are enabled/disabled by RX.I.LE, TX.I.LE, SYNC.LE and PR.LE bits in the ACSR, ACSR and
PCSR.

Error Codes

3.4.8

When an interrupt condition occurs, the DMB32 provides status and error information in several registers.
e

RBUF, TBUF and LNCTRL hold async status and errors

SBUF, TLNCTRLn and RLNCTRLn hold sync status and errors.

PCTRL and PCSR hold printer status and errors

The error codes in bits <23:16> of TBUF, LNCTRL, SBUF, TLNCTRLn, RLNCTRLn and PCTRL are
described in this section. Other status and error codes are described in the appropriate register bit
descriptions of Section 3.3, or in the Chapter 4, Section 4.3.2.1 (Self-Test error codes in the RX FIFO).

3-67

The format of bits<23:16> in all the above registers is the same. The top four bits indicate the error;
the
low four bits supply further information about the error. Bits<23:20> are interpreted as follows:

Bits

Hexadecimal
Value

Error

0
0
0
0
0
0
|
|

0
0
0
1
1
]
0
0

0
1
1
0
0
|
0
0

|
0
1
0
|
0
0
1

No error

|
2
3
4
5
6
8
9

DMA error
Message error
Last character incomplete
Buffer error
Modem error
Aborted by host
Printer not connected
Internal error

The interpretation of bits<19:16> depends upon the error. This is explained in the following sections.

3.4.8.1

No Error - In this case bits<19:16> are always 0.

3.4.8.2 DMA Error - This error occurs when the DMB32 was not able to perform a DMA operation to
the specified buffer (or to the page tables describing the buffer).

After a DMA has completed, the byte count register will indicate the number of characters that were not

transferred to/from host memory. The address, although valid, may have been swapped to a disk and will
not therefore be in the buffer following text). For a DMA error, the code in bits<19:16> can be
interpreted as follows.
|

Bits

Error relates to:

A system PTE
A global PTE

Memory did not respond. In this case the buffer address register holds
the physical address of the failing memory location. (The address may
be rounded down to the octaword boundary below the actual failing
address).

Uncorrectable error in the memory (for example, parity). In this case
the buffer address register holds the physical address of the failing
- memory location. (The address may be rounded down to the octaword
boundary below the actual failing address).

PTE was not valid. In this case the buffer address register holds the
address (either physical or virtual) of the bad PTE.

A process PTE
The buffer itself

PTE did not allow the required access (for example, kernel mode
READ or WRITE). In this case the buffer address register holds the
address (either physical or virtual) of the bad PTE.

3-68

3.4.8.3

Message Error — This error occurs when a received message is invalid. Bits<19:16> indicate the

error that was detected.

Bits

Hexadecimal
Value

Bad block-check in header (DDCMP only)

Bad block-check in data

Message longer than buffer with good block check

Message longer than buffer with bad VRC Bsd+ /¢ %

Abort character received

Invalid character received

Error

3.4.8.4 Last Character Incomplete — This error only occurs for received bit-oriented protocol messages.
Bits<19:16> indicate the number of bits that were missing from the last character.
3.4.8.5

Bits

Buffer Error - Indicates an error in the buffer to be transmitted.

|
18

Hexadecimal
Value

Invalid header

Invalid message length in header

Invalid character in the message

3.4.8.6

Modem Error - Indicates a problem with a modem or its cable.

Hexadecimal
Value

Bits

3.4.8.7

Bits

Error

Modem clock stopped (No modem clock was detected
far at least one second)

Invalid modem status
Cable error (The code signals from the cable have
changed, or no valid cable is present)

Aborted by Host — This indication occurs when the host aborts an operation.

Hexadecimal
Value

Error

Aborted by the host

3-69

3.4.8.8

Bits

Printer Offline — Indicates that the printer Connect Verify signal is not asserted.

Hexadecimal
Value

3.4.8.9

Bits

Error

The printer is not connected.

Internal Error — Indicates that the DMB32 detected an internal error.

Hexadecimal
Value @

Error
Data overrun — the host memory was not able to handle

all the data received from the communications
channels. (This may be the result of attempting
to run a
sync protocol faster than it is able to go.)

Data underrun - the DMB32 was not able to move data
fast enough from host memory. (This may be the result
of attempting to run a sync protocol faster than it is
able to go.)

3.4.9

Automatic Flow-Control

Flow-control is the control of data flow on a communications channel. Its purpose is to prevent loss of data

due to overrun of the FIFOs or communications channels. Control is achieved by embedding flow control
characters XON and XOFF in the data stream.
A channel that receives an XOFF stops sending characters until it receives an XON. A channel that is in
danger of being overrun by received data, sends an XOFF. It sends an XON when the congestion is
relieved.
In a system that includes a DMB32, the host can choose from three methods of flow-control.

Use driver software to issue and respond to XONs and XOFFs

Program the DMB32 to do this automatically (auto-flow)

Directly command the DMB32 when to issue XONs and XOFFs

Method 1 causes the greatest software overhead, and creates delay in responding to received XOFFs. It
does not stop the DMB32 from being overrun but it does allow the host to prevent overflow of its internal
buffers.
Method 2 relieves the host software overhead and improves the response to received XOFFs. The DMB32
will not overrun but host buffers may.

Method 3 is applied to received data only. It causes some software overhead, and will protect host buffers
but not the DMB32.

Methods 2 and 3 can be combined to prevent data loss at the host, the DMB32, or the equipment at the
other end of the communications channel.

3-70

If both the host and the DMB32 perform flow-control on the same channel, it is difficult to keep track of
XONs and XOFFs that have been sent and received. Therefore method 1 should not be combined with
any other method.
NOTE

XONs and XOFFs issued by the DMB32 will be
transmitted even if TX.ENA is cleared. XONs and
XOFFs inserted in the data stream by the host will
not.

“ The DMB32 can be programmed for automatic flow control (auto-flow) on any or all async channels. If so
programmed, it will automatically regulate the flow of characters. Four bits control this function.
IAUTO.FLOW
—
SNDOFF
OAUTO.FLOW
DISCARD.FLOW -

LPR<22>
LSTAT<23>
LPR<23>
LPR<I15>

IAUTO.FLOW and SNDOFF both operate on received characters. IAUTO.FLOW is an enable bit that
allows the state of the RX FIFO to control the generation of XON and XOFF codes. SNDOFF is a direct
command from the host. It can be used to prevent overflow of data buffers in the host. If SNDOFF is set,
the DMB32 will behave as though the RX FIFO is critical (see following text).

OAUTO.FLOW and DISCARD.FLOW operate on transmitted characters. OAUTO.FLOW is an enable
bit that allows the DMB32 to respond to XONs and XOFFs from the channel. DISCARD.FLOW controls
the reporting of such XONs and XOFFs to the host.

3.4.9.1

IAUTO.FLOW - The DMB32 hardware recognizes when the RX FIFO:

Is full

Was 3/4 full and is not yet down to 1/2 full (critical)

Is empty

Has just become ‘not empty’

The firmware uses state b for auto-flow control.

If the host sets a channel’s IAUTO.FLOW bit, the DMB32 will send that channel an XOFF if it receives a
character after the RX FIFO becomes 3/4 full. If the channel does not respond to XOFF, the DMB32 will
send an XOFF in reply to every alternate character received on that channel. An XON will be sent when
the RX FIFO becomes less than half full unless SNDOFF for that channel is set. XONs are only sent to
channels to which an XOFF has been sent.

3-71

3.4.9.2 SNDOFF - When SNDOFF is set, the DMB32 sends an XOFF and then acts as if
IAUTO.FLOW is set and the RX FIFO is critical. When SNDOFF is reset, an XON will be sent unless

IAUTO.FLOW is set and the RX FIFO is critical.
NOTE
Whenever both SNDOFF and IAUTO.FLOW
become clear while the channel is in the XOFF state,
an XON is sent immediately.
3.49.3

OAUTO.FLOW - If the host sets OAUTO.FLOW, the DMB32 will automatically respond to
XON and XOFF characters from the channel. It does this by setting and clearing the TX.ENA bit. Up to
three characters may be transmitted after XOFF has been received.

The host program may also control the TX.ENA bit. In this case it is important to keep track of received
XON and XOFF characters.
NOTE
The DMB32 may change the state of TX.ENA for

‘up to 20 microseconds after OAUTO FLOW is
cleared by the host.

3.4.9.4

DISCARD.FLOW - When OAUTO.FLOW is set, received XON and XOFF characters will be

reported via RBUF unless DISCARD.FLOWis set. When DISCARD.FLOW s set, any received XONs
~and XOFFs will be discarded. DISCARD.FLOW has no effect if OAUTO.FLOW is clear; received

XONs and XOFFs will be treated as data.
3.4.9.5 Flow-Control State Diagrams — State diagrams for DMB32 flow-control operations follow.
Figures 3-4 and 3-5 are for auto-flow of transmitted and received data. Figure 3-6 is for program initiated
flow-control by the SNDOFF bit.

OAUTO.FLOW=0

SET

XON
RCVD

Tx.ENA
|

OAUTO.FLOW = 1
START

XOFF
RCVD

_A_OAUTO.FLOW = 0

CLEAR

Tx.ENAJ
OAUTO.FLOW = 0

‘

XOFF
RCVD

RE204

Figure 3-4

Automatic Flow-Control of Transmitted Characters

NOTE
The RX FIFO becomes critical when it is 3/4 full. It
remains critical until it is less than 1/2 full.

3-72

FIFO NOT CRITICAL

FIFO NOT CF“T!CAL

IAUTO.FLOW=1

F”:O CH‘T!CAL

‘AUTO‘FLOW = 0

NULL

{

STATE

)

FIFO CRITICAL

IAUTO.FLOW =1

STATE

FIFO NOT
CRITICAL

IAUTO.FLOW =0

XON

lAUTO.FL‘DW = 0

NULL

IAUTO.FLOW = 1

SEND

QAW

(

FIFO CRITICAL

SEND'

XOFF

CHAR
RCVD

IAUTO.FLOW = 0

FIFO NOT

CRITICAL

SEND
XOFF

IAUTO.FLOW =0

FIFO NOT CRITICAL

REZ05

Figure 3-5

Automatic Flow-Control of Received Characters

SND.OFF = 1

CHAR.RCVD
NULL

CHAR.

STATE

CHAR.RCVD

RCVD

SND.OFF
=0
CHAR.RCVD
SND.OFF =0

RE206

Figure 3-6

Program Initiated Flow-Control

3-73

Received XOFF
=
Transmitted XOFF =
Received XON
=
Transmitted XON =

CTRL/S
CTRL/S
CTRL/Q
CTRL/Q

=
=
=

13
134
1l

3.4.9.6 Flow-Control Characters — The host can select the codes to be used as received and transmitted
XONs and XOFFs on a channel by writing to the channel’s FLOWC register. The default values for all
channels are:

116

NOTE
When checking for flow-control characters, the
DMB32 only checks characters that do not have
transmission errors. The parity bit is stripped and
the remaining bits are checked for XON and XOFF
codes.
3.4.10 Async Modem Control
Each async channel provides modem control outputs DTR and RTS, and monitors modem status inputs
ML2, CTS, DSR, DCD and RI. These signals can be used for modem control or as general purpose inputs
and outputs.
V

CTS, DSR and DCD are sampled every 10 ms. Therefore, to make sure a change is detected, these signals
must remain steady for at least 10 ms after a change of state. RI is also sampled every 10 ms, but it must
remain steady for three consecutive samples (at least 30 ms) before a change of state is recognized. A copy
of CTS, DSR, DCD and RI is maintained in LSTAT. It is updated after any change.
The only hardware control between the modem control logic and the receiver and transmitter logic is

USE.CTS (see below). Therefore any coordination should be done under program control. Two control
bits, REPORT.MODEM and USE.CTS, are provided to support such coordination.
If REPORT.MODEM is set, modem status changes will not only be recorded in LSTAT but will also be
reported via the RX FIFO. Thus the host can use the appropriate protocol to control the channel. If
REPORT.MODEM is clear, reports via the FIFO are inhibited. By polling LSTAT, control and status can
still be managed by the host if required.
When the DMB32 is transmitting a DMA buffer, the host has no control over CTS protocol. By setting
USE.CTS, the host can stop the DMB32 from transmitting until CTS is asserted. If USE.CTS is clear, the
DMB32 will ignore CTS.

Input ML2 (LSTAT<10>) is set if the modem is in test mode.
3.4.11

Sync Modem Control

Sync modem status and control signals are recorded in LPR2<15:0>. (See Section 3.3.35, LPR?2).
When a modem status change occurs on the sync channel, the new state is put in LPR2<15:8> and the

host is alerted via the sync interrupt. A change of any status bit except SYNC.RI will be recorded in
LPR2 as soon as detected, but SYNC.RI must remain steady for at least 30 ms before the DMB32 will
recognize a change of state.

When the host writes modem control bits to LPR2<7:0>, it should not write to the byte that contains
modem status. Otherwise, changes of modem status may be lost.

3-74

The only hardware control between the modem control logic and the receiver and transmitter logic is
MODEM.OVERRIDE (see below). Therefore any coordination should be done under program control.
MODEM.OVERRIDE is provided to support such coordination.

If MODEM.OVERRIDE is set, transmission and reception can occur regardless of the state of the modem
control bits. If MODEM.OVERRIDE is clear, then loss of DCD, DSR, or Receive Clock will cause the
DMB32 to abort reception; loss of DSR, CTS, or Transmit Clock will cause transmission to be aborted. In
either case, modem status reports and sync interrupts will occur as previously described.
The remaining control and status signals CLOCK.CONTROL, LOOP, and SYNC.TEST.INPUT are

used for test purposes.

3.4.12

Selecting Protocols

Synchronous protocols DDCMP, SDLC, HDLC, IBM BISYNC, and GEN BYTE are selected by PROTOCOL<2:0> in LPR2.

3-75

CHAPTER 4

TROUBLESHOOTING

4.1

SCOPE

This chapter describes how diagnostics are used to diagnose faults on the DMB32 option. A troubleshooting flowchart is included.
CAUTION
You must wear an anti-static wrist strap connected
to an active ground whenever you work on a system
with the covers removed, or handle the T1012
module.

4.2

DIAGNOSTICS

There are five types of diagnostic provided for the DMB32.
1.

On-board self-test diagnostic

Standalone diagnostic: EVDAK (level 3)

Online diagnostics: EVDAJ, EVDAL, EVAAA (level 2R)

User Environment Test Program (UETP)

Data Communications Link Test (DCLT)

As its name suggests, the dn»board self-test exists in ROM on the module.
Both level 3 and 2R diagnostics run under the VAX Diagnostic Supervisor (VDS). EVDAK is standalone,
while the level 2R diagnostics run online under the VAX/VMS operating system.

UETP is a system exerciser that runs diréctly under the VAX/VMS operating system.
DCLT is a level 2R diagnostic that tests a data communications link to another processor that is also
running DCLT. DCLT can also run with a loopback connector on the modem connection.

4.3 ON-BOARD SELF-TEST DIAGNOSTIC
The self-test diagnostic occupies less than 8 Kwords of the DMB32’s firmware ROM. It runs
automatically:
e

At power-up

After a hardware or software reset

When the Node Reset (NRST) bit (VAXBICSR<10>) 1s set

The self-test performs extensive functional tests of the DMB32 hardware, and then partially initializes the
DMB32 before passing control to the functional firmware.

During the tests, the two yellow GO/NOGO LEDs on the T1012 module are turned OFF. They are
turned ON again when the option has passed the self-test. If the option does not pass, the LEDs will stay
OFF. The GO/NOGO LEDs are driven by the DIAG.FAIL bit (MAINT<I11>).

The self-test also reports error and status information to the host through the RX FIFO and some other
registers. This information is used by system-based diagnostics such as EVDAK. Diagnostic messages are
covered later in this chapter.

Although the self-test is comprehensive, a successful test sequence does not guarantee that all sections of
the module are good.

There are three conditions that will cause the self-test sequence to be modlfied
e

[f the SKIP.SELF.TEST bit (MAINT<3>)is set, the self-test will samply initialize the module

and pass control immediately to the functional firmware.
e

[f the FORCE.FAIL bit (MAINT<0>) is set, the self-test will act as if the self-test has failed. It

will write an error code into the RX FIFO indicating that it has been forced to fail.

[f the bus signal BI STF L (Self-Test Fast)is asserted a fast self-test wxll be done. Contml will be
passed to the functional firmware within 250 ms.

The scope and duration of these vanatxons of the self-test are summamzedin Table 4-1.

~ Table 4-1 Scope and Duration of Self—Test
BI STF L

Skip Self-Test?

|
Force Fail?

Duration

YES

(very short)

YES

(very short)

<10s

50 to 90

YES

<250 ms

15 to 20

Asserted?

X = don’t care

4-2

% of Module Tested

Starting the Self-Test

4.3.1

There are several methods by ‘which the host system can start the self-test diagnostic.
®

System power-up

Bus reset

Programmed reset
(MAINT<1>)

Node Reset

(VAXBICSR<10>)

—

Genera'tes a bus reset (via DC LO L) at all nodes (includes
resetting BIIC)

Same as system power-up

Does not cause BIIC to self-test, but SKIP.SELF.TEST
(MAINT<3>) and FORCE.FAIL (MAINT<0>) bits are
examined

—

Causes full reset and self-test, including BIIC

Whatever the method of initiation, the dmgnosuc will always test the state of the bus signal BI STF L
(Self-test fast).

If the self-test was caused by power-up, bus reset, or by the NRST bit, the BIIC will be reset and will
perform its own self-test. During this operation, the BLBROKE bitin BICSR<12>is set. It will be cleared
after a successful test sequence.

Self-Test Indications and Error Codes

4.3.2

When the self-test begins, it sets the DIAG.FAIL bit (MAINT<I 1>), and sets the PROGRAM-

MED.RESET bit (MAINT<1>).

DIAG.FAIL - Switches OFF the GO/NOGO LEDs and asserts the bus signal BLBAD.L

PROGRAMMED RESET - Indicates that the contents of registers are not valid

During the testing of the option, error and status information is transferred to:
¢

The RX FIFO (RBUF)

MAINT <0,1,3,8,9,10,11,13,14,15>

CONFIG <23:0>

TSMR <31> and <25:0> (GPRO)

BICSR <12> (the BIIC self-test uses other bits of this register)

The programmed reset is then cleared to show that register contents are valid. If there are no errors,
DIAG.FAIL is cleared (GO/NOGO LEDs ON).

A detailed mterpretatmn of the information in the MAINT, CONFIG, TSMR, and BICSR registers is
given in Chapter 3, Operation and Programming. The mterpretatmn of the error codes loaded into the RX
FIFOis given here.

4-3

4.3.2.1 Self-Test Error Codes in the RX FIFO - Error codes that the self-test can load into the RX
FIFO are explained in Table 4-2. The table is arranged in numerical order according to the lower word of
the error number. This makes the list easier to use for reference but gives a random appearance to the
grouping of the tests. The error numbers are actually made up in the following way:
<0>
<5:1>

<7:6>
<14:8>
<15>
<20:16>
<30:21>

<31>

Always 1
Test number
Error number
Not used, always 0
Always
1
Channel number or EV code
Not used, always 0
Always 1

The FIFO may contain up to 21 such codes after completion of the self-test.
Table 4-2

Self-Test Error Codes in the RX FIFO

Error Code

(hexadecimal)
8000 8001
8000 8003
8000 8005
8000 8007
8000 8009
8000 800B
8000 800D
8000 800F
8000 8011
8000 8013

Error code meaning
* 68000/RAM Stack R/W Fail
* 68000 microprocessor Fail
* ROM CRC Fail
* Local RAM R/W Fail
* Timer Data Path Fail

* Timer Functionality Fail
* Cable Connector Key Fail

* CASRAM R/W Fail
RX FIFO Alarm Status Fail
TX Action FIFO Alarm Status Fail

8000 8015
808$ 8017
80$$ 8019
80$$ 801B
80$$ 801D

Asynchronous Address/Data Path Fail
Asynchronous Internal TX/RX Fail
Asynchronous External TX/RX Fail
Asynchronous Framing Error Fail

80$$ 801F
80$$ 8021
80$$ 8023
80$$ 8025
803%$ 8027

Asynchronous Parity Error Fail
Asynchronous Split Speed Fail
Asynchronous Modem Signals Fail
Synchronous Data Path Fail
Synchronous Internal BOP TX/RX Fail

Sync TX FIFO Alarm Status Fail

indicates the channel number; that is: async channels O to 7, sync channels A (0), B (1).

%% indicates the EV code obtained from the BIIC via the CGA.
@@ 1ndicates for Digital Internal Use only.
*
indicates errors that are FATAL to the self-test.

4-4

Table 4-2

Self-Test Error Codes in the RX FIFO (continued)

Error Code

(hexadecimal)

Error code meaning

80$$ 8029
8000 802B
8000 802D
8000 802F
8000 8031

Synchronous External V.11 TX/RX Fail
Synchronous Modem Signals Fail
Printer Port Data Output Fail
BIIC/CGA Loopback Timeout or Data Fail
BI/CGA Intra-node Timeout Fail

8000 8033
8000 8051
8000 8053
8000 8055
80$$ 8067

BI/CGA Intra-node Mask Timeout Fail
RX FIFO Data Fail
TX Action FIFO Data Fail
Sync TX FIFO Data Fail

808$ 8069
8000 806D

Synchronous External V.10 TX/RX Fail
Printer Port Control Signals Fail

Synchronous Internal COP TX/RX Fail

80%% 806F
80%% 8071
80%% 8073
8000 80A7
80$$ 80A9
80%% 80AF
80%% 80BI
80%
% 80B3

BIIC/CGA Loopback Master Seq Fail
BI/CGA Intra-node Master Seq Fail
BI/CGA Intra-node Mask Master Fail
Bad Synchronous Interrupt Fail

8000 80EF
8000 80F1
8000 80F3

BIIC Self-Test Fail
BI/CGA Intra-node Data Error Fail
BI/CGA Intra-node Mask Data Fail

80@@ 8FFF

Forced Failure

Synchronous External V.35 TX/RX Fail
BIIC/CGA Loopback Slave Seq Fail
BI/CGA Intra-node Slave Seq Fail
BI/CGA Intra-node Mask Slave Fail

indicates the channel number; that is: async channels 0 to 7, sync channels A (0), B (1).

%% indicates the EV code obtained from the BIIC via the CGA.
@@ indicates for Digital Internal Use only.
*
indicates errors that are FATAL to the self-test.

4.3.2.2 Test Summary Register Bit Definitions — With certain self-test detected errors, it is not possible
to report via the RX FIFO. As a safeguard against such errors, the DMB32 also makes error reports via
the TSMR (also called GPRO).

TSMR <24:00> is used as a bit mask for errors detected by the self-test. If a bit is set, the related error
exists. The diagnostic also sets bit <31> to indicate that the data in TSMR is valid. The TSMR register is
described in chapter 3, Operation and Programming, Section 3.3.9.

4-5

4.4 EVDAK STANDALONE DIAGNOSTIC
EVDAK is a suite of functional verification tests. The tests run standalone under the VAX Diagnostic
Supervisor (VDS) V9.0 or later. The supervisor is documented in the VAX Diagnostic System User’s
Guide (EK-VX11D-UG).
EVDAK is intended for:
)

Users; to identify failing DMB32s and as a confidence check

)

Field Service; to isolate faults and to test installations

Manufacturing; as a final test

Final Assembly; as part of a system test

EVDAK has four modes of operation:
1. Internal loopback

In this mode a physical loopback connector is not used. The selected
channels are looped back internally. Therefore the line drivers and
receivers will not be tested.

2. Manufacturing

This mode is used by DIGITAL to test T1012 modules during
manufacture, and is for internal use only.

3. External loopback

In this mode the appropriate loopback connector must be installed on
any selected async or sync channel. The connection is made on the
H3033 distribution panel. Line drivers and receivers of the looped back
channels will be tested.

4. Modem loopback

In this mode only the data lines are tested. Tests can be run with an
external loopback connector or a modem on the channel to be tested. If
a modem is used it must be looped back manually.

The printer channel can be tested in all available modes (manufacturing mode is not available, and is

therefore disregarded in the rest of this chapter). However, a printer is required, and one of the tests
requires operator intervention.
EVDAK consists of 33 tests. Any or all of tests 1 to 32 can be selected to run during one pass. Test 33
needs manual intervention and is started with a separate command (see Section 4.4.4). The tests are listed

in Table 4-3.

Table 4-3

Test

Function

Device Address test

BIIC Device Address test

Maintenance Modes test

Self-test test

Configuration test

10
11
12
13

EVDAK Tests

ASYNC PORT TX Enable/Action/TX FIFO test
ASYNC PORT RX FIFO test
ASYNC PORT Interrupt test
ASYNC PORT DMA Start And Abort test
ASYNC PORT Maintenance Mode test
ASYNC PORT Parameters test
ASYNC PORT Split Speed test
ASYNC PORT Error Detection test

14
15
16

ASYNC PORT XON/XOFF test
ASYNC PORT Modem Signals test
ASYNC Port Reset test

SYNC PORT TX Completion FIFO Test

SYNC PORT DMA Start And Abort test

SYNC PORT Maintenance Mode test

SYNC PORT Interrupts test

21
22
23
24

SYNC PORT Line Protocol test
SYNC PORT Line Parameters test
SYNC PORT Modem Signals test
SYNC PORT Port Reset test

25
26
27
28
29
30
31

PRINTER PORT DMA Start And Abort test
PRINTER Port Interrupts test
PRINTER PORT ALL Characters test
PRINTER PORT Port Formatting test
PRINTER PORT Prefix And Suffix Characters test
PRINTER PORT Width And Size test
PRINTER PORT Test Patterns

Exercise test

PRINTER ONLINE/OFFLINE test

(V)

(V)
(V)
(V)
(V)

(M) Will only run in Manufacturing Mode
(V) Requires visual check of printout

()

(M)
(M)

Requires manual intervention and a separate START command

4-7

4.4.1 Starting EVDAK
Before EVDAK can be run, the operator must:
e

Boot the VDS (EBSAA for VAX-8200, EZSAA for VAX-8800)

Load EVDAK

ATTACH and SELECT the DMB32(s) to be tested

START the diagnostic

These operations are described in the V.AX Diagnostic System User’s Guide.
An example of how to run EVDAK is shown in Example 4-1. In the example, TRACE is set to cause all
tests to be reported.
DIAGNOSTIC
DS>»

LOAD

SUPERVISOR.

Z2Z-EBSAA-

EVDAK

DS»> SET TRACE
DS> ATTACH
DMB32

HUB TXA

DS>»

START

TXA

15:36:22

program

load

the

)

set

trace

HUB

linked

TXA
1

=
=

Device Name as appropriate
VAXBI Node ID (hexadecimal)

select

start

;i1
1

SELECT

2-0CT-1985

DS>

9.0-325

Example 4-1

the

VAXBI

device

for

test

diagnostic

Starting EVDAK
NOTE

If the machine does not have native VAXBI but uses
an adapter, this must be attached before the
DMB32. For example, on the VAX-8800 the attach
sequence might be:
DS»

ATTACH

DS»>

iiACH NBIB Nfiimlfigffi

NBIA

HUB

NBIAO

By default, tests 1 to 32 are all run (though tests 12 and 13 will abort without doing anything). Test 33 is
run using the \SECTION=MANUAL switch (see Section 4.4.4)

4-8

4.4.2 Options
After the start command has been entered, the operator is prompted to select the area to be tested. All

possible prompts are illustrated in the example test run shown in Example 4-2.
DIAGNOSTIC

DS>»

LOAD

DS>»

ATTACH

Device

SUPERVISOR.

2ZZ-EBSAA-

9.0-32S5

2-0CT-1985

15:36:22

EVDAK

type?

DMB32

Device Link? HUB
Device Name? TXA
Node_id? 1
T
DS» SEL TA
DS>»

START
Program:
at

EVDAK,

Testing:

_TA

Test

the

ASYNC

Loop

back

type

Lines

Line

speed

2000,
Bits

revision

1.0,

15:36:59.45.

?
?

[(300),
4800,

Byte

[(YES),

YES,

[CINTERNAL),

tested

2400,
per

port

tests,

NO1

[(ALL),

REVERSE,

50,

110,

7200,

[(8),

75,
9600,

INTERNAL,
134.5,

19200,

EXTERNAL,

EVEN,

0ODD,

150,

384001

MODEM]

MODEM

0,1,2,...,6,71

300,

600,

1200,

1800,

1200

Parity ? [CEVEN), NONE, ODD, EVEN]1 0ODD
the SYNC port ? [(YES), YES, NOT YES
Loop back type ? [CINTERNAL), INTERNAL, EXTERNAL,

Test
Test

the

Line

printer

Printer
Printer
Do

you

PRINTER
Page
Page

want

port

fitted

width
length
default

Pattern

Type

Enter

test

string

FOX

JUMPED

Repeat
End
time

[(NO),

[(132),
?

[(66),

patterns

[(DIAG),

OVER

THE

[

LAZY

times

errors

DIAG,

Default

pattern
run,

[(YES),

2-0CT-1985

YES,

NOl

MODEM]

MODEM

YES

0-132(D)>1
80
0-66(D)]1
?

[C(YES),

YES,

NO]l

HORIZ,

VERT,

characters

all

CHAR]

HORIZ
1

THE

QUICK

BROWN

DOG

[(1),

CONT,

detected,

1,
pass

count

4,
is

6
o

15:39:35.24

DS»>

Example 4-2

EVDAK Diagnostic Prompts

In the “Lines to be tested” question, up to eight lines can be selected, in any order. The diagnostic will test
them in the order that they were entered. “ALL” tests all the lines in ascending order; “REVERSE” tests
all the lines in descending order; “EVEN” tests lines 0, 2, 4, and 6; “ODD” tests lines 1, 3, 5, and 7.
When the sync port is tested with an external loopback, the diagnostic will check which of the two 50-way
loopback connectors is fitted and will test as appropriate.

Examples of the test patterns for the printer test are shown in Example 4-3. Three different test strings are
shown in all four pattern types, the page width is 15 and the page length 1s 7.
Test

CHAR

HORIZ

VERT

Stiring:

pattern

default

string

THE

BROWN

QUICK

AAAAAAAAAAAAAAA

TTTTTTTTTTTITTITT

ooooo000000CO0COOO

AAAAAAAAAAAAAAA

TTTTTTTTTITTITITITT

000000000000000

AAAAAAAAAAAAAAA

TTTTTTTTTTTITTITT

000000000000000

AAAAAAAAAAAAAAA

TTTTTTTTTTTTITTT

000000000000000

AAAAAAAAAAAAAAA

TTTTTTTTTTTITTITT

000000000000000

AAAAAAAAAAAAAAA

TTTTTTTTTTITITTITT

000000000000O0OCO

AARAAAAAAAAAAAAA

TTTTTTTTTTTITTTT

000000000000000

ABCDEFGHIJKLMNO

THE

QUICK

BROWN

010101010101010

ABCDEFGHI JKLMNO

THE

QUICK

BROWN

010101010101010

ABCDEFGHI JKLMNO

THE

QUICK

BROWN

010101010101010

ABCDEFGHIJKLMNO

THE

QUICK

BROWN

010101010101010

ABCDEFGHI JKLMNO

THE

QUICK

BROWN

010101010101010

ABCDEFGHI JKLMNO

THE

QUICK

BROWN

010101010101010

ABCDEFGHIJKLMNO

THE

QUICK

BROWN

010101010101010

000000000000000

AAAAAAAAAAAAAAA

TTTTTTTTTTTTITTT

BBBEBBBBEBBBEBBBBB

HHHHHHHHHHHHHHH

1111111111111
11

cCCccccccccecceccec

EEEEEEEEEEEEEEE

000000000000000

EEEEEEEEEEEEEEE
FFFFFFFFFFFFFFF
GGGGGGGGGGGGGGE

elefefefefefefefeefelefefefel
vuuuuuuuvuuuuuuuu
ITTITITIIIIIIINI

000000000000000

ABCDEFGHI JKLMNO

THE

010101010101010

"M1T111111111111

DDDDDDDDDDDDDDD

DIAG

pattern

QUICK

THE

OABCDEFGHIJKLMN
NOABCDEFGHIJLKM

MNOABCDEFGHI
JKL

LMNOABCDEFGHI
JK

OWN

BROWN

QUICK

THE

ROWN

JKLMNOABCDEFGHI

BROWN

101010101010101

BRO

010101010101010

101010101010101

010101010101010

QUICK

010101010101010

QUICK

THE

QUICK

THE
THE

TM1T11 1111111111

000000000000000

BROW

QUICK

THE

KLMNOABCDEFGHIJ

Example 4-3
4.4.3

QUICK

101010101010101

Printer Test Patterns

EVENT Flags

There are five EVENT flags related to the EVDAK diagnostic. However, they are only used in Manufacturing Mode tests and must not be set in other modes.

4-10

4.4.4 Sections
There are two SECTION switches for the START command. These are:

/SEC=DEFAULT

Runs tests 1 to 32

/SEC=MANUAL

Run test 33 only

4.4.5 Error Messages
An error message may indicate that the option is defective or that an illegal parameter has been selected.
Error numbers are interpreted in the diagnostic listing EVDAK.LIS. An example of an error message is

shown in Example 4-4.
TR EREERER

EVDAK

Pass

Hard

error

Current

¥rxxexx*

1»0

was

End

LR X

subtest
testing

number

data

while

line

Expected
Actual

test

error

TA:

ASYNC

5-SEP-1985
PORT

FIFO

16:30:04.55
Failed

0006

0007

Hard

error

number

Example 4-4

#*#***x&xsx

EVDAK Error Message

4.5 EVDAJ ONLINE DIAGNOSTIC (ASYNC)
This level 2R diagnostic runs online under VMS V4.4 or later. The operator interface is via the VAX
Diagnostic Supervisor (VDS) V9.0 or later. EVDAJ provides a confidence check of the async channels of
the DMB32. It consists of five tests:
1.

Internal data loopback test on selected channels in sequence.

Internal DMA data loopback test on selected channels in sequence.

Internal DMA data loopback test on selected channels at the same time.

External loopback test (using the H3197 loopback) of modem control signals.

External data loopback (using the H3197 loopback, or via a modem). If a modem is used, it
must be set up manually.

4-11

Before running EVDAJ, the user should be aware of the following points:

The tests run online, therefore it is essential to define the channels to be tested. The test will not
run if a channel which is allocated to another process is selected for testing. Channel allocations
can be checked by using the VAX/VMS command SHOW DEVICE/FULL. In Example 4-5,
channels 0 and 1 are free and channel 2 is allocated to job control.

SHOW

DEVICE/FULL

TXA

is online, record-oriented
Terminal TXAO0:, device type VT100,
device,

carriage

control.

0
.
00000000
0

Error count
Owner process
Owner process ID
Reference count

118
Operations completed
[1,4]
|
Owner UIC
,W:
S:RWLP,0:MG:
Dev Prot
80
Default buffer size

Terminal TXA1:, device type VT100, is online, record-oriented
device,

carriage

control.

0
..
00000000
0

Error count
Owner process
Owner process ID
Reference count
Terminal TXA2:,
device,

device type VT100,

carriage

Error count

113
Operations completed
[1,4]
Owner UIC
,W:
S:RWLP,0:MG:
Dev Prot
80
Default buffer size
is online,

record-oriented

control.

"Job_controlTM
Owner process
00000088
ID
Owner process
1
Reference count

Example 4-5

Operations completed
Owner UIC
Dev Prot
Default buffer

113

[1,4]
,W:
S:RWLP,0:MG:
80
size

The SHOW DEVICE/FULL Command

If test 4 is being run, an H3197 loopback connector must be fitted to the selected channel. By
setting EVENT flag 20, the operator will cause the program to halt before each channel is
tested. This allows the H3197 to be moved to the next channel to be tested. Another event flag
(21) causes the program to halt before each complete DMB32 has been tested.

If test 5 is to be run, a modem or an H3197 must be fitted to the selected channel. EVENT

If tests 4 or 5 are run without some form of loopback installed, error messages will be generated.

flags 20 and 21 also function in this test.

The EVDAJ diagnostic is supported by the online help facility EVDAJ.HLP.

The VAX Diagnostic System User’s Guide (EK-VX11D-UG) provides instructions on how to load and
run programs under the diagnostic supervisor. For details of online tests, refer to the diagnostic listing
EVDAIJ.LIS, or the help file EVDAJ.HLP.

4.5.1
Starting EVDAJ
Before EVDAJ can be run, VMS must be running and the operator logged into the system maintenance

account. The operator must then:

Allocate the lines to be tested
Boot the VDS (EBSAA for VAX-8200, EZSAA for VAX-8800)

Load EVDAJ
ATTACH and SELECT the DMB32(s) to be tested

START the diagnostic
These operations are described in the VAX Diagnostic System User’s Guide.

ALL

TXAO

ALL

TXA1

ALL

TXAZ2

An example of how to run EVDAJ is shown in Example 4-6. Where appropriate, commands for different
host systems are included.

RUN

EBSAA

For

VAX-8200

;

For

VAX-8800

EZSAA

ATTACH

ZZ-EBSAA-

DS>

SELECT

DS>

START

DMB32

TXA

HUB TXA

Load

tested

9.0-325

2-0CT-1985

the

diagnostic

DMB32

W
E

DS>

SUPERVISOR.

EVDAJ

HUB

linked

LOAD

lines

TXA

Device

Name

DS>

VAXBI

Node

the

device

wAE

DIAGNOSTIC

select

RUN

Allocate

start

the

Example 4-6

15:36:22

VAXBI

as
ID

appropriate
(hexadecimal)

for

test

diagnostic

Starting EVDAJ

NOTE
If the machine does not have native VAXBI but uses
an adapter, this must be attached before the
DMB32. For example, on the VAX-8800 the attach
sequence might be:

4-13

Options

4.5.2

After the start command has been entered, the operator is prompted to select the options. There are two
questions to be answered, and they are illustrated in the example test run shown in Example 4-7.
DIAGNOSTIC SUPERVISOR.
DS»

LOAD

2ZZ-EBSAA- 9.0-325

2-0CT-1985

15:36:22

EVDAJ

DS»

ATTACH
Device type?

DMB32

Device Link? HUB
Device Name? TXA
o
Node_id? 1
DS» SEL TXA
DS>» START
Program: EVDAJ 1.0, 5 tests,
Testing: _TXA

Lines

to be

LEVEL 2R DIAGNOSTIC FOR ASYNC DMB32,

revision

15:36:59.45.

tested ?

[(ALL),

Line speed ? [(9600), 75,

REVERSE,

110,

134,

EVEN,

0ODD,

0,1,2,...,6,71

150, 300, 600,

2400, 4800, 192001 19200
End of run, 0 errors detected, pass
2-0CT-1985 15:37:11.08
time is

count

1200,

0ODD

1800, 2000,

DS»

Example 4-7

EVDAJ Diagnostic Prompts

In the “Lines to be tested”” question, up to eight lines can be selected, in any order. The diagnostic will test
them in the order that they were entered. “ALL” tests all the lines in ascending order; “REVERSE” tests
all the lines in descending order; “EVEN" tests lines 0, 2, 4, and 6; “ODD” tests lines 1, 3, 5, and 7.
4.5.3

EVENT Flags

Event flags are used to control multi-channel or multi-DMB32 tests. For example:
DS>»

SET

EVENT

Event flag 20

Functions in tests 4 and S only. When flag 20 is set the program halts before
each channel is tested. This allows the operator to move the H3197 loopback
connector to the channel to be tested next, or to put the modem into local
loopback.

Event flag 21

4.5.4

Functions in all tests. When flag 21 is set, the program halts before each
DMB32 is tested.

Sections

There are three SECTION switches for the START command. These are:
e

/SEC=DEFAULT

Runs tests 1, 2 and 3

/SEC=EXTERNAL

Runs tests I, 2 and 3, and tests 4 and 5 in external loopback mode

/SEC=MODEM

Runs tests 1, 2 and 3, and test S in external loopback mode

4-14

4.5.5

Error Messages
If an error is detected during test, the program will output an error message. This may indicate that the
option is defective or that an illegal parameter has been selected. Error numbers are interpreted in the
diagnostic listing EVDAJ.LIS. An example of an error message is shown in Example 4-8.
*ekxxarxe

EVDAJ

Pass

Hard

error

AND

test

LEVEL

subtest

while

DIAGNOSTIC

testing

error

TXA:

FOR

ASYNC

6-SEP-1985

TRANSMITTED

RTS,

DMB32

1.0

***xxsxs

13:23:43.53
EXPECTED

CARRIER

CTS

LINE:

DEVICE

NAME:

_TXA1:

EXPECTED MODEM
ACTUAL
XOR

MODEM

SIGNALS

¥RRXXXEY

SIGNALS:

30(X)

70C(X)

40C(X)

End

Hard

s RING

error

number

Example 4-8

******xsx

EVDAJ Error Message

4.6 EVDAL ONLINE DIAGNOSTIC (SYNC)
This level 2R diagnostic runs online under VMS V4.4 or later. The operator interface is via the VAX
Diagnostic Supervisor (VDS) V9.0 or later. EVDAL provides a confidence check of the sync channels of
the DMB32 option. It consists of four tests:

DDCMP protocol test

BISYNC protocol test

HDLC protocol test

Modem signal test

In tests 1, 2 and 3:
e

Data is transferred in groups of 16, 64, 512, and 1000 bytes, using five different data patterns.

If the 50-way balanced loopback connector H3196 is fitted and the /EXTERNAL section is
being run, the test will automatically run twice. Once with V.35 clear and once with V.35 set.

In test 3:
e

SDLC is not specifically tested as it is a subset of HDLC.

In test 4:
e

The diagnostic detects which loopback connector/adapter cable is connected. The appropriate

modem signals are tested.

The EVDAL diagnostic is supported by the online help facility EVDAL.HLP.

The VAX Diagnostic System User’s Guide (EK-»VX] 1D-UG) provides instructions on how to load and

run programs under the diagnostic supervisor. For details of online tests, refer to the diagnostic listing

EVDAL.LIS, or the help file EVDAL.HLP.

4-15

4.6.1 Starting EVDAL
Before EVDAL can be run, VMS must be running and the operator logged into the system maintenance
account. The operator must then:
e

Allocate the lines to be tested

Boot the VDS (EBSAA for VAX-8200, EZSAA for VAX-8800)

[oad EVDAL

ATTACH and SELECT the DMB32(s) to be tested

START the diagnostic

These operations are described in the VAX Diagnostic System User’s Guide.
An example of how to run EVDAL is shown in Example 4-9. Where appropriate, commands for different
host systems are included.

EZSAA

DIAGNOSTIC
DS>»

LOAD

DS>»

ATTACH

SUPERVISOR.

DS»

SELECT

DS>»

START

HUB

SIA

;

For

VAX-8800

Z2Z2-EBSAA-

EVDAL
DMB32

VAX-8200

9.0-325

2-0CT-1985

the

diagnostic

;

Load

RUN

For

HUB

linked

A
E

;

SIA

Device

Name

W
E

EBSAA

VAXBI

Node

the

device

wi®

RUN

select

ai®

start

DMB32

the

Example 4-9

15:36:22

VAXBI
as

appropriatle

(hexadecimal)

for

test

diagnostic

Starting EVDAL

NOTE
If the machine does not have native VAXBI but uses
an adapter, this must be attached before the
DMB32. For example, on the VAX-8800 the attach
sequence might be:
DS>

ATTACH

NBIA

HUB

DS>»

ATTACH

NBIB

NBIA

NBIAO

ATTACH DMB32 NBIBO

NBIBO

TXA

4.6.2 EVENT Flags
One event flag can be used to control multi-DMB32 tests. For example:
DS>»

SET

EVENT

Event flag 21

—

Functions in all tests. When flag 21 is set the program halts before each DMB32 is
|
tested.

4-16

4.6.3 Sections
There are three SECTION switches for the START command. These are:

/SEC=DEFAULT

Runs tests 1,2 and 3 in internal loopback mode. Loopback connectors
are NOT REQUIRED in this mode.

/SEC=EXTERNAL

Runs all tests
in external loopback mode. In this mode, a loopback
connector IS REQUIRED. Several different loopback connectors can
be used with this test:
H3195 50-way loopback
H3196 50-way loopback

H3250 (V.35)
H3248 (RS-232)
H3198 (RS-422, RS-423)

fitted to the
distribution panel

connected via
the appropriate
adapter cable

To fully test the T1012 module, the diagnostic must be run twice, first
with H3195 fitted, and then again with H3196 fitted.

/SEC=MODEM

Tests 1, 2 and 3 in external loopback mode. This test checks the data
lines only. It can be run with any of the loopback arrangements
described in /EXTERNAL above, or with a modem installed. If a
modem 1is used, it must be set manually into loopback mode.

4.6.4

Error Messages
If an error is detected during test, the program wm output an error message. This may mdlcate that the
option is defective. Error numbers are interpretedin the diagnostic listing EVDAL.LIS. An example of an
error message is shownin Example 4-10.
#r¥¥wwxx»
Pass

System

EVDAL

test
fatal

LEVEL

subtest

error

while

DEVICE

NAME:

IOSB

0000002CCX)

=
=

STATUS
¥rxxxx2r*®

2R
0,

DIAGNOSTIC
error

testing

17,
SIA:

FOR

SYNC

3-DEC-1985
ERROR

DMB32

***x#%i=

21:27:12.89

OCCURRED

DURING

WRITE

OPERATION

_SIAO

00010000CX)

MESSAGE:
End

XABORT,

System

abort

fatal

error

Example 4-10

number

****xxxa

EVDAL Error Message

4.7 EVAAA ONLINE DIAGNOSTIC (Printer)
This level 2R diagnostic runs online under VMS V4.4 or later. The operator interface is via the VAX
Diagnostic Supervisor (VDS) V9.0 or later. EVAAA provides a functional test of printers connected to
any VAX-11 or VAXBI system (it is not specific to the DMB32).
EVAAA consists of 33 tests for a range of printers. When the diagnostic runs, only those tests relevant to
the type of printer connected will be used. A successful test of an attached printer implies that the DMB32
printer port is good.
All EVAAA tests require intervention by the operator or visual inspection of the printout. For details of
the tests, refer to the diagnostic listing EVAAA.LIS

4-17

Starting EVAAA

4.7.1

Before EVAAA can be run, VMS must be running and the operator logged into the system maintenance

account. The operator must then:

Allocate the lines to be tested

Boot the VDS (EBSAA for VAX-8200, EZSAA for VAX-8800)

Load EVAAA

ATTACH the DMB32(s)

ATTACH the printer(s)

SELECT the printer(s) to be tested

START the diagnostic

‘

These operations are described in the VAX Diagnostic System User’s Guide.

An example of how to run EVAAA is shown in Example 4-11. Where appropriate, commands for

“different host systems are included.

RUN EZSAA

;

For VAX-8800

ILIA
1

LNO1
LIA
LIA1

select the device for
start the diagnostic

wk B

Load the DMB32 diagnostic
HUB = linked to VAXBI

il %

DS> LOAD EVAAA
DS» ATTACH DMB32 HUB LIA

DS>

DS»
DS>

ATTACH

SELECT

LNO1

LIA LIAD

LIAO

START

2-0CT-1985

Z2Z- EBSAA 9.0-325

DIAGNOSTIC SUPERVISOR.

For VAX-8200

- ¥

;

d &

RUN EBSAA

ER IS 3

=
=

15:36:22

Device Name as appropriate
VAXBI Node ID (hexadecimal)

printer
linked

=
=

Example 4-11

device

tested

LIA

name

test

Starting EVAAA
NOTE

If the machine does not have native VAXBI but uses
an adapter, this must be attached before the
DMB32. For example, on the VAX-8800 the attach

sequence might be:
DS»
DS»
DS

ATTACH
ATTACH
ATTACH

NBIA HUB NBIAO O
NBIB NBIA NBIBO 0
DMB32 NBIBO TXA 4

4-18

4.7.2 Error Messages

If an error is detected during test, the program will output an error message. This may indicate that the

option is defective. Error numbers are interpreted in the diagnostic listing EVAAA.LIS. An example
of an
error message is shown in Example 4-12.
#¥¥wxx®**
Pass

EVAAA

test

System

fatal

FRE¥XXXXE

End

LINE

error
of

PRINTER

subtest

while

system

DIAGNOSTIC
error

testing

fatal

..Aborted program at pass

test

5.6 ***wxxxxs

13-JUN-1985

LCAO:

error

Example 4-12

4.8

SYSTEM

number

08:42:26:64

ERROR

WRITE

¥*¥*xxwx

subtest 0, PC 000003EF.

EVAAA Error Message

USER ENVIRONMENT TEST PROGRAM (UETP)

After the DMB32 has successfully passed the relevant diagnostic tests, the UETP system exerciser should
be run to check for interaction problems between DMB32 and other options.

49 DATA COMMUNICATIONS LINK TEST (DCLT)

If the on-board self-tests detects no faults, DCLT can be used to test the external line.

DCLT 1s a diagnostic program that tests communications links. It is used to isolate errors to the local
communications device, the modem, the physical line, or the remote communications device. Each DCLT

diagnostic is written for the specific option on which it runs, but a DCLT diagnostic can communicate with
any other DCLT diagnostic via a communications link. For this test, the system at each end of the link

must have DCLT loaded and running.
4.10

FIELD REPLACEABLE UNITS (FRUs)

CAUTION
You must wear an anti-static wrist strap connected
to an active ground whenever you work on a system
with the covers removed, or handle the T1012

module.

The T1012 module is supplied in protective antistatic packaging. Do not remove the module from its
packaging until you are about to install it.
There is no preventive maintenance for the DMB32. Corrective maintenance is based on identifying and
replacing a defective FRU. The FRUs for DMB32 are:
®

T1012 module

17-00740-xx ribbon cable

H3033 distribution panel

12-22246-01 transition header assembly

There are six 17-00740-xx ribbon cables on each DMB32 option, but the diagnostics cannot isolate a fault
to a single cable. If a faultis isolated to the ribbon cables, Table 4-4 identifies which cable carries which
set of signals, and can be used to determine which cableis likely to be faulty. Refer to Chapter 1, Table 11 to relate the CCITT circuit numbers given in Table 4-4 to their EIA equivalents.
Table 4-4 Ribbon Cable Signal Distribution
Cable

VAXBI

H3033

Zone

Socket

Signals Carried

C-1

J10

Async: channels 0 and 2: Printer: DAT<2:1>, ONLINE

C-2

J13

Async: channels 1 and 3; Cable Code <3:0>

D-1

J11

Async: channels 4 and 5; Printer: DAT<5>, DAT<3>

J14

Async: channels 5 and 7

J12

Sync: GND, circuit 107, 111, 114; V.10 circuit 104; V.11 circuit

D-2

E-1

108; V.35 circuit 103, 113, 114 115; Printer: DAT<4>, DAT<0>,

DEMAND, STROBE
E-2

J15

Sync: circuit 104, 106, 109 115 125, 142; V.10 circuit 103, 113;
V.11 circuit 103, 105, 113; V 35 circuit 104; Printer: DAT<7: 6:>
CONN DAVFU

Defipending on local maintenance practice, adapter 'cables, extension cables and modems may also be

considered as FRUs.

4-20

4.11

TROUBLESHOOTING FLOWCHART

SYNC PROBLEM

> ASYNC PROBLEM

PRINTER PROBLEM

RUN EVAAA I NOTE: VAX/VMS WILL NOT CONFIGURE THE
]

LINE PRINTER PORT (LIxO) UNLESS
A VALID PRINTER IS CONNECTED

ERRORS

i
YES

|
|

CHECK VAX/VMS
AND PRINTER

SETUP
RUN EVDAK
AND REPLACE
FAILING FRU

PROBLEM

RESOLVED

CONTACT

TECHNICAL
SUPPORT

=
RE1264

4-21

TROUBLESHOOTING FLOWCHART (continued)
VAX/VMS WILL NOT CONFIGURE THE
SYNCHRONOUS PORT (Six0) UNLESS A VALID

NOTE:

ADAPTER CABLE IS CONNECTED

SYNC PROBLEM
CHECK SYNC PORT
| ADAPTER CABLE AND
| S/W DRIVER INSTALLED

THE SYNC
PORT

HAS

VAX/VMS
CONFIGURED

| (SYS$SYSTEM:SIDRIVER.EXE)

RUN EVDAL

(DEFAULT
/SEC = INT)

ERRORS

REPLACE

‘

T1012 MODULE

{NO

RUN EVDAL TWICE,
FIRST WITH H3195,
THEN WITH H3196.
(/SEC = EXT)

‘

CHECK RIBBON
CABLES AND
DISTRIBUTION

ERRORS

l
>

PANEL

AND REPLACE

RS~¢22/RS«§§§ “Hatos | WITHCABLE
b%%zafg%

FAILING FRU

V.24 - H3248

CHECK

USE STANDARD
NETWORK TROUBLESHOOTING
| TECHNIQUES

9
RE1265

4-22

TROUBLESHOOTING FLOWCHART (continued)

ASYNC PROBLEM
RUN EVDAJ
(DEFAULT

/SEC = INT)

REPLACE

ERRORS

T1012 MODULE

CHECK RIBBON

RUN EVDAJ
WITH H3197
(/SEC = EXT)

CABLES AND
DISTRIBUTION

ERRORS

PANEL

CHECK VAX/VMS

AND TERMINAL

SETUP
RUN EVDAK

YES

| CHECK TERMINAL I
|

AND CABLING

‘

PROBLEM
RESOLVED

ERRORS

‘

| CHECK MODEM !

AND CABLING.

\/—1‘
x !“ Y

SET MODEM IN
REMOTE LOOP
RUN EVDAJ
(SEC = MODEM)

RE1611

4-23

TROUBLESHOOTING FLOWCHART (continued)

1
SET FAR-END
MODEM IN REMOTE |}
LOOP. RUN EVDAJ
|

(/SEC=MODEM)

LINE PROBLEM

ERRORS

| | OR FAR-END
|

MODEM PROBLEM

TERMINAL OR

TERMINAL CABLING
PROBLEM

RE1266

4-24

APPENDIX A

GLOSSARY

This glossary defines terms used to describe the VAXBI bus, the BIIC, and the DMB3?2 option.
Adapter

A node that interfaces other buses, communication lines, or peripheral devices to the VAXBI bus.
Asserted
To be
in the “true” state.
Asynchronous
A method of serial data transmission in which data is preceded by a start bit and followed by a stop bit.
The receiver provides the intermediate timing to identify the data bits.

Auto-answer

Facility of a modem or terminal to automatically answer a call.
Auto-flow
Automatic flow control. Method by which the DMB32 controls the flow of data by means of special
characters within the data stream.

Backward Channel
|
Channel which transmits in the opposite direction to the usual data flow. Normally used for supervisory or
control signals.
Base Address

The address of the CSR.
BCI
VAXBI chip interface; a synchronous interface bus that provides for all communication between the BIIC
and the user interface.
BIIC

Backplane interconnect interface chip; a chip that serves as a general purpose interface to the VAXBI bus.
BIIC CSR Space
The first 256 bytes of the 8 Kbyte nodespace, which is allocated to the BIIC’s internal registers. See also
Nodespace.
Bus Adapter
A node that interfaces the VAXBI bus to another bus.

CCITT
Comite Consultatif International de Telephonie et de Telegraphie. An international standards committee
for telephone, telegraph and data communications networks.

A-1

Dataset
See Modem

Deasserted

To be in the “‘false’ state.
Decoded ID

The node ID expressed as a single bit in a 16-bit field.
Device Type

A 16-bit code that identifies the node type. This code is contained in the BIIC’s Device Register.
DIL

Dual-In-Line. The term describes ICs and components with two parallel rows of pins.
DMA

Direct Memory Access. Method which allows a bus master to transfer data to/from system memory
without using the the host CPU.
DMA adapter

An adapter that directly performs block transfers of data to and from memory.
DUART

Dual Universal Asynchronous Receiver Transmitter. IC used for transmission and reception of serial

asynchronous data on two channels.

Duplex

Method of transmitting and receiving on the same channel at the same time.
EIA

Electrical Industries of America. American organization with the same function as CCITT.
EMC

Electro-Magnetic Compatibility. The term denotes compliance with field-strength, susceptibility and static

discharge standards.
Encoded ID

The node ID expressed as a 4-bit binary number. The encoded ID is used for the master’s ID transmitted

during an imbedded ARB cycle.
Even Parity

The parity line is asserted if the number of asserted lines in the data field is an odd number.
FCC

Federal Communications Commission. American organization which regulates and licenses communications equipment.

FIFO

First In First Out. The term describes a register or memory from which the oldest data is removed first.
Floating Address

CSR address assigned to an option which does not have a fixed address allocated. The address is dependent
upon other floating address devices connected to the bus.
A-2

Floating vector
Interrupt vector assigned to an option which does not have a fixed vector
allocated. The vector is
dependent upon other floating vector devices connected to the bus.
FRU

Field Replaceable Unit

GO/NOGO
Test or indicator which defines an ‘error’ or ‘no error’ condition only.
H

;

Designates a high-voltage logic level (that is, the logic level closest to Vcc). Contrast

with L.

IC
Integrated Circuit

Interrupt Vector
In VAX/VMS systems, an unsigned binary number used as an offset into the
system

system control block entry pointed to by the VAXBI interrupt vector contains

control block. The
the starting address of an

interrupt-handling routine. (The system control block is defined in the V.AX-11
Architecture Reference
Manual.)

I/0
Input/Output
L
Designates a low-voltage logic level (that is, the logic level closest to ground). Contrast

with H.

LSB
Least Significant Bit
LSI-11 bus
Another name for the Q-bus

Master
The node that gains control of the VAXBI bus and initiates a VAXBI or loopback
transaction. See also
Pending Master.
Master Port
Those BCI signals used to generate VAXBI or loopback transactions.
Master Port Transaction
Any transaction initiated as a result of a master port request.

Microcomputer
An IC which contains a microprocessor and peripheral circuitry such as memory,
I/O ports, timers, and
UARTs.
Modem
'
The word is a contraction of MOdulator DEModulator. A modem interfaces a
terminal to a transmission
line. A modem is sometimes called a dataset.

Module

A single VAXBI card that attaches to a single VAXBI connector.
MSB

Most Significant Bit

Multiplexer

A circuit which connects a number of lines to one line.
Node

A VAXBI interface that occupies one of smtcen loglcal locations on a VAXBI bus. A VAXBI node
consists of one or more VAXBI modules.
Node ID

A number that identifies a VAXBI node. The source of the node ID is an ID plug attached to the

backplane.

Node Reset

A sequence that causes an md1v1dual node to be mntxahzed mltlated by the setting of the Node Reset bitin
the VAXBI Control and Status Register.

Nodespace

An 8 Kbyte block of 1/0 addresses thatis allocated to each node. Each node has a unique nodespace based

on its node ID.
Null Modem

A cable which allows two terminals which use modem control signals to be connected together directly.

Only possible over short distances.
Odd Parity

The parity line is asserted if the number of asserted linesin the data fieldis an even number.
PCB

Printed Circuit Board

Power-down/ Power-up Sequence

The sequencing of the Bl AC LO L and BI DC LO L lines upon the loss and restoration of power to a

VAXBI system. See also System Reset.
Protocol

Set of rules which define the control and flow of datain a communications system.
PSTN

Public Switched Telephone Network
Q-bus

Global term for a spemflc DIGITAL bus on Wthh the address and data are multnplexed

Q22, Q18 and Q16

Terms used to define 22-, 18- and 16-bit address versions of Q-bus.
RAM
Random Access Memory

RESERVED code
A code reserved for use by DIGITAL.
RESERVED field

A field reserved for use by DIGITAL. The node driving the bus must ensure that all VAXBI lines in the
RESERVED field are deasserted. Nodes receiving VAXBI data must ignore RESERVED field information. This requirement provides for adding functionality to future VAXBI node designs without affecting

compatibility with present designs. Example: The BI D<31:0> L and BI 1<3:0> L lines during the third
cycle of an INTR transaction are RESERVED fields.

Reset Module
In a VAXBI system, the logic that monitors the BI RESET L line and any battery backup mltages and
that initiates the system reset sequence.
Resetting Node The node that asserts the BI RESET L lme
RFI

Radio Frequency Interference
ROM
Read Only Memory

Slave
A node that responds toa transactlon mltlated by a node that has gained control of the VAXBI bus (the

master). -

Slave Port
Those BCI signals used to respond to VAXBI and loopback transactions.
Spllt-speed

Facility of a data communications channel which can transmit and receive at different data rates at the
same time.
System Reset
An emulation of the power-down/power-up sequence that causes all nodes to initialize themselves; initiated by the assertion of the BI RESET L line.
Transaction
The execution of a VAXBI command. The term “transaction” includes both VAXBI and loopback
transactions.

UART
Universal Asynchronous Receiver Transmitter. IC used for transmission and reception of serial asynchronous data on a channel.
UNDEFINED Field

A field that must be ignored by the receiving node(s). There are no restrictions on the data pattern for the
node driving the VAXBI bus. Example: The BI D<31:0> L and BI I<3:0> L lines during read STALL
data cycles and vector STALL data cycles are UNDEFINED fields.
User Interface
All node logic exclusive of the BIIC.

A-5

User Interface CSR Space
That portion of each nodespace allocated for user interface registers. The user interface CSR space is the 8

Kbyte nodespace minus the lowest 256 bytes, which comprise the BIIC CSR space.
VAX Interrupt Priority Level (IPL)

In VAX/VMS systems, a number between 0 and 31 that indicates the priority level of an interrupt with 31
being the highest priority. When a processor is executing at a particular level, 1t accepts only interrupts at a
higher level, and on acceptance starts executing at that higher level.
VAXBI Primary Interface
The portion of a node that provides the electrical connection to the VAXBI signal lines and implements the
VAXBI protocol; for example, the BIIC.

VAXBI Request
A request for a VAXBI transaction from the Master Port interface thatis asserted on the BCI RQ<1:0>
L lines.
VAXBI System

All VAXBI cages, VAXBI modules, reset modules, and power supplies thhat are required to operate a
VAXBI bus. A VAXBI system can be a subsystem of a larger computer system.
VAXBI Transaction
A transaction in which information is transmitted on the VAXBI signal lines.
Window Space

A 256 Kbyte block of I/O addresses allocated to each node based on node ID and used by bus adapters to
map VAXBI transactions to other buses.
XOFF

Control code (23 octal) used to disable a transmitter. Spec:1al hardware or software is needed for this
function.
XON
Control code (21 octal) used to enable a transmitter which has been disabled by an XOFF code.

A-6

Digital Equipment Corporation - Bedford, MA 01730