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Document:	DMB32 Technical Description
Order Number:	EK-DMB32-TD
Revision:	001
Pages:	132
Original Filename:

OCR Text

EK-DMB32-TD-001

DMB32
Technical Description

EK-DMB32-TD-001

DMB32

Technical Description

Prepared by Educational Services
of

Digital Equipment Corporation

First Edition, May 1986

The information in this document is subject to change without
notice and should not be construed as a commitment by Digital

Equipment- Corporation. Digital Equipment Corporation assumes
no responsibility for any errors that may appear in this document.

Using Digital’s networked computer systems, this book was
produced electronically by the Media, Publishing and Design
Services department in Reading, England.

Printed in U.S.A.

The following are trademarks of Digital Equipment Corporation.

dlijoliltlal
DEC

PDP

DECmate

P/0OS

UNIBUS

DECUS

Professional

VAX

DECwriter

Rainbow

VMS

DIBOL

RSTS

MASSBUS

RSX

Work Processor

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DMA Operation........cccccevevnnnn. ereerens ettt eeerenanattereeretaeeetarareenans
VAX-11 Address Translatxon,m.. ........ erennaes eeeeeees
Address Of Buffer.......ocveveviveiiieneirnineneienenenennn. e reerereneeererans
Physical Address of Page Table......ccocovviniiiiininiiiiiiiiiiiiiiiiiii..
System Virtual Address of Buffer..........cocvviiiiiiiiiiniiiiiiiiiiininn.
System Virtual Address of Process Page Table....................
Interrupts............ e eneneaseeieneeaes e eeeererreeeetteeaeteeee
s e ranrenennenan
Synchronous Operation.......ceeeeeveereneeriieieeineeennns
Synchronous Transmit Full DMA File Queue........................
Synchronous Transmit Done DMA File Queue............cooeiiiiinninnn
Synchronous Receive Empty DMA File Queue.................
Synchronous Receive Full DMA File Queue............ccoooiiiiiiinii

FUNCTIONAL DESCRIPTION

CHAPTER 2

»
L

B W N
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M&@NH

Interrupts
to the Host........... e eeeeeeerareeeeerraneaees
HARDWARE OVERVIEW
. ..c.iiiiiiiiiiiiiiiiiieieieeeeieneeeinnnnesennnns
VAXBI Interface (BIIC) . ..cviiiiiiiiiiiiiieriiieiiiiiiieiinnessssissisiesnnsneesenenes
USer INterface....cvviieriiiiiiiinneeiereironnioeerrennsestosssrnssssosssesansesssssnnnees
Data Paths....................
| 311E 1110 ). S PP
CA S R AM . L iiiiiiiiiiiiititretraetiarssesessssstesasaseseennssesannsens ereens
Address Translation Gate Array (ATGA)...ccccvvviiiiiiiiiiiinnnnnnnn.
Control Gate Array (CGA)....vvviiiiiiiiiiiiiiiierennnns ceesessniersresenian
Communications Interface......oovvveviiiiiiiiiiiiiiiiiiniiieiiiiiiiisisiiinneneeene.
Microprocessor............... e eeeteieineereeiiaae
ASYNChronous PoOrtS.....c.ceiiiiiiineiiiiiiieiiiiiiioneriiiiiiiieeeiennnee.
Synchronous Port............ PN :
Printer Port (Parallel Port)....covviiiiiiiviiiiiiiiiiireiiiireieinssseesnaseces
Line Drivers and ReCeIVEIS....vviiiiiiiieiiiiiiiinrsieierereseseciessssssssssnnns
DATA ROUTING.......c.c..........

1-4

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NENESESENES
NSRS RSN SR SN E R SR
e sl N

Programmed (RX FIFO) Asynchronous Reception...........
Programmed (Preempt) Asynchronous Transmission.....................

S BN
— ——

N 610 4 ST
PP
GENERAL OVERVIEW............ ettt aateeeeaneteaaansereenneeaernreeaaareeaaareaaan
Communications INterface......covvveiiriiiiiiiieiiiieiiiiiieiieiiisieietiseeesenns
(876)
115 o) N 000 T4 (TP et ereeirereeeearaaees
Common Address Store RAM (CASRAM)....cvviiiiiiiiiiiiiiiiniiennn.
User Interface................. e eaeeerrerereaareaeaaaes e eebeaeeeseeeeeeteaanns
VAXBI Interface.................... e eteererannenneaeeeeeaen e erereereieeriaaees
T4 13 =)
VAXBI Required Registers.........
BIIC Specific Registers....covuveiiiiiiiiniiiiiiiiiiiiiiiiiiiiiiiiiinieeenne.
User RegiSters...cceeiiinrrirereiiieneerreiinnaneeesns e eeetieeteiiernaae
Types of Data Transfer......cccvviviiiiiiiiiiiiniiiiiiiiiiiiiiiiiiiiine,
DI\ VN B 11 ) (-

GENERAL DESCRIPTION

CHAPTER 1

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RS

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NN ESEEEEEEEEEREER ENENRNENRNERENREJEEJEJEEJEJEJSS.] [ EE RNEEEEEEEEERNENEM]

03 2 O U
| N D IR
2-11

Character S1Z€.....ccovvivieiriiiiiiiineeennnns e eeeeennrereeerarnnnas
Aborting Transmission........... e ettt ettt e tetetete e raarararaaas
IBM BISYNC SUPPORT (SYNC PORT)......c..........
Message Definition.........ccovviiiiiiiiiiiiiinnnnnnnn,
Transparent Mode........ccoovvviivviiinieinnnnnnnn.n.
Block Check..ovviviiiiiiiiiiiiiiiiiiiiiiinneene,

#8565 88

N B W R

D NS ES

2-11
2-11
2-11
2-12
2-12
2-13

Insert SYNC Characters......ceeviieriniiiirennnnens
2-13
PAD CRaracters.
. eeeeeteiiiiiiieeeerisiiesiseessesssssnnssesseseens
(@721
¢ o3 5 gl 1 =1 1 TP 2-13
2-13
ASCII Character Set...uuviiiiierieernrereeereernnnnnssseeeens

L4
&

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S &

) 23 ) 21 O L eereeeeenans
CONTROL....viiiiiiiiiiiineneenns
2-11
ADDR..coiiiiiciieeee
2-11
CRCI....
2-11

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& % B & & & & 2 52 &8 RSB E DS E S EEEEIEEETEEREEESEFES [ ENEEEEEEEEEEREREEEEEEEEE
RN BN

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8588

2-14
EBCDIC Character Set.........
2-15
Aborting a Transmission.......c.ovevvvvveeieeannnns ettt
GENERAL BYTE SUPPORT (SYNC PORT)..evviiiiiiiiiiiiiiiiieieeeeieeeenen 2-15
2-15
General Description..........ccoeevvvveenn.. et ereereeee
et teerataaraaaaaaaanns
2-15
Received Data.....coovviiiiiiiiiiiiiiiiiiiiiireriireenneness
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SYNSEQ ittt
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Start 0f Message (SOM)..ounriiiiiiiiiiii it
2-10
COUNT ..ottt
QSYNC........

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Modem Control Signals......ovevriiiiiiiiiiiiiiiiiiiiiiiiiiiiieeeer
s
PROTOCOL SUPPORT (SYNC PORT)..cccvvvvnniennnnnnns
HDLC/SDLC SUPPORT (SYNC PORT).cciiiiiiiieieieeicinaane,
Message Definition................ e e e eaeeenenaeeeetreeeeeeeeeeerereatasaesinssanannnas
Block Check...... PP
(@1 11:1 ¢ Toi (=) g ) V4 =P
PP PP
Address Bytes................... e ettt e e e e e et et e et et eee et e
earaaaaaanaaees
Aborting
a Transmission.......

Synchronous Buffer Translate Queue......................
Further Information.......ocovvviiiiiiiiiiiiiiiiiiiiiiciecceicneee,
SYNCHRONOUS INTERFACE............ P
PPPP

EEEENEEEEEEEEEEEENEEEE
SRR RS EEEEEEEEESEEEEEEEEESEES

Character SIZ€......vvvvvvreriernnnreensnereeennnnss

%5 & 5

& &8 58S

EFEERTESEETERES L]

Block Check..ovvvviiiviiiiiiiiiiiiiinens
Aborting a Message..........
ASYNCHRONOUS INTERFACE. ...cciiiiiiiiiiiiiiiiiiiiiiieiiisaieaeaeannenns
Speeds................
RNEEENEENERENEEENEENENEENERSEJEJE;SJEJRJE};SJIEJESEES
N (I

£ 8 8 5% % 8 5% %X ERERE S S NFRETEDESSE

TSRS I

EEE R EEEENEEEEESEN]

EEEEEEEEENEEENEEEEENEENREENRENERSEEESENEN]

Speed Selection.....cvviiiiiiiiiiiiiiiiiiiiiiieeeennanens eeeees
Performance..m....” ......................... Ceveeeeenes

DATA TRANSFERS (ASYNCHRONOUS PORT).“..,..,

S R B B

R B

2-16
2-16
2-17
2-17

EE R EEENEEENREEEEEEE
SRS

RS EN

Receive Data....cccoovviiiiiiiiiiiiiiiieieiiiiinennnenns

Transmit Data......... ettt
e e aeree e eeaaaaaees
Interrupts.......cvvvvvnn et eeetetteeeenaneeteeeeeeeereannaraans
J\Y (Y6 15319 B @0 ) 1 18 o )VS
Protective GroUNd. ..oovveeeeriiiiiieierersnueieeseessssnnnnesaeeeees

2-16

R EESE

&8 B S

B EB

EES

SRS

2-18

2-18
2-19

2-20

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TECHNICAL DESCRIPTION

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MEMORY MAPS......ccooiiiiiinn erenees e ereeeeeee e neeentetereteeeeeeeeees

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3-8

ADDRESS TRANSLATION GATE ARRAY (ATGA)..cccivviiiiiiiiiiiiinnenenen..

3-8

3-6

d
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[ 3

3-5
3-6
3-6

Backplane Interconnect Interface Chip (BIIC) .....................................

3-7

Address Translation. ooueeeiiiiiiiiii ittt
er
e ennarererereereeees 3-8
Indexing...... e eeeeenaareeesabateeenrreaaaans e eeereeansieeeesentiaserensniecessse 3-8
FIFO Controllers. ..ouueeiiiiiiiiiiiiiiiiiiieiiiiiiiiirerenseeeennnnaness veeees 39
Inversion of Microprocessor Addresses............ ceeenens ererereieees veeee 3-10
AN
K€ 7N =4
T (- ¢ P rereeea oo 3-10
DATA PATHS............... et ee e eeeeaeaeeeea e eteeetetetetteeettetenteaearaananans 3-11

68000 BUS MULTIPLEXER......... ererrereeeeen eeeerrenaes eeeeeeeaeereeeeeeeenes .. 3-12

68000 MICROPROCESSOR....... R
e erteeretreneeeeerereaeeararaaaas . 3-13
FIRMW
A RE FLOW . ittt
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sanessseaeseseenens 3-13

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3-8

DMB32 Slave Response/ Interpretatlcn .............................................
DMB32 Master Commands.........cccceviiiinnnnnnnnnns e e erereiieieeieaes
VAXBI CORNER.............. e rrreereieae eereeeeeeees e ttetereiteeeeeeeeeeeeraaaaaa,
L3 o Yol QO ) ] 1 )1
COMMON ADDRESS STORE RAM (CASRAM)....cvvvieiiiiiiiiiinnnnnnnns vereens

DMB32 COMMANDS........ eeeen e, e rereerenrannas errrnrnneeneeeee

CONTROL GATE ARRAY (CGA ) iiiiiiiiiiiiiiiiiiiiiiirieiiieeteteteteeneesenns 3-10

e T T

3-1
3-1

CHAPTER 3

L2 L2 Lo o o o Lo o W) W0 L) L Lo L0 L0 Lo 0 L0 L0 L) Lo L L L L0 L0 L) L) L0 L) L) W) W L0 W W W W W

Auto XON/XOFF Operation......cccevviiiiiiiiieiiiiniiiieiaieacinaanns. ceereraes 2-20
Received XON/XOFF CharactersS. ..ooceueeiiieeeiiiesiruessessosesessesessnneesenns 221
Transmitted XON/XOFF Characters.....uuuuuuiierieteeiniiiieeeeeeneennnnnnenens 2-21
PRINTER INTERFACE................. errenans N
.3 |
(0515 214 10 o IR 2-21
| X6} 0 40 12 1181 o 1 2-22

ASYNCHRONOUS PORIS(AR
R E R E R EEEEEEEEENEEREREEEEEEEEEEEEEEREEEEEEEREEEEEEEEEEEREEREEREERSE. 3(“17
SYNCHRONOUS PORI& & ¢ & & 6 & 4 65 B P EEFFES I E S EEE S SRS S E R EE R GRS SRS B R B EEE S E S EE ST S SRR S e 3_17
PRINTER PORT AND DISCRETE I/ O T 3-19
OUTPUT/TTL LEVEL CONVERSION. ..ciiiiiiiiiiiiiiiiiiiieeeeaeen s 3-21
COMMUNICATIONS INTERFACE.......cccocevvvevnn e eteeeeeetesaneateeseesaanans 3-21
Address and Signal Decoding................ e rrernnnrneneaeneeeeeess 3-21
BCI INTERFACE.
... ittt
et tetieteesetetnsteesessesesnssessessensusnnnes 3-24
DMB32 Slave Transactlons ............................................................ 3-26
Slave Read Transaction................ ettt ettt teete ettt et te e
e nas 3-27
Slave Write TranSacCtionN . .uueeeuieteiiieeerriererneeeeeneeeessessssnesennssesnns 3-28
I
E N T T ranSaC
IO . e e steieeeennneensseesennesesssssessssesssseessassssansnnss 3-31
Maintenance Levels......covviiiiiiiiiiiiiiiiiiiiiiiiisiiiiiisessssssssssesessess 3-31
DMB32 Master TranSaCtioN.
. .uueeeuieeeeeieeennitereseeeannessesseeeesnnseseeneees 3-33
Master Write TranSaCtiON. ..oeeeeee ettt eieeeeesieesaearereeeenennannnnns 3-36
Master Read Transaction.................. e aeesenaasossasensansacassssnsennonns 3-36
|IfeY0)
0] oF:1e1 G B 1 s 11 ot 5 (o ) V- TP 3-38
VAXBI INT
R T ransactions. .ocuueeuuieeeteeteeeutnnieeeeerssnnsssereesennnssessesees 3-38
OVERALL CONTROL LOGIC OPERATION AND TIMING.....ovvmeeeeeeenn. 3-40
Microprocessor Write to CASRAM.....ccoviiiiiiiiiiiiiiiiiiiiiiiciiiiiienenenen.. 3740
Microprocessor Read from CASRAM. ....ciiiiiiiiiiiiiiiiiiiiiiiiiineeeeees. 3-41

APPENDIX A IC DESCRIPTIONS
A.l
A.2

A.2.1
A.2.2

L0 73 o 1 A-1
Signals and PInout........ooiiiiiiiiiiiiiiiiiii
i
et A-2

8530 UNIVERSAL SYNCHRONOUS/ASYNCHRONOUS
RECEIVER/TRANSMITTER .....ooiiiiii
et

AN
B -—

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N
N
N
N
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GATE ARRAYS

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B
ADDRESS TRANSLATION GATE ARRAY (ATGA),,,,,, ceretretierirseeeenes B
N Tel0 o1 P Ceeeeereeneenas P Derivation Of CASRAM Addresses‘..,.,.m.‘. ................. . ... B
ATGA Register Overview.............. e ereeeetnnneetetananetrecirasneteieciinsecesaess DB
SIGNAL DESCRIPTION
S . ittt i e eniire e, BCONTROL GATE ARRAY (CGA) . iiiiiiiiiiiiiiiiiiiiiiiniireeeeiiniineeenannans B
N 70 o 1
P B
L =3 o 1=
B
CGA RegiSter OVeIVIEW. .ouiiiiiiiiiiiiiiarateetteeeeiaisessseeeesessesesssssseeresenns B
Signal Descriptions............... ereereres ettt eeeer
e e eeeteeeraaaaaaaees .. B-11

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iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii

1.3
1.4
4.1.5
2

A-5

8536 COUNIER/IIMER ..................................................................... A*IO
Overview . .
‘
A-10
Ihe CPU InterfaCe&i'!iiQ‘iiiiiiiii’i!ii"%iiii‘OQQtDOiitéifl iiiiiiiiiiiiiii * & & & B & & iQA-ll
I/0O Ports......... e e teneracenensenneneanennrenanesnenesneanaeeenennsnneeeneneenes JA-11
(000110010
048 5111
1= o DU A-11
Interrupts.Q'#!i’&"*fii*#'#‘*l&‘i*Qi#**Q*#fib‘3*%#»###%?#?QQ#&’*#"*#%#Q‘QQQ#Q‘QQGl’%#?A*Il
R eglster S eecthni"ti!iCOQQitiltlQ’QQ*QDQQQQ?lfi!ili.!#!iiti!*iiiiii.liiitfii’ittfii'l
1
A 12
Silgna| an d Pilnoutfltil'iiiQ!Qil)i”i!%i!lt‘Q)iii!!li)ltd!)ist.ii)!Iii)”t‘t%itttf} !!!!!!!!! A-14
2681 DUARIitl’tii’Q?i’fitii'ii!%*t‘it QQQQQQQQQQQQQQQQ E 2R 2 BN 3% B Bk R NE NE N R BE BE E NN NE B NN R NE N OBE B B N AN 2 ’i#fi!!it)ritf’tA 15
O VerVIewttt!&i!*’fi*it’f'titt!t!‘tifiQQ‘!!!!O%F"!!I!!!
i
!!!!! 2 3 % B B FE N ETESE B F S F SR TS EERSEEEEEEN A-15

4.1.1
1.2

DI
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GLOSSARY

Title

DMB32 Functional BloCK Diagraml.....ccvvvrereiiiiiiiiiiereeeeieeessirirnsnereeessennns 1-2
Hardware Overview Diagram......civviiiiiiiiiiiiiieiiiiiiieiiiiiinreeersiieinnseeseennns 1-6
DMB32 Overview Diagraml......c.cvvviiiiireriiieiiirtereiaisseertisinsnseseessrsssseenennns 3-2
VAXBI I/0 Address Space......cccvviiiiiiiiiiiiiiiiiiiiiiinneeenns . 3-3
IDA\Y
B2 X Y (515T0)
57281 E: ) o PR
" |
DMB32 ClOCK CIrCUItS. et viiiiittteeerinnrreererssissreereresssesssssnssseeseesesssssranennes 3=7
CASRAM BloCK Diagram.....uueeeieiiiienieiiieiieetrerieeeteeernneeersesernneeerennnes 3-9
Data Paths LoOgIC..vivieiiiiiiiiiiiieiiiiiereeriiernreetreneneereesssencsserscrsnsesceennases 3=11
Multiplexing the 68000 Microprocessor Bus................... e rerneerreeanereennnerans 3-12
DMB32 Firmware FIow Diagram.......cccoevvvviiiiiiiiiiiererieieiineinnnnns. cerreeeeeess 3-14

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Figure No.

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FIGURES
Page

Control of Sync Channel Drivers and Receivers...... e
ete et eeeeeeeeees 3-18
Printer Port and Discrete LogiC....uiviiniiiiiiiiiiiiiiiiiii
i
eiiineeeeannnn 3-20

Title

W
wA
g g mwmmwwg‘»wwmmmm
bo [ I
B
R
R
e I

Data Bus Arrangement — Communications Interface...........cc.ccooevviiiiiiiannn.. 3-22
68000 Microprocessor Bus Address and Signal Decoding...........coeovvvvvviiennnn... 3-23
DMB32 BOIL INterface. .ovvviueeiiiiiiitiiiiiiiieetiriireeeeieseresseeceninssceeessnseeeess 3-24
Control and BCI Interface LogiC...ovvuiiveiiviiiiiiiiiiiiiniiiiirineereeesiseserennnneees 3-25
DMB32 Slave Read Transaction...........c.ccoeevevnnnen.. et eeeraeeteeeiianeeeeaaaaa 3-29
DMB32 Slave Write Transaction.............cceveuvee.n. Ceeeeeenaeeee eeerrreeeeenneeaaae, 3-30
VAXBI IDENT Transaction...ccoveeuueriiereeereeiininnessreeeseesssssnssseeeeecsosanssess 3-32
VAXBI Window Space Write to Mlcreprecesscr I/0 Space P RPPPRP X T |
VAXBI Window Space Read from Microprocessor RAM............ccecviennennn. ... 3-35
DMB32 Master Write Transaction....ccccviiiiieiiienieiiiireeeiineeeeisnsesassssecennees 3-37
DMB32 Master Read Transaction Timing......cccevviiiiiiiieiiiiiiiiieiinerieeerennens 3-39
Busmux Write Transaction Timing......coeviieiiiiiiererireeereinseeeeineresesserennnnens 3-41
Busmux Read Transaction Timing.......c.ooovviviiiiiiiiiiiiiiiiiiieiinrereineseinsecsneses 3-42
68000 ATCHItECIUTIC. tvviiiitteteteeertereiierresseeeseseessssnsnsssesssesesensnsnsessssssnnns A-2
68000 Input/Output SigNaAlS.....ccovvvriiririiiiererineerirerersrrerinsecrsereerneesenssennes A
68000 PinOUL. .cveiiiiiiiiiiiiiiiiiiiiiiieiiieeeissseerseessssessssssessssecsnssessssesansacasss A
8530 ATCHIEECIUIC. . ovuiiiieteiiiineirerineetereineeeeesnseersesneesernsscsssesssesssssessnseses A=
8530 REgIStET SUMIMIAIY . e tttttiiiiiiinererertererersnrenesseeeesesensassassssessessssnasees A
A
8530 PinOUL. e eiiiiiiiiiii it i ittt eirnateretrrrraeeeeiaeaeeeans
O LO-N (ol 4 V1 {-To1 41§- e Y-|
CIO Pinout Details.....c.vvviiiiiiiiiiiiiiiiiiiidiiiireniieiiieeriseseseessseesenensenss..
A-14
2681 Dual Universal Asynchronous Receiver Transmitter...........ccoeeevvvieennnnns A-16
2681 Pinout Diagraml. ..ceiiiiiiiiiiiieiiiiiiiieiiierieissiisssssnssssssssssssssssssssssssases A-17
ATGA Pinout Diagram.....cccvuiiiiueriiinieiiineiineeeriirerernsessseecesnssssnssccsssscesss B2
Representation of Address Translation Functions..................... PP - X
CGA Pinout Diagram..ccceveiriiviieierieeiiiisrereereessserssnseosnseessssasnnssessssenssss B-8

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Figure No.

Page

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TABLES

Title

Page

Maximum Sensible Speeds (Sync Port).....cccoevviviiiiiinvnnnnnn.n. ereeerrennnns cereeee. 276
Synchronous Interchange CirCUItS. ..ovvivreiiiiiiiiiiiiirreriareiinssseeeeennns ceeen 2-7
Supported Speeds (ASYNC POTt) . .iviiiiiiiiiiiiiiitiiiiiiiireeeiiiissseeisersnseerernnnes . 2-17
Redefinition of Conflicting Speeds......vvvivviiriiiiiieiiiiiiiiiieerinneenn. eeeenaen 2-17
Asynchronous Interchange CircuitS.......coevviirvieiiinneiniinneeernneennns. erernneeeens 2-19
Address Latch Truth Table.......covveviiiiiiiiiiiiiiiiiiiiiiiiiiiieiiiiesineenenesenaess 3-13
CGA Decoding of Microprocessor Addresses.......vevvvieviiiiirererireersenseocennsss 3-21
DMB32 Response to VAXBI Commands..........ccevvviiiiiiiininennn. erreesneneeeens 326
68000 Signal DesCriPtionS. . cuvvvirireeriiierirrerrereernreresnserecinseccssnessensneseeeensss A-4
8530 Signal DesCriPtiONS. . evvrevrerreiiiinrererirrreissrsesesssssressssesersnssssssnsseennnees A-8
Counter/Timer EXternal ACCeSsS....cvviriiiiiriiiiriiiieierineiiierereseesssssesessenasss
A-ll
CIO Register SeleCtion.....cvviuiiiieiiiiiniiiiieiiiieiiareeeiiretinseeninseenreseerasecraesee
A=12
8536 RegiSters...cuveiiirrriiiiineereennnnn. e eeereaneeteteraneeeeteaateerearaaaes veeeeennc A-13
8536 Signal DesCriPtion...cvvvireiiiiiiiiiiiiieiiirreeiisiinseerieiassseseesssssscecennness.
A-14
2681 Signal Description....... PP
PP
T £.
ATGA RegISIEr Ma . iiiiiiiiiiiiiiriiiiiiiiitetieirisstteeessssseeerannnsesrsannnes veeeere. B-4
ATGA Signal DescriptionsS...ueieiereeeiierreeeeiireessieseeessreescssssecssssssossssssessasss B=3
CGA Register Map....uviiiiiriiiiiinieriineeieeinneresrssssssessssssesssssssassssesssssessnssss
B=10
CGA Signal DesCriptions....covveveeeiiueeeeriiareeseneesssesssssssessssssssssesssssensessss
B-11

vii

PREFACE

This document gives a functional and technical description of the DMB32 asynchronous/synchronous
multiplexer. It contains information for field service support, and for anyone who needs to know, in detail,
how the DMB32 works.

The manual is organized into three chapters plus appendixes.
Chapter 1
Chapter 2
Chapter 3
Appendix A
Appendix B
Appendix C

— General Description
— Functional Description
— Technical Description
— 1C Descriptions
— Gate Arrays
— Glossary of Terms

The following is a list of related titles.

Document
DMB32 User Guide
DMB32 Field Maintenance Print Set

Number
EK-DMB32-UG
MP-01797-01

CHAPTER 1

GENERAL DESCRIPTION

1.1

SCOPE

1.2

GENERAL OVERVIEW

Chapter 1 provides a general description of the main functions of the DMB32 module. This is followed by
a hardware overview section which provides more information on the functions of the on-board devices.
Two supporting block diagrams are included as an aid to understanding the descriptions.

The DMB32 is an intelligent communications adapter for the VAXBI. The primary function of the
DMB32 is to transfer data between its communications ports and other VAXBI nodes, by the methods
described later in this chapter. The DMB32 communications ports consist of:
e

One synchronous port handling data at up to 64 Kbits per second.

Eight asynchronous ports each handling data asynchronously at up to 38.4 Kbits per second.

One parallel printer port handling up to 1200 lines per minute.

The VAXBI host needs only to make a DMA buffer available, and to program the CSRs, as described in

the DMB32 Users Guide. All other tasks are carried out by the firmware-driven on-board microprocessor
which performs and manages all configuration and data transfer functions and instructs the relevant logic
to do whatever tasks are required. The microprocessor will initiate and manage DMA transfers and will
ensure that the selected communications interface protocols are observed.

Figure 1-1 shows a simplified block diagram of the DMB32 in which the three main functional areas are
identified as follows:

Communications Interface

Control Logic

VAXBI Interface

Data flow is also indicated on Figure 1-1.

1-1

CPU
NODE

MEMORY
NODE

( UP TO SIXTEEN

VAXBI BUS

5 VAXBI NODES

VAXBI! INTERFACE
(PART OF VAXBI CORNER)

VAXBI| REQUIRED REGISTERS
AND BIIC SPECIFIC

BIIC

REGISTERS

ADDRESS
DATA

NODE

__ __ SELECTED

_CONTROL o

CONTROL LOGIC

USER
>

READ/WRITE
N CISTERS

GATE ARRAYS|
LATCHES AND|
REGISTERS

INTERFACE

| ARBITRATION
| AND
DMA LOGIC

INITIATE
DMA
TRANSFERS

ADDRESS

;
AND
CONTROL

B
DATA
ouT

DATA
IN

READ/WRITE

MOVE DATA

STATUS AND
CONFIGURATION

INFORMATION

1 CASRAM

PRINTER
gm fiLes
'

TPRINTER

SERVICE THE PORTS

DATA

SYNC.

\j Y

321{32555‘

INTERRUPT

Rx FIFO
\

__ SYNCHRONOUS
DATA

clO

PRINTER

’

AND
CONTROL

CSRs

INTERRUPT

ASYNC

SYNC
DMA FILES

DMA FILES
AND PREEMP
REGISTERS

L~
— — 1 — =
ASYNCHRONOUS DATA
’

USART

FOUR DUARTS

’
PRINTER

CHANNEL
DATA

PROCESSOR

COMMUNICATIONS
INTERFACE

CHANNEL

ROM AND
RAM

J
RE

Figure 1-1

DMB32 Functional Block Diagram

Communications Interface

1.2.1

This consists of the asynchronous, synchronous, and printer ports under the control of a 68000
microprocessor. The microprocessor has firmware ROM and dedicated scratch RAM. It controls the
VAXBI Interface by a combination of interrupts and polling.
Control Logic

1.2.2

For explanatory purposes, this can be subdivided into two areas of operation:
1.

Common Address Store RAM (CASRAM)

User Interface

1.2.2.1 Common Address Store RAM (CASRAM) - CASRAM is accessed by the VAXBI host, or by
the on-board microprocessor. It contains data buffer areas and most of the CSRs used by the DMB32.
1.2.2.2 User Interface - The interface between the BIIC and the user functions will be called the User
Interface in this manual, to conform with the VAXBI generic documentation. Gate arrays in this block
contain most of the DMB32 logic, and one of the arrays arbitrates between host and microprocessor access
to CASRAM.

The User Interface can respond as slave to commands passed on by the BIIC, or as bus master it can
request VAXBI transfers. VAXBI transfer requests are made to the BIIC, which arbitrates for the bus and
then controls the transfer.
VAXBI Interface

1.2.3

Handling of VAXBI protocol, parity, and the recognition of commands and addresses are all performed by
a VAXBI interface chip (BIIC) on the VAXBI Interface. Valid commands addressed to this node are
passed to the User Interface which can then respond via the BIIC, as bus slave. The BIIC contains registers
whose functions are described in Section 1.2.4.
Registers

1.2.4

The device registers (CSRs) are mapped into CASRAM; however, some are in the BIIC and some are
duplicated in the gate arrays. Device registers can be considered as three groups.
1.

VAXBI Required registers

BIIC Specific registers

User registers

1.2.4.1 VAXBI Required Registers — These are provided on every device (node) that is connected on the
VAXBI. These registers hold status and control information which defines how the DMB32 will respond to

commands on the VAXBI.

1.2.4.2 BIIC Specific Registers — These registers are not required by the VAXBI specification. They
support specific functions implemented by this BIIC. Features selected by the BIIC Specific Registers
include the commands to be implemented by this node.

1-3

1.2.4.3 User Registers — These are the registers through which the device application is controlled. They
can be further subdivided into four groups as follows:
e

General Registers

Used to control parameters and functions common to

the communications interface.
e

Asynchronous Registers

—

Used to control and monitor the asynchronous ports.

Synchronous Registers

Used to control and monitor the synchronous port.

Printer Register

Used to control and monitor the printer port.

- 1.2.5

Types of Data Transfer

The function of the DMB32is to move data between the VAXBI and the communications interface; this
can be achievedin three ways:
1.

DMA Transfer

Programmed (RX FIFO) Asynchronous Reception

Programmed (Preempt) Asynchronous Transmission

1.2.5.1 DMA Transfer - Synchronous RX and TX data are transferred between host memory buffers
and CASRAM by DMA. The microprocessor monitors the buffers, and initiates further DMA transfers as
they are needed. Transfers between CASRAM and the synchronous port are initiated by interrupt from
the synchronous port to the microprocessor.

Printer data is also transferred across the VAXBI by DMA. Transfers of data from CASRAM to the
printer port are performed by the microprocessor. Printer status is polled by the microprocessor, which
also makes status information available in the CSRs.

Asynchronous TX data can be transferred by DMA or by programmed transfer. DMA transfers to
CASRAM are controlled in the same way as synchronous data transfers. The microprocessor monitors the
asynchronous ports to check if they are ready to accept data.
1.2.5.2 Programmed (RX FIFO) Asynchronous Reception — The microprocessor transfers asynchronous
RX data to a 512-character RX FIFO in CASRAM. The host reads the data, from the RX FIFO,
together with error status information. The RX FIFO is also used to send diagnostic reports to the host and
to send modem change information.

1.2.5.3 Programmed (Preempt) Asynchronous Transmission — Asynchronous TX data may be transferred to CASRAM by DMA, or it can be written to a single-character preempt register (one exists in
each asynchronous channel). From there the transfer is completed by the microprocessor. A character
written to the preempt register of a channel which is transmitting a DMA buffer, will be transferred to the
asynchronous port before the remaining DMA data.

1-4

1.2.6

Interrupts to the Host

The DMB32 can be programmed to interrupt a VAXBI host under the following conditions:
e

When a channel is ready for another preempt character.

When transfer of a DMA buffer from system memory to an I/O channel has:

been aborted

been terminated due to a memory read error

—

been successfully completed

When a received character has been placed in a previously empty RX FIFO. (The DMB32 can
be programmed to delay this interrupt so that several characters can be placed in the FIFO
before the interrupt is raised).

When modem status information has been placed in the RX FIFO. This action overrides any
programmed interrupt delay.

1.3 HARDWARE OVERVIEW
The major DMB32 hardware blocks and the buses that interconnect them are shown in Figure 1-2. In this
figure, the three areas of logic are identified for comparison with Figure 1-1. A brief overview of the
hardware is provided in the subsequent sections.

1.3.1 VAXBI Interface (BIIC)
The BIIC is the major functional element of the VAXBI interface. The BIIC provides a standard VAXBI
family interface between the VAXBI bus and the user.
1.3.2

User Interface

The functions of the devices within the user interface are defined as follows:

1.3.2.1 Data Paths - The Data Paths is a data bus multiplexer, Latches in this block isolate the BCI

(VAXBI Chip Interface) and internal data buses. Latching the data allows the DMB32 to meet VAXBI
timing requirements.
1.3.2.2

Busmux - The Busmux is a bus multiplexer and isolator. This group of latches and drivers

multiplexes the microprocessor data and address buses (68000 bus) onto the internal data bus.
1.3.2.3 CASRAM - CASRAM is a 2 K-longword RAM that contains device registers used by both the
VAXBI host and the DMB32 microprocessor to configure and control the DMB32 module. All data to and
from the communications interface is transferred via registers and data buffer areas in CASRAM.

1.3.2.4 Address Translation Gate Array (ATGA) - The ATGA multiplexes primary (VAXBI) and

secondary (microprocessor) addresses for the CASRAM. It also performs address translation functions
such as indexing and FIFO addressing, and 68000 versus VAX-11 addressing convention.

VAXBI BUS

BHC

GNOTORREE

OWOWMSOR

SEORONE

WONIAIGNSE

SUNGRWRSS

ORNNWIRMD

CONTROL

DATA

PATHS

GATE

CONTROL

ADDRESS
TRANSLATION
|ADDRESS
e
=

ARRAY

(ATGA)

RS-

ICOM MUNICATIONS INTERFACE CONTROL

SRR

BRSO

USER
INTERFACE

PRIMARY ADDRESS

INTERNAL DATA BUS
CONTROL
LOGIC

SECONDARY ADDRESS DATA

CONTROL

»|

]

Rva
BUSMUX

68000 BUS

Y
8536

g"&%"é‘

LATCHES

t.* - - »T

MODEM STATUS

LINE

AND CABLE
CODES

DRIVERS
AND

Ao
0TO 7 A

LINE

DRIVERS
AND

| RAM

ROM

DRIVERS | L - —
AND

RECEIVERS | | RECEIVERS |

PRINTER J

STATUS

DUART

|
LINE

F=—=|—=—=— —=— —-———]

y
vy |
v
ax2681 | | | scratch | | Fiamwane

USART

A
0TO7|

v
8530

CIO

NS
fifiggg

PROCESSOR

COMMUNICATIONS

INTERFACE

CONTROLLER

—

| RECEIVERS

COMMUNICATIONS
PRINTER
DATA

SYNCHRONOUS
DATA

ASYNCHRONOUS

CHANNEL

CHANNELS

INTERFACE

DATA
RE183

Figure 1-2

Hardware Overview Diagram

1-6

1.3.2.5 Control Gate Array (CGA) - The bulk of the DMB32 logic is in the CGA. By controlling the
ATGA, the CGA arbitrates between the primary and secondary address ports, allowing only one port to
address the CASRAM at any time. The CGA controls the CASRAM, Data Paths and Busmux, as
necessary to transfer the data.

Some of the control and decoding logic for the microprocessor and the communications interface is
integrated in the CGA.

1.3.3

Communications Interface

The functions of the devices within the communications interface are described in the following sections.
1.3.3.1 Microprocessor — A68000 microprocessor with dedicated ROM and RAM forms the Communications Interface Controller. The controller controls and configures the communications interface in
response to information in device registers in the CASRAM. (Like the DMB32 itself, the ICs that form
the 1/O ports are controlled and configured by access to internal registers).

1.3.3.2 Asynchronous Ports - Eight asynchronous ports are provided by four 2681 Dual Universal
Asynchronous Receiver Transmitter (DUART) ICs. These ICs perform the serial/parallel conversion of

data, generate parity, and provide modem status and control signals.

1.3.3.3 Synchronous Port — The synchronous port uses an 8530 Universal Syncl{roncus Asynchronous

Receiver Transmitter (USART) IC. This IC performs serial/parallel conversion of data, generates and
checks CRC, and provides the modem status and control signals required for the synchronous port.

1.3.3.4 Printer Port (Parallel Port) - The port is formed by an 8536 Counter/timer and parallel I/O
chip (CIO). This IC has three ports, one of which is used for the printer. Other ports support the printer
function, monitor some of the asynchronous port modem signals, and supply a clock to the synchronous
port. Counter/timers in the CIO are used to provide delays, and to alert the microprocessor to tasks that
must be performed at regular intervals.

1.3.3.5 Line Drivers and Receivers — Line drivers and receivers provide circuitry to drive data on a line, |

and to reconstitute received data. In the case of serial data communications lines, line drivers and receivers
convert between TTL levels on the option and EIA levels on the lines. The printer channel is at TTL level
only.

1.4

DATA ROUTING

During DMA transfers, or when the host writes or reads a register, data between the VAXBI and
CASRAM is routed as follows:

WRITE

BIIC - Data Paths - CASRAM

READ

CASRAM - Data Paths - BIIC

Data to or from the I/O ports is routed as follows:

WRITE

BIIC - Data Paths - CASRAM - microprocessor — I/O Port

READ

I/0 Port — microprocessor - CASRAM - Data Paths - BIIC

For each type of transfer, the CGA controls the ATGA, CASRAM, Data Paths, and Busmux, as
necessary.

1-7

CHAPTER 2
FUNCTIONAL DESCRIPTION

2.1

SCOPE

Chapter 2 provides operational information on the facilities provided by the DMB32. The Overview
section contains details of DMA Operation, VAX-11 Address Translation, Interrupts, and Synchronous
Operation; this is followed by a section on compliance with the Electrical Interface Standards. Sections are
also included on Modem Control, DMB32 Protocol Support, HDLC/SDLC Support, DDCMP Support,
IBM Bisync Support, and General Byte Support. Finally, the chapter provides information on the Asynchronous Multiplexer, and the Printer Interface.
2.2

OVERVIEW

The DMB32 module, containing an on-board 68000 microprocessor and firmware, implements a communications controller as described in the previous chapter. The main functions of the DMB32 are to provide
the following communications facilities:

Synchronous Controller handling the following protocols:
e

HDLC/SDLC

[IBM BISYNC

DDCMP

GEN BYTE

Asynchronous Multiplexer for eight lines

Line Printer Interface

The microprocessor is the main controller of the DMB32 but some state oriented control is implemented
by the CGA controlling the CASRAM in particular. All VAXBI bus protocol and control is handled by
the BIIC.
2.2.1

DMA Operation

DMA data transmissions are implemented for synchronous transmission and reception, asynchronous
transmission, and line printer output. DMA operations support both virtual and physical mapping of the
host memory.

In order to use the maximum bandwidth of the VAXBI bus, the DMB32 attempts to use octaword
transfers wherever possible, and achieves this by the use of internal DMA files kept in CASRAM. A
DMA file is used to accept data from the VAXBI on transmit, and to supply data to the VAXBI on
receive. The DMA file holds up to an octaword of data and the relevant physical address within the host
memory buffer.

During the progress of a DMA, the DMB32 does not update the count and address registers, so it is not
possible for the host to track the progress of a DMA via these registers. An exception to this is when the
GEN BYTE protocol is being used in receive messages; for these messages, only the count register is
maintained. The count is a DMA count and because of the nature of the DMA files, at any given time it
may be up to 16 bytes out of date.
2.2.2 VAX-11 Address Translation
The DMB32is able to carry out VAX-11 address translation for use when accessing DMA buffers It can
use one of four modes of address translation as describedin the subsequent sections.

2.2.2.1 Physical Address of Buffer - The DMB32 performs no address translation, but is given the
physical address of the buffer and the length. The buffer must be contiguous in physical memory. This
mode makes no assumptions about the virtual address structure used by the host processor.
2.2.2.2 Physical Address of Page Table - The DMB32 is given the physical address of a page table.
Each entry in the page table is 4 bytes long. The DMB32 is given the offset of the first byte of the buffer
which is in the page described by the page table entry. (This number must be less than 512). Each page
table entry contains bits 9 to 29 of the physical address of the page that is to be accessed. The remaining
high order bits in the page table entry are ignored. This mode allows buffers to be split into several pages.

2.2.2.3 System Virtual Address of Buffer - This mode of address translation uses the VAX Address
Translation Structure, as described in the VAX Architecture reference manual.
The DMB32 is given the system virtual address of the buffer. It then accesses page table entries in the
system (and possibly global) page tables to perform the address translation. A page table entry has the
following format:
e

Bits<20:0>

—

PFN. These bits contain the high order 21 bits of the
physical address to be used to access the page (except
when the PTE indicates that a global page table entry is

to be used).
e

Bits<21:0>

—

Global Page Table Index. When the PTE indicates a
global page is to be accessed, these bits indicate the
index to be used to access the global page table entry.

NOTE
Only one of the above formats will apply at any given
time, as determined by bits 31, 26, and 22.

Bit<22>

This bit, together with bits 26 and 31, indicates the
format of the PTE. The following combinations are
recognized:

22
X

—

valid page

—

valid page

—

use PFN to index global page
table (not valid in an entry in
the global page table).

not valid

)

Bits<25:23>

—

Not used

Bit<26>

See bit 22

Bits<30:27>

—

Protection code. This field is checked to ensure that

kernel mode has access to the page. The field must not
contain O or 1 when the page is to be read by the
DMB32, and must not contain 0, 1, 3,7, 11 or 15 if the
page is to be written by the DMB32. Only one
protection code field is used for any page to be

accessed. This comes from the first PTE that describes
the page. The codes in global page table entries and in
system page table entries, that are accessed in order to
find another page table entry, are ignored.
.

Bit<31>

See bit 22

When the PTE indicates that a global page table entry is to be found, the DMB32 calculates the system
virtual address of the global page table entry by multiplying the index (bits<21:0>) by four and adding the
result to the address of the base of the global page table. The DMB32 reads the PTE which results in
another system page table translation. This second system PTE must not refer to another global page
table, nor must the entry be found in the global page table. At most, one global page table entry is fetched
for translating any page address.

2.2.2.4 System Virtual Address of Process Page Table - The DMB32 is given the system virtual address
of a process page table entry which describes the page containing the first byte of the buffer. The
longwords that follow describe the succeeding pages of the buffer. The format of the page table entries is
the same as in the previous mode. This method allows the DMB32 to directly access process buffers. The
use of the system virtual address allows for the handling of non-contiguous PTEs describing a process
buffer.
|
Address translations using the system page table are necessary to access the entries in a process page table.
If the entry in this table refers to a global page then further PTEs will need to be accessed from the system
page table and the global page tables as described for the previous mode.
2.2.3

Interrupts

There are four interrupt vectors used by the DMB32, these are defined as follows:
e

BIIC error interrupts

Asynchronous Interrupts (Transmit and Receive)

Printer Interrupts

Synchronous Interrupts

2-3

These interrupts are all at the lowest interrupt prmnty on the VAXBI bus. The DMB32 interrupts with a
vector made up in the following way:
e

Bits<l:0>

Bits<5:2>

—~

The Node ID (Node Identifier)

Bits<7:6>

—

The value for the type of interrupt, identified as

follows:
0 — BIIC error interrupts

1 = Synchronous Interrupts
2 — Asynchronous Interrupts
3 - Printer Interrupts

Bit<8>

Bits<31:9>

The use of these interrupts is controlled by four interrupt enable bits (two for asynchronous, one for
synchronous, and one for printer). The error interrupt is controlled by a separate mechanism in the BIIC.

If the appropriate enable bit is set when an interrupting condition occurs, then the DMB32 will interrupt
immediately. If the enable bit is not set then the interrupt will be delayed until the interrupt enable bit is
set. This interrupt may occur even if the interrupt condition has been removed; for example, if the host
empties a FIFO and then sets the interrupt enable bit, an interrupt may be generated with the FIFO
empty.

If the enable bit is cleared after an interrupt request is made by the DMB32, then the interrupt may still
take place; for example, if the interrupt enable bit is cleared while the host is running at an IPL which
would prevent the interrupt taking place. The interrupt may still have taken place when the IPL was
lowered, even if the interrupt condition had been removed and the interrupt enable bit cleared.

If the interrupt enable bit is cleared after an interrupt is requested, but without processing the interrupt
condition, then there may not be a second interrupt if the enable bit is set later. This applies even if the
condition which caused the original interrupt remains; for example, if a FIFO is not emptied but the enable
bit is cleared, then when the enable bit is later set again, there may not be a further interrupt until the
FIFO is emptied and new entries made. This means that the host driver is not able to set the interrupt bit,
and therefore get an interrupt to continue processing the interrupt data, unless it is sure that the interrupt
condition was removed when the enable bit was cleared.
2.2.4 Synchronous Operation
In order to facilitate synchronous communications the host system must first allocate a host memory
buffer. The address and size of this buffer must be then passed to the DMB32 via the appropriate registers
and the appropriate DMA START bit must be set.
Due to the time-critical nature of synchronous communications and use of generally higher transfer
speeds, the synchronous port may be allocated two buffers for transmit and two for receive. This allows the
host system to service one buffer while the DMB32 is transferring data to or from the other. For the same
reasons, the DMB32 allocates two internal DMA files to each synchronous buffer within the host, thus
allowing similar double buffering to take place between the microprocessor and the CGA. To permit the
microprocessor to order these and other tasks, the synchronous DMA files are assigned to different work
queues representing the DMA file state. The following queues are used:

2.2.4.1 Synchronous Transmit Full DMA File Queue — This queue is used to order the transfer of data
from TX DMA files, having been filled with data transferred from the host memory transmit buffers, to
the synchronous communications port.

2.2.4.2 Synchronous Transmit Done DMA File Queue - This queue is used to order the refilling of TX
DMA Files from the host memory transmit buffers, once their contents have been transferred to the

synchronous communications port.

2.2.4.3 Synchronous Receive Empty DMA File Queue - This queue is used to order the presenting of
RX DMA files with valid translated physical addresses, to the synchronous receive process. These files are
then filled with receive data from the synchronous line.

2.2.4.4 Synchronous Receive Full DMA File Queue - This queue is used to order the unloading of the

RX DMA buffers to the host memory buffers once they have been filled by the synchronous receive
process.

2.2.4.5

Synchronous Buffer Translate Queue — This queue is used to submit requests for host buffer

address translation. It is shared by the synchronous transmit and the synchronous receive processes.

2.2.4.6 Further Information — The internal DMA files are pointed to indirectly, via Synchronous File
Status Blocks (SFSBs) which track the contents of the DMA file and the phase of the communications
protocol in use. The SFSBs also point to another status block called the Synchronous Buffer Status Block
(SBSB) which describes and tracks the host memory buffer.

In the case of Synchronous RX DATA the synchronous receive process requests a DMA file from the
Synchronous Receive Empty DMA file queue. This file is empty of data but contains the valid physical
address of the next octaword to be filled in the host memory buffer. The microprocessor fills the file with
16 bytes of data received from the synchronous line. In the case of start or end of buffer, where less than
an octaword transmission is required, the size of transfer is tracked via the SFSB. This information is used
for the byte mask during the VAXBI data cycle. When filled, the DMA file is queued to the Synchronous
Receive Full DMA file queue. The CGA gate array controls the actual DMA of the data in the DMA file,
across the VAXBI bus to host memory. The microprocessor first has to set up the following registers:
1.

DMA File Address Register

This register is found in the ATGA and contains the

VAXBI Command Register

—

This register is found in the CGA. Writing to the

address of the DMA File in CASRAM. The address is
incremented as each longword is transferred.
register causes the corresponding command to be
initiated on the VAXBI bus.

VAXBI Mask Register

—

This register is found in the CGA, and is used by the
microprocessor to indicate which bytes to transfer,
when less than a longword transfer is required.

The CGA indicates the status of the transfer to the microprocessor via its VAXBI Status register. Having
completed the DMA the CGA indicates this to the microprocessor. The empty DMA file, after being
loaded with a valid host memory physical address, is passed back to the Synchronous Receive Empty
DMA file queue ready to accept more synchronous receive data.

2-5

The synchronous transmit procedure is similar to that of the receive procedure. This time the address of an
empty DMA file, with a valid host memory transmit buffer physical address written into it, is loaded into
the DMA file Address Register. Where necessary, the VAXBI mask bits are loaded into the VAXBI Mask
Register and the appropriate command is loaded into the VAXBI Command Register. The CGA controls
the DMA of data from host memory into the DMA file. When this transfer is complete the microprocessor
places the full DMA file in the Synchronous Transmit Full DMA file queue. The synchronous transmit
process can now service this queue, transferring data from the DMA file to the synchronous line. TX

DMA files, when empty, are now passed to the Synchronous Transmit Done DMA file queue for re-use.

The use of two DMA files per host buffer will allow the CGA to be filling or emptying one file while the
microprocessor services the other.

2.3 SYNCHRONOUS INTERFACE
Electrically and mechanically, the T1012/H3033 synchronous port is:
e

Compliant with RS-232-C, RS-422-A/RS-449, V.11, X.27 and V.35

Compatible with RS-423-A/RS-449, V.28/V.24, V.10 and X.26

The maximum sensible speed that can be used on the sync port depends on the protocol and electrical
interface standard selected. Table 2-1 lists the maximum sensible speeds for all the supported protocols.
The maximum total throughput for the sync port is 16000 char/s.
Table 2-1

Maximum Sensible Speeds (Sync Port)

Electrical Interface Standard

Protocol

RS-232

RS-423

RS-422

V.35

DDCMP

19200

Data rate

HDLC

19200

64000

48000

(Bits/s)

BISYNC

9600

GEN BYTE

9600

2.4 MODEM CONTROL (SYNC PORT)
Modem status changes are reported by an interrupt. Since there is no indication of which bits have
changed, the host is expected to keep a record of the last modem status it saw. This will enable the host to
~identify which bits have changed. There are two special modem control bits which show whether or not the
receive and transmit clocks are working. If no transition is detected on any clock line from the modem for
1 second, the appropriate modem control bit is cleared. When one of these bits is cleared, any transfer in
the corresponding direction will terminate with an error indication. Other modem state changes can also
affect transfers; for example, loss of DCD or DSR will abort a received message, and loss of DSR or CTS
will abort a transmission. If the host drops DTR or RTS during a transmission, the DMB32 will not drop
the corresponding signal to the modem, until the message and trailing pads have been transmitted.

2.4.1 Modem Control Signals
Table 2-2 lists the interchange circuits which are supported for the synchronous port on the DMB32.
The state of the modem status lines is sampled at 10 ms intervals and compared to the last reported state.
If there has been a change of state the line status register is updated. Ring Indicator signal (Circuit 125) is
monitored over a period of 30 ms, and a change recorded only if the state of the signal has been constant
over this period.

2-6

Table 2-2

Synchronous Interchange Circuits

EIA RS-449
Signal Name

EIA RS-232-C
Signal Name

CCITT V.24
Signal Name

Shield

Signal Ground

Protective Ground

Signal Ground

102

Send Common

Receive Common

Terminal In Service

—~

—

Signal Ground

Incoming Call

Ring Indicator

125

Calling Indicator

Terminal Ready (+)

Data Terminal Ready

108/2 Data Terminal Ready

Terminal Ready (—)

Data Mode (+)

107

103

Data Mode (-)

Send Data (+)

Send Data (—)

Received Data (+)

Received Data(—)

Terminal Timing (+)

Terminal Timing (-)

Send Timing (+)

Terminal Timing (—)

Receive Timing (+)

Receive Timing (—)

Request To Send (+)

Request To Send (—)

Clear To Send (+)

Clear To Send (—)

Receiver Ready (+)

Receiver Ready (—)

Signal Quality

Data Set Ready
Transmitted Data

Received Data

Transmitter Signal
Element Timing (DTR
Source)

Transmitter Signal

Element Timing (DCE
Source)

Receiver Signal
Element Timing

Request To Send

Clear To Send
Received Line Signal

Detector

Signal Quality

Detector

104

113

114

115

105

106

109

110

New Signal

Signaling Rate Selector

Data Signal Rate
Selector (DTE Source)

111

Signaling Rate
Indicator

Data Signal Rate
Selector (DCE Source)

Data Set Ready

6
-

Transmitted Data

2
-

Received Data

3
-

Transmitter Signal
Element Timing (DTR
Source)

Transmitter Signal

Element Timing (DCE
Source)

Receiver Signal
Element Timing

17
-

Request To Send

4
-

Clear To Send

5
-

Data Channel Received

Line Signal Detector

8
-

Data Signal Quality
Detector

21
-

Data Signaling Rate
Selector (DCE Source)

23
-

Local Loopback

141

Local Loopback

Remote Loopback

140

Remote Loopback

Test Mode

142

Test Indicator

Select Standby

Standby Indicator

2-7

2.5 PROTOCOL SUPPORT (SYNC PORT)
The synchronous controller will support message framing and CRC generation and checking of the
following protocols:
e

HDLC/SDLC

DDCMP

IBM BISYNC

Error recovery, message sequencing, and retransmission are not performed by the DMB32. Software
assistance is required to implement the full protocols.
Other byte oriented protocols can be supported by the GEN BYTE protocol. This allows the DMB32 to
receive and transmit messages in other protocols, but software is required for all intelligent interpretation
of their contents.

The synchronous line is capable of running at 64 Kbit/s (full duplex) for HDLC and SDLC protocols only.
For DDCMP it will run at 19.2 Kbit/s. Other protocols are capable of running at 9600 bit/s.
2.6 HDLC/SDLC SUPPORT (SYNC PORT)
The DMB32 supports HDLC/SDLC protocol message framing. No error recovery or message sequencing
is carried out without software help.

2.6.1 Message Definition
An HDLC/SDLC message is a frame consisting of a sequence of bits preceded by a flag character
(01111110) and followed by either a flag character or a 7-bit abort sequence (1111111). The bits between
these delimiters are the data followed by the block check characters.
To prevent bit patterns in the data stream from being wrongly interpreted as flag characters, the data is
transparently encoded by inserting an extra ‘0’ bit following each ‘11111’ sequence found in the data to be
transmitted.
|
On reception, these inserted ‘0’ bits are removed. This bit stuffing and stripping is carried out by the
DMB32. Only messages which are a multiple of the character size long are legal. If the final flag is not on
a character boundary then an error is indicated.
The block check is normally found in the final bits of the frame; however, if the frame is terminated by an
abort sequence then there is no block check sequence in the frame. After the transmission of the closing
flag of a frame, the DMB32 can either send further flag sequences or a continuous mark, depending on the
state of the IDLE.SYNC bit.

At least one flag will be transmitted before a message, this flag can be the same flag that closes the
previous message. Messages must have at least two data characters. If a shorter message is received it will
be discarded.
~

2.6.2 Block Check
The block check is normally CRC-CCITT, but the following block checks can also be specified:
e
e

CRC-CCITT preset to 1s
No block check - no block check is transmitted, but one can be included at the end of the

buffer if an alternative block check is desired.

2-8

2.6.3

Character Size

2.6.4

Address Bytes

Only the eight bit character size can be spcmfled for HDLC/SDLC

If the device is set up as a secondary station then the first one or two bytes of a message are inspected to
determine if they match the station address, in ADDRESS1 and ADDRESS?2. If they do not match then
the received message is ignored and the receiver waits for the next message.

The address match procedure is not the same for SDLC and for HDLC. SDLC only uses one-byte
addresses; the first byte of the message is compared with the first byte of the address. The all stations
address (11111111) is also recognized as an address match.

HDLC can use one- or two-byte addresses. The low bit of the first address byte indicates whether one- or
two-byte addresses are used. If this bit is a ‘0’, two-byte addresses are used. If it is a ‘1’, then one-byte
addresses are used. The appropriate bytes of the message are compared with the address bytes provided by
the host. The all stations address (11111111) is also recognized as an address match.
The ADCCP protocol can also be implemented using HDLC mode. ADCCP allows more than two bytes
of address. In this case the DMB32 checks the first two bytes, further bytes are checked by the host.
2.6.5

Aborting a Transmission

If the host aborts a transmission after the first byte has been passed to the USART, and before the final
flag has been transmitted, then the DMB32 will transmit an 8-bit abort sequence (11111111) to abort
transmission. A transmission may also be aborted if some error is discovered while transmitting a message;
for example, memory error or transmit underrun condition.
2.7

DDCMP SUPPORT (SYNC PORT)

The DMB32 supports the framing of DDCMP messages, valid start of message recognition, and CRC
generation and checking. Software is required to support error recovery, message sequencing, and
retransmission.

2.7.1

Message Definition

The DMB32’s interpretation and actions with regard to the structure of a DDCMP message are described
as follows:

2.7.1.1 SYNSEQ - A number of SYNC (synchronization) characters (96,¢) precede a DDCMP message. The DMB32 will accept abutting DDCMP messages that have no synchronization characters
separating them, provided that no error has been detected and the QSYNC bit in the previous message is
clear. The DMB32 will normally attempt to send abutting messages.

If a message that has the QSYNC bit set is sent, the DMB32 will send at least four synchronization
characters following the message. If no message is available for transmission abutting a message with
QSYNC clear (or the value in LPR1 is not zero), then at least 8 synchronization characters will be sent
between messages. If any transmit error is detected; for example, memory error, or transmit underrun,
then at least eight synchronization characters will be sent before the next message. The DMB32 will
always send at least the number of synchronization characters specified in LPR1.

2-9

DDCMP requires that eight synchronization characters are transmitted before the following messages:
e

Maintenance messages (starting with DLE)

Messages with the SELECT bit set

Messages with a change in the ADDR field

Control messages other than ACK

Any message after starting up

Any message after idling mark

The first message after receiving a NAK

Messages with a change in the ADDR field

The DMB32 does not automatically send these synchronization sequences for the first five classes listed.
The host is required to set the number of synchronization characters in LPR1 before initiating transmission. The DMB32 will force an eight byte sequence in the last two classes.
The DMB32 will not send PAD characters after a message if the next message abuts the first or is
separated from it by exactly four synchronization characters (due to QSYNC being set).
2.7.2 Start of Message (SOM)
A single character indicates the start of a DDCMP message. This character must be one of the following
valid DDCMP start of message characters:

SOH (81;4) - Data Message

ENQ (054) - Control Message

DLE (90,4) - Maintenance Message (MOP)

The start of message character is transferred to memory on a received message.

If the first character of the message is not one of the valid starting characters then the DMB32 will resynchronize, looking for a new SYNC character.
2.7.2.1 COUNT - This is a two byte field which indicates the number of characters in the data field of
the message. Only the bottom 14 bits of this word are used as the count; the high order two bits are the
control flags QSYNC and SELECT. The two bytes are transferred to memory on received messages. In a
control message there is no data field and therefore no COUNT is required. In this case the count field
contains control information.

2.7.2.2 QSYNC - This flag is bit six of the second byte of the COUNT field; it indicates that the next
message will not abut this message. On transmission, the DMB32 uses the contents of the bit to check if it
must insert SYNC characters between messages. On received messages the DMB32 uses the bit to check
if it must re-synchronize at the end of the message.
2.7.2.3 SELECT - This flag is used in DDCMP to control line turn around in half duplex working. The
DMB32 does NOT use this bit.

2-10

2.7.2.4 CONTROL - This field contains two bytes of control information on control messages. On
received messages, the DMB32 will just transfer these bytes to memory.
2.7.2.5

ADDR - This field is one byte in length and is used in DDCMP multi-point operation, however

the DMB32 does not support DDCMP multi-point operation.

2.7.2.6 CRC1 - This field is two bytes in length containing CRC-16 information for the message header:
SOM, COUNT, CONTROL, and ADDR. This field is not transferred to memory on receive messages
and 1s generated by the DMB32 on transmit messages. On received messages if this CRC is incorrect,
reception is terminated and re-synchronization takes place.
2.7.2.7

DATA - This field contains COUNT bytes of data that are transferred to memory on receive

messages. This field is not present in a control message that is started by an ENQ character (05,¢).
2.7.2.8 CRC2 - This field contains two bytes of CRC-16 data for the DATA field that is not transferred
to memory on receive messages. The DATA field is not present in control messages.
2.7.2.9 PAD - The PAD field consists of a number of DEL bytes (FF,4) which are transmitted following
the final CRC. The DMB32 accepts messages that do not have these bytes. The DMB32 always transmits
two PAD characters after a message. This field is not transferred to memory on received messages. If the
character following the last byte of the last CRC in a message is not a DEL, DLE, SOH, ENQ or SYN
then the last CRC is regarded as being invalid and re-synchronization takes place.
2.7.3 Character Size
The only character size allowed is 8.

2.7.4 Aborting Transmission
DDCMP does not allow a transmitter to abort transmission. If it is necessary to abort a transmission, for
example, if a memory error occurs, then the DMB32 will transmit CAN characters (18,¢) until three
characters after the following CRC would have been sent. This is likely to cause a CRC error to be
detected by the other receiver. Following this it will send at least eight further synchronizing characters
before the next message, to allow the other receiver to re-synchronize.

2.8

IBM BISYNC SUPPORT (SYNC PORT)

2.8.1

Message Definition

The message defined here is the unit of transmission that is contained in one buffer, and does not
correspond with the definition of a message used in the description of IBM BISYNC.

A message starts with the first non-synchronizing character, and continues until one of the following
sequences is recognized:
e

ENQ

ACKO

ACKI

NAK

WACK

RVI

TTD

EOT

ETB + block check

ETX + block check

The DMB32 assumes that the data in a transmit buffer is a complete message, and thus does not check
that the message ends with one of the above sequences.
When a message is received, the DMB32 automatically starts searching for a new synchronization
sequence.

2.8.1.1 Transparent Mode - It is not possible to transmit certain control characters in a message. If
binary data is being transmitted, a transparent mode must be used to enable these characters to be sent.
Transparent mode is indicated by the sequence DLE, STX in the message. Once this sequence has been
seen, the characters that follow are in transparent mode, until a block check sequence is received.

In transparent mode a DLE has to be transmitted before any of the following characters:
e

ETB

ETX

SYN

ENQ

DLE - to allow DLE to be part of the message

ITB

Control characters received without the preceding DLE are assumed to be part of the text of the message.
The DMB32 will transfer these DLE characters to the buffer that the host provides, on reception, and
expects them to be in the transmit buffer. DLE characters are included in the block check.
Following a DLE, ITB, block-check sequence, non-transparent mode is entered. Normally a DLE, STX
will be received which will return the DMB32 to transparent mode.

2.8.1.2 Block Check - Either VRC/LRC or CRC-16 are normally used with IBM BISYNC.
VRC/LRC is normally used for ASCII, and CRC-16 for EBCDIC. The DMB32 will support either block
check sequence for ASCIIL. If VRC is specified then 7-bit characters must also be specified. 8-bit
characters must be specified with CRC-16.
|
The DMB32 will commence calculating the block check for a message, after it sees the first STX or SOH
character. This character is not included in the block check. Other characters not included in the block
check, are those preceding the STX or SOH.

2-12

The block check is inserted in transmitted messages and checked in received messages after the following
characters; the character is included in the block check.
)

ETX

)

ETB

)

ITB

ITB characters are used to separate records within one message. Each record has its own block check. If
any of these checks fail in a received message, a block check error is indicated to the host.
On transmission, the VRC/LRC block check character is followed by two PAD characters, and if a PAD
character is received it will be discarded. On reception, the block check characters are transferred to
memory. On transmission, the host is expected to insert dummy characters in the buffer, and these are
replaced by the calculated block check, unless the block check mode specifies that a block check is not
required.

2.8.1.3 Inserted SYNC Characters - SYNC characters can be embedded in messages. These characters
are not included in the block check and are ignored when they are received. The DMB32 will insert a
SYNC sequence whenever the transmission has been in progress without a SYNC for more than 1 second.
Note that SYNC sequences in transparent messages are formed by the combination DLE SYN, and for
normal messages by SYN SYN.

At least three SYNC characters are transmitted Qbefere each message to ensure that the receiver is

synchronized. This value is taken from NUMBER.SYNC in LPR1. This is normally set to three for IBM
BISYNC by the host.

2.8.1.4 PAD Characters - A PAD character is transmitted after every message. This character is FF ¢,
and it is sent to ensure that data is passed to the modem before it turns the line round (BISYNC normally
operates in half duplex mode). The DMB32 will ignore a PAD character following a message.

2.8.1.5

Character Sets - IBM BISYNC can work in either ASCII or EBCDIC, selected by a bit in the

2.8.1.6

ASCII Character Set — The following control character sequences (in hexadecimal) are used in

line parameter register (6-bit transcode is not supported by the DMB32). The control characters used by
BISYNC depend on which character set is selected.

ASCII mode:
e

SYN- 164

ENQ-05

STX -02

SOH - 0l

ETB-17

EOT - 04

ETX -03

2-13

NAK - 15

ACK - 064

ITB- 1F4

ACKO - DLE, 30

ACKI - DLE, 314

WACK - DLE, 3B

DLE - 10,

RVI-DLE, 3Cq

TTD - STX, ENQ

BEL - 07

The character size must be seven with VRC checking, or eight without VRC checking.
2.8.1.7 EBCDIC Character Set — The following character sequences (in hexadecimal) are used in
EBCDIC mode:
e

SYN-32

ENQ- 2Dy

STX - 02

SOH - 014

EOB/ETB - 264

EOT -37

ETX -03

NA
- 3D,
K

ACK - 2E

ITB- IF,

ACKO - DLE, 70,

ACKI - DLE, 61

WACK - DLE, 6B

2-14

DLE - 1044

RVI-DLE, 7C

TTD - STX, ENQ

BEL - 2F

The character size must be eight.

2.8.1.8 Aborting a Transmission — If the host aborts a transmission after the first byte has been passed to
the USART, and before the final character has been transmitted, then the DMB32 will transmit an ENQ
sequence (DLE ENQ in transparent mode) to abort the transmission. A transmission may also be aborted
if some error is discovered while transmitting a message; for example, memory error or transmit underrun
condition.

2.9

GENERAL BYTE SUPPORT (SYNC PORT)

2.9.1

General Description

The GEN BYTE protocol is provided as an aid in using protocols that are not directly supported by the
DMB32. It allows the host to receive and send arbitrary synchronous characters.

2.9.1.1 Received Data - Once synchronization is established, using the synchronization character specified by the host, all received characters are transferred to memory. Embedded synchronization characters

can be transferred or ignored, as desired by the host. Block check is calculated on all characters transferred
to memory. A transfer terminates at the end of the buffer, when the optional match character is detected
or when some error is detected; for example, modem status error, or memory error. The host is expected to
do the analysis of message structure from the characters received in the buffer, the DMB32 does little
more than transfer them into memory.

The byte count field in RXBUFCT(1/2) is updated after every DMA. This enables the host to determine
how many characters have been received while a message is being received, thus allowing the host to
process messages before the host buffer is filled up. This is useful because there are many protocols for
which the DMB32 is not able to determine the end of message itself.

Because of the use of internal DMA files by the DMB32, a DMA transfer will normally take place when
sufficient characters have been received to cross an octaword memory boundary. This means that the
DMA byte count will often be up to 16 bytes behind the actual received characters. Due to internal
buffering the DMA byte count can be up to 322 bytes out of date.

2.9.1.2

Character Size — If VRC is not specified then a character size of 6 or 8 is selected. If VRC is

specified then character size of 7 is selected.

NOTE

If VRC/LRC is specified as the block check then a
parity bit will be added to all characters transmitted.

2-15

2.9.1.3

Block Check - The following block checks are supported:

No block check - 6, 7, 8 bits per character only

CRC-16 - 8 bits per character only

VRC even - 7 bits per character only

VRC odd - 7 bits per character only

VRC/LRC even - 7 bits per character only

VRC/LRC odd -7 &bits per character iny

2.9.1.4 Aborting a Message — If a transmission is aborted then either mark or SYNC characters will be
sent, according to IDLE.SYNC.

2.10 ASYNCHRONOUS INTERFACE
The DMB32 implements an 8-line asynchronous multiplexer, with split speed and full modem control
capabilities. The following formats are supported in half duplex or full duplex modes:
e

| start bit

5,6, 7 or 8 Data bits

Odd parity, even parity, or no parity

I, 1.5 or 2 stop bits

Electrically and mechanically, the T1012/H3033 asynchronous ports are:
e

Compliant with RS-232-C

Compatible with V.28/V.24

The T1012 module is also compliant with RS-423-A, V.10 and X.26, but the H3033 is not, due to pin
limitations on the 25-way D-type connector.
Half duplex operation is only supported on systems using coded link control, because the DMB32 does not
support the secondary transmit and receive signals which are often used for link control. The asynchronous
ports are implemented using DUARTS and are associated in the following manner:
e

Ports 0 and 1 use the same DUART

Ports 2 and 3 use the same DUART

Ports 4 and 5 use the same DUART

Ports 6 and 7 use the same DUART

2-16

2.10.1 Speeds
Split speed operation, using different transmit and receive speeds, is supported on the DMB32 asynchronous ports. The supported speeds are given in Table 2-3.

Table 2-3

Supported Speeds (Async Port)

Speed (bit/s)
50
75
110
134.5
150
300
600
1200
1800
2000
2400
4800
7200

Groups
A
B
A and B
A and B
B
A and B
A and B
A and B
B
B
A and B
A and B
A

9600
19200
- 38400

A and B
B
A

2.10.2 Speed Selection
The transmit and receive speeds selected for both ports sharing a DUART must be contained in the same
group (A or B). If the transmitter and receiver of a port are configured in conflicting groups, then the
group of the receiver will be used. If two ports sharing a DUART are configured in conflicting groups,
then the group of the most recently configured channel will be used.

Certain speed combinations are not valid. Any speed combination that requires a speed from the group 50,
7200 and 38400 and also a speed from the group 75, 150, 1800, 2000, 19200 on the same DUART is not
valid. If the speed group of a port is changed by configuring a partner port in a conflicting group, then the
new speed of that port is redefined as shown in Table 2-4.

Table 2-4

Redefinition of Conflicting Speeds

Previously Selected
speed (bit/s)

New Speed
(bit/s)

50
75
150
1800
2000
7200
19200
38400

735
50
200
7200
1050
1800
38400
19200

2.10.3 Performance
|
Each asynchronous channel is capable of full-duplex operation at data rates of up to 38400 bits/s.
However, the DMB32 cannot support eight channels operating at 38400 bits/s at the same time. The total

maximum throughput of the DMB32 is around 21000 characters per second (eight data bits with start and
one stop bit), including all characters transmitted and received on the synchronous line and the printer
port.

If congestion occurs, the DMB32 will give priority to the synchronous line, followed by the reception of
async characters.
‘
The individual maximum throughput for each async port is 1000 char/s.

2.11

DATA TRANSFERS (ASYNCHRONOUS PORT)

2.11.1 Receive Data
After characters have been assembled into a parallel form, as defined by the port characteristics, they are

merged with the port number and any error status bits, and put into a 512-character FIFO. This can be
read by any processor on the VAXBI bus.

If at any time both the received character FIFO and the DUART’s internal FIFO become full, then new
received characters are discarded until the congestion is relieved. If this happens, the DMB32 purges the

DUARTs: internal FIFO and then inserts a null character with an overrun error in the received character
FIFO. When this is completed, the DMB32 resumes normal operation on that line.
The FIFO is also used for passing modem status information and diagnostic messages to the host.

2.11.2 Transmit Data
Transmit data is handled by the DMB32 either by DMA buffers or by loading single characters direct into
the DMB32 by the host.
~
When using DMA buffers, the host passes a descriptor to the DMB32 for the start of a buffer which is to
be transmitted. The DMB32 transmits the buffer and, if enabled, interrupts the host when the last
character has been sent. The DMB32 translates addresses using page tables as previously described. DMA
output can be terminated prematurely by use of the transmit DMA abort bit in the line control register.
Asynchronous transmit DMA, uses internal DMA files in a similar manner to the synchronous port, but

because the latency of the asynchronous operation is not as critical, DMA file queues are not used.
In the single-character mode, one character at a time is transferred to the DMB32. This character will be

transmitted as soon as possible, having priority over those characters in DMA buffers. This is called a
PREEMPT transfer.

2.11.3 Interrupts
The host can be interrupted on any of the following conditions, assuming the appropriate interrupt enable

bit is set :
e

The single character buffer has become empty.

A DMA buffer previously passed to the DMB32 has completed (the last character has been
transmitted).

A DMA buffer previously passed to the DMB32 has been aborted by the host and the abort is
now complete.

2-18

A DMA buffer previously passed to the DMB32 has been terminated due to a memory read

error (nonexistent memory, memory parity error, or invalid PTE).

The received character FIFO has at least one character in it after a transition from the empty
state.

The DMB32 has two interrupt control bits associated with the asynchronous lines; one enables the host to
be interrupted (TX INTERRUPT ENABLE) on the first five conditions in the above list, and the second
(RX INTERRUPT ENABLE) allows interrupts on the sixth condition . The receive interrupt can be
delayed to allow more efficient processing by the host.

The received character FIFO data assembled in the receive FIFO includes modem status change information, and diagnostic data, in addition to actual received characters.
2.11.4

Modem Control

Table 2-5 lists the interchange circuits which are supported for each of the asynchronous channels on the
DMB32.

Table 2-5
EIA RS-449
Signal Name

Asynchronous Interchange Circuits

EIA RS-232-C
Signal Name

CCITT V.24
Signal Name

Pin
-

Shield

Protective Ground

Signal Ground

102

Send Common

—

Receive Common

—~

Terminal In Service

Incoming Call

Ring Indicator

125

Terminal Ready (+)

Data Terminal Ready

Terminal Ready (—)

Data Mode (+)

Data Mode (-)

Send Data (+)

Send Data (—)

Received Data(+)

Received Data(—)

Terminal Timing (+)

Terminal Timing (=)

Send Timing (+)

- DB

Terminal Timing (-)

Receive Timing (+)

Receive Timing (-)

Data Set Ready

Transmitted Data
Received Data

Transmitter Signal

Element Timing (DTR
Source)

”
Transmitter Signal

Element Timing (DCE
Source)

Receiver Signal

Element Timing

2-19

Signal Ground

—

Calling Indicator

108/2 Data Terminal Ready

107

103

104

113
|

114

115

Data Set Ready

6
-

Transmitted Data

2
-

Received Data

3
-

Transmitter Signal

Element Timing (DTR
Source)

Transmitter Signal

Element Timing (DCE
Source)

Receiver Signal

Element Timing

17
_

Table 2-5
EIA RS-449

Signal Name

Asynchronous Interchange Circuits (continued)
EIA RS-232-C

CCITT V.24

Signal Name

105

106

109

Request To Send (+)

Request To Send (-)

Clear To Send (+)

Clear To Send (-)

Receiver Ready (+)

Request To Send

Clear To Send

Received Line Signal

Detector
RR

Receiver Ready (-)

Signal Quality

Request To Send

Detector

110

Clear To Send

5
-

Data Channel Received

Line Signal Detector

Signal Quality

8
-

Data Signal Quality

Detector

New Signal

Signaling Rate Selector

Data Signal Rate
Selector (DTE Source)

111

Signaling Rate
Indicator

Data Signal Rate
Selector (DCE Source)

Local Loopback

141

Remote Loopback

140

Remote Loopback

Test Mode

142

Test Indicator

Select Standby

Standby Indicator

Data Signaling Rate
Selector (DCE Source)

Local Loopback

2.11.5 Protective Ground
EIA Circuit AA (Protective Ground) is also supported. There is no CCITT equivalent
of this circuit. A
wire link (zero ohm resistor) on the distribution panel PCB (H3033) can
be removed to disconnect the
protective ground.

The state of the modem status lines is sampled at 10 ms intervals and compared
with the last reported
state. If there has been a change of state, the line status register is updated. If the
port is configured for
modem control operation (LINK.TYPE = 1) the new line status information is
also loaded into the
received character FIFO. The Ring Indicator signal (Circuit 125) is monitored over
a period of 30 ms, and
a change is recorded only if no change has been detected in the signal over this period.

2.11.6 Auto XON/XOFF Operation
The DMB32 can be programmed to automatically respond to, and issue, XON and
XOFF codes. This
facility is individually selectable on a per-channel and responding or issuing
basis

2-20

2.11.7 Received XON/XOFF Characters
When enabled, the DMB32 will stop transmitting data on any channel for which an XOFF has been
received; transmission will resume when an XON character is received. The maximum number of
characters, excluding XON/XOFF, characters which will be transmitted following the receipt of an
XOFF, is three characters. This provides the following features:

Reduced overheads on the host

Quicker actioning of a received XON/XOFF

than if host intervention is required, thus reducing

the chance of lost characters

Host can override XON/XOFF state at any time

Irrespective of whether or not this mode is enabled, XON and XOFF control characters are always passed
to the host. This enables the host to monitor the state of the line and keep a check for potentially lost XON
characters.
2.11.8 Transmitted XON/XOFF Characters
If it becomes congested when it is enabled, the DMB32 will transmit an XOFF character; ‘congested’
means that the received character FIFOis over three-quarters full. To avoid unnecessary line traffic, the
XOFF will only be sent out to channels on which characters are received after the congestion has occurred.
When the congestion is relieved (when the FIFO becomes less than half full), then the DMB32 will
transmit an XON on any channel that has had an XOFF transmitted. If characters are received on a line
which has had an XOFF sent then every second character received will result in an XOFF being
transmitted.

The host can also request the DMB32 to transmit XON/XOFF characters for any line. If the host has
requested XOFF then this will override the automatic sending of XON when the FIFO becomes less than
half full.
The characters used for XOFF and XON are programmable for each line.
2.12 PRINTER INTERFACE
The DMB32 supports the LP32 generic printer specification, this includes: LNO1, LNO1-B, LNO1-S,
LP25, LP26, LP27, LXY12, LXY22 printers.
2.12.1 Operation
To start printing, the host sets up the DMA address, offset and count registers, and sets the DMA start bit
(PR.DMA.START).

The printer interface section of the DMB32 uses DMA files in a similar fashion to the asynchronous
multiplexer. The DMB32 will clear the DMA start bit and interrupt the host when the print operation is
finished. The type of VAX-11 address translation used for the DMA buffers is specified by the
PR.DMA.PTE and PR.DMA.PHYS bits.

The host can abort the print operation at any time by setting the abort bit (PR.DMA.ABORT). When it
detects that the abort bit is set, the DMB32 stops transferring characters to the printer, clears the DMA
start bit, and interrupts the host.
After a print operation, the host can examine the number of bytes transferred to the printer, and if
formatting is enabled, the number of lines of paper used.

2-21

The host can determine the printer status at any time by examining the printer CSR (PCSR). This
contains three bits which are returned from the printer; these are defined as follows:
e

PR.OFFLINE

When set, this bit indicates that the printer is offline.

PR.CONNECT.VERIFY

When set, this bit indicates that a printer is connected

to the distribution panel via the cable.
e

2.12.2

PR.DAVFU.READY

This bit is set when the printer is ready for a DAVFU
command sequence.

Formatting

The host can specify optional formatting operations to be performed by the DMB32. The formatting
control information must be set up before the DMA is started, and must not be modified until the DMA
has finished. The formatting functions are:
°

Prefix Characters

Prefix characters can be sent to the line printer before
the data in the DMA buffer is sent. The number of
characters sent is controlled by PREFIX.COUNT. The
character to be sent is controlled by PREFIX.CHAR.
This feature is used to insert a form feed or new line
before sending the data to be printed.

Suffix Characters

Suffix characters can be sent to the line printer after
the data in the DMA buffer. The number of characters
sent is controlled by SUFFIX.COUNT. The character
to be sent is controlled by SUFFIX.CHAR. This
feature can be used to insert a form feed or new line,
after the data to be printed.

Automatic Carriage Return

If this mode is selected, carriage return characters will
be inserted in the data stream, before any form feed or
line feed character that is not already preceded by a
carriage return,

If this bit is set, any form feed in the data stream will be
converted to the appropriate number of line feeds in
order to reach the next top of form. The number of

Insertion

Automatic Form Feed to Line
Feed Conversion

lines on a page must be specified in PR.PAGE.
e

Non-Printing
Deletion

Character

Conversion to Upper Case

Automatic New Line Insertion
(line wrapping)

Tracking of Carriage Position

The DMB32 tracks the carriage position and uses this

information to determine how many line feeds to
convert a form feed to, and when it is necessary to
insert a new line automatically.

2-22

CHAPTER 3
TECHNICAL DESCRIPTION

3.1

SCOPE

This description is based on the DMB32 Overview Diagram given in Figure 3-1. This diagram can be used
as a reference throughout the Chapter. Operation of the individual blocks, and the use of buses, 1s
described in the subsequent sections of the chapter.
3.2

MEMORY MAPS

The VAXBI has 30 address lines and can therefore address a space of one gigabyte (1024 Mbytes). Of
this, locations 0000 0000, to 1FFF FFFF,¢ are assigned as memory space, and locations 2000 0000,4 to
3FFF FFFF
¢ are assigned as I/O space. Up to 16 VAXBI nodes (processors, memory, or adapters) can be
serviced by one VAXBI bus, and up to 16 VAXBI buses can be mapped into I/O space.
Within I/0 space, each VAXBI node is allocated an 8 Kbyte block of addresses for device registers. This
is called its node space. The base address of the block for a given node is defined by the node identity
(node ID) plug that is installed on the VAXBI backplane for that node, and is independent of the position
of the node module in the VAXBI backplane.

In addition, each node is allocated a 256 Kbyte block of addresses in 1/O space called its window space.
This can be used to map non-VAXBI buses (for example, UNIBUS) to the VAXBI space via an adapter.
In the DMB32, when it is in maintenance mode (MAINT<5> or <4> set), the DMB32 register space may
be accessed through the window space.
Figure 3-3 shows the memory map of the DMB32, in which areas allocated to VAXBI required registers,
BIIC specific registers, and DMB32 registers are identified. The term ‘Base’ refers to the first address
within the node space.
The VAXBI required registers MUST be provided by each node. They hold control and status information
relevant to the VAXBI interface. The following data are available:
e

Device Type

Revision Level

Type of BIIC

Module and BIIC self-test control and status bits
e

Enable and control and status bits for error interrupts

Type of arbitration used by this node

)

Node ID

3-1

CONTROL

BIIC

VAX

VAXBI

TIME

DATA

:
BCI

BCI

;

: Z \

VAXEI

PHASE

CONTROL

DA’TA

—

;

vaxel A A

PATHS

CASRAM

ADDRESS CONTROL

CLOCK

RECEIVERS

|
.

20 MHz BCI TIME
|

CONTROL

ATGA

{

INTERNAL

:BCS

5 MHz BCI P??ASE

P
|
*AS{;’SE“;‘;’
|AND

>
VAXB! CGRNER

ADDRESS

;TQ ANQ FRQM

TTTTTTT T EEETEemT VAXBI) |

-j

RAM

SUS

(SECONDARY
FROM
l ADDRESS

VAXBf GR

MICROPROCESSOR

CONTROLCONTROL <

TO CSRs)

CGA

CONTROL LOGIC

CONTROL
TR

SRR

CON'{‘ROL

68000 BUS MULTIPLEXER
|

(TRANSCEIVERS

AND BI-DIRECTIONAL

LATCHES)

COMMUNICATIONS INTERFACE

68000 BUS

PRINTER PORT

%’;g”mmus

>
ASYNCHRONOUS

COMMUNICATIONS

PORTS

CONTROLLER

(MICROPROCESSOR,

SCRATCH RAM,
FIRMWARE (ROM)

(4 DUARTS)

A
-

- -

DRIVERS AND RECEIVERS

PRINTER

CHANNEL

[

SYNC

EIGHT

CHANNEL

|==--8~--.

ASYNCHRONOUS

Y CHANNELS

BACKPLANE CONNECTOR

Figure 3-1

DMB32 Overview Diagram

3-2

HEX ADDRESS
2000 0000
NODE O NODESPACE

2000 1FFF

(BKE)

2001 E00O

‘
NODE 15 NODESPACE
(8KB)

MULTICAST SPACE

(128KB)

2001 FFFF

2002 0000

2003 FFFF

2004 0000
NODE PRIVATE SPACE
(3,75MB)
203F FFFF

—

2040 0000

WINDOW SPACE
(256KB)

2043 FFFF

ODE 15

207€ 0000

WINDOW SPACE

207F FFFF

(256KB)
RESERVED

RESERVED
(FOR MULTIPLE VAXBI SYSTEMS)

(480MB)

2200 0000

3FFF FFFF
RE184

Figure 3-2

VAXBI I/O Address Space

Error status bit for transfers on the VAXBI/BCI interface

ID of nodes to which this node can send an INTR command and from which it can accept an
IDENT command.

BIIC specific registers are not required by the VAXBI specification. They support specific functions
implemented by this BIIC. The following data are available:

The range of addresses, outside device register space, to which the device will respond as slave

User interrupt control and status bits

Enable/disable bits for the various VAXBI commands

Flags to control use of general purpose registers.

3-3

VAXBI

ADDRESS
(HEX)

BASE

VAXBI REQUIRED
REGISTERS

BASE +20
BIC
SPECIFIC
REGISTERS

IN BIIC

BASE +44

UNUSED

GENERAL PURPOSE

BASE +FO

REGISTERS

BASE +100

IN CASRAM,
CGA AND
ATGA

DEVICE

(USER)
REGISTERS

BASE + 214
IN CASRAM

NOT ACCESSIBLE

BY HOST EXCEPT
IN MAINTENANCE

MODE
(MAINT <4> OR

USED BY MICROPROCESSOR
FOR MANAGEMENT
OF DMA: AND CONTROL,
STATUS AND BUFFERING

OF PORTS

<5> SET)

BASE +1FFC
RE185

Figure 3-3

DMB32 Memory Map

3-4

The user registers are the CSRs via which the device 1s controlled. Most of the registers support the
communications functions of the option, but some are used to support maintenance functions and the
translation of virtual addresses. In broad terms, the functions of the user registers are:
Transfer of data to/from the communications channels

Configuration, control and monitoring of the communications functions
Reporting of configuration status
Holding system page table information (held by DMB32 to access system memory for address
translation purposes)
Support of maintenance functions and diagnostics.

3.3

DMB32 COMMANDS

Commands on the VAXBI demand an appropnate response from all connected nodes. At power-up or
initialization, each node programs its BIIC to give the correct response for its node.
A node that i1s not addressed by a command, or that is unable to implement it, will respond with NO ACK.
An addressed node that can implement the command will respond with ACK, and will execute the
command. If the node can implement the command but is not ready, STALL or RETRY responses will be
issued until an ACK is generated.

The DMB32 does not implement the full set of VAXBI commands.
3.3.1

DMB232 Slave Response/Interpretation

The DMB32 supports the following VAXBI commands:
Read

Interlock read
Read with cache intent
Write

Write with cache intent

Unlock write — mask with cache intent
Write mask with cache intent

Ident

Stop.
For more information see Section 3.17.1.

3-5

3.3.2

DMB32 Master Commands

In order to perform DMA transactions across the VAXBI, or to interrupt the host CPU, the DMB32

becomes bus master. As bus master it can issue only the commands listed below.
e

Read

Write

Write Mask

Interrupt (INTR).

All DMA transfers of communications data are octaword.

3.4 VAXBI CORNER
The specification of the electrical and physical parameters of options on the VAXBI bus is very critical
because of the high bandwidth (13.3 Mbyte/s) of the VAXBI bus. Variations of impedance, signal delay,
and other factors, can affect the proper operation of the bus. For this reason, all VAXBI adapters use a
standard design and layout of the VAXBI bus interface. This common section of the module is called the
VAXBI Corner.

3.4.1 Backplane Interconnect Interface Chip (BIIC)
The BIIC forms the major part of the standard interface for all VAXBI adapters and performs the
following functions:
e

Provides all VAXBI bus drivers and receivers (except for clocks and some async signals)

Handles all aspects of VAXBI arbitration protocol

Performs the address recognition function

Handles VAXBI bus protocol and error-checking

Handles all VAXBI transfers to/from the DMB32

Can be programmed to provide parity for data and addresses from the DMB32

Implements commands which are addressed to the VAXBI required registers

Passes address, data, and command information addressed to the DMB32 registers

Performs a BIIC self-test at power-up or reset, and disables its VAXBI drivers if the test fails.

Although the BIIC can implement all VAXBI command-types, the DMB32 only uses a subset of these. At
initialization, the DMB32 firmware programs the BIIC for only those commands which are implemented
by the DMB32. ACKs and certain other responses to VAXBI commands, can be made autonomously by
the BIIC.

3-6

—|BCL.TIMEL

BL_TIME+H
BL__TIME-L

BL_PHASE+H

BIIC

>
|

cLock
necgver

BI_PHASE-L

BCQPHASE L
,
|BCLLPHASE H

10MHzH _ 70O

MICROPROCESSOR

CGA

BCL TIME H
(NOT USED)
;

5MHzH

BI CORNER

_ TO USART

TM AND CIO

|
§

T50

T100

BCI TIME L

BCIPHASEL

10 MHzH

]

BCI PHASE H

T150

|
|

L1
l
i

{
RE188

Figure 3-4
3.4.2

DMB32 Clock Circuits

Clock Circuits

The VAXBI bus carries differential square-wave clock signals at 20 MHz (BI TIME) and 5 MHz (BI
PHASE). These are the basic timing elements for the VAXBI system and they connect directly to the
clock receiver which produces BCL_TIME and BCI_PHASE signals at TTL levels. Figure 3-4 shows how
the DMB32 clocks are derived.

The VAXBI corner layout provides for clock drivers and receivers to be mounted. Only one node of a

VAXBI system is permitted to drive clock signals on the bus; clock drivers of all other nodes are either
disabled or not mounted.

Drivers are not mounted in the DMB32, therefore the receivers are driven by clock signals from the
VAXBI. These clock signals synchronize the DMB32 logic to operations on the VAXBI.
BCI_TIME L and BCI_PHASE L provide clocks for the BIIC and the CGA. BCI_PHASE H provides a
clock for the 8530 USART and the 8536 CIO ICs

A 10 MHz clock, derived by the CGA from BCI_TIME L and BCI._PHASE L, provides a clock for the
MiCroprocessor.

3.5 COMMON ADDRESS STORE RAM (CASRAM)
CASRAM is a 2K longword memory shared by the VAXBI host and the 68000 microprocessor. Access to
CASRAM is arbitrated by the CGA, and addresses are translated by the ATGA.

CASRAM is used for DMB32 device registers and data buffering. It is mapped into the VAXBI system
I/O space, its exact address is determined by the node ID plug on the backplane slot into which the
specific DMB32 is installed.

On any VAXBI bus, up to 16 blocks of 2K longwords (8 Kbytes) can be defined as node space. Therefore,
up to 16 VAXBI nodes can exist on a single bus.

Figure 3-5, the CASRAM block diagram, shows that the ATGA supplies a common 11-bit address to
each 2 Kbyte RAM chip. Chip Select (CS) signals for each byte, and common Write Enable (WE) and
Output Enable (OE) signals are supplied by the CGA. Data is written to and read from the RAM via the
data bus, D<31:00> H.
For word or byte accesses, only the relevant CAS_CS L signals are asserted.

Timing of CASRAM control signals is dependent upon the type of transaction being performed. However,
two examples of signal relationships (for CASRAM Read and Write transactions) are given in Figure 3-5.

3.6 ADDRESS TRANSLATION GATE ARRAY (ATGA)
The ATGA is an address multiplexer which also performs some address translation functions.

CASRAM ports that are multiplexed by the ATGA are:
©

The primary access port - this is the VAXBI access port

The secondary access port — this is the 68000 microprocessor access port.

The primary access port is input only. It carries addresses and command information received from the
VAXBI.

The secondary access port accesses CASRAM via a multiplexed address and data bus. Addresses, which

come from the microprocessor are input only. Data, from the microprocessor or the VAXBI host, is both
input and output.

The ATGA contains on-board registers which are used to support its address translation function. These
registers are a duplication of similar registers in CASRAM. There is very little control logic in the ATGA;
strobes which select address or data, and enable signals for the primary or secondary access ports, are
provided by the Control Gate Array (CGA).
|
3.6.1 Address Translation
Addresses from the VAXBI host or from the microprocessor are translated before they are used to address
the CASRAM. Translation includes the indexing of addresses, selection of FIFO counters in the ATGA,
and the inversion of microprocessor addresses.

3.6.1.1 Indexing — Each async port has some indexed registers and these are accessed by a field in
ACSR,; for example, each port’s PREEMPT register can be accessed at the same node space address after
the port number is written to ACSR<7:0>.
It is the ATGA’s indexing function that combines the index in ACSR with the PREEMPT address to
access the correct CASRAM location.

BYTES

ATGA

RA<10:00> H

[cs e OF

D<31:24> H

D<23:16> H

BYTES

CS wg OF

-———-——9 T T

> gg‘!’E:NAL

— 1]
«

CAS_ CS<3> L

CAS_ CS<2> L
CGA

CAS_CS<1> L

| 2K

> BYTES

CS e OF

CAS_CS<0> L

D<15:08> H

BYTES
CSWEeOE

D<07:00> H

3
‘

”

BUS

CAS__WE L

CAS_OE L

RA<10:00> H

D<31:00> H

——( WRITE DATA }-—

CAS_CS<n> L

CAS_OE L

CAS_WE L

—\

READ DATA )——

/!
i
DATA

STORED
RE1BS

Figure 3-5
3.6.1.2

CASRAM Block Diagram

FIFO Controllers - The ATGA controls three FIFOs in CASRAM. These are:

RX Data FIFO (512 longword entries)

TX Completion FIFO (16 longword entries)

Sync Line Completion FIFO (16 longword entries)

Each FIFO is accessed via a single location. When a FIFO address is recognized by the ATGA, an address
from the appropriate FIFO counter maintained in the ATGA, is output to CASRAM.

3-9

The RX Data FIFO - (RBUF) is used for async port RX data and status, async modem status,
and diagnostic reports.

The TX Completion FIFO - (TBUF) is used to queue reports of async channels which have

completed, aborted or terminated transmission of a DMA buffer, or which have just emptied
their preempt register.

The Synchronous Line Completion FIFO - (SBUF) is used to report that a DMA transfer on

the sync channel has been completed with or without error, or that a modem status change has
been detected.
3.6.1.3 Inversion of Microprocessor Addresses - CASRAM is a common resource for both the VA XBI
host and the microprocessor. However, the significance of bytes within words, and words within longwords,
is different for the 68000 microprocessor and VAX-11. To overcome this difference, addresses supplied by
the microprocessor are inverted in the ATGA. This correction of the data structure is invisible to the user.
Address inversion is described in Appendix B.
The ATGA also controls octaword DMA files in CASRAM (these are not accessible to the user). They
exist for each sync, async, and printer channel.
3.6.2 ATGA Registers
By writing to specific registers in ATGA, the microprocessor can clear individual FIFOs or reset all
ATGA registers to their initial power-on condition. Other ATGA registers hold information used by the
ATGA and the microprocessor to provide CASRAM addresses, to manage the FIFOs, and for diagnostic
use.

Information held by the registers includes:

Channel number

Copies of the channel number from the async CSR and
the sync CSR.

Base addresses

Base addresses of FIFOs and the CASRAM areas
allocated to sync and async registers. These values, are
loaded at initialization.

FIFO status

—

Status bits used for control of the FIFOs, generation of
async RX data interrupts, generation of auto-flow
characters and so on.

DMA file

Points to the beginning of a DMA file address in

CASRAM.

The ATGA, its registers and control signals, are described in more detail in Appendix B.
3.7 CONTROL GATE ARRAY (CGA)
The major functions of this array are:
e

To control the BCI

To control the ATGA and CASRAM

The BCI consists of a slave port and a master port. The slave port responds to valid VAXBI commands
addressed to the node identified by the node identification plug on the BI backplane slot. Node and
command recognition are performed by the BIIC.

3-10

By asserting a request on the BCI, the CGA can initiate a transaction across the VAXBI. Before causing
the request to be asserted, the microprocessor must set up the appropriate DMA file in CASRAM and
load the DMA File Address register in the ATGA. For a WRITE transaction, the DMA file must be
loaded with the data to be transferred. The BIIC uses the VAXBI address from the DMA file, to address
system memory.

The ATGA is presented with address and command information at its primary and secondary access ports.

The CGA monitors both ports, and provides signals to enable the appropriate port and to control the
transfer of information into and out of the ATGA. The primary access port has priority over the secondary
access port.

To reduce the component count, much of the microprocessor memory/peripheral decoding logic is
included in the CGA.
3.8

DATA PATHS

To comply with BCI timing requirements, a number of latches are used to transfer data between the BIIC
and CASRAM. Before it is written to CASRAM, data from the BIIC is latched to make time for the BIIC
to check parity, so that bad data is not written. Data is fetched from CASRAM and is held in the latches
until the VAXBI needs it, thus avoiding the need to stall the VAXBI.

The above latching requirements are met by the data paths logic, which consists of latches controlled by
the CGA and the BIIC. By use of these latches, a longword can be latched and enabled from the BCI to
the internal bus, or from the internal bus to the BCI. (The CASRAM is on the internal bus D<31:00>).
Figure 3-6 shows the bus arrangement.

| 4x

LS374

;

~ LATCH_BCI H

«a

o~
CK

, INTERNAL

D<31:00> H | DATA

Bci<31:00> H

FROM | ENABLE BCL_CAS L

7 BUS

CAS/BCI LATCHES

CGA

S373

.
FROM
aiic

LATCH_CAS H

BCL_MDE L
BCL_SDEL

ot |

ENABLE_CAS_BCI L

l
RE1S0

Figure 3-6

Data Paths Logic

The BCI/CAS latches are configured for input (fnaster READ §0r slave WRITE) and the CAS/BCI
latches are configured for output (master WRITE or slave READ).

In Figure 3-6 LATCH_BCI H, LATCH_CAS H and ENABLE_BCI_CAS L are supplied by the CGA.
BCI Master and Slave Data Enable signals (BCI_MDE L and BCI_SDE L) come from the BIIC. ORing
MDE and SDE, allows the BIIC to read the data as required by the VAXBI.

During any VAXBI command cycle, even those not addressed to this node, the command address is
latched into the data paths. However, the latched address is not used except when the DMB32 is in
maintenance mode (MAINT<4> or <5> set).

3-11

3.9 68000 BUS MULTIPLEXER
CASRAM is organized as longword memory but the 68000 microprocessor is a 16-bit (word) device.
To
allow access to and from the high and low words of CASRAM, the microprocessor data bus is switched
by
four LS245 transceivers onto both words of the internal data bus. The switched microprocessor data
is

time multiplexed with microprocessor addresses, using two L.S646 latches. These latches are bi-directiona

to allow the VAXBI to access the microprocessor local bus (in maintenance modes only).

Figure 3-7 shows the relationship between the 68000 microprocessor bus and the internal bus,
and
identifies signals by which the CGA controls the Busmux.
.

“““““ —']

|
>

LATCH__ADDRESS H

FROM | CAS__ADDRESS TO_MICRO H

CGA

ENABLE__ADDRESS L

| , f
|

[
D<15:00>

CAS__DATA_TO__MICRO H
CGA

—

ENABLE_MSW L

D<31:16>

v i /L
Y

LONGWORD

2 X

LS245

CEIVERS
DIR

[

68000

‘

MICRO—~

PROCESSOR

TRANS-

DIR G
]

ADD<15:01>

CAB

LATCHES

BUS

fsxezis

2 x

LS245

CEIVERS
.

DIR

TRANS-

DAT<15:00>

cfsus ‘

]

v v
TO: SCRATCH RAM
ASYNC PORTS

CASRAM

SYNC PORT

PRINTER PORT

STATUS LATCHES
FIRMWARE ROM

Figure 3-7

Multiplexing the 68000 Microprocessor Bus

The LS245s are transceivers. When ENABLE_LSW L or ENABLE_MSW L is asserted, the appropriate
transceivers are enabled in the direction selected by CAS_ADDRESS_TO_MICRO H (Asserted
= to
microprocessor, de-asserted = from microprocessor). When transceivers are not enabled they are tri-stated.
The LS646s are transceivers with integral latches configured to achieve the functions defined in Table

3-1.

Table 3-1

Address Latch Truth Table

Dir

CAB

Function

Hor L

Buses isolated

Latch address from D<15:00> H

Hor L

Enable latched address onto ADD<15:01> H

Enable ADD<15:01> H, from the microprocessor onto D<15:01> H

(Transparent state)

x = don’t care
3.10

68000 MICROPROCESSOR

The 68000 mlcroprocessor is a 16-bit device with an address range of 16 Mbytes (8 Mwords). In the
DMB32, the top eight microprocessor address bits are not connected, therefore the address range is 64
Kbytes (32 Kwords). The microprocessor uses an 16 Kword ROM and a 2 Kword scratch RAM. The
microprocessor manages DMB32 functions such as:

Self test and initialization at power-up and reset

Programming, configuring and monitoring the communications and printer ports in accordance

with information written to the CSRs

Managing data buffers and DMA queues in CASRAM, and transferring data between CAS-

Controlling and monitoring modem and printer control and status signals

Initializing DMA sequences to transfer sync port RX data to system memory, from DMA files

Translating VAX-11 virtual addresses to physical addresses

Sending flow control characters as required.

RAM and the communications and printer ports

in CASRAM

Microprocessor functions are performed in a priority sequence defined by the firmware.

311 FIRMWARE FLOW

The functions of the DMB32 are defined by firmware routines. Routines are performed according to a
fixed priority. The microprocessor checks a list of tasks and takes the one at the top of the list; tasks at the
top of the list have the highest priority.

To keep track of tasks, and the channels on which they have been performed, the microprocessor
maintains flags and copies of status registers in its scratch RAM.

The structure of the priority loop is shown by Figure 3-8. Note that there is no routine to transfer
characters between the USART and the DMA files in CASRAM. This is done under microprocessor
interrupt control.

3-13

‘

INITIALIZE )
il
-

Y
TASK
1

SYNC Rx

CHARACTERS

TRANSFER l

YES
’

TO SYSTEM

YES

TO DMA

DMA BUFFER I

}

TASK 2

SYNC Tx
CHARACTERS

TRANSFER l
FILE

NO
TASK 3

SYNC

ACCESS

BUFFER ADDRESSTMN\YES

_!Ff;iiézfgg

TRANSLATIONS

|
ADDRESSES

TASK 4

ASYNC
BUFFER ADDRESS
TRANSLATION

YES

ACCESS PTEs

AND
TRANSLATE
ADDRESSES

NO
TASK 5

YES

REGISTERS

WRITTEN

SYN

TASK 6

SET UP l
I

DUFFER

COMPLETED/

TERMINATED

N YES

RAISE SYNC

INTERRUPT

STARTIT

NO
NOTE:

TASK7
ANY

ACSR2, SCSR2, PCSR2

NEW SYNC

LPR1,20R3
TLNCTRL 1 OR 2
RLNCTRL 1 OR 2

BUFFERS

LPR

LNCTRL

)

PREEMPT
PCTRL

YES

(SEE NEXT PAGE)

RE186

Figure 3-8

DMB32 Firmware Flow Diagram

CONTINUED FROM

TASKS8

YES

TRANSFER TO

Rx FIFO

NOTE

CHANNEL

ANY

ASYNC Rx
CHARACTERS

NUMBER
*%

TASKS
YES

NOTE

SEND

CHANNEL
NUMBER

ANY

XON/OFFs TO

* ¥

()

ANY

YES

SEND

TASK 10

TO SEND

NOTE
CHANNEL
NUMBER

TNo
TASK 11

\
ANY
DMA Tx CHARS
_ TO SEND

YES

SEND

NOTE
CHANNEL
NUMBER
L

TASK 12
7

—

,
PRINTER

READY, AND
DATA IN
DMA FILE -~

YES

SEND IT

NOTES:

NO
SEE TEXT

«+

ASYNC Rx TIMER
PRINTER STATUS
SANITY TIMER (LOSS OF CLOCK)
X21 TIMER
MODEM STATUS CHANGE

TAKE

APPROPRIATE
ACTION

RE187

Figure 3-8

DMB32 Firmware Flow Diagram (continued)

The sequence of Figure 3-8 is as follows. Note that after any task is performed, the next task is task 1.

1. Is there a sync channel RX DMA file ready for transfer ’to system memory? If so, send it.
2.

Is there a sync channel TX DMA file able to accept data from system memory? If so, get it.

Do any sync buffer addresses need translating? If so, access PTEs and do the translation.

Do any async buffer addresses need translating? If so, access PTEs and do the translation.

Have any of the listed registers* been accessed since the last check?
If so, do any configuration
and set up registers as necessary.
Has a sync DMA buffer completed/terminated? If so, and the
sync interrupt is enabled,
interrupt the host at the sync interrupt vector.

Is there a new sync DMA buffer to start? If so, start it.
Is there an async RX character ready in a DUART? If so, transfer it to the
RX FIFO. Note the
channel number**.

If the FIFO was previously empty and the RXIE is set and no delay is program

the host at the async RX interrupt vector. If a delay is programmed, start
Is there an XON or XOFF

med, interrupt

the delay counter.

to send? If so, send it. Note the channel number**.

10.

Is there a preempt character to send? If so, send it. Note the channel number**
. If TXIE is set,
interrupt the host at the async TX interrupt vector.

11.

Are there any async TX DMA characters to transfer to or from a DMA
file? If so, and
TX.ENA is set, do the DMA transaction and/or transfer one character
to the DUART as
required. Note the channel number**.

If TXIE is set and transmission of the DMA buffer is complete, interrupt the
host at the async
TX interrupt vector.
12.

Are there any printer characters to transfer to or from the DMA file? If
s0, and the printer is
ready, do the DMA transaction and/or transfer one character to the CIO
as required.

If PR.LE is set and transmission of the DMA buffer is complete, interrupt
the host at the
printer interrupt vector.
,
13.

Have any timers timed-out?*** Take appropriate action for the relevant

(For example if the RX timer has timed-out, raise the RX interrupt)

timer-driven function

When the host writes to any of the registers listed on the flowchart
, bits are also set in a CSR
Change register (CSR_CHGE) in the CGA. The firmware reads CSR_CH
GE to check if
registers have been written.
* %k

Async channels are checked in a cyclic sequence, and a flag is
set when an operation is
performed on a channel. When the microprocessor returns to this step,
the next channel will be
checked first.

* k%

Modem and printer status lines are checked at intervals determined
by timers in the 8536 IC.
By polling the timers, the microprocessor can check the status as required.
Timer intervals are:
10 ms - async port modem status
1 ms - sync port status

More information on the 68000 microprocessor is given in Appendi

x A.

3-16

3.12 ASYNCHRONOUS PORTS
Four type 2681 DUARTSs (Dual UARTS) provide eight async serial data channels. The DUARTS are
controlled and serviced by the microprocessor.

Each DUART has internal CSRs and data registers. By reading and writing these internal registers, the
microprocessor transfers data, and configures and controls each async channel.
A common polled output tells the microprocessor when one of the DUARTSs has assembled a receive
character. Incoming data goes into the Rx FIFO.

Data and modem control lines of each DUART are connected via line drivers and receivers.
More details of the 2681 DUART are given in Appendix A.
3.13 SYNCHRONOUS PORT
|
|
The 8530 USART is a dual channel device. However, in the DMB32, some modem control and status lines
are shared by the two channels, so only one channel can be selected at a time. In the DMB32, channel B is
used for a CCITT V.35 standard interface and channel A is used for all the others. Both channels are
connected to a 50-pin, miniature D-type male connector on the distribution panel. The female connectors
on four different adapter cables supplied for RS-422, RS-423, V.24, and V.35, are wired to use only the
appropriate pins.

The USART has internal CSRs and data registers. By reading and writing these registers the rnicmprccessor transfers data, and programs the IC.

Functions which are programmable on the 8530 are:

The method of signal encoding

Type of protocol (see below)

Flag and zero insertion and stripping

CRC and parity generation and stripping

When it has assembled a received character, or is ready for a transmit character, the USART interrupts
the microprocessor which then performs the transfer to or from the CASRAM.
Modem status lines are polled by the microprocessor.

Data and modem control/status lines are connected to the interchange circuits by line drivers and
receivers.
Sync protocols supported by DMB32 are:

SDLC/HDLC

— bit oriented

IBM BISYNC

- byte oriented

DDCMP

— byte-count oriented

GEN BYTE

— protocol supported by the host

3-17

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Details of protocol support provided by the DMB32 are given in Chapter 2. More detail of the 8530
USART is provided in Appendix A.

All signals are made available or monitored at the sync interface connector, Except for the data and clock
signals. A specific standard is selected by connecting the appropriate adapter cable to the interface
connector.

Figure 3-9 shows several sync interface and modem control signals provided by the CIO and DUARTS 0 |
and 3. These are:
e

SYNC_DTE_CLOCK L is an internally generated clock intended for direct DTE to DTE

connections

SYNC_DTE_CLOCK_SELECT H selects either the internally generated clock, or the clocks
received from the modem

Asserted = Internally generated clock to USART
De-asserted = Modem clocks to USART
e

FORCE_SYNC_TXD H provides a steady 1 or 0 condition on the TXD lines during internal
loopback tests

Asserted = Steady 1 condition
De-asserted = Steady 0 condition
e

SYNC_LOOP_SELECT H connects TXDA and TXDB to RXDA and RXDB for internal
loopback tests, and outputs FORCE_SYNC_TXD on TXDA and TXDB
Asserted = Loopback ON, and FORCE_SYNC_TXD H out
De-asserted = Loopback OFF, and TXDA and TXDB out

VII_RX H enables the V.11 (balanced) or V.10 (unbalanced) data receivers

Asserted = V.11 receiver enabled
Deasserted = V.10 receiver enabled
3.14 PRINTER PORT AND DISCRETE I/0
An 8536 IC and two LS374 latches form a common interface for the printer, for modem status signals,
and for discrete 1/O signals.

The 8536, which is covered in Appendix A, is a counter/timer and parallel I/O chip (CIO) that has three
parallel ports and three counter/timer circuits. Figure 3-10 shows the use of the ports, of which A and B
are byte-wide, and C is 4-bits wide. Note that some lines of port C are programmed as inputs and some as
outputs. The sync port internal clock (SYNC_DTE_CLOCK L) is driven by the counter/timers.
CODE_SEL<7:0> is used to identify the type of sync cable that is connected.

3-19

CABLE IDENTITY CODE >

DAT<15:08>

LS374
LATCH

~ AS L

FROM

gfiéCROPROCESSOR JRDL
CGA

DISCRETE_
0. SEL
_ L

FROM
PORT B

ASYNC RING INDICATORS » ASYNC

<7:0>

CONNECTORS

ClO
78536

(FFOM

SYNC_DTE_CLK LWC

ASYNC__SERVICE_REQ L

PRINTER)

- _

PRINT_DEMAND L _

| PORT
C

CE L P

PRINT_STROB H
.

conT

A<1:0>

—

PRINTER

PRINTER__SEL L

|~ 3.0

PRINT_DAT<7:0>H | A

<7:0>

ADD<2:1> H

FROM

DAT<7:0> H

SELF TEST FAST

BI_STFL

FROM VAXBI

PRINT _ONLINE L

STATUS

PRINT DAFVU L
SRINT CONN L

‘

FROM PRINTER

SYNC TEST_inDicaToRL

ZROM SYNC

o
SYNC RING__INDICATOR Lo

CHANNEL

SYNC DSR__INDICATOR L _ a

LS374

| HATC"

STATUS

MICROPROCESSOR
OR VAXBI

DAT<15:00> H

IE|

DAT<7:0> H

L OF

RE193

Figure 3-10

Printer Port and Discrete Logic

3-20

3.15

OUTPUT/TTL LEVEL CONVERSION

Line drivers and receivers convert between TTL levels at the sync and async port logic, to output levels on
the communications lines.

Drivers and receivers (printer status) on the printer lines operate at TTL levels only, so there is no
conversion.

3.16

COMMUNICATIONS INTERFACE

The communications interface provides an interface between the DMB32 and the sync, async, and printer
channels. It consists of an interface controller and a number of peripheral I/O ICs. See Figure 3-11.

The USART and CIO are connected to DAT<7:0> to allow their interrupt capability to be used. This is
because the microprocessor reads interrupts on the low data byte only.
3.16.1

Address and Signal Decoding

Much of the microprocessor address and control signal decoding logic has been built into the CGA. Figure
3-12 includes an equivalent circuit of control signal decoding.

Address decoding in the CGA is in two parts. ADD<15:13> selects the control signals to be generated by
the CGA. ADD<15:12> selects how many wait states are to be inserted in the present microprocessor
transaction cycle. This is done by delaying the assertion of DTACK L for a number of cycles.
Table 3-2 relates addresses to devices, control signals, and wait states. Note that a wait state is a full period
of the 10 MHz clock.

Table 3-2
Microprocessor Address

CGA Decoding of Microprocessor Addresses

(Hex)

Devices

XX0000 to XX7FFF

firmware ROM

XX8000 to XX9FFF

scratch RAM

RAM_SEL L

XXA000 to XXDFFF

CASRAM

] **

XXEO000 to XXEFFF

DUARTS

IO_SEL L

XXF000 to XXFFFF

USART, CIO

IO_SEL L

XXF800 to XXFFFF

discrete 10

IO_SEL L

Signals Generated

Appropriate combination of CAS_OE L, CAS_WE L and CAS_CS<3:0> L for the type of
CASRAM access.

Default Wait States

In addition to any wait states caused by CASRAM arbitration.

3-21

<LDAT<7:G> H

MICRO,
PROCESSOR
GAT‘“ 5:08>
H

2PL<2> o

ADD<15:01> H
1/O__SEL L

sizs

RO_L—|

|/
= <12:10>
.
<}.\Do
H
ASYNC__SEL<O>'L

8DECODER
FROM 3

FIRMWARE
ROM

ADD<14:01>H

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ASYNC_SEL<1> L

>
|

(0000)

|—o

@ ’

@ SCRATCH
AN

0
[|(8000)

RAM.
SEL L —

ASYNC__SEL<3> L

BE——

SYNC SEL L

4 x 2681

DUARTS

PRINTER SEL L

o
|

_RD_L

5{
"

—0

ADD<14:01>H

[ASYNC_SEL<2> L

I
4

WR_UDS L—|

| WR

RDL—y/|

|——0lRD

.
ADD<4:1>H

(E000)
(E400)

ASYNC__SEL<3:0>L

(E800)

ASYNC CHANNELS

————

(ECO0)

LS374

SYNC CABLE

LATCH

(F800)

—

ol INT

|
WR_LDS
L —|
,

ADD<2:1>H

(FOO0O)

RDOL—]

IE| |-

8530

USART

|——mg
|——@

SYNC__SEL_L

SYNC CHANNEL
EO

o INT

<::> o

RINTER CHANNEL

8536

WR_LDS L —|

ropcr

L—

(F400)

PRINTER

|————d WR
oo

—_—

PRINT_STROBE L

PRINTER_SEL L

< PRINT_DEMAND L

f
'

PRINT__DAFVU L
|

PRINT__CONN L

4
"
A

\V/

)

v
68000 BUS
TO THE DMB32 INTERNAL DATA BUS
(D<31:00>H) VIA BUSMUX
(F800)

Figure 3-11

PRINT__ONLINE L

LS374

LATCH

fegSTF=L

_ SYNCTEST_IND L
.

SYNC RING__IND L
SYNC DSR_IND L

<«

REZ228

Data Bus Arrangement - Communications Interface
3-22

FC<2>

FC<1>

72| Fe<o>
A

——

—

AS L (OUTPUT IN MAINT MODE)

{

‘

P
|

———

| | UDS L (OUTPUT IN MAINT MODE)
e

;

oot

f""‘" -

Vol

FROM

¢ MICROPROCESSOR

Oq |

S
]

>
RWH (OUTPUT IN MAINT MODE)

LDS L (OUTPUT IN MAINT MODE]

> )

R
\

{

oL
I

I
I

LSB_WR L

MSB_WR L
et
IR
B

T0
e

RD L
~~~~~~~~~~~~~~~

>
>

INTACK L

COMMS

| INTERFACE
-

ADD<12>
H

FROM

ADDRESS
DECODER

ADD<15:13> H
RAM__SEL L

BI_TIME

Bl PHASE

10_SELL

DTACKL

10MHz H

MICROPROCESSOR
N
>

| T0ocomms

[ INTERFACE

T0
MICROPROCESSOR

TO
MICROPROCESSOR

ATGA

RE1S4

Figure 3-12

68000 Microprocessor Bus Address and Signal Decoding

3-23

3.17 BCI INTERFACE
Figure 3-13 shows the architecture of the DMB32 BCI interface which is
formed by the data path logic
and the BCI sides of CGA and the ATGA.
The BCI interface has two ports, one for master transactions and one for
slave transactions. The ports are
separate, making it possible for the master port to perform a data transaction
to or from the slave port.

This type of transfer (VAXBI loopback) is used during diagnostic procedure
s. Timing of data transfers
across the interface is controlled by the BIIC.
In Figure 3-13 the interface connections and the function of each line
are identified. Note that
BCI_D<31:00> H, BCI_I<3:0> H, BCI_EV<4:0> L and BCL_PO H are common
to both ports and that
the BIIC alone is responsible for enabling these lines, allowing the slave and master
ports to share these
signals.
A description of DMB32 BCI interface signals is provided in the CGA and
ATGA material in Appendix
B.
CGA

=== 1

f
|
| USER INTERFACE |
:
f

| REQ Q Bl TRANSACTION OR LOOPBACK

§ ABORT THE TRANSFER

;

|
|

MASTER

]

}

STATUS/ERROR CODES

-«

BCl
PO H-<—

NOACK,

RETRY CODE
: ACK ‘: D(;E;STALL,
c*:x.s
S

gééyrE

| EN STATUS ONTO 1<3:0> H
INTERFACE |<t——"

<« SMD/AD

;

ADDRESS VAL;D

SELECT CSR OR

—=B| PO L

BCl EV<4:0> L

~«—— BCIDC LO L=

BIACLO L

BI DC LOL

—

o S——

ol &c RS<1:0> L
BCI CLE H

BCI SDE L

;

BCI SEL L

WINDOW SPACE’

BC1 SC<2:05 L

;%%RRUP

| INTERFACE |

BCl 1<3:0> H *——»B| [<3:0> L

~—— BCI AC LO L -

PARITY BIT

;

»| BCI D<31:00> H<—B| D<31:00> L |

|
E———

|e————

BI CNF<2:0> L |je——

COMMAND/STATUS

—

ADDRESS/DATA

BI BSY L

BINOARBL

BCl MDE L

BCI viAB L

BCI NXTL

| EN BYTE MASK INFO ONTO 1<3:0> H

BUS

BCI RAK L

PROVIDE/ACCEPT NEXT DATA

‘

INTERFACE [~

VAXBI

»| BCI RQ<1:0> L

<{B”C IS MASTER

PORT

;

BIIC

BCI BUS

INTERRUPT<6:4>

> BCI INT<6:4>

{

|
.

TIME L

PHASE L

s
l

l
ed

FROM VAXBI CLOCK RECEIVER
RE196

Figure 3-13

DMB32 BCI Interface

3-24

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In this section, the operation and interaction of the BIIC, the gate arrays, CASRAM, and the data paths
are described. Timing diagrams are provided for each type of transfer. Some VAXBI signals are included
in the diagrams for reference only and are not described.
Figure 3-14 is an overall block diagram of the logic which illustrates the overall control exerted by the

CGA. It contains details of all relevant signal lines except those of the communications interface, which
are covered in Section 3.15. Signal lines are grouped according to their function.

As in all VAXBI transfers, the number of longwords to be transferred is indicated by BI_D<31:30>

during a VAXBI command address cycle.

In the DMB32, all DMA buffers larger than one octaword in length are transferred as a series of octaword

transactions. If the buffer is not aligned on octaword boundaries some of the data will not be required. For

a Write transaction, the unwanted data is masked out. For a Read transaction the complete octaword is
transferred to the DMA file, but only the relevant data is transferred to the 1/O ports. The unwanted data
is overwritten when the DMA file is used again.
3.17.1 DMB32 Slave Transactions
The DMB32 supports Read and Write longword transactions from the VAXBI; byte and word write
operations use masked longword transactions. The only other transactions supported by the DMB32 are
the IDENT transaction following an interrupt request, and the STOP transaction.

The DMB32 looks at the BCI I<3:0>H command lines and in addition checks the BCI D<31:30>H lines
during the command address cycle. If the function translates to a read or write, then the BCI D<31:30>
lines are checked to see if the transfer is a longword; if it is, then the BCI SEL L line is checked to ensure
this node is addressed. Any other transfers are invalid, and will be NO ACKed by the DMB32. Table 3-3
shows the action taken when any VAXBI command is received.
Table 3-3

DMB32 Response to VAXBI Commands

Command Code
BCI 1<3:0>

|
Command Mnemonic

0000

Reserved

0001

READ

0010

IRCI (Interlock read with
cache intent)

Translates to a Read Function

0011

RCI (Read
intent)

Read performed as above

0100

WRITE

0101

with

BCI
D
<31:30>

Action Taken

NO ACK

Read Longword

as above

cache
L

Write Longword

WCI (Write with cache

Write performed as above

0110

UWMCI (Unlock write
mask with cache intent)

Performs Write Mask (No
Interlock)

0111

WMCI (Write mask with
cache intent)

Performs write mask

1000

INTR (Interrupt)

intent)

3-26

NO ACK

Table 3-3 DMB32 Response to VAXBI Commands (continued)
Command Mnemonic

D
BCI
<31:30>

Action Taken

1001

IDENT (Identify)

Interrupt vector sent

1010

Reserved

NO ACK

1011

Reserved

NO ACK

1100

STOP

ACK Microprocessor halted

1101

INVAL (Invalidate)

NO ACK

1110

BDCST (Broadcast)

NO ACK

1111

IPINTR

NO ACK

Command Code
BCI 1<3:0>

X = don’t care

A slave transaction is started when a VAXBI command/address cycle addressed to this node is recognized

by the BIIC. A VAXBI command/address cycle is recognized from the preceding VAXBI cycle by the

assertion of BL_NOARB L and the de-assertion of BL_BSY L during that cycle.

The current VAXBI bus master puts a command on BI_I<3:0> L, and an address on B_D<31:00> L.
When a BIIC recognizes a command/address cycle on the VAXBI, it asserts BCI_CLE H and transfers
the command/address information from the VAXBI onto BCI_I<3:0> H and BCI_D<31:00> H.

The gate arrays use the de-asserting edge of BCI_CLE H to latch the command/address information from
the BCI_I<3:0> H and BCI_D<31:0> H lines. At the same time, the CGA asserts LATCH_BCI H to
latch the address into the data paths. Although the BCI address information is always latched it is only
used during VAXBI maintenance procedures.

If the VAXBI address selects the slave node the BIIC asserts BCI_SEL L and a select code on the
BCI_SC<2:0> L lines. When the CGA recognizes BCI_SEL L, it de-asserts DECODE_SEC_ADDR L
to enable VAXBI access to CASRAM (by default, the microprocessor has access). This causes the
address, translated as necessary by the ATGA, to be output on the CASRAM address bus RA<10:00> H.
If no assertion of BCI_SEL L is detected by the CGA, the interface returns to an idle state.
The CGA verifies that the addressed location selects an implemented CSR before selecting the CASRAM.
If the address selects a non-implemented CSR then the CGA will return a NOACK response on the
BCI_RS<1:0> and the interface returns to an idle state.

3.17.1.1 Slave Read Transaction — During the VAXBI arbitration cycle, the CGA issues the STALL
code on BCI_RS<1:0> L (which the BIIC then drives on B_CNF<2:0>L), while the CASRAM chips
are enabled by CAS_CS<3:0> L and CAS_OE L, and the selected data is latched into the data paths by
the CGA assertion of LATCH_CAS H.

VALID_DATA L is asserted with CAS_OE L and is used by the ATGA, or CGA,to enable a selected
internal register onto the least significant word of the CASRAM data bus. If an internal gate array register
is selected the CGA will not assert CAS_CS<1:0>, thus disabling the least significant word of CASRAM.

3-27

During the following cycle, the BIIC enables the data path latches onto BCI_D<3
1:00> H, and the CGA
supplies a READ DATA STATUS code on BCI_I<3:0> H
together with an ACK code on
BCI_RS<1:0> L.
N
The BIIC enables the contents of the data paths latches onto
BCL_D<31:00> H by the assertion of
BCI_SDE L. Note that BCI_SDE L is asserted twice because the first
data cycle is stalled, the data being
transferred by the second assertion.
This information is output onto BI_D<31:00>L and BI_I<3:0>L. The
ACK is transferred to the VA XBI
on BI_CNF<2:0>L. Parity is controlled by the BIIC.
At the end of the data cycle, the CASRAM chips are deselected and
the ATGA MICroprocessor port is
enabled again.
Figure 3-15 gives timing details of a VAXBI master reading data from
the slave DMB32.

3.17.1.2 Slave Write Transaction — During the VAXBI imbedde
d arbitration cycle, the CGA issues the
ACK code on BCI_RS<1:0> L, and the CASRAM chips are
enabled by CAS_CS<3:0> L.

After this imbedded arbitration cycle, the VAXBI master places data on
BI_D<31:00> L, and for a writemask transaction, a byte mask on BI_I<3:0> L. The selected slave
BIIC passes this information to the
BCI_D<31:0> H and BCI_I<3:0> H lines at the end of the VAXBI
cycle.

The BCI data is latched into the data paths by LATCH_BCI H while the byte

mask information is latched

by the CGA. The data is enabled onto the CASRAM data bus by
the assertion of ENABLE_BCI_CAS
L, by the CGA.
The BIIC checks the parity of the VAXBI bus during data cycles
and if bad parity is detected, will assert a
BPR event code on BCI_EV<4:0> L. This occurs during the VAXBI
cycle following the detection of bad
parity. If bad parity is not detected the CGA writes the data to the
addressed CASRAM location by
asserting CAS_WE L. Masked writes are implemented by using
the byte mask to de-assert one or more of
CAS_CS<3:0> L as required.

VALID_DATA L is asserted with CAS_WE L and is used by the ATGA,
or CGA, to write to

internal register from the least significant word of the CASRA

a selected

M data bus. If an internal gate array

CASRAM. This permits the contents of some write only registers
within the gate arrays to be read from
CAS.
At the end of the write, the CASRAM chips are deselected and the ATGA
microprocessor port is enabled
again. The CGA completes the transaction with two ACK cycles, using
BCI_RS<1:0> L, to indicate a
successful transfer of data.

If bad parity is detected the CGA will not assert CAS_WE L
and will return to the idle state issuing
NOACKSs on the BCI_RS<1:0> L lines.
Figure 3-16 gives timing details of a VAXBI master, writing data
to the DMB32

3-28

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3.17.1.3 IDENT Transaction - IDENT transactions are treated by the DMB32 in
a similar way to
READ transactions, although the VAXBI transaction itself has an additional arbitration cycle.
On

detection of an IDENT command the BIIC will assert the BCL_SEL L line. Assuming that an interrupt is

pending, the CGA will recognize the IDENT command and will assert the JAMO L signal.

This forces the
ATGA to ignore the address from BCI_D<31:0>H and to output an address of ‘0’ on the CASRAM
address lines RA<10:0>H.

The BIIC on the DMB32 module is programmed to request an external vector, in response to an IDENT
command. The CGA will supply the least significant word of the required vector, the
most significant
word being sourced from longword 0 of CASRAM. The DMB32 will stall the first vector cycle in response
toa VAXBI IDENT command, returning an ACK response with a valid vector in the next VAXBI cycle.
Figure 3-17 details the BCI timing during an IDENT transaction.
In the delay between requesting a processor interrupt and supplying the interrupt vector, it is possible
that
the interrupt may have been disabled after it was posted. If a single pending interrupt is cleared by
the
host, via the interrupt enable control bits, the DMB32 will return a vector with bits 7 and 6 of the interrupt
vector clear. This is used as the BIIC error interrupt vector (see Section 2.2.3) and will result in
an error
logging routine being executed. The error logging routine must, therefore, check whether either of
the
error summary flags in VAXBICSR are set, and whether the force bit in EINTRCSR is set. If none
of
these bits are set, the error interrupt resulted from a sync, async, or printer interrupt that was cleared
by
the host before the IDENT cycle.

3.17.1.4
follows:

Maintenance Levels - Maintenance Levels are selected by bits 4 and 5 of the MAINT CSR as

Normal Operation

Maintenance Level 1

Maintenance Level 2

Maintenance Level 3

During normal operation, unimplemented CSRs, within DMB32 node space, and all of DMB32 VAXBI
window space will receive a NO ACK, but in two of the three possible Maintenance Levels all
8 Kbytes of
node space, and 256 Kbytes of window space will be accessible. Maintenance Level 1 transactions
to
window space cause the CGA to request control of the microprocessor bus for the duration
of the
transaction. This will result in extended, stalled transactions.
The contents of window space are defined by the mapping of devices on the microprocessor bus. This
will
include the CASRAM. Note, however, that although CASRAM will be selected at the MiCroprocess
or
memory map addresses, the CASRAM itself is accessed by the addresses from the BCI rather than

from

the microprocessor. This results in CSRs being located at the VAXBI addresses, rather than the inverted
microprocessor addresses within CASRAM. Gate array registers are not accessible via window space, thus
permitting the host to perform pure RAM tests on CASRAM via window space while being able to access
any of the gate array registers via node space.

NOTE
The microprocessor memory map on the DMB32 is
64 Kbytes deep, resulting in it being replicated 4
times within the 256 Kbytes of WINDOW space.

3-31

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Due to differences in bus widths, the CASRAM area within the window space will be longword accessible,
while the remainder of window space will only be word accessible.

The duration of VAXBI transfers to window space is controlled by the response time of these peripherals
on the microprocessor bus and additionally, in Maintenance Level 1, by the bus grant response time of the
MIiCroprocessor.

On gaining control of the microprocessor bus the CGA will drive all of the microprocessor control signals,
except FC<2:0>, and will emulate a microprocessor access to the devices on this bus. Figure 3-18 shows a
VAXBI write to microprocessor RAM and Figure 3-19 shows a VAXBI read from microprocessor RAM.
In Maintenance Level 2, transfers to DMB32 VAXBI window space are similar to those for Maintenance
Level 1, with the exception that the CGA requests control of the microprocessor bus with the setting of
Maintenance Level 2, and will maintain mastership until exit from this maintenance level.

In Maintenance Level 2, all accesses to the module are assumed to be directed to the microprocessor bus,
and care must be taken when addressing node space, so that CASRAM is selected by the microprocessor
address bus before accessing node space. This means that CASRAM must be accessed via window space

before node space is freely accessible; if any non-CASRAM locations are then addressed via window
space, a CASRAM address must be accessed via window space before re-accessing node space.

Failure to follow this procedure will result in invalid data being transferred on the VAXBI, for node space
read transactions, and will result in the last accessed window space location being modified by node space
write transactions.

Maintenance Level 3 is intended for board testing and should not be selected. In Maintenance Level 3, the
CGA will request control of the microprocessor bus as in Maintenance Level 2, but will leave all
microprocessor control lines disabled to permit the use of external test equipment to control the bus.
3.17.2

DMB32 Master Transactions

When it needs to perform a VAXBI transaction as master, the DMB32 microprocessor constructs a DMA
file within CASRAM, writes to a file address register within the ATGA, updates a VAXBI mask register
within the CGA (if a write mask command is to be requested) and finally, writes a command to the
BI_COMM register in the CGA. This final write causes the BCI interface to initiate the transaction.
The CGA requests a transaction by asserting a request code on BCI_RQ<1:0>L. This may be for either a
VAXBI transaction or a loopback transaction.

The CGA asserts the ATGA control signals RST_DMA_ADDR L and EN_DMA_ADDR L; this sets
the DMA file address count field, RA<2:0> H, to 111 and enables the DMA file address onto
RA<10:00> H. Thus the address on RA<10:00> H points to the location of the VAXBI address held in
CASRAM. Once the address is latched, the DMA file address count field is incremented to 000 (to
address the first data longword of the DMA file).

On receiving the request code, the BIIC arbitrates for the bus and asserts BCI_MDE L, to enable the
VAXBI address from the data paths BCI_D<31:0> H, and the command from the CGA, BCI_I<3:0> L.
This assertion of BCI_MDE L may occur as early as the cycle following the assertion of a request code,
but may be delayed according to current BCI slave port activity. BCI_RAK L is now asserted to indicate
that the BIIC has won control of the bus and is now bus master.

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The assertion of BCI_RAK L is always accompanied by the
assertion of BCI_CLE H, indicating that a
command/address cycle is present on the VAXBI bus. The
slave port responds to the master port cycle by
latching the command/address information into the CGA
and ATGA. LATCH_BCI H latches the
VAXBI address into the data path.

Any DMB32 master transaction can be aborted by BCI_MAB
L; this signal is asserted by the CGA if any
errors are detected during a master transaction or if a VAXBI
retry timeout occurs.

3.17.2.1

Master Write Transactien — CAS_CS<3:0> L and CAS_OE L remain asserted

throughout

the transaction, to provide write data for the transaction. The
data output to the CASRAM data bus will
change as the CASRAM address changes.
When the BIIC is ready for data, it asserts BCI_NXT L. The
CGA responds by latching the data with
LATCH_CAS H, and incrementing the DMA file address
with an assertion of INCR_DMA_ADDR H,
The BIIC enables the data onto BCI_D<31:00> H , together
with byte mask information from the CGA
on BCI_1<3:0> H, by asserting BCI_MDE. The data is output
on the VAXBI during the next VAXBI

Cycle.

The sequence of INCR_DMA_ADDR H, BCI_NXT L, LATCH

_CAS H and BCI_MDE L is repeated
until all data cycles are complete, then the CASRAM is
disabled and de-selected, and the DMA file
address is removed from RA<10:00> H.

When the data is transferred and the BIIC receives two ACK
cycles from the VAXBI slave; BCI_RAK L
is de-asserted and the BIIC outputs a MASTER TRANSACTION COMPL
ETE code on BCI_EV<4:0>
L. The CGA verifies that this code is present following the
de-assertion of BCI_RAK L and updates an
internal status register with a completion code.

The'example in Figure 3-20 is for an octaword write-mask transaction. A normal

identical, but BCI_I<3:0> L is ignored during data cycles. For

occurs.

write transaction is

a longword transaction only one data cycle

3.17.2.2 Master Read Transaction — In a Master Read Transact
ion the data direction is from the BCI,
s0 BCI_MDE L is not asserted during data cycles; for a read transact
ion BCI_NXT L indicates that valid
read data is on BCI_D<31:00>L. In response to assertions of
BCL_NXT L, the data is written to
CASRAM.
|
The CGA latches data into the data paths by asserting LATCH
_BCI H, firstly during the imbedded
arbitration cycle and then in every following data cycle. The data
latched during the imbedded arbitration
cycle is not used by the BCI interface. With the assertion of
LATCH._ BCI H, during the imbedded
arbitration cycle, the CGA asserts ENABLE_CAS_BCI L to
enable the contents of the data paths onto

the internal bus.

In the following cycle, the assertion of BCL_NXT L indicates that
the slave node acknowledged the first
DATA cycle and returned data and data status on the BCL. This
data is latched onto the internal data bus
by LATCH_BCI H, and written to the bottom of the DMA file by
CAS_WE L. With the de-assertion of
CAS_WE L the CGA asserts INCR_DMA_ADDR H to
increment the DMA File address.
The sequence of INCR_DMA_ADDR H, BCI_NXT L, LATCH

_BCI H and CAS_WE L is repeated
until all data cycles are complete. The data paths and DMA file
address are then disabled, and CASRAM
is de-selected.
|

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After the last data cycle, the master BIIC sends two ACKs on the VAXBI to indicate to the slave that data
has been correctly received. THE BIIC deasserts BCI_RAK L as the final ACK is being enabled onto the
VAXBI and asserts the MASTER TRANSACTION COMPLETE code on BCI_EV<4:0>L.

The example in Figure 3-21 is for an octaword read transaction. For a longword transaction only one data
cycle occurs.
Data 1s written to the DMA file regardless of the receive data status or received parity. If a parity error
occurs the BIIC aborts the transfer and supplies an error code to the CGA, which sets an error code within
an internal summary register. Receiving a READ DATA SUBSTITUTE status code for any longword
does not abort the transaction, but causes a READ DATA SUBSTITUTE code to be output by the BIIC,
on BCI_EV<4:0> L, with the de-assertion of BCI_RAK L at the end of the transaction.
|

The CGA sets an error code within an internal summary register which the microprocessor reads to
determine if the master transaction was successfully completed.
3.17.3 Loopback Transactions
The DMB32 uses loopback transactions during power up self test, to initialize certain BIIC registers, to
check for BIIC self-test completion and to verify correct CGA master and slave port control signals.

Loopback transactions are identical to Intranode transactions via the VAXBI except that the only VAXBI
signals asserted by the BIIC are VAXBI BSY L and VAXBI NOARB L. Loopback transactions do not
require bus arbitration and therefore permit rapid access to the BIIC internal registers. The onboard self

test will not use Intranode transactions via the VAXBI if any failure is detected with VAXBI Loopback
transactions.
3.17.4 VAXBI INTR Transactions
VAXBI INTR commands are initiated by the DMB32 to request a host interrupt.
The DMB32 will always interrupt at level 4, the lowest VAXBI interrupt level. Interrupts are controlled
via the CGA which monitors the interrupt enable flags within the sync, async, and printer CSRs. When
the microprocessor sets a request bit within the BL_INTR register, and assuming that this interrupt is

enabled, the CGA will synchronously assert a BCI INT L signal. The BIIC then requests control of the
VAXBI and, upon becoming master,transmits a VAXBI INTR command.

Should this VAXBI INTR receive a NO ACK, or illegal confirmation from the slave node(s), the BIIC
will inform the CGA via the BCI EV<4:0> L lines. This will cause the CGA to de-assert the BCI_INT L
line and set the FIR (FAILED INTERRUPT EV CODE RECEIVED) within an internal status register.
The CGA will re-assert the BCI INT L signal upon the microprocessor reading this register, permitting the
event to be logged and the interrupt to be retransmitted.

A successful VAXBI INTR command transmission causes the host node to log the interrupt and respond,
once the host processor priority level is lower than the pending interrupt, with
command.

3-38

a VAXBI IDENT

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3.18

OVERALL CONTROL LOGIC OPERATION AND TIMING

3.18.1 Microprocessor Write to CASRAM
|
Figure 3-22 shows the waveforms for a Write To CASRAM by the microprocessor.
Clock states SO to S7
identify the microprocessor Write cycle. The sequence is described in following paragraphs
.
At the end of S1, the microprocessor outputs the required CASRAM address
on ADD<15:01> H. As the
default state of the Busmux address drivers/latches is transparent in the direction
microprocessor bus to
internal bus, the address will appear on the internal bus.
A direct version of ADD<15:12> (not via the Busmux) is continually decoded
by logic in the CGA. When
a CASRAM address is decoded, the CGA asserts CAS_RQ L to prepare
the ATGA secondary access
port for the assertion of AS L. Both must be asserted to enable the port. They
must remain asserted for the
duration of a secondary access port transaction.
At the end of S2, AS L is asserted to enable the secondary access port.

Thus the CASRAM address,
in the ATGA by the de-assertion
Busmux by the de-assertion of

translated as necessary, appears at RA<10:00> H. The address is latched

of LATCH_SEC_ADDR
ENABLE_ADDRESS L.

and

inhibited

the

After asserting AS L, the microprocessor outputs the data on DAT<15:00>
H, asserts UDS L and LDS L
to identify a word transaction, and de-asserts RW H to provide a Write
Strobe. LSB_WR L and
MSB_WR L, which are derived from RW H, UDS L and LDS L are generated
, but these are not used for
CASRAM accesses.

In Figure 3-22 the waveforms are for a least significant word write transaction. When
ENABLE_LSW L
is asserted, the data DAT<15:00> H is enabled onto the internal bus D<]5:00
> H.

CAS_CS<1:0> L selects the low word of CASRAM, and the RAM
is enabled by CAS_WE L;
VALID_SEC_DATA L is also asserted. This signal enables the gate array
data ports in case the data is
also to be written to a gate array register. The Write action is completed by
the de-assertion of CAS_WE
L, and in the case of gate array data, VALID_SEC_DATA L. The CASRAM
is de-selected by the deassertion of CAS_CS<1:0> L.
|
In all microprocessor transactions, wait states are inserted accordin
g to values loaded in the
MICRO_DELAY register in the CGA. These predetermined values are loaded
at initialization time; they
cannot be modified by the host.
|
|
The extension of the transaction is achieved by delaying the assertion of DTACK
L. Unless this signal is
asserted, the microprocessor will insert wait states. DTACK L is sampled
during S4, and during every
subsequent wait state. When DTACK L is detected, the transaction cycle
will proceed.
At the end of the microprocessor transaction, ENABLE_LSW L,ASL, UDSL,
LDSL and DTACK L
are de-asserted, and the microprocessor address and data lines are tri-stated.
Two clock cycles later,
ENABLE_ADDRESS L is asserted to re-enable the Busmux address
latches ready for the next
MICroprocessor transaction.
|
|

LATCH_SEC_ADDR H is asserted, ready for the next secendary port access.

3-40

\\\

AS L
uDS L
LDS L

1/
\\
\\

CASRAM ADDRESS

ADD<15:1> |

STACK L

\\\ B

ENA ADDRESS L

/]]c

ENABLE LSW L

A\\\

\\\ D

CASCSL<3:0> |

CASWEL

J\\\\

DATASTRB L

J\\\

it/

R R

KXO—EKA

DATA

CASSEL L

_//f

/1]

KXY cAsRAM ADDR. RF—O0%]

SAD<15:0> |

OOt

\\ LATCH CASRAM ADDRESS IN ATGA

RA<10:0> |

DATA FOR CASRAM

—XXX)

DAT<15:0> =

LATCH__SEC__ADDR L

[/
1/}

CGA DECODES CASRAM ADDRESS

11111

LEGEND

A = SELECT SECONDARY PORT

B = PERMIT MICROPROCESSOR TRANSACTION TO PROCEED

C = DISABLE LS646s

D = ENABLE DATA TO INTERNAL BUS
E = WRITE PULSE FOR ATGA
F = WRITE STROBE

RE201

Figure 3-22
3.18.2

Busmux Write Transaction Timing

Microprocessor Read from CASRAM

The example of Figure 3-23 illustrates how the command/address cycle of a primary port access (DMB32
slave) can occur during accessing by the secondary access port. The command/address information is
latched into the primary access port by BCL_CLE H, without disrupting accessing by the secondary access
port. The secondary access port transaction will be complete before the primary access port needs access to
the internal bus.

The Microprocessor Read transaction starts with the CASRAM address on ADD<15:01> H. Then ASL,
UDS L, LDS L and RW H are all asserted. Thus the Read strobe RD L is generated.

The CASRAM address is enabled into the ATGA by AS L, and"'latched by the de-assertion of
LATCH_SEC_ADDR H.

In the Busmux, the address latches are disabled and the data latches enabled by the de-assertion of
ENABLE_ADDRESS L and the assertion of ENABLE_MSW L. Note that in this case the most

significant word is addressed by CASRAM address bit RA<1> H.

3-41

"CAS_(CS<3:2> L selects the most significant word and CAS_OE L enables it to the microprocessor via
the internal bus and the Busmux. The data is latched internally before the microprocessor de-asserts AS L,
UDS L and LDS L, and tri-states the address lines.

CAS_CS<3:2> L and CAS_OE L are de-asserted to disable the CASRAM.

Two clock cycles later LATCH_SEC_ADDR H is asserted. However, the latches remain disabled by
ENABLE_ADDRESS L which remains de-asserted during the primary access port activity that is now in
progress.

TIME L
PHASE L

10 MHz

BCID<31:0>[
BCIRS L<1:0> [

~T0

M
N/

ryuuuyuyLo
/i
\\
/8

L
\

) 086“81”82\583”84\5\&”W“SS”S@“ST[/SS siffs2\_J

BCI CLE H

\\
X4 CASRAM ADDRESS

DATA<15:0>

RD L

yij

READ STROBE

KA
(1]

__[]]

W\ LATCH cASRAM ADDRESS INATGA

LATCH__SEC_ADDR L

[/
[/

W\ A
\\

LDS L
ADDRESS<15:1> |

“/F

BCI SELL

SEC ENB L
AS L
uDS L

Ut
|\

R
XX 0
[ OO0
stait KXY AcCK
B

|
NO ACK

y/i

DTACK L

\\\ C

/1]

/[ DISABLE ADDRESS LATCHES

ENBADDRESS L

\\\

ENABLEMSW L

SAD<15:0> |

CASRAM ADDRESS VIA ATGA

RA<10:0> [

PN
WAVRY,

SAD<31:16>

CASCL<3:0> |

CASOEL
DATASTRB L

UNSELECTED

\\\\\

CASSEL L

\
CGA DECODES CASRAM ADDRESS

A\\\
\ A\

/5
[7]

Ill]]
UNSELECTED

LEGEND

< = PREVIOUS CASRAM ADDRESS

A = SELECT SECONDARY PORT

J = DATA OUT (FOR Bl)

C = PERMIT MICROPROCESSOR TRANSACTION TO PROCEED
D = ENABLE DATA TO MICROPROCESSOR
E = CASRAM ADDRESS

F = DATA OUT (FOR MICROPROCESSOR)

G = CASRAM DATA TO INTERNAL BUS (FOR MICROPROCESSOR)
H = CASRAM DATA TO INTERNAL BUS (FOR BI)

RE202

Figure 3-23

Busmux Read Transaction Timing

3-42

APPENDIX A

IC DESCRIPTIONS

A.1 SCOPE
This appendix contains data on the following major ICs used on the DMB32:

68000 Microprocessor (Section A.2)

8530 Universal Synchrenous/Asynchronous Receiver/Transmitter (USART) (Section A.3)

8536 Counter/Timer and Parallel 1/0 Unif (Section A.4)

2681 Dual UART (DUART) (Section A.5)

More detailed information on the ICs is given in the manufacturer’s data sheets. The smaller, more
common ICs are well described in semiconductor data books and are not included here.
A.2

68000 MICROPROCESSOR

A.2.1 Overview
|
|
The 68000 is a 16-bit microprocessor which has 32-bit internal architecture. Its main features are:
e

16-bit asynchronous data bus

23-bit asynchronous address bus, capable of addressing 16 Mbyte in conjunction with data

strobes (UDS and LDS).
e

Eight 32-bit data registers

Seven 32-bit address registers

Memory-mapped I/O

Compatibility with 6800-series peripheral ICs

Single +5 V power supply

Mounted in a 64-pin DIL package.

The architecture of the 68000 is shown in simplified form in Figure A-1.

A-1

PROGRAMMING MODEL

16 15

8 7

EIGHT

D3 | pata

16 15

REGISTERS

A2 | SEVEN
) ADDRESS

A4 | REGISTERS

} TWO SYSTEM

STACK
POINTERS

| PROGRAM COUNTER
[5T~T:T

SYSTEM BYTE

USER BYTE

1] STATUS REGISTER
A

STATUS REGISTER

SYSTEM BYTE

USER BYTE

08 07

njz]|v]c

TRACE MODE _
SUPERVISORY MODE
INTERRUPT MASK

EXTEND
NEGATIVE
ZERO

OVERFLOW
CARRY
RE228

Figure A-1

68000 Architecture

A.2.2 Signals and Pinout
The signals to and from the 68000 microprocessor can be considered as being divided into groups. These
groups are shown in Figure A-2. The functions of these groups and their signals are described in Table
A-1, the power supply and ground connections are included.

ADDRESS

VCC (2)

Gnd (2)

A1-A23

/" oATA

CLK

FUNCTION

CODE

\‘l DO-D15

FCO -

FC1

FC2 -

68000

O————» AS

O—
@]

UDS

» R/'W

RES €——3»()

M6800
PERIPHERAL

INTERFACE

VPA ———{)

HLT 3=

BERR

LINES

DTACK

(e BR

E VMA =

BUS
CONTROL

BUS

O
» B
(O<«———BGACK

ARBITRATION
LINES

O<«——IPLO

INTERRUPT

PLT

iPL2

PRIORITY

LINES

RE230

Figure A-2

68000 Input/Output Signals

The physical connections that correspond to the signals, and the power supply and ground connections, are
identified in the pinout diagram Figure A-3.

D4aC]1e
D3

D14

DO
AS

5
6

DTACK

] 10

3 D7

61—

60 [—1 D9
59 1 D10

UD5 . 7
R'W

64
1 D5

63 [

58 1 D11
57

1 D12

1 D13

55 1 D14

BG ] 11

54 1 D15

BR .13

BGACK ] 12
vee

53 3 GND

114

1 A23

511 A22

CLK

3 A21

GND

] 16

3 vce

RESET

] 18

1 A19

33 A7

HALT .17
VVA

48 3 A20

119

46 1 A18

VPA ] 21

443 A16

BERR
] 22

43|

TPL2

421 A4

] 23

] 24

A15

A13

PLO
] 25

FC2

] 26

39 [

FC1

] 27

A10

Fco [

A12

28
] 29

373 A9

A1
A2

] 30

351 A7

36
1 A8

A3 [] 31

A4 .

REZN

Figure A-3

68000 Pinout

A-3

Table A-1

68000 Signal Descriptions

Address and Data Bus

Address Bus Lines
(A1l to A23)

23-bit output bus to address 16 megabytes, in conjunction with
UDS and LDS. Lines A1, A2 and A3 are also used to signal the
interrupt level while an interrupt is being serviced.

Data Bus Lines
(DO to D15)

16-bit bidirectional bus to transfer data in words or bytes. Lines
DO to D7 are also used to receive a vector number during an
interrupt-acknowledge cycle.

Bus Control
Address Strobe

An output indicating that a valid address is on the address bus.

(AS)
Data Strobes
(LDS, UDS)

Outputs indicating whether data transfer is on the upper, the
lower or both bytes of the data bus.

Read/Write

An output indicating whether a data bus transfer is Read or

(R/W)
Data Transfer Acknowledge
(DTACK)

Write, and also controlling external bus buffers.

An input which extends the data bus cycle time until it is
asserted, so allowing the data bus to synchronize with slow
devices or memories.

Bus Arbitration
Bus Request

An input from a device asking for control of the bus.

(BR)
Bus Grant

An output from the 68000 granting control of the bus.

(BG)
Bus Grant Acknowledge
(BGACK)

An input from a device confirming that it has control of the

bus.

Interrupt Priority
Interrupt Priority Lines
(IPLO, IPL1, IPL2)

Inputs which give the priority level of an interrupting device or

process. The priority level is in the range 0 to 7; 0 is ‘no
interrupt’ and 7 is the highest priority. IPL2 is the MSB.

Function Code

Function Code Lines
(FCO, FC1, FC2)

Outputs which indicate to external devices the status (User or
Supervisor) and the type of cycle being executed.

M6800 Peripheral Interface

Valid Peripheral Address
(VPA)

An input that indicates to the 68000 that the device or memory
region addressed is an M6800 type and that data transfer
should be synchronized to the Enable signal (E).

Valid Memory Address
(VMA)

An output in response to VPA which indicates that a valid
address is on the address bus and that the 68000 is synchronized
to the Enable Signal.

Enable

An output which is the standard enable clock signal for M6800

(E)

systems.

A-4

Table A-1

68000 Signal Descriptions (continued)

System Control and Timing
Bus Error
(BERR)

An input from an external device that terminates the current
bus cycle in the event of a problem. Also interacts with the Halt

signal (HLT).
Reset
(RES)

A bidirectional signal line that either receives an external reset

signal or outputs a reset signal to external devices, causing
either the 68000 or the external devices to perform an
initialization sequence. Also interacts with the Halt signal

(HLT).
Halt
(HLT)

Clock
(CLK)

A bidirectional signal line that either receives an external halt
signal or outputs a signal indicating to external devices that the
68000 has stopped. An external halt signal causes the 68000 to
stop at the end of the current bus cycle, a halted 68000 can only
be re-started by an external Reset. Also interacts with the Bus
Error and Reset signals.
The input to the 68000 from the master system clock, the
frequency is 5 MHz.

Power Supply

+5 volts
(Vce)

The single power supply input, connected to two pins.

Ground
(GND)

The zero-voltage side of the power supply, connected to two
pins.

A.3

8530 UNIVERSAL SYNCHRONOUS/ASYNCHRONOUS RECEIVER/TRANSMITTER

A.3.1 Overview
|
The 8530 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) is a peripheral IC for
data communications. It can be software configured to handle several types of encoding and protocol. Its
main features are:
e

Two channels

Programmable baud rates

NRZ, NRZI and FM encoding

HDLC and SDLC bit-oriented synchronous protocols

Monosync and Bisync byte-oriented synchronous protocols

CRC generation and checking

Flag and zero insertion and checking

6-bit to 8-bit character lengths and residue handling

Mounted in a 40-pin DIL package.

A-5

The architecture of the 8530 USART is shown in Figure A-4, and its register set is summarized in Figure
A-S.

RATE
SBAUD
ERATOR
A

| } SERIAL DATA

CHANNEL A | “} CHANNEL CLOCKS
-/

INTERNAL

CONTROL
Loalc

DATA

ADDRESS
’»

|
CPU
SUS /O

t—»

SYNC

_
»

WAIT REQUEST

CHANNEL A

REGISTERS

DISCRETE

S
—

CONTROL [ | MODEM DMA OR
:JL> AND
___» [ OTHER CONTROLS
o
STATUSA |

INTERNAL BUS

CONTROL

DISCRETE |e—— | MODEM DMA OR

CONTROL

A AND

STATUS B

5 { OTHER CONTROLS
>

INTERRUPT

CONTROL

LINES | €

—

CONTROL
LOGIC

ggég?géss

B
mmm—

N CHANNEL B
BAUD RATE

|GENERATOR 8|

} SERIAL DATA

| }CHANNEL CLOCKS

<—>»
»
|

SYNC

WAIT/REQUEST

RE233

Figure A-4 8530 Afchitecture

READ REGISTER FUNCTIONS

RRO
RR1

RR2

TRANSMIT/RECEIVE BUFFER STATUS AND EXTERNAL STATUS

SPECIAL RECEIVE CONDITION STATUS
MODIFIED INTERRUPT VECTOR
(CHANNEL B ONLY)
UNMODIFIED INTERRUPT VECTOR
(CHANNEL A ONLY)

RR3

INTERRUPT PENDING BITS

(CHANNEL A ONLY)
RR8

RECEIVE BUFFER

RR10

MISCELLANEQUS STATUS

RR12

LOWER BYTE OF BAUD RATE GENERATOR TIME CONSTANT
UPPER BYTE OF BAUD RATE GENERATOR TIME CONSTANT

RR13

RR15

EXTERNAL/STATUS INTERRUPT INFORMATION

WRITE REGISTER FUNCTIONS
WRO

CRC INITIALIZE, INITIALIZATION COMMANDS FOR THE VARIOUS
MODES, SHIFT RIGHT/SHIFT LEFT COMMAND

WR1

TRANSMIT/RECEIVE INTERRUPT AND DATA TRANSFER MODE

WR2

INTERRUPT VECTOR (ACCESSED THROUGH EITHER CHANNEL)

WR3
WR4

RECEIVE PARAMETERS AND CONTROL
TRANSMIT/RECEIVE MISCELLANEOUS PARAMETERS AND

WRb5

TRANSMIT PARAMETERS AND CONTROLS

WR6
WR7

SYNC CHARACTERS OR SDLC ADDRESS FIELD
SYNC CHARACTER OR SDLC FLAG

WRS8

TRANSMIT BUFFER

DEFINITION

MODES

WR9

:
MASTER INTERRUPT CONTROL AND RESET (ACCESSED THROUGH

WR10

MISCELLANEOUS TRANSMITTER/RECEIVER CONTROL BITS

EITHER CHANNEL)
WR11

CLOCK MODE CONTROL

WR12

LOWER BYTE OF BAUD RATE GENERATOR TIME CONSTANT
UPPER BYTE OF BAUD RATE GENERATOR TIME CONSTANT

WR13
WR14
WR15

MISCELLANEOUS CONTROL BITS
EXTERNAL/STATUS INTERRUPT CONTROL
RE234

Figure A-5

8530 Register Summary

A-7

A.3.2

Signals and Pinout

The function of the signals to and from the 8530 USART are described in Table A-2, the power supply
and ground connections are included for completeness. The physical connections that correspond to the
signals, and the power supply and ground connections, are identified in the pinout diagram Figure A-6.
D.CJ1e

40 £

D,
D,

39 3D,
38 (3 D,

3 2
33

D,
3 4

B33 D

INT 35

3 RD

IEO
] 6
Bl =17

35 [
34 [

INTACK ] 8
+5vV
1 9
WREQA 110
SYNCA [1 11
RTxCA 112

WP
AB
3 CE

8530

33
32 (3 0C
31 £33 GND
30 ] WREQB
29 [

5YNCB

RxDA
1 13

3 RTxCB

TRxCA
] 14

1 RxDB

TxDA
] 15
DTR REQA ] 16
RTSA
] 17
CiSA
[ 18
DCDA
] 19

PCLK
£ 20

26 [ TRxCB
25 [ TxDC
24 ] DTRREQ
B
23 [J RTSB
22

CTSB

21 |3 DCDB

RE235

Figure A-6

Table A-2

8530 Pinout

8530 Signal Descriptions

Data Bus

Data Bus Lines
(DO to D7)

8-bit bidirectional bus to transfer data in bytes.

Bus Timing and Reset

Read

(RD)

Write

(WR)

An input indicating that data is to be transferred to the 8530
via one of the serial channels, and enabling the 8530 bus
drivers. Also used to transfer an interrupt vector to the data
bus.
An input indicating that data is to be transferred from the
8530, via one of the serial channels. If RD and WR are asserted
together the 8530 will perform a Reset operation.
(Note that both RD and WR are dependent on the CE signal).

Control
Channel Select

(A/B)

An input which selects whether Channel A or Channel B is to
be used for a Read or Write operation.
|

Chip Enable

An input which enables the 8530 for a Read or Write operation.

(CE)
Data/Control Select

(D/C)

An input which defines the type of information to be
transferred to or from the 8530. High assertion indicates a data
transfer, low assertion indicates a command transfer.

Table A-2

8530 Signal Descriptions (continued)

Interrupt

An output indicating that the 8530 needs to interrupt the

Interrupt Request
(INT)

68000.

Interrupt Acknowledge

An input indicating that the 68000 is processing the 8530
interrupt. When the interrupt daisy-chain stabilizes, RD is
asserted and the 8530 outputs the interrupt vector on the data
bus.
|

Interrupt Enable In
(IEI)
|

An input indicating that the 8530 can interrupt the 68000
MICroprocessor.
|

Interrupt Enable Out
(IEO)

signal to a lower priority device).

Not connected (normally used to output the Interrupt Enable

Serial Data (Channel A and Channel B)

Transmit Data Line

An output signal to transmit serial data at standard TTL levels.

(TxDA, TxDB)

Receive Data Line
(RxDA, RxDB)

An input signal to receive serial data at standard TTL levels.

Channel Control (Channel A and

Channel B)

Synchronization
(SYNCA, SYNCB)

Not connected (normally used to synchronize Read and Write
operations).

Wait/Request
(W/REQA, W/REQB)

A dual-function output that is programmable either as a
Request line for DMA control or as a Wait line to synchronize
the data rate of the 8530 to that of the 68000.

A dual-function output that is programmable (by the DTR bit)

Data Terminal Ready/Request
(DTR/REQA,DTR/REQB)

either as a general-purpose output or as a Request line for
DMA.

Request to Send
(RTSA, RTSB)

An output indicating that there is data ready to transmit on the
serial line.
|

Clear To Send
(CTSA, CTSB)

An input in response to the RTS signal indicating that data can

Channel Clocks
Channel B)

be transmitted.
(Channel A

and

Transmit/Receive Clock
(TRxCA, TRxCB)

Programmable in several modes.

Receive/Transmit Clock
(RTxCA, RTxCB)

Programmable in several modes

Table A-2

8530 Signal Descriptions (continued)

System Clock
Clock
(PCLK)

An input to receive the master system clock 5 MHz signal.
|

Power Supply

+5 volts (Vee)

Ground (GND)
A.4

The power supply input.

The zero-voltage side of the power supf)ly.

8536 COUNTER/TIMER

A.4.1 Overview
|
The 8536 Counter/Timer and parallel 1/O (CIO) is a general-purpose peripheral support IC which
has
three I/0 ports (PA, PB and PC) and three counter/timer circuits (CT1, CT2 and CT3). These are shown
in the basic block diagram of Figure A-7. The ports and the counter/timer are programmed
via the CPU
interface.

PORT A

INT -—

INTERRUPT

INTACK ——
s

CONTROL

INTERNAL BUS

lEl —»1 | 0GIC

PORT
A

IEQ ——
=

DATA
ABUSN

N Ml

~
PORT C

CPU

COUNTER

€ 2] AP —>1 INTERFACE |
SB

TIMER 3

;

Al ——»
. AQ ——P»
CLK =3

: > COUNTER <:>
: T'MER 2

INTERNAL

CONTROL

LOGIC

|
|

COUNTER

PORT B

TIMER 1

RE238

Figure A-7

CIO Architecture

A-10

There are five potential sources of interrupt for events in the CIO. These have the priority CT3, PA, CT2,
PB, and CT1.

A.4.1.1 The CPU Interface - The CPU is accessed and programmed via control, status, and data
registers in internal control logic, via the registers, data can be transferred, ports can be configured,
counter/timers can be programmed and enabled, and status can be monitored.
Data registers for ports A, B, and C can be directly addressed and accessed by means of five control
signals; CE, WR, RD, and A<1:0>. Status and control registers are accessed in a two-stage process via an
address pointer register. Data to or from the addressed register is moved on the data bus.
A 5 MHz signal (CLK) provides a clock signal for the CIO logic. CLK is also divided by two to provide a
count signal for the timer functions of counter/timers 1, 2 and 3.
A.4.1.2 1/0 Ports — A and B are eight-bit I/O ports which can be programmed, as bytes or as individual
bits. They can be input, output or bidirectional. Port C can be programmed as individual input, output or
bidirectional bits. It can also provide handshake signals to support data transfer on ports A or B.

Ports B and C also have a counter/timer function. When so programmed, B<3:0>, B<7:4> and C<3:0>
can be used as external connections to counter/timers 1, 2 and 3 respectively.
To ease the servicing needs of ports A and B when they are used for transferring data, these ports may be
single or double buffered.
A.4.1.3 Counter/Timers — Via the CPU interface, counter/timer registers are loaded with a count value.
The register is then counted down by a clock signal (timer function) or an event signal (counter function).
If needed, the count value can be reloaded without further access by the CPU.

If it is programmed to use the associated I/O port, a counter/timer can be controlled and monitored
externally. If the I/O port is not used, timeout must be reported by interrupt, or the CIO must be polled.
Table A-3 shows the function of external access pins.
Table A-3

Counter/Timer External Access

Function

C/T1

C/T2

C/T3

Counter/Timer Output

PB4

PB 0

PC O

Counter Input

PB 5

PB 1

PC 1

Trigger Input

PB 6

PB 2

PC 2

Gate Input

PB 7

PB 3

PC 3

A.4.1.4 Interrupts — Interrupts are raised by the signal INT (see Figure A-7) and acknowledged by
INTACK. However, for the CIO to raise an interrupt, the interrupt must be enabled by both software and
hardware. The software enable is implemented by writing a bit to a CIO register, and interrupt enable in
(IEI) and out (IEO) provide daisy-chaining connection for a hardware interrupt priority scheme. If IEI is
positive, the IC can raise an interrupt. If the IC is not involved in an interrupt sequence, the positive level is
extended to IEO. Thus the IC nearest the positive source has the highest priority, and the IC furthest away
has the lowest priority.

In the DMB32, CIO interrupts are software disabled, so although the daisy chain is implemented, it has no
effect.
A.4.1.5 Register Selection — There are 48 registers in the CIO, so they cannot all be directly addressed
by bits A<1:0>. For this reason, only the data registers are directly addressed. Control and status registers
can only be accessed after the address has previously been written to a ‘pointer’ register.

Table A-4 shows how the address lines are decoded. An 0, 1 or 2 code on A<1:0>, directly accesses data
registers for ports C, B and A respectively. A 1,1 code specifies a control operation. Higher address lines
are decoded elsewhere in order to generate CE L (The address is F400,4 in DMB32).
All access is
barred unless CE L is asserted.
Table A-4

CIO Register Selection

CE L

Port C

Port B

Port A

Control

None

x = don’t care
The two stages of the control operation are as follows.

Write the register address to the pointer register

Read or write the addressed status or control register

Between stages 1 and 2, many of the CIO internal operations are suspended and status registers are not
updated, so stage 2 should immediately follow stage 1.
Table A-5 lists the register set for the 8536, and gives the address (to be supplied on DAT<5:0>) and the
type of access for each register. Note that the data registers can also be accessed directly (without using
the address pointer).

A-12

Table A-S
Internal

Address
(Binary)
A

Read/Write

000000
000001
000010
000011
000100

000101

000110
000111

8536 Registers

‘

Name

Main Control Registers

R/W
R/W
R/W
R/W
R/W

Port B Interrupt Vector
Counter/Timer Interrupt Vector

R/W
R/W

Port C Data Direction
Port C Special I/0 Control

R/W

Master Interrupt Control
Master Configuration Control
Port A Interrupt Vector

Port C Data Path Polarity

Most Often Accessed Registers

001000
001001
001010
001011
001100
001101

*
*
*
*
*
R/W

Port A Command and Status
Port B Command and Status
Counter/Timer 1 Command and Status
Counter/Timer 2 Command and Status
Counter/Timer 3 Command and Status
Port A Data**

001110

R/W

001111

Port B Data**

R/W

Port C Data**

Counter/Timer Related Registers

010000
010001

R
R

Counter/Timer 1 Current Count MS Byte
Counter/Timer 1 Current Count LS Byte

010010
010011
010100

R
R
R

010101
010110

010111
011000
011001
011010
011011
011100
011101
011110
011111

Counter/Timer 2 Current Count MS Byte
Counter/Timer 2 Current Count LS Byte
Counter/Timer 3 Current Count MS Byte

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R

Counter/Timer 3 Current Count LS Byte
Counter/Timer 1 Time Constant MS Byte

Counter/Timer 1 Time Constant LS Byte
Counter/Timer 2 Time Constant MS Byte
Counter/Timer 2 Time Constant LS Byte
Counter/Timer 3 Time Constant MS Byte
Counter/Timer 3 Time Constant LS Byte
Counter/Timer 1 Mode Specification
Counter/Timer 2 Mode Specification
Counter/Timer 3 Mode Specification
Current Vector

Port A Specification Registers
100000

100001

100010

100011

100100
100101
100110

100111

R/W

Port A Mode Specification

R/W

Port A Handshake Specification

R/W

Port A Data Direction

R/'W

R/W
R/W
R/W

R/W

Port A Data Path Polarity

Port A Special I/O Control
Port A Pattern Polarity
Port A Pattern Transition

Port A Pattern Mask

Port B Specification Registers

101000
101001

R/W
R/W

101010

R/W
R/'W

101011

101100

Port B Mode Specification
Port B Handshake Specification
Port B Data Path Polarity
Port B Data Direction

101101
101110

R/W
R/W
R/W

101111

Port B Special 1/O Control
Port B Pattern Polarity
Port B Pattern Transition

R/W

Port B Pattern Mask

* All bits can be read and some bits can be written,
** Also directly addressable in Z8536 using pins A, and A, .
RE244

A-13

A.4.2

Signal and Pinout

D4 11

'::;
o

The functions of the signals to-and from the 8536 CIO are descrxbedin Table A-6, the power supply and
ground connections are included for completeness. The physical connectlons that correspond to the signals
are identifiedin the pinout diagram Figure A-8.
]

D5 ] 2
D6 . 3
D7 L] 4
RDL 35

39 [ DAT<2> H
38 [ DAT<1> H
37 3 DAT<O0> H

WRL []6

35 [ A1

PBO [] 8

33 [ PAO

PB1 ] 9

PB2 110

31 [ PA2

36 1

34 [ A0

(3 PA1

PB3 [ 11

30 1 PA3

PB4 112

29 [ PA4

PB5 ] 13

28 [ PA5

PB6
PB7
PCLK
IEl
IEO

27
26
25
24
23

] 14
1 15
] 16
317
] 18

PCO 119

[
[
[
[
(3

PA6
PA7
INTACK
L
INTL

22 3 pC3
- PC2

REZ40

Figure A-8

Table A-6

CIO Pinout Details

8536 Signal Descriptions

Address Lines
(A0, A1)

These two lines are used to select the register involved in the
CPU transaction: Port A Data register, Port B Data register,
Port C Data register, or a control register.

Chip Enable

A low level on this input enables the CIO to be read from or

(CE)

written to.

Data Bus Lines
(D0-D7)

These eight‘ data lines are used for transfers between the CPU
and the CIO.

Interrupt Enable In
(IEI)

IEI is used with IEO to form an interrupt daisy chain when
there is more than one interrupt driven device. A High IEI
indicates that no other higher priority device has an interrupt
under service or is requesting an interrupt.

Interrupt Enable Out
(IEO)

IEO is High only if IEI is High and the CPU is not servicing an
interrupt from the requesting CIO or is not requesting an
interrupt (Interrupt Acknowledge cycle only) IEO is connected
to the next lower priority devices IEI input and thus inhibits
interrupts from lower priority devices.

Interrupt Request

This signal is pulled Low when the CIO requests an interrupt.

(INT)
Interrupt Acknowledge
(INTACK)

This input indicates to the CIO that an Interrupt Acknowledge
cycle is in progress INTACK must be synchronized to PCLK,
and it must be stable throughout the Interrupt Acknowledge
cycle.

A-14

Table A-6
Port A I/O Lines
(PAO to PA7)

8536 Signal Descriptions (continued)
These eight I/O lines transfer mformatmn between the CIO
Port A and external devices.

Port B I/O Lines

(PBO to PB7)

These eight I/O lines transfer information between the CIO
Port B and external devices. May also be used to provide

external access to the Counter/Timers 1 and 2.

Port C 1/0O Lines
(PCO to PC3)

These four I/O lines are used to provide handshake, WAIT,
and REQUEST lines for Ports A and B or to provide external
access to Counter/Timer 3 or access to the CIO Port C.

Peripheral Clock
(PCLK)

This 1s the clock used by the internal control logic and the
counter/timers in timer mode. It does not have to be the CPU

clock.

Read
(RD)*

This signal indicates that a CPU is reading from the CIO.
During an Interrupt Acknowledge cycle, this signal gates the
interrupt vector onto the data bus if the CIO is the highest
priority device requesting an interrupt.

Write

(WR)*
*

This signal indicates a CPU write to the CIO.

When RD and WR are detected low at the same time (normally an illegal condition), the CIO is
reset.

A.5

2681 DUART

A.5.1

Overview

Figure A-9 shows the functional blocks of the 2681 Dual Universal Asynchronous Receiver Transmitter

(DUART). There are control registers in every block except the bus buffer (which is a parallel holding
register). It is via these registers that the DUART is programmed and monitored.
When the chip enable line (CEN)is low, the registers can be accessed by read or write actions of the host.
Address lines A3 to AO provide the address. RDN or WRN provides the timing and control. Commands,
status, or data are transferred on the data lines D7 to DO. The operational control block manages these
parallel operations.

Two serial data channels (A and B) perform the parallel/serial and serial/parallel conversion. Each
TRANSMIT channel has a 2-byte buffer. This allows the next character to be loaded while the previous
one is being transmitted. Each RECEIVE channel has a 4-byte buffer to allow for delays in interrupt
response.

Also related to the serial interface are a 7-bit input port and an 8-bit output port. These lines can be used
as individual, sense, and flag lines. Each line has a secondary function which may be used to provide
modem control for the serial data lines.
A 3.6864 MHz crystal provides the basic timing for the timing block. This section contains a programmable counter/timer which can be programmed for many RECEIVE and TRANSMIT data rates. The
counter timer can also be clocked by input port 2.

A
00-07 {
e|

;’

8/
7

BUS BUFFER

Y
N

CHANNEL A

TRANSMIT

HOLDING REG

>~ TxDA

TRANSMIT
SHIFT REGISTER

RDN

WRN

= J

CEN

A0-A3

RESET

OPERATION

4/
v

hant

CONTROL

ADDRESS
DECODE

[ S—

l RIW CONTROL l

RECEIVE

HOLDING REG

(3)

pre——

RECEIVE

RxDA

SHIFT REG

INTERRUPT

CONTROL

INTRN -

P S—

——

CHANNEL 8

(AS ABOVE)

r.-

+ TxDB

«
i

RxDB

~ =

it
@

INPUT PORT

°l

g |

TIMING

l BAUD RATE

GENERATOR l

m——

CHANGE OF

STATE

[oeTEcToRs (|

7
fe—K

IPO-1P6

IPCR
ACR

CLOCK

SELECTORS
>

COUNTER/
TIMER

(

OUTPUT PORT

FUNCTION
.

S;_%&%T

:
X1/CLK

XTAL OSC l

‘

> OP0-OP7

n-finanfin-CSR

CSRB

ACR

_ CTUR
CTLR

RO1170

Figure A-9

2681 Dual Universal Asynchronous Receiver Transmitter

Interrupts are generated when at least one of eight maskable interrupt conditions
occurs. INTRN will
inform the controlling processor of chan ges in the DUART status. The interrupt routine
should read status
and then take the appropriate action.

The DUART can also be operated in the polled mode.
Characters to be transmitted must be written to the appropriate transmit holding register.
Received characters must be read from the appropriate receive holding register.
A.5.2

Signals and Pinout

a0 [1]
P3 [2]

a1 [T
P (@]

A2 5
A3 (€]

35]

wo [7]

34] RESET

WRN [8

33] x1CLK

RON [9
RXD8 [10

csN

32] x2
SC2681

31] RXDA

TX08 [11,

[30] TxDA

op1 [12]

28] opo

or3 (i3]

28] oP2

ops [i4]

27] oP4

op7 [i5]

26] OP6

01 [18]

25]
Do

03 [i7]

24]
D2

05 [18

D4
23]

22]
06
21] INTRN
RD1171

Figure A-10

2681 Pinout Diagram

A pinout diagram is provided in Figure A-10. The related signal functions are listed
in Table A-7. This
information applies only to the 40-pin DIL version of the 2681.

A-17

Table A-7

2681 Signal Descriptions

Used to transfer commands, data, and status between the

Data Bus
(DO to D7)

DUART and the CPU. DO is the least significant bit.

Chip Enable
(CEN)

When low, data transfers between the CPU and the DUART
are enabled on DO to D7 as controlled by the WRN, RDN, and
AO to A3 inputs. When high, places the DO to D7 lines in the 3state condition.

Write Strobe
(WRN)

When low, and CEN is also low, the contents of the data bus
are loaded into the addressed register. The transfer occurs on
the positive-going edge of the signal.

When low and CEN is also low, causes the contents of the

Read Strobe
(RDN)

addressed register to be placed on the data bus. The read cycle
starts
on the negative-going edge of RN.

Address Inputs
(A0 to A3)

Select the DUART internal registers and ports for read/write
operations.

Reset
(RESET)

A high level clears the internal registers (SRA, SRB, IMR, ISR,

OPR, OPCR), puts OP0O to OP7 in the high state, stops the
counter/timer, and puts channels A and B in the inactive state
with the TxDA and TxDB outputs in the mark (high) state.

Interrupt Request
(INTRN)

A low level signals to the CPU that one or more of the eight

Crystal 1
(X1/CLK)

Crystal or external clock input.

Crystal 2

Connection for the other side of the crystal.

maskable interrupting conditions are true.

(X2)
Channel A Receiver Serial Data Input
(RxDA)

The least significant bit is received first. Mark is high, space is
low.

Channel B Receiver Serial Data Input
(RxDB)

The least significant bit is received first. Mark is high, space is

Channel
Output
(TxDA)

The least significant bit is transmitted first. This output is held

Transmitter
|
'

Serial
|

Data

low.
in the mark condition when the transmitter is disabled, idle, or
when operating in local loopback mode. Mark is high, space is
low.

(OPO to OP7)

General purpose outputs.

(IPO to IP6)

General purpose inputs.

(Vo)

Power supply +5 V supply input.

(GND)

Ground.

A-18

APPENDIX B

GATE ARRAYS

B.1 OVERVIEW
This appendix contains brief functional descriptions, and signal information
for the gate arrays used on the
DMB32.
These arrays are:

B.2

Address Translation Gate Array (ATGA) - Appendix B-2

Control Gate Array (CGA) - Appendix B-3

ADDRESS TRANSLATION GATE ARRAY (ATGA)

B.2.1 Scope
The ATGA is a CMOS array designed to perform address translation tasks and to multiplex
addresses for
the DMB32 common address store, CASRAM. Arbitration between ports
is not an ATGA task, but is
done by the CGA and BIIC.
|
A pinout diagram of the ATGA is shown in Figure B-1.

B.2.2 Derivation Of CASRAM Addresses
Address translation functions performed by the ATGA are shown in Figure B-2. The
inversion function
applied to the secondary address is to correct for differences between VAX-11
and 68000 addressing

structures.

Address outputs RA<10:00> from the ATGA can be of eight types.
-

Sync FIFO Address

RX FIFO Address

TX Action FIFO Address

DMA File Address

‘0’ Address (all zeroes)

Index from Async Base Offset

Index from Sync Base Offset

Direct (not translated)

B-1

VDD

RAD5

fjgo

RAD3

RAD1

JAMOL | ©ner

| DMAENL|

64
RAD2

62
| RADO

60
VES
58
56
(pxep) | DSTRBL [ INCR

DMARSL | SECENL

2
PASTRB |

1
PRIWE |

66
RAD4

KEY

PAD5

PAD4

SAD5

390

333
(RCMD)

PAD3

PAD2

(RCMD,) |

PAD7

PADS

SAD3

PADS

gss

ATGA

(TOP VIEW)

| PAD10

RAD7
2

SAD2

48
|

SAD4

SAD6

SAD10 |

SAD9

37
sap12

PSELOL | PSEL1L | RADG
19

51
SADT

41
ga
SAD8 | (RemD)

PADS

16
15
PAD13 | PAD12
17

SAD7

PAD11

52
SADO |

| ReMD)

54
| SASTRB [

RAD8

26
vss

38
| SAD11
36

| RAD10 | (riep) | RAMOEL | RESETL | SSELEL | SAD14 | SAD13
25

VoD

RADY | (Fixep)

TSTENL | SECWEL | SSEL1L | SAD15
7

11
RE1438

Figure B-1

ATGA Pinout Diagram

Primary (VAXBI) addresses are decoded to identify an address:
e

Of a directly addressed register (no translation)

Of a channel-specific register

OfaFIFO

If the address is that of a directly addressed register, it is passed untranslated to RA<10:00>.

If the address is that of a channel-specific register, it is indexed by the channel number held in the ACSR
or SCSR registers.
If the address is that of a FIFO, the appropriate FIFO controller is enabled, and the address of the next
available location in that FIFO is output.
Except when they point to a FIFO, all secondary addresses are direct, and are passed, after inversion,
directly to RA<10:0>.
FIFO addresses supplied on the secondary port are decoded to identify the FIFO. The appropriate FIFO is

then enabled.

B-2

CASRAM

N
DMA
DMA FILE ADDRESS [FILE

ONTROLLER

_—:> DECODE

| @'A TO/FROM REGISTERS

(NO

DIRECT

SLATED)

~DIRECT
DIRECT ADDRESS

ADDRESS

NOT

>$
Al

DIRECT ADDRESS | DIRECT N

(INVERTED ONLY) | heeone . [N\ —

TRANSLAT

|
|

FROM BIIC
< —
ADDRESS :> DECODE :> LOGIC ADDRESS>
ALL'O's
PRIMARY

INDIRECT

,
ADDRESS

INDEXING | INDEXED
,

LOGIC

AN
© ol

= 2|

—

DECODE |

—
SECONDARY

READ FROM

EMPTYFIFO

ENABLE APPROPRIATE ,_l FIFO

FIFO CONTROLLER

ADDRESS
—

)

Zggaess

INVERSIO

|INVERSION

CONTROLLERS
|

NABLE
giPGROPR!ATE

;‘;gfigss /1—
DECODE

\r—

CONTROLLER

PRIMARY SECONDARY DMA

SELECT

FIFO ADDRESS

= Tx FIFO ADDRESS

OR Rx FIFO ADDRESS
OR SYNC FIFO ADDRESS

SELECT

R
v

FROM CGA
RE246

Figure B-2

Representation of Address Translation Functions

In DMA transactions, the DMA file controller provides a pointer to a DMA buffer address stored in
CASRAM. The controller then functions as an address pointer for a DMA file established in CASRAM.
Before initiating a DMA transaction, the microprocessor loads the DMA file register with the appropriate
pointer address.
|

‘0" address is an ‘all zero’ address that is output if JAM “0” L is asserted or an empty FIFO is read.
To access the ATGA internal registers, data is transferred via the multiplexed secondary address/data bus.
Data is transferred without being inverted (see Figure B-2), to and from registers in the blocks marked *.
NOTE
The primary-port normally has no access to ATGA
registers, but when certain registers in CASRAM
are written, the data is also written to the appropriate ATGA register.
|

B-3

B.2.3 ATGA Register Overview
To support its address translation functions, the ATGA holds address
information. For example, to index
an async address, the ATGA must hold the ASYNC.IND.ADDR
bits from the ACSR. This information
is heldin the internal ATGA registers listed in Table B-1, which
also indicates the addresses and access
restrictions for both the primary and secondary ports. Note that secondar
y addresses are the inverse of
primary addresses.

Table B-1

ATGA Register Map

Primary
Address*

|
|
‘Access |

Base + 104

Base + 108

Base + 220

Base + 224

Secondary
Address**

Access

Async CSR (ACSR)

Base + 1EF8

Sync CSR (SCSR)

Base + 1EF4

*** FIFO Status (FSTAT)

Base + 1DDC

*** DMA File Address

Base + 1DD8

(DFADD)

Base + 228

Base + 22C

~
-

***FIFO Reset (RESET)

Base + 1DD4

*** Last RAM Address

Base + 1DDO0

*** Tx Act FIFO Base

Base + 1DCC

*** Sync FIFO Base

Base + 1DC8

(LRADD)

Base + 230

(TABASE)

Base + 234

WO
|

(SFBASE)

Base + 238

*** Rx FIFO Base
(RFBASE)

Base + 1DC4

Base + 23C

*** Sync CSR Base
(SCBASE)

Base + 1DCO

Base + 240

*** Async CSR Base

Base + 1DBC

(ACBASE)

* Base is decode of VAXBIID |
**

Base" is decode of 68000 address bits A<15:12>

oxk Ai:céssiblé in maintenance mode only
WO = Write only.

RO = Read Only.

NOTE
ATGA reglsters are only 16 bits wide. The most
significant word of the longword address is in
CASRAM.
The async and sync CSRs exist in the CASRAM,
but they are also duplicated in the ATGA. The

ATGA registers hold only a subset of the full CSR

contents.

B-4

B.2.4 SIGNAL DESCRIPTIONS
|
<
|
The ATGA has 55 Signal connections and 8 power and ground connections. Each
of the signals 1is

described in Table B-1.

Table B-2

ATGA Signal Descriptions

VDD

+5 V power connections (4 off)

VSS

Ground connections (4 off)

PA<12:02> H

The primary address port consists of 11 lines which are used to pass
address information to the ATGA. When interfaced to the BIIC signals
PA<12:02> H have a one to one correspondence to BCI D<12:02> H.

PA<13> H

PA<13> is an additional primary address input and is used to enable
direct mapping of all 2 Kbyte Common RAM Store locations.

On the DMB32, PA<I13> is connected to BCI D<22> H and is used to
detect ‘Adapter Window Space’ accesses. This feature is provided for
diagnostic use.

SAD<15:00> H

The secondary address port consists of 16 bidirectional lines which provide

a multiplexed information path, used to pass address and data information

to and from the ATGA.

The input address is assumed to run from AO to A15, thus the interface
from the 68000 should drive the least significant bit to a logic 0 when
accessing the Common Address Store. This is required since the 68000
does not provide an A0 output, but uses dual data strobes. The ATGA will
not use the A0 input since it only produces Longword address information
for Common RAM Store Access, and permits only longword or word
length accesses to internal registers. Byte and word accesses of CASRAM
are controlled through the derivation of the RAM selects which on the
DMB32 module are generated by the CGA.

DATASTRB L

The data strobe signal is an active low input which is used to enable data
information onto the secondary bus. The direction of data flow on this bus
is determined by SECWE L for secondary port access and PRIWE L for
primary port access. The DATASTRB L signal must be active during data
transfers initiated from either port, and for both input and output.
Data I/O to the BIIC passes via the secondary bus, not directly onto the
primary bus.

On the DMB32 module this permits the data hold time to be controlled by
the CGA because the data is held in the latches which separate the
primary and secondary buses.
PASTRB H

The primary port address strobe is an active high signal which indicates

the start of a cycle on the PA<15:00> H lines. This signal allows an
address to be latched by the primary port during a secondary port access.
This condition arises when DTACK has been issued to the microprocessor
by the CGA.
PASTRB H is directly used to latch the valid address information. In the
DMB32, PASTRB H is connected to BCI CLE H from the BIIC.

B-5

Table B-2

ATGA Signal Descriptions (continued)

SASTRB H

The secondary address strobe is an active high signal which, when
asserted, causes the secondary port address latches to become transparent,
and latches the SAD<15:0> lines when de-asserted.

SECENB L

The secondary port enable signal indicates which of the two ports is
allowed to access the CASRAM. A high logic level indicates that the

primary port has access.

PRIWE H

PRIWE H is the primary port write enable signal. This signal indicates
whether the present cycle is a Read or Write access.
~

In the DMB32, PRIWE H is connected to BCI I<2> H and
is latched by

the de-asserting edge of PASTRB.

The use of BCI I<2> as a WE H signal causes the following VAXBI
commands to be interpreted as WRITE commands; WRITE, WCI,
UNLKM, WMCI, INIT, INVAL, BROADCAST and IP INTR.
SECWE L

The secondary port write enable signal indicates whether a current
secondary port cycle is a Read or Write (asserted = write).

INCR H

This is an active high level input signal, the asserting edge of which causes
the DMA file address register value to be incremented by one (longword)
address. (Providing that DMA ENB L is asserted).

RA<10:00> H

The 11 RAM address lines form the translated address information
derived from the incoming address of either port. Note that address
‘information passing via the ATGA from the secondary port is inverted
prior to output on the RA<10:00> lines. This feature caters for the

differences between the data structures of the 68000 microprocessor and
the host.

SECSEL<1:0> L

The secondary port select signals are active low inputs and when both
asserted, enable the ATGA to translate the address information on the
secondary port. These signals must remain asserted throughout the
information transfer.

If the address bit SAD<13> is set to a logic “1” then the 8 Kbytes of
Common RAM Store will be directly addressed. (The FIFOs and internal
CSRs will be disabled and all CASRAM locations will be directly
mapped).
For primary port transactions, the CGA determines whether the addressed
location is accessible. (The CGA has control of the data path routing logic
and the Common RAM Store enable signals).

B-6

Table B-2

PRISEL<1:0> L
~

ATGA Signal Descriptions (continued)

If either of the two primary port select signals are asserted, the ATGA is

enabled to decode the primary port address.

Use of two input selects

permits the use of the BIIC select code outputs.

On the DMB32, PRISEL<0> L is connected to BCI SC<0> L, to enable
detection of VAXBI accesses to user CSR Space. PRISEL<I> L is

connected to BCI SC<1> L to enable detection of VAXBI accesses

VAXBI adapter window space.

The PRISEL <1:0> L signal is not required to be active throughout a
transfer. The current transfer is determined to be completed on the deasserting edge of the DATASTRB L signal, whereupon the RA<10:00>
H lines shall return to their default “0” address.
DMAENB L

DMA enable is an active low input signal which when asserted, causes the
contents of the DMA file address register to be driven onto the
RA<10:00> output lines. Assertion of this signal enables the DMA file
address counter to be incremented by INCR H.

JAM “0” L

Assertion of the signal forces all Os on the RA<10:00> lines.

DMARST L

When asserted, DMARST L causes the DMA file address counter to be
reset to its initial condition. In the event of an error this enables the CGA

to retry certain transfers, without intervention from the microprocessor.

RESET H

When asserted, RESET H initiates a total chip reset. This signal must be
asserted at power-on. This operation is externally identical to the soft reset
provided by the chip reset bit within the internal reset register.

ROE L

RAM address output enable is an active low signal, and, when asserted

enables the RA<10:00> H lines. If this signal is deasserted, these address
lines adopt a high impedance state. This feature is not used on the
DMB32, but can be used during device test. An internal pull down resistor
is provided, so that the RA<10:00> H lines are enabled if left open
circuit.
TESTENB L

This is an active low signal, which, if asserted, enables the test functions
within the ATGA. An internal pull up resistor is provided and the signal is
deasserted if left open circuit. Assertion of TESTENB affects the
operation of RXFIFO and is used only in device testing. If the signal is
asserted with DMARSR L, then PA<22>, PA<12:02> and PRIWE
become outputs, providing a test facility for the address decode logic.

B-7

B.3

CONTROL GATE ARRAY (CGA)

B.3.1

Scope

The CGA is a large scale integrated circuit, designed to provide an interface to the

I/O nodes such as the DMB32. The major components of the CGA are

BCI Slave Port Sequencer

BCI Master Port Sequencer

Busmux Sequencer

BIIC, as required by

identified as follows:

An additional feature of the CGA is that it is able to handle
the majority of the DMB32 68000
memory/peripheral decoding tasks. The user interface to th
¢ CGA is via a 16-bit address/data multiplexed bus, whose control is internal to the CGA.

A pinout diagram of the CGA is shown in Figure B-3
|

120
117
116
,
BCIEVLO | BCIEVL3 | BCIEVL4 |

LDSL

UbsL

7
BCIMABL | AIOMHZ |

RST

111

,
108|107
ENBMICP.
[ cNSMICP
[ 1osELL
[RamsELL|

112
119
115
DATACAS
| BCIEVLY | wRLDSL | DA

6
5
|
vss
BCIIDLO | SECWEL | oty

BCDL2 |

113

ROL

118
114
|
14
| BOIEVL2 [ wRuDsL

4
ASL

105
109
VDD
INTRGL | eixep) |
110

106

lensmicr|
[ENEMIC

vss
Fixeo)

104

101

A12

A15

103
A13

| 99
,
| BUSRaL

| 100
’
| CASSELL

102

| 98

A14

| oTackL

86
Fco

KEY
PIN

16
VSS

CGA

(TOP VIEW)

25
BCIRAKL | BCIMDEL |

BCII2

BCI1

BCIO

| BCICLE

BCISDEL |

VDD

BCIINTL

BCID9

INCR

|SEcensL |PMARESE|DATASTR|
TL

SASTRB | BCID12

46
VSS

BCID11

(Fixep)

BCID4

54
sAD1

58
saps

71
| sAD12

67
|

sAD8

69
| sAD10

61
VSS
65
66
[ gemp, [ BCID3O | BCID3?
59

(FIXED)

on 0. | VDD

| BCID22 |

BCIDI

| capis

70
| saD11

31
VSS
34
| (Remp,) | JAMOL |

DMAENBL|

BCI3

>ral |36

RCEL1

VSS

sap9

RCEL2 |

cAD13 | cap14

BC)IDL3| BCINXTL | BCISELL

(FIXED) | (FIXED) | 4

83
| RCEL3

RCELO | DECODEE | TESTENB
NB
L

BCIRGLO | BCIRGLO | BCIRSL1

ROEL

BCIRSLO | (FixeD) | (FIXED)
18

FC2

RWEL

VDD

BUSCEL

94
91
89
LATCHBC | VSs
|/
(Rempy | INTACKL |

ENBBCIC

87
FC1

BCITIME | BCIDCLO | BCIPHAS
L

LTCHUPA|

97
95
92
ENBUFAD | ADDRCAS| LATCHCA
|ENE
e
o

| BCDLA

|LTS

BCIDS

BCID2

SADO

sap3

sapa

sap7

RE1438

Figure B-3

CGA Pinout Diagram

B-8

B.3.1.1 Overview — VAXBI slave port transfers are conducted by the BIIC
independent of any external
control, while VAXBI master port transfers require only the setting up of an address/da
ta file and a write
to the BCOM register to initiate the transfer.
Master and slave sequencers are independent in their operation and will handle
transfers from longword
through to octaword in length. This independence permits the use of loopback transaction
s, either locally,
using the BIIC LOOPBACK, or by the node initiating a VAXBI transactio
n addressing its own
node/window space.

The CGA provides a programmable number of STALL cycles for VAXBI, Busmux and 68000
transactions.

Unimplemented CSRs receive NOACKSs on the VAXBI during normal operation, although
all 8 Kbytes of
node space is accessible in maintenance mode. In addition up to 256 Kbytes of the
68000 memory space,
are accessible via VAXBI window space in maintenance mode.
VAXBI interrupts are supported at one of 3 programmable levels via the
BCI INT<7:4> L lines, the
resulting levels being dependent on the connection of these three lines.

BIIC external vectors are supported via a CGA internal interrupt vector register capable
of supplying one
of 3 prioritized codes, dependent on the interrupting condition defined by the BINT
register within the
CGA.
A single interrupt is provided for use by the 68000, which may be masked for

specific CSR activity.

general VAXBI and/or

Figure 3-14 in Chapter 3 shows how the CGA may be interfaced to the BCI and
a 68000 bus, and shows
its use on the DMB32 module.

B.3.2 CGA Register Overview
,
The internal registers of the CGA are listed in Table B-3. The table gives the
addresses and access
restrictions for both the primary and secondary ports. Note that secondary addresses
are the inverse of
primary addresses.

Table B-3

CGA Register Map

Primary
Address*

Access

Secondary
Address**

Access

Base + 100

Maint CSR (MAINT)

Base + 1EFC

Base + 104

Async CSR (ACSR)

Base + 1EF8

Base + 108

Sync CSR (SCSR)

Base + 1EF4

Base + 10C

Printer CSR (PCSR)

Base + 1EF0

Base + 280

Base + 1D7C

*** Async Line Param
(ALPRC)

Base + 284

*** Async Line Control
(ALC)

Base + 1D78

Base + 288

*** Async Preempt (APC)

Base + 1D74

Base + 28C

- *** CSR Change (CSRC)

Base + 1D70

Base + 290

*** Device Setup CRS

Base + 1D6C

*** VAXBI Command

Base + 1D68

Base + 294

(DSCSR)

(BCOM)

Base + 298

*** VAXBI Data Mask
(BMSK)

Base + 1D64

Base + 29C

*** VAXBI Vector (BVEQ)

Base + 1D60

Base + 2A0

*** VAXBI Interrupt (BINT)

Base + 1D5C

Base + 2A4

*** Micro Delay (MDEL)

Base + 1D58

Base + 2A8

¥** VAXBI Summary
(BSUM)

Base + 1D54

Base + 2AC

¥** VAXBI Delay (BDEL)

Base + 1D50

Base + 2B0

*** Micro Interrupt (MIMK)

Base + 1D4C

Base is decode of VAXBI ID

Base is C000,, if internal CGA decode is selected

*** Accessible in maintenance mode only

WO = Write only.

RO = Read Only.

RW = Read/Write.

B-10

CGA registers are only 16 bits wide. The most significant word of the longword address is in
CASRAM.

The async and sync CSRs exist in the CASRAM,
but they are also duplicated in the CGA. The CGA

registers hold only a subset of the full CSR contents.

B.3.3 Signal Descriptions

The Control Gate Array has 108 Signal connections and
12 power and ground connections. Each of the
signals are described in Table B-4.

Table B-4

CGA Signal Descriptions

Data Signals
PA<12:01> H
|

The primary address port consists of 11 lines which are

used to

pass address information to the CGA. When interfac
ed to the

BIIC signals PA<12:01> H have a one-to-one correspondence
to BCI D<12:01> H PA<9:3> H are additionally used
as
device test outputs.
PA<l13> H

The PA<13> H is an additional primary address input and
is
used to enable direct mapping of all 2 Kbyte Common
RAM
Store locations. On the DMB32 module PA<13> H
is
connected to BCI D<22> H to provide recognition of adapter
window space access as distinct from node space access. This

feature is provided for diagnostic use.
PA<15:14> H
,

PA<I15:14> H indicate the number of longwords associa
ted

with a VAXBI transaction:

15
0
0
1
1

SAD<15:00> H

14
O
1
0
1

Transfer length
Illegal
Longword
Quadword
Octaword

PA<15:14> are connected to BCI<31:30> on the DMB32

The secondary address port consists of 16 bidirectional
lines
which provide a multiplexed information path, used to
pass
address and data information to and from the CGA. On
the
DMB32 module this bus is interfaced to a microprocessor
bus
via an external interface. The timing of this multiplexed
bus is
controlled by the data and address strobe signals generat
ed by
the CGA.
The input address is assumed to run from A0 to A15, thus
the
interface from the 68000 should enable the A1 address bit
onto
SAD<1>, SAD<0> being ignored.

B-11

Table B-4

CGA Signal Descriptions (continued)

Busmux Interface Control Signals

LTCH UP ADDR H

This signal is an active high output which is used to latch
primary port addresses into the Busmux interface address

latches. Address information is latched on the asserting edge of
LTCH UP ADDR H.
This signal will be asserted during primary port accesses of the
68000 przvate bus.
DATA CAS UP H

Thisis an active high s:)utput signal and when asserted causes
the Busmux interface data transceivers to pass data from the
Busmux to the 68000 private bus, and vice-versa when
deasserted.

ADDR CAS UP H

This 1s an active high output signal and when asserted causes
the Busmux interface address latches to pass information from
the Busmux to the 68000 private bus, and vice-versa when
deasserted.

ENB UP ADDR L

This active low output signal is used to enable the Busmux
interface address latches. The direction of information flow is

controlled by ADDR CAS UP H.
ENB MICRO LSW L

This active low signal permits the data transceivers of the
Busmux interface connected to the least significant word of the
32-bit CAS BUS. The direction of data flow through the
interface is controlled by DATA CAS UP H.

ENB MICRO MSW L

This active low signal permits the data transceivers of the
Busmux interface connected to the most significant word of the
32-bit CAS BUS. The direction of data flow through the
interface is controlled by DATA CAS UP H.

Primary Port (BCI) Data Path Control
Signals
LATCH CAS L

The asserting edge of this active low signal is used to latch
information from the 32-bit CAS BUS into the BCI input
latches.

LATCH BCI L

The deasserting edge of this active low signal is used to latch
information from the BCI D<31:0> H lines into the BCI output
latches.

ENB BCI CAS L

This active low signal is used to enable the BCI output latches
onto the 32-bit CAS BUS.
The associated enabling of the BCI input latches is not under
the control of the CGA but these latches must be enabled by
the assertion of BCI MDE L or BCI SDE L.

B-12

Table B-4

CGA Signal Descriptions (continued)

CASRAM Control Signals
CASOEL

This signal is used to provide the output enable control for the
Common Address Store.

The period of assertion of CAS OE is controlled by the BDEL
register for VAXBI slave accesses, and the MDEL Register for
Busmux accesses.
For master sequencer reads of the CASRAM the CAS OE L
assertion period is dependent on the slave node response, but
has a minimum pulse width of 200 ns (nominal).
CAS WE L

This signal is used to provide the write enable control of the
Common Address Store RAM.

The period of assertion of CAS WE is controlled by the BDEL
register for VAXBI slave accesses, and the MDEL register for
Busmux accesses.
VAXBI master sequencer writes to the CASRAM use a fixed
75 ns (nominal) CAS WE assertion period.

CAS CS<3:0> L

These signals are used to provide the chip select control of the
Common Address Store RAM.
The period of assertion of CAS CS<3:0> is controlled by the
BDEL register for VAXBI slave accesses, and the MDEL
register for Busmux accesses.

For master sequencer reads of the CASRAM the CAS

CS<3:0> L assertion period is dependent on the slave node

response, but has a minimum pulse width of 200 ns (nominal).

68000 Control Signals

SECWE L

The secondary write enable signal indicates whether a current
secondary port cycle is a read or write (active low) operation.
This signal is an input at power up, and during normal

operation, but is an output during mastership of the 68000
private bus. This signal is connected to the 68000 R /W signal.

SECSEL<1:0> L

The secondary port select signals are bidirectional signals.
When configured as inputs they are active low signals, which,
when asserted enable the CGA Busmux sequencer to initiate a
transfer via the secondary port. These signals must remain
asserted throughout the information transfer.

SECSEL<O0> is connected to the 68000 address strobe (AS L),
and is bidirectional, being driven by the CGA during
mastership of the 68000 private bus.
SECSEL<1> is decoded from the 68000 address lines. The
required decode logic for DMB32 is provided within the CGA,
and this signal is an output, when DEC ENB H is asserted. If
the signal DEC ENB H is deasserted SECSEL<1> is an input,
permitting the use of any external decode.

B-13

Table B-4

CGA Signal Descriptions (continued)

INTRQ L

This is an active low signal, which, when asserted causes an
interrupt to the 68000 microprocessor. The assertion of this
signal may be prevented through use of the MIMK register in
the CGA. The signal will remain asserted until a read of the
interrupt register has occurred, indicating that the interrupt
service routine has been entered.

This implementation of interrupt acknowledgment does not
support “daisy chaining” of interrupting devices, nor the
programmed vector capability of the 68000.

On the DMB32 the INTRQ L line will be connected to the
interrupt line from the four 2681 DUARTS on the board.
UDS L

This active low signal is used to indicate participation of the
upper byte in any 68000 transfer. It is an input at power-up and
under normal operating conditions. During CGA mastership of
the 68000 private bus, only possible in maintenance modes, it is
an output fulfilling the 68000 timing requirements.

LDS L

This active low signal is used to indicate participation of the
lower byte in any 68000 transfer. It is an input at power-up and

under normal operating conditions.

During CGA mastership of the 68000 private bus, only possible
in maintenance modes, this signal is an output fulfilling the
68000 timing requirements.
DTACK L

This active low output signal is
acknowledgment for 68000 bus cycles.

used

provide

If the input DEC ENB H is asserted, DTACK is produced for
all internally generated select signals (memory and 1/0). The
number of WAIT cycles involved in memory/peripheral

accesses is programmable:

0to 3 cycles for each of two banks of I/0

0Qor 1 cycles for ROM and RAM

1to7 cycles for CAS

6 or 7 cycles for INTACK acknowledge cyciles through

use of the MDEL register

If the input DEC ENB H is not asserted then DTACK L will be
issued only for accesses to CASRAM, (CAS SEL L assertion)
thus permitting the use of external decode for all devices on the
68000 private bus.
BUSGR L

This active low signal is used to indicate that the 68000

will
release control of its bus at the end of the current bus cycle.
Therefore all related CGA output signals remain tri-stated until
AS L is also deasserted.

B-14

Table B-4

BUSRQ L

CGA Signal Descriptions (continued)
This active low output signal is used to request masters
hip of
the 68000 private bus, to permit access to this bus from
the
VAXBI.

The signal will remain asserted 'thmughout CGA bus
mastership, and the 68000 acknowledgment signal BGACK

is not used.

Maintenance modes 1 and 2 enable the 68000 private bus to
be
accessed from the VAXBI, the CGA taking control of
the
68000 bus through BUSRQ L. In maintenance mode 1, control

of the 68000 bus will be requested for any access to window

space only and released after access is completed.

Maintenance mode 2 causes the CGA to request control of the
68000 bus. Control will be retained until maintenance mode 1,

or no maintenance mode, is selected.

Maintenance mode 3 causes the CGA to request control of the
68000 private bus, but prevents any control signals from
being
driven. This allows an external test device to drive the
68000
control signals and verify the operation of the CGA
microinterface logic, the CGA Busmux sequencer, all devices on the
68000 private bus and the CASRAM.
WR UDS L

Write upper data strobe is an active low signal generated
from
the logical AND of UDS L with SECWE L (68K R/W). It
is
synchronized to the 10 MHz H output.

WR LDS L

Write lower data strobe is an active low signal generated
from
the logical AND of LDS L with SECWE L(68K R/W). 1t is
synchronized to the 10 MHz H output.

RDL

Read is an active low output signal generated during 68000
read cycles. For accesses to memory, RD L is the logical
AND
of AS L with the inverse of SECWE L(68K R/W). For devices
in I/O bank 2, the time from the 68K AS L assertion to RDL
assertion is programmable, controlled by a field in the MDEL
register.

INTACK L

Interrupt acknowledge is an active low signal generated
from
the logical AND of the 68000 function code signals (FC<2:0>)
with the inverse of AS L.

Note that FC<2:0> L are not driven when the CGA has control

of the 68000 bus, and INTACK L is gated off by the assertio
n
of BUSGR L to avoid this output being indeterminate.
RAM SEL L

RAM select is an active low signal generated during 68000

accesses to the address range 32 to 40 Kbytes.

RAM SEL L is derived purely from 68000 address bits
13
through 15 (A<15:13>).

B-15

Table B-4

I/O SEL L

CGA Signal Descriptions (continued)

I/O select is an active low signal generated during 68000

accesses to the address range 56 to 64 Kbytes.

I/O SEL L is derived purely from 68K address bits 13 through
15 (A<15:13>).

FC<2:0> H

The three function code bits are used to determine when the

68000 is executing an interrupt acknowledge cycle, refer to
INTACK L.

A<15:12> H

10MHZ H

Address bits 13 through 15 are used to derive the [/O SEL L
and RAM SEL L output signals. A<12> is used internal to the
CGA to enable different DTACK L and RD L Signal delays for
each of two I/0 banks.
This is a 10 MHz clock signal derived from the 20 MHz clock,
TIME L, and synchronized to the 5 MHz clock, PHASE 1.

68000 bus cycles are synchronized to VAXBI bus cycles by use
of this signal as the 68000 clock input.
ATGA Control Signals

DATASTRB L

The data strobe signal is an active low level output used to
enable data information onto the secondary bus. The direction
of data flow on this bus is determined by the WE L signal,

(SECWE L for secondary port access and PRIWE L for
primary port access). Therefore, the DATASTRB L signal

must be active during data transfers initiated from either port,
and for input and output.

DATASTRB L is asserted for writes to the least significant
byte or for any read of the least significant word, of any
CASRAM longword CSR. Exceptions to this are accesses to
RAM by the master sequencer, when there will be no assertion
of DATASTRB L, and during VAXBI IDENT operations with
BIIC external vector fetch.
Data I/O to the BIIC passes via the secondary bus rather than
directly onto the primary bus. This permits a reduction in the
gate array I/O count and assists in reducing the complexity

SECENB L

The secondary port enable signal indicates which of the two

ports has been permitted access to the RAM Store, a high logic
level indicating that the primary port presently has access. By
default this signal is asserted, being deasserted only during
primary port accesses.

SASTRB H

|
DMAENB L

Secondary address strobe is an active high signal which is used
to latch address information from the Busmux, during a
secondary port access (68K) of CAS, on its deasserting edge.
DMA enable is an active low output signal, used to enable the
DMA file address register, within the ATGA, onto the
CASRAM address lines.
|

B-16

Table B-4
DMARST L

CGA Signal Descriptions (continued)
- DMA reset is an active low output signal and when asserted
causes the least significant 3 bits of the DMA file address to
be
reset to their initial value (111).

INCR H

This is an active high level output signal, which, on the asserting
edge, causes the DMA file address value, held within the
ATGA, to be incremented by one (longword) address. This is

providing that the DMAENB L signal is asserted. When this
output is asserted within DMAENB L, the slave sequencer
within the CGA attempts to increment a longword count for
slave transfers of quad/octa word length.

The assertion of INCR without DMAENB causes no action.

RST OUT H

Reset out is an active high output signal generated from BCI
DCLO L, or the programmed reset bit within the MAINT
Register.
The period of RST OUT H assertion is equal to that of BCI
DCLO L, or, for a programmed reset, is a minimum of 800 ns.

JAM
O L

This is an active low output signal which will be asserted by the
CGA during VAXBI IDENT transactions involving the
module. This provides for BIIC external vector support, in that
the most significant word of the external vector is fetched from
location ‘0’ of CASRAM. The ATGA will jam all Os onto the
CASRAM address lines in response to the assertion of JAMO L.

BIIC Interface Signals
PASTRB H

The primary port address strobe is an active high signal which
indicates the start of a cycle on the PA<15:00> H lines. This
signal permits an address to be latched by the primary port
during a secondary port access. This condition arises when an
acknowledgment, DTACK L, has been issued to the active
device on the secondary port.
PASTRB H is used directly to latch the valid address
information and on the DMB32 module, is connected to BCI
CLE H from the BIIC.

BCI SEL L

The BCI select signal is an input to the CGA, and when
asserted, indicates the valid selection of this node by a VAXBI
transaction. The BIIC checks for bus errors, verifies node ID,
and asserts the SEL signal if the transaction type has been
enabled via the BCI control register.

B-17

Table B-4

BCI RS<1:0> L

CGA Signal Descriptions (continued)

The response codes RS<1:0> L are active low outputs
controlled by the CGA slave sequencer.
10
HH

Description
NOACK

NOACK

ACK

ACK, NOACK

STALL

STALL, ACK or NOACK

RETRY

RETRY, NOACK

Possible BIIC outputs

The default output for the CGA slave sequencer is NOACK,
and the RETRY code cannot be generated by the CGA.
BCI RQ<1:0> L

BCI EV<4:0> L

The request lines, RQ<1:0>, are active low output signals
enabled by the CGA master sequencer, the enabled value being
determined from the content of the BCOM register.
10
HH

Description
No Request

VAXBI Transaction Request

L H

Loopback Request

Not Used

These 5 lines are used to provide information on transfer
completion/errors on the VAXBI bus, as detected by the BIIC.

The codes detected are:
Value

(Hex)
00

Mnemonic
NO

MCP

02
03
04
05
06
07
08

AKRSD
BTO
STP
-~ RCR
IRW
ARCR
NICI

Description

EVENT

NICIPS *

AKRE

OB
0C
0D
OE
OF
10

IAL
EVS4
EVSS5
EVS6
EVS7
STO

B-18

Master Action Complete

ACK Rcv for Slave Read Data
Bus Time Out
Self Test Pass
Retry CNF Rcv
BIIC Internal Reg Written
Advanced Retry
o
NOACK/ILLEGAL CNF for
INTR

NOACK/ILLEGAL IP
INTR/STOP
- ACK Rcv for ERROR
VECTOR
IDENT ARB Lost
Ext. Vector Sel @ level 4
Ext. Vector Sel @ level 5
Ext. Vector Sel @ level 6
Ext. Vector Sel @ level 7
Stall Time Out (Slave Error)

Table B-4

CGA Signal Descriptions (continued)
11

BPS

ICRSD

BBE

AKRNE4

AKRNES

AKRNES6

AKRNE?7

RDSR

19
1A

ICRMC
NCRMC

Bad Parity For Slave
Illegal CNF for Slave Data
VAXBI BUSY error
ACK Rcv Non-Err Vect
@level 4
ACK Rcv Non-Err Vect
@level 5
ACK Rcv Non-Err Vect
@level 6
ACK Rcv Non-Err Vect
@level 7
RD DATA SUBS. or reserved
code
Illegal CNF for Command
NOACK Rcv for Command
BAD PARITY received
Illegal CNF for data
Retry Time out
Bad Parity, Master
Master Xmit Check error

1B
BPR **
1C
ICRMD
1D
RTO
1E
BPM
1F
MTCE
* NICIPS only output if IPINTR FORCE bit in the BCI
control register is used; if initiated via master port then
NCRMC or ICRMC will be output.
**BAD PARITY is internally gated to determine whether the
error was slave or master related.

AKRNEX is used to clear the CGA interrupt pending flop
which deasserts the CGA interrupt request signal to the BIIC.
BCI INT L

BCI interrupt is an active low signal which, when asserted
causes the BIIC to initiate an interrupt transaction (INTR) on
the VAXBI bus. Two other bidirectional signals, DEC ENB H

and TESTENB L, provide additional interrupt request lines. On
the DMB32 the CGA output BCI INT L is connected to the
lowest priority level, VAXBI Level 4 (VAX IPL 14).
BCI DCLO L

BCI DCLO L is an active low signal which, when asserted

causes the CGA to be reset, and to assert its RST OUT H signal

to reset the remaining node logic.

BCI NXT

BCI NXT is an active low input signal, sourced from the BIIC,
which provides information about data flow on the VAXBI
during MASTER port transactions.

BCI MAB L

Master abort is an active low output signal which is derived
from the VAXBI master sequencer within the CGA. BCI MAB
L will be asserted if a retry timeout occurs on the VAXBI or in
the special case of a slave write being received during the
initiation of a master write cycle.

B-19

Table B-4

BCI I<3:0> H

CGA Signal Descriptions (continued)

The BCI information lines, BCI 1<3:0> H, pass command
information to the slave sequencer (from the BIIC) and from
master sequencer (to the BIIC) within the CGA.
Value
(Hex)
0
|
2

CGA

Description
RESERVED CODE
READ
INTERLOCK READ
WITH CACHE
INTENT

Mnemonic
~
READ
IRCI

Action
READ
READ

READ WITH

RCI

READ

WRITE

WCI

WRITE

UWMCI

WRITE
MASK

CACHE INTENT
4

WRITE

WRITE WITH
CACHE INTENT
UNLOCK WRITE
MASK WITH
CACHE INTENT
WRITE MASK
WITH CACHE
INTENT
INTERRUPT
IDENTIFY
RESERVED CODE
RESERVED CODE
STOP
INVALIDATE
BROADCAST
INTERPROCESSOR

8
9
A
B
C
D
E
F

WMCI

WRITE

MASK
INTR

IDENT
—
STOP
INVAL
BDCST
IPINTR

BI INTR
IDENT
STOP
-

*
*

* INVAL and INTR commands will be acknowledged by
the CGA (if enabled in the BIIC), although INVAL
performs no action and INTR only causes the VAXBI
interrupt received flag to be set in the BSUM register.
Reception of the STOP command causes the CGA to request
mastership of the 68000 bus, by assertion of BUSRQ L. The

CGA will output STALL on the BCI RS<1:0> L lines until the
input BUSGR L is asserted, completing the action taken on

receipt of a STOP command. The BIIC will translate the first
STALL response into an ACK response on the VAXBI, since
ACK and NOACK are the only legal responses, and will then
hold the VAXBI BSY L signal until the BCI STALL code is
removed.
During slave read data cycles the BCI I<3:0> H lines pass
“Read Status’ information to the BIIC:

Status Code (Hex)

Description

Mnemonic

READ DATA

B-20

Table B-4

CGA Signal Descriptions (continued)

Read Data is the only read status code supplied by the CGA,
since Corrected Read Data and Read Data Substitute have no
meaning without ECC checking of RAM contents.

BCI I<2> H is ignored (don’t care) by the master node decode,
within the BIIC. The CGA does not use the read status
information, but always outputs the RD code on read data

cycles, with BCI I<2> H driven to “L”.

The VAXBI transaction continues even if a RDS (Read Dat&

Substitute) code is received. Reception of an RDS code is
logged in the BSUM register through use of the BIIC event
codes.
Thus invalid longword(s) will have been written to the DMA
File in CASRAM with no information as to which longword(s)
is invalid. Therefore the occurrence of this error indicates that
the DMA transfer must be repeated.
During an assertion of BCI DCLO L the BCI I<3:0> L lines are
used for passing “ID” information, as presented at BI ID<3:0>
H, to the BIIC.
The BCI I<3:0> L lines are also used for passing byte mask
information during master write transactions. An assertion of
any of BCI I<3:0> L will mask in the associated data byte,
permitting it to be written to CASRAM.

BCI SDE L

BCI MDE L

BCI RAK L

Slave data enable is an active low input signal only used to
enable the read data status, on BCI I<3:0> L, during slave read
transactions.
|

Master data enable is an active low input signal used to enable
the byte mask information, onto BCI I<3:0> L, during master
write transactions. It is also an input to the master sequencer
control.
Request acknowledge is an active low input signal which
indicates that the BIIC has VAXBI bus mastership and is
participating in a bus transaction.

VAXBI Interface Signals

BI ID<3:0> H

The ID lines are active high input signals hard-wired on the
VAXBI backplane. These signals are enabled onto BCI I<3:0>
L during a BCI DCLO L assertion.

DIAG FAIL L

Diagnostic fail is an active low output signal asserted in
conjunction with BCI DCLO L. This signal is asserted upon
setting the programmed reset bit within the MAINT register
unless the skip self-test bit, within the same register, is also set.
This signal will be deasserted by reseting the “DIAG FAIL” bit
within the MAINT register.

B-21

Table B-4

CGA Signal Descriptions (continued)

BCI TIME L

This signal is the input 20 MHz clock and is connected to BCI
TIME L, as connected to the BIIC, from the VAXBI clock
receiver chip.

BCI PHASE L

This signal is the input 5 MHz clock and is connected to BCI
PHASE L, as connected to the BIIC, from the VAXBI clock
receiver chip.

Other Signals

TEST L

Test is a fitogrammab]e signal which, following an assertion of
BCI DCLO L is an active low input signal. This input is only
used during device test, and enables internal nodes to be
monitored.

The pin may also be programmed to be an output (via the
DSCSR register). The special test operation of the device will
be disabled when this pin is selected to be an output signal. The
output provided will be the internal BCI INT L signal,
permitting a selection of interrupt levels. On the DMB32 this
signal i1s used as an output connected to the BIIC signal BCI
INT<5> L.
DECODE ENB H

DECODE ENB H is a programmable pin which, following an
assertion of BCI DCLO L is an active high input signal. When
asserted this input enables the use of internal CGA decode to
derive CAS SEL L, and the generation of the acknowledgment
signal, DTACK L, for all 68000 address space.

If DEC ENB H is deasserted, the signal CAS SEL L is treated
as an input signal, requiring external 68000 address decode. In
addition, DTACK is only generated in response to CAS SEL L
and thus external logic must generate the DTACK for other
- peripheral and memory devices.
This pin can also be programmed to be an output (via the
DSCSR register). The internal CGA decode is enabled when
this pin is selected as an output signal. The output provided will
be the internal BCI INT L signal, permlttmg a selection of
interrupt levels. On the DMB32 this signalis used as an cutput
connected to the BIIC signal BCI INT<6> L.
|
VDD

+5 V power connections (4 off)

VSS

Ground connections (8 off)

B-22

APPENDIX C

GLOSSARY

This glossary defines terms used to describe the VAXBI bus, the BIIC, and

Adapter
|
A node that interfaces other buses, communication lines, or periphera
l

the DMB32 option.

devices to the VAXBI bus.

Asserted

To be in the “true” state.
Asynchronous
A method of serial data transmission in which data is preceded by a start bit
and followed by a stop bit.
The receiver provides the intermediate timing to identify the data bits.
Auto-answer
Facility of a modem or terminal to automatically answer a call.

Auto-flow
|
Automatic flow control. Method by which the DMB32 controls the flow
of data by means of special
characters within the data stream.
Backward Channel
Channel which transmits in the opposite direction to the usual data flow.
Normally used for supervisory or
control signals.
|
Base Address
The address of the CSR.
BCI
|
VAXBI chip interface; a synchronous interface bus that provides for all
communication between the BIIC
and the user interface.

BIIC
Backplane interconnect interface chip; a chip that serves as a general purpose

interface to the VAXBI bus.

BIIC CSR Space
The first 256 bytes of the 8 Kbyte nodespace, which is allocated to the
BIIC’s internal registers. See also
Nodespace.
|

Bus Adapter
A node that interfaces the VAXBI bus to another bus.

C-1

CCITT
Comite Consultatif International de Telephonie et de Telegraphie. An international standards committee
for telephone, telegraph and data communications networks.

Dataset

See quem
Deasserted
To be in the ““false” state.
Decoded ID
The node ID expressed as a single bit in a 16-bit field.

Device Type
A 16-bit code that identifies the node type. This code is contained in the BIIC’s Device Register.
DIL

Dual-In-Line. The term describes ICs and components with two parallel rows of pins.
DMA

Direct Memory Access. Method which allows a bus master to transfer data to/from system memory
without using the the host CPU.
DMA adapter

An adapter that directly performs block transfers of data to and from memory.
DUART
Dual Universal Asynchronous Receiver Transmitter. IC used for transmission and reception of serial
asynchronous data on two channels.

Duplex
|
Method of transmitting and receiving on the same channel at the same time.
EIA

Electrical Industries of America. American organization with the same function as CCITT.
EMC
|
Electro-Magnetic Compatibility. The term denotes compliance with field-strength, susceptibility and static
discharge standards.
|

Encoded ID
The node ID expressed as a 4-bit binary number. The encoded ID is used for the master’s ID transmitted
during an imbedded ARB cycle.

Even Parity
|
|
|
The parity line is asserted if the number of asserted lines in the data field is an odd number.
FCC

Federal Communications Commission. American organization which regulates and licenses communications equipment.

FIFO
First In First Out. The term describes a register or memory from which the oldest data is removed first.

C-2

Floating Address
CSR address assigned to an option which does not have a fixed address allocated. The address is dependent
upon other floating address devices connected to the bus.
Floating vector
|
Interrupt vector assigned to an option which does not have a fixed vector allocated. The vector is
dependent upon other floating vector devices connected to the bus.

FRU
Field Replaceable Unit

GO/NOGO
Test or indicator which defines an ‘error’ or ‘no error’ condition only.
H

Designates a high-voltage logic level (that is, the logic level closest to Vcc). Contrast with L.
IC
Integrated Circuit
Interrupt Vector

In VAX/VMS systems, an unsigned binary number used as an offset into the system control block. The
system control block entry pointed to by the VAXBI interrupt vector contains the starting address of an
interrupt-handling routine. (The system control block is defined in the VAX-11 Architecture Reference
Manual
)
I/0
Input/Output
L

Designates a low-voltage logic level (that is, the logic level closest to ground). Contrast with H.
LSB
Least Significant Bit
LSI-11 bus
Another name for the Q-bus
Master
The node that gains control of the VAXBI bus and initiates a VAXBI or loopback transaction. See also
Pending Master.

Master Port
|
Those BCI signals used to generate VAXBI or loopback transactions.
Master Port Transaction
Any transaction initiated as a result of a master port request.
Microcomputer
An IC which contains a microprocessor and peripheral circuitry such as memory, 1/O ports, timers, and
UARTs.

Modem
The word is a contraction of MOdulator DEModulator. A modem interfaces a terminal to a transmission
line. A modem is sometimes called a dataset.

Module
A single VAXBI card that attaches to a single VAXBI connector.
MSB
Most Significant Bit

Multlplexer
A circuit which connects a number of lines to one hne

Node
A VAXBI interface that occupies one of sixteen logical locations on a VAXBI bus.
consists of one or more VAXBI modules.
Node ID
A number that identifies
backplane.

A VAXBI node

a VAXBI node. The source of the node ID is an ID plug attached to the

Node Reset

A sequence that causes an individual node to be initialized; initiated by the setting of the Node Reset bitin
the VAXBI Control and Status Register.

Nodespace
An 8 Kbyte block of I/O addresses that is allocated to each node. Each node has a unique nodespace based
on its node ID.

Null Modem
A cable which allows two terminals which use modem control signals to be connected together directly.
Only possible over short distances.

Odd Parity
The parity line is asserted if the number of asserted lines in the data field is an even number.
PCB
Printed Circuit Board
Power-down/Power-up Sequence
The sequencing of the Bl AC LO L and BI DC LO L lines upon the loss and restoration of power to a
VAXBI system. See also System Reset.
Protocol
Set of rules which define the control and flow of data in a communications system.
PSTN
Public Switched Telephone Network

Q-bus
Global term for a specific DIGITAL bus on which the address and data are multiplexed.

Q22, Q18 and Q16

Terms used to define 22-, 18- and 16-bit address versions of Q-bus.
RAM

Random Access Memory
RESERVED code
A code reserved for use by DIGITAL.
RESERVED field

A field reserved for use by DIGITAL The node driving the bus must ensure that all VAXBI linesin the
RESERVED field are deasserted. Nodes receiving VAXBI data must ignore RESERVED field information. This requirement provides for adding functionality to future VAXBI node designs without affecting
compatibility with present deSIgns Example: The BI D<31:0> L and BI I<3:0> L lines during the third
cycle of an INTR transaction are RESERVED fields.
Reset Module

In a VAXBI system, the logic that monitors the Bl RESET L line and any battery backup voltages and
that initiates the system reset sequence.
Resetting Node
The node that asserts the Bl RESET L line.
RFI
Radio Frequency Interference
ROM

Read Only Memory

Slave

A node that responds to a transaction initiated by a node that has gained control of the VAXBI bus (the
master).
Slave Port

Those BCI signals used to respond to VAXBI and loopback transactions.
Split-speed

Facility of a data communications channel which can transmit and receive at different data rates at the
same time.
System Reset

An emulation of the power-down/power-up sequence that causes all nodes to initialize themselves; initiated by the assertion of the BI RESET L line.
Transaction

The execution of a VAXBI command. The term “transaction” includes both VAXBI and loopback
transactions.
UART

Universal Asynchronous Receiver Transmitter. IC used for transmission and reception of serial asynchronous data on a channel.

C-5

UNDEFINED Field
A field that must be ignored by the receiving node(s). There are no restrictions on the data pattern for the
node driving the VAXBI bus. Example: The BI D<31:0> L and BI 1<3:0> L lines during read STALL
data cycles and vector STALL data cycles are UNDEFINED fields.
User Interface
All node logic exclusive of the BIIC.
User Interface CSR Space
That portion of each nodespace allocated for user interface reglsters The user interface CSR space is the 8
Kbyte nodespace minus the lowest 256 bytes, which comprise the BIIC CSR space.
VAX Interrupt Priority Level (IPL)
In VAX/VMS systems, a number between 0 and 31 that indicates the priority level of an interrupt with 31
being the highest priority. When a processor is executing at a particular level, it accepts only interrupts at a
higher level, and on acceptance starts executing at that higher level.
VAXBI Primary Interface
The portion of a node that provides the electrical connection to the VAXBI signal lines and implements the
VAXBI protocol; for example, the BIIC.
VAXBI Request

A request for a VAXBI transaction from the Master Port interface that is asserted on the BCI RQ<1:0>
L lines.
VAXBI System

All VAXBI cages, VAXBI modules, reset modules, and power supplies that are required to operate a
VAXBI bus. A VAXBI system can be a subsystem of a larger computer system.

VAXBI Transaction
A transaction in which information is transmitted on the VAXBI signal lines.
Window Space

A 256 Kbyte block of I/O addresses allocated to each node based on node ID and used by bus adapters to
map VAXBI transactions to other buses.
XOFF
Control code (23 octal) used to disable a transmitter. Special hardware or software is needed for this
function.
XON
Control code (21 octal) used to enable a transmitter which has been disabled by an XOFF code.

C-6

Digital Equipment Corporation - Bedford, MA 01730