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Document:	DLV11-E and DLV11-F Asynchronous Line Interface User's Manual
Order Number:	EK-DLV11-OP
Revision:	001
Pages:	132
Original Filename:

OCR Text

EK-DLV11-OP-001

DLV11-E and DLV11-F
asynchronous
line interface
user’'s manual

digital equipment corporation - maynard, massachusetts

1st Edition, June 1977

The material in this manual is for informational
purposes and is subject to change without notice.

Digital Equipment Corporation assumes no responsibility for any errors which may appear in this

manual.
Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment

Corporation, Maynard, Massachusetts:
DEC

DECtape

DECCOMM

DECUS

PDP
RSTS

DECsystem-10

DIGITAL

TYPESET-8

DECSYSTEM-20

MASSBUS

TYPESET-11
UNIBUS

CONTENTS
Page

1.
1.
1.

W
e

CHAPTER 1

INTRODUCTION

PURPOSE AND SCOPE . . . . . .
e e
OPERATING FEATURES
. . . . . @ o
e
MODULE SPECIFICATIONS . . . . . . o i i
MAINTENANCE
. . . . .
e e e e e e

CHAPTER
2

GENERAL DESCRIPTION

2.1

GENERAL

2.2

MODULE FUNCTIONS

2.3

CIRCUIT FUNCTIONS . . . . o o

. . . .

e e

. . . . o

e e e
e
e
e e e e
e e e

1-1
1-1
1-3
1-3

e e e e e e e e e e e e

2-1

e e e e

e
e
e
e

e e e e e e e e e e e e e - 2-1

e e e e e e e e e e e e s e e e e e

General

e e

2-3

2.3.2

234

BusInterface
. . . . . . . . . . i
e e e e e e,
I/O Control Logic
. . ... ... e e e e e e e
e e e e
Control/Status Registers . . . . .. .. e e e e e e e e e e
..

2-3
2-4
24
2-7

2.3.5

DataBuffers

2.3.6

Receiver Active Circuit

237

Interrupt Logic

2.3.8

Baud Rate Control

2.3.9

Break Logic

2.3.10

Maintenance Mode Logic

12.3.11
- 2.3.12

e e e e e e e e e e e e e e e e e

2-3

2.3.1

233

. . . . . L

e
e
e
e

. . . . . . . . @ . @ @ i i i i

. . . . . . . . . . o v v v i

. . . . . . . . .

. . . . . . . . . .

DLV11-F Peripheral Interface . . ...

CHAPTER 3

INSTALLATION

3.1
3.2

GENERAL

2-7

e e

2-8

e e

. .. .. ..e

e e

2-8

. ...

2-8

e e e e e e e e e e e

2-8

... ... e e e e e e e

. . . . . . . . .

. . . .

o @ v v v e e e

e e e e e

3.3

3.4

MODULE CHECKOUT

it e e i e e e e e

2-9

3-1-

CONFIGURATION . . . .
e e e e e e e e e e e e e s s s,
MODULE INSTALLATION ... ... .. e e e e e I
. . . . . . .

247

. . . . . . . . . . . . . ..

DC-to-DC Power Inverter

e e e e e e

. . . . . . . . . . . . . o

DLV11-E Peripheral Interface

2.3.13

e e e e

3-1
3-1

e e
e e e s 3-11

34.1

DLVI1I-ECheckout

. . . . . . . . @ @ @ @ i i i i i i i i i i i s i 3-15

34.2

DLVI11-FCheckout

. . .. . . . @ . @ . @

CHAPTER 4

PROGRAMMING

i v i i

i i i i i

.. 3-15

4.1

INTRODUCTION

4.2

DEVICE REGISTERS

4.3

INTERRUPTS

4.4

TIMING CONSIDERATIONS

. .. .. e

e b

. ... .. S

. . . . . o

e e

e e e e

aie e e

e e e e e e e

h e e e ee

e e e e e

e e e e

4-1

e e e e e L...

. . ... ... ....... e

44.1

Receiver

44.2

Transmitter

4.4.3

BREAK Generation Logic

. . .. .. .. .... e

4-1

e e

e e e e e . . 4-10

e e e e e e e e e e e e e e ... 410

. . . . .. .. .. .... "
5[¢

444

4.5

PROGRAMMING EXAMPLES

4.6

PROGRAMMING NOTES

System Reset Timing

. . . .. ... ... ... ... e e e

. . . . . . . . .

v v v v v

. . . . . . . . .

. . . . . .

e e

.. 410

e 4:10
e s e

. 4-10

e e e e e e e e

. 4-18

CONTENTS (CONT)
Page

CHAPTER 5

DETAILED TECHNICAL DESCRIPTION

5.1

GENERAL

5.2

BUS INTERFACE

5.2.1

5.2.2
5.3

5.3.1

. ... ... .... e

Address Decoding

5-1

e e e e e e e P

5-1

. . . .. ...
.. e e

e .

Vector Addressing . . . . . . . e e
e
e
e e e e e e e
I/O CONTROL LOGIC
. .. .. ......... S
Input Operation . . . . .. P
e
e e e e e e e e ...

5-1

5.3.2

Output Operation

. . . ... ... .. s

5.3.3

Vector Operation

. . . . . . . . . .

5.4

CONTROL/STATUS REGISTERS

e e e

5-2
53

e e .. ..

0 v v i i e e e e e e e e

5-7

. . . . . . . . . . ... ... ......

5.4.1

CSRDataFlow

. ............................

5.4.2

Input Operation

. . . . .......... e e P

& B

5.4.3

Output Operation

5.5

DATA BUFFERS

. . . . . ... ... ... e e e e e e

. . .. . . .. .. .. .. ....... e

5.5.1

Receiver Operation

. . . . . . .. S

5.5.2

Transmit Operation

. . . . . . . . . .

5.6

RECEIVER ACTIVE CIRCUIT

5.7

INTERRUPT LOGIC

e e e e 5-11

e e e e e e e 5-12
5-13

. .

. o

e 5-15

. ... .... e e e e e e e e e e e e 5-16

. . . . . . . . . .

. ... L.
.. 5-16

5.7.1

DLV1I1-E Receiver Interrupts

e e e e e e e e e e e

5.7.2

DLV11-F Receiver Interrupts

. . . . . . . . . . .. ... ... ..., 5-18

5.7.3

Transmitter Interrupts

. . . . . . . . ... ... e e e

5.7.4

Interrupt Transactions

. . . . . . . . .. . . ... ... ... e
e . 5-19

5.8

BAUD RATECONTROL

. . . . .

e e e e e e e

5-17

e e e 5-19

... ... ...
.. e

e e e e 5-20

5.8.1

Program Control

. . . . .. e e e e e e

5.8.2

Jumper Control

. . . . . . . . . Lo - 5-23

5.8.3

External Control

5.8.4

Clock Selection

5.9

. . . . . .

BREAK LOGIC

. . . . . . . . . . . .. . ... .. ... ... ..523

. . . . . . ... ... ..... e

. . ...
.e e e e

5.9.1

Receive Operation

5.9.2
5.10

MAINTENANCE MODE LOGIC

5.11

DLV11-E PERIPHERAL INTERFACE

5.12

DLVI11-F PERIPHERAL INTERFACE

5.12.2

e e

e e e e e R 5-23

e e B 5-23

. . . . . . . . . . . . o i i i it

Transmit Operation

5.12.1

e ... 520

e .. 524

. . . . . .. ... ... . 5-24

. . . . . . . .

EIA Data Leads Only Operation
Current Loop Operation

. ..

.. 5-25

.. ... ... ............526
. ..
. .. e e e e e e e

. . . . . . . ..

o .. .. 5-28

... ..... ... 528

. . . . .. . ..e e e e e e e e e e e e e e 5-29
. . . . . . . . . ... ...
... ... . . 5-29

5.13

DC-TO-DC POWER INVERTER

APPENDIX A

IC DESCRIPTIONS

A.l

DCO0O3 INTERRUPT LOGIC

DC004 PROTOCOL LOGIC

A.3

DC005 TRANSCEIVERLOGIC
.. ... ... ... ... .........
Al
UNIVERSAL ASYNCHRONOUS RECEIVER/ TRANSMITTER . ... ..
A-19
Receiver Operation
. . . . . .. e
e e e
e e e e e
A-19

A4.l

. ...
.. .. T
. . . .. ... .... e

e e e e e e e e e e

A-1
A-1

CONTENTS (CONT)
Page

A4.2

Transmitter Operation

. . . . . .. e

5016 DUAL BAUD RATE GENERATOR
APPENDIX B

WIRE WRAP INSTRUCTIONS

B.1

PURPOSE

B.2

DEFINITIONS

B.3

CONNECTIONS

B.4

PROCEDURE

e e

... .. e

e e

A-21

e e e e e e e

A-29

.. ........... e E R
. . . . . . . . .

ee e e e

et e

.. ... ... .... SIS

e e

et e e e .. e

e e e e .

B-1

e e e e

B-1

e e e e e e e e - B-2

... ... e e
e e e ee e e e e e e e e e e e e e e B3

Figure No.

Title

Interfacing Examples . . . . .. ... ... ..... .

e e

DLV11-E and DLV11-F Data Flow, Slmphfied Block Diagram
DLV11-E and DLV11-F Functional Block Dmgmm

Page
e e .

2-2

. .. ...
.

2-3

e e e e e e e e e

DLVI1I1-E Jumper Locations . . . . ... ... .....e e

245

e e e e e e

3-2

'DLVI1I1-F Jumper Locations

. .. ... ... S

3-3

DLVI11-E Cabling Example

... .. ...... N

DLVI11-F Cabling Examples

. . . . . . . . . .. . i, 3-10

Typical Backplane Configuration

.. ... .. .. . . .

.. .. ...... 3-11

DLV11-E RCSR Bit Assignments

. . . ... ... R

4-2

DLVI11-F RCSR Bit Assignments

. . . . ... ... .............

DLVI11-E and DLV11-F RBUF Bit Assignments
DLVI11-E and DLV11-F XCSR Bit Assigments

. ... ... ........
. . . ...

DLV11-E and DLV11-F XBUF Bit Assignments
DLVI11-F Programming Example
Serial Data Format

4-5
4-6

.. ........

4-7

. ... ...........

4-8

. ... .. ... ..... e

e e e e e 4-15

. . . . . . . . . . .. . ... ... .. ... 4-18

DLVI11-E and DLV11-F Addresses

LI P L

5-2

DLV11-E and DLV11-F Interrupt Vectors

. . . . . ... . ... .. ....

5-2

I/O Control Logic, Block Diagram

. . . . . .. ... ... ... .......

Datalnput Timing

. . . . . . . . . . . . .. . . . .

Data Output Timing

. . . . . . . . . . . . . . . . .

...

5-4

...

5-5

.. i

5-6

DLVII-ERCSRDataFlow

. ... .. ... ... .. .. ... .......

5-8

DLVII-FRCSRDataFlow

. . .

5-9

... ... .. .. ... .. .. .....

DLVI11-E and DLV11-F XCSR DataFlow

Control/Status Registers During DATI

... ... ............ 5-10

. . . . . . . ... .. ... ..... 5-11

5-10

Control/Status Registers During DATOorDATOB

5-11

UART Signal Flow

. . . . .. .. ...... 5-12

5-12

DLVI11-E
and DLV11 FRBUFData Flow

. .. .. ... .......... 5-14

5-13

DLVI1-E and DLVI11-F XBUF DataFlow

. . . ... ...

. . . . ... .. .. .... e e

e e e e e 5-13

... ...... 5-16

' FIGURES (CONT)
| Figure No.

Title

5-14

Receiver Active Circuit

. . . . . . .. e

515

Interrupt Vector Signal Flow

5-16

Interrupt Timing

5-17

Page

. . . . . .. e

e 5-17

ee e e

.. . 518

. . . ... ... e e e e e e e e e e e e e e ... 519

~Baud Rate Control Signal Flow

. . . . . . ... .. ... ...... ... 521

5-18

Break Logic Receive Signal Flow

. . . . . ...
.. ... e

5-19

Break Logic Transmit Signal Flow

. . . . . .. S

520
5-21

Maintenance Mode Logic

5-22

Data Lead Only Interface

5-23

20 mA Transmitter and Reader Run Circuit

. . ...

e e e e

5-25

A
S

.. ... .... e e e e e e e e e e 5-26

DLV11-E Peripheral Interface Signal Flow

. Ce die s

e e e e e e e

5-27

. . ... ... ... .. .. ... .........528

. . . . . . . ... ... ..... 5-30

5-24

Active Receive 20mA Current Loop

. . . . . . . . . . . . ... ... ... 5-31

5-25

Passive Receive 20 mA Current Loop

.......... e

5-26

A-1

Interlock Jumper Data Flow

- DCO03 Simplified Logic Diagram

. . . ... ... ... e

. . . . ... ... .. ...

DCO003 “A” Interrupt Section Timing Diagram

A3
A4
A-S
A-6

DCO003 “A” and “B” Interrupt Section Timing Diagram
DC004 Simplified Logic Dlagram

T e e i e ee

. . . . . . . ...

e ee

. . . .. .. .. ... e i e e

e e e e e e e

e e e i e e

e e

- DCO04 Loading Configuration for Table A2

DCOO0S Simplified Logic Diagram

'DCOOS Timing Diagram

e e e e e 5-31

e e e e e ...

A-2

DCO004 Timing Diagram

. . . . . .. ... ... .. ..... e . 5-32

UART Data Format

v e

.. .. ...
. ....

e i e

e eeia e

UART Receiver
— Block Diagram

A-11

UART Transmitter
— Block Diagram

A-16
A-17

. .. ... ... R

A-10

A-13

-~ A-14

. . . . .. . . . .

. . . . .. «

A-19

. . . . . ... ... .. .........

A20

UART Pin Locations

. . .. . . .. ... ... ......

A-21

A-12
A-13

A-14

5016 Block Diagram . . .. .. ... ...... e e
e e
e e e e
5016
Pin Locations . . . . . . v v i it e e e e e e e e e
e e oo ..

A-29
A3

B-1

Solderless Wrapped Connection on ere Wrap Pin . .....e

B-2

Full Turn

B-3

B-4

. . . . .e e e

e e

e e - A-22

e e

B-1

e .. e e e e e e e e

B-2

“Half Turn . . . . ... ... .... e e e e e e e e e e i
e e e e e e
TwoLevelsoforeWrap
e e e e e e ee
e e e e
. ...

B-2
B3

. . . . . . . .

B-S

Defective Wire Wraps

‘B-6

Loading the Wire Wrapping Kit

. . . . . . . ...
. e e v

. . . . .. .. e

e e e

eie e

e e e e e

e e

e e e

e e

B-6

TABLES

| Table No.

Title

)

Page

1-1

Feature Comparison

. . . . . . @ e e e e e e

e e ee e e e e e e e

1-2

3-1

Jumper Definitions

. . . ... ... e

3-4

3-2

Baud Rate Selections

. . . . o v v v e

e e e

e e

3-6

TABLES (CONT)

Table No.
3-3

3-4
3-5
3-6

3-7
3-8

4-1
4-2
4-3

4-4
4-5

4-6

4-7

5-1
5-2
5-3

A-1
A-2
A-3

A-4
A-5

A-6
A-7

Title

Page

. . . . . v o e e e e e e e e e e e e e e e e e e e 3-6
Data Bit Selections
Jumper Configuration When Shipped . . . . . . . . .. .. ... ... .. 3-7
Module Application Examples . . . . . . . . .. . .00 39
DLV11-E 40-Pin Header Connector Pinning . . . . . . . . . .. ... . ... 3-12
DLV11-F 40-Pin Header Connector Pinning . . . . . . . . . .. ... .. .. 3-13
DLV11-E and DLV11-F Edge Connector Pinning . . . . . .. ... ... .. 3-14
. . .. ... ... ........ 41
Register Addresses for Console Interfacing
e e e e e e e e e e e e e e e 4-2
..
.
.
.
.
Assignments
Bit
RCSR
DLV11-E
"DLVI11-F RCSR Bit Assignments . . . . . . . . .
o
v v v v v v oo 4-5
. . . . . ... ... .... 4-6
DLVI11-E and DLV11-F RBUF Bit Assignments
.. 47
. . . . .. ... .. e
DLV11-E and DLV11-F XCSR Bit Assignments
DLV11-E and DLV11-F XBUF Bit Assignments
. . . . . . ... ... ... 4-8
. . .. ... ... ... ... ....... 4-11
DLV11-E Programming Example
Register Selection . . . . . . . . . . . . . L e 5-3
Byte Selection (Output OperationsOnly) . . . . .. ... ... ... ..., 5-7
UART ClocKk SOUTCES + « v v v e e e e e e e e e e e e e e e e e e e e e e 5-24
DCO003 Pin/Signal Descriptions
. . . . . . . . .
o oo A-7
DCO004 Signal Timing vs Qutput Loading . . . . ... .. ... ... ... A-11
. . . . . . . . . . . .. . ... A-14
DCO004 Pin/Signal Descriptions

v vt o e

A-18

UART Pin Functions
. . . . . . . .« .«
v o v v v v ve e e e e e
e
oo e
. . . . . . .« v o o o
5016 Selectable Frequencies
5016 Pin Functions . . . & v v v v i i e e e e e e e e e e e e e e e e e e

A-23
A-30
A-31

DCO005 Pin/Signal Descriptions

. . . . . . .« o

INTRODUCTION

1.1 PURPOSE AND SCOPE
The DLV11-E and DLV11-F are asynchronous line interface modules that interface the LSI-11 bus to
any of several standard types of serial communications lines. The modules receive serial data from

peripheral devices, assemble it into parallel data, and transfer it to the LSI-11 bus. They accept data

from the LSI-11 bus, convert it into serial data, and transmit it to the peripheral devices. The two
modules differ in that the DLV 11-E offers full modem control, whereas the DLV11-F supports either
20 mA current loop or EIA-standard lines, but does not include modem control.
This manual describes these modules to the user. It treats the two modules together for those functions
common to both, and separately for those areas in which they differ. It is assumed that the reader has a
general familiarity with the operation of the LSI-11 computer and with the requirements of theperiph-

eral equipment. Refer to Microcomputer Handbook, EB 06583 76, for detailed information about the
LSI-11.

1.2 OPERATING FEATURES
Each asynchronous line interfaceis constructed on a single 21.6 cm X 122.7 cm (8. 5in x 5.0 in) dualheight module. The module mounts in any slotin the LSI-11’s backplane Both the DLV11-E and the
DLV11-F have the following features:
e Jumper- or program-selectable crystal-controlled baud rates: 50, 75, 110, 134.5, 150, 300, 600,
1200, 1800, 2000, 3600, 4800, 7200, and 9600.

* Provisions for user-supplied external clock inputs for baud rate control.
e Jumper-selectable parity and data bit formats.

e LSI-11 bus interface and control logic for interrupt processing and vectored addressing of
interrupt service routines.

e Control, status, and data buffer registers directly accessible via processor instructions.

e Program and peripheral connector plug compatible with the PDP-11 DL11 series of asynchronous line interface modules.

The DLV11-E is designed to interface data sets (modems with control capability) such as Bell models
103, 202C, and 202D.
The DLV11-F is designed for either 20 mA current loop equipment or EIA-standard ‘“data leads only”
(no modem control) operation. Flexibility is achieved by the use of wire wrap jumpers. Table
1-1 compares the features of the DLV11-E and DLV11-F with those of the DLV11 and the DL11
series.Refer to Paragraph 4.4, Timing Considerations, for further information.

1-1

Table 1-1

Feature Comparison

(NOTE: X indicates feature available.)

| Featurés

DL11-A
through D

DL11-E

Programmable Baud Rates
(Write Only Bits)

DLV1l1

DLV11-F

DLVI11-E

- Modem Control

‘ EIA “Data Leads Only”
20 mA Current Loop

Jyurnpcr Seléctable |

n’ooX

Active or Passive
- 20mA Current Loop

On-board Clocks for
- Split Speed Operation

bTT

M‘aifitenancc Bit

S T

Receiver Active Bit

BREAK Gcneratidn Bit

“Error Flags

UART Cleared by INIT

UART Cleared by DCOK
No Trap on Write
to RBUF
1.5 STOP BITS

Modem Status Bit

Boot on Framing Error

Halton Framing Error

1.3 MODULE SPECIFICATIONS
‘
The following spccnficatmns and pamculars are for informational purposes only and are subwct to
change without notice.
:

Dxmensmns

Circuit Card

Circuit Card Plus Handles

Length: 21.6cm(8.5in)

Height:
Width:

22.8
cm (8.9 in)

12.7cm (5.0in)
1.3cm(0.5in)

13.2cm (5.21in)
1.3cm (0.5in)

Cable Connection
Mounting Requirements

One 40-pin header connector
W

Plugs directly into any dual-heightslotson the
LSI-11 backplane or LSI-11 expansion box

backplane.
Electrical Characteristics
Module Type
DLVI11-E: M8017
DLVI 1-F: M8028

Power Reqmrcments
1.0 A (nominal) @ +5V :ES% S0W
150 mA (nominal) @ +12V £5, 1.8 W
LSI-11 Bus Loading
Presents one bus load.
Environmental Characteristics
Temperature

Operating

5°Cto50°C(41° Fto 122° F)

Nonoperating

-40° Cto 66° C(-40° Fto 151° F)

Humidity (Operating and Nonoperating)
10% to 95%, maximum wet bulb 32° C
(90° F) and minimum dew point 2° C (35° F)

Altitude
Operating
Nonoperating

2.4 km (8,000 ft)
9.1 km (30,000 ft)

1.4 MAINTENANCE
This manual explains the normal operation of the asynchronous line interface modules. This information and the diagnostic maintenance programs will aid the user when analyzing trouble symptoms to
determine necessary corrective action. A set of engineering drawings is available for each of the two
modules. Refer to DLV11-E Asynchronous Line Interface, Circuit Schematics (DIGITAL part number D-CS-M8017-0-1) or DLV11-F Asynchronous Line Interface, Circuit Schematics (DIGITAL part
number D-CS-M8028-0-1).

Sngnal names in the DLVll E and DLVll F print sets are in the f@llowmg basxc form
SOURCE

SIGNAL NAME

POLARITY

SOURCE indicates the drawing number of the print set where the mgnal omgmates The drawmg
number of a print (K~3 K-4 K 5, etc.) is located above the title block
|
SIGNAL NAMEis the proper name of the signal. The names usedin the print set are also usedin

this manual.

POLARITY is either H or L to indicate the voltagc level of the signal: H= +3V; L R ground.
As an example, the signal:
(K-3) INIT H

~originates on sheet K-3 of the drawings and means “when INITis true, this sngnalis at approximately +3 V.”

LSI-11 bus signal lines do not carry a SOURCE indicator. These names represent a bidirectional wire-

ORed bus. As a result, multiple sources for a particular bus signal exist. The LSI-11 bus sxgnal names
begin with a “B”’ for ‘““bussed.”

The DLV11-E moduleis shipped with an H315 modem test connector mcluded This is plugged into

the interface cablein place of a data set when runmng maintenance programs. The DLVI11-F does not
use this test connector.

A paper tape diagnostic maintenance program is shipped with the modulc for checkout and mamtenance. The following programs are available:
DLV11-E: MAINDEC-11-DVDVA
DLV11-F: MAINDEC-11-DVDVC

CHAPTER 2
CRI DT
S
E
D
L
A
GENER

2.1 GENERAL
|
|
The DLV11-E is designed to interface equipment that transmits and receives data over communications lines and conforms to EIA Standard RS232C and CCITT Recommendation V.24. The
DLV11-E is used by the program to control a communications data set through the use of control
signals and handshake sequences.
|
The DLVI11-F supports either EIA-compatible data lines or 20 mA current loop data lines. When
configured for EIA support, the DLV11-F transmits and receives bipolar levels over the data lines to
the device. This operation does not include control lines. When configured for 20 mA current loop
operation, the DLV11-F can support either active or passive current loop devices. Figure 2-1 illustrates
several applications of the modules.
2.2 MODULE FUNCTIONS
»
|
The DLV11-E and DLVI11-F asynchronous line interface modules take data from the LSI-11 and
convert it to the speed, character format, and signal levels required by the user’s peripheral devices.
Conversely, they assemble inputs from the peripheral devices into the format required for transfer to
the computer. The computer program can address any of four registers in the interface modules to
transfer data or status information. It can also enable the interface modules to generate interrupts.
When a peripheral device requires service, the interface module will, if enabled, interrupt the program
and vector to the necessary service routine.
Data passes through three main circuits on its way to and from the peripheral device (Figure 2-2).
During computer output operations, parallel data is taken off the LSI-11 bus by a bus interface circuit
and placed on the module’s internal three-state bus. The data on the three-state bus enters a data
buffer, where it is serialized and formatted for the peripheral device. From there it goes to a peripheral
interface circuit that changes it from TTL to either EIA-compatible bipolar levels (DLV11-E or
DLV11-F) or 20 mA current loop signals (DLV11-F only). The data then leaves the module on an
interface cable and goes to the user’s peripheral device. Data coming into the computer from the
peripheral device goes through this process in reverse order.
The control functions within the interface module are carried out by circuits that handle I/O transfers,
interrupt requests, and control and status information. The DLV11-E interfaces control signals as well
as data between the LSI-11 and the peripheral. The extent of this interaction is determined by the
program and the type of peripheral being supported.
|
|
The DLVI11-E and DLV11-F also have a self-test function. When the computer program places the
module in the maintenance mode, parallel data travels through the bus interface and the data buffer,
is
serialized, and then loops back through the data buffer, is converted back to parallel, and travels
through the bus interface to the computer to be checked for accuracy.

LSI-11 BUS

—

LSI-11 BUS

TELEPHONE LINES

| DATASET|
|

DLVII-E

‘TERMINALI

EIA/CCITT

LSI-11 BUS

INTERFACING A REMOTE TERMINAL

I LSI-11 I

< |

INTERFACING A REMOTE LSI-11

l Lsrwnl

LSI~11 BUS

[ oLvi-e|
l MODEM l

—

PRIVATE LINES

LSI-11 BUS
[TERMINAL |

LSI-11

EIA/CCITT

REMOTE COMMUNICATIONS via PRIVATE LINES
20mA

<:: |
‘ LSI-11 I

LSI-11 BUS

LSI -11 BUS
DLV1I-F

EIA/CCITT

INTERFACING A LOCAL TERMINAL

| PP -11 l'
INTERFACING A REMOTE PDP-11
i1~4958

Figure 2-1

Interfacing Examples

rwmmmmmwwmmmmmmmmmmfl
lASYNCHRONOUS LINE INTERFACE
|

/\f

PARALLEL
LINES

]

~ PARALLEL

| CONTROL

DATA

LINES

Bus

LSI-{1 BUS

LINES]

|PeRIPHERAL

PERIPHERAL

CONTROL FUNCTIONS |

11-4959

Figure 2-2

2.3

DLVI1I1-E and DLVI11-F Data Flow, Simplified Block Diagram

CIRCUIT FUNCTIONS

coverage of circuit operation, refer to Chapter 5.
2.3.2 Bus Interface
|
The bus mterface mrcmt performs three basxc functwns
1.

It converts signal levels of data moving between the LSMI bus and the mterface module S
internal three-state bus.

It decodes the device address and produces an address match (MATCH H) signal.

It generates mwrrupt vectors and places them on the LSI-«ll bus.

The LSI-11 signals are standard TTL levels. The module’s mtemal thwewstatc bus, however, has three
signal conditions. It has TTL high and low states, and also a disabled state. When a bus interface
transceiver output is disabled, it goes to a high impedance condition that does not affect other devices
connected to the sameline. This permits the lines to be used
iin both dlrectmns by hlgh speed, low
power dewces

The bus interface is normally enébled to receive from the LSI-11 bus. It can be switched to transmit
onto the LSI-11 busby either the I/O control logic or the mwrwpt logic. The mgnals mcewad from the

LSI-11 bus are ignored unless the address decoding functionis enabled.

2-3

The bus interface circuit monitors LSI-11 bus lines BDALOO L through BDAL1S5 L. It inverts these
signals and places them on three-state bus lines DATO0O0 H through DAT15 H. If the information on
the BDAL linesis the address of a locationin the upper 4K of addressing space, i.e., in the I/O page,
the LSI-11 asserts BBS7 L. This sxgnal enables the device address decodmg functlon in the bus
interface.
To decode the address, the circuit compares BDALO3 L through BDAL12 L with address jumpers A3
through A12. If the states of the BDAL lines match the corresponding jumpers the user has installed,
the circuit sends MATCH H to the I/O control logic. MATCH H is a prerequisite for data
transactions.
The bus interface logic generates vector addresses under the control of the interrupt logic and the
vector address jumpers. The circuit creates two vectors; one for receiver interrupts and one for transmitter interrupts. The combination of VECTOR H and VECRQSTB H from the interrupt logic and
the states of vector address jumpers V3 through V8 determines what vector will be placed on the LSI11 bus lines.
2.3.3 1/0 Control Logic
The I/O control logic directs data transactions between the LSI«II and the interface modulc A data
transaction can be a word or a byte, a high byte or a low byte, an input or an output, or status
information or character information. The I/O control logic monitors the LSI-11 bus lines to recognize what type of transaction is to be accomplished. It uses this information to control four device
registers. The registers are named after their functions as follows:

Receiver Control /Status Register
(RCSR)
Transmitter Control/Status Register
o
(XCSR)
Receiver Buffer
(RBUF)
Transmitter Buffer
(XBUF)
These four registers are described in subsequent paragraphs of this chapter.

An I/0 operation begins with the LSI-11 addressing the interface module. The bus interface decodes
the address, asserts MATCH H to the I/O control logic, and places the address on the three-state bus
lines. The I/O control logic decodes the three least significant bits of the three-state bus lines (DAT00
H through DATO02 H) and the LSI-11 bus control signals. The circuit develops register selection and
byte selection signals to enable the correct data paths between the computer and the appropriate device
register. It also controls INWD L, which determines whether the bus interface transceivers are transmitting or receiving. When data becomes available, the 1/O control logic gates it to its destination
(from the LSI-11 bus to the three-state bus for an output transfer, or from the three-state bus to the
LSI-11 bus for an input transfer),
2.3.4

Control/Status Registers

The DLVI11-E and DLV11-F each have two control/status registers: the RCSR and the XCSR. The
computer writes control bits out of these registers and reads status bits in from them. The registers
consist of a series of latches, data selectors, and gating circuitry. During data transactions mvolvmg
control and status information, the I/O control logic enables the XCSR or RCSR to elthcr latchin
control bits or gate out status bits.
When status information is to be read into the computer, the LSI-11 addresses the device register
containing the desired information. The bus interface and 1/O control logic decode the address and
enable the contents of the selected register to be placed on the bus and transferred into the computer.
When control informationis to be written out to the interface modules, the computer addresses the
device register thatis to be loaded. The bus interface and I/O control logic decode the address and
enable the register to load the control information when it is placed on the bus.

2-4

=582 2
WaGlmr
w g w g £ -

BBS7 L

DATO00-15 H

TRANSCEIVERS

J DEVICE

ADDRESS

REGISTERS

TRANSMITTER

cemaausmwsl

TM~

prveas—

ADDRES

JUMPERS

A3-A12

V3-V8

)

MAINT H

LEADS

(BOTH DLV11-E
AND DLV11-F)

20 mA CURRENT
LOOP AND
READER RUN

(DLV11-F ONLY)

;

| BREAK

DETE;?!GN

’—03*§

DC-TO-DC

POWER

VECTOR H

LSI-11 BUS

)

< BT,

FEW

LLosic

EIA DATA

[

VECTOR

JUMPERS

BREAK
GENERATION

(DLV11-E ONLY)

le—|

RECEIVER

CONTROL/STATUS
T

il L

TCLK H

STATUS

ADDRESS

RBUSY H

]| seriaLour

<g@ <xg

CONTROL/

VECTOR

& )

EsoZ|EH
.
e|E3

RCLK H

DECODER | GENERATOR

BSYNCL

EIA DATA

SET CONTROL

é 2 b §b

THREE-STATE BUS

INWD L

LOGIC |g

INTERFACE

BDAL 00.15 L

—4 mMODE

cfc|duT

BUS

seriaLIN | MAINTENANCE

INTERFACE

CONTROL CIRCUITRY

WOW|E

PERIPHERAL

BUFFERS

€

CIRCUIT

VEC

TOR

1/0 CONTROL

BAUD RATE CONTROL

BWTBT L
BRPLY L

INVERTER

+12V

MATCH H

VECRQSTB H

BDOUT L

BDIN L

.
BIRQ L

BIAKI L
BIAKO L

CONTROL
CIRCUITRY

TRANSMITTER
| CHANNEL

RECEIVER

TRANSMITTER

JUMPERS

RO-R3

TO-T3

RECEIVER
CHANNEL

BINITL

INTERRUPT LOGIC
_ BHALTL
. BDCOK H
i

11-4960

Figure 2-3

DLVI11-E and

DLV11-F Functional Block Diagram

2-5

TO PERIPHERAL EQUIPMENT

RECEIVER
ACTIVE

DATA

Not all control and status bits are both read and write; some are read~only bits and some are write-only
bnts A detailed descmptmnaf cach hxtis given thh the pmgmmmmg mfmmatmnin Chapwr 4
2.3.5 Data Buflers
,
The DLV11-E and the DLV11-F each have two data buffers one for receive data (RBUF) and one for
transmit data (XBUF). Both data buffers handle dma by bywsThe RBUF also hald& error flag bits
pertammg w the status of the re:cewed data
|

The data recewed from the pernpheral device i s tmnsferwd semallyfrom thepempheral mterfacc circuit

into a receive shift register in the data buffer. From there it is transferredin parallel to a holding
register. At the appropriate time, the buffer control circuitry places the parallel data, along with error
information, onto the module’s internal three-state
bus. The bus interface then transfers the data to the

computer.

Data to be transmitted to the peripheral deviceis taken off the thre:ewstate busin pamllel by the XBUF
and then shnfwd serially out to the penpheml mterface cmmt

Both the RBUF and the XBUF provide “double—»buffermg” of the data The buffcmngis doublein that

the circuits each have both a serial shift register and a parallel holding reglster This allmws one character to be held whfle anmheris bemg moved mtoorouttf tlw buffer
|

2.3. 6 Recelver Actlve Circult
The receiver active circuit monitors the serial received data line from the peripheral interface and a
receiver done (RDONE H) status bit from the RBUF. The circuit generates a busy signal (RBUSY H)
to indicate that the receiver is active. This signal sets the RCVR ACT bit in the RCSR.
2.3.7 Interrupt Logic
When a peripheral device interfaced by a DLV11-E or DLV11-F needs service, the module can, if
enabled, interrupt the computer program and vector to a service routine. The interrupt logic can
initiate two types of interrupts: a receiver interrupt and a transmitter interrupt. These interrupts are
handled through separate receiver and transmitter channels.

For an interrupt transaction to occur, first the program sets the interrupt enable bit in the control/status register. Next, the interrupt logic recognizes the condition requiring service and asserts the
interrupt request line (BIRQ L) to the computer. When the interrupt is acknowledged by the com-

puter, the mterrupt logic enables the bus mterface to placm the vector on the bus lines.

There are two vectors* onefor a receiver mtermpt and one for a transmlttar mterrupt The mtermpt
logic uses VECRQSTBH to mdwate whlch vecmr is enablwd
SR
|
The LSI-11’s interrupt acknowlcdgc sngnal (BIAKI L / BIAKO L)is daxsywchamed thmugh the devices
on the LSI-11 bus. A device’s priority is established by its position in the mterrupt acknowledge daisy-

chain. The interrupt acknowledge chain goes through both the receiver section and the transmitter
section of the module’s interrupt logic. It goes through the recewer smftmn fimt thereby gwmg the
receiver channel priority over the transmitter channel.

A receiver interrupt is initiated when the RBUF has received and assembled a character of data and is
ready to transfer it to the computer. A transmitter interrupt is initiated when the XBUF’& holding
reglster is empty andisready fm another data mput from the computer.

The DLV1 le mffers from the DLVHF in that it recogmze& a mmd conmtmn requiring a receiver
interrupt. The DLV 11-E initiates areceiver interrupt when the data set thatit is interfacing signals for
a handshake. The computer program can read the DLV11-E’s RCSR to determine whether the

receiver interrupt is for a handshake or for another character of data.
2-7

2.3.8

Baud Rate Control

‘

The baud rate control circuit gcncratcs clock signals that contml the speeds at which the RBUF and
XBUF move serial data. The circuit can provide a common clock to both data buffer circuits (common
speed operation) or separate transmit and receive clocks (split speed operation).

Should it be desired to use a baud rate not available from the baud rate mmrol’s crystal--»comrolled
clock generator, the module has provisions for external inputs for both the transmit and receive clocks.
2.3.9 Break Logic
A BREAK signal is a continuous spacing condltwn on the sanal data line. The DLVll-»E and

DLV11-F can receive BREAK signals from a peripheral device (normally the console device) and can
transmit BREAK signals to a peripheral device (normally another processor). Elther opcratnon can be
enabled or mhlblted by wire wrap jumpers.

When the interface module receives a BREAK signal from the serial data line, it mterprets the absence
of STOP bits as a framing error. It can respond to this apparent error (or to an actual ermr)in one of
three ways:

2.
3.

It can ignore it the apparent error.

It can place the LSI-11 in the HALT mode.
It can cause the LSI-11 to re-boot.

Which action the module takes is controlled by wire wrap jumpers. To placc the computarin the
HALT mode, the break logic asserts BHALT L. To cause the computer to reload a bootstrap, thc
break logic negates BDCOK H. Refer to Paragraph 5.9 for further mfmmatmn

2.3.10

Maintenance Mode Logic

2.3.11

DLVI1I1-E Penpheml Interface

The DLV11-E and DLV11-F have a maintenance mode for venfymg the opcratwn of the modulcs
data paths up to (but not including) the peripheral interface circuitry. This modeis controlled by the
computer program, butis used only for checking the interface module, not the computer. In maintenance mode, data from the computer is transferred from the bus interface to the XBUF and serialized,
as in normal operation. But then,in addition to going to the pcnpheral interface circuit, a sample of
the XBUF’s serial output is also routed back to the RBUF’s serial input. There it is converted to
parallel, placed on the three-state bus to the bus interface, and transferred back into the computer. The
program can then compare the received data with the transmittcd data to check for errors.

The peripheral interface circuitry converts the DLV11- E’s data and mndem control signals from TTL

levels to EIA-standard bipolar levels for the peripheral device. Likewise, it converts the peripheral’s
data and control lines from EIA levels to TTL levels for the interface module.
|

The circuit can receive four modem control signals (RING, CARRIER, CLEAR TO SEND, and

SECONDARY RECEIVED DATA) and can transmit four modem control signals (DATA TERMINAL READY, REQUEST TO SEND, FORCE BUSY, and SECONDARY TRANSMITTED
DATA). The control signals are routed through the control/status registers. The interrupt logic uses
the received control signals to initiate data set interrupts. The program uses the transmitted control
signals to perform handshakes with the data set. Refer to Paragraph 5.11 for an emmpie of a handshake sequence.

In common speed operation, both transmit and receive baud rates are either set by wire wrap jumpers
RO through R3 or programmable by three-state bus lines DAT12 H through DAT15 H. In split speed
operation, the transmit baud rate is set by jumpers TO through T3, while the receive baud rate remains
under the control of either RO through R3 or the computer program.

2.3.12

DLV11-F Peripheral Interface

The DLV11-F peripheral interface operates in one of two possible modes:

EIA Data Leads Only - This type of operation supports terminals that use EIA levels, but
do not require control signal interaction.

20 mA Current Loop - This operation supports terminals that use either active or passive
current loops. It also controls the paper tape reader on DIGITAL-modified TTY units that
have a reader run relay.

When interfacing EIA-level equipment, the module performs the TTL-to-EIA and EIA-to-TTL level
conversion on the transmit and receive data leads only. During data leads only operation, the module
does not monitor incoming control signals. Outgoing control signals (REQUEST TO SEND, FORCE
BUSY, and DATA TERMINAL READY) are held by driver circuits in a continuous TRUE
condition.

When the DLV11-F interfaces a 20 mA current loop peripheral device, it can be jumpered to operate in
either active or passive configuration. In the active configuration, the peripheral interface supplies the
current for the loop; in the passive configuration, the current is supplied by the peripheral device. In

either case, the receive data line from the peripheral is optically isolated from the DLV11-F’s internal
data path.

The 20 mA current loop transmitter operates in either the active or passive configuration. The transmit
data lines are optically isolated from the DLVI11-F’s internal data path only in the passive
configuration.

A Reader Run signal is produced for a peripheral device that has a reader run rélay. When enabled by
the program, the peripheral interface circuit supplies current to the relay, causing the reader to
advance the paper tape.

2.3.13

DC-to-DC Power Inverter

Both the DLVI11-E and DLV11-F need -12 V for the data buffers and the peripheral interface. This

voltage is produced on the module by a small power inverter. The inverter uses the +12 V power
available on the LSI-11 backplane to produce a regulated -12 V for the data buffers and peripheral
interface circuits.

CHAPTER 3
INSTALLATION

3.1

GENERAL

This chapter describes thejumper configuration, the installation requirements, and thc checkout of the
DLV11-E and DLV11-F asynchronous line interface modules. The wire wrap jumper functions are
defined and application examples are presented. Wire wrapping instructions are presented in
Appendix B.

3.2

CONFIGURATION

Before installing the module, ensure that it is configured for your application. The jumper locations
are depicted in Figures 3-1 and 3-2. Their functions are defined in Tables 3-1, 3-2, and 3-3. Table 3-4
explains the configuration in which the modules are shipped from the factory. Table 3-5 lists common
applications of the DLV11-E and DLV11-F; Figures 3-3 and 3-4 illustrate examples of typical cabling
requirements.

The DLV11-F is shipped from the factory with capacitor C29 installed (Figure 3-2). This capacitor is
provided for applications using Teletype® terminals. For applications using DIGITAL terminals, remove capacitor C29.

3.3

MODULE INSTALLATION

The DLVI11-E or DLV11-F module can be installedin any slotsin the LSI-11 backplane, except the
first four slots (the LSI-11 processor always occupies the first slots). Do not leave any unused optmn
locations between the processor and the DLV11-E or DLV11-F. An open slot would break the interrupt acknowledge daisy chain. The priority of the moduleis determined by its proximity to the processor on the bus (refer to Figure 3-5). The closer the slotis to the processor module, the higher the
interface module’s priority.

Determine the appropriate slot for the module. For example, if a DLV11-E is interfacing communications lines from a host computer, it would normally be placed in the slot closest to the processor
module, followed by the module interfacing the console terminal. Refer to Microcomputer Handbook
(DIGITAL part number EB 06583 76) for system considerations.

®Teletype is a registered trademark of Teletype Corporation.

wFDi I-»FFt

lKG
e
W

11-5172

Figure 3-1

DLV11-E Jumper Locations

3-2

RO
R1
R2
R3
—
—
—

I PB
Sclaononem
<LIILILI<A

IHIHHH o

i
:

MIR WO
0

115173

‘Figure 3-2 DLVI11-F Jumper Locations

3-3

Table 3-1

Jumper Definitions

NOTE
This table pertains to both the DLV11-E and the
DLV11-F, except as noted. Jumpers are inserted to
enable the function they control except for those
jumpers that indicate negation (such as ‘“-B” and
“B’’). Negated jumpers are removed to enable the
functions they control.
Jumper

Function

A3-Al2

These jumpers correspond to bits 3-12 of the address word. When
inserted, they will cause the bus interface to check for a True condition
on the corresponding address bit.

V3-V38§

Used to generate the vector during an interrupt transaction. Each
inserted jumper will assert the corresponding vector address bit on the
LSI-11 bus.

R0O-R3

Receiver and transmitter baud rate select jumpers, during common
speed operation.
Receiver only baud rate select jumpers during split speed operation (see
Table 3-2).
|

TO-T3

Transmitter baud rate select jumpers during split speed operation.

Both receiver and transmitter baud rate if maintenance mode is entered
during split speed operation (see Tale 3-2).
BG

Jumper is inserted to enable Break generation.

Jumper is inserted for operation with parity.

Removed for even parity; inserted for odd parity. Receiver checks for

appropriate parity and transmitter inserts appropriate parity.

1, 2

These jumpers select the desired number of data bits (see Table 3-3).

Jumper is inserted to enable the programmable baud rate capability.

C, Cl

These jumpers are inserted for common speed operation. (Note that S

S, S1
H

and S1 must be removed when C and C1 are inserted.)

Inserted for split speed operation. (Note that C and Cl must be re-

- moved when S and S1 are inserted.)

This jumper is inserted to assert BHALT L when a framing error is

received, except when the Mamtenance bltis set. This places the LSI-11
in the halt mode.
|
|

Table 3-1 Jumper Defimtions (Ct:mt)
Jumper
B, -B
(DLV11-E)

| VFunction
Jumper B is inserted to negate BDCOK H when a BREAK signal or
framing error is received, except when the Maintenance
bit is set. This

B,B

causes the LSI-11 to reload the bootstrap. (Jumper -B or B must be

-FD
(DLV11-E
only)

Jumper is removed to force DATA TERMINAL READY signal on.

(DLV1I-F)

-FR
(DLVII-E
only)

RS
(DLVII-E
only)
FB

(DLVI11-E

removed when B is inserted.)

Jumper is removed to force REQUEST TO SEND signal on.

This jumper is inserted to enable normal transmission of the
REQUEST TO SEND signal.

Inserted to enable transmlssmn of the FORCE BUSY mgnal (for Bell
model 103E data sets).

only)

1A, 2A,
and 3A
(DLV11-F
only)

These three jumpers are inserted to make the 20 mA current loop
receiver active. (Jumpers 1P and 2P must be removed when 1A, 2A, and
3A are inserted.)
5

1P, 2P
(DLV11-F
only)

These jumpers are inserted to make the 20 mA current loop receiver
passive. (Jumpers 1A, 2A, and 3A must be removed when 1P and 2P are
installed.)
|

4A, S5A

Inserted to make the 20 mA current loop transmitter active. (Jumpers

(DLVI11-F
only)

3P and 4P must be removed when 4A and 5A are inserted.)

3P, 4P
(DLV11-F
only)

Inserted to make the 20 mA current loop transmitter passive. (Jumpers
4A and SA must be removed when 3P and 4P are inserted.)

Jumper is removed to enable the error flags to be read in the high byte

(DLVI11-F
only)

of the Receiver Buffer.

MT
(DLVI11-F
only)

When inserted, enables maintenance bit.

M, Ml

These are test jumpers used during the manufacture of the module.
They are not defined for field use.

Table 3-2

Program Control
Receive Jumpers
Transmit Jumpers

Baud Rate Selections

Bit

15
R3
T3
I
I
I
I
I
I
1
I
R
R
R
R
R
R
R

14
R2
T2
I
I
I
I
R
R
R
R
I
I
1
I
R
R
R

13
R1
Tl
I
I
R
R
I
I
R
R
I
|
R
R
I
I
R

Bit

12
RO
TO
1
R
1
R
I
R
I
R
I
R
1
R
I
R
I

11*

Baud
Rate
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600

I = Jumper Inserted = Program Bit Cleared.
R = Jumper Removed = Program Bit Set.

*Bit 11 of the XCSR (Write Only Bit) must be set in order to select a new baud rate under program control. Alsa,
jumper PB must be inserted to enable baud rate selection under program control.

Table 3-3 Data Bit Selections |
J nmper‘s
'

I
I
R
R

|
R
I

Number of Data Bits |
5
6
7
8

Jumper

Table 34 Jumper Configuration When Shipped

Jumper

State

Designation | DLV11-E | DLV11-F

»
>

A4
AS

I
I

R
R

]

| - J umpers A3 thmugh ’Al 2 impl{z;ement;‘d‘evice jaddress

17561X for the DLV11-E and 17756X for the DLV11-F.
The least significant octal digit is hardwired on the module
to address the four device registers as follows:
“
|
X=0
RCSR

A6
A7
A8

I
R
R

R
I
R

Al0
All

I
R

R
R

Al2

I
I
R

R
R
I

-~ This jumper selection impleméfits interrupt vector address

V7
V8

R
I

I
I

~ interrupts.

V4
VA
V6

TO
T1
T2

I
R
R

‘

- Function Implemented

X=4
X=6

XCSR
XBUF

3004 for receiver interrupts and 3044 for transmitter
interrupts on the DLVI11-E. On the DLV11-F it selects
604 for receiver mtermpts and643 for transmitter

The module is configured to receive at 110 baud.

The transmitter is cmnfigured fm 9600 baudif split speed
operation is used.

Break generafion is enabled.
Parity bit is disabled.

Parity type is not applicable when P is removed.

* Operation with 8 data bits per character.

Programmable baud rate function disabled.. |

Common speed operation enabled.

Table 3-4

Jumper
Designation

Jumper Configuration When Shipped (Cont)

Jumper State
[DLVII-F

.
|
B
Function Implemented

| DLVI1-E

Split speed operation disabled.

Halt on framing error disabled on DLV 11-E; enabled
on DLVI11-F.

-B
B

I
N/A

N/A
I

“N/A

-FD

-FR

The DATA TERMINAL READY signal is not forced

continuously True.

N/A

Boot on framing error disabled.

The REQUEST TO SEND signal is not forced continuously
True.

N/A

The circuitry mntmlling the REQUEST TO SEND signal
is enabled.

N/A

The FORCE BUSY signal is disabled.

N/A

The 20 mA current loop receiver is configured as an

N/A

active receiver.

N/A

R
R

N/A

The 20 mA current loop transmitter is configured for

N/A

active operation.

N/A

Error flags are enabled on DLV11-E; disabled on DLV11-F.

Factory test jumpers. Not defined for field use.

"N/A

~ Maintenance bit disabled.

Table 3-5 Module Application Examples

Module/Mode

DLVII.E

Equipment Supported

Modem Control

BellDataSets, Models:

103

202C
202D
212A

DLV11-F
EIA Data Leads Only

DLVILF

Bell Model 103 Data Set (in automode).
Teletype Model 37 Teletypewriter

|
-

Teletype Model 33 and 35 Teletypewmers

P LA36 DECwhter(read

writer (read

| 20mA Current Loop

/write

LA35 DECwriter (read only)

write

VTO5B Alphanumeric Terminal
VTS50 DECscope (12 line)
VT52 DECscope (24 line)

RTO02 Alphanumeric Terminals
DFO01-A Acoustic Telephone Coupler
- LT33 Teletypewriter
,
LT35 Teletypewriter

DATA SET CONTROL
40 PIN

DLVI1-E

CONN

Ml IFI

—

DB-25

Im| |F|
|

BELLIOS

LL 202

11-4961

Figure 3-3

DLVI11-E Cabling Example

'CURRENT LOOP MODE
40 PIN

CONN.

DLVII=-F

F |

BCOSM

MATE ~N-

LOK

LA36

VT52

ALs

40 PIN

(RECEIVER
PASSIVE,

TRANSMITTER
ACTIVE)

DLV11—F
(

...BCOSM

F i

PASSIVE,

40 PIN

CONN.

PASSIVE)

BCOSF

{F]

[

[
|

F |

BCOSM _

MATE-N-

LOK

40 PIN

| F

(RECEIVER

TRANSMITTER
ACTIVE)

c;oww.

BCO5M

PASSIVE,

40 PIN

LOK

|_BcosF_

| |

MATE-N -

BCOSM

Ml | F

MATE ~N -

RECEIVER

TRANSMITTER

MATE-N-

DL11~C

EIA "DATA LEADS ONLY" MODE
40 PIN
CONN

DLV11-F

“
DB-25

BCOS5C
M

DB-25

BCO3P
I F

NULL MODEM CABLE

40 PIN
CONN

TERMINAL

vTosé

DB -25

BCO5C

DLVII-F

EIA/CCITT

MODEL 103
DATASET

(AUTO MODE)

11-4962

Figure 3-4

DLVI11-F Cabling Examples

3-10

VIEW FROM MODULE SIDE OF BACKPLANE
A

KD1-F

MSV11-B

DLVII-E

MSV11 - B

RX V11

REV11

DRV11

CONNECTOR
BLOCK
11-4963

Figure 3-5

Typical Backplane Configuration

After the module has been configured properly and the desired location determined, install it in the
computer as follows:

CAUTION

DC power must be removed from the backplane during module insertion and removal.
The module and backplane connector block may be
damaged if the module is plugged in backwards.

Position the module so that the components side is facing row 1.

Slide the module into its slot, taking care that the module fingers mesh correctly with the

backplane connector block.

Press the module into the connector block, making sure that the deep notch on the module

seats against the connector block rib.
4.

Next, plug the interface cable into the module’s 40-pin header connector.

When the other end of the interface cable is installed, the module can be powered up and checked out.
Interface cable installations are shown in Figures 3-3 and 3-4. Interface connector pinning is listed in
Tables 3-6 and 3-7. Bus connector pinning is listed in Table 3-8.
3.4

MODULE CHECKOUT

A diagnostic program is shipped with the module, and should be run to verify the proper operation of
the module. The program runs on an LSI-11 with the most basic options. Perform the diagnostic
checkout as explained in Paragraph 3.4.1 or 3.4.2. If a malfunction is detected, contact the nearest
DIGITAL Field Service office.

Table 3-6
Header
Berg

M8017 Module

Signal Names

A
B
C
D
E
F
H
J
K
L
M
N

P
R
S
T
U

\'%

\\%
X
Y

Z
AA
BB

DLV11-E 40-Pin Header Connector Pinning

BC05C Modem Cable
Signal Names

Ground

Ground
Force Busy (EIA)
Serial Input (TTL)
Serial Output (EIA)

Ground
Force Busy
Sec. Clear to Send
Interlock In «
Transmitted Data

Serial Input (EIA)

Received Data

EIA Interlock

Interlock Out
Serial Clock XMIT

External Clock

Sec Request to Send
Serial Clock RCVR
Clear to Send (EIA)

Request to Send (EIA)

Clear to Send

Request to Send
- Power

Ring (EIA)

Ring
+ Power

Data Set Ready
Carrier (EIA)

Carrier

CC
DD
EE
FF
HH
JJ
KK
LL
MM
NN
PP
RR
SS
TT

External Clock Input (TTL)
Data Terminal RDY (EIA) | Data Terminal RDY

Serial Output (TTL)
+5V

Uuu
\'A'%

Ground
Ground

Secondary XMIT (EIA)
External Clock ENB (TTL)
Secondary Rec (EIA)

202 Sec XMIT
202 Sec RCVR

EIA Sec XMIT
Signal Quality
EIA Sec RCVR
|

Ground
Ground

*This jumper is built into the cable.

3-12

Table 3-7

DLV11-F 40-Pin Header Connector Pinning

Header
Pin

M8028 Module
Signal Names

BC0SC Modem Cable
Signal Names
|

BCO05M 20 mA Cable

A
B
C
D
E

Ground
Ground
Force Busy (EIA)

Ground

H
J

20 mA Interlock

K
L
M
N
P

R
S
T

Serial Input (TTL)

Serial Output (EIA)

Transmitted Data

Serial Input (EIA)

Received Data

Serial Input + (20 mA)

~
External Clock
Interlock Out
Serial Clock XMIT
Sec Request to Send

EIA Interlock

Serial Clock RCVR

Serial Input - (20 mA)

Request to Send (EIA)

X
Y

Interlock Out

Received Data +

Received Data -

Request to Send
- Power
“Ring
+ Power

Data Set Ready
Serial Output+(20 mA)

Transmitted Data+

Carrier
Ext. Clock Input (TTL)
Data Terminal RDY

Data Terminal RDY

(EIA)
Reader Run - (20 mA)

|
.;
Interlock In

Clear to Send

Z
AA
BB
CC
DD

Ground
Ground
Force Busy
Sec Clear to Send
Interlock In

Reader Run 202 Sec XMIT

Ext. Clock Enb (TTL)

202 Sec RCVR

KK
LL
MM
NN
PP
RR
SS
TT

Serial Output

Serial Output (TTL)
+5V

Uuu
‘A"

Ground
Ground

o
Reader Run+(20 mA)

EIA Sec XMIT
Signal Quality
EIA Sec RCVR

*
Reader Run+

Signal Rate

Ground
Ground

3-13

Ground
- Ground

Table 3-8 DLV11-E and DLV11-F Edge Connector Pinning
Mnemonic

AA2

+12
BBS7L
BDALOL
BDALIL

AD?2
AP2
AU2
AV?2

BIAKOL*
BINITL
BDMGIL*
BDMGOL*
BIRQL
BRPLY L
BSYNCL
BDCOKH
GND
GND(
GND
GND
MSPARE A (-12V)

AKl1

BA?2

BDAL2L
BDAL3L
BDALA4L
BDALSL
BDALG6L
BDAL 7L
BDALSL
BDALO9L
BDAL IOL
BDAL11L
BDAL I2L
BDAL 13L
BDAL 14 L
BDAL ISL
BDIN L
BDOUTL
BHALTL
BIAKIL*

BE2
BF?2
BH?2
BJ2
BK2
BL2
BM?2
BN2
BP2
BR2
BS2
BT2
BU2
BV?2
AH?2
AE2
API
AM?2
AN?2
AT2
AR2
AS?2
AL2
AF2
Al2
BAI1
AC2
ATl
BC2
BT1

MSPARE B (EXT R CLK)
SSPARE4
SSPARE 5
SSPARE 6
SSPARE 7
SSPARE 8 (EXT T CLK)

€

ALl

BK1 ::]
BL1

BCl1
BDI1
BE1
BF1
BHI1

*These signals are not bussed, they are daisy-chained.

**This jumper is wired on the backplane.

3-14

3.4.1

DLVI11-E Checkout

To verify the operation of the DLV 11-E, turn off the dc power and remove the interface cable from the
data set. Leave the other end connected to the module’s header connector. Plug an H315 terminator
into the free end of the interface cable. Power up the computer. Load and start MAINDEC-11DVDVA. When the program has been completed successfully, turn off the dc power and reconnect the
interface cable to the data set.

3.4.2 DLVI11-F Checkout
The DLVI11-F does not require a terminator plug for checkout. Load and start MAINDEC-11DVDVC. Successful completion of the program indicates the module is acceptable.

3-15

CHAPTER 4
PROGRAMMING

4.1
INTRODUCTION
|
Both the DLV11-E and DLV11-F are program compatlblc with PDP-11 software. Programs written
for PDP-11’s using DL11-A through -D interface modules will run on an LSI-11 using a DLV11-F

configured for the same application. Programs written for a DL11-E will run with a DLV11-E. Also,
the DLV11-F will operate with LSI-11 programs written for the DLV11.
This chapter defines the bitsin each of the four device registers, discusses interrupts and timing consid-

erations, and gives programming examples.

4.2 DEVICE REGISTERS
All software control of the DLV11-E or DLVII F Asynchronous Line Interface is performed by
means of four device registers. These registers have been assigned bus addresses and can be read or
loaded (with the exceptions noted) usmg any LSI-11 instruction referring to their addresses. Address
assignments can be changed by alteringjumpers on the module to corrcspond to any address within
the range of 160000 to 177777. Table 4-1 lists the addresses of the registers when the moduleis used to
interface a console device. The RCSRis at the base address. Each subsequent register is two locations
up from the one preceding it.

Table 4-1

Mnemonic

Address

Receiver Control/Status Register
Receiver Buffer Register
|
Transmitter Control/Status Register
Transmitter Buffer Register
.

RCSR
RBUF
XCSR
XBUF

177560
177562
177564
177566

The DLVI1I1-E RCSR differs from the DLV11-F RCSR; therefore, the bits for these two RCSRs are
defined separately. The DLVII-E and DLV11-F operate identically with respect to the three other
device registers. The bit definition for these registers applies to both modules. Figures 4-1 and 4-2 show
RCSR bit assignments. Figures 4-3, 4-4, and 4-5 show the RBUF, XCSR, and XBUF, respectively.
Tables 4-2 through 4-6 define the bit assignments.

DATA
CLR
| CAR |RCVR| SEC
SET
TO | DET | ACT | REC
ST | RING | stp

08
l

RESERVED
l

Figure 4-1

DLVI11-E RCSR Bit Assignments

Table 4-2

DLV11-E RCSR Bit Assignments

Bit

Name

Meaning and Operation

DATA SET INT
(Data Set Interrupt)

This bit initiates an interrupt sequence provided
the DATA SET INT ENB bit (05) is also set.

This bit is set whenever CAR DET, CLR TO
SEND, or SEC REC changes state; i.e., on a 0-to-1
or 1-to-0 transition of any one of these bits. It is
also set when RING changes from 0 to 1.

Cleared by INIT or by reading the RCSR. Because

reading the register clears the bit, it is, in effect, a
“read-once’’ bit.

RING

When set, indicates that a RINGING signal is
being received from the dataset. Note that the
RINGING signal is not a level but an EIA control
with the cycle time as shown below:

l2sec

4 sec

4 sec
2 sec

2 sec L

Read-only bit.
13

CLR TO SEND
(Clear to Send)

The state of this bit is dependent on the state of the
CLEAR TO SEND signal from the data set. When
set, this bit indicates an ON condition; when clear,
it indicates an OFF condition.
Read-only bit.
»

CAR DET

(Carrier Detect)

This bit is set when the data carrier is received.
When clear, it indicates either the end of the current transmission activity or an error condition.
Read-only bit.

RCVR ACT
(Receiver Active)

When set, this bit indicates that the DLVI11-E’s receiver is active. The bit is set at the center of the
START bit, which is the beginning of the input se-

rial data from the device, and is cleared by the lead-

ing edge of R DONE H.

Read-only bit; cleared by INIT or by R DONE H

(bit 07)
4-2

Table 4-2

Bit

Name

SEC REC
(Secondary Received
or Supervisory
Received Data)

DLVI11-E RCSR Bit Assignments (Cont)

Meaning and Operation

This bit provides a receive capability for the reverse
channel of a remote station. A space (®+10 V) is
read as a 1. (A transmit capability is provided by
bit 03.)
- Read-only bit.

9-8

Not Used

Reserved for future use.

RCVR DONE
(Receiver Done)

This bit is set when an entire character has been
received and is ready for transfer to the LSI-11.
When set, initiates an interrupt sequence provided
RCVR INT ENB (bit 06) is also set.

Cleared whenever the receiver buffer (RBUF) is
addressed. Also cleared by INIT.

Read-ofinly bit

RCVR INT ENB

(Receiver Interrupt
Enable)

When sef, allows an interrupt sequence to start
when RCVR DONE (bit 07) sets.

Read/write bit; cleared by INIT. See Note 1.

DSET INT ENB
(Data Set Interrupt
Enable)

When set, allows an inerrupt sequence to start
when DATA SET INT (bit 15) sets.

Not Used

Reserved for future use.

SEC XMIT
(Secondary Transmitted
or Supervisory
Transmitted Data)

This bit provides a transmit capability for a reverse
channel of a remote station. When set, transmits a
space (®+10 V). (A receive capability is provided
by bit 10.)

|
Read/write bit; cleared by INIT. See Note 1.

Read/write bit; cleared by INIT.
02

REQ TO SEND
(Request to Send)

A control lead to the data set which is required for
transmission. A jumper on the DLV11-E ties this
bit to REQ TO SEND or FORCE BUSY in the
data set.
Read/write bit; cleared by INIT.

Table 4-2
Bit

Name

DTR (Data Terminal)

DLV11-E RCSR Bit Assignments (Cont)
Meaning and Operation

Ready)

A control lead for the data set communication

channel. When set, permits connection to the channel. When clear, disconnects the interface from the

channel.

Read/write bit; must be cleared by the program, is
not cleared by INIT. (See Note 2.)

NOTES
When clearing an interrupt enable bit,
first set the processor to its highest prior-

ity [Processor Status Word (PSW) bit 7
= 1]. After the interrupt enable bit is
cleared, the processor may be returned to
its normal priority (PSW bit 7 = 0).
For example:
MTPS #200
BIC #100, CSR
MTPS #0
EXIT

For further information refer to Paragraph 4.6.
The state of this bit is not defined after

power-up.

4-4

]

RESE‘RVED :

1
"

RCVR
et

09
|

n::s;nv:-":p

©O6

| reVR
RCVR | NT |
oone

04
|

O3
P

02
|

,
Riesmveim

]

RDR
RbA

11-4965

Figure 4-2

DLVI11-F RCSR Bit Assignments

Table 4-3

DLV11-F RCSR Bit Assignments

Bit

Name

. Meaning énd Opération

15-12

| NaiUsed

’ Rcserved for future use.

RCVRACT

| When set, this bit indicates that the DLV11-F in-

Active)

of the START bit, which is the beginning of the

Receiver

terface receiver is active. The bit is set at the center

input serial data from the device, and is cleared by
the leading edge of RDONE H.

Read-only bit; cleared by INIT or by RCVR
DONE (bit 07).

10-08

Not Used

Reserved for future use.

RCVR DONE

This bit is se"t” when an entire character has been

(Receiver
Done)
e

received and is ready for transfer to the LSI-11 bus.

- When set, initiates an interrupt sequence provided
RCVR INT ENB (bit 06) is also set.

Read-only bit; cleared whenever the receiver buffer

(RBUF) is addressed or whenever RDR ENB
(bit 00) is set. Also cleared by INIT.
|
06

05-01
00

RCVR INT
ENB
(Receiver
Interrupt
Enable)

When set, allows an interrupt sequence to start
when RCVR DONE (bit 07) sets.

Not Used

Reserved for future use.

RDR ENB

When set, this bit advances the paper-tape reader

(Reader
Enable)

Read/write bit; cleared by INIT.

in DIGITAL-modified TTY units (LT33-C; LT35A, -C) and clears the RCVR DONE bit (bit 07).

This bit is cleared at the middle of the START bit,

- which is the beginning of the serial input from an
external device. Also cleared by INIT.

Write-only bit.

4-5

eRROR | 0% | TR | ho

RESERVED

©O5

RECEIVED DATA BITS
11- 4966

Figure 4-3

DLVI11-E and DLV11-F RBUF Bit Assignments

Table 4-4

DLV11-E and DLV11-F RBUF Bit Assignments

Bit

Name

- Meaning and Operation

ERROR
(Error)

Used to indicate that an error condition is present.
This bit is the logical OR of OR ERR, FR ERR,
and P ERR (bits 14, 13, and 12, respectively).

Whenever one of these bits is set,
it causes ERROR
to set. This bit is not connected to the interrupt
logic.
i

Read-only bit; cleared by removing the error-producing condition.
NOTE
Error indications remain present until the next character is received, at which time the error bits are
updated. INIT clears the error bits.

OR ERR
(Overrun
Error)

When set, indicates that reading
of the previously

received character was not completed (RCVR
DONE not cleared) prior to receiving a new
character.

Read-only bit. Cleared by INIT.

FR ERR

When set, indicates that the character that was

Error)

S
Read-only bit. Cleared by INIT.

(Framing

P ERR
(Parity
Error)

read had no valid STOP bit.

When set, indicates that the parity received does
- not agree with the expected parity. This bit is
always 0 if no parity is selected.
Read-only bit. Cleared by INIT.

11-08

Not Used

07-00

RECEIVED

DATA BITS

Reserved for future use.

Holds the character just read. If less than eight bits

~ are selected, then the buffer is right-justified into
the least significant bit positions. In this case, the
higher unused bit or bits are read as 0’s.

Read-only bits; not cleared by INIT.
4-6

| et
| S0
ggf
ggfi
| QEE ‘“
3
2
{
o |ENB |

©O8

'fieseweo‘ ~

i T | Reserven

| RDY | enB

wamT||SERVED|
RE- BREAK
11-4987

Figure 4-4

DLVI11-E and DLV11-F XCSR Bit Assignments

" Table4-5 DLV11-E and DLV11-F XCSR Bit Assignments
Bit

Name

15-12

PBR SEL

(Programmable
Baud Rate
Select)

“j Meaning and Operation
1

When §s¢t, these bits choose a baud rate from
50-9600 baud. See Table 3-2.

S
Write-only bits.

PBR ENB

This bit must be set in order to select a new baud

(Programmable

rate indicated by bits 12 to 15.

Baud Rate

Enable)

10-08

Write-only bits.

| NotUsed

XMIT RDY
(Transmitter
Ready)
-

Reserved for future use.
This bit is set when the transmitter buffer (XBUF)

can accept another character. When set, it initiates
~an interrupt sequence provided XMIT INT ENB
(Bit 06) is also set.

Read-only bit; set by INIT.
06

05-03
02

XMIT INT ENB
(Transmitter
Interrupt

When set, allows an interrupt sequence to start
when XMIT RDY (bit 07) is set.

Enable)

Read/write bits; cleared by INIT. See Note.

Not Us‘c’dn

Reserved for future use.
Used for maintenance function. When set, connects the transmitter serial output
to the receiver
serial input while disconnecting the external device
- from the receiver serial input. It also forces the re-

ceiver to run at transmitter baud rate speed when
split speed operation is enabled.
Read/write bit; cleared by INIT

Table 4-5

DLVI11-E and DLV11-F XCSR Bit Assignments (Cont)

Bit

Name

Meaning and Operation

Not Used

Reserved for future use.

BREAK

When set, transmits a continuous space to the external device.

Read/write bit; cleared by INIT.
NOTE

“

When clearing an interrupt enable bit, first set the
processor to its highest priority (PSW bit 7 = 1).
After the interrupt enable bit is cleared, the processor may be returned to its normal priority (PSW bit
7 = 0). For example:
MTPS #200
BIC #100, CSR
MTPS #0
EXIT

For further information refer to Paragraph 4.6.

15
RESERVED

07
TRANSMITTER DATA BUFFER

11-61656

Figure 4-5

DLVI11-E and DLV11-F XBUF Bit Assignments

Table 4-6 DLV11-E and DLV11-F XBUF Bit Assignments

’

Bit

Name

Meaning and Operation

15-08

Not Used

Not defined. Not necessarily read as 0s.

07-00

TRANSMITTER
DATA BUFFER

Holds the character to be transferred to the external device. If less than eight bits are used, the character must be loaded so that it is right-justified into

the least significant bits.

Write-only bits. Not necessarily read as 0s.

The unused and load-only bits are always read as 0’s except for the XBUF, in which unused bits are
undefined. Loading unused or read-only bits has no effect on the bit position. The mnemonic INIT
refers to the initialization signal issued by the processor. Initialization is caused by one of the following: issuing a programmed RESET instruction; pressing “G’’ while in ODT; or the occurrence of a
power-up or power-down condition of the processor power supply.
,
In the following descriptions, ‘‘transmitter” refers to those registers and bits involved
in accepting a
parallel character from the LSI-11 for serial transmission to the external device; “receiver” refers to
those registers and bits involved with receiving serial information from the external device for parallel
transfer to the LSI-11.
4.3

INTERRUPTS

Both the DLV11-E and the DLV11-F have two interrupt channels: one for receiver interrupts and one
for transmitter interrupts. These two channels operate independently. If, however, simultaneous interrupt requests occur, the receiver channel has priority over the transmitter channel.

In both the DLV11-E and the DLV11-F, a transmitter interrupt can occur only if the interrupt enable
bit (XMIT INT ENB) in the XCSR is set. With XMIT INT ENB set, setting the transmitter ready
(XMIT RDY) bit initiates an interrupt request. When XMIT RDYis set, it indicates that the XBUF is
empty and ready to accept another character from the bus for transfer to the external device.
A receiver data interrupt can occur only if the interrupt enable (RCVR INT ENB) bit in the receiver
RCSR is set. With RCVR INT ENB set, setting the receiver done (RCVR DONE) bit initiates an
interrupt request. When RCVR DONE is set, it indicates that an entire character has been received
and is ready for transfer to the bus. The receiver data interrupt occurs in both the DLV11-E and the
DLVI11-F. The DLVI11-E also has a data set interrupt.
The receiver portion of the DLV11-E handles multisource interrupts. One of the receiver interrupt
circuits is activated by RCVR INT ENB and RCVR DONE. The other interrupt circuit can cause an
interrupt only if the data set interrupt enable bit (DATA SET INT ENB) in the RCSR is set. With
DATA SET INT ENB set, setting the DATA SET INT bit initiates an interrupt request. The DATA
SET INT bit can be set by any of four other bits: CAR DET, CLR TO SEND, SEC REC, or RING.

'NOTE

When servicing a receiver interrupt from the
DLVI11-E, if a second receiver interrupt condition
develops a second interrupt request may not occur.
To avoid missing this second interrupt condition,
either all possible receiver interrupt conditions
should be checked after servicing the first condition,
or else both interrupt enable bits (bits 05 and 06)
should be cleared upon entry to the service routine
and then set at the end of service.

4-9

4.4

TIMING CONSIDERATIONS

When programmmg the DLV11-E or DLV11-F Asynchmnous Lme Interfacc, 1t is 1mportant to con-

sider timing of certain functions in order to use the system in the most efficient manner. Timing
considerations for the receiver, transmlttcr, and brcak generation logic are dlscusscdin the followmg
paragraphs.
|
—
|
|
4.4.1

Receiver

The RCVR DONE flag (blt 07 in thc RCSR) sets when the receiver has asscmblcd a full charactcr

This occurs at the middle of the first STOP bit. Because the receiver is double buffered, data remains
valid until the next character is received and assembled. This permits one full character time for
servicing the receiver interrupt.
4.4.2 Transmitter
The transmitter is also double buffcrcd Thc XMIT RDY flag (bit 07in thcXCSR)is sct aftcrinitialization. When the XBUFis loaded with the first character from the bus, the flag clears but then
sets again within a function of a bit time. A second character can then be loadcd Wthh clears the flag
again. The flag then remains cleared for ncarly one full character time.
|
.
|

4.43 BREAK Generatmn Logic
'«
IS IRt
When the BREAK bit (bit 00 in the XCSR) is set, it causes transmtssmn of acontmucus space.
Because the XMIT RDY flag continues to function normally, the duration of a BREAK can be timed
by the pseudo-transmission of a number of characters. However, because the transmitter is double
buffered, a null character (all 0’s) should precede transmission of the BREAK to ensure that the
previous character clcars thc line. In a similar manner, the final pseudo-transm1tted characterin the
BREAK should be null.
»
|
|
e
4.4.4 System Reset Timing
A system reset should not be pcrfcrmcd immediately after the processor loads a character into the

transmitter buffer for serial transmission. If the system is reset before the last character has left the
transmitter buffer, the character will be lost when the buffer is cleared by INIT. To avoid this, the

program should transmit two null characters after thc last character and then wait for XMIT RDY to
return to its true state.

Programs developed on the DLV-11 Serial Line‘Unit
(M7940) may not include these null characters, since
the DLV-11s transmitter bufferis not clcared by the
INIT sugnal
S
|
-

4.5

PROGRAMMING EXAMPLES

Table 4-7 is an example of a typical pmgram that can be used as an echoprogram for a DLVI1I1-E
interfacing a Bell Model 103 data set. When a remote terminal dialsin, this program answers the call
and provides a character-by-character echo. Characters are also coplcd onto the console device.

Figure 4-6 depicts a DLV11-F program. The program demonstrates the flexibility of programming
with interrupts. It is performed on a console terminal interfaced by the DLV11-F. The program exercises the module’s full-duplex capability.

4-10

Table 4-7

DLV11-E Programming Example

000200
000200

000167

=200
001616

START-

IMP

BEGIN

;JUMP TO BEGINNING
;OF PROGRAM

:SYMBOL DEFINITIONS
040000

RING=

040000

;BIT 14 OF RCSR, RING

020000

CTS=

020000

;BIT 13 OF RCSR,

000200

RDONE=

000200

;BIT 07 OF RCSR,

,CLEAR TO SEND
;RECEIVER DONE

000002

DTR=

000002

;BIT 01 OF RCSR, DATA

000200

XRDY=

000200

,BIT 07 OF XCSR,

,TERMINAL READY
;,TRANSMITTER READY

002000
002000

175610

002002

175612

002004

175614

002006

.=2000

RCSR:

175610

;CSR OF RECEIVER

RBUF:

175612

;BUF OF RECEIVER

175616

XCSR:
XBUF:

175614
175616

;BUF OF TRANSMITTER

002010

177564

CXCSR:

177564

;CSR OF CONSOLE

002012

177566

CXBUF:

177566

;BUF OF CONSOLE

002014

000000

;CSR OF TRANSMITTER

;TRANSMITTER
;,TRANSMITTER
BUFFER:

;HOLDS CHARACTER

;RECEIVED

002016

000000

002020

000000

DELAY:

;HOLDS DELAY COUNT,

;HIGH ORDER

;BEGINNING OF ECHO PROGRAM
002022

005077

002026

032777

002034

001774

002036

052777

002044

177752

040000

BEGIN:

177744

LOOPI:

CLR

@RCSR

;LOW ORDER

;START BY INITIALIZING

;ALL BITS TO ZERO

BIT

# RING,@RCSR

;CHECK FOR INCOMING CALL

BEQ

LOOPI

;BRANCH IF PHONE IS NOT
;RINGING

012767

000002

177734

BIS

#DTR,@RCSR

;PHONE IS RINGING, SO
;ANSWER WITH DTR

000005

177744

MOV

#5,DELAY

,SET UP COUNT FOR DELAY

4-11

LyL

Table 4-7

002052

032777

020000

177720

DLV11-E Programming Example (Cont)

LOOP2:

BIT

#CTS,@RCSR

,CHECK FOR CLEAR
;,TO SEND

002060

001007

002062

162767

000001

002070

005667

177722

002074

001752

177730

BNE

LOOP3

;BRANCH IF ON

SUB

#1,DELAY+2

;CHECK DELAY

SBC

DELAY

;DECREMENT A

BEQ

BEGIN

;,TWO-WORD INTEGER

002076

;BRANCH IF WE HAVE
;WAITED TOO LONG

000765

LOOP2

;BRANCH AND CONTINUE
,TO WAIT FOR CTS

002100

032777

002106

001745

002110

032777

002116

001770

020000

177672

LOOP3:

BIT

#CTS,@RCSR

;IS CHANNEL STILL

BEQ

BEGIN

;BRANCH IF CTS NOT

BIT

#RDONE,@RCSR

;CHECK FOR RECEIVED

BEQ

LOOP3

;ESTABLISHED?

;PRESENT
000200

177662

;CHARACTER

002120
002126

;BRANCH IF NO

,CHARACTER RECEIVED
017767

032777

177656

000200

177666
177650

002134

001774

002136

016777

177652

177642

002144

032777

000200

177636

002152

001774

002154

016777

MOV
LOOP4:

BIT
BEQ

177634

LOOPS:

#XRDY @XCSR

LOOP4

MOV

BUFFER,@XBUF

BIT

#XRDY,@CXCSR

BEQ

177630

@RBUF BUFFER

MOV

LOOPS

BUFFER,@CXBUF

;READ RECEIVED

;CHARACTER INTO BUFFER
,CHECK FOR TRANSMITTER

;READY
;BRANCH IF NOT READY
;TRANSMIT CHARACTER
;TO REMOTE TERMINAL

;CHECK FOR CONSOLE
;,TRANSMITTER READY

;BRANCH IF NOT READY
;,TRANSMIT CHARACTER
;,TO CONSOLE

002162

000746

LOOP3

;BRANCH AND WAIT FOR

;NEXT CHARACTER

4-13

5_: o;_w&%;

}

PROGRAMMING

THE

BavoeQ

zoeobe
goeoee
20064
Jeoe6s

20113¢

Ldo2oa

pooLe?

B0Q204

BuoRRY

EXAMPLE

FLEXIBILITY

FOR

THE

DLV1i=F

PRUGRAMMING

. 860
JWORD

INPUT

}

RECEIVER

JWORD

340

velese

}

PRIORITY

CNORD

QUTPUT

]

TRANSMITTER VECTOR

o234y
nee2ew

JWORD

340

FLAGST

voovol
Bodoae

INUONES 1
QUTLONES2

eeoi102

INTENBS

177560

100

177560
DLADD
DLADD#+¢
DLADD+4

ABUFs

DLADD+e

» 51000

e2102@

pa1edd

]

Amkannmnn

INITIALIZE

a32767
veLT74

BETWEEN THME MAIN MODULE AND

}

THE

INTERRUPT

}
}

BIT
BIT

@
1

}

BIT POSITION OF THE

THE

MAIN

TU BE SET IN FLAGS TO
TELL
*MAIN® WHICH ROUTINE I8 DONE,

ENABLE

BIT

MODULE

WHICH

CONTROLS

THE

FLOW

DATAnwaw

MOV

PC, 8P

=(8P) ,=(SP)

SET UP THE STACK POINTER

MAKE

SURE

STARTS

BELOwW

US,

INSTRUCTIONS

INSTRY

177174
21264

PPeR1ve

177584

Gevene

177154

201932

CLR
MOV
BIlS

FLAGS

START

BINST,R}
PINTEND,@#¥XCSR

}
§

Rl I8 QUR OQUTPUT BYTE POINTER
SET INTERNUPT ENABLE IN XCSK

QZT
BEQ

BUOUTUUNE,PLAGS
1%

WAIT

OUTPUT

.
INSTEAD OF

CLEAN

FOR

QUTPUT

ROUTINE

FINISH

wWILL

SET

BIY

7
1 IN FLAGS WHEN DONE
WAITING WE COULD BE DOING OTHER PROCESSING MERE

RESTRT:

Je1032

2050867

177146

CLR

FLAGY

¢o1a3e
¢ajeae

RESTARY CLEAN

212721
BOS5067
ni2rae

ov134r
beuvibe

MOV

#POEM, N

]

CLR

INCUUNT

INITIALIZE

052737
052737

eueiva

177560

eev1a9

177564

gaies2
810260

INTERRUPY

IN BOTH THE

RCSR AND XCSR

STACK

CMP

}

reiede

ROUTINES,

} GIVE THE STACK SOME ROOM
THIS

STARTS

212708
gededn

}

eo1032

J USED AS THE COMMUNICATION LINK

RBUF
=
XCSR»

DLADD=
RCSRs

177560

177562
177564
177566

pesae7
glevey
252737

PRIORITY

STaARY

JMP

}

eaieeq
221224
Rei010
go10e14
poleee
o102

VECTOR

+ 8200
BuvsST4

}

201000

INTERRUPTS

veo3de

}

gaioee

SHOWING

WITH

PQ1535%

MoV

BIS
BIS

BLINE,N2

BINTENG,##RCSR
BINTENS,@8XCSR

7
)

FUR

THE

R2 FUR THE
SET

QUTPUT

BYTE

INPUT

COUNTER

POINTER

INPUT BYTE POINTER

INTERRUPT ENABLE
AND XCSR

RCSKR

11-5174

Figure 4-6

DLV11-F Programming Example
(Sheet 1 of 3)

4-15

ALL

WE CAN VO NOW
BOTH TRANSMITTER

epi074

02767
eR1374

eopoes

goL876

005067

17111922

177110

CMP

eeiiee

a12701
52767

L2RR
L
gaL114
ee11ee

22767
V31374

eai126

176450

Poveee

177862

HAVE

CLEAN
NOW

WILL

BIS

BINTEND,XCSR

LET

INTERRUPT

CMp

BQUTUONE ,FLAUS

BNE

aveoen

HALT
BR

LINE

HESTRT

END

/
;

LINE

ALL

THE

MAIN

MODULE

YET?

DONE

TYPED

MUST

PATIENT

AGAIN

#ataswntun

TH1IS

I
i
}
}

BEACH

eeeT2?

G21154

123404

221156

eases?
QuaTe7

Qwwese
rveess

110422
005267

QvAR4a

Ayvese

eev11d

THE

STORAGE
WHILE

INPUT

ROUTINE,

CHARACTER
1Y

WLUBAL

THE

THIS

PUINTER

INPUT

RUUTINE

INTERRUPT

THE

DRIVEN

DLVileF

THE

LOCATION

FOR

STREAM,
THE

PRIORITY

WHEN A CARNIAGE RETURN IS SEEN, IT 13 STORED AND
A LINE FEeD IS INSERTED AFTER IT, SINCE THIS IS
OUR SIGNAL TO STOP WE WILL CLEAR INTERRUPY
ENABLE ON THE RCSW AND SET INDONE IN FLAGS,

CRw
IL.F=

Muve

PERUUF ;R4

BiC
CMP
BEQ

R4, #LR

108

CMP

INCUUNT,n72,

DO WE MAVE 72 CHARACTERS ON THIS LIMNE

BLO

NO==SKIP

CLR
JSR

INCUUNT
”C;CNLf

RESET

COUNTER

INSERT

CRLF

MOVE

R4, (K2)+

INC

INCOUNT

i13

/
;
/

JCARRIAGE RETURN
i LINE FEED

#17700¢,R4

1358

Qoo4yy

RECEIVED

GENERATED,

01146

pel4ts

THE

INTERRUPT

177562

177600
00015

o2vae7

gai2e4
gegeie

AGAIN

115704
@4e724

eaL149
Co1144

goie0e

INPUTS

PoBP1S

ee11Te
gaLive

BOTH DONE?

388

eapuie

pal16e
Q01166

SPEED,

THE POUEM OUT,

BLINE,N]

ca1170
21174

IN AND

MOV

}
f
}
!

Ba116e

LINE
FLAGS

Fhamanhunn

go1132
2031134

PULL

CLR

eavT4y

eaiile

7 ARE THEY
IF NOT, WAILIT

paLla4

NOW

021535

bewivo

WORKING

#leUNt&OUTDUNE'FLkfia

BNE

eaiinm2

CHECKING,

28t

geiees
gelese

I8 WALIT AND KEEP
AND RECEIVER ARE

THIS CODE

WRAPS

SAVE CHARACTER IN REGISTER
STRIP OFF PARITY AND JUNK
IS IT A CARRIAGE RETURN
IF 80, WERE DONE

AROUND

CHARACTER
COUNT
EXIT

<«CRLF>»

INSERTION

INTO LINE

AFTER RECEIVING A CARRIAGE RETURN

1091

oo4Te7

10sa1e
va2767
52767t

goie2e
gpi22e

poaaqoe

peieeea
aei22e
pai2ee
po1e3e

112722
112722
eeo297

Bep1234

eo0R29

coveee
genioe
vvooe!l

JSR
CLRB
BIC
BIsS

176346
178764

PC,CRLF

FINISH

LINE

(R2)

APPEND

NULL

#INTENB,RCYR

# INOUNE,FLAGS

SIGNAL

MURE

BYTE"

INTERRUPTS

DONE

11398
RT1

EXIT

CRLF?3

geeels
eovnie

Move

BCRy(Rg)

MOove

BLF
) (KHe)+

RTS

INCOUNT
O

CARRIAGE

RETURN

LINE FEED

RETURN

CHARACTERS

PER

LINE

COUNT

11-5175

Figure 4-6

DLVI11-F Programming Example
(Sheet 2 of 3)

4-16

OUTPUTS

THES IS

Yew

ge§23e

201236
paL242
goi24y

112137
105711}

201246
rei12se

242737
Us2707

ai1aee
001262

poQeRe

177566
eevlive
oovane

NULL BYTE

TSTHB
BNE

177564
176722

201370
921376

021406

Ba1414
na1422

goi43e
621436
o144}
1446

201454
BR1462
221470
Pa14ve
021501
po1506
201514
291522
€o1530
091535

127

042511
52105
205015
219
deay sy
gaviat
242514
vvesSae
249
2de106

253440
P44ste
veu1e3
206454
191
242526
waasie
42510
us4s2e
eees24

240
040514
251501
paou1as
eeTi17
229
B2l

THE

TEaanuvxuN

A A

042520

V44440

v4rs3y

es11es

ea7T111
ea4s04

22eies

043516

esS2111

Q20112

251125
oo

02T116

240503
gueser

vas4le
R40sSle
A44sS14

R4s240Q

eS1122
251040

esiiet
2eaieqd
52124
246501

"R Y
nS523111
v4eses
251504
naesed

Q4p44e

garield

253517

012
g4cile

g54%2¢e

p4asee

vewniad
2535440
ele
g44124d
Vu1ils
A51440
p4ars24

2250215

INST?S

POEM3

eeelel
Q423503
2534490

Q42440

LINE

] NEXT

BYTE

NULL?

}

EXIT

AND

;

BOUTUOUNE,FLAGS

UUT!UT«

azfiumg.

PINTENG,PRXCSR

YflhNQMIT YNE CHlflACTEW
NO==

WAIY

NO MURE INTERRUPTS

}OEXIY

R R

INSTRUCTIONS, PUEM,

ki :i 2 3222

AND INPUT LINE.

~ +ASCI1

JTYPE

- «ASCIZ

/WITH
A CARRIAGE RETURN,/<CR><LF>

YUUR LINE

«ASCII

CCR>CLF>/MARY HAD

«ASCII

+sASCILI

PS3440

]

RTY

4221914

AT A PRIORITY OF

TRANSMITTER
IS READY

&Rl3*;00M$U¢

} ASCII STORAGE AREA:
254524
eevtle
R40040
garyas

ROUTINE.

(R1)

BIC
BlS

go1264
201272
201300
p21308
291314
001315
201322
2e133on
201336
081344
9e1347
021354
201362

UUTPUT

INTERNUPT DRIVEN,

*QUTPUT? RUNN

HQVB

geigee

THE

IT ALSO IS

THIS WOUTINE
I8 CALLED WMEN THE
TO VUTPUT ANOTHER CHARACTER,
Rl IS UUR GLUBAL PUINTER TO YHE

ENDING

A LITTLE LAMB/<CR><|F>

118 PLEECE WAS WMITE AS SNOW,/<CR><LF>

~/ANU

EVERY

WHERE

THAT

MARY

WENT/<CR><LF>

052uvde
P4051s
@4710%

veuiey
v53440

«ASCIZ

THE

LAMB

WAS

SURE

TO GO,/7<CR>»<|
P>

BS1125

v43lda0
11

LINE?

#BYTE ¥ §

STURAGE FOR INPUT LINE STARTS HERE

«END
11-5176

Figure 4-6 DLVI11-F Programming Example
(Sheet 3 of 3)

4-17

4.6

PROGRAMMING NOTES

Several programming considerations are presented below. Additional information is available from
program listings and current software manuals.
Character Format - Figure 4-7 shows the serial character format. Note that when less than
eight data bits are used, the character must be right-justified to the least significant bit. The

character format pcrtams to both the receiver and the transmitter.

Mamtenance Mode - The maintenance modeis selected by setting the MAINT bit (bit 02) in
the XCSR. In this mode, the interface disables the normal input to the receiver and replaces
it with the output of the transmitter. The programmer can then load various bits into the
transmitter and read them back from the receiver to verify propcr operatmn of the DLVl 1-E
and DLVI 1-F logic cxrcmts

Clearing Interrupt Enable Bits
- Before executing an instruction that will clear the XCSR or
RCSR interrupt enable bits, the processor should be set to its highest priority (PS bit 7 = 0).
This will prevent the processor from recognizing an XCSR or RCSR interrupt request that
occurs during instruction execution and then erroneously acknowledging that request after
the instruction has cleared it. If the computer were to acknowledge the interrupt request
after the interrupt enable bit has been cleared, it could resultin a bus timeout error when the
processor attempts to inputa vector from the device.

Programmable Baud Rate— The baud rate is programmed by loading the desired bits into
the high byte of the XCSR and setting bit 11. An cxamplc of a program step that does thisis:

MOVB #130,XCSR+1 ;300 BAUD BIT11 ENABLE PROGRAMMABLE

CINEb!

le
T

8 DATA BITS

e
oot
OR2_..4
BITS

A
|
—— STATE
OF LINE-

l JO”T“MTM"T-MT”‘T T “0‘; STOP I,STOP| )
10t302103304|05l061
START

—|

k—cma BIT TtMEwQNE/aAUD RATE

g’?ART Bfl" (5F'
NEW

CHARACTER

f1~-4968

Figure 4-7

Serial Data Format

4-18

CHAPTER 5§
DETAILED TECHNICAL DESCRIPTION

5.1 GENERAL
This chapter describes,
on a detailed functional level, each of the 12 circuits discussed in Chapter 2.
For a description of the major LSI chips, refer to Appendix A. For circuit schematics, refer to DLV11-

E Asynchronous Line Interface, Circuit Schematics (DIGITAL part number D-CS-M8017-0-1) or to
DLV]1-F Asynchronous Line Interface, Circuit Schematics (DIGITAL part number D-CS-M8028-0-1).
The functional areas described in this chapter are illustrated individually. It may be helpful, however,
to refer back to Figure 2-3 for a general overview.

5.2

BUS INTERFACE

Four DCO0O0S5 transceiver chips perform the bus interface functions. The chips receive from and transmit to both the computer’s Bussed Address/Data Lines (BDALs) and the module’s three-state bus
data lines (DATSs). The chips decode the module’s address from the LSI-11 bus and place interrupt
vectors on the LSI-11 bus.

5.2.1 Address Decoding
The computer addresses the module for both input and output data transfers. A data transferoccursin
two stages: address time and data time. (These are described furtherin Paragraph 5.3,1/0 Control
Logic.) During address time the computer places the address on bus lines BDALOO L through
BADLI15 L and asserts the memory bank 7 select signal (BBS7 L). This signal indicates that the

address is in the 28-32K range of addressing space, and enables the DCO005 transceiver chips to decode
the address. The circuit performs a logical inversion on the entire address word and places it on the
three-state bus. However, it decodes only bits 03 through 12 (Figure 5-1). Bits 00 through 02 pertain to
device register selection, and are routed to the 1/O control logic for decoding. Bits 13 through 15
pertain to the selection of addressing space. Their states are already indicated by BBS7 L. Bits 03
through 12 contain the address of the specific DLV11-E or DLV11-F being addressed. The bus inter-

face’s address decoding circuitry compares the states of bits 03 through 12 with the conditions set by
addressjumpers A3 through AIZ If a matchis decoded, the circuit asserts MATCH H to enable the
I /O control logic.

Durmg data tlmc, the transceivers transfer data from the LSI-11 bus lines to the three-state bus lines if
the operation is an output data transfer. If the operation is an input data transfer, the I/O control logic
asserts the *“‘in word” signal (INWD L), switching the transceivers to theiroppositestate, in which thcy \
transfer data from the three-state bus to the LSI-11 bus.
|
|
|
5.2.2

Vector Addressmg

The bus interface circuit can place one of two vector addresses on the BDAL lmes when the mterrupt

function is enabled by the program. Which vector is placed on the bus lines
is determined by the
interrupt logic. Bit 02 of the vector word (Figure 5-2) is controlled by VECRQSTB H from the interrupt logic. This bitis in a TRUE state for a transmitter mterrupt andis negated for a receiver interrupt.
Bits 03-08 can be selected by the user by removing or msertmg vector jumpers V3 thmugh V8. The
remaining bits are all zeros.

5-1

BDAL
BITS

=1/

=1 (L)

N
-¢

=
<

SR U

.8
<t

o
<

®
-§

~
<

0
<L

||
)

—~

ADDRESS JUMPERS:

=0
INSTALLED
REMOVED

= RECEIVER
= TRANSMITTER

0 = CSR

}

1 = DATA BUFFER

0 = LOW BYTE
1 = HIGH BYTE

RANGE = 160000g ~ 177776
11~ 4914

Figure 5-1

BDAL

BITS

DLVI11-E and DLVI11-F Addresses

'SELECTED BY USER. I

ASSERTED BY INTERRUPT 2
LOGIC CIRCUIT .

i l
>

VECTOR JUMPERS:
INSTALLED=0

REMOVED=1

l.. O =RECEIVER

’

1 = TRANSMITTER

CONTROLLED BY INTERRUPT
LOGIC CIRCUIT.
RANGE=0~-7748
1-4912

Figure 5-2

DLVI11-E and DLV11-F Interrupt Vectors

To place a vector on the bus lines, the interrupt logic asserts VECTOR H. VECTOR H enables those
bits whose corresponding vector jumpers have been installed. This action does not require BBS7 L or
INWD L.

5.3

1/0 CONTROL LOGIC

The 1/0 control logic monitors LSI-11 bus control signals, decodes the device address from the last
three bits of the address word, and controls the flow of data in the module. The major element in the
1/0 control logic is a DC004 protocol chip. This chip decodes DAT00 H through DAT02 H, monitors
VECTOR H from the interrupt logic and MATCH H from the bus interface, and responds to the
following LSI-11 bus control lines:
‘BSYNCL
BWTBT L
BDINL
BDOUTL

Bussed Synchronize
Bussed Write Byte
Bussed Data In
Bussed Data Out
5-2

The chip controls four register select lines for enabling the device registers (Table 5-1). It also generates
OUTHB L and OUTLB L signals to control which byte of a register is loaded. The chip produces the
“in word” signal (INWD L) to control the direction of data flow through the bus interface transceivers. It also generates a reply (BRPLY L) to the LSI-11 bus.

DATO2 H
Low
Low
High
High
5.3.1

Table 5-1

|
DATO01H

Low
High
Low
'High

Select Line
Asserted
SELOL
SEL2L
SEL4L
SEL6 L

RCSR
RBUF
XCSR
XBUF

Input Operation

When the LSI-11 program reads data in from the DLV11-E or DLVll F to the computer (DATI bus
cycle), the input data transfer pmceeds as follows:
1.

The program places the devnce address on LSI-11 bus lines BDALOO L thmugh BDALISL,
and asserts BBS7 L (Figures 5-3 and 5-4). BWTBT L is negated at this time because all input
transfers are full words rather than bytes.

BBS7 L enables the bus interface logic to decode the address. The circuit decodes the address
and sends MATCH H to the I/O control logic. It also inverts the address word and places it
on three-state bus lines DAT00 H through DAT15 H. DAT00 H thmugh DATO02 H are
applied to the I/O control logic.

The computer asserts BSYNC L. The leading edge of BSYNC L latches the states of
MATCH H and DAT00 H through DATO02 H into the pmmml chip of the 1/O control
logic. The chip decodes DATO00 H through DATO2 H to recognize the address of the device
register, and then asserts the appropriate rchswr select line, It asserts SEL2 L, for example,
if the program is addressing the RBUF. The register select mgnal conditions a gate that will
later be enabled for the data transfer.

The computer next removes the address from the LSI-11 bus lines, negates BBS7 L, and
asserts BDIN L. BDIN L is gated with the register select lines. This enables the selected
register to place its contents on the three-state bus. BDIN L is also routed to the protocol
chip, which asserts INWD L. INWD L causes the bus interface transceivers to transfer the
data from the module’s three-state bus to the LSI-11 bus. The chip waits about 150 ns for the
data to stabilize on the three-state bus lines and then asserts INWD L and BRPLY L.
BRPLY L signals the computer that the data is on the bus.

The 1/0 control logic responds to the negation of BDIN L by negating BRPLY L.

The computer terminates the bus cycle by negating BSYNC L.

The computer reads in the data and then negates BDIN L.

In the absence of a TRUE condition on BSYNC L, the protocol chip releases the register
select and INWD L signals. The bus interface reverts to its normal condition of receiving
from the LSI-11 bus and transmitting onto the three-state bus.

5-3

BUS

INTERFACE DCOOS

BDALOO
15 L

THREE -STATE

BUS

DATOO-15H

BUS

TRANS CEIVERS

BBS7 L
BUS

»|

ADDRESS
DECODER

Y
E;:S'

LST-14

RCSR

RBUF
:

XCSR

,
|

|
]

XBUF

—

BSYNC L |

swreT L |
BOIN L

BOOUT

|
|

MATCH H

|INWD L

OUTHBL

COUTLBL

—

BRPLY L

- PROTOCOL CHIP DCO04

|'seL oL

| |
|

GSEL2 L
L SEL 4 L

HSEL 6 L

11~ 4913

Figure 5-3

1/0 Control Logic, Block Diagram

R/T DAL

]

R SYNC
¥

CTDATA

[*—125nsMAX.

—s

[+—100ns MAX

@ 5ns MIN
— |=t

gl 780 |
MIN

| GONSMAX g 150ns MIN— fi’m
ey

DIN

\ 65ns |

235ns MAX |

j&- 150ns
MIN -»

N\MAX

~
T

300 ns MIN

RPLY

1ans

MIN
ns

-»

R WTBT

25ns MIN

(4)

NOTES:

(4)

I. Timing shown ot Master and Slave Device
Bus Driver inputs and Bus Receiver Qutputs.

2. Signal name prefixes are defined below:
|

T = Bus Driver Input

R= (Bus Ram&wr Qutput

)

3. Bus Driver Qutput and Bus Receimmnput
signal names includeo "B" prefix.

4. Don't care condition.

11-4914

Figure 5-4

Data Input Timing

5.3.2 Output Operation
The DLVI11-E and DLV11-F can accept data from the computer in either bytes or words. To write a
word out to the interface module, the computer performs a DATO bus cycle; for a byte, a DATOB bus
cycle. An output data transfer proceeds as follows:

The program places the device address on LSI-11 bus lines BDALOO L through BDALI1S L,
and asserts BBS7 L (Figure 5-5). BWTBT L is asserted at this time. (During address time,
BWTRBT L is negated for an input operation and asserted for an output operation.) BBS7 L
enables the bus interface to decode the address and send MATCH H to the I/O control
logic. The bus interface also applies DATO00 H through DATO02 H to the I/O control logic.

“'\I‘hc computer asserts BSYNC L. The leading edge of BSYNC L latches the states of

DAL

MATCH H and DATO00 H through DATO02 H into the protocol chlp The chlp decodes the
register address and asserts the appropriate select line.

R ADDR

(4)

4—25ns MIN

R SYNC

R DATA

X
‘ L——25n5MIN
‘

//
MIN

M IN
Ons MAX
MINTM 200ns
140ns

25ns _y,

100 ns MIN
j#—

—=>{ 150nsMIN

——01 75 ns MIN

R BS7

(4)

R WTBT

(4)

ASSERTION = BYTE

L—— 25ns MIN

MIN

I——— 300ns MIN

—{45ns MAX

150 ns M N —»

10nleN

|e—

25ns MIN

»a—

MIN

T RPLY

(4)

\
25ns

—p]

R DOUT

(4)

NOTES:

Timing shown at Master and Slave Device
Bus Driver Inputs and Bus Receiver Qutputs.

2. Signal name prefixes are defined below:
T =

R =

Bus Driver Input

Bus Receiver Qutput

3. Bus Driver Qutput and Bus Receiver Input

signal names include a "B" prefix .

4. Don't care condition.
11-49135

Figure 5-5

Data Output Timing

5-6

3.
|

The computer removes the address from BDALOO L through BDAL15 L and negates BBS7
L. If a byte is to be transferred out to the device register, BWTBT L remains asserted. If a
word is to be transferred, BWTBT L is negated. At this time the computer places data on the
LSI-11 bus lines and asserts BDOUT L. BDOUT L goes to the protocol chip and enables it
to decode the states of BWTBT L and DATO00 H. The chip uses these signals to determine
- the desired byte of the addressed register (Table 5-2). The device registers are configured for
output transfers unless switched otherwise by BDIN L. Therefore, BDOUT L is not gated
with the register select and byte lines.

Table 5-2

Byte Selection (Output Operations Only)

BWTBT L

DATOO H

High

Don’t Care

Low

High

Select Line

Byte

| Assefted

Selected

'OU‘TL;B Land

Both

OUTLB L

Low

OUTHBL

High

OUTHBL

About 150 ns after it receives BDOUT L, the protocol chip issues BRPLY L to the computer
to signal that the module is loading data.

The computer removes the data from its bus lines and*negaics BDOUT L.

The protocol chip responds to this by terminating BRPLY L.

The computer then terminates the bus cycle by negating BSYNC L and, if applicable,
BWTBT L.
|
|

When BSYNC L is negated, the protocol chip negates the register select and byte select lines.

5.3.3 Vector Operation
B
The I/O control logic has the additional function of asserting BRPLY L in response to VECTOR H
from the interrupt logic. This action is independent of BSYNC L and MATCH H. It is part of the
interrupt sequence and is discussed further in Paragraph 5.7.
|
5.4 CONTROL/STATUS REGISTERS
|
The RCSR and XCSR each consist of several types of flip-flop latches, rather than single devices.
Status bits from various circuits are placed in the registers and then, under the control of the I1/0
control logic, gated on to the three-state bus for transfer to the computer. Control bits from the
computer are loaded into the registers from the three-state bus. While in the registers, they direct the
operation of the modules.

5-7

'5.4.1 CSR Data Flow

RCSR operation differs between the DLViI1-E and DLV11- F onlyin thosc areas concerned with the
penphe:ral interface reqmrements (Figures 5-6 and 5-7). Some bits are set by the penpheral interface
circuit, receiver active circuit, and the RBUF, while others are set by the program via three-state bus
lines DATO00 H through DATO06 H. All RCSR bits except the DLV11-F’s Reader Run Enable bit may
be read by the program. Refer to Chapter 4 for a listing of how the bits are set and cleared.

DESTINATION

PERIPHERAL
INTERFACE
CIRCUIT

DATA SET

INTERRUPT

RCSR

SOURCE

" RING

DATi4 H

CLEAR
TO SEND

DAT13 H

CARRIER

DAT12 H

DETECT

RBUF

‘

DATO6 H —»
DATOS

H —#

DATO3 H —»

DATO2 H —{

DATO{ H —»

RECEIVER
DONE

RECEIVER

INTERRUPT
ENABLE

DATA SET
INTERRUPT
ENABLE

SECONDARY
TRANSMIT

REQUEST

TO SEND

DATIO H

RECEIVE

DATO7 H

be it

SECONDARY

& DAT1{1

INTERRUPT

LOGIC

RECEIVER
ACTIVE

RECEIVER
ACTIVE
CIRCUIT

DAT1S H

"PERIPHERAL
INTERFACE

CIRCUIT

DATA
TERMINAL

READY

11-4916

Figure 5-6

DLV11-E RCSR Data Flow

5-8

SOURCE

RECEIVER
ACTIVE
CIRCUIT

RCSR

RECEIVER
»
ACTIVE

RECEIVER

RBUF

DONE

ATO6 H—»|

DESTINATION

» DATH

» DATO7

RECEIVER

NET,\;EA?;&JEPT

INT

=
-

INTERRUPT
LOGIC

DATOO H —»

ENABLE

READER RUN

”

———’l y%xggng

PERIPHERAL

t1-4917

Figure 5-7

DLVI11-F RCSR Data Flow

XCSR operation is the same for both the DLV11-E and the DLV11-F (Figure 5-8). The bits for the
baud rate control circuit are write only bits. TRANSMITTER READY is a read only bit. The other

XCSR bits are both read and write bits.

SOURCE

XCSR

pat1s H —s
‘

PROGRAMMABLE _

BAUD RATE SELECT

DAT14 H =TM
Caris

PBR

ABR

PBR

o ECT 2
or

BAUD RATE

SELECT 1

CONTROL

PBR
SELECT O

DAT!{ H —»|

PROGRAMMABLE
BAUD RATE
ENABLE

TRANSMITTER

_ DAT12 H —»

DATO6 H —»

DATOZ H —+

DATOO H —#

READY

> DATO7

TRANSMITTER
|INTERRUPT

INTERRUPT

MAINTENANCE

BREAK

BREAK LOGIC

LOGIC

ENABLE

MODE

MODE LOGIC

DESTINATION

f1-4918

Figure 5-8

DLVI11-E and DLV11-F XCSR Data Flow

5-10

5.4.2 Input Operation
The contents of the RCSR and XCSR are read into the LSI-11 by an input data transfer (DATI). The
computer places the address of the register on the LSI-11 bus and then the bus interface and I /O

control logic decode the address. The I/O control logic generates register select signals that switch data
selectors to the desired source (Figure 5-9).

The select sign@als also enable the output of the data selectors and, if the RCSR is addressed, enable bus
drivers. The status information leaves the CSRs on the three-state bus. The bus interface circuit then
transfers the data to the LSI-11 bus.

DATA SELECTORS

7415257

TRANSMITTER

STATUS

BITS

o5 THREE
- STATE BUS

RECEIVER

STATUS

BITS

:>>

N\N\\M\k
aoi:#,,

/lk
DRIVERS:

I/0

CONTROL
LoGIC
|

ENABLE

11-4919

~ Figure 5-9 Contrdl/ Status Registers During DATI

5
|

5.4.3 Output Operation
~
|
|
The LSI-11 writes control bits out to the CSRs by an output data transfer (DATO or DATOB).
Normally the RCSR is loaded by a DATOB cycle because only the low byte contains control bits. (The
bits used in the high byte are all read only status bits.) The XCSR can be loaded by a DATOB cycle if it
is desired to load only the high byte (e.g., to change the baud rate), or only a low byte. The computer
uses a DATO cycle to transfer a full word to the XCSR.
When the computer addresses the desired register, the bus interface and I/O control logic circuits
decode the address. The I/O control logic generates register and byte selection signals that enable the
chips comprising the selected register (Figure 5-10). Flip- flops latch in control bits that are held in the
register, and data selectors route other bits to latches in the circuits which they control.

5-11

TRANSMITTER

CONTROL

LATCHES

;

» TRANSMITTER

CIRCUITS

THREE- STATE BUS

RECEIVER

CONTROL

LATCHES

» RECEIVER

CIRCUITS

AND BYTE
SELECT

1/0

LINES

CONTROL

LOGIC

11-4920

Figure 5-10

5.5

Control/Status Registers During DATO or DATOB

DATA BUFFERS

" Both transmitter and receiver data buffering functions are performed mainly by a single LSI chip. The
chip is a Universal Asynchronous Receiver/Transmitter (UART). The UART is a double-buffered,
full-duplex receiver/transmitter. The receiver section performs the RBUF function, accepting asynchronous serial binary characters, converting them to parallel format, and placing them on the threestate bus. The transmitter section performs the XBUF function, accepting parallel data from the threestate bus and converting it to a serial aysnchronous output. The receiver strips START, STOP, and
parity bits off the data coming in from the peripheral device. The transmitter appends START, STOP,
and parity bits to the data being transmitted out to the peripheral device. Jumper control of the STOP
and parity bits, and the number of data bits, is defined in Chapter 3.

The UART is driven by a clock signal (or two clock signals, for split speed operation) from the baud
rate control circuit. The clock speed is 16 times the baud rate of the UART. The UART transmitter

internally synchronizes the START bit with the clock input to ensure a full 16-element (clock periods)
START bit independent of the time of data loading. The receiver rejects any received START bit that
lasts less than one-half of a bit time.

5-12

5.5.1
Receiver Operation
Serial data coming in from the peripheral device is converted to TTL levels by the peripheral interface
and is applied to the UART’s receiver section (Figure 5-11). The UART samples the serial input data
line at 16 times the data bit rate. The line is in a continuous marking state when idle. When
a START
bit arrives, the UART detects the mark-to-space transition and begins loading the received character
into the receiver shift register. The character is shifted to have its least significant bit in the lowest
bit
position of the register. If jumpered for checking parity, the UART checks the total of the received
data bits plus the parity bit. (It checks for an even total if even parity has been selected, and an
odd
total if odd parity has been selected.) A parity error will result in a flag bit (P ERR) being set (Figure
512).
|
|

DATA FORMAT
JUMPERS

BUS
INTERFACE

N
UART

THREE-STATE
Qe

coNToL |

DATA BITS

ey X CLK

CONTROL |R CLK

BAUD RATE

,_l.____!!...

CONTROL

RDY

——

]

IseriaL

PARALLEL-TO-SERIAL

TRANSMITTER SHIFT REGISTER

TORNMASAG.

OMSMMSRGSE

XCSR

BIT 7

—

Jouteut PERIPHERAL

INTERFACE

TRANSMITTER
MEGCRNER

SSOSGIER

NREN.

SMSRGN

OWSSSGE

SSRRMGN

enee

RECEIVER
»

SERIAL

PERIPHERAL | INPUT
INTERFACE

‘,

SERIAL -TO-PARALLEL

RECEIVER SHIFT REGISTER

R DONE

RCSR

BIT 7

M CONTROL
—

BREAK

F ERR
|
5

HOLDING | STATUS
REGISTER
BITS

I/0
cogrggL
LOG

DETECTION

LOGIC

|
DATA BITS

|
,

rV
DATA
SELECTOR

N/
THREE -STATE
|BUS DRIVERS

—

THREE-STATE BUS

BUS

INTERFACE

11-4921

Figure 5-11

UART Signal Flow

5-13

PERIPHERAL|
INTERFACE

DATA FORMAT
- JUMPERS.

|
.
RECEIVED DATA

THREE - STATE

STATUS BITS

BUS LINES

af i

>
n=

OR_ERR

ERR
'

ERR

ERROR

DATIS

OVERRUN
ERROR

DAT14

L
-

FRAMING
ERROR

DATI3

L
o

PARITY
ERROR

DAT12

.
"

DATO7

ERR

RDONE

BIT 7

RECEIVED
DATA BITS

UART

(RECEIVER SECTION)

)

__I RCSR

RDS8

RD7

DATO6

RD6

DATOS

RD5

DATO4

RD4

DATO3

RD3

DATO2

RD2

DATO!

RD!

DATOO

1
REGISTER SELECT LINES

O
e

BAUD
RATE
CONTROL

11—~ 4922

Figure 5-12

DLVI11-E and DLVI11-F RBUF Data Flow

5-14

The UART checks the STOP bit to see if it is marking. If the line is spacing when the UART checks for
a STOP bit, the UART sets the framing error flag (FR ERR).
When the UART receives the center of the first STOP bit, it transfers the data in parallel from the
receiver shift register to the holding register. At this time, the data and error bits become available for
gating on to the three-state bus, and the UART asserts the receiver done (RDONE H) signal. This sets
the RECEIVER DONE status bit in the RCSR.

If the receiver interrupt enable bit is set, RDONE H initiates an interrupt request. The LSI-11 then has
a full character period to service the interrupt before the next character moves into the holding register.
During this time the next character is being assembled in the receiver shift register. After an LSI-11
DATI sequence has taken the data, the I/O control logic resets the receiver done status bit. If the LSI11 program does not take the data before the next character enters the holding register, RDONE H
does not get reset. In this case, the UART sets the data overrun flag (OR ERR). This bit goes with the
next received data word to indicate that the old data was lost.
Any of the three error conditions (Overrun Error, Framing Error, or Parity Error) sets an end check
error flag (ERR) as well as its own flag. These error bits do not initiate an interrupt request, but they
are available in the high byte of the RBUF for the programmer’s use.
5.5.2 Transmit Operation
The XBUF consists of two registers and their controlling logic, all of which are contained in the
UART chip. A holding register stores the parallel data taken off the three-state bus, and then transfers
it in parallel to the transmitter shift register. Next, the data is shifted out serially. The format of the
character being transmitted is controlled by the data format jumpers.

During idle time the UART transmits a continuous marking signal and holds the transmitter ready
status bit (XMIT RDY) asserted in the XCSR. XMIT RDY initiates a transmitter interrupt request if
the transmitter interrupt enable bit is set in the XCSR. If the interrupt function is not enabled, the
UART transmitter remains idle until the program requires it.
When the program has data to transmit to a peripheral device, it uses a DATO or DATOB sequence to
address the XBUF and place the data on the bus lines. The bus interface moves the data from BDALQO
L through BDALO7 L to DAT00 H through DATO07 H. The 1/O control logic enables the XBUF to
load the data into its holding register (Figure 5-11). When the data enters the holding register, the
UART negates XMIT RDY. The UART then transfers the data in parallel from the holding register
to the transmitter shift register and reasserts XMIT RDY. In the transmitter shift register, the UART
attaches the selected START, STOP, and Parity bits. The assembled character is then shifted serially
out of the XBUF to the peripheral interface circuitry (Figure 5-13).

- The time between the leading edge of the register select signal from the I/O control logic and the
corresponding mark-to-space transition of the serial output line is within one clock cycle (1/16 of a bit
time) if the transmitter has been idle.

XMIT RDY is asserted as soon as a character is transferred from the holding register to the transmitter shift register, thereby indicating that the holding register is empty. The next character may be
loaded immediately, even while the first character is still being serially shifted out of the transmitter
shift register. Thus, if the holding register and transmitter shift register are both empty, the LSI-11 can
parallel-transfer a two-character pair into the XBUF in less time than it takes for a single character to
be serially transmitted to the peripheral device. This advantage of double-buffering applies only to the
first two characters; that is, if a series of characters is being transmitted each character after the second
must wait a serial character period for the XBUF to become ready again. The actual time depends on
the baud rate.

5-15

DATA

" BAUD

FORMAT
RATE |
conTroL| | JUMPERS

TRANSMIT DATA BITS

ouf —|a fi

O
o

DATO5 H —»

DATO3 H —s| (TRANSMITTER SECTION)

|
XMIT

DATO2 H —»
DATO1 H

PERIPHERAL

TM INTERFACE

DATOG H —

RDY

XCSR
7
BIT

DATOO H —»
3

CONTROL
LOGIC
11-4823

Figure 5-13 DLVII-E and DLV11-F XBUF Data Flow

5.6

RECEIVER ACTIVE CIRCUIT

RBUF is receiving a character of
The receiver active circuit produces a status bit to indicate that the of
the received data character and
bit
ART
ST
the
by
set
is
,
data. This status bit, RECEIVER ACTIVE
UART.
cleared by the receiver done (RDONE H) signal from the

H from the peripheral interface holds
During the period between received data characters, SI MARK
a START bit is received, SI MARK
the receiver clock counter in the cleared state (Figure 5-14). When
counter begins to count receiver
H changes state and releases the CLEAR line to the counter. The
H pulse is 1/16th of a bit time. The
clock pulses from the baud rate control circuit. Each RCLK START
then asserts RBUSY H.
counter counts to eight, which places it in the center of thethe programbit,
RECEIVER ACTIVE. It
RBUSY H is routed to the RCSR, where it can be read in by clearing theascounter
. When the RBUF
is also used to stop the counter and to inhibit SIMARK H from E H. RDONE H clears
the counter,
has finished receiving the character, the UART asserts RDON initial condition. Thus, RECEI
VER
thereby negating RBUSY H and returning the circuit to its
H.
DONE
R
of
edge
ACTIVE is set during the time from the center of the START bit to the leading
INTERRUPT LOGIC

t logic are handled by a single DC003
Both transmitter and receiver interrupt functions of the interrup
t logic has a receiver interrupt
interrupt chip. This chip is described in Appendix A. The interrup
5-15 shows the signal flow
Figure
y.
channel, a transmitter interrupt channel, and control circuitr
|

5.7

associated with the interrupt chip.

5-16

BAUD RATE

CONTROL

BITH

R _BUSY H
COUNTER

COUNT ENABLE

PERIPHERAL|
INTERFACE

~ |inmigi
GATE

SI MARK H

| CLEAR
_RECEIVER ACTIVE CIRCUIT|

;

MAINT
MODE

paTa

ISELECTOR

RCSR

BIT 7
g
W

r -l R DONE H

:l RBUF | " THREE
- STATE BUS >

RCVR

DONE

) S

mJ
it-4924

Figure 5-14

Receiver Active Circuit

5.7.1 DLVI11-E Receiver Interrupts
In the DLV1I1-E, a receiver interrupt sequence is started by either the UART or the peripheral interface circuitry. Both cases require that the appropriate enabling bit be set in the RCSR. When the
computer program sets RECEIVER INTERRUPT ENABLE (bit 06) in the RCSR, an interrupt can
be caused by RDONE H from the UART. The UART asserts RDONE H when the RBUF has
received and assembled a character of data. When the program sets DATA SET INTERRUPT
ENABLE (bit 05) in the RCSR, an interrupt can be initiated by DATA SET INTERRUPT from the
peripheral interface circuit. The peripheral interface sets DATA SET INTERRUPT when it receives
control signals from a data set. When either pair of conditions is satisfied, the receiver channel will be
enabled to request to interrupt the program. When the interrupt is acknowledged (discussedin Paragraph 5.7.4), the interrupt chip asserts VECTOR H. This signal causes the assertion of the vector
address bits that correspond to the vector jumpers which the user has inserted. The bus interface circuit
places the bits set by jumpers V3 through V8 onto LSI-11 bus lines BDALO3 L through BADLOS L.
All other BDAL’s are negated at this time. When the computer locates the service routine, it may
check the status bitsin the RCSR to determine what condition initiated the interrupt. Refer to Paragraphs 4.3 and 4.6 for notes regarding simultaneous receiver and data set interrupt conditions.

5-17

" PART OF

RCSR

INTERRUPT LOGIC-'

PERIPHERAL] DSET INTH _| DATA
SET | BIT 15'Y
INT *
R DONE H

UART

XMIT

C DATOS H

DSET INT|BIT 5 '

TH‘QQE*- )
STATE

)

DATO6 H

DONE

ENB

ENB*®

] co%gm. _
LOGIC

|
"] INT ENB
PART OF

XCSR

BIAKI L

9D | BIAKO L

BDAL 12 L

BDAL11 L

BDALIOL

JUMPERS

(V8)

XMTR

|, | BDALOS
L

|BDALOSB L

| >

1o
-

|BDALO7L

(V5)

L
BDALOS

o(v4)o

BDALO4
L

' o

BDAL 13 L

| _(v6)__|35|BoALOSL | %

T
' cowmm.r

'-J

BDAL 14 L g

| Aooress

< BIRQ

— —_—
BINIT L
H

BIT 6

BDAL1S L

'
!

BRPLY 2

|BIT 7 |

XMIT

» XMIT RODY

|BIT7 ,

o RCVR INT | BIT 6 |

BUS

RCVR

ROY H

Co;gO?Efl

INTERFACE

CIRCU!TSI

|11

RCVR

VECTOR H
VEC RQST B H

(V3)

BDALO3 L

' .

BDALO1 L
BDALOO L

l
l

g
e
>

—

* DATA SET INT AND DSET INT ENB
APPLY TO DLVI1-E ONLY.

11-4925

Figure 5-15

5..7 2

Interrupt Vector Signal Flow

DLV11~FRecenver Interrupts

The DLV11-F interrupt vector flowis the same as that of the DLVI1-E, with the exception that it has
no DATA SET INTERRUPT or DATA SET INTERRUPT ENABLE bits. The module does not

support data set control, and therefore produces a receiver interrupt only for servicing the RBUF.

5-18

5.7.3 Transmitter Interrupts
|
The DLVI11-E and DLV11-F function alike for transmitter interrupts. The interrupt logic generates a
transmitter interrupt when the program sets TRANSMITTER INTERRUPT ENABLE (bit 06) in the
- XCSR and the UART asserts XMIT RDY H. The UART asserts XMIT RDY H when the XBUF is
empty and ready for more data from the computer. When XMIT RDY H and TRANSMITTER
INTERRUPT ENABLE are both TRUE, the transmitter channel of the interrupt chip is enabled to
request interrupt service. (Although these two signals are functionally bits 06 and 07 of the XCSR, they
are physically located in the interrupt chip.) After the computer acknowledges the interrupt logic’s
interrupt request, the circuit asserts both VECTOR H and VECRQSTB H. VECTOR H is applied to
vector address jumpers V3 through V8, the same as for a receiver interrupt vector. In this case, how-

ever, VECRQSTB H causes the bus interface to assert BDALO2 L, as well as the other selected bits on

BDALO3 L through BDALO8 L. This results in the vector addressing of the transmitter interrupt
service routine.
5.7.4 Interrupt Transactions
- Either type of interrupt begins with the interrupt logic asserting BIRQ L, the interrupt request line.
This is followed by an interchange of control signals and the vector address being placed on the LSI-11
bus lines. The sequence proceeds as follows:
1.

The request is initiated by the interrupt logic asserting BIRQ L (Figure 5-16).
|

INTERRUPT LATENCY
MINUS SERVICE TIME

@ns MIN

150ns MAX [*®

T IRQ
——-.‘

Rom

150
ns MIN.

ja—

40ns

T RPLY

" max [

—.!\

-’l 125 ns MAX. r-——

DAL

“

100 ns
MAX.

VECTOR

R SYNC

/\ oTM
u

R IAKI

1 30
ns MIN
150
ns MAX

195ns MIN

320ns MAX

(UNASSERTED)

BS7

(UNASSERTED)

{5ns MIN

65ns MAX

NOTES:
1.

Timing shown at Requesting Device Bus Driver Inputs and Bus Receiver Qutputs .

2. Signal Name Prefixes are defined below:
b

T = Bus Driver Input

R = Bus Receiver Qutput

3. Bus Driver Output and Bus Receiver Input signal names include a "B" prefix.
11-4926

Figure 5-16

Interrupt Timing
5-19

The LSI-11 responds to BIRQ L by asserting BDIN L and then BIAKI L.

BIAKI L is passed down the priority chain until it reaches the section of the interrupt logic

that initiated the request. When the circuit receives both BDIN L and BIAKI L, it asserts
VECTOR H (and also VECRQSTB H, if a transmitter interrupt) and negates BIRQ L.

VECTOR H causes the I/O control logic to issue BRPLY L to the ,computer. VECTOR H

(and VECRQSTB H, if applicable) also causes the bus interface to place the vector on the
LSI-11 bus lines.

The computer reads in the interrupt vector and then, as a result of receiving BRPLY L,

The interrupt logic negates VECTOR H (and VECRQSTB H, if applicable). |

The negation of VECTOR H causes the 1/O control logic
to negate BRPLY L, and the bus

negates BDIN L. Shortly after this it also negates BIAKI L.

interface to remove the vector from the LSI-11 bus lines.

~ An interrupt transaction does not require MATCH H, BSYNCL, BBS7L, or INWD L The interrupt
logic overrides the module’s normal I/O protocol. When the computer is initialized, the interrupt logic
is cleared by BINIT L.

5.8

BAUD RATE CONTROL

The baud rate control circuit establishes the speeds at which the RBUF and XBUF operate. The
circuit consists of two sets of wire wrap jumpers, gating circuitry, an oscillator, and a 5016 dual baud
rate generator. The 5016 chip divides the oscillator frequency down to the frequency selected by the
jumpers or the program. In the split speed mode of operation, it produces two separate clock frequencies: one for transmit and one for receive. The circuit routes either these clocks or an external clock to
the UART to control the baud rate(s) at which the module operates.

Also included in the baud rate control are gates that decode a selection of 110 baud. When this
condition is detected, the circuit asserts 110 BAUD H. This signal enables the UART to handle a data
format having two STOP bits (Figure 5-17).

5.8.1

Program Control

The 5016 chip has two sections, each of which is driven by a 5.0688 MHz clock from the oscillator. The
two sections of the chip each divide the 5.0688 MHz clock by a selectable amount. The selection for
section B of the chip is accomplished by jumpers TO through T3. The frequency in section A, however,
can be controlled by either jumpers RO through R3 or three-state bus lines DAT12 H through DATIS
H. The source of control for section A of the chip is selected by a data selector chip. This data selector
is functionally part of the high byte of the XCSR. It is addressed by a combination of the Programmable Baud Rate Enable bit (on DATI11 H) and register select lines from the I/O control logic. If
DATI11 H is asserted during a DATO output transaction, the data selector chip will route the logic
states of DAT12 H through DAT15 H to the dual baud rate Generator chip to program the frequency.
When DATI11 H is not asserted, the data selector chip will select jumpers RO through R3 to control the
dual baud rate generator.

When computer power is first switched on, the assertion of BDCOK L causes the data selector to select
jumpers RO through R3 as the source of the section A frequency control. From that time on the circuit
can choose either the jumpers or the XCSR bits, as determined by the state of the Programmable Baud
Rate Enable bit. A table of jumper combinations and their corresponding baud rates is presented in
Chapter 3.

5-20

BAUD RATE

DAT12 H
THROUGH

cc I

GENERATOR

DATIS H

CONN CLK

INPUT H

FOUR BIT

DATA SELECTOR

Bki

BL{

sEcTion |5y MSPAREB

(81)

Lock

CONTROL |

(C1)

RCLK H

MULTI
-

PLEXER
RECEIVE
JUMPERS

|_
S

TRANSMIT
JUMPERS

(PB)

BDCOK L

I/0
CONTROL
LOGIC

Bht |

DATI{ H

EXT TCLK H

GATING

5.0688 MH 2

0S¢

'HH l CONN CLK

UART

(C)

¥
F

(MT)®

(s)

TCLK H

MAINT H

L’J
DATA
FORMAT
JUMPERS

110 BAuD | 110 BAUD H

DECODE
11-4927

Figure 5-17

Baud Rate Control Signal Flow

5-21

5.8.2 Jumper Control
o
When the Programmable Baud Rate Enable bit is not set, section A of the 5016 chip is controlled by
jumpers RO through R3. This section is used to control the receiver baud rate during split speed
operation. During common speed operation, section A (and jumpers RO through R3) controls both
transmitter and receiver baud rates.

Jumpers TO through T3 always determine the output frequency of section B of the chip. During split
speed operation, this establishes the baud rate of the transmitter. During common speed operation,
jumpers TO through T3 and section B of the chip are not used. When the module is operating in its
maintenance mode and in split speed, TO through T3 and section B produce the clock for both the
RBUF and the XBUF.
5.8.3 External Control
External clock inputs can be introduced through either the backplane connector or the header connector. Pins BK1 and BL1 are connected together by a jumper (MSPAREB) at each module location
on the LSI-11 backplane. The output of section A is routed through this jumper.

The jumper can be cut and an external clock applied to backplane pin BL1. This clock will then drive
the receiver in split speed operation, or both the receiver and the transmitter in common speed
operation.
|
An external clock can be used for the transmitter in split speed operation by removing jumper S1 and
applying the external clock to backplane pin BH1. External clock frequencies must be 16 times the
desired baud rate.
|
|
|

The baud rate can be controlled by an external peripheral device via the cable to the module’s header
connector. When a TTL logic low enabling signal is applitd to J1 pin HH it causes the clock control
multiplexer to select the external clock on pin CC. When the enabling signal is negated the baud rate
reverts to its former configuration.
|
|
‘"
5.8.4 Clock Selection
|
|
The receiver and transmitter clock inputs to the RBUF and XBUF timing circuitry (in the UART) are ‘}
selected by two jumpers and a multiplexer. Normally the multiplexer selects the input from pin BL1 as
the receiver clock. The CONN CLK EN L signal, however, causes the multiplexer to select header

connector pin CC as the receiver clock. Additionally, during the maintenance mode only, MAINT H
causes the multiplexer to choose the transmitter clock as the source of the receiver clock in split speed
operation, and the receiver clock as the source of the transmitter clock in common speed operation
when jumper MT is installed.

During split speed operation, jumpers S and S1 are inserted and jumpers C and C1 are removed. This
routes the receiver clock to the RBUF section of the UART, and the transmitter clock to the XBUF
section. For common speed operation, jumpers S and S1 are removed and jumpers C and CI are
inserted. This routes the receiver clock to both the RBUF and XBUF sections of the UART.

Table 5-3 summarizes the possible connections discussed in this section.

5.9 BREAK LOGIC

‘

;

The break logic performs two functions: it causes a BREAK to be transmitted, and it determines the
action taken when a framing error or a BREAK is received.

5-23

Table 5-3

- Dual Baud Rate Generator

Common Speed

SplitSpeed

Transmitter Speed

Receiver Speed

~ Clock Source

UART Clock Sources

R0O-R3

RO-R3

T0-13

External Clock on Backplane

V
BL1

Split Speed

External Clock on
Header Connector

‘Common Speed Only

(Requires Enable on pin HH)

' 5.9.1

BL1
BHI1

BL1

Common Speed

Receive Operation

. During normal operation, the UART checks each received character for the proper number of STOP
" bits. It does this by testing for a marking condition at the appropriate time. If it finds a spacing
~ condition instead, it sets the framing error flag (FR ERR). The BREAK signal is a continuous spacing
~condition, and is interpreted by the UART as a data character that is missing its STOP bit(s). The
UART, therefore, responds to the BREAK signal by asserting FR ERR H (Figure 5-18). MAINT L
from the XCSR is gated with FR ERR H to inhibit the framing error signal (FE H) during the
H is applied to jumper B, and is inverted and applied to jumper H. If jumper B
maintenance mode.FE
is inserted and -B (or B) is removed, FE H will negate control line BDCOK H. BDCOK H indicates to

‘the LSI-11 that dc power is “OK.” When FE H negates this signal, it causes the computer to reload its
bootstrap.

B) is inserted, the computer will not “boot” on a framing
If jumpei'Bis removed and jumper -B (or
|

~error. |

If jumper H is inserted, FE H will negate control line BHALT L. This causes the computer to halt

when a framing error is received.
o

- CAUTION

interrupts the memory refresh cycle.

5.9.2

If the LSI-11 is using MOS memory, data may be
lost when BDCOK H is negated because this action
|

Transmit Operation

To transmit a BREAK signal the program sets the BREAK bit (bit 00) in the XCSR (Figure 5-19). The
output of the XCSR latch holding the BREAK bit is used to inhibit the serial data output of the
XBUF. This causes the peripheral interface circuitry to transmit a continuous spacing condition
(BREAK signal) on the serial communications line.

BREAK generation can be enabled by inserting jumper BG. This allows the state of DAT00 H
(BREAK bit) to control the BREAK inhibit gate. When the BREAK bit is set, BREAK(0) L is
clocked to a continuous FALSE condition, thus inhibiting the flow of serial data from the XBUF to
the peripheral interface.

5-24

BIT 2

MAINT L L
v

l >‘..J

(H),_BHALTL _

(B)

BDCOK H

FRERR

INHIBIT &t

__|GATE
FR ERR H

UART

e
—»

RBUF

DATA
SELECTOR

t—

~B (OLVI1-E)

——

B (DLVII-F)

)
Figure 5-18

»>BA{

11-4928

Break Logic Receive Signal Flow

DATOO H —»
XCSR

BIT O

(BG)

o—o—*

BREAK (0) L

E—

xguF FSERIAL OUTH l

‘

BREAK}__SO MARK H
GATE

PERIPHERAL

1 INTERFACE

1-4929

Figure 5-19

Break Logic Transmit Signal Flow

5.10 MAINTENANCE MODE LOGIC
|
|
|
In the maintenance mode, the DLV11-E and DLV11-F modules route their output data back to their
input (Figure 5-20). To accomplish this the computer program sets the MAINTENANCE bit in the

XCSR. The latch holding this bit has two outputs. One goes to the break logic to prevent the generation of framing error signals during operation in the maintenance mode. The other output is applied
to the maintenance mode data selector.
The data selector normally routes the incoming data from the
peripheral interface to the RBUF. In the maintenance mode, however, it switches its input to the
output of the XBUF. This action loops the serial data out of the XBUF back into the RBUF and
disconnects the peripheral interface’s received data. While in the maintenance mode, the serial output
of the XBUF continues to go to the peripheral interface and out to the peripheral device.

5-25

MAINTENANCE MODE
DATA SELECTOR

PERIPHERAL | SI MARKH_ |
INTERFACE

l
‘_/

SERIAL IN H |

]

BUF

|SOMARK H

i
|

)

PERIPHERAL
INTERFACE

MAINT H

DATO2 H —»]
XCSR
BIT 2

1/0
| REGISTER SELECT
cONTROL

MAINT L

LOGIC
BREAK
LOGIC
11-4930

5.11

Figure 5-20

Maintenance
Mode Logic

DLVI11-E PERIPHERAL INTERFACE

The DLV11-E provides data set control by producing and responding to EIA-compatible control
signals. EIA-level receivers in the peripheral interface circuit monitor the following control lines:
RING, CLEAR TO SEND, CARRIER, and SECONDARY RECEIVED DATA (Figure 5-21). Each
of these control lines is represented by a bit in the RCSR. The peripheral interface will set the DATA
SET INTERRUPT bit in the RCSR if RING changes state from a 0 to a 1, or if any of the three other
signals changes state from either a O to a 1 or a 1 to a 0. Thus, when the computer program has set
DSET INT ENB, a signal on any of the incoming EIA control lines can initiate a receiver interrupt.
When the interrupt is acknowledged, the program can check the RCSR to determine which signal
initiated it. The program can then respond by asserting the appropriate control bits in the RCSR. The
peripheral interface responds to a True condition on RCSR bits 1, 2, or 3 (DATA TERMINAL
'READY, REQUEST TO SEND, and SECONDARY TRANSMITTED DATA, respectively) by
transmitting a TRUE condition on the corresponding EIA control line. (If the data set has a FORCE
BUSY function, jumper FB should be inserted to drive this control line with the REQUEST TO
SEND bit.) The exchange of control signals allows a remote data set to establish a channel of communication with the LSI-11 through the use of a handshake.

A typical handshake sequence proceeds as follows: A remote data set calls the local data set. The local
data set sends a RING signal to the DLV11-E asynchronous line interface. The RING signal initiates a
receiver interrupt (assuming DSET INT ENB is set). The program reads the RCSR and determines
that the interrupt was caused by the RING signal. Then, through a service routine, it issues the DATA
TERMINAL READY and REQUEST TO SEND signals. These signals direct the local data set to
answer the remote data set by sending it a carrier signal. The remote data set acknowledges the carrier
signal by returning its own carrier signal. The local data set detects the remote data set’s carrier signal
and indicates this to the DLV11-E by asserting its CARRIER control line. This causes another
receiver interrupt. Upon recognizing the CARRIER-caused interrupt, the program can either receive
for this handshaking sequence are that the program use approor transmit data. The only prerequisites
set interrupt enable bit be set in the RCSR.
data
the
that
and
routines
priate service

5-26

DLVUI-E

BIT #

TTL/EIA
LEVEL

CONVERTER

INTERRUPT

RING

CLEAR

TO SEND

CARRIER

“peTecT

]

}

;

{x “

¢ T ¢4

BB <

RING INDICATOR

;

{22
¢

CLEAR TO SEND

¢ 5 &4

< 8 &+— CF

CARRIER

| ¢ yy

‘
9

DSET

4
TTL/EIA

A Z

SECONDARY
TRANSMIT

|
I
{uu
&
T

DATA
READY

GROUND

SIGNAL

GROUND

K
&

RBUF

‘

SIGNAL GROUND

!
|

|
i

SECONDARY TRANSMITTED DATA

/., »,

REQUEST TO SEND

AL
<4

!
|

|
FORCE

BUSY

‘

; h

D &—

;

<
|

DATA TERMINAL READY

&
TM,

|
<20 &+
; A

DATA

|
RECEIVED

|
Jor
AN

‘

E1A

INTERLOCK

Figure 5-21

7 <T—~

EIA/TTL

|
LT

NG
L~

CC |

REQUEST
TO SEND

TERMINAL

PROTECTIVE

| L, || PROTECTIVE GROUND
W
'

—-——-r< B &
<

INT ENB

<16

16 <

1 w(j

SECONDARY RECEIVED DATA

bo
»

RECEIVE

e s/

SECONDARY

DESIGNATION
BA

]

T<2

EIA/TTL

P <

DATA SET

J1 ¢ ¢ ¢J1 TRANSMITTED DATA

«
RCSR

DLVI11-E Peripheral Interface Signal Flow

YBUF

MCO5C MODEM CABLE

Other exchanges involving CLEAR TO SEND and SECONDARY RECEIVED DATA may be pro|

grammed, as required, by the equipment.

SECONDARY RECEIVED DATA and SECONDARY TRANSMITTED DATA are provided for
the exchange of secondary or supervisory data with data sets having this capability. SECONDARY
" RECEIVED DATA allows the remote data set to set one bit in the RCSR and to cause a receiver
interrupt. SECONDARY TRANSMITTED DATA allows the LSI-11 to transmit the state of one bit
in the RCSR to the remote data set. These exchanges involve only two RCSR bits and are independent
of normal data exchanges between the peripheral device and the DLV11-E’s data buffer registers.

EIA-level data from the data set arrives at the DLV11-E on the RECEIVED DATA line. The peripheral interface converts it to TTL levels and routes it to the RBUF. Data to be transmitted from the
computer to the data set is serialized in the XBUF and then routed to the peripheral interface. The
interface circuitry converts it to the EIA-levels and transmits it out the TRANSMITTED DATA line
5.12

to the data set.

DLVI11-F PERIPHERAL INTERFACE

)

The DLV11-F supports either EIA data leads (‘“Data Leads Only” operation) or 20 mA current loops.
It does not perform handshakes or exchange control signals with data sets.

5.12.1

EIA Data Leads Only Operation

The DLV11-F does not monitor EIA control lines but it does, however, hold three outgoing EIA
control lines in a continuous TRUE condition. REQUEST TO SEND, FORCE BUSY, and DATA
TERMINAL READY are held continuously TRUE by separate EIA drivers (Figure 5-22). The
peripheral interface converts data from TTL levels to EIA levels for transmission on the TRANSMITTED DATA line. Data received over the RECEIVED DATA line is converted from EIA levels to
|

TTL levels and routed through an interlock jumper to the RBUF.

BCO5C MODEM CABLE

DLVii-F
Ji{

REQUEST TO SEND

————[>———r—> VD

‘

|
{

caur

|
|

FORCE BUSY

DATA TERMINAL READY.

'5 . :mausm-rrso DATA

| « S | RECEIVED DATA

eTA/TTL |

{>—~J—> M D |

|
l

|
RBUF

ETA INTERLOCK

fe—1> E >
11~4932

Figure 5-22

Data Lead Only Interface
5-28

5.12.2 Current Loop Operation
The peripheral interface directly interfaces terminal devices that use 20 mA current loops. It provides
current for receiver and transmitter circuits, and also controls the paper tape reader on teleprinters
equipped with a Reader Run relay. Both the transmitter and receiver circuits use neutral current loops,
in that current flows in only one direction (as opposed to polar current loops, in which it flows either
way).

The transmitter can be jumpered for active operation by inserting jumpers 4A and 5A (Figure 5-23),
or
for passive operation by inserting jumpers 3P and 4P. In active operation, the transmitter provides
20 mA (nominal) current to loop through the peripheral device. The current is switched on and
off by
data bits from the XBUF.
In passive operation, data bits from the XBUF are optically isolated from the transmission
lines.
Through the isolator, the data controls a switching circuit that switches the 20 mA current on and
off.
In passive operation, the peripheral device provides the power for the current flow.

The reader run circuit supplies a negative voltage (approximately -12 V) and a positive
voltage
(approximately +5 V) to energize the peripheral device’s reader run relay. If the READER ENABLE
bit is set in the RCSR, the reader run circuit causes the peripheral terminal’s paper
tape reader to
advance. When the START bit of the next character is received, the Receiver Active circuit asserts
RCVR BUSY H. RCVR BUSY H clears the reader enable bit, thereby switching off the current
to the
peripheral terminal’s reader run relay. The reader run bit must be set again by the program
before the
reader run circuit can drive the relay again.
The receiver circuit can be jumpered to be either active or passive. When configured
for active operation (Figure 5-24) the circuit supplies a ground and a positive voltage to the peripheral
device. When
jumpered for passive operation (Figure 5-25), the receiver uses power supplied by
the peripheral
device. In either case, current passes through an optical isolator. The isolator produces
a TTL output
that is electrically isolated from the current loop. The TTL output is routed to the RBUF.

The RBUF accepts TTL inputs from either the EIA interface circuit or the 20 mA circuit. The routing
1s determined by the cable attached to the 40-pin header connector (Figure 5-26). An
EIA modem
cable will jumper the output of the 20 mA receiver to the input of the RBUF.
5.13 DC-TO-DC POWER INVERTER
The power inverter operates on +12 V from the LSI-11 power supply and produces
-12 V for the
UART, the EIA drivers, and, on the DLV11-F, the reader run circuit. The power inverter circuit
consists of an oscillator driving a charge pump.

The output of the oscillator is capacitively coupled to a rectifier, which develops a negative-goi
ng
output. This output pumps up an inductive charge storage network and is Zener-regulated back
to
12V,

5-29

BCO5M CABLE

DLV11-F
A

A 1

+12V

+5V

{::
PART OF

ACTIVE

TRANSMITTER

XBUF

TRANSMIT

’/'

\—»

CIRCUIT

é’

PASSIVE TRANSMITTER

(5A)

PART OF

(4P) '

o——-o—-—-{—% KK

ACTIVE

TRANSMITTER

+5V

l SERIAL
ouUtT(-)

]

RCSR

SWITCHING

DATA

DATOO
H

OUT (+)

i>““*43-~1~9~AA e
(3P)

SERIAL

(4A)

BIT 0

'RUN

RELAY DRIVER

o
RCVR

READER

b
> PP /7
I

READER
RUN (+)

H
BUSY

10
| CONTROL
LOGIC

| > ee ~ |

RECEIVER

READER

RUN (-)

ACTIVE
CIRCUIT

-12V
11-4933

Figure 5-23

20 mA Transmitter and Reader Run Circuit

5-30

+5V

+12V

|
)
L
G
:
E
(
F
u
5
/;:"? 0.00
c29

FOR TTY
ONLY

(1A)

S
L. V)

RNV NI

|
|

(3a)

| seriAL DATA IN

‘

S >““””“ (“)

{
20mA RECEIVED DATA

pyl

TTL SERIAL DATA IN

|20mA INTERLOCK

AN
> E >.._.L.._._

11~ 4834

Figure 5-24

Active Receive 20 mA Current Loop

+5V
)

(1P) u1

———O=—0—1—> K )-—1————(4-)

| ceo

-1~ 0.005 uF

FOR TTY _/
ONLY

‘

lSER M.. DATAIN

) |

.____M 5

(=)

|
|
l

|
20mA/TTL RECEIVED DATA

| >

RBUF L

€

TTL SERIAL DATA IN

H
l

20mA INTERLOCK

11-4935

Figure 5-25

Passive Receive 20 mA Current Loop

5-31

INTERFACE CABLE

DLVII-F PERIPHERAL INTERFACE
r
P

Y AR

SRS

PART OF EIA DATA

J LEADS ONLY CIRCUITRY

|
|

'|
EIA/TTL
LEVEL

CONVERTER

EIA RECEIVED DATA

J“:} ;>

PART OF

BCOSC CABLE

| « MS

CBUF

TL SERIA

e)
S

TTL SERIAL IN

‘}/

BN
S
|

| PART OF 20 MA CURRENT
| LOOP CIRCUITRY

I
ll

|
|
i

ACT IVE

‘

passive | |

RECEIVER

PART OF

R
|
| SK >

20 MA SERIAL DATA IN (+)

20 MA SERIAL DATA IN (-)

BCOSM CABLE

11-4936

Figure 5.26 Interlock J umper Data Flow

5-32

APPENDIX A

IC DESCRIPTIONS

A.1
DC003 INTERRUPT LOGIC
The interrupt chip is an 18-pin DIP device that provides the circuits to perform an interrupt transaction in a computer system that uses a “pass-the-pulse” type arbitration scheme. The device is used in
peripheral interfaces and provides two interrupt channels labeled ‘A’ and *B,” with the A section
at a
higher priority than the B section. Bus signals use high-impedance input circuits or high-drive
opencollector outputs, which allows the device to directly attach to the computer systems bus. Maximum
current required from the V. supply is 140 mA.,

Figure A-1 is a simplified logic diagram of the DC003 IC. Timing for the A interrupt section is
shown
in Figure A-2, while Figure A-3 shows the timing for both A and B interrupt sections. Table
A-1
describes the signals and pins of the DC003 by pin and signal name.
A.2 DC004 PROTOCOL LOGIC
The protocol chip is a 20-pin DIP device that functions as a register selector, providing the
necessary to control data flow into and out of up to four word registers (8 bytes). Bus

signals

signals can

directly attach to the device because receivers and drivers are provided on the chip. An RC
delay
circuit is provided to slow the response of the peripheral interface to data transfer requests. The
circuit
is designed such that if tight tolerance is not required, then only an external 1K +20 percent resistor
is
necessary. External RCs can be added to vary the delay. Maximum current required from the Vee
supply is 120 mA.
Figure A-4 is a simplified logic diagram of the DC004 IC. Signal timing with respect to different
loads
are tabularized in Table A-2 and are shown in Figure A-5. Figure A-6 shows the loading for the
test
conditions in Table A-2. Signal and pin definitions for the DC004 are presented in Table A-3.
A.3 DC005 TRANSCEIVER LOGIC
The 4-bit transceiver is a 20 pin DIP, low-power Schottky device for primary use in peripheral
device
interfaces, functioning as a bidirectional buffer between a data bus and peripheral device logic.
In
addition to the isolation function, the device also provides a comparison circuit for address selection
and a constant generator, useful for interrupt vector addresses. The bus I /O port provides high-impedance inputs and high-drive (70 mA) open-collector outputs to allow direct connection to a computer’s
data bus structure. On the peripheral device side, a bidirectional port is also provided, with standard
TTL inputs and 20 mA tristate drivers. Data on this port is the logical inversion of the data on
the bus
side.
Three address jumper inputs are used to compare against three bus inputs and to generate the
signal
MATCH. The MATCH output is open-collector, which allows the output of several transceiver’s
to be
wired-anded to form a composite address match signal. The address jumpers can also be put
into a
third logical state that disconnects that jumper from the address match, allowing for “don’t care”
address bits. In addition to the three address jumper inputs, a fourth high-impedance input line
is used
to enable/disable the MATCH output.

A-1

Three vector jumper inputs are used to generate a constant that can be passed to the computer bus.
The three inputs directly drive three of the bus lines, overriding the action of the control lines.
Two control signals are decoded to give three operational states: receive data, transmit data, and
disable.

Maximum current required from the V¢ supply is 100 mA.

Figure A-7 is a simplified logic diagram of the DCO005 IC. Timing for the various functions is shown in
Figure A-8. Signal and pin definitions for the DC005 are presented in Table A-4.

A-2

+vec—{ig]
+2§C

fie]enasT H

RosTA H [17}
[oseT

NADATA
H [15}———

ENAD

ENACLK H 19

[—or

—

VECTOR HOJ!

CLR

17[IRQSTA
H

BDIN L

16[0 ENAST H

BIAKO L

BIAKI L g7

12| ENBDATAH

GND

10[3 RQSTB H

INITO
L4
15 ENADATAH
BINIT L5 PC003 yalEnacLk H

—

Tan] L

BIRQ L8

BOIN L

ENBCLK H [13}—pc 2

—S5t Lvee

ENBCLK

11 P ENBST
H

fos] sra L

131

{o6] B1AKO L

ENBDATA H |121

18P vCC

VECRQSTB H

ENBST H

>—101] VECTOR H

1 SET

CGR |

TM\

—“D—M VECRQSTB H
+VCe

RQSTB H h(}}~

CLR

a]—ano

{o4] InzTO L
IC-0173

Figure A-1

DCO003 Simplified Logic Diagram

A-3

—f

ENA DATA H

ENA CLK H

30 Mle-I»:

e
I
I

ENA ST H

RQSTA

7-30 —

—

BIRQ L

15-—65"‘*’: l::__“j_J"ZO-QO
|

BDIN L

I
i

BIAKI L

35 M:N-—-mu-i

VECTOR H

10- 45—

35 MIN—
!

[

>
{

| 10-45

»r

{

BIAKO L

12-55 —

i
|
I

t: >

|
12-55

NOTE

Times are in nanoseconds
11- 4150

Figure A-2

DCO003 “A” Interrupt Section Timing Diagram

A-5

MIN

—

|300 300!

INITO

ey T

7»35%«-

BINIT L

12-50

ENB DATA

ENB CLK

ENB ST

BIRQ

RQSTB

ENA DATA

ENA CLK H

30 Mwm—-—m:

—

ENA ST

RQSTA

|
B DIN

;

35 MIN —y

" BIAKI

ja—

10-45
10-45kee] reef
{

VECTOR

35 MIN —y

fa—

P |

10-45te-e
§
:

i
{

15-65 le—e

VECRQSTB

le—e110-45
i

|
|

i 15-65

NOTE:

Times are in nanoseconds

Figure A-3

{1~ 4158%

DC003 “A” and “B”’ Interrupt Section Timing Diagram
e

A-6

‘Table A-1

Signal

VECTORH

be used to gate the appropriate vector address cmm the bus and

to form the bus signal called BRPLY L.

VECRQSTBH
|

RQST “B” service vector address is required. When unasserted,
indicates RQST “A” service vector address is required. VEC‘TOR H is the gating signal for the entire vector address. VEC
RQST B H is normally bit 2 of the vector address.

BDIN L

. 4

VECTOR REQUEST “B” signal. When asserted, indicates

|
o
|

INTERRUPT VECTOR GATING signal. This signal should

2
Y

‘Description

INITOL |
~

BINITL

BIAKO L

DCO003 Pin/Signal Descriptions

BUS DATA IN. This signal, generated by the processor BDIN,

|
»

always precedes a BIAK signal.

‘

INITIALIZE OUT signal. Thisis the buffered BINIT L signal
usedin the device interface for general initialization.

BUS INITIALIZE signal. When asserted, this signal brings all

driven lines to their unasserted state (except INITO L).

BUS INTERRUPT ACKNOWLEDGE signal (OUT). This
signal is the daisy-chained signal that is passed by all devices not
requesting interrupt service (see BIAKI L). Once passed by a
device, it must remain passed until a new BIAKI L is generated.

BIAKIL

BUS INTERRUPT ACKNOWLEDGE signal (IN). This signal is the processor’s response to BIRQ L true. This signal is
daisy-chained such that the first requesting device blocks the
signal propagation while nonrequesting devices pass the signal
on as BIAKO L to the next device in the chain. The leading edge
of BIAKI L causes BIRQ L to be unasserted by the requesting
device.

BIRQL

ASYNCHRONOUS BUS INTERRUPT REQUEST from a
device needing interrupt service. The request is generated by a

true RQST signal along with the associated true interrupt
enable signal. The request is removed after the acceptance of the

BDIN L signal and on the leading edge of the BIAKI L signal,
or the removal of the associated interrupt enable, or due to the
removal of the associated request signal.

10
17

REQSTBH
REQSTA H

DEVICE INTERRUPT REQUEST SIGNAL. When asserted,
with the enable ““A” flip-flop asserted, will cause the assertion
of BIRQ L on the bus. This signal line normally remains
asserted until the request is serviced.

A-7

Table A-1 DCO003 Pin/Signal Descriptions (Cont)
Pin

11
16

Signal

Description

ENBSTH
ENA STH

INTERRUPT ENABLE “A” STATUS signal. This signal
indicates the state of the interrupt enable ““A” internal flip-flop,

- which is controlled by the signal line ENA DATA H and the

'ENA CLK H clock line.
12
15

ENB DATA H
- ENADATAH

ENB CLK H

ENACLKH

INTERRUPT ENABLE “A” DATA signal. The level on this
line, in conjunction with the ENA CLK H signal, determines
the state of the internal interrupt enable ‘“A”’ flip-flop. The output of this flip-flop
iis monitored by the ENA ST H signal.

INTERRUPT ENABLE “A”TM CLOCK. When asserted (on the

positive edge), interrupt enable “A” flip-flop assumes the state

of the ENA DATA H signal line.

A-8

VECTOR H

BDAL2 L

BDALI L

)

vee

ENB H

RXCX
H

BDALO L C
BWTBT L C

1 SEL6 L
1 SEL4 L

BSYNC L

BDIN L
BRPLY L

SEL2 L

SELO L

OUTHB L

BDOUT L

3 OUTLB L

GND

INWD L

SYNC

DAL 2

SEL6
L

DECODER

SEL4L
BDAL!

0‘2

SEL2L

DAL 1

SELOL

BDALO L @

OUTHB L
ouTLB L

BWTBT L

RXCX H

BRPLY

BDOUT L M

VECTOR H

INWD L
IC-0174

Figure A-4

DCO004 Simplified Logic Diagram

A-9

Table A-2

DCO004 Signal Timing vs Output Loading

Respect

Signal

Test

Output
Being

Figure A-5

Cond.

Asserted

Ref.

Min

Max

Min

(ns)

Sel (0,2,4,6) L
OUTLB L
OUTHB L

INWD L

BSYNC L
BDOUTL
DBOUTL

BDIN L

Pin 18

BRPLY L

OUTLB L

Connection

(Load A)

(Load B)

3508 +5%

BRPLY L

OUTHB L

15 pf +5%

(Load A)

(Load B)

Max
(ns)

Load B

Load C

| Load B

Load C

9> °10

| LoadB

Load C

9 °10

Load A

Load B

11> 12

-10

45
t13, t14

RX = 1K +5%

-10

_—

13> 14

BRPLY L

INWD L

(Load A)

(Load B)

-10

BRPLY L
(Load A)

VECTOR H

13> t14

Pin 18

BRPLY L

OUTLB L

300

400

-10

Connection

(Load A)

(Load B)

BRPLY L

OUTHBL

(Load A)

(Load B)

13:'14

13’ 14

RX = 4.64K +1%

CX =220 pf +1%

300

400

-10

400

-10

BRPLY L

INWD L

300

(Load A)

(Load B)

BRPLY L

VECTOR H

330

13> t14

13> 14
430

(Load A)

A-11

t13:t14

soAL (2.1.0) L 777728 wNas wa 77000000

|
BSYNC L

mlc-—-

T5->

SEL (0,2,4,6) L

|
|

15' MIN.—»| te—

15 MIN.i| [e—

BDOUT L

]

BOIN L

— T“?‘“““

:
T

BRPLY L

e Ti3fe—
t

ReCeH

—

| u.......i'ng“.__

SRS

IWD L

H
VECTOR

:
'
N Giml-—- .

THB L

gBTLB L

{
}

""""‘3 T3 /2= 2.av
i

;MfisI-—-

MT’GF—
|

* TIME REQUIRED TO DISCHARGE Ry Cx FROM ANY CONDITION ASSERTED =150ns

NOTE:
i

Times are in noanoseconds
11~ 4348

Figure %A-aSM DC004 ’I"in'zinpgw Diagram

A-13

Vee

360N
~

FROM

OUTPUT 7

1~ 200 pF

280.0
.
°

FROM

OUTPUT 7/

ey !SpF%

|ODE
-

_J_

1~ 150pF

FD777

LOAD

FROM

OUTPUT 7

LOAD

LOAD C

11-4349

Figure A-6 DC004 Loading Configuration for Table A2

Table A-3

DC004 Pin/Signal Descriptions

Signal

Description

VECTOR H

VECTOR. Thls input causes BRPLY L to be generated through
the delay circuit. Independent of BSYNC L and ENB H.

2
3
4

BDAL2L
"BDALIL
BDALOL

BUS DATA ADDRESS LINES. These signals are latched at
the assert edge of BSYNC
L. Lines 2 and 1 are decoded for the
select outputs; line 0 is used for byte selection.

BWTBT L

BUS WRITE/BYTE. While the BDOUT L input is asserted,
this signal indicates a byte or word operation: Asserted = byte,
unasserted = word. Decoded with B OUT L and latched
BDALO L to form OUTLB L and OUTHB L.

BSYNCL

BDINL

BUS SYNCHRONIZE. At the assert edge of this signal,
address information is trapped in four latches. While unasserted, disables all outputs except the vector term of BRPLY L.

BUS DATA IN. Thisis a strobing sngnal to effect a data input

transaction. Generatcs BRPLY L through the delay circuit and
INWD L.

A-14

—

Table A-3
Pin

DCO004 Pin/Signal Descriptions ( Cont)

Signal

Description

BRPLY L

BUS REPLY. This signal is generated through an RC delay by
VECTOR
H, and strobed by BDIN L or BDOUT L, and
BSYNC L and latched ENB H.

BDOUT L

BUS DATA OUT. This is a strobing signal to effect a data
output transaction. Decoded with BWTBT L and BDALO to

form OUTLB L and OUTHB L. Generates BRPLY L through
the delay circuit.

INWDL

IN WORD. Used to gate (read) data from a selected register on
to the data bus. Enabled by BSYNC L and strobed by BDIN L.

OUTHBL
OUTLBL

OUT LOW BYTE, OUT HIGH BYTE. Used to load (write)
data into the lower, higher, or both bytes of a selected register.
Enabled by BSYNC L and decode of BWTBT L and latched
BDALO L, and strobed by BDOUT L.

SELOL
SEL2 L
SEL4 L
SEL6 L

SELECT LINES. One of these four signals is true as a function
of BDAL2 L and BDALI1 L if ENB H is asserted at the assert
edge of BSYNC L. They indicate that a word register has been
selected for a data transaction. These signals never become
asserted except at the assertion of BSYNC L (then only if ENB
H is asserted at that time) and, once asserted, are not unasserted
until BSYNC L becomes unasserted.

RXCX

EXTERNAL RESISTOR CAPACITOR NODE. This node is
provided to vary the delay between the BDIN L, BDOUT L,
and VECTOR H inputs and BRPLY L output. The external
resistor should be tied to VCC and the capacitor to ground. As
an output, it is the logical inversion of BRPLY L.

ENB H

ENABLE. This signal is latched at the asserted edge of BSYNC
L and is used to enable the select outputs and the address term
of BRPLY L.

A-15

JAT L 1

201

vCC

JAZ L 2

191

JA3 L

MATCH
H [13

181

DATO H

REC H 4
XMITHOS5

17 DAT1
peoos

JV3 H

DAT3 H [J6

16H
157

DAT2 H Q7

147

JV1i

BUS3 L (8
BUS2 L [J9

1300 MENB L
123 BUSO L

"3 BUS!

M,L@%

—<
BUS L {OQ}

JAZ2 L lOZ}

\‘%

—<

—

‘

TM
L~

D
Vele

(10—

{17' DAT! H

{15' JV2 H

{OGI DAT3 H

{03' MATCH H

’

5 v v[

A
v Ay

BUSO L Il?_’}

BUST L t‘ll }

()

GND [J10

Jve H

DWC:DLD_

GND

Figure A-7

IC-DCO05

DCO005 Simplified Logic Diagram

TRANSMIT

DATA

]

REC H (GROUND)

5703008

—~|

;

DAT

H~INPUT

XMIT

DATA FROM BUS

(BUS INITIALLY

H—-OUTPUT

HIGH)

le-0 10 30ns

—INPUT

le- 0 TO 30ns

< 8 TO 30ns

RECEIVE

DATA FROM BUS

(BUS

INITIALLY LOW)

(GROUND)

REC

prssssse

e
-

BUS L

H
i

DAT

L____

XMIT

-5
TO 25ns

(GROUND)

REC

DAT

RECEIVE

le-5 T0 30ns
]

5 TO 25ns
—»

BUS

XMIT H

BUS L=-OUTPUT
«

H-QUTPUT

O TO 30ns

BUS L — INPUT

__.{

“_0 TO 30ns

]

@
8 TO 30ns

VECTOR TRANSFER TO

BUS

JV H

]
-

@ 20ns MAX

-o{

e 20ns MAX

- 10 TO 40ns

BUS L - QUTPUT

ADDRESS

BUS L - INPUT

DECODING

«»{
MATCH

MENB

B
#

]o— 10 TO 40ns
X

5 TO 40 ns

RECEIVE

MODE

LOGIC DELAY

XMIT H

REC

H
i

- 40 TO 90ns

DAT (3:0) H (OUTPUT)

1~ 4892

Figure A-8

DCO005 Timing Diagram

Table A-4
Pin

12
11
9
8

18
17

DCO00S Pin/Signal Descriptions

Name

Function

BUS(3:0) L
BUSO
BUSI
BUS2
BUS3

BUS DATA. This set of four lines constitutes the bus side of the
transceiver. Open-collector outputs; high-impedance inputs.
LOW = 1.

DAT(3:0)H
DATO
DATI

PERIPHERAL DEVICE DATA. These four tri-state lines car-

ry the inverted received data from BUS (3:0) when the transceiver is in the receive mode. When in transmit data mode, the

DAT?2

data carried on these lines is passed inverted to BUS (3:0).

DAT3

When in the
HIGH = 1.

JIV(3:D)H

VECTOR JUMPERS. These inputs, with internal pull-down

14
15
16

Jve
JV2
JV3

disabled

mode,

these

lines

open

(hi-z).

resistors, directly drive BUS (3:1). A low or open on thejumper
pin will cause an open condition on the corresponding BUS pin
if XMIT H is low. A high will cause a one (low) to be transmitted on the BUS pin. Note that BUSO L is not controlled by
any jumper input.

MENBL

MATCH ENABLE. A low on this line will enable the MATCH
output. A high will force MATCH low, overriding the match
circuit.

- MATCHH

ADDRESS MATCH. When BUS (3:1) match with the state of
JA (3:1) and MENB L is low, this output is open; otherwise, it is
low.

JA3:1)L
JA1L
JA2-L
JA3-L

ADDRESS JUMPERS. A strap to ground on these inputs will
allow a match to occur with a one (low) on the corresponding
BUS line; an open will allow a match with a zero (high); a strap
to V.. will disconnect the corresponding address bit from the
comparison.

XMITH
|

CONTROL INPUTS. These lines control the operational of the
transceiver as follows:

'RECH

REC XMIT

1
2
19

DISABLE: BUS, DAT open

0
1
1

1
0
1

XMIT DATA; DAT Bus
RECEIVE: BUS DAT
RECEIVE: BUS DAT

To avoid tristate overlap conditions, an internal circuit delays
the change of modes between XMIT DATA mode, and delays
tristate drivers on the DAT lines from enabling. This action is
independent of the DISABLE mode.

A.4 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER
The Universal Asynchronous Receiver/Transmitter (UART) is an LSI subsystem that
accepts binary
characters from either a terminal device or a computer and receives or transmits these characters
with
appended control and error detecting bits. In order to make this subsystem
universathe
l, baud rate,

bits per word, parity mode, and number of STOP bits are selected by external logic

circuits.

The UART is a full duplex receiver/transmitter. The receiver section accepts asynchron

ous serial

binary characters and converts them to a parallel format. The transmitter section
accepts parallel
binary characters from the bus and converts them to a serial asynchronous output
with START and
STOP bits added.
All UART characters contain a START bit, five to eight DATA bits, one or
two STOP bits, and a
PARITY bit which may be odd, even, or turned off. The STOP bits are opposite
in polarity to the
START bit. Refer to Figure A-9.
|
|
Both the receiver and transmitter are double buffered. The UART internally synchroni
zes the START
bit with the clock input to ensure a full 16-element (clock periods) START bit independe
nt of the time
of data loading. Transmitter distortion (assuming perfect clock input) is less than
3 percent on any bit

up to 10K baud. The receiver strobes the input bit within +8 percent of the theoretica
l center of the bit.
The receiver also rejects any START bit that lasts less than one-half of a bit
time.

LINE

8 DATA BITS
1011021031041

051061

S8 i
gMsBl

START
BIT

—+

RETURN TO IDLE

oo 730,%2—-4

[

STATE OF LINE
R

—

NEW

‘

CHARACTER

k- ONE BIT TIME=ONE/BAUD RATE

11-4968

Figure A-9

UART Data Format

A.4.1
Receiver Operation
_
S
,
|
A block diagram of the UART receiver is shown in Figure A-10. When
the receiver is in the idle state,
it samples the serial input line (SERIAL IN, pin 20) at the selected clock
edges (R CLK, pin 17) after
the first mark-to-space transition of the serial input line. If the first
sample is a mark (high), the
receiver returns to the idle state and is ready to detect another mark-tospace transition. If, however,
the first sample is a space (low), then the receiver enters the data entry
state.
v

If the receiver control logic has not been conditioned
to the no parity state (a low on pin 35), then the
receiver checks the parity
of the data bits plus the parity bit following the data bits and compare
s it

with the parity sense on the parity select line (pin 39). If the parity sense
of

the received character

differs from the parity of the UART control logic, then the receive parity
error line (P ERR, pin 13)
goes high and causes the P ERR bit in the RBUF register to set.
~
o

If the receiver control logic has been conditioned to the no parity state
(a high on pin 35), then the
receiver takes no action with respect to parity and maintains the parity
error line (P ERR, pin 13) in
the FALSE (low) state. When the control logic senses a parity error, it generates
a P ERR signal. The
DATA AVAILABLE signal updates the parity error indicator.

A-19

DATA BITS

;

MSB ‘

DATA

ENABLE

~—

‘
LS B

el PHII MY
[

(RDE)

AND GATES

g
gg

STATUS

reset
JREGISTER
|1
DATA
R

F AVAILABLE

OVERRUN

D |

Ew;w

PR ANE

XMIT

TS G

PARITY

——

ISET

V I'

I DATA HOLDING REGISTER

AND GATES

SHOWN AS

SERIAL

DATA —
INPUT

LOCK

RECEIVER SHIFT REGISTER
|

EVEN
PARITY
SELECT

fl |

SINGLE BUFFERING

DATA AVAILABLE

CONTROL LOGIC ~ faniY ERROR
o

NO
PARITY

|[FRAMING ERROR

NB2
NBt
NUMBER OF
BITS/CHARACTER
11-4970

Figure A-10 UART Rcceivcr - Block Diagram
The receiver samples the first STOP bit that occurs either after the PARITY bit, or after the data bits if
no parity is selected. If a valid (high) STOP bit exists, no further action is taken. If, however, the STOP
bit is FALSE (low), indicating an invalid STOP code, then the UART control logic provides a framing
error indication (a high on FR ERR, pin 14).

Because the serial input from the external device is shifted into the UART a bit at a time (SI, pin 20),
has been received and shifted into
occurrence of a STOP code indicates that the entire data character
the receiver shift register. After the STOP bit has been sampled, the receiver control logic parallel
transfers the contents of the shift register into the receiver data holding register and then sets the data
available (R DONE) flag.

The data available signal also functions as the clock input to the FRAME ERR, PARITY, and
OVERRUN flip-flops in the UART status register. At this point, the DA flip-flop is set, the OVERis clear but has a high on the data input because of the output from the DA flip-flop,
"RUN flip-flop
and the PARITY and FRAME ERR flip-flops are set or cleared depending on the signal (TRUE or
FALSE) strobed in from the control logic.

An OVERRUN condition indicates that another data character is being sent to the UART before the
previous character has been transferred out. If the DA flip-flop is set, indicating a character is stored in
the holding register, and the UART control logic attempts to set the DA flip-flop again (indicating a
new character has been shifted into the shift register), the DA signal from the control logic provides a
clock input to the OVERRUN flip-flop. This flip-flop then sets because the data input is high (DA
flip-flop was already set by the previous DA signal).

A-20

If the serial input line goes from a mark (high) to a space (low) and remains at the low level, the
receiver shifts in one character, which is all spaces, then sets the FR ERR indicator and waits until the
input line goes high (marking) before shifting
in another character.
A.4.2

Transmitter Operation

A block diagram of the UART transmitter is shown in Figure A-11. When the UART transmitter is in
the idle state, the serial output line (pin 25) is a mark (high). When it is desired to transmit data, a
parallel character is strobed into the UART transmitter data buffer (lines connected to pins 26-33) by
means of the data strobe signal (pin 23). The time between the low-to-high transition of data strobe
and the corresponding mark-to-space transition of the serial output line is within one clock cycle (1/16
of a bit time) if the transmitter has been idle.
*'
o
|

NO.STOP BiTSmfi*

39
EVEN PAR. SEL."“""S‘?

NO PAR&TY*:;;-*

BITS/CHAR. —128,

CONTROL

LOGIC

PAR

GEN [

1o
i

‘

BITS) DB4 —»

_ SERIAL

#?SO%FE)ACTER

OUTPUT
LOGIC

DB7 ——
DATA

—® OUTPUT

ENCODER

DATA

END

SHIFT

BUFFER

figgfg&m

DB1—>

LOAD

SHIFT
T

DATA STROBE

TRANSMITTER BUFFER EMPTY

(XRDY)

TBMT
F/F

40
CLOCK INPUT —f
»|

Zzhglggbé§MITTER

1uinG
GENERATOR

11-4871

Figure A-11

UART Transmitter - Block Diagram

A-21

When the data has been loaded into the UART data buffer, it is next transferred to the transmitter
shift register under control of signals from an encoder that selects the format determined by the control
logic. This permits selection of parity or no parity (pin 35), the type of parity (pin 39), the number of
STOP bits (pin 36), and the number of data bits per character (pins 37 and 38).

The end-of-character (pin 24) signal goes high each time a full character (including STOP bits) is
transmitted. If this line goes low, it prevents the timing generator from loading another character into
- the shift register. The line is normally high when data is not being transmitted and goes low at the start
of transmission of the next character.

If the transmitter data buffer is loaded while the previous character is being shifted through to the

output line, the START bit of the new character immediately follows the last STOP bit of the previous

character.

Figure A-12 shows the pin locations and Table A-5 defines the pin functions.

PAY LT AVIVIVIVIY T VAVIVAVAVAVAVEY

11-5036

Figure A-12

UART Pin Locations

A-22

Table A-5
Pin No.

I/0

Name

UART Pin Functions
Mnemonic

Function

V.. POWER SUPPLY

VCC

+5 V supply.

Vg POWER SUPPLY

Vgg

=12 V supply.

GROUND

f Ground

RECEIVED DATA ENABLE

RDE

A low on the receiver enable line places the
received data onto the output lines.

RECEIVED DATA BITS

These are the eight data output lines. These

RD8—-RD1

“lines may be wire-ORed. When 5, 6, or 7 level
code is selected, the most significant unused
bits are low. Characters will be right justified
into the least significant bits. RD1 (pin 12)
" is the least significantbit, RD8 (pin 5) is the
most significant bit. A high indicates a mark.
13

RECEIVE PARITY ERROR

PER

This line goes to a high if the received char-

acter parity does not agree with the selected

' POE.
14

FRAMING ERROR

- This line goes to a high if the received character

FER

~ has no valid stop bit, i.e., the bit following
the parity bit is not marking.
15

OVERRUN

This line goes to a high if the previously

received character is not read (DA line not

reset) before the present character is trans- ferred to the receiver holding register.
16

STATUS WORD ENABLE

SWE

A low on this line places the status word bit
- (PE, DA, TBMT, FE, OR) onto the output

lines.
17

RECEIVER CLOCK LINE

RCP

* This line is for a clock whose frequency is
16 times (16X) the desired receiver baud
- rate.

RESET DATA AVAILABLE

RDA

RECEIVED DATA AVAILABLE

A low on this line will reset the DA line.

- This line goes to high when an entire character
has been received and transferred to the receiver
holding register.

A-23

Table A-5
Pin No.

I/0

UART Pin Functions (Cont)

Name

NO PARITY

Mnemonic
NP

Function
A high on this lead will eliminate the parity

bit from the transmitted and received character.
The stop bits will immeidately follow the last

data bit on transmission. The receiver will
not check parity or reception. It will, when
asserted, also clamp the PE to a low.

TWO STOP BITS

2SB

This lead will select the number of stop bits,
one or two, to be appended immediately

after the parity bit. A low will insert one
stop bit and a high will insert two stop bits.

37-38

NUMBER OF BITS/CHARACTER

NB2, NB1

These two leads will be internally coded to

EVEN PARITY SELECT

PEV

(38)

(L)

(L)
H)
H)

1
0
1

(H)
(L)
(H)

Bits/Character

NB1

(37)

NB2
el
e B e

select either 5, 6, 7, or 8 data bits/character.

The logic level on this pin selects the type

of parity that will be appended immediately

after the data bits. It also determines the parity
that will be checked by the receiver. A low
will insert and check odd parity and a high

will insert and check even parity.

TRANSMITTER

TCP

This line is for a clock whose frequency is
16 times (16X) the desired transmitter baud
rate.

A-25

Table A-5

)

Pin No.

I/0

UART Pin Functions (Cont)

Name
SERIAL INPUT

Function

Mnemonic

This line accepts the serial bit input stream.
A high must be present when data is not

being received. High is a mark. Low is a space.

EXTERNAL RESET

A high level pulse on this pin will reset TSO,

TRMT, and EOC to a high level and RDA,
PER, FER, and ROR to a low level.

TRANSMITTER BUFFER EMPTY

TBMT

The transmitter buffer empty flag goes to a

high when the data bits holding register may
be loaded with another character.

DATA STROBE

A low to high transition on this line will

enter the data bits into the data bits holding
register. Data loading is controlled by the
rising edge of DS.

END OF CHARACTER

EOC

This line goes to a high each time a full

character including stop bits is transmitted.
It remains at this level until the start of
transmission of the next character. Start of

transmission is defined as the mark to space
transmission of the start bit. It remains at a

high when data is not being transmitted.

SERIAL OUTPUT

2633

DATA BIT INPUTS

DB1-DB8

This line serially, by bit, provides the entire

transmitted character. It remains at a high when
no data is being transmitted. High is a mark;
low is a space.

‘These are the eight parallel data input lines.
1If 5, 6, or 7 bits are transmitted, the least

‘most significant bits are used. DB1 is the

least most significant bit (pin 26). DB8 is the

€

‘most significant bit (pin 33). A high input
will cause a mark (high) to be transmitted.

CONTROL STROBE

A high on this lead will enter the control bits

(POE, NB1, NB2, SB, NP) into the control
bits holding register. This line can be strobed
or hard wired to a high level.

A-27

A.5 5016 DUAL BAUD RATE GENERATOR
The 5016 is an LSI MOS device containing two independent sections. Each section divides its input
clock frequency by one of 16 divisors to produce one of 16 different clock outputs. The divisors are
stored in ROMs on the chip. The ROMs are addressed by circuits that latch in and decode the logical
states of the address lines (Figure A-13). The address lines may be strobed or held at a dc level. Table
A-6 lists the frequencies selected by the address lines. Figure A-14 depicts the 5016 pin locations. Table
A-7 defines their functions.

STT

'
DECODE

CIRCUITS

ROM

CLOCK

DIVIDER

—

»|

DIVIDER

}

DECODE

ROM

CIRCUITS

]

STX

11-4972

5016 Block Diagram

Figure A-13

A-29

CLOCK — 1
Vee

18 |— CLOCK

— 2

17 |

—

16 |— Tp

— 4

15—

14 |— Tc¢

Rg — 5

Rc — 6

— 7

12 |— STT

STR

— 8

11 |— GND

Vpp

— ©

10 |— NC

{11-4973

| Figure A-14 5016 Pin Locations

Table A-6

Transmit/Receive
Address

0
0
0
0
-0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
|

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

5016 Selectable Frequencies

Baud

Theoretical
Frequency

Actual
Frequency

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200

0.8
1.2
1.76
2.152
24
4.8
9.6
19.2
28.8
32.0
384
57.4
76.8
115.2
153.6
307.2

0.8
1.2
1.76
2.1523
2.4
4.8
9.6
19.2
28.8
32.081
38.4
- 57.6
76.8
115.2
153.6
316.8

Rate

16X Clock (kHz) | 16X Clock (kHz) | Divisor

Crystal Frequency = 5.0688 MHz

A-30

6336
4224
2880
2355
2112
1056
528
264
176
158
132
88
66
44
33
16

Table A-7

Pin No.
|

Mnemonic
CLOCK

5016 Pin Functions

Name

Function

External Clock

This input is either one pin of a crystal oscilla-

Input

tor package or one polarity of another external
input.

Power Supply

+5 V supply.

Reciever Output

This output runs at the frequency selected

Frequency

by the receiver address.

Ra, Rp; Res Rpy | Receiver Address | The logic levels on these inputs select the
receiver output frequency, fp.

STR

Strobe-Receiver

A high level input strobe loads the receiver

Address

address (R As RB, RC, RD) into the latch and
decode circuits. This input may be strobed
or hard wired to a high level.

VbD

Power Supply

No Connection

GND

Ground

STT

Strobe-Trans-

A high level input strobe loads the transmitter

mitter Address

+12 V supply.

address (TA TB, TC, TD) into the latch and

decode circuits. This input may be strobed or
hard wired to a high level.

13—-16

Tp, T, T, Ty

Transmitter

The logic levels on these inputs select the

Address

transmitter output frequency, fr.

Transmitter

This output runs at the frequency selected by

Output

the transmitter address.

Frequency

CLOCK

Inverted External | This input is either ofie pin of a crystal pack-

Clock Input

age or one polarity of another external input.

A-31

g
5,

APPENDIX B

WIRE WRAP INSTRUCTIONS

B.1

PURPOSE

This appendix is intended to assist the user who installs or removes wire wrap jumpers. It describes and
illustrates the preferred procedures and standards for producing high-grade solderless wrapped jumper
wire connections.

B.2

DEFINITIONS

The following terms are used in discussing wire wrapping:

Solderless wrapped connection- This connection consists of a helix of continuous, solid uninsulated
wire tightly wrapped around a wire wrap pin to produce a mechanically and electrically stable connection. In addition to the length of uninsulated wire wrapped around the wire wrap pin, a half turn of
insulated wire is wrapped around the pin to ensure better vibration characteristics (Figure B-1).

END TAIL

/
AN

TAPERED TIP ON

THE PIN (APEX)
CORNER OF THE PIN

No. 30 AWG WIRE

WRAP OF

INSULATED WIRE

REFERENCE CORNER
11-4974

Figure B-1

Solderless Wrapped Connection on Wire Wrap Pin

A turn of wire — A turn of wire consists of one complete, single, helical ring of wire wrapped 360 degrees
around a wire wrap pin, intersecting four corners of the pin. Thus, a connection having “n”’ turns in
contact with the wire wrap pin will intersect the reference corner “n + 17 times (Figure B-2).
A half turn of wire — A half turn of wire contacts three of the four corners of a wire wrap pin (Figure
B-3).

End tail — An end tail is the end of the last turn of wire on the wire wrap pin.

_—
4

WIRE CONTACTS ALL FOUR CORNERS,
AND CONTACTS THE REFERENCE
CORNER TWICE.
11-4975%

Figure B-2

Full Turn

WIRE CONTACTS

THREE CORNERS
OF PIN

11-4976

Figure B-3

Half Turn

B.3 CONNECTIONS
Turns are counted along the edge of a reference
corner (Figure B-1). There should be seven to nine
turns of insulated wire on the wire wrap pin. Each turn
should be adjacent to the next turn; one turn
should not be wrapped over another turn. The end
tajl may extend tangentially away from the wire
wrap pin, but should not extend more than one wire
diameter.
If a second level of wire wrap is placed on a wire
wrap pin, the bare wire of the second level wrap
should not overlap the first level wrap. The first turn
of the insulated wire of the second level wrap
may, however, overlap the last turn of the first level
wrap (Figure B-4).

The wire used for the jU,mpers should be good quality wrapping wire. DIGIT

specifications for the jumpers installed at the factory

Conductor

Gauge
30 AWG solid
M aterial

Silver-coated copper
Diameter
0.0257 + 0.0008 cm or -0.0003 cm (0.0101 + 0.0003
in or - 0.0001 in)

B-2

AL uses the following

SECOND LEVEL

bb)

—

FIRST LEVEL

11 -4977

Figure B-4

Two Levels of Wire Wrap

Insulation
Material

Vinylindene flouride

Outside Diameter

0.048 £06.003 cm (0.018 £0.001 in)
U.L. Style No.
1423

DC Resistance/304.8 m (1000 ft)
113.6 ohms
NOTE

This wire should not be used for solder applications.

Figures B-1 and B-4 show recommended solderless wrapped connections. Figure B-35 illustrates connections that should be avoided.

B.4

PROCEDURE

To install a wire wrap jumper, proceed as follows:

Cuta p}ece of 30 AWG wire 5.7 cm (2-1/4 in) longer than the distance between the two wire
|

wrap pins.

Strip 2.7 cm (1-1/16 in) off each end of the wire.

B-3

L
OVER

LAJ

WRAP

END TAIL TOO LONG

INSUFFICIENT TURNS

—

INSUFFICIENT INSULATION

IMPROPER SPACING AND
OVER TAPER END

OVERLAP

Van

fl"!

{
j

LlJ
BENT

WRAP -POST

OPEN WRAP

SPIRAL WRAP
11-5037

Figure B-5

Defective Wire Wraps

Insert the wire into the wire wrap bit far enough for the insulation to enter the feed slot
(Figure B-6).
Loop the wire through the anchoring notch.

Place the tool on the wire wrap pin and actuate the rotating spindle (bit). This should
produce eight turns of bare wire and one-half to two turns of insulated wire on the wire wrap
pin.

Load the free end of the wire into the wire wrap bit and wrap the other wire wrap pin.

Use an unwrapping tool to remove a wire wrap jumper. A jumper may be snipped out to break the
electrical connection, but when it is desired to reuse the wire wrap pin the remaining wire should be
removed carefully. Pulling the wire off may bend the pin and dent the pin corners. Therefore, it is
recommended than an unwrapping tool be used to remove jumper wire wraps.

Place the tool over the wire wrap pin and insert the end tail of the wrap into the unwrapping tool bit.
Carefully unwrap the wire and discard it. Jumper wires should not be reused.
If it is desired to place a second level wrap on a wire wrap pin, care should be taken not to overlap the
first wrap. If there is insufficient space left on the wire wrap pin for a second level wrap, remove the
first level jumper and install a new one lower on the pin. A wire wrap joint that is installed too high on
the pin should not be forced to a lower level; it should be unwrapped and replaced with a new one at
the lower level.

B-5

\, STATIONARY
SLEEVE

FEED SLOT

ROTATING SPINDLE

STRIPPED WIRE

(BIT)

WIRE ANCHORING
NOTCH

WIRE INSERTED

TOOL TIP

WRAP- POST
INSERTION

WIRE ANCHORED

TYPICAL

CONNECTION

11-5038

Figure B-6

Loading the Wire Wrapping Kit
B-6

DLV11-E AND DLV11-F

ASYNCHRONOUS LINE INTERFACE
USER’S MANUAL

EK-DLV11-OP-001

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