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Document:	DJ11 Asynchronous 16-line Multiplexer Maintenance Manual
Order Number:	EK-DJ11-MM
Revision:	003
Pages:	123
Original Filename:

OCR Text

EK-DJ11-MM-003

DJ11 asynchronous
16-line multiplexer
maintenance manual

digital equipment corporation - maynard, massachusetts

Ist Edition, May 1973

2nd Printing, (Rev), January 1974
3rd Printing, September 1974

4th Printing, (Rev), August 1976

The material in this manual is for informational

purposes and is subject to change without notice.
Printed in U.S.A.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

DECtape

DECCOMM

DECUS

PDP

RSTS

DECsystem-10

DIGITAL

TYPESET-8

DECSYSTEM-20

MASSBUS

TYPESET-11
UNIBUS

8/76-14

CONTENTS
Page

CHAPTER 1

GENERAL DESCRIPTION

1.1

SCOPE

1.2

PURPOSE

1.3

TYPICAL SYSTEM BLOCK DIAGRAM

1.4

OPTIONS

1-1
.

o,
.

...

1-1

1-2

1-3

1.5

1.6

SPECIFICATIONS

CHAPTER 2

INSTALLATION

2.1

SCOPE

2.2

CONFIGURATION DIFFERENCES

2-1

UNPACKING AND INSPECTION

INSTALLATION

24.1

...

2-1
.

...

... 2-8

PROGRAMMING

3.1

SCOPE

3.2

ADDRESSABLE REGISTERS

o, 3-1
.

Receive Buffer Register (RBUF)

...

..
.

3.2.1

Control Status Register (CSR)

3.2.2

... 3-1
...

... 3-3

...

... 33

3.23

Transmit Control Register (TCR)

Transmit Buffer Register (TBUF)

...

3.2.5

Break Control Status Register (BCSR)

CHAPTER 4

DETAILED DESCRIPTION

4.1

SCOPE

4.2

FUNCTIONAL BLOCK DIAGRAM DISCUSSION

4.3

DETAILED BLOCK DIAGRAM DISCUSSIONS

e
.

Receiver Section

4.3.2

Transmitter Section

4.3.3

Address Selection Logic

4.3.4

Interrupt Control Logic

435

Distribution Panels H317A/B

4.3.6

Maintenance Logic

4.3.7

Universal Asynchronous Receiver/Transmitter (UART)

LOGICDISCUSSION

.
.

...

... 4-9

4.4.1

BusInterface

Output Interface and TBR, TCR Registers

H/D Gatingand CSRBits

Transmit Line Request Detect

4.4.5

Trans Scan Control

4.4.6

Receiver Scanner

4.4.7

e, 4-1
. . . . .. . .... 4-1

4.4.3

... 3-5

4.44

... 34

...

4.4.2

. . . . . . . . . . . . ... . ... 4-2
L. 4-2

4.3.1

... 3-1

324

4.4

..., 2-1

Installation Procedure

Setting Character Done Interrupt Constant
CHAPTER 3

1-1

...

L. 4-4

..o 4-6
.

.
.

...
.
.

.
.

... 4-6
.
.

...
.

.. 4-8
.

4-10

4-12

...

4-14

...

4-15

...

.....

4-16

...

4-17

...

4-19

Miscellaneous Control

...

4-20

4438

Clock and Distribution

...

4-22

4.4.9

Multiple UART Card Lines 15:00

...

4-22

4.4.10

DJ11 Control Interface

...

4-24

CONTENTS (Cont)

4.4.11

4.4.12
4.4.13

FI/FO Buffer Control Logic
. .
TTL Output Interface
.

4.4.14

EIA Output Interface

4.4.15

TTY Output Interface

CHAPTER 5§

e
. o v o oo
« .«

. .

.« .

.«

..o

MAINTENANCE

. . . . . . . .
Diagnostic Testing
. . . . . . .
DJI1 TESTPROCEDURE
Logic Verification DJ11-AA,AB,AC

INTRODUCTION

5.2.1

5.2.2

Test Equipment Required

5.3

54.1

PREVENTIVE MAINTENANCE
. . .
Mechanical Checks

5.2

5.3.2

5.1

5.3.1

DJ11 FI/FOBuffer

.
CORRECTIVEMAINTENANCE
General Corrective Procedures

.« oo
e
e e
.o

..o

.«

..o

...

o000

542

Interface Check DJ11-AA

543

Interface Check DJ11-AB

544

Interface Check DJ11-AC

.«

54.5

Error Analysis During Test

..o

CHAPTER 6

ENGINEERING DRAWINGS

6.1

GENERAL

APPENDIX A

IC SCHEMATICS

GENERAL

A2
A3
A4

7485 4-BIT COMPARATOR
7490 FREQUENCY DIVIDER

A9
A.10

7492 FREQUENCY DIVIDER
7493 FREQUENCY DIVIDER

.«

.
.

8266 2-INPUT 4-BIT MULTIPLEXER
. .

8837 HEX UNIBUS RECEIVER

.
.

.«
.

.. e

.
.

A.lS

74123 RETRIGGERABLE MONOSTABLE MULTIVIBRATOR WITH CLEAR

A.16

74151 8-LINE TO 1-LINE MULTIPLEXER

A.14

. . . . . . . ..

9305 FREQUENCY DIVIDER (VARIABLE MODULO COUNTER)

.
. . . . . . . . . .
..
.
.
.
.
.
.
.
.
.
.
.
.
.
.

. .

. . .

A.17

74153 DUAL 4-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER

A.18

74155 3-LINE TO 8-LINE DECODER

A.19

74157 QUADRUPLE 2-LINE TO 1-LINE MULTIPLEXER

A.20
A21

74161 4-BIT BINARY COUNTER .
74175 QUAD D-TYPE FLIP-FLOPS

A.22

74193 4-BIT BINARY COUNTER

. .

oo ..
oo .

. . .

. . . . . . . .
..

. . . . . . . . . . . ..
o

. .

o«

..
..

. .
9318 8-INPUT PRIORITY ENCODER
74121 MONOSTABLE MULTIVIBRATOR

8838 QUAD BUS TRANSCEIVER

oo
e

A.12

. . . . . . . . ..

. . . . . . . . . . . . ..
7474 DUAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
74H74 D-TYPE EDGE-TRIGGERED FLIP-FLOPS . . . . . . . . . . . . . . . ..

3341 4-BIT X 64-WORD PROPAGATEABLE REGISTER (FI/FO)

CONTENTS (Cont)
Page
APPENDIX B

SIGNAL GLOSSARY

B.1

GENERAL

.o,

APPENDIX C

C.1
C2

APPENDIX D

FORMS

T w4

ILLUSTRATIONS

Figure No.

Title

1-1

DI11 Typical System Block Diagram

...

1-2

DJ11-AA Asynchronous 16-Line Multiplexer

...

1-3

DJ11-AC Asynchronous 16-Line Multiplexer

...

1-4

DJ11 Module Utilization

...

M7285 Board Showing Jumper and Switch Selection

Power Harness ColorCode

BCO8S-15 Polarization

...

Strapping on H317B Distribution Panel

Cinch Connector Strapping on H317B Distribution Panel

Filtering and Mode Strapping on H317A Distribution Panel

...

CHARACTER DONE INT Jumpers

Control Status Register Bit Assignments

...

3-2

Receive Buffer Register Bit Assignments

...

Transmit Control Register Bit Assignments

...

Transmit Buffer Register Bit Assignments

3.5

Break Control Status Register Bit Assignments

4-1

DJ11 Functional Block Diagram

4.2

Receiver Detailed Block Diagram

4-3

FI/FO Format

...

4-6

Device Register Select Address Format

...

4.7

Active and Passive Receiver Wiring
DI11 DataPath

4-9

DJ11 Multiple UART Functional Block Diagram

4-10

UART Receiver, Block Diagram

.
.

DJ11 H/D Gatingand CSRBits

...

...
..

4-15

Transmit Line Request Detect Block Diagram
Trans Scan Control Block Diagram

4-17

TBMT MOS Decay Protection

...

4-16

...

....
..

...
.

...

.....

...

4-14

...

....

...

DJ11 Interface and Registers TCRand TBR

4-13

UART Transmitter, Block Diagram
DJ11 Mux BusInterface

411

4-12

.
.

...

... ..
. . ...

Transmitter Detailed Block Diagram

M105 Address Selector Block Diagram

..
...

4-4

4-5

...

4-8

...

3-1

..
.

.
.

...
.

.....

...

....
L.

...

.....

...

....

ILLUSTRATIONS (Cont)
Figure No.
4-18
4-19
4-20

4-21
4-22

4-23
4-24

4-25
4-26
4-27
4-28
5-1

5-2

5-3
54
5-5

5-6
A-1
A2
A-3
A4
A-5

A-6

A-7
A-8

A9
A-10

A-11
A-12
A-13
A-14
A-15

A-16
A-17

A-18
A-19

A-20
A-21

Page

Title

Receive Scanner Block Diagram . . . . . . . . . . . . oo o000
Receive Scan Clock Events . . . . . . . . . . . . . ..o oo
DJ11 Clock, Functional Block Diagram . . . . . . . . . . . . . . . . . .. ..

Multiple UART RCV SCAN Selection Scheme

4-21
4-22
4-23

. . . . . . . . . . . .. ... ... 4-25

. . . . . . . . . . .. .. ... .. 4-26
Multiple UART Trans Line Selection Scheme
... 4-27
. . . . . .« . . . .« o
.
.
.
UART Data Format Breakdown . . .
4-27
e
o
o
.«
.
.
.
.
.
.
. . . . . . . .
FI/FO Buffer Format
4-28
..
...
.
.
.
.
.
.
.
.
.
.
.
.
.
. . . .
FI/FO Buffer Control Block Diagram
4-30
..
.
.
.
.
.
.
.
.
.
.
.
.
M5900 Level Converter Block Diagram . . . . .
4-31
...
..
.
.
.
.
.
.
.
.
.
.
.
M5901 Level Converter Block Diagram . . . . . .
4-31
...
.
..
.
.
.
.
.
.
.
.
M5902 Level Converter Block Diagram . . . . . . .
5-10
..
.
.
.
.
.
.
.
.
.
.
.
.
DJ11 Receiver, Maintenance Flow Diagram . . . . . .
5-11
..
.
.
.
.
.
.
.
.
.
.
.
DJ11 Transmitter, Maintenance Flow Diagram . . . . . .
5-14
oo
.
.
.«
.
. . . . . . . . . .
DCO08-CS Test Jumper Chart
5-16
e
.
.
Clock Signal . . . . . . . . . .
5-17
...
...
..
.
.
.
.
.
.
.
.
. . . . .
Receive Scan Timing, WaveformNo.1
5-18
oo
.
.
.
.
.
.
.
.
.
.
Receive Scan Timing, WaveformNo.2 . . . .
A-2
..
..
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
3341 4-Bit X 64-Word Propagateable Register
A3
..
...
...
.
.
.
.
.
.
.
.
.
.
.
7474 Dual D-Type Edge-Triggered Flip-Flop
A4
...
..
...
..
.
.
.
.
.
.
.
.
.
.
.
74H74 D-Type Edge-Triggered Flip-Flops
e e e A-6
e e
. . . . . . . . . . . e e e e
7485 4-Bit Comparator
A-8
oo
..o
.
.
.
7490 Frequency Divider . . . . . . .
A9
o
..
.
.
.
.
.
7492 Frequency Divider . . . . .
A-10
oo
...
o
.
.
.
.
7493 Frequency Divider . . . . . .
. . . . . . . . . ..o A-11
8266 2-Input 4-Bit Multiplexer
8837 Hex Unibus Receiver . . . . . . . . . .« o« o . o oo A-12
e A-13
8838 Quad Bus Transceiver . . . . . . . . . . . . e 0. e e e e
. . . . .. A-15
.
.
.
.
.
.
.
.
.
.
Counter)
9305 Frequency Divider (Variable Modulo
o A-16
..
.
.
.
.
.
.
.
. .
9318 8-Input Priority Encoder
A-17
oo
...
.
.
.
.
.
.
.
. .
74121 Monostable Multivibrator
A-18
..
.
.
.
.
.
.
.
.
.
.
.
.
Clear
With
74123 Retriggerable Monostable Multivibrator
A-20
..o
.
.
.
.
.
.
.
.
.
.
.
.
.
74151 8-Line to 1-Line Multiplexer
A-21
..
.
.
.
.
.
.
.
.
.
.
.
.
.
exer
74153 Dual 4-Line to 1-Line Data Selector/Multipl
A-23
oo
..o
.
.
.
.
.
.
.
.
.
74155 3-Lineto 8-Line Decoder . . .
A-24
..
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
74157 Quadruple 2-Line to 1-Line Multiplexer
A-25
e
e
e
oo
oo
oo
o
.
.
.
.
.
.
.
.
.
. . . .
74161 4-Bit Binary Counter
A-26
oo
oo
.
.
.
.
.
.
.
74175 Quad D-Type Flip-Flops . . . .
A-28
e
e
e
oo
..o
.
.
.
.
.
.
.
. . . . .
74193 4-Bit Binary Counter
TABLES

Table No.
1-1

22
2.3

Title

Page

. . . . . . . . .o 1-2
DI11 Options
e e e e e 2-1
. . . . . . . . . . . . . . . . .. e
DJ11 Option Designations
2-2
o
oL
..o
L
.
.
.
.
.
.
.
.
.
Parameter Switch Settings
2-3
..o
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Chart
Sample Customer’s Preference
2-4
o
..
.
.
.
.
.
.
.
.
.
.
.
Chart
Sample Installation

TABLES (Cont)
Table No.

Title

Page

3-1

Control Status Register Bit Assignments

Receive Buffer Register Bit Assignments

5-1

List of Recommended Spares

5-2

Test Equipment Required

5-3

DJ11 Diagnostic Logic Tests and Fault Location

6-1

DJ11 Engineering Drawings

B-1

DJ11 Signal Glossary

D-1

Customer’s Preference Chart

...

... 3-2

...

... 34

...

... 5-1

...

.. 5-2

... 54

., B-1

vii

...

... 6-1

...

D-2

CHAPTER 1
GENERAL DESCRIPTION

1.1

SCOPE

This chapter provides a general description of the DJ11 Asynchronous 16-Line Multiplexer. Inciuded is a definition
of its purpose in a PDP-11 system, a typical system block diagram, a mechanical description of the unit, and a brief

list of unit specifications of particular interest to maintenance personnel.
1.2

PURPOSE

The DJ11 Asynchronous Multiplexer provides the PDP-11 Unibus with connection to as many as sixteen serial
asynchronous communication lines operating at standard rates of between 75 and 9600 baud. Character lengths used
on the lines can be mixed 5-, 6-, 7-, or 8-level code, with or without either odd or even parity. Stop codes can be
either 1 or 2 units, except on lines employing 5-level codes in which cases stop codes are set to 1 or 1.5 units. Line
parameters are jumper selectable in four line groups with split-speed capability.

1.3

TYPICAL SYSTEM BLOCK DIAGRAM

A typical DJ11 system is shown in Figure 1-1. Note that up to 16 DJ11s can be connected to one Unibus, providing
a maximum of interfacing for 256 serial communications type devices.

PDP-11

PROCESSOR

OTHER

MEMORY

DJ11

DEVICES

o e o 00 .U’: T.O. e o0 oo
16

DJ11

SERIAL
ASYNCHRONOUS

COMMUNICATIONS
INTERFACE

UP TO

|°® :6"

SERIAL
ASYNCHRONOQUS

SERIAL
ASYNCHRONOUS

COMMUNICATIONS
INTERFACE

.UF.’ IO.

SERIAL
ASYNCHRONOUS

COMMUNICATIONS
INTERFACE
11- 1805

Figure 1-1

DIJ11 Typical System Block Diagram
I-1

1.4

OPTIONS

Three DJ11s are provided as standard options; each option is capable ofeither 50- or 60-Hz operation. The options
are listed in Table 1-1 and described below. For characteristics other than those listed, contact DEC Computer
Special Systems.

Table 1-1
DJ11 Options

Characteristics

Variation

DJ11-AA

16 lines (data only)
Input/output EIA

16 lines (data only)

DJ11-AB

No level conversion

DJ11-AC

16 lines (data only)
Input/output 20 mA current loop

The DJ11-AA (Figure 1-2) is a prewired system unit containing all modules to implement a 16-line data-only
multiplexer. EIA level conversion is provided on the interfacing input and output lines. These lines are available on a
passive distribution panel that mounts either on an H960 19-in. cabinet or to a wall. Connections to the panel are
made by Cinch EIA connectors. Interconnecting cables are provided between the system unit and the distribution
panel. These cables provide a positive (ON) voltage to the Data Terminal Ready and Request To Send leads of the
Cinch plugs. Hardware for this option is as follows:

1 7009179 Wired Assembly System Unit
2M7280 UART Card

1 M7279 Receive Silo Card
1 M105 Address Select
1 M7821 Interrupt Control
1 M7285 Hex Mux Control
1 M5901 EIA Level Converter Card
2 BC08S-15 Cables

1 H317-B Distribution Panel
1 M920 Unibus Connector
1 H315 Test Connector

The DJ11-AB Multiplexer is identical to the DJ11-AA except that no level conversion is provided. The system unit is
provided with a TTL interface card that contains two Berg headers and the mating cables; a distribution panel is not
provided. Also, no test connector is provided. Hardware for this option is identical to that listed for the DJ11-AA
except for the following:

1 M5900 TTL Output Card
No Distribution Panel
No Test Connector

BCOBS~-15

CINCH ETA

CABLES

CONNECTORS

NOTE:
Test connector

not shown.

Figure 1-2

DJ11-AA Asynchronous 16-Line Multiplexer

The DJ11-AC (Figure 1-3) is identical to the DJ11-AA except that 20 mA current loop operation is provided. The
passive distribution panel is a different model that provides screw-type connectors. No test connector is provided.

Hardware is identical to the DJ11-AA except for the following:
1 M5902 TTY Level Converter Card

1 H317-A Distribution Panel
No Test Connector

The multiplexer is contained in a single system unit. Module utilization is shown in Figure 1-4. Note that only

functional names are assigned in those locations where the module designation varies with the option. Note also that
a hex card is used; because of this, the unit cannot be utilized with the older PDP-11/20 BA11 boxes. It must be

installed in the newer PDP-11/40 or PDP-11/45 extender box.

1.6

SPECIFICATIONS

Environmental
Operating Temperature Range

+40 to +120°F

Operating Humidity Range

10 to 95% Relative

(without condensation)
Power Requirements

DJ11-AA

DJ11-AB

-15 Vdc

0.250A

1.0A

+5 Vdc

4.7A

5.3A

+15 Vde

0.250A

N.A.

DJ11-AC

1-3

H317-A

BCO8S-15

DISTRIBUTION

CABLES

PANEL

A
M920

NI20NN

M7280

UART CARD
# 1

LEVEL CONVERTER
8 ouT

M7280

UART CARD# 2

(M5900,5301,5902)

M7285 HEX MUX CONTROL

M105

M7821

ADDRESS | INTERRUPT|

UNIBUS

SELECT | CONTROL

MT2T9

RECELE
11-1806

Figure 14

Power Consumption

DIJ11 Module Utilization

35W

Performance

Receivers

Conversion
Levels

Serial to Parallel

5+ 1 Startand 1 or 1.5 Stop
6,7,8 + 1 Start and 1 or 2 Stop
Jumperable in 4-line groups

FParity

0dd, even, or none; jumperable in 4-line groups

Data Rate

Independent of transmitter (split-speed)

Jumperable in 4-line groups
BAUD

TOL

+0.1%

10.1%

110

+0.1%

134.5

+0.24-0.00%

150

+0.1%

300

+0.1%

600

+0.1%

1200

+0.1%

1800

+0.1%

2400

+0.1%

4800

+0.1%

9600

+0.1%

Allowable Input Distortion per Bit
Input Speed Tolerance

Breaks

42% Mark to Space

+5% with at least 1.5 Stop marks

Detection provided

Transmitters

Conversion
Levels

Parallel to Serial

5+ 1 Startand 1 or 1.5 Stop

6,7,8 + 1 Start and 1 or 2 Stop
Jumperable in 4-line groups

Parity

Odd, even, or none; jumperable in 4-line groups

Data Rate

Independent of receiver (split-speed);
Jumperable in 4-line groups;

Same rates and tolerances as listed for receiver
Allowable Output Distortion
Breaks

2.5% Mark to Space + Gross Start to Stop as measured at TTL output

Allowable on any line

Input Requirements/Option

Item
Mark

DJ11-AC

DJ11-AA

DJ11-AB

-15to -3V

0.8V@5 mA

Active Receiver
20 to 30 mA @ 20082

(looptload)
Space

+3 to +15V

2.0V @40 uA

OtoS mA

Passive Receiver
+20 to +30 mA @

2200
+5t0-30mA @
22082

1-5

Input Requirements/Option

Active Receiver

DJ11-AC

Passive Receiver

Item

DJ11-AA

DJ11-AB

Impedance

3to 7k§2

091to 1.2k

4400

22092

NMT 3V

NMT 6V

NMT 16V

NMT 60 us

50 ft up to

25 ft any speed

NMT 50 us

75 — 9.6 kbaud

Low NMT 300 baud
Med NMT 2400 baud

Open Ckt

Voltg.
Max.

Distance

9600 baud

i€ cable

< 2500 pF

Rise & Fall

Times

Speed
Range

NMT 50 us

75 — 9.6 kbaud

Hi NMT 9.6 kbaud

Output Requirements/Option

DJ11-AC

DJ11-AA

DJ11-AB

Mark

-15to-6V

04V @10 mA

Space

+6 to +15V

24V@1mA

NMT 1 mA

Impedance

NMT 300€2

100 to 12582

NMT 800£2

NMT 30V

NMT 6V

22V

Rate

30V/us

60V/us max

Max.
Distance

50 ft up to
9600 baud

25 ftup to
9600 baud

Item

Open Ckt

Voltg.
Slew

if Ccable

< 2500 pF

20 mA @ NMT 200€2
(looptload)

if Ccable

< 500 pF

1-6

Hi NMT 9.6 kbaud

BusLoad

1 unit load to Unibus (1 receiver and 2 drivers)

Max Configuration

16 DJ11s/Unibus

Single Device Throughput

(Theoretical)

43,840 char/sec*

(Processor
Limited

11/05,11/15

11/20)

20,000 char/sec**

(Processor
Limited

11/45)
Interrupts Available

80,000 char/sec
’

= CHARACTER DONE INT — Occurs each time a character appears at output of FI/FO
buffer. Enabled or disabled from the bus. Can be jumpered to interrupt only when there are
5,9, or 17 characters in the silo.

TRANSMIT INT — Occurs when transmit scanner finds a UART buffer empty condition
and
the transmitter control register bit for that line is set. Enabled or disabled from the bus.
LR

vilsaa

Kaa

FI/FO OVERRUN INT — Occurs when FI/FO is full and receiver scanner stops attempting

input to FI/FO. This interrupt vector is same as RCV vector but is separately enabled.

Interrupt Level

Normally 5 as supplied. Can be modified by priority plug.

* Computed on the following:

9600 bits/second/line/direction

7 bits/character
**Based on 50 us processor time per character.

1-7

CHAPTER 2
INSTALLATION

2.1

SCOPE

This chapter contains the procedures necessary to install
the DJ11 Asynchronous 16-Line Multiplexer. It is not
intended to supersede the installation requirements given
in the Customer’s Site Plan. Included is a brief checkout

procedure to ensure proper operation once installation

in Chapter 5 of this manual.

is complete. Detailed test and checkout procedures arc

found

CAUTION

OEMs should not attempt installation until DEC has been
notified and a Field Service representative is present.
Failure
to do so can void equipment warranty.
2.2

CONFIGURATION DIFFERENCES

Installation procedures can vary, dependent upon the particula

r system configuration. For example, the DJ11 can be

supplied with or without a distribution panel. There
are two possible distribution panels supplied which differ
mechanically and electrically. There are variations in level
converter cards and in the type of cable connectors used.

A listing of the basic option designations, with functional differences
, is given in Table 2-1. For a complete list of
differences in nomenclature, refer to Paragraph 1.6, Specifications.

Table 2-1
DJ11 Option Designations

Nomenclature

2.3

Functional Differences

DJ11-AA

EIA level conversion

DJ11-AB

No level conversion

DJ11-AC

20 mA current loop conversion

UNPACKING AND INSPECTION

The DJ11 is packaged in accordance with commercial packaging practices.
the equipment against the shipping list. Any damage or shortages must

the DEC representative. Check all wiring and inspect the modules
2.4

Remove the packaging material and check
be reported immediately to the shipper and

for obvious damage.

INSTALLATION

Because the DJ11 is capable of operating at many different baud
rates and signal parameters, it is necessary to obtain
the customer’s preferences when installing the unit. Obtainin
g this information prior to installation will simplify
installation.

2-1

the first four
The DJ11 allows the user to have independent speeds and parameters in 4-line groups. For example,
300
operate
might
lines may operate at 110 baud, 8 bits per character, with no parity; while the second four linessolderable jumpersat that
baud, 6 level, with odd parity, etc. These parameters are selectable by means of switches and
are part of the M7285 Hex Control Board.

a given condition.
The parameters to be selected by the switches are given in Table 2-2, with the settings toandachieve
the Hex control
on
E82
E80
as
These switches are illustrated in Figure 2-1. Note that the switches are called out IC. If all switches are
open (dot on
an
board and that the switches are numbered 1 through 10, similar to the pins on
must be
settings
switch
The
bits.
stop
2
switch up away from the board), all lines are set for 8 level, no parity, and
in the
used
DJ11s
l
additiona
all
for
made four times for the four groups of lines, and must be set in 4-line groups
installation.

Table 2-2

Parameter Switch Settings

Function

Character Length
NB1
NB2

Parity
NP

POE

Stop Code

Note:

Parameter/Settings

Switch

8 bit/char

7 bit/char

6 bit/char

5 bit/char

open
open

closed
open

open
closed

closed
closed

No Parity

0dd Parity

Even Parity

open

closed

open

1 Stop

closed

NSB

open

closed

2 Stop*
open

An open switch setting is indicated when the white dot on the rocker arm is in the up position, away from
the board.

* For 5-level code, this setting provides 1.5 unit Stop.

Speed selection is set by an array of split lugs mounted on the M7285 board (Figure 2-1). These split lugs should be
wired with no. 30 insulated solid wire.

speed and the lower
The eight split lugs on the left are arranged in two groups of four, the upper group for transmit numbers
are marked
lug
The
order.
in
y
group for receive speed. The line groups are as shown and are not necessaril
on the board adjacent to the lugs.

on the board.
The eleven split lugs on the right provide the selectable speeds. The lug numbers are as they appear
be wired to
must
side
d
right-han
the
on
Figure 2-1 shows the speeds for each lug. To set speeds, one of the split lugs
chapter.
this
in
given
examples
the
for
one or more split lugs on the left-hand side. Figure 2-1 illustrates the wiring
Actual wiring must be determined from the tables in this chapter.
CAUTION

Speed selection must be arranged in descending order, with
line 15 set to the highest speed desired and line O set to the
lowest.

2-2

SPLIT LUG

SPEED

/l/SELECTION BY JUMPERS
DJ11

CONTROL

M7285

BOARD

SIDE !

/’_/.P\'s 12-15 — 12 /o‘/
8-11

TRANS SPEEDY 03 s s .\
RCV

SPEED

—» 13

—» 18

10 «— 110

2:?

—

«—300

8-11 [ 600 | 300

Boil —

<150

2715|1800 | 1800

@2 o+ 4scc

EBO0

@ 3 «— 3600

]

| S8 i

‘L

58 |

NB1

/'/1\

9 9

o 10

\o 4 <— 1800

,7]2

NBI

EES}LINES 0-3

/’/'POE

EEEL

{NBZ‘/’
LINES 12-15¢
NSB

<— 2400

4-7

J’

LINES| RCV [TRANS

E82

LINES 8-11{ ;‘ge
NsB \N\

® 2 <— 1200
6 -« 75

)

( NBI

0-3 —» 19
12-15

0 «— 50

® 11 <1345

Ngs
LINES 4-7
N
E

NP
POE

PARAMETER SELECTION — | ]
BY

SWITCHES

Sys=——

11-1807

Figure 2-1

M7285 Board Showing Jumper and Switch Selection

The example in the figure is wired for the following requirements:
Lines

Receive Speed

Transmit Speed

0-3

4-17

110

8—11

600

300

12—-15

1800

Table 2-3
Sample Customer’s Preference Chart

Speed Selection
Group

Level

Parity

Lines 0—3

Lines 4—7

Odd

Lines 8—11

Even

Lines 12-15

Note:

Stop Bits

XTR

110

Yes

600

300

Yes

1800

1.5

RCV

Split

Have customer prepare one of these for each DJ11 (up to sixteen) in the system. See Appendix D for
blank chart.

2-3

Table 2-3 is given as an example of a Customer’s Preference Chart, which should be prepared prior to installation and
filled out by the customer. From this, an installation chart based on the information in Table 2-1 and Figure 2-1 can
be prepared before installation begins. A sample installation chart, Table 2-4, is based on the examples used in this
chapter.

Table 2-4
Sample Installation Chart
Installation Chart

Lines

Switch

0-3

E80

Pin No.

Position

Jumper Pins

Open

8to 19

19 to 15

4-7

E80

Open

Closed

Open

8to 18
14 to 10

8—11

E82

Closed

Open

Closed

5to 17

6to 13

12—15

E82

Open

Closed

4to 16
16 to 12

Note:

2.4.1

Open

Entries based on examples given in this chapter.

Installation Procedure

To install any DJ11, proceed as follows:

Mount logic system unit into suitable customer supplied box (either PDP-11/40, PDP-11/45, or
PDP-11/35) and attach power to spade lugs located on front (Figure 2-2).
NOTE

Do not install connections to distribution panel at this time.

SIGNAL

COLOR

DCLO

VIO

ACLO

YEL

4°

3
4

-15VDC

BLU

GND

BLK

+5VDC

RED

LTC

BRN

+15VDC

GRY

MATE-N-LOCK

(MALE)
11-1808

Figure 2-2

Power Harness Color Code

Install all modules per Figure 1-2.
NOTE

If DJ11 is last device on the bus, the terminator module
(M930) plugs into slots A4—B4.
A
o

Apply power to the unit, load and run the logic diagnostic (MAINDEC-11-DZDJA-A-PB) on the
equipment gs it is received from the manufacturer. Note that no modifications as to line parameters

should as yet be made, except address and vector jumpers as required. Run the diagnostic for a single pass.
NOTE
All shipments from the factory are set for 8-level, no parity, 2

stop bits, and single speed. Use these parameters in the
diagnostic opening dialogue. (Standard configuration is all
switches off.)

If a failure occurs in this initial run, refer to the diagnostic for type of error and location of probable
fault. Note in the Installation Report that the unit did not function as shipped. (Refer to Chapter 5.)
Set all parameters per the installation chart (Table 2-4) prepared from the customer’s preference chart

(Table 2-3).

When all parameters have been set, rerun the DJ11 logic test; enter the new parameter information for
the opening dialogue. Run the test for two passes or five minutes, whichever occurs first.

When installing the DJ11-AB proceed to step 10. When installing either the DJ11-AA or DJ11-AC,
mount the H317 Distribution Panel at the location specified by the customer. This can be in a cabinet or
along a wall. It must be located at a point where incoming lines can be attached, and it must be within

the constraint of the 15 ft BCO8S Cable.
Connect the BCO8S-15 Cable between the output card in the logic (location 3-A/B on backplane) and
the H317 Panel. On the H317A, interconnect J1 with J1 of the M5902 module, and J2 with J2 of that
same module. On the H317B, interconnect J17 with J2 of the M5901 module, and J20 with J1 of that
same module.

2-5

CAUTION

Cables are neither marked nor keyed and if improperly
connected can damage equipment. On the H317, the rib side
of the cable must be away from the board. On the M5901 or
M5902, the smooth side of the cable must be away from the
board (Figure 2-3).

DISTRIBUTION

PANEL
(o]

’

UNMARKED BERG
RIB SIDE
upP

BCO8S-15

CABLE

NOTE:

This applies to both BCO8S-15
cables on all options.

SMOOTH
SIDE UP

UNMARKED BERG
-

OUTPUT BOARD
11-1809

Figure 2-3

BC08S-15 Polarization

There are jumpers on the distribution panel that must be set. Refer to Figures 2-4 and 2-5 for
particulars. These jumpers have to do with RTS and DTR strapping on the H317B Distribution Panel,
and the Cinch connector strapping on that panel.

10.

11.

When installing the DJ11-AC, the H317A Distribution Panel must be strapped active or passive according
to the various line requirements. In addition, the proper filtering must be set for the particular line
speeds used. This strapping is shown in Figure 2-6. Refer to D-CS-5410262-0-1 for capacitor values.
When installing the DJ11-AB, the output lines can connect to either the DC08-CS Telegraph Interface, a
DM11 Distribution Panel (7008483-0-0), or to some special interface. In these cases, refer to pertinent
documentation for those equipments, to the interconnection diagrams in the print set, and to the 1975

Peripherals Handbook, Page 4-124.

2-6

W\/\J\Mm
H317B

|
s1e \]IL1|
|
K

o (((g(((

C CCCCCCCC

CCCCCee

LINE]| SIG

LEFT-HAND END|

e
| [

[

¢ ceeecece

LINE[S!IG

oo
]

LINE[SIG

LINE|SIG

|DTR

|RTS

|DTR

[RTS

|RTS

IRTS

|RTS

|DTR

[RTS

|IDTR

IRTS

IDTR

|RTS

|DTR

|RTS

|DTR

[DTR

[RTS

|DTR

iRTS

(DTR

|DTR

Figure 2-4

IDTR

|DTR

|RTS

[DTR

|IDTR|

Strapping on H317B Distribution Panel

MODEM

CINCH
CONNECTOR

103E,G,H|

—

BELL ORJ

4 €<2:€

SEC XMIT
RESTRAINT

50 8:3
Oie
28 O15

SEC RCV

10 owu

103F

113A

* | *

300 BAUD

FULL DuUP

IN|

300 BAUD FULL DuP

LAR

300 BAUD ONLY

ORIGINATE

BAUD

¥*| K| *

12 DUP

TwWX

EIA

[IN

JUMPERS PIN 25 704—J

JUMPERS PINN1TO 14 —————J
JUMPERS

PIN 12 TO 16

JUMPERS

12 TO 17

SIGNAL

MODEM

REQ

TO SEND

SEC

TRANS

SEC REC'D DATA

202

represents that signal on the DJI11 dist.

SEC TRANS

panel with jumpers

DATA

E1A

SEC

DATA

RESTRAINT

BUSY

the

RS232-C (SEE BELOW) PUT] IN| IN fouT]

PIN NO.

In special cases, any given signal from

LOW SPEED

CASES

NOTE:

8118

*DON'T CARE

H317B

1121314

300 BAUD FULL DUP

202C,D | 1800

) S

EQUIV

JUMPERS

DESCRIPTION

TYPE

103A

80
020
70 ol9

RIGHT-HAND
END

DATA

—

BELL

MODEM should be put on whatever pin
1,2,3, or 4,

MODEM schematic and
this

compare

Check

REC'D

with

figure.

811B

103 E,G,H
1-1811

Figure 2-5

Cinch Connector Strapping on H317B Distribution Panel

2-7

)

000)

N >:““;“ " BHHHH
LINE®15
NO.

0— 300

PASSIVE

JUMPERS

SPEED

RANGE

[]

FILTERING CHART

LINE NO— 15 14 1:3> @ " @ 9 8
[]

0—+2400

ouT

OVER 2400 | ouT | out

ACTIVE

NOTE: POLARITIES ARE SHOWN FOR ACTIVE MODE. IF STRAPPED FOR

PASSIVE MODE, POLARITIES ARE REVERSED FOR RECIEVE.

11-1812

NOTE: Polarities are shown for Active mode. If strapped for Passive mode, polarities are reversed for receive.
Figure 2-6 Filtering and Mode Strapping on H317A Distribution Panel
2.4.2 Setting Character Done Interrupt Constant

The CHARACTER DONE INT occurs each time a character appears at the output of the FI/FO buffer (or silo). This
interrupt is enabled or disabled from the bus. As described in more detail in Paragraph 4.4.12, this is a result of a
comparator signal in the silo control circuit shown on drawing D-BS-M7279, sheet D11-3 (CHARACTER
AVAILABLE).

These signals, against which the Silo Status Register is compared, are actually shown on the lower left-hand side of
drawing M7285, sheet D2-9, where jumpers W1, W2, and W3 apply ground to signals G REG (04:02). When all three
jumpers are installed, the interrupt occurs on each character loaded in the silo. When cut, a discrete number of
characters must be loaded before the interrupt will occur. The cutable jumpers and associated character delays are as
follows:

Signal

Jumper

Number of Characters

G REG 02

G REG 03
G REG 04

w2
w3

9
17

By cutting any one, that many characters will be loaded before CHARACTER AVAILABLE is generated. By cutting

all three, the sum of all possibilities, or 31 characters, will be loaded before the interrupt is generated on the 32nd
character loaded (FI/FO half full).

2-8

This preference must be solicited from the customer and the appropriate jumpers removed (Figure 2-7).
NOTE

The diagnostic requires that this delay be set for one character.
When running the diagnostic, these jumpers must be replaced
temporarily.

HFEDC
BA
T
11-1813

Figure 2-7

CHARACTER DONE INT Jumpers

CHAPTER 3
PROGRAMMING

3.1

SCOPE

This chapter is intended to provide a basis for DJ11 programming. It does not contain detailed software information.
This data is contained in the pertinent software specifications and documentation for this equipment. Included is a

description of the addressable registers with their formats illustrated, together with a description of the addresses
assigned to these registers and vector information.

3.2

ADDRESSABLE REGISTERS

The DJ11 contains five addressable registers:
a.

Control Status Register (CSR) 76xxx0

Receive Buffer Register (RBUF) 76xxx2

Transmit Control Register (TCR) 76xxx4

Transmit Buffer Register (TBUF) 76xxx6

Break Control Status Register (BCSR) 76xxx4

The addresses assigned to the DJ11 reside in the floating address space of the PDP-11. The DJ11 addresses are
assigned contiguously before the DH11 address in the floating address space.

This floating address space is from 7600105 to 764000g. Each DJ11 requires increments of +10g octal locations.
The unit uses two interrupt vectors, one each for transmit and receive. The CHARACTER DONE INT is at xx0;
TRANSMITTER INT is at xx4. The DJ11 vectors are assigned after the DH11 vectors.

3.2.1

Control Status Register (CSR) 76xxx0

The Control Status Register is a 16-bit register that maintains the status of various control functions in the device.

By their setting or clearing, these bits exert control functions on the device and cause interrupts to be generated.
This register format is illustrated in Figure 3-1 and described in Table 3-1.

TRAN| TRAN|
sTAT
INT| FL/FO|
O-

R/W
BK

RDY ! ENA|

RUN|

REG

R/W

MSTR

TRAN DONE| RCV
INT

BSY | MOS MAINT H/D | RCV

R/W

SEL | EN

CLR| CLR
WO

R/W

R/W
ti-1814

Figure 3-1

Control Status Register Bit Assignments

3-1

Table 3-1
Control Status Register Bit Assignments

Function

Name

Bit

Transmit Ready

Read only bit. Set by the hardware when transmitter clock stops

(TRAN RDY)

on a line whose transmit buffer may be loaded with another

character and whose associated TCR bit is set. This bit clears
when TBUF is loaded, or when TCR bit for line pointed to by

scan is cleared, or by reset. When cleared, this bit enables transmit

clock if MSTR TRAN SC EN (bit 8) is set. When loading a
character into TBUF, ready will clear, but if another line needs
service, flag will reappear in less than 1.3 us from completion of
load TBUF bus cycle.

Transmit Interrupt Enable

Read/write bit, cleared by reset. Must be set for transmit ready to

(TRAN INT EN)

cause an interrupt.

FI/FO Overrun

Read only bit. Set by hardware when FI/FO buffer is full and the

(FI/FO ORUN)

RCV scanner attempts to place a character in the FI/FO buffer.
Cleared on a read of the receive buffer. Note that the receive

scanner does not halt at this line number, but continues to scan
other lines.

Status Enable

Read/write bit, cleared by the hardware. Must be set for FI/FO

(STATUS EN)

ORUN to cause an interrupt.

Not used.

11
10

Read/Write Break Register
(R/W BK REG)

Read/write bit, cleared by reset. When set, causes a read or write
command issued to address 76xxx4 to access the Break Register
instead of the TCR. When clear, addressing 76xxx4 accesses the
TCR.

Not used.
Master Transmit Scan Enable

(MSTR TRAN SC EN)

Read/write bit, cleared by reset. Must be set by program. When
set, enables the transmitter clock to run. When clear, TRAN RDY
(bit 15) is inhibited from setting.

Done

(DONE)

Read only bit. Set by the hardware and cleared by a read of the
RBUF. Sets when character appears at the output of the FI/FO
buffer. Clears only if silo is empty after the read. Will always
toggle low and come back up if FI/FO buffer has another
character. In this event it stays low a maximum of 1 us. Causes an
interrupt if bit 6 is set.

Receiver Interrupt Enable

Read/write bit cleared by reset. Must be set for DONE to cause

(RCV INT EN)

an interrupt.

Not used.

3-2

Table 3-1 (Cont)

Control Status Register Bit Assignments

Bit
4

Name

Function

Busy Clear

Read only bit. Set when the 2 us MOS CLR pulse is in process.

(BSY CLR)
3

MOS Clear

Write only bit. When set produces a 2 us clear pulse to silo and

(MOS CLR)

UART:s but does not affect any other registers. Should be written
to a one only with RCV EN clear.

Maintenance

Read/write bit, cleared by reset. When set, loops all transmitter

(MAINT)

lines into corresponding receivers. In addition, forces transmitter
speed of each group into the receiver clock for each group. As
any split-speed groups are forced to run at transmitter

such,

speeds.

Half Duplex Select

Read/write bit, cleared by reset. When set, forces all lines to

(H/D SEL)

operate in half duplex mode by disabling receivers of lines that

are currently transmitting. Refer to Paragraph 4.4.3.

Receive Enable

Read/write bit, cleared by reset. When clear, prevents receiver

(RCV EN)

from depositing characters in the FI/FO buffer and inhibits scan

of the receiver.

3.2.2

Receive Buffer Register (RBUF) 76xxx2

This is a 16-bit read only register that contains the received character
at the output of the FI/FO buffer. A read of
the register causes the data to disappear and the next character stored
in the FI/FO buffer to appear at the output.

As each character is read, the register is updated with the next character.
a 0. This register format is illustrated in Figure 3-2 and described

g:fig RESRN Foan | PAR

[

LINE NO

[

When the silo is empty, bit 15 reads back as

in Table 3-2.

RCV CHARACTER

7
)

RO
1N-1815

Figure 3-2

3.2.3

Receive Buffer Register Bit Assignments

Transmit Control Register (TCR) 76xxx4 (if CSR10 clear)

This is a 16-bit register that contains a control bit for each channel
or line. Any bit, when set, will stop the scan if
TBMT for that line is set, and will cause an interrupt to be generated
if MSTR INT EN is set. Restart of the clock

occurs when the TBUF is loaded with a character or if the TCR
bit for the line on which the clock

cleared. TCR bits must be cleared only when the scanner is not running,

is stopped is

i.e., when RDY is set or when MSTR TRAN

SC EN (CSR bit 8) is clear. Bits are read/write: the register is cleared
by reset. Line 15 has the highest priority and
line O has the lowest. The format for this register is shown in Figure
3-3.

3-3

Table 3-2

Receive Buffer Register Bit Assignments

Function

Bit

Name

Character Present
(CHAR PRES)

Read only bit. Set to 1 when a character is present at the output
of the silo. Cleared when silo is empty. Note that the last

Overrun Error Indicator
(ORUN ERR)

Read only bit. Set if character had not been removed from UART
buffer before next character was received on that line. Indicates a

Framing Error Indicator

Read only bit. Set if character did not have valid stop bit.

Parity Error Indication

Read only bit. Set if parity error occurred for this character.

11:8

Line Number

Read only bits. Set by program. Indicate the line number of this

7:0

Received Character

Read only bits. Contain the character just received, right-justified.

character is never emptied from the silo even if this bit is cleared.

character was lost on this line.

(FRM ERR)

(PAR ERR)

received character.

(LINE NO.)

(RCV CHARACTER)

CH/L|CH/L|CH/L |CH/L
12
13
14
15

CH/L |CH/L |CH/ZL |CH/L |CH/L | CH/L |CH/L |CH/L |CH/L |CH/L |CH/L JCH/L
o
1
2
3
4
5
6
7
8
9
10
"
T

R/W

}

CLRD BY RESET

1-1816

Figure 3-3 Transmit Control Register Bit Assignments

3.2.4 Transmit Buffer Register (TBUF) 76xxx6

is write only.
This is a 16-bit register used to load characters into the multiplexer for transmission. The low byte
number.
channel
r
transmitte
4-bit
a
Characters to be transmitted are written in the low byte. Bits 11:8 contain
set.
being
15)
bit
(CSR
RDY
TRAN
by
These bits are read only, but only if the transmitter scan clock is stopped
3-4.
Figure
in
illustrated
is
register
These bits indicate the line into which the character is to be loaded. This
11

TRANSMITTER

CHANNEL REG

CHAR TO BE XMITTED

NN N

IF CSR 15

=(1)

11-1817

Figure 34 Transmit Buffer Register Bit Assignments
34

3.2.5

Break Control Status Register (BCSR) 76xxx4 (if CSR 10 set)

This is a 16-bit register containing a control bit for each line. Setting a bit will force a space on that line’s
causing a break condition. This condition prevails until that bit is cleared by the processor. Break timing

output

must be

done by the software using the clock interrupts. All bits are read/write and the register is cleared by reset. This

BK
L
15

| BK
L
14

[ BK
L
13

| BK
L
12

| BK | BK | BK
L
L
L
11
1C
S

BK | BK
L
L
8
7

BK | BK
L
L
6
5

BK | BK
L
L
4
3

| BK
L
4

| BK | BK
L
L
i
o
J

R/W
4
i

CLRD BY RESET
11-18i8

Figure 3-5

Break Control Status Register Bit Assignments

3-5

CHAPTER 4
DETAILED DESCRIPTION

4.1

SCOPE

This chapter provides a detailed description of the DJ11 Asynchronous Multiplexer. The discussions
in this chapter
are

supported by a complete

set of engineering drawings contained in a companion volume entitled DJ]]

Asynchionous Multiplexer Engineering Drawings.
4.2

FUNCTIONAL BLOCK DIAGRAM DISCUSSION

The DJ11, shown in Figure 4-1, comprises twelve basic functional blocks: Selection Logic, Interrupt Logic, Internal
Register Logic (RBUF, CSR, TCR, BCSR, and TBUF), Universal Asynchronous Receiver/Trans
mitter (UART),
Transmitter Control Logic, Receiver Control Logic, Clock Logic, Maintenance Mode Logic,
Bus Drivers and
Receivers, Break Generation Logic, Level Conversion, a First In/First Out Buffer, and a Unibus
Transceiver. As
shown in the figure, a common level conversion board (when used) applies 16 communication line interfaces
to 16
individual UARTSs which, by selection, feed a common set of logic for the data transfer to the Unibus.

The selection logic determines if the DJ11 multiplexer has been selected, which line has been selected,
and what

type of operation (transmit or receive) is to be performed. It permits selection of one of four internal registers
and
determines if the register is to perform an input or output function.
The interrupt logic permits the multiplexer to gain bus control and perform a program interrupt. Either the

receiver

or transmitter can issue an interrupt request. The priority level of a bus request (BR) can be changed by the user.

Communication line priority is fixed and is arbitrated within the DJ11

logic in ascending order by line number.

Five internal registers, addressable by the program, provide data transfer, command and control, and
status

monitoring functions for the multiplexer. Transmitter control logic provides necessary input control signals

from the
UARTSs when they are used to convert parallel data from the bus to serial data required by the external
lines.
Receiver control logic provides necessary input control signals from the UARTs when they are used to convert
serial
data to the parallel data required for transmission to the Unibus. The buffer registers are used to double buffer
the

data to and from the Unibus. The break generation logic permits the transmission of a continuous “break” on any of

the 16 lines and maintains a status of those lines.

The UARTSs perform the necessary serial-to-parallel or parallel-to-serial data conversion, supplying control and error
detecting bits. There is a separate UART for each line. They are selectable from within the DJ11.
The First In/First Out Buffer (FI/FO or silo), provides a sequential accumulation of up to 64 words for transmission
to the Unibus. Each word contains not only the data but also the line number on which it was received, error bits,

and an indication of whether or not that character is valid. Loading is at the top, and readout to the bus is from the
bottom; each character moves down to the output as a character is removed.

Clock logic determines the clock frequency and, therefore, the baud rates for the transmitter and
receiver sections of
the UARTs. Thirteen baud rates are derived from a single crystal and distributed to the various
UARTSs. The
frequencies distributed are hard-wired in 4-line groups, settable at installation time by swit~hes and jumpers.

4-1

PARALLEL

DISTRIBUTION

BUS

BUFFER
RECVR

FI/FO

DRIVERS

BUFFER

(R BUF)

PANEL

:
D<15:00>

¥
| TRANSCEIVER

SEL 2

1A< 17: 03;,%%5%%
ADDRESS
sng:cnon -t
:

#0
||

L
E

vE
L

INTFX paiNE O
COMM

U
A

YN | LooP
R

|
I

S
'

INTERRUPT
CONTROL |e
LOGIC

S | mant

SEL|

INTFX

ouT

1¢

sTatus { !B

U
| LINE# TRAN RDY S

BREAK
|
STATUS
(BSR)

aRANS

PARALLEL OUT

(TBUF)

LA R —

COMM | LINE 15 TM M

[

» REGISTER

LOGIC

TRAN

(TCR)

CLOCK

(CSR)

TRANS.
CONTROL

BBSY,SSYN | p

SACK BR-BG INTR | p
t
s
I
!

STATUS | |

‘

|
SEL
0
CONTROL

[

SEL
4

LOGIC

|
BUS

RCVRS

D<15:00>

‘
,

UARTS 1-15

1-1819

Figure 4-1

DJ11 Functional Block Diagram

Maintenance mode logic performs a closed loop test of the DJ11 control logic by tying the serial output of the
transmitter into the receiver input and forcing the receiver clock to be the same frequency as the transmitter clock.
The bus drivers and receivers are part of the Unibus transceiver logic that interfaces the Unibus to the DJ11 buffer
registers. The level conversion logic comprises one of three different arrangements in which the levels are converted
for use with EIA levels, a 20 mA current loop environment, or straight TTL output conditions (no conversion).
Finally, jumper arrangements are provided on the distribution panels to adapt the DJ11 to various line conditions.
By jumpering, active or passive operation can be implemented, response characteristics can be modified, and current
limiting resistors can be added.

4.3 DETAILED BLOCK DIAGRAM DISCUSSIONS
4.3.1

Receiver Section

The DJ11 receiver section contains a separate UART for each of the 16 lines. The UART provides serial assembly of
the characters, parity error checking, break detection, and overrun detection. The UART is double buffered,
allowing a full character time to remove the received character to the hardware buffer. A complete description of the
UART is given in DEC Specification 19-10459. The UART uses a 16x clock that provides a 42 percent distortion
margin on incoming characters.

4-2

ERROR BITS
LINE 0<3>
UART

ERROR BITS

LINE O

LINE 1<3>

§1

ERROR BITS

LINE 15<3>

ERROR BITS <3>

LINE # < 4>

mux

LINE #

ERROR BITS

DATA BITS

;JF;'?R

OATA IN

D <16>

Bus

CHARACTER<8> | 16 X 64

SERIAL

DATA

IN O

AVAle%Lg
L

DATA AVAIL
EoC

5
4.....7

CLOCK DATA

LOAD

GENERATOR

DUPLEX

PULSE

DONE

TIMING

—t

GaATE

INTR

L
EOC

EOC

Mux

DATA

UART
LINE 1

SEL

AVAILABL.E 1

<4>

—

<X>=# OF BITS

—I

ENABLE

4BIT

DATA

COUNT

ENABLE]

SERIAL

IN 1

DATA IN

DATA AVAIL

M105

INTR

EOC §

BUFFER

INHIBIT
HALF

LNeS | Mux

DATA EN

HALF DUPLEX

SELECT

|RrRBUF

DRIVERS

A<18>

SEL|

¢ | DECODE

EOC
DATA EN

e | DECODE

CLEAR DATA AV

RESTART | SCANNER

ENABLE RCV

SCAN

Efifa{E‘J

\/L

(2]

- 000

HALT
SCAN

11-1820

Figure 4-2

Receiver Detailed Block Diagram

Figure 4-2 is a detailed block diagram of the DJ11 receiver section. The UART is scanned by a receiver scanner that

runs at a nominal 1 mHz. This scanner sequentially checks for a Data Available flag. When a flag is found, the
scanner stops and the character is automatically stored in a 16 bit X 64 word FI/FO buffer.
If space is available in this buffer, the character is written into it. The character is then automatically propagated
down to the first available open slot where it remains until a character is removed from the output side. As each
character is removed, remaining characters propagate toward the output.

The format of the FI/FO is shown in Figure 4-3. Data bits are stored in the low byte or first 8 bits, the channel
number is stored in the low 4 bits of the upper byte, with bits 14:12 holding the status bits for parity, overrun, and
framing errors. Bit 15 is used as a Valid Entry Present bit.

UPPER BYTE

LOWER BYTE

13
ERRORS

CHARACTER _J
PRESENT

FI/FO

OVERRUN

LINE

NO.

)

DATA

o
>

L PARITY ERROR
FRAMING

ERROR
tt-182t

Figure 4-3

FI/FO Format

Once any character reaches the output of the buffer, a CHARACTER DONE INT occurs (normal jumpering), and
the computer must service the interrupt and read the buffer to obtain the character. As the character is read, the

FI/FO buffer output is incremented, causing the contents to propagate down, thus providing the next character
stored in the buffer,
The software services the character Done flag on either an interrupt or flag checking basis. In either case, characters

are serviced out of the FI/FO buffer; as each character is read from the buffer, the next character present is made
available at the output.

The service routine should process all characters in the FI/FO to avoid the overhead involved in entering and leaving
the service routine. In the block diagram of Figure 4-2, note that the scanner state is not capable of being altered or

read by the program. The program deals only with the output of the FI/FO buffer.
The multiplexer has a half duplex capability. By setting a bit in the CSR, the receivers of any lines that are currently
transmitting are disabled by inhibiting the deposit of the assembled characters into the silo. This is done by means of
the EOC signal from the UARTSs.

4.3.2

Transmitter Section

The transmitter utilizes UARTS for parallel-to-serial conversion of each line. A detailed block diagram of this section
is given in Figure 4-4. A single 16-bit TCR is used to enable transmitters on a per line basis. Setting the bit for a
particular line causes the “pseudo-scanner” to stop at this line if TBMT (Transmit Buffer Empty) is set and sets the

TRAN RDY bit. If the TRAN INT EN bit is set, an interrupt is generated. Note that if all TCR bits are clear, the
TRAN RDY bit will be clear. This is a departure from conventional single line unit ready flags.

4.4

(16)

(3)

g 333

(16)

UART

TRAN CONTROL REGISTER
0

DATA
LINE O

«—]

TBMT

F‘

::::)__SERIAL
oUT 0

TRAN

] ENABLE

[ TewT s

gaTA

J. ® &6 © o o 0
DATA

HOLDING

SAMPLE

r‘:

® ® o 060 000 o

0 oTM | oate

GATES

UART
)

INTR

PRIORITY

SERIAL

q::::>__—OUT1

LINE
1

ENCODER

—

DECODER

LINE # (4)
-

[——

TBMT

g?TA

)

[]

°
]

°
.
L]

TRAN READY

TRAN

READY

etc.

(18)

SEL
6
HALT

SCAN

MI105
ADDRS

SELECT

SEL O

»!

MASTER|
ENABLE CLOCK
TRAN
SCAN

TRAN
CLOCK
¢

(16)
¢

J,
TO

OTHER

‘

ol
BREAK

eso oo

UARTS
11-1822

Figure 44

Transmitter Detailed Block Diagram

If the TCR bit is set for a particular line, the “pseudo-scan” will halt when it detects the AND condition of TCR and
TBMT (from the UART) for this particular line, and set Ready. If TRAN INT EN is set, an interrupt will be
generated. The program then reads, from the high byte of TBUF, the line number to which the channel number
points. The program then loads the appropriate character into the low byte of TBUF, and the hardware
automatically clears Ready and begins searching for another AND condition of TBMT and TCR.

The “pseudo-scan” is really a 16-level priority encoder. A clock samples the state of the 16 AND gates for TBMT
and TCR. The output of these gates is presented to the priority encoder, which provides the channel number of the
highest priority line needing service. The clock then stops and waits for the character to be loaded. Once loaded, the

clock is restarted. New samples are taken every 400 ns and presented to the priority encoder. If two lines come up at
the same time, the encoder will put out the line with the highest priority. Line 15 has the highest priority, line 00
has the lowest.

When operating in interrupt mode, the program should service the channel at which the clock stopped; but, before
leaving the service routine, it should check to ensure that no other lines have TBMT or TCR flags up. This procedure
reduces the number of times that the service routine must be entered, thereby reducing overhead per character.

Breaks can be transmitted on any line by asserting the corresponding bit in the Break Status Register (BSR). This
pulls the output line to a space and holds it there until the bit is cleared. Timing of the breaks must be done by the
software.

4.3.3

Address Selection Logic

The address selection logic (drawing C-CS-M105-0-1) decodes the signals that determine which register has been
selected and whether it is to perform an input or output function. Jumpers on this logic can be altered so that the
module responds to any address within the range of 760000 to 767777.

Although these addresses have been selected by DEC as the standard assignments for the DJ11, the user may change
the jumpers to any address desired. However, any MAINDEC program or other software that references these
standard assignments must be modified accordingly if other than the standard assignments are used.

The first five octal digits of the address indicate that the DJ11 has been selected as the device on the Unibus to be
used. The final octal digit, consisting of address lines A02, AO1 and A0O, determines which register has been selected
and whether a word or byte operation is to be performed. The two mode control lines, COO and CO1, determine

whether the selected DJ11 register is to perform an input or output operation (provided the selected register is a
read/write register).

A block diagram of this module (M105) is given in Figure 4-5. Note that IN and OUT are always used with respect to

the master (controlling) device; thus an OUT transfer is a transfer of data from the Unibus to the DJ11 and an IN
transfer transfers data from the DJ11 to the Unibus. Inputs consists of 18 address lines, A(17:C0), 2 bus control
lines (1:0), and a master synchronization (MSYN) line. Decoding of lines A(12:03) is determined by jumpers. When
a line is jumpered, the address selector searches for a 0 on that line. If none exists, the selector searches for a 1. Lines
A(17:13) must be all 1s thereby specifying an address within the top 8K byte address bounds for device registers.
Note that in the DJ11 five internal registers are selected by four addresses. The duplicate address 75xxx4 selects two
registers (TCR and BSR), depending on the state of bit 10in the CSR.
The Device Register select address format is given in Figure 4-6.
4.3.4

Interrupt Control Logic

The interrupt control logic permits the DJ11 to gain control of the bus (become bus master} and perform an
interrupt operation. Jumpers on the logic can be altered so that the logic has a normal vector address within the
range of 000 and 776.

4-6

The interrupt control logic consists of a dual-input request and grant acknowledge circuit for establishing bus
control. One input, A, is connected to the receiver section and provides a vector address of xx0. The other, B,
connects to the transmitter section and provides a vector address of xx4. The two circuits operate independently;

however, if simultaneous interrupt requests occur, the receiver section has priority over the transmitter section.
NOTE

The final octal digit of the vector address is not affected by
the jumpers;

therefore,

regardless

of the vector address

selected by the jumpers, the final octal digit is always 0 for

receive and 4 for transmit.

The block diagram for this module is shown in drawing D-BS-DJ11-0-7.

SSYN INH L

£1
BUS

BUS MSYN L

SSYN

CONTROL

BUS A17 L

TO BUS

SELECT

K2
E:

R
E

_m_ S
0“ O
—_—Om —O 10 %
—3—0 o Oo—
—zF
—09

O—

—%1—o~—06

0—

—\’2-0'—04

O—

BUS A3 L—=(—0
3

SELECT
LINES

SELECT

o—

—-g—05

O0—

___q' —O0

)

SELECT

3
E

—5 908 o

SIGNALS

,—_J*_

JUMPER FOR
A O,NO JUMPER
FOR A 1

BUS A@2 L

:11

BUS A@1 |

BUS A0L
BUS

BUS

Co
L

—2
T3

Ne— OUT HIBH H \ caTing

GATING

CONTROL

OUT

LOW

SIGNALS

INH

CoTE:
L2

+5V A2

MIO5

GND C2,
T1

ADDRESS

SELECTOR

resT

POINT

EXT. GND

— ] (MUST BE GROUNDED)
11-0046

Figure 4-5

M105 Address Selector Block Diagram

SELECTED

BY JUMPERS

OO0

]

—

MUST BE ALL 1's

DECODED FOR 1 OF 4 REGISTERS «—
BYTE CONTROL

11-0029

Figure 4-6

Device Register Select Address Format

4-7

4.3.5

Distribution Panels H317A/B

The distribution panels (shown as a dotted line in Figure 4-1) supplied with the DJ11-AA and DJ11-AC are used to
fan out the lines to the communciation interfaces. Neither panel type requires power. They are completely passive.
Data is sent from the DJ11 to the distribution panel with its level conversion already performed. Interconnection
with the panel is by two flat cables that terminate in Berg connectors. The panel fans out the lines either to
individual Cinch EIA connectors on the H317B, or to 4-wire terminal strips on the H317A. Note that the PC board
for the TTY (H317A) panel contains several components of the TTY circuit.

Several jumper selections are available on the distribution panels. In the EIA case, the DTR lead and the REQUEST
TO SEND lead will normally be strapped to a positive or ON voltage. This strapping can be removed on a per line
basis. Removal would be in order, for example, if the panel was used for a full modem control arrangement in which
the modem control signals were combined with the data signals on the distribution panel. This is done with the four
additional Berg connectors on the H317B panel. The modem control signals must be presented at the distribution
panel already converted to EIA levels.

On the H317A panel (20 mA current loop operation), two jumpers are used to convert the receiver portion of the

TTY circuit from active to passive operation. The active receiver is required for Teletypes ® and similar devices that

merely provide a switch opening or closing for a binary 1 or 0. The disadvantage of this mode is that the signaling is
single-ended and noise introduced on the line can cause errors. When wired as a passive receiver, the device has
common mode rejection, since any noise introduced on the wires appears on both wires and hence causes no net
change in the current through the diode (Figure 4-7).
NOISE

COUPLED TO WIRE CAUSES

CURRENT TO FLOW AND ERRORS RESULT.

I
|
OPTICAL

COUPLER

[ 77v TrRaNs.|

= |

x
ct

*
c2

T
=

=
|

COUPLER

{

]

|_____|

ACTIVE

—— _——"

| LOGIC DRIVE

Howi

|
l

|
|

ADDS. NO NET

|
CURRENT
|
|
l
R
[
|
| \
|
|
PASSIVE |
|
|
|

|
|
[ RCVR _JH317-A|

[_ACTIVE TRANS. |

*SPEED RANGE ADJUSTMENT
11-1823

Figure 4-7

Active and Passive Receiver Wiring

® Teletype is a registered trademark of Teletype Corporation.

4.8

The H317A also contains two other jumpers for each line. They are used to insert capacitors to slow the response of
the circuit. There are three speed ranges. The low speed range should be used for 300 baud and below. Both
capacitors are left in for this range. Filtering adds 10 percent distortion maximum to a 300 baud signaling rate. The

medium range is used for 2400 baud and below. Capacitor C1 is removed, and the filtering will cause a 10 percent

distortion maximum to a 2400 baud signal. The high range occurs when both capacitors are removed and should be
used above 2400 baud (Figure 4-7). For the higher speed ranges it is preferable that the remote device be the current
source so that the DJ11 receiver can be strapped as a passive receiver with common mode rejection.

4.3.6

Maintenance Logic

When set, the Maintenance (MAINT) bit (bit 2 of CSR) loops back all 16 lines internally. If split speed is selected on
any or all groups, the transmitter speed is forced into the receiver so that loop back can occur. This can be seen on

any of the interface card schematics. The signal MAINT (H), generated on D-CS-M7285-0-1, sheet 5, is used to
switch 74157 or 8266 Multiplexers and thereby bring in the output signals from the transmit side to the second set

of gates on those multiplexers. This feeds the outputs to the inputs. In the clock (D-CS-M7285-0-1, sheet 10),
MAINT (H) forces an 8266 Multiplexer to feed TRANS SPEED to RCV SPEED outputs, thereby tying the receive
speed to the transmit speed.

UNIBUS

’x

N
BUS D (15:00)

D2-2

!\
/

/%838\

XCVR

74153

MUX

RCV BUF

BD (07.00)

(7:0)

Di1-2

D2-6 «

Fi/FO

uct/2

RCV DATA
1-8

74175

)

QUAD

BUF RCV

DATA

TRAN

DATA
|

1-8

TRAN

DATA

PARALLEL
PARALLEL

D3-X
|

!
[

!
UART

RCV| XTR
4

]
]

SERIAL
IN 00-15 —ot—
|

D33-2]

L SERIAL OUT 00-15

t1-1824

Figure 4-8

DJ11 Data Path

4-9

4.3.7 Universal Asynchronous Receiver/Transmitter (UART)

The UART, a fundamental part of DJ11 operation, converts serial data to parallel data and parallel data to a serial
bit stream. The data path of the DJ11 is illustrated in Figure 4-8. Data from a single communications line is traced
through to the Unibus and back through the principle hardware blocks in that path, indicating the drawing numbers
on which those blocks are located in the block schematics. The transceiver shown takes the place of the receiver and
transmitter buffers shown in Figure 4-1. This device (8838) is described in more detail in Paragraph 4.4 (under the
description of drawing D-CS-M7285-0-1, sheet 3).

As can be seen from the figure, serial data in from the line is fed to the UART and from there transferred, in parallel,
to the FI/FO where the line number is inserted in the parallel character together with error information and a bit for
validity. The output of the FI/FO is then multiplexed to the transceiver and out onto the Unibus when the control
handshaking sequence has been satisfied.

Information from the Unibus is fed through the same transceiver to a Quad F/F register from which it is applied, in

parallel, to the transmit side of the UART (dedicated to that line) and then out on the serial line.

Sixteen separate UARTS are assigned, one to each line, in the DJ11 (Figure 4-9). The Unibus data lines are applied to
all UARTs, for both DATI and DATO, and selection signals are used to select the proper UART (line number) as
determined prior to the transfer transaction.

# 00 RCV LINE CONTROLS IN

RCV DATA (8:1) TO MEM.

le—— SERIAL IN LINE 00

,/«5ARALL/E/I; ouT
7

TRAN DATA {8:1) FROM MEM.

l— SERIAL QUT LINE OO
.

4
|

}
T

*
.

# 07 RCV LINE CONTROLS IN

- —--UART----

PARALLEL IN

#00 TRANS LINE CONTROLS OUT

o
jla—— SERIAL IN LINE O7

|- —-UART--|l—» SERIAL OUT LINE O7

l——o-#O? TRANS LINE CONTROLS OUT
#08 RCV LINE CONTROLS IN

je—— SERIAL iIN LiNE OB

- --UART-SERIAL OUT

LINE O8

\——4#08 TRANS LINE CONTROLS OUT
#15 RCV LINE CONTROLS IN

le—— SERIAL IN LINE 15

| __UART--|—»

SERIAL

OUT

LINE

\———o #15 TRANS LINE CONTROLS OUT
11-1825

Figure 49 DJ11 Multiple UART Functional Block Diagram

4-10

In order to make the UART universal, the baud rate, bits per word, parity mode, and number
of stop bits are
selected by external logic circuits (external, i.e., from the UART).
The UART is a full duplex receiver/transmitter. The receiver section accepts asynchronous serial

binary characters

and converts them to a parallel format for transmission to the Unibus. The transmitter section accepts

characters from the bus and converts them to a serial asynchronous output with start and

parallel binary

stop bits added.

All serial characters contain a Start bit, five to eight Data bits, one, one and a half, or two Stop bits,
and a Parity bit,
which may be odd, even, or turned off completely. The Stop bits are opposite in polarity to the Start
bit.

Both the receiver and transmitter are double buffered. The UART internally synchronizes
the Start bit with the
clock input to ensure a full 16-element (clock periods) Start bit independent of the time of data loading.
Transmitter
distortion (assuming perfect clock input) is less than 2.5 percent on any bit up to 10 kbaud. The receiver
strobes the

input bit within +8 percent of the theoretical center of the bit. The receiver also rejects

than one-half of a bit time.

any Start bit that lasts less

Figure 4-10 is a block diagram of the UART receiver. When the receiver is in the idle state. it samples the serial input
line at the selected clock edges after the first mark-to-space transition of the serial input line. If the first sample is a

mark (high), the receiver returns to the idle state and is ready to detect another mark-to-space transition. If,
however, the first sample is a space (low), then the receiver enters the data entry state.

STATUS
WORD
ENB

DATA BITS

AND GATES

BDO7

RD7

BUF

RDO

DATA

ENABLE ——

AND GATES

(RDE)

BDOO

‘

IUART

STATUS

reset IREGISTER

DATA

AvaeLE |

HOLDING
[

SET

OVERRUN
c

PARITY

RAME

/
SHOWN AS
SINGLE BUFFERING

SERIAL
DATA
INPUT

CLOCK

INPUT

RECEIVER SHIFT REGISTER

T
EVEN
PARITY
SELECT

CONTROL LOGIC
T

NO
PARITY

DATA AVAILABLE

P‘;R';LGEZ':;ZR
FRAMI

NB2
NBI
NUMBER OF
BITS/CHARACTER
11-1350

Figure 4-10

UART Receiver, Block Diagram

If the receiver control logic has not been conditioned to the no parity state, then the receiver checks
the data bits plus the parity bit following the data bits and compares it with the parity sense on the

the parity of

parity select line.

If the parity sense of the received character differs from the parity of the UART control logic,
then the receive

parity error line goes high and causes the parity error bit in RBUF to set.

If the receiver control logic has been conditioned to the no parity state, then the receiver takes no action with
respect to parity and maintains the parity error line in the false (low) state. When the control logic senses a parity
error, it generates a P ERR signal. The DATA AVAILABLE signal updates the parity error indicator.

The receiver samples the first Stop bit that occurs either after the Parity bit, or after the data bits if no parity is
selected. If a valid (high) Stop bit exists, no further action is taken. If, however, the Stop bit is false (low), indicating
an invalid Stop code, then the UART control logic provides a framing error indication. The status of the framing
error bit can also be read from the RBUF.

Because the serial input from the line is shifted into the UART a bit at a time, the occurrence of a Stop code
indicates that the entire data character has been received and shifted into the receiver shift register. After the Stop
bit has been sampled, the receiver control logic parallel transfers the contents of the shift register into the receiver
data holding register and then sets the data available (R DONE) flag.

The data available signal also functions as the clock input to the FRAME ERR, PARITY, and OVERRUN flip-flops
in the UART status register. At this point, the DA flip-flop is set, the OVERRUN flip-flop is clear but has a high on
the data input because of the output from the DA flip-flop, and the PARITY and FRAME ERR flip-flops are set or
cleared depending on the signal (true or false) strobed in from the control logic.

An Overrun condition indicates that another data character is being sent to the UART holding register before the

previous character has been transferred to the DJ11 receive buffer (FI/FO).

Whenever the serial input line goes from a mark (high) to a space (low) and remains at a low level, the receiver shifts
in one character, which is all spaces, then sets the FRAME ERR indicator and waits until the input line goes high
before shifting in another character.

A block diagram of the transmitter portion of the UART is shown in Figure 4-11. When in the idle state, the
transmitter sends out a mark (high) on its serial output line. When data is transmitted, a parallel character is placed
on the bus data lines and strobed into the UART transmitter data buffer by means of the data strobe signal. The
time between the low-to-high transition of the data strobe and the corresponding mark-to-space transition of the
serial output line is within one clock cycle (1/16 of a bit time) if the transmitter has been idle. The data strobe is
used to strobe a character from the Unibus into the TBUF.

After the data has been loaded into the UART data buffer, it is transferred to the transmitter shift register under
control of signals from an encoder that selects the format determined by the control logic. This permits selection of
either parity or no parity, the type of parity, the number of Stop bits, and the number of Data bits per character.

The transmitter logic converts the parallel character from the Unibus into serial output that isin a format selected
by the control logic.

Whenever the transmitter data buffer is loaded while the previous character is being shifted through to the output
line, the Start bit of the new character immediately follows the last Stop bit of the previous character.

When the data strobe loads the UART data buffer, the DJ11 transmitter buffer is unloaded. Therefore, the data
strobe sets the condition TBMT to yield a signal that indicates transmitter ready. It is this signal that is ANDed with
TCR and allows the clock to stop and set TRAN RDY (CSR bit 15).

4.4

LOGIC DISCUSSION

The discussions in this paragraph are referenced to the block schematics that are part of the manufacturing drawing
set supplied with the equipment and part of the manual entitled DJ11 Engineering Drawings. In these discussions,
each sheet of each drawing is discussed separately, in numerical order, as they appear in the schematics. Discussing
the circuits in this order does not imply a logical sequence.

4-12

NO. STOP BITS—
EVEN PAR. SEL.—2w|
35
NO PARITY

BITS/CHAR. 37,38

...
LOGIC

PAR

GEN

fsoo7——g—
32

ENCODER

soos—jfiu

DaTa
BITS | 8004 23,

oo e

8002 =
27
8001
26
| BDOO

DATA

STROBE

QUTPUT
LOGIC

BDO6E —

XMTR

DATA

INPUT —

(EOC)

SHIFT

TRANSMITTER BUFFER EMPTY

22 TRANSMITTER
READY

(XRDY)

GENERATOR

{1-1351

Figure 4-11

BUF AO2

BUF AO1

UART Transmitter, Block Diagram

8838

QUAD

BUS

TRANSCEIVER

TO/FROM

UNIBUS

“—* 8uUs D

M105 L 2

(15-00)
L

]

F—i__/

o)
TBR(15:00)

H —{ D

TCR{15:00)

H —— ¢ 74153

» BD(15:00)H

TO DJ1H

DUAL

RCV BUF (15:00) H — B yixs

.
L]

CSR(15:00)

H — A

BUF AO1 (H)
READ

_SHIFT

LOAD

1 \ine

- gng%ETE"

PUR

TBMT
F/F

CLOCK

SERIAL

TM OuTPUT

TBR (H)

BUF A02 (L)

74153

(1)= S1=BUF AO1 (L)+READ TBR (H)
« BUF A02 (L)
(1)=SO=BUF AQ2 (H)

SO | S1|

ouT

110

11-1826

Figure 4-12

DJ11 Mux Bus Interface

4-13

4.4.1

Bus Interface (drawing D-CS-M7285-0-1, sheet 3)

The logic on this sheet comprises the data bus interface. This is made up of Dual 4:1 Multiplexers (74153s) with
each pair feeding Quad Bus Transceivers (8838s). Figure 4-12 is a functional block diagram of this logic showing that
16 bits each from the TBR, the TCR, the RBUF, and the CSR are multiplexed out onto the Unibus through the
transceivers as a function of BUS AO1 and A02.

Note that pins 7 and 9 on all transceivers are grounded so that they are enabled all the time. Signals out to the
Unibus are gated on and off by the control logic at the 74153 Multiplexer. The presence of an IN signal at DM2
indicates a DATI to the master, signaling that data from some register is to be presented to the bus. Data from the
bus is received, for example, as BUS D15 L at pin 4 of the 8838 at E1. This is fed back out of the transceiver as
BD15 H from pin 6.

4.4.2

Output Interface and TBR, TCR Registers (D-CS-M7285-0-1, sheet 4)

This logic, simplified in Figure 4-13, comprises the two major registers in the DJ11, the TCR and TBR. These
registers are fed by BD (15:00) H, one bit for each line in the installation. These registers are byte-operable with one
gate enabling the high byte, and the other gate the low byte. The registers are made up of 74175 Quad D-Type
flip-flops. Both registers are addressed at the same location (76xxx4). Selection is made by CSR bit 10, used on
sheet 5 to generate READ TBR (H), when set, and READ TCR (H), when clear. The registers are cleared by RESET,
and the byte control is by OUTLOW or OUTHIGH generated on drawing D-BS-DJ11-0-7.
OUT LOW (H)

READ TCR (H)

BD 00 (H)

.
.
.

BD 07 (H)

[

74175
QUAD-D

.
.

.
®

TCR

OUT

74H1

HIGH (H)

———————— TCR 08 (H)

p
.
.

8D 15 (H)

& TCR 07 (H)

(LOW)

]

BD 08 (H)

+ TCR 00 (H)

74175
QUAD-D

TCR

(HIGH)

o
.

.
L]

TCR 15 (H)
p—————#

—* TBR 00 (L)

24175

» TBR 00 (H)

TBR

(LOW)

:
.

QUAD-D

» TBR 07 (L)

®—» TBR 07 (H)

[

S——
T Y- R

74475

QUAD-D

RESET (L)

TBR

(HIGH)

—‘—‘.—FTBR 08 (H)

|—
= TBR 15 (L)

———
TBR

15 (H)

OUT LOW (H)
SEL 4 (H)

OUT HIGH (H)
READ TBR (H) ——4

—

TM\

11-1827

{7an11

Figure 4-13 DIJ11 Interface and Registers TCR and TBR
4-14

4.4.3

H/D Gating and CSR Bits (D-CS-M7285-0-1, sheet 5)

This logic is simplified in Figure 4-14. This print contains two sections, the CSR bits on the right and the half duplex

gating logic on the left.

The CSR bits are set by bits BDxx (H), as shown, into two 74175 Quad-D Registers that are read/writeable. The
register is byte selected by OUTHIGH and OUTLOW in combination with SEL 0 (H). They are cleared by RESET.
The logic on the left-hand side of the sheet is concerned with half duplex selection. In the DJ11, the term “half

duplexTM means that if any line is transmitting, that line is inhibited from receiving for that period. This mode is
selectable on a 16 line basis, i.e., either all 16 lines are half duplex or none are.

CSR

BDO8 —

10 —
12—

—— MASTER TRAN SCAN EN

74175

L peap TER

QUAD-D
¢
}— sTATUS EN

i4 ——]

OUT HIGH

——- TRAN INT EN

\
WRITE CSR HIGH

—__/
RESET
SEL O

74151

WRITE CSR LOW

o]
BDOO —
o1 —{

02—

D
—- RCV

74175

QUAD-D
ff

|—

MAINT

H/D SEL

—— RCV INT EN

RCV SCAND H

—

EOC LINE 00 ————+]
7%':?'
X
MU

olo|o]1

oloji}o

OlO(1

ojf1]0f{o0

OJ1

o111

10100

LINE

|
_—|o|1|t]|o]|

0|1

Oj0|0}|O

[

etc.

EOC LINE O7

[]

RCV SCAN A

[

RCV SCAN B

;Do—fi

RCV SCAN C

INHIBIT

SILO LoAD
A

EOC LINE 08 "
[]

74151

MU
X

EOC LINE 15

RCV SCAN D (L)

T
t1-1828

Figure 4-14

DJ11 H/D Gating and CSR Bits

4-15

When this mode is imposed on the DJ11, the UART is permitted to assemble the received character but that
character is never loaded into the FI/FO. The end of character signal (EOC H), generated by the UART (M7280

module), is used to indicate that a given line is transmitting. The combinations of RCV SCAN (D:A) are used to
select the particular line on 74151 8:1 Multiplexers. The resultant output is ANDed with H/D SELECT (H) to
generate INHIBIT SILO LOAD (L). This signal, in turn, is used on sheet 8 to disqualify the 74H11 gate at E41 and
thereby disable the LOAD SILO CONTROL flip-flop. This prevents the loading of that character into the silo.

The low version of INHIBIT SILO LOAD is then used to qualify the gate at E42 where it fires the RESET one-shot
and clears the data available flag for that character, effectively throwing it away.

NOTE

For proper half duplex operation, there must be no more than
one half bit time between serial transmit and serial receive.
4.4.4

Transmit Line Request Detect (D-CS-M7285-0-1, sheet 6)

Figure 4-15 is a simplified block diagram of this logic. This logic is used to sense when a request to transmit is raised
on a particular line and to translate that line number to selection signals (TRANS SCAN x) that are used throughout
the DJ11 to multiplex operation.
The DJ1!1 “scanner” is not the traditional type used in most cquipments. This is not a scquential stepping scanner

that would rotate through the lines in a systematic manner before any line could be brought up. This logic, in a
sense, looks at all lines simultaneously and responds to the request immediately. When more than one request is

raised, it responds to that line with the highest assigned priority. So, in addition to being able to respond to lines in a
random fashion, it has the added feature of assigning priorities to those lines.
The TCR controls transmission such that if the program sets the control bit for a particular line, and if the TBMT
flag is set for that line, the so-called scanner will “stop” at that line. This is what is accomplished by the row of AND
gates down the left-hand side of the sheet. Their outputs feed 74175 Quad-D Registers.
RESET —

TBMT

LINE 00:

TeR LINE 00

1*—1

TBMT LINE 07

2408

—

74175

7400
9318

QUAD-D

8-INPUT

(2)

ENCODER

SIGNAL

|A2
eoie
.
—
_ TRANS

PRIORITY A

7408

TCR LINE O7

GROUP

SCAN C

SCAN B

TRANS

l
TRANS

TRANS

SCAN A

SCAN D

TBMT LINE OS8

TCR LINE 08

£O

7408

74175

QUAD-D

TBMT LINE 15 :!

TCR LINE 15

GS —-

[

(2)

TM~

9318

8-INPUT

ENCODER

7408
J

PRIORITY | Al

TRANS SAMPLE CK —
11-1829

Figure 4-15

Transmit Line Request Detect Block Diagram

4-16

The inputs to these registers are sampled every 400 ns by TRANS SAMPLE CK, which is used to clock-load these
registers. TRANS SAMPLE CK clocks the 74175 on its leading edge and remains high for approximately 400 ns to

i
i
i
i
p
ity
Deonndace
give
the input
signals
time
to propagate through thc
9318 Priority
Encoders.

The priority encoders are designed to yield the binary combination representing the line number at their inputs.
When an input goes low, if for example it was line 4, the output would be 100; but if two or more inputs go low at

the same time, the output of the encoder will be the binary combination representing the highest numbered input,
e.g., line 7 output would be 111. When any input goes low, the inverting OR at E52 pin 11 yields GROUP SIGNAL

(H).

The signal GROUP SIGNAL (H) is used on sheet 7 to set the Ready flag when TRANS SCAN CLOCK goes low. In

addition, when the Ready flip-flop sets, its O side is used to force a high out of the OR gate at E32, thereby shutting
off the clock and causing the scanner to not proceed from the line number on which it stopped.

The line number to which the TRANS SCAN x outputs on sheet 6 are pointing are readable by the program when it

accesses the high byte of register 06. At this point the data to be transmitted is fetched from the appropriate buffer

and 1oaded into the low byte of register 06, {ioin which it is lvaded into a buffer register (TBUF) on sheet 7.
Note that TRANS SCAN D is not ORed on its output as are the other trans scan signals. Instead, both the high and
low versions are made available to select between UART lines 0—7 (low version) and lines 8—15 (high version).

4.4.5

Trans Scan Control (D-CS-M7285-0-1, sheet 7)

This logic is simplified in Figure 4-16. It is here that the control signals for the transmit scan function are generated,
and a means is provided to permit the programmer to leave a line that he has erroneously selected, without having

load a character to achieve it.

The clock TRANS SAMPLE CK (H), shown at the top of the page, is

the result of two 74123 one-shots that produce
the 400 ns/50 ns duty cycle shown at the top of the page. The operation of
this pulse train is under the control of an
OR of MSTR TRAN SC EN (CSR bit 8), GROUP SIGNAL (READY)
and a 1 us one-shot at E39. The assertion of
any of these signals will, by virtue of the logic mismatch into the clock,
stop the clock from running.
The character to be transmitted is stored in the holding register at
the bottom of the page.

74175 Quad-D flip-flops, was loaded from the low byte of register 06

(H) and OUTLOW (H).

This TBUF, a pair of
[BD (07:00)] by the combination of SEL 06

The timing arrangement of these signals is shown in Figure 4-17. The ANDing of SEL 06 (H) and OUTLOW (H) fires
both the 1 us and 300 ns one-shot. The signal TRANSMIT STROBE (H) is only sent to the UART selected by the
trans scan combination. The second one-shot, however, is used to hold off the clock an additional amount of time to

allow TBMT to decay in the MOS device. This decay time is approximately 500 ns, well within the 1.2-us delay.
Delaying the start of the clock in this way prevents overlaying characters into the UART that would occur if the
same TBMT were to be seen a second time by the next TRANS SCAN CLOCK.
The two 8:1 Multiplexers (74151s) on the right-hand side of the sheet are used to restart the scanner should the
program stop the clock on a line and then not wish to transmit a character. Here all TCR bits are multiplexed by the

TRANS SCAN x combination. All that is necessary is for the program to clear that TCR bit for the line on which the
clock is stopped. This output, ANDed with TRAN RDY yields a TCR CLR flag. That 50-ns pulse through the 8815
gate at E49 will direct clear the Ready flip-flop and restart the clock.

4-17

H
TRAN RDY

GROUP

SIGNAL
READY

TRANS

SCAN D(H)

74123

1/8

(2)

TCR 00

MASTER

TRAN SCAN EN
TCR CLR FLAG

8815

[

74151

8:l

C*"—j

|
|

TCR 07 ——1——
.D

TRANS SCANC———@

7408

TCR CLR
FLAG

TRANS SCAN B
TRANS SCAN A

8I-¥

74123
1/S

800ns

SEL 06 ———]

TCR 08 —

74151

7400

8:1

MUX

OUTLOW

/8
300ns

CR |5 —1—

TRAN STROBE(H)

TRANS SCAN D{L) T

>——<{>‘|NH(L)
SSYN

BDOO —T—

OUTPUT

O0(0]|]

TCR OO

010|0]1

ojo{1j0

0j110]0

ofoj|

+3V

L“{

74151

TRANS SCAN
olcTlela

)

CLR

——— TRAN DATA1

7475

QUAD-D
ff

BDO7? ——H

Figure 4-16

(2)

S
TRAN DATA

Trans Scan Control Block Diagram

11-1830

l——500 nsec
worst case

|
|
|

SEL 06

A OQUTLOW

TRAN STROBE

| ’/-]\BUS CYCUE~ 400nsec

300nsec

i.2usec

DELAY CK ——j\
]
SAMPLE

{
|
|
]

|
I

:
|

TRANS

n
/ +————CLOCK ON

lf <«+— CLOCK OFF ——»
11-1831

Figure 4-17

4.4.6

TBMT MOS Decay Protection

Receiver Scanner (D-CS-M7285-0-1, sheet 8)

The DJ11 receiver, unlike the transmitter, uses the standard scanning technique. This logic, simplified in Figure 4-18,
uses a scanning counter to sequentially look at each line. Once it has looked at a line, it will not look at that line

again until all other lines have been looked at in order.
The counter, designated RCV CH # CT, (Receive Channel No. Count) is a 74193 that yields outputs, RCV SCAN

A:D (H), that are sent to decoders on the UARTSs (M7280 cards). To take care of the full 16 lines, two polarities of
RCV SCAN D are sent back with the low version sent to UARTs 0—7 and the high version to UARTs 8—15.
The counter is incremented by the setting of the INC SCAN flip-flop at E44 which is, in turn, clocked by a 74123
RCV SCAN OSC clock at E15. The clock is enabled by RCV ENABLE (H), a function of CSR bit 0. Characters
cannot be received, and the scanner cannot run, unless this bit is set,

The operation of this logic can best be described by first assuming that there are no characters coming into the DJ11
and hence no characters being assembled in the UARTSs. If these conditions are assumed, no DATA AVAILABLE
signals will be generated, and four lows will exist on the 8815 gate at E49. When this is true, the D input of the INC

SCAN flip-flop will be high and on the next clock from RCV SCAN OSC, the RCV CH # CT increments.
When INC SCAN sets, it enables the SAMPLE LINE flip-flop causing its O side to go low. This yields a 50-ns pulse
from the 7402 pulse-former at E34 that feeds a 74H11 at E41 to clock the LOAD SILO CONTROL flip-flop if INH
SILO LD is false, and if the silo is READY IN (L).
If the silo is ready, a signal is generated on that board that indicates that the silo can accept another character. If it is
assumed that this is the case, and that no MASTER DAs are present, or that no UART had a character assembled,
the next clock will drive LOAD SILO CONTROL (1) low and the resulting mismatch on the 8815 and at E49 causes
a low on the D input of INC SCAN. The next succeeding clock will then complement SAMPLE LINE, causing the
next clock to set INC SCAN and increment the RCV CH # CT (Figure 4-19).

The scan line outputs of the counter go out to enable multiplexers on the M7280 board to yield one UCx MASTER
DA from all the data available signals on that UART card. When the 50-ns pulse from the pulse-former at E34 is
generated, the multiplexers look at only one DA, the one pertaining to the UART on the line selected.

4-19

The counter then performs the same test on the next line in order, checking to see if the DA is up and if the silo is
ready. If the silo is ready, it is clocked; if no DA is asserted, the scanner moves to the next line. If, however, on that
second clock pulse, the MASTER DA shows that a character is assembled in the UART (high), when the 50-ns pulse
is asserted, the LOAD SILO CONTROL flip-flop is set. This forces a low on the D input of INC SCAN by

disqualifying the AND at E49, and forces a high on the D input of RCV ENA flip-flop. When this occurs, the third
clock pulse in the series just described sets RCV ENA sending RCV DATA ENA (H) out to that UART where it
enables the received data leads of the selected UART.
NOTE

The UARTSs are tri-state outputs on the receive lines. They are
wire ORed and, when they are enabled, data is sent out on the
received data lines.

When RCV ENA sets, its O side fires a 74123 1-us one-shot that generates TEMP INHIBIT. This is doubled back to
the input of the clock and causes it to turn off. This is done because the width of the basic clock pulse is 300 ns
which is not enough time to allow the data to set up in the FI/FO.

Once RCV ENA is set, after TEMP INHIBIT times out, the next clock will set START LOAD causing LOAD SILO

(L) to be issued to the FI/FO on D-BS-DJ11-0-6, sheet 1. Combinational logic on that sheet converts this to LOAD

SILO (H), which is used to clock the FI/FO chips on sheet 2. Here, along with loading in the data, the line number
and status information pertinent to that data is also loaded. On sheet 1, LOAD SILO L clocks the 74H74 at E25,

yielding LOAD IN PROGRESS L. This flip-flop clears once the silo is loaded. LOAD IN PROGRESS then is used to
stop the clock on D-CS-M7285-0-1, sheet 8, during the period that the silo is being loaded, providing an interlocked
communication between the receive scanner clock and the FI/FO.
Once loading is complete, the clock resumes, thereby setting the CLEAR DA flip-flop which, in turn, fires a 1-us
one-shot at E28. This generates both RESET DA and TEMP INHIBIT, stopping the clock and resetting the data
available flag for that UART. The opposite side of the one-shot is used to clear both the LOAD SILO CONTROL
flip-flop and the last three flip-flops in the chain just described.
The next clock after the end of TEMP INHIBIT L increments the count to the next line and the sequence begins
again.

If at this time MASTER DA is asserted but READY is not, the indication is that the silo is full. In this case, the
program must be warned that the UART has assembled a character but is unable to put it into the silo. This warning

is accomplished by FI/FO OVERRUN, which sets on this combination of conditions. The signal does not indicate an
overrun but it does say that an overrun is imminent. It gives the program an opportunity to unload a character from

the FI/FO before any characters are lost.

When anything is read out of the silo, READ RCV BUFFER (H) clears the FI/FO OVERRUN flip-flop.

4.4.7

Miscellaneous Control (D-CS-M7285-0-1, sheet 9)

This print contains various pieces of combinational logic that perform control functions in the DJ11. The MASTER

DA signals from the two UART cards (UC1 and UC2) are ORed to produce MASTER DA (H). REQ RCV INT (H) is
sent to the M7821 Interrupt Card on the presence of an FI/FO OVERRUN when status is enabled, or when a RCV
INT is enabled and there are characters available.

BUS INIT produces two polarities of reset. It also ORs to clear out all the UARTS, i.e., initializes all the UARTSs and
FI/FO without initializing any of the other registers. When BDO3 is set, a 2-us one-shot fires to clear out all the
UARTs or flush the FI/FO buffer.
This sheet also shows the priority jumper at E45.

4-20

RESET

1L°A°
1

7474

4BIT UP/DWN

AEE————
Y

#CT

—————= RCV SCANC

CTR RCV CH
74193

INC
SCAN

:g\c ss%‘:\':‘g
RCV

RESET

SCAN D

RSD (L)

* TO UART

RCV EN

Tmfls

178

RCV

LD IN
PROG

7474
SAMPLE
LINE

SCAN
0SC

1/S
74123
RCV ENA (L)

74123
>O

1
CLEAR

—

DA (1)H

I\e

1/8
74123

TEMP
INHIBIT

RESET DA

D—

L:,L

INH

SiLO

SAMPLE

LINE (O)

MASTER DA

)

1
RESET 1/S

LOAD

O L =

SILO
CONTROL

INHIBIT

—

7474

SILO LO

READY IN

__J

READY IN

50 ns

— D

Fi/FC OVERUN

7474
FIZFO

RESET

(/SO LO

A RESET

!
7%1&5

[»

RESET
D

OvERSEL 2

= REV

DATA

c
RESET

ENA(H)

LN p—

RESET

74175

ENA

READ

START

RCV

BUFFER

LOAD

11833

0
c

jL RESET

_o LOAD
SILO (L)

|9]

RESET

CLEAR

DA(1) H

74175

CLEAR
DA

[
RCV
= ENA(O)L
11-1832

Figure 4-18

Receive Scanner Block Diagram

4-21

INCREMENTS COUNTER
TESTS FOR DATA AVAILABLE

COMPLENTS SAMPLE LINE

/INCREMENTS COUNTER

RCV SCAN CK J ! U ? U 3 u ? l_'-_

11-1834

Figure 4-19 Receive Scan Clock Events

4.4.8 Clock and Distribution (D-CS-M7285-0-1, sheet 10)

schematic by chip and
This logic is shown in simplified form in Figure 4-20. The figure has been keyed to the block
d diagram, but should be
pin number to facilitate correlation. The description is referenced to the simplifieection
of ICs is looped in a
simultaneously traced by the reader on the block schematic since the actual interconn
complex fashion.

The basic crystal-controlled 5-MHz oscillator (5.0688) is fed first to a divide by 11 to yield 460.8 kHz. This
frequency, in turn, is divided by 3 to give the 9600 baud rate.

is
The 460.8 kHz output is also divided by 6 in the same chip to yield 76.8 kHz or 4800 baud. The 76.8 kHz output
kHz) is

then divided sequentially by 2 to produce the 2400, 1200, and 600 baud rates. The 600 baud output (9.6
then divided by 2, 4, and 8 to yield the 300, 150, and 75 baud outputs.

The 460.8 kHz output of the divide by 11 chip is also fed to a divide by 2 chip to yield 230.4 kHz, which is then
divided by 2, 4, and 8 to produce the 7200, 3600, and 1800 baud set.

latter
Finally, the basic oscillator frequency is also used to feed a divide by 16 string producing 316.8 kHz.theThis
baud
110
for
string
6,5
6,
a
to
and
output,
baud
134.5
the
for
frequency is fed first to a 3,7, 7 combination
output.

Note that the UART specifications require the frequency to be 16 times the baud rate. This relationship can be seen

by the frequencies shown in Figure 4-20.

d. They can be
The odd value counters used in this logic are designed so that they will count to 16 when unmodifie
In the 74161
factor.
e
differenc
that
by
divide
preset to any number below 16 to count the difference and thereby
(1111), where the next carry
divide by 11 chip at E84, the counter is preset to 3 so that it will count 11 places to 15
will reset it to 100 or 4.

4.4.9 Multiple UART Card Lines 15:00 (D-BS-DJ11-0-3, sheets 2—5 and D-BS-DJ11-0-4, sheets 2—5)
This logic is simplified in Figures 4-22 and 4-23. These eight sheets represent the identical circuitry for the 16 lines
multiplexed by the DJ11. Each sheet contains two UARTS with identical input and output signals. The leads on the

upper portions of each UART block pertain to the receive function with the received serial data from the line fed in
at pin 20. The assembled character is then fed out to the memory from pins 5 (MSB) through 12 (LSB). These
outputs are wire-ORed from all UARTs. The output of the UART is a tristate totem-pole construction with a
transistor for a 1 and a separate transistor for a 0. When both transistors are turned off, the output floats. When an
output is enabled, no others are enabled and the data is sent out on the line(s) selected.

4-22

S5MHz
0scC

460.8

38.4 KHz

KHz

5068.8
KHz

<11

74161

7492

E84

153.6KHz
—» 9600 BAUD

E67

7492

76.8KHz
—»

E67

= 2400 BAUD

14|

4 7383

E76

124114

7492

7490

E67

E72

19.2KHz

e 230.4KHz

— = 1200 BAUD
2

7493

)

9.6 KHz

E77

7439
a4

7493

E77

7a92

9 | 4.8KHz

7493 |° {°

£77

= 600 BAUD
[28%HZ_

— ~ 300 BAUD
—=

'
7493

115.2KHz

E76

-4

7493

1267.2KHz
.

28.8 KHz

9305
+2

E76

7492

7452 P2
+

E78

E73

E74

[12

E79

T1o

2534.4KHz

6336 KHz

—=

7200 BAUD

3600 BAUD

—=

1800 BAUD

134.5 BAUD

9305

E73

2.152KHz

E74

[5 15064k
5

316.8KHz

8.8KHz

+6
7492

+ 6
7492

=5
7490

E79

E78

52
8 KHz

1.76KHz

10 BAUD

E72

h
11-1835

Figure 4-20

BAUD

110

9305

105.448 KHz

E79

7492

150 BAUD

—

57.6 KHz

E76

' | 7493

<6 BAUD

E77

4800 BAUD

DJ11 Clock, Functional Block Diagram

The leads on the lower portion of the UART block pertain to the transmit function. Here the parallel data to be
transmitted from memory is fed to pins 26 (LSB) through 33 (MSB), converted to a serial stream, and fed out to the
line from pin 25.

On the schematic, the various UART parameter controls are fed into the bottom of the block.

All the BUE RCV DATA x bits, converted from SERIAL IN on the UARTs are commonly inverted on sheet D3-3 to
UC1 RCV DATA x bits and on sheet D4-3 to UC2 RCV DATA x bits and sent to the input gates on the FI/FO on
drawing D-BS-DJ11-0-6, sheet 2. The parallel characters from memory to be transmitted out on the lines are
buffered on sheets D3-4 and D4-4 to BUF TRAN DATA x bits. The data input to these sheets is from the transmit
buffer on drawing D-CS-M7285-0-1, sheet 7.

The selection schemes of a specific UART for reception or transmission are shown simplified in Figures 4-21 and

4-22, respectively. For actual UART blocks, refer to the drawing set.

In the receive case, 74155 1:8 Multiplexers are used to convert the combinations of RCV SCAN A:D to discrete
Read Data Enable and Read Data Available signals for the UARTs. Note that the inverse sensing of RCV SCAN D is
located on drawing D-CS-M7285-0-1, sheet 8, and not on this card. This permits the enabling of the upper set of
UARTs and the disabling of the lower set when any line between 8 and 15 is called for. The 74155 Multiplexers are
also used in similar fashion to select the BUF DS LINE control signals for the UARTSs. This is the transmit strobe
line.

In the transmit case, shown in Figure 4-22, 74155 8:1 Multiplexers are used in a similar selection scheme to produce
a single set of control (MASTER) signals from the various UART outputs.

The operation of the UART is described earlier in the block diagram discussions and is also described in detail in
UART specification A-PS-1910459-0-0; therefore, this discussion is not repeated here. However, & timing diagram of
the UART data format is given in Figure 4-23 for reference.

4.4.10 DI11 Controel Interface (C-CS-M105-0-1 and D-CS-M7821-0-1)

These sheets show the block diagram representation of these standard PDP-11 modules. Their operation is standard
and is described in detail in Paragraphs 4.3.3. and 4.3.4. The one deviation from ordinary use is that AO1 and AQ2
are buffered versions of these bus signals received in the DJ11 on sheet 3 of the M7285 module.
4.4.11

DJ11 FI/FO Buffer (D-BS-DJ11-0-6, sheet 2)

This sheet shows the logic for the FI/FO buffer used in the DJ11 to accumulate and buffer characters received from
the various serial lines (via their UARTs) and transmit them to the host computer when Unibus dialogue has been
satisfied.

The FI/FO (or silo) is a set of four 3341 4 bit wide X 64 word propagateable registers which, when concatenated,
provide the Unibus with a 16-bit word that contains a data character and pertinent data as to the line number on
which it was received and various status conditions about that character (Figure 4-24).

The silo is fed from four 74157 4-bit 2-input multiplexers that feed the 15 bits required for one FI/FO word. These
multiplexers are normally selected by a 01 combination that causes them to send out the ORed inputs from the
UARTS:, the RCV SCAN x combinations, and the Master status information from either of the UART cards (UC1 or
UC2). When the select combination is 11, by jumpering EOIR1 to EOIT1, the alternate inputs ‘o the multiplexers
are sent to the FI/FO allowing alternate 1s and Os in adjacent bit positions to be deposited into the silo for
maintenance purposes.

Data multiplexed to the input pins of the 3341s is loaded into the top position by LOAD SILO H generated on sheet
1. That character or word is then propagated down to the last open word position in the chip by internal logic. The
data residing in the bottom position of the chip is read out by READ SILO H, also generated or sheet 1. There are
two flags, READY IN that indicates that a character may be loaded in, and READY OUT that indicates that a valid
character is available at the bottom of the silo.

4-24

RCV
D

SCAN
L

LOCATED ON

BUF RDE LINE oo\‘
—

~_ o D2-7

DATA

74155

> BUF RDE LINEO3 { (|NE cONTROLS
'8

|—

0——1 DE(iODER

BUF RDE LINE 04

]

TO UARTS

|—— BUF RDE LINE 07

TRANS SCAN DL

TRAN

STROBE H

—— BUF RDE LINE 08

74155

-— — —4

DECODER

\LOCATED ON
SHEET D2-7

L BUF RDE LINE 1

LINE CONTROLS

74155

[T BYUFRDELINEIZ P TOUARTS

> BUF RDE LINE 15

A
'8

]

—=

SCAN —

—— | ———= BUF O3 LiNE 05

BUF RDA LINE 00

o | » B BUF RDA . LINE 03
LINE CONTROLS
g
— BUF RDA LINE 04 | TO UARTS

RESET __ |
DA H

74155
- — - ~ -

|—= BUF RDA LINE 07

olol1lo

ololils

0
oprjo

etc.

74155

T
L

RCV
A

SCAN
H

olololo

LINE 07

ololo]
olol
|o

1
»

olo|1

—*

BUF DS LINE 08

of1fo]o

BUF DS LINE 11

of1|o]l

[

BUF DS LINE 12

8
neArNnNED

DECCDER

plc|s|a]

_____

— ¢

ojoio

| — = BUF RDA LINE 08

TRA NSSCANCH

74155
REV SC AN

ojolo|n

DECODER

RCV SCAN

STcTalal

LINE O4

- BUF DS

—e BUF DS

74155

TRANS SCAN

DECODER [

72155

RCV

BUF
BUF
DS LINE 00

etc.

DECODER |
——a= BUF

TRANS SCAN B H

LINEIS

TRANS SCAN AH

= BUF RDA LINE

rasr

LINE CONTROLS

—» BUF RDA LINE 12 [ TO UARTS

BUF RDA LINE ISJ

|
11-1836

Figure 4-21

Multiple UART RCV SCAN Selection Scheme

4-25

RCV
SCAN
oL

BUF DA LINE 0O

74151
8:1
MU

o7
A

RCV SCAN(

B
C

uct
MASTER
DA H

uce
MASTER
DA H

74151
8:1
MU

RCV SCAN(

A |
B

BUF OR LINE 0O

74151
8:1
MU

uci
MASTER
OR H

[a-

RCV SCANiB—‘
c
08

ucz2
MASTER
ORH

74151
8:

MUX

RCV SCAN( B
c

BUF FE LINE
OO

uc4
MASTER
FE H

74151
8:1
MUX

RCV

SCAN(

A____J o
B

C
08

74151
8:1
MUX

RCV SCAN

ucz
MASTER
FE H

2|
(B

BUF PE LINE 0O

uci
MASTER
PE H

RCV SCAN [2—’ ‘
c—

74151
8:1
MUX

ucz
MASTER

PE H

[¢]]

RCV SCAN{(

B
C

~]
1-1838

Figure 4-22

Multiple UART Trans Line Selection Scheme

Note that bit 15 of each word (Valid Data) is the product of combinational logic and is not a stored bit in the

FI/FO. This bit is a copy of Valid Data which is produced on sheet 1 as a function of READY OUT.

8-BIT ASCII

DATA RECE!VED\ sTarT

PAR COND

JUMPER

PE.BIT

’ *’*

"IN STATUS

gninly

PAR

le—1 BIT TIME —]

16 CLOCK

PERIODS
be—pATA

loLock PO—slfe—
IDLE|

START

DATA

PULSE

DATA

| T||

L.S.B.

DATA 58—

\ k

]

PARITY

STROBE

BIT

STROBE

SAMPLE PULSE

DATA

ENTRY

STATE

§TROBE

BIT,

e (RCVING (

DATA

STOP

P ———————

ENTERS

FIRST

FEE.SET IN STATUS.

"MARK"

] -

FIRST M-»S TRANSITION
START

IDLE STATE

sToe

——— - | IF (0) ON SAMPLING

DATA

y
IF (1) DATA PARALLEL

TRANSFERRED

FROM SHIFT

REG. TO DATA HOLDING REG.
11-1839

Figure 4-23

RBUF

77XXX2

errors

UART Data Format Breakdown

LINE NO.

RCV CHARACTER

]

OVERRUN

ORIFE | PF_

16 BITS WIDE

}

o forlon
o
w0

JOR|FE | PE

—
ISR
SR FCR Ol )

(1)

RENESENES

FE | PE

|JOR!

|OR | FE | PE

oo |o

(1)

olojo

FE | PE

>le(>|>|p
>

|OR|

JOR|FE | PE

Clolo |ojo|o

(1)
(1)

ASC11 <8:1)>
e

olo|lo|lalo|o

s¢
—~—

PAR ER

|
|

®|l®fow

FRAMING ER

N[N~~~
~

3341s :

|lojlo|m

ool

F1/Fo

- VALID DATA

olololojojo

WORDS
|

LONG

‘J
11-1840

Figure 4-24

4.4.12

FI/FO Buffer Format

FI/FO Buffer Control Logic (D-BS-DJ11-0-6, sheet 1)

This logic is simplified in Figure 4-25. It is the control logic for
the FI/FO buffer discussed in the preceding

paragraph.

4-27

READY
74H74

74H74
READ
EXEC

READ
INIT

READ RCV

BUFFER

pa
/ » READ SILO
|+

R'E_éo

|Jons
72121

30ns

(SILO STATUS

8TV

COUNT

CONTENTION CONTROL.

DOWN

CANNOT READ FROM FIFO

SMHz —» g::g‘é

WHILE LOADING FIFO

74193"s FIFO [ooo o

MOS

oon

74H74
LOAD

LOAD SILO —#

LOAD

LOAD IN

PROGRESS

>°—AVA.,_
CHAR

‘

—» LOAD SILO
74HT4

EXEC

ofb—————»|

7485's

ggUNT

CHAR COUNT

COMPARE

L=ic

7L"g§[‘)

HARDWARE

P'g

COMBINATION

170ns

(30ns

LOAD

E(C))ZECHIANRT

»—*—"
(. se

11-1841

Figure 4-25

FI/FO Buffer Control Block Diagram

When a character is to be loaded into the FI/FO, the Load Silo command is issued and used to clock the LOAD INT

flip-flop at E25 (74H74). This is an inverted flip-flop which then enables the LOAD EXEC flip-flop (74H74, E18).

This flip-flop is clocked by the 0 side of the PHASE flip-flop at E25. This is a complementing flip-flop fed by the
basic 5-MHz clock signal. Note that it’s outputs are arranged to clock either a loading chain or a reading chain to

avoid any contention problems.
When the LOAD EXEC flip-flop sets, its low O side fires a 170-ns one-shot to produce the LOAD SILO signal sent
back to sheet 2, where it clocks the data into the FI/FO. Once data is clocked in, the one-shot falls back; but the
30-ns delay on the O side of that one-shot is fed back to clear the LOAD INIT flip-flop. This delayed pulse also feeds
the FI/FO character counter (74193s) that keeps track of the amount of data in the silo.
These counters are up/down counters that are activated by READ SILO L + 30 ns for down-counting and LOAD
PULSE, which is LOAD SILO + 30 ns for up-counting.

The sequence of control for reading out of the FI/FO is identical as shown in the figure except that the initializing

flip-flop is enabled by READY and clocked hy READ RCV RUFFER. The EXEC flip-flop is clocked by the
opposite phase of the PHASE flip-flop which, in this case, fires a 100-ns one-shot for reading. Clearing of the chain

and character decrementing are identical.
The two 7485s at the left-hand side of the sheet are used to compare the SSR (Silo Status Register) outputs of the

up/down counters with the hardwired combination on its other input. When comparison is found, a CHARACTER
AVAILABLE is generated on READY OUT. Based on that preset combination, this signal will either come up on the

first character moved, or it will wait until a number of characters have been moved. Normally on a
character-for-character basis, the pins are all grounded, but they can be selectively cut to cause comparison on 5, 9,
or 17 characters. This provides the delayed CHARACTER DONE INT feature described in Chapter 1.
In operation, read out of the FI/FO is continued until bit 15 is found to be cleared, indicating that the silo has been
flushed. The signal MOS CLR is used to clear the FI/FO but it is used merely to clear the flag (bit 15), it does not
clear any of the information in the FI/FO. However, once cleared in this way, new information can be loaded into
the FI/FO, it will propagate down to the last position, overlay the now invalid data that was in that position, and

will set bit 15, indicating that that new information is now valid.
4.4.13

TTL Output Interface (D-CS-M5900-0-1)

The M5900 TTL Output Interface Card is shown simplified in Figure 4-26. The 16 receive lines (LINE 15:00 IN) are

applied to the normally enabled B inputs of 8266 Multiplexers and fed out as SERIAL IN (15:00) H to the DJ11.
The 16 transmit lines [SERIAL OUT (15:00) H] are each ANDed with the fact that the break bit in the TBR for

that line is set and thence to the transmit line.
If the MAINT bit is set in the CSR (bit 02), the B inputs of the multiplexers are disabled, preventing reception from
the line, and the A inputs are enabled. This provides the loop around feature used by maintenance activities to check
out the DJ11.
In the receive case, line signals of 0.8 Vdc (mark) and +2 Vdc (space) are transferred in as +3 Vdc (mark) and ground

(space) signals to the DJ11

circuits.

In the transmit case, +3 Vdc (mark) and ground (space) signals are transferred to the line as +2.4 Vdc (mark) and

+0.4 Vdc (space) signals to the line.
As can be seen, in maintenance mode the TTL signals are not inverted but are received back as they are transmitted.

4-29

Do_d

+0Q 8

8266

MR
I l

2:!

SPACE

LINE 00 IN —s}
space / |
+2
|

QUAD |
SERIAL INOO H —+
Mux

GND

MARK

LINE 00 L

T
L

LINE 00 OUT

SPACE
+0.4

won

—}e

MARK

LINE 15 OUT

—fe

TBR

[]

jooa |
A

MARK

| SERIAL OUT 15 H <+— —I l—GND
|

00 L

:
|
|

| SERIAL OUT 00 H

—W——]

SPACE

LINE 15 L

L+

SERIAL

LINE 15 IN

MAINT H

t1-1842

Figure 4-26

M5900 Level Converter Block Diagram

4.4.14 EIA Output Interface (D-CS-M5901-0-1)

The M5901 EIA Output Interface Card is shown in Figure 4-27. The multiplexing arrangement is identical to that of
the M5900 with the MAINT bit creating the same loop around feature. The modules make the conversion between
standard EIA signals on the lines to signal levels suitable for the DJ11.

In the receive case, line signals between =3 and - 15 Vdc (mark), and between +3 and +15 Vdc (space) are transferred
in as +3 Vdc (mark) and ground (space) to the DJ11 circuits.

In the transmit case, +3 Vdc (mark) signals and ground (space) signals are converted and transferred to the line as -6
to =15 Vdc marking signals, and +6 to +15 Vdc spacing signals.

4.4.15 TTY Output Interface (D-CS-M5902-0-1)
The M5902 20 mA Current Loop Output Interface Card is shown in Figure 4-28. The multiplexers (8266) are used
to provide the maintenance feature described for all of these cards.

The card uses an opti-coupler on the receiver side to provide the total line isolation required. The coupler (Ex)
comprises a light-emitting diode, that is excited by signals on the line, to activate a light-sensitive transistor feeding a
transistor buffer (Qx). The resultant signals are fed to the B inputs of the line multiplexers (8266 2:1). On the
transmit side the signals are transistor-coupled to the line.

In the receive case, 20 mA (mark) and no current (space) signals are converted to the standard +3 Vdc mark and
ground space in the DJ11.

4-30

LINE 00 IN ___"_‘
l
+‘5__SPACE/I

+_3_91_2m"

-x

| £47Opf

MARK

EFIMKL o

&JAv

A mAA~r

SrAVE

MARK

LINE 00 our—n—@

/" |——SERIAL ouT ooH<—!i
LGND

———
|

—\

——TBR

SPACE

OOL

—

space

GND

MUX

LINE OOH

el |—>SERIAL IN 0OH—»

NOISE FILTER

[

wagK

‘

LINE 15 OUT —e——0X

LINE

15H

SERIAL

LINE 15 IN——e——]

STB

| T

15H

'
MAINT H

r—-SERIAL OUT I15H

\_}—srsH

4705t

1
I

1-1843

Figure 4-27

M5901 Level Converter Block Diagram

‘————

LINE OO IN

MARK

)

8320

SERIAL IN OO H

GND

2:1

SPACE

MUX
AN\

20ma MARK
|,

|
oma

]

MARK *+3

LINE 00 L
~——

SERIAL

OUTOO

H___

SPACE

GND

SPACE

LINE 00 OUT 7 =

7°0

TEROOL

)

[]

750

LINE 15 OUT

[]

‘/

C :—SERIAL OUT 15 H

LINE 15 H

RIS L

V\\/\A

LINE 15 IN

SERIAL IN 15 H

MAINT H
11-1844

Figure 4-28

M5902 Level Converter Block Diagram

4-31

CHAPTER 5
MAINTENANCE

5.1

INTRODUCTION

DJ11 maintenance philosophy is based on the premise that an optimum amount of preventive
procedures,
performed regularly, can eliminate many costly equipment breakdowns and forecast failures before
they occur. The

design is such that, in the event a specific item fails, module replacement can restore the equipment to

minimum of time.

In the event that a module is found to be faulty, a module should be substituted from spares

service in a

(Table 5-1) and the

faulty module returned to DEC for repair. Depot repair facilities have been located strategically
throughout the

world to enable users of DEC equipment to receive prompt, efficient service. At the user’s option, a national
transportation firm, contracted by DEC, can be used to route equipment to and from the depot facility.

Table 5-1
List of Recommended Spares

Module

Quantity

5.2

M7285

M5900

0
0

M5901

M5902

M7280

M7821

M105

M7279

PREVENTIVE MAINTENANCE

Preventive maintenance consists of tasks performed at periodic intervals to ensure proper equipment operation and
minimum unscheduled downtime. These tasks consist of running diagnostics, visual inspection, operational

adjustment, and replacement of marginal components.

checks,

The preventive maintenance schedule depends on the environmental and operating conditions
that exist at the

installation site. Normally, preventive maintenance consists of inspection and cleaning every 600 hours of operation

or every 4 months, whichever occurs first. For extreme conditions of temperature, humidity,
or dust, and with

abnormally heavy work loads, more frequent maintenance may be necessary. It is recommended

that the éxerciser
tests, part of the diagnostic for the DJ11, MAINDEC-11-DZDJB-A-PB, be run once a week as part of the
normal

preventive maintenance schedule.

5-1

5.2.1

Mechanical Checks

Periodically inspect the DJ11 and it’s distribution panel for general condition. Inspect all wiring and cables for cuts,
breaks, frays, deterioration, kinks, strain, and mechanical security. Check all modules to see that they are properly
seated. Check seating of EIA plugs in H317B. Check security of connections at screw terminals of H317A. Tape,
solder, or replace any defective wiring or cable covering.
5.2.2 Test Equipment Required

Maintenance activities for the DJ11 require the standard test equipment and diagnostic programs listed in Table 5-2,
in addition to standard hand tools, cleaners, test cables, and probes. Special test equipment required for any
adjustments are given as part of that procedure.

Table 5-2

Test Equipment Required

Manufacturer

Equipment

Designation

Multimeter

Triplett or Simpson

Model 630-NA or 260

Oscilloscope

Tektronix

Type 454 or better

Module Extenders

DEC

W982 (Single)
W984 (Double)
W989 (Quad)
NOTE

For Hex Boards use a
quad and a double.

Diagnostic Self-Test Routines

5.3

MAINDEC-11-DZDJA-A-PB (tape)

DEC

MAINDEC-11-DZDJA-A-D (abst)
MAINDEC-11-DZDJB-A-PB (tape)
MAINDEC-11-DZDJB-A-D (abst)

CORRECTIVE MAINTENANCE

The procedures that follow are based on standard troubleshooting techniques. Once the defective module has been

located, replace it with a spare module and return the defective module to DEC for repair or replacement.
5.3.1

General Corrective Procedures

Before beginning troubleshooting procedures, ensure that the equipment external to the DJ11 is operating correctly.
Refer to the pertinent maintenance manuals for procedures. Also examine the DJ11 Maintenance Log to determine
if the fault has occurred before and, if so, note what steps were taken to correct the condition.

NOTE

A recurring fault can indicate a common uncorrected fault
elsewhere.

5-2

Visually inspect the physical and electrical security of all cables, connectors, modules,
and wiring. In particular,
check the security of ground connections between racks. Faulty grounds can produce a
variety of faults.

5.3.2

Diagnostic Testing

DEC provides special diagnostic programs (MAINDECs) to assist in localizing
faults within the equipment.
Functionally, the programs fall into two categories: test and reliability. Test programs
isolate genuine go/no-go type
hardware failures that are more easily recognizable; reliability programs isolate failures
that are difficult to detect
because they are marginal and occur infrequently or sporadically.
The family of test programs are written so that, when run successfully, they test

portions of the hardware then gradually expand until they involve the entire

the equipment beginning with smali

machine. To accomplish this, they are

built around instructions and portions of instructions whose demands on equipment
capabilities progress from
simple operations to the most involved manipulations. As portions of the system
are proven operable, they become

available to succeeding tests for use in checking unproven portions of the

machine.

There are two MAINDECs for the DJ11, MAINDEC-11-DZDJA-A-PB (Logic Tests)
and MAINDEC-11-DZDJB-A-PB
(Exerciser and On-Line Tests).
The Logic Tests diagnose problems with the DJ11 in maintenance mode. They
check that all the control registers
function properly, that interrupts occur at the right level, and that data can be transmitted
and received correctly.
Note that this set of programs does not test if the input and output leads are
functioning.
The various tests within this diagnostic are listed in Table 5-3, together with
the fault they find and the board
location of the component that is probably producing that fault.

This diagnostic will test up to 16 DJ11s. Each subtest is run 16 times before continuing to the

next. To run each test
only once, set SW(11) to 1. To loop on an error, set SW(9) to 1. To loop on any subtest,
set the test number in the

right-hand byte of the switch register, and set SW(8) to 1. The test will continue
to loop until either the test number
is changed or SW(8) is set to 0. The program will run as usual on a nonexistent
test. When testing more than one
DJ11, if multiple DJ11s are selected, this diagnostic performs all tests on one DJ11 at a time.
The bell will ring when
the first DJ11 tests are complete and before the second DJ11 tests are started. Each test
can be Power Fail tested
without errors. At any time, a power down followed by a power up will cause the routine
to type “POWER” and
then restart with no other error printouts.

This test uses memory locations 0 to 17500. It should always be started at location 200
and can be restarted at
location 1000 after parameters have been set. To load, use standard procedure for ABS tapes.
Worst-case testing is with all switches down. Refer to Diagnostic Abstract for further information.
A Scope subroutine call (via a Trap instruction) is placed between each subtest in the instruction

the starting address of each subtest as it is being entered in location “LAD”. If a scope loop

section. It records

is requested, the current

subtest will be looped upon. SW(11) on a 1 inhibits iteration of subtests. The contents of
“LAD”’ may be used to
determine the last subtest successfully completed.

A HLT routine (called by an EMT instruction) prints out an error message. If SW(9)
is on a 1 and an HLT is
executed, the subtest will be looped upon until 16 consecutive good passes are completed.
To inhibit typeouts, put

SW(13) on a 1. To ring the bell on an error, put SW(10) on a 1.

5-3

Table 5-3

DJ11 Diagnostic Logic Tests and Fault Location

Dwg.

Comp.

M7285

D2-6

E29

M7285

D2-2

E25

Test

Test Description

Probable

Tests ability to reference CSR without trapping and

M105

Tests that CSR 01 can be set and cleared.

No.

Fault

ability to clear CSR.

Loca.

D2-4

E47
E64

M7285

Tests that CSR 02 can be set and cleared.

D2-2

E25

D24

E47

E7
E64

M7285

Tests that CSR 06 can be set and cleared.

D2-2

D24

E47

E18
E64

M7285

Tests that CSR 08 can be set and cleared.

D2-2
D2-4

E6
E18

E47
E31

M7285

Tests that CSR 10 can be set and cleared.

D2-2

E30

D24

E47

E24
E31

M7285

Tests that CSR 12 can be set and cleared.

D2-2

ES5

D24

E47

E31

M7285

Tests that CSR 14 can be set and cleared.

D2-2
D24

E3
El

E47
E31

Tests that CSR 00 (Receiver enable) can be set and

cleared, and that CSR 03 (MOS CLR) is write only.

M7285

D2-2

E26

E36
E7
E24

D2-8

E17
El14

El15

Table 5-3 (Cont)
DJ11 Diagnostic Logic Tests and Fault Location
Test

Probéble

Test Description

No.
12
13

Dwg.

Loca.

Tests that CSR responds properly to byte commands.

M7285

D2-4

E47

Tests that BIS and BIC instructions set and clear R/W

M7285

D24

E47

M7285

D2-2

All

D2-3

bits of CSR.
14

Comp.

Fault

Tests that TCR is R/W.

E20

E21
E43

E4i

Tests that TCR responds properly to byte commands.

M7285

D2-3

E41

Tests that the BIS and BIC instructions set and clear

M7285

D2-3

E41

D2-5

All

TCR R/W bits.
17

Tests that CSR 15 (Transmit Ready) sets and clears

M7285

when TCR 00 is set and cleared, and that proper

D2-6

line number (0) appears in TBUF.

E23
E32
E33
E49

D2-2

E3
El

Tests that CSR 15 (Transmit Ready) sets and clears

M7285

when each TCR bit is set and cleared, and that

D2-5

D2.-6

proper line number appears in TBUF.

All

E23
E32

E33
E49

D2-2

E3
El

Tests that CSR 08 (TRAN SCAN ENABLE) on (0)

M7285

D2-6

E49

disables CSR 15 (Transmitter Ready) when TCR

E23

bit, line 0, is set.

E32
E33

Tests that interrupt does not occur at level 7.

M7821 (Jumper wiring and proper

parity chip)
23

Tests that interrupt does not occur at level 6.

M7821 (Jumper wiring and proper

parity chip)
24

Tests that interrupt does not occur at level 5.

M7821 (Jumper wiring and proper

parity chip)

5-5

Table 5-3 (Cont)

DJ11 Diagnostic Logic Tests and Fault Location

Probable
Fault

Test Description

Test
No.

Dwg.

Comp.
Loca.

Tests that interrupt does occur at level 4.

M7821 (Jumper wiring and proper

Tests that interrupt does occur at level 3.

M7821 (Jumper wiring and proper

Tests that interrupt does occur at level 2.

M7821 (Jumper wiring and proper

Tests that interrupt does occur at level 1.

M7821 (Jumper wiring and proper

Tests that interrupt does occur at level 0.

M7821 (Jumper wiring and proper

Tests that line O can transmit and receive a character
(377).

M7285
M7279

1$:

parity chip)

D2-7

checks that DONE sets in a
reasonable time.

2$:

checks that valid data (CHAR
PRESENT) is in F1/FO.

3$:

checks that no errors are in

FI/FO.

4%:

checks that right line no. (0)
is in FI/FO.

5%:

checks that character length
is right.

6$:

checks that correct data
received.

78:

checks that CHAR PRESENT
clears.

8%:

thru

checks that DONE clears.

Tests that lines 1 through 15 can transmit and receive

a character (377), in similar fashion to above.

5-6

(Same as above)

All
All

Table 5-3 (Cont)

DJ11 Diagnostic Logic Tests and Fault Location
Test

Test Description

Probable

No.
52

Dwg.

Fault
Tests that RBUF 15 Valid Data (CHAR PRESENT)

M7285

is cleared by CLR MOS.

Comp.

Loca.
D2-8

E17
El4

E15

Test that Transmitter Ready clears when TBUF is

loaded.

M7279

All

M7280

All

M7285

D2-6

E39

E23
E49
NOTE

Because UART is double-buffered,

load two characters to insure seeing
Transmitter Ready

Clear.

Tests that Receiver Enable on a 0 inhibits DONE and

M7285

D2-7

Character Present.
55

E32
E15

Test that CSR 01 (H/D Select) disables receiver UARTS.

M7285

D24

E32
E17

E22

D2-2

ES5
El

Tests that Receiver Interrupt does not occur at level 5.

M7281 (Jumper wiring and proper
parity chip)

Tests that Receiver Interrupt does occur at level 4.

M7281 (Jumper wiring and proper

parity chip)
60

Tests FI/FO Overrun. Note the FI/FO should hold 64

characters.

M7285

D1-7

E32

E17
E22

D2-2

ES
El

60A

Tests that FI/FO comes up when 65th character is
received without reading FI/FO.

60B

Tests that reading the receiver buffer causes FI/FO
overrun to clear.

NOTE

Because of FI/FO timing, overrun can
come up after reading one character,
so a second must be read to insure that

FI/FO overrun is clear.

5-7

Table 5-3 (Cont)

DJ11 Diagnostic Logic Tests and Fault Location

Test Description

Test
No.

Probable
Fault

Dwg.

Comp.
Loca.

M7285

D2-2

Tests that FI/FO overrun interrupt doesn’t occur

60C

when the processor is at level 5.

Tests that FI/FO overrun interrupt does occur when

60D

processor is at level 4.

Tests that UART overrun is detected on all lines.

El
All

M7280

All

M7285

Tests that BCSR bits are R/W.

M7279

D2-2

ES
El

D2-3

El6
E2
E19

E35

Tests that line O can transmit and receive a break, and
checks RBUF 13 (framing error) and RBUF 12 (parity
error) if odd parity selected.

M7285

D2-2

D2-3

ES
El
El16
E2
E19
E35

Tests each line as in test 63.

(Same as above)

Tests that RESET clears all buffers.

M7285

D2-8

NOTE

Only CHARACTER PRESENT (bit 15)
is cleared.

Sends a binary count pattern on each line.

(Anywhere)

The error message printout is in the following format:

ADR

DJADR

(R1)

(R2)

(R3)

where:

ADR is the address of error HLT

DJADR is the CSR address of DJ11 under test
(Rn) is the contents of general register “n”.

5-8

(R4)

E13

NOTE
From none to four of these register contents will be typed

depending on the number following the HLT; e.g., “HLT+3”
would type (R1 through R3), whereas “HLT” would stop

after ADR and DJADR.

To find the failing test, look at the listing above the address typed. In most
cases the comment beside the HLT
indicates what logic was checked and what result was expected. Table 5-3 gives
possible starting points in the
determination of probable failing logic. Refer also to Figures 5-1 and 5-2, that provide
signal flow information for

maintenance purposes and aid in troubleshooting.

To recover from an error, restart test at location 200 or 1000. An error count is kept in
ERRORS, location 1202.
This count can be cleared from the console by restarting at 200 or by reloading the program.
Note that this diagnostic is configuration independent.

The Excreiscr and

ON-Line tesis comprise ihree subprograms that exercise up to i6 DJils.
NOTE

ACT11 and DDP monitors will run only Program 1 of this
diagnostic.

Program 1 is an off-line exerciser that operates on up to 16 lines simultaneously
in maintenance mode. Three
different data patterns, selectable from the switch register, are repeated a minimum
of 16 times for each pass. The
program should be run for at least 2 passes with all switches down. SW(9) on
a 1 disables the maintenance mode,

requiring turn-around cards at the termination of each line being tested. This

simultaneous feature, however, is not

always available in the field as only one turn-around card is supplied with the option.

CAUTION
When using the Exerciser Program in non-maintenance mode
on either the DJ11-AB or DJ11-AC options, a single error
will be reported for all unselected lines. These

message

messages can be ignored. This is explained below. Refer to

print D-IC-DJ11-0-10 for notes on termination of unused lines.

The DJ11-AB uses an M5900 Interface Module and the DJ11-AC uses an M5902. When
unterminated lines are

connected to these boards, they input a space causing the UART to assemble a break
character

into the FI/FO. The program will then see a character from an unselected line and print

one message will be printed for each unterminated line so long as that spacing

occur on the DJ11-AA since the M5901 module inputs a mark for unterminate

and then dump it

out an error message. Only

condition continues. This does not

d lines.

Program 2 is an On-Line Continuous Echo Exerciser that continuously transmits

the last character received on the

respective line. A null (000) will echo 72 times and then turn off the
transmitter. This program is operator

dependent, it will not loop. Program 3 is an On-Line Echo Test that first transmits
the text heading “Echo Test” and
then echoes everything that it receives.
CAUTION
On Program 3, if characters are received faster than they are
transmitted, software buffers may overflow.

o]
SETCSR O
ENABLE SCAN

PROGRESS-REC EN
INo
|LOAD
AY

je——— D27(7410E32)

-TEMP INHIBIT

{
'

INCREMENT

LINE COUNTER

CHECK FOR

e D2.7(8815.649) [SAMPLEiNC SCAN'COAD STLO]

e
mm—

D2-8 (7402-E14) [UC‘I MASTER DA‘]
+

DATA AVAIL

UC2 MASTER DA

D2-7 (7474-E22)

DATA

[LOAD SILO CONT (1)]

AVAILABLE

SET
?

D2-4 (74175-E64)

EOC SET FOR

THIS LINE

YES

EOC
SET

P D2-7 (7404-E46)

{READY IN}

SET RCV EN
WAIT 1 sec

SET FI/FO
OVERRUN

[H/D SELECT)

l@—— D2.4(74151-E65)

[EOC LINE 15:00]

RESET DATA

AVAILABLE

—

D2.7 {74175-E12) l

[LOAD SILO CONT (11}

CSR 13

ASSERT

D27 (74175-E12)

LOAD SILO

[START LOAD (0)}

D27 (7410-E32) | READY IN
MASTER DA

SAMPLE LINE

sILo

LOAD

VES

COM':LETE

M7279 D113

(14H74-E25)

[LOAD IN PROG]

RESET DATA
AVAILABLE

ASSERT
READY

D2-7 {74123-€28)

M7279 D11-2 {7420-E9)
[READY IN]

11-1845

Figure 5-1

DJ11 Receiver, Maintenance Flow Diagram

Program 3 is also operator dependent. It is loaded with the standard ABS tape procedures. For worst-case testing, set

all switches down. The program should be started at 200 but may be restarted at 1000. For Program 1 only, the bell
will ring upon completion of a pass of the entire program, and alternate passes will run with T bit set. To set the T
bit, put SW(12) on a 0. When T is set, the processor traps after each instruction.

HLT operation and Error Printout Format are the same as the logic test diagnostic. For more information, refer to
the Diagnostic Abstract.

5-10

D2-4 (74175-E31)
MASTER

[BDOS]

YES

SCAN SET
CSR8

|
START TRAN

AR RN

D2-6 {7410-E32)

p————

—_—

RMQUJ
: M]

+ MASTER TRAN SCAN EN

SAMPLE TCR-TBMT
&

LOAD

D2-5 (74175-E51, 53, 56
plf———————

LATCH

& E68)

{TRANS SAMPLE CK]

D2-5 (7400-E52)

[GROUP SIGNAL]

HALT CLOCK

SET READY

f-———

D26 (7474-E23)

[GROUP SIGNAL}

WAIT FOR
CHAR LOAD

D2-6 (7402-E63}

D2-6 (7400-E54)

[FOR CLEAR FLAG]

SEL 06-OUTLOW
+300 ns

TCR CLEAR

FOR THIS

LINE

D2-6 (74123-£39)

STROBE UART

SEL 06:OUTLOW-

300 ns

RESTART
CLOCK

j@——————

D26 (7410-E32)

[SEL 06-OUTLOW:
£800 ns

11-1846

Figure 5-2

5.4

DJ11 Transmitter, Maintenance Flow Diagram

DJ11 TEST PROCEDURE

This procedure is in two parts: a) verifies the internal logic in maintenance mode, and b) checks the unit output
interface logic by driving signals to a terminal or by looping signals beyond the output interface card. For
maintenance procedures, only those lines in question can be tested. For initial checkout, all lines should be checked.

5.4.1

Logic Verification DJ11-AA, AB, AC

For this procedure, the output cables need not be connected to the M5900, M5901, or M5902 Output Interface
Card. All speeds should be strapped to 9.6 kbaud (split lug no. 3) to shorten test time.
1.

Using the scope, verify that the pulse trains listed below exist at all split lugs from 1 through 11.

NOTE

They will not all be square waves. Do not verify frequency
tolerance. They are all crystal controlled and will be more
accurate than any scope measurement.

5-11

—

6.5

Period (us)

34.8

1IN

Lug No.

208

104

416

566

—_

832

465

If any signals are not present, check divider chain on M7285, sheet D2-9.

Load logic test (DZDJA-A-PB). Refer to document for startup procedure.

Run unit for 5 minutes. If errors occur, refer to Paragraph 5.4.5 for more information. Also, check the
diagnostic document for hints in troubleshooting. Use Table 5-3 as a guide in locating the probable fault.
Once the fault has been located, rerun exerciser for at least two passes to verify fault correction.
NOTE

Proceed to proper test below for configuration being tested.

5.4.2

Interface Check DJ11-AA

This is the EIA version of the DJ11. In addition to regular test equipment, this test requires an EIA terminal, such as
a VTO05 and a BCOS cable, plus an H312 Null Modem. In addition, an H315 Test Connector is required.
1.

With the unit still set for 9.6 kbaud, attach the H317B Distribution Panel to the M5901 card using the
two BCO8S-15 cables supplied. These cables must be carefully polarized. Refer to Figure 2-3 for
instructions.

Add the H315 Test Connector to the first line to be tested.

Load exerciser tape DZDJB-A-PB, select the first line to be tested, and run one pass of Program 1 in
standard configuration.

Run one pass of Program 1 with SW(9) up.
NOTE

This forces test to run in non-maintenance mode, and shows
up cable problems along with problems with H317B and/or
M5901.

Repeat steps 1 through 4 for each of the other lines to be tested, resetting the test connector, resetting
the program, and reselecting the appropriate line each time.

Strap DJ11 to 2400 baud (lug 1) and set VTOS accordingly. Attach VTOS to first line to be tested using
VTOS cable and an H312 Null Modem.

RunProgram 2 (Echo Test). Hit several keys on keyboard to ensure proper operation.

Move cable down a line at a time for each line to be tested, hitting several keys for
each line until
questionable lines are verified.

all

NOTE

The following tests require either a DM11 Distribution Panel
or a DCO8-CS Telegraph Line System Option. If these are not

available,

the

following

tests

cannot

performed

described.

5.4.3

Interface Check DJ11-AB

This is the TTL version of the DJ11. In addition to regular test equipment, this test
requires a DM11 Distribution
Panel (7008443). If this is not available, the lines can be looped through a DCO8-CS. In
this case, proceed to step 6
below.
1.

With the unit still set for 9.6 kbaud, attach DJ11 to DM11 Distribution Panel using
a single BC0O8S-15

cable plugged into J1 connector of M5900 at one end, and the M971 plugged into slot
B1 of 7008443

assembly at the other end. Be careful to observe cable polarities. Use the M974 DM11

turn the lines around at the DM11

Test

Connector to

panel (slot B3).

Load exerciser tape DZDJB-A-PB and run one pass of Program 1 in standard configuration.

Run one pass of Program 1 with SW(9) up.
NOTE

This forces test to run in non-maintenance mode, and shows
up cable problems along with M5900 problems.
4.

Connect BC08S-15 cable to connector J2 and slot B1 of DM11 panel observing proper cable polarities.

Run one pass of Program 1 with SW(9) up, plus select only lines 0—7 to run [SW(8) up, see progra
listing]. This verifies connector J2 on the M5900. This step concludes this test when a DM11

distribution panel is used.
6.

If the DJ11-AB is to be tested with a DCO8-CS (a current loop telegraph interface), the DJ11 MAINDEC
must be run with data looped at the output of the DCO8-CS. This unit uses TTL to switch high voltage

(60 to 80 Vdc approximately).

CAUTION

Do not wire the DCO8-CS Receiver directly to the transmitter

or smoke may result. Refer to the DCO8 documentation.

The only resistance in the circuit when the transmitter is looped to the receiver is 10082 located in the
relay coil. Since the maximum current through the coil is 100 mA, a current limiting resistor must be
used between the transmitter and receiver. The value of the resistor is a function of the voltage used with

the DCO8-CS Interface. A typical resistor value would be 2.2 k€2, 2W for a 60V battery (refer to Figure
5-3 for pins to jumper).

5-13

—

TRANSMIT
LINE 00

- p3-p

LINE

|2|

——0

3
—
|
5

__pZ_A___@ 2 Q
+P3-C

RECEIVE{

SAME PATERN ON

/ALL TB'S

% P1-C

— ) 01

——

Q@ 6Q

__—

——
n

han
4

—

——
n

Q 8 QO

14
—

14
1

14
]

@100

T85

T86

]

°7

—

@ 7 O
o9

-1\

HHH

QD 4

3
|

5 )

o 3 @

TB4

783

182

TB1

14
—

TB7

188

o O

@12

@13 O

@14

—

—]
3

5 ]

— ) 17
7

@15 @+

16 O—=

— ? 21
7

—

—1 ) 24
3

]
3

5 1

|—

%% CAUTION: NEVER CONNECT
OUTPUT DIRECTLY TO INPUT.
JUMPER WITH 2.2K Q,

10
—
n

10
— ( 22
1
12

10
—— 7 26
1!
12

GROUND ON ALL TERMINAL
BLOCKS USED
s

[ 13 ]
14
-1

13 |
14
V23
L1

| 14 |

DCO8 MAINT MANUAL

('8

2W RESISTOR

%%% CONNECT 4,8,12,16 TO

15
16

|—

—— ¢ 29

— ) 25

% FOR PIN NOS REFER TO

13 |
15
16

»8

)

10
— ( 30
11
12

[ 13 ]
14 |
15

16
11-1847

Figure 5-3

DCO08-CS Test Jumper Chart

When the DCO8-CS output terminals have been jumpered (including the limiting resistor), run Exerciser
Program no. 1.
NOTE

Test will have no meaning unless SW(9) is on a 1, disabling
maintenance mode.

Run the diagnostic long enough to ensure that the DCO8-CS can pass data. This should be about 15
minutes or 2 passes, whichever occurs first. This concludes this test when a DCO8-CS is used.

5.4.4 Interface Check DJ11-AC

This is the 20 mA current loop version of the DJ11. In addition to the regular test equipment, this test requires a
special cable assembly (BCO4-R, P/N 7006594-0-0 or equivalent) with a Mate-N-Lok connector at one end and
screw-type terminals at the other end. In addition, a TTY type terminal, preferably a VTOS set for 2400 baud, is
required.

5-14

Strap DJ11 to 300 baud (lug 6) and connect cables between M5902 and H317A Distribution Panel.

CAUTION

Cables are

neither marked nor keyed and, if improperly

connected, can damage equipment. On the H317A the rib side

of cable must be away from the board. On the M5902, the
smooth side of the cable must be away from the board (Figure

2-3).

Run Program 1 of DZDJB-A-PB for one pass under standard configuration.

Using the special cable, connect the VTOS to line 00 and set the VT0S for 300 baud.

Run Program 2 (Echo Test). Hit several keys on keyboard to ensure proper operation. Line 00 must be

selected in response to opening program dialogue.
5.

Repeat steps 3 and 4 for each line, hitting several keys for each line until all 16 lines are verified. For
maintenance purposes, only those lines in question need be verified.

5.4.5

Error Analysis During Test

As explained under diagnostic testing, error typeouts that occur during the logic tests provide the ERROR PC, the
CSR address of the faulty DJ11. and other information such as expected data and received data that are a function

of the test being run. There are 66 individual routines in the logic program alone. The sections of the logic that
these tests check can be grouped into various categories as follows:

Test 1

Checks M 105 response.

Tests 2—17

Check all R/W register bits.

Tests 20—22

Check transmitter scanner.

Tests 23—-32

Verify the capability of the DJ11 to interrupt and to interrupt at correct level.

Tests 33—52

Do a transmit and receive character check for each line. See description of items
checked in program listing.

Tests 53—-56
Tests 57—60

Check various miscellaneous features such as clear MOS bits, haif dupiex, etc.
Check receiver interrupt level.

Test 61

Tests FI/FO overrun bit.

Test 62

Tests UART overrun.

Tests 63—64

Check break operations.

Test 65

Checks reset operation.

Test 66

Does a binary count data check.

These tests are listed in the Diagnostic Abstract. In the listing, references are made to the suspected IC that could be

at fault. This information is also listed in Table 5-3. It should be noted that these references are merely the most
obvious location of trouble; trouble could exist elsewhere in the logic chain either leading to or from that IC. It will

be necessary to trace back or forward through the logic levels to locate the specific faulty component.

When analyzing various problems with the transmitter and receiver sections of the DJ11, several static checks can be

made to simplify the troubleshooting process.

To checkout the transmitter section, use the following procedure:
1.

Remove both M7280 cards.

Set only CSR (08).

5-15

With the scope, check E33, pin 13, for the clock signal shown in Figure 5-4. Trace the signal through to
all destinations (pins 9 of E51, E53, E56, and E68). This verifies that the clock is running and that it is
present at all its destinations. At any point that it does not appear, of course, further standard
techniques should be followed.

400
ns

11-1848

Figure 5-4

Clock Signal

Set any TCR bit (register 04).

The transmit clock signal, E33 pin 13, should have stopped, and the high byte of TBUF should contain
the line number. If the clock has not stopped, check Ready flip-flop E23 or E32. If necessary, trace back
from these points to find the fault.

If the results of step 5 are correct, the following program should be toggled in to determine if the UART
can be loaded with characters.
NOTE

The addresses given are dependent upon which DJ11 in the
system is being tested.

200 :

MOV # 400, CSR

12737
000400

160020

MOV # 100000, TCR

12737
100000
160024

TST CSR

005737
160020

BPL -4
MOV # 0, TBUF

100375
12737
00000

160026

JMP 200

000137
000200

With the above program running, check that pulses appear at E39, pins 5 and 13. The pulse at pin 5
should be 1 us +200 ns. The pulse at pin 13 should be 300 ns +50 ns. This check verifies that the
transmit buffers (E9 and E40) are being clocked. If pulses do not appear, troubleshoot further.

The above procedure should have verified all transmitter logic on the M7285 card. If the transmitter still
does not function, check the M7280 (UART) cards and the M5900/01/02 output interface cards.

5-16

50ns ———=

jo—

300ns —‘i -

£44-3811_] J-I_l—l.
EO0241
EO2S1

L1-S

E£0242
EO2R1

EO2K1
EO02S1

EO2N1

DO2N1

CONDITIONS:
M7279 REMOVED
M7280s in unit

CSR(0)= (1)

i1-1849

Figure 5-5

Receive Scan Timing, Waveform No. 1

Remove silo card M7279 from unit. UART cards are left in unit.

To checkout the receiver section, use the following procedure:

Set CSR (00).

The pulse train shown in Figure 5-5 should appear at E44 pin 3 and 11. All other signals shown on
Figure 5-5 should appear at the pins indicated.

Remove both UART cards and jumper pin C2L2 to ground on the back plane. Remove power for this
step.

Replace power and reset CSR (0). Refer to Figure 5-6 and verify all pulses illustrated. If any signals do
not appear, further troubleshooting is required from these points. If all pulses are found and trouble still
persists, refer to the schematics on either the M7280 board or the Silo board, M7279.
NOTE

The above procedure has merely verified that the receiver

scanner is capable of providing all signals to remove the
character from the UART and place it in the silo. It has not

verified that data errors have not existed or occurred in those
characters.

1t CYCLE

350ms —»

}t—

J T

f— 1us —+]

UL
e

1ps —

T IUT

E44 PIN 5 _J

E22 PIN 3

‘I

]

50ns PULSE

BO2F1

BO2J2

—

E34 PIN 4

E22PIN S

BU1

1-1850

CONDITIONS:
M7279

Removed, M7280s Removed,CSR (0)=1,0nd CO2L2 grounded.

Figure 5-6

Receive Scan Timing, Waveform No. 2

5-18

CHAPTER 6
ENGINEERING DRAWINGS

6.1

GENERAL

Table 6-1 contains a brief list of applicable engineering drawings for the DJ11 including
those drawings referenced in
this manual. For a complete set of engineering drawings, refer to DJ11 Asynchrono
us Multiplexer Engineering
Drawirigs.

Table 6-1

DJ11 Engineering Drawings

Eng.

Sketch

Drawing

No.

D1-1

D-BS-DJ11-0-7

DJ11 Control Interface

D2-2

D-CS-M7285-0-1

thru

DJ11 Mux Control Board

Sheets 3—10

Title

D2-9
D3-2

D-BS-DJ11-0-3

thru

Sheets 2—5

D3-5

D-CS-M7280-0-1

Mulitipie UART Card, Lines 00—07

Sheets 3—6
D4-2

D-BS-DJ11-04

thru

Sheets 2—5

D4-5

D-CS-M7280-0-1

Multiple UART Card, Lines 08—15

Sheets 3—6

D11-2

D-BS-DJ11-0-6

FI/FO Buffer

Sheet 2

D11-3

D-BS-DJ11-0-6

Sheet 1
D-CS-M7289-0-1

Sheets 1&2

D33-2

D-CS-M5900-0-1

DJ11 TTL Output Interface

6-1

Table 6-1 (Cont)

DJ11 Engineering Drawings
Eng.

Eng.

Sketch

Drawing

No.

Title

D33-2

D-CS-M5901-0-1

DJ11 EIA Output Interface

D33-2

D-CS-M5902-0-1

DJ11 TTY Output Interface

—

D-IC-DJ11-0-8

Interconnection Diagram (DJ11-AB)

Sheets 1&2

D-IC-DJ11-0-9

D-IC-DJ11-0-10

Interconnection Diagram (DJ11-AA)

Sheets 1&2

Interconnection Diagram (DJ11-AC)

Sheets 1&2

D10-1

D-IC-DJ11-0-5

Unibus Connectors

—

D-CS-H315-0-1

Modem Test Connector

C-IA-BC08S-0-0

I/O Cable Assembly (Diag Jumper)

C-CS-M105-0-1

Address Selector (M105)

—

C-CS-M920-0-1

Internal Bus Connector (M920)

D-CS-M7821-0-1

Interrupt Control (M7821)

D-CS-M971-0-1

Cable Interface Board no. 2

C-1A-7009179-0-0

Wired Assy (DJ11)

D-MU-DJ11-0-12

Module Utilization

B-DD-H317-0

H317 Cable Box Assy

D-UA-DJ11-0-0

Unit Assembly DJ11

6-2

APPENDIX A

IC SCHEMATICS

A.1

GENERAL

The DJ11 16-Line Asynchronous Multiplexer uses 21 types of integrated circuit chips (IC). A logic diagram of each,
including a packaging diagram with pin number designations and a truth table, is given in this appendix.

The following IC schematics are included:
3341

4-hit X 64-word Propagateable Register (FI/FQ)

7474

Dual D-Type Edge-Triggered Flip-Flops

74H74

D-Type Edge-Triggered Flip-Flops

7485

4-Bit Comparator

7490

Frequency Divider

7492

Frequency Divider

7493

Frequency Divider

8266

2-Input 4-Bit Multiplexer

8837

Hex, Unibus Receiver

8838

Quad Bus Transceiver

9305

Frequency Divider

9318

8-Input Priority Encoder

74121

Monostable Multivibrator

74123

Retriggerable Monostable Multivibrator with Clear

74151

8:1 Multiplexer

74153

Dual 4:1 Multiplexer

74155

3:8 Line Decoder

74157

Quad 2:1 Multiplexer

74161

4-Bit Binary Counter

74175

Quad D-Type Flip-Flops

74193

4-Bit Binary Counter

A-1

A.2 3341 4-BIT X 64WORD PROPAGATEABLE REGISTER (FI/FO) (Figure A-1)

The 3341 is a 64-word X 4-bit memory that operates in a first in/first out (FI/FO) mode. Inputs and outputs are
completely independent (no common clocks). The device is used in the DJ11 as an asynchronous buffer. When both

INPUT READY and SHIFT IN are high, the four bits on DO through D3 are loaded into the first bit position where

they stay until INPUT READY and SHIFT IN go low. This causes the bits to propagate to the second bit position (if

empty) where they are propagated to the bottom of the silo by internal control signals.

When data has been transferred to the bottom of the memory, OUTPUT READY goes high indicating the presence
of valid data. When both OUTPUT READY and SHIFT OUT are high, data is shifted out of the silo. This causes
OUTPUT READY to go low. Data is maintained until both OUTPUT READY and SHIFT OUT are low. At this time
the bits in the adjacent upstream cell are transferred into the last cell causing OUTPUT READY to go high again. If
the memory has been emptied, OUTPUT READY will stay low.

LOGIC BLOCK DIAGRAM

Dy —*

FIFO

SHIFT IN

—»

MAIN REGISTER
CONTROL LOGIC

CONTROL

LOGIC

[

OUTPUT| |,
STAGE |—»

MAIN REGISTER

STAGE

D, —»|

FIFO_

64 WORD x 4 BIT

6 | INPUT

—

)

OUTPUT

Q4
Q5

la—— SHIFT OUT

CONTROL | 14

LOGIC

}|—» QUTPUT READY

VSS=P|N 16

MASTER

RESET

1
Vgg:=PIN

INPUT
READY

SHIFT
ouT

Vee

Qo F— 13

s — o,

o b— 12

6 —| D,

Q; b— 1

SHIFT IN[] 3

3341
4 —1Dg

VIEW)

INPUT READY [] 2

3 —{sHIFTIN - ONTRoT — 14

7 —03

CONFIGURATION

(TOP

LOGIC SYMBOL

16[] Vss

15 [] SHIFT ouT
14 [7] OUTPUT READY

0o []4

13{] Qo

12 ] o4

Do [s

1] Qp

D3 []7

10[] Q3

Voo [ 8

9] MR

Q3 — 10
MASTER RESET

Ts
Vgg =PIN 16 +5V

Vpp= PIN 8 GND

11-1851

Figure A-1

3341 4-Bit X 64-Word Propagateable Register
A-2

A.3

7474 DUAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS (Figure A-2)

The 7474 consists of two D-type edge-triggered flip-flops. Each flip-flop has individual direct clear and preset inputs
and complementary Q and Q outputs. Input information is transferred to the outputs on the positive edge of the

clock pulse.

Truth Table (Each Flip-Flop)

th
Input

Signal/Pin Designations

tytl

Signal Name

Output

Circuit no. 1

Circuit no. 2
12

CLOCK

CLEAR

NOTES:

1. t, = bit time before

clock pulse.

PRESET

2.t *1 = bit time after
clock pulse.

PRESET o

}

CLEARO—

CLOCKO

—

11-1852

Figure A-2

7474 Dual D-Type Edge-Triggered Flip-Flop

A.4 74H74 D-TYPE EDGE-TRIGGERED FLIP-FLOPS (Figure A-3)

The 74H74 consists oftwo D-type edge-triggered flip-flops. Each flip-flop has individual clear and preset inputs and
complementary Q and Q outputs. Information at input D is transferred to the Q output on the positive-going edge of
the clock pulse.

Signal/Pin Designation

Truth Table (Each Flip-Flop)

th
Input

thtl

Signal Name

Output

Circuit no. 1

CLOCK

CLEAR
PRESET

1
4

13
10

H = high level, L = low level

NOTES:

A. t, =bit time before clock pulse.
B. t *1 =Dbit time after clock pulse.

CLEARO—

=
11-1853

Figure A-3

. Circuit no. 2

74H74 D-Type Edge-Triggered Flip-Flops

A.5

7485 4BIT COMPARATOR (Figure A-4)

The 7485 performs magnitude comparison of straight binary or straight BCD codes. Three fully decoded decisions

(A>B, A<B, A = B), about two 4-bit words (A,B), are made and are externally available at three outputs.

Truth Table

A3, B3

Comparing

Cascading

Inputs

Inputs
A<B

A2, B2

Al,Bl1

A0, BO

A>B

Outputs
A=B

A>B

A<B

A=B

A3 > B3

A3 <B3

A3 =B3

A2>B2

A3 =B3

A2 <B2

L
L

A3 =B3

A2 =B2

Al >BI

A3 =B3

A2=B2

Al <BI

A3 =B3

A2=B2

Al =Bl

A0 > B0

A3 =B3

A2=RB2

Al =Bl

A0 <BO

A3 =B3

A2=B2

Al =Bl

A0 =BO

A3 =B3

A2 =B2

Al =Bl

A0 =B0

A3 =B3

A2=B2

Al =Bl

A0 =B0

NOTE:

H = high level, L = low level, X = irrelevant

Signal/Pin Designation
Signal Name

Pin Designation

[ A0

Inputs

Outputs

A<B

A>B

A=B

A>B

A=B

A<B

A-5

Y
1

A3 \L5)
83

(1)

]

(5) A>S

(13)

(14)

I
4

-3

LA<B1TIN

\cy

—
.—\

(3)

LA BT IN o—

LA<B! IN

(4)

A=B

(12)

(11)

(7)

(10)
(9)

:I
Pin (16)=Vcc, Pin (8)=GND

Figure A4

7485 4-Bit Comparator

A-6

)

1-ig54

A<B

A.6

7490 FREQUENCY DIVIDER (Figure A-5)

The 7490 consists of four dual-rank, masterslave flip-flops internally interconnected to provide a divide-by-two

counter and a divide-by-five counter. Gated direct reset lines inhibit count inputs and return ail outputs to 0 or to a

binary coded decimal (BCD) count of 9.

Truth Tables
BCD Count Sequence

(See Note 1)

Count

Output
D

A
0

Reset Count

(See Note 2)
Reset Inputs

Output

Ro(1)

Ro(2)

1001

COUNT

Ro(1)

Ro2)

DCBA

0000

COUNT

NC = No Internal Connection

Notes:

1. Output A connected to input BD for BCD count.
2. Xindicates that either a logical 1 or a logical 0
may be present.

A-7

DUAL-IN-LINE PACKAGE (TOP VIEW)

INPUT

GND

CH+¢

AH-

—acp

—

'NggT Ro(1) Ro(2y

LR DJ

——olcp

$
J Y¥s
{s2

Vce

o"‘

Roqy) Rg(2)

t1-1855

Figure A-5

7490 Frequency Divider

A-8

A.7

7492 FREQUENCY DIVIDER (Figure A-6)

The 7492 is a 4-bit binary counter comprising four master-slave flip-flops internally connected to form a
divide-by-two and a divide-by-six counter. A gated direct reset line inhibits the count inputs and simuitaneousiy
returns the four flip-flop outputs to logical 0.

Truth Table
Count

Outputs
D

DUAL-IN-LINE PACKAGE (TOP VIEW)

GND

f2]

D
8

T T ERT G J Dj
cP

—talcp

-0l CP

{

INPUT

Vee

Roqr)

Rofz)

11-1856

Figure A-6

7492 Frequency Divider

A.8

7493 FREQUENCY DIVIDER (Figure A-7)

The 7493 is a 4-bit binary counter comprising four master-slave flip-flops internally connected to form a
divide-by-two and a divide-by-eight counter. A gated direct reset inhibits the count inputs and simultaneously

returns the four flip-flop outputs to logical 0.

Truth Table

Output

Count

1
2

3
4
5

DUAL-IN-LINE PACKAGE (TOP VIEW)

INPUT

GND

J aH [ e[v chv oJ

Rozy

Veg

INEUT Ro()

Locp

Lolcp

-o|cP

11-1857

Figure A-7

7493 Frequency Divider
A-10

A.9

8266 2-INPUT 4-BIT MULTIPLEXER (Figure A-8)

The 8266 is a 2-input 4-bit digital multiplexer that has the capability of choosing between two different 4-bit input
sources as controiled by one selection input while the other input is held to O.

Truth Table

Select

Lines
So

Output
S

f,(0,1,23)

Vee

GND

11-1858

Figure A-8

8266 2-Input 4-Bit Multiplexer

A.10 8837 HEX UNIBUS RECEIVER (Figure A-9)

The 8837 consists of six inverters whose inputs have Unibus characteristics with common enable on sets of three.
When the strobe disables the receivers, all outputs are forced low.

Signal/Pin Designations

Pin Designation

Signal Name

IN 1

IN2

IN3

IN 4

INS

IN6

OouT1

OUT 2

OuUT 3

OuT 4

OUT 5

OuTe6

STROBE 1,2,3

STROBE 4,5.,6

Vee

9
16

Grd

[14] [3] 2] [] o] [9] [e
N

AX | 080

080

l[fl G @G B

Tve
I

L
(¥4-] phinke
MAX

MAX

002

-015

|e
140

MAX

f 020 max

[

125 MAX

|leo7s ‘lmo

010

OUT,y

OuT,

'"rD—:Do_somZ ) >
IN

010

326025

INg

IN,

INaAD;
STR]oaag |

ING‘-D— :Dofoure

0 VT3

STROBE

456

o 1
003

11-1859

Figure A-9

8837 Hex Unibus Receiver

A-12

A.11

8838 QUAD BUS TRANSCEIVER (Figure A-10)

The 8838 consists of four identical receiver/driver combinations in one package for use on the PDP-11 Unibus. Data

from the equipment on DATA IN 1, e.g., appearing on pin 2 will be driven out of pin 1 (BUS 1) to the Unibus (if
enabled). A BUS 1 signal received from the Unibus on pin 1 will be fed out of pin 3 (DATA OUT 1) to the
equipment,

Signal/Pin Designations
Signal Name

Circuit
1

BUS

DATA IN

DATA OUT

ENABLE

GROUND

1
BUS 1 1

Vee

DATA INT —

BUS 4

3
DATA OUT 1 ———

DATA IN 4

BUS 2 —2

5
DATA IN2 ——

DATA OUT 2 —>|
ENABLE A —
GROUND

pataout 4
BUS 3

DATAIN3
DATA OUT 3

ENABLE B

((———————BUS 1
—_

ENABLE A

;

—

DATAIN1——

\\__/’

DATA OUT1

ENABLE B
ONE OF FOUR
11-1860

Figure A-10

8838 Quad Bus Transceiver

A-13

A.12 9305 FREQUENCY DIVIDER (VARIABLE MODULO COUNTER) (Figure A-11)

The 9305 consists of four master-slave flip-flops that are separated into a single toggle stage and a three-stage
synchronous counter. By external connections, the device can be programmed to provide division or counting by
either 2 and 4, 5, 6, 7, 8, or 10, 12, 14, 16. This configuration allows synchronous binary counting by the last three
stages and independent modulo 2 operation with the first single stage.

Asynchronous Mode

COUNT

Alternate
Programming Connections

Programming Connections
For Last Three Stages

For Last Three Stages

Modulo

Q
NC
Q,
NC

Q
3

NC
Q
NC
Q,

Q,
Q

6
6
7
7

Modulo

Q
Q,
Q

Q
Q,
Q,

6
7
8

8
8

NC = Not Connected

Connections for Modulo 10, 12, 14, 16
Binary Counters and
50 Percent Duty Cycle Dividers
For Binary Counting

QO connected to CPI
Incoming clock to CP

For 50% Duty Cycle Output
Q3 connected to CPO
Incoming clock to CP

A-14

Available

Modulo

Output

Output
Fanout

14/8

14/7

15/7

LOGIC DIAGRAM

Ls 5o 0~L1

s "0olg |

s °0 ¢

)

»)

s 0 @ of—+

O—Do—acP

——. N

R cp 0P+

——acp

[

-q CP

R cp G~

Figure A-11

”

(O =PIN NUMBER

9305 Frequency Divider (Variable Modulo Counter)

A-15

L% gop
e
T

alds)

cPyf_Ji0

Jo2 o[ s

7[Jono cp [

we[
s

R cp Qp—

6000

Vee[
e

s[jasz

R cp @

ITMMS

2[Jas

A.13 9318 8INPUT PRIORITY ENCODER (Figure A-12)

The 9318 8-Input Priority Encoder accepts data from eight active low inputs and yields a binary representation on

its three active low outputs. Each output is assigned a priority such that when two or more inputs are simultaneously
active, the input with the highest priority is represented on the output. Input line 7 has the highest priority.

The number of priority levels is increased by cascading encoders by connecting the most significant output (EO) to
the next most significant encoder’s enable input (EI).

A group signal output (GS) is active level low when any input is low indicating when any input is active. An enable
output (EO) is also active level low when all inputs are high.

Truth Table

H
L

X
H

H
H

H
L

L
L

X
X

X
L

L
H

L
L

L
H

L
L

H
H

L
L
L
L
L
L

X
X
X
X
X
L

X
X
X
X
L
H

X
X
X
L
H
H

X
X
L
H
H
H

X
L
H
H
H
H

L
H
H
H
H
H

H
H
H
H
H
H

L
L
L
L
L
L

L
H
L
H
L
H

H
H
L
L
H
H

L
L
H
H
H
H

H
H
H
H
H
H

H = High Voltage Level
L = Low Voltage Level

X = Do Not Care

1213 14 15

HIGHEST PRIORITY LEVEL

f ENABLE

586

€&

9318

8 INPUT PRIORITY ENCODER

174 9002

E0__Ao

c¢s

fi‘

PRIORITY ADDRESS

fi'

A2
?

cs
?

|MOST SIGNIFICANT
ENCODER

1/4 9002

174 9002

fi’

PRIORITY FLAG

Figure A-12 9318 8-Input Priority Encoder
A-16

n-1862

A.14

74121 MONOSTABLE MULTIVIBRATOR (Figure A-13)

The 74121 is a monostable multivibrator that provides dc triggering from positive or gated negative-going inputs

with inhibit capability. Pulse triggering, at a particular voltage level, is not directly related to input pulse transition

time. Once fired, outputs are not dependent on further input transitions, but rather are a function of timing
parameters.

Truth Table
tu Input

tn+1 Input

Output

Inhibit

One Shot

Inhibit

0= Vin(O) <0.8V

|13

TIMING PINS

~__ NC

|10

11-1863

Figure A-13

74121 Monostable Multivibrator

A-17

A.15 74123 RETRIGGERABLE MONOSTABLE MULTIVIBRATOR WITH CLEAR (Figure A-14)
The 74123 Multivibrator provides dc triggering from gated low level active (A) and high level active (B) inputs. It

also provides overriding direct clear inputs and complementary outputs. The retriggering capability simplifies
generation of extremely long duration output pulses. If the input is triggered before the output pulse is terminated,
the output pulse is extended. An overriding clear feature allows any output pulse to be terminated at a
predetermined time, independent of timing components.

JORN DUAL-IN-LINE OR

W FLAT PACKAGE (TOP VIEW)

Vee

1Re)fl
Cext

1
Cext

2
CLEAR

gLEAR

Q4|

)

(

E:’::II ol

T e
X

|(|>»
-

B|Q

XTI

INPUTS | OUTPUTS

TRUTH TABLE

GND

positive logic

Low input 10 clear resets Q to low
level and inhibits datainputs
11-1864

Figure A-14 74123 Retriggerable Monostable Multivibrator With Clear

A-18

A.16

74151 8-LINE TO 1-LINE MULTIPLEXER (Figure A-15)

The 74151 selects one of eight data sources for multiplexing the output onto one line. The circuit can be used for
paraliel-to-serial conversion or as a five-variabie function operator.

Truth Table

Inputs

Outputs

Strobe

)

X
X

0
1

1
0

When used to indicate an input, X = irrelevant.

J OR N DUAL-IN-LINE
W FLAT PACKAGE (TOP

DATA

INPUT

DATA

VIEW)
SELECT

DATA INPUTS
e

8
GND

ouTPuTs STROBE

_POSITIVE LOGIC

Y=S(ABCD(+ABCD1+ABCD 2+ABCD3+ABCD4+ABCDs+ ABCDg
ABCD7)

W=Y

-0634

A-19

sTROBE (7)

(ENABLE)

4
rDO()

Dyo

Dz (o

DATA

(3)

(2)

(5)

0301”

INPUTSfi

::}1

(15)

]

OUTPUT

(®)s outPUT W

(14)

(13)
Dg 0—

}—

c(12)

(11)
>(>—4L—1 >O—A
A o———{

GND:=PIN8

8
B

(10)

B
ol

DATA

SELECT <

(BINARY)

11-0635

Figure A-15

74151 8-Line to 1-Line Multiplexer

A-20

A.17

74153 DUAL 4-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER (Figure A-16)

The 74153 is a dual 4-line to 1-line multiplexer with separate strobe lines applied to each section. It can be used for
data multiplexing, parallel-to-serial conversion, pulse pattern generation, and as a Boolean function generation.

Address

ol qpie il el ol i

ol ol

Output

R e R e
e R e R R

Strobe

ol wn e ol ol sl

]

XTI
T X X
4

e R e R o "Rl
e

a ol ol ol e oiia ol el il

jasiasfasiiasll
ol el aall quli+*

e R e R e R e R ol"Rl

Data Inputs

Inputs

Address inputs A and B are common to both sections.
H = high level, L = low level, X = irrelevant

STROBE

(ENABLE)

1G _ (1)

(6)

(1coo-8L
(5)

1C10—

(7) . OUTPUT

DATA 1 {

(4)

'f'

1C20—

(3)

L1c30—-

J' 5 of2)

ADDRESS

A:(I4)

|>°

(10}

2C10-

(2c00—

(n)

DATA 2¢
2C20

(9)

(12)

(13)

\2C30—

STROBE zeo(‘5)

(ENABLE)
Pin (16) = Ve,

JouTPuT

Pin (8) =GND
11-1865

Figure A-16

74153 Dual 4-Line to 1-Line Data Selector/Multiplexer

A-21

A.18 74155 3-LINE TO 8-LINE DECODER (Figure A-17)

The 74155 3-Line to 8-Line Decoder consists of 1-to-4 line demultiplexers with individual strobes and common
binary-address inputs in a single 16-pin package. When both sections are enabled by strobes, the common
binary-address inputs sequentially select and route associated input data to the appropriate output of each section.
The individual strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied to an input
1C is inverted at its outputs and data applied at 2C is not inverted through its outputs. The inverter following the 1C
data input permits use as a 3-to-8 line decoder or 1-to-8 line demultiplexer without external gating. When used as a
decoder, data inputs 1C and 2C are connected to each other and used for enabling and for cascading.

3-Line To 8-Line Decoder

Outputs

Inputs

Select

Strobe | (0)

(1)

(2)

(3)

(5)

(6)

(7)

or Data

2Y0

2Y1

2Y2

2Y3

1Y0

1Y1

1Y2

1Y3

X
L
L
L
L
H
H
H
H

X
L
L
H
H
L
L
H
H

X
L
H
L
H
L
H
L
H

H
L
L
L
L
L
L
L
L

H
L
H
H
H
H
H
H
H

H
H
L
H
H
H
H
H
H

H
H
H
L
H
H
H
H
H

H
H
H
H
L
H
H
H
H

H
H
H
H
H
L
H
H
H

H
H
H
H
H
H
L
H
H

H
H
H
H
H
H
H
L
H

H
H
H
H
H
H
H
H
L

Signal/Pin Designation
Signal

Pin Designation

Name

STROBE 1G

STROBE 2G

SELECT A
SELECT B

13
3

DATA IC

DATA 2C

OUTPUT 1Y0

OUTPUT 1Y1

OUTPUT 1Y2

OUTPUT 1Y3

OUTPUT 2Y0

OUTPUT 2Y1

9
10

OUTPUT 2Y2

OUTPUT 2Y3

A-22

A
ENABLE/DATA

OUTPUT
1Y0

STROBE 16 o——c_x

__J/

DATA 1C

ENABLE /DATA

P000 Pt

ADDRESS SELECT

OUTPUT
1Y1

OUTPUT
1Y2

SELECT Bo——Do—J»—4>

OUTPUT
1Y3

OUTPUT
2Y0

SELECT A o—-Do—<>—4>

OuTPUT
2vi

OUTPUT
2y2

[\
STROBE 26—/
DATA 2C o———(Q

OuTPUT
2Y3

11-1866

Figure A-17

74155 3-Line to 8-Line Decoder

A-23

A.19

74157 QUADRUPLE 2-LINE TO 1-LINE MULTIPLEXER (Figure A-18)

The 74157 Quadruple 2-Line to 1-Line Multiplexer provides buffered inputs and outputs. All inputs are low when
disabled (enable high). The truth table and logic diagram are shown below.

Inputs

Output Y
SN54/74157

Enable

Select

SN54S/74S157

H = high level, L = low level, X = irrelevant

1ao2)

g d?

‘

(4)

2A (5)

l
0—1

2B ~(6)

(7)

‘

—

1g (13)

‘

—

ap 100

SELECT-r“) Dc

ENABLE o)

<{>

Pin (16) = V¢, Pin (8)=GND

Pin 16 =V¢c,Pin 8=GND

o ay

1n-1867

Figure A-18

74157 Quadruple 2-Line to 1-Line Multiplexer

A24

A.20

74161 4-BIT BINARY COUNTER (Figure A-19)

The 74161 binary counter is a 4-bit counter with internal look ahead for fast counting and a carry
output for n bit

cascading,

Count Enable

Load

(CEP - CET)

Mode

Count Up

No Change

Parallel Load

H= high level, L = low level, X = irrelevant
[

Loap o2
J

ceean

(14)

3
Qp

T ) e

DATA o2

FFD)\J % ( )OB
13

R
DATA

cLock

(4)
.

INPUTS

12)

J
—

doutputs

cLock

DATA

cLOCK

(s)
K

(2)
J

()

—9
ENABLE

cLock

(7)

DATA

EnasLe (10}
(O)

—CEP

-——{CET
CLOCK

(5)

)

Pin(16)=Vec . Pin (8)=GND

RippLE
CARRY

CARRY

J—CEP
—{CET

CARRY

[-—~CLOCK

L—CEP
CET

—{CLOCK

CARRY

|—-CEP
CET

CARRY

{*—4CLOCK

COUNT
F1-1868

Figure A-19

74161 4-Bit Binary Counter

A-25

A.21

74175 QUAD D-TYPE FLIP-FLOPS (Figure A-20)

The 74175 contains four D-type flip-flops with dual outputs. Each flip-flop has direct clear and buffered clock
inputs.

Input

Outputs

tn+1

t, = bit time before clock pulse.
t,+1 = bit time after clock pulse.

A O

(4)

(2)
QQb——o00Q,

) 3,
——dcLk Qa |
CLR

cLk

(6)

CLR

0———T
C o-

(12

(10)

Q0%

ck Q¢
CLR

(13)

(15)

QD ———————OQD

Do—

(9)

CLOCK O———|

an Qc

—qCLK

Qp—0aq,,

CLR

CLEAR

Pin (16) =V, Pin (8) = GND

11-1869

Figure A-20 74175 Quad D-Type Flip-Flops

A-26

A.22

74193 4-BIT BINARY COUNTER (Figure A-21)

The 74193 Binary Counter has an individual asynchronous preset to each flip-flop, a fully independent clear input,
internal cascading circuitry, and provides synchronous counting operations.

Signal/Pin Designation
Signal Name

Pin Designation

DATA INPUT A

DATA INPUT B

DATA INPUT C

DATA INPUT D

CLEAR

LOAD

DOWN COUNT

BORROW OUTPUT

CARRY OUTPUT

UP COUNT

OUTPUT Q4

OUTPUT Qp

OUTPUT Q¢

OUTPUT Qp,

Count Up

Count Down

Load

Mode
Parallel Load

CLOCK

Count Up

CLOCK

Count Down

H = high level, L = low level, X = irrelevant

A-27

BORROW
QUTPUT

INPUT A

DOWN

COUNT

OUTPUT

DATA

_oCARRY

|:>c

PRESET

O OUTPUT Qp

dr
uP

COUNT

CLEAR

DATA

INPUT B

PRESET

OUTPUT
Qg

CLEAR ©

B
DATA

INPUT C ©

—

PRESET

[¢)

CLEAR ©

D
DATA

INPUT D&

CLEARO—DO
PRESET

-0 OUTPUT
Qp

CLEARGD

LOADO—{{:>C
11-1870

Figure A-21

74193 4-Bit Binary Counter

A-28

APPENDIX B

SIGNAL GLOSSARY

B.1

GENERAL

Table B-1 lists selected DJ11 signals in alphabetical order with their meanings. This table

use throughout the text.

is provided for reference

Table B-1
DJ11 Signal Glossary

Mnemonic
Di-1

INH

Definition
A gating control signal used to gate data from the device register
onto the bus (DATI + DATIP).

D1-1

INT REQL

This is the Interrupt Request sent out to the Unibus by the 7821

module.
D1-1

MIO05L2

A gating control signal used to gate data from the device register
onto the bus (DATI + DATIP).

Di-i

OUTHIGH H

A gating control signal used to gate D(15:08) into the high byte

of the device register.
D1-1

OUTLOWH

A gating control signal used to gate D(07:00) into the low byte of

the device register.

D1-1

SELOH

Selects the CSR as a result of address decoding.

Di-1

SEL2H

Selects the RBUF as a result of address decoding.

Di1-1

SEL4H

Selects either the TCR (if CSR 10 is 0) or the BSR (if CSR 10 is

1) as a result of address decoding.

Di-1

SEL 6 H

Selects the TBUF as a result of address decoding.

D2-2

BUF A(02:01) L

Buffered version of Unibus signals A(02:01), used to control
which set of 16 bits from either TBR, TCR, RBUF, or CSR are
sent out onto the Unibus.

B-1

Table B-1 (Cont)
DJ 11 Signal Glossary
Definition

Mnemonic

D2-2

BD 15(H):00(H)

Bus data from the Unibus fed back out to the DJ11 from the bus
transceivers.

D2-2

D 15(L):00(L)

Data lines 15:00 from/to the Unibus.

D2-3

TBR 15:00(L)/(H)

Transmitter Break Register bits 15:00 used to issue a break on
one of 16 lines designated by a discrete bit in this register.

D2-3

TCR 15:00 (H)

Transmitter Control Register. A specific bit is assigned to each
line. When asserted, allows selection of that line if TBMT for that
same line is also asserted.

D2-4

H/D SELECT (H)

Used to prevent reception on any line when that line is
transmitting.

D24

INHIBIT SILO LOAD (L)

Used during half duplex select to prevent loading of an assembled
UART character into the FI/FO.

D2-4

MAINT (H)

D2-4

MASTER TRAN SCAN

ENABLE (H)/(L)

Asserted on BDO2 to force entrance into the maintenance mode.
Asserted on BDO8 by program to enable running of the
transmitter clock. When clear, prevents TRAN RDY from setting.

D2-4

RCV ENABLE (H)/(L)

When asserted on BDO0O, enables receiver scan which allows
characters to be loaded into FI/FO. When clear, inhibits same.

D2-4

RCV INT ENABLE (H)

When asserted on BD06, permits DONE to cause an interrupt.

D2-4

READ TBR (H)/(L)

When asserted on BD10, permits access of TBR on SEL 04. When
clear, permits access of TCR on SEL 04.

D2-4

STATUS ENABLE (H)

When asserted on BD12, permits an interrupt to be generated on
a FI/FO overrun.

D2-4

TRAN INT ENABLE (H)/(L)

When asserted on BDI14, permits TRAN RDY to cause an
interrupt. When clear, negates same.

D2-4

WRITE CSR HIGH (H)

When asserted, permits reporting of the high byte of the CSR.

D24

WRITE CSR LOW (H)

When asserted, permits reporting of the low byte of the CSR.

D2-5

GROUP SIGNAL (H)

Asserted whenever the TBMT and TCR for any line is set. Sets
the READY flag and stops the scanner on that line.

D2-5

TRANS SCAN A:D (H)

Four outputs of a priority encoder that provides the binary
address of the line number of the line selected. Used to select the
proper UART and to indicate line number for each entry in the
FI/FO.

B-2

Table B-1 (Cont)
DJ11

Signal Glossary

Mnemonic

Definition

D2-6

SSYN INHIBIT (L)

Delays the generation of SSYN by the M105.

D2-6

TCR CLEAR FLAG

Asserted when the program clears the TCR bit for the line on
which the scanner has stopped. Used to restart the transmit
scanner when stopped on a line over which transmission is not

desired.
D2-6

TRAN DATA 1:8

Output of the transmit buffer holding register which drives the
UART during character loading. Represent the character to be
transmitted.

D2-6

TRAN READY (H)

Indicatcs that scanner has stopped on a line whose TCR and

TBMT bits are set. Shows that the UART can be loaded with a

character.
D2-6

TRAN STROBE (H)

A Transmit Strobe sent only to the UART that has been selected.
Used to strobe the character into the selected UART.

D2-6

TRANS SAMPLE CK (H)

Used to sample all line inputs of the TCR and TBMT.

D2-7

FI/FO OVERRUN (H)

Indicates to the program that the FI/FO is full and that a
character must be unloaded from the FI/FO before another
received character can be loaded.

D2-7

LOAD SILO (L)

When asserted on START LOAD, provides half of the interlocked
communication with the FI/FO enabling clocking of the FI/FO
chips.

D2-7

RCV DATA ENABLE (H)

Used to enable the received data leads of the selected UART
when a character has been assembled by that UART.

D2-7

RCV SCAN A:C (H)

BUF RCV SCAN A:C (H)
RCV SCAN D (H)/(L)

Selection signals to the UARTS. Result of output of RCV CHAN

# COUNT. Used as Receive Line selection signals throughout the
DJ11. Note that the two versions of Scan “D” allows selection of
either the high 8 or low 8 lines.

D2-7

READ RCV BUFFER (H)

Asserted anytime a character is read out of the FI/FO and is used
to increment the output of the FI/FO and to clear a FI/FO

OVERRUN condition.

D2-7

RESET DA (H)

Indicates that the FI/FO has been loaded. Used to clear the data

available flag for the UART from which that data has just been
taken.
D2-7

TEMP INHIBIT (L)

Asserted on RCV EN and RESET DA to inhibit receive scan

clock until setup time is adequate.

B-3

Table B-1 (Cont)
DJ11

Signal Glossary

Mnemonic

D2-8

BUSY CLEAR (H)

Definition

This bit reads back as bit 4 on the bus indicating that MOS CLR
is in process.

D2-8

DONE (H)

Indicates that a received character has been placed in the FI/FO
and is available for reading out.

D2-8

MOS CLEAR (L)

Used to clear bit 15 in all word locations of the FI/FO rendering
their contents invalid, and clears all UARTs.

D2-8

MASTER DA (H)

Indicates that data is available in the selected UART.

D2-8

REQRCVINT (H)

Sent to the interrupt card if a FI/FO OVERRUN exists with
status enabled, or when characters are available and the receiver
interrupt is enabled.

D2-8

RESET (H)/(L)

Asserted on BUS INIT and used to clear all DJ11 registers.

D29

RCV SPEED 0-3

Receive baud rate for lines 0—3 as jumpered.

D2-9

RCV SPEED 4-7

Receive baud rate for lines 4—7 as jumpered.

D2-9

RCV SPEED 8-11

Receive baud rate for lines 8—11 as jumpered.

D29

RCV SPEED 12-15

Receive baud rate for lines 12—15 as jumpered.

D29

TRANS SPEED 0-3

Transmit baud rate for lines 0—3 as jumpered.

D2-9

TRANS SPEED 4-7

Transmit baud rate for lines 4—7 as jumpered.

D29

TRANS SPEED 8-11

Transmit baud rate for lines 8—11 as jumpered.

D29

TRANSSPEED 12-15

Transmit baud rate for lines 12—15 as jumpered.

D29

S5SMHZ

Basic clock frequency output. Used on FI/FO board to eliminate

D3-2
thru

BUF DA LINE 07:00

Buffered version of signal indicating that data is available within
the UART receiver holding register for transmittal to FI/FO.

BUF FE LINE 07:00

Buffered version of signal indicating that a framing error (invalid
Stop code) has been detected in data character received on this

contention between FI/FO read and write functions.

D3-5

D3-2
thru
D3-5

line.

BUF OR LINE 07:00

Buffered version of signal indicating that an overrun has been
detected on character received on this line. This means that
another character was received by the UART before the previous
character had been transferred to the FI/FO.

Table B-1 (Cont)
DJ11 Signal Glossary

Mnemonic

D3-2
thru

Definition
Buffered version of signal indicating that a parity error has been

BUF PE LINE 07:00

detected in character received on this line.

D3-2

thru

Indicates that a full character (including Sto
EOC LINE 07:00 H

D3-5

half duplex operation.

D3-2
thru

transmitted from this line. Used to condition sil

(=N]

D3-5

Represents the assembled ASCII characters received on lines

RCV DATA 1:8

07:00 and sent to the FI/FO.

D3-5

D3-2

thru

The serial bit stream as transmitted on these lines.

SERIAL OUT 07:00 H

D3-5
D3-2

thru

A signal from each of these UARTSs indicating that the TBUF is

TBMT LINE 07:00 H

empty.

D3-5

D3-2

BUF RCV SCAN D

Buffered version of one of four binary outputs from the receiver
scanner used in line selection.

D3-2

BUF RDA LINE 07:00

A selected signal to the UART receivers on these lines used to

reset the Data Available flag in the UART status register.
D3-2

BUF RDE LINE 07:00

A selected signal to the UART receivers that enables the reading

of characters out of the selecied UART.
D3-2

BUF RESET

A buffered version of MOS CLR that clears the UART holding
register.

D3-4

BUF TRAN DATA 8:1

Buffered versions of the ASCII character to be transmitted as fed
to the UART.

D3-2

UC1 MASTER DA H

Indicates that data is available on any of lines 07:00. Used to
generate a MASTER DA to control silo loading.

D3-2

UC1 MASTER ORH

Indicates an overrun error has been detected in a character of any
of lines 07:00. Used to feed bit 14 of the FI/FO.

D3-3

UC1 RCVDATA 8:1L

Wire-ORed data outputs of UARTSs 07:00. Used to feed the data
inputs of the FI/FO.

D3-4

UC1 MASTER FE H

Indicates a framing error has been detected in a character on any
of lines 07:00. Used to feed bit 13 of the FI/FO.

B-5

Table B-1 (Cont)
DJ11 Signal Glossary

D3-4

Mnemonic

Definition

UC1 MASTER PE H

Indicates that a parity error has been detected in a character on

any of lines 07:00. Used to feed bit 12 of the FI/FO.
D4-2

Buffered version of signal indicating that data is available within

thru

BUF DA LINE 15:08

the UART receiver holding register for transmittal to FI/FO.

D4-5

D4-2

Buffered version of signal indicating that a framing error (invalid

thru

BUF FE LINE 15:08

Stop code) has been detected in data character received on this

D4-5

line.

D4-2

Buffered version of signal indicating that an overrun has been

thru

BUF OR LINE 15:08

D4-5

another character was received by the UART before the previous

character had been transferred to the FI/FO.

D4-2

thru

detected on character received on this line. This means that

Buffered version of signal indicating that a parity error has been

BUF PE LINE

15:08

detected in character received on this line.

D4-5

D4-2

thru

Indicates that a full character (including Stop bits) has been

EOC LINE 15:08 H

D4-5
D4-2

thru

transmitted from this line. Used to condition silo loading only on
half duplex operation.
Represents the assembled ASCII characters received on lines

RCV DATA 1:8

15:08 and sent to the FI/FO.

D4-5

D4-2

thru

The serial bit stream as transmitted on these lines.

SERIAL OUT 15:08

D4-5

D4-2

thru

A signal from each of these UARTSs indicating that the TBUF is

TBMT LINE 15:08 H

empty.

BUF RCVSCAND

Buffered version of one of four binary outputs from the receiver

D4-5

D4-2

scanner used in line selection.

D4-2

BUF RDA LINE 15:08

A selected signal to the UART receivers on these lines. Used to
reset the data available flag in the UART status register.

D4-2

BUF RDE LINE 15:08

A selected signal to the UART receivers that enables the reading
of characters out of the UART.

D4-2

BUF RESET

A buffered version of MOS CLR that clears the UART holding
register.

B-6

Table B-1 (Cont)
DJ11

Signal Glossary

Mnemonic
D4-2

UC2MASTER DA H

Definition
Indicates that data is available on any of lines 15:08. Used to
generate a MASTER DA to control silo loading.

D4-2

UC2MASTERORH

Indicates an overrun error has been detected in a character on any

of lines 15:08. Used to feed bit 14 of the FI/FO.
D4-3

UC2RCVDATAS8:1L

Wire-ORed data outputs of UARTs 15:08. Used to feed the data

inputs of the FI/FO.
D4-4

BUF TRAN DATA 8:1

Buffered versions of the ASCII characters to be transmitted as fed

to the UART.

D4-4

UC2MASTER FE H

Indicates a framing error has been detected in a character on any

of lines 15:08. Used to feed bit 13 of the FI/FO.
D4-4

UC2MASTER PE H

Indicates that a parity error has been detected in a character on

any of lines 15:08. Used to feed bit 12 of the FI/FO.
D11-2

CHARACTER AVAILABLEL

Generated by the FI/FO buffer whenever a valid character is

available at its output pins.
D11-2

RCV BUF 15:00H

Represents one 16-bit character including line number, errors,

and a valid data bit as stored in the FI/FO buffer.
D11-2

READYINL

Generated by the FI/FO buffer. Used by the receive scanner to

indicate that a character can be loaded in the FI/FO.
D112

READY OUTL

Generated by the FI/FO buffer. Indicates that a character is

ready for reading at the bottom of the buffer.
D11-3

CK CHARACTER

AVAILABLE L

Output of a hard-wired comparator that is used to vary the
amount of characters that can be accumulated in the FI/FO

before a CHARACTER DONE INT is generated.
D11-3

LOAD IN PROGRESS L

Generated by the FI/FO buffer control logic while a character is
being loaded in the FI/FO.

D11-3

LOADPULSEL

Generated when the FI/FO is loaded. Used to increment the silo
status register.

Di11-3

LOAD SILOH

Results from LOAD SILO L in the receiver scanner and is used to

clock the FI/FO chips.
D11-3

MOS CLEARH

Buffered version of D2-8 MOS CLEAR L. Used to initialize the
silo

control,

clear

the

silo

status

CHARACTER AVAILABLE indication.

B-7

to clear

Table B-1 (Cont)
DJ11 Signal Glossary

Mnemonic
D11-3

READSILOH

Definition
Generated when a character is READY OUT in the FI/FO and

reading is enabled. Used to read a character out of the FI/FO.
Delayed version is used to decrement the silo status register.

D11-3

SSR 13:08 H

Outputs of the silo status register, used by a comparator to enable
generation of a CHARACTER DONE INT.

D11-3

VALID DATAH

Generated on READY OUT and READ RCV BUFFER. Used to
set bit 15 in the FI/FO word to indicate that that word is valid
for reading.

B-8

APPENDIX C

FLOATING DEVICE AND VECTOR ADDRESSES
FOR COMMUNICATION DEVICES

C.1

INTRODUCTION

Starting with the DJ11, new communications devices are to be assigned floating

production devices are to be retained.

The

addresses. The addresses for current

word “floating” means that addresses are not assigned absolutely for the
maximum number of each

communications device that can be used in a system.

C.2

DEVICE ADDRESSES

Floating device addresses are assigned as follows:
a.

The

floating

address

space

starts

location

760010

and

designations).

extends

location

764000

(octal

The devices are assigned in order by type: the DJ11 first, followed by the DH11, and
then the next
device introduced into production. Multiple devices of the same type must be assigned
contiguous
addresses.
The first address of a new type device must start on a modulo 104 boundary.

A gap of 10g, starting on a modulo 104 boundary, must be left between the last address of one
type
device and the first address of the next type device. A gap must be left for any device on
the list that is
not used, if the device following is used.
No new type device can be inserted ahead of a device on the list.

If additional devices on the list are to be added to a system, they must be assigned contiguously

after the

original devices of the same type. Reassignment of other type devices already in the
system may be
required to make room for the additions.

The starting address of the DH11 must be on a modulo 204 boundary because the DH11
utilizes eight

device addresses.

The following examples show typical floating device address assignments for communication

C-1

devices in a system.

Example 1: 2DJ11s, 1 DHI1, and 2 XX11s (future device with 2 registers)
760010

Dill1 #0

first address

;2883

g;ii jg

760016
760020

DJ11 #0
DJ11 #1

last address
first address

760022
760024
760026

DJ11 #1
DJ11 #1
DIJ11 #1

last address

760040

DH11 #0

first address O

760030

DJ11 Gap (indicates that there are no more DJ11s)

760042
760044

DHI11 #0
DHI11 #0

760052
760054

DHI11 #0
DHI11 #0

;288:8
760056
760060

760072

760070

DJ11 requires 4 addresses

DH11 requires 8 addresses

first address
address }
last

.
2 addresses
XX11 requires

ggi} fig
DHI11 #0
DH11 Gap

XX11 #0
0
XX11

last address ./

etc.

Example 2:

1DJ11 and 1 DH11

760010

DJ11 #0

760012
760014

DJ11 #0
DJ11 #0

760016

DJ11 #0

760020

DJ11 Gap

760040

DH11 #0

760042
760044
760046
760050
760052
760054
760056
760060

DH11 #0
DH11 #0
DH11 #0
DHI11 #0
DHI11 #0
DHI11 #0
DH11 #0
DH11 Gap

760030

first address

last address

Cannot be used for DH11. Not a modulo 20g boundary.
first address

last address

etc.

C.3 VECTOR ADDRESSES

The floating vector addresses are assigned starting at 300 and proceed upward. The addresses are assigned to devices
in the following order: DCI11; KL11/DL11-A,B; DP11; DM11-A; DNI11; DM11-BB; DR11-A; DR11-C; PA611
C, D, E; DJ11; DH11.
s;
DX11;DL11che
DT11;
Readers; PA611 Pun
New devices are added as they are introduced into production.
C-2

APPENDIX D

FORMS

D-1

Table D-1

Customer’s Preference Chart
DJ11

Line

Groups
0-3

4-7
8—-11

12-15
0-3

4-7
8—11
12-15

0-3

8-11

_—

—_

e
W

[S—

]

12-15

Levels

Parity

Speed Selection

Stop
Bits

XTR

RCV

Split

Table D-1

Customer’s Preference Chart (Cont)
DJ11

Line

Groups
11
4-7

8—11
12-15

0-3

8-11
12-15

13
4-7

8—11
12-15

0-3
4-7

8-11
12-15
15

0-3
4-7

8-11

12-15

Levels

Parity

Speed Selection

Stop
Bits

XTR

RCV

Split

DJ11 Asynchronous

16-Line Multiplexer

Reader’s COmmentS

Maintenance Manual

EK-DJ11-MM-003

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