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EK-DHV11-TM-002

September 1985

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Document:	DHV11 Technical Manual
Order Number:	EK-DHV11-TM
Revision:	002
Pages:	189
Original Filename:

OCR Text

EK-DHV11-TM-002

DHV11

Technical Manuadl

EK-DHV11-TM-002

DHV11

Technical Manual

Prepared by Educational Services

of
Digital Equipment Corporation

First Edition, September 1983
Second Edition, November 1985

The information in this document is subject to change without
notice. Digital Equipment Corporation assumes no responsibility
for any errors herein.

Notice: This equipment generates, uses, and may emit radio
frequency energy. The equipment has been tested and found to
comply with the limits for a Class A computing device pursuant
to Part 15 of FCC rules, which are designed to provide
reasonable protection against such radio frequency interference
when operated in a commercial environment. Operation of this
equipment in a residential area may cause interference in which
case the user at his own expense may be required to take
measures to correct the interference.

Printed in U.S.A

The following are trademarks of Digital Equipment Corporation.

DEC

PDP

DIBOL
MASSBUS

RSTS
RSX

VT
Work Processor

DECmate
DECUS
DECwriter

P/OS
Professional
Rainbow

UNIBUS
VAX
VMS

INTRODUCTION

Page

SCOPE. .. o
e
OVERVIEW L
e
e
General Description . .........o.iiiiiiiiiii
i
Physical Description . .........cooiiiiiiiiii
it
Versions of DHV
L. ... ... . i,
ConfigUIAtIONS. . ..ottt i
e
e
e
CONNECHIONS ..ottt ittt i
i
e
e
e
SPECIFICATION. ..o
e
e
Environment Conditions. ............coiiiiiiiiiiii i
Electrical Requirements ..............oviiiiiiiiiiiiiiinneennnnnn.
Performance ................ e
et
it
Data Rates. . ...ttt
Throughput. . ... ...
i e
INTERFEACES.
i
i
e it
it c et
System Bus Interface.............c.ccoiiiiiiiiiii
i,
Serial Interfaces . ...t
i
Interface Standards.............
... oo
Serial Data Format. . ............
i i
i
i
Line Receivers. .......coouiiiiiiiiiii
i
Line Transmitters ...........coiiiinneeeiiiineeeinnnnne.
Speed/Distance Considerations ...............covviiinnneen...
FUNCTIONAL DESCRIPTION ...
i
Control Function ........ ... i
i e
Q-BusInterface ...........co i
Serial Interfaces . ........cooiutiiiiii
i
e

1-1
1-1
1-1
1-2
1-4
1-4
1-6
1-6
1-6
1-7
1-7
1-7
1-8
1-8
1-8
1-8
1-8
1-10
1-11
1-11
1-11
1-12
1-12
1-12
1-12

W N

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CHAPTER 1
ek

CONTENTS

[ \S
R wi~

TN P
S S

INSTALLATION
SCOPE. . o
e

2-1

UNPACKING AND INSPECTION ..ottt
iiiie
e 2-1

S otadd

G G NN S N RS AT e

NRRDRONNRNONONRNNORNNNNNNONONON

CHAPTER 2

INSTALLATION CHECKS ..ottt
ettt
Address SWitches. .......oi ittt
e i
e
Vector SWitches .. ....oiiii i
i
e
i
e
Backplane . . . . .
...t
e
e
Connectiontothe Q-Bus...............coiiiiiiiiiii
...
Bus Grant Continuity Jumpers................coiiiiiiiana..
PRIORITY SELECTION . ...t
DMA RequUest .. ..oitiiitii ittt ettt ettt
Interrupt Request . . ...t
i
i et
e
MODULE INSTALLATION. ... ..ot
CABLES AND CONNECTORS ... it
inaannns
Distribution Panel .......... ... .
i
i
Staggered Loopback Test Connector H3277 ........................
Line Loopback Test Connector H325 .................ccovvivinn...
Null Modem Cables ........ooiiuiiiiiei
ittt
eiiiiiinnnnn.
Full Modem Cables. .......ooiiiiiinii
it
ittt
Data Rate to Cable Length Relationships................covvevn..
..
MULTIPLE COMMUNICATIONS OPTIONS ...,
Floating Device Addresses. ...ttt

iii

2-2
2-2
2-3
2-4
2-4
2-5
2-6
2-7
2-7
2-8
2-9
2-9
2-12
2-13
2-13
2-15
2-16
2-16
2-16

90 50 00 00 1

N
W

Floating Vectors. ..........uuiiiiiiiiii
i
INSTALLATION TESTING. ...
i,
Testing in PDP-11 Systems .......... ... ...,
Testing in MicroVAX I Systems......coooviiiiiiiiiiiiinnnnn....
Testing in MicroVAX II Systems .........ccoiiiiiiiiiinnnnnnnn...

Nolo JEN Ne W

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SISESINISESESISESRNE
(=

CHAPTER 3

HwWN

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2-24

PROGRAMMING

SCOPE. . ...
e
REGISTERS ..ttt
et ettt
inans
Register ACCeSS ... .oiii ittt
i
e e
e
Register Bit Definitions. . ...........oiiiiin
it it ciienns,
Control and Status Register (CSR) ..................coiun....
Receive Buffer (RBUF)........ ... ..
Transmit Character Register (TXCHAR) ......................
Line Parameter Register (LPR) ................cccoviiiia.
...
Line Status Register (STAT) .....oiiiiiiiiiiiiiiiiiiinnnn,
Line Control Register (LNCTRL)..........coiiiiiiiiiiannn...
Transmit Buffer Address Register Number 1 (TBUFFADI)......
Transmit Buffer Address Register Number 2 (TBUFFAD?2)......
Transmit DMA Buffer Counter (TBUFFCT)...................
PROGRAMMING FEATURES. ...
iiiiiiieeeee e

3-1
3-1
3-1
3-3
34
3-6
3-8
3-8
3-11
3-12
3-15
3-15
3-16
3-17

i
i
e
e 3-17
Configuration . ........ccouiiiiiiiiiiiii
ittt
e
s 3-17
Transmitting . ...t
i
i
e 3-18-DMA Transfers .........vuuiiiiiiineeeneeeeennnnns 3-18
Single Character Programmed Transfers ....................... 3-18
Methods of Control. . ...... ...ttt 3-19
Receiving. . ...t
i e 3-19
Interrupt Control . ... ... ...
i
i
e 3-19
Auto X-ON and X-OFF .. ... ... . i 3-19
Error Indication ........ et
e
e
et
e 3-21
Modem Control . ...
e 3-21
Maintenance Programming. ............. ..ot 3-22
Diagnostic Codes. ......... o 0322
Self-Test Diagnostic Codes ..........cvviiiiiniiirineennnnnnn 3-22

i, e,

3-26

Single Character Programmed Transfer ........................

3-26

DMA Transfer. . ...
e
Aborting a DMA Transfer ............ .o,
ReECEIVING . . .ottt
i
i i it et et
e e
Auto X-ON and X-OFF ... ... i
Checking Diagnostic Codes . ............oiiiiiiiin i,
Modem Control ........ouuiiiii
et

3-27
3-28
3-28
3-29
3-30
3-31

Transmitting . ..............

3-22
3-23
3-24
3-24
3-24
3-25

Interpretation of Self-Test Codes............cccviviinven....
Skipping Self-Test.............cciiiiiiieiiin...e
Background Monitor Program (BMP)..........................
PROGRAMMING EXAMPLES ... ...
Resetting the DHVI1 ... ... ... ... . i,
Configuration ........c.oiiiiiiiiiiii
ittt
e
i

oL bhWLWWLWWN

2-22
2-23

Initialization ........... ..o

PhrARRARBRRRRLLWL

2-20
2-22

CHAPTER 4
4.1
4.2
4.3
4.3.1
4.3.2,
4.4
44.1
44,2
4421
44.2.2
4423
44.3
444
4.4.5
44.6
4.4.7
4.4.8
4.5
45.1
45.2
4.6
4.6.1
4.6.2
4.6.3
4.6.4
46.4.1
4.6.4.2
46.4.3
4.6.4.4
4.6.5
4.7
4.7.1
47.1.1
4.7.1.2
4.7.1.3
4.7.1.4
4.7.2
4.7.3
4.7.4
4.7.4.1
4.74.2
4.7.5
4.7.6
4.8
. 4.8.1
48.1.1

TECHNICAL DESCRIPTION
SCOPE. ..
i
e
e
e
e
Q-BUSINTERFACE. ... ...
e
SERIAL INTERFACES . ...
i
it
et
ieanean
Modem Control and Status Lines . ...,
EIA/TTL Level Conversion .............coiuuieiinenenennrennannns
CONTROL SECTION. ... ittt
ittt
et teiieee e
General ..ot
e
e e
e e
Common RAM. ... .
i
i et ettt
Memory Map. .. ..ot
i i
e e
T4
]7
PP
FIFO. . o
et
et
e
RAM ACCESS vvvi ittt eiie ittt e te e taseteetaereeenaeenaananans
Store ArbItrator . ... ..o
e
e
MICIOCOMPULETS . . .o et oe e eiee ettt eiieeeneeenaneeenaeannannan
Addressand Data Latches. . ........ciiiiiiinin
i iininannnss
FIFO Addresses .......covvriiirietiie
ittt iaeiaenanans
FIFO Control. . ..oott ittt ittt ettt et et
e e iaanenn
OTHER CIRCUIT
S . .
i
ittt e et et e e e eiaaas
Voltage Converter . .....vvtn
e inereneetnaeneenaenaannnens
L 1o 1 o3 -G
DAT
A FLOW
i e
e ettt ettt
aaas
Host Read froma Register.............
... oo,
Writingtoa Register. ...ttt
Single-Character Transmit.................cciiiiiiiiiiinenenn..
DMA TransmiSsSions . . ....vvvetuieeninneiiinrernnerenneennneenns
DMA Block Transmit ............ e i,
DMA Data Management. .............coiieinrnrennnnnnnnns
DMA Error Detection and Timeout . .................ovion...
DMA AbBOIt. .\ttt
ettt
ettt
Receiving................ e
e e
TECHNICAL DETAIL. ...
ettt
DHVI1 Internal /O Control ........... ...ttt
PROCI1 Memory-Mapped I/O............coiviiiiiinn... ..
PROCI Integral I/O Port Functions...........................
PROC2 Memory-Mapped /O ..........ccoiiiiiiii i,
PROC2 Integral I/O Port Functions...............c.coouin....
Q-Bus Interrupts ........coviniiinii
i
i
Common RAM Arbitration . .......... ... ...ttt
i,
FIFO Counter Control . ...ttt
ittt iiieienanannn
Host Read fromthe FIFO ........ ... ... ... ... .. .o,
PROC2 Writetothe FIFO...............
...
i,
Control/Status Register (CSR) .........coiiiiiiii
i,
Voltage Converter (SMPS) ...
ROM-BASED DIAGNOSTICS ... ... ittt
T
g =11
General. ... ...
e
e e
e

4-1
4-1
4-6
4-6
4-6
4-6
4-6
4-7
4-7
4-8
4-8
4-9
4-10
4-10
4-10
4-11
4-11
4-11
4-11
4-11
4-11
4-12
4-13
4-14
4-15
4-17
4-17
4-17
4-18
4-18
4-20
4-20
420
4-22
4-23
4-25
4-26
4-26
4-30
4-31
4-31
4-31
4-33
4-35
4-35
4-35

4.8.1.2

Location and Interpretation of Diagnostic Codes ................

4-35

4.8.2

Background Monitor Program (BMP) ..............
... ... .. ..., 4-36

MAINTENANCE

TRTYVETEVEVEVEVET XV RV SV RV EVEV TRV EV YV VRV XV VRV RV VTRV RV YV RV VRV RV

1T010
) 2
MAINTENANCE STRATEGY ..... ...ttt
iiiiiienenennnnnnn.
Preventive Maintenance .............cciiiiiiiiii ittt
Corrective Maintenance ...........ccviiiiereernrenneenneennnnnn,

5-1
5-1
5-1
5-1

INTERNAL DIAGNOSTICS . ...t
aene
Y]
=] AP
Background Monitor Program (BMP) .............. ...
XXDP+ DIAGNOSTICS ... i e
CVDHA?, CVDHB?, and CVDHC?........cciiiiiiiiiiineeiinnnn,
Functions of CVDHA? ...... ...ttt
iiiiiiiinnnnn.
Functions of CVDHBY?. ... ...ttt
Functions of CVDHC? ... ... . i,
DECX/11 EXerCiSer. ..o ovittiinteeeeeeeaesaeanannanunnnnenes
DIAGNOSTIC SUPERVISOR SUMMARY............coiviiiiiiot,
Loading the Supervisor Diagnostic.............coiieiiiiiernni.,
Four Steps to Run a Supervisor Diagnostic .........................
Supervisor Commands . .........c.cvvtiiitiiriie
it
e
Command Switches ...........coiiiiiiiiiiiiii i,
Control/Escape Characters Supported. ...........cooiviiiiiiin....
Example Printouts. ..ottt
ittt

5-2
5-2
5-2
5-2
5-2
5-3
5-3
5-3
5-3
5-3
5-4
5-4
5-5
5-6
5-6
5-7

CORRECTIVE MAINTENANCE ON MICROVAX I SYSTEMS ......
The Macroverify Diagnostic..........coiviiiiii
i iiiinnneenn.
Setting Up Procedures. . ..........
it iiinneeeenn.
Bootstrapping Procedure. ...t
Macroverify Operation ................... e
DHV11 Diagnostic EHXDH. ............
. ittt
Setting Up Procedures. ...ttt
Bootstrapping Procedures . ........ ..ottt

5-8
5-8
5-9
5-9
5-9
5-9
5-10
5-10

RUNNING MICROVAX II DIAGNOSTICS ...
Overview of the MicroVAX II Maintenance System.................
Running the Customer Version of the MicroVAX II Diagnostic.......
Running the Maintenance Version of the MicroVAX II Diagnostic....
FIELD REPLACEABLE UNITS (FRUS).......coiviiiiiiiiiiinnnnn..
TROUBLESHOOTING FLOWCHART .........cccoiiiiiiiiiiaaan..

5-18
5-18
5-19
5-19
5-25
5-25

COMPONENT REPLACEMENT ....... . ... i,

5-25

WHR
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CHAPTER 5

APPENDIX A IC DESCRIPTIONS
Al
A2
A2l
A2.2
A23
A3
All
A3.2
A4
A5
A6
A7

A-1

8051 MICROPROCESSOR/MICROCOMPUTER.....................

SCOPE . .

A-1

8051 Block Description. . ....coviii ittt ittt e et
L@feY1111101
14 1o 1 U
Read/Write Timing. .......c.ovtiniiniiii
it iiiiiieranenneeneenns
SC2681 DUAL UART (DUART) . .....ciiiiiiie
i iiiiiieeeennnnnn.
Block Description . .......coiiuiiiii
it
it it
i
Pin-Out Information. ... ......ccoviitiiit
ittt ittt iiineenns
DCOO3 INTERRUPT IC ... ..
i
it
it
c i
e

A-1
A-2
A-4
A-5
A-5

DCO04 PROTOCOL IC . ..

A-13

ittt ittt ettt ittt ite et

A-7
A-9

DCO005 BUS TRANSCEIVER IC ... .ttt
eiecii e A-17
DCO010 DIRECT MEMORY ACCESSLOGIC............ccccvvveenn.. A-21

APPENDIX B

MODEM CONTROL

B.1
B.2
B.2.1

SCOPE ..
e e e
e
MODEM CONTROL ...t
it ittt
Example of Auto-Answer Modem Control for the PSTN.............

B-1
B-1
B-2

APPENDIX C GLOSSARY OF TERMS
Cl1
C.2

SCOPE ...
GLOS
S ARY . .

e e
e
e e

e
e

C-1
C-2

APPENDIX D AUTOMATIC FLOW CONTROL
D.1
D.2
D.3
D.3.1
D.3.2
D.3.3

OVERVIEW .
i
i
e ettt
e
iaaans D-1
CONTROL OF TRANSMITTED DATA ...t D-1
CONTROL OF RECEIVED DATA. ...ttt
ieiiiiieianns D-2
Flow Control by the Level of the Received Character FIFO.......... D-2
Flow Control by Program Initiation ............................... D-3
Mixing the Two Types of Received Data Flow Control .............. D-4

APPENDIX E INSTALLATION GUIDE FOR THE DHV11 REMOTE
DISTRIBUTION PANEL CABINET KIT

E.l1

GENERAL DESCRIPTION. .. ....iiiiiiiittiiiiiiiiieeneaanannnanns

E-1

E.2
E.2.1
E.2.2
E.2.3
E.2.4
E.3
E.4
E.4.1
E4.1.1
E4.1.2
E.4.2

FUNCTIONAL DESCRIPTION. ..ottt
iiiiieene s
H3176 Bulkhead Panel .................
.. ... iiiiiiiiiiiannn...
H3175 Remote Distribution ..............cciiiiiiiiiiiiinnnnn...
BC22H-10 ..t
e e
BOOS
- X X .ot
e
e
INSTALLATION. ...
e
e
e eeas
DIAGNOSTICS . .
e i i e e e
e
MicroPDP-11 Diagnostics .........ouviiiiiininreeriinnaneennnns
CVDHBE Test. . ....oiiiiiiiiiit
ittt
iiiiiinneeannn
LOA"AD)
3 (030 08 1 -1 S
MicroVAX II Diagnostics. .. ....covviritiiiiiiiiiiiiiieneeennn

E-4
E-4
E-4
E-4
E-4
E-4
E-5
E-5
E-5
E-6
E-6

vii

FIGURES

>
3> > >
o b
o A RLLEO
=S

bbb

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[]

]

[}

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N et
e e
LRARWW DN NN

e \D 00 ~1 O\ U B0 N — N — =ORIANNBEBWN=OEWND
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~ Figure No.

Title

Page

M3104 Module. .. ..ottt
it et e e e e e e
Example of DHV11 Configuration .............ccoiiiiiiiiiiiiinnn..
DHVI11 CONNECtioNS . . ...ovttiieee et iiiiienneeeeenneneeennnns
Serial Character Format ....... ... ... .. i,
DHVI11 Functional Block.........
... . i i,

1-3
1-5
1-6
1-10
1-11

Location of Switchpacks. .. ..o it
i i e i
e e
Setting the Device Address ...ttt
ittt
Setting the Vector Address. ...ttt
ittt nrenanns
Bus Grant Continuity ...........coiiniriinriiineenieeenneennnans
DHVII Installation. . ......iiiuntn
ittt it e it et et e it cn e
H3173-A Layout. ....co ittt
ittt et et et iaenaennns

2-2
2-3
2-4
2-6
2-8
2-9

H3173-A Circuit Diagram. ..........ciiiiiin
ittt et iiieiaaannn 2-10
Staggered Loopback Test Connector ...........coiiriiiiieeinnnnnnnnnn. 2-12
Line Loopback Test Connector. . .......vvvvtineiieiniieiiaaennannn 2-13
Null Modem Cable Connections. ............ccovuirinreinrrnrennnnnnn. 2-15Register Coding. ......oiiiiiiiiiniii
ittt ittt teeneenanennonnas 3-3
Diagnostic/Status Byte .........c.iiiiiiiii
i
e 3-22
" DHVI1 Block Diagram. . ..........vviiiniieienirneieenreneneenanenns 4-2
DATI Bus CycCle. ..ot
e
et et
eiii e einar e 4-4
DATO or DATOBBus Cycle. .......ciiiii
ittt it it iiannen 4-4
Interrupt Request/Acknowledge Sequence.............c.civiininnenn.. 4-5
DMA Request/Grant SeqUence. ........ovuuiireerineeienneeennarnansns 4-5
Common RAM -Memory Map .........ccovriiiiiiiiiniiininnnennnnnn. 4-7
Common RAM ACCESS ... .oouiiiiitiiiiiii it 4-9
Reading from a Register ............oiiiiiiiiiiiiin
i iiiiiinnenennnnn. 4-13
Writing to a Register ..... . .
i
it i e i ie e 4-14
Single-Character Transmit ............
... it iiiiiiiiiinininnenen.. 4-15
DMA Data Transfer ........c.oiiiiuinniiineriiiettiieernneeenneennn 4-16
DMA Character Handling ............. .ottt
iieennnnn. 4-17
DMA/Memory Error Generation .............cciiiiiiiniiineennneenn. 4-18
Receivinga Character .......... .ottt ittt
ennns 4-19
PROCI /O Decoding. .. ...ovviniiee
ittt e iiiinee
s 4-21
PROC2 I/O Decoding. . .. .oiviiie it
e e et iie e iieeas 4-24
Interrupt Logic. . ..ottt
i
i i
i e e e
et 4-27
RAM Arbitration and Timing. . .......... ittt
iaeennnnn 4-28
Store Access Timing Cycle. ......... it
i
i i eiiee e 4-29
CSR and Register Address Circuits ............cciiiiiniiiinnnennnn. 4-32
DHVI11 Voltage Converter. .........oouiiiiiiiiiie
e iineraenaaanns 4-34
Register Contents After Self-Test ...........
... ..., 4-35
Troubleshooting Connection Diagram. .............cciiiiiiiinnennan... 5-1

Troubleshooting Flowchart.........
... ... ... ..., 5-26
8051 Block Diagram...........oiiiiiiiiiiiii ittt A-1
8051 Symbol and Pin-Out Diagrams..............ccoviiverineinennn...
Program Memory Read Cycle ....... ... .. . i,
Data Memory Read Cycle........ ...ttt
Data Memory Write Cycle ....... ... it
SC2681 Dual Universal Asynchronous Receiver Transmitter (DUART) ...
SC2681 Pin-Out Diagram ............coiiiiiiiiiniiiieieennnnn,
DCO003 Logic Symbol. . ..ottt
it
e
e

viii

A-2
A-4
A-5
A-5
A-6
A-7
A-9

DCO003 A Section Timing ..........coiiiiiiiiiiiir
i iiiiiiiianeeennans
DCO003 A and B Section Timing ...........
...
iiiiiiiiiinenn...

A-10
A-11

DCO004 Simplified Logic Diagram ....................c.coiiiiiieenn...
DCO004 Timing Diagram ..............oiiiiiiiiiiiie
it iiiaaannnnn.
DCO005 Simplified Logic Diagram ............
... ...,

A-14
A-15
A-19

DCOO0S5 Timing Diagram ..........oiiuniiinreiiieeiieianeeennnns
DCO010 Simplified Logic Diagram .............
.. .00 iiiiiiiinenn.n..

A-20
A-21

DCO010 Logic Symbol/Truth Table .............. ...,
DCO10 Voltage Waveforms. . ........ciiiiiin
it
iiinneeennns
DCO010 Timing Diagram, DMA Request/Grant ....................c.....
DCO10 Timing Diagram ............ciuiiiiiiie
e eineneenans
Transmitted Data Flow Control .......... ... ... ...
it iiiin...
Received Character FIFO-Level Flow Control..........................
Program-Initiated Flow Control ......... ... .. ... ..
i oo,
DHVII Module. ... ...
i
i i i et
i
DHV11 Remote Distribution Panel Cabinet Kit.........................

A-23
A-23
A-24
A-25
D-1
D-3
D-4
E-2
E-3

Title

Page

DHVI1 Data Rates . ......oiiiiiiiii
it ettt et e e eie e
EIA/CCITT Signal Relationships.............ccoiiiiiiiiiiiiiiiiin,
DHVI11 Bus ConnectionsS. . ..o vvitnt
e
s e aeiaeneienaaenannnns

1-7
1-9
2-5

PROC?2 Integral I/O Port Functions...............ccoiiiiiiiiiinnn.
8051 Pin Description .. ... ...ttt
ettt
SC2681 Pin Designation ...........uuuiirntineeneeenanernrciannneens
DCO03 Signals. .. ..ooi ittt
e
et
et
e
DCO004 Pin/Signal Descriptions . ...........ciiiririiiiiiiieiinneennns.
DCO05 Pin/Signal Descriptions ...........cuuitttnnernrenraneeennnns
DCO010 Pin/Signal Descriptions . .........cuuiieerinerrnneeennneennnnnn
Modem Control Leads. ...ttt
it iiiieeiiannan
Cabinet Kit Details . ........ it
i
i it i e

4-25
A-3
A-8
A-12
A-16
A-17
A-21
B-2
E-1

—

O w

=Gy dn = BLWN M

Table No.

@@
IRIRIR
> 222> > PP PP WN
=L RGN =N =

TABLES

H3173-A CONnections . .....vurttnte
et e eie e eareineninnnenns
Data-Rate/Cable-Length Relationships . ............
... ..ot
Floating Device Address Assignments. .............coiiiviiiiinennnnnn,
Floating Vector Address Assignments.............ocoviiniiiniiniennn,s
DHV
I Registers ..ottt i it ittt
etan et
eannns
Data Rates . ... oottt
e
i
DHVI11 Self-Test Error Codes. . ... ..oiiuiiii ittt eiiiianeans
PROC1 Memory-Mapped I/O. . ..ot
PROCI Integral I/O Port Functions. ............c.ciiiiiiiiiiiiniennnn.
PROC2 Memory-Mapped I/O .. ... ... i i

2-11
2-16
2-17
2-20
3-2
3-10
3-23
4-20
4-22
4-23

PREFACE

This document describes the installation requirements and servicing procedures for the DHVI11
asynchronous multiplexer. It contains information for first-line service, field service support, and for
customer engineers. A substantial programming chapter is included. Appendix C contains a glossary of
terms used in this manual.
The manual is organized into five chapters plus appendices.

Chapter 1
Chapter 2
Chapter 3

—
—
—

Introduction
Installation
Programming

Chapter 5
Appendix A
Appendix B
Appendix C

Maintenance
Integrated Circuit Descriptions
Modem Control
Glossary of Terms

Appendix

Automatic Flow Control

Appendix E

Installation Guide for the DHV11 Remote Distribution Panel Cabinet Kit

Chapter 4

—~

Technical Description

The following is a list of related titles and document numbers.

Document

Number

LSI-11 Microcomputer Interfaces Handbook
LSI-11 Systems Service Manual
Communications Mini-Reference Guide
Terminals and Communications Handbook
Microcomputers and Memories
DHV11 Print Set
DHV11 Maintenance Card

EB-20175-20
EK-LSIFS-SV
EK-CMINI-RM
EB-20752-20
EB-20912-20
MP01793
EK-DHV11-MC

ORDERING THIS MANUAL
DIGITAL Personnel Ordering
Additional copies of this document and printed copies of the documents listed may be obtained from:

Digital Equipment Corporation
444 Whitney Street
Northboro, Massachusetts 01532
ATTN: Printing and Circulation Services (NR2/M15)
Customer Services Section
Customer Ordering Information
Purchase orders for supplies and accessories should be sent to:
Digital Equipment Corporation
Accessories and Supplies Group
Cotton Road
Nashua, New Hampshire 03060

Contact your local sales office or call DIGITAL Direct Catalog Sales toll-free 800-258-1710 from 8.30
a.m. to 5.00 p.m. eastern standard time (US customers only). New Hampshire, Alaska, and Hawaii
customers should dial (603)-884-6660. Terms and conditions include net 30 days and F.O.B. DIGITAL
factory. Freight charges will be prepaid by DIGITAL and added to the invoice. Minimum order is

$35,00. Minimum does not apply when full payment is sent in with an order. Checks and money orders
should be made out to Digital Equipment Corporation.
European Customers
European customers should order the manual from their local Accessories and Supplies Group (A and

SG).

xii

CHAPTER 1
INTRODUCTION

1.1

SCOPE

Chapter 1 provides general information and specifications. It describes how the module can be configured,
and how it interfaces with the system bus and the serial data lines. Physical and functional descriptions are
'

also included.
1.2

OVERVIEW

The DHV11 is an LSI-11/Q-bus option. All future references to the bus will be by the global term Q-bus.
The specific terms Q16, Q18, or Q22 will be used where needed to identify versions with 16-,18-,0r22bit addresses.

1.2.1 - General Description

The DHV11 option is an asynchronous multiplexer which provides eight full-duplex asynchronous serial
data channels on Q-bus systems. The option can be used in many applications. These include data
concentration, terminal interfacing, and cluster controlling.
The main features of the DHV11 are as follows:

Eight full-duplex asyrichronous data channels

Direct Memory Access (DMA) or single-character programmed transfers on transmit

Large 256-entry First-In-First-Out (FIFO) buffer for received characters, dataset status

RS-423-A/V.10/X.26 and RS-232-C/V.28 compatible

Full-duplex point-to-point-or auto-answer dial-up operation

Programmable split speed per line

Total module throughput of 15000 characters per second

Ql6, Q18, and Q22 bus compatible

Automatic flow control of transmitted and received data

Self-test and background monitor diagnostics

Programmable test facilities

Single quad-height module (M3104)

Allfunctions are programmable, except for device address and vector selection which are done

changes, and diagnostic information

by hardware switches on the module.

1-1

Enough modem controlis provided on all eight channels to allow auto-answer dial-up operation over the
Public Switched Telephone Network (PSTN). Suitable modems to use this facility are the Bell models
103,113,212, orequivalent. The DHV11 can also be used for point-to-point operation over prlvate lines.
Modem controlis'implemented by softwarein the host.

The module provides DMA or single-character transfers from the host system to the serial lines. A 256-

character

FIFO buffer is provided for data received from the serial lines.

By using microcombfiters (referred to as PROC 1 and PROC 2 in this manual), the DHV11 releases the

host system from many of the data handling tasks.

One 8051 microcomputer controls DMA and single-character transmissions from the host system to the DHYV11. A second 8051 controls four SC2681 Dual Universal Asynchronous Receiver Transmitters

(DUARTs) which carry out the serial/parallel and parallel/serial conversion of data.
The DHV11 carriesROM-based diagnostics which are executed independently of the host. A full range of

dlagnostlc programs is also available.
A green LED gives the GO/NO-GO status of the module. More detailed diagnostic information is also
made available to the host system via the FIFO buffer. Loopback test connectors are available for use with
the system-based diagnostics.

I/O addresses and interrupt vectors for the module are selected on two Dual-In-Line (DIL) switchpacks.
All other DHV11 functions and configurations are programmable.
«
To prevent data loss at high throughput levels, the DHV11 can be programmed for automatic X-ON and
X-OFF operation.
1.2.2
Physical Description
‘
The option is based on a standard quad-height module (M3104). The layout of this module is shown in
Figure 1-1. The dimensions are 21.6 cm x 26.5 cm (8.51 inches x 10.44 inches).
The module is connected to the Q-bus via connectors A and B. J1 and J2 are connected to the
communications lines via BCOSL-xx cables and H3173-A distribution panels.

On some backplanes jumpers W1 (BIAK) and W2 (BDMG) extend the bus grant signals to the next
module slot via connectors C and D.
DIL switchpacks E58 and E43 select the device address and vector address of the module.

LOW CHANNELS {0-3)

DUART SC2681
(CHANNELS 6/7)

DUART SC2681
(CHANNELS 0/1)

PROC 2

24MHz

0sc

8051

( BERG CONNECTOR j

\Onr:

BERG CONNECTOR

DUART SC2681
© (CHANNELS 2/3)

HIGH CHANNELS {(4-7)

' DIAGNOSTIC LED

3.6864

DUART SC2681
(CHANNELS 4/5)

PROC 1

8051

MHz 0SC

ADDRESS ADDRESS AND
VECTOR SELECT
SELECT

“

E58

€43

/a3
W2

BACKPLANE CONNECTORS
W1 ~ INTERRUPT ACK GRANT
W2 - DMA GRANT

)

Figure 1-1

IN FOR H9270 AND H9275 BACKPLANES

OUT FOR H9273 AND H9276 BACKPLANES
RD1141

M3104 Module

1-3

1.2.3 Versions of DHV11
To facilitate installation in different system packages, and to allow installation in
non-specified cabinets,
the DHV11 module (DHV11-M) can be supplied with one of three cabinet kits. Except for
the length of
the flat ribbon cables, the cabinet kits are the same.
DHV11-M is made up of the following;
e
e
e

The module
This technical manual
Packaging.

M3104
EK-DHV11-TM

The three cabinet kits are:
e
e
o

CK-DHVI11-AA (21-inch cables); example of use, PDP-11/23S
CK-DHV11-AB (12-inch cables); example of use, Micro/PDP-11
CK-DHV11-AC (30-inch cables); example of use, PDP-11/23 PLUS

Each kit is made up of:

Two BCOSL-xx cables (see NOTES)
H325 line loopback connector
H3277 staggered loopback connector
Two H3173-A distribution panels (see NOTES)
Mounting bolts and washers for H3173-A.
Adapter plate (contained in CK-DHV1 1-AC)
NOTES
The H3173-A distribution panels provide noise
filtering and static discharge protection on the
communications lines.

BCOSL-xx cables are supplied in different lengths
for each kit. The kits are specified in Section 2.2.
DIGITAL does not supply a cabinet kit for
installing the DHV11 in non-FCC-compliant
cabinets.
The hardware is connected as in Section 1.2.5.

1.2.4
Configurations
Figure 1-2 shows some possible DHVI11 configurations. The position of the module
on the bus
(backplane) determines its DMA and interrupt priorities. A guide to positionin
g is given in Section 2.4,
Any or all of the data channels can be connected to a terminal or to a data communicat
ions line.

}

SYSTEM BUS (Q22 OR LSI11)

PROCESSOR
HOST

LOCAL

— e e | |——— —

EQUIPMENT

REMOTE
EQUIPMENT

——

DEVICE

{}

M3104 MODULE

TELEPHONE OR
\

‘

DATA COMMS

| 8 DATA CHANNELS

‘

|_DHV11 OPTION

——————

LINE

» MODEM

TELEPHONE OR

DATA COMMS

LINE
|
—
I

MODEM

[«—= REVIOTE
|

Q22 OR LSI11 BUS

REMOTE

PROCESSOR

RD1142

Figure 1-2

Example of DHV11 Configuration

1-5

1.2.5
Connections
Figure 1-3 shows the connections for the DHV11. These include normal operating connections and test

connections. More detail is shown in Figure 2-3 in Section 2.

40 PIN BERG
CONNECTORS

CHANNELS

0-3

7
=

[ve]

N
g

STAGGERED

H3173-A

LOOPBACK

DISTRIBUTION

TEST

CONNECTOR

Y
Q

PANEL

25 PIN D TYPE
CONNECTORS

g
o8]

BCO5L-xx
CHANNELS

CABLE

4-7

= = NORMAL CONNECTION

H325

= = TEST CONNECTION

LINE

LOOPBACK TEST
CONNECTOR

NOTE:

BCO5L:01 = 30.48 CM (12 INCHES)
BCO5L-1K=53.34 CM (21 INCHES)
BCOS5L-2F = 76.2 CM (30 INCHES)

RD1143

Figure 1-3

1.3

DHVI11 Connections

SPECIFICATION

1.3.1

Environment Conditions
o
o
o

Storage temperature: 0°C to 66°C (32°F to 151°F)
Operating temperature: 5°C to 60°C (41°F to 140°F)
Relative humidity: 10% to 95% non-condensing

1-6

Electrical Requirements

1.3.2

+5 V dc + or — 5% at 4.25 A (typical)
+12 V dc + or — 20% at 520 mA (typical)

Negative 12 V dc is generated by a Switched Mode Power Supply (SMPS) circuit on the DHV11. It has
the following specification:

_11.85 V dc + or — 7.25% at 400 mA (maximum)
Output ripple is 200 mV peak to peak at 36.7 kHz

Loads applied to the Q-bus are as follows:
Q-bus ac loads
Q-bus dc loads
1.3.3

2.9 ac loads
1.0dc loads

Performance

r of speeds. If
can be programmed to operate at one of1-1a numbe
1.3.3.1 Data Rates — Each channelrates
can be different (split speed). Table shows the data rates

needed, the transmission and reception
which are possible. The maximum rate per channel is 38400 bits per second (bits/s).
els are
four DUART ICs (Integrated Circuits).all Chann
The eight serial channels are implemented with
se of the method of data rate generation, transmit and

Becau
paired as follows: 0/1, 2/3, 4/5, 6/7.
l-pair must be in the same group (A or B).
receive rates for a DUART channe

Table 1-1

DHVI11 Data Rates
Groups

Speed (Bits/s)

B.
Aand B
A and B

75
110
134.5

150
300
600
1200

B
Aand B
A and B
Aand B

1800
2000
2400
4800

B
B
A and B
A and B

7200

Aand B
B
A

9600
19200
38400

Data rate selection is covered in Chapter 3 (Programming).

1-7

1.3.3.2 Throughput — Each channel is capable of full-duplex operation at data rates of up to 38400
bits/s. The DHV11, however, cannot handle eight channels operating at this rate at the same time. Total

maximum throughput is also dependent on the application and configuration.

Maximum throughput:

Per channel (send)

1000 characters per second in single-character transfer mode

2000 characters per second in DMA mode
(receive)

On any channel, the DHV11

_per second at the same time.

Total (8 channels)

4000 characters per second.

can send at one of the above transmit rates and receive at 4000 characters
15000 characters per second

NOTES
The DMA firmware cannot handle transmit data

faster than 2000 characters per second (19200
bits/s). If the transmit data rate is increased to
38400 bits/s, the duration of each character will

be halved but there will be gaps in transmission.

1.4

15000 characters per second is the sum of both
transmitted and received characters on all
channels. This throughput could support all
channels transmitting or receiving at 19200 bits/s,
or all channels transmitting and receiving at 9600
bits/s. The above figures are based on a 7-bit
character with start bit, parity bit, and one stop
bit.

INTERFACES

1.4.1
System Bus Interface
The M3104 module will connect directly to the Q-bus via connectors A and B. To make the module
compatible with backplanes which have Q-bus on C and D also, two jumpers (W1 and W2) are provided.
The use of these jumpers is described in Section 2.3. Backplane signals, together with pin details, are listed
in Table 2-3.
.
1.4.2

Serial Interfaces

1.4.2.1
Interface Standards — The DHV11 provides interface signals which conform to a subset of
the EIA/CCITT standard RS-232-C/V.24. The electrical characteristics conform to EIA/CCITT
standards RS-232-C/V.24 and RS-423-A/V
.28 (unbalanced interface). The interface is compatible with
X.26/V.10 standards but does not comply with the slew rate requirements.
Connections to the external equipment are via 25-pin male subminiature D-type connectors, as specified
for RS-232-C.

By means of suitable cables and connectors (not supplied or supported by DIGITAL) the channels can be

made compatible with the following:

1.
2.

Subset of EIA interchange standard RS-449
EIA electrical standard RS-422 (balanced).
NOTE

Even when RS-422 is implemented; RS-423-A
cable length/data rate recommendations should
be followed.

The distribution panel does not support split
grounds.

Table 1-2 shows RS-232-C/V.24/RS-449 signal relationships, and pin connections for the male
subminiature D-type connectors.

Table 1-2

EIA/CCITT Signal Relationships

D-Type RS-232-C

Signal

Name

Circuit

CCITT V.24

RS-449

(GND)

(SIG GND)

102

Transmitted Data

(TXD)

103

Received Data

(RXD)

104

Request to Send

(RTS)

CA\§

105

Clear to Send

(CTS)

106

Data Set Ready

(DSR)

107

Data Terminal Ready

(DTR)

108/2

(RI)

125

(DCD)

109

Protective Ground

Signal Ground

Ring Indicator

Data Carrier Detect

NOTE
The backward channels listed below are not

supported. However, by using another channel
for this function, and by connecting a suitable
cable (H1200 or H1201 for example), backward
channel operation is possible.

1-9

Circuit No.

118
120
119
121
122

Function

Transmitted backward channel data
‘Transmit backward channel line signal

Received backward channel data
Backward channel ready
Backward channel received line signal detector

1.4.2.2 Serial Data Format — Serial characters are made up of a coded sequence of bits which are
enclosed between a start and a stop signal. The start signal is always 1 bit long but the stop signal is
programmabile to 1, 1.5, or 2 bits. The duration of a bit is dependent on the selected data rate.

Character codes may be 5, 6, 7, or 8 bits long, optionally followed by a parity bit. Parity can be

programmed as even, odd, or no parity.

‘

'On serial data channels controlled viathe DHV11, the data line is held marking when inactive. Transfer of
~ each character begins with a start bit (space) and ends with one or more stop bits (mark).
Figure 1-4 shows the reception of an 8-bit character with parity. The Least-Significant Bit (LSB) of the
character code is transmitted first. If another character is not ready for transmission, the line will stay
marking. The figure shows 1, 1.5, and 2 stop bits.

NOTE

This description applies to signals at the DUART
pins. Signals measured on the interchange circuits
will have the opposite polarity to those shown.

The data rate clock which times the serial data, is 16 times the programmed data rate. Arrows show when
the bits are tested for polarity.

8 DATA BITS

MARK + )

SPACE —

START BIT

MSB LAST PARITY BIT STO

LSB FIRST

P BITS S

RD1144

Figure 1-4

Segrial Character Format

The DHV11 allows the following serial character formats:

Characters of 5, 6, 7, or 8 bits with or without parity and with 1 stop bit
Characters of 6, 7, or 8 bits with or without parity and with 2 stop bits
Characters of 5 bits with or without parity and with 1.5 stop bits.

1-10

1.4.2.3 Line Receivers — The serial line receivers used in this module are 9637AC or equivalent.
They convert the EIA input signals to TTL levels suitable for the DUARTS.
Signals are inverted by the receivers.

1.4.2.4 Line Transmitters — The serial line transmitters used in this module are 9636AC or
equivalent. They convert TTL level signals from the DUARTS to EIA levels on the data lines.
Signals are inverted by the transmitters.

1.4.2.5 Speed/Distance Considerations — The maximum data rate which can be used on a line
L=

depends upon a number of factors. These are:

The characteristics of the line transmitters and receivers
The characteristics of the serial cable (or link)
The length of the cable

Noise (interference) which affects the line.

A ‘speed against distance’ table for typical conditions is provided in Section 2.6.6.

PROC 1
DMA AND
INTERRUPT

) {'42 Eo'flnj

DMA ADDRESSES AND DATA

;

SYSTEM BUS (Q22 OR LSH 1)

DMA
INTERRUPT
)
AND
PROTOCOL
LOGIC

REGISTERS

DATA AND CONFIG

AND

BUS

DRIVERS
AND
RECEIVERS
ADDR

AND DATA
/0

ADDRESS

RECOG—
NITION

BUFFERS

REAID ADDRESS ENABL

FIFO

CONTROL

FIFO

LINE

INTERFACE

FIFO

| (256 CHARS)

|AD

p———
wd
<L

[

PROC 2

DUART CONTROL

WRITE ADDRESS|

ENABLE

I3k

(4K ROM

PARALLEL

yv—

DMA REQUEST

8 DUPLEX CHANNELS

INTERFACE

Q22/LS111 BUS

HFPHANLLY

SERIAL INTERFACES
CONTROL SECTION

RD 761

Figure 1-5

DHV11 Functional Block

1-11

1.5

FUNCTIONAL DESCRIPTION

1.5.1
Control Function
In the DHV11 ‘module (Figure 1-5), data is transferred by three methods:

By DMA. Blocks of data are transferred from system memory to the serial interface. DMA data
is routed via the bus receivers, PROCI1, the RAM, and PROC?2.
,

Inthe non-DMA mode, single characters can be transferred from the host system to the serial
interface. The route for single charactersis via the bus receivers, the RAM, PROCl the RAM,
and PROC?2.

Single characters can be transferred from the serial interface to the host system. The route for
received characters is via PROC2, the FIFO buffer, and the bus drivers.

At the center of the control section is a 1 K-word RAM. By writing control words to registers in the RAM,
the host can indirectly configure and command the module. The host can also write data bytes to registers
in the RAM.
Two microcomputers (PROC 1 and PROC 2), which contain their own programs in internal ROM, scan
the RAM in order to detect a new configuration, or data to be transferred. They also write status
information to the RAM, which can then be read by the host.
PROC 2 configures the DUARTS as instructed, and transfers transmit and receive data between the
RAM and the DUARTS. Received characters are written to FIFO addresses provided by FIFO control.
Among other functions, PROC 1 controls DMA actions. Using DMA information provided by the host, it
starts DMA circuits which control each DMA transfer. PROC 1 keeps track of DMA addresses and
character count, and reports to the host when the block has been transferred.
Both microcomputers execute background diagnostics when not busy with other tasks.

1.5.2
Q-Bus Interface
v
The DHV11 module is considered by the host system as a number of I/O ports. The bus drivers and
receivers recognize DHV11 addresses and allow the host to access the

FIFO buffer and the registers.
When the FIFO buffer is being read, FIFO control provides the read addresses.

Standard DIGITAL LSI protocol, interrupt, and DMA integrated circuits (ICs) control the interface.

Module address switches are connected to comparators in the bus driver/receiver ICs. When an I/O

address from the host is the same as the address on the switches, the DHV11 responds to the host. On’
receiving the response, the host proceeds with the transaction.
Vector address switches are also connected to the bus drivers. These allow the DHV11 to supply two
interrupt vectors (transmit and receive) to the host during an interrupt acknowledge sequence.

1.5.3

Serial Interfaces

Eight full-duplex serial interfaces are provided by four DUARTS. These ICs, controlled by PROC 2, are
configured as needed by the host system. They carry out the serial/parallel and parallel/serial conversion.
When a received character is assembled PROC 2 is interrupted.
The status of modem control lines for each channel is polled by PROC 2. If programmed to do so, the
DHV11 will report changes of modem status to the host. Such reports are made via the FIFO buffer and
the device registers.

1-12

CHAPTER 2
INSTALLATION

2.1

SCOPE

This chapter contains information on how to prepare and install the DHV11 option. It contains sections

on the following:

Device and vector address selection
Rules for backplane positioning
Recommended cables
Test connectors
Floating address and vector assignment
Testing after installation.

2.2

UNPACKING AND INSPECTION

There are a number of versions of the DHV11, all of which are based on the module kit DHV11-M. This
may be ordered with one of the three cabinet kits listed below. Examine all parts for physical damage.
Report damaged or missing items to the shipper and the DIGITAL representative.
DHV11-M

M3104 + EK-DHV11-TM .
(field upgrade base option)

DHV11-AP

System integrated DHV11
(DHV1 I-M + appropriate cabinet kit)

Field Upgrade Cabinet Kits

Single line loopback

H3277
H3173A
BCO5L-1K
BCO05L-01

Staggered loopback
4-line 25-way distribution panel
40-way ribbon cable, 21 inch
40-way ribbon cable, 12 inch

90-06021-01
90-06633-00

Boit
Washer

BCO5L-2F
74-28684-01

40-way ribbon cable, 30 inch
Adapter plate

2-1

1|11

11111
2
12
2
2
2
o0 00

H325

co 00

Contents

PDP-11/23S systems
MicroPDP-11 and MicroVAX systems
PDP-11/23+ systems

CK-DHVI11-AA
CK-DHVI11-AB
CK-DHVI11-AC

2.3

2.3.1

INSTALLATION CHECKS

Address Switches

The device address for the DHV11 is set on switchpacks ES8 and E43. The location of these switchpacks
is shown in Figure 2-1. Figure 2-2 shows the method of setting the device address on the switchpacks. The
example shown is for a Q22-bus address of 17760440g.

From the information contained in Figure 2-2 it can be seen that switches 5 and 8 on switchpack E58 must
be set to ON for the example shown.

—%
[

] 1

5
|

]

]y —1

JUMPERS W1 AND W2 ARE REMOVED FOR TYPE H9276

AND H9273 BACKPLANES AND INSTALLED FOR TYPE
H8275 AND H9270 BACKPLANES

ES8[

[

]E43

e
RD2342

Figure 2-1

Location of Switchpacks

Use the following method to set the device address.

Define the octal address. This may or may not be the factory default, and will depend upon what
other devices are contained within this system configuration. Refer to Table 2-4 for information
on floating device address assignments.

2.
3.

Convertthe octal address to a binary bit pattern. You can write this pattern on Figure 2-2, in the

blank character line left for this purpose.

Relate the binary address to the switches on the switchpacks, and set switches to ON where
they relate to binary 1.

SWITCHPACK E43

SWITCHPACK E58

0}
D = SWITCH OFF {binary

EXAMPLE

SETTING
= 17760440

I = SWITCH ON (binary 1)
'
INTERPRETED

BIT No.

DEVICE

ADDRESS

A///

///////////// ///

11|

214204194184 17 [ 16 |15 [ 14 {13 | 12|

) 1990470549774

—_—\

1
!

1
: :

QBUSONLY ASALLONES
NOT ON UNIBUS

SEE NOTE /A/

—

1
"

ROW TO
USE THE BLANKADDRESS
PENCIL-IN THE
PATTERN YOU NEED

o|=6

1i=7

Vector Switches

1
!

1
:

'
|

1
:

|
|

DECODED
BY DEVICE

10| 09| 08| 07| 06| 05| 04| 03 02} 01{ 00

J
N\

I\
I

—

’

\\|/
me—

ololo]=0

8 ? 3, _ ;

ol1]111=3

1{ojo|=a

1{ol|1]=5

111]l0]|=6
11
]1]=7

Figure 2-2
2.3.2

0
I

.
:

,
1
.
EACH GROUP IDENTICAL

|
|

NOTE:

Setting the Device Address

t vector to the host. The six
During an interrupt acknowledge sequence, the DHYV11 returns a 7-bit interrup
of switchpack E43. The
high-order bits of this vector are derived from the settings of the last six switches
of these switches set to
example
location of this switchpack is shown in Figure 2-1. Figure 2-3 provides an
4 and 5 must be set to
switches
an address of 300g. From the information in Figure 2-3 it can be seen that
ON for the example shown.

You can use the following method to set up the vector address.

Define the octal address. This may or may not be the factory default. Refer to Table 2-5 for

Convert the octal address to a binary bit pattern. You can write this pattern on Flgure 2-3inthe
blank line left for thls purpose.

information on floating vector address assignments.

3.
-

Relate the binary address to the switches on the switchpack, and set switches to ON where they
relate to binary 1.

PART OF

LEGEND

SWITCHPACK E43

D = SWITCH OFF (binary 0)
EXAMPLE

. = SWITCH ON (binary 1)
.

iES.Ig(I)NG
T

[

INTERPRETED

- |

AS ALL ZEROES

)

DECODED
BY DEVICE

SEE NOTE
BIT No.

15|14
—

VECTOR

ADDRESS:

}13

|12

111]10|09]08|07|06]05]04]|03]02]01]|00
)L

{

—

’

)

BOTH GROUPS IDENTICAL

/'
\N/

—

NOTE:
USE THE BLANK ROW TO
PENCIL-IN THE ADDRESS
PATTERN YOU NEED

_ON SWITCHPACK E43
SWITCH 2 IS NOT USED

o]
o]
0
0
1
1
1
1

O
o
1
1
0
0
1
1

o|=0
11=1
0|=2
11=3
0
|=4
1]1=5
0
|=6
11=7

RD2255

Figure 2-3

2.3.3

Setting the Vector Address

Backplane

2.3.3.1 Connection to the Q Bus-The DHV11 interfaces with the system via the Q-bus. The physical
connection is made via the A, B, C, and D edge connectors on the module.

Bus signals, their categories, functions, and pin designation are listed in Table 2-1.

Table 2-1

DHYV11 Bus Connections

Category

Signal

Function

Pin Number

Data/Address

BDALO.L - 1.L

Data/Address Lines

AU2 - AV2

BDALI1.L - 15.L

BDALI16.L - 17.L
BDALI18.L - 21.L

Data Control

BE2 - BV2

ACl1 - AD1
BC1 - BF1

BDOUT.L

Data Output Strobe

AE2

BDIN.L

Data Input Strobe

AH2

BWTBT.L
BBS7.L

Write Byte Control
I/O Page Select

AK2
AP2

Interrupt Control

BIRQ.L
BIAKIL
BIAKO.L

Int. Req. Level 4
Int. Ack. Input
Int. Ack. Output

AL2
AM2
AN2

DMA Control

BDMR.L
BDMGI.L
BDMGO.L
BSACK.L

DMA Request
DMA Grant Input
DMA Grant Output
Bus Grant Acknowledge

AN1
AR2
AS2
BNI1

System Control

BINIT.L

Initialization Strobe

AT2

Power Supplies

+5V

DC Volts

AA2 - DA2

Grounds

GND

Ground Connections

AC2 -DC2

BRPLY.L

BSYNC.L

+12V

GND
GND
GND

Reply Handshake

Synchronize Strobe

DC Volts

Ground Connections
Ground Connections
Ground Connections

AF2
AJ2

BD2

ATl - DT1
AJl - BJ1
AM1 - BM1

2.3.3.2 Bus Grant Continuity Jumpers — Backplanes suitable for DHV11 fall into two groups:
Q/CD -

Q-bus on A and B connectors, user-defined signals on C and D
Q-bus on A and B, and C and D connectors.

In Q/CD backplanes, bus grant signals pass through each installed module via the A and B connectors of
each bus slot.

Q/Q backplanes are designed so that two dual-height options can be installed in a quad-height bus slot.

The Q-bus lines are routed as follows:
AB,
CD,
CD,
AB,

first slot
first slot
second slot
second slot

and so on.

' ’Li\’\nes AM2, AN2, CM2, and CN2 (BIAK) and AR2, AS2, CR2, and CS2 (BDMG) carry the bus grant
signals. Figure 2-4 uses BIAK as an example of bus grant routing. The same method is used for continuity
’

of BDMG.

Q/CD BACKPLANE

Q/Q BACKPLANE

—_——————

DUAL
MODULE

|
l

]

- ———n

W1 EXTENDS

BIAK

CN2

CNzT_—'—-

oo | | mressuer

AN2

BIAK

:
"TM

cm2

[

M
|

INTERRUPT : # |I | |conTroL
inTermuPT : Y

AMz
buaL

BIAK

AB | | conTroL

l‘/SHORT-CIRCUIT
| IF INSTALLED

——_—

CONTROL

CN2

)

L _Mobute |
sLoT

amz
QUAD

| =0

| _Mooue _|

AM2

e
|
T_l'_

|
|

AN2
|
T_-_'_

INTERRUPT| || Y | |controL
INTERRUPT| || Y
I |conTroL
!

:
|

AM2
DUAL

|
|

L _Mooute |

sLoT

cM2

SLOT

AM2
QUAD

|
|

L _MODULE _|

o
AM2

sLoT

e————— B AC KPLAN
E

——— MODULE WIRING
RD153%

Figure 2-4

Bus Grant Continuity

Each dual-height module will extend the continuity of bus grant signals BIAK and BDMG to the next

module.

If a quad-height option is installed, jumpers perform the grant continuity function of a dual option installed
on C and D.
'
Therefore, with a Q/Q backplane, W1 and W2 should be installed. H9275 and H9270 are examples of
'

this type of backplane.

In a Q/CD backplane, pins CM2, CN2, CR2, and CS2 are available for user-defined signals. Therefore
W1 and W2 must be removed. H9276 and H9273 are examples of this type of backplane.
24

PRIORITY SELECTION

The DHV11 uses the BIRQ4 line to request interrupt service. It does not monitor any of the higher-level
interrupt request lines. Because of this, both the interrupt request and DMA (non-processor request)
priorities of the DHV11, are selected by the position of the DHV11 on the bus.
The bus (backplane) position may be a compromise between DMA and interrupt priority requirements.
As a general rule, DMA request priorities should be considered first, and then interrupt (bus) requests.

2-6

)

2 4.1

DMA Request

DMA request priority is usually selected on a basis of throughput. The faster devices (higher throughput)
will usually have priority over slower DMA devices; for example, disk, tape, and then communications
devices. Thisis because a fast device will usually reach an overrun/underrun condition sooner than a
slower device.

The simple approach can be further complicated by hardware bufferingin the device. For example, a disk
controller may read a full sector of information into a hardware buffer. It may then raise a DM
A request to
_ move the data to system memory. If the request is not serviced immediately, thereis no danger of data loss.
However, a magnetic tape unit or a communications device without buffering may need to be serviced
quickly. In this case the slower unit might be serviced first. This method of priority selection could, of
course, reduce disk throughput.

The system designer should consider the following four factors in determining DMA priorities:
Device average service time

Maximum wait time to be allowed (before loss of data)
Average time between DMA requests
Slack time.

Using the above parameters, the system designer should assume that all DMA requests are made at the
same time. He should then check that his selected priority sequence does not violate the parameters of any

DMA device.

If there is only one DMA device in the system there is no DMA contention. The device’s position on the

bus will be determined by its interrupt (BIRQ) priority.
NOTE

If the system memory needs refresh cycles via the

- bus, these should be considered as DMA requests.
2.4.2

Interrupt Request

Interrupt requests have four levels of priority. The lowestis Level 4 and the highestis Level 7. Requestsare made on bus interrupt request lines BIRQ4 to BIRQ7 To avoid: contentlon, lower-prlorlty devices

usually monitor the higher request lines.

Within any priority group, priority is decided by backplane position. The most time-critical interrupts
must be nearer the CPU.

There are two common types of configuration for devices which need interrupt service:
1.
2.

The position-independent configuration
The position-dependent configuration.

In the position-independent configuration, devices of different priority groups can be placed anywhere in

the backplane.

In the position-dependent configuration, devices of different priority groups are positioned in descending
order of priority from the CPU.

Because the DHV11 is a Level 4 device which does not monitor higher request lines, it must be positioned
after all devices that do. Therefore DHV11 priority is position dependent in either configuration.

2-7

By assuming that all interrupts are raised at the same time, the system designer can check his priority
sequence as for DMA requests.
2.5

MODULE INSTALLATION

Once the backplane position of the DHV11 has been defined, the module can be installed and the

backplane checked with a testmeter.

CAUTION

Switch off power before inserting or removing

CE
A

PIN A

40 PIN BERG

DF
B

modules. Be careful not to snag module components
on the card guides or adjacent modules.

CONNECTORS

CHANNELS

— —

8
@

—

TM~

H3277

RED LINE \"‘]l

NN RepLine
M) oA

STAGGERED
LOOPBACK

TEST

CONNECTOR

%
3]

~
//
\\ -

\\\ -

\§\<\

= = NORMAL CONNECTION

ON PCB

R
N

A, PRINTED

TOA

H3173-A
DISTRIBUTION

-3

[J2

PANEL

7178

/ fl/
/

25 PIN D TYPE

CONNECTORS

_ 7 RED LINE
TO A

=
SSo—=

= = TEST CONNECTION

SH7ANNELS
H325
LINE

LOOPBACK TEST
CONNECTOR

NOTE:

BCO5L-01 = 30.48 CM (12 INCHES)
BCO5L-1K=53.34 CM {21

INCHES}

BCO5L-2F = 76.2 CM (30 INCHES)
RD1540

Figure 2-5

DHVI11 Installation

2-8

Connect the BCO5L cables to J1 and J2. Figure 2-5 shows how the parts of the option connect
together.

Install the module in its correct backplane position as defined in Section 2.4.

2.6
2.6.1

Check that +5 V is present between AA2 and ground.

Check that +12 V is present between BD2 and ground.

CABLES AND CONNECTORS
Distribution Panel

Each H3173-A distribution panel adapts one of the DHV11’s berg connectors to four subminiature Dtype RS-232-C connectors. Noise filtering is provided on each pin of the RS-232-C connectors. This
reduces electromagnetic radiation from the cables. It also provides the logic with some protection against
static discharge.

Figure 2-6 shows the layout and Figure 2-7 shows the circuit. There is no CCITT equivalent of EIA
circuit AA (protective ground). The 0-ohm link W1 can be removed to disconnect this circuit as needed.

Table 2-2 is for two distribution panels. Information in parentheses applies to channels 4 to 7.
METAL PLATE
FILTERED D-TYPE (x4)

SCREWLOCK (x8)

4.57cm (1.80in)

8.38cm (3.30in)

._1.88cm

)

J1 [:
-

THREADED
[
It

N S—

PCB

=
—

INSERT (x4)

| - FORG6-32

BOLT 90-06021-01

2]
.

[

= e

BERG (J5

nL_'l‘

2.62cm

(1.031in)

5.24cm (2.062in)
NOT DRAWN TO SCALE
6.60cm (2.60in)

RD1146

Figure 2-6

H3173-A Layout

2-9

The following is an example of the use of Table 2-2.

Signal TXDO is the Transmitted Data line for channel 0. Its CCITT circuit number is 103. Itis connected

to J5 pin B on the H3173-A for channels O to 3.

Signal TXD4 is the Transmitted Data line for channel 4. Its CCITT circuit number is 103. Itis connected

to J5 pin B on the H3173-A for channels 4 to 7.
J1

KA\
SIGNAL GROUND
=

TRANSMIT DATA 0/4

Y | DATA CARRIER DETECT 2/6

RECEIVE DATA 0/4

& |

DATA TERMINAL READY 0/4

2.0

RING INDICATOR 0/4

2'2

;

CLEAR TO SEND 0/4

REQUEST TO SEND 0/4

DATA SET READY 2/6

B-.B

REQUEST TO SEND 2/6

C.C

CLEAR TO SEND 2/6

D.D

RING INDICATOR 2/6

2'2

£ | DATA TERMINAL READY 2/6

2’0

%
K|

DATA SET READY 0/4

RECEIVE DATA 2/6

DATA CARRIER DETECT 0/4

H.H

TRANSMIT DATA 2/6

;

J.J

SIGNAL GROUND

;

SIGNAL GROUND

TRANSMIT DATA 1/5

K‘K

DATA CARRIER DETECT 3/7

RECEIVE DATA 1/5

L’L

DATA SET READY 3/7

DATA TERMINAL READY 1/5

M.M

RING INDICATOR 1/5

2.2

REQUEST TO SEND 3/7

CLEAR TO SEND 1/5

CLEAR TO SEND 3/7

REQUEST TO SEND 1/5

Ffi

RING INDICATOR 3/7

2'2

S=S

DATA TERMINAL READY 3/7

2'0

\./
Vé/

DATA SET READY 1/5

TeT

RECEIVE DATA 3/7

>'<

DATA CARRIER DETECT 1/5

TRANSMIT DATA 3/7

Vo/_|

SIGNAL GROUND

NSy

\_/
il

-0—o—

— PROTECTIVE GROUND
RD1147

Figure 2-7

H3173-A Circuit Diagram

2-10

Table 2-2

H3173-A Connections

Circuit No.

JS Pin No.

102
103
104
108/2
125
106
105
107

1-A (2-A)
1-B (2-B)
1-C (2-C)
1-D (2-D)
1-E (2-E)
1-F (2-F)
1-H (2-H)
1-K (2-K)

SIGGND 1(5)
TXDI(5)

102
103

1-M (2-M)
I-N (2-N)

CTS1(5)
RTS1(5)
DSRI(5)

DCDI1(5)

106
105
107
109

1-T (2-T)
1-U (2-U)
1-W (2-W)
1-X (2-X)

DCD2(6)

109

1-Y (2-Y)

RTS2(6)
CTS2(6)

105
106

1-BB (2-BB)
1-CC (2-CC)

TXD2(6)
SIG GND 2(6)

103
102

1-HH (2-HH)
1-JJ (2-17)

Signal

Name

SIG GND 0(4)
TXD0(4)
RXDO0(4)
DTRO(4)
RIO(4)
CTS0(4)
RTS0(4)
DSRO0(4)

Transmitted Data
Received Data
Data Terminal Ready
Ringing Indicator
Clear to Send
Request to Send
Data Set Ready

DCDO0(4)

Data Carrier Detected

RXDI1(5)
DTRI1(5)
RIL(5)

109

104
108/2
125

DSR2(6)

107

RI2(6)
DTR2(6)
RXD2(6)

125
108/2
104

1-L (2-L)

1-P (2-P)
1-R (2-R)
1-S (2-S)

1-Z (2-2)
1-DD (2-DD)
1-EE (2-EE)
1-FF (2-FF)

DCD3(7)
DSR3(7)
RTS3(7)
CTS3(7)

109
107
105
106

1-KK (2-KK)
1-LL (2-LL)
I-NN (2-NN)
1-PP (2-PP)

DTR3(7)

108/2

1-SS (2-SS)

TXD3(7)
SIG GND 3(7)

103
102

1-UU (2-UU)
1-VV (2-VV)

RI3(7)

125

RXD3(7)

104

2-11

1-RR (2-RR)

1I-TT (2-TT)

2.6.2

Staggered Loopback Test Connector H3277

(See Figure 2-8.) The H3277 test connector is used during diagnostic tests. It allows all channels to be
tested. Using this connector, you can trace a channel fault to one of two channels.
J2

J
8

TXDO j

RXD2

TXD2

RXDO

DTRO

{

TXD4

RXD6

TXD6

RXD4

DTR4

RI6

RI2

DSR2

DSR6

DTR2

DTR6

RIO

RI4

DSRO

DSR4

RTSO

RTS4

cTS2

CTS6

DCD2

DCD6

RTS2

RTS6

CTSO

CTS4

DCDO

DCD4

TXD?

TXD5

RXD3

RXD7

TXD3

RXD1

DTR1

RI3

DSR3

5
g

5
e

8
3

8
o

TXD7

RXD5

DTR5

~—

RI7

PHYSICAL ARRANGEMENT

DSR7

————

DTR3

DTR7

RIS

DSR1

DSR5

RTS1

RTS5

CTS3

CTS7

DCD3

DCD7

RTS3

RTS7

CTS1

CTS5

DCD1

DCD5

x
RD1148

Figure 2-8

Staggered Loopback Test Connector

2-12

2.6.3

Line Loopback Test Connector H325

This connector is shown in Figure 2-9. It can be used during diagnostic tests to trace a fault to a single
channel.

CCITT No.

NAME

24
TM
NOT USED ——
15

NOT USED

TM
NOT USED —
NOT USED —————

103

TXD

104

RXD )

105

RTS

106

CTS

109

pcb ——

[O@D Cj

TM
—

H325

PHYSICAL ARRANGEMENT

NOT USED AL S
107

DSR

108.2

oTR 22

125

RI 22

jv\”

W1 IS PERMANENTLY IN

FOR DHV11 TESTING

CONNECTIONS
RD1149

Figure 2-9

2.6.4

Null Modem Cables

Line Loopback Test Connector

Null modem cables are used for local RS-232-C connection. Because of Federal Communications
Commission (FCC) regulations, the cable specifications for the United States and Canada are different
from those for non-FCC countries. Other countries may also have similar ElectroMagnetic Interference
(EMI) control regulations. EMC/RFI shielded cabinets (see glossary) are now available for systems
which conform to FCC requirements.

Recommended null modem cables are as follows:
BC22D (for EMC/RFI shielded cabinets)

Lengths available:
BC22D-10
BC22D-25
BC22D-35
BC22D-50
BC22D-75
BC22D-A0
BC22D-BS

3.1 m (10 ft)
7.62 m (25 ft)
10.72 m (35 ft)
15.24 m (50 ft)
22.9 m (75 ft)
30.48 m (100 ft)
76.2 m (250 ft).

BCO3M

Round 6-conductor (three twisted pairs), each pair shielded

Cables over 30.48 m (100 ft) have a 25-pin subminiature D-type female connector at one
end. The other end is unterminated for passing through conduit.

Cables 30.48 m (100 ft) and less have a similar connector at each end.

Lengths available:
BCO3M-25
BCO3M-AO
BCO03M-B5
BCO03M-EO
BCO3M-LO

Round 6-conductor fully shielded cable to FCC specification
Subminiature 25-pin D-type female connector moulded on each end

{

e
e

7.62 m (25 ft)
30.48 m (100 ft)
76.2 m (250 ft)
152.4 m (500 ft)
304.8 m (1000 ft).

BC22A

e
e
e

Round 6-conductor cable
Subminiature 25-pin D-type female connector moulded at each end
Lengths available:
BC22A-10
BC22A-25

3.1 m (10 ft)
7.62 m (25 ft).

Cables of groups 1, 2, and 3 are all connected as in Figure 2-10. The cables are not polarized and can
therefore be connected either way.

2-14

NUMBERS

NUMBERS
1 o PROTECTIVE GROUND

PROTECTIVE GROUND o1

20 TRANSMITTED DATA

RECEIVI?D DATA 03

o- RECEIVED DATA

TRANSMITTED DATA 0

7 0 SIGNAL GROUND

SIGNAL GROUND 07

6 O DATA SET READY

DATA TERMINAL READY 0 20

20 C‘rDATA TERMINAL READY

DATA SET READY 06
RL1150

Figure 2-10

Null Modem Cable Connections

2.6.5 Full Modem Cables
Recommended full modem cables are as follows:
1.

BC22F (for EMC/RFI shielded cabinets)

¢
e
e

Round 25-conductor fully shielded cable
Subminiature 25-pin D-type female connector on one end, male connector on the other
Lengths available:
BC22F-10
BC22F-25
BC22F-35
BC22F-50
BC22F-75

—
-

3.1 m (10 ft)
7.62m (25 ft)
10.72 m (35 ft)
15.24 m (50 ft)
229 m (75 ft)

BCO5D

e
e
e

Round 25-conductor cable
Subminiature 25-pin D-type female connector on one end, male connector on the other
Lengths available:
BCOSD-10
BCO5D-25
BCO5D-50
BCO5D-60
BCOSD-A0

—
—

3.1 m (10 f)
7.62m (25 ft)
15.24 m (50 ft)
18.6 m (60 ft)
30.48 m (100 ft).
CAUTION

In some countries, protective hardware may be
needed when connecting to certain lines. Refer to
the national regulations before making a connection.

2-15

2.6.6

Data Rate to Cable Length Relationships

All the recommended cables have data rate/cable length characteristics as in Table 2-3. Cables of lengths
different from those quoted in Sections 2.6.4 and 2.6.5 will have to be specially made. A suitable nonFCC cable for this purpose is Belden type 8777.

Table 2-3
Data Rate

(Bits/s)
110
300
1200
2400
4800
9600

Data-Rate/Cable-Length Relationships

Cable Length

914
914
152
152
76
76

3000
3000
500
500
250
250

(Meters)

(Feet)

NOTE

Cables longer than 15.24 m (50 ft) or with a total
capacitance greater than 2.5 nanofarads violate
RS-232-C and V.28 specifications.
CAUTION

RS-232-C is meant for local communication.
Communication devices can be damaged by induced
high voltages. You can usually minimize these
voltages by limiting the total cable length to 100 m
(300 feet), or by installing surge-limiting devices.
Do not run the cable outdoors. Keep low-voltage
data wiring away from ac power wiring, as required
by electrical codes of practice.
2.7

MULTIPLE COMMUNICATIONS OPTIONS

2.7.1
Floating Device Addresses
On UNIBUS and Q-bus systems, a band of addresses (xxx60010g to xxx63776g) in the top 4K words is
assigned as floating address space (xxx means all top address bits = 1).
Options which can be assigned floating device addresses are listed in Table 2-4. This table gives the
sequence of addresses for both UNIBUS and Q-bus options.
Having one list allows us to use one set of configuration rules and one configuration program.

2-16

Table 2-4

Rank

Floating Device Address Assignments

Size
(Decimal)

Modulus
(Octal)

4
8
4
4
4
4

10
20
10
10
10
10

DZS11, DZ32
KMCl11
LPP11
VMV21
VMV3l1
DWR70
RL11, RLV11
LPA11-K

4
4
4
4
8
4
4
8

10 (DZ11 before DZ32)
10
10
10
20
10
10 *
20 *

RX11/RX211,
RXV11/RXV21
DR11-W
DR11-B
DMPI11
DPV11
ISB11

4
4

10
10

Device

1
2
3
4
5
6

DJ11
DH11
DQ11
DU11, DUV11
DUP11
LK11A

DZ11/DZV11,

9
10
11
12
13
14
15
16
17

18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

DMCI11/DMRI11

KW11-C
Reserved

DMV11
DEUNA
UDA50/RQDX DMF32

KMSI11

VS100
TU81
KMV11
DHV11/DHU11 ~

10 (DMC before DMR)

10 *
(RX11 before RX211)
10
10 **
10
10
10

4
4
4
4
4
8
4
2
16
6
8
2

20
10 *
4 *
40

20
4
20
20

8
8

* The first device of this type has a fixed address. Any extra devices have a floating address.
#k The first two devices of this type have a fixed address. Any extra devices have a floating address.

NOTE

DZ11-E and DZ11-F are treated as two DZ11s.
When there are no previous floating address
space options in a system, the address of the first
DHYVI11 installed will be 760440g.

2-17

Devices of the same type are given addresses in sequence, so all DZV11s have addresses higher than
DUV1is and lower than RLV11s.
The column Size (Decimal), in Table 2-4, shows how many words of address space are needed for each
device. The column Modulus (Octal) is the modulus used for starting addresses. For example, devices
with an octal modulus of 10 must start at an address which is a multiple of 10g. The same rule is used to
select a gap address after an option, or for a nonexistent device.

The address assignment rules are as follows.

Addresses, starting at 17760010g, are assigned according to the sequence of Table 2-4.

Option and gap addresses are assigned according to the octal modulus as follows:
a.

Devices with an octal modulus of 4 are assigned an address on a 4g boundary (the two
lowest-order address bits = 0)

Devices with an octal modulus of 10 are assigned an address on a 10g boundary (the three
lowest-order address bits = 0)

Devices with an octal modulus of 20 are assigned an address on a 20g boundary (the four
lowest-order address bits = 0)

Devices with an octal modulus of 40 are assigned an address on a 40g boundary (the five
lowest-order address bits = 0)

Address space equal to the device’s modulus must be allowed for each device which is
connected to the bus

A 1-word gap, assigned according to rule 2, must be allowed after the last device of each type.
This gap could be bigger when rule 2 is applied to the following rank

A l-word gap, assigned according to rule 2, must be allowed for each unused rank on the listifa
device with a higher address is used. This gap could be bigger when rule 2 is applied to the
following rank.

If extra devices are added
to a system, the floating addresses may have to be reassigned in agreement with
.
these rules.
In the following example, a brief description of address assignment is given. Note that the list includes
floating vector addresses. These are explained in Section 2.7.2.

Example:

One DUVI1I1, one RLV11, and two DHV11s

Address (Octal)

Vector

xxx60010
xxx60020
xxx60030
xxx60040

DJ11 gap
HI11 gap
DQ11 gap
DUV11

xxx60050

DUV11 gap

2-18

300 .

Vector

Address (Octal)

{

xxx60060
xxx60070
xxx60100
xxx60110
xxx60120

DUPI11 gap
LK11A gap
DMCI11 gap
DZV11 gap
KMCI11 gap

xxx60130
xxx60140
xxx60160
xxx60170

LPP11 gap
VMV21 gap
VMV31 gap
DWR70 gap

xxx60200

RLVI11

xxx60210
xxx60220
xxx60230
xxx60240
xxx60250

RLVI11 gap
LPA11-K gap
KW11-C gap
reserved gap
RXV11 gap

xxx60260
xxx60270
xxx60300

DR11-W gap
DR11-B gap
DMP11 gap

xxx60320

ISBI11 gap

xxx60310

310

DPV11 gap

xxx60340
xxx60350

DMVI11 gap
DEUNA gap

= xxx60354

UDASO gap

xxx60400
xxx60420

DMF32 gap
KMSI11 gap

xxx60440
xxx60444
xxx60460
- xxx60500
+ xxx60520

VS100 gap
reserved
KMV11 gap
Ist DHV11
2nd DHV11

xxx60540

DHV11 gap

320
330

The first floating address is xxx60010. As the DJ11 has a modulus of 10g, its gap can be assigned to

xxx60010. The next available location becomes xxx60012.

As the DH11 has a modulus of 20g, it cannot be assigned to xx60012. The next modulo 20 boundary is
xxx60020, so the DH11 gap is assigned to this address. The next available location is therefore
xxx60022.

A DQI11 has a modulus of 10g. It cannot be assigned to xxx60022. Its gap is therefore assigned to
xxx60030. The next available location is xxx60032.

A DUV11 has amodulus of 10g. It cannot be assigned to xxx60032. It is therefore assigned to xxx60040.
As the ‘size’ of DUV11 is four words, the next available address is xxx60050.

2-19

There is no second DUV11, so a gap must be left to indicate that there are no more
DUV11s. As
xxx60050 is on a 10g boundary, the DUV11 gap can be assigned to this address. The
next available
address is xxx60052.

And so on.
2.7.2 Floating Vectors
Addresses between 3003 and 774g are designated as the floating vector space. These
addresses are
assigned in sequence as in Table 2-5.
Each device needs two 16-bit locations for each vector. For example, a device with one
receive and one
transmit vector needs four words of vector space.
:
The vector assignment rules are as follows:

Each device occupies vector address space equal to ‘Size’ words. For example, the

occupies 16 words of vector space. Ifits vector was 3003, the next available

340g.

There are no gaps, except those needed to align an octal modulus.

An example of floating vector address assignment is given in Section 2.7.1.
Table 2-5

Rank

Floating Vector Address Assignments

Device

Size

(Decimal)
1
1

DC11
TUS58

2
2

KL11
DLI11-A

Modulus

(Octal)

4
4
4

10
10
10

4
4

10
10
10
10
10
10

DLI11-B

2
2
3
4

DLV11-J
DLV11, DLVI11-F
DPI11
DM11-A
DN11

8
9
10

DM11-BB/BA
DH11 modem control
DRI11-A, DRV11-B
DRI11-C, DRV11
PA611 (reader + punch)

2
2
4
4
8

11
12
13
14
15

LPD11
DIO7
DX11
DL11-C to DLV11-F
DJ11

4
4
4
4

10
10
10
10

6
7

4
4
4
2

2-20

4
4
10
10
10

DLV11-J

vector would be at

Table 2-5

Floating Vector Address Assignments (Cont)

Rank

Device

Size
(Decimal)

Modulus
(Octal)

16
17
17
18

DHI11
VT40
VSVil
LPS11

4
8
8
12

10
10
10
10

20
21
22
23
24

KWI11-W, KWV11
DUI11, DUV11
DUPI11
DV11 + modem control
LK11-A

4
4
4
6
4

10
10
10
10
10

25
26
27

DWUN
DMCI11/DMRI11
DZ11/DZS11/DZV11,

4
4

10
10

(DMC before DMR)

(DZ11 before DZ32)

KMC11

32
33

LPP11
VMV21
VMV3l

VTVO01
DWR70

4
4
4

10
10
10

34
35
36
37
38

RL11/RLV11
TS11, TU80O
LPA11-K
IP11/1P300
KW11-C

2
2
4
2
4

4
4
10
4
10

%
%

RX11/RX211
RXV11/RXV21

DRI11-W
DR11-B
DMPI11

2
2
4

4
4
10

%
(RX11 before RX211)

43
44
45
46
47

DPV11
MLI11
ISB11
DMYV11
DEUNA

4
2
4
4
2

10
4
10
10
4

48
49
50
51
52

UDASO/RQDX1
DMF32
KMS11
PCL11-B
VS100

2
16
6
4
2

4
4
10
10
4

28
29
30
31

40
41
42

DQI11

DZ32

4
4

10
10

(MASSBUS device)
=

* The first device of this type has a fixed vector. Any extra devices have a floating vector.

2-21

Table 2-5

Floating Vector Address Assignments (Cont)

Rank

Device

Size

TUS81

54
55
56
57

KMV11
KCT32
IEX
DHVI11/DHU11

4
4
4
4

10
10
10
10

(Decimal)

Modulus

(Octal)

NOTE
A KL11 or DL11 used as the console has a fixed
vector.

ML11 is a MASSBUS device which can connect
to UNIBUS via a bus adapter.

2.8
INSTALLATION TESTING
All individual device diagnostics should be run without error before DECX/11 is used.
2.8.1
Testing in PDP-11 Systems
The following tests should be run after installation:
1.
2.
3.
4.
5.

Internal loopback

Staggered loopback
Line loopback
Modem loopback.
Keyboard echo (CVDHC only)

The self-test runs automatically when the bus or DHV11 is reset. If no fault is found, the diagnostic LED
will flash OFF/ON/OFF and then come ON permanently. The first off state is very short and may not be

seen. However, ifthe LED goes off before coming on permanently the diagnostic has found no faults. This
does not prove that the option is serviceable.
During the self-test diagnostic operation, bytes are written to the FIFO. By reading these bytes, the

engineer can receive more detailed information about the state of the DHV11. Diagnostic bytes and their
interpretation are described in Section 3 of this document. The self-test can take up to 2.5 seconds.

CVDHB? and CVDHC? have four modes of operation:

1.
2.
3.
4.

Internal loopback
Staggered loopback
Line loopback
Modem loopback.

2-22

The mode can be selected by answering a prompt from the diagnostic program. A summary of the use of
the diagnostic supervisor is provided in Chapter 5.

Test the module in the following sequence. There is a test flowchart in Section 5.9 of this manual.
1.

Switch on power, or reset the system. Check the diagnostic LED sequence.

Run the CVDH?? diagnostics for one error-free pass (CVDHB? and CVDHC? in the internal
loopback mode). Any fault message indicates a defective module.
Connect the H3277 staggered loopback connector and run CVDHB? and CVYDHC? for one
error-free pass in the staggered loopback mode. Any fault message indicates a defective
DHYV11 or cable. Swap cables (as in Figure 5-2, configuration C) and repeat the test in order to
find the defective component.

Connect the BCO5L-xx cables as for normal operation. Install an H325 line loopback
connector at line number O of the distribution panel. Run CVDHB? and CVDHC? in line
loopback mode on line number O for one error-free pass. Repeat for all lines.
Run the DECX/11 exerciser to verify that the DHV11 will run with other options of the
system.

NOTES
The DHV11 should now be ready for connection

to external equipment. See Section 2.6 if necessary,
for recommended modem and null-modem cables.
The CVDH?? diagnostics can be used, in modem
loopback mode, to check the communications
link. The modem must be set up manually. The

diagnostic will test to the point where the line is .
looped back.

2.8.2

Testing in MicroVAX I Systems

The following diagnostic tests are available for testing a DHV11 in MicroVAX I systems.
EHXDH

EHKMZ

DHV11 Test

Macroverify-MicroVAX System Test

Macroverify is a standalone diagnostic which contains a DHV11 test module. Further information is
contained in Chapter 5. Chapter 5 also contains information on testing in MicroVAX II systems.
Test the option as follows:
1.

Boot from the MicroVAX system diskette (number 2 of 2). Attach and select the DHV11
which you want to test.

Run EHXDH for three error-free passes of the internal (default) test.
Install the H3277 staggered loopback connector on the M3104 ribbon cables (see Figure 2-5).
Run EHXDH for three error-free passes of the staggered test.
Remove the H3277 and configure the DHV11 for normal operation.

2-23

Ifyou want to test the operation of a terminal link, connect the terminal line to the distribution

panel. Runthe EHXDH echo test on that line until the link is proven. Depending on the type of

terminal, you may need a null modem for this test. Press CTRL/Z to exit from the echo test.

Remove all external cables and connectors from the distribution panel. Boot the CPU tests
diskette (number 1 of 2). The Macroverify diagnostic runs automatically when the boot process
is complete. When the test completes, the status of all options is displayed.

Ifnodevice has a TEST FAILED status, the DHV11 is now ready for connection to external
equipment. If the connection is to a local terminal, you must use a null modem cable assembly.

Use the BC22A, BC22D, or BCO3P null modem cables for connection between the option and
the terminal. You can also use the H312-A null modem unit in place of null modem cables.
Use a BC22E or BCO5D cable to connect the option and a modem.
Because they are not components of a DHV11 option, all of the referenced cables must be ordered
separately.

2.8.3 Testing in MicroVAX II Systems
|
Refer to Section 5.7 of Chapter 5, and run the maintenance version of the diagnostic as described
in
Section 5.7.3. Run the DHV11 test for three error-free passes.

If you want to test the operation of a terminal link, you can select the appropriate echo test from the menus.
When the echo test has completed, run the first part of the MicroVAX II diagnostic; this is option 1 on
the
main menu. When this test has completed, refer to step 7 of Section 2.8.2.

2-24

CHAPTER 3
PROGRAMMING
/

3.1

SCOPE

This chapter describes the CSR and control registers, and how they are used to control and monitor the

DHV11. The chapter covers:

o
e

The bit functions and format of each register
Programming features available to the host.

Some programming examples are also included.

Chapter 4, Sections 4.1 to 4.6, is recommended reading for anyone programming this device.
3.2

REGISTERS

The host system controls and monitors the DHV11 module via several registers which are 1mplementedin

RAM.

Command words or bytes written to the registers are interpreted and executed by the firmware. Status

reports and data are also transferred via the registers.

One of the functions of the microcomputers is to scan the registers for new instructions or data.
-

3.2.1

DHVI11 reglsters occupy eight words (16 bytes) of Q-bus, memory-mapped 1/O space. However, by
indexing, th1sis expanded on the DHV11 to 114 words.

The positionof the eight words within the top 4K words of memory, is switch-selected onthe DHV11. In
order to access the module, b1ts <12:4> of an I/0 address must match the address switch coding.

Table 3-1 lists the DHV11 registers and their addresses. The suffix (M) means that there are elght of these
registers; one for each channel. When an (M) register is accessed, the address (Table 3-1)is indexed by
the contents of CSR<3:0>.

NOTE

CSR<3:0> allows 16 registers to be addressed.
However, only the bottom eight registers of each
block are used. Therefore CSR bit 3 must always
be 0.

The term ‘Base’ means the lowest I/O address on the module. That is to say, when the four low-order
address bits = 0.

3-1

‘

Table 3-1

DHV11 Registers

(CSR)

Receive Buffer
Transmit Character
Line Parameter Register
Line Status
-

Line Control

(RBUF)
(TXCHAR)
(LPR)
(STAT)

‘

Type

Base

Read/Write

Base + 2
Base +2
Base +4
Base + 6

(LNCTRL)

Transmit Buffer Address 1
Transmit Buffer Address 2
Transmit Buffer Count

Address (Octal)

(M)
(M)
(M)

Read Only
Write Only
Read/Write
Read Only

Base + 12 (M)
Base + 14 (M)
Base + 16 (M)

Read/Write
Read/Write
Read/Write

Base + 10 (M)

(TBUFFADI)
(TBUFFAD2)
(TBUFFCT)

Read/Write

NOTE
It is physically possible to write to the line status
register. However, this register must not be written
by the host.
Registers are accessed by instructions which use ‘base + n’ as a source or destination. However, before
multiple (M) registers are accessed, the channel number must be written to the CSR. The following
example explains this.
To read the line status register of channel 3, the following I/O commands would be executed:

MOVB #CHAN,@#BASE
MOV @#BASE+6,R0

;WRITE CHANNEL NUMBER (SEE BELOW) TO CSR
;READ THE LINE STATUS REGISTER

In the above example:

CHAN = Oer00011,

Where e

= the RXIE bit

and r
= the MRST bit (would be 0)
and 0011, = channel number 3

‘Base + 6’ will address a block of 16 line status registers, only eight of which are used. The DHV11
hardware will index this address by three, thereby selecting line status register number 3.
NOTE
1.

Not all register bits are specified. In a write

action, all unspecified bits must be written as
Os. In a read action, unspecified bits are
undefined.
2.

The exception to the above rule is that a bit
may be written as logical 1 or 0 if it is read as
logical 1. That is to say, read-modify-write
instructions work correctly.

3-2

3.2.2

Bits marked * may hold data set status, or special information from the diagnostic programs.

These are covered in Section 3.3.10.

Registers which are modified by reset sequences are coded as shown in Figure 3-1.

CLEARED BY MASTER RESET

SET BY MASTER RESET

_— CLEARED BY BINIT

BUT NOT BY MASTER RESET
RD2249

Figure 3-1

3.2.2.1

Control and Status Register (CSR) -

CSR (BASE)

R R/Wl

R |R'W | R/W
Y |

4
:

R/W | R/W |R/W | R"W
:

RCVE

DIAGNOSTICS

ACTION

| FAILURE

TRANSMIT

A& TRANSMIT
:

L’L&BLE

LINE NUMBER

(RXIE)

RCVE DATA

DMA ERROR

AVAILABLE

INDIRECT ADDRESS REG POINTER

(CHANNEL No.)

MASTER
RESET

Bit

Name

Description

<3:0>

IND.ADDR.REG

These bits are used to select the wanted channel register when

(Indirect Address
Register) (R/W)

accessing a block of indexed (M) registers. They form the binary
number of the channel which is to be accessed.

MASTERRESET
(Master Reset)

Set by the host, in order to reset DHV11. Stays set while DHV11
runs a self-test diagnostic, and then performs an initialization
sequence. The bit is then cleared to tell the host that the process is
complete.

(R/W)

This bitis set by BINIT (bus initialization signal), or by the host
processor setting CSR<5>,

The host should not write to this bit when it is already set.
6

RXIE
(Receiver
Interrupt
Enable)

(R/W)

When set, this bit allows the DHV11 to 1nterrupt the host when
RX.DATA.AVAILis set. An interrupt is generated under the
following conditions:
\

1.
2.

RXIE is set and a character is placed into an empty FIFO
The FIFO is not empty and RXIE is changed from O to 1.

Cleared by BINIT but not by MASTER.RESET.
7

RX.DATA.
AVAIL
(Received Data
Available) (RD)

When set, indicates that a received character is available. This bit is
clear when the FIFO is empty. It is used to request an RX interrupt.
Set after MASTER.RESET because the
information.

FIFO contains diagnostic

Bit
<11:8>

- Name

Description

TX.LINE

If TX.ACTION is set, these bits hold the binary number of the

(Transmit Line
Number) (RD)

channel which has just:

1.
2.
3.

Completed a DMA block transfer
Accepted a single character for transmission
Aborted a DMA block transfer.

If TX.DMA.ERR s also set, these bits contain the binary number of
the channel which has failed during a DMA transfer.
12

TX.DMA.

If set with TX.ACTION also set, means that the channel indicated

ERROR

by CSR<11:8> has failed to transfer DMA data within 10.7

(Transmit DMA
Error) (RD)

microseconds of the bus request being acknowledged, or that there is
a memory parity error.
’
TBUFFADI and TBUFFAD?2 registers will contain the address of
the memory location which could not be accessed. TBUFFCT will
be cleared.

DIAG.FAIL
(Diagnostic Fail)

(RD)

When set, indicates that DHV 11 internal diagnostics have detected
anerror. The error may have been detected by the self-test diagnostic

or by the BMP.

This bit is associated with the diagnostic-passed LED. Whenitis set,
the LED will be off. When it is cleared, the LED will be on.
The bit is set by MASTER.RESET. It is cleared after the internal
diagnostic programs have been run successfully.
It is only valid after the MASTER.RESET bit CSR<5> has been cleared.
14

TXIE
(Transmit Interrupt
Enable) (R/W)

When set, allows the DHV11 to interrupt the host when CSR<15>
(TX.ACTION) becomes set.
'
:
Cleared by BINIT but not by MASTER.RESET.

TX.ACTION
(Transmitter
Action) (RD)

This bit is set by DHV11 when:
1.

The last character of a DMA buffer has left the DUART

A DMA transfer has been aborted

A DMA transfer has been terminated by the DHV11 because
of nonexistent memory being addressed, or because of a
memory parity error

Bit

‘Name

Description
4.

When a single-character programmed output has been
accepted. That is to say, the character has been taken from
TX.BUFF.

This bit is cleared when the CSR is read by the host.
Also cleared by MASTER.RESET.
NOTE

CSR contents should only be accessed by a MOV or MOVB
instruction. Other instructions may lose the state of the TX
ACTION bit (CSR<15>).

3.2.2.2

Receive Buffer (RBUF) — This register has the same address as the Transmit Character

register (TXCHAR). However, a READ from ‘base + 2’ is interpreted by the DHV11 hardware as a
READ from the FIFO. Therefore, RBUF is a 256-character register with a single-word address. The
Least Significant Bit (LSB) of the character is in bit 0.
RBUF (READ BASE + 2)

N
DATA

VALID

FRAMING

| ERROR

OVERRUN

ERROR

RECEIVE

LINE NUMBER

|
RECEIVED

CHARACTER
gr

DATA SET

PARITY

(FROM HIGH BYTE

STATUS FLAGS OF STAT)

ERROR

OIR
DIAGNOSTIC INFO

Bit

Name

Description

<7.0>

RX.CHAR

If RBUF<14:12> = 000, these eight bits contain the oldest

Character)
(RD)

,
If RBUF<14:12> = 001, 010, or 011, these eight bits contain the

(Received

character in the FIFO. The character is good.

oldest character in the FIFO. The character is bad.

Bit

Name

Description

If RBUF<14:12> = 111, these eight bits contain diagnostic or
modem status information. In this case, RBUF<0> has the
following meanings:

0 = Modem status in RBUF<7:1> (see Section 3.2.2.5)
1 = Diagnostic informationin RBUF<7:1> (see Section 3.3.10).

If there is an overrun condition, the UART data buffer for that

channel will be cleared. A null character, with RBUF<14> set, will
be placedin the receive character FIFO. The cleared data will be
lost.

The DHVI11 does not have a break detect bit. A line break is
indicated to the program as a null character with the

FRAME.ERR

set.

<11:8>

RX.LINE
(Receive
Line Number)

These bits hold the binary number of the channel on which the

character of RBUF<7:0> was received or on which a data set
change was reported.

(RD)
12

PARITY.ERR
(Parity Error)

Set if this character has a parity error and parity is enabled for the
channel indicated by bits <11:8> (also see RX.CHAR).

(RD)
13

FRAME.ERR
(Framing Error)

Set if the first stop bit of the received character was not detected (also
see RX.CHAR).

(RD)
14

OVERRUN.ERR
(Overrun Error)

(RD)

Setif one or more previous characters of the channel indicated by bits
<11:8> were lost because of a full FIFO or failure to service the
UART:s (also see RX.CHAR).

NOTE
The‘all 1s’ code for bits <14:12>is reserved. This code indicates
that modem status or diagnostic information is held in
o
RBUF<7:0>.
15

DATA.VALID
(Data Valid)

(RD) -

Set if the FIFO is not empty. Cleared by MASTER.RESET or by
the FIFO becoming empty.
After self-test, diagnostic information is loaded into the FIFO.
Therefore this bit is always set after a successful master reset
sequence.

3-7

3.2.2.3

Transmit Character Register (TXCHAR) - Single-character programmed transfers are

made via the transmit character register. Bit function is as follows:
TXCHAR (WRITE BASE + 2)
15

wilwlwl|lw]|lw]|w]|lw]|w

TRANSMIT

DATA VALID

CHARACTER

Bit

Name

Description

<7.0>

TX.CHAR

Character to be transmitted. The LSB is bit 0. For 7-, 6-, or 5-bit

(Transmit

characters, unused bits must be ‘0’.

Character)

(WR)
15

TX.DATA.

When set, instructs the DHV11 to transmit the character held in bits

(Transmit Data
Valid) (WR)

character, clears the bit, and sets TX.ACTION.

VALID

<7:0>. The bit is sensed by the DHV11 which then transfers the

TX.DATA.VALID and the character can be written together, or by
separate MOVRB instructions.

3.2.2.4

Line Parameter Register (LPR) — This register is used to configure its associated channel.

Bit function is as follows:
LPR (BASE + 4)

R‘W|R/W|R/W |R/W |R/W |

W | R“"W | R“W | RAW |

TRANSMIT

STOP

RECEIVE

PARITY

EVEN

3-8

“

ENABLE

PARITY

SPEED

R“W | R"W | "W | R“W | R“W | R“/W

CODE

SPEED

CHARACTER

LENGTH

DIAGNOSTIC

CODE

Bit

Name

Description

<2:1>

DIAG

Diagnostic control codes. Used by the host as follows:

(Diagnostic
.

Code)

00 = Normal operation

(R/'W)

01 = Causes the Background Monitor Program (BMP) to report
the DHV11 status via the FIFO. BMP reports are covered in
Section 3.3.10.

<4:3>

CHAR.LGTH

Defines the length of characters. Does not include start, stop, and

(Character

parity bits.

Length)

(R/W)

00 = 5 bits

01 = 6 bits
10 = 7 bits
11 = 8 bits
Set to 11 by MASTER.RESET.

PARITY.ENAB
(Parity Enable)

(R/'W)

Parity enable. Causes a parity bit to be generated on transmit, and
checked and stripped on receive.
1 = Parity enabled
0 = Parity disabled

Cleared by MASTER.RESET.
6

EVEN.PARITY
(Even Parity)

(R/'W)

If LPR<5> is set, this bit defines the type of parity.

1 = Even parity
-~ 0= 0dd parity
" Cleared by MASTER.RESET.

7 .

STOP.CODE
(Stop Code)

(R/'W)

Defines the length of the transmitted stop bit.
’

0 = 1 stop bit for 5-, 6-, 7-, or 8-bit characters
1 = 2 stop bits for 6-, 7-, or 8-bit characters, or 1.5 stop bits for
5-bit characters

Cleared by MASTER.RESET.

<11:8>

<15:12>

RX.SPEED

Set to 1101 by MASTER.RESET (9600 bits/s).

(Received Data
Rate) (R/W)

Defines the receive data rate (Table 3-2).

TX.SPEED
(Transmitted
Data Rate)

Set to 1101 by MASTER.RESET.
Defines the transmit data rate (Table 3-2).

(R/'W)

3-9

Code

Data Rate
(Bits/s)

0000
0001
0010
0011

50
75
110
1345

‘

Table 3-2

Data Rates

Maximum
Error (%)

Groups

0.01
0.01
0.08
0.07

B
Aand B
Aand B

0100
0101
0110
0111

150
300
600
1200

0.01
0.01
0.01
0.01

B
A and B
A and B
A and B

1000
1001
1010
1011

1800
2000
2400
4800

0.01
0.19
0.01
0.01

B
B
A and B
A and B

1100
1101
1110
1111

7200
9600
19200
38400

0.01
0.01
0.01
0.01

A
A and B
B
A

NOTE

The 8-channel interface uses four dual-channel
ICs. Channels0and 1,2 and 3,4 and 5, and 6 and
7 are paired. It is the responsibility of the user to
select transmit and receive data rates of the same
group (A or B) for any pair of channels.
Group B contains most of the commonly used
rates, therefore most software could use this
group only and thus avoid the problem of interaction
between adjacent channels.

If the transmitter and receiver of a channel are configured in different groups, the group of the receiver is
selected.

If a ‘pair’ of channels are configured in different groups, the group of the most recently configured channel

is selected. This changes the data rate of a channel when its paired channel is reconfigured to the other

group.

3-10

3.2.2.5

Line Status Register (STAT)— The high byte of this register holds modem status information.

The low byteis undefined.

STAT (BASE + 6)
15

DSR

DCD

(RING’

CTs

ALWAYS 0

INDICATOR)

Bit
8

Name

Description

STAT<8>

Permits the software to distinguish between DHV11 and DHU11.

(Status

(RD)
11

0 =DHV11

1 =DHUI11

CTS

Gives the present status of the Clear To Send (CTS) 81gnal from the

(Clear to Send)

modem.

(RD)

1=0ON

0 = OFF
12

DCD
(Data Carrier
Detected) (RD)

Gives the present status of the Data Carrier Detected (DCD) signal
from the modem.

1 =0N
0 = OFF

Bit

Name

Description

RI (Ring
Indicator)

Gives the present status of the Ring Indicator (RI) sngnal from the
modem.

(RD)

1=O0ON
0 = OFF

DSR (Data

~ Gives the present status of the Data Set Ready (DSR) signal from the

Set Ready)

modem.

(RD)

1 =0ON
0 = OFF

NOTE

In order to report a change of modem status, the DHV11 writes
the high byte of STAT into the low byte of RBUF.
RBUF<14:12> = 111 to tell the host that RBUF<7:0> do not

hold a received character (see modem control, Section 3.3.8).

3.2.2.6 Line Control Register (LNCTRL) The main function of this register 1s to control the line
interface.
LNCTRL (BASE + 10)
15

R/W

R’W | R/W

RTS

DTR

|RW | R/
W | R“"W | "W ]| R/W | R“W | R“W | R“'W

MAINTENANCE
MODE

LINK
TYPE

__Bit.

OAUTO

FORCE.
XOFF

DMA

ENABLE

BREAK

ABORT

IAUTO

Name

Description

TX.DMA.ABORT
(Transmit DMA
Abort) (R/W)

Set by the driver program to halt the transfer of a DMA buffer. The
transfer can be continued by clearing TX.DMA.ABORT and then
setting TX.DMA.START. No characters will be lost.
The program must make sure that TX.DMA.ABORTis clear before
setting TX.DMA.START. Otherwise the transfer will be aborted
before any characters are transmitted.
See Section 3.3.3.1,
TX.DMA.ABORT.

DMA

Cleared by MASTER.RESET.

3-12

Transfers,

for

the

use

Bit

Name

Description

IAUTO

This is the auto-flow control bit for inéoming characters. If it is set,

(Incoming Auto

the DHV11 will control incoming characters by transmitting X-ON

Flow) (R/W)

and X-OFF codes.

If the FIFO becomes congested, the DHV11 will send an X-OFF
code to channels with this bit set. An X-ON will be sent when the
congestion is reduced. See Auto X-ON and X-OFF, Section 3.3.6.

NOTE
An X-ON code = 21g= DCIl = CTRL/Q.
An X-OFF code = 23g = DC3 = CTRL/S.
No other codes are specified for the interface.

RX.ENA
(Receiver Enable)

(R/W)

If set, this receiver channel is enabled.

If reset when this DUART channel is assembling a character, that

" character is lost.

Cleared by MASTER.RESET.

BREAK

If set, this bit forces the transmitter of this channel to the spacing

(Break Control)

state.

(R/W)

Transmission is restarted when the bit is cleared.

NOTE
There is a short delay between writing the bit and the channel
changing state. The delay is dependent on throughput. Because
of the normal length of a BREAK signal, this should not cause
problems.
4

OAUTO
(Outgoing Auto
Flow) (R/W)

This bit is the auto-flow control bit for outgoing characters. When
set, if RX.ENA is also set, the DHV11 will automatically respond to
X-ON and X-OFF
codes received from a channel. The DHV11
uses the TX.ENA bit in TBUFFAD?2 to stop and start the flow. See
Auto X-ON and X-OFF, Section 3.3.6.

FORCE.XOFF
(Force X-OFF)

This bit can be set by the program to indicate that this channel is
congested at the host system (for example, if the typeahead buffer is
full). When it sees this bit set, the DHV11 will send an X-OFF code.
Until the bit is reset, X-OFFs will be sent after every alternate
character received on that channel. When the bit is reset, an X-ON
will be sent unless IAUTO is set and the FIFO is critical. See Auto
X-ON and X-OFF, Section 3.3.6.

(R/'W)

3-13

Bit

Name

Description

<7:6>

MAINT
(Maintenance Mode)

test the channel.

(R/W)

These bits can be written by the driver or test programs, in or¢
The coding is as follows:

00 = Normal operation
01

Automatic echo mode — Received data is retransmitted
(regardless of the state of TX.ENA) at the data rate
- selected for the receiver. The received characters. are

- processed normally and placed in the received character

FIFO. In this mode, the DHVI11 will not transmit any
characters (this includes internally generated flow-control
characters). The RX.ENA bit must be set when operating
in this mode.
10

Local loopback— The DUART channel output is internally
connected to the input. Normal received data is ignored
and the transmit data line is held marking. In this mode;
flow-control characters will be looped back instead of
being transmitted. The data rate selected for the transmitter
is used for both transmission and reception. The TX.ENA
bit still controls transmission in this mode. The RX. ENA
bit is ignored.

is retransRemote loopback — In this mode, received data
mitted at a clock rate equal to the received clock rate. The
data is not placed in the receiver FIFO. The state of
TX.ENA is ignored. The RX.ENA bit must be set on the
respective channel.

LINK.TYPE
(Link Type)

(R/'W) -

This bit must be set if the channel is to be connected to a modem.
When the bit is set, any change in modem status will be reported via
the FIFO as well as the STAT register.

If this bit is reset, this channel becomes a ‘data leads only’ channel.
Modem status information is loaded in the high byte of STAT but is

not placed in the FIFO.

DTR

(Data Terminal
Ready) (R/W)

RTS

(Request To Send)

(R/W)

“This bit controls the Data Terminal Ready (DTR) signal.
1=ON
0 = OFF

This bit controls the Request To Send (RTS) signal.
1 =0ON
0 = OFF

3-14

3.2.2,7 Transmit Buffer Address Register Number 1 (TBUFFADI) TBUFFAD1 (BASE + 12)
15

R/’W |R/W |R’W |

W |R/W |

W | R“W | R“W | R/W | "W |

W | R“"W |

W | R“W | R“W | R“W

TXMIT
XMl DMA ADDRESS
(BITS O - 15)
RD1178

Bit

Name

Description

<15:0>

TBUFFAD<15:0>
(Transmit Buffer
Address [Low])

Bits <15:0> of the DMA address (see Section 3.2.2.8).

(R/W)

‘3.2.2.‘8 Transmit Buffer Address Register Number 2 (TBUFFAD?2) TBUFFAD2 (BASE + 14)

R/W

TXMIT
ENABLE

DMA
START

R'W|RW]RW|RW|RW|RW
2

Name

Description

<5:0>

TBUFFAD<21:16>
(Transmit Buffer
Address [High])

Bits <21:16> of the DMA address.
Before

TXMIT DMA ADDRESS
(BITS 16 - 21)

Bit

(R/W)

a DMA transfer, TBUFFAD1

and the low byte of

TBUFFAD?2 are loaded with the start address of the DMA buffer.

This address is not valid during a DMA transfer. When TX.ACTION
is returned, the address will be valid.

3-15

Bit

Name

Description

TX.DMA.START
(Transmit DMA
Start) (R/W)

Setby the host tostart a DMA transfer. The DHV11 will reset the bit

before returning TX.ACTION.

Cleared by MASTER.RESET.
NOTE

After setting this bit, the host must not write to TBUFFCT,

TBUFFADI, or TBUFFAD2 <7:0> untll the TX.ACTION
report has been returned.

TX.ENA
(Transmitter Enable)

(R/'W)

When set, the DHV11 will transmit all characters.

When cleared, the DHV11 will only transmit internally generated
flow-control characters.

Set by MASTER.RESET.
In the OAUTO mode, this bit is used by the DHV11 to control outgoing characters. See Auto X-ON and X-OFF, Section 3.3.6.

3.2.2.9

Transmit DMA Buffer Counter (TBUFFCT) -

TBUFFCT (BASE + 16)

RW|RW|{RW|RW]IRW|RW|RW|RWIRW|RW]|R'W|RW|R'W|R'W|RW|RW

/£

DMA CHARACTER COUNT
-

Bit

<15:0>

(WHEN VALID, HOLDS No. OF CHARS. STILL TO BE SENT)

Name

Description

TX.CHAR.CT

Loaded with the number of characters to be transferred by DMA.

Count) (R/W)

The number of characters is specified as a 16-bit unsigned integer.

(Transmit Character

After a DMA transfer has been aborted, this location will hold the
number of characters still to be transferred.
See also the previous NOTE.

3-16

3.3

PROGRAMMING FEATURES

3.3.1

[Initialization

The DHV11 is initialized by its on-board firmware.
Initialization takes place after a bus reset sequence, or when the host sets CSR<5> (MASTER.RESET).

Before starting initialization, the on-board diagnostics run a self-test program. The results of this test are
reported by eight diagnostic bytes in the FIFO.

NOTE

This self-test diagnostic can be skipped on
command from the program. This is covered in
Section 3.3.10.3.

The DHV11 state, after a successful self-test, is as follows:

Eight diagnostic éodes are placed in the FIFO

The diagnostic fail bit (CSR<13>) is reset
All channels set for:

VOBEIFTIPR TM QOO

2.
3.

The DHV11

Send and receive 9600 bits/s
Eight data bits
One stop bit
No parity
Parity odd
Auto-flow off
RX disabled
TX enabled
No break on line
No loopback
No modem control
DTR and RTS off
DMA character counters zero
DMA start addresses zero
TX.DMA.START cleared
TX.DMA.ABORT cleared.
clears the MASTER.RESET bit (CSR<5>) when initialization and self-test are complete.

3.3.2
Configuration
After DHV11 self-initialization, the driver program can configure the DHV11
the LPR and LNCTRL registers.

as needed. This is done via

By writing to the associated LPR and LNCTRL the program can select data rate, character length, parity,
and stop bit length for each channel. Individual receivers and transmitters can be enabled and auto-flow
selected.

3-17

For operation with any device which uses modem-type signals, LINK.TYPE of the associated LNCTRL

NOTE

If RX.ENA is reset while a receive character is
being assembled, that character will be lost
Writing to the LPR or LNCTRL registers of any
line impacts transmission performance on every
line.
3.3.3

Transmitting

Each channel of the DHV11 can be programmed to transmit blocks of characters by DMA, or single
characters only. Such transfers are covered in the following three subsections. For data flow and timing
considerations see Chapter 4, Section 4.6.

3.3.3.1 DMA Transfers — Before setting up the transfer of a DMA buffer, the program should make
sure that TX.DMA.START is not set. TBUFFCT, TBUFFADI, and TBUFFAD?2 should not be

written unless TX.DMA.START is clear.

Transmission will start when the program sets TX.DMA.START.

The size of the DMA buffer, and its start address, can be written to TBUFFCT, TBUFFADI, anq
TBUFFAD? in any order. However, TBUFFAD2 contains TX.ENA and TX.DMA.START, soitis
probably simpler to write TBUFFAD2 last. By using byte operations on this register, TX.ENA and
TX.DMA.START can be separated.
"

The DHV11 will perform the transfer and set TX.ACTION when it is complete. If TXIE is set, the
program will be interrupted at the transmit vector. Otherwise, TX.ACTION must be polled.
TX.ACTION is not returned until the UART has completely transmitted the last character of the DMA

buffer.

‘

To abort a DMA transfer, the program must set TX.DMA.ABORT. The DHV11 will stop transmission,
and update TBUFFCT, TBUFFADI1, and TBUFFAD2<7:0> to reflect the number of characters
which have been transmitted. TX.DMA.START will be cleared. If the interrupt is enabled, TX.ACTION
will interrupt the program at the transmit vector. After the TX.ACTION has beenreturned, if the program
clears TX.DMA.ABORT and sets TX.DMA.START, the transfer can be continued without loss of
characters.

If a DMA transfer fails because of a memory error, the transmission will be terminated. TBUFFADI and
TBUFFAD?2 will point to the failing location. TBUFFCT will be cleared.

3.3.3.2 Single Character Programmed Transfers — Single characters are transferred via a channel’s
TX.CHAR register. The character and the DATA.VALID bit must be written as defined in Section
3.2.2.3. Note that the character and the DATA.VALID bit can be written by separate MOVB
instructions.

The DHVI11 returns TX.ACTION when it reads the character from TX.CHAR. As with DMA
transfers, this bit can be sensed via interrupt or by polling the CSR.
(
i

3-18

In single-character mode, TX.ACTION is returned when the DHV11 accepts the character, not when it
has been transmitted. Each channel has a 3-character buffer. Therefore, if modem status bits or line
parameters are changed immediately after the last TX.ACTION of a message, the end of the message
could be lost. The program can prevent loss by adding three null characters to the end of each singlecharacter programmed transfer message.

3.3.3.3 Methods of Control— Examples of control by polling or by the use of interrupts are given in
Section 3.4, Programming Examples.
3.3.4 Receiving
Received characters, tagged with the channel number and DATA.VALID, are placed in the FIFO buffer
(RBUF). If a character is put in an empty RBUF, the DHV11 sets RX.DATA.AVAIL. It stays set while
there is valid data in there. If RXIE is set, the program will be interrupted at the receive vector. The
program’s interrupt routine should read RBUF until DATA.VALID is reset.
NOTE
The interrupt is dynamic. It is raised as
RX.DATA.AVAIL is set after RXIE, or as RXIE
is set after RX.DATA.AVAIL. If the interrupt
routine does not empty the FIFO, RXIE must be
toggled to raise another interrupt.
If RXIE is not set the program must poll RBUF often enough to prevent data loss.

3.3.5
Interrupt Control
During an interrupt request sequence, assuming that interrupts are enabled, the DHV11 can provide two
vectors:

1.
2.

The ‘base’ vector set on the interrupt vector switches
‘Base’ vector + 4.

The base vector is supplied each time data is put into an empty FIFO.

The ‘base + 4’ vector is supplied when:
1.

A DMA block has been transferred.

2.
3.

A DMA transfer has been aborted, or terminated because of a memory error.
A single-character programmed transfer is complete.

At the two vectors, the host must provide the addresses of suitable routines to deal with the above
conditions.

3.3.6 Auto X-ON and X-OFF
X-ON and X-OFF codes are commonly used to control data flow on communications channels. To use
thlS facility, interfaces must have suitable decoding hardware or software.
A channel which receives an X-OFF stops sending characters until it receives an X-ON. A channel which
is becoming overrun by received data sends an X-OFF. It sends an X-ON when the congestion is relieved.

3-19

If the DHV11 is programmed for automatic flow control (auto-flow), it can automatically control the flow
of characters. Three bits control this function:
1.
2.
3.

IAUTO
FORCE.XOFF
OAUTO

LNCTRLL1>
LNCTRL<5>
LNCTRL<4>

IAUTO and FORCE.XOFF both control incoming characters. IAUTO is an enable bit which allows the
state of the FIFO counters to control the generation of XOFF and XON codes. The FORCE.XOFF bit
is a direct command from the program.

The DHVI11 hardware recognizes when the FIFO is three-quarters full and half full. The
firmware uses these states for auto-flow control.

Tf the program sets a channel’s IAUTO bit, the DHV11 will send that channel an X-OFF ifit
receives a character after the FIFO becomes three-quarters full. If the channel does not respond
to X-OFF, the DHV11 will send an X-OFF in response to every alternate character received.
An X-ON will be sent when the FIFO becomes less than half full, unless FORCE.XOFF for
that channel is set. X-ONs are only sent to channels to which an X-OFF has been sent.
By inserting X-ON and X-OFF characters into the data stream, the program can perform flow
control directly. However, if the DHVI11 is in the IAUTO mode, the results will be
unpredictable.

InIAUTO mode, if RX.ENA is set, X-ONs and X-OFFs will be transmitted even if TX.ENA

is cleared.

When FORCE.XOFF is set, the DHV11 sends an X-OFF and then acts as if IAUTO is set
and the FIFO is critical (was three-quarters full, and is not yet less than half full). When
FORCE.XOFTF is reset, an X-ON will be sent unless the FIFO is critical and IAUTO is set.

If the program sets OAUTO, the DHV11 will automatically respond to X-ON and X-OFF
characters from the channel. It does this by clearing and setting the TX.ENA bit.

The program may also control the TX.ENA bit, so in this case it is important to keep track of
received X-ON AND X-OFF characters.

Received X-ON and X-OFF characters will always be reported via the FIFO. It is possible
during read/modify/write operations by the program, for the DHV11 to change the TX.ENA
bit between the read and the write action. For this reason, if DMA transfers are started while
OAUTO is set, it is advisable to write to the low byte of TBUFFAD?2 only.
NOTES

The DHVI1I may change the state of TX.ENA
for up to 20 microseconds after OAUTO is
cleared by the program.

When checking for flow-control characters,
the DHV11 only checks characters which do
not contain transmission errors. The parity
bit is stripped and the remaining bits are

checked for X-ON (21;) and X-OFF (23g)
codes.

3-20

Further information on automatic flow control for the DHV11 is contained in Appendix D.
3.3.7

Error Indication

The program is informed of transmission and reception errors by means of four bits:

1.
2.
3.

TX.DMA.ERR
PARITY.ERR
FRAME.ERR

OVERRUN.ERR

—
-

CSR<12>. See Section 3.2.2.1
RBUF<12>. See Section 3.2.2.2
RBUF <13>. See Section 3.2.2.2

RBUF <14>. See Section 3.2.2.2.

RBUF<14:12> are also used to identify a diagnostic or modem status code.
3.3.8

Modem Control

Each channel of the module provides modem control bits for RTS and DTR. Also on each channel are
modem status inputs CTS, DSR, RI, and DCD. These bits can be used for modem control or as general
purpose outputs and inputs (see STAT register, Section 3.2.2.5).

CTS, DSR, and DCD are sampled by PROC2 every 10 ms. Therefore, for a change to be detected, these
bits must stay steady for at least 10 ms after a change. Rl is also sampled every 10 ms, but a change is not
reported unless the new state is held for three consecutive samples. There are no hardware controls
between the modem control logic and the receiver and transmitter logic. Any coordination should be done
under program control. Modem status change reports are placed in the received character FIFO at the
correct position relative to the received characters.

By setting LINK. TYPE (LNCTRL<8>>), a channel can be selected for modem operation. Any change of

the modem status inputs will be reported to the program via the received character FIFO. Modem control
bits must be driven by the program’s communication routines. Control bits are written to LNCTRL.
Appendix B gives more detail of modem control.

By clearing LINK.TYPE the channel is selected as a ‘data lines only’ channel. Modem control and status
bits can still be managed by the program but status bits must be polled at the line status register. Changes of
modem status will not be reported to the program.

NOTE

When transmitting by the single-character
programmed transfer method, up to three
characters can be buffered in DHV11 hardware.
If modem control bits are to be changed at the end
of a transmission, three null characters should be
added. When TX.ACTION is set after the third
null character, the last true character has left the
UART.

Status change reporting is done via the FIFO as follows:
e

When OVERRUN.ERR, FRAME, ERR, and PARITY.ERR are all set, the eight low-order
bits contain either status change or diagnostic information. In this case:

If RBUF<0> = 0, RBUF<7:1> holds STAT<15:9> (see Section 3.2.2.5).

IfRBUF<0> = 1, RBUF<7:1> holds diagnostic information (see Section 3.3.10).

3-21

3.3.9

Maintenance Programming

As well as using on-board and external diagnostic programs, the host can also test each channel directly.
Bits 7 and 6 of LNCTRL allow each channel to be configured in normal, automatic echo, local loopback,
and remote loopback modes (see LNCTRL Section 3.2.2.6).
The host must provide suitable software to test these configurations.
3.3.10

Diagnostic Codes

3.3.10.1 Self-Test Diagnostic Codes — After bus reset or master.reset, the DHV11 executes a self-test
and initialization sequence. At the end of the sequence, eight diagnostic codes are put in the FIFO.

RX.DATA.AVAIL is set and MASTER.RESET is cleared.

After an error-free test, DIAG.FAIL will be reset. The ‘diagnostic passed’ LED will be on. If an error is
detected, DIAG.FAIL will be set and the LED will be off.

An example program which reads and checks the diagnostic codes from RBUF, is included in Section 3.4.
3.3.10.2 Interpretation of Self-Test Codes — The high byte of diagnostic codes in RBUF can be
interpreted as in Section 3.2.2.2, except that bits <11:8> are not the line number. They indicate the
sequence of the diagnostic byte. That is to say, 0 = first byte, 1 = second byte, and so on.

Figure 3-2 shows how the diagnostic code in the low byte of RBUF, should be interpreted. Table 3-3 gives

the meaning of each implemented diagnostic byte.

DIAGNOSTIC STATUS BYTE
0 = MODEM STATUS CODE
1 = DIAGNOSTIC CODE
IF D7 =1, THEN:

0 = PROC1 SPECIFIC ERRORS IN D4— D2
1 = PROC2 SPECIFIC ERRORS IN D4—D2

IF D7 = 1, THEN:

— O = SELF-TEST CODE IN D5—D1
——— 1 = BMP CODE IN D5—D1
—— 0 = ROM VERSION IN D6—D2, D1 IS THE PROC No.
— 1 = DIAGNOSTIC CODE IN D6—D1
AD1163

Figure 3-2

Diagnostic/Status Byte

3-22

Table 3-3
Code

DHVI1I1 Self-Test Error Codes

Test

(Octal)
201
203
211
213
217
225
227
231
233
235
237

Self-test null code (used as a filler)
Self-test skipped
Basic data path error from PROC2
Undefined UART error
Received character FIFO, logic error
PROC1 to common RAM error
PROC?2 to common RAM error
PROCI1 internal RAM error
PROC?2 internal RAM error
PROCI1 ROM error
PROC2 ROM error

If D7 = 0 and DO = 1, ROM version number is in D6 — D2.
D1 = PROC number (0 = PROC1)
NOTE

Codes not shown in this table indicate undefined

errors.

After self-test, the eight codes in the FIFO will consist of six diagnostic codes and two ROM version
codes. If there are less than six errors to report, null codes (201g) fill the unused places.
After an error-free test, six null codes and two ROM version codes will be returned.
If self-test is skipped (see next section), six 203g codes and two ROM version codes will be returned.

3.3.10.3
Skipping Self-Test — Self-test takes up to 2.5 seconds to complete. Depending on system
software, this may cause a 2.5-second hangup. The Skip Self-Test facility allows the program to bypass
the self-test diagnostic.
'

Skipping self-test is done as follows:
1.

The program resets the DHV11

The diagnostic firmware writes 125252g throughout the common RAM within eight
milliseconds (ms) of reset

The program waits 10 ms (+ or— 1 ms) after issuing reset. It then writes 052525 gthroughout the
control registers (not the CSR), within the next 4 ms

3-23

The diagnostic firmware waits until 16 ms after reset. It then checks for a 0525254 code in
common RAM.

If it finds the code, self-test is skipped. The DIAG.FAIL bit is cleared and control is passed to

the communications firmware which starts initialization.
If the code is not found, self-test starts.

NOTE
The program must not write to the CSR or the
control registers during the period starting 15 ms
after reset and ending when the MASTER.RESET
bit is cleared. This could cause a diagnostic fail
condition.

3.3.10.4

Background Monitor Program(BMP) — When not busy with other tasks, the DHV11’s

microcomputers perform background tests on the option. This is done by checking the timer-generated
interrupts used by the firmware (one interrupt in PROCI1 and two in PROC2). One of two codes is
returned to the FIFO:
305¢
3073

—
—

DHVI1I1 running
DHVI1 defective.

A single diagnostic word is returned via the FIFO. The low byte contains the diagnostic code. In the high
byte, OVERRUN.ERR, FRAME.ERR, and PARITY.ERR are all set to indicate that bits<7:0> do not
hold a normal character. The line number (RBUF<11:8>) = 0.
If PROC2 stops running, PROCI1 will set DIAG.FAIL and will turn off the LED. The LED will stay off,
even if the fault clears. If PROCI stops running, PROC2 will load a 307 code into the FIFO.

Normally, the BMP will only report when it finds an error. However, if the program suspects that the
DHYV11 is not working it can get a BMP report at any time. This is done by setting DIAG (LPR <2:1>) of
any channel to 01. The line number returned is that of the LPR used to request the report.
On completion of the check, the BMP will clear the 01 code in DIAG. The host should not write to the
LPR of that channel until DIAG has been cleared.

34 PROGRAMMING EXAMPLES
This section contains programming examples. They are not given as the only method of driving the option.
These programs are not guaranteed or supported.
3.4.1
Resetting the DHV11
In the following example:

DIAG is a routine to check the diagnostic codes. It returns with CARRY set if it detects an

Theloop at 18 can take up to 2.5 seconds, so the programmer could poll via a timer or poll at

error code (see Section 3.3.10).

interrupt level zero.

3-24

CORRECTLY.
-~

NOTE:

A SOPHISTICATED PROGRAM WOULD TIME
IF THE RESET DID NOT COMPLETE.

OUT

AFTER

SECONDS

we
we
—e

A ROUTINE T0 RESET THE DHV11l AND CHECK THAT IT IS FUNCTIONING

DHVRES::

MOV
1$:
:

#490,@#DHVCSR

BIT
BNE
BIT

#40, @#DHVCSR
18
#20000,@¥DHVCSR

BNE

DIAGER

‘

28:

we
W

SET MASTER.RESET AND
CLEAR

;i
;
;

WAIT FOR MASTER.RESET TO
CLEAR.
CHECK THE DIAGNOSTICS FAIL

;

BIT.

;
;

NOTE:

INTERRUPT

ENABLES.

TEST INSTRUCTION IS
OK BECAUSE THERE ARE

p
MOV

#8.,R5

;
;
;

TEST

MOV

Q#RBUFF, R0

;

GET NEXT DIAGNOSTIC CODE,

;
;

PROCESS IT.
CARRY SET -

;

JSR
BCS

- PC,DIAG
DIAGER

PROCESS

NO TX.ACTS
THE EIGHT

PENDING.
SELF

CODES.

MUST

HAVE

SOB

R5,2$

;

GO BACK

RTS

;

RETURN

FOR NEXT CODE.
-

CARD

RESET.

DHV11 HAS FAILED TO RESET PROPERLY, SO HALT AND WAIT FOR
THE

FIELD

SERVICE

DIAGER:

ENGINEER.

HALT
BR

DIAGER

3.4.2 Configuration
This routine sets the characteristics of channel 1 as follows:
SNhwh=

Transmit and receive at 300 bits/s
Seven data bits with even parity and one stop bit
Transmitters and receivers enabled
No modem control
No automatic flow control.
i
i

SET

CHARACTERISTICS

CHANNEL

TO THE

FOLLOWING

STATE:-

i
i

;

TRANSMIT

;

TRANSMITTERS AND

;

NO MODEM CONTROL.

NO AUTOMATIC

;

DATA

AND

RECEIVE

BITS WITH

EVEN

304

B.P.S.

PARITY

AND

RECEIVERS

FLOW CONTROL.

3-25

BEEN

ERROR.

;
;

ONE

ENABLED.

STOP

BIT.

SETUP::

’

MoV

SELECT

INTERESTED

DATA

PARITY

#4,@#LNCTRL
$#200,@4#TBFAD2+1

ENABLE

MOV B

#1,@#DHVCSR

ENABLE

RTS

;

RETURN

#052560,Q#LPR

Mov

MOV

3.4.3

THE

LINE

RATE,

IN.

STOP

WE'RE
BITS,

AND
THE

RECEIVER.

THE

TRANSMITTER.

LENGTH

CHANNEL

DONE.

Transmitting

3.4.3.1 Single Character Programmed Transfer — This is a program to send a message on channel 1.
The message (MESS) is an ASCII string with a null character as terminator.
Polling is used but a TX.ACTION interrupt could also be used.

This program would function on a DHV11 with only this channel active. Otherwise it would lose

MODE.

ROUTINE

WRITE

MESSAGE

CHANNEL

USING

SINGLE

CHARACTER

TX.ACTION reports of other channels. However, a program to control all channels would be too big to
use as an example.

MOVB

(RO)+,@4#TXCHAR

MOVB

MOV

;gflfl,@#TXCHAR+l

POINT
MOVE

BEQ

#MESS,
R0

MOV

18:

POINT

#1,@4DHVCSR

MOV

SINGOT::
TO

TALK
TO

BIC

#176377,R1

ISOLATE

CMP
BNE

#000409,R1
2%

RTS

’

+ASCIZ

WISH

MESSAGE.

CHARACTER

WAIT

TRANSMIT

BUFFER

GO RETURN IF ALL CHARACTERS GONE.
SET DATA VALID BIT TO START.

@#DHVCSR,R1

BPL

CHANNEL

TO.

FOR

IGNORE

TX.ACT

CHANNEL
THE

NUMBER.

TX.ACT

ITS

NOT OURS (SHOULDN'T HAPPEN)
GO BACK FOR NEXT CHARACTER.,

38:

SINGLE

CHARACTER

MESSAGE

SENT.

FOR CHANNEL

.EVEN

3-26

MESS:

DMA Transfer —

THIS PROGRAM SENDS A MESSAGE OUT ON EACH LINE OF THE DHV11 AND

3.4.3.2

HALTS

MACHINE

WHEN

ALL

TRANSMISSIONS

HAVE

COMPLETED.

THE MESSAGES ARE TRANSMITTED USING DMA MODE,

wms

THE

USED

SIGNAL

TRANSMISSION

AND INTERRUPTS ARE

COMPLETION.

Rl,@#DHVCSR

#DMASIZ, @#TBFCNT

MOVB

MOV

EIGHT

#8.,R0

CLR

START

MOV

SET UP THE INTERRUPT VECTORS.
INTERRUPT PRIORITY FOUR.

SELECT

#TXINT,
@4 TXVECT

#200,@#TXPSW

SET

LENGTH

MOV

SET

LOWER

DMAINT::

START

LINES

LINE

START.

ZERO.

1$:

CLR

MOVB

#1909 ,@#DHVCSR+1

CMP

#8.,R5
28

BNE

BITS

ARE

POINT

REPEAT

2$:

RG,1$

ENABLED

INC
SoB

BANK.

MESSAGE.

ADDRESS

BITS.

TRANSMITTER

(ASSUME

UPPER

ADDRESS

ZERO).
NEXT

CHANNEL.

FOR

ALL

LINES.

USED

INTERRUPT

ENABLE

WAIT

DMA WITH

#100200,@%TBFAD2

#DMAMES,
@4 TBFAD]

MOV

THE

TRANSMITTER

FOR ALL

LINES

ROUTINE.

INTERRUPTS.

FINISH.

38$:
HALT

ALL

DONE,

STOP.

TRANSMITTER

INTERRUPT

ROUTINE.

INCREMENTED AS

EACH

LINE

COMPLETES.

INC

BIT

GET

BNE

R0
@4#DHVCSR,
$#10000,R0
43

MOV

CHECK

TXINT::

LINE
HALT

FLAG

NUMBER

FOR

THAT

DMA

MEMORY
ANOTHER

RTI

4$:
~

HALT

MEMORY

DMAMES:

.ASCII

<15><12><7><7><7>/SYSTEM CLOSING

DMASIZ

.~DMAMES

+.EVEN

3-27

PROBLEM

DOWN

FINISHED

LINE.

FAILURE,

NOW/

PROBLEM.
LINE

HAS

FINISHED.

Aborting a DMA Transfer -

THIS

SPECIFIED

wme

3.4.3.3

ROUTINE

THAT

CALLED

LINE.

ARE

TO ABORT
ROUTINE

OTHER

DMA

MAKES

TRANSFERS

TRANSFER

THE

(RATHER

PROGRESS

RASH)

ASSUMPTION

PROGRESS.

THERE

THIS

ENTRY,

CONTAINS

THE

NUMBER

THE

LINE

ABORTED.

R@, @4DHVCSR

BIS

#1,@$LNCTRL

MOV

@$#DHVCSR, R1

BPL

WAIT

THE

;

CHECK

ITS

OUR

DMA

FOR

#177769,R1

CMP

R@,R1

BNE

CHANNEL

ABORT

THE

ABORTED.

BIT.

TX.ACT

#1,Q@#LNCTRL

LINE,

;

IGNORE

;

ASSUMPTION

;

CLEAR DOWN THE ABORT FLAG

;

FOR

RTS

BUFFER

THE

WHERE

DMA

ITS

WAS

NOT

(OUR

WRONG!)

TIME.

COMPLETELY

ABORTED,

REGISTERS

REFLECT

THE

DHV11

GOT

TO.

Ne
we

Receiving

THIS
IF

THE

SWAB

BIC

ROUTINE

XQFF

PROCESSES

RECEIVED

RECEIVED,

CHARACTERS

THETRANSMITTER

OFF. IF AN XON IS RECEIVED, THE
OTHER CHARACTERS ARE IGNORED.

FOR

TRANSMITTER

UNDER
THAT

INTERRUPT CONTROL.
CHANNEL IS TURNED

TURNED

BACK

ON.

ALL

USE

THE

JUST

EXAMPLE,

AUTOMATIC

A BETTER
CAPABILITIES OF

WAY
THE

TO PERFORM
DHV1l.

FLOW CONTROL

THIS

SET

BIC

3.4.4

POINT

1§z

MOV

DMABQT::

RXAUTO:
:

;

SET

#200,Q§RXPSW

;

PRIORITY

THE

#8.,R0

;

ENABLE

CLR

;

STARTING

MOVB

R1l,@#DHVCSR
#4,@#LNCTRL

SELECT THE

BIS

;

ENABLE

INC

;

SET

SOB

RG,1$

MOVB

#100,@#DHVCSR

ENABLE

THE

RTS

RETURN

ROUTINE

THE

MAIN

TASK.

INTERRUPT

3-28

INTERRUPT

LEVEL

MoV

1$:

#RXINT, @¥RXVECT

MOV

ALL
AT

THIS

POINTER

THE

VECTORS.

FOUR.
RECEIVERS,

CHANNEL

ZERO,

LINE.
RECEIVER.,
TO

RECEIVER

INTERRUPTS

CHANNEL.

INTERRUPTS.
DO

THE

RESET.

SAVE

GET

RO,
- (SP)

wme

MOV

CHECK

RXINT::

DIAGNOSTICS

CALLERS

REGISTERS.

RXNXTC:

MOV

@#RBUFF,
R0

BPL

RXIEND

MOV

R@,-(SP)

#197777,
(SP) +

BNE

RXNXTC

BIC

$170200,R0

SWAB

BIS

#100,R0

MOVB

RO ,@#DHVCSR

SWAB

CMPB

$21,R0

we
we
~e
W,

BISB

#200,Q4TBFAD2+1

ENABLE

RXNXTC

INTERRUPT

BITS.

CHARACTERS

LINE.

ENABLE

BACK

BIT.)

LOWER

BYTE.

"XON"?

CHECK
THE

CHECK

FOR

"XOFF"

TRANSMITTER.

FOR

CHARACTERS.

WAS IT AN "XOFF"?
NO -

GO CHECK

BICB

#200,@4#TBFAD2+1

DISABLE

RXNXTC

#23,R0

BNE

THIS

CHARACTER

THEM.

UNNECESSARY

MOV

(SP)+,RP

CMPB

CODES.

IGNORE

THE

PUT

18:

AND

(ADD

;

FINISHED.

MODEM

WE'VE

ERRORS,

POINT

WAS

BNE

VALID,

FOR

REMOVE

/
s

CHARACTER.

DATA

JUST

—e

BIC

THE

RESTORE

THE

CHECK

FOR MORE

CHARACTERS.

TRANSMITTER.

FOR

CHARACTERS.

RXIEND:
THE

DESTROYED

RTI

3.4.5

Auto X-ON and X-OFF
PROGRAM

HALTS

THE

SENDS

MACHINE

MESSAGE

WHEN

ALL

OUT

EACH

LINE

TRANSMISSIONS

HAVE

COMPLETED.

THE

DHV1l1l

AND

USED

MESSAGES
TO

ARE

SIGNAL

TRANSMITTED

TRANSMISSION

USING

DMA

MODE,

AND

INTERRUPTS

ARE

COMPLETION.

LYW

THE

TRE

THIS

AUTOMATIC

FLOW

CONTROL

ENABLED

THE

OUTGOING

DATA.

MOV

#ATOINT,@4#TXVECT

SET

MOV

$200,Q4#TXPSW

TXAUTO:
:

INTERRUPT

INC

SOB

RG,1$

CLR

MOVB

$100,@4DHVCSR+1

we
“s
e
we
N
We

#AUTOM
@4 TBFAD1
S,
$#100200,@$TBFAD2

ON
SET

LENGTH

MOV

ENABLE

SET

LOWER

#AUTOSZ ,@#TBFCNT

SELECT

START

THE

LINE

START.

THE

TRANSMITTED

ENABLED
ARE
TO

POINT

REPEAT

ENABLE

BANK.
CONTROL

FLOW

DATA.

MESSAGE.

ADDRESS

DMA WITH

BITS

VECTORS.

FOUR.

ZERO.

AUTOMATIC

MOV

LINES
AT

$24,@#LNCTRL

Rl,@#DHVCSR

BIS

INTERRUPT

PRIORITY

EIGHT

MOVB

1$:

THE

START

#8.,R0
R1

MOV
CLR

BITS.

TRANSMITTER

(ASSUME

UPPER

ADDRESS

ZERO).
NEXT

CHANNEL,

FOR

ALL

LINES.

USED

INTERRUPT

TRANSMITTER

ROUTINE.

INTERRUPTS.

25
CMP

$8.,R5

BNE

35:

’

HALT

e we Ne_
e me

FOR

ALL

LINES

ALL

DONE,

STOP.

FINISH.

TRANSMITTER
R5

WAIT

INTERRUPT

INCREMENTED

ROUTINE.
EACH

LINE

COMPLETES.

ATOINT::

MOV
BIT
BNE

@#DHVCSR,
RO
$#10000,R0
43

GET

INC

FLAG

LINE

CHECK
GO

NUMBER

FOR

HALT

THAT

DMA

FINISHED

LINE.

FAILURE.

MEMORY

PROBLEM.

ANOTHER

LINE

HAS

FINISHED.

RTI

45:

)
HALT

’

MEMORY

PROBLEM

AUTOMS:

.ASCII

<15><12><7><7><7>/SYSTEM CLOSING DOWN NOW/

AUTOSZ

.~AUTOMS

.EVEN

Checking Diagnostic Codes

THIS

ROUTINE

CHECKS

THE

DIAGNOSTICS

CODES

RETURNED

FROM

THE

DHV1l.

ENTRY,

CONTAINS

THE CHARACTER

RECEIVED

FROM THE

DHV11l.

ON EXIT, THE CARRY BIT WILL BE CLEAR FOR SUCCESS, SET FOR FAILURE.

—e

3.4.6

DIAG::

#197776,R0
$070001,R0

BNE

DIAGEX

MOV

BIC
CMP

SAVE

R@,-(SP)

CHECK

MOV

NOT,

JUST

EXIT

(SP) ,RO

GET

THE

CODE

BACK.

BITB

#200,R0O

CHECK

FOR

BEQ

DIAGEX

CMPB
BEQ

#201,R0
DIAGEX

SELF

TEST

CMPB

#203,R0

SELF TEST

BEQ

DIAGEX
DHV

SEC
BR

DIAGXX

3-30

FOR

IT'S

LATER.

A DIAG.

NULL

CODE.

NORMALLY.

ROM VERSION

NUMBER.
;

CODE.

SKIPPED CODE.

RUNNING

CODE.

DIAGEX

THAT

ALL

THE

#305,R0

BEQ

CODE

ERROR

CODE

CMPB

THE

REST

SET

THE

CARRY

ARE
WAS

ERROR

CODES.

RECEIVED,

FLAG.

]

CLC

DIAGXX:

(SP) +,R0
PC

EVERYTHING

;

RESTORE

OK,

THE

CLEAR

CARRY.

CHARACTER/INFO.

Modem Control

ROUTINE

HANG

THIS

3.4.7

MOV
RTS

DIAGEX:

THE

WILL

ANSWER

MODEM

CALL,

OUT

MESSAGE

AND

PHONE,

MESSAGE

INTERNAL

WOULD

NEED

BUFFERING

TO
OF

PADDED

THE

DHV11,

OUT

WITH

THREE

NULLS

DUE

THE

DMA MODE IS USED. IF SINGLED CHARACTER MODE WERE USED, THEN

MODEM:
:
MOV

#8.,R0

CLR

MOVB

R1,@#DHVCSR

MOVB

#125,@#LPR+1
#400, @#LNCTRL

SET

ALL

CHANNELS

FOR

MODEMS.

#MRXINT, @#RXVECT
#200, @#RXPSW

MOV

T
, @¥TXVECT
#MTXIN

MOV

“e

MOV

R#,1$

SET

INC
SOB

30@

POINT

MOV

POINT

SET

ALL

18
TO

SET

INTERRUPT

MODEM

DATA

DISABLE
NEXT

RECEIVER,

CHANNELS.

VECTORS.

INTERRUPTS.

ENABLE

LET

UP,

CHANNEL,

LEVEL

#200,@#TXPSW
#40100,@#DHVCSR

SET

RATE.

(INTERRUPT

MoV

MOV

CHANNEL

BPS

THE

FOUR)

28
INTERRUPT

ROUTINES

EVERYTHING

TRANSMITTER

INTERRUPT

ROUTINE.

MTXINT:
MOV

RO,-(SP)

MOV

@#DHVCSR,RO

GET

SWAB

SELECT

BIC

(RETAIN

SAVE

THE

BIS

#177760,R0
#100,R0

MOVB

RO, @#DHVCSR

MOV

#400,@#LNCTRL

DROP

MOV

(SP)+,R0

RESTORE

RTI

3-31

INTERRUPTING

THIS

CHANNELS

INTERRUPT

DTR,

RTS

THE

WE
LINE

AND

USE.
NUMBER.
REGISTERS.

ENABLE)
CLEAR

ABORT.
USED.,

we
we

INTERRUPT

ROUTINE.

RECEIVER

MRXINT::
-e

MOV

@#RBUFF,RO

GET

BPL

MRXEND

SAVE

RO,~-(SP)

EXIT

MOV

RO, -(SP)

BIC
CMP

#107776,R0
#070000,R0

MOV

THE

USE.

MRXLOP:

INTERRUPTING

SAVE

FOR

FOR MODEM

SKIP

(SP),RO

SWAB
BIC

BIS
MOVB

#100,R0
RO, @#DHVCSR

(RETAIN

MOV

(SP),RO

CHECK

BIC

#177547,R0
#230,R0

MRXNXT

INFO.

FOR

THIS

LINE.

FOR

TRANSMISSION.

ASSERT
WERE

DSR, DCD & CTS NOT SET, TRY START.
CLEAR DOWN ABORT BIT (IN CASE WE
SET IT WITHOUT A DMA IN PROGRESS).
RTS

MOV

#100200,@#TBFAD2

MRXNXT

BIT

#200,R0
28

CHECK

BEQ

MOVB

#23,@#LNCTRL+1

OUTPUT MESSAGE.
(TRANSMITTER
CLEARS DOWN

ASSERT

MRXNXT

CASE

ASSERTED

#NOSYSZ ,@#TBFCNT
#NOSYS, @#TBFAD1

READY

#23,@#LNCTRL+1

FOR

MOVB

ENABLE)

INTERRUPT

#1,@#LNCTRL

MOV

USE.

#177760,R0

BIC

MOV

LATER

IF NOT.
SELECT REGISTERS

BNE

LINE.

DONE..

TEST

MOV

CMP

ALL

LOOK

CTS

THE

AND

SAME

ROUTINE

INTERRUPT
THE

DSR
TIME.

CALL.)

FOR MORE.

16:

BISB

#1,@#LNCTRL
#1,@#LNCTRL+1

MOVB

ASSERT

ABORT

ANY

DROP

MODEM

CALL.

FOR
GO

RING

INDICATOR.

CLOSEDOWN

CALL.

DTR.

LOOK

FOR MORE.
CURRENT

DMA

TRANSFERS.

SIGNALS.

MRXNXT:
TST

(SpP)+

REMOVE

MRXLOP

MOV

(SP)+,RO0

MRXNXT

CHECK

3$:

NEW

FOR MORE.

#3,@#LNCTRL+1

LOOK

FOR

RTS.

MOVB

DSR.

CHECK

#40,(SP)
33

FOR
GO

BIT
BEQ

SIGNALS

ROUND

FROM

THE

STACK.

USED.

AGAIN,

MRXEND:
RESTORE

THE

RTI

NOSYS:

+ASCII

<15><12><7><7><7>/SYSTEM

NOSYSZ

.—NOSYS

.EVEN

3-32

UNAVAILABLE,

PLEASE

TRY

LATER/

CHAPTER 4
TECHNICAL DESCRIPTION

4.1
SCOPE
This chapter describes:
Operation of the main hardware blocks
Data flow
Control of address and data
Operation of the microcomputers
Use and control of the RAM
Internal diagnostics.

The chapter starts with a descrlptlon at block diagram level. Thisis followed by a section on data flow, and
then specific areas are described in more detail. A basic description of the DHV11’s ROM based
diagnostics completes the chapter.
It is assumed that the reader has read Chapter 3, Sections 1, 2, and 3 of this document.
Refer to Figure 4-1 throughout this description.

42 Q-BUS INTERFACE
Thesimplified block of the Q-bus interfacein Figure 1-5is expandedin Figure 4-1. The interfaceis made
up of all the components between the external and internal buses.
DCO005 bus transceivers control the address and data lines BDAL<17:0> and BAL<21:18>. Bus
transceivers also:

1.
2.

Recognize device addresses
Provide vectors during interrupt sequences.

When (1) the DHVI11 is bus slave, access to the DHV11 is allowed when BBS7 is asserted (I/O
operation) and BDAL<12:4> ‘matches’ the address on the module address switches. By this means, the
DHV11 recognizes a valid device register address. Transceiver directionis controlled by BDIN and
BDOUT, which indirectly generate XMIT.H and REC.H. The ‘match’ condition generates the signal
MATCH
In an interrupt acknowledge cycle (2), the DC003 interrupt IC responds to BIAKI. The signal VECTOR
enables the vector switches onto the BDAL lines via the DC005s. VECT.2.H
is the low bit of the vector
address. It identifies a receive (0) or transmit (1) interrupt vector. VECTOR also generates BRPLY via
DCO004 protocol logic.

REQ

}

BDMGI

. oaTin

BDMGO

bcoto

|—

BINIT

OMA

—=wmasTer|

BOMR

CONTROL

BRLY

BSYNC

DaTIO.

[~ ADREN

AD<15 =

VECTOR

SWITCHES

‘

= <:>

ki2i1e 10>

BDAL

5<1514a13>
@

ocoos

ooos

FK——
2

owos

BAL

16>

» 1€19.18,3 & 2>

]

IND<3:0>
:

I
<

——

ADDRESS

—

ATCH
YXMIT.H

5 [ERRON

REC.H

DCO04

BDIN

PROTOCOL | VECTOR

LOGIC

|oourie

AD<2:0>|

INDIRECT

ADDRESS

[

LATCH

VECTOR
o
Ve

AD5

‘

DCO03

.._'}

LOGIC

'—}A PORT B__TX ACTION (P1108.L)

INTERRUPT

Jo—

PORTA

¢¢

—_——

LATCHE

)

- /
o [<13:8>
]
%

r
|

FIFO
_l_
|controL
|

_—> =]

& <6:0>

[sDAT 14

( FIFO NOT EMP
MPTY)

|
wiw|
wlw

MRES

RX.DATA. AVAIL

|sparais

BIAKI

L— -

—

TX
setion

—

BIRQ
BINIT

I oUTPUT

Z
é
%

I
|

A<15:8>|

-l
CSR STROBE I

‘

AD15'

NEg

K
-

[——

. [ ap<3:0>T | ReEGISTER

2
ENlenwo
| OUTHE | | |2

BDOUT

l CsR

D<15:8>

e
|

-~ ;

—_— e

SELO

A<T7:0>

<15:8>

Ab<is:0>

o118
)&

AD
|mem

D<7:0> | neuT
LATCH

AD<7:0>

ADT6

|Latches|

X 8
-

AD17

BRPLY

| ADREN
z
[l ®
\
WE

2
&3

:;\:/TNBJ

BITS

DMA

—

ADDRESS| _

l L- — _l

8
BAL
ST
gi12017¢

DCO0S

| |

bCoos

—

9 & 8=00|

s S Go—

<654 & 0>

BDAL

16> :-;-

]

<:>TRANSCEIVERQ
<987 & 1>

]

—

|aTcHES

VECTOR

DMA DATA|

C: N

—

——/

| |" ] |:

8> | %

ADDR
SWITCHES

)

{(FROM PROC1)

P1AD<7:0> & P1A<15:8>

I | =
3

_
AD<7:0>

‘——>DIN
BOUT

ESS

BDAL

REQ

LATCH

[=]

K
REINI

MODULE

BDAL , |sus

—

1 5

6 MHz

Bss7L

ADL7:
o>

——» DATEN

DMA REQ
—

TER

MAS
—] LATCH
RESET

BIAKO

INITO

TXIE
RXIE
_—

Figure 4-1

DHYV11 Block Diagram

—

DMA REQ

AD'<7_ 1
g\

|| 13| T TM
——

sbao

| 1[F]

[

| | @

8> |

| 21|

| |

|
AD<21

I L
- J

a6 [ ] |
<

—

L —_— _J

g‘:

AD16

J <

c—

]

A<15:8>| R :

AD15

|
|

ACTION

LATCH

ADS

<6:0

(FIFO NOT EMPTY)

Sk MRES 7& |SDAT' 15
:

wlwl

—{ masTER
RESET

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When the bus transceivers recognize a valid device register address, the DC004 is enabled. MATCH
allows BDIN or BDOUT to generate BRPLY. The external bus signals are decoded by the DC004 which

generates the following as necessary:

INWD
OUTLB
OUTHB

—
—
-

Word transfer, DHV11 to the bus master
Low byte (AD<7:0>) transfer, bus master to DHV11
High byte (AD<15:8>>) transfer, bus master to DHV11.

Both OUTHB and OUTLB are generated to transfer a word to DHV11.
The DCO04 also decodes the low address lines to generate a number of register select

SELO is the signal which selects the CSR.

(SEL) signals.

If a condition which needs interrupt service occurs, the DC003 interrupt logic interrupts the host (BIRQ).

When the acknowledge signal (BIAKI) is returned, VECTOR and VECT.2 are generated as previously
described. BIAKO provides bus grant continuity.
BINIT is the bus initialize signal. It resets the DHV11 to a known state.
The DCO10 is a DMA controller used by the DHV11 to perform a DMA transfer. A hardware DMA
request enables the IC, which then makes a request via BDMR (bus DMA request) for control of the bus.

The DCO10 provides the appropriate bus-control signals to transfer a word of data to DHV11. After each
transfer the bus is released. Another DMA request is needed for the transfer of the next word. DMA data
does not pass through the DCO010.

Figures 4-2 and 4-3 show the DATI (INWD), DATOB (OUTLB or OUTHB), and DATO (OUTLB
and OUTHB) handshake sequences. In each case the DHV11 is bus slave.

Figure 4-4 shows an interrupt request/acknowledge sequence which requests the host processor to read an
interrupt vector from the DHV11. This sequence is followed by a DATI operation which transfers the

vector.

In Figure 4-5, a DMA request/grant sequence is shown. Note that when bus grant (BDMGO) is received,
the DCO10 becomes bus master. It generates the signals for an INWD transfer from system memory to the
DMA data latches.

NOTE

A DATIO or DATIOB sequence is made up of a
DATI followed by DATO or DATOB.
NOTE

On Q-bus systems, BDAL<17:16> are used to
provide data parity information to the bus master.
To prevent the DHV11 from generating false
parity information, AD<17:16> are only enabled
onto the BDALSs when the DHV11 is bus master.
ADREN from the DMA controller performs the
enable function.
A description of DC003, DC004, DCO005, and DCO010 is included in Appendix A.

4-3

BUS MASTER

LAVE

(MEMORY OR DEVICE)

{PROCESSOR OR DEVICE)
ADDRESS DEVICE MEMORY
* ASSERT 8DAL <{7:00>

LWITH

ADDRESS AND

ASSERT BBS7 IF THE ADDRESS
IS IN THE IO PAGE
ASSERT BSYNC L
—_—
—_—

—

DECODE ADDKRESS
*

STORE"DEVICE SELECTED”

OPERATION

REQUEST DATA

"--

« REMOVE THE ADDRESS FROM

> L AND NEGATE BBS7
BDAL <17:00
L

——

* ASSERT BDIN L

T—

INPUT DATA

PLACE DATA ON BDAL < 15:00> L

-+ ASSERT BRPLY L

« PLACE PARITY INFO ON BDAL<17:16>L

e —
o

TERMINATE INPUT TRANSFER

« ACCEPT DATA AND RESPOND
BY NEGATING BDIN L

—
—

TERMINATE BUS CYCLE
* NEGATE BSYNC L

T—

— —

-—

Figure 4-2

OPERATION COMPLETED
s NEGATE BRPLY L

DATI Bus Cycle

SLAVE
(MEMORY OR DEVICE)

BUS MASTER
(PROCESSOR OR DEVICE)}
ADDRESS DEVICE/MEMORY
« ASSERT BDAL <17:00> L WITH
ADDRESS AND

ASSERT BBS7 L IF ADDRESSIS
IN THE

10 PAGE

ASSERT BWTBT L (WRITE

CYCLE)
* ASSERT BSYNC L

—_—
—_—

—

DECODE ADDRESS

* STORE"DEVICE SELECTED”

OPERATION

OUTPUT DATA

» REMOVE THE ADDRESS FROM

BDAL < 17:00> L. AND NEGATE BBS? L
AND BWTBT L

* PLACE DATA ON BDAL < 16:00> Lt
—
e ASSERT BDOUT L

—_—
—

T -

TAKE DATA

RECEIVE DATA FROM BDAL
LINES

e = ASSERT BRPLY L

TERMINATE OUTPUT TRANSFER

-—

* NEGATE BDOUT L (eND BWTBT L
\F A DATOB BUS CYCLE!
» REMOVE DATA FROM BDAL < 1:00> L\

—
—_—
—_—

OPERATION COMPLETED

_ - -

NEGATE BRPLY L

TERMINATE BUS CYCLE
e NEGATE BSYNC L

Figure 4-3

DATG or DATOB Bus Cycle

4-4

_DEVICE_

SLES

INITIATE REQUEST

o e

STROBE INTERRUPTS
«

ASSERT BDIN L

ASSERT 8IRQ L

—

——
—

—_

RECEIVE BDIN L
»

STORE “INTERRUPT SENDING
IN DEVICE

GRANT REQUEST

PAUSE AND ASSERT BIAKO L~

— —

_—
—

RECE{VE BIAKI L
»

RECEIVE BIAKI L AND INHIBIT
BIAKO L

PLACE VECTOR ON BDAL < 15:00 > L

ASSERT BRPLY L

——+ NEGATE BIRQ L
e

—

RECEIVE VECTOR & TERMINATE
REQUEST

INPUT VECTOR ADDRESS

NEGATE BDIN L AND BIAKO L
Te

—
—_

—

—_—

COMPLETE VECTOR TRANSFER
»
___—-*

REMOVE VECTOR FROM BDAL BUS
NEGATEBRPLY L

e -

—

PROCESS THE INTERRUPT
« SAVE INTERRUPTED PROGRAM
PC AND PS ON STACK
» LOAD NEW PC AND PS FROM
VECTOR ADDRESSED LOCATION

s EXECUTE INTERRUPT SERVICE
ROUTINE FOR THE DEVICE

Figure 4-4

Interrupt Request/Acknowledge Sequence

__cru

_DEVICE_
REQUEST BUS

GRANT BUS CONTROL

—

¢ NEAR THE END OF THE

—— 77 » ASSERT BOMR L

= o

CURRENT BUS CYCLE

(BRPLY L IS NEGATED).
ASSEAT BOMGO L AND

~—

INHIBIT NEW PROCESSOR

—~—

ACKNOWLEDGE BUS

~—

GENERATED BYSNC L FOR
THE DURATION OF THE

MASTERSHIP

——

« WAIT FOR NEGATION OF

DMA OPERATION

¢ RECEIVE BOMG

BSYNC L AND BRPLY L

TERMINATE GRANT

SEQUENCE

« ASSERT BSACK L

—

¢ NEGATE BDMR L

* NEGATE BDMGO L AND

WAIT FOR DMA OPERATION TM

TO BE COMPLETED

EXECUTE A DMA DATA
TRANSFER
+ ADDRESS MEMORY AND
TRANSFER UP TO

4 WORDS

OF DATA AL DESCRIBED

FOR DATI.

OR DATO BUS

CYCLES
—~

o
-

—

» RELEASE THE BUS BY

TERMINATING BSACK L
INO SOONER THAN

NEGATION OF LAST BRPLY

ENABLE PROCESSOR-

GENERATED BSYNC L

(PROCESSOR IS BUS

WAIT 4 45 OR UNTIL

MASTER) OR ISSUE

ANOTHER FIFO TRANSFER

L IS ASSERTED

REQUESTING BUS AGAIN

ANOTHER GRANT (F 8DMR

Figure 4-5

\S PENDING BEFORE

DMA Request/Grant Sequence

4-5

4.3

SERIAL INTERFACES

The serial interfaces shown in Figure 1-5 are made up of four DUARTS and a number of line drivers and

receivers. These are shown in the bottom right-hand corner of Figure 4-1.

The four DUARTS are controlled and serviced by PROC2. All parallel data into and out of the DUARTS
is transferred via PROC2.

A common interrupt tells PROC2 when one of the DUARTS has assembled a received character. In order

to find the interrupting channel, PROC2 checks each DUART status in turn. It then constructs a status
byte, transfers it to the FIFO, reads the character from the DUART, and transfers that to the FIFO.
All other DUART status information, such as:

e
e

Ready to accept a character for transmission
Status change on a modem control line

is polled by PROC2.

Modem Control and Status Lines

4.3.1

Each DUART has output lines for the modem control signals Request To Send (RTS) and Data Terminal
Ready (DTR). There are also inputs for the modem status signals Clear To Send (CTS), Data Set Ready
(DSR), and Data Carrier Detected (DCD). The status of the input lines is visible to the host through the
STAT register. Output lines can be controlled via the LNCTRL register.

Ring Indicator (RI) signals are input directly to PROC2 from the line receivers.

There is no ‘break detect’ bit in the status registers. A break condition is reported via the FIFO as a null
character with the framing error bit set.
4.3.2.

EIA/TTL Level Conversion

Interface to the serial lines is provided by 9636 AC line drivers and 9637AC receivers. These inverting
amplifiers convert between EIA levels on the serial lines, and TTL levels at the DUARTS.
NOTE

More detail of the SC2681 DUARTS used in the
DHYV11 is provided in Appendix A3.
4.4

CONTROL SECTION

4.4.1

General

The control section (Figure 1-5) is made up of everything except the two interfaces which have just been
described. This section contains:

The common RAM — via which almost all commands and data are routed

The store arbitrator — which regulates all RAM access requests from the host and the DHV11’s
two microcomputers

The microcomputers — PROC1 and PROC2

Data and address latches and drivers

4-6

FIFO control and address circuits — which supply the appropriate FIFO addresses

The CSR - which is the main control register.

The CSR is a separate set of latches and is not part of common RAM.
4.4.2

Common RAM

4.4.2.1

Memory Map — The common RAM (common to both microcomputers) is mapped to
microcomputer addresses 800016 to 87FF
4 as shown in Figure 4-6.

PHYSICAL

MICROCOMPUTER

{(WORD)

(BYTE)

ADDRESSES

(HEXADECIMAL)

Diacnostic ] O°FF

87FE

BYTES

SCRATCH
AREA

SINGLE CHAR BUFFER

INTER-

con

DMA OUTPUT BUFFERS

BUFFERS

8 x 8 WORDS

8 x 1 WoRD ] 0248
CHAN

CHAN

%
3

CHAN

HI BYTE = FLAG

CHAN

LO BYTE = CHAR

CHAN

256 WORD

= READ BASE+2
= RBUF

{512 BYTES)

FIFO

LOGICAL

ADDRESSES

BASE+16
BASE+14
BASE+12

16 x LNCTRL

BASE+10

16 x STAT

BASE+6

16 x LPR

BASE +4

16 x

TXCHAR (WRITE)

0070

0080

8100

0060

80CO

}

0040

0050

80A0

0030

8060

0020

8040

0000

8000

}
HIGH
BYTE

The top 1K bytes (above the
scratch area.

BASE

Figure 4-6

8200

UNUSED

~ BASE+2

NOT USED

0100

AREA

(OCTAL}

16 x TBUFFCT
16 x TBUFFAD2
16 x TBUFFAD1

8400

}
QBUS

0000

ADDRESS OF FIFO

8490

0010

LOow

80EOD

8080

8020

BYTE

Common RAM — Memory Map

FIFO) are used by PROC1 and PROC?2 for interprocessor buffers and a

Each channel has an 8-word buffer for DMA characters. There are also eight 1-word buffers (one for each

channel) for single-character programmed transfers. By using buffers, the DHV11
efficiently. Buffers are filled by PROCI1 and emptied by PROC?2.

4-7

is able to transmit more

Each word of a buffer has a flag byte (D<15:8>) and a character byte (D<7:0>). When PROCI1a

transfers a character to a buffer, it sets the flag byte to a non-zero condition. When PROC2 transfers
character to a UART, it clears the flag byte to zero. In this way, the flag byte is used as a handshake
between PROC1 and PROC2.

The top eight words are reserved for self-test diagnostic bytes.

4.4.2.2

Registers — The DHV11 is controlled via registers. There are seven for each channel, plus the

FIFO (RBUF) and a common CSR. The functions of registers are as follows:

CSR

— Main control register for channel selection, important flags, and control bits

RBUF

— FIFO for received characters, and status and diagnostic information

TXCHAR

- Any character written to a channel’s TXCHAR is transmitted on that channel

LPR

— Command codes written by the host to this register configure the channel

STAT

— Indicates the current modem status

LNCTRL

— Command register via which the host controls the channels

TBUFFADI1 - Loaded by the host, while setting up a DMA transfer with the 16 low-order bits of
a DMA address

TBUFFAD2 - Holds the six high-order bits of a DMA address, plus control bits

TBUFFCT

- Loaded by the host, while setting up a DMA transfer, with the number of DMA
characters to be transferred.

Figure 4-6 shows the location of registers and their physical addresses. Each block allocated to a register
contains 16 word locations, only 8 of which are used. These locations are indexed by an address
previously written to CSR<3:0>. For example, in order to write to the TXCHAR register for channel 7,
the host must first write 7 to CSR<3:0>. When the host then writes to TXCHAR (BASE + 2), the

address is indexed by 7. This accesses the appropriate TXCHAR register from the block of 16.

The host can also write bytes to the registers. In that case, even addresses (BASE + 2, BASE + 4, and so
on) will access the low byte (D<7:0>). Odd addresses (BASE + 3, BASE + 5, and so on) will access the
high byte (D<15:8>).

‘

Transfers to the master, from the registers and the FIFO, are routed via the output data latches. Transfers
from the master to the registers pass through the input data latches.

4.4.2.3 FIFO-This 256-word RAM area usually contains received characters and status information.
When the host reads from BASE + 2(RBUF), the oldest word in the FIFO is transferred.
There is only one received character buffer (RBUF). The index bits (CSR<3:0>) are ignored during a
read action from RBUF.

4.4.3
RAM Access
(See Figure 4-7.) The common RAM can be accessed by the host, or by each of the DHVI11
microcomputers. Therefore, it is a 3-port memory.

|
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HOST

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DATA

LATCHES

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DATA

TRANSCEIVERS|TM

DATA

TRANSCEIVERS[TM

TO/FROM

HOST

TO/FROM

PROC2

PROC1

PROC1
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RD1153

Figure 4-7

Common RAM Access

Addresses (Figure 4-7) come from four sources:
PROC1

PROC2
The host processor (via translation logic)
The FIFO Fill and Empty counters.
During a write to FIFO (by PROC?2) or a read from FIFO (by the host), the RAM address is given by one
of the FIFO counters. Dotted lines in Figure 4-7 indicate that this area is oversimplified.

Figure 4-1 shows more detail of the same circuit.

4-9

Store Arbitrator

4.4.4

When one of the microcomputers or the host needs to access the RAM, it will generate a request for store
access. The store arbitrator (Figures 4-7 and 4-1) sequentially scans the request lines. When it detects a
request, that request is granted and the other two requests are locked out. The arbitrator issues enable
signals for the appropriate address and data sources, and starts memory timing and control logic.

Signals produced by the timing and control logic perform the read or write action and then terminate the
access.

Microcomputers

4.4.5

Using the RAM as a common reference point, PROC1 and PROC2 manage the functions of the DHV11.
Under control of firmware, contained in internal ROM in each microcomputer, the RAM is scanned for
commands or data. The main functions of each microcomputer are as follows:
PROCI1

1.
2.

3.
4.

Single-character transfers from the TXCHAR register to the output buffers in common RAM.
Control of DMA transfers from system memory to the output buffers in common RAM.
Reporting back to the host via the TX.ACTION bit in the CSR.
Executing the Background Monitor Program (BMP) when not busy with other tasks.

PROC2

Transfer of characters (DMA and single character) from the output buffers to the appropriate

Transfer of received characters and error status from the DUARTS to the FIFO. Recognition
of automatic flow control (auto-flow) characters X-ON and X-OFF. Auto-flow is described in

DUART channel.

Chapter 3, Programming.

3.
4.
5.
4.4.6

Servicing internal interrupts which are raised when the host writes to the LPR or LNCTRL

registers.

Scanning the modem status lines for a change of state. Reporting back to the host viathe STAT

Executing BMP when not busy with other tasks.
Address and Data Latches

To meet the interface timing demands, latches are used for all transfers between the host and the DHVI1I1.
For example, to transmit a single character, the host writes the character to the TXCHAR register.
During this action the TXCHAR address is latched into the register address latch. The data is latched into
the input data latches. The arbitration and timing and control circuits complete the transfer to TXCHAR.

Characters transferred by DMA are not routed through the TXCHAR register. Special DMA latches are

provided for this purpose.

At the beginning of a DMA cycle the next DMA address is written to the DMA address latches (Figure 4-1).

This generates a DMA request to the DMA control IC, DCO010, which transfers the next word from host
memory to the DMA data latches. PROC1 will transfer the word (two characters) from the latches to the
DMA buffer area in common RAM, except at the beginning or end of an odd length buffer.

4-10

4.4.7

FIFO Addresses
The FIFO is implemented in common RAM. It is filled by PROC2 and emptied by the host. It is made to
act like a FIFO by the action of two counters.

The Fill counter provides addresses during PROC2 FIFO WRITE actions. It points to the next available
location. The counter is incremented after each word (two separate bytes) is written.
The Empty counter provides addresses during a FIFO READ action by the host. It addresses the oldest
word in the FIFO. It is incremented after each word is read.

4.4.8
FIFO Control
Received characters are transferred from the DUARTS to the FIFO in order to be read by the host.
PROC?2 loads the status (high) byte and then the character (low) byte. The host reads this information as a
full word. A FIFO control circuit manages these actions by monitoring GRANT signals from the store
arbitrator and READ or WRITE signals from the host or PROC2.
The functions of the

FIFO control circuit are as follows:

Gating the appropriate FIFO counter onto the store address (SAD<9:0>) bus
Incrementing the appropriate counter after access
Disabling both FIFO addresses when the FIFO is not being accessed

Reporting the state of the FIFO (FULL, ALARM, EMPTY) to PROC2 and the CSR.

4.5

OTHER CIRCUITS

4.5.1

Voltage Converter

Line drivers and receivers need both +12 V and-12 V in order to generate line signals at EIA levels. The
voltage converter, whichis a small Switched-Mode Power Supply (SMPS), produces —12 V from the +12
V supply.

4.5.2

Oscillators
Also on the module are the following circuits:

4.6

Oscillator to provide 24 MHz, 12 MHz and 6 MHz clock signals for the timing circuits

Oscillator of 3.6864 MHz to provide the basic clock for DUART data rates.

DATA FLOW

DHV11 firmware uses interrupt timers in PROC1 and PROC?2 to enter certain routines which handle

data and check the control registers. Therefore a delay, dependent on the timer interval, can be introduced
into some data paths. When referring to Figures 4-8 to 4-14, these delays must be considered.
The delays are as follows:

TXCHAR to single-character transmit buffers:
Every 780 microseconds PROC1 checks for characters in each TXCHAR register. If
available, one character will be transferred to the buffers from each register. It is this timer
which limits single character transmission to 1000 characters per second.

DMA data latch to DMA buffer area:

Each time PROCI services the single-character buffers it also checks, and services if needed,
one pair of channels for DMA. The channels are serviced in rotation. This means that a specific
channel is serviced every 4 X 780 microseconds = 3.12 milliseconds. PROCI1 will transfer up
to eight characters to each of the two DMA output buffers in common RAM (Figure 4-6).
Single-character or DMA output buffer to DUART:

Every 480 microseconds PROC?2 checks the interprocessor buffers for valid data. If there is
data waiting, a character will be transferred to each DUART channel which is ready to take a
character. It is this timer which limits DMA transmission per channel to 2000 characters per
second.

DUART to FIFO:

Received characters are not handled by timer-driven interrupts, but by direct interrupt from the
DUART. Therefore, in comparison with transmitted characters, the delay is not significant.
The DMA start bit is sampled every 3.12 milliseconds. There is also a delay of up to 480
microseconds in PROC2. This gives an average delay of 1.8 milliseconds before a DMA
transfer is started.

Timer dependent tasks of PROC2 may be delayed by:
1.

The receive interrupt

The parameter change interrupt which is raised (by hardware) when the host writes to the LPR
or LNCTRL registers. (It may have to change the DUART configuration or the state of modem
control lines)

The need to monitor modem status lines. These are sampled every 10 milliseconds.

From the foregoing it should be clear that PROC2 delays are to a great extent dependent on application
and on throughput.
In the following descriptions of data flow, the basic timer delays are noted against the appropriate data
paths on the diagrams.
4.6.1
Host Read from a Register
(See Figure 4-8.) Except for RBUF or the CSR, the channel number must first be written to CSR<3:0>,
This is followed by a READ from BASE + n (see Figure 4-6).

4-12

INDIRECT

ADDRESS

CHANNEL NUMBER

CSR<3:0>

ADDRESS
LATCHES

ADDRESS

INDEXED ADDRESS

ADDRESS

RAM
DATA

DATA
TRANSCEIVERS
fi

LATCHES
e
REGISTER

BUS

GRANT

READ
ENABLE

€0

NTROL

EggggCOL

BUS REC

» ARBITRATOR

BUS GRANT

TIMING

AND

CONTROL

RD133%

Figure 4-8

Reading from a Register

The register address is latched into the register address latches, to be applied to the RAM when bus access
is granted.
The READ action from the host generates a BUS REQUEST to the store arbitrator, which generates
BUS GRANT. This starts the timing signals which read a word from the addressed register. When BUS
GRANT is deasserted, the data is latched into the output data latches.
BRPLY (Figure 4-2) is inhibited until data transfer to the output latches is complete. BRPLY is then

asserted. READ signals on the Q-bus transfer the word to the host.

4.6.2 Writing to a Register
(See Figure 4-9.) In order to write to a register the channel number is first written to CSR bits <3:0>. This
is followed by a WRITE to BASE + n (see Figure 4-6).

4-13

INDIRECT

CHANNEL NUMBER

ADDRESS
REGISTER

(CSR<3:0>)

ADDRESS

INDEXED ADDRESS

LATCHES

ADDRESS

RAM
BUS

DATA

INPUT

DATA

TRANSCEIVERS

DATA

LATCHES
EN

BUS

GRANT

WRITE

CONTROL

DCO04

BUS REQ

PROTOCOL

ENABLE

ARBITRATOR

BUS GRANT

TIMING

»>1EN

AND
CONTROL

RD1340

Figure 4-9

Writing to a Register

The register address is latched into the register address latches and is applied to the RAM when the bus
access is granted. The data to be written is latched into the input data latches.
The WRITE action from the host generates a BUS REQUEST to the store arbitrator. BUS GRANT
enables the data from the input data latches and provides RAM timing signals. Data will be written to the
addressed register.
For a WRITE BYTE action, address line O will select the high or low byte of a word.

4.6.3

Single-Character Transmit

(See Figure 4-10.) To transmit a character by use of the single-character transmit facility, the character

and the DATA.VALID bit can be written to the TXCHAR register. This would be done exactly as in
Section 4.6.2. To transmit subsequent characters, the TX.ACTION bit for this channel must be checked
by polling or via interrupts.

4-14

RAM

PROC1

WRITE

SINGLE CHAR

READ

DATA

TRANSMIT BUFFER

DATA

READ

PROC2

WRITE

DATA

DUART

TRANSMIT
DATA

TX CHAR

DATA

%__)

DELAY UP TO 780 ps

DELAY NORMALLY UP TO 480 ps

(390 ps TYPICAL)

{(MAY BE EXTENDED BY LINE PARAMETER
CHANGES OR BY RECEIVED CHARACTERS)

Figure 4-10

RD1341

Single-Character Transmit

PROCI1, which scans the TXCHAR register, detects from the data valid bit that a new character has been
written. It reads the character and then transfers it to the single-character buffer area in the common RAM
(Figure 4-6). PROC1 writes the channel number and the TX.ACTION bit to report acceptance of the
character.
PROC?2, which scans the buffer area, reads the character from the buffer area and writes it to the
appropriate DUART. The DUART then transmits the character serially on the appropriate channel.

4.6.4 DMA Transmissions
Section 3 (Programming) describes how a DMA block transfer is set up. The host writes a DMA buffer

start address, the number of characters to be transferred, and a TX.DMA.START bit to TBUFFADI,
TBUFFAD?2, and TBUFFCT.

4-15

INVY

|——

4-16

4.6.4.1

DMA Block Transmit — Figure 4-11 shows the data flow for a DMA transfer.

When the host sets TX.DMA.START, PROCI1 writes the DMA address (in three bytes) to the DMA
address latches. Writing the most significant address byte sets the DMA request latch, which starts a
DMA transfer.

The DCO10 performs a READ from memory, using the DMA address held in the address latches.
The DMA cycle always transfers a word from system memory to the DMA data latches. PROCI reads
the word (two characters) one byte at a time, and transfers them, via its data transceivers, to a buffer areain
RAM. Note that PROCI1 can only write to the buffer area if there is space for at least two characters.
PROC?2, which scans the buffer area, reads the character from the buffer area and writes it to the
appropriate DUART.

The DUART transmits the character serially on the appropriate channel.

4.6.4.2 DMA Data Management — When a DMA block starts with an odd address, or ends with an
even address, PROC1 will transfer the addressed character only, to the output buffer.
Figure 4-12 shows how DHV11 manages a 9-byte DMA transfer. The start address is 1061g and the end
address is 1072g.
PROC?2 transfers characters from the buffer area, exactly as in Section 4.6.4.1.
START OF

END OF

DMA BLOCK

LOC
1060

LOC
1061

LOC
1062

LOC
1072

FIRSTWORD

READ FROM

MEMORY TO
DMA DATA
LATCHES

FIRST BYTE

LOC
1073

BYTE

RAM

LAST BYTE

TRANSFERRED TRANSFERRED TRANSFERRED TRANSFERRED
TO COMMON
TO COMMON TO COMMON TO COMMON
RAM

LOC
1074

RAM

)

LAST WORD

READ FROM

MEMORY
TO DMA

DATA LATCHES
RD1160

Figure 4-12

DMA Character Handling

4.6.4.3
DMA Error Detection and Timeout— Q-bus protocol demands that, during a bus transaction,
a bus master which does not receive BRPLY within 10 microseconds of sending BSYNC should terminate
the transaction. For a DMA transfer the DHV11 becomes bus master; therefore it must obey the timeout
rule. The DHV11 also checks parity bits BDAL 17 and 16.
At the beginning of each DMA cycle the DMA controller uses ADREN (address enable) to gate the
DMA address onto the Q-bus. The trailing edge of this signal starts a hardware counter (Figure 4-13)
which will time out after 10.7 microseconds if there is no reply from the bus. The counter is cleared by its
own timeout or by a bus reply.

4-17

The DMA error status is cleared by aDMA request. It will generate a DMA error signal (DMA ERROR)
if the timer times out or if a memory parity error (BDAL 17 and 16 asserted) is detected. The parity error is
latched when the bus reply goes false at the end of the transaction.

At the end of the DMA cycle, when the DC010 deasserts BDIN, a DMA COMPLETE signal (Section
4.7.1.2)is generated. When PROC1 detects DMA COMPLETE it checks the state of DMA ERROR. If
an error is detected, the DHV11 will read the same location once more before reporting an error to the
host.
REPLY (HIGH)
P1102.L (DMA REQ)

MEMORY PARITY ERROR [

Lowy

—

SET

DMA

.
ERROR

LOW IF REPLY

REPLY (LOW)

OR TIMEOUT
X

]

[ SET

)

10.7 ps
o

HIGH

_—

.TOCLEAR

—L.

P1109.H

CreseT P>
(DMA ERROR)

TIMEOUT (HIGH) |

TM cLEAR

E62

ADREN.L

LATCH

I
| 2MHy

CLK
RD1161

Figure 4-13

DMA/Memory Error Generation

4.6.4.4 DMA Abort— PROCI transfers DMA data from the host, in blocks of up to eight characters
(four words). The data is held temporarily in the DMA output buffer area in common RAM. PROC2
scans the buffer for data, and transfers it byte by byte to the DUARTS. Separate buffer areas are reserved
for each channel.

A DMA sequence can be terminated by a DMA abort command from the host. When this happens,
PROC? stops the transfer of characters to the DUART channel. PROCI1 stops transferring data, counts
the characters in the buffer, corrects TBUFFCT, TBUFFADI1, and TBUFFAD?2, and then clears the
DMA buffer area for this block. It then sets TX.ACTION to report that the transmission has been
aborted. To continue transfer of the aborted block, the host need only clear TX.DMA.ABORT and set the
TX.DMA.START bit. The transfer will continue without losing characters.
4.6.5

Receiving

(See Figure 4-14.) When a serial channel has assembled a character, it will raise an interrupt. PROC2 will
respond by reading status from each DUART in turn. When it finds the interrupting channel, PROC2 will
transfer an error/line-number status byte and the character byte to the FIFO.
PROC?2 writes all receive information to a 1-word address in the RAM; C040 = low byte, CO41 = high
byte. These addresses are decoded and ANDed with ‘PROC2 grant’ to enable the FIFO Fill counter.
This counter provides the actual FIFO address. The counter is incremented after each character byte is
transferred. Therefore the character (low byte of RBUF) is transferred last.

4-18

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4-19

J030L0Hd

To read the FIFO, the host performs a ‘read from register’ sequence as described in Section 4.6.1. In this

case, however, the DC004 recognizes that the FIFO (Base + 2) is being read. This causes the Empty
counter and the FIFO to be enabled.

The data is transferred via the data output latches as for a ‘read from register’ operation.
If characters are received faster than they are removed by the host, the FIFO will eventually become full.
PROC2 will stop taking characters from the DUARTS. A further four characters can be buffered in any
DUART channel before the overrun condition is reached. When this happens, any overrun channel will
be flushed.
When space is available, a null character (one for each overrun channel) with the overrun error bit set will
be placed in the FIFO.
4.7 TECHNICAL DETAIL
This section provides a more detailed description of specific areas of DHV11 logic and electronics.

4.7.1
DHVI1I1 Internal I/0 Control
PROCI and PROC?2 firmware defines the functions of the DHV11. The functions managed by the
microcomputers are controlled and monitored via I/O ports associated with each microcomputer.
These
are memory-mapped I/O ports, and integral ports P1 and P3. (See Appendix A2, 8051 Microcomputer.)

Memory-mapped I/O used internally on the DHV11 is very similar to PDP-11 memory-mapped
1/0
architecture. I/O addresses start at C000;¢ on each microcomputer.

4.7.1.1

PROCI1 Memory Mapped I/O — Table 4-1 lists the addresses and functions of PROC1

memory-mapped I/O. Figure 4-15 shows how the addresses are decoded.

Table 4-1

Address

PROC1 Memory-Mapped 1/0

I/O Type

Signal Name

Function

C000

Write

P1100.L

Load low-order eight bits of DMA
address into DMA address latch.

C001

Write

P1IO1.L

(Hexadecimal)

Load middle eight bits of DMA address
into DMA address latch.

C002

Write

P1IO2.L

Load high-order six bits of DMA address

into DMA address latch. Set DMA
request latch,

C003

Not used.

C004

Read

P1IO4.L

Read low byte of DMA data from
DMA data latch.

C005

Read

P1IOS.L

Read high byte of DMA data from
DMA data latch.

C006

Not used.

4-20

PROC1 Memory-Mapped I/O (Cont)

Table 4-1
Address

(Hexadecimal)

C007

I/O Type

Signal Name

Function

Write

P1107.L

PROC1 CSR write. Also starts adummy

store-access sequence. This is to prevent
access conflicts to this register.

+VE

DMA
REQ

f———

P1AD<7:0>

L LAaTcH | DMAREQTO

P1AD<2:0>

(SDEL7ECT
-

DMA CONTROLLER

0 p-F1100.L

P1AD14 HIGH

P1RD OR WR STROBE
ACP1

)

MREQUEST SYNCHRONIZER

—

|
I

||
|

+VE

|
N

b—de34

_————— — — — —

:
BYTE - Ap<i5:8>
A MID

5 o P1I05.L

ENABLE IS:
P1AD15 HIGH> 00

]

:A[k‘”)) >

P1AD<7:0>

3P pri0a

7 o—

,pP1i02.L

———|ENABLE

léeTV\é

L _Pii01.L

OMA ADDRESS |

LATCHES

]

|
S

cL =
@

et
CSRFC.L

- E9

P1AD<5:0> >

E90

|
|

HiGH

HisH

I
|pstowL |

—————-

P1 CLK

[~ bmapata |1

|
LATCHES
|
PADTOS| Low /11__

AD<7:0>
70>
L d BYTE JAD<
|

PI1AD<7:0>|
I

P1SRQ.H

[Ap<21:16>

.1
Bvre

[C_AD<15:8>
|

i
RD2250

Figure 4-15

PROCI! I/O Decoding

4-21

4.7.1.2
PROCI Integral I/O Port Functions — Table 4-2 lists the functions of the integral ports used
by PROCI.
Table 4-2
Port

Direction

PROCI Integral I/O Port Functions

Signal Name

Function

(Explanatory
Title)
P1.0

Input

P1108.L
(TX ACTION)

1=DHV11 has completed or terminated
a transmit action. Waiting for read by
host.

0= CSR has been read by host. This bit
is cleared when host reads CSR.
P1.1

Input

P11I09.H
(DMA ERROR)

1 = Error during last DMA transfer.

0 = No DMA error.
P1.2

Input

P1IO10.H
(DMA COMPLETE)

1 = Last DMA request has been
completed.

0 = Not completed.
P1.3

Output

P1IO11.H
(DIAG ERROR)

1 = Error found during self-test diagnostic
or BMP.

0 = No error was detected during selftest diagnostic or BMP.
This bit drives the ‘diagnostics passed’
LED and the ‘diagnostics fail’ bit in
the CSR.

P1.4

Not used.

P1.5

Not used.

P1.6

Output

P1I014.L
(MR CLEAR)

0 = Clear and hold master reset latch.

1 = Release hold.

P1.7

Not used.

P3.0

Input

IPSLO

P3.1

Output

IPSL1

Serial input line to PROC!1 internal
UART.

Serial output line from PROCI internal

UART.

The above two serial lines connect to

PROC2 internal UART for direct
reporting during diagnostics.
P3.2

Not used.

4-22

Table 4-2
Port

Direction

PROCI Integral I/O Port Functions (Cont)
Signal Name

Function

(Explanatory
Title)

P3.3

Not used.

P3.4

Input

P2INT1.L

PROC?2 interrupt monitor
0= Pending change to LPR or LNCTRL
registers.

1 = No pending change.

P3.5

Not used.

P3.6

Output

PIWR.L

P3.7

Output

PIRD.L

Write strobe for common RAM and

the DUARTS.

Read strobe for common RAM and

the DUARTS.

4.7.1.3 PROC2 Memory-Mapped I/O — Table 4-3 shows the addresses and functions of PROC2
memory-mapped 1/O. Figure 4-16 shows how the addresses are decoded. The low address lines are used
to select one of 16 registers in each DUART.
Table 4-3

Address

PROC2 Memory-Mapped 1/0

I/0 Type

Signal

Name

Read/Write

UARTO.L

Read/Write

UARTI1.L

Read/Write

UART2.L

Read/Write

UART3.L

Write

FIWR.L

Function

(Hexadecimal)

C000
to

Chip select DUART 0.
Internal registers addressed by ADO to AD3.

COOF

Co010
to

Chip select DUART 1.

As above.

COlF

C020
to

Chip select DUART 2.

As above.

CO2F

C030
to

Chip select DUART 3.
As above.

CO3F

C040

Writes the low byte of the FIFO word
(usually the received character) to the FIFO.

The trailing edge increments the FIFO
address pointer (so it is written after the
status byte). ADO = 0.

4-23

Table 4-3
Address
(Hexadecimal)

C041

PROC2 Memory-Mapped 1/0 (Cont)

I/O Type

Signal

Name

Write

FIWR.H

Function

Writes the high byte (status) to the FIFO.
Written before the low byte. ADO = 1.

C050

Write

FICL.L

Clears the
DHV11

C060

FIFO address counters at bus or

reset. (In effect empties the FIFO.)

Not used.

C070

Write

INTCL.L

Clear interrupt request PROC2. When the
LPR and LNCTRL registers are written, a
hardware interrupt request is raised to alert

PROC2. During the interrupt routine,
PROC2 clears the interrupt request via
INTCL.L.

P2AD<3:0>
P2AD<6:4>

INTERNAL REGISTER SELECT > SEL
> SELECT O

UARTO.L

0-3

| |

UART2.L

sk
b

DUARTS

UART1.L

| |

UART3.L

FIWR.L

5fp———————

6p—
——————={ENABLE

7f0———

E\E’?EL,EHGSQ}:COXX

FoonTen [ADDRESS X #ODRESS TsAp<7:055

Ram

AD14 HIGH
P2 RD OR WR STROBE

L_FicLL

P2 INT 1.L

INTCL.L
RD1156

Figure 4-16

PROC?2 I/O Decoding

4-24

4.7.1.4 PROC2 Integral I/O Port Functions— Table 4-4 shows the function of the integral ports used by
PROC2.

Table 4-4

PROC2 Integral I/O Port Functions

Port

Direction

Signal Name

Function

P1.0

Inputs

RIBO.L

to
RIB7.L

Indicates the state of the Ring Indicator lines

0 to 7 from modems.
0 = ON, 1 = OFF.

P3.0

Input

IPSL1

Serial input line to internal UART, PROC2.

P3.1

Output

IPSLO

to
P1.7

Serial output line from internal UART,

PROC2.

The above two serial lines connect to the
PROCI internal UART for direct reporting
during diagnostics.

P3.2

Input

0 = DUART service interrupt request active.

P2INTO.L

1 = Interrupt inactive.

P3.3

Input

0 = CHANGE interrupt request active.

P2INTI.L

Becomes active each time the host writes to

LPR or LNCTRL.

1 = Interrupt inactive.

P3.4

Input

0 = FIFO

FULL.L

is full

1 = FIFO is not full

P3.5

Input

0 = FIFO has reached three-quarters full

ALARM.L

condition and has not yet been emptied
below half full.

1 = FIFO not in the above state.

P3.6

Output

P2WR.L

Write strobe for common RAM and the

P3.7

Output

P2RD.L

Read strobe for common RAM and the

DUARTS.

DUARTs.

4-25

4.7.2 Q-Bus Interrupts
(See Figure 4-17.) The function of the DC003 interrupt logic is to make interrupt requests and to supply a
vector to the host. Signal sequences for interrupt request and acknowledge are given in Figure 4-4.

If interrupts are enabled, they are generated under the following conditions:
1.

When areceived character is loaded into a previously empty
indicate this state)

When, with data in the

When, during a single-character programmed transfer, a character is removed from a
TXCHAR register

'When a DMA block transfer is completed, or has been aborted, or has failed because of a DMA

FIFO (EMPTY.L is asserted to

FIFO, RXIE is changed to the enable state

error.

For conditions 3 and 4, the signal TX.ACTION.H is generated.

EMPTY.L, when it goes false, causes a receive interrupt request (RQA) and TX.ACTION.H causes a
transmit interrupt request (RQB).
Interrupts are enabled by writing a 1 to CSR bit 6 and/or CSR bit 14. This action generates receive
interrupt enable (RXIE) and transmit interrupt enable (TXIE) respectively. The host can read the status
of these lines by a CSR read action.

The enable signals are ANDed with the appropriate request, and latched to generate RQA or RQB. If
both are true, priority is given to RQA.
Forboth RX and TX interrupts, bus interrupt request (BIRQ.L) is generated. The request is cleared again
by RDIN.L at the start of an interrupt acknowledge cycle.

NOTE
Both RX and TX interrupt requests are latched by
a rising edge. Therefore in order to raise another
interrupt request, one of the inputs to AND gates
A or B must be deasserted and then asserted.

In an interrupt acknowledge cycle, the DCO003 interrupt IC responds to BIAKI.L. The signal
VECTOR
.H enables the vector switches onto BDAL<3:8>. VECT.2.H provides the low bit of the
vector address on BDAL<2>>. It identifies a receive (0) or transmit (1) interrupt vector. VECTOR.H
also generates BRPLY via DC004 protocol logic. The vector is transferred to the host by a DATI
sequence which follows the interrupt request/grant sequence.

4.7.3
Common RAM Arbitration
(See Figure 4-18.) To allow the common RAM to be accessed by the microcomputers and by the host, the
DHV11 provides arbitration circuitry. However, arbitration introduces a delay into a memory access
sequence. To account for this delay, the store access cycle of the requesting device must be extended.

Data addresses and control signals from the external bus are extended by delaying BRPLY.L. This signal
is disabled until the store access is complete. The 8051 microcomputers, however, cannot be controlled in

this way. They have no handshake signal such as WAIT, and because they are dynamic it is not possible to
stop the clock.

4-26

CSR

DRIVERS

ARE

RXIEl gre

TXEL g7 14 ADLA,
EN

CSR
READ
T

|
-

ADO6.H
CSR WRITE

RXIE

L EMPTY.L—4=
-

BIAKLL

AD14.H

CSR WRITE !

HIGH BYTE

REQ

ROA

LATCH

8
BIRQ.L
—L>1

CONTROL L4+ VECTORH

INHIBIT B|PRIORITY

TXIE
> |ATCH

TXACTION.H_ 10

Liprios.l)

CLR REQ A

L24+ veCT2.H

[}

PORT B { (CWR.HB.H)

_— |

RDIN.L —4217

aQb—

LOW BYTE —l——> LATCHo

(CWR.LB.H)

PORT A

— -

TM
REQ

ROB

LATCH | c|lrREQ B

PART OF DCOO3 INTERRUPT LOGIC

|
RD1151

Figure 4-17

Interrupt Logic

The DHV11 solves the problem by slowing down the related microcomputer clock every time PROCI1 or
PROC? tries to access the RAM. The normal clock frequency is 12 MHz. This is reduced to 1.5 MHz
during RAM access. Approximately 330 nanoseconds after a store request has been granted, the normal
clock frequency is enabled.

Figure 4-18 provides more information on the RAM arbitration and timing blocks. A description of the
operation follows.

A 4-state scan counter (O to 3) is driven by the 12 MHz clock. The output is used as a synchronized count
for a request multiplexer and two accept decoders.

On each positive edge of the clock one of the latched store request lines (SRQDs) from PROC1, PROC2
or the bus is connected to the request latch. On each negative edge the input to the latch is sampled. Avalid
store request will set the latch. The scan counter will be stopped and the RAM state counter will be
enabled.

With the scan counter stopped, the MUX and the decoders will also stop. One of the grant signals, ACP1,
ACP2, or ACB (accept PROC1, PROC2, or BUS), will be true. The equivalent SCS (store chip select)
signal will be selected but not enabled.

Now that the RAM state counter is enabled, it is incremented by the 12 MHz clock from 000 to 101. The
counter is then held in the 101 state by END.L.

4-27

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4-28

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LNNOD

[ MO1S

)

Figure 4-19 gives timing details for a store access cycle.

12MHz CLK

)

SRQD

MUX

GRANT

SCAN CT ENABLE

B (WRTS)

C (TS4)
END.L

STOPS RAM TIMING COUNTER
RD1343

Figure 4-19

Store Access Timing Cycle

In Figure 4-19:

Write Time State (WRTS) is inverted to enable the selected Store Chip Select (SCS) signal via
the decoder. This action performs two functions:
1.

It enables the appropriate Chip Select (CS) signals via the chip select logic

It enables the appropriate write enable line. SWR.L will be true when one of the gates
E83, E84, or E102 is enabled and its input is low. That is to say, when PROCI1,PROC2,
or the host are writing to the RAM.

4-29

SWR.L, and CS signals for the high and/or low byte, perform the RAM access. If SWR.L is

false, a read action is performed.
e

In a PROCI write to the CSR, WRTS is used to set the TX.ACTION bit.

Time State 4 (TS4)~-If a PROCI1 or PROC2 request is valid, the related microcomputer clock
will be running slow at 1.5 MHz. TS4 switches the clock back to 12 MHz. TS4 also deasserts
any active store request. SRQD will be deasserted on the next negative-going 12 MHz clock.

o
e

END.L holds the RAM timing counter at 101 as previously described.
Chip select logic uses ADO, OUTHB, and OUTLB to select a byte or word. If the CSR
is being

addressed, both chip select lines will be inhibited.
e

Atthe end of the memory cycle, SRQD is deasserted. On the next negative 12 MHz clock, the
request latch and the RAM state counter will be reset, and the arbitrator will continue
to scan
for requests.
NOTE

Store request signals (SRQDs) to E69 are
supplied by a 748374 octal latch (E70), part
number 19-13671-51. This IC has special timing/

stability characteristics and must only be replaced
by an IC of the same type.

4.7.4 FIFO Counter Control
(See Figure 4-1.) It is the action of

FIFO counters which makes a section of common RAM act as a FIFO.

During initialization, the counters are cleared. As characters and status are written to
counter steps ahead of the Empty counter which is still addressing the bottom

the FIF O, the Fill

of the FIFO. As the host

reads each word the Empty counter is stepped to address the next word. The difference
counters is the number of characters in the

between the
FIFO. Both counters will roll over after a count of 255,

Comparator circuits check the two counters. The conditions, empty, half full, three-quarters
full, and full
can be detected.
When EMPTY is deasserted, a hardware request is generated for receive interrupt service.
This can be
disabled by software.
FULL is a signal which stops PROC2 from putting more characters into the FIFO.

ALARM is asserted when the FIFO becomes three-quarters full. Tt stays asserted
until the FIFO
becomes less than half full. These signals are used when the DHV11 is programmed
for auto-flow on
incoming characters. X-OFF characters are generated when the FIFO is more than
three-quarters full.
X-ON characters are generated when it becomes less than half full.
To address the appropriate FIFO location, address bits SAD9 and SADS must be
set to 0 and 1

respectively and the appropriate address counter must be enabled. The correct
SAD<9:8> code is
generated for any FIFO access, that is to say:

When the FIFO (READ from base + 2) is addressed and ACB (Figure 4-18) is

4-30

asserted

2. When PROC2 generates a FIFO WRITE signal (FIWR.L) and ACP2 (Figure 4-18) is
asserted.

4.7.4.1 Host Read from the FIFO — During a host READ from the FIFO the contents of the Empty
counter are latched onto SAD<7:0> by a decode of:
1.
2.

INWD from the DC004 protocol IC
The RBUF address (base + 2)
ACB from the RAM arbitrator.

By the same signals, a strobe is generated to increment the counter ready for the next action. If the FIFO is
empty (EMPTY.L asserted), the strobe is inhibited.

Chip select logic decodes BSCS and INWD to generate CS signals for both bytes of the addressed word.
4.7.4.2 PROC2 Write to the FIFO — When PROC?2 writes to the FIFO (FIWR.L asserted), the
contents of the Fill counter are latched onto SAD<7:0> by an AND of:
1.

FIWR.L from PROC?2 (see Table 4-3)
PROC?2 accept signal (ACP2).

However,
By the same signals, a strobe is generated to increment the counter ready for the nextisaction.
written. For this

because PROC2 can only write bytes, the strobe is only enabled when the low byte
reason the low byte is always written last.

The high or low byte is selected by ADO from PROC?2 (see Table 4-3). Chip select logic decodes the state
of ADO in order to generate the correct CS signal. The ADO = O state is used to enable the strobe which
increments the Fill counter.

Control/Status Register (CSR)

4.1.5

This is the main control register of the module. PROC1 updates the high byte as necessary. The host can

poll the CSR to find the DHV11 status.

Assbciated with the CSR (see Figure 4-20) are the following:
e Indirect Address Register—a 4-bit latch (ADO to AD3) which holds the number of the channel

which is to be accessed. The contents of this register are used to index the addresses supplied by
the host. Figure 4-20 shows how indexing is performed.
NOTE

The indirect address register holds the channel
number. Therefore, to configure a channel, the
register has only to be loaded once. The control
registers for that channel can then be loaded in

sequence. Only when the host needs to access
another channel must the indirect address register
be reloaded.

Master Reset Latch—set by BINIT or by writing a 1 to bit 5 of the CSR. Cleared by P1I014.L
from PROCI.

P11014.L and MRST.L are ORed at E29 to make sure that MRST does not go false until the
end of P1I014.L strobe.

4-31

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N—

DCO003 interrupt controller— provides interrupt enable status to the CSR. If bit 6 is set, receive
interrupt is enabled. If bit 14 is set, transmit interrupt is enabled.

FIFO Control — indicates that there is valid data in the FIFO.

e
e

TX ACTION Latch - indicates when a transmit action has been completed. It is cleared when

the CSR is read.

PROCI ~ provides the following information:
On SDAT<11:8> - The related transmit channel number
On SDATI12
— Diagnostic fail bit
On SDATI13
- TX.DMA.ERROR bit
On SDAT15

4.7.6

- TX.ACTION bit.

Voltage Converter (SMPS)

The DHV11’s line drivers and receivers need both +12 V and-12 V supplies. The +12 Vis supplied from
the backplane, but—12 V is derived from +12 V by a voltage converter. This device uses switched-mode
power supply techniques to generate the negative voltage.

The circuit is built around a TL494 switching regulator which uses pulse-width modulation to regulate the
-12 V output. The maximum current supplied is approximately 400 mA.

Switched-mode power supplies of the type used by DHV11 operate according to the following principles

(refer to the simplified circuit diagram of Figure 4-21).

Switching pulses from a pulse width modulator/regulator switch a transistor (Q1) to convert a dc input (V

IN) to a pulsed dc current in an inductor (L).

When Q1 is switched on, point X becomes positive causing current to flow through L. This generates a
magnetic field around L.

When Q1 is switched off, the current stops and the field collapses. This drives point X negative, and puts a
forward bias on diode D. Current generated by the collapsing field is transferred via the forward-biased
diode to the smoothing capacitors. In this way a negative voltage (V OUT) is generated.
As current is transferred to the output, the voltage at X rises until the diode is cut off again. The circuit will
stay in this state until the next switching pulse opens QI.
The inset of Figure 4-21 shows waveforms of the current through L, as seen by an oscilloscope across
R14. When Q1 is switched on, current rises linearly until Q1 is switched off again. The collapsing field
generates current, which reduces linearly as it is transferred to the output. With wider switching pulses,
more current is transferred to the output. Therefore, the power transferred (shaded in the inset) is
proportional to the width of switching pulses.

Feedback (VAR) from V OUT to the pulse width modulator is compared with a reference voltage (REF).
If VAR is too negative (V OUT is too high), the width of switching pulses is reduced. If VAR is too
positive, the width is increased. This action maintains V OUT at the correct level.

The same method of comparison is used to detect an over-current condition. When the voltage

(proportional to output current) across R14 gets too high, the switching pulse width is reduced. This
reduces the current.

4-33

The switching frequency, selected by R12 and
C9, does not change. In DHV11 this frequency is 36.7
kHz. If the oscillator is working, a sawtoothed
36.7 kHz waveform can be detected on pin 5 or
6.

+12V SUPPLY

FUSE

VIN

<é fi

-12v

vV oUT

| SWITCHING

PULSES

+5V REG
-

R21

vee
1'2 11&8

“TsMooTHING
CAP

C4,C5 & C7

PULSE-WIDTH

R18

MODULATOR
/REGULATOR
VAR _

TL494

REF

=
R22

[

R20

R12

OVER

16
5
l

CURRENT

V5I*%pF

—L
(Vacrly)
R14

€9

PROTECTION
FEEDBACK

= POWER TRANSFERRED TO O/P

RD1158

Figure 4-21

DHV11 Voltage Converter

4-34

4.8

ROM-BASED DIAGNOSTICS

4.8.1

Self-Test

4.8.1 jl General- When DHV11 or the Q-bus is reset, the DHV11’s master reset latch is set. This causes
the microcomputers to execute a DHV11

self-test sequence.

During self-test, diagnostic codes are stored in the top six words of the common RAM, and also in the top

two bytes of PROC2’s internal RAM.

At the end of self-test, control is passed to the communications firmware, which starts the initialization
‘routine. During initialization the diagnostic codes are transferred to the FIFO.
At the end of the initialization process, the master reset latch is reset, thereby clearing CSR bit 5 (MRST).
This bit is polled by the host. When MRST is cleared the host can read and interpret the diagnostic codes.
The ‘diagnostic fail’ bit in the CSR indicates whether the diagnostic program detected an error condition.
The green ‘diagnostic passed’ LED is on when the bit is cleared and vice-versa.

When a serviceable DHV11 is reset, the LED follows this sequence:
1.
2.
3.
4.

Off for about 0.03 seconds
On for about 0.2 seconds
Offfor 1 to 2.5 seconds
On permanently.

If the LED does not follow this sequence, the DHV11 is defective.

4.8.1.2 Location and Interpretation of Diagnostic Codes — Figure 4.22 shows where diagnostic
information is loaded immediately after self-test. DIAG 0 to DIAG 7 are the diagnostic bytes stored
during self-test. Diag O to Diag 7 are the same bytes which are transferred during initialization.
HEX
ADDRESS
7F

1
DIAG

DIAG 0

PHYSICAL (WORD)
ADDRESSES (HEX)

EXTERNAL RAM
LSB
MSB

PROC2
|\ oo eam

(1111

DiAG3

03FB

DIAG 2

1111 | 0001 |

Diag1

|OOOO|

03FD
03FC

03FA

| myyr

fRC;GTCH

7
Diag
6
Diag
5
Diag

HH ! 80?? |
1111 } 0010

|osre | TOPOF
EXTERNAL

DIAG 5
DIAG 4

| 0110
| 0101 |
1

1111
1111

ADDRESS = BASE+ 2
(FIFO)

Diae

Diag

D:gg3
Diag2

Diag O

[

RD1162

Figure 4-22

’

The high byte of RBUF can be interpreted as in Chapter 3, Section 3.2.2.2, except
that bits 11 to 8 are not
the line number. They indicate the sequence of the diagnostic byte. That s to say,
0 = first diagnostic byte,
1 = second diagnostic byte, and so on.
Chapter 3, Programming, explains how to interpret diagnostic codes.

4.8.2 Background Monitor Program (BMP)
Many of the regular operations by PROC1 and PROC2 are controlled by internal timers.
generate internal interrupts which vector the microcomputers to the appropriate routine.

The timers

When they are not busy with other tasks, PROC1 and PROC2 check their timer-generated interrupts.
If
there is an error, a NOGO report is passed to the host via the FIFO.
BMP can also be activated by command from the host. In this case a GO/NOGO report is passed to
the
host.
Any time the BMP finds an error, DIAG.FAIL is set in the CSR and the diagnostic LED is switched off.
The LED will stay off, even if the fault clears.

4-36

CHAPTER 5
- MAINTENANCE

5.1

SCOPE

This chapter explains the maintenance strategy and how the diagnostic programs are used to find a
defective Field Replaceable Unit (FRU). The description is supplemented by a troubleshooting
flowchart.

5.2
5.2.1

MAINTENANCE STRATEGY
Preventive Maintenance

No preventive maintenance is planned for this option. However, if the host system is being serviced, a
visual check should be made for loose connectors and damaged cables.
5.2.2

Corrective Maintenance

The M3104 module, BCO5L-xx cables, and H3173-A distribution panels are all FRUs. Corrective
maintenance is therefore based on finding and replacing the defective FRU. However, if the fault is not in
the option, it may be possible to perform tests of external equipment. Figure 5-1 can be used as a basis for

troubleshooting.

M3104

DISTRIBUTION
PANELS
H3173-A

MODEM

|—Z——|

Mmobem B——=§§—— o A
RD1164

Figure 5-1

Troubleshooting Connection Diagram
5-1

5.3
INTERNAL DIAGNOSTICS
Internal diagnostics run without intervention from the operator. There are two tests, called self-test and
background monitor test.
5.3.1

Self-Test

This test starts immediately after bus or device reset. It is a limited test, which checks the internally
accessible parts of the DHV11 and gives a GO/NOGO indication via the DIAG.FAIL bit and the
‘diagnostics passed’ LED. Self-test also reports error or status information to the host via the FIFO. This
information is used by system-based diagnostics such as CVDH??.

During a successful (no defects) self-test, the LED flashes OFF/ON/OFF before coming ON
permanently. The first OFF period is very short and may not be seen. However, if the LED goes off and
then comes on permanently, the diagnostic has found no faults. If self-test is skipped (see Chapter 3,
Section 3.3.10.3), the LED will just go on.

Because of the limitations of self-test, a correct sequence does not guarantee that all sections of the module
are good.

5.3.2 Background Monitor Program (BMP)
The BMP carries out tests on the DHV11 when the option is not engaged in other tasks. If it detects an

error, the BMP reports to the host via the FIFO. It also switches off the ‘diagnostics passed” LED.

By writing codes to the LPR, the host can cause the BMP to report the DHV11
not been detected. It is used if the host suspects that the DHV11 is dead.

status even if an error has

NOTE

More detail of the self-test and BMP diagnostics
is given in the technical description and programming sections of this manual.
54.

XXDP+ DIAGNOSTICS

In order to run these diagnostics, the host system must have at least the minimum configuration specified.
Loopback connectors will be needed for some of the tests. For more information, refer to the program
documentation at the beginning of the CVDH?? listings.

54.1

CVDHA?, CVDHB?, and CVDHC(C?

These programs form a Functional Verification Test (FVT) which runs on Q-bus members of the PDP-11
processor family. This test runs under the PDP-11 Diagnostic Supervisor. It will run standalone using the
XXDP+ monitor, or it can be run automatically under the Automatic Product Test (APT) system.
The minimum system requirements are:

Q-bus CPU
32K bytes memory
Console terminal

XXDP+ load device with Diagnostic Runtime Services (DRS) supervisor
DHV11 option.

, the diagnostic uses the fol}OWing a.ddress
In order to test the full DMA address capability of the DHV11
ns as
patterns. If the high address lines are to be tested, the host must have memory at the following locatio
well as the 32K bytes defined in the previous paragraph:

Address bits

Memory address

(High bank)

(Low bank)

This vyill not
If memory is not available at these locations, some high DMA address bits will not be tested.specifying
the
on
informati
display
can
prompt,
a
be considered as an error. The operator, by answering

bits which were tested.

and
5.4.1.1 Functions of CVDHA?- This program checks the reset and the register access functions,
reports
checks
also
It
correctly.
operating
is
host
the
and
verifies that the handshake between the DHV11
from the self-test and BMP.

Loopback connectors are not used in this test.

5.4.1.2 Functions of CVDHB? — This program checks the major communication functions of the
DHV11. It verifies the correct operation of modem control signals and the register bits which control and
report them. CVDHB? does not perform extensive data transmission and reception tests.
Loopback connectors can be used in this test.

5.4.1.3 Functions of CVDHC? — This program checks the major communication functions which
use the DUARTS. It checks split-speed operation, and verifies that DUART errors are reported correctly.
Extensive data transfer tests are performed in both DMA and single-character modes. CVDHC? also
includes a keyboard test.

Loopback connectors can be used in this test.
DECX/11 Exerciser

5.4.2

When a DHV11 or other option is installed or replaced, it is necessary to run the DECX/11 exerciser
CXDHVxx. The exerciser must first be configured to match the host system. For more information, refer
to the DECX/11 User Manual (AC-FO35B-MC) and DECX/11 Cross-Reference (AC-FO55C-MC).

" DECX/11 should not be run until all modules have passed their own diagnostic tests. Therefore, before
running the exerciser, the DHV11 must pass all phases of CVDH??.
5.5

DIAGNOSTIC SUPERVISOR SUMMARY

The CVDH?? diagnostics have been written for use with the Diagnostic Runtime Services (DRS)
supervisor. DRS, which provides the interface between the operator and the diagnostic programs, can be

used with load systems such as ACT, APT, SLIDE, XXDP+, and ABS loader. By answering prompt
questions supplied by the supervisor the operator can define the following:
1.
2.

The hardware configuration of the DHV11s being tested
The type of test information to be reported

The conditions under which the test should be terminated or continued.

5-3

Loading the Supervisor Diagnostic

5.5.1

The diagnostic program may be loaded and started in the normal way, using any of the supported load
systems. For example, using XXDP+, the program CVDHBA.BIN is loaded and started by typing
R CVDHBA.

The diagnostic and the supervisor will be loaded and the program started. The program types the following
message:

CVDHBA.BIN
DRSC7
CVDHB-A-0
DHV-11 FUNCT TEST PART2
UNIT IS DHV-11
RESTART ADDR: xxxxxx
DR>

DR>> is the prompt for the diagnostic supervisor routine. At this point a supervisor command must be
entered (supervisor commands are listed in Section 5.5.3).

AO on the end of CVDHB indicates the revision level (A) and the patch level (0).
5.5.2

Four Steps to Run a Supervisor Diagnostic
1.

Enter the start command.
When the prompt DR> is issued, type:

STA/PASS:1/FLAGS:HOE<CR>
The switches and flags are optional.
Answer the hardware parameter questions.
The program prompts with:
CHANGE HW?

You must answer Y to this query if you want to change the hardware parameter tables. The
program will then ask a number of hardware parameter questions in sequence. For example,
the first question is:
# UNITS?

At this point, enter the number of units to be tested.
NOTE

Some versions of the diagnostic supervisor do not
ask the CHANGE HW? question at the first start
command. Instead they go straight into the hard-

ware parameter question sequence.

The answers to the questions are used to build hardware parameter tables (P-tables) in memory. A series
of questions is posed for each device to be tested. A hardware P-table is built for each device.
5.4

Answer the software parameter questions.

When all the hardware P-tables are built the program responds with:
CHANGE SW?

If other than default parameters are wanted for the software, type Y. If the default parameters
are wanted, type N.

to these will be
If you type Y, a series of software questions will be asked and the answers
only once,
asked
be
will
ns
questio
e
entered into the software P-table in memory. The softwar
regardless of the number of units to be tested.
Diagnostic execution

After the software questions have been answered, the diagnostic starts to run.

What happens next is determined by the switch options selected with the start command, or
errors occurring during execution of the diagnostic.

5.5.3

Supervisor Commands

The supervisor commands that may be issued in response to the DR> prompt are as follows:
START

Starts a diagnostic program

RESTART

When a diagnostic has stopped and control is given back to the supervisor,

CONTINUE

Allows a diagnostic to continue running from where it was stopped

PROCEED

Causes the diagnostic to resume with the next test after the one in which it

this command restarts the program from the beginning

halted

EXIT

Transfers control to the XXDP+ monitor

DROP

Drops units specified until an ADD or START command is given

ADD

Adds units specified. These units must have previously been dropped

Prints out statistics if available

DISPLAY

Displays P-Tables

FLAGS

Used to change flags

ZFLAGS

Clears flags.

All of the supervisor commands except EXIT, PRINT, FLAGS, and ZFLAGS can be used with switch
options.

5.5.3.1

Command Switches

Switch options may be used with most supervisor commands. The available switches and their functions

are as follows:

/TESTS:

Used to specify the tests to be run (the default is all tests). An example of the
tests switch used with the start command to run tests 1 to 5, 19, and 34 to 38
would be:

DR> START/TESTS:1-5:19:34-38<CR>

/PASS:

Used to specify the number of passes for the diagnostic to run. For example:
DR> START/PASS:1<CR>

In this example, the diagnostic would complete one pass and give control

back to the supervisor.

/EOP:

Used to specify how many passes of the diagnostic will occur before the end

/UNITS:

Used to specify the units to be run. This switch is valid only if N was entered

/FLAGS:

Used to check for conditions and modify program execution accordingly.

of pass message is printed (the default is one).
in response to the CHANGE HW? question.

The conditions checked for are as follows:

‘HOE

Halt on error (transfers control back to the supervisor)

:JER

Inhibit error reports

:PNT

Print the number of the test being executed before execution

:LOE

:IBE
IXE
:PRI

:BOE

:UAM
:ISR

:JIOU

Loop on error

Inhibit basic error information
Inhibit extended error information
Print errors on line printer
Ring bell on error

Run in unattended mode, bypass manual intervention tests
Inhjbit statistical reports

Inhibit dropping of units by program.

Control/Escape Characters Supported

5.5.4

The keyboard functions supported by the diagnostic supervisor are as follows:

Returns control to the supervisor. The DR> prompt would be typed in

CTRL/C("C)

CTRL/Z ("Z)

Used during hardware or software dialogue to terminate the dialogue and

CTRL/O (®O)

Disables all printouts. This is valid only during a printout.

CTRL/S("S)

Used during a printout to temporarily freeze the printout.

CTRL/Q ("Q)

Resumes a printout after a CTRL/S.

response to CTRL/C. This function can be typed at any time.
select default values.

5-6

ss
Two examples of diagnostic printouts follow. The first is error-free. In the second test, the device addre
Example Printouts

5.5.5

is incorrect.

ine without an entry shows that the operator has presse
Entries by the operator are underlined. An underler.
the RETURN key to select the default paramet
1.

Error-free pass
R _CVDHBA
CVDHBA.BIN
DRSC7

CVDHB-A-0

DHV-11 FUNCT TEST PART2
UNIT 1 IS DHV-11
RESTART ADDR: 147670
DR>START

CHANGE

2 ¥

2 1

(D)

#UNITS
UNIT

(L)

CSR ADDRESS: (0) 160460 ? 160500
INTERRUPT VECTOR ADDRESS: (0) 300 ?__
ACTIVE LINE BIT MAP: (0) 3772_

TYPE OF LOOPBACK

2=STAGGERED,
3=25 PIN CONNECTOR, 4=MODEM):

(1=INTERNAL,

INTERRUPT BR LEVEL:
CHANGE

(L)

(0)

? ¥

REPORT UNIT NUMBER AS EACH UNIT IS TESTED:

(L)

Y ?__

NUMBER OF INDIVIDUAL DATA ERROR TO REPORT ON A LINE:
CVDHB

EOP

CUMULATIVE ERRORS

DR>EXIT

2 ?2__

(D) 0 ?

Test with wrong device address selected
R

_CVDHBA

CVDHBA.BIN
DRSC7

CVDHB-A-0

DHV-11 FUNCT TEST
UNIT IS DHV-11
RESTART

ADDR:

PART2

147670

DR>START

CHANGE

#UNITS
UNIT

(L)

(D)

2?2 ¥

? 1

CSR ADDRESS:
(0) 160460 ? 160500
INTERRUPT VECTOR ADDRESS:
(0) 377 ?2__
ACTIVE LINE BIT MAP:
(0) 377 ?2__
TYPE OF LOOPBACK (1=INTERNAL, S=STAGGERED,
3=25PIN CONNECTOR, 4=MODEM):
INTERRUPT

LEVEL:

CHANGE

(L)

REPORT

UNIT

(0)

?2___

?__

NUMBER

EACH

UNIT

TESTED:

(L)

?2__

NUMBER OF

INDIVIDUAL DATA ERRORS TO REPORT ON A LINE

(D)

CVDHB DVC

FTL

PC:

021354

DEVICE
BUS

ERROR

00101

TIME-OUT

TRAP

UNIT

TST

001

SUB

000

2__

ERRORS

CAUSED

READ

ATTEMPT

BUS TIME-QUT TRAP CAUSED BY WRITE ATTEMPT
DHV MAY BE AT THE WRONG Q-BUS ADDRESS.

UNIT
PASS

CVDHB
1

DROPPED FROM

ABORTED

FOR THIS

EOP
1
CUMULATIVE

FURTHER TESTING

UNIT

ERRORS

DR>

5.6

CORRECTIVE MAINTENANCE ON MICROVAX I SYSTEMS

Corrective maintenance is performed when operational failures or diagnostic tests indicate that the
DHV11 is defective. Diagnostic test programs for DHV11s installed in MicroVAX I systems are listed
below.

EHKMV

Macroverify-MicroVAX Systems Test

EHXDH

DHV11 Tests

5.6.1 The Macroverify Diagnostic
Macroverify is a system test which is quick to run, and is used:
e

As afirst-line check before using device diagnostics

e
e

As a confidence check
To verify the complete system after installation or maintenance.

5-8

the CPU Tests diskette is
a standalone basis and operates when
The Macroverify diagnostic runs on. The
program takes up to four minutes to run and needs 30K bytes of
booted from one of the RX50 drives
memory.

The tests performed by Macroverify do not destroy information recorded on the disks.
drives for
upall devices in the configuration. Set all the disk
5.6.1.1 Setting Up Procedures — PowerDiscon
the
tors
nect any external cables or test connec from
I/O. Place a diskette in each RX50 drive. the system
a
output
will
erify
is not set up correctly, Macrov
DLVJ1 and DHV11 distribution panels. If
TEST FAILED message.

5.6.1.2 Bootstrapping Procedure — To boot the Macroverify diagnostic, mount the CPU Tests
diskette in one of the RX50 drives and type:
or:

B DUALI

(boot from drive 1)

B DUA2

(boot from drive 2)

completed
5.6.1.3 Macroverify Operation — Macroverify runs as soon as the boot operation is ions.
successfully. The program contains routines which check for all possible system configurat
For each possible device, a test is made to see if the device responds to its assigned Q-bus address. If the
device does not respond, the following status message is displayed on the console.
DEVICE xxxxx WITH CSR yyyyyy, VECTOR zzz NOT FOUND.
NO TESTING PERFORMED.

NOTES

The vector number will not be displayed for

The standard address and vector are 7604403
and 300g respectively, but early versions of
Macroverify expect the address to be 760500g.
The status message will be displayed even if
the DHVI11 is configured correctly. Later
versions of Macroverify test the DHVI11 at
the standard address of 760440 vector 300.
Note that, if other floating address devices
are installed, the DHVI11 address will be
moved within the floating address space, and
will not be recognised by Macroverify.

devices with floating vectors.

For each device that responds to its assigned address, a sequence of user-level tests is performed. A ‘test
succeeded’ or ‘test failed’ message is displayed, together with the time taken for a successful test.
5.6.2

DHVII Diagnostic EHXDH

The EHXDH diagnostic is resident on the MicroVAX system tests diskette number 3. This diagnostic
runs under VDS, and should be run if an operational failure or the Macroverify program indicates a
defective DHV11.

5-9

5.6.2.1
Setting Up Procedures — Before running the diagnostic, make sure that the address and
vector are correctly set up, as described in Chapter 2, Sections 2.3.1 and 2.3.2.
Disconnect all external cables from the distribution panel.

5.6.2.2

Bootstrapping Procedures — To boot from the MicroVAX system test diskette, mount

diskette 2 on drive O of the RX50 drive, and diskette 3 on drive 1 of the RX50.
NOTE

The DHV11 diagnostic is contained on the third
diagnostic diskette. This diskette does NOT contain
a bootable diagnostic monitor. Therefore, the
user must boot diskette 2 on drive 0, and load the
diagnostic from diskette 3 on drive 1.

The diagnostic can now be booted in the manner described in the first example of the test format.
Examples of the test format are shown in the following pages. Operator inputs are underlined in the
examples.
>>> B/10 DUAl
ATTEMPTING BOOTSTRAP
VAX DIAGNOSTIC

SOFTWARE

PROPERTY OF

DIGITAL

EQUIPMENT CORPORATION

** CONFIDENTIAL AND PROPRIETARY **
Use Authorized Only Pursuant To A Valid Right-to-use License

DIAGNOSTIC SUPERVISOR.

ZZ-EHSAA-V6.13-001

1-JAN-1983 00:00:03

DS> ATTACH RX50

Device Link? DUA
Device Name?

DUA2

DS> SET LOAD DUA2:

The above sequence enables diskette 3 mounted in drive 1 (logical device DUA2)
How to Call Up the Directory for This Diagnostic
DS> DIR

Directory DUA2:[SYSO.SYSMAINT]
EHXDH.EXE; 1

EHXDH .HLP;1

EHXVS.EXE;1l

EHXVS.HLP;1

EVRMA.EXE;1

EVRMA .HLP;1

EVRMB.EXE; 1

EVRMB.HLP;1

EVRMC.EXE;1

EVRMC .HLP; 1

Total of

10 files

5-10

g the

Several test options are available to the user. Details of these options may be obtained by runnin

diagnostic HELP file.

Example of Running a HELP File
DS> HELP EHXDH

HELP

The DHV1l is an asynchronous multiplexer that provides an
interface between eight asynchronous serial data communications
channels and any processor that supports Q 22 bus devices.

It 1is
EHXDH is the name of the MICRO VAX Standalone Diagnostic.
VAX
MICRO
a
to
bus
22
Q
via
ed
connect
to be used to verify that a DHV1l
system

functioning

correctly.

Additional information available:

'HELP
OPTIONS

SECTIONS

RUN_TIME
EVENT_FLAGS
Errors

REQUIREMENTS
SUMMARY
TEST_DESC

PREREQUISITES
DEVICE

ATTACH_DHV11
QUICK

How to Attach, Load, and Start a DHV Diagnostic at Standard Address and Vector
DS> LOAD EHXDH

DS> ATT DHV11
Device Link? HUB

Device Name? TXA
Device Address? 760440
Vector Address? 300
BR Level? 4
DS> SEL TXA:

5-11

Example of Running an Internal Test
DS> START

.. Program: DHV1l - VAX Functional Verification Test, revision 1.0, 29 tests,
at 00:02:30.28.
Testing:

_TXA

lines to test [(ALL) or 0,1,2,...7] <RET>

Line

Speed

7200, 9600,

[(4800), 50, 75, 110, 134.5, 150, 300, 600, 1200, 1800, 2000, 2400,

19200, 38400] 9600

loop type [(INTERNAL), EXTERNAL, STAGGERED] <RET>
Micro Processor number 1 ROM version is 2
Micro Processor number 2 ROM version is 2

Frame error bit not tested; wrong looptype.
.. End of run, O errors detected, pass count is 1,

(This is not an error)
(Successful pass)

1-JAN 1983 00:06:28.40

time is

Example Showing Sections Available for the EHXDH Diagnostic
DS> HELP EHXDH SEC

SECTIONS

There two sections supplied with this diagnostic;
¢

MODEM

ECHO

The modem Ssection runs a modem loopback test and is

by using the vds command ST/SE=MODEM.

invoked

The ECHO section allow a user to select a line with a
terminal attached. All characters typed on the terminal will be
checked for errors, then echoed back to the terminal.
Example Showing the Options That Are Available
DS> HELP EHXDH OPT
OPTIONS

Additional information available:
LINES TO_TEST

BAUD_RATE

LOOP_TYPE

5-12

Example Showing the Tests Available for the EHXDH Diagnostic
DS> HELP EHXDH TEST

TEST_DESC

Additional information available:
Test
No.
1.

Test Description

Device Register Address Test. This test verifies that the UUT will respond to the proper
Q-bus handshaking when accessed. Line O only is tested.

Master Reset/Self-Test Test. This test verifies that the self-test is operational.
Master Reset/Skip Self-Test Test. This test verifies that the master reset bit clears within a
short time after it is set, if the Skip Self-Test sequence is used. The test verifies that the Skip
Self-Test return codes are normal.

Diag Field (BMP) Test. This test verifies that a request for BMP code reporting is answered

by the UUT within the specified time.

Self-Test Forced Failure Test. This test verifies that the self-test will report errors correctly
when it is forced to fail. The test verifies that the diagnostic fail bit will go to the active and
inactive states.

ROM Version Printout Test. This test reports the versions of numbers of the 8051 ROMS.
Register Address Test. This test verifies that the indexed registers can be uniquely addressed.
ID Bit Test. This test verifies that the identity bit which determines whether the device is a

DHUI11 or a DHVI1 is either set (DHUI11) or clear (DHV11).

Tx Enable/Action. This test verifies that if a data word is written without the Tx data bit set, no
Tx action is generated.
10.

Rx Data Available/Rx Data Valid/Rx Enable Test. This test verifies the following.
e

That all relevant bits are initialized correctly

That Rx DATA AVAILABLE and Rx DATA VALID remain clear if a character is

transmitted with Rx ENABLE clear

That Rx ENABLE sets and clears data and on the current line only

That Rx receives data and on the current line only

.
°

That Rx DATA AVAILABLE is cleared when the buffer is read, but that Rx DATA

VALID remains set until the FIFO is empty

That transmitted data is correct and that no errors have occurred

5-13

11.

12.

Maintenance Mode Test. This test verifies that the maintenance modes are working correctly.

The test will operate only if staggered loopback is selected.

Rx FIFO Test. This test verifies that the FIFO locations can be uniquely addressed from the
Q22 bus. The FIFO is filled with 256 unique bytes of data, and is then checked for data
integrity.

13.

Interrupts Test. This test verifies that the Tx and Rx interrupts are operating correctly.

14.

DMA Start/ DMA Abort Test. This test verifies that each DMA start bit will initiate a DMA
Tx on a line, that it can be aborted and resumed, and that DMA aborts and that completions
cause interrupts.

15.

Byte Count Register Test. This test verifies that the byte count registers function correctly, by
checking that the number of bytes received is the same as the number of bytes transmitted.

16.

DMA Address/Data Test. This test verifies the ability of the device to correctly increment
addresses and byte counts.

17.

Speed Test. This test transmits characters at all speeds on all lines in internal loopback mode,

using the Tx FIFO to transmit characters.

Test. This test verifies that X-ON/X-OFF control is functioning correctly.

18.

XON/XOFF

19.

Data Format Test. This test verifies that all sizes and formats function correctly. Ten

20.

characters are used and each line is verified.

Modem Signal Test. This test verifies that changing the UUT line control DTR bit affects the
state of the DTR control line and looped signals, and verifies that no unexpected bits are set.
The test also verifies that changing the UUT line control RTS bit affects the state of the RTS
control line. Provision is made for testing the ability of the modem to connect to another
modem.

21.

22.

23.

Framing Error/Break Bit Test. This test verifies that forced framing errors are reported

correctly.

‘

Parity Generation/Detection Test. This test verifies that parity works correctly and that

parity errors are reported. The test functions only in staggered loopback.

Overrun Detection Test. This test verifies that the UUT will receive the maximum number of
characters without causing an overrun error, and that the receipt of one more character will
cause an overrun error.

24.

Exerciser Test. This test causes all lines to transmit simultaneously. 1024 byte buffers are used
for transmission and reception. The format is 8 bit, no parity, and 1 stop bit.

5-14

25.

26.

Modem Loop Test. This test is run on amodem in loopback mode, oris runon a remote modem

that is in remote loopback mode.

received on a line. The
Terminal Echo Test. This test loops back all characters that arewill
permit isolation of the
this
echoed;
be
operator is asked to which line the characters are to
direction of a failing line.

28.

LAUTO Test. This test verifies that the LAUTO bit is functioning correctly.
Split Speed Test Part A. This test verifies the correct functioning of split speed operation. The

29.

Split Speed Test Part B. This is a continuation of the previous test.

217.

test operates only in staggered loopback mode.

Running Two Passes of the Diagnostic Staggered Loopback Test

Remove the ribbon cables from the distribution panel and connect them to the H3277 test connector, as
shown in Figure 2-5.

DS> START/PASS=2

.. Program: DHV1l - VAX Functional Verification Test, revision 1.0, 29 tests,

at 00:09:30.42.
Testing: _TXA

lines to test [(ALL) or 0,1,2,...7] <RET>
Line Speed [(4800), 50, 75, 110, 134.5, 150, 300, 600, 1200, 1800, 2000, 2400,
7200, 9600,

19200, 38400] 9600

loop type [(INTERNAL), EXTERNAL, STAGGERED] STAGGERED
Micro Processor number 1 ROM version is 2
Micro Processor number 2 ROM version is 2

.. First pass done, O errors detected, time is

1-JAN-1983 00:14:38.06

Micro Processor number 1 ROM version is 2
Micro Processor number 2 ROM version is 2

.. End of run, 0 errors detected, pass count is 2,
time is

1-JAN-1983 00:19:05.14

Restore the ribbon cables to their original positions in the distribution panel. See Figure 2-5.

5-15

The following example is the single loopback test with the H3277 loopback connector on line 0 of
the distribution panel (see Figure 2-5)
DS> START

.. Program: DHV1l - VAX Functional Verification Test, revision 1.0, 29 tests,
at 00:30:19.98.
Testing:

_TXA

lines to test [(ALL) or 0,1,2,...7]1 O
Line Speed [(4800), 50, 75, 110, 134.5, 150, 300, 600, 1200, 1800, 2000, 2400,
7200, 9600, 19200, 38400] <RET>

loop type [ (INTERNAL), EXTERNAL, STAGGERED] EXTERNAL

Install all H325 turnaround connectors, type RETURN key when done [(No), Yes]

<RET>

Micro Processor number 1 ROM version is 2
Micro Processor number 2 ROM version is 2

Frame error bit not tested; wrong looptype.

.. End of run, 0 errors detected, pass count is 1,
time is

(This is not an error)

1-JAN 1983 00:33:02.17

Remove all the test connectors, and reconnect the terminals if they have been removed for test purposes.

The following example is of the terminal echo test line 0. Any character typed on the terminal will be
echoed.

This test can only be effective if an additional VDU and cable are available.
DS> START/SEC=ECHO

.. Program: DHV1l - VAX Functional Verification Test, revision 1.0, 29 tests,
at 00:33:38.60.
Testing:

_TXA

lines to test [(ALL), or 0,1,2,...7]1 O

Line

Speed

[(4800), 50, 75, 110, 134.5, 150, 300, 600, 1200, 1800, 2000, 2400,

7200, 9600, 19200, 38400] 9600

"“C

5-16

The following test example shows errors
> START

.. Program DHV1l - VAX Functional Verification Test, revision

1.0, 29 tests,

at 00:22:17.95.

Testing: _TXA

lines to test [(ALL) or 0,1,2,...71 0 5, 150, 300, 600, 1200, 1800, 2000, 2400,

110, 134.
Line Speed [(4800), 50,0] 75,
9600
7200, 9600, 19200, 3840

GERED] EXTERNAL
loop type [(INTERNAL), EXTERNAL, STAGrs,
type RETURN key when done [(No), Yes]

Install all H3277 turnaround connecto
YES

Micro Processor number 1 ROM version is 2
Micro Processor number 2 ROM version is 2

on Test - 1.0 jalalialalalole
axwxxx%% DHV1l - VAX Functional Verificati
00:24:56.18
pass 1, test 18, subtest 1, error 15, 1-JAN-1983
failed
Hard error while testing TXA: XON/XOFF Test

current line number =

xxxxkrxx

End of Hard error number 15 ***xx¥xx*

‘*#xx¥x*
wxxe#xxxx DHV1l - Vax Functional Verification Test - 1.0 06.66
00:25:
Pass 1, test 20, subtest 1, error 16, 1-JAN 1983
Hard error while testing TXA: Modem Signal Test failed

Current line number =

xxxxxxx*

End of Hard error number 16 ******»x

xxxxxxx%* DHV1l - VAX Functional Verification Test - 1.0 *»**x¥**
Pass 1, test 20, subtest 1, error 22, 1-JAN-1983 00:25:15.74
Hard error while testing TXA: Modem Signal Test failed

Current line number = 0

xxxexxx*x

End of hard error number 22 *****¥**

(RAEEERER
TR DHV1l - VAX Functional Verification Test - 1,0 24.87
00:25:
Pass 1, test 20, subtest 1, error 35, 1-JAN-1983
Hard error while testing TXA: Modem Signal Test failed

Current line number =

wxxxxxxxx

End of Hard error number 35 **xxkxxx

5-17

Frame error bit not tested; wrong looptype.

kkdkxx**xx

DHY1]1 - VAX Functional Verification Test — 1.0

Pass 1, test 21, subtest 1, error 3,

(*¥*xdk*x

1-JAN-1983 00:25:36.46

Hard error while testing TXA: Framing Error/Break Bit Test failed
Current line number = 0

*xxxxxx*x

pnd of Hard error number 3 *Xxd**kxx

*kxkk%x*

DHY1] - VAX Functional Verification Test = 1.0

(***kkwxx

1-JAN-1983 00:25:54.65
Pass 1, test 24, subtest 1, error 8,
Hard error while testing TXA: Exerciser Test Failed

Current line number =

pnd of Hard error number § ***x*x*x*

xxxxxxxx

*xxkkxxxx DHY11 - VAX Functional Verification Test — 1.0 (*¥x**k*x
1-JAN-1983 00:26:04.10
Pass 1, test 27, subtest 1, error 9,
Hard error while testing TXA: I.auto test failed

Current line number = 0
|

End of Hard error number 9 ****xxxx

*xwxxxix

.. End of run, 7 errors detected, pass count is 1,
time is

1-JAN-1983 00:26:12.89

DS>

5.7

RUNNING MICROVAX II DIAGNOSTICS

These diagnostics are entirely different from MicroVAX 1 diagnostics in that they are based on

VAXELN, and not on the VAX diagnostic supervisor as in MicroVAX L
Overview of the MicroVAX II Maintenance System

5.7.1

The MicroVAX II Maintenance System (MMS) is a menu-driven maintenance and diagnostic system
X Diagnostic Monitor (MDM). MMS is booted from an RX50 diskette drive, or
which uses the MicroVA
from a TK50 tape drive. MMS is available in two versions.
e

The customer version packed with each system

The service version which is available to the customer under license

5-18

the same main menu, but only the maintenance version contains full
The two versions share
troubleshooting and maintenance capabilities.
eted,
The loading procedure is the same for both versions. After the power-on preliminaries have compl
there is a countdown sequence before the main menu is displayed.

the MicroVAX II Diagnostic
5.7.2. Running the Customer VersioninofSecti
on 5.7.3 for the service version, but selection from the

ibed
The customer will proceed as descr
4 are not available. Normally the customer will select option 1to
and
3
ns
optio
and
main menu is limited,
test the system.
message is output to the
version of the diagnostics, an errorDEC
If there is a failure during the custotomer
trained staff.
from
d
neede
consider whether help is
terminal. The user may then want

MicroVAX II Diagnostic
5.7.3 Running the Maintenance Version ofallthefixed
disk drives are off-line, and that the doors to all

When booting from the TK50, make sure thattakes about three minutes.
diskette drives are open. Booting the TK50

If the halts are disabled before the system is powered ON, MMS will automatically boot.
appear when the system is powered
If the halts are enabled on the MicroVAX II system, the prompt will
ds
on. To boot the MMS under these conditions, enter the comman after the prompt as follows.
>>> b DUAx

(where x is the number of the disk drive containing the MMS)
>>> b MUAx

(where x is the number of the tape drive containing the MMS)

After bqoting, a disclai_rr}er message appears on the screen, together with copyright and license
%nformatlon, and the revision level of MMS. The revision level is important because the newer levels
include testing for additional options.

An example of the format now follows. Operator inputs are underlined.

5-19

>>> B DUA2

KA630-A.V1.0

Performing normal

system tests.

7..6..5..4..3..
Tests completed.

Loading system software.
2..1..0..
VAXELN Vv2.,0-00

MicroVAX

Maintenance

System

MDM Version 1.02

CONFIDENTIAL DIAGNOSTIC SOFTIWARE
PROPERTY OF
DIGITAL

EQUIPMENT CORPORATION

Use Authorized Only Pursuant

(c)

to a Valid Right-to-use

1985

Digital Equipment Corporation
Current date and time

is:

17-NOV-1985

15:30:11.64

Press the RETURN key to continue,

OR enter new date and

time,

then press

the RETURN key.

[DD-MMM-YYYY HH:MM]: <RET>

MAIN

Test

the

Show

system configuration and devices

Display the Utilities Menu

Display the Service Menu

Exit MicroVAX Maintenance System

Type the number,

system

then press

the RETURN key.

5-20

> 2

License

SYSTEM CONFIGURATION AND DEVICES
SYSTEM CONFIGURATION

CPUA ... MicroVAX CPU

KA630-AA 1MB, FPU MOO HOO
MEMA ... MicroVAX memory system
3 megabytes. 6144 Pages.

KA630 ... CPU module, 1MB on-board memory.

MS630-BA ... Quad height memory module, 2MB.

RODXA ... Winchester/floppy disk controller.
Revisions =94 and 6

RX50 ... Floppy disk drive.

... Cannot identify drive, Offline.
TK50A ... Cartridge Tape Controller
DEQNAA ... Ethernet controller.
08-00-2B-02-08-9D

DHV11A ... 8 line asynchronous multiplexer
ROM Rev 11 9

Press the RETURN key to return to the previous menu. > <RET>
>

MAIN

MENU
1

Test the system

2 - Show system configuration and devices

3 - Display the Utilities Menu

4 - Display the Service Menu

5 - Exit MicroVAX Maintenance System

Type the number,

then press the RETURN key. > 4

5-21

SERVICE MENU

CAUTION:

This menu

intended for

]

Exercise

Display the device menu

- Enter

service

could destroy data.

system continuously

system commands

Type the number,
OR type 0 and

use by qualified

the commands

test message and parameters

Set

Misuse of

1 -

personnel only.

then press the RETURN

Press

the RETURN key to

Kkey,
return

the main menu.

> 4

SERVICE MENU
ENTER SYSTEM COMMANDS

CAUTION:

You are entering the MicroVAX Diagnostic Monitor

via the command
enter

line processor.

the monitor.

Refer

(MDM)

There are no menus once you

to the MDM User's Guide for detailed

instructions.

To return to the Main Menu

from

the MicroVAX Diagnostic Monitor

type "RESTART" and press the RETURN key,

Press

the RETURN key to enter

OR type 0 and

Press

or reboot the system.

the MicroVAX Diagnostic Monitor,

the RETURN key to

return

5-22

to the Main Menu.

> <RET>

MDM>>

HELP

Current Commands Are:

Configure System

CONFIGURE
SELECT Diag_Name
ENABLE Diag_Name

Select diagnostic (all units) to run

Allow a diagnostic to run

Prevent a diagnostic from running

DISABLE Diag_Name

SET

DETAILED MESSAGE ON

Display detailed messages

MODE VERIFY

Set verify mode tests
Set service mode tests

DETAILED MESSAGE OFF
SERVICE

Print no progress messages
Controller progress messages

PROGRESS OFF
PROGRESS BRIEF
PROGRESS FULL

Controller and test progress messages

SECTION FUNCTIONAL
UTILITY
EXERCISER
ALL

TEST

DO NOT display detailed message

Set functional test section
Set utility test section
Set exerciser test section
Run all tests

Run only test number xx

Number

Run tests for xXx passes

PASSES Number

Start selected tests running

START

Start all tests running
show configuration information
Show default settings

START ALL

SHOW CONFIGURATION
SHOW DEFAULT

SHOW DEVICE UTILITIES
SHOW ERRORS

Show utility titles

Show reported errors

CONFIG

CPUA

Enabled

KA630-AA 1MB, FPU MOO HOO

MEMA

Enabled

3 megabytes.

SHOW CONFIG

DEQNAA
DHV11A

RQDXA

Enabled

TK50A

Enabled

Enabled
Enabled

6144

08-00-2B-02-08-9D
ROM Rev 11 9

MDM>> SEL DHV11A
MDM>> ENA DHV11A

MDM>> SHOW DEV UT

DHV11A 8 line asynchronous multiplexer
1 - Transmit Pattern Test
Terminal Echo Test

Pages.

Revisions =94 and 6

Bulkhead Loopback Test

5-23

MDM>>

SHOW DEF

Selected Device:
6

DHV11A

Enabled

Mode is

SERVICE

Section

ROM Rev

FUNCTIONAL

Number of passes

is:

No time limit
Tests

to be run:

ALL

Continue on error

Detailed message is

Off

Progress message

Off

MDM>> START

Please ao

the

following

Open the Backpanel

Disconnect

from the

flat ribbon cables.

See DHV1l Technical Manual

...

Thank you for attaching the

loopback H3277

connector.

SET DET ON

MDM>> SET PROG FULL
START
Pass

number

DHV11A DSL

Pass

number

DHV11A DSL

Pass

number

DHV11A DSL

Pass

number

DHV11A DSL

Pass number

Test number
Test number
Test
Test

number

Test

number

Cables A and B passed Functional
DHV11A ended with no

test

number

errors

MDM>>

5-24

wN -

started by MDM

DHV11A DSL

DHV11A

MDM>>

for

1-6.

Hit return when finished

MDM>>

DHV1l

loopback connector between the

ribbon cables.

illustration PG.

things:

the MicroVax.

the bulkhead

Place the H3277
two flat

When all tests have been completed
On completing the test sequence with zero errors:

5.8

Remove the diagnostic media and store it in a safe place

Restore the system configuration.

FIELD REPLACEABLE UNITS (FRUs)

The FRUs are:

Reference No.

Item

M3104
BCO5L-xx
H3173-A
H3277
H325

Quad-height module
Flat cable, 40 conductor
Distribution panel
Staggered loopback test connector
Line loopback test connector

The last two items do not affect the operation of the system.

Depending on local maintenance strategy, modems and/or external cables may also be FRUs. See Figure
5-1.

TROUBLESHOOTING FLOWCHART

When troubleshooting is necessary, the flowchart sequence of Figure 5-2 should be used as a guide.
The flowchart is based on the CVDH?? diagnostics. Note that CVDHA? has no loopback mode.
5.10

COMPONENT REPLACEMENT

The M3104 module is a multilayer fine-line-etch PCB. Only the microcomputers, which are on sockets,
can be replaced in the field. This should only happen if the firmware is updated.

5-25

INSTALLING
OR REPLACING

YES

MODULE
?

WORKING CONFIG
RUN TEST
(INTERNAL LOOP)

YES

REPLACE

DHV11

ERROR?
\

ol O

NO LOOPBACK
MODE

NOTE:
CVDHA? HAS

CONFIG A
RUN TEST
(STAGGERED)

ERROR?

YES

CONFIG C

RUN TEST

(STAGGERED)

—»@

CONFIG B
RUN LINE LOOPBACK
TEST FOR EACH

LINE

ERROR?

YES

REPLACE

H325

REPLACE

ASSOCIATED
DIST. PANEL
(3173-A)

‘

[

y
DHV11 O.K
DO YOU WANT TO
TEST LINES?

ves | | EXTERNAL
LINE CHECKS
USING MODEM
LOOPBACK TEST

"NO

WORKING CONFIG.

RUN SYSTEM

EXERCISER

NOTE:

THIS FLOWCHART ASSUMES THAT THE SYSTEM IS INITIALLY
IN THE NORMAL WORKING CONFIGURATION

RD2343

Figure 5-2

Troubleshooting Flowchart

5-26

(1)

REPLACE
CABLE
v

LOW CHANS TO

REPLACE

DHV11

CABLE
X

FIRST

TIME THIS
LOOP?

REPLACE
H3277

3173-A

LOW
CHANS

H325

0-3

‘

0
1

3
=

H3277

HIGH
CHANS
4-7
|

5
6

CONFIGURATION A

CONFIGURATION
B

CONFIGURATION C
RD1562

Figure 5-2

Troubleshooting Flowchart (Cont)

5-27

APPENDIX A
IC DESCRIPTIONS

SCOPE
in the DHV11. The
x contains data on the 8051 microcomputers and other LSI chips used
appendi
This
not included. For
are
books,
e
referenc
smaller common ICs, which are well described in standard
data sheets.

A.l

information not included in this document, read the appropriate manufacturer’s
A.2
A.2.1

8051 MICROPROCESSOR/MICROCOMPUTER
8051 Block Description

The 8051 is a microcomputer based on the Intel 8048. Its configuration is programmable. The block
diagram is shown in Figure A-1.
FREQUENCY

COUNTERS

REFERENCE

OSCILLATOR

4096 BYTES

TIMING

ROM

gos1
CPU

4
BUS
64K-BYTE
EXPANSION

INTERRUPTS

PROGRAMMABLE
SERIAL PORT

FULL DUPLEX
* FULL

PROGRAMMABLE 1/0

¢ SYNCHRONOUS

T
CONTROL

SHIFTER

I
INTERRUPTS

T
TIMER/EVEN
COUNTERS

DATA MEMORY

MEMORY

AND

TWO 16-BIT

128 BYTES

S OGRAN

CONTROL

PARALLEL PORTS,

ADDRESS/DATA BUS,

[

SERIAL
IN

B
SERIAL
ouT

AND 1/0 PINS

RD1166

Figure A-1

8051 Block Diagram

A-1

As well as having 128 bytes of RAM for register space, stack, and data memory, the IC contains:
4K bytes of program memory ROM
Two 16-bit programmable timer/counters

A full-duplex programmable serial UART capable of data rates up to 1 M bits/s
32 programmable 1/O lines arranged as four 8-bit ports.

Other features not indicated in the diagram are:
e

Single +5 V supply

64K bytes program memory and 64K bytes data memory addressing capability

Up to 128 bytes stack

Four 8-byte register banks

Two-level interrupt system with programmable priority. Interrupts may also be triggered by the

Byte or bit addressing capability.

A.2.2

counter/timers.

Configuration

Figure A-2 provides more information on how the 8051 can be configured. It also gives pinout details.
RST/VPD

VSS VCC

| l

XTAL1

__L_>

2
L T <_>T 8

B
° |

TXD<— |

INTO —»~ | <>

L;< NTT

3051

ADO

381 Po.1

AD1

.
37 ] PO.2

AD2

P1.4 []5

361 PO.3 AD3
PO.4

AD4

P15 C]6

Ppi.e

3471 P05

AD5

P1.7 .38

33[3J PO.6

AD6

-“

RST/VPD [ 9
RXD

>
)

393 Po.0

P12 33

ALE/PROG -—

40 1 vcC

P11 ]2

SSEN

> | -

EA/VDD —»1

P1.3 — 4

-[ - rZ

XTAL2

Z ( RXD—»

P1.0

321 PO.7 AD7

P3.0 [J10 gos1 31

EA/VDD

> g L

TMD

P3.1 [ 11

iNTO

P3.2

29 ] PSEN

iNT1

P3.3 []13

283 P27

Als

e«

P34 [J14

271 P26

At4

> N —»

P35 []15

261 P25

A13

P3.6 C]16

251 P24

A12

P37 []17

243 P23

A11

| >

30 ] ALE/PROG

T0_><8<_>

e
S —>

XTAL2 []18

233 P22

A10

S|
S|

T | WR=— | <>

xTALt
19
vss [ 20

22
P21
213 P20

A9
A8

RD=-—

L >

[

| —»
|>

)

—

RD1169

RD1167

Figure A-2

8051 Symbol and Pinout Diagrams

A-2

(A7 to AQ)
es a multiplexed 8-bit data bus / low-orderbeing
When external memory is addressed, port O becom
used in
not
When
than 255, port 2 providgs Al5 to A8.
address bus. If the external address is higher its
programmed condition.
combination with port O, port 2 returns to

The 8051 signals are briefly described in Table A-1.
Table A-1

8051 Pin Description

Vss

Circuit ground potential.

Vce

+5 V power supply during operation, programming, and verification.
PORT 0

Port O is an 8-bit open-drain bidirectional I/O port. It is also the multiplexed low-order address and data
bus when using external memory. It is used for data input and output during programming and verification.
Port O can sink/source LSTTL loads.
PORT 1

Port 1 is an 8-bit quasi-bidirectional I/O port. It is used for the low-order address byte during

programming and verification. Port 1 can sink/source four LSTTL loads.
PORT 2

Port 2 is an 8-bit quasi-bidirectional I/O port. It also issues the high-order address byte when accessing
external memory. It is used for the high-order address and the control signals during programming and
verification. Port 2 can sink/source four LSTTL loads.
PORT 3

Port 3 is an 8-bit quasi-bidirectional I/O port. It also contains the interrupt, timer, serial port, and RD and
WR pins that are used by a number of options. The output latch corresponding to a secondary function
must be programmed to a 1 for that function to operate. Port 3 can sink/source four LSTTL loads. The
secondary functions are assigned to the pins of port 3, as follows:

RXD/data (P3.0). Serial port receiver data input (asynchronous) or data input/output

TXD/clock (P3.1). Serial port transmitter data output (asynchronous) or clock output

INTO (P3.2). Interrupt O input or gate control input for counter O

INTI (P3.3). Interrupt 1 input or gate control input for counter 1

TO (P3.4). Input to counter O

TI1 (P3.5). Input to counter 1

(synchronous)

WR (P3.6). The write control signal latches the data byte from port O into the external data
memory

RD (P3.7). The read control signal enables external data memory to port 0.

A-3

Table A-1

8051 Pin Description (Cont)

V) resets the 8051. IfVPD is held within
A change of level from low to high on this pin (at approximately 3specific
ation, VPD will provide staqdby
its specification (approximately +5 V) while Vece drops below
power to the RAM. When VPD is low, the RAM’s current flows from Vce. A small internal resistor

RST/VPD

permits power-on reset using only a capacitor connected to Vcc.
PSEN L

The Program Store Enable output is a control signal that enables the external program memory to the bus

during normal fetch operations. Not connected on DHV11.
EA/L/VDD

When held at a TTL high level, the 8051 executes instructions from the internal ROM/EPROM when the

PC is less than 4096. When held at a TTL low level, the 8051 fetches all instructions from external

program memory.

XTALI1

Input to the oscillator’s high-gain amplifier. Grounded on the DHVI1I.
XTAL2

Output from the oscillator’s amplifier. Driven by a 12 MHz clock on the DHV11.

A.2.3

Read/Write Timing

Read/write timing cycles are shown in Figures A-3, A-4, and A-5.

T10

ADDRESS Ay5-Ag

PORT 2

PORT 0 <

FLOA>< A7-AC

FLOATX INSTR

Figure A-3

IN FLOA’X A7-Ag

ADDRESS A1s5-Ag

FLOATXINSTR N

Program Memory Read Cycle

T12

Sggggss OR

> <A

FLOAT

’/ADDRESS OR

SFR P2

ADDRESS A15-Ag

PORT 2

porTo { INSTR IN FL@( A7-Ag

FLOAT J(
Figure A-4

PORT 0 <|NSTR

IN |FLOAT

ADDRESS A15-Ag
DATA OUT

A7-Ag )(
Figure A-5

] FLOAT
i

OR FLOAT

> < ADDRESS

Data Memory Read Cycle

)(

PORT 2

DATA IN

>< ADDRESS OR
X g[;TL%S:T

Data Memory Write Cycle

AQ. Latching occurs on
In each cycle, ALE (Address Latch Enable) is issued as a latching signal for A7 tobe
used to transfer data.

the negative-going edge of ALE. Once the low address bits are latched, portO can

If program memory is being read, Program Store Enable (PSEN L) must be asserted before the instruction
is read in. RD L and WR L will both be invalid.

When data memory is being accessed PSEN L is false and RD L or WR L are asserted.
Note that with a 12 MHz clock (OSC), a program memory cycle takes 500 nanoseconds. A data memory
cycle takes one microsecond.

A.3
A.3.1

SC2681 DUAL UART (DUART)
Block Description

for the bus buffer, which is
Block diagram Figure A-6 shows the functional blocks ofthe DUART. Except
these registers that the
via
is
It
a parallel holding register, there are control registers in every block.
DUART is programmed and monitored.

When the chip enable line (CEN) is low, the registers can be accessed by read or write actions of the host.
Address lines A3 to A0 provide the address. RDN or WRN provides the timing and control. Commands,
status, or data are transferred on the data lines D7 to DO. The operational control block manages these
parallel operations.

DO-D7<:i>

BUS BUFFER

<:::>

CHANNEL A

TRANSMIT
HOLDING REG

> TxDA

TRANSMIT

RDN &
—

WRN +—————
|

CEN—
A0-A3

CONTROL

RECEIVE

HOLDING REG

ADDRESS

DECODE

<:>

RESET

(3)

RECEIVE

SHIFT REG

AxDA

RIW CONTROL

MRAT1,2
CRA

SRA

SERIAL INTERFACES

PARALLEL INTERFACES

SHIFT REGISTER
OPERATION

INTERRUPT

INTRN

CONTROL

)

ISR

CHANNEL B

——

TxDB

RxDB

(AS ABOVE)

TIMING

INPUT PORT

o -] E

CHANGE
OF

BAUD RATE

STATE

DETECTORS (4)

GENERATOR

CLOCK

IPCR

ACR

+ IPO-IPG

SELECTORS

OUTPUT PORT
L

-).

COUNTER/
TIMER

FocTN
Z
-

SELE
LOGIC

> 0P0-0P7
-

PN (——

X2———

XTAL OSC

OPCR
-

OPR

CSRA
CSRB
ACR

CTUR

CTLR

vee

GND

—_—
RD1170

Figure A-6

SC2681 Dual Universal Asynchronous Receiver Transmitter (DUART)

A-6

Two serial data channels (A and B) perform the parallel/serial and serial/parallel conversion. Each
TRANSMIT channel has a 2-byte buffer. This allows the next character to be loaded while the previous
one is being transmitted. Each RECEIVE channel has a 4-byte buffer to allow for delays in interrupt
response.

Also related to the serial interface are a 7-bit input port and an 8-bit output port. These lines can be used as
individual, sense, and flag lines. Each line has a secondary function which may be used to provide modem
control for the serial data lines.

A 3.6864 MHz crystal provides the basic timing for the timing block. This section contains a
programmable counter/timer which can be programmed for many RECEIVE and TRANSMIT baud
rates. The counter/timer can also be clocked by input port 2.

Interrupts are generated when at least one of eight maskable interrupt conditions occurs. INTRN will
inform the controlling processor of changes in the DUART status. The interrupt routine should read status
and then take the appropriate action. INTRN is commonly used to indicate that a received character has
been assembled or that the DUART can accept a new character for transmission.
The DUART can also be operated in the polled mode.

Characters to be transmitted must be written to the appropriate transmit holding register.
Received characters must be read from the appropriate receive holding register.
A.3.2

Pin-Out Information
[40] vec

a0 [T]
3 (2]

[39] 1Pa

a1 [3]

[38] IP5

1p1 [4]

[37] 1Ps

a2 (5]

[36] 1p2

A3 [§]

[35] CsN

iro (7]

[34) RESET

wrN (8]

[33] xticLk

RON [3]

[32) x2

rxoB [10]

SC2681

[31] RXDA

Txo8 [11]

[30] TxDA

or1 [i2]

25] OPO

op3 [13]

[28] op2

ops [12]

[27] oP4

op? [i5]

[26] oPs

D1 [i8]

[25] po

03 [i7]

[24] D2

05 (i8]

[23] D4

o7 [19]

[22) o6

[21] INTRN

GND [25]

RD1171

Figure A-7

SC2681 Pin-Out Diagram

A pin-out diagram is provided in Figure A-7. The related pin functions are listed in Table A-2. This
information applies to the 40-pin DIL version of SC2681 only.

A-7

Table A-2
Mnemonic

Direction

DO to D7

I/0

SC2681 Pin Designation

Pin Name and Function
Data Bus — Bidirectional 3-state data bus used to transfer
commands, data, and status between the DUART and the CPU.
DO is the least significant bit.

CEN

Chip Enable - Active-low input signal. When low, data transfers
between the CPU and the DUART are enabled on DO to D7 as
controlled by the WRN, RDN, and AO to A3 inputs. When high,
places the DO to D7 lines in the 3-state condition.

WRN

Write Strobe — When low, and CEN is also low, the contents of
the data bus are loaded into the addressed register. The transfer
occurs on the positive-going edge of the signal.

RDN

Read Strobe — When low and CEN is also low, causes the
contents of the addressed register to be placed on the data bus. The
read cycle starts on the negative-going edge of RN.

A0 to A3

Address Inputs — Select the DUART internal registers and ports
for read/write operations.

RESET

Reset — A high level clears the internal registers (SRA, SRB,
IMR, ISR, OPR, OPCR), puts OPO to OP7 in the high state, stops
the counter/timer, and puts channels A and B in the inactive state
with the TxDA and TxDB outputs in the mark (high) state.

INTRN

Interrupt Request — Active-low open-drain output which signals
to the CPU that one or more of the eight maskable interrupting
conditions are true.

X1/CLK

Crystal 1 — Crystal or external clock input. Grounded on the
DHVI11.

Crystal 2 — Connection for the other side of the crystal. Connected
to a 3.6864 MHz crystal on the DHV11.

RxDA

Channel A Receiver Serial Data Input— The least significant bit
is received first. Mark is high, space is low.

RxDB

Channel B Receiver Serial Data Input— The least significant bit
is received first. Mark is high, space is low.

TxDA

Channel A Transmitter Serial Data Output — The least
significant bit is transmitted first. This output is held in the mark

condition when the transmitter is disabled, idle, or when operating
in local loopback mode. Mark is high, space is low.
OPO to OP7

General Purpose Outputs — Used by the DHV11 for modem

control.

SC2681 Pin Designation (Cont)

Table A-2

Pin Name and Function

Mnemonic

Direction

IPO to IP6

Vce

Power Supply

GND

Ground

A.4

General Purpose Inputs — Used by the DHV11 to monitor

modem status.

+5 V supply input

DC003 INTERRUPT IC

The interrupt controller is an 18-pin DIL device that provides the circuits to perform an interrupt
transaction in a computer system that uses a ‘pass-the-pulse’ type arbitration. The device provides two
interrupt channels, A and B, with the A section at a higher priority than the B section. Bus signals use highimpedance input circuits or open-collector outputs, which allow the device to be attached directly to the
computer system bus. Maximum current taken from the Vcc supply is 140 mA.
Figure A-8 is a simplified logic diagram of the DC003 IC. Timing for the interrupt section is shown in
Figure A-9, while Figure A-10 shows the timing for both A and B interrupt sections. Table A-3 describes
the signals and pins of the DC003 by pin and signal name.

DC003
17

RQSTA H
16

ENA DATAH

BIRQ L D____

ENA CLKH

05
03

BIAKO L

P———

BINIT L

INITOL

P————

BDIN L

VECTOR H

ENB CLK H
12

BIAKI L

ENA ST H

VEC RQSTB H

ENB DATA H
1

10
RQSTB H

ENBSTH

MK 0164

Figure A-8

DCO003 Logic Symbol

A-9

300

MINY

BINIT L

INITOL

300

/MIN
]

7-35

—u

ENA DATA H

[

]

ENA CLK H 30MIN—»IE 1

1
|

ENA STH

7-30— [

RQSTA H

|
;

BIRQ L

15-65— [+— —

BDIN L

}

[+—20-90

;

Coy

BIAKI L

|
:

35 MIN —=

35 MIN—
1

VECTOR H

[

10-45 ! F»: F1o-45
1

;
!

i
|
3

BIAKO L

1255+ l:-"' F—12—55
NOTE:
TIMES ARE IN NANOSECONDS.

Figure A-9

DC003 A Section Timing

A-10

e 0173

300

|MiInf300!

BINITL
I
ol

INITO L

7-35

ENB DATA H

MIN

l
of12-50
|

]

[ ]
0MIN-=
1

ENB CLKH

ENBSTH

L
BIRQ

RQSTB H

ENA DATAH

ENA CLK H

ENASTH

RQSTA H

L
BDIN

35M|N——n|

BIAKI L

35M|N——.I
|

VECTORH

VECRQSTB H
NOTE:

MK 0175

TIMES ARE IN NANOSECONDS.

Figure A-10

DCO003 A and B Section Timing

A-11

Table A-3

DCO003 Signals

I/O Name

Symbol

Function

Interrupt

VECTOR H

This signal gates the appropriate vector address to

No.

Vector Gating

the bus and forms the bus signal BRPLY L.

Signal

Vector
Request B

VEC RQSTBH

When asserted, this signal indicates RQST Bservice
vector address is wanted. When not asserted it
indicates RQST A service vector address is wanted.

Signal

VECTOR H is the gating signal for the complete
vector address; VEC RQSTB H is normally bit 2 of
the address.

Bus Data In

BDIN L

The BDIN signal always precedes a BIAK signal.

Initialize Out

INITO L

This is the buffered BINIT L signal used in the

Bus Initialize

BINIT L

When asserted, this signal brings all drive lines to

Bus Interrupt
Acknowledge
(Out)

BIAKO L

This signal is the daisy-chained signal that is passed
by all devices not requesting interrupt service (see
BIAKIL). Once passed by a device, it must continue

Bus Interrupt
Acknowledge

BIAKI L

device interface for general initialization.

their non-asserted state (except INITO L).

to be passed until a new BIAKI L is generated.

This signal is the processor’s response to BIRQ L
true. This signal is daisy-chained so that the first
requesting device blocks the signal, while non-

(In)

requesting devices pass the signal on as BIAKO L to
the next device in the chain. The leading edge of
BIAKI L causes BIRQ L to be deasserted by the
requesting device.

Asynchronous
Bus Interrupt
Request

BIRQ L

This request is generated when a RQST signal and
the appropriate Interrupt Enable signal become
valid. The request is removed after the acceptance of
the BDIN L signal and on the leading edge of the
BIAKI L signal, or the removal of the appropriate

interrupt enable, or by the removal of the appropriate
request signal.

17
10

Device
Interrupt
Request

RQSTA H
RQSTB H

Interrupt
Enable Status

ENA STH
ENB ST H

Signal

16
11

When asserted with the enable A/B flip-flop asserted,
this signal causes BIRQ L to be asserted on the bus.
This signal line normally stays asserted until the
request is serviced.

This signal indicates the state of the interrupt enable
A/B internal flip-flop which is controlled by the

signal line ENA/B DATA H and the ENA/B CLK
H clock line.

A-12

Table A-3 DCO003 Signals (Cont)

Function

I/O Name

Symbol

15
12

Interrupt
Enable Data

nction with the
level on this line, in conju
ENA DATAH The
of the
CLK H signal, determines theThestate
ENB DATAH ENA/B
t of
outpu
al interrupt enable A flip-flop.

No.

intern
this flip-flop is monitored by the ENA/B ST H
signal.

14
13

Interrupt
Enable clock

ENA CLK H
ENB CLK H

When asserted (on the positive edge), interrupt
enable A/B flip-flop assumes the state of the ENA/B
DATA H signal line.

DC004 PROTOCOL IC
selector, providing the signals
The protocol chip is a 20-pin DIL device that functions as a register
Bus signals can be directly
bytes).
(8
s
register
word
four
necessary to control data flow to and from up to
An RC delay circuit is
chip.
the
on
provided
are
attached to the device because receivers and drivers
The circuit is designed
requests.
transfer
data
to
provided to slow the response of the peripheral interface

A.5

is needed. External
so that if close tolerance is not wanted, only an external 1 kilohm (+ or— 20%) resistor
is 120 mA.
supply
Vcc
the
from
taken
current
m
Maximu
RCs can be added to change the delay.

Figure A-11 is a simplified logic diagram of the DC004 IC. Signal timing in relation to different loads is
shown in Figure A-12. Signal and pin definitions for the DC004 are shown in Table A-4.

A-13

VECTOR H [T]1

BDAL 2[]2
BDAL 1[]3
BDALO[]4

2083

vee

JENB H

DCOD4

183 RXCX H
172 SEL6 L

BWTBT L [[]5s

16[JSEL4A L

BSYNC L []6

15[3SEL2L

BDINL[]7

14[JSELO
L

BRPLY L[]8

13[JOUTHB L

BDOUT L ]9

12[JouTLs L

GND[J10

1MJINWD L

_+VCC

ENB H[19]

ENB
LATCH

BSYNC LF‘G

BDAL2 L|02

ENB

Vcc

SYNCD

GND

02
LATCH

BDAL1 L{03

DAL 2

DECODER

01
LATCH

BDALO L]o4

SEL6 L

O———16]seLaL

O—-@SELz L

DAL 1

SELO L

_}
1

13JouTtHe L

12JOUTLB L

00
LATCH

—G
BWTBT L

‘

18]RXCX H

BDOUT L
BDI
L [07]-O
N

))

11]iInwD
L
MK 01721

Figure A-11

DCO004 Simplified Logic Diagram

A-14

/25 MIN

BDAL (2,1,0) L /A
15 MINy

ens w7

15 MIN

1 V7.
———

SEL(0,2,4,6) L

BSYNC L

—>§ 151040

510 30

BWBT L
!

OUTHB L
OUTLB L
BDIN L

]

51030~

—

5to30—;|

—

{

LI
|

]

WD L

[—5130

—

BDOUT L

|—5130
|

BRPLY L

2010430
—

{

VECTOR H

[

I e

101045

—
}

Rx Cx H

"TIME REQUIRED TO DISCHARGE Rx Cx FROM ANY CONDITION ASSERTED = 150ns
NOTE:
TIMES ARE IN NANOSECONDS.
RD1346

Figure A-12

DC004 Timing Diagram

Table A-4
Pin
1

DC004 Pin/Signal Descriptions

Signal

Description

VECTOR H

Vector — This input causes BRPLY L to be generated through the delay
circuit. It is independent of BSYNC L and ENB H.

2
3
4

BDAL2 L
BDALL L
BDAIOL

BWTBT L

Bus Data Address Lines— These signals are latched at the assert edge of
BSYNCL. Lines 2 and 1 are decoded for the select outputs; line 0 is used
for byte selection.
Bus Write Byte — While the BDOUT L input is asserted, this signal
indicates a byte or word operation: asserted = byte, not asserted = word.
Decoded with BDOUT L and latched BDALO L to form OUTLB L and
OUTHB L.

BSYNC L

Bus Synchronize— Atthe assert edge of this signal address information is
trapped in four latches. When not asserted, disables all outputs except the

vector term of BRPLY L.

BDIN L

Bus Data In — This is a strobe signal to effect a data input transaction.
Generates BRPLY L through the delay circuit and INWD L.

BRPLY L

Bus Reply — This signal is generated through an RC delay by VECTOR
H, and strobed by BDIN L or BDOUT L, and BSYNC L and latched

ENB H.

BDOUT L

Bus Data Out— This is a strobe signal to effect a data output transaction.
Decoded with BWTBT L and BDALO to form OUTLB L and OUTHB
L. Generates BRPLY L through the delay circuit.

INWD L

In Word — Used to gate (read) data from a selected register onto the data
bus. Enabled by BSYNC L and strobed by BDIN L.

12
13

OUTLB L
OUTHB L

Out Low Byte, Out High Byte — Used to load (write) data into the lower,
higher, or both bytes of a selected register. Enabled by BSYNC L and
decode of BWTBT L and latched BDALO L, and strobed by BDOUT L.

14
15
16

SELO L
SEL2 L
SEI4 L

SEL6 L

Select Lines — One of these four signals is true as a function of BDAL2 L
if ENB H is asserted at the assert edge of BSYNC L. They indicate that a
word register has been selected for a data transaction. These signals never

become asserted except at the assertion of BSYNC L (then only if ENB H
is asserted at that time) and, once asserted, are not deasserted until
BSYNC L is deasserted.

RXCX

External Resistor Capacitor Node — This node is provided to vary the
delay between the BDIN L, BDOUT L, and VECTOR H inputs and
BRPLY L output. The external resistor should be tied to Vcc and the
capacitor to ground. As an output, it is the logical inversion of BRPLY L.

ENB H

Enable — This signal is latched at the asserted edge of BSYNC L and is
used to enable the select outputs and the address term of BRPLY L.

A-16

A.6 DCO005 BUS TRANSCEIVER IC
The 4-bit transceiver is a 20-pin DIL low-power Schottky device for primary use in peripheral

device
1nterfages. It functions as a bidirectional buffer between a data bus and peripheral device logic. In addition

to the isolation function, the device also provides a comparison circuit for address selection,

and a

constant generator, useful for interrupt vector addresses. The bus I/0 port provides high-impedanc

inputs and open-collector outputs to allow direct connection to a computer’s data bus. On the peripheral

device side, a bidirectional port is also provided, with standard TTL inputs and 20 mA tri-state drivers.
Data on this port has the opposite polarity to the data on the bus side.

Three address jumper inputs are used to compare against three bus inputs and to generate the signal

MATCH. The MATCH output is open-collector, which allows the output of more than one transceiver to
be wire-ANDed to form a combined address match signal. The address jumpers can also be put into a third
logical state that disconnects that jumper from the address match, allowing for ‘don’t care’ address bits. In
addition to the three address jumper inputs, a fourth high-impedance input line is used to enable/disable
the MATCH output.

Three vector jumper inputs are used to generate a constant, that can be passed to the computer bus. The
three inputs directly drive three of the bus lines, overriding the action of the control lines.

Two control signals are decoded to give three operation states: receive data, transmit data, and disable.

Figure A-13 is a simplified logic diagram of the DC00S IC. Timing for the functions is shown in Figure A-14.
Signal and pin definitions for the DC0O05 are given in Table A-5.
Table A-5

DCO005 Pin/Signal Descriptions

Name

Function

12
11

BUSO L
BUSI L

9
8

BUS2 L
BUS3 L

Bus Data — This set of four lines constitutes the bus side of the transceiver.
Open-collector outputs; high-impedance inputs. Low = 1.

18
17
7
6

DATO H
DAT1 H
DAT2 H
DAT3 H

Peripheral Device Data — These four tri-state lines carry the inverted
received data from BUS (3:0) when the transceiver is in the receive mode.
When in transmit data mode, the data carried on these lines is passed
inverted to BUS (3:0). When in the disabled mode, these lines go open (high

14
15
16

JV1 H
JV2 H
JV3 H

Vector Jumpers — These inputs, with internal pull-down resistors, dirqc'tly
drive BUS (3:1). A low or open on the jumper pin causes an open condition
on the corresponding BUS pin if XMIT H is low. A high causes a 1 (low) to

impedance). High = 1.

be transmitted on the BUS pin. Note that BUSO L is not controlled by any

jumper input.

MENB L

MATCH H

Match Enable — A low on this line enables the MATCH output. A high

forces MATCH low, overriding the match circuit.

Address Match — When BUS (3:1) matches the state of JA (3:1) and
MENB L is low, this output is open; otherwise, it is low.

A-17

Table A-5

DCO005 Pin/Signal Descriptions (Cont)

Name’

Function

1
2

JAI L
JA2 L

Address Jumpers — A connection to ground on these inputs allows a match
to occur with a 1 (low) on the corresponding BUS line. An open allows a

JA3 L

match with a O (high). A connection to Vcc disconnects the corresponding
address bit from the comparison.

5
4

XMIT H
RECH

Control Inputs — These lines control the operation of the transceiver as
follows.
REC XMIT
0
0
1
1

O
1
0
1

DISABLE: BUS and DAT open
XMIT DATA: DAT to BUS
RECEIVE: BUS to DAT
RECEIVE: BUS to DAT

To avoid tri-state overlap conditions an internal circuit delays the change of
modes between XMIT DATA and RECEIVE mode, and delays the
enabling of tri-state drivers on the DAT lines. This action is independent of
the DISABLE mode.

A-18

JATL

L 20vce

JA2L

|19 JA3 L

MATCH H 3
RECH

4 -

XMITH

DAT3H

BUSO L

18 DATOH
L 17 DAT1H

- 16 JV3
H

15 JV2
H

DAT2
H

14 JVI H

BUS3L

| 13 MENB L

BUS2
L

12 BUSO
L

GND

104

| 11 BUST L

<{>

{T8)

DATO

BUST L [E———<{>

-1/]\

i{:} DAT1

JA1

‘i@

BUS2

Jv2

ij l %D DAT2

JA2

\L—(j,l‘/" Fe

8Us3 1 [B—{>

REC

—{03] MATCH

{@J DAT3

L [19)

JA3

]l/k\

MK.0170

H @ -

(20} Ve
Figure A-13

(10— GND
DCO00S Simplified Logic Diagram

A-19

DC005 TRANSCEIVER

TRANSMIT DATA TO BUS
XMITH

REC H (GROUND)

5T030ns

BUS L - OUTPUT
5TO 25 ns

DAT H — INPUT

l+-5
TO 25 ns

RECEIVE DATA FROM BUS (BUS INITIALLY HIGH)
XMIT H (GROUND}
RECH

DAT H - OUTPUT

[ 0TO30ns

BUS L - INPUT

R 0TO30ns

-8
TO 30 ns

RECEIVE DATA FROM BUS (BUS INITIALLY LOW)
XMIT H {GROUND)

REC H

-0 TO 30 ns

DAT H — OUTPUT

l-0TO 30 ns
—

BUS L —INPUT

le8 TO 30 ns

VECTOR TRANSFER TO BUS
IV H

|
-~

le- 20 ns MAX

_
}+- 20 ns MAX

BUS L — OUTPUT

ADDRESS DECODING

X
-~

BUS L — INPUT

=10 TO 40 ns

MATCH H

+~5TO40ns

l- 10 TO 40 s

MENB L

RECEIVE MODE LOGIC DELAY
XMIT H
REC H

le- 40 TO 90 ns

DAT (3:0) H (OUTPUT}
MK 0174

Figure A-14

DCO005 Timing Diagram

A-20

A.7

DC010 DIRECT MEMORY ACCESS LOGIC

This DMA controller provides the logic to perform the handshaking operations needed to request and to

gain control of the system bus. Once the DC010 becomes bus master it generates the signals needed to
perform a DIN, DOUT, or DATIO transfer as specified by control lines to the chip. The DC010 IC has a
control line that will allow multiple transfers or only four transfers to take place before giving up the bus.
Figure A-15 is a simplified logic diagram of the DC010 IC. The logic symbols and truth table are shown in
Figure A-16, and the DCO10 voltage waveforms are shown in Figure A-17. Table A-6 describes the
signals and pins of the DCO10 by pin and signal name. Figures A-18 and A-19 show the timing.
(MASTER L);D_EDM“ -

o
[9
INIT

CLR

([MASTER ENA)

CLR

MASTER H

B
- oELay )—D

BOMGI L

BOMGO

D H)
CNTa H

2807

BINARY
COUNTER

[oX]

|MASTER ENAY

TMOUT K

IMASTER §'D m—?

}

)
o

DaTIN L

DATIO L —.

C
-

]

LATCH -

DATEN L

ADREN H
CLK
CLR

(END CYCLE H)

TSYNC H

ouT
1N OUT)

JEND CYCLE !
JNIT

[IMAX H)

SET

DIN

3BIT

BINARY

DOUT K

COUNTER

RPLY L——10
Cin L —

{MASTER ENA)

—

P
puaLRank o | _ [T'RPLYSOH
SYNCHRONIZER

CLK

ASYNC #

DUAL RANK

SYNCHRONIZER

’-OCLK

Signal

REQH

Figure A-15

DCO010 Simplified Logic Diagram

Table A-6

DCO010 Pin/Signal Descriptions

Description

Request (TTL Inputs) — A high on this signal initiates the bus request
transaction. A low allows the termination of bus mastership to take

place.

BDMGI L

DMA Grant Input (High Impedance) — A low on this signal allows
bus mastership to be established if a bus request was pending (REQ =

high); otherwise this signal is delayed and output as BDMGO.

CNT4H

Count Four (TTL Output) — A high on this signal allows a maximum
of four transfers to take place before giving up bus mastership. A low
disables this feature and an unlimited transfer will take place as long as
REQ is high. If left open this pin will assume a high state.

A-21

Table A-6

DCO010 Pin/Signal Descriptions (Cont)

Signal

Description

TMOUT H

Time-Out (TTL Input/Open Collector Output) — This I/O pin is low
while SACK H is high. It goes into high impedance when SACK H is

low. When driven low it prevents the assertion of BDMR; when driven
high it allows the assertion of BDMR to take place if BDMR has been
deasserted because of the 4-maximum transfer condition. An RC
network may be used on this pin to delay the assertion of BDMR.

DATIN L

Data In (TTL Input) — This signal allows the selection of the type of
transfers to take place according to the truth table (Figure A-16).

DATIOL

Data In/Out (TTL Input) — This signal allows the selection of the type
of transfer to take place according to the truth table (Figure A-16).
During a DATIO transfer, this signal must be toggled in order to allow
the completion of the output cycle of the 1/O transfer.

RSYNC L

Receive Synchronize (TTL Input) — This signal allows the device to
become master according to the following relationship:
RSYNC L - RPLY L - SACK H = MASTER

CILK L

Clock (TTL Input) — This clock signal is used to generate all transfer
timing sequences.

REPLY L

Reply (TTL Input) — This signal is used to enable or disable the free
clock signal.

This signal also allows the device to become master according to the
following relationship:
RSYNC L - RPLY L - SACK H = MASTER
19

INITL

Initialize (TTL Input) — This signal is used to initialize the chip to the
state where REQ is needed to start a bus request transaction. When
INIT is low, the following signals are deasserted: BDMR L, MASTER
H, DATEN L, ADREN L, SYNC H, DIN H, DOUT H.

BDMR L

DMA Request (Open Collector Output) — A low on this signal
indicates that the device is requesting bus mastership. This output may
be tied directly to the bus.

MASTER H

Master (TTL Output) — A high on this signal indicates that the device
has bus mastership and a transfer sequence is in progress.

BDMGO L

DMA Grant Output (Open Collector Output) — This signal is the
delayed version of BDMGTI if no request is pending; otherwise it is not
asserted. This output may be tied directly to the bus.

A-22

Table A-6

DCO010 Pin/Signal Descriptions (Cont)

Signal

Description

TSYNC H

Transmit Synchronize (TTL Output) — This signal is asserted by the
device to indicate that a transfer is in progress.

DATEN L

Data Enable (TTL Output) — This signal is asserted to indicate that
data may be placed on the bus.

ADREN H

Address Enable (TTL Output) — This signal is asserted to indicate
that an address may be placed on the bus.

DIN H

Data In (TTL Output) — This signal is asserted to indicate that the bus
master device is ready to accept data.

DOUT H

Data Out (TTL Output) — This signal is asserted to indicate that the
bus master device has output valid data.

0Cco10

REQ HT1
gz

DATIO L

DATIN LT3

wfvee
19
B INITL

18[JDATEN L

TRUTH TABLE
WHERE L = TTL LOW

H = TTL HIGH

X = DON'T CARE

178cik H

ADREN H{]4
DOUTH[]s

16[JCNT4
H

DINH[]6

15[JAPLY L

NPUTS

TRANSFER

Tsync HId7

143 TMOUT H

DATIN|

DATIO

TYPE

somGo L8

13[18OMGI f L

DATIO

BsAcCk{{s

123 RSYNC H

DIN

ano(d1o

11{JBOMR L

DouT

LOGIC SYMBOL

Figure A-16

DCO010 Logic Symbol/Truth Table.

INPUT

15V

!
!

QUTPUT IN
PHASE

:
i
[
s
[
l
t

OUTPUT OUT

OF PHASE

i
1

15v

|
]
s

|
|

jot 1oV

|
|
|
ok

[

158V

]

PULSE CONDITIONS FOR DELAY MEASUREMENTS
MA

Figure A-17

1108

DCO010 Voltage Waveforms

A-23

CLK
|

REQ H

lvr

———

1
[<30-90

ADREN H

DATEN L

Ofl

)©

TSYNCH

DIN H

RPLY H

—

|
END CYCLE
DATIN L

| — 60 =—

DATIO L

MASTER H

18-66

10-68

TIMES IN
NANOSECONDS

SINGLE NUMBERS
ARE MINIMUM
TIMES
RD1345

Figure A-19

DCO010 Timing Diagram

A-25

APPENDIX B

MODEM CONTROL

B.1

SCOPE

This appendix contains information useful to both the programmer and the engineer. It defines con_trol

signals, describes typical modem control methods, and warns against likely network faults. A detailed

example of auto-answer operation is included.
B.2

MODEM CONTROL

The DHV11 supports sufficient modem control to permit full-duplex operation over the public switched
telephone network (PSTN) and over private telephone lines. Table B-1 lists the control leads supported by
the DHV11 together with an explanation of their use and purpose. In this appendix, the terms MODEM
and DATASET have the same meaning. They refer to the device which is used to modulate and
demodulate the signals transmitted over the communications circuits.

The DHV11 modem control interface can be used in many applications. These include control of serial
line printers, terminal cluster controllers, and industrial I/O equipment, in addition to the more usual
applications in telephone networks. Use of the control leads described in Table B-1 is therefore
completely application dependent, although there are international standards which telephone network

applications should obey. There are no hardware interlocks between the modem control logic and the
transmitter and receiver logic. Program control manages these actions as necessary.

A subset of the leads listed in Table B-1 could be used to establish a communications link using modems
connected to the switched telephone network. Ring Indicator (RI), Data Terminal Ready (DTR), and
Data Carrier Detected (DCD) are the absolute minimum requirements. In some countries Dataset Ready
(DSR) is also needed. It is usually desirable, however, to implement modem control protocols which will
operate over most telephone systems in the world. Also, some protection should be included to guard
against network faults, particularly in applications such as dial-up time-sharing systems. Such faults
include:

Making a channel permanently busy (hung) because of a misdialed connection from a non-data
station

Connecting a new incoming call on an in-use channel. This fault might occur, for example, after
a temporary carrier loss, if the host system assumed that the carrier was reasserted by the
original caller.

Modem control with some protection against common faults, and which is compatible with the telephone
networks in most geographic areas, can be implemented by using all the signals listed in Table B-1, in the
way described by the CCITT V.24 recommendations. Section B.2.1 describes a method of implementing
a full-duplex auto-answer communications link via modems over the PSTN. It is provided here only to
show the operation and interaction of DHV11 modem control leads in a typical application.

Table B-1
Name

RS-232-C

V.24

25-Pin

GND

Modem Control Leads
Definition

Protective ground. This provides a path between the
modem and DHV11
static electricity.

GND

102

for discharge of potentials such as

Signal Ground. This is a reference level for the data and
control signals used at the EIA interface.

103

From DHV11 to modem. This signal contains the
serial bit stream to be transmitted to the remote station.

RXD

104

From modem to DHV11. This signal is the serial bit
stream received by the modem from the remote station.

RTS

105

From DHV11 to modem. Causes the modem’s carrier
to be placed on the line.

CTS

106

From modem to DHV11. Indicates that the modem has
successfully placed its carrier on the line and that data
presented on circuit BA will be transmitted to the
communication channel.

DSR

107

DTR

CDh

108/2

From modemto DHV11. Indicates that the modem has
completed all call establishment functions and is
successfully connected to a communications channel.

From DHV11 to modem. Indicates to the modem that

the DHV11 is powered up and ready to answer an
incoming call.

DCD

109

125

From modem to DHV11. Indicates to the DHV11 that
the remote station’s carrier signal has been detected and
is within appropriate limits.

From modem to DHV11. Indicates that a new incoming

call is being received by the modem.

B.2.1
Example of Auto-Answer Modem Control for the PSTN
The system operator determines which DHV11 channels should be configured for either local or remote
operation. Local operation implies control of data-leads only, while remote operation implies that modem
control will be supported. The host software will assert DTR and RTS together with the Link Type
bitin
the LNCTRL register for all DHV11 channels configured for remote operation. DTR informs the modem
that the DHV 11 is powered up and ready to acknowledge control signals from the modem. RTS
is asserted
for the full-duplex mode of operation and causes the modem to place its carrier on the telephone line when
the modem answers a call. Link Type (LNCTRL<8>) enables modem status information to be placedin
the receive character
FIFO where it will be handled by an interrupt service routine. Modem status
changes are always reported in the STAT register regardless of the state of LNCTRL<8>. The
modem is

now prepared to auto-answer an incoming call.

B-2

Dialing the modem’s number causes RI to be asserted at the EIA interface. This informs the DHV11 that
anew call is being received. RI has to be in a stable state for at least 30 ms or else the change will not be
reported by the DHV11. Since DTR is already asserted, the modem will auto-answer the incoming call
and start its handshaking sequence with the calling station. The time needed to complete the handshaking
sequence can be in the order of tens of seconds if fallback mode speed selection and satellite links are
involved. The modem will assert DSR to indicate to the DHV11 that the call has been successfully
answered and a connection established.

NOTE

On some older types of modemused on the PSTN,
the opposite effect is also true. The RI signal may
be very short, or it may not even occur if DTR is
previously asserted. When this type of modem
answers an incoming call it asserts DSR almost
immediately and deasserts RI at the EIA interface.

Programs must therefore expect RI or DSR or

DCD as the first dataset status change received

from the modem when establishing a connection.

As RTS was previously asserted, the modem’s carrier will be placed on the line when DSR is asserted.
When the modem has successfully placed its carrier on the line it will assert CTS which indicates to the
DHV11 that it may start to transmit data. Should the incoming call be the result of a misdialed number
then it is possible that a carrier signal would never be received. To guard against this, the host starts a timer
when it detects RI or DSR. This is usually in the range of 15 to 40 seconds, within which time the carrier
must be detected. When the modem detects the remote modem’s carrier signal on the line, it will assert
DCD which indicates to the DHV11 that data is valid on the RXD line.

The modem may now exchange data between the DHV11 and the calling station for as long as DCD,
DSR, and CTS stay asserted. If any of these three signals disappear, or if RI should be detected during
normal transmission, it would indicate a fault condition. A change of state of any of these signals would
cause an interrupt via the receive FIFO.

The handling of the fault conditions now becomes country-specific as some telephone systems tolerate a
transient carrier loss while others do not. In the USA it is usual to proceed with a call if carrier resumes
within two seconds. In non-USA areas it is possible for telephone supervisory signals, such as dial-tone, to
be misinterpreted by the modem as a resumption of carrier. In this case the host program would assume
that the connection had been reestablished to the original caller and would cause a ‘hung’ channel. To
prevent this, DTR should be deasserted immediately after the loss of DCD, CTS, or DSR to abort the
connection. DTR should stay deasserted for at least two seconds, after which time a new call could be
answered.

APPENDIX C

GLOSSARY OF TERMS

SCOPE

C.1

This appendix contains a glossary of terms used in this manual. The terms are in alphabetical order for

easy reference.

C.2

GLOSSARY

asynchronous

A method of serial transmission in which data is preceded by a start bit and followed bya

stop bit. The receiver provides the intermediate timing to identify the data bits.

auto-answer
auto-flow

A facility of a modem or terminal to automatically answer a call.

Automatic flow control. A method by which the DHV11 controls the flow of data by means

of special characters within the data stream.

backward channel

A channel which transmits in the opposite direction to the usual data flow.

Normally used for supervisory or control signals.
Bus Address Line.

BAL

Bus Data and Address Line.

BDAL

base address

The address of the CSR.

Background Monitor Program.

BMP

CCITT

Comite Consultatif International de Telephonie et de Telegraphie. An international standards

dataset

See modem

committee for telephone, telegraph, and data communications networks.

DIL

Dual-In-Line. The term describes ICs and components with two parallel rows of pins.

DMA

Direct Memory Access. A method which allows a bus master to transfer data to and from system

memory without using the host CPU.

DUART

Dual Universal Asynchronous Receiver Transmitter. An IC used for transmission and

reception of serial asynchronous data on two channels.

duplex

A method of transmitting and receiving on the same channel at the same time.

EIA

FElectrical Industries of America. An American organisation with the same function as the CCITT.

EMC

Electro-Magnetic Compatibility. The term denotes compliance with field-strength, susceptibility,

and static discharge standards.

C-1

FCC

Federal Communications Commission. An American organisation which regulates and licenses

communications equipment.

FIFO

FirstIn First Out. The term describes a register or memory from which the oldest data is removed

first.

floating address A CSR address assigned to an option which does not have a fixed address allocated.
The address is dependent on other floating address devices connected to the bus.
floating vector

An interrupt vector assigned to an option which does not have a fixed vector allocated.

The vector is dependent on other floating vector devices connected to the bus.
FRU

Field Replaceable Unit.

GO/NOGO A test or indicator which defines only an ‘error’ or ‘no error’ condition.
IC

Integrated Circuit.

I/O

Input/Output.

LSB

Least Significant Bit.

LSI-11 bus

Another name for the Q-bus.

microcomputer

An IC which contains a microprocessor and peripheral circuitry such as memory, I/O

ports, timers, and UARTSs.

modem The word is a contraction of MOdulator DEModulator.
transmission line. A modem is sometimes called a dataset.
MSB

A modem interfaces a terminal to a

Most Significant Bit.

multiplexer

A circuit which connects a number of lines to one line.

null modem A cable which allows two terminals which use modem control signals to be connected
together directly. Only possible over short distances.
PCB

Printed Circuit Board.

protocol

A set of rules which define the control and flow of data in a communications system.

PSTN

Public Switched Telephone Network.

Q-bus

A global term for a specific DIGITAL bus on which the address and data are multiplexed.

Q22,

QI8 and Q16

Terms used to define 22-, 18-, and 16-bit address versions of Q-bus.

RAM

Random Access Memory.

RFI

Radio Frequency Interference.

ROM

Read Only Memory.

SMPS

Switch Mode Power Supply.

split-speed A facility of a data communications channel which can transmit and receive at different data
rates at the same time.

UART

Universal Asynchronous Receiver Transmitter. An IC used for transmission and reception of

serial asynchronous data on a channel.

X-OFF

A control code (23g) used to disable a transmitter. Special hardware or software is needed for

this function.

X-ON

A control code (21g) used to enable a transmitter which has been disabled by an X-OFF

code.

APPENDIX D

AUTOMATIC FLOW CONTROL

D.1
OVERVIEW
Flow control is the control of data flow along a communications line, to prevent an overspill of queues or
buffers, or to prevent loss of data when the receiver is unable to accept it.

The method of flow control adopted for the DHV11 is datastream-embedded ASCII control characters. The
control characters used are X-OFF (023g) and X-ON (021g). X-OFF stops transmission and X-ON starts
transmission. The codes are transmitted in the opposite direction to the data which they control.
The DHV11 has one mode of operation for transmitted data (received flow-control characters) and two
modes of operation for received data (transmitted flow-control characters). Each mode can be enabled on
a ‘per-channel’ basis. Each direction of flow is discussed separately within this appendix.

D.2 CONTROL OF TRANSMITTED DATA
The mode of flow control for transmitted data is the simplest of the three flow-control modes of the
DHVI11.

When the DHV11 receives an X-OFF character for a particular channel, the TX.ENA bit for that
channel is cleared. When this bit is clear the DHV11 will not transmit any data on that channel; however,
internally generated flow-control characters will still be transmitted. When an X-ON character is
received, the TX.ENA bit for that channel is set. Figure D-1 illustrates the operation of the transmitted
data flow control.

XON
RECEIVED

OAUTO=1
XOFF
RCVD

OAUTO=0

XOFF
RECEIVED

RD2251

Figure D-1

Transmitted Data Flow Control

D-1

Only characters without transmission errors are checked for X-ON and X-OFF

have their parity bit stripped before comparison.

codes. The characters

NOTE

For the automatic flow control to operate correctly,
the DHVI11 and the connected equipment must
have the same line configuration.

The transmitted data mode of flow control is enabled by setting OAUTO (bit 4 of the line control register),
and is disabled by clearing OAUTO. The default for this mode is ‘disabled’. The DHV11 may alter the
state of the TX.ENA bit up to 20 microseconds after the program clears the OAUTO bit.
The DHV11 always passes flow-control characters back to the program via the received character FIFO,
whether or not this mode is enabled.

D.3 CONTROL OF RECEIVED DATA
The flow control of received data is slightly more complicated than that of transmitted data; therefore, for
descriptive purposes, the two modes of received data flow control are first treated separately.
D.3.1
Flow Control by the Level of the Received Character FIFO
Occasionally, the program may not be able to empty the received character FIFO as fast as the received
data is filling it. Since the program is unaware of how full the FIFO is, it is unable to take appropriate
action to prevent data loss. To overcome this problem, the DHV11 can be programmed on a ‘per-channel’
basis, so that an X-OFF is sent before the FIFO reaches a critical condition. In these circumstances,
when the FIFO becomes three-quarters full, the X-OFF is sent to the channels from which data is
received, and thereafter an X-OFF character is sent in response to every second received character.
When the FIFO level drops below half full, an X-ON character is transmitted. The operation of the
FIFO-level flow control is shown in Figure D-2.
The FIFQO-level flow-control mode is enabled by setting IAUTO (bit 1 of the line control register). The

mode is disabled by clearing IAUTO. The default for this mode is ‘disabled’. IFTAUTO is cleared after an
X-OFTF is sent but before an X-ON would normally be sent, an X-ON is sent anyway.

D-2

FIFO.CRIT=F
FIFO.CRIT=F

IAUTO=1

FIFO.CRIT=T

IAUTO=1

IAUTO=0

FIFO.CRIT=F

IAUTO=0

FIFO.CRIT=T

IAUTO=1

FIFO.CRIT=T

IAUTO=0

FIFO.CRIT=F

IAUTO=0

FIFO.CRIT=F

RD2252

NOTE
FIFO.CRIT is set true (T) when the FIFO level
rises to three-quarters full, and is again set false
(F) when the FIFO
level falls below half full.

Figure D-2

Received Character FIFO-Level Flow Control

D.3.2 Flow Control by Program Initiation
Sometimes there may be a requirement for the program to invoke flow control automatic

ally; for example,

when internal buffers become full. Under these circumstances, the DHV11 provides
a FORCE.XOFF
bit; this is bit 5 of the line control register. When the FORCE.XOFF bit is
set, the DHV11 transmits an
X-OFF character for that channel, and a further X-OFF bit is transmitted
for every second character
received on the channel. An X-ON is sent when the FORCE.XOFTF bit is cleared.
F igure D-3 illustrates
the operation of program-initiated flow control.

D-3

CHAR RCVD

FORCE.XOFF=1

CHAR RCVD

CHAR
RCVD

FORCE.XOFF=1

FORCE.XOFF=0

CHAR RCVD

FORCE.XOFF=0

RD2253

Figure D-3

Program-Initiated Flow Control

NOTE
The X-ON and X-OFF codes are not transmitted
instantly, because of firmware delays in seeing
and acting on the program requests; therefore, if
the FORCE.XOFF bit is set and then immediately
cleared, this does not cause an X-OFF/X-ON
sequence to be transmitted.
The FORCE.XOFF

bit is set to zero by a DHV11 reset sequence.

D.3.3
Mixing the Two Types of Received Data Flow Control
To calculate the effect of using the two modes, they should be logically ORed together; an X-ON will not
be sent until both sources are inactive. f FORCE.XOFF is set while the FIFO-critical mode is active, the
SEND XOFTF is immediately entered even if an X-OFF has just been transmitted. If the FIFO-critical
mode becomes active while FORCE.XOFTF is set, an X-OFF is sent in response to the next received
character.

D-4

APPENDIX E
INSTALLATION GUIDE FOR THE DHV11 REMOTE
DISTRIBUTION PANEL CABINET KIT

E.1
GENERAL DESCRIPTION
The DHV11 remote distribution panel cabinet kit (Figure E-2) allows eight RS-232 data-only serial lines
to be distributed from one type-B (6.60 cm X 8.38 cm) (2.60 in X 3.20 in) bulkhead panel.
This arrangement overcomes limitations of space in the host system by doubling the number of DHV11
serial lines that can be installed in the host’s I/O panel.

Four variations of the cabinet kit are available. The cabinet kit contains the following components.
.

H3176

H3175

Bulkhead panel — fits into one type-B I/O panel cutout in the host system.
Remote distribution panel — contains eight 25-pin D-type subminiature
connectors.

BC22H-10

25-conductor external 3-metre (10-foot) cable — connects the H3175 remote
distribution panel to the bulkhead panel.

BCOSL-xx *

40-conductor internal ribbon cables (two) — connect the DHV11 module to the
inside of the H3176 bulkhead panel.

H315-B

Loopback connector (one).

Screws

6-32 screws (four) used to attach the H3176 bulkhead panel to a system I/O
panel.

74-28684-01

Adapter plate (-VC cabinet kit only). Adapts the H3176 bulkhead panel to the
PDP-11/23+ H349 distribution panel.

The cabinet kits are listed in Table E-1. The difference is the length of the internal cables.
Table E-1

Cabinet Kit Details

Cabinet Kit

Internal Cables (Two)

Where Used

CK-DHV11-VA

BCOS5L-1K (53.34 cm, 21 in)

BA123 enclosure

CK-DHV11-VB

BCO5L-01 (30.48 cm, 12 in)

BA23 enclosure

CK-DHV11-VC

BCOS5L-2F (76.20 cm, 30 in)

PDP-11/23+ H349 distribution panel

CK-DHV11-VF

BCO5L-03 (91.44 c¢m, 36 in)

H9542 cabinet systems

* Cable length varies — see Table E-1

E-1

LOW CHANNELS (0-3)

HIGH CHANNELS (4-7)

DIAGNOSTIC LED
BERG CONNECTOR

[

BERG CONNECTOR

]

[

ADDRESS

ADDRESS AND

SELECT

VECTOR SELECT

EG8

E43

BI"’LA

[

BACKPLANE CONNECTORS
MR-14074

Figure E-1

DHV11 Module

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FUNCTIONAL DESCRIPTION

E.2

H3176 Bulkhead Panel

E.2.1

The H3176 bulkhead panel consists of two 40-pin vertical headers and a fully filtered female 25-pin
D-type subminiature connector. The H3176 is connected to a DHV11 by two BCOSL-XX cables which
bring eight pairs of data signals (transmit/receive), plus signal ground for each pair, to the H3176. There is
also a connection to chassis ground, using a 0-ohm jumper. This jumper can be cut if chassis ground is not
desired.

Overall dimensions: 8.38 ¢cm X 6.60 cm (3.3 in X 2.6 in)
E.2.2

H3175 Remote Distribution Panel

The H3175 remote distribution panel distributes the eight pairs of data signals (transmit/receive), plus
signal ground for each pair, to eight male 25-pin D-type subminiature connectors. The connection to the
H3176 bulkhead panel is made by the BC22H-10 cable.

Overall dimensions: 27.94 cm X 8.37 cm X 1.78 cm (11 in X 3.4 in X 0.70 in)
BC22H-10

E.2.3

The BC22H-10 is a 3-metre (10-foot) male-to-male 25-conductor D-type subminiature fully shielded
EIA cable.

BCO5SL-XX

E.2.4

The BCOSL-XX cables are 40-conductor flat ribbon cables. The length of the cables depends on the
system in which they are installed.
E.3

INSTALLATION

The DHV11 remote distribution panel cabinet kit is installed in a system in the same way as an ordinary
cabinet kit.

Slide the DHV11 module (Figure E-1) partially out of the system backplane.

Insertthe two BCO5SL-XX cables into the two Berg connectors onthe DHV11 module. The red
striped edge of the cables should be installed onto Pin A of the DHV11 module Berg
connectors.

Reinstall the DHV11 module.

Ifyou are installing this cabinet kit into a PDP-11/23+ system, install the adapter plate (part
number: 74-28684-01) into one of the 4X4 openings in the H349 distribution panel.

Install the H3176 bulkhead panel into the system I/O panel using the four 6-32 screws.

Insertthe BCOSL-XX cables into the rear connectors of the H3176 bulkhead panel. Attach the
cable from DHV11 connector J1 to the top connector of the H3176, and the cable from
DHV11 connector J2 to the bottom connector. There are small arrows on one edge of the
H3176 internal connectors. The red striped edge of the cables should be attached to the arrow
side of the H3176 connectors.
This procedure ensures that there is a one-to-one correspondence between the labeling of the
H3175 and the actual physical line numbers of the DHV11. If this procedure is not followed,
the physical line numbers will not correspond to the H3175 labeling (0 to 7).

Insert the BC22H-10 cable into the external connector of the H3176 bulkhead panel.

E-4

Insertthe BC22H-10 cable into the bottom ‘Input’ connector of the H3175 remote distribution
panel,

Place the H3175 remote distribution panel in a location that is accessible, but where it will not
be disturbed. The H3175 has three tear-drop cutouts at both the top and bottom so that it can be
mounted on a wall three different ways, or on the floor.

E.4

DIAGNOSTICS

Diagnostic testing for the DHV11 remote distribution panel cabinet it is available for MicroPDP-11 and
MicroVAX II systems. Contact your local DIGITAL sales office for the order numbers of the diagnostic

kits.

E.4.1

MicroPDP-11 Diagnostics

The following MicroPDP-11 diagnostic tests are used for the DHV11 remote distribution panel cabinet

kit.

e
e

CVDHBE (revision level E)
CVDHC? (? = revision level D or E)

CVDHCD (test C, revision level D) will be available in November of 1985. CVCHBE and CVDHCE
will be available in February of 1986, in release 126 of the MicroPDP-11 field service kit.
E.4.1.1 CVDHBE Test - CVDHBE tests the ability of the device to transmit and receive characters
correctly. It tests features such as automatic X-ON/X-OFF, correct operation of modem bits, and
whether there are any bad interactions between modem signals, data signals, or other lines.
From the XXDP+ prompt (.), run the test and reply to the set-up questions as follows (the replies are
either underlined, or explained in parentheses).
.R VDHBEQ
DR>START

CHANGE HW (L)

? Y

# UNITS (D) ? 1

UNIT 0
CSR ADDRESS: (0) 160460 ? (Enter the CSR address of the DHV1l, or just press
RETURN if the CSR address is 160460)

INTERRUPT VECTOR ADDRESS: (0) 300 ? (Enter the interrupt vector of the DHV1l,

or just press RETURN if the vector is 300)

ACTIVE LINE BIT MAP: (0) 377 ? (Press RETURN)

TYPE OF LOOPBACK (1=INTERNAL, 2=H3277, 3=H325, 4=H310l1, 5=H3103, 6=70-22629,
7=H315-B):

(0) 2 ? 1

INTERRUPT BR LEVEL: (0) 4? (Press RETURN)
CHANGE SW (L)

? N_

E4.1.2 CVDHC?0 Test — (?=revisions D and E.) CYDHC tests DMA and split speed. It al_so tests
modems and terminals, and verifies that data integrity checks (such as framing and parity checking) are
working,
From the XXDP+ prompt, run the test and reply to the set-up questions as follows (the replies are either
underlined, or explained in parentheses).
.R_VDHC?0

DR>START
CHANGE HW

# UNITS

(L)

(D)

? ¥

? 1

UNIT 0
CSR ADDRESS:

(0)

160460

(Enter

the CSR address of

the DHV1l,

RETURN if the CSR address is
INTERRUPT VECTOR ADDRESS:

(0)

300

(enter

or
ACTIVE

LINE BIT MAP:

(0)

377

just press

160460)

the interrupt vector of

just press RETURN if

the DHV11,

the vector

300)

(Press RETURN)

NOTE
The choice of loopback connectors differs between
revision D and E of this test, as follows.
Revision

TYPE OF

LOOPBACK

(CVDHCDO):
(1=INTERNAL,

(0)

Revision E

2=H3277,

(Select 3,

3=H325,

4=MODEM,

5=KEYBOARD ECHO):

but use the H315-B)

(CVDHCEQ):

TYPE OF

LOOPBACK

6=H3101,

7=H3103,

(1=INTERNAL,

10=70-22629,

2=H3277,

3=H325,

11=H315-B):

(0)

4=MODEM,

5=KEYBOARD ECHO,

?°11

When you have chosen the appropriate loopback connector, continue as follows:
INTERRUPT BR LEVEL:

CHANGE SW

(L)

(0)

(Press RETURN)

?jl

E.4.2
MicroVAX II Diagnostics
MicroVAX II diagnostic tests for the DHV11 remote distribution panel cabinet kit are in the MicroVAX
maintenance kit. The MicroVAX maintenance kit is available on RX50 diskettes or a
TK50 cartridge.

These kits contain the MicroVAX Maintenance System (MMS). The MicroVAX Diagnostic Monitor
(MDM) in MMS is used in conjunction with the H315-B loopback connector to test a suspected bad serial
line on the device. Load the media according to the instructions in the maintenance guide included with the

kit.

When you reach the main menu, select:
4 — Display the Service Menu

From the service menu, select:
4 — Enter System Commands

Two modes of testing are available in MDM
- verify and service. Tests in service mode require the use of
loopback connectors, and may destroy customer data. Use service mode to test the DHV11 remote
distribution panel cabinet kit. Write-protect all mass-storage devices before running the test.

Each mode is divided into three sections — functional, exerciser, and utility. Tests in the utility section are

typically interactive. Use the utility sections to test the DHV11 remote distribution panel cabinet kit.

To get a list of the MDM commands, enter ‘help’ at the MDM prompt. Refer to the MicroVAX
Maintenance Guide for a detailed explanation of MDM.

After selecting ‘4 — Enter System Commands’, press the RETURN key to start MDM. From the MDM
prompt, ‘MDM>>>" enter the following sequence.

Prompt

User Response

Meaning

MDM>>>

setpf

Set progress full

MDM>>>

set det on

Set detailed messages on

MDM>>>

set mod serv

Set MDM to service mode

MDM>>>

set sec util

Set section to utility

MDM>>>

conf

Configure the system

MDM>>>

sho conf

Show the configuration

MDM>>>

sel 4

Select the number of the DHV11 you want to test from the displayed
configuration (4 here is an example only)

MDM>>>

settest 1

Select the staged loopback test

MDM>>>

Start the staged loopback test

At this point a series of set-up questions appear. The
default responses appear in brackets. Press the
RETURN key (KRET>), if you want to enter the default
response. The default responses are valid for the
DHV11 remote distribution panel loopback test, with the
following exception.
o

The default response [y] of the first question (test modem control
lines?) will not correctly test
the remote distribution panel, since it is a data-only device.
Answer NO to this question.

The set-up questions appear as follows (the replies which you

explained in parentheses).
Do you wish

test

should give are either underlined, or

modem control

lines?

[y]

like to test

(0-7)?

[all connections]

Which port would you

Which baud rate would you

like to test?

(0-15)?

[13]

<RET>

(Press RETURN to test at
9600 baud,

How many data bits

Parity enabled
Parity sense

Number of

(5,

(Yes =

(1 = even,

stop bits

enter

list the baud-rates)
7

No =

8)?

[8]

<RET>

0)?

[0]

<RET>

0 = odd)?

[0]

<RET>

(1 or 2)?

[1] <RET>

Attach the H315-B loopback connector to the port to be tested and press the RETURN key. The test will

run and the results of the test will be displayed.

If you want to test another port, or restart the diagnostic program for any reason, you must reconfigure the
system. To do so, begin again at the ‘conf’ command:

MDM>>>

conf

and continue with the remainder of the sequence listed above.

E-8