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EK-DHQ11-TM-001

February 1987

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Document:	DHQ11 Technical Manual
Order Number:	EK-DHQ11-TM
Revision:	001
Pages:	142
Original Filename:

OCR Text

EK-DHQ11-TM-01

DHQ11
Technical Manual

dliigliltiali]

U
.

EK-DH@14-TM-O1

IHQ'M

Technlcol Mcnucl

. EK-DHQU-IM-O1

DHQ'M

Technlccl Mcnuol

Prepared by Educatnonal Services
|

Dugltal Equnpment Corporat:on

[]

First Edition. February 1987

The information in this document is subject to change without
assumes
Corporation
Equipment
Digital
notice.
responsibility for any errors that may appear herein.

Printed in US.A.

g are trademarks of Digital Equipment
owin
foll
The
Corporation:
DEC

- DECmate

DECsystem-10
DECSYSTEM-20

DECUS

- DECwriter

DIBOL

RT-l1

POS
Professional

VAX
~ VAXBI

- PDP

MASSBUS.

Rainbow
RSTS

- RSX

UNIBUS

VMS
VT

Work Processor

SRR

> )

CONTENTS
PREFACE

e L2 D —

Preventing Data Loss ..., R P

Physncal Description ......... B AR R U
On-Board Switchpacks .............................. U

P
D

-3

Versions Of The DHQll T e Lo
ConfigUrations ............c..ciiiiiiiiei i e

14
1-4

Connections

1-6

........e

e ese e
e nay e

<—‘

—

S LN
—

LmeTransmxtters e iR e R
T
o
Speed And Distance Conmderanons PP
- ,FUNCTIONAL DESCRIPTIONi NP
|

PN
-

19
—

-2

£
T
Electrical Requirements ................ ...oo, P
]
~
Q-busLoads ............... L P e 1-8
Performance .............ciiiiiiiiiiiiii s, e DI
1-8
Data Rates ...........cooviiiiiiiiiiiiiiie, P oo,
18
Throughput ...............ccoiininn.... TS P
.1
SERIAL INTERFACES ...........cooiiiiiiiiiiiia, [ S 19
Interface Standards ........................ e PO
£
Line Receivers ...............
...
..ooe. P
£ 01}

Gener-al R

R SO
C IE O

‘Main Functions .~ ;g. oo

OCTART Chip

| INSTALLATION

O3 (1
£ () I
3 2
£ V4

AP e Le120

Control Chip ......oooiiiiiiiiiiie i, PO N

e oo

£
1-2
P

SPECIFICATION ....... e PR B
SR
Environmental Conditions ........ S ST o

g
g
g
pmal)

General Description ... ...B B
S ST R
“Modem Control Facility ........ T e SR
Self-Test Facility ...... e
e e e AU
Diagnostic Programs ....... S
N
el

CHAPTER 2
121212121219 19 19

A
S
BN
e ISR
B

Communications Standard ................... e

Sinbnbbarbrbhbhobbbuiviig

- INTRODUCTION
"SCOPE ..................... R T P
"OVERVIEW .............. R

I 1991219219019
—

| geemess pem—e gpm—

1
CHAPTER

R PR

£ I

SCOPE....... e R T
T
U
S e
241
UNPACKING AND INSPECTION e
g
ee
241
- PREPARING THE DHQI1 MODULE ..................... SR
2-2
- Address And Vector Ass:gnment e
e
e et
293
Setting The Address Switches .. ... S e P e
223
- Setting The Vector Swntches e
e e e e e 25
BUS CONTINUITY ...l A
2-6
Bus Grant Continuity Jumpers ......................................
2-7

19 19 19 19 12 19 19 19 19 12 19 19 19 19 19 19 19 19 N 19 19 10

5.1
5.2

5.3
6

6.4

7.1

Installing The M3107 Module ................... SA
‘Distribution Panels .................................. e
[nstalling The EIA-232-D Distribution Panels .......................

Installing The DEC423 Distribution Panels .......... e

INSTALLATION TESTING ................... P

2-8
2-8
2-8
2-8

2-8

2-11
211

o240

ST RIS212

Staggered Loopback Test Connector H3277 ............ 23
~ Line Loopback Test Connector H3197 e 2418
H3101 Loopback Connector ....... R
See
2413
- H3103 Loopback Connector ..................... PR e
24T
CABLES AND CONNECTORS — EIA-’37 D..... P e L 2-17
Distribution Panel ............... e Wil ceeee
2417

8.3
8.4
9
9.1
9.2
9.3
10

Null Modem Cables
........
e
Full Modem Cables ................... B
o221
CABLES AND CONNECTORS — DEC4" .............. R 2-22

CHAPTER 3
|

2.1
2.2
2.2.1
222
2.2.3

2.2.5
2.2.6
2.2.7
2.2.8
2.29
3
3.1
3.2
3.3
3.3.1
3.3.2
3.4
3.5
3.6
3.6.1
3.6.2
3.6.3

3.6.4

2.8

DIAGNOSTIC TEST CONNECTORS................... ... e RS

8.1
8.2

3.7

iiee ..

S
e oo

[nstallation Tests On MicroPDP-11 Systems ............. 2402
Testing In MicroVAX II Systems ............................. R
2-13

7.2

2.2.4

DMA Request Priority ..............S
Interrupt Request Priority ............. e

Recommendations ........................ ...l e.
INSTALL
THEING
DHQI1 .................... e e

6.1
6.2
6.3

PRIORITY SELECTION .......... R e e

PROGRAMMING
-

SCOPE ................... e
b eee e s SVA
SR
08 |
"REGISTERS .............. e
e
e
e
e
3A]
~
Register Access ..........B
R SRR

Register Bit Definitions ................. I S PR
Control And Status Reglster (CSR) .......... S e
- Receive Buffer (RBUF)............................ e .
Transmit Character Register (TXCHAR).......................

Line-Parameter Register (LPR) ................................

3-2
33
36
3-7

3-8

)

- Line-Status Register (STAT) .......................... e.
3-10
|
Line-Control Register (LNCTRL) P
PN
) 17
Transmit Buffer Address Register Number | (TBUFFADI) ..... - 3-15
Transmit Buffer Address Register Number 2 (TBUFFADZ) ceee.
3-16
Transmit DMA Buffer Counter (TBUFFCT) ............... e
3417
PROGRAMMING FEATURES ........SRR L e ee
3-18
|
[nitialization ................. S TR ..
3-18
Configuration .......... e et e i e
3-19
Transmi‘tting e T S s
3419
|
DMA Transfers ........................ POe . 3-19
- Programmed [/O ....... e e v e e eeeeae.
3220
Receiving .......... T
R S eP
)
~Interrupt Control ................... PR EORT
AR AR e oo 3220
- Auto XON And XOFF ...... T e e
3221
|
IAUTO ......... T A A L
A Pe 3
FORCE. XOFF R ERR
Pe
3922
)
OAUTO .............e
eB e
322

DISAB.XRPT

Error Indication

........... e sa e e e

e e

e o322

.................... T
O SD

322

338

Modem Control

3.3.9

3.3.10

Diagnostic Codes ...... P il ee i

3.3.10.1

3.3.10.2

3.3.10.3
3.3.10.4

341

)

Configuration .......... e
e ee

3927

TransmItting ...t e

328

3432

DMA Transfer ...........T

AR e

3229

e IR

3-31

Checking sznostrc Codes ...

3-33

Aborting A Transmlssxon

344

345

CHAPTER4
4.1

44,1

)

Auto XON AndXOFF e
e e

S PP R

e es

PR {1

PREVENTIVE MAINTENANCE ........... PR e PUUEER5
TROUBLESHOOTING PROCEDURES ...... B - 1

INTERNAL DIAGNOSTICS

SelfTest

..... ket T e el

e[ N

Background Momtor Program (BMP)

422

4.3

45
~
MicroPDP-11 DIAGNOSTICS ......... e T
et e s
43
451
- User-Mode'DiagnoStics R PPe
43
4.5, 1 s
Running User-Mode Tests ................. U .
43
46
chroVAX II DIAGNOSTICS R SR PP - 4-3
46.1
User-Mode Tests ........... B R RS Y
X
4.7
~
USING THE LOOPBACKS ........occooiivnii.., P e P
4-3

471

473
474

4.8
48.1
4811
482
49
49.1
492
493
494
410

5.1
5.2
5.3

)

Recewving ..., i e O

SCOPE .......L L4l

- H3277 Staggered Loopback Test Connector e e

472

T A

TROU BLESHOOTNG

44.2

’

it Lo

3-28

346

3-24

Single- Character Proerammed Transter e S

Ry
4.2
>
43

Skipping Self-Test ........................... e e 3-24
Background Monitor Program (BMP) ........... PR .
325

................... P

323

326

3433

Interpretation Of Self-Test Codes

3.23

3-23

Resetting The DHQIL ............i P co.3-26

343

Self-Test Diagnostic Codes .........................
.. ...

323

PROGRAMMING EXAMPLES...................... PP Lo

342
_\

................... U S SR

Maintenance ProgrammmgA
SO
e

5.3.1
3.3.2

3.3.2.1

H3197 Line Loopback Test Connector ........... PP

H3101 Loopback Connector .....................R
H3103 Loopback Connector

...

43
-=

44
44

MicroPDP-11 SERVICE-MODE DIAGNOSTICS S e e e P L0
45
chroPDPllFuncnonalDlagnostxc T
O TS e
45
|
‘Test Summaries ........... e el e v s 4.5
'DECXI! Object Module ...... T
Ve e e e
eeR
MicroVAX II SERVICE-MODE DIAGNOSTICS e et cive.
410
‘Configuration Tests .............. AN F
P o 410
Field Service Functional Tests ....... .. R e e
4410
.
Field Service Exercxser Tests .......... PR I
28
}
- Utilities ........e
e B
B
TS N S
- 4-11
eA

3-12

SCOPE ... .. e e
e
R
OVERVIEW ..... T s
DHQI!1 FL\ICTIO‘\JAL BLOCKS ............... L i
e e

FIELD-REPLACEABLE U\IITS (FRUS)

RAM ....... e e
e e
e
OCTART ........... e Pe ST
T TS
s

“Control-Chip lntertace

........................................

315

-15

4-15
3-17

4-18
318

Loop-A
Control ..............
rou
..............
nd.... .. . L. 4-18
Baud-Rate Generator B
T- 4-18
| Control Chip ...... BT U i, AR - 4-18

LN —

PN ULBLLbLLLLLLDNDNN
N

PhhpULUULULUVLULLLWLWLLLWLLGLWLWL

MUUUUUULUULUUUUUULUKUGB
KK,
W

Line-Pa_rarneterRegister e

Modem-Status Multiplexer ........ P e .

Timer And RAM Test Sequencer (TTR)

Q-bus

Interface (QIF)

e i - 4-18

..................

....

4-19

00 4O\ W £

DMA Fast Sequencer (DMF) en
o R T SV 419
DMA Slow Sequencer (DMS) ..... T e 419
Data [.O Sequencer
(DIO) ..................... e
319
UART Fast Sequencer (UAF) .......................U 4220
UART Slow Sequencer (UAS) .......... U [ Lo
$20
RAM Arbitrator (RARB) ........... .. 30
Swntchpack And Shitt Registers .................... 422

Q-bus Drivers And Receivers ...........................SN Lo 423

[

o —

Modem Latches ..................c........... T
4-23
Line Interfaces ............. S
N
SS
. 1 )
|
Power Converter .......... P e A e
250
DATA FLOW ..... e e PR . B
T
4-27
Data Flow For Character Receptxon ...... e
e e e
427
‘Data Flow For Character Transmlssxon e
e [ ceis
4227
DMA Operation ................. PR e e 327

5422
-

Programmed I,’O Operanon Te

42T

APPENDIX
A

MODEM CONTROL

A.l

SCOPE ...\ i)
ee,G e ASL

MODEM CONTROL

......ocovvieiiininn.., I -18

Example Of Auto-Answer Modem Control F or The PSTN ..........

A.2.1

APPENDIX
B FLOATING ADDRESSES ,

A-2

FLOATING DEVICE ADDRESSES R
Bl
‘FLOATING VECTORS ...........RS N
NP eeee...
B3

AUTOMATIC FI..OW CONTROL

bl
—

OVERVIEW .....oooooooeoo

HeleleYoYeTe

APPENDIX E

i C

CONTROL OF TRANSMIT'TED DATA ........ EERTRRE P
CONTROL OF RECEIVED DATA ........................... e
Flow Control By The Level Of The Recewe FIFO e P .
Flow Control By Program Initiation ................................
- Mixing The Two Types Ot' Recewed Data Flow Control T

APPENDIX D GLOSSARY OF TERMS

CSCOPE ..oovveeie e e
GLOSSARY

Ree

DHQll Q BLS CO\NECTIOVS

&
CC
Ce

...

D-l

- D-1

CONTROL CHIP AND OCTART — PINOUTS

APPENDIX F
F.1

SCOPE .................. e

e e

e ese
eU

.......e P ETTTRrEy B R

Figure No.

Title

-1

Layout of the DHQI1 Module ...... R DS .

-3

DHQI1 Connections| EIA-232- D) ........... P

o PP G2 09 1D B2 DD DD 19 1D 10 19 P12 1D 1D 10— — — — —

"OCTART

-2

Page

Location of Switchpacks

-2
-3
4
-5
-6
-7

..................e S S

|-7
-14

.24
2-3
246
2T
210
2-10
2-11

[/O Insert Panel (DEC423) ..............ccovi... B

A
SL.

2-12

Voltage Converter ............. P e P

4-26

Receive Character Data Flow ................. i T
Lo
Transmit Character Data Flow ......... e
e
e
e
Transmitted Data Flow Control ........................ R R Selin
- Receive FIFO-Level Flow Control ............... e
‘Program-Initiated Flow Control .............. e T i

4-28
4-29
C-2
CS3
C4

H3277 Staggered Loopback Test Connector ................ e
2414
H3197 Line Loopback Test Connector ................... e oo
2415
-~ H3101 Loopback Connector ......... e e
2-16
~
H3103 Line Loopback Test Connector e e e 2-17
H3173-A Circuit Diagram .............. e e
e,
2418
Null Modem Cable Connectxons ......... e FE
Pe
2221
Register Coding ...................... e e e
e e e
3-3
Troubleshooting DEC423 Installanons T e e
o 4.2
Using Loopback Connectors in EIA-232-D Installatxons eI
.
Using Loopback Connectorsin DEC423 Installatxons e e AU ..
45
DHQI!! Block Diagram ...............e
e
e
AU .
4-14
RAM Assignment ................ e ee
416
OCTART ................ e e e R
2 Y/
Switchpack and Sluft Regxster Logxc e e i et 422
Modem Latches .................... P
T e P - 4-24

-7
-8
C-1
C-2
C-3

-1

P 16

Setting the Device Address ............................... P
Setting the Vector Address .................. e S
e vt L.
- Bus Grant Continuity ..... e e
~Installing the DHQHEIA 232-D) e ..
[nstalling the DHQI1 (DEC423) .................. e i PR
[;O Insert Panels and Adapter Plate (EIA- 732 D) ..... S

-6

Table No.

i mee e e s

DHQ!1!l Connections (DEC4
..............A
DHQ!! Functional Block Dld21’dm e
e

-1

F-3

Example of a DHQI1 Configuration

-4
-5

F-l

" F.3

9
-10
-11
-12
-13
-14
-1
l
2
3
1
-2
-3
-4
5

F-1

CONTROL CHIP ...e .o...

TABLES

Title

Page

EIA.CCITT Signal Relanonshxps

e PR S O T 19

Maximum Dtstance Guidelines for DHQll

Ve F

£ B

-1

DHQIl Optlons

e ee e

]

..... P i

—

DD e

mq:m >

W
— W N

H3173-A Connecnons AR PO

SRD S e

2419

- DHQI! Registers ............cooooiiinnin.. ii i e
~ Data Rates ..... S
s it e i e L.

3.1
3-10

Floating Device Address Assngnments eS AU ...

B-l-

Serial-Line Connections for the 36-P1n Connector ...........eL

DHQllSelf-TestErrorCodes R
e
Modem Control Leads ........................ S et ieen..
Floating Vector Address Assxgnments e
iP
-~
DHQI! QBusConnectxons R P R

viil

2-22

3.24
A-1
B-3
-1

PREFACE
The DHQ 1 Technical Manual provides reference information on physical layout, system configuration,

installation and testing, programmmg characteristics, and maintenance. There is also a glossary of

technical terms generally usedin DIGITAL technical manuals. The manualis dmded mto five chapters S

as follows:

CHAPTER ] INTRODUCTION This chapter g1ves a physxcal descnptlon of the DHQll explams B
how it can be configured and explains how it mterfaces with the system bus and serial data lines.

CHAPT ER 2 INSTALLATION Chapter 2 descnbes how to install a DHQ!1 option, thh detailed

- information on device and vector address selectxon backplane posxtlomng, cables and connectors and :
testing after installation.

CHAPTER 3 PROGRAMMING Thxs chapter descnbes the DHQIl11 reglsters Some programmmg
examples are also 1ncluded

CHAPTER 4 TROUBLESHOOTING Chapter 4 explains the maxntenance strategy, and how to use
dlagnostxc programs to locate a faulty module

CHAPTER § TECHNICAL DESCRIPTION Thxs chapter gives a techmcal descnptnon of the DHQI 1
asynchronous multlplexer It is assumed that you have some knowledge of Q-bus operatlons

| APPENDICES These 1nclude addmonal lnformanon on topncs dxscussedin this manual

APPENDIXA

APPENDIXC

AUTOMATIC FLOW CONTROL

CONTROL CHIP AND OCTART

APPENDIXB

APPENDIXD
APPENDIXE

)

“

APPENDIXF

MODEM CONTROL

FLOATING ADDRESSES

GLOSSARY OF TERMS
DHQIl BUS CONNECTIONS

- l1

'CHAPTER 1
INTRODUCTION

SCOPE

1 asvnchronous multiplexer. descrxbes the teatures that 1t
- This chapter gives an overview of the DHQI
electncal requtrements
and
parameters
phvsxcal
) ofl‘ers and defines1S
) 1.2 OV ERVIEW

121 General Descnpnon 5

The DHQI! option is a serial-line mtertace W h:ch provides etaht tull-duplex serml data channels on

Q-bus systems. The DHQI11 option consists of a single Q-bus module. and one ot two groups ol cubinet

- kits, dependtng on the communication standard supported The cabnnet klIS contain the cubmet
bulkhead panels and connecung cables.

| -The main apphcatton of the DHQll is Gt interactive termmal handlmo It can also be used tor data

concentration and real-time processing. The DHQl l remster set 1s comp 1ble with the remster set of the.

o -'DI-IVll ‘I'hemam features of the DHQll are:

e . : -,Erght full-duplex asynchronous data channels o |
@

For transmxssxon DMA transfers or program transfers toa l~character transrmt bufl'er for

IR -each hne

® For receive: a 256-entry FIFO buffer for recewed characters dataset status changes and
~diagnostic lnformatxon

'It supports EIA-232-D/V 28 or DEC423 w1th theappropnate cabmet klt -

NOTE

DEC423is a term used in thls manual to mdlcate a
data-leads-only implementation of the RS-423-A

‘electrical standard. DEC423 uses MMJ connectors

- lnstead of the 37-way connectors specrfied by RS-449

| 0 | It 1S compatxble w1th all DIGITAL DI-IVll device dnvers |
®

Itcan auto-answer on a swuched lme

0 The transmxt and receive baud rates loreach line can be lndi»'iduallx' proararnmed
e It has a total module throuahput of60 000 characters per second using 3-bit characters. with
-all channels operatmg at 38.4 kbaud for both character receptlon and transmission

}The DHQll supports 16- 18- or 22 blt addressmsz mcludlna blocl\mode data transler mth
suitable memories

The D“HQI 1 can be programmed to filter XON/XOFF charécters from the received data flow |

@ Self-test and background monitor tésting

Dual-height mddule; M3107

° ' Switchpacks for selecting the Q-bus base address and vector' éddreSS

All othér functions are selected'by program. |
1.2.1.1

Modem Control Facility— All eight channels have sufficient modem ~control to allow

- auto-answer dial-up operation over the public switched telephone network using suitable
modems, such

‘as DIGITAL's DF124, or Bell models 103, 113, 212. Equivalent modems from other manufacturers can
also be used. The DHQI! is designed to minimize software requirements for modem link control.
Appendix A gives further information on modem control. Modem control can be used for driving

modems over both public and private lines. Please note that, in some countries, modems must be

‘approved by the PTT for that country for connection to the public network.

1.2.1.2 Self-Test Facility— The

DHQI1

iné'brporaies' self-test sequencers which ‘operate

independently of the host. The result of the self-test is provided to the host system through the receive
FIFO buffer. A green LED indicates GO/NO-GO status for the device. More details are given ‘i'n Section
43.

l-.2.1,3 Dlagnostlc Progr'ams' - A full range of diagnostic' prdgi'éms is'availéb,le. Theserun undet the -

- MicroPDP-11 diagnostic supervisor
or MicroVAX
II maintenance system. Loopback test connectors
- are not needed when running the user-mode diagnostics. Service-mode .diagno_stics and
loopback
- connectors are available from DIGITAL.

1.2.1.4 Pfeventing- Data Loss - The DHQI! can be»pro,grammé‘d: for automatic XON and XOFF

operation, to prevent the loss of data at high throughput. The reporting of received XON/XOFF
Ccharacters to the software driver can be enabled or disabled. @~
o
|
1.2.2

Physical Description

The DHQ!1

is an M3107 dual-height Q-bus module. It is 21.6
cm (8.51 inches) long and 13.2 cm (5.19

inches) wide. Figure 1-1 shows the layout. Connectors A and B are for the Q-bus, while connectors

and J2 interface to the communications lines via BCOSL-xx cables and distribution panels. Two

distribution panels are supplied with an EIA-232-D option, and a single panel is supplied with
a
DEC423 option. Connector J3 provides power to the active distribution panel supplied with
DEC423
options. This connector is not used with EIA-232-D options. Mixed use, that is, one EIA-232-D
and one
DEC423 panel connected to a single module, is not supporte
by
d DIGITAL.

1.2.2.1 On-BoardSmtchpacks -"'TheDHQl.l has two on-board sWitchpacks to select the following

functions.

Switchpack E-19 (10-position)

Switches 2 to 10 select the device address.

@ :‘SwitchpackE-l‘il_'(8-p0.Sit;i'On) S
~

Switch 1 enables the on-board oscillator. This is a manufacturing test switch, and is closed for

normal operation.

Switch 2 selects manufactunng self-test mode Tlusisa manufactunng test swrtch and1S open
;

for normal operanon

Sw1tches 3 to 8 select the dev1ce vector address

Chapter, gives further mformatxon about these sthchpacks

1.2.2.2 Commumcatlons Standard — The serial drivers on the M3107 module are compatlble with
EIA 73’D. However. the CK- DHQll-W cabinet kits provrde level conversion for DEC4’3
a

|
: -

5 Io Y (A JZCONNECTOR
CHANNELS 4

Ipowsa *

CONNECTOR

-7

;
- ( | J1CONNECTOR \

)

CHANNELSO-3"_

OCTART

aooress |

CONTROL

CHIP

| vector |

10 POSITION 8 POSITION
SWITCHPACK

SWITCHPACK

Figure 1-1 Layout of the DHQ!I Module
-3

1.2.3 Versno- OfThe DHQI11
The DHQ11-M option consists of the M3 107 Q-bus module and the User Guzde It can be used wuh one
ofsix cabinet kits. The choice of kit depends on the type of system cabinet, and on whether a EIA-’BZ D
or a DEC423 commumcanon mterface 1S needed
|
|

The cabmet kits avaxlable for use w1th the DHQllM are:

ElA22D
o

CK- DHQll AA for BA1’3 BAI1-M boxes

e CK-DHQI l-AB_forw BA23 boxes

CK-DHQIUI-AF for H9642 cabinets

. DEC423

| ° CK-DHQI' lWA for 4BA123 BAI l-M boxes
¢ CK-DHQI |-WB for BA23 boxes
|
@

CK-DHQII-WF for H9642 cabinets

1.2.4 Configllratlons

‘

The DHQI!
1 can be used1m many dlfi'erent system configuratlo fs. Figure 1-2 shows a typxcal EIA 232 D

'apphcanon

)

| oevice | | pevice

HOST

PROCESSOR|

@Bus

LOCAL

EQUIPMENT

TERMINAL

SATA.

[

| CHANNELS

'MODEM
TELEPHONE

OR DATA COMMS
LINES

ANY

| ASYNCHRONOUS
DEVICE

~REMOTE

) EQUIPMENT
-

| ReEMOTE

| TERMINAL

PLTRCRANNELS

| 1t I t t i‘ o

—

- TERMINAL

- REMOTE

DHQ11 OR

‘ ;,Q-B’u.s‘v

| remore

—

"Figu'_re [-2

DHVI11T

|RemoTe

_|PROCESSORY|

E_x’éirnple'ot’ a DHQI11 Configuration

1.2.§

Connections

The DHQI11 moduleis connected dxrectly to the Q-bus by connectors A and B. Fxgures l 3 and 1-4 show

the mterconnecnons for EIA-232-D and DEC423

40-PIN BERG

CONNECTORS

CHANNELS

BACKPLANE (Q22/LSI11 BUS)

{0TO 3

H31 73 A
DlSTRlBUTlON PANELS

|~
-

BCOSL-XX

CABLE

25 PIN O-TYPE

CONNECTORS
|

b
(

“CHANNELS
4TO7

NOTE: BCOSL-01 = 30 cm (12 INCHES)
BCOSL-1K = 53 cm (21 INCHES)
~
BCO5L-03 = 92 cm (36 INCHES)

2¢l

B Figure 1-3 DHQI1 Connections (EIA-232-D)

BACKPLANE

00 ACTIVE
70-22775-XX ~H31
BULKHEAD PANEL

COLQOURED STRIP

— (Q22,LSI BUS)

- POWER CABLE

40 PIN BERG

" CONNECTORS
H3104 CABLE

CONCENTRATOR

BCOS5L-XX

CABLE

NOTE

BCO5L-01 =30cm (12 INCHES)
- BCOSL-1K=53cm (21 INCHES)
BCOSL- 03=92cm (36 INCHES)

Figure 1-4 DHQI! Connections (DEC423-) |

13 SPECIFICATION
1.3.1 Environmental Condmons

The following environmental constramts t‘or storage and operatton apply to the DHQll
o

,The storage temperature must be wrthm the range O degrees Cto 66 degrees C(32 deerees Fto
151 degrees F).

@
-~

The operating temperature must be wrthm the range 5 degrees C to 60 degrees C (41 degrees F
to 140 degrees F).

When operatmg, the relatwe humtdtty must be within the range 10 percent to 95 percent -

non-condensing. at a maximum wet-bulb temperature of 32 degrees C and a minimum dew
.poxnt of
2 degrees C.

DIGITAL normallv defines the operatme temperature ranze for a system as 5 deerees C to 50 deerees C

(41 degrees F to 122 degrees F): the 10 degrees C dxfi'erence between the upper llmxts quoted allows tor

| the temperature gradient w1th1n the system box

The maximum operating temperatures must be derated
by 1.8 degrees C/lOOO m above sea level (1
degree F/1000 ft) for operation at high-altitude sites.
1.3.2 Electrical Requirements
The DHQll needs the following electrical supphes
@

ForEIA- 232 D optxons 5 volts dc plus or minus § percent at 1. 8 A
rnaxtmurn current 1.4 A
typical

For DEC423 opttons 5 volts dc plus or rmnus 5 percent at 2.3 A maximum current, 1.9

| t)’P tcal

o ‘For EIA-232-D and DEC423 optxons 12 volts dc plus or mmus 5
percent
rnaxxmum 300 mA typical

at 380 mA

| An on-board switched- mode power supply generates alO A supply t’or the senal line drivers.
| 13 2.l

Q-bus Loads- The loads apphed to the Q-bus are:

532 ac loads '
e 05 dc loads

1.3.3 Performanee

1331 DataRates - Each channelcan?be separately programmed to operate at one of 16 speeds (in
bits/s):

50
75
110
134.5

1800
2000
2400
4800

150

7200

300
600

1200

9600

19200

38400

NOTE .'
See also Section 1.4.4 (Speed and Distance
Conslderano-)

Chapter 3 contams further mformatton on data rates for EIA 232 D
1332 Throughput - Each channelis capable of full-duplex operatton at the maximum data
rate. The .
followmgma Ximum throughputis obtamable

At7 bits per character wnth | start b1t 1 stop b1t and l partty btt the throughput1S 61440

characters per second

-8

® AtS bnts per character, W1th l start bnt, 1 stop bit, and no panty, the throughput S 87771' o
characters per second

o This throughput may be lumted by your dnver software.
1.4 SERIAL _INTERF ACES,
1.4.1

Interface Standards

- The DHQ!1 provides modem comrol suznals which conform to EIA,;CCITT standard EIA 232-D V.24, | |
“standards. The slew-rate requxrements for RS-423-A. V28 are dlfierent from the slew-rate requxrements |
|

tor X. ’6 V.10.

'r/ -

The electrical characteristcs of the data signal lines conform either to EIA-232-D V.24 or to

RS-423-A,V.28. depending on which cabinet kit is fitted. The interfaceis compatible with X.26 V.[0

Connections to external equnpment are made via 23--pin male subrmmature Dt\pe connectors as

specified tor EIA- "3" D or 6-pin \/I\rU connectors for DEC423.

NOTE

The H3173—-\ dlStlellthll panel does not support
separate transmrt and receive grounds

| Table 1-1 shows how the sngnals In. EIA 737 D V.24, and RS-449 Are related and hsts the pln
connecnons for male subminiature D-type connectors
|
|
|
|
_

Table l l

Signal Name
Sl

f
b

R (SIG‘! .
GND

D-type

EIA-232-D' Circuit Circuit

Signal Ground - |

| RS-423-A Receive Common

Transmitted Daa
~
)

~* Not Connected

RequestToSed
- Clear
To :S’end‘

EIA/CCITT Slgnal Relatlo-hlps

(TXD)
(RTS)
: R

(CTS)

CCITT

RS-449

102B

103

105

VRS 5

- CB

106

Table 1-1

EIA/CCITT Signal Relationships (Cont.)

Signal Name
|

D-type
-

' Ring Indicator

EIA-232-D

Circuit
CCITT

135

Circuit
~

RS-449

(DS

107

Data Terminal Ready

o ,(DTR)"

CD :

1082 o

TR ;

Data Carrier Detect

109

‘RR

DataSetReady

(DCD)
»

l 4 2 Lme Receners

“The DHQ!! uses octal serial- hne receivers which convert line mput suznals to TTL levels tor the
OCTART. Suznals are inverted by the receners

143

Line Transmltters

The DHQI11 uses EIA transmitters whxch convert TTL level srgnals from the OCTART to line levels on |
the data hnes

14 4 Speed And Distance Consnderanons o

As of December 1985, the Electronics Industries Assocratron (EI A) have replaced the " RS- 1dent1fier |

~ for RS-232-C with “EIA”. Therefore RS-232-C has been replaced by EIA 737 D. These two standards

-are compattble with each other This rnanual uses EIA- 232 D.

e The RS-232-C/CCH'1' V. 28 standard was ongmally desrgned to specxfy the connection between alocal
-interface and a modem. It was not intended to be used for connecting to terminals over long distances.
~ The maximum specified cable lengthis 50 feet (15 metres). Shielded cable must be usedin order to meet
~ the requirements of FCC and VDE Radio Frequency Interference (RFI) regulanons
Although cable lengths greater than 50 feet can be used with reasonable success, cable capacrtance noise
and ground potential difference restrict the line speed as the distances increase. Consequently, the

performance of long-distance communications to a terrmnal using EIA- 732 D often does not meet

”today s requxrements for terrmnal wiring.

DEC423is a data-leads—only 1mplementatxon of the RS-423-A/CCITT V.10 standard. RS-423-A hasa
different groundtng and signal return path arrangement from EIA- 732 D.

- DEC423 uses line driver and receiver chxps whrch have better filtering and tighter level tolerances than
those specified by RS-423-A. In addition. DEC423 devices include transient suppressors for electrical
overstress (EOS) and electrostatic discharge (ESD) protectlon DEC4’3 dewces may also be connected

with unshrelded cable

The features 'provrded by DEC423 devices are reliable data communication over increaseddiStances.

typically 1000 feet (300 metres) at 9600 baud. See Table 1-2 for maximum-distance guidelines.

1-10

Table 1-2 Maicinium Disranee Guidelines for DHQ11
Upte

48Kb

9.6Kb

1000 ft

DEC423 to DEC423

1000 ft

300m

to EIA-232-D
DEC423

B0 f

2000

19.2 Kb

38.4 Kb

1000 ft

500 ft

300m

150 m

| The DEC473 >tandardis for data-leads-only eonnecuons to terminal equrpment and is not thabletor

~ connection to modems or other Wide Area Network equipment. The standard also specifies the use ot a

6-pin Modified Modular Jack
( \l\«U) connector. instead of the much larger 37-pm D-ty pe eonneeror
used with RS-423- A

DEC4’3 1S slznal-companble with the EIA-232D standard when used for data-lead: onlx
“interconnection. in that interconnection between devices using the ditferent standards is po::rble

However. the restncuons on the speed and dlstance of EIA- 232 D wnll still applv

DEC423 should always be used in preference to EIA-737-D for drrect termmal-connection overv
|
|
|
|
extended drstances
\IOTE

- An H3105 active tenmnal adapteris necessan when

using an EIA-232-D terminal with a DEC 423

interface if the longer cable lengths obtamable mth_'
- ’DEC423 are reqlnred
.

The recommended cable for DEC423IS BC16E XX, whxchis avarlable wrth 6-pm MMJ plugs at each ,

end, in lengths up to 100 feet. This cableis also available without MMJ connectors in 1000-foot reels,
DIGITAL part number H8220. Unshielded four-twrsted-pair cable can also be used Thxsis avarlablein

| ,lOOO-foot reels, DIGITAL part number HB8245-A

DEC423 to EIA-232-D is intended for local
communication. In general, communication devices

canm become non-operational or be damaged if the

~
'

total cable length exceeds 300 metres (1000 feet) for
DEC423 devices. The cable should not be run outside
the building, and the low-voltage data wiring must be
~ separated from ac power wiring. The installation or =
~ sites may require additional devices to correct
_problemsin commumcatlon

N OTE

Under tdeal condrtions, DEC423 devrces can dnve

cables considerably longer than the 1000-foot
maximum stated above. However, differences in
ground potential, pick-up from mains ac power
cabhng, and risk of induced interference limit the
maximum distance for reliable communications in

most practical srtuanons

15 FUNCTIONAL DESCRIPTION
1.5.1 General

" The DHQI ! functional blocks are showniin qure 1-3. Vlost ol the lunctlons are prowded b\ two chlps
~the control chip and the OCT-\RT chip.

Q- bus bufl'enng uses six DCO021 bidirectional buffers. Serial-line intertace bufl'ermg uses h\e octal lme
recexvers (5l80) and three octal line transmltters (3170) used for data and modem signals.
A 7k X 8 static RAM chip (’OlSD-45) provrdes the memory requlrements Swrtchpacks pronde vector
address and module address.

Rt 52 Main Functions

The main t'uncttons of the DHQ‘ll are:

‘Transmrsston — Smgle characters can be transmrtted usmg programmed transfers.
Characters can also be transferred by DMA

| Receptron — Recexved characters are desenahzed by the OCTART and transferred to a
four-character area in the RAM (one such area per line) by the control chip's OCTART
sequencer, following an interrupt from the OCTART. The control chip’s OCTART sequencer
later removes characters from the bottom of the 4-character F IFO. and places themin the 256

- x 16 recetve FIFO whxch can be read by the host

- Modem ControlThe modem control latches are external to the control chip. Data 1S
written to the latches from RAM by the UART interface sequencer. The sequencer also

samples modem status lines every 10 milliseconds and reports on changes via the STAT
register (and also via the receive FIFO if programmed to do so).

1.5.3 Coantrol Clnp
L
The control clnp contatns the followmg functronal blocks

| Q bus Interface — \'latches addresses generates vector addresses and handles mterrupts It
also mterfaces the Q- bus sxgnals to other l'uncttonal blocks

| Data I/O Sequencer— Controls host access to devrce remsters

OCTART Sequencers — Transfers data between the OCTART and RAM. and handles How
control

»Self-Test Power-Lp Sequencer — Thts section powers up the module to a hxed set of initial
~conditions. such as 9600 baud rate on all ltnes it also handles self-test
|

———— ——————

o DMA Sequencer — Imtlates and manages all DMA data transfers to the module
o

RAM Arbitrator— Provxdes RAM and OCTART bus access to the vanous sequencers

154 OCTART Chip_

el data
This chip contains eight UARTs which perform parallel-to-serial and serial-to-parall
and four are

conversions. ft interfaces with the control chip through euzht registers. F our are read-only
write-only. An index register is used to access individual lmes The OCTART chip shares the RAM bus
with the control chip. and the RAM itself. The OCTART chxp also mcludes

i ~Q | Recexve and transmit control blocks

[nterrupt logic tor mtertdcmg mth the Lontrol Chlp

A [6-output baud-rate generator- |

vQI

All necessary line-parumeter"regis-ters

Diegn‘osti‘c loopback l_ogic' o

Modem status multiplexers.

1-13

TTYNOILDIHIOIY]OHINODw|dIHD viva
NvY -

2noSTvNois-1
/010

10HINOD

WVH

N3I‘ND3

sSN8-0

-14

L DORAR

8 STINNVH)

W|/01Y0 -/ |o vivaIn Sw
—TMSTYNOISNI
8N
WO3INAOVW

CHAPT ER 2

INSTALLATION
21

SCOPE

This chapter describes the preparatxon and lnstallanon of the DHQI l optlon [t contams the tollowmo o |
sections.

Unpacking

APreparation'

0 Installa_tion
[

Testxnz

2.2 UNPACKING AND INSPECTION

If ordered as part of a system, the DHQll wrll already be rnstalkd and you should refer to the -

- mstructlons for unpacking the system.

©If ordered as an add-on optron to an exrstxng system a DHQH M (Q bus module) will be supplied
together with a cabinet kit, distribution panels, and interconnecting cables. The choice of cabinet kit
~ depends on the type of system and on whether EIA-232- Dor DEC423 connection standards apply
(Table 2-1 gives detaxls of these optlons) -

NOTE
DEC423 is a term used in this manual to mdncate a

data-leads-only unplementation of the RS-423-A
electrical mterfaee standard
.

'If the equxpment1is to be mstalled by DIGITAL Fteld Servrce the customer should not open the
packages

If the DHQll was ordered as an add-on optxon find the carton marked OPEN FIRST and carefully
Bunpack 1t Thereis a shrppmg list 1ns1de the carton.

- Undo each package and examxne the contents for physrcal damage Check that the contents of each |

- package are complete. Report any damaged or missing items to the shipping agent and to the DIGITAL
representative. Do not dlspose of the packmg material untrl the unit has been xnstalled and 1S
0perattonal
|
.
EOVR

Table 2-1
DHQ11-M

DHQu Options

M3107 module + DHQll User Guide (EKDHQll LG)

| (Base Opnon)

CK-DHQI!-AA
CK-DHQI1-AB

CK-DHQ!1-AF

EIA-737D Cabmet Kits

BA123 boxes
BA23 boxes

H9624 cabinets -

Contents
H3173A
BCOSL-IK

|
|
~

BCO5L-01
BCOSL-03

4-line 23-way distribution panel
40-way ribbon cable. 21 inch
40-way ribbon cable. 2 inch
- 40-way ribbon cable. 36 inch

2
|

2
I

2
2

2
S

”

DEC423 Cabinet Kits

- CK-DHQI11-WA
CK-DHQI!1-WB
CK-DHQI!1-WF

BA123 boxes BA23 boxes ——
- H9624 cabinets

Contents

H3100
- BCOSL-1K
- BCOSL-01
- BCOSL-03
- 70-22775-01

70-22775-03

Active bulkhead panel
Ribbon cable
— 2"
o
Ribbon cable
— 12"
~ Ribbon cable —36~
=
~
Bulkhead power cable
- Bulkhead power cable
@
.
Bulkhead power cable

"H3101

Cable concentrator
Multiway cable

Multxway cable loopback |

1
]
.
|
|
2
2
|
S
o

|
-

1
2
o
o
-

1
l

l
l

s
l
]

23 PREPARING THE DHQll MODULE
)
|
Please check that your system has sufficient power and bus load capacity betore
mstallme addmonal
-modules; see your system manual. Before installing the DHQI11. vou must define two
parameters bv

| -selectmg them on the DHQll on-board swntchpacks The paramete

rs are:

o Module address

o
|

70-22775-1K

H3104
BCl16C-25

e ‘Intefrupt vector |
|

o
'NOTE

Easure that you are Wéaring an ahtis_tatié Wfiststrap, |

part number 29-11762-00

2.3.1 Address And Vector Assngnment SRR

The DHQI1 has a floating device address and vector. [tis shxpped trom the factorv with a device dddress
of 17760440, and a vector of 300,. These assignments are determined by the floatmq address and vector
rules. The factory settings are only correct if no other floating address option is mstalledin the system.

Otherw1se the proper rules for addres: asawnment must be apphed these are given in Appendm c..

2. 3 2 Settmg The Address Switches

The device address for the DHQI1 is set on the lO-position switchpack E19: the location of thxs.

//'

sthchpack is shown in Figure2-1. SW-1 is not used and must be set OFF (open)

] [enr]

10 POSITION

8 POSITION

(ADDRESS)

(VECTOR)

SWITCHPACK

L
Figure 2-1. Location of Switchpacks
- ‘Figure 2-2 shows how to set the device address on the switchpack. The example shown is for the
factory-set address of 17760440..

DHV/DHU MODE SELECTION.

LEGEND
|

D = SWITCH OFF (BINARY 0)

;

)

).L‘

—_—

—

( 1= '-'*‘)

mum

1] EXAMPLE

SETTING

- =1776044

o
b
'
|

I
R

—

T
I

B
S

|
|

NOTE:

|
.

USE THE BLANK ROW TO

PENCIL-IN THE ADDRESS

}

FRu

)

|
.-

—~

pecooep

BYDEVICE
_

|21]20|19f18|17] 16|15 -I,” 13|12 11| 10| 09| 08| 07| 06| 05| 0a|03|02]|01|00
. \,‘_JL‘

ADDRESS

o0
o

~DEVICE

AS ALL ONES

BTNO.

PART OF SWITCHPACK £36

l = SWITCH ON (BINARY 1)

SEE NOTE

EACH GROUP IDENTICAL

.‘

0o|=6
1 | =7

—l

\\-'// o

:
.

‘o|lofo]=0
olo]|
ol

|{=1

|=3

11l ol=2

PATTERN YOU NEED

110]

110
1]|=5
1
1{0|=86
1] 1]=7
1|

L‘

0!l=4

Fxgure 22 Settmg the Dev1ce Address
'2 33 Settmg 'l'he Vector Switches
The six high-order bits of the 1nterrupt are set on the eight-position sw1tchpack Ell Flgure 2-1 shows

the location of this switchpack. Figure 2-3 shows an example of these switches set to the factory setting

of 300,. Switches 1 and 2 are used dunng manufacture, SW-1 must be set ON (closed) and SW-2 must be

- set OFF (open) for correct operatlon of the DHQII

OVER PALE.

MANUFACTURING TEST SWITCHES
-

SW1 MUST BE ON
- CLOSED

SW2 MUST BE OFF
- OPEN
- PART OF SWITCHPACK E11

)

LEGEND

VECTOR ADDRESS SELECTION
PART OF SWITCHPACK E1

SWITCH OFF
BINARY
0) OPEN

;

-SE B

- SWITCH ON

EEEENIE
'

(BINARY 1) CLOSED

F'»~ - f— EXAMIPLE

INTERPRETZD

AS ALL ZEROES

322008
D

—

SEE NOTE'

BITNO.
~

VECTOR

~ADDRESS:
1VNOTE |

1514131121110
.
0

'073_, 06 (05|04
N

’/’

|03]02|01|00]|
»

BOTH GROUPS IDENTICAL -

USE THE BLANK ROW TO

PENCIL-IN THE ADDRESS

’PATTEF!NYOUNEED

|09

1941010

[=0

Q101
o
|1
0
0
1
1

=1
= 2
1 =3

|=8

1= 7

=4
|

Figure 2-3 ‘Setting the Ve_c‘t'or Address
24 BUS CONTINUITY

Bus grant continuity jumper cards (M904‘7) are usedin vacant backplane slots to provnde bus contmuntv
(see Fxgure 2-4).
|
|
|
|
_

'NOTE
To find out the type of backplane on vour swstem.
consult your system manual

Q/Q BACKPLANE
A

'Q/CD BACKPLANE

PROCESSOR

TERMINATOR

6
7

Flgure 2-4
2.4. l Bus Grant Contmmty Jumpers

Bus Grant Contmmty Ly

RE3202

Backplanes sultablefor DHQll fall into two groups
»Q/CD_

Q-bus on A and B connectors user-defined srgnals on

C and D

Q bus on A and B and C and D connectors.

v' In Q/CD backplanes bus grant 51gnals pass through each mstalled module via the A and C connectors
of each bus slot

- Q/Q backplanes are desxgned SO that two dualhexght optlons can be mstalledin a quadhexght bus slot s
- The Q-bus lines are routed as follows
o
|
)

AB, first slot

CD,firstslot

CD, second slot

AB, second slot

and so on.

Each dual-height module extends the continuity of the bus grant signals BIAK and BDMG to the next

module. Therefore, with a Q/Q backplane, if a quad module (DHV11) is replaced with
a dual module
(DHQ11), a Q-bus grant continuity card M9047 is needed for the vacant slot. o
|
|

25 PRIORITY SELECTION

The bus (backplane) position may be a compromise between DMA and interrupt priority requirements.

As a general rule, consider

DMA request priorities first, and then consider interrupt (bus) requests.

'2.5.1 DMA Request Priority
-

Loy

e B

DMA request priority is usually assigned according to throughput. Faster devices (higher
throughput)
usually have priority over slower DMA devices; for example, disk has priority over tape, which
itself has
priority over communications devices. This is because fast devices usually reach overrun or underrun
conditions sooner than slower ones.

- 2.5.2

Inteirupt RequestPriority

The DHQI1 has a fixed interrupt priority level of 4, and cannot be changed to other priority
levels. It
does not monitor any of the higher-level interrupt request lines. Because
of this, both the
interrupt-request and DMA (non-processor request) priorities of the DHQI1 are selected
by the
position of the DHQI1 on the bus; it must therefore
be positioned after any device that does monitor
any of the request lines. Devices closest to the processor module have the highest priority.

2.5.3 Recommendations

- In general the DHQI1 bus position is not critical. However, it is recommended that
you
module after any mass-storage interfaces and high-speed synchronous communica

. are more sensitive to bus position.

26 INSTALLING THEDHQU

Once you have defined the backplane positio
for
n the DHQIl1, you can begin

‘module.

in this chapter.

ATTENTION

Avant d’effectuer I'une des procédures de ce chapitre, |

mettez le systéme hors temsion et débranchez le
cordon d’alimentation.
.
SR

VORSICHT!

~ Schalten Sie das System ab, und ziehen Sie das
Netzkabel,

bevor

Sie

die

diesem

beschriebenen Anweisungen ausfiihren.

to install the DHQI11

system power cord before perfonmng any procedure

~
~

place the

tions options; these

Kapitel

~ ATENCION

Apague el snstema y desconecte el cable principal de

alimentacion antes de reahzar mngnnprocednmlento

de este capltulo

s Connect the BCOSL cables to J 1 and J2. thure 2-5 for EIA-232- D mstallatlons and thure - 2-6 for DEC423 tnstallatxons show how the parts of the option connect together
'Install the module in its correct backplane posxtton asprevmusly defined

Be careful not to snag module components on the card gmdes or ad]acent modules

Check that bus contlnutty extsts If necessary, 1nstall bus grant contmutty cards
Do not connect the cables to the bulkhead panels

H3100

ACTIVE

DISTRIBUTION

'POWER CONNECTOR

PANEL

H3101

BCOS5L-XX
CABLES

H3101

\l’\c

H3104

CABLE

CONC=".TRATOR

] TERMINAL |
| ETC.

"E':.‘f'

Figure 2-5 Installing the DHQI! (EIA-232-D)

ACEo0o0O0O

BDfFooCc
OO

H3100

70-22778-XX

5‘ PIN A

<—_BACKPLANE

(Q22/LSI BUS)

RED LINE

ToA

)

“'
’

I,' AL
s

‘

3100 ACTIVE

BULKHEAD PANEI

BERG
40-PIN
~ CONNECTORS

COLOURED STRIP
BCO5L XX
CABLE

POWER CABLE
70-22775.XX

NQTE

8COSL-01 =3Ccm (12 INCHES)
"BCOSL-1K =53cm (21 INCHES)
. BCOSL-03 :92cm (36 INCHES:

Figure 2-6

Installmg the DHQll (DEC-P )

.
o
2.6.2 Dlsmbutmn Panels
The rear /O distribution panel has six cutouts: two type-A cutouts and four type-B cutouts. In addmon |
a removable bracket between the third and fourth cutout allows you to install three more type-A insert
panels by mountmg an adapter plate thure2-7 shows typtcal type-A and type-Binsert panels and the
~ adapter plate

2.6.3

Installmg The EIA-232 D Distribution Panels

The DHQ! 1 has two type-B distribution panels. Figure2-7 shows how these are lnstalledin a BA73 box
lnstallatton in BAl73 and I-l9647 cabinets is similar.

\e._,/l

To fit the dxstrtbutxon panels

Remove the two type-B blanking panels.

*Bolt the tn?o I-l3l73-A distribution panels into the Cutot1ts

Cod

Connect the tree end of the BCOSL XX cable from connector Jl of the module to the Arst

o ‘4.

dtstrtbutton panel

Connect the free end of the BCOSL-XX cable from connector J" ol'the rnodule to the second B

dtstnbutton panel

REMOVABLE INSERT

50-PIN CONNECTOR

EXPANSION SL,OTS_'-TYPE A

|
1£3204

Flgure2--7 IO Insert Panels and Adapter Plate(EIA-737 D)
2.6. 4

lnstallmg The DEC423 Dlstrtbutlon Panels

- The DHQI1 has one type-B distribution panel. Figure2-8 shows how this ilS mstalledin a BA’3 box.
Installatxon m BA173 and H9642 cabtnets 1S snmllar

To ht the dlStl‘lbUthfl panels:
|

Remove atype-.B bla_nking panel.

Bolt the H3100 active distribution panel into the cutout.
Connect the free end of the BCO5L-XX cable from connector J l of the module to the upper. |
J 2) connector on the dtstnbutxon panel.

Connect the free end of the BCOSL-XX cable from connector J" of the module to the lower

J l) connector on the dxstnbutton panel

Connect the free end of the power cable (70-22775 XX) to the left-hand power connector Js)
on the distribution panel

e (1)

REMOVABLE INSERT

EXPANSION SLOTS

83208

| Flgure 2- 8 I/O Inse'rt Panel'(DEC423)
2.7

INSTALLATION TESTING

‘This section details the diagnostics used to test theoptxon dunng and after 1nstallatton The dxagnostxcs
are also used to test other Q-bus modulesin the same famxly, for example, DHV11. The diagnostics will
automatxcallysize’ the option to determine which one is being tested

‘Both MicroPDP-11 and MicroVAX II diagnostics are described. After successful completxon of the

appropriate system test, the DHQ1 | may be connected to external equtpment F urther information on
- the diagnostics is given in Chapter 4.
2. 7 1 Installation Tests On MicroPDP-11 Systems
To verify that the MtcroPDP 11 system and the DHQll module are tuncnonxnz correctl»
.

watch on the s»stem

come on. call DIGITAL Field Semce

| RV )

After2 seconds check that the 2reen self-test LED on the DHQl 1 moduleis on. [fit does not

| Boot the Micro-11 Customer Dlagnosttc medla Refer to your MicroPDP-11 S vstem Manual "
|

~ for further 1nformatxon |

Type ‘I’ at the main menu to allow the dxagnostxcs to 1dent1fy the new module and add it to

the configurauon file

- NOTE
Look at the list of devices displayed, and make sure
that the new moduleis included. If it is not included,
repeat the installation sequence, and make sure that
the module switches have been set correctly

- Type ‘T’ at the main menu to run the system tests. These should complete w1thout error; if an
|

“error occurs, call DIGITAL Freld Service.

office.
A MlcroPDP-ll Mamtenance Kit is available, and may be ordered from your local DIGITAL
diagnostic

~ This kit allows trained personnel to run individual diagnostic programs under the XXDP +

monitor, and to configure and run DECX11 system test programs. The XXDP + functional dtagnostlc_

is VHQA**.BIN, and the DECX11 moduleis XDHV**.OBJ.

2.7.2 Testing In MicroVAX II Systems

To verify that the MicroVAX II system and the DHQll module are functromng correctly
| Check that the green self-test LED on the DHQllmoduleis on.
2.

'Boot the MicroVAX Mamtenance System mcdxa Refer to yourMicroVAX II System Manual
for further xnformatxon

Type 2’ at the main menu to show. 'the' system configuration and devices.
NOTE |
Look at the list of devrces dtsplayed and make sure
that the new moduleis included. If it is not included,
- repeat the installation sequence, and make sure that
the module smtches have been set correctly
~

Type ‘1’ at thc main menu to run the system tests. These should complete wrthout error; ifan

error occurs, call DIGITAL Field Serv1ce

28 DIAGNOSTIC TEST CONNECTORS 2.8.1 Staggered Loopback Test Connector H3277

The H3277 test connector (see Figure 2-9) is used dunng servxce-mode dlagnostlc tests on either

EIA-232-D or DEC423 installations. It allows allchannels to be tested Using this connector, you can
trace a channel fault to one of two channels.

‘

—4
)
N

(L)

DSR2

—

40-PIN BERG CONNECTOR
N
B

o { © 40-PIN BERG CUNNLCIOR

;

PHYSICAL ARRANGEMENT

Figure 2-9

H3277 Staggered \Loopback Test Connector

2.8 2 Line Loopback Test Connector H3197
|
|
.
This connector is shown in Figure 2-10. It can be used durmg serv1ce-mode dragnostrc tests to trace a
fault to a single channel for EIA-232-D
installations. The older-style H325 test connector provrdes the

same srgnal loopbacks as the H3179 and may be used’in place of it.

ccITT No. " NAME

’P|N

NOTUSED

NOTuUSEp

——

———

NOT USED

104 -

105

.:Z

RXD

RTS.

DCD

107

DSR

125

3
C),

o3|
o

Q05

———

DOTR

o
.

109

1082

S
-

—=

f
|

106
CTS
R

———

PIN1

pNZ5

—

25-WAYD-TYPE

CONNECTOR (MALE)

CONNECTIONS
RD2758

Flgure 2-10
2.8.3

H3l97 Lme Loopback Test Connector

H3101 Loopback Connector

‘The H3101 loopback connector (see ‘Frgure 2- 11) 1S used durrng dragnostrc tests for DEC423 .
installations. Itis two loopback connectors in one package, and consists of a female 36-way loopback
connector and a male 36-way loopback connector. It can be inserted into the cabling at the distribution
panel, or at the cable concentrator. To test the cables, type characters at the keyboard and make sure
that they are echoed to the screen (refer to Chapter 4)

2-15

Tx = 3——-;

3r—-bTx*

Tx =

LINE 2

Tx +

Tx+

INE
O

LINE 1

L!NEIZ _

T+ .

g in-z’ :Hx+'
LINE4
) Rx+o—JlOl——on+

LINE 3

}

'uNé 5

Tx +

Tx«r-A

CTx+

Tx +

LINE 7

—

LINEO
CLINET

LINE 2
LINE 3

LINE 4

_LINE.' 5
LINE6
LINE 7

15—

; ng'q-:ts

NOT USED
'NOT USED

0—
o—

Tx=
Tx -

;

LINE 6

Rx +

NOT
NOT

”n"-

Ax -

Tx=-

Tx=)

Tx
=

O=——m

25 Tx-

%
)

)
¢\

Tx -

27 Tx-

LINE _1"

Rx - ] LINE 2

; Rx-:z Rx = i
;‘ Rx—z:j Rx = |
Tx -

LINE 7

LlNE 0

Rx = I

Rx-:2

LINE'S

Rx +

——o
L—0

g nx-:]2

&
LINE

Tx
+

17
18

; Rx-':-_—jz

LNE3

_Tx'+»

z }Ri*:fd- :

LINE 6

" MALE CONNECTOR

o
Tx+

+
Tx

LINE 3

LINE 4.

Tx -

- ::Rx- 3 LINE5
- O 31
TxO——J32
Rx - |

LNE B

Tx-

O--—-q33r———OTt-

Rx- O——-‘34L-—-3Hx-

'NOTLSED 35 r——o NOT USED
NOT USED 4-——-1 36 ——o NOT USED

Figure 2-11

H3101 Loopback Cor_inector
216

FEMALE CONNECTOR

; — 4 —o Rx
; Rx#g:qu-

——

LINE1

Ax = o 2 3
Rx +

———— ——

<, ~———

LINEQ

2.8.4

H3103 Loopback Connector

The H3103 loopback connector (see Figure 2- 12) is used dunng service-mode dlagnostxc testmz with

DEC423 installations to test each line from the DHQI!L at the output from the H3104 cable

concentrator

omoruseo

Cglin- IR
O 5Rx+

—

—‘OGNOTUSED

A€2440

Fxgure 2-12 H3103 Line Loopback Test Connector
29

CABLES AND CONNECT ORS - EIA 232-D

2. 9.1 Dlstnbutlon Panel

- Each H3173-A distribution panel adapts one of the DHQll Berg connectors to four submmxature
- D-type EIA-232-D connectors. Noise filtering is provided on each pin of the EIA-232-D connectors.

‘This reduces electromagnetlc radlatxon from the cables and also prov1des the logic thh some protecuon
; agamst static dxscharge

| anure 2-13 shows the circuit of the H3l73 A. There is no CCITT equxvalent of EIA CIrcuilt -\A
| ,(Protecuve Ground) You can remove the 0ohm lmk Wl to dxsconnect thxs CII‘CUI[ if necessary.

T—- ?7: e ?‘I qv.n ?m foflfl,?m ?DE

(

SIGNAL GROUND
TRANSMIT DATA 0/4

DATA CARRIER DETECT 2/6

_RECEIVE DATA 0/4

DATA SET READY 2/6

DATA TERMINAL READY 0/4 |

RING INDICATOR 0/4

' REQUEST TO SEND 2.°6

CLEAR TO SEND 0/4

CLEAR TO SEND 2/6

REQUEST TO SEND 0.4

RING INDICATOR 2,6
_DATA TERMINAL READY 2.6

' DATA SET READY 0,4

" RECEIVE DATA 2.6

DATA_CAR,RI&R.DETECT 0/4

TRANSMIT DATA 2,6

)

SIGNAL GROUND

( PSIEQITE 93 g 9Z 02 gF 9R

TRANSMIT DATA 1/5
RECEIVE DATA 1/5

DATA CARRIER DETECT 3/7

_DATA SET READY 3/7

DATA TERMINAL READY 1/5|
RING INDICATOR 1.5

REQUEST TO SEND 3/7

CLEAR TO SEND 1/5

CLEAR TO SEND 3/7

REQUEST TO SEND 1/5

_RING INDICATO
3/7
R
DATA TERMINAL READY 3/7

DATA SET READY 1/5 |

RECEIVE DATA 3/7

TRANSMIT DATA3/7

DATA CARRIER DETECT 1/5|

| SIGNAL GROUND _

owt

= PROTECTIVE GROUND

Figure 2-13 H3l73-ACircuit Diagram
2-18

————

. e

et
s

“Table 2-2 is for two dtstnbutton panels The numbers w1th1n parentheses apply to channels ‘07
Table 2-2

‘Stgnal

TXDO(4)
- DTRO(4)
RIO4)

RTSO(4)

~ DSRO(4)

Data Terminal Readvy
Ringing Indicator

Request to Send

Data Carrier Detected

SIG GND [(9)

CTSI1(5)

R
o

RTS2(6)
- CTS2(6)
RI2(6)

1035

Cl-H (2-H)

106

103

I-F (2-F)

1K (2-K)
l-L (2-0)

P (2-P)
[-R (2-R)
1-8 (2-§)

106

1T (2-T)

109

1-X (2-X)

109

1Y (2-Y)

107

1-Z (2-2)

SRR

105
AR
106
125

RIS

1-M (2-M)

1N (2-N)

;

1-D (2-D)
1-E (2-E)

104
L
1082
|
125

DTR2(6),

1082
125

109

)

[-B(2-B)

1-C (2-C)

l-BB (2-BB)
1-CC (2-CO)
1-DD (2-DD)

108/2

I-EE (2-EE)

102

1-JJ (2-1]))

R
S

o
o
o
I

DCD2(6)

104

J5 Pin No.

"DCD1(5)

DSR2(6)

_Ctrcmt Vo -

103

Data Set Ready

IXbDus»

. RXDI(3)
DTRI(S)
RIS

~Clear to Send

Received Data

DCDO(4)

Transmitt'ed' Data

RXDO0(4)

CTSO0(4)

Vame_ S

H3173—A Connecnons

SIG GND 2(6)
DCD3(7)
DSR3(7)
RTS3(7)

CTS3(7)
RI3(7)

o
|

DTR3(7)
RXD3(7)
TXD3(7)
SIG GND 3(7)

o
R
B
|

)
|
o
o

A
|

109

-KK (2-KK)

107
105

l-LL (2-LL)
[-NN (2-NN)

106
|
125

1-PP(2-PP)
1-RR (2-RR)

R
|

S
1082
o
104
|
B
P
R
103
e
R
102
|

1-SS (2-S§)
[-TT (2-TT)
[-UU (2-UL)
1-VV (2-VV)

* The following examples show how to use Table 2-2.
|

512!'131 TXDO 1S the transmttted data lme for chdnnel 0 the CCITT Cll‘CUl[ number 1s 10? and it s

connected to JS pin B on the first H3l73 A tor channels O to 3.

)
Signal TXD4 is the transmxtted data line for channel 4, the CCITT circuit number is 103 and it is
connected to JS pin B on the second H3l73 A for channels 4to07.
2.9.2 Null Modem Cables
»
Null modem cables are used for local EIA-232 D connectxon when a modem is not used. Because of

Federal Communications Commission (FCO) regulations, the cable specifications for the United States

and Canada are different from those for non-FCC countries. Other countries may also have
similar
electromagnetic interference (EMI) control regulations. EMC, RFI shxelded cabmets are now avaxlable
|

- for systems whxch conform to FCC requxrcments
Recommended null modem cables are as tollows
l

BC?.ZD (for EWC RFI shtelded cabmets)

Rounded 6-conductor tull» shlelded cable to FCC spemficatxon

Submxmature 25-pln D-txpe female connector moulded on each end

Lengths avanlable.

S BC22D-10
BC22D-25
BC22D-35
BC22D-50

BC22D-75

BC22D-A0
BC22D-BS

31m

(10fy

7.6 m
107m
I1S2m

(25 fv)
(35 ft)
(50 ft)

29m

(75 ft)

30.5m
76.2 m

(100 ft)
(250 ft)

2. _Bcosm o
o
®

Round i6-conductor (three twisted pairs), each pair shielded

Cables over 30.5 m (100 ft) have a 25-pin submmlature D-type fcmale connector at one
| cnd The other end is unterminated, for passing through the condunt
|

Cables 30 Sm (100 ft) and less have a similar connector at each end

’Lengths available:

BCO3IM-25

76m

(25f)

BCO3M-LO

3048 m

(1000 fr)

- BCO3M-A0
BCO3M-BS
BCO3M-E0
|

BC22A

30.5 m
76.2m
1524 m

(100 fr)
(250 ft)
(500 ft)

. 'Round‘6-chducror cable
| o Subminiature 25-pin D-type female connector moulded at each end ’ h

o - Lengths aVailable:
3lm
BC22A-10

T6m

BC2A2S

(10 ft)

(2SM)

Cables of groups 1, and Jareall connected as in Fi1gure2 14 The cables are | not polanzed| Thev can
be connected etther way round.

e C_QATA SET READY

TRANSMITTED DATA_{) )

RECE!VED DATA

76 SIGNAL GROUND

SO NUMBERS

PROTECTIVE GROUND
RECEIVED DATA_O5
_

1 QROTECTNE' GROUND
c_lRANSMITTED DATA ' -

ZOCfi

NUMBERS

SIGNAL GRouND—o 7

20
:_ DATA TERMlNAL READY

|
SET 2EADY
DATA TERM!NAL READY. ERRE_DATA
_——06
.
~

ap11%0

)

Figure 2-14 Null Modem Cable Connections
293 Full Modem Cables

Recommended full modem cables are as follows

. 1. BC22F (for EMC/RFI-shxelded cabtnets)

Rounded 25-conductor fully shxelded cable |

0 Subtmmature 25ptn D-type female connector on one end male connector on the other

o Lengths avaxlable |
BC2F-10

BC2F-25

BC22F35

~ BC22F-50
BCZFIS

z BCOSD

’3.1 m

(10f)

107m

(35f)

76m

152m
29m

(25f)

(0f)
(50

Round ’5-conductor cable

Submtmature 25-pin D-type. _t'e_m'ale connector on one end. male connecto,r-_on the other

Lengths available: |

@
~

BCO5D-10
BC05D-25
BC05D-50
BCOSD-60
BCOSD-A0

3.1 m
76m
15.2 m
186m
30.5m

(10 fr)
(25 ft)
(50 ft)
(60 ft)
(100 fr)
NOTE

’In some countries, prote_ctive hardware may be

" needed when connecting to certain lines. Refer to the
nanonal regulanons before makmg a connection.

210 CA.BLES AND CONNECTORS — DEC423 _ L

'The H3100 active distribution panel adapts the two DHQI Bero wnnectors to one 36-way AMP
connector. Noise filtering is provided on each pin of the connector. This reduces electromagnetic |

radlatxon from the cables and also provides the logic with some protectxon aoamat static discharge.

Table 2-3 shows connectlons to the 36-pm A\/IP filtered connectors u:ed on DHQll \ch DEC4’3' -

" installations.

- Table 2-3 .-Se'rial-Line_ Connections for the .’»h-Pin_Connectnr a

Blu/Wht

Line0

Org/Wht

Line 0

Gm/Wht

Line I

SiyWht

Line2

Bm/Wht

Line 1

Blu/Red

Line 2

7 Org/Rcd
8

Gm/Red |

‘Line 3 L
Line 3

Transmit +

Wht, Org

WhtBlu

Line0

Transmit -

Transmit + 21

Wht/Gmn

Linel

:iTtans'rnit -

Tramsmit + 23

WhySlk

Line2 Tramsmit -

Receive +

TranSmit +

BluBlk

LineS$

Transmit + 29

Line 6

Transmit: + 31

Org/Blk

Line 5

13 ~ Gm/Blk
14

Bm/Blk

Line 6

SlyBlk

Line 7

17
18

Blu, Yel

Org/Yel

- Grn/Yel

~Line 7

Spare
Spare

Receive +

Receive

Receive +

Transmit +

Receive

Line 3

Transmit -

"Red/Bl‘n'. ‘ Line 4
Red/Slt

Line 4

" Transmit -

BlkBlu

Line5

Transmit-

Blkj}Grn

Line 6

Blk,Org

Blk Brn

Line
3

Line 3

Line6

YelBlu

Blk
St

. Line 7

YE’l.Ofg'

Spare

Receive -

_Receive -

27 |

Line 4

Receive-

Line2

26 - Red/Gm ~

Brn/Red Lined

Line 1

Red/Blu =~

Receive +

Sit/Red

Wht/Brn

Transm_it + i 35 ~Red/Org

Line 0

YelGmn

Line7

‘Spfare o

Receive -

Transmit
—

Receive -

Transmit - )
Receive -

CHAPTER
3

~ PROGRAMMING
|

3. l SCOPE

This chapterdescribes the devu.e reatsters and how they are used to control and monitor the DHQl L.
S

The chapter COvers:

e The btt functions and format of each register
Programming features available to the host.

Some p_rocramming examples are also included.

32 REGISTERS

The host system controls and monitors the DHQl l module through several Q- bus addressable revrsters

Command words or bytes wrttten to the regtsters are mterpreted and esecuted by the module Status o

| - reports and data are also transferred through the registers.
-

3.2.1

The DHQll reglsters occupy 8 words (16 bytes) of Q bus mernory-mapped I/O space

| The base physrcal address of the etght DHQI l regxsters is selected by ustng swrtcheson the rnodule The

~address selected is in the peripheral I/O space. The term “base’ rneansthe lowest I/O address on the

Table 3-1 lists the DHQI1 regxsters and theu' addresses The sufiix (I) means that there are etght of these
registers, one for each channel. When an (I) register is accessed, the contents of CSR< 3.0> selects
‘which of the etght reg13ters at that addressis actually accessed
|

NOTE-

CSR<3:0> allows up to 16 channels to be

addressed. However, only the lower eight channeils are

| ‘used. Therefore CSR btt 3 must always be 0

Table 3-1 DHQll Registers
Register

Address
o

Control and Status

‘Register
Receive Buffer

Transmit Character

|
T

Type

A(Octal

kN (CSR) Base

AT
(RBUF) Base+2

(TXCHAR)

Base+2(I)

\,v

//'

module; thatis to say, when the four low-order address bits = 0.

Reud Write

S
-

U R
_Read Only
Write Only

Table 3-1
Register

‘Line-Parameter
Register

Address
(Octal)

(LPR)

|
-

Transmit Buffer

Address
2
|
Transmxt Bufl'er Count

(STAT)
(LNCTRL)
(TBUFFADI)

|
.

Base+4 ()

Line Status
Line Control
‘Transmit Buffer
Address |

DHQI1 Registers (Cont.)
Type
o

Read/Write |
-

Base+6 (I)
Base+10(I)
Base+12(I)
|

Read Only
Read. Write
- Read Write

(TBUFFAD?2)

Base+ [4I)

|
(TBUFFCT)

o
Base+l16([)

Read Write
Read Write

- NOTE

It is possible to write to the line-status register.
However. the host should not write to this reglster

| Thereare eight line-parameter registers, only one of which is accessed at any one txme The regxster

| whxchis accessed xs assocxated w1th the lme selected usingC §R< 3 O>

" For example to read the line-parameter reglster of channel the followmg IO commands would be
executed

MOVB SCHAN,QeBASE »;unttz°cununzt Nunnrngcsrz aztou; T0 CSR
MOVB @8BASE+4,R0

;READ THE LINE PARAMETER REGISTER

Where:
¢
ro

0011

= the RXIE bit of the CSR
=

- =

the MASTER.RESET bit (whtch would be O)

channel number 3

NOTE_ «

1. ~Not all register bits are used. In a write actxon.
all unused bits must be written as 0s. In a read
‘acnon, unused blts are undefined
|
|

Read-modlfv-wnte instructions may be used on
all regxsters except CSR and RBLF

3.2.2 Reglster Blt Definitions
|
c
Reglsters which are modified by reset sequences are coded as shownIn Flgure 3- L.

~ CLEARED BY MASTER RESET
SET BY MASTER RESET

BY BINIT.
CLEARED

~ BUT NOT BY MASTER RESET
am

qure 3- l
Control —\nd Status Regtster (CSR) -

CSR(BASE)

14 13 12

| R R/WI R{R|R|

R|R|

R [RW R/W

S l

TX
| DIAGNOSTICS |
ACTION | FAILURE

TRANSMIT
LINE NUMBER

RCVE DATA

T-ENABLE pmaerrOR

Bit.,

gl&BLE
| @xig |

D
& TRANSMIT
s

AVAILABLE

'Name'

JR,W R-W [R-W | R/W

RCVIE -

INDIRECT ADDRESS REG POINTER
[CHANNELNO)

MASTER
RESET

- Description

TX. ACTION

This bit is'.set by itvh,e;-DHQl L when: o

(Transmtter Actxon)(R)

The last character of a DMA bufl'er has left the -

| OCTART

A DMA transfer has been aborted

A DMA transfer has been termmdted by the
DHQI11 because non-existent memory has been

| addressed or because ot a hostmemory parity
error.

| 4.‘ A smszle-character proorammed output has been

dccepted that is to sav. the Chdl‘dCtél‘ has been ‘

. 'taken from TX CHAR

]

I N

'\ d

322”1

219

Name |

Bit

Description |
The bit is cleared if the host reads the CSR after the
TX.ACTION FIFO has become empty. To avoid
losing TX.ACTION reports. the host must not let

more than 16 reports accumulate. It is advisable to
read the CSR until TX.ACTION becomes clear.

NOTE
TX. ACTIOV reports may be lost if the upper byte of

the CSR is discarded followmg a read of the CSR.

f TXIE

When set. this bit allows the DHQl | to mterrupt the

Transmrt Ihterrupt Enable)

‘host when CSR< 15> (TX AtCTIO\J) becomes set, B

- (RiW)

Lt ois cleared

BINIT.

but not

MASTER.RESET.

. DIAGFAIL
~

(Diagnostic Fail) (R)

When set, this hit indicates that the DHQI internal
diagnostics huve detected an error. The error may
have been detected by the self-test sequencer or by

the background monitor program (BMP).

This bit is associated thh‘the dxagnostxc-pasSed

LED. When it is set, the LED will be ofl' When 1t is-

cleared, the LED will be on.

Thebit s set by MASTER RESET. Itis cleared after
the self-test has run successfully.

| Not valtd if MASTER RESETis set.
12

If this blt is set and TX ACT IONis also set, etther
the channel indicated by CSR < 11:8> has failed to
transfer DMA data within 10 microseconds of the

~-TXDMAERROR (Transmit DMA Error) (R)

bus request being acknowledged. OR thereis a host
memory parity error.

The TBUFFADI and TBUFFAD’ registers wxll“
contain the address of the memory location at which
the error occurred. TBUF FCT will be cleared.

<118

TX.LINE
|
(Transmxt Lme \Iumber) (R) |

If TX'ACTION is set. these bl[S hold the lme
number to which TX ACTION refers.

) Name

. Bit

RX.DATA.AVAIL

. When set, this bit indi_cates that af received character
is available. It is clear when the receive FIFO is

empty Itis used to request a receive mterrupt

.
.

Itis set after MASTER.RESET because the receive
FIFO contams dxagnostlc 1nforrnatxon |
|
~

RXIE |

| ‘When set, this bit allows the DHQll to mterrupt the

(Receiver Interrupt Enable)
| '(R/W)

host when RX.DATA.AVAIL is set. An interrupt is
generated under the following condmons

Desc.riptien S

(Received Data Available) (R)
|

——

1L - RXIE is set and a character is placed into an

B, empty receive FIFO

2. The receive FIFO contains one or more
characters, and RXIE is changed from 0to I.

C
-

o MASTER RESET

S '(Master Reset) (R/W)

- This b1tis set by the host to reset the module [t stays "
set while the DHQI! runs the self-test and performs

an initialization sequence. The bitis then cleared to
tell the host that the'proce'ss is compiete.

~
<Z3:0A.>}'__vf o IND ADDR REG

(Indirect Address Reglster)

| ’(R/W)

ltis cleared by BINIT but not by MASTER RESET

This bit can be set dxrectly by the host, or 1nd1rectly

- by BINIT (bus 1mt1ahzat10n signal).

For mdexed registers, these bltS select one of exght
channels

3.2.2.2 Receive Buffer (RBUF)- A read from‘base + 2'is mterpreted by the DHQl | hardwareas a

read from the receive FIFO. Therefore RBUFis a 256-characterregister w1th a l word address.
The
least-significant bit (LSB) of the character1s in bit 0.
|
|

RBUF (READ BASE + 2)

1§

DATA

LINE NUMBER

PARITY
ERROR
|

QR
_DATA

SET

(FROM

STATUS FLAGS
|

15
~

HIGH BYTE

OF STAT)

C?R

DIAGNOSTIC INFO

Bit

1 o

CHARACTER
|

'OVERRUN
ERROR

RECEIVED

RECEIVE

VALID | ERROR |
|

| FRAMING |

;

10
9

Name

Description

DATAVALID

This bit
is set if there is data in the receiVe,FIFO.

(Data Valid) (R)

When thxs blts clear, the contents of RBUF < 14:0>
1S not valxd

~ After self- test dragfiOstic'mforrnatxonis loaded into

the receive FIFO. Therefore. this bit is always set
after a successful master reset sequence

OVERRUN ERR
(Overrun Error) (R)

~
-~
-

This bitis set if one or more previous characters of
the channel indicated by bits <11:8> were lost
because of a full recewe F IFO
|

NoTE

The ‘all 1s’"code for bits <14:12> is reserved. This

code

indicates that RBUF <7:0> holds

status or dlagnosnc information.

13
|

,FRAME ERR

~(Framing Error) (R)

PARITY.ERR

(Parity Error) (’R‘)‘ o

modem

~ This bit is set if the first stop bit of the recewed o
character was not detected (also see RX.CHAR)

This bitis set 1fthls character has a parity error. and if
parity is enabled for the channel indicated by bits

- <11:8> (also see RX. CHAR)

Bit

Name

| <.1 l:-8 > | RX LINE

(Recexve Lme Number) (R)

' <7:0>

RX.CHAR

Description

’These bits hold thet..hinary _n'urnber of the channel on

on which a data-set change was reported.
or

of RBUF <7:0> was received,
which the character

If RBUF <14:12> = 000, these eight bits contain

the oldest character in the receive FIFO. The

(Recexved Character) (R)

character is good.

If RBUF<14:12> = 001, 010, or oL, theseeight |
~

bits contain the oldest characterin the receive FIFO.
The characteris bad

If RBUF< 14: 12>

lll these exght bltS contam.

diagnostic or modem status information. In this case,
RBUF<O> has the following rneamngs

O'= Modem status in RBUF<7 1>

1 = Dlagnostlc mformatlonin RBUF< 71>

- If there is an overrun condmon the four-character
- UART receive buffer for that channel will be cleared.

This data will be lost. A null characteris placed in the receiveFIF O and RBUF < 14> 1s set.

The DHQll does not have a break-detect blt A line
-

breakis indicated to the program as a null character

w1th F RAME ERR, set, and overrun is clear

3.22.3 Transmlt Character Reglster (TXCHAR) -Smgle-character programmedtransfers are made
through the transmlt character reglster

'TXCHAR (WRITE BASE +2)
a4 13 12

TRANSMIT

- DATA VALID

'»,_TRANSMIT

CHARACTER
RE3238

Bit

) Description

~ Name

TX.DATA.VALI

When set. this bit instructs the DHQll to transmxt
the character heldin bits < 7:0>. The bitis sensed by
the DHQ!
1, which then transfers the character. clears
the bit, and sets TX. ACTIO\I

TX.DATA.VALIDand TX.CHAR can be written
tozether' or by Separate \«IOVB tnstructions.

g 70>

TX.CHAR

3.2. 2 4

| ,(Tra'nsmit Character) (W)

This contains the character to be transmttted The
'_LSBl:bttO
|
.

Lme-Parameter Regtster (LPR) - ThlS register is used
to configure its associated channel.

LPR (BASE +4)
15

‘«13

RWIRWI|R/WI|RWI|RWI|RW[|RW|RW

| TRANSMIT
SPEED

|RW RWIRWIRW|R WI|R WI|R W|RW

STOP
CODE

RECEIVE

EVEN

| SPEED.

PARITY

DIAGNOSTIC

ENABLE

CODE *

PARITY

CHARACTER

LENGTH

DISABLE

- REPORTS

=, OO NORMAL OPERAT!ON

01 = SCREEN RECEIVED XON/XOFF CHARACTERS

- FROM ENTRY INTO RECEIVER BUFFER IF

-0 AUTO ISSET
_

N
qE2719

o ,Bit E
<15:12>

~ <118>
|

Name

Description

TX.SPEED

This bit is set to 1101- by \'IASTER RESET (9600
(Transmltted Data Rate) (R/W) bnts/s) It defines the transmxt data rate (Table 3-2).

RX.SPEED
| (Recetved Data Rate) (R/W)

STOP.CODE

(Stop Code) (R/W)

This bit is set to 1101 by MASTER.RESET (9600
~

buts/s). It defines the receive data rate (Table 3-2).

Thts bit defines the length of the transmitted stop btt.y |

- StOP bit for 3-. 6-, 7-. or 8-bit charactetsf |
stop bits for 6-. 7- or8 btttharacters orl. 3' stop bits for 3 bit characters
-

3-8

Bit

. Name

Descnptlon
|

The bitis cleared by MASTER RESET

. EVEN.PARITY

If LPR< 5> is set, this brt defines the type of panty_ g

(Even Parity) (R/W)

l = Even parity
0= 0Odd panty

" The bitiscleared by MASTER. RESET.
PARITY.ENAB

~ (Parity Enable) (R/W)

Thrs blt causes a parxty bit to be generated on transrmt.
and checked and. stripped on receive.
Parity enabled

Panty disabled

The b1tis cleared by MASTER RESET

. CHARLGTH

Character Length) (R/W)

These two bits define the length of characters. The
length does not include start, stop, and parity bits.

00
01

5 bits
6 bits
7 bits

8 brts N

o<21>

DIAG

- (Diagnostic Code) (R/W) -

They are set to 11 by MASTER RESET
Dlagnostrc control codes are are used by the host as
follows

00 = | Normal operation ‘
01 =

Causes the background monitor program

(BMP) to report the DHQL11 status through
the recexve FIF O

. Other codes are reserved

<0>

DISAB.XRPT

(Disable XON/XOFF

‘. 0=

XON and XOFF characters are reported on

all channels

Reporting) (R/W)

IfLNCTRL<4> is also set for a
.particular

~
N

3-9

- channel, these characters are filtered from the

received data stream, to relieve the host of the need to do so

Name

- Bit

| Description'
~ On mmahzatxon this bitis cleared. In order to read or
write to this bit, CSR< 3 0> must equal zero.

\IOTE

An XON code = 21, DC C
= TRL/Q An XOFF
code =23,=DC3=CTRL/S. No other codes are
specxfied for the interface.

Table 3-2

Data Rates

~ Code

Data Rate

0000

0001

0011

)

1100

72000

1110
S

19200

ool

)

001

o
|

0.01

»
B

138400

0.07

2000
2400

4800

1800

1011

Error (%)

o001

300

Maximum

o0l

- 0101

1001
1010

1345

0100

1000

)

- (Bits/s) |

0.19
001

001

0.0l

)

’

- 0.01

0.01

3.2.2.5 Line-Status Register (STAT)
-. The hxgh byte of thxs regxster holds modem status mformauon |
The low byteis undefined.

STAT (READ BASE+6)

13 12

R|IRrR|R|

DSR

- DCD
RI

(RING
INDICATOR)

9
|

rR|R

7 6 5 4

)
|

cts

MDL
= MODEM SUPPORT PROVIDED FOR THIS LINE

1 = MODEM SUPPORT NOT PROV!DED FOR THIS LINE
L
‘
o
310

Bit

_Descripfion |

| Name
DSR

(Data Set Ready) (R)

~ This bit gives the present status of the Data Set
|
- Ready (DSR) srgnal from the modem.
1

-0

ON
OFF

| NoTE‘
In order to report a change of modem status, the
" DHQI11 writes the high byte of STAT into the low
< 14:12> = 111 indicatesto
byte of RBUF. RBUF
the host that RBUF <7:0> holds modem status
o
| mformatlon instead of a received character.
13

RI
. (ng Indlcator) (R)

~ This bit gaves the present status of the ng Indxcator B
|

(RI) srgnal from the modem

DCD

| (Data Camer Detected) (R)

ON
OFF

o
This bit gives the present status of the Data Carrier
-

- De tected (DCD) 51gna1 from the modem
ON
OF F

|
|
CTS
(Clear to Send) (R)

| Thrs bit gives the present status of the Clear To Send
(CTS) srgnal from the modem

1 =ON
0= OFF

ERT

Bit

Name

Déscription |

MDL

Always reads as 0 for DHQll o mdxcate that the

'(MDL Modern Support Low) (R)

module has modem support capabnhtv

NOTE

Itis only necessary to read the modem support status

for one line, since all the other lines will have the same
semng

Reserved

3. 2 2 6

mtertace

This bit is set to zero on t'actory‘-‘is;ued' boards.

Lme-ControI Regnster (L\CTRL) - The main tunctxon ot this rem:ter 15 1O gontml the lme

LNCTRL (BASE + 10)

1§

12 11 10

1rw

RTS

09 08 07

06 05 04

rw
| rw [rw [rw | rw!lewlrw!|rw|rw|rw

DTR

MAINTENANCE

MODE

0aUTO | RX
-

FORCE.

COLNK

TYPE

XOFF

ENABLE |

BREAK

ABORT

IAUTO

‘Bit

“Name

. Descnptlon

| RTS

This bit controls the Request To Send (RTS) signal.

~ (Request To Send) (R/W)

1= ON

0 = OFF

(Data Terminal Ready) (R.W)

This bit controls the Data Terminal Ready (DTR) 'signal. o
- ON

DIR

O —

OFF

», N ame

Bit

~ This bit must be set if ’;thechannel is to be connected to a-

LINKTYPE

(Link Type) (R/W)

modem. When the bitis set, any changein modem status

- will be reported through the receive FIFO as well as the
STAT reglster

If this

bit is cleared,

this channel

becomes a

‘data-leads-only’ channel. Modem status information is

- loadedin the high byte of STAT, but is not placedin the
| recexve FIFO
|
| MAINT |

?(\/Iamtenance Mode) (R/W)

L These bits can be wntten by the dnver or test programs in
- order to test the channel
|
|
e ‘_The codmg-is as follows:

00 =

Normal operation

Automatic echo mode — Received data is
- looped back to the terminal (regardless of the

state of TX.ENA) at the data rate selected for

the receiver. The received characters are
processed normally and placed in the receive
FIFO. Any data that the host attempts to
transmit on this channel will be discarded by
- the OCTART. The RX.ENA
bit must be set
when operating in this mode.
|

‘Local 1O0Pback — Data trahsrnitted by . thev»_

to the receive buffer. Data
~ host is looped back
~ received from the terminal
is ignored, and the

- transmit data line to the terminal is held in the
mark condition. The data rate selected for the
~transmitter is used for both transmission ‘and
reception. The TX.ENA bit still controls

transmission in thxs mode The RX.ENA bitis .

ignored.

1= Remote loopback — In’ this mode, data

received from the terminal is looped back to the

~ terminal at a clock rate equal to the received
clock rate. The datais not placedin the receive

313

FIFO. The state of TX.ENA is ignored. The
RX.ENA bit must be set on this channel.

;_Name

- Description

FORCE. XOFF

Thts bit can be set by the program to 1nd1cate that this
channelis congested at the host system (for example, if the
typeahead buffer is full). When it sees this bit set. the
DHQI
1 will send an XOFF code. Until the bitis cleared.
XOFFs will be sent after ev ery alternate character received

- (Force XOFF) (R/W)fl

~on this channel. When the bitis cleared. an XON will be

received from a channel. The DHQI1 uses the TX.ENA
in TBUFFAD?2 o stop und start the tHow. It

bit

- DISAB. ‘(RPT 1s also set. XON XOFF codes are not
entered 1n the receive FlFO

BREAK
’(Break Control) (R W)

’

[f set. this bit forces the transmxtter of this channel to the
spacing state.

If this bit is set whi.. a character s bemg transmxtted

transmission is compi&.[Cd before breakis asserted on the

line.

Transmission is re-enabled when the bit is cleared.

\IOTE

Ifthe lineis tdle there may bea delay of up to 170

~
~

microseconds between writing the bit and the channel
changing state. If a character is aiready being

transmitted by the OCTART, the BREAK signal will

'be tramnntted immediately afterwards

RX ENA

If thxs blt is set this receiver channel 1S enabled

(Receiver Enable) (R/W)

[f this bit is cleared when thxs channel is assemblmg a
| character that characteris lost

~ The bit is cleared by \/IASTER RESET.
- IAUTO

- (Incoming Auto Flow) (R W)
-

Thisis the auto flow control bit tor mcommo characters
Ifitis set. the DHQI1 will controlincoming chardcters by
transrmttmc XO’\I and ‘(OFF codes

.'/

Thlb bit is the auto- How control bit for outgoing
characters When set. it RX.ENAis also set. the DHQll
- will automatically respond to XON und NOFF codes

Outeomo Auto Flow) (R W)

foacro

/.‘

- sent unless [AUTOis set and the recene FIFOis crmcal

Bit

Name

If the receive FIFO becomes more than three-qttarters full,

the DHQI11 will send an XOFF code to that channel, and
to any other channel which receives a character and has
the IAUTO bit set. When FIFO becomes less than half
~ full, an XON will be sent to all channels Wthh had
~ previously beensent an XOFF.

TX.ABORT

Thxs bit is set by the dnver program to halt data

(Transmit Abort) (R/W)

transmission. If a DMA transfer was in progress, the
DMA address and count registers (TBUFFADI.
TBUFFAD?2, and TBUFFCT) will be updated to reflect
~the number of characters which have been transmitted.
~ The transfer can be continued by clearing TX:ABORT,

and then setting TX. DMA. START m TBUFFAD- \Io

characters will be lost.

If DMAis not in pro’gress,'no action is taken.

When an abort seQuence has beerr completed, the »DHQ l lf,

will set the TX.ACTION bitin the CSR. If the transmitter
~ interruptis enabled, the program will be 1nterrupted at the

transmtt VCCtOl'

"The prograrn must make sure that TX. ABORT 1S clear |

before setting TX.DMA.START, otherwise the transfer
~will be aborted before any characters are transrmtted

The bit|1s cleared by MASTER RESET

3227 Transmit Buffer Address Register Number 1 (TBUFFADI) TBUFFAD1 (BASE +12)

6 5

aw [rRw [rw | rw [rw [ Rw [rw | Rw [rw [Rew | Rw

aw [rw |rw | Rw

"TXMIT DMAADDRESS
|
(BITSOTO15)
‘

- Bit

Name

< 1‘5:O.I> | .TBUFFAD <15: 0>

(Transmit Buffer Address [Low])

Descnptlorl'
Bits <15: 0> of the DMA address

(R/W)

3-15

3.2.2.8

Transmit Buffer Address Regxster Number 2 (TBUFFADZ)-

TBUFFAD2 (BASE +14)
:,15

122

Trw

TXMIT

COMA

- ENABLE

START

Name

TXMI
ODMA ADDRE
T
SS
1BITS 16 TO 21)

| Description |

15 TXENA

| .'(Transmrtter Enable) (R W)

When this blt is set. the DHQH will transmut all
chdracters
|

When this bit is cleared, the DHQII will only

transmit internally generated flow-control characters. -

The bit is set b\ \/IASTER RESET

In the OAUTO mode, thrs bitis used by the DHQll
to control outgoing characters.

7
-

TX.DMASTART

(Transmit DMA Start) (R/W)

This bitis set by the host to start a DMA transfer.

The DHQI!!1 will clear the bit before returning
TX.ACTION.
|
|

The bit is cleared by MASTER.RESET.
N OTE

<50>

After setting this bit, the host must not write to
TBUFFCT, TBUFFADI1, or TBUFFAD2 <7:0>
until the TX.ACTION report has been returned

TBUFFAD<21:16>

(Transmit Buffer Address [ngh])
( R/W)

Bits <21:16> of the DMA address. Before a DMA -

transfer, TBUFFADI!
and the low byte of
TBUFFAD?2 are loaded with the start address of the
DMA buffer. This address will be contmuously
»changmg during a DMA transfer and has no
meanmg Once TX.ACTION has been returned. the
- register c.ontams the final DMA transfer address.

3-16

3. 229 Transmit DMA Bufl'er Counter (TBUFFCT) -l
B

TBUFFCT(BASE+16) |
15

DMA CHARACTER COUNT

(WHEN VALID HOLDS NO OF CHARS STILL TO BE SENT)

Bit
'.<1&0>_

) Name

~ Descnpnon

TX CHAR CT

Thxs word1s loaded with the number of characters to

(Transmlt Character Count) (R/W) -be transferred by DMA.

The nurnber of characters 1S specxfied as a 16-bit
un51gned integer.

After a DMA transfer has been aborted this locatxon
- will hold the number of characters Stlll to be
g transferred
|
|
|
.

See also the prewous NOTE

3-17

3.3

PROGRAMMING FEATURES

[nitialization

'33.1

The DHQIL is mmahzed by 1ts on-board sequencers

Inmahzatxon takes place

| "(MASTER RESET)

after

bus

reset

sequence

when the host

sets C5R<J>

B
|

Before starting initialization. the on--board sequencers perform a self- test. The results of thl: test are

'reported by euzht dxaznostlc b\,tes in the receive FIFO.

The DHQll state. atterd auecesstul self-test. is as tollows

s 1.
2

)

Euzht dxaenostlc codes are pLu.ed In the receive FIFO |
The d;agnostne tail bit (CSR< 13>)1s clear_

All chanr_iels are set for:

a. Send and receive 96’00 bits s
b ‘Eight da:.tav bit_S R
c

One stop bit

d.. No pafity |
‘e

|
R
|

Parityodd

.'f. Auto-flow off

g Receive disabled
h. Transmit enabled
.

’

)

No break on ,line

j. No loo'pb'ackv

k. v Link type set to data-leads-only
I DTR and RTS off

’m. | DMA chara_cter co_unter‘ zero

| n ' DMA start address\ r-vegisters} zero
0.

TX.DMASTA RT cleared

,é.'TXABORTeleared q.

Auto fow reports enabled

)

‘The DHQl l clears the MASTER. RESET b1t (CSR <5> )when 1mt1ahzatlon and self-test are complete
332 Configuratlon

- After DHQII self-mltlahzatlon the dnver program can configure the DHQII as needed ThlS1S done

through the LPR and LNCTRL registers.

The line charactenstxcs for a channel can be set up by wntmg to the LPR and LNCTRL regrsters
associated w1th this channel These are:
®

Transmit speed g

o 'Recelve speed

o | Number of stop blts
)

'Panty type or par1ty dxsabled

| 0- " Character length
e _Flow-contrOl characteristics

° “Normal or maintenance .r,node.
° Receiver enable/disable B
@ Modem or data-leads-‘only. )
o
o

' NOTE-

| IfRXENA:smetwhfleareceivedcharactensbemg
assembled,thatcharactermllbelost. R

) 333 Transrmttmg

- Each DHQll channel can be set up to transfer the characters by DMA or under program control

3. 3 3 1 DMA 'Ihnsfers - Before settmg up the transfer of a DMA buffer, the program should make
sure that TX.DMA. START is not set. TBUFFCT TBUFFADl and TBUFFAD?2 should not be

written unless TX. DMA STARTis clear.

Transmission will start whenthe program sets TX DMASTART The size of the DMA bufi'er and 1ts I
start address, can be written to TBUFFCT, TBUFFADI, and TBUFFAD?2in any order, provided that
the TX.DMA start bit (TBUFFADZ <7>)is not set. However, TBUFFAD?2 contains TX.ENA and
- TX.DMA.START, so it is probably simpler to write TBUFFAD?2 last. By usxng byte operanons on this
register, TX. ENA and TX. DMA START can be separated.

“The DHQIl! will perform the transfer and set TX ACTION when it is complete If TXIE is setthe“
program will

be interrupted at the transmit vector. Otherwise, TX. ACTION must be polled.

TX.ACTIONis not returned untll the UART has completely transmitted the last character of the DMA
buffer.

3-19

To abor
a DMA
t transfer, the program must set TX.ABORT. The DHQI ! will stop transmission. and

update TBUFFCT, TBUFFADI, and TBUFFAD2<7:0> to reflect the number of characters which
have been transmitted. TX.DMA.START will be cleared. If TXIE is set. TX.ACTION will interrupt the
program at the transmit vector. If the program clears TX.ABORT and sets TX.DMA.START. the
transfer can be continued without loss of characters.
o
e
o
-

If a DMA transfer fails because of a host memory error. the transmission will be terminated.
TBUFFADI! and TBUFFAD?2 will point to the failing location. TBUFFCT will be cleured.

3.3.3.2

Programmed I/O - Single characters are transferred thtough‘ the c_h‘a‘nnelTX.C HAR register. |

The character and the DATA.VALID bit must be written as defined in Section 3.2.2.3.
Note that the
character and the DATA.VALID bit can be written by separate MOVB instructions.

When the DHQI I removes the character trom TX.CHAR. it returns TX.ACTION. This will generate

an interrupt
if TXIE is set.

NOTE

In single-character mode, TX.ACTION is returned

when the DHQ!11 accepts the character, not when it

has been transmitted. Each channel can buffer up to
three characters. Therefore, if line parameters are

changed immediately after the last TX.ACT[ON ofa
- message, the end of the message could be lost unless
three null characters are added to the end of each
single-character programmed transfer message.

3.3.4 Receiving
|
|
S
e
|
S
|
et
|
Received characters, tagged with the channel number, error information and DATA.VALID, are placed
in the receive FIFO. RX.DATA.AVAIL
is clear when the receive FIFO is empty. When a character is put

into the empty receive FIF
the O,
DHQI1 sets RX.DATA.AVAIL.
A receive interrupt is generated if

RXIE is set. RX.DATA.AVAIL stays set while there is valid data in the receive F [FO. [t is recommended
e

that the

receive character

routine continues to

read characters from

the receive

FIFO

until

providone
es of two vector addresses during a bus interrupt sequence. The receive

vector

DATA.VALID is clear.

:NOTE.

The inter_nll!t‘ ‘is dynamié'; It s raisedv’ as

RX.DATA.AVAIL is set after RXIE, or as RXIE is
set after RX.DATA.AVAIL. If the interrupt routine

~does not empty the receive FIFO, RXIE must be

- toggled to raise another interrupt.
.

If RXIE. Is not s»et.’the program must 'poll’ RBUE often é’nough' to'prexieht data Ioés.

3.3.5 Interrupt Control
The DHQI!

address is the address set up on the vector address switches. The transmit vector address
is the receive
vector address + 4.

‘

Thereceive mterrupt vector 1s generated when:

- N

RXIE 1S set and a character1s placed 1nto an empty recexve F IFO
0

RXIE is changed from 0to L, and the receive FIFO contalns one or more characters

The transmxt mterrupt vector 1S generated when:

o TXIE is set and TX ACTION becomes set

'@ TXIE is changed from 0 to | while TX.ACTION is set
v,

- /)

NOTE

Up to 16 TX.ACTION reports are buffered. It is
|
)

therefore recommended that your program reads the
CSR until the TX.ACTION bit becomes clear,
othermse TX.ACTION will be lost
-

At the two vectors, the host must provrde the addresses of suttable routmes to deal with the above
condmons
-

33.6 Auto XON And XOFF

o ~XONand XOFF characters are commonly used to control data fiow on commumcattons channels To
~use this facrhty, mterfaces must have suttable decodrng hardware or software

Ee—

o
-

- A channel usmg fiow control that recetves anXOF F stops sendtng characters untll 1treceives an XON |

B If the receive FIFO becomes more than three-quarters full, the DHQI 1 wxll send an XOFF code to that
‘channel, and to any other channel which receives a character and has the IAUTO bitset. When FIFO
‘becomes less than half full an XON will be sent to all channels whrch had prevrously been sent an
XOFF

The DHQI! automattcally controls character flow when programmed accordmgly (auto-fiow) Four

Rblts control thrs function:

IAUTO

FORCEXOFF — LNCTRL<S>

e OAUTO
°

— LNCTRL<1>

— LNCTRL<4>

DISABXRPT e LPR<0>

- IAUTO and FORCE XOF F both controltncomtng characters IAUTOis an enable bit which allows N
the level of the receive FIFO to control the generation of XOFF and XON characters. The
'FORCE. XOFF bltis a direct command from the program to control the mcormmg data stream |
3.3. 6 1

IAUTO The DHQI1 hardware recognizes when the receive FIF OIS three-quarters full and

half full The logic uses these states for auto-flow control

3-21

'Each channel has a separate IAUTO bit. If there are 191 or more characters in the receive FIF O. and a

- character is received on a channel with [AUTO set, an XOFF characteris sent. [f the channel does not
respond to the XOFF, the DHQI! will send another XOFF in response to every alternate character
received. An XON will be sent when the receive FIFO contains less than 128 characters. unless the
FORCE.XOFF

bit for that channel is set. XONs are only sent to channels to whxch an XOFF has

prevxously been sent.

By inserting XON and XOFF characters into the data stream. the proeram can perform flow control
directly. However. if the DHQI1 is in IAL TO mode. the results will be unpredlctable
|
[n IALTO mode if RX. E\IA1s set. XON and ‘(OFF characters will be transmltted even ll TX. E\ Als
cleared.

3.3.6. 2

FORCE XOFF - When FORCE.XOFFis set. the DHQI| sends an NOFF md then acts asit

[AUTOis set and the receive FIFOis critical (was three-quarters full. andis not vet less than halt tull),
When FORCE XOFF1S reset an ‘(O\ will be sent unless the receive FlFOIS crttlcal and [ALUTOI~ ~el

3.3.6.3 OALTO- Il'the proeram sets OAL TO the DHQl 1 mll automatically respond to .\O\ d

XOFF characters from the channel It does this bv clearing or setting the TX. E\ A bl[

The program may also control the TX. ENA blt 50 in this ¢case it is lmportant to keep track of recened
XON and XOFF characters

Recetved XON and XOFF characters will always be reported thtough the receiveFIFO unless the

DISAB.XRPT bit is set. It is possible, during read-modify-write vperations by the program. for the
- DHQI1 to change the TX.ENA bit between the read and the write actions. For this reason. if DMA
e transfers are started wl'nle OAUTOis set it lS advisable to write to the low byte of TBUFFADZ only

- 3.3.6. 4 'DISAB.XRPT - If DISAB XRPTis clear. XON and XOFF characters will be processed as

normal characters and are entered into the receive FIFO. DISAB.XRPT allows the individual lme
- OAUTO bits to control whether XON or XOFF characters received on that channel are dtscarded
When DISAB XRPTis set and OAUTO is set, thrs filtenngis enabled.
NOTES‘

When checking for flow-control characters, the
'DHQI11 only checks characters which do not
contain transmission errors. The parity bit is
stripped, and the remaining bits are checked for
XON (21 s) and XOFF (23,) codes.

Auto flow-control does not absolutely guarantee
that overrun errors will not occur. These errors
may still occur if the transmitting devices do not

respond to the XOFF immediately.

3 3. 7 Error Indtcatlon
Four bits mform the proeram of transmission- and reccptlon errors
o

TXDMAERR

—

CSR<12>.

e PARITYERR

— RBUF<IZ>. -

FRAMEERR — _.RBUF<‘13>.
e OVERRUN. ERR — RBUF<14>.

e
~

RBUF<14 12> also 1dent1fy a dxagnostxc or modem status code.

338 Modem Control

Each channel of the module provides modem control bits for RTS and DTR. Also on each channel are

" modem status inputs CTS DSR, RI, and DCD. These bits are used t’or modem control (see Section
13.2.2.5).

CTS. DSR and DCD are sampled every 10 ms. Therefore fora change to be detected, these bltS must

- stay steady for at least 10 ms. Rlis also sampled every 10ms, but a changeis not reported unless the new
state is held for three consecutive samples. Modem signals must be coordinated under program control;
thereis no hardware modem control logic. Modem status change reports are placedin the receive FIFO
only if LINK.TYPE is set, but any changes are updated in STAT 1rrespect1ve of the state of
- LINK. TYPE

~ Appendix A nges more detalls of modem control

By cleartng LINK. TYPE, a channelis selected asa ‘data-hnes only channel Modem control and status
bits.can still be managed by the program, but status bits must be polled at the hne-status reglster
Changes of modem status will not be reported to the program

| Status change reportmg is done through the receive F IFO as follows @

When OVERRUN. ERR F RAME ERR, and PARITY.ERR are all set, the erght low-order |

~ bits contatn erther statuschange or dxagnostlc information. In this case:

If RBUF<O> = O RBUF<7l> holds STAT<159> (see Sectxon 3225)

If RBUF<O> = ], RBUF<7 l> holds dtagnosttc mformatlon (see Sectlon 3. 3 10)

3.3.9

Mamtennnce Progr

The host can set bits 7 and 6 of LNCTRL to allow each channel to be configuredin norrnal automatic

echo, local loopback, and remote loopback modes. These modes allow an individual data channel to be

f,looped back
to the host, or to be looped back to the termmal to assxst m 1solatmg commumcatxon
problems.

- The hostmust provide suxtable software to use these modes

) 3 3. 10 Dlagnostxc Codes

3.3. 10 1 Self-Test Dtagnostlc Codes After bus reset or master reset, the DHQll executes a self-test
and initialization sequence. Dunng the sequence, etght diagnostic codes are put in the receive FIFO and

RX.DATA. AVAILis set.

After an error-free test, DIAG FAIL w1ll be reset and the ‘dragnostrc passed’ LED wxll be on. If anerror
is detected DIAG FAIL wxll be set and the LED wxll be ofl’

323

33 10.2 Interpretanon of Self-Test Codes- The htgh byte of dtagnosnc codes in RBUF can be

interpreted as in Section 3.2.2.2, except that bits <11:8> are not the line number. They indicate the
“sequence of the diagnostic byte, thatis to say, 0 = first byte, | = second byte. and so on. Table 3-3 shows

the meamng of each of the error codes.
Table 3—3

DHQll Self-Test Error Codes

Test

Code
bits<7:0> |

| "'301»

ar
225

Sell’-test null code (used as a filler)

'OCT-\RTerror
S

235

RAM error

RTS-CTS- DCD'err'or

" DTR- RI- DSRerror

All other error codes should be treated as an undefined error..

vIl‘ bit 7O and bit 0 =1, then btts < 5 7>contatn ctrcutt re\rston tnforrnatton

Bit 6 always reads | for the DHQll and mdtcates that the Cll'CUlt contains control and OCTART
chips.

~ Bitl indicates to which chi‘p t_he"int'ormation refers:*O", -—-”- Control, | = OCTART. »
After self-test the eight FIFO codes consist of six dtagnosttc codes and two circuit revision codes If
there are less than srx errors to report aull codes (2013) fill the unused places

. After an error-free test six null codes and two c1rcurt rev1sxon codes will be returned
Self-test may be skxpped to shorten the tmttahzatton cycle (see Sectxon 3 3 lO 3)

" The modules still tested evenif self-testis skxpped The reset delayis much shorter but test coverage is
not affected therefore sktpprng self-testis advantageous.

After ‘skip self-test’ self-test, the eight FIFO codes consist of six dtagnosttc codes and two circuit
revision codes. If there are less than six errors to report, 203, codes All the unused places |

After an error-free test, six ’03q codes and two cxrcutt revision codes mll be returned

33103 Skipping Self-Test - The following methodis used
|.

The program resets the DHQll

2. The program waits lO ms (£ | ms) afterissuing reset. and then attempts tow rite 0:»"5’3 to
any of the control remsters except the CSR mthtn the next 4 ms.

3. F ollowmg self-test, the DHQII hardware checks whether an attempt was made to write the

skip code to the registers during the 4 ms window after reset (see step 2 above). If an attempt

was made, the MASTER.RESET bitis cleared at 30 ms afterissuing a reset mstead of 1.2s.
The 1.2 s reset time was retamed for compatlbrhty thh the DHVll
N OTE

~ The program must notwnte to the CSR, or to the

control registers, during the period starting 1S ms
after reset, and ending when the MASTER.RESET

~ bitis cleared. Writing during this penod could cause a

diagnostic fail condmon

3.3, 104 Background Momtor Program (BMP) ~ The DHQll BMP logic performs background
self-tests by checkmg for OCTART tnterrupts One of two codes is returned to the receive F IFO:

3053— DHQll runnmg

- 307 — DHQI1 defectlve (also LED ofi)

A single dlagnostlc word1s returned to the receive FIFO The low byte contams the dxagnosttc code.In

~the high byte, OVERRUN.ERR, FRAME.ERR, and PARITY.ERR are all set to mdxcate that
bits<7: 0> do not hold a normal character The line number (RBUF < ll 8>)
|

BMP normally only reports when it finds anerror. However, the program can get a BMP report atany

time to check the DHQll Thisis done by setting DIAG (LPR <2:1>) of any channel to 01 The hne. |
| _number returnedis that of the LPR used to request the report.

On completmg the check, BMP clears this 01 code. The host should not wnte to the LPR of that channel
unt11LPR<21>becomesOO

3225

= £ SRR

3. 4 PROGRAMMING EXAMPLES

These programs are not presented as theonly way of dnvmg the opuon and are nexther zuaranteed nor

supported.

3.4.1 ResettingThe DHQII
In the following example'
®

DIAGCisa routme to check the dxaenosnc codes [t retums with
~error code

CARRY set lfit detects an

The loop at ‘l_S 'ta_k‘es‘ __l“.._v’.,’_‘second‘s.'"so-- the 'pr'ogrammer could poll fithrOugh

_av timer or poll at

- interrupt level zero.

‘A ROUTINE TO RESET THE DH011 AND CHECK THAT IT IS FUNCTIDNI
NG
CORRECTLY.
.

MOV

JSR
BCS

@sRBUFF,R0

wse we
-

WAIT FOR HflSTER RESET O

CLEAR.
|
CHECK THE DIAGNOS"CS
FAIL BIT.
NOTE: TEST INSTRUCTION IS
' OK BECAUSE THERE ARE
'NO

TRANSMIT.ACTS PENDING.

SET UP A COUNT.

GET NEXT DIAGNOSTIC CDDE
PROCESS 1IT.

PC,DIAG
DIAGER

SRR

BEEN AN ERROR.

GO BACK FOR NEXT CODE.

RS,2s

'CARRY SET - MUST HAVE

; RETURN - CARn‘Is RESET.

DHAi1Y HAS FAILED TO RESET PROPERLY S0 HALT AND HAIT FOR

THE FIELD SERVICE ENGINEER

" RTS

8. ,RS

DIAGER: HALT
~
BR

DIAGER

‘CLEAR INTERRUPT ENABLES.

QCSR

s
%20000, eoouocsn
DIAGER
|

-.SET HASTER RESET AND

840, ECDH

2$:

MOV

WE WE

fBIT

BNE
CBIT
| BNE
o

Wa We

'135

NMe

340 @ODHOCSR

MOV

DHARES: :

342

Configuratlon

This routine sets the charactenstlcs of channel l as follows
Transmxt and recexve at 300 bltS/S

2. Seven data bltS w1th even panty and one stop b1t

Transmitters and receivers .enabled

No modem “c4o_ntrol
‘No automatic _fl_dw control.

RIS

; LOAD INDEX REG

#082560,@8LPR

MOV . =4,@8LNCTRL
MOVB

s{,@DHQCSR

#200,@eTBFAD2+1

WEe

MOV

)

'HOV

WITH CHANNEL NO.
DATA RATE, STOP BITS,

PARITY AND LENGTH.
ENABLE THE RECEIVER.

ENABLE THE TRANSMITTER.

- CHANNEL { DONE.
PC; RETURN
)

- 3ETUP::

327

3ct3”'1}anmmunfing
3.4.3.1 Smgle-Character Programmed Transfer - Thisis a prozram to send a message on channel l.
The message (MESG) is an ASCII stnng thh a null character as terminator.
|
Polling is used, but a TX.ACTION interrupt could also beused.

This program would function on a DHQI! with only this channel active. Otherwise it would lose

TX.ACTION reports of other channels Howe»er a proszram to control all channels would be toobigto
use as an example

;

A ROUTINE TO URITE A MESSAGE TO CHANNEL t USINC SINGLE CHARACTER
HUDE

SINGOT: ;

MOV
|

~
|

%200,@8TXCHAR+1

MOV

@eDHGCSR,Rt

BPL

BNE

;

RETURN IF

ALL

CH- RACTERS

; SET DATA VALID BIT T0 START

;

#000400,RY

ISOLATE CHANNEL»NUHBER.
|

~; IGNORE THE TX.ACT IF IT IS
o

; GOME.

Rty

RTS

MESG:

; MOVE CHARACTER ro TRANSMIT
; BUFFER.
|

s174377,Rt

CHANNEL NO.

;-UAIT FOR TX. ACT

5 POINT TO MESSAGE.

MOVB

CMP

TXI

BIC
;

(RO)+, esrxcuaa .
»

BE@

o LOAD INDEX REG UITH |

cnsscRO

MOVB_
.
~

sy, @cDHQCSR'-_

MOV

NOT

OURS

(SHOULD

NOT

HAPPEN).

GO BACK FOR NEXT CHARACTER.

; MESSAGE SENT.

.ASCIZ /A SINGLE-CHARACTER MESSAGE FOR CHANNEL
1/

THIS PROGRAM SENDS A MESSAGE OUT ON EACH LINE OF THE DHO11 AND

HALTS THE MACHINE
WHEN ALL TRANSNISSIONS HAVE COWPLETED.

“TME

3.4.3.2 DMA Transfer -

USED TO SIGNAL TRANSMISSION COMPLETION.

was

%Ne

THE MESSAGES ARE TRANSMITTED USING DMA MODE, AND INTERRUPTS ARE

DMAINT::

STXINT,@#TXVECT

MOV

CLR

MOVB
MOV
MOV
~
MOV
-

INC
S0B

CLR
MOVB
|

~
28:
|

CMP
BNE

HALT

R ,@eDHQACSR
sDMASIZ,@sTBFCNT
sDMAMES ,@sTBFAD1
#100200,@sTBFAD2
|
|
R{
RO,1$

;,SELECT THE REGISTER BANK
; SET LENGTH OF MESSAGE.
n
; SET LOWER 16 ADDRESS BITS.
; START DMA WITH TRANSMITTER
; ENABLED (ASSUME UPPER ADDRESS
; BITS ARE ZERO).
; POINT TO NEXT CHANNEL.
; REPEAT FOR ALL LINES.

; RS IS USED BY INTERRUPT ROUTINE.

; START AT LINE ZERO.

40100 Q'DHOCSR+1 ;;ENADLE TRANSMITTER INTERRUPTS
v_CB.,RS

;»NAIT FOR ALL LINES TD FINISH

-; ALL noflz, so sruP;

TRANSNITTER INTERRUPT ROUTINE

RS IS INCRENENTED AS EACH LINE COMPLETES.

; INTERRUPT PRIORITY FOUR.
; EIGHT LINES TO START.

'SET UP THE INTERRUPT VECTORS.

8200 ,@8TXPSW
*8.,R0

TXINT::
-

|
~

MOV
BIT

INC

@#DHQCSR,RO; GET LINE NUMBER OF FINISHED LINE.
*100000,R0
4$
.

TXINT

; CHECK FOR (ANOTHER) TX.ACTION.

; IF NOT, GO RETURN AND WAIT.

) FLAG THAT ANOTHER LINE HAS FINISHED

RTL

HALT

_5‘”

- DMAMES:

.ASCII

DMASIZ

=
.EVEN

5 MEMORY PROBLEN

(15)(12)(7)(7)(7>/SYSTEN CLOSING DONN NOW/
-DHANES

- 3.29

THIS ROUTINE
IS CALLED TO ABORT A TRANSMISSION (EITHER DMA OR

FIFO)

PROGRESS.

ON ENTRY

OTHER

TRANSFERS

”

RO CONTAINS THE,NUHBERIOF THE LINE roflssinaonrzn;“

“we

PROGRESS ON A SPECIFIED LINE. THIS ROUTINE MAKES THE

(RATHER RASH) ASSUNPTION THAT THERE ARE NO

‘-

-e

wWe

- 3433 | Aborting A Transmission -

'TXABRT;:

MOV

~ BIS
i$:

RO,@%DHACSR
*1,@8LNCTRL

MOV

- @#DHACSR,RY

SWAB

|
| #177760,R1.
RO,RL
1)

BPL

BIC

BNE

s
RY

POINT T0 THE CHANNEL TO BE ABORTED
SET THE TRANSMIT ABORT BIT.

WAIT FOR THE TX.ACT.

CHECK IT IS OUR LINE.
; IGNORE IT IF IT IS NOT (OUR
ASSUHPTIGN WAS URONG')

BIC

1,@8LNCTRL

;.CLEAR DOUN THE ABORT FLAG
FOR NEXT TIHE

RTS

kpcl
va:»
'
:

BUFFER COHPLETELY ABORTED
=
IF A DMA WAS IN PROGRESS, THE
‘DMA REGISTERS REFLECT UHERE
THE DNGii HAD GOT TO

3-30

ROUTINE PROCESSES

THIS

RECEIVED

CHARACTERS

UNDER INTERRUPT

IF AN XOFF IS RECEIVED, THE TRANSMITTER FOR THAT
THE TRANSHITTER
CHANNEL IS TURNED OFF. IF AN XON IS RECEIVED

CONTROL.

IS TURNED BACK ON.

ALL OTHER CHARACTERS ARE ICNORED

PRy

THIS IS JUST AN EXAHPLE A BETTER UAY TD PERFURH FLOW CDNTROL IS
TO USE THE AUTOMATIC CAPABILITIES oF THE DHa14.

»e

3.4.4 Receiving |

MOV

CLR

'HOVB'

8200, @sRXPSH

8.,R0
R1

" R1,@%DHACSR
“s4,@8LNCTRL

INC

RO is

MovB

#100, e-nnacsn

" RTS

- INTERRUPT PRIORITY FOUR..

ENABLE ALL THE RECEIVERS,
STARTING AT CHANNEL ZERO,

SELECT THE LINE.

; ENABLE THIS RECEIVER.

TO NEXT CHANNEL.
5 SET POINTER

; ENABLE THE RECEIVER INTERRUPTS.
; RETURN - INTERRUPTS
DO THE RESET.
?

.“\\‘

/' .

SOB

MOV

. SET UP THE INTERR
VECTORS.
UPT

-wa

SRXINT,@8RXVECT

| RXAUTO::

3-31

"\_L/

. INTERRUPT ROUTINE TO DO THE MAIN TASK.
.

’

RXINT::

RXNXTC:

MOV

Ro, -(SP) . -SAVE CALLER S REGISTERS

MOV
BPL
MOV
BIC
BNE

QORBUFF RO
RXIEND

BIC
SWAB
BIS

; GET THE CHARACTER

RO,-(SP)

RXNXTC

#170200, RO

g _REHOVE UNNECESSARY BITS

*107777,(SP)+ -‘DIAGNOSTICS CDDES

MOVE

#{00,R0
RO, @ODHQCSR

SWaAB
CMPB

RO
i
821, RO

13{

CHPB

BNE

; POINT TO THIS CHARACTER’S
LINE.
. ; (ADD THE INTERRUPT ENABLE BIT. )

. 2200, @8TBFAD2+1 ; ENABLE THE TRANSHITTER

|
GO CHECK FOR MORE CHARACTERS

~RXNXTC

23,0
RXNXTC

UAS IT AN "XOFF*?
o NO- GO CHECK FOR MORE cuaaacrzns )

- BICB ' -2oo @sTBFAD2+1 ; DISABLE THE TRANSHITTER
RXNXTC

RXIEND:

MOV
RTL

C(SPY+,RO

; GO CHECK FOR MORE CHARACTERS.

RESTORE THE DESTROYED REGISTER.

“

= JUST IGNORE THEM (BAD PRACTICE).

3 PUT CHARACTER BACK IN LOHER BYTE
3 WAS IT AN “XON°?
NO - G0 CHECK FDR AN 'XOFF""

BNE
BISB

; IF NODATA VALID, WE HAVE FINISHED.
CHECK FOR ERRORS, HODEH AND

_,’—_-—__.

THIS PROGRAM SENDS A HESSAGE OuT ON EACH LINE OF THE DHG1{ AND

HALTS THE HACHINE WHEN ALL TRANSMISSIONS HAVE COMPLETED.

THE MESSAGES ARE TRANSMITTED USING DMA MODE, AND INTERRUPTS ARE_ i

USED TO SIGNAL TRANSNISSION COMPLETION.

AUTOHATIC FLOW CONTROL 18 ENABLED ON THE OUTGOINC DATA

wWe

345 Anto XON And XOFF

MOVB
~BIS

- MOV

824 ,@sUNCTRL

~8AUTOSZ,@8TBFCNT
,
@8 TBFAD1
SAUTOMS

#100200,@8TBFAD2

SOB

RO,1i$

CLR
HOVB

-'100 QODHOCSR+1

CHP
BNE

_'Zi

2%:

_ 3‘:

HALT
BR

THE

AUTOMATIC FLOW CONTROL

TRANSMIT
DATA.
TED

SET LENGTH OF MESSAGE.
SET LOWER 16 ADDRESS BITS.
START DMA WITH TRANSMITTER
ENABLED (ASSUME UPPER ADDRESS

BITS ARE ZEROD).
POINT TO NEXT CHANNEL.
- REPEAT FOR ALL LINES

A
,,

we e

INC

THE REGISTER BANK.
| SELEC

~; ENABLE
EN

MOV

* R{,@sDHACSR

CLR

WA
. %s

" INTERRUPT PRIORITY FOUR.
EIGHT LINES TO START.
START AT LINE ZERO.

8. ,RO
R

MOV

SATOINT,@8TXVECT . SET UP THE INTERRUPT VECTORS.

#200,@8TXPSW

MOV

wWa

TXAUTU::

; RS IS USED BY INTERRUPT ROUTINE.
; ENABLE TRANSHITTER INTERRUPTS

; WAIT FOR ALL LINES T0 rrursu

’

ALL DONE, SO STOP.

3-33

we
‘s
we

AS EACH LINE COMPLETES.
RS IS INCREMENTED

“ws

TRANSMITTER INTERRUPT ROUTINE.

“ATOINT:
MOV

@eDHACSR,RO ; GET LINE NUMBER OF FINISHED
LINE.

BIT
'BNE

ING
2% .
48

#10000,R0

; CHECK FOR DMA FAILURE.

;GO HALT - MEMORY PROBLEM.

; FLAG THAT ANOTHER LINE HAS FINISHED.

RTI

HALT
BR

; MEMORY PROBLEM

AUTOMS: .ASCIT (18)<12)<7)(7)(7)/SYSTEM
CLOSING DOWN NOW/
.~AUTOMS

AUTOSZ

J/,

.EVEN

334

" THIS ROUTINE CHECKS THE DIAGNOSTICS CODES RETURNED FROM THE

| DHQ1i.
. DHGL1.

ON ENTRY,
RO CONTAINS THE CHARACTER RECEIVED FROM THE
ON EXIT, THE CARRY BIT WILL BE CLEAR FOR SUCCESS, SET

MOV

BIC

BNE

\\-m/

CHP

MOV
BITB

RO,-(SP)

; SAVE THE CODE FOR LATER.

#107776,R0

; CHECK THAT IT IS A DIAG. CODE.

DIAGEX

; IF NOT, JUST EXIT NORMALLY.

3070001 ,RO

CBEQ

DIAGEX

%203 ,R0

CMPB #3085,R0
BEQ

nxnczx

S
BR

DIAGXX

DIAGEX:

YT
DIAGXX:
MOV
RTS

|
; SELF-TEST NULL. CODE.

; SELF-TEST SKIPPED CODE.
,

A_;[nflo'auuntnc'CODE.
|

+ ALL THE REST ARE ERROR CODES.

; AN ERROR CODE WAS RECEIVED, SO

; SET THE CARRY FLAG.

~; EVERYTHING OK, SO CLEAR CARRY.
T
L
(SP)+,RO
PC

o cuzcx FOR CHIP VERSION NUHBER

#200,R0

DIAGEX
#201,R0
DIAGEX

PRI

(SP),RO; GET THE CODE BACK.

BEG
CHPB
BEQ

CMPB

| FOR FAILLRE.

; RESTORE THE CHARACTER/INFO.
o

3-35

CHAPTER 4

TROUBLESHOOTING > |

41 SCOPE

This chapter explains how to isolate the cause of a communications problem between the DHQl l and |
the equrpment to which it 1s connected

42 PREVENTIVE MAINTENANCE
No preventive maintenance is needed for this option. However, you should always ensure that all cables o
are clear of danger, and that all the connectors are secure.

Make sure that all cables are clearly labelled, so that you can easily identify Wthh channel number andy

- which DHQI11 module are associated with each terminal.

4.3 TROUBLESHOOTING PROCEDURES
Troubleshooting procedures are to identify whether the problem iscaused by:

o The» module
e

A termrnal
The cabhng and dxstnbutxon panels

First decide whether the problemIs assoctated with one channel a group of four channels or all eight

\\"-‘V//

channels

If all channels are faulty, run the user dtagnosttcs to test the module Also check whether your software
B has a driver for the DHQll
__If a group of four channels are faulty, check the BCOSL-xx cable connected to the module ,For smgle—channel problems (EIA-232 D)
l.
- 2.

Check for loose cables and connectors
Venfy that the terrmnalIS workmg correctly If necessary, swap it w1th another one.

3 When a modem line 1s suspect check that the modem 1S correctly configured l'or modem
signals supported by the DHQIL. Also check that the software driver has the correct
baud-rate setting and that modem support is enabled for that lme

If the problem cannot be solved call DIGITAL Fteld Serwce

F or smgle-channel problems (DEC423)

. Check for loose cables and connectors.l

Verify that the terminal is working correctly. If necessary, swap it with another

one.

'Di5connect the BC16C-XX cable from the distribution panel, and connect it to .the H3tot

Type characters at the terminal connected to the suspect line. If characters are echoed back
when the H3101 is connected, the cables and terminal are working. If characters are not

loopback connector.

echoed back, the fault lies with the cable connection to the terminal. or with the terminal

itself.

| 6.

Rectify the cable or terminal fault. if there is one. If not. make sure that the user diagnostics
for the module run correctly.
|
R
ST

[f the problem cannot be solved. call DIG(TAL_Field Servicé.
l

|
|
|
l

H3101 LOOPBACK
CONN§CTO-R |

___—

———

H3104

BC16C-XX

TO TERMINALS

Figure 4-1

4.4 INTERNAL DIAGNOSTICS

-Tro’ubleshooting DEC423 Installations

)

Internal diagnostics run without intervention from the operator. There are two tests:
the self-test and the
background monitor program (BMP).
|
I
|

4.4.1

Self-Test

The self-test starts immediately after the Q-bus or module has been reset. [t performs
Internal logic test but does not test the Q-bus interface. The DIAG.FAIL

a comprehensive

bit and the "diagnostics passed’

LED on the module give an indication of asuccessful self-test. The self-test
also reports error or status
information to the host via the receive FIFO.
|
C
|
|
The self-test has completed successfully if the LED is ON 1.2 seconds
after the self-test has been
nitiated. The module is initiated by powerup
ing
the module. by resetting the module through the
program interface, or by a Q-bus initialization sequence. The
LED is turned off while the self-test
sequencer is executing; it will flicker during this time. The
duration of the OFF period depends on

whetheor
r not the self-test was invoked using the self-test skip feature of the

‘will not exceed 1.2 seconds.

program intertace. but it

Self-test provides a high level of confidence that the majonty of the module logxciS workmg The user

diagnostics must also be used to test the Q- bus mterface and verify that the switch settings on the module

~ switchpacks are correct.

4.4.2 BackgroundMonitor Program (BMP)

‘When the DHQI1 is not doing other tasks, ‘the BMP carries out tests on the module If an error is
-

detected, the BMP reports to the host vra the FIFO, and also switches OFF the dragnostxcs passed’
LED.

By writing codes to the line-parameter register, the host can cause the BMP to report the status of the

device, even if an error has not been detected. Thus facilityis used if the host suspects that the optton R

faulty.

NOTE

More information on the self-test and BMP
dlagnostlcs is glven in Chapter 3 of thns manual.
45

MlcroPDP-ll DIAGNOSTICS

4 5.1

User-Mode Dlagnostlcs
These tests can be used by an untrained operator to venfy the basic operatxon of the option. User-mode
tests do not cause any disruption to data networks or devices to which the DHQI1 may be connected.
Such networks and devices do not have to be disconnected from the DHQI! during the tests. The
MicroPDP-11 system manuals describe how to load and run these diagnostics.

4.5.1.1 Running User-Mode Tests
— All user--mode tests are run by selection from the test menu
dlsplayed when the user dxagnostlcs are booted. See Chapter 2 for more details.

A MicroPDP-11 Mamtenance K1t1S avarlable whxch allows trained personnel to run individual
' dlagnostlc programs under the XXDP + diagnostic monitor, and to configure and run DECX11 system
test programs. The XXDP+ functtonal dlagnostlc iS VHQA“'"‘ BIN, and the DECX1! module is
- XDHV**OB,

4.6 MicroVAX II DIAGNOSTICS

Diagnostics for MicroVAX II systems all run under the chroVAX Mamtenance System (MMS). The

MicroVAX II system manuals describe how to load the MMS into the MicroVAX II, and how to run

MMS diagnostics. All the tests can be run by selection from the test menus dlsplayed when MMSis
booted
|
|
|
46 1 User-Mode Tests ~
|
|
|
These tests can be used by an untrained operator to venfythe basic operatlon of the optton User- mode
|
tests do not cause any disruption to data networks or devices to which the DHQ!1 may be connected. Such networks and devices do not have to be disconnected from the DHQll durmg the tests. See
Chapter 2 for more detalls
|
|
.

4. 7

USING THE LOOPBACKS

4.7.1

H3277 Staggered Loopback Test Connector
|
|
The H3277is used during maintenance diagnostic tests on erther EIA-232D or DEC423 mstallatlons
.(see Frgure 4-2 and Frgure 4-3). It allows all channels to be tested

4.7.2

H3197 Line Loopback Test Connector

The H3197 is used during maintenance-mode diagnostic tests on EIA-232-D installations
(see Figure

'4-2) to trace a fault to a single channel. The older style H325 test connector provides the same signal
loopbacks as the H3179, and may be used in its place.
o
|

H3197

- DISTRIBUTION
PANELS
H3173-A

BCO5L-XX
CABLES

\———XTM MODEM |—Z—|

MODEM

::—_::gs:—_—_}ig"" NA";

Figure 42 Using Loopback Connectors in EIA-232-D Installations
4.7.3 H3101 Loopback Connector

' The H3101 loopback connector
(see Figure 4-3) is used during diagnostic tests for DEC423 installations.
It 1s two loopback connectors in one package, and consists of a female 36-way loopback connector
and a
male 36-way loopback connector. It can be connected either to the active bulkhead panel or to the 8-way o
~distribution panel. @@=
|
.
.
-

4.7.4
-

H3103 Loopback Connector

The H3103 loopback connector (see Figure 4-3) is used during maintenance diagnostic testing with
- DECA423 installations to test each line from the DHQI1 at the output from the H3104 cable

concentrator.

H3100

ACTIVE

|
-

POWER CONNECTOR

DISTRIBUTION

PANEL
H3101

BCOSL-XX

CABLES

- H3104

CABLE

CONCENTRATOR

’

o e—— Z$SM|NAL
38322

Fi1gure 4-3

4.8

Usmg Loopback Connectors in DEC423 Installatxons

MlcroPDP-ll SERVICE VIODE DIAGNOSTICS

4.8. 1
chroPDP-ll F uncnonal Diagnostic
The functional diagnostic for the MicroPDP-11 is VHQA"'* BIN This also tests other modulesin the
same family. for example the DHVI11.
After bootmg the program asks you four questlons about the hardware configuratlon These are

C SR address
| Vector address

~ Active line bitmap

Loopback type
~

The diagnostic will then 'size’ the option to determme modem or data leads-only. 8 or 16 lines, and then
print this information. The control chip and OCTART revrsxon levels are also printed. Always check
- that the unit ‘sizes’ correctly

- 4811 ,'Test Summaries - The.fouowing list summarizes the MicroPDP-.lil‘function diagnostic tests.

NOTE

These test numbers are only ngen as a gmde For
details of the tests for the revision you are using, see

‘the appropnate diagnostic hstmg

: " Reg15ter Address Test — Verifies that the Q bus can read and wnte to the unit under test.
‘MASTER RESET Test — Verifies that a master reset clears wnthm S seconds

_MASTER RESET (Skxp Self-Test) Test — Venfies that a master reset clearsIn approximately
20 ms when the sk1p—self—test sequence is used.

RX CHARACTER Fteld Test — Verifies that th.e data bits of the codesin the receive FIFO

after a master reset and skip-self-test are consistent w1th the sklp-self-test codes.

| RX FLAGF 1eld Test — Verifies that the three data status bits (overrun framing, and parity
error) are all set on each of the skip-self-test codes in the FIFO after a master-reset and

skip-self-test sequence.

RX DATA.AVAIL Test — Verifies that the RX.DATA. AVAIL bit
is set when the sklp-self-test
codes are in the FIF O, and that it clears after they have been read.

RX. DATA VALID Test — Verifies that the RX DATA. VALID b1tis set for all the codesin the
FIFO and clear after all the codes have been read

—RX. LINE Field Test — Venfies that the RX LINE lme fields are correct for the
slop-self-test codes

BMP Check Test — Venfies that the unit does not 1mmed1ately faxl the background monitor

program, as this may invalidate further tests

10.

Sk1p Self-Test Test — Verifies that the unit skips the self-testin the txme allowed and that the

FIFO contains the correct codes after its completlon

DIAGNOSTIC.FAIL Test — Verifies that, by usmg the skip-self-test sequence,

DIAG. FAIL bit sets and clears with the allowed tlmes
12

the

Self-Test Test — Verlfies that the unit’s self-test executes W1thm the correct txme and that the

correct codes are returnedin the FIFO after its completion.

13. Self-Test Fail Test — Venfies that the unit will report errors when it is forced to fatl by using
the special fail self-test sequence (decimal 146314 written to transmit buffer count register).

The DIAG FAIL bit sets, and at least one self-test faxlure code(231)is in the receive
14.

FIFO.

Chip Versmn Number — Verifies that the clup version numbers are reported correctly, and if

requested, prmts them out.
15, - Not used.

16. - Word Access Read/Wnte Test— Verlfies that the registers respond correctly to read and write
-accesses.

4-6

Word Access Read/Modtfnynte Test — Verifies that the registers will respond correctly to

18.

Byte Access Read/Wrtte Test — Vertfies that the registers will respond correctly to bvte
read/write accesses.

read/modify/write accesses.

)

Byte Access Read/Modxfy/Wnte —Venfies that the registers will respond correctlv to byte
read/modtfy/wnte accesses.

TX DATA Invaltd Test — Venfies that if a character is written to the transmtt character
register (TXCHAR) without TX. DATA VALID < 15 > set no TX. ACTION occurs.

. TX.DATA Valtd Test — Venfies that if a characteris written to the transmit character regxster '(TXCHAR) thh TX DATA. VALID< 15> set, a TX ACTION occurs.

TX. ENABLE (Inactwe) Test
— Venfies that when a line's TX. ENBL bitis clear, transmission
will not take place on that ltne

. TX. ENABLE (Actwe) Test —Venfies that when a llne s TX.ENBL bitis set, transmxssxon |
will take place on that line.

DMA START Test — Venfies that each DMA start btt wrll mttxate a DMA transmission on a
line.

: :DMA ABORT Test — Vertfies that each DMA abort blt will stop a DMA transmission,
return a TX. ACTION and successfully restart the DMA

DMA. ERROR Test — Venfies that the DMA error bit in the CSR reports DMA errors

correctly when they occur.

.. FIFO Data Test — Verifies that the FIFO wrll hold 256 characters w1thout corrupttng data,

and that the overrun set 1S clear.

O. AUTO Inactwe Test
— venfies that the unit will not respond to mcommg XON and XOFF

characters when 0. AUTO 1S clear

0. AUTO Actwe Test — Venfies that the unit. responds correctly to tncomtng fAow-control

| characters when acttve

- 30. L AUTO Inactxve Test — Venfies that the unit will not generate XON and XOF‘F charactersin
response to the appropnate FIFO condttxons when LAUTO is 1nact1ve

31 LAUTO Acttve Test — Vertfies that the unit will generate XON and XOFF characters in
response to the appropnate FIFO condmons when IAUTO IS active.

XON-XOFF
-

Ftltertng

Test

— Verifies that when

LPR<O>

DISABXRPT

and

LNCTRL <4> OAUTO are set, XON-XOF F characters are not placedin the receive silo.

Interrupt Test — Vertfies that the untt w1ll generate receptton and transmxssron 1nterrupts
correctly

4-7

34, ‘ Diagnostic Field (BMP) Test — Verifies that a requeSt to the unit to report BMP status codes
is complied with within the specified time. All active lines are tested.

- 35.

FIFO 3 /4 Level Inactive Test — Verifies that the 3/4 leVél alarm does not

the 3/4 level.
36.

become active belo_w
|

FIFO 3/4 Level Active Test — Verifies that the 3/4 level alann becorynes‘ actiVe

when th‘c FIFO

FIFO 3/4 Level Active/Inactive Test — Verifies that the 3/4 level alarm,

once activa‘te'd,

is 3/4 full.

remains active until the FIFO is reduced below the

38.

FIFO 1/2 Level Test — Verifies that the FIFO | /2 lével alarm
inactive at the correct levels.

39,

| /2 level.

system becomes active and

Break Generation Test( — Verifies that all serial transmit lines can generate
a break by setting

the BRK bit in the associate‘d. LNCTRL register.

No Overrun Error Test — Verifies that the unit under
test will not report data overrun errors
when they do not occur.
|
|
~

Overrun Error Test — Verifi’es that the unit will report data

41.

charac_ters are received.

oVerrun errors when 257

4. DTR Test — If ;"mode'rn' cohtfol available, verifies that changing the state
of the DTR
affects the state of the DTR control line.

43. -

RTS Test —If modem control available, verifies that‘ changing thestate

the state of the RTS control line.

DSR Test — If modem control available, verifies that the DSR status

the state
of the looped-back DTR control line.

state of the looped-back DTR control line.

CTS TeSt — If modem control a’Vailable, verifies that the CTS status

DCD Test — If modem control available, verifies that the DCD

47,

the state of the looped-back RTS contro

l line.

49,

bit

of the RTS bit affects

signal co‘rrectly_' reports |

the RI status signal cbrrectly reports the

the state of the looped-back RTS control line.
-

.signal_ correctly reports

status sngnal correctly reports

DTR IntetaCtions Test — If modem control available, vefifies that changing the

sta'te of the

RTS. Interactions Test
— If modem control available, _veri’fies that changing the

state of the

DTR control signal on any line does not affect the
state of any status signals that it is not
looped-back to.

RTS control signal on any line does not affect the
state of any status signals that it is not
looped-back to.
|
|
|
|
|

4-8

Transmit Line Test — Verifies that the transmit lines and receive lines are working correctly

through the device cables, distribution panel and loopback connectors. Executed only tf

external mode is selected

Transmit Lmes Interaction Test — Looks for any 1nteractton between ltnes Executed only if
.v
._
one of the external loopbacks is selected.
Receive Ttmer Test — Vertfies that the hold-off timer for receive mterrupts 1S operatmg

correctly, and that the 3'4-full level overrtdes the ttmer

53.

Not used.

54,

\lot used
DMA Address Test — Venfies that the umt can access the full memory Wthh Is on the |

56.
57.

machme via DMA access

Modem Loopback Test — If modem control avatlable allows the operator to test modem
links Wthh are attached to the unit senal ports

Keyboard‘ ‘Echo Test
— Allows the operator to test terminal links (or other communications

’links) which are attached to unit serial ports. from remote ends of the links.

Smgle Character Test — Venfies that the unit W1ll transmlt and receive correctly usmg".

non-DMA mode at varous lme parameters

59. | DMA Mode Test — Vertfies that the unlt W1ll transmit and receive correctly usmg DMA at
| ‘vanous lme parameters
—
-

| Framtng Error Test— Venfies that forced t‘rammg errors are reported correctly H37‘77'
staggered loopback only

Panty Error Test — Ve rtfies that forced parxty errors are reported correctly H3277 Staggered'v
loopback only

- Split Speed Test — Vertfies that the unit wxll functlon correctly using different transmtt and
»recexve speeds on each active line. H3’77 starzgered loopback only

63.

Report BMP Codes Test — This pseudo test reports the first 32 characters which were

discoveredin the FIFO during the execution of the other tests. This avoids interruption of the
other tests by these codes 1if they are not cnttcal to the pert‘ormance of the tests.

482 DECXII Object Module

TheDHQll Object Module is the same as for the DHVll XDHV*"' OBJ
NOTE

Early versions of this module DO NOT support the
DHQll

The mimmurn parameters wiiich mi.ist. be specified are:
L

DVA (Device Address)

2. VCT (Vector,Address)

DVC (Device Count), if more than one.

The default operating mode is with all lines leoped back in‘}temally. at 9600 baud. o

49 MicroVAX II SERVICE-MODE DIA_GNOSTICS

The DHQ!1 uses the same diagnostic module as for the DVHVI 1, NADHA*.

49.1 C‘onfiguratioii Tests

I -

The module is ‘sized’ to check the number of lines (8 or 16), and whether it supports modems or is
data-leads-only. This information, together with the control chip and OCTART revision levels, is added

to the system configuration file.

4.9.2 Field Service Functional Tests
;
|
|
|
Before the diagnostic runs a field service test, the set-up procedure for the DHQI1 diagnostic is

executed. You will be prompted to attach any loopback connectors or cables (for instance, bulkhead
loopback connectors). On pressing the RETURN Kkey, all ports are sized
to see to which ports (on the
‘same controller) the loopbacks are attached. This information
is then displayed, and the field service
tests are started. This set-up procedure is run only once after configuration of the diagnostic system.

- There are 10 tests. Numbers 1 to 5 are verify-mode tests, numbers 6 to 10 are service-mode tests.

'TEST 1:

TEST 2:
-

In this test, the DHQII is initialized anda’ddressa*bility checks are made on ifarious .

registers.

Uses loopback connectors and cables sized during the setup procedure to send single
characters
in programmed output mode over port 0; using baud rates of 300, 1200, 9600
and 38.4k bauds; and with various data lengths, stop bit sizes, and parity options. It should
be noted that, due to execution time constraints, this is the only test, other than the utilities,

- which exercises the entire range of character options.

TEST 3: Performs extensive DMA testing through loopback connectors and cables sized during-the
setup procedure, using different buffer sizes. All ports are tested simultaneously at 19.2

kbytes/s. FIFO overrun and DMA abort are tested. In addition, if a port is determined to
be connected to a port other
than itself, a more thorough test of outgoing data flow-control
is performed.
o
R
|

TEST 4:
D

This test uses loopback connectors and cables sized duriiig the_setup procedure to perform
extensive flow-control testing. OAUTO, IAUTO, and FORCE.XOFF functions are

exercised. The break signal function is also tested.

TEST S:

Test 6:
~

)

This test exercises the modem control signals for each of the connected channels that were

determined to be looped back during the setup procedure. This ensures that the
- corresponding input signals are valid and that the DHQI 1 may be configured to interrupt
‘when a modem control signal is asserted.
|

This is the same as test 1, except that,vtesting occurs through -cables and loopback
connectors sized during the setup procedure with baud rates of 300, 1200,
9600, and 38.4K.

4-10

This 1s the same as test 2. except that testing occurs through the cables and loopback

Test 7.

connectors.

This 1s the same as test 3 except that testing occurs throuszh the cables and loopback-i’

Test 8:

connectors.

| This test exercises the modem control signals for each port. ensuring that the DHQI | may

Test 9:

be confiqured to mterrupt on the transition of a modem signal.

Test 10:

This is the same as test 5 except that testmg occurs throueh the cables and loopback

~connectors.

4.9.3 Field Service Exerciser Tests

The exerciser test is designed to stress the svstem by snmulatmz normal svstem operation This 1S
|

achieved by exercisingseveral dewces sxmultaneously

Test 1 is a combination of the verify-mode tests.
Test 2 is a combination of the verify- and service-mode tests.

These tests are run at [9.2 kbytes only. using cables and loopback connectors found during set-up.
Utilities

4.9.4

The three utihties provide simple routmes to:

Run echo tests and termmal tests on specific lines.

® Locate cable faults. using the loopbacf( connectors to loop data back to the module

Checkthata terrninal. or Vremote equipment, is correctly transmitting and receiving characters

Utility 1

This utxhty permits >taged testing of the DHQI | and associated cables/connectors The

diagnostic request> configuration parameters from the operator, and then repeatedly
tests the port(s) for data loopback mtegnty The operator may, by strategically placing
loopback connectors at various points in the communications path. isolate defective -

units. The operator is not prompted as to where to place the 1oopback connectors. nor

~ does the diagnostic interpret the results of the tests.
Culity 2

This utility permits testmg of remote communications devices. The diagnostic puts all
~ports into remote loopback maintenance mode. All characters sent to any port will be
echoed back to the sender. at baud rates up to 9600 baud. No operator configurationis
necessary. Because of inherent DHQ!| bufi'ennz limitations characters may be lost if

transmitted too rapidly by the terminal.

Utility 3

This utility sends test stnngs to the port(s) specxfied bv the operator to aid diagnoses of

remote communications devices. The operator may choose any baud rate or character'
specifics. The port under test is confizured thh auto-flow control for outgome
characters

411

4 10

FIELD-REPLACEABLE UVITS (FRUS)

The FRUs are:

C -

Reference No.

Dual-height DHQI1 module

M3107 SR

40 conductor
Flat cable.

BCOSLxx

" For EIA 232-D Installanonsdnobold

H3173-A

For DEC423 Installations

Distribution'panel

Active distribution panel

H3l0

~ Multiway cable

BC16C-25
'H3104

Item

70-22775-XX

Cable concentrator

Power cable

a12

CELAPTTI!S*
TECHN ICAL DESCRIPTION

‘51

scopa

This chapter gives a technical descnptxon of the DHQl 1 asynchronous multxplexer Flgure 5-1 shows a

block diagram of the DHQI
L. and each block identifiedin the diagram is described in this chapter.

While readmg this chapter you may find it useful to have access to a DHQI1 pnntset (part number
MP-02380).

OVERVIEW

o Flgure 5- l shows a block diagram of the DHQll It can be broken down into the following sections:
RAM— stores control information and provxdes the data bufi’ers
OCTART — contams eight asynchronous recexver/transnntters baud- rate generators and
vrnterface logic
|
|
.
Control Chip—contaxns sequencers and other logic to xmplement all the functrons of the
DHQ!1 outside of the OCTART

watchpack and Shift Regxster Sectxon — defines the devrce address and vector and the rnode

of operatxon

) Q-bus Dnvers and Recewers — provrde the electrlcal mterface to the Q-bus
| Modem Latches — latches the RTS and DTR rnodem control signals
.~

Lme Interface — converts srgnals to and from line levels

B Power Converter — provrdes posmve and negauve lO \% supplxes for the lme mterface
Each ol' these blocks is descrrbed In more detaxlin Sectxon 5 3. Sectxon S 4 descnbes the flow of data
. through the rnodule

N|EIESRTEI SRN8-0 |(swa;)|< JH1vHnV)N}S—O| aSwIHIAIVT(>Y0S1QA<700

,10HINODSizw.h.m" -—:.”_u.zm_bw“m|wm1(>wmal<o
undy1-G (1IOHA Jo ig wesdeid

(Svn)A1+ |O |D HHIIM1HOIdANOD __ .N --

O.(OSNNHY8IVA-M0vAiOv( TOH1IHWNIvOWHDISS-LHldHN1HSaIiSIL1wyIHVa|S11N)I|)4IIHHwNDIIMADLYS~NIINVSMISN|D~IS.-1o_y.a¥Yv3NIa.,ANI__NO|D)ISi;J_ri(Wgvo|u._Ywvy1H)_OIVH1g8Yc|LTS,O¥_4HIv>|3HnIA|NOQ3DYI|NLvD3ISV—1 s1||)a~1 mvooia‘v_a 1)30W1Y31(Iya4Nm,o1ow0|<ST(o00Ls(>0>v—lS|y<H0
WvH

RSN

ana

'S1)
'R

ysa S-1Y yia)

3IV4HILNI INIT

SNg-0

5-2

5.3 DHQll FL\JCTIONAL BLOCKS
L

RAM

5.3.1

- Figure 5-2 shows the way in which the RAMis assxgned to the various functxons Two kbyte of RAMis
used Wthh 1S dmded into three main sectxons

[

The top l kbyte contains the 64-character transmit F IFOs one per channel The DHQll uses

The next 5 12 bytes contain the 256-word receive FIFO. The low byte of each word containsa

received character. and the high byte contains status information. such as channel number

and error status

®
5.3.2

only eight channeis and the rest of this area is unused.

The bottom Jl’ bytes contain the 32-byte control register areas, one per channel. These

reg1sters control the data flow through the DHQI 1 using the sequencers In the control chip.

OCTART

’

The OCTART contains 8 asvnchronous receiver;transrmtters a l6-output baud-rate generator, and
interface logic. The UARTSs are compatible from a serial-line vxewpomt with thosein the 2681 DUART.

Each channel has only a single buffer on both transmit and receive. The UART fast sequencer on the

~ control chip (see Section 5.3. 3 6). together with the RAM, provides double buffering for the transmitters
and a 4-word-per-line FIFO for each receiver, thus completing compatibility with the 2681 DUART.

5-3

)< r|l.lnlllllnl———w_o—t.ozoeE|Oem‘]——l——sm—.eo:ogt|lllll

|W3gSsminmm| YMIAIE)YI _ andv0i4y34g0¢-_S|WY.Jouo9w5u7d43i9s0sy INHYT

g|e |NILTHoI - |I oKamwTves|- lAllz.flN oMV _n_u..faimw_u..oL|- |— |] = sv|b n -l l l l lol
_

sSng-0

—.

]

y
‘\

CONTROL-CHIP
INTERFACE

|
.

o e 4

RECEIVER REAQY

. INTL | SCANNER

| TRANSMITTER READY

WAL

|BiGHT
,

]

ARQUND

CONTROL |
|

SERIAL

- OUT>

REGISTERS

ATAOUT

(0 TO 7)

|8auUD RATE.

SYSTEM

rimer

—

DATAIN

"N{QTO 7

SIGNALS

LOQP-

INDEX

EIGHT

RPN

‘LC LB|LA

R
o

ASERIAL

- RECEIVERS

SR
,

IC|18 | 1A

~ <1

| MQDEM

:— 1

K CHANNEL?

STATUS LINE
MULTIPLEXER

'psR

Ag32ed

" Figure 5-3 OCTART

n for the
5.3.2.1 Control_-Chip Interface - This manages two Séparate’ 's_oui_'ces of informatio
L
|
.
OCTARTS: they are:

®
®

together with | the
bits L<C:A>. s
Receiver/Transmitter-Ready Scanner Register
|
,
»

- receiver-ready bit

Index Register bits [<C:A>.

" The scanner logic scans each channel in turn until it locates a channel needing servicing. It then asserts
the interrupt line to the control chip. A channel is ready for servicing when either it is free to accept a
character for transmission. or a character has been received, as indicated by the receiver ready bit.

5-5

Dunng the serv1cxng of this 1nterrupt by the control Chlp, the L < C A> bits tell the control Chlp which
channel has interrupted. If it is a receive interrupt, the received characteris presented on the
D<7:0>
lines. If it is a transmit interrupt, the control chip will either present a character on D<7:0>, or
performs a dummy transfer, which has the effect of temporarily disabling transmit interrupts from that
channel. Note that the receivers are glven pnonty over transnutters
Reglster bltS I<C:A> select one of etght channels during a reglster access. Address lmes A< 1:0>
“select one of four registers associated w1th that channel.

- 5.3.2.2

Lme-Parameter Register — Each ltne has its own line-parameter register denved from the

| Q bus-acce531ble LPR and LNCTRL reglsters

5323 Modem-Status Mulnplexer ThlS presents to the control-chxp mterface the four modem
control inputs for the channel bexng addressed by I<C A> when the control ch1p reads the

| modem-status register. .

5.3.2.4

Loop-Around Control This implements the functions of the maintenance rnode bits (see

B Section 3.2.2.6)

5.3.2.5 Baud-Rate Generator - Thts provxdes 16 1ndependent baud rates for transmit and receive.

Transmitter baud rates are 1ndependent from the recexve rates, and thereis no mterdependency between
channels

5.3.3 Control Clnp
|
|
‘The control chip contains all the necessary logic and sequencers to control the operatlon of the DHQl
1.
The functions of this IC can be broken down into eight blocks:
| o

Timer and RAM Test Sequencer ('I'I'R) -

| @

Q-bus Interface (QIF)

| K " ‘DMA" Slow Sequencer (DM.'S) |

DMA Fast Sequencer (DMF)

Data l/O Sequencer (DIO)

UART Fast Sequencer (UAF)

UART Slow Sequencer '(UAS)

RAM Arbitrator (RARB).

53.3.1 Tlmer And RAM Test Sequencer (TTR) - Thxs sequencer controls the power-up sequence of |

the rnodule On power-up, the TTR

@ Resets the OCTART
®

Resets the modem latches

Clocks the switchpack settings into the control chip. RAM address lines are used to select the

shift register operation. and RWR.L (RAM write) is used to clock the shift register (see

Tests the RAM (which takes 26 ms) and leaves it In a defined state Wthh reflects the power-up
state descnbed m Sectron 3.3.1.

Section 5.3.4 for more information)

T he sequencer- also .ge.nerates mternal txrmng ’signalsv for the control chip.

5.3.3.2 Q-bus Inte-rfa‘ce (QIF) - This block contains the logic to handle data [/O and interrup.t |

- operations. and also DMA operations thrOugh its DMF sequencer, described in Section 5.3.3.3.
The QIF also 1ncludes other functlons such as:

'A specxal data out handler 50 that the Q bus1S glven a fast response time wnhout havmg to

- Walt for RAM access

Loglc to handle mterrupt request generatton and vector assertion (usmg data read from the |
| sw:tches at power up)
|

Some device regtster btts are also implemented
in this block, such as:

)

Indirect addr’ess register pointers

Interrupt enable b1ts |

5.3. 3 3 DMA Fast Sequencer (DMF) DMAoperatlons are controlled by a combination of the

DMF (DMA-Fast) sequencer descnbed here and the DMS (DMA Slow) sequencer (descnbed m
_Sectlon 5.3. 3 4).
|
|

The functlon of the DMF sequencer is to become Q- bus master and then acquire characters from the |
Q-bus at maximum Q-bus speeds At an average rate of 1 word every 850 ns in block-mode DMA., the

DMF acquires up to 8 words (16 characters) duringits bus mastership. In non-block operations, up to 4

words are acquired while it is bus master. These characters are transferred to the transmit FIFO under

the control of the DMS sequencer The DMF sequencer operates as a slave to the DMS sequencer

5. 3 3.4

DMA Slow Sequencer (DMS) - Thxs sequencer has three mdependent functxons

To scan the channels unttl 1t detects the need for a DMA operatron

| o"

To handle a DMA transfer by controlhng the DMF sequencer

To handle an ABORT request

To report a TX ACTION at the end of a DMA operatron (thlS includes successful operatlons |

aborted operations, and operatrons terminated after a bus error)

5.3.3.5 Datal/O Sequencer (DIO) - Thls sequencer waits in an tdle loop untrl srgnals from the Q bus
(through the QIF ) cause it to perforrn one of the Q bus data I/O operatlons — DATI DATO(B)
and

DATIO(B)

This sequencer also detects operations on certain registers and takes appropriate action. For example,

after a write operation to an LPR or LNCTRL register, it sets a bit in the RAM control
area for that
channel to indicate to the UAS sequencer that the contents may have changed.

'53.3.6 UART Fast Sequencer (UAF) ~ This sequencer handles interrupts from the OCTART. When
an interrupt
is received, the UAF reads the OCTART status register to find the channel number,

ascertain whether it is a receive or transmit interrupt.

and to

For a transmit interrupt, having checked that there is a character ready to transmit, the UAF transfers

the character directly from the RAM to the OCTART. For a receive interrupt, the UAF transfers
the
character directly from the OCTART to the top of the 4-word FIFO in RAM (low byte). Then the
error

status, which had previously been read from the OCTART status register, is written

byte).

to the FIFO (high

5.3.3.7 "UART Slow Sequencer (UAS) - This seqaencer scans
all 8 channels ('in' 160 us, to guarantee
operation on all channels at maximum possible data rates). For each channel, the

UAS:

Moves received characters from the bottom of the 4-word FIFO in RAM into the 256-word |
shared receive FIFO. It also handles received XON/XOFF

control characters.

Implements one of the following six actions (listed} in priOrity order) before repeating step 1

for the next channel: Modem service — it checks modem status every 10 ms -

@
~

Line-Parameter Register writ“ten check — it checks Whether ‘this register has been
changed by the DIO sequencer

Line-Parameter Register change
— if during the last pass it detected that this register

had been changed, it now updates the OCTART registers with the new informatio
n

e BMP Report — genera'tes-va BackgIOund Mom‘tor Program report
® Transmitsa sin_:gle eharacter from the TXCHAR register, or transmits an XON or XOFF
, eharacter

Transmits from the transmit FIFO'} |

The UAS block also includes:
®

RBUF FIFO control

‘

| ’, e TXACTION FIFO contrpl '
®

Background Monitor Prograrn (BMP) logic.

5338 RAM Arbitrator (RARB) - "‘ll'his arbitrates between the five RAM access sequencers described

in sections 5.3.3.1 and 5.3.3.4 to 5.3.3.7, giving one of them ‘3¢cess to the
RAM/OCTART data bus,
depending on the priority scheme described here.

The TTR sequencer has the top priOrity, so that it gets 100% RAM access for the first 26 ms
power-up. This guarantees that the RAM will be powered-up to an operationa

sequencer can begin. After 26 ms this sequencer idles.

5-8

after

l state before any other

H /
N,

‘Although it cannot gain access to RAM during the 26 ms power-up time, the DIO sequencer still

operates. This is needed for CSR access and skip-self-test operations from the Q-bus (see Section
|
132.2.0).

To ensure that the progress of each sequencer is predictable, RAM access is alternated between the two

'UART sequencers (UAF and UAS) and the two CPU sequencers (DIO

and DMS). During "CPU-time’,

~ only CPU sequencers are granted access. During "'UART-time’, UART sequencers have priority, but if
neither UART sequencer requires access, a CPU sequencer can steal the cycle. The overall effect of this
i1s that:
~
~

The UART sequencers progress at a predictable rate. This guarantees service to each channel
at a rate fast enough to maintain maximum throughput, while still allowing a required
minimum time between OCTART write operations
SR
|
.

Access ,byA the CPU sequencers is;'maximized(and h_enc'e‘-Q-bus BRPLY delay times

~minimized) by allowing them RAM access during unused UART cycles. along with normal

CPU cycles.

In "UART-time', the UAF has priority over the UAS to make sure all data transfers to and from the

OCTART are done as quickly as possible. Of the CPU sequencers, the DIO has priority over the DMS
to guarantee minimum delay in asserung BRPLY.
|
|
|

5.3.4 Switchpack And Shift Registers
e
e
e
s
The TTR sequencer shifts-in the contents
of the shift registers after the module has been reset (by BINIT
or MASTER.RESET). Since the switchpack contents are only examined atthis time, the module
must
be reset (BINIT or MASTER.RESET) in order to set new values.
|
|

£t The TTR 'Sequéncer in the control chip has been designed for use in several different applications and
therefore needs
to determine whether the module has 8 or 16 channels, and whether it is a Q-bus

- UNIBUS application (the DHQI1 isset up for 8 channels on Q-bus). Figure 5-4 shows a simplified
diagram of the switchpack and shift register logic, which can be used with the following

5-9

explanation.

{

VCC

E36
S
AD10 >—

- ADO1
1

NOT

BHYL
—

SHFT LD
—D7

CLR]suprH
SERIAL INPUT
Q———= TO CONTROL

105

b4 SHIFT

D3 REGISTER
D2 E37

—01

___ADOO

]}

]

| _sasL
L | | [SHFF
D
[SHFTLC

C,R]

NOT

CONNECTED

~05

4 SHIFT

1D3 REGISTER
02 E29

—D1
|
~
~

SWITCHPACK
PART OF E28

RWR

{00
L

__SERI

d—

SLOOP.L

GND

RE2714

Figure 5-4

Switchpack and Shift Register Logic

- First, the switch settings connected to the D<7:0> inputs of the shift registers are
synchronously
loaded into the shift registers. This is done by holding AD00 and ADO1 low while pulsing
RWR.L. The
switch settings are clocked into the shift registers by the trailing edge of RWR.L. AD09 and
AD10 are
held low during this first operation to ensure that the respective D7 settings (DHV.L and
SAS.L) are
loaded in the same way as all the other switches. On DHQI11, the switch generating DHV.L
is held
electrically closed by jumper W1, which locks the module in the DHV11 mode
of ‘operation.

After thxs load the first bit (D7 of shxft regxster E20)is present at the SHFT. H input to the control Chlp

“and is latched internally by the TTR sequencer. Then 16 RWR.L pulses are applied with AD00 and
ADO1 high (this selects the shift function). The remaining bitsin the shift register are thus clocked into °
‘the control chip and latched bythe TTR, including the last shifted-in setting (SERI input) to the E12
|
|
shift-register (SLOOP L). making a tOtal of 17 bltS
Two further settmgs need to be determmed.

Whether the devivcesu_pp'orts' 8 lines (as doesflDHQl 1)’ or 16 lines

'Whether,the device operates ,o.n the Q-bus (as d()es DHQ!) or on the UNIBUS.

After the 17‘ switch settings have been latched, the control chip sets AD09 and AD10 high. It then selects

the load function (ADOO and ADO1 low) and pulses RWR.L. Because of the high level on ADO0S and
ADI10, a high level is latched into D7 of both shift registers, regardless of the switch setting.

The control chip now tries to clear these two bltS If the dewce supports 16 lines. ADOSis connected to
-

the CLR input of E20. If the device operates on the UNIBUS, ADO2is connected to the CLR input of
E12. The control chip therefore pulses ADO02 and ADOS8 low to try and clear the registers. On the
- DHQI!1 neither of these connections is made (both CLR inputs are simply pulled high); therefore the
~ registers do not clear. The control chip can now test the state of the SHFT.H line and determine (since
'SHFT.H is high) that the DHQI1 has eight lines. After applying eight RWR.L pulses, a second test of
the SHFT.H line shows that the DHQH operates on Q-bus (SHFT H 1S agam hxgh)
B

5.3.5

Q-bus Drivers And Receivers

Six DC021 Q-bus driver/receiver chips are used. EIO1S w1red for receive only and E2 for transmit only »

- The direction (transmit or receive) of the other four (El, E9, E17. E22)is controlled by signals from the

control chip. To avoid bus contention, the change of state of the signals from the control chip from

tri-state to active is carefully timed before and after changing the direction. In addition, E1 and E9 are

disabled by EN1.L and EN2.L while changing the direction. This avoids the possibility of accxdentally
assertmg control signals such as BSYNC.L or BRPLY L on the Q bus while changmg direction.
5.3.6

Modem Latches

- Two 8-bit addressable latches are used to latch the modem control 51gnals When the control chip wants )
-

to write the modem control signals (RTS and DTR) it selects the appropriate channel using address lines
AD<7:5> (see Figure 5-5). At the same time, AD04 writes the value for RTS.L, and ADO3 writes the
value for DTR.L, to their respective addressable latches. The control chip then asserts MDL to latch

these two values. The RTS. L and DTR L 51gnals are wntten active low as they are mverted by the ine
|
|
|

drwers

RTS.L - CHANNEL 7

| ADO4 >
Q5

9—G

MDL >

gair

ADDRESSABLE

LATCH

E15

Q4r

—
_

I
I
|

|
|

|
|
|
|
I
|
|

—~

Qi1

- QOf—

- RTS.L - CHANNEL O

DTR.L - CHANNEL 7
|

ADO3 >—

Q6 —

I
|
.
|

96 gair
|

ADDRESSABLE
LATCH

E14

ADQ7 >

ADOE >—

ADOS >—

-1

|
|

o
|
I
|
|
I

- DTR.L - CHANNEL O

Ag3248

Figure 5-5

Modem Latches

5-12

5.3.7

Line Interfaces

’

The interface to the serial linesis provxded by five octal hne recetver chxps (type 51 80) and three octal line
driver chips (type 5170). These are inverting buffers which convert between line levels at the J1 and ]2

connectors and TTL levels at the OCTART and modem latches.
" S, 3 8

Power Converter

The line drivers require + and -10 volts dc. The Q- bus backplane supplies only + l" volts dc A nommali

+ 10 volts is generated by dropping down the + 12 volts across two diodes. The —10 voltsis derived from
+ 12 volts by a voltage converter. This device uses switched-mode power-supply techniques to generate

‘the negative voltage. The circuit is built around a TL494 switching regulator (see Figure 5-5). This uses

| pulse-width modulation to regulate the -10 volt output

Sw1tch1na—pulses from the modulator swrtch a tran51stor (Ql) to convert a dc mput to a pulsed dc

current in an inductor. When Q! is switched on. point X becomes positive. causing current to flow

through L. Duringthis period. energy is storedin the inductor. When Q1 is switched off. the polarity of

~ the voltage across the inductoris inverted. and the energy storedin the inductoris transferred through
the now forward biased diode to the smoothing capacitors. As current is transferred to the output. the voltage at X rises until the diodeis cut off azam The circuit wxll stav in this state unul the next switching

pulse turns Ql on.

| :

The inset of szure 5- 6 shows tvprcal mductor current waveforms With QI sw1tched on. current rises

linearly until Ql is switched off again. With QI switched off, the collapsing field in the inductor
“maintains current flow, which reduces linearly as it is transferred to the output. The wider the sthchmg
pulses, the more power that 1s transferred to the output

Feedback from the output is compared w1th a reference. If the output is too hrgh the pulse width is
reduced; if too low, the pulse width is increased. This feedback action maintains output voltage

regulation for varying loads. This same method of comparison is used to implement over-current

protection. The inductor current is sensed across Rc. If this exceeds a preset limit, the sw1tch1ng pulse

widthis reduced. The switching {requency (60 kHz)1S selected by Rs and Cs If the oscxllatorIS workmg,,
a sawtooth waveform can be seen at pm 5.

5-13

N |

-12vV
Jvour

| SWITCHING
tPuLSES

vee
D

m
=

A <

—J14 !
~

1168

PULSE-WIDTH

MODULATOR

/REGULATOR

VAR

[SMOOTHING

|CAPACITOR

|
OVER

CumRENT

FEEDBACK

)

- Figure 5-6 Vclt;age'Convert,er

5-14

. POWER TRAI\;SFERRED ro orp

S. 4 DATA FLOW
'
o
This section descnbes the general flow of data throuzh the DHQI!! between the Q-bus and the sertal

| lmes for both the receive and the transmxt operauons
5.4. 1

Data Flow For Character Recepnon

‘Data is clocked into the OCTART in serial form. Whenr—the OCTART has completed the

serial-to-parallel conversion, it generates an tnterrupt (LINT.L) to the control chip (see Figure 5-7). The
UAF sequencer quickly transfers the data into the four-word FIFO for the appropriate channel in
RAM, and sets a receive-data-available flag. The UAS sequencer sees this flag and processes the
character by moving it. together with the channel number and error mformatton to the top of the
’56-word shared receive FIFO.

The CPU accesses the bottom of the receive FIFO by readmg the RBUF regxster This transfer 1S
~handled by the DIO sequencer.

s. 4 2

'54.2.1

Data Flow F or Character Transmrssmn

DMA Operatlon - The CPU starts a DMA operatton by writing the start address for the

channel into TBUFFAD! and TBUFFAD2. writing the number of characters to be transmitted into

TBUFFCNT. and then setting the DMA.START bit. The DMS sequencer detects DMA.START being
set. and begins the DMA transfer to the appropriate transmit FIFO with the aid of the DMF sequencer. ,‘
The UAS sequencer reads the status of that channel's transmit FIFO, removes the character (assuming

- thereis one) from the bottom of the FIFO. places it in the Transmit Holding Register (THR). and sets
the transmit-character-available flag for the channel The THR1s contamedin RAM as anelement of
the control regtster area.

The OCTART mterrupts the control chlp when it is able to handle a transmit character. The UAF
sequencer reads the transmit-character-available flag and, if it is-set, transfers the character from the
THR to the OCTART The OCTART converts it to serlal format and transmxts it to the hne dnvers

5.4.2. 2 Programmed I/O Operation - The host writes a smgle character to the TXCHAR reglster and
sets the TX.VALID bit. Characters to be transmitted are handled by the DIO sequencer. The UAS

- sequencer removes this character trom the TXCHAR register, places it in the THR, clears the TVD bit.

~and sets TX.ACTION. Transfer to the sertal line then contmues as descnbed above for DMA transfers

Subsequent TXCHAR transfers must only be tnmated after the TX ACTION has been set for the

| prevxous transfer

5-15.

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APPENDIX A

' MODEM CONTROL

A.l SCOPE.
[t defines contrz_ol |
ammef and the engineer.k faults.
tion useful to bdth the prc)gr
‘This appendix contains informa
A detailed
networ
likely
modem control methods, and warns against
signals. describes typical

~ example of auto-answer operation is included.

A2 MODEM CONTROL

d
full-duplex operation over the public switche
The DHQ! 1 supports sufficient modem control to permit
ted
suppor
leads
control
the
lists
A-1
one lines. Table
telephone network (PSTN) and over private teleph
use and purpose. In this appendix, the terms
their
of
tion
explana
an
with
r
togethe
.
DHQI1
the
by
to the device which is used to modulate and
refer
They
g.
modem and dataset have the same meanin
|
demodulate the signals transmitted over the communications circuits.

Name

| GND

Definition

EIA-232-D V.24 "~ 25Pin

line interface.

- 'R,XD'

104

Cc1s
|

CB o

contains the serial bit stream 1o ‘be
transmitted to the remote station.

106

e e

From modem to DHQI!. This signal is

the serial bit stream received by the

~ modem from the remote station.

! to modem. Causes ,the'f'"
~ Fromm’sDHQI
carrier to be placed on the line.

4 |

RTS | ¢cA | 105

From DHQI! to modem. This signal

ce level '
a referen
. This is signals
Ground
~ Signal
7 for
at the
used
control
and
data
the

| 102

mode
|
.' Indicates that |
5 o - From modem to DHQ’lll
successfully placed 1its
|

the modem has

carrier on the line. and that data presented
d the
on circuit BA will be transmitteto
communication channel.

DSR
-

cc
IR
|

6
-~

-~ From modem to DHQI! L. Indicates that
S the modem has completed all call
functions
establishmentsuccessfully connected
communications channel.

A} l

and
to

1S
a
B

" Table A-T 'Mo,dem Contri)l Leads (Cont.)v |

Name

EIA-22-D

DTR

V.24

25-Pin

1082

Definition

From DHQI! to modem. Indicates to the

modem that the DHQI1 is powered up

and ready to answer an incoming call.

DCD

109
.

From modem to DHQll. Indicates to the

DHQI11 that the remote station’s carrier

signal has been detected and is within

appropriate limits.

\ CE

o 125

From modem to DHQl-l'.VI‘ndicates thata

- new incoming call is being received by the

‘modem.

The DHQI1! modem control interface ca_n be used in many applications. These include control of serial
line printers, terminal cluster controllers, and industrial
I/O equipment, in addition to the more usual

- applications
in telephone networks. The use of the control leads described in Table A-1 is therefore
- completely dependent on the application, although there are international standards which telephone
network applications should obey. There are no hardware interlocks between the modem control logic
- and the transmitter and receiver logic. Program control manages these actions, as necessary.

A subset of the leads listed in Table A-1 could be used to establish a communications link using modems

connected to the switched telephone network. Ring Indicator (RI), Data Terminal Ready (DTR), and
Data Carrier Detected (DCD) are the absolute minimum requirements. In some countries Dataset

Ready (DSR) is also needed. It is usually desirable, however,
to implement modem control protocols

which will operate overmost telephone systems in the world. Also, some protection should be included

-to guard against network faults, particularly in applications such as dial-up timesharing systems. Such

| faults include:

'@
N

—

Making a channel permanently busy (hung) because of a misdialed connection from a

non-data station

C’onnectinga' new incoming call on an in-use channel. This fault might occur, for example,

after a temporary carrier loss, if the host system assumed that the carrier was reasserted bythe |
original caller.
|

Modem control with some protection against common faults, and which is compatible with the

telephone networks in most geographic areas, can
be implemented by using all the signals listed in Table

- A-l, in the way described by the CCITT V.24 recommendations. Section A.2.1 describes a method of

implementing a full-duplex auto-answer communications link through modems over the PSTN. It is
provided here only to show the operation and interaction of DHQI1 modem control leads in a typical

- application.

A.2.1 Example Of Auto-Answer Modem Control For The PSTN

The system operator determines which DHQI1 1 channels should be configured for either local or remote
operation. Local operation implies control of data-leads-only, while remote operation implies that

modem control will be supported. The host software will assert DTR and RTS together with the
- LINK.TYPE bit in the LNCTRL register for all DHQI1 channels configured for remote operation.
- DTR informs the modem that the DHQI11 is powered up and ready to acknowledge control signals from

to place iis N
th_é modem. RTS is asserted »for'the full-duplex rnode of operation. and 'ca‘usés the modem <8>)
enables

carrier on the telephone line when the modem answers a call. Link Type (LNCTRL
modem status information to be placed in the receive character FIFO. where it will be handled by an
interrupt service routine. Modem status changes are always reported in the STAT register regardless of
the state of LNCTRL <8>. The modem is now prepared to auto-answer an incoming call.

at the line interface. This informs the DHQl | that
Dialing the modem'’s number causes RI to be asserted

" a new call is being received. RI has to be in a stable state for at least 30 ms. or the change will not be
reported by the DHQ!1. Since DTR is already asserted. the modem will auto-answer the incoming call -~
and start its handshaking sequence with the calling station. The time needed to complete the
handshaking sequence can be in the order of tens of seconds if fallback-mode speed selection and
to indicate to the DHQI1! that the call has been
satellite links are involved. The modem will assert DSR
successfully answered and a connection established.

NOTE

On some older types of modem used on the PSTN,
the opposite effect is also true. The RI signal may be
very short, or it may not even occur if DTR was
~ previously asserted. When this type of modem
answers an incoming call, it asserts DSR almost
immediately and deasserts RI at the line interface.

- Programs must therefore expect RI or DSR or DCD

_as the first dataset status change received from the

modem when establishing a connection.

As RTS was previously asserted, the modem'’s carrier will be placed on the line when DSR is asserted.
When the modem has successfully placed its carrier on the line it will assert CTS. This indicates to the
DHQI!1 that it can start to transmit data. If the incoming call is the result of a misdialed number, a
carrier signal may never be received. To guard against this, the host startsa timer when it detects Rl or
DSR. This is usually in the range 13 to 40 seconds, within which time the carrier must be detected. When
to | .
‘the modem detects the remote modem'’s carrier signal on the line. it will assert DCD. This indicates
the DHQI11 that data is valid on the RXD line.

" The modem can now exchange data between the DHQI1 and the calling station for as long as DCD,

- DSR. and CTS stay asserted. If any of these three signals disappears. or if RI is detected during normal S
|
transmission. a fault condition is indicated. A change of state of any of these signals causes an interrupt
through the receive FIFO.

The handling of the fault conditions now becomes country-specific. since some telephone systems

tolerate a transient carrier loss. while others do not. In the USA it is usual to proceed with a call if carrier

resumes within two seconds. In non-USA areas it is possible for telephone supervisory signals. such as

‘dial-tone. to be misinterpreted by the modem as a resumption of carrier. In this case the host program
would assume that the connection had been re-established to the original caller and would cause a_

hung’ channel. To pre’vent.this.,DTR should be deasserted immediately after the loss of DCD. CTS. or °

'DSR. to abort the connection. DTR should stay deasserted for at least two seconds. after which timea
new call could be answered.

A-3

B
'APPENDIX
* FLOATING ADDRESSES |
| B 1 FLOATING DEVICE ADDRESSES

On Q-bus systems a block of addressesin the top 4K words of address space Is reserved for optxons with
floating devxce addresses. This range is from 17760010, to 177637768

Options which can be assmned floating device addresses are listed in Table B-1. This table gives the
sequence of addresses for both UNIBUS and Q-bus optxons For example the address sequences could
|
|
|
be:

DIl
DHI1!

DQIl1
-

DUIL DUV

and so on.

Having one hst allows us to use one set of configuratlon rules and one confiquratxon prozram
Table B-1

Rank

Device

Slze

17760010
17760020

DUPll gap

LK11A gap

DQI! gap
DU!l, DUVII gap

4
4

-~ DMCII/DMRllgap
- DZ11,DZVH/DZSII D232

'DHI1 gap

| '_ Modulus Address

(Decimal) (Octa)

DIl gap

Wb
W —
~N O

“

Floatmg Devnce Address Assngnments

10
10

17760030
17760040

4
4

10
10 wwx

~_gap-

17760060

17760070
17760100
o

KMCll gap

LPP11 gap

17760120

VMV2l gap

17760130

4
4
8

10
~10*
20*

17760150
17760160
17760200

VMYV31 gap

1314
15

DWR70gap
RLI1. RLVI1! gap
LPA11-K gap

KWIL-Cgap

17
18 AN

17760050

VSV2I gap
4
RXll/RXle/RXVllRXVZ] 4

10
S 10*

gap

B-1

17760110

17760140

17760210

- 17760220
17760230

‘Table B-1
Device

Floating Device Address Assignments (Cont.)

Size
Modulus
(Decimal) (Octal)

‘DRIILWgp

DMPI1 gap

DPVIl gap

~ ISB11 gap

3
4

KDA50/UDAS50/RQDX3 gap 2

29
30

DMF32 gap
KMSllgap
VS100 gap
TUS8I gap

=
"

KMV gap

16
6
8
2

1‘7760240_

17760260

17760300

17760320

10 *

17760330

17760334

17760250

40
20
20
4

| DHVII/DHUII/DHQII gap _8

10**

DMVI1 gap
DEUNA gap

DRI11-B gap

Address

17760270

17760340

17760360
17760400
17760404

17760420

17760440

The first device of thrs type has a fixed address Any extra devxces have a floanng address

“ *e The first two devices of this type have a fixed address Any extra devices have a floatmg address
*** The DZ11- E and DZ11-F are treated as two DZ11s.

- The address a531gnment rulesare as follows
Addresses,startmg at 177600103 for Q- bus systems, are assrgned accordmg to the sequence of
Table B-l.
|

Optron and gap addresSes are assigned aCcording to the octal m‘odulus as follows
’Dev1ces with an octal modulus of 4 are ass1gned an address on a4, boundary (the two

1 lowest-order address bits = O)

.Dev1ces with an octal modulus of 10 are ass1gned an address on a 108 boundary (the
three lowest-order address bits
= 0).

Devrcesthh an octal modulus of 20 are a551gned an address on a 20,) boundary (the

) four lowest-order address bits = 0)

| 'Dev1ces w1th an octal modulus of 40 are assxgned an address on a 40, boundary (the five

) _' lowest-order address btts = 0)
|

Address space equal to the devxce S modulus must be allowed for each device which is
connected to the bus.

A 1-word gap, assigned accordmg to rule 2 must be allowed after the last device of each type.

This gap could be bngger when rule 2 is applied to the following rank.

‘B-2

5. Al-word gap. assmned accorqu to rule2. must be allowed for each unused rank on thetolisttheif.
a device with a hlgher addressis used Thxs gap could be bigger when rule2 is applied
|

following rank.

| If extra devices are added toa system the fioatma addresses may have to be reassaned m agreement
with these rules

B2 FLOATING VECTORS

Each device needs two 16-bit locations for each vector. For example a devxce W1th one recewe and one

transmit vector needs four words of vector space
The vector assignment rules are as follows:

Each device occupies vector address space equal to "Size' wordsFor example the DLVH J

| 1.
|

occupies 16 words of vector space. Ifits vectorwere 300,, the next avallable vector would be at

340,

/a’

to align"an octal modulus.
2. ~ There are no gaps. except those needed

1
2
2
2

DLVII-]

DM11-BB/BA

-4
4
4
2

- DRI1I-C. DRVIl
PA61! (reader + punch)

no
|

DHI11 modem control .
DR11-A, DRVI11-B

9
10

10
10 **
10
- 10 **

10
10
10
4

4
8
8

- B-3

4
4
4

DHll
VT40
- VSVI1
LPSI1

(Octal)

4
10

DTO07
|
DXI11
DLII-C to DLV11- E
DJII

2
4

4
-8

LPDI1

(Decimal)

4
4
4
4

DLVI11. DLVI1I-F
DPI11
DMI11-A
|
DNI11

7
8

16
17
17
18

DCIl

2
3
4
-5

12
13
14
15

TUS8
- KLI1
DLI1-A
DLI11-B

Table B-2 Floating Vector A_ddfess 'Assignments"'

10
_10‘

10
10

10
10
10
10
10
10

‘Table B-2 Floating Vector AddressASsigfiments (Cont.)
Device
-

- Size

(Decimal)

DQl1

KWI11-W, KWVl1l1

Modulus
(Octal)

20
21
- 22

- DUIL, DUVI1I
DUP11

4
4

10
10

23
24

"DVIl + modem control
LK]I-A
|
-

6
4

10
10

DWUN

- 26
27

- KMCl11

LPPI1

VMV21

VMV3l

DZ11/DZS11/DZV11, DZ32

32
33

DMCI11/DMRI11

VTVO0l
DWR70

RL11/RLVI1I

-4
4

4
4
4

10
10

10
10
10

4
4

10
10

4 *

35
36
37
38
39

~ TS11, TU80
LPA1l-K
[P11/IP300
KwWl11-C
RX11/RX211 RXVII/RXVZI-

2
4
2
4
2

4 *
10
4 *
10
4 *

40
41

| DRII W
DRI1-B

42
43

DMP11
DPV1l1

4
4

MLI11

45
46
47
48
49

ISB11
DMVI11
'DEUNA
|
KDASO/RQDX3
'DMEF32

50
51
52
53

KMS11
PCLI11-B
VS100
TUS8I

55
56

KMVl

KCT32
- IEX
|
| DHVII/DHUII/DHQII

4 *
10
10

4 *nw

2
16
6
4
2
2

-4
4
4
4

10
10
4 *
4 *
4
10
10
4
4

10
10
10
10

Table B-I-Z Floating Vector Addréss Assignments (Cont.)
| Ran_k.

- Device
o

)
e
Ny

QNA

- VS31
LNV1I
QPSS
QTA

64
63

CPI32(sync)

(Decimal)

DMZ32,;CPI132(async)

Size

QVSS

DSV1l1

Modulus
(Octal)

2
2
2
2

4
4
4
4

The first device of this typehas a fixed vector. Any extra devices have a floating vector. |

Ifa KL11 or DLII is used as the console. it has a fixed vector.

»’*"“" MLII is a MASSBUS dev1ce which can connect to U\IIBUS v1a a bus adapter B

B-5

APPENDIX C

AUTOMATIC FLOW CONTROL
|
C.1 OVERVIEW
Flow control is the control of the flow of data along a communications line. to prevent an overspxll of

| ’queues or buffers, or to prevent the loss of data whxch the receiver is unable to accept.

The method of flow control adopted for the DHQI 1 is datastream-embedded ASCII control characters
S

The control characters used are XOFF (octal 023) and XON (octal 021). XOFF stops transmission and =~
XON starts transmission. The codes are transmxttedin the opp051te dxrectton to that of the data thev |

control.

)

o The DHQI 1 has one rnode of operatxon for transmttted data (received fiow-control characters) and two f
modes of operation for received data (transmitted flow-control characters). Each mode can be enabled
on a "per channel’ basis. Each dxrectlon of flow is dxscussed separately W1thm this appendtx
C.2

CONTROL OF TRANSMITTED DATA

The transmitted-data mode of flow control is the 51mplest of the three flow-control modes of the

DHQll

‘When the DHQll receives an XOFF character for a parncular channel. the TX. ENA bit for that o
channel is cleared. When this bit is clear, the DHQI11 will not transmit any data on that channel;
however, internally generated flow-control characters will still be transmitted. When an XON character

~is received, the TX.ENA bit for that channel 1s set thure C 1 1llustrates the operatlon of the
transmitted data flow control

C-1

RECEIVED

OAUTO=0

‘

XON RECEIVED

~ OAUTO=1

XOFF

~ |RCVD

—_OAUTO=0
XOFF RECEIVED

XOFF
»

QAUTO=0
S

RECEIVED

anlls:

| .’-Figure-C}-l A‘Transmitted' Déta Flow Control
| Only characters without trénsmission errors are checked for XON and XOFF codes. The characters
have their parity bit stripped before comparison.

‘For the automatic flow control to operate correctly,

~-the terminal must also recognize and respond to
- flow-control characters.
|

The transmitted-data mode of flow control is enabled by setting OAUTO (bit 4 of the line c'on_tr.VOIV

Received flow-control characters are processed in the same way as normal characters.
and are placed
into the receive FIFO. This is not affected by OAUTO. but these characters can be filtered
out by setting
DISAB.XRPT. If DISAB.XRPT is set. you do not need a routine in your software
driver to filter
~ flow-control characters from the data stream.
B
.

C.3 CONTROL OF RECEIVED DATA

‘Received-data flow control is slightly more complicated than transmitted-data flow control. Therefore
the two modes of received-data flow control are described separately.
»

C.3.1

Flow Control By The Level Of The Receive FIFO

- Occasionally, the program may not be able to empty the receive FIFO as fast as the
received data is
filling it. Because the program does not know how full the receive FIFO is. it cannot take
action to
~prevent data loss. To overcome this problem, the DHQ!1 can be programmed on a ‘per channel”
basis.

When the receive FIFO becomes three-quarters
full, an XOFF

is sent to the channels from which data is

received. An XOFF character is then sent
in response to every second received character. until the

receive FIFO level drops below half full. An XON character is then transmxtted The Operauon of
receive FIFO- evel flow control is shown in qure C-2.
»
|
e

FIFOCRIT=F

FIFO.CRIT=F

1AUTO=1

CFIFOGRIT=T

1AUTQ=0

\JAUTO=0

IAUTO=V1' FIFOCRIT=F
.

cHaR
~ (senp |

XON

IAUTO=1

FIFO.CRIT=T

[ SEND )
XON

FIFO.CRIT=F

CHAR

RCVD

IAUTO=0

~FIFO.CRIT=F

an22s82

Figure C-2 Receive FIFO'.L,e'vel‘ Flow Control -

C-3

The receive 'FIFO-leVel flow-control mode is enabled by‘settmg IAUTO (bit 1 of the line control

after an XOFFis sent, but before the recexve FIFO level drops below half full, an XONis still sent. | |
NOTE
FIFO.CRIT is set (T) when the receive FIFO is being
filled, and contains 192 characters. Itis cleared (F)
when receive FIFO reaches 127 characters as it is

) being empued

| _C32 Flow Control By Program Initiation

Occasionally, the program itself may need to invoke flow control, for example, when host bufi‘ers become full. To allow this, the DHQ11 has a FORCE.XOFF bit (bit 5 of the line control register). When
‘the FORCE.XOFF bit is set, the DHQ!1 transmits an XOFF character for that channel. A further

o XOFF bitis transmitted for every second character received on the channel afterwards. An XONis sent

when the FORCE.XOFF bit is cleared. Figure C-3 shows the operation of program-lmtxated flow
o control The FORCE XOFF bitis cleared by a DHQll reset sequence
|
CHAR RCVD

— FORCE.XOFF=1

CHAR
FR(:\/ED» S

FORCE.XOFF=1

AORr=T

CHAR RCVDN\_
Sl

—_

CHAR RCVD
-

FORCE.XOFF=0

eihd

“FORCE.XOFF=0

RD22%3

' Figure C-3 Program-Initiated Flow Control
|

NOTE

If the program sets the FORCE.XOFF bit and then
immediately clears it, the XOFF code may not be
transmitted. This is because there is a delay of up to
-

350 microseconds before the DHQ11 detects the need
to send an XOFF. If the conditions for sending an
XOFF clear before within this time delay, no XOFF
code wnll be sent.
|
o

[

C.3.3 thmg The Two Tvpes Of Rece:ved-Data Flow Control

To calculate the effect of using the two modes. they should be lomcallx ORed tozetheran XON will not

be sent until both sources are inactive. An XOFF will be sent when FORCE.XOFF is set. even if
FIFO-critical modeis active and an XOFF has already been sent on that channel.If the receive FIFO

critical mode becomes active whilst FORCE XOFFis set. then another XOFFis sent in response to the
|

- next received character.

C-5

‘.

)

v
C

—~—

’
.

APPENDIXD
GLOSSARY OF TERMS
Dl

SCOPE

This appendtx contains a glossary of terms used in [hlS manual and in other DIGITAL techmcal |
manuals in thlS series. The terms are in alphabettcal order for easy reference
D.2

GLOSSARY

Asynchronous. A method of serial transmissionin which data IS precededby astart blt and followed'_j £
by a stop bit. The receiver provrdes the mtermedtate ttrmng to 1dent1fy the data bltS

Auto-answer A facxhtv of a modem or terrnmal to answer a call automatrcallly

Auto-flow. Automatic flow control A method by whxch the DHQll controls the flow of data bv means

of special characters within the data stream

Backward channel. A channel which transmtts in the OppOSttedtrectlon to the usual data fiow L
|

Normally used for supervlsorv or control sxgnals

Base address. The Q-bus address of the first (lowest) dev1ce reglster (CSR) ‘-f ,»
- BMP.

Background Momtor Program

CCITT. Comite Consultatxf Internattonal de Telephome et de Telegraphxe Anmternattonal»l'

'standards committee for telephone telegraph and data communtcattons networks
Dataset

See modem

DMA Direct Memory Access A method Wthh allows a bus master to transfer data to or from system.'_

memory without using the host CPU
Duplex.

A method of transmttttng and recexvxng on the samechannel at the same ttme
\

EIA.

Electrical Industnes Assocratton An Amertcan orgamzatton wrth the same functton as the, g

FCC. Federal Commumcattons Commxssnon An Amertcan organtzatton Wthhregulates and hcenses o
communxcattons equtpment

FIFO First In First Out. The terrndescribes a .register ot‘ rnerno'ry‘_ from\ whi‘ch,the ol'dest data_iis' e
removed first

Floating address An address assrgned to an optton Wthh does not have a fixed address allocatedThe_addressis dependent on other floating address devrces connected to the bus

;o Floatmg vector An mterrupt vector assrgned to an optton whtch does not have a fixed vector allocated
~ The vector is dependent on other floatmg vector devrces connected to the bus

D-1

G FRUFreld-Replaceable Umt
IC. Integrated Ctrcurt

y I/O Input/Output
‘v .,;,_LSB Least-Srgmficant Blt

MMa Modrfied Modular Jack.
|

Modem The word1s a contractlon of MOdulator DEModulator A modem mterfaces a terrmnal to
a transmrsswn line. A modem is somettmes called a dataset.

FT»MSBMost Slgmficant Blt
Multxplexer A devrce whrch allows a number of mputs to share one common output

i:-Null modem Acable whrch allows two termmals whrch use modem control srgnals to be connected

-OCTARTA smgle IC contammg erghtUARTs

T together dtrectly It s only possrble over short dtstances

_-L_.-,.PCB Prtnted Ctrcutt Board
| Protocol A set of rules whxch define the control and flow of data in a commumcattons system
o PST\I Pubhc Sw1tched Telephone Network

Q-bus A global term for a specrfic DIGITAL bus on whrch the address and data are multrplexed

o RAM Random Access Memory
o RFI Radro Frequency Interf
erence

SR v'VZROM Read Only Memory

o "-'.'Spht-speed A facxl.tty ofa data commumcattons channel whrch can transmrt data at a drfi‘erent speed
~ from the recerved data

UART Umversal Asynchronous Receiver Transmitter. A device which converts between serial and
e ) ‘parallel data used for transmrssxon and receptton of sertal asynchronous data on a channel.

- _XOFF Acontrol code (233) used to dlsablea transmrtter Specxal hardware or softwareis needed for

| 1 ._‘thts functton

XON A control code (21) used to enable a transrmtter whrch has been dtsabled by an XOFF code.

APPE’\IDIX E

DHQll Q-BLSCON\IECTIONS
" Table E-1 DHQll Q Bus Connecnons T
- Signal