This Technical Manual describes the DHQ11, an asynchronous multiplexer developed by Digital Equipment Corporation (DEC). Published in February 1987, it serves as a comprehensive reference for the DHQ11's physical layout, system configuration, installation, testing, programming, and maintenance.
The DHQ11 is a dual-height Q-bus module (M3107) that provides eight full-duplex serial data channels for Q-bus systems. It is primarily designed for interactive terminal handling but can also be used for data concentration and real-time processing. Key features include:
- Communication Standards: Supports EIA-232-D/V.28 or DEC423.
- Data Transfer: Offers both DMA transfers and programmed I/O for transmission, and utilizes a 256-entry FIFO buffer for received characters.
- Programmability: Each line's transmit and receive baud rates can be individually programmed, achieving a total throughput of 60,000 characters per second (using 8-bit characters with all channels operating at 38.4 kbaud).
- Modem Control: Includes sufficient modem control for auto-answer dial-up operations and can filter XON/XOFF characters.
- Addressing: Supports 16-, 18-, or 22-bit addressing, including block-mode data transfer.
- Diagnostics: Features self-test and background monitor testing.
The manual is organized into five main chapters and several appendices:
- Introduction: Provides an overview of the DHQ11's physical description, configuration options, and how it interfaces with the system bus and serial data lines.
- Installation: Details the steps for installing the DHQ11 module, including setting device and vector addresses via on-board switchpacks, backplane positioning, cabling, connectors, and post-installation testing.
- Programming: Describes the DHQ11's registers and includes programming examples for controlling and monitoring the device.
- Troubleshooting: Explains maintenance strategies and the use of diagnostic programs to locate and resolve faults.
- Technical Description: Offers an in-depth technical explanation of the DHQ11's internal functional blocks, such as the Control Chip and OCTART Chip, and details data flow mechanisms.
- Appendices: Provide supplementary information on modem control, floating addresses, automatic flow control, Q-bus connections, and pinout details for the control chip and OCTART. A glossary of technical terms is also included.