DEC-10-H1CA-D MX10 Memory Data Multiplexor Maintenance Manual May69

This document is the Maintenance Manual for the Digital Equipment Corporation (DEC) PDP-10 MX10 Memory Multiplexor, first printed in May 1969.

The MX10 is an optional component designed for PDP-10 computer systems, enabling up to eight peripheral processors (such as the DF10 Data Channel) to share access to the memory system. It is typically installed in a DF10 Data Channel cabinet, is a passive unit with no operating controls, and receives power from the DF10.

Key features and operation include:

• Priority Management: It incorporates logic to grant memory access priorities to the eight peripheral processors (Port 0 has the highest priority, Port 7 the lowest) to resolve simultaneous requests.
• Access Handshake: A DF10 requests access, and the MX10 responds with an acknowledgment, allowing the DF10 to gate out address and command information.
• Memory Cycle Management: The MX10 facilitates Read, Write, and Read-Modify-Write memory cycles by acting as an intermediary for data and control signals between the peripheral processors and the main memory bus. A "BUSY" flag prevents other requests during an ongoing memory cycle.
• Compatibility: It is not designed for connection to KA10-type central processors.
• Specifications: Notable specifications include support for 8 ports, a 20 ns delay, and 85W power consumption.

The manual provides detailed descriptions of its installation and principles of operation (covering power-on, request handling, memory read/write cycles, and handling of nonexistent memory). It also outlines specific maintenance procedures, including test configurations (disk, off-line with DF10 tester, and off-line with a dedicated MX10T tester) and voltage margin tests. Essential supporting information includes engineering drawings, a glossary of mnemonics and technical terms, and a comprehensive spare parts list for troubleshooting and repairs.