M8417-C 32K PDP-8 MOS Memory Engineering Specification

Summary

This document provides the engineering specifications for the M8417-C, a 32K x 12-bit MOS memory module designed to interface with the PDP-8 Omnibus.

Key Technical Details:

• Capacity: 32K words (12 bits per word) using 4K MOS dynamic RAM chips.
• Compatibility: Designed for the PDP-8 Omnibus; requires +5V, -5V, and +15V power supplies.
• Memory Addressing: Address space can be strapped to start on any 16K boundary from 0 to 128K.
• Performance: Features a 265 nsec (max) access time and 1.4 µsec (max) fetch cycle time.
• Operational Integrity: Includes built-in transparent refresh cycles every 15.6 µsec. If power is lost, the stored data is lost (volatile).
• Maintenance & Testing: The module includes test points for internal timing adjustments and a connector for manufacturing test purposes. It is designed to be a standard module with a handle and supports conventional pin-based connectivity.
• Physical Layout: The document includes schematic diagrams (Pages 3-5) and pin configuration tables (Pages 1-2) detailing jumper configurations, IC pin locations, and timing resistor values for field or factory adjustment.