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Document:	DFC11-A EIA Level Converter/Clock Recovery Module Maintenance Manual
Order Number:	EK-DFC11-MM
Revision:	002
Pages:	36
Original Filename:

OCR Text

DFC11-A

EIA level

converter/clock recovery
module maintenance manual

dlilgliltiall

~ EK-DFC11-MM-002

DFC11-A EIA level
converter/'cIQCk recovery

module maintenance manual

digital equipment corporation - maynard. massachusetts

Ist Edition, August 1974

The material in this manual is for informational
~

purposes and is subject to change without notice.

Digital Equipment Corporation assumes no responsibility. for any errors which may appear in this
- manual.

Printed in U.S.A.

The followrng are trademarks of D1g1ta1 Equrpment
Corporatron Maynard Massachusetts

DEC
FLIP CHIP

DIGITAL

PDP
FOCAL

COMPUTER LAB

2nd Printing (Rev), April 1975

CONTENTS
Page

CHAPTER
1

INTRODUCTION
SCOPE

1.3

. ........ e

SR PP
T

1-1

PHYSICALDESCRIPTION

. .. .................. AP AR

.. ......... B

CSPECIFICATIONS

CHAPTER 2

- GENERAL DESCRIPTION

1.1
12

S
e e e e

e e e
e e 1-1

. . ..o

INSTALLATION

"GENERAL
. ............ S

2.1

2.2

- UNPACKING AND INSPECTION

2.3
2.3.2

' CHAPTER 3

[ S

e e e,

2-1

. . . . . . .. .ttt

2-1

. . . . . . .

INSTALLATION
AND CHECKOUT

2.3.1

e e e

DUlllInstallation Procedure

. . . . . . . . . v v v v v i i

DPI] Installation Procedure

. . ... ...
.. e

2-1

e e e e e

e ee

e e e e

2-3

THEORY OF OPERATION |

FUNCTIONAL BLOCK DIAGRAM DISCUSSION

3.1

3.2

e e e e e e e e e e e e

3-1

. ... .. ... ......... e e e e e

3-1

. . . .. ... ... ... ... .. . . . . ... .. ...

3-1

| _DETAILEDLOGIC DISCUSSION

- 3.2.1

Clock Generation
Logic
Clock Divider Logic

. . . . . . . o i i e i

Level Converter LOZIC

3.2.3

324

. . . . v v o v

Clear To Send Delay Logic

. . . . .e e

MAINTENANCE PHILOSOPHY

e e e e e e e

e e

3-1

e e e e e e
e

3-1
e

3-1

e e

3-5

e e

3-5

)

. . ... ... .. e e
e
e

MAINTENANCE PROCEDURES

4.3

_REPAI:-RPROCEDURES e

CHAPTER
5

e e e

. . . . . . . . i

MAINTENANCE

CHAPTER 4

e e e

. . . .............. e

Clock Source Selection Logic
DCRegulator

e e it

; Clock Synchronization _Logic’__ e e et

3.2.5

. ... ..........L....... P

e e e

e e e I

4-1
X% |

MANUFACTURING DRAWING SET

’IN TEG’ ';{ ;.”'TED CRCUIT DESCRIPTION S

ILLUSTRATIONS
" Figure No.

Tltle

DFCll-A EIA Level Converter/Clock'Recovery Module

1-1

- 2-1

22
31

»'

DFCllALocatloanUllSystem

1-1

R e

DFC11-A Locationin DP11 System . . . ... ... T
~

DFC11-A Functional Blocleagram

~ Clock Logic Block Diagram-

A‘Page‘ |

N N

IR
S

. ... ... .. .00, e

2-3
3-2

e e

3-3

A L.

e e e e n e e e e

393

v v v ... . e

3-3

Baud Rate Selection

. ... .. ST

R T

"EIA/TTLLevel Converter

. . . . ...«

v v

- 3-5

TTL/EIA Level CONVETtEr

. . . . v v v v ot

e e e e v e e e e

Clock Synchronlzatlon Logic Block Dlagram
Clear To Send Delay Logic Block Diagram

Clock Recovery Logic Block Diagram

ee e

3-3

T T

3-4

e e e e e

e e e e e e

e e

e e e e e e e e e ..

..... G
)

iii

CHAPTER 1

INTRODUCTION

1.1

SCOPE

This manual contains information concerning the DFC 11 A
EIA Level Converter/Clock Recovery module (M5942).

Included is a list of specifications covering the module’s

performance and I/O requirements, instructions for its
installation in various systems, the theory of operation, and

maintenance information.

This chapter consists of a general description of the
module’s purpose and use, a physrcal descnptron, and a list
of specrficatrons
1.2 GENERAL DESCRIPTION

The DFC11-A is an EIA level converter that is compatlble 5 |
with the DF11-A specifications for synchronous interfaces

and with the RS-232-C/CCITT for baud rates up to 10,000.

and cable lengths up to 50 feet. The unit has provision for

either a synchronous clock option that provides a clock

-source on EIA/CCITT transmit element timing lead (DTE),

pin 24, or a clock recovery option. Baud rates are 300, 600,

1200, 2400, 4800, and 9600. Frequencies are crystalcontrolled to 0.05 percent at a crystal frequency of 614.4
kHz.

| 7‘406-‘1 .
Frgure l 1

DFCll -A EIA Level Converter/Clock
Recovery Module

The clock recuovery‘ option is used with EIA SynchIOHeUSj |

interfaces when connected to an asynchronous data set or
equivalent.

A crystal clock source is provided for the

transmitter and receiver. In addition the receiver clock
source is synchronized with the incoming ‘data by the
carrier detector.

The DFC11-A will operate with a DPlllb DUI1, or any
other synchronous interface which has access to a DF11

slot. It will not operate in a DM11 or DH11 distribution
panel.

R
Sy
1.3 PHYSICAL DESCRIPTION
The DFC11-A consists of an 8-1/2 inch by double modulef

AT
|

(type M5942). Pinning is per DF11 spe01ficat1ons The

module, shown in Figure 1-1, accepts either a BCOSC 25or;- ;

- a BCOSC 50 cable

"Power requrrements are +5 Vdc at 400 mA, +15 Vde atr”.": o
22 mA, and -15 Vdc at 20 mA. The temperature range is

10° to 50° C at 90 percent humidity (noncondensmg)

Without

panelin which it is installed.

EIA/CCITT cable connector.

1.4

By switch selection, may be turned on either by first

SPECIFICATIONS

I/O Specifications

Clock Recovery:

Taken from pin 17 of

All DFC11-A operating power is derived from the mountrng

received data Mark-to-Space transition, or by a carrier

Data Set Side

Off-to-On transition.

‘Meets failsafe RS-232-C/CCITT for baud rates up to
10, 000 and cable lengths to 50 feet.

By switch selection, may be resynchronized by any
data Mark-to-Space transition, or not synchronized

Interface Slde

from turn-on.

TTL compatible

By switch selection, may be turned off by no data
General

transition for 0.5 second, or by a carrier On-to-Off

TTL/EIA voltage level relationships are noninverting.

transition.

Performance Specrficatlons
Baud Rates

(0.05% tolerance) (SW1tch selectable)

Transmit (TX) Clock

~ negative edge of clock (+3 to 0 V)

With Clock Recovely Taken from pin 15 of EIA/

Request To Send

‘May be switched to always ON (EIA)

CCITT cableconnector sourced to p1n 24,
Without Clock Recoveijy Internal transmrt clock

Clear To Send

always ON to interface.

” '_ NOTE

Recelved data should be strobed onv

300, 600, 1200 2400 4800 9600 and 19,200 baud

By switch selection, maybe forwarded to interface at

delays of 0, 0.1, 0.2, or 0.3 second.

NOTE

Interface should change transmltted data

only on pos1t1ve edges (O to +3V) of

Contains extra capac1tors and threshold adjustments

‘transmit clock.

for an unterminated connection.

Receive (RX) Clock

With Clock Recovery: Reconstructed clock from a

NOTE

The DFCll A is capable of functlomng asa

source clock. No more than 6.25% distortion from
- shifted strobe time from bit center.

normal DF11-A.

1-2

(

CHAPTER 2
INSTALLATION

GENERAL

the DFC11-A

consrsts of

unpackmg,

inspection, connection, and- checkout of the unit in a

//////////////////////////

DFC11-A

configurations: systems using a DU11 Synchronous Interand systems

umeus IN

system. At present, the moduleis intended for use with two

face

M7822

using a DP11-A Synchronous Line

- Interface. This chapter covers installation of the DFC11-A

ee
/

////////////////

UNIBUS ouT

in these configurations. As future options become available,

MODULE SIDE VIEW

[instructions pertaining to DFC11-A 1nstallatron wrll appear

11-2533

in documents covering those Optlons :

2.2

2.1

Installation of

“Figure 2-1

UNPACKING AND INSPECTEON

Unpack the DFC11-A and check the oontents of the .

DFC11-A Location in DUI1 System

2. Mount the DFC11-A in slots AB_2 and/or AB3.

- package against the shrpprng list. It should contam an

M5942 module, a maintenance manual and a dragnost1e- 2
tape MAINDEC-11 -DZDFA-A-D.

NOTE

- Grant Contmulty module (G727) is insertedin each slot that does not receive

an interface logic module.

"Check eXposed leads for apparent'| damage' Inspect the

3..

-~ module for damage during shipment, such as loose com-

| | ponents or abrasrons to the module itself.

Plug the BCO5C cable (which comes with the

DU11)

into the

DFC11-A

module

Berg connector
and into

the

the H315

test

_‘ connector at the other end.

2 3 INSTALLATION AND CHECKOUT

‘There are two applications in‘which the DFCll-A can be o
-

~ installed. One is in apanel,
systeminwith
a DU11-A andaDD11-B
whrch the DU11-A interfaces
peripheral mounting

- the Bell 201 synchronous modem or equivalent; the otheris

with a DP11 and a 200 series modem In the latter

- DD11-B mounting panel or equivalent (with DD11-B ECO |
No.3or hrgher)is requrred Proceed as follows

»Onc,e installed, return power to the system and
check out by running MAINDEC-11-DZDF
A- A-D for 15 minutes. It should run error free.

When checked out, remove power, remove the
H315 test connector, and connect the cable to

1. Removepower from the system and install the
DU11 in module slotsC, D, E,and F2 and/or
C,D,E,and F3 (Frgure 2-1)

EIA(2)and 811 (1).

23 DUl Installatron Procedure A
- If the DFC11-A is to be used ina system wrth a DU1l, a
~

On the A portron of the board cut ]umpers
-

- configuration, power is derrvederther from the computer or

_from a BAll mountrng box.

Set the swrtches on the module per the requirements of the installation (Table 2-1). Software
o documentationalso contains these settings.

the modem.

Return power and restore the system to
-

normal.

Table 2-1

'DFC11-A Switch Position/Function
Switch

812

Position

Function

~ Enable DFC11-A.

NOTE

This switch must be ON for the module to operate; one

~switch of S2-3 through 10 must also be ON to select the
clock for clock recovery.

S1-2

OFF

Disable DFC11-A.
In this pos1t10n the module operates as aDFll A Sl 8 ON.

| supplies the extemal clock.

S1-1

RX clock turned on by carrier Off-to On transmon -

Sl§3

ON _4

RX clock turned on by first receive. data Mark toSpace transmon.'

S1-4

RX clock resynchronized by any Mark—to-Space data transition-.

S1-5

OFF

RX clock turned off by no data transition aftera p_eriod of 0.5 second.

S1-5

- RX clock turned off by On-to-Off carrier transition.

S1-10

OFF

Request To Send always on.

S1-9

Clear To Send with no delay.

$1-9

OFF

S1-6

| Clear To Send with 0.1-second delay. o

S1-9

OFF

S1.7

- 819

OFF

S1-6

S2-3—

| Clear To Send with 0.2-second delay.f

" Clear To Send with 0.3-second delay.

‘Select baud rate.

S2-10

2-2

2 3.2

DP11 Installation Procedure

( A If the DFC11-A is to be used in a system wrth a DPll a

BCO5C cable is required. Proceed as follows

| UNIBUS w
GSOOO

‘Remove power from the system and mstall the
DFC11-A

in slot CD4 (Figure 2-2).

A M105

Plug the BCOSC cable into the Berg connector

software documentatlon

also

M?B?O

| M405 | M239_ I

orct-a

~ MODULE SIDE VIEW

test connector at the other end

The

M7075 M7065 M707'5 ‘M7065

VUNI:Bus,oUT“ |

Set switches on the DFC11-A per Table 2-1.

| _ wrees

on the DFC11-A module and into the DPll -

11-2534

Figure 22 DFC11-A Location
in DP11 System

contams'

these settmgs
4,

- On the A portlon of the board, cut ]umpers; .
EIA (2), 811 (1), and BUSY(I)

- 6.

test connector, and connect the cable to the

modem

Once installed, return power to the system and o
check out by running MAINDEC-11-DZDFA-

A-D for 15 minutes. It should run error free.

When checked out, remove power, remove the

Return

»normal

|
power and

restore

|
the system to_

CHAPTER
3
THEORY OF OPERATION

3.1

F UNCTIONAL BLOCK DIAGRAM DISCUSSION

C35 and C36 control the circuit range. The circuit as

~ A functional block'diagram of the DFC11-A is shown in

- configured can oscillate over a wide range of frequencies,

Figure 3-1. This should be referenced to Schematrc Drawing

but the range of crystals that can be utilized is limited by

D-CS-594 2-0- 1 (Chapter 5)

‘the response of the 1489 EIA receivers.

'-The DFCllA is an EIA/TTL and TTL/EIA level converter

~ 3.2.2

that contains a crystal clock with a chain of ‘dividers.
Circuits are included to enable the DFC11-A to function as
-

Clock Divider Logic

The clock divider logic is shown in Figure 3-3. The output

of the basrc clock oscillator is fed to a pair of 74197

a clock-source or as a synchronizer for the 'i‘ncoming- .data. |

frequency dividers in tandem. The 614.4 kHz is sequentially divided by two to produce the range of frequencies

__The option consists of the followmg functronal blocks of

logic (F1gure 3- 1)

l.fi

- equal to 19,200 to 150 baud. The common points of eight

switches ‘may be selectively closed to the desired rate and

fed to a pair of 74197s, where the signal is divided by 16

Two nonmvertmg level converters that trans-

- and separated into transrmt and receive clocks.

and the 1nterface

323 Level Converter Loglc |

form the signals to and from both the modem

There are two sets of level converters in the DFC11-A.

2. An intemal”clock”that feeds:adivider

Level conversion is achieved by the use of EIA receivers

(1489) and drrvers (1488)

3. ) A d1V1der cham that feeds the transmrt and‘

‘_Frgure 34 shows_a typical EIA/TTL conversion circuit. The

» 'recerve clock logic.

EIA signal is brought in and the TTL output is inverted by

Clock synchromzatron logrc thatis actrvated by

_'erther recerved data or a Carrrer Detect signal.

” 5

Clear To Send logrc w1th provrsron to vary the

7404s. These interface the Bell modems to the computer

logic. All EIA level signals of +6 to +25 V (logic 0) and -6

to=25 V (logic 1) are converted to +3 V (logic 1) and 0 V

- (ground), representing a logic 0.

- amount of delay

3. 2 DETAILED LOGIC DISCUSSION

Figure 3-5 shows a typical TTL/EIA converter. These

~convert the logic level signals to the operating voltage levels

The followmg discussions are keyed to the blocks contamed
in Figure 3-1 and Drawing D-CS-5942-0-1. For detailed
-

of the Bell modems. All logic signals of 3 V or more are
-

information concermng 1ntegrated circuits (ICs), refer to

converted to +6 V or more. The level converter threshold

Appendr:x A.

321 Clock Generatlon Loglc

voltage is 3.0 V. Any inputs less than 3.0 V will not cause
the converter to switch.

A block diagram of the clock logrc is shown in Frgure 3-2.
-

converted to -6 V or less. All ground (0 V) logic signals are

3.2.4

Clock Synchronization Logic

This is a standard clock configuratlon using a 614.4 kHz

The clock synchronization logic is shown in Frgure 3-6.

crystal, a pair of 380s, and a 74121 one-shot set for 40-ns.

With this circuit, the receiver clock may be resynchronized

3.1

FROM

MODEM

c1A oS

EIA CS

TTL CS

CLR TO|

SEND

peLAY

TO INTERFACE

= TTL CS
DELAYED

ETIA/

LEVEL
| CONVERTER

o
-

XTAL
CLOCK

| CLOCK
DIVIDER
LOGIC

,/f“\

cLock [

CLOCK [

EIA
SCT
EXT

— R —

o
\/
TTLo;;‘)—_

EIA
|
EXTSCRl

= TTL SCT e

+TTL SCR

e
|TTL SCR

EIA RCV
DATA
|

TTL RCV
|DATA

.
\

» TTL RCV
DpaTA

SYNC
LOGIC

EIACD
|
it

TTL CARRER]-

ETA

EIA

EXTCLKl iever |,

CONVERTER

» TTL CARRIER

DETECT

BTN

11-2535

Figure 3-1 DFCI1-A Functional Block Diagram

3-2

R
10K

Ri2

10K

74121

E10

ONE SHOT

D—» CLOCK

DIVIDER

1 614.4

]"‘ KHz

C36

470pf

R10
2K
11-2536

Figure 3-2' Clock Logic BloCk Diagram
BAUD
ek
s
614.4 —»
KHz -

1s
~2F

——
~—————

9600

153.6

4800

76.8

74197

<4pP—1

E16

+3pP—t4—+4e+———

E22

————

28—~

FREQ (KHz)

R
19200
307.2

1le

9710856
34

1200

19.2

300

74197 | RECEIVE
RX —16}» CLK

74197 | TRANSMIT
U 11-2837

ETA IN —

TTL IN—7404 >
11-2538

Figure 3-4 EIA/TTL Level Converter

Figure 3-5 TTL/EIA Level Converter =

74197
RX

LD
o

EIA
DATA

‘

)

\74121]

/S
D—‘

—d

oM
ZEROES

EIA CD

7474

EE P

S1-

o—

»11—2540

Figure 3-6 Clock Synchronization Logic Block Diagrafn

by any Mark-to-Space transition of data, by a Carrier

turn-on. Selection of this option is by switches S1-3, S1-4,

resynchronized at every high-to-low transition. If S1-1 is

- Detect transition of Off-to-On, or not synchronized from
and S1-1.

synchronization, if S1-4 is also closed, the receiver clock-is

closed, a Carrier Detect transition will perform the same

This is the sync recovery feature of the DFC11-A. Tt is
useful in

situations in which the two clocks are not

function.
3.2.5

Clear To Send Delay Logic

matched, or in systems using a modem that does not supply

The Clear To Send (CS) delay logic is shown in Figure 3-7.

a clock. Without this feature, a free running clock would

With this circuit, Clear To Send can be manipulated by sets

not guarantee accurate character timing.

of switches in the logic. With S1-9 closed, CS is propagated
through the logic with no delay other than gate delays. If

As can be seen from the figure, when S1-3 is closed, any

S1-9 is opened, CS is forced through the 74121 one-shot at

transition from high to low at the EIA input causes the

E6 and, after a set delay, to the TTL CS output via the

one-shot to fire and, as a result, loads the Receiver Clock

7474 flip-flop at E7.

ETA cs~Do-q{> .
S1-7
2.3

2.2

SEC

' —)

74121

0/S
E6

11-2541

Figure 3-7

Clear To Send Delay Logic Block Diagram

Under these conditions, combinations of S1-6 and S1-7
control the amount of delay applied to the appearance of

" EXT CLOCK (INT) is sourced from the DFC11-A intemal

CS. Closing S1-6 applies a 0.1-second delay. Closing S1-7

it is open, the serial external clocks for transmit and receive

increases the delay to 0.2 second. With both switches

are allowed to pass through at a TTL level.

closed, the delay is set at 0.3 second. These figures are
approxnnate and the timing here is not critical.

clock source from the Transmit Clock register (TX). When

When S1-8 is closed, the EXT CLK INT from the DFC11-A
is sent out as EIA EXT CLOCK. With S1-8 open, the EXT
CLK from outside is sent through as EIA EXT CLOCK.

3.2.6 Clock Source Selection Logic

‘This is the clock recovery option (Figure 3- 8) of the

327 DC 'Regulator

DFC11-A. This option is either enabled by S1-2 being

The dc regulator, composed of Q1, Q2, and zeners D1 and

closed, or disabled by S1-2 being open. When it is closed,

D2, serves to maintain the voltage supplied at 10 V.

FROM TX

—EXT CLK (INT)

EIA

TTL

SCT

(EXT)

SCR—

>t}

—

TTL

SCR

EIA
EXT
CLOCK

EXT CLOCK 11-2542

Flgure 38 j‘-Cloc;k; -Recovery Logic Block Diagram

CHAPTER 4
MAINTENANCE |

4.1 MAINTENANCE PHILOSOPHY

4.3 REPAIR PROCEDURES

Maintenance of the DFC11-A consists of running the
DFC11-A diagnostic, MAINDEC-11-DZDFA-A-D, and

When the M5942 module is to be: 'repai'red standard
troubleshootmg techniques should be utilized in isolating

instructions contained in‘ the document

the defective component using the theory discussions in

supplied with the tape. The tape has prov1S1on for testmg

Chapter 3 and the logic block schematics supplied as part of

the DFC11- A with either-a DU11 or a DPll

the manufacturing drawmg set (Chapter 5).

following

the

4.2 MAINTENANCE PROCEDURES

If running the diagnostic indicates that a malfunctlon ex.13ts
in the system in which the DFC11-A

A multimeter can be used to check for continuity or to

measure the resistance of suspected components.

is ‘installed, a check
|

should be made to determine if the problem exists in the

CAUTION

The X10 multimeter range is recommended for

- DUI1 or DP11 interface.
The diagnostic should indicate

checking semiconductor devices.

this. (Refer to the applicable maintenance manuals for
procedures.) It should then be determined if the system
modem is operating properly. Instructions for this can be

found in the manuals supplied with the equipment.

- Once the malfunction has been isolated to the DFC11-A,
the next step is to swap cables to see if that corrects the

| problem. If it does not, troubleshooting techniques should
- be performed on the M5942, after a module that
is known

Most multimeters apply a positive voltage to the common
lead when adjusted for measuring resistance. Therefore, the

polarity of the multimeter leads should be checked before
measuring the resistance of semiconductor devices.

Only the input, output, and power terminals are available
thus,

static

multimeter

testing is limited to

to be good has been swapped from spares.

It is beyond the scope of this manual to give detailed

continuity checks for shorts between terminals. IC checking
is best done under dynamic conditions using a module

troubleshooting procedures for the M5942. The module is

extender to make terminals readily accessible.

ICs;

- sufficiently unsophisticated so that standard techniques can
be utilized.

‘When soldering semiconductor devices (transistors, diodes, - |

“ A visual inspection can be performed to check for broken

heat, physical shock, or excessive electrical current, use a
heat sink, such as a pair of pliers, to grip the lead between
the joint and device being soldered. Use a 6-V pencil-

~connectors, frayed or broken insulation, improper seating
of the module, worn or bent contacts in the mountmg

panel or overheated components

Power supply voltages should be checked at the mounting
panel

source

pins.

Refer to

the manual covering the

rectifiers,
or integrated circuits) that can be damaged by

- -pointed-tip iron with an isolation transformer. The smallest
iron adequate for the work should be used.

Perform the soldering operation in the shortest possible

particular panel for the specific system to detennme the

time

proper voltages, pms and tolerances.

delamination of the module etch.

prevent

damage

the

component

and

To remove ICs, use a solder sucker to remove all excess

CAUTION

solder from the contacts. Then, by straightening the leads,

These cleaning agents will damage plastic handles.

save the defective component for test purposes, clip the IC

‘In all soldering
and unsoldering operations in the repair and

- lift the IC from its terminal points. If it is not desired to

replacement of parts, avoid placing excess solder or flux on

leads close to the chip and remove the chip portion of the
IC. Then apply heat to individual leads (side 2) and remove

adjacent parts or service lines. When repair has been

leads from side 1, using a pair of needlenose pliers. Do not

~completed, remove all excess flux by washing the junction

hold the lead with pliers whfle applying heat; the pliers will

with a solvent such as trlchlorethylene Be very careful not
to expose paint or plastic surfaces to this solvent.

act as a heat sink.

CAUTION

If the IC is to be saved, heat each hole individually (side 2),

~ Never attempt to remove solder from the

‘removing excess solder with a desoldering tool. Insert the

terminal points by heating and rapping the
module against another surface. This practice
can result in module or component damage.
Remove solder with a solder sucking tool or

new component, ‘bending appropriate leads. (Only leads
with tear drop lands should be bent. They should be bent in
the direction of the point.) Clip protrudmg component

leads from side 2. Do not cut flush with the board. Leads

solderwick.

and solder joints should not exceed 1/16 inch from the

When _rémdvifig any part for replacement, all leads or wires

bottom of the board.

that are unsoldered or otherwise disconnected should be

Iegibly tagged or marked for identification with their

Solder all leads
on side 2 and‘clean.flux f_rombothi Sides of

respective terminals. Always replace defective components
with parts of equal or better quality and equal tolerance.

the board with trichlorethylene, Freon, or equivalent.

4.2

(

~ DRAWING SET

This chapter contains key manufacturing drawings for the
DFC11-A. These drawings represent the levels of revision

in existence at the time of this manual’s publication.

s S SS

'MANUFACTURING

CHAPTER 5

Further revisions will not be supplied until the manual is

reprinted or revised. If in doubt about the revision of the

equipment in use, contact Digital Equipment Corporation

- for the latest revisions of drawings.

5-1

“THIS DRAWING AND SPECIFICATIONS, HEREIN, ARE THE

]

eo rernaouceson
common caemwio: | NOTES:

OFCOPYRIGHT
ITEMS WITHOUT
WRITTEN PERMISSION,
— -o
©) 1974, DIGITAL EQUIPMENT CORPORATION"

/\fl

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[

APPENDIX A
~

INTEGRATED

CIRCUIT DESCRIPTIONS

Th1s section provides diagrams, truth tables pin assignments, and some descrlptlons of the 1ntegrated circuit units usedin the
- DFC11-A loglc The ICs coveredin th1s section are:

1488

1489
74121

74123
74197

Quad Lme DI'IVCI‘S
Quad Line Receivers

‘Monostable Multivibrator
| Retrlggerable Monostable Multmbrator W1th Clear
50- MHZ Presettable Decode and Binary Counters/Latches

MC148SL QUAD LINE DRIVER

> 130

2 O—

40—

5 O—

N
| )o

o
o6

;

(TOP VIEW)

L
|

V+ 11-0486

V- =

11-0459

‘

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$8.2K
)

INPUT 4 O—j—4

5 0—q—¢
1]

INPUT

300

—\—0 6 OUTPUT

10 O—

>—08

VT 1o
.
NOTE:

174 of circuit shown.
11-0760

MC1489 QUAD LINE RECEIVERS

10—

)3 130—].

V+ -

O 14

—

”

‘

11-0486

" 11-0460

o514 V*
>

:SK
N

::ZK

p—————0 3 OUTPUT

RESPONSE

CONTROL

RF
VA

ANA

INPUT 1 o———wA

$10K

NOTE:

174 of circuit shown.
:

S
-

0 7 GROUND

A-3

1-0761

74121 MONOSTABLE MULTIVIBRATOR
Truth Table

t,Input

tnfl Input

Inhibit

Inhibit
Inhibit

-0

0 '.

One Shot

Inhibit

1= Vin(l) =2V

TIMING PINS

13| fi2 | 1]

——~

o] |9l |8

37| 4

GND

11-1863

A-4

| 74123 RETRIGGERABLE MONOSTABLE MULTIVIBRATOR WITH CLEAR -

JORN DUAL-IN-LINE OR

W FLAT PACKAGE (TOP VIEW)

Rext

~Vec "Cexi

Cext

1@
2Q

CLEAR

2B
i

‘

[__CLEAR |
Q

TRUTH TABLE

—/

I
X

X
I

|P>

INPUTS
|cLEAR[]

positive logic

Low input to clear resets Q to low

ievel and inhibits datainputs

A \\

1N1-1864

74197 50-MHz PRESETTABLE DECODE AND BINARY COUNTERS/LATCHES

J ORN DUAL-IN-LINE

W FLAT PACKAGE

(TOP VIEW)®

DATA INPUTS
r

Vec

CLEAR

_[]

. [ie]

QD.

COUNT/
LOAD

Q¢

DATA INPUTS

CLOCK
i

[s]

=]
|

COUNT/LOAD

B -

CLOCK {

Qq CLOCK 2

. : -

CLEAR

)

- Qpa
|

el 1

CLOCK
2

GND

ASYNCRONOUS INPUT: LOW INPUT TO CLEAR SETS Qp
QB,Qc AND Qp LOW.

*Pin assignments for these circuits are the same for all packages.
|

11-0482

SN74197 TRUTH TABLE

(See Note A)
- Count

Output

" H

NOTE A: Output Q4 connected to clock-2 input.

A-6

74197 50-MHZ PRESETTABLE DECODE AND BINARY COUNTERS/LATCHES (Cont)

COUNT/LOAD

CLEAR

DATA

PRESET

CLOCKi

CLE AR

t i\ ife IY

| (-

DATA B

PRESET

CLOCK
2

CLEAR

DATAC

PRESET

Q¢

CLEAR

DATAD ©

PRESET

9 Qp
Qp —

CLEAR

11-0481

A-7

DFC11-A EIA LEVEL

CONVERTER/CLOCK RECOVERY

der’s Comments

MODULE MAINTENANCE MANUAL

EK-DFC11-MM-002

Your comments and suggestions will help us in our continuous effort to improve the quality and usefulness of |
our publications;

What is your gCneral reaction to this manual? In your judgment is it complete, accurate, well organized, well
written, etc.? Is it easy to use?

CUT OUT ON DU+

ED LINE

What features are most useful?

What faults do you find with the manual?

Does this manual satisfy the need you think it was-intended to satisfy?
Does it satisfy y()ur'nccds? |

Why?

Would you please indicate any factual errors you have found.

Name ‘-

Clty

State

Organization

Zip or Country

FIRST CLASS
-

PERMIT NO. 33
MAYNARD, MASS.

BUSINESS REPLY MAIL

NO POSTAGE STAMP NECESSARY IF MAILED IN THE UNITED STATES
Postage will be pald by

Digital Equipment Corporation
Technical Documentation Department
146 Main Street

Maynard, Massachusetts 01754

DIGITAL EQUIPMENT CORPORATION
MAYNARD, MASSACHUSETTS 01754