Digital PDFs

EK-DEUNA-UG-001

May 1983

184 pages

Original

5.4MB

view download

OCR Version

6.1MB

view download

Document:	DEUNA User's Guide
Order Number:	EK-DEUNA-UG
Revision:	001
Pages:	184
Original Filename:

OCR Text

EK-DEUNA-UG-001

DEUNA

USER'S GUIDE

Prepared by Educational Services

of
Digital Equipment Corporation

ation

The information in this document is subjec
t to change without notice
and should not be construed as a commitment
by Digital Equipment
Corporation. Digital Equipment Corporation
assumes no responsibility
for any errors that may appear in this docume
nt.

Printed in U.S A.

The manuscript for this book was create
d on a DIGITAL Word
Processing System and, via a translation progra
m, was automatically

typeset on DIGITAL’s DECset Integrated
Publishing System. Book
production was done by Educational Service
s Development and

Publishing in Nashua, NH.

The following are trademarks of Digital Equipment

flfl@flflflfl

DATATRIEVE

DEC

DECmate
DEChnet

DECset

DECtape
DECUS
DECwriter

DIBOL
MASSBUS
PDP

Corporation:

Rainbow
RSTS
RSX

UNIBUS
VAX
VMS

DECsystem-10

P/0OS

DECSYSTEM-20

Professional

Work Processor

CONTENTS

SCOPE . ...

1-1
1-1
DEUNA GENERAL DESCRIPTION ...........
... .. .. .. ...
.. 1-3
DEUNA SYSTEM OPERATION ...... ... .. ... .. i, 1-5

ETHERNETOVERVIEW . ...

... .. ... ..

ETHERNET Physical Channel Functions .. ................... 1-7

ETHERNET Data Link Functions . . ......................
... 1-7
Data Encapsulation .............
... ... .. .
.. 1-7

ek
ek
ek
ek
e
i
e
ek
ek
ek prmd
ek
vk pemmk

INTRODUCTION

Data Decapsulation ...........
... ... ... ... ... . 1-8
Link Management . ............
... .iuitinniianananan.. 1-9
Functional Overview ...........
... ... ... ... ... ... 1-9
ReceiveFunction. . .........
... ... .. ... ... . ... 1-9
TransmitFunction..................
.. .. .. ... .. ... 1-10
Diagnostics and Maintenance ............................. 1-11
DEUNA SPECIFICATIONS .. ...
...
1-12
RELATED DOCUMENTS ... ... ... ..
1-13

INSTALLATION
SCOPE .. ..o 2-1
UNPACKING AND INSPECTION. . ....... ..ot 2-1
PREINSTALLATION CONSIDERATIONS ...................... 2-2
Backplane Requirements . .. ... ... ... ... ... .. ... 2-2

—

CHAPTER 2
DRNNNONNDD
PRRRLLLLN-

cbrrrrrbirbhibb-

CHAPTER 1

Bus Latency Constraints ................ ..., 2-2
Loading Requirements. . ..........
... .. ... ... ... ... ..., 2-2

PREINSTALLATION PREPARATION .. .........
... ... ... ..
.. 2-3
Backplane Power Checks and Preparation. . ................... 2-3
Device Address Assignment . ............
... .. ... ... ... ... 2-3
First DEUNA Device Address (774510).................. 2-4
Second DEUNA Device Address (Floating Address). . ... ... 2-5
Vector Address Assignment . ................oouiiiiia... 2-5
First DEUNA Vector Address (120) . .. .................. 2-6
Second DEUNA Vector Address (Floating Vector) . ........ 2-6

R
1o
-=
WD

R R RN R C
R R

o abhininninia

Boot Option Selection (PDP-11 Host Systems Only) ............ 2-7
Self-Test Loop (For Manufacturing Use) ..................... 2-7
INSTALLATION AND CABLING . ...............

ot 2-8

M7792 Port Module Installation ............................ 2-8
M7793 Link Module Installation . . ......................... 2-10
Bulkhead Interconnect Panel Assembly Installation . ........... 2-11

Cabinets Without a Cabinet Bulkhead .................. 2-11
Cabinets Witha Cabinet Bulkhead ..................... 2-13
Connectthe D-Connector ............................ 2-14
TESTING . . ... 2-14
Postinstallation PowerChecks .. ...............
... . ... ... 2-14
Light Emitting Diode (LED)Checks . .. ..................... 2-14
Diagnostic Acceptance Procedure . ......................... 2-17

iil

SERVICE

W W W

SCOPE . ...
3-1
MAINTENANCEPHILOSOPHY . ..........
.. ... ..
...
... .. 3-1
DIAGNOSTICDESCRIPTION ... ......
.. ... ...
...
... ..
.. 3-1
Self-Test. . ...
3-1
DEUNA VAX-11 Functional Diagnostic (EVDWB REV *EY L
3-4
DEUNA PDP-11 Functional Diagnostic (CZUAB*) ....
. ... ...
. 3-5
DEUNA VAX-11 Repair Level Diagnostic (EVDWA REV *
%y, . .37
DEUNA PDP-11 Repair Level Diagnostic (CZUAA*). ... ...
... 3-11
NI Exerciser (CZUAD*/EVDWCREV *.*) .
.. .. ... .. . .. 3-14
DEC/X11 DEUNA Module (CXUAC*) ................
.. ... 3-14
CORRECTIVEMAINTENANCE . ............
.. ...
....
... ..
. 3-14

W W

~NONVN
AW N —

L)W
DL
L

L0 L

WL LWL

LI N

CHAPTER 3

CHAPTER 4

PROGRAMMING

4.1

INTRODUCTION . ......
... .. ...
..... 4-1
PROGRAMMING OVERVIEW .. ... ........ ... . ... ... ...
... 4-5
PORT CONTROL AND STATUS REGISTERS ...................
4-7
Port Control and Status Register 0 (PCSRO) ..........
... . .. 4-16
PORT CONTROL BLOCK FUNCTIONS ..........
.......
... ... 4-17

4.2
4.3

4.3.1
4.4

4.4.1

442
443

4.4.4
445

4.4.6

4.4.7
4.4.8
449

4.4.10
4.4.11

4.4.12
4.4.13

4.5
4.6
4.7

4.8
4.9

4.9.1
49.2

4.9.3

494
49.4.1
4942
495

4.9.6
4.9.7
4.9.8
4.9.9

Function Code 0 — No-Operation.

. ..................
... ...
. 4-19
Function Code 1 — Load and Start Microaddress ... ............ 4-20

Function Code 2 — Read Default Physical Address ............. 4-21
Function Code 3~ No-Operation. ...............
... ... ... 4-22

Function Codes 4/5 — Read/Write Physical Address . ........... 4-22
Function Codes 6/7 — Read/Write Multicast Address List . . . . . . .. 4-24

Function Codes 10/11 — Read/Write Ring Format.

.. ........
.. 4-26
Function Codes 12/13 — Read/Read and Clear Counters . . . .. . . .. 4-29

Function Codes 14/15 — Read/Write Mode . ............
... ... 4-36
Function Codes 16/17 — Read/Read and Clear Port Status . . . . . .. 4-39
Function Codes 20/21 — Dump/Load Internal Memory.......... 4-41
Function Codes 22/23 — Read/Write System ID Parameters . . . . . . 4-44
Function Codes 24/25 — Read/Write Load Server Address . . . . . .. 4-50
TRANSMIT DESCRIPTORRINGENTRY ............
......
..., 4-52

RECEIVE DESCRIPTORRINGENTRY .. ..............
... ..
... 4-57

TRANSMIT DATABUFFERFORMAT .................
....
... 4-60
RECEIVE DATABUFFERFORMAT ..................
... ... 4-62

DEUNA OPERATION ........
... ......
... ... ..
...
..... 4-63
PowerOn ... . ... . ... . ... ... ... . .. . . . ... . ... 4-63

Port Command Capability ........................
... ...
.. 4-64
Software Initialization . ............
... ... ....
... .. ....
.. 4-66

Polling ...... ... .. . ..
4-66
Receive Polling . ................................
... 4-67

TransmitPolling .................................
.. 4-68
Datagram Reception ........................
.. ...
....
... 4-69
Datagram Transmission . . ..................
. .. ...
....
.. . 4-69
Parameter Alteration ........................
... . ... ..
.. 4-69

Suspension of Operation-Port Command ................
. ..
. 4-71
Restart of Operation..........................
...
....
... 4-71

4.9.10

DEUNA States . . ..o oo

e e 4-72

4.9.10.1

DEUNA State Related Functions . ..................... 4-72

4.9.10.2

DEUNA State Transition ...................covv.o.. 4-73

4.9.10.3

DEUNA State Information Retention . .................. 4-75
EXCEPTIONAL OPERATIONS . .. ...
4-76

4.10

4.10.1
4.10.2

Channel Loopback .. ............
... .
L 4-76
Remote Console and Down-Line Load ...................... 4-81

4.10.2.1

Remote Boot ... ... ... ...

4.10.2.2

Local Boot.

4.10.2.3

BootonPowerUp............
... ... ... .......... 4-95

4.10.2.4

Primary Load State .. ............
... .. ... ... .... 4-96

APPENDIX A

.. ...

... . . . .

. 4-88

... ... ... . .

4-95

FLOATING DEVICE ADDRESSES AND VECTORS

Al
A3

DEVICE AND VECTOR ADDRESS ASSIGNMENT EXAMPLES ... A-5

APPENDIX B

REMOTE BOOTING AND DOWN-LINE LOADING

INTRODUCTION . ... e B-1

0 W W W

SYSTEM CONFIGURATION GUIDELINES .................... B-1
REMOTEBOOTDISABLED . ...... ... ... ... ... i, B-2

REMOTE BOOT WITHSYSTEMLOAD ....................... B-2
REMOTEBOOTWITHROM

........
... .. ... ... ......... B-4

...... B-5

NETWORK INTERCONNECT EXERCISER
INTRODUCTION . ... e
e C-1
RUN-TIME ENVIRONMENT REQUIREMENTS

................ C-2

FUNCTIONAL DESCRIPTION . ....... ... ... ... ... ........ C-2

AW
—

UnattendedMode.
Build ...

. ......

...

.. ...

...

C-2
C-2

Direct Loop Message Test. . . ......................... C-2
PatternTest .. ...

.. ...

...

C-3

Multiple Message Activity Test ....................... C-4

Operator-Directed Section . . .. ............................ C4

Operator Conversation ....................coouner.... C-4
CollectIDs (Build) ..........
.. ... .. ... ... ... ... ... C-7
RequestID. ...

...

. . .

C-7

Pair-Node Testing . .. ............
.. ... ... .. ... ..... C-7
AN

L Lo L) LI L) L W L) L LW L

R —

APPENDIX C

aonoaooaononnoaonononnnn

REMOTE BOOT/POWER-UP BOOT WITH SYSTEM LOAD

NI All Node Communications Test (End-to-End).

. ........ C9

SummaryLog ........ .. ... C-10

VECTOR ADDRESS (REVB)

Uouooyu

VECTOR ADDRESS ASSIGNMENT ...,
First DEUNA Vector Address (120) .....................
...
Second DEUNA Vector Address (Floating Vector) ............
BOOT OPTION SELECTION (PDP-11 HOST SYSTEMS ONLY) ...
SELF-TEST LOOP (FOR MANUFACTURINGUSE)..............

w[\)h—d:—‘i—l

APPENDIX D

APPENDIX E

DEUNA MICROCODE ECO PROCESS

E.l1
E.2
E.3

FIGURES

Page

DEUNA to ETHERNET Connection .................coiiiiiiiiiiiiniaeennn.. 1-4
PDP-11 Host System Block Diagram . ............
... ... .. .. ... .
... 1-5
VAX-11 Host System Block Diagram . ... ........ ... ... .. .
i i 1-6
Format of an ETHERNET DataPacket . .............
... . ... ...
s, 1-8
DEUNAReceive DataPath . . ... ... ... .. . .. ... .
1-10
DEUNA Transmit DataPath . ......... ... ... ... ... ... .
1-11

0 ~-1AWN
A WM -

DEUNA Port Module Self-Test LEDs . ... ... ... e 3-2
DEUNA Troubleshooting Procedure . . ......... .. .. . i, 3-14

NNNII\)NNNN

M7792 Port Module Physical Layout .............
... .. ...
i 2-4
M7793 Link Module Physical Layout . . ...........
... ... ... .. ... ..o 2-8

N
N
e i
[

AN B

Typical Large-Scale ETHERNET Configuration ................................. 1-2

Title

Figure No.

4-2
4-3
4-4

4-6
4-7
4-8
4-10

4-11
4-12

DEUNA Cable Connection Details .. ........ ... ... ... .
Typical Module Installation . . . .......... . ... ... .

... 2-9
2-10

Bulkhead Interconnect Panel Assembly .......... ... ... ... ... oo 2-11
Bulkhead Interconnect Panel Assembly Installation . ............................. 2-12
Typical System Cabinet Bulkhead Installation .................................. 2-13
Digital ETHERNET Loopback Connector ............
... ... ... ... 2-15

DEUNA CSRs and Host Memory Data Structures . ..............
.. .. .. .ovin.., 4-6
PCSROBitFormat . . ...
e 4-10
PCSRIBitFormat . ........ ...
e 4-12
PCSR2BitFormat . ........ ...
4-14
PCSR3BitFormat . ... ... . e 4-15
Port Control Block Diagram . .......... ... ... . ... . . i 4-17
Function Code 0 —No OperationBitFormat . .. ................................. 4-19
Function Code 1 — Load and Start Microaddress Bit Format. . ...................... 4-20
Function Code 2 — Read Default Physical Address BitFormat . ..................... 4-21
Function Codes 4/5 — Read/Write Physical Address BitFormat . .................... 4-22
Function Codes 6/7 — Read/Write Multicast Address List PCBB Bit Format . .......... 4-24

Function Codes 6/7 — Read/Write Multicast Address List UDBB Bit Format. . ......... 4-26

4-21

Function Codes 10/11 — Read/Write Ring Format PCBB BitFormat . ................ 4-26
Function Codes 10/11 — Read/Write Ring Format UDBB BitFormat. . ............... 4-28
Function Codes 12/13 — Read/Write and Clear Counters PCBB Bit Format .. .......... 4-29
UNIBUS Data Block Format forCounter List. . .. ..........
... ... ... ........... 4-31
Function Codes 14/15 — Read/Write Mode PCBB BitFormat ...................... 4-35
Function Codes 16/17 — Read/Read and Clear Port Status PCBB Bit Format . ... ....... 4-39
Function Codes 20/21 — Load/Dump Internal Memory PCBB Bit Format . ............ 4-41
Function Codes 20/21 — Load/Dump Internal Memory UDBB BitFormat. . ........... 4-43
Function Codes 22/23 — Read/Write System ID Parameters PCBB Bit Format . ........ 4-44

4-23

Function Codes 22/23 — Read/Write System ID Parameters UDBB Bit Format . . ...
. ... 4-46

4-23
4-24

Transmit Descriptor Ring Entry Format . ........ ... ... ... ... ... ... ..... 4-51

4-13
4-14

4-15

4-16
4-17

4-18
4-19

4-20

4-25

4-26
4-27
4-28

Function Codes 24/25 — Read/Write Load Server Address PCBB Bit Format .......... 4-51
Receive Descriptor Ring Entry Format .. ........ .. ... .. ... . . o o oLl 4-57
Transmit Data Buffer Starting on an Even Byte Boundary ......................... 4-60
Transmit Data Buffer Starting onan Odd Byte Boundary . ...................
... ... 4-61
Receive Data Buffer Format ....... ... .. ... ... ...
4-62

vil

Port Command Sequence. ............
...
...
......
. . .. ....
...
.... 4-65
DEUNA Software Initialization Sequence ..............
..... ........... ..
4-66
Loop Message Format ................
...
....
... ......
... .. ...
.... 4-77
Loopback Message Processing Flow . ............
....
...
....
........ 4-79
Request ID Message Format ................
....
... ....
...
..... 4-83
System ID Message Format . ............
...
......
.. ......
... ...
"
. 4-85
Boot Message Format ...............
...
......
... .....
....
.
.. 4-88
Program Request Message Format .........
...
......
... ...
...
.. ..... 4-92
Memory Load with Transfer Address Message Format.
................
......
.. ... 4-98

UNIBUS AddressMap ........................
..................

N W=

—

M7792 Port Module Physical Layout ........
........
.. .. ....
... . ...
... D-2
PatchFileFormat.

NONNN

Direct Loop Message Test Example ........
........
...
....
... ....
.
C-3
Transmit Assist Loopback Testing Example ....
... ...
..
... ...
..
... .. ...
..
.. ... C-8
Receive Assist Loopback Testing Example..
...
... .....
... ...
...
... .....
.. .. C-8
Full Assist Loopback Testing Example ........
........
... ...
....... C-9
Example Test Configuration for All Node Communicatio
ns Test.. C-9

PDP-11System ...........o. ...
B-1
Remote Boot with System Load Functional Flow .. ...
...
...
...
.. ...
.... B-3
Remote Boot with System ROM Functional Flow ....
........
......
... ... B4
Power-Up Boot with System Load Functional Flow .. ...
...
... ...
...
. . B-5

[a—ry

wWww

.... A-1

....... ... ... ... . ... ... ... ... . . ...
...
E-1
DataBlock Format..............
... ....
... ... .....
.. .. ... ...
....
"
. E-2

TABLES

Title

Page

DEUNA Specifications ............
...
...
...
. ... .. ...
.. ... .... 1-12
Related Hardware and Software Documents ... ....
........
... ....
. .. . .. 1-13
DEUNAParts List .........
... ...
...
... .....
. . . . ...
...
. 2-2
DEUNAUNIBUS Loading . ........................
................... 2-3
DEUNAPower Chart ......
... ......
..
.....
..
...
..
... . ...
..
...
.. 2-3
Floating Address Assignment ............
....
.. ...
....
... .....
...
.. 2-5
Floating Vector Assignment ............
....
.. ... ...
....
... . .... 2-6
Boot Option Selection (M7792 E62 — S8 & SO
2-7
Self-Test Loop Switch (M7792E62—S10). ......
......
.. ...
...
... ...
..
2-8
DEUNA LED Indicator Functions .........
...
... ......
... ...
...
.. .. 2-16
DEUNA Diagnostics . ............
...
...
...
...
...
..
...
.~ 2-17

DEUNA Self-Test LED Codes ................
....
.....
..... 3-3
DEUNA VAX-11 Functional Diagnostic Summary (EVDW
B REV*.*) ... ... . . . . . . . 3-4
DEUNA PDP-11 Functional Diagnostic Summary (CZUAB
*) .. ..
...
..
... ...
..
. . .. 3-5
DEUNA VAX-11 Repair Level Diagnostic Summar
y (EVDWAREV * %) ... . .. . . .. 3-7
DEUNA PDP-11 Repair Level Diagnostic Summary (CZUAA
*) ... ............... 3-10

viii

4-1

43
4-4
45

DEUNA Control Functions . ......... ...

i 4-2

DEUNA Port Commands. . ......... ..

i ettt 4-2

DEUNA D ataFunctions ........ ... ...

. . i, 4-3

4-7

DEUNA Ancillary Commands .............
..
i, 4-3
Maintenance Functions . ...... ... ... .
4-4
PCSROBitDescription . .. ... .. o
e
e 4-7
PCSR 1 Bit Description . . ... ..ot
e 4-11

4-8

PCSR1 (13.08) Self-TeSt COES . . .. oottt 4-12

4.9

PCSR 2 Bit Description . . ... 4-14

4-10

PCSR3BitDescription . ......... ...

4-11

Port Control Block Bit Descriptions .. .......... ... ... .. .. 4-17

4-12

Port Control Functions . .. . ...

4-13

4-15

.. .. e 4-18

4-14

Function Code 0 — No-Operation Bit Descriptions ............................... 4-19
Function Code 1 — Load and Start Microaddress Bit Descriptions . .................. 4-20

4-15

Function Code 2 — Read Default Physical Address .. ............................. 4-21

4-16

4-17

Function Codes 4/5 — Read/Write Physical Address Bit Descriptions. . ............... 4-23
Function Codes 6/7 — Read/Write Multicast Address List PCBB Bit Descriptions.. . . . . .. 4-24

4-18

Function Code 10/11 - Read/Write Ring Format PCBB Bit Descriptions ............. 4-27

4-19

Function Code 10/11 — Read/Write Ring Format UDBB Bit Descriptions ............. 4-28

4-20

Function Code 12/13 — Read/Read and Clear Counters PCBB Bit Descriptions . . . ... ... 4-30

4-21

Function Code 12/13 — Read/Read and Clear Counters UDBB Bit Descriptions ... ..... 4-33

4-22

Function Code 14/15 — Read/Write Mode PCBB Bit Descriptions . .................. 4-36

4-23

Function Code 16/17 — Read/Read and Clear Port Status .......................... 4-39

4-24

Function Code 20/21 — Dump/Load Internal Memory PCBB Bit Descriptions. ... ... ... 4-42

4-25

Function Code 20/21 — Load/Dump Internal Memory UDBB Bit Descriptions ......... 4-43

4-26

Function Code 22/23 — Read/Write System ID Parameters PCBB Bit Descriptions . . . . . . 4-44

4-27

Function Code 22/23 — Read/Write System ID Parameters UDBB Bit Description . . . . .. 4-47

4-28

Function Code 24/25 — Read/Write Load Server Additional PCBB Bit Descriptions . . . . . 4-51

4-29

Transmission Descriptor Ring Base (TDRB) Bit Descriptions . ..................... 4-52

4-30

Receive Descriptor Ring Entry Bit Descriptions . .. .............
... ... .. ... ...... 4-58

4-31

DEUNA Self-Test Failure Results . . . ........ ... ... . ... i, 4-63
DEUNA Port Commands. . . ...t 4-64

4-32
4-33

4-34

4-35

Format of an ETHERNET DataPacket .. ............
... ... ... ... ... . ... ... 4-69
RUNNING State Parameter Alteration Impact Summary .. ..........
... ... ...... 4-70

4-37

DEUNA State Function Summary . . . ...
i
4-72
DEUNA State Transition ... ...
i
i
i 4-73
State Information Retention Summary .............
.. ... ..
. 4-75

4-36
4-38

Loopback Message Field Descriptions . ...........
... ... ... ... ... ... ...... 4-78

4-39

Boot Select Capability of the DEUNA ....... ... ... .. ...

4-40

Request ID Message Field Descriptions . ...........
... .. ... .. . oo, 4-84

4-41

System ID Message Field Descriptions ... .......... ... ... ... 4-86

4-42

Boot Message Field Descriptions . ........ ... .. .. .

4-43
4-44

Program Request Message Field Description ..........
... ... ... ... ... ...... 4-93

... . .

... 4-82

. i 4-89

Memory Load with Transfer Address Message Field Descriptions . . ................. 4-99

Floating Device Address Ranking Sequence . . ............. ... ... ... ... ... .... A-2
Floating Vector Ranking Sequence . ......... ... ... ... .. i A-3

Remote and Down-Line Load Configuration Guidelines ........................... B-2
Message Pattern Test Message Types .. ... .. C3
Operator Command Summary . . ........... ..
C-4
All Node Communications Testing Matrix .............
... ... ... ... .. .. .... C-10
Summary Information ........ ... ...
C-10

D-1

D-2
D-3

Floating Vector Assignment ......
... ....
... . ......
... ... .. ...
... .. ... D-1
Boot Option Selection (M7792 E62 —ST&SS8) ... ..o
D-3
Self-Test Loop Switch (M7792E62—S9) . ..........oo o
o D-4

EXAMPLES

Example No.
4-1
4-2

Title

Page

Writing Interrupt Bitin PCSRO ... .......... . ... ... .. .. . . . . .
.. ... 4-16
Ring Pointer Initialization . .........
... ......
... .
. ....
. . .. ... ..
...
..
4-67

CHAPTER 1
INTRODUCTION

1.1 SCOPE
This chapter introduces the DIGITAL Equipment UNIBUS Network Adapter (DEUNA), including its operation and specifications, and overviews the ETHERNET local area network. Additional documents are listed
for the reader who wishes more information about the ETHERNET, the DEUNA, or local area networks.

1.2

ETHERNET OVERVIEW

ETHERNET is a local area network that provides a communications facility for high-speed data exchange
among computers and other digital devices located within a moderately sized geographic area. It is intended

primarily for use in such areas as office automation, distributed data processing, terminal access, and other
situations requiring economical connection to a local communication medium carrying traffic at high-peak
data rates.
The primary characteristics of ETHERNET include:
e

Topology — Branching bus

Medium - Shielded coaxial cable, Manchester encoded digital base-band signaling

Data Rate (Physical Channel) — 10 million bits per second (maximum)

Maximum Separation of Nodes — 2.8 kilometers (1.74 miles)

Maximum Number of Nodes — 1,024

Network Control — Multiaccess — fair distribution to all nodes

Access Control — Carrier Sense, Multiple Access with Collision Detect (CSMA/CD)

Packet Length — 64 to 1518 bytes (includes variable data field of from 46 to 1500 bytes less 8-byte
preamble).

The ETHERNET falls into a middle ground between long-distance, low-speed networks that carry data for

hundreds or thousands of kilometers and specialized high-speed interconnections generally limited to tens of
meters. Using a branching bus topoloy, ETHERNET provides a local area communications network allowing
a 10M bits/s data rate over a coaxial cable at a distance of up to 2.8 km (1.74 mi).

1-1

A single ETHERNET can connect up to 1,024 nodes for a local point-to-point/multipoin
example of a typical large-scale ETHERNET configuration is shown in Figure 1-1.

t network. An

TRANSCEIVER CABLE

[ ]

seGMENT 1 [[J——
—]

NODE

TRANSCEIVER

::JSEGMENT 2

rereater

]

SEGMENT 3
=

COAXIAL
CABLE

||
REMOTE

REPEATER

POINT-TO-PO

LINK (1Tooo M":ATAX)

|—

jC>_[:] SEGMENT &
SEGMENT 4['_'

—{]]
—{

Figure 1-1

TK.9817

Typical Large-Scale ETHERNET Configuration

To configure ETHERNET, certain limits are imposed on the physical channel to ensure the optimal per-

formance of the network. The maximum configuration for an ETHERNET is as follows:
®

A segment of coaxial cable can be a maximum of 500 meters (1640.5 feet) in length. Each
segment must be terminated at both ends in its characteristic impedance.
Upto 100 nodes can be connected to any segment of the cable. Nodes on a cable segment must

be spaced at least 2.5 meters (8.2 feet) apart.

1-2

The maximum length of coaxial cable between any two nodes is 1,500 meters (4921.5 feet).

The maximum length of the transceiver cable between a transceiver and a controller is 50 meters
(164.05 feet).

NOTE
In addition to internal cabling between the DEUNA

and its bulkhead assembly, the DEUNA will support an additional 40 meters of transceiver cable.
¢

A maximum of 1,000 meters (3281 feet) of point-to-point link is allowed for extending the
network.

Repeaters can be used to continue signals from one cable segment of the ETHERNET to another.
A maximum of two repeaters can be placed in the path between any two nodes.

1.3

DEUNA GENERAL DESCRIPTION

The DEUNA is a data communications controller used to interface VAX-11 and PDP-11 family computers to

the ETHERNET local area network. Features of the DEUNA include:

High speed transmission and reception

10M bit data rate

Transmit and receive data link and buffer management

Data encapsulation and decapsulation

Data encoding and decoding

Collision detection and automatic retransmission

32-bit Cyclic Redundancy Check (CRC) error detection

32 KB (16 KW) buffer for datagram reception transmission, and maintenance requirements

Down-line loading and remote load detect capabilities

Internal ROM based microdiagnostics to facilitate diagnosis and maintenance of both the
DEUNA-AA and the DIGITAL H4000 transceiver

Unique 48-bit Default Physical Address (reprogrammable)

1-3

The DEUNA has two hex-height modules, a bulkhead interconnect panel, and associated cables. It physical-

ly and electrically connects to the ETHERNET cable via the DIGITAL H4000 transceiver and the appropriate
transceiver cable as shown in Figure 1-2.

BNE2x ETHERNET

COAXIAL CABLE

BNE3x-xx

H4000

TRANSCEIVER

ETHERNET

TRANSCEIVER
CABLE
DEUNA

BULKHEAD

PANEL

SURGE
CURRENT
LIMITER

L/
.

M,
W )S
S W
,¢
L1

{—

/////// /

///////////

)T e

M7793

MODULES
(2)

-l

[

M M 1

[

HOST SYSTEM
TKA818

Figure 1-2

DEUNA to ETHERNET Connection

1-4

1.4

DEUNA SYSTEM OPERATION

The DEUNA controller performs both the ETHERNET data link layer functions and a portion of the physical

channel functions. It also provides the following network maintainability features.
®

Loopbacks maintenance messages from other stations.

Periodically transmits system identification.

Loads and remotely boots UNIBUS systems from other stations on the network.

The DEUNA is a microprocessor-based device that, when connected to the DIGITAL H4000 ETHERNET
transceiver, provides all the logic necessary to connect VAX-11 and UNIBUS PDP-11 family minicomputers
to an ETHERNET local area network (Figures 1-3 and 1-4). The controller performs data encapsulation and

decapsulation, data link management, and all channel access functions to ensure maximum throughput with
minimum host processor intervention.

M7792
PORT

MODULE

M7793

H4000

LINK

MODULE

ETHERNET

TRANSCEIVER

DEUNA

BULKHEAD

PANEL

TK-9816

Figure 1-3

PDP-11 Host System Block Diagram

1-5

Ndd

d31dvav

WIW "LNOD -

IT1NAOW

CBLLN
1H0d

XSNEVSAYN SNWI3SINYIN 21ndig-1[-XVA10HwaIsAgJolgweIgerq
SNAINN
431dvav

3IINAOKW

E6LLN

VYNN3Q
avaHdINg
T13ANVYd

SL86"ML

ANIT

SN8INN

w 7]

1-6

1.4.1

ETHERNET Physical Channel Functions

The DEUNA provides the following specific ETHERNET physical channel functions necessary to interface
to the DIGITAL H4000 ETHERNET transceiver:
During Transmission

Generates the 64-bit preamble for synchronization.

Provides parallel-to-serial conversion of the frame.

Generates the Manchester encoding of data.

Ensures proper channel

access

by monitoring

and

sensing the carrier from any stations’

transmission.
®

Monitors the self-test collision detect signal from the DIGITAL H4000 transceiver.

During Reception
®

Senses carrier from any station’s transmission.

Performs Manchester decoding of the incoming bit streams.

Synchronizes to the preamble and removes it prior to processing.

Provides serial-to-parallel conversion of the frame.

Buffers received packets.

1.4.2 ETHERNET Data Link Functions
The DEUNA provides the following specific ETHERNET data link layer functions:

1.4.3

Calculates the 32-bit CRC value and places it in the packet sequence field upon transmission.

Attempts automatic retransmission upon collision detection.

Checks incoming packets for proper CRC value.

Performs address filtration.

Data Encapsulation

The ETHERNET packet format is shown in Figure 1-5. Each packet begins with a 64-bit preamble used for
synchronization by the receiving station, and ends with a 32-bit packet check sequence. Packets are separated
by a specified minimum spacing period of 9.6 us.

The destination address field contains the address(es) of the station(s) where the packet is sent. The address
may represent: the unique or physical addresses of a particular station; a multicast, or group address, associ-

ated with a set of stations; and a broadcast address for all stations on the network.

The source address field specifies the physical address of the transmitting station. Each DEUNA has a unique
48-bit address value determined during manufacture. This value is called the default physical address. The

system software can override this value and assign a different physical address.

1-7

PREAMBLE/ | DEST.

STARTBYTE|

SOURCE

ADDRESS | ADDRESS

TYPE

FRAME

DATA

CHECK [ INTERFRAME |

SEG.

SPACING

_____!

8BYTES

6BYTES

Figure 1-5

6BYTES

2BYTES

46 TO 1500 BYTES

4BYTES

9.6 us

Format of an ETHERNET Data Packet

The type field is specified for use by high-level network protocols. It indicates how the content of the data

field is to be interpreted. The type field is used by higher-level architecture to further decapsulate the data.

The data field may have between 46 and 1500 bytes of data. The DEUNA can be initialized to automatically
insert null characters if the amount of data is less than the minimum 46-byte data size.

The packet check sequence contains a 32-bit Cyclic Redundancy Check (CRC) value determined and inserted
by the DEUNA during transmission.

1.4.4 Data Decapsulation
The DEUNA continuously monitors the signals transmitted by the DIGITAL H4000 transceiver. After sens-

ing a carrier, the preamble sequence of the received packet is used by the controller for synchronization. It

then processes the destination address field through a hardware comparator to determine whether or not the

incoming packet is intended for its station. The DEUNA accepts only packets with a destination address that
matches one of the following types of address:
1.

The physical address of the station

The broadcast address for all stations

One of the ten multicast group addresses the user may assign to the DEUNA, when desired

Any multicast address, when desired

All addresses, when desired

The DEUNA performs a hardware comparison of the 6-byte destination address to determine if there is a

match with the station’s physical address or with one of the ten user-designated multicast addresses. If neces-

sary, all multicast addresses may be passed to higher-level software for decoding when more than ten multicast address groups are required by the user.

To assist in network management functions and fault diagnosis, the DEUNA can operate in a mode that
effectively disregards the internal address filter logic. This allows all packets received from the network to be
accepted. The DEUNA verifies the integrity of the received data by performing a 32-bit CRC check on the

received packet.

1-8

1.4.5 Link Management
The method by the ETHERNET for channel access is called carrier sense, multiple access with collision,

detect (CSMA/CD). The DEUNA controls all of the link management functions necessary to successfully
place or remove a packet of data on the ETHERNET network. These functions include:

Carrier Deference — The DEUNA monitors the physical channel for traffic. When the channel is
busy, it defers to the passing packet by delaying any transmission of its own.

Collision Detection — Collisions occur when two or more stations attempt to transmit data simul-

taneously on the channel. The DEUNA monitors the collision sense signal generated by the
DIGITAL H4000 transceiver. When a collision is detected, the DEUNA continues to transmit

long enough to ensure that all network stations detect the collision.

Collision Backoff and Retransmission — When a controller attempts transmission and encounters
a collision on the channel, it attempts a retransmission a short time later. The schedule for retrans-

mission is determined by a controlled randomization process. The DEUNA attempts to transmit a

total of sixteen times and reports an error if it is not successful.

1.4.6 Functional Overview
The DEUNA is a microprocessor-controlled interface between the UNIBUS (host memory) and the
ETHERNET. It has two basic functions: Receive and Transmit.
1.4.6.1
Receive Function — Figure 1-6 shows the data path through the DEUNA for the receive function.
The data travels through the DEUNA as follows:
1.

Data from the ETHERNET is received by the LINK which:

Performs Manchester decoding of data

Decapsulates data

Filters address

Converts serial to parallel data

Checks CRC

Moves data to local memory and notifies T11 that there is a message to be sent to host
memory

When the message is in local memory, the T11 microprocessor gets the starting address of where
the message is to go in host memory and sets up the DMA engine.

The DMA engine moves the message to host memory.

After data is moved the T11 informs the host of the message.

1-9

l- DEUNA
l

—

TN
HOST
PROCESSOR

;

UNIBUS
LINK

MEMORY

CEIVERS

~*1 ENGINE
DMA

—
Figure 1-6

1.4.6.2

TRANS-

UNIBUS

-~
DEUNA

TK-10025

Receive Data Path

Transmit Function - Figure 1-7 shows the data path through the DEUNA for the transmit func-

tion. The data travels through the DEUNA as follows:
1.

The host processor notifies the T11 that there is a message the host wants transmitted on the
ETHERNET.

The T11 moves the message from host memory to local memory via DMA and tells the link there

is a message to be transmitted.

The link transmits the message by doing the following:

Generates the preamble.

Performs parallel-to-serial conversion.

Generates CRC.

Performs manchester encoding of data.

Transmits the message.

If there is a collision on the ETHERNET, attempts to re-transmit the message up to 15 times.

The T11

notifies the host when the message has been transmitted.

1-10

DEUNA

ped T11

HOST
,

LINK

-»|

UNIBUS

MEMORY

TRANS-

CEIVERS

PROCESSOR

9
@

5
DMA

1 ENGINE

TXK-10024

Figure 1-7

DEUNA

Transmit Data Path

1.4.7 Diagnostics and Maintenance
The DEUNA utilizes both microdiagnostics and extensive system and network diagnostics to greatly mini-

mize the time to isolate and diagnose a network communication fault. On-board self-test microdiagnostics

automatically test the major DEUNA component logic both on powerup and at the user’s discretion. Lightemitting diodes on the edge of the port module (M7792) indicate a specific module problem.

The DEUNA does not transmit longer than the maximum ETHERNET packet transmit period. It contains an

automatic control to prevent monopolizing the ETHERNET channel. A built-in Time Domain Reflectometry
circuit is provided to help find the location and nature of cable faults.
The controller continuously monitors the power applied to the DIGITAL H4000 transceiver to ensure compli-

ance with the tranceiver requirements. In addition, the H4000 provides a positive functional verification
(heartbeat) after every attempted transmission which indicates its proper operation, including the collision
sense circuitry.

Comprehensive system diagnostics provide loopback capability through the DEUNA, transceiver, or the

ETHERNET network itself. The DEUNA allows remote stations to loopback once it has successfully passed
the on-board self-test microdiagnostic. This provides both a local and remote station diagnostic capability.
Network error conditions are detected and statistics tabulated for use by higher level network management

applications.

1.5

DEUNA SPECIFICATIONS

Table 1-1 lists the DEUNA specifications.

Table 1-1

DEUNA Specifications

Specification

Description

Operating Mode

Half-duplex

Data Format

ETHERNET specification

Date Rate (Physical Channel)

10M bits/s

Network Specifications

1024 stations maximum

UNIBUS Bus Loading
Module Pair

1 dc loads

4 ac loads
DC Power Requirements
Port Moduie
Link Module

+5V,70A
+5V,90A
—15V, 1.0 A (for H4000 transceiver)

Physical Size
Port and Link Modules

Height (hex): 21.4 cm (8.4 in)
Length: 39.8 cm (15.7 in)

Cable Interface Panel

Height: 10.6 cm (4.0 in)
Length: 10.6 cm (4.0 in)

Operating Environment

Temperature

10°C to 40°C (SOOF to 104°F)

Relative Humidity

10 to 90% (noncondensing)

Wet Bulb Temperature

28°C (82°F) maximum

Dew Point

29C (36°F) minimum

Altitude

Sea level to 2.4 km (8,000 ft)

Shipping Environment

Temperature

—40°C to 66°C
(—40°F to 151°F)

Relative Humidity

0 to 90% (noncondensing)

Altitude

Sea level to 9 km (30,000 ft)
1-12

1.6 RELATED DOCUMENTS
Table 1-2 lists related documents.

Table 1-2

Related Hardware and Software Documents

Title

Document Numbers

MICRO T-11 Microprocessor User’s Guide

EK-DCT11-UG

H4000 Technical Description

EK-H4000-TM

The ETHERNET, A Local Area Network, Data Link Layer, and
Physical Layer Specifications

AA-K759A-TK

ETHERNET Installation Guide

EK-ETHER-IN

Introduction to Local Area Networks

EB-22714-18

DEUNA Maintenance Print Set

MP-10378

DIGITAL personnel may order hardcopy documents from:

Digital Equipment Corporation
444 Whitney Street
Northboro, MA 01532
Attn: Publishing and Circulation Services (NRO3/W3)
Order Processing Section

Customers may order hardcopy documents from:
Digital Equipment Corporation

Accessories and Supplies Group
Cotton Road
Nashua, New Hampshire 03060
For information call: 1-800-257-1710

Information concerning microfiche libraries may be obtained from:
Digital Equipment Corporation
Micropublishing Group (BUO/E46)
12 Crosby Drive
Bedford, MA 01730

1-13

CHAPTER 2
INSTALLATION

2.1

SCOPE

This chapter provides the necessary information and procedure for installing a DEUNA in a PDP-11 or
VAX-11 host system. The chapter is divided into the following sections.

Unpacking and Inspection — Verify that shipment is complete and undamaged.

Preinstallation Considerations — Verify that the host system meets the installation requirements of
the DEUNA.

Preinstallation Preparation — Prepare the host system and the DEUNA subsystem for proper
operation.

Installation and Cabling — Install and cable the DEUNA in the host system.

Testing — Verify that the DEUNA and the host system are operating correctly.
2.2

UNPACKING AND INSPECTION

Unpacking a DEUNA subsystem consists of removing the equipment from its shipping containers, verifying
that there are no missing parts, and inspecting the equipment for damage. Report any damages or shortages to
the shipper and notify the DIGITAL representative.
1.

Before opening the shipping containers, check them for external damage such as dents, holes, or
crushed corners.

Open and unpack each container. Inventory the contents against the shipping list. Table 2-1 lists
the parts supplied with each DEUNA subsystem.
NOTE

Shipping containers and packing materials should
be retained if reshipment is contemplated.

Inspect each DEUNA part for shipping damage. Check the modules carefully for cracks, breaks,
or loose components such as socketed chips.

2-1

Table 2-1

DEUNA Parts List

Description

Part Number

DEUNA Port Module

M7792

DEUNA Link Module

M7793

Module Interconnect Cable

BCOSR-1 (2)

Bulkhead Cable Assembly

70-18798-08

Bulkhead Interconnect Panel Assembly

70-18799-00

DEUNA User’s Guide

EK-DEUNA-UG

2.3
PREINSTALLATION CONSIDERATIONS
The following factors should be considered before installing a DEUNA to verify that the host
system can
accept the DEUNA and that it can be installed correctly.

2.3.1
Backplane Requirements
The DEUNA requires two hex-height, Small Peripheral Controller (SPC) slots that can be configured
for
Nonprocessor Request (NPR) operation. Two adjacent slots are preferred, but not necessary. Any
SPC backplane (DD11-B(REV E) or later) can accept the DEUNA modules. The DEUNA can be placed anywhere
on
the UNIBUS before all UNIBUS repeaters.

2.3.2

Bus Latency Constraints

Bus latency is an important factor in determining where to place the DEUNA in the backplane.

On systems
with many high-speed Direct Memory Access (DMA) devices, the bus latency may adversely
affect the
DEUNA’s performance.

To obtain optimum performance, select a backplane location that places DEUNA on the UNIBUS

bus before
all devices with a lower NPR rate and before all UNIBUS repeaters. The closer the physical placement of the

DEUNA to the processor, the higher its DMA device priority. If optimum performance is not a

factor, the
DEUNA can be installed anywhere on the UNIBUS (before all repeaters) that meets the requirements of the

system. Reconfigure the system as necessary to provide the DEUNA with backplane slots at the selected
UNIBUS location for the desired performance.

2.3.3

Loading Requirements
Make sure that system loading capacities are not exceeded as a result of installing the DEUNA subsystem.

Tables 2-2 and 2-3 list the UNIBUS loading and power supply current requirements
of the DEUNA,

respectively.

NOTE
Check power supply voltages before and after
installation to verify that no overvoltage or over-

loading conditions exist.

2-2

Table 2-2

DEUNA UNIBUS Loading

Modules

UNIBUS DC Loads

UNIBUS AC Loads

M7792 & M7793 (combined)

Table 2-3

DEUNA Power Chart

Maximum

Minimum

Backplane

Voltage

Module

Voltage Rating

M7792

+ 5 Volts @ 7.0 A

+ 5.25 Volts

+ 4.75 Volts

CA2

M7793

+ 5 Volts @ 9.0 A

+ 5.25 Volts

+ 4.75 Volts

CA2

-15 Voits @ 1.0 A

-15.75 Volts

-14.25 Volts

FB2

(for H4000 Transceiver)

PREINSTALLATION PREPARATION

2.4

Prepare the host system and DEUNA subsystem for proper operation using the following procedure.
2.4.1

Backplane Power Checks and Preparation

Perform the following operations on the backplane slots previously selected for DEUNA module installation.
1.

With system power OFF, conduct resistance checks on the backplane voltage sources to ground to

Turn system power ON. Verify that backplane voltages are within specified tolerances. Refer to
Table 2-3 for the voltage ranges and backplane pin assignments. Turn system power OFF-.

If present, remove the grant continuity modules.

If present, remove the Nonprocessor Grant (NPG) jumper wire that runs between backplane pins

be sure that no short circuit conditions exist.

CA1 and CBI1 on the slot selected for installation of the M7792 port module.
NOTE

If the M7792 port module is removed from the system, be sure to either replace the NPG jumper wire
and install a G727 single-height grant module, or
install a G7273 dual-height grant module.
2.4.2

Device Address Assignment

Assign the DEUNA a device address from the Input/Output (1/0) page of memory address space. The first
DEUNA being installed in a system must be assigned the address 774510. For the second, and any subse-

quent DEUNA being installed in the same system, the device address must be selected from the floating
address space of the /O page. The device address is assigned by configuring switch pack E40 on the M7792

port module to the desired address.

2-3

2.4.2.1
First DEUNA Device Address (774510) — Assign device address
774510 to the first DEUNA
being installed in a system by configuring switch pack E40 on
the M7792 port module as shown below. Note
that this address could overlap the twenty-third (2379) DPI11
if present in the system. Refer to Figure 2-1 for
the location of E40 on the M7792 module.

M7792 - E40
S1

S10

OFF

NOTE
An OFF (open) switch responds to a logical one 1)

on the bus.

SELFTEST

CABLE

STATUS

VERIFY

INTERCONNECT

LEDs

LED

CABLE JACKS

MODULE

/
J2

E40

£62

0002000000

SWITCH PACK E62

SWITCH PACK E40

SWITCH OFF (OPEN) = LOGICAL 1

—— ve

012345673910

012345678910

0
£

0
F

L seLFTEST
LOOP

VECTOR ADDRESS

A12

BOOT SEL O

SELECTION

I
I

DEVICE ADDRESS
SELECTION

BOOT SEL 1

TK-10029

Figure 2-1

M7792 Port Module Physical Layout

2.4.2.2

Second DEUNA Device Address (Floating Address) — Assign a device address to the second (or

subsequent) DEUNA being installed in a system by configuring switch pack E40 on the M7792 port module

to the desired address determined from the floating address allocation. Refer to Table 2-4 for the correlation
between switch number and address bit. The ranking device address assignment of the DEUNA is twentyfive (25). Refer to Appendix A for more information on floating address allocation.

Table 2-4

Floating Address Assignment

MSB

LSB

414

(13

SWITCH
NUMBER

1211

|10 ] 9

716

514

SWITCH PACK E40

S10§

S9 | S8 [ S7

|S6 | S5 | S4 | S3

|S2 | S
ofFf}

010

FLOATING
ADDRESS
760010

OFF

760020

OFF|OoFF]
OFF
ofr|
OFF
OFF|oFF
oFF|oFF{oFF]

760030
760040
760050
760060
760070

OFF

760100

OFF
OFF|OFF

760200
760300

lore

OFF

760400

OFF

765500

OFF{OFF

760600

OFF|OFF|OFF

760700

OFF
OFF

761000
762000

OFF|OFF

763000

OFF

764000

NOTE: SWITCH OFF (OPEN) RESPONDS TO LOGICAL ONE ON THE UNIBUS.
TK-9760

2.4.3

Vector Address Assignment
NOTE

For M7792 Revision B modules, refer to Appendix
D of this guide.

Assign the DEUNA a vector address from the reserved vector area of memory address space. The first
DEUNA being installed in a system must be assigned the vector 120. The second (and any subsequent)
DEUNA being installed in the same system must select the vector address from the floating vector area of
reserved vector address space. The vector address is assigned by configuring switch pack E62 on the M7792
port module to the desired vector.

2-5

2.4.3.1

First DEUNA Vector Address (120) — Assign vector address 120 to the first DEUNA in the system by configuring S1-S7 of switch pack E62, on the M7792 port module, as shown below. Note that this
vector is also used by the XY 11. Refer to Figure 2-1 for the location of E62 on the M7792 module.

M7792 - E62

OFF

NOTE
An OFF

(open) switch produces a logical one (1) on

the bus.
2.4.3.2

Second DEUNA Vector Address (F loating Vector) — To assign a vector address to the
second (or
subsequent) DEUNA, configure S1-S7 of switchpack E62 on the M7792 port module
to the desired vector
determined from the floating vector allocation. Refer to Table 2-5 for the correlation between
switch number
and address bit. The ranking vector address assignment of the DEUNA is forty-seven (47).
Refer to
Appendix A for more information on floating vector allocation.

Table 2-5

114113112

]11

Floating Vector Assignment

[10

}o9

ojoflo|lolo]o

|o8

[07

|os

|05

|04

SWITCH PACK E62

Jo1

|00

0o1]o

|
SWITCH

|02

|87

|[s6

|[s5

|s4|s3|

s2]s1

NUMBER

|FLOATING

VECTOR

OFF|

OFF

OFF|

OFF

OFF|
OFF|

304

OFF

310

OFF

OFF|OFF|

314

OFF|

324

OFF|

OFF

OFF|

OFF

OFF|

OFF

OFF|

OFF

OFF|

OFF

OFF|

OFF

OFF|{

320
330
OFF|

334
340

OFF|

OFF

OFF|

344

OFF | OFF|

OFF

350

OFF | OFF|

OFF

OFF|OFF|

354

OFF|

OFF | OFF

OFF|

OFF | OFF

OFF|

OFF | OFF | OFF|

OFF

OFF|

OFF | OFF | OFF|

OFF|OFF|

OFF

360

OFF|

364
370
374

400

OFF

OFF | OFF
OFF

300
OFF|

|OFF|

500

600
OFF

700

TK-10019

2-6

2.4.4

Boot Option Selection (PDP-11 Host Systems Only)

The DEUNA provides for remote booting and down-line loading of PDP-11 family host systems. These functions are switch selectable via two boot option select switches located on switch pack E62 on the M7792 port

module.

NOTE
Refer to Appendix B for additional information on
DEUNA remote booting and down-line loading.
When installing a DEUNA in a PDP-11 family host system, configure switches S8 and S9 on switch pack
E62 (M7792 module) for the boot function desired. Table 2-6 lists the switch settings and corresponding boot

option functions. Refer to Figure 2-1 for the location of E62 on the M7792 module.
When installing a DEUNA in a VAX-11 family host system, set both S8 and S9 on E62 (M7792 module) to

the ON (disabled) position of the switch.
NOTE
An OFF (open) switch produces a logical one (1).

This is the ENABLED state of the switch function.

Table 2-6

Boot Option Selection (M7792 E62 - S8 & S9)

BOOT SEL 1

BOOT SEL 0

Function

ON*

Remote boot disabled

OFF

Remote boot with system load

OFF

Remote boot with ROM

OFF

Remote boot with power up boot and
system load

Switch settings for a DEUNA installed in a VAX-11 system.

2.4.5

Self-’f@& Loop (For Manufacturing Use)
NOTE
For M7792 Revision B modules, refer to Appendix
D of this guide.

The self-test loop is provided on the DEUNA for manufacturing testing. This is a switch-selectable feature
that allows the on-board self-test diagnostic program, once it is initiated, to continuously loop on itself. This

feature is controlled by S10 on switch pack E62 on the M7792 port module and should be disabled during

installation.

When installing a DEUNA, disable the self-test loop feature by setting S10 on switch pack E62 (M7792 mod-

ule) to the ON (closed) position, as indicated in Table 2-7. Refer to Figure 2-1 for the location of E62 on the
M7792 module.

2-7

Table 2-7

Self-Test Loop Switch (M7792 E62 - S10)

Position

Function

ON* (closed)

DISABLED

OFF (open)

ENABLED

Switch setting for normal operation

2.5

INSTALLATION AND CABLING
Install and cable the DEUNA component parts in the host system using the following procedure.

2.5.1

MT7792 Port Module Installation

Locate the two BCO8R-1 module interconnect cables supplied.

Plug one end of one of the cables into J1 on the M7792 module. Plug one end of the second cable

into J2. Refer to Figure 2-2 for the physical layout of the M7792 port module and Figure 2-3 for

cable connection details.

NOTE
BCO08S-1 cables may be substituted for BCOSR-1

cables. No restrictions exist regarding alignment of
the BCO8R-1 (or BC08S-1) cables with J1 and J2.
Neither the cables nor the jacks are keyed.

MODULE

INTERCONNECT
BULKHEAD

CABLE JACKS

Lr’lr’lr’lr’Lr‘LI

TK-9759

Figure 2-2

M7793 Link Module Phy

sical Layout

2-8

BERG

BULKHEAD

CONNECTOR

BULKHEAD

CABLE ASSEMBLY

INTERCONNECT

PANEL ASSEMBLY

D-CONNECTOR

MODULE
INTERCONNECT

CABLES
TK-9756

Figure 2 3

DEUNA Cable Connection Details

2-9

Carefully insert and secure the M7792 port module into the SPC backplane slot previously select-

ed (Figure 2-4).

LINK MODULE

(M7793)

PORT MODULE
{M7792)
\ \

“~

TO DEUNA BULKHEAD ASSY

STRIPED EDGE (REF.)

ANY SPC BACKPLANE SUCH AS —_—
THE DD11B.

NOTE:

REMOVE THE NPR JUMPER (CA1TO CB1) BEFORE

THE PORT MODULE (M7792) IS INSTALLED. THIS
JUMPER MUST BE INSTALLED IF THEDEUNA IS
REMOVED FROM THE SYSTEM.

THE ORDER OF MODULE INSTALLATION IN THE
BACKPLANE IS NOT FIXED.

POWER:

+5VDC@ 16A

—-15vDCe@ 1A
TK-10112

Figure 2-4

2.5.2
1.

Typical Module Installation

M?7793 Link Module Installation
Slide the M7793 link module into the module guides of a slot adjacent to the M7792 port module.
DO NOT insert or secure the module all the way into the slot at this time (Figure 2-4).

Connect the two BCO8R-1 bus cables from J1 and J2 on the port module to J1 and J2 on the link

module. There should be NO TWISTS in these cables. Refer to Figure 2-2 for the physical layout

of the M7793 module and Figure 2-3 for cable connection details.

2-10

Locate the bulkhead cable assembly supplied (P/N 70-18798-00) and carefully plug the BERGT
connector end into J3 on the link module. Do NOT force the connector into the jack. Both the con-

nector and jack are keyed and may be connected together only when aligned correctly.
4.

Carefully slide the M7793 link module all the way in to the backplane slot and secure it. Fold each

of the BCO8R-1 cables against the component side of either the port or link module to allow the
cables to fit inside of the mounting box.
5.

Route the bulkhead cable assembly through the cabinet cable ways to the back section of the sys-

tem cabinet.
NOTE
Make sure that all cables are seated properly.

2.5.3

Bulkhead Interconnect Panel Assembly Installation

The Bulkhead Assembly (P/N 70-18799-00) supplied with the DEUNA may be mounted in host system
cabinets with or without a cabinet bulkhead.

2.5.3.1

Cabinets Without a Cabinet Bulkhead /

Secure the bulkhead panel to the bulkhead bracket, as shown in Figure 2-5, using the four (4) cap-

tive screws.

-15V

-15v

STATUS LED

CIRCUIT
BREAKER

"
BRACKET __—
MOUNTING

SLOTS

BULKHEAD

BRACKET

BULKHEAD

PANEL

SLOT-HEAD

CAPTIVE

SCREW
(10F 4)

Figure 2-5

Bulkhead Interconnect Panel Assembly

BERGTM is a trademark of Berg Electronics.

TK-9757

Select a mounting location at the back of the system cabinet with no obstructions. The entire bulk-

head assembly should be mounted on the cabinet frame (Figure 2-6).

CAUTION
The back of the bulkhead panel contains a circuit
board which carries —15 V. Be sure this circuitry
will not be touching anything that could cause a
short circuit on power-up.

BULKHEAD
INTERCONNECT
PANEL

ASSEMBLY

CAB UPRIGHT ~al

TM~ TO LINK MODULE
(M7793)

FROM

TRANSCEIVER /[

\ 5

\
TK-10109

Figure 2-6

Bulkhead Interconnect Panel Assembly Installation

Align the two bulkhead bracket mounting slots (Figure 2-5) with the cabinet frame holes at the
selected location and attach two Tinnerman nuts to the cabinet frame at these locations.

Secure the bracket to the cabinet frame with two 10 X 32 screws.

2-12

2.5.3.2

Cabinets With a Cabinet Bulkhead —

Mount the bulkhead panel to an available I/O cutout on the cabinet bulkhead (Figure 2-7).

Secure the bulkhead panel to the cabinet bulkhead with the four captive screws.

CAB UPRIGHT

FRAME LOWER

1/0

TO LINK MODULE (M7993)

BULKHEAD
PANEL

FROM TRANSCEIVER

Figure 2-7

Typical System Cabinet Bulkhead Installation

2-13

2.5.3.3

Connect the D-Connector — Connect the D-connector on the bulkhead cable

back (component side) of the bulkhead panel circuit board as shown in Figure 2-3.

together by sliding the latch assembly located on J1 to the lock position.

2.6

assembly to J1 on the

Secure the connector and

TESTING

Perform the following system tests to verify that the DEUNA and the host system are operating

correctly.

NOTE
An operational ETHERNET transceiver, or loop-

back connector, must be connected to the DEUNA
for

the

self-test

microdiagnostics

run

successfully.

An H4080 loopback test transceiver is not supplied

with the DEUNA option. Digital personnel may
obtain the H4080 through their local Digital Field
Service Branch office. Customers may obtain the
H4080 through
Representative.
2.6.1

their local

Digital

Sales

Postinstallation Power Checks

Perform the following tests on the backplane slots that contain the DEUNA modules.

Conduct resistance checks on the backplane voltage sources to ground to be sure that no short circuit conditions exist. Refer to Table 2-3 for backplane pin assignments.

Tumn system power on and verify that backplane voltages are within the specified tolerances listed

in Table 2-3.

2.6.2

Light Emitting Diode (LED) Checks
Eight LEDs are provided on the DEUNA to aid in determining the operational status of the subsystem. Seven

of these LEDs are located on the M7792 port module (Figure 2-1); the eighth is located on the bulkhead interconnect panel (Figure 2-5). Refer to Table 2-8 for a summary of the LEDs and their function.

Connect either an ETHERNET transceiver or a DIGITAL ETHERNET Loopback Connector
(Figure 2-8) to J2 on the bulkhead interconnect panel (Figure 2-5).

Apply system power and wait at least 10 seconds to allow the self-test diagnostics to complete.

Check the LEDs on the Port module and make sure they cycle ON and OFF. This indicates that the

DEUNA sub-tests are running.

2-14

2-15

NOTE
If power-up boot is enabled, self-test will not run
and all LEDs will be ON.

Check LEDs D1 — D7 on the M7792 port module and verify that they are all lit (ON).

Check LED D1 on the bulkhead interconnect panel and verify that it is lit (ON).

Table 2-8

DEUNA LED Indicator Functions

Location

LED

Function

M7792 Module

When lit (ON), verifies that the two module interconnect cables are
properly connected to J1 and J2 on both the port and link modules.

M7792 Module

D2 -D7

Visually indicates the current status of the ROM-based self-test
microdiag- nostics. All LEDs are lit (ON) following successful completion of the self-test.
The self-test microdiagnostic program is initiated each time the
DEUNA is powered-up, and takes about 10 seconds to run. During this
period, these LEDs blink rapidly as the various functions of the
DEUNA are tested.

NOTE
If DEUNA power-up boot is not enabled and the LEDs

do not blink, refer to Chapter 3.

When the DEUNA protocol enters the run state under system software,
LED D7 blinks ON and OFF at a one second rate (approximate). For
more information on the self-test microdiagnostics, see Chapter 3.
Bulkhead Panel

Indicates that -15 V transceiver power is available at bulkhead connector J2. This verifies that
1.

The bulkhead cable assembly is properly connected at both ends,

and
2.

The bulkhead interconnect panel circuit breaker is properly set.

2-16

2.6.3

Diagnostic Acceptance Procedure

The final step in the DEUNA installation procedure is to exercise the M7792 Port module and the M7793
Link module as one complete unit on the UNIBUS bus and on the ETHERNET cable (if possible).
If an ETHERNET transceiver and transceiver cable are available, perform the following steps:

Connect and lock one end of the transceiver cable to J2 on the bulkhead interconnect panel (Figure
2-5).

Refer to Table 2-9 and run the appropriate PDP-11 or VAX-11 diagnostic programs (depending on
the type of host system). Run the diagnostics in the order listed. When each diagnostic program
has run a minimum of five error-free passes, proceed to the next step.

Table 2-9

DEUNA Diagnostics

Diagnostic

PDP-11

VAX-11

Repair

CZUAA#* - Standalone

EVDWA REV ** - Level 3 - Standalone

Functional

CZUAB¥* - Standalone

EVDWB REV *.* - Level 2R - On-Line

DEC/X-11

CXUACY* - Standalone

N/A

NOTES

VAX-11 Level 2R diagnostics must be run online under VMS.

PDP-11 standalone diagnostics must be run
under the diagnostic supervisor.

Run the appropriatt ETHERNET (NI) exerciser program (CZNID* for PDP-11 systems or
EVPBA REV *.* for VAX-11 systems).

If an ETHERNET transceiver and transceiver cable are not available, perform the following steps:

Connect the H4080 loopback test transceiver (Figure 2-8) to J2 on the bulkhead interconnect panel
(Figure 2-5).

Disconnect the H4080 loopback test transceiver from J2 on the bulkhead interconnect panel.
NOTE

Refer to Appendix C for additional information on
the NI exerciser programs.

2-17

CHAPTER 3

SERVICE

3.1

SCOPE

This chapter provides information for servicing the DEUNA. It is divided into the following sections:
e

Maintenance Philosophy — Defines the DEUNA Field Replaceable Unit (FRU).

Diagnostic Description — Describes all VAX-11 and PDP-11

diagnostics for the DEUNA.

Corrective Maintenance — Describes both VAX-11 and PDP-11 corrective maintenance procedures for the DEUNA using troubleshooting flow charts.

A description of the DEUNA Network Interconnect (NI) Exerciser can be found in Appendix C.

3.2

MAINTENANCE PHILOSOPHY

The Maintenance Philosophy for the DEUNA is isolation of the Field Replaceable Unit (FRU). The FRUs for
the DEUNA are faulty modules, cables, or the bulkhead assembly.

It is possible for some apparent failures in the DEUNA to be caused by faults in the ETHERNET physical
channel; that is, transceiver cable, transceiver, or ETHERNET cable. Faults that can be isolated to the
ETHERNET physical channel should be referred to Network support.

3.3 DIAGNOSTIC DESCRIPTION
This section describes the diagnostics available for the DEUNA on both VAX-11 and PDP-11 systems.
Section 3.4 describes the proper order for running these diagnostics. The individual diagnostic abstracts provide specific instructions for running each diagnostic.

3.3.1

Self-Test

The DEUNA Self-Test verifies the DEUNA microprocessor, internal memory, the UNIBUS interface, and
the link module through various loopback levels. The path from the DEUNA to the transceiver and
ETHERNET coaxial cable is also verified during Self-Test.

The ROM-based Self-Test is initiated in two ways: each time the DEUNA is powered up and when a SelfTest Port Command is issued. The Self-Test Port Command is issued by writing a 3 to PCSRO. Refer to
Section 4.3 of this document for a description of PCSRO and the Self-Test Port Command.

3-1

The results of the Self-Test are available
on LEDs (D2 through D7) on the Port modul
e (M7792). The execution time of the Self-Test is seven to ten seconds.
During execution, the Self-Test LEDs should turn
ON and
OFF

indicating the various tests being performed. If the
Self-Test LEDs remain ON and do not cycle ON
and
OFF, this is considered a DEUNA failure, probably
the M7792 module. Refer to Figure 3-1 and Table 3-1
for a description of the Port module LEDs.

In addition to the Self-Test LEDs, one LED on the Port module
D1, verifies the cable connection between the
Port and Link modules.

NOTE
When the DEUNA is in the Running State, LEDs

D1 through D6 are constantly on; D7 blinks on and
off at a rate of about once per second.

SELF TEST CODE
REFER TO TABLE 32

©eeleee|d

—]

r_
Figure 3-1

CABLE VERIFY

r’

DEUNA Port Module Self-Test LEDs

Table 3-1

DEUNA Self-Test LED Codes

(Module)

Code D7 D6 D5 D4 D3 D2 TestName
77

1
2
3
4

ON ON ON ON ON ON NeverGot Started

ON CPU Instruction
ROM
ON
ON ON Writeable Control Store
T11 UNIBUS Address Register
ON

5
6
7

10
11

ON
ON

ON Receiver UNIBUS DMA
ON
PCSR1 Lower Byte & T11 DMA Read
ON ON
ON ON ON PCSRO Upper Byte & T11 DMA Write

Timer

ON ON Physical Address ROM

40
41
42
43
44
45

ON
ON
ON
ON
ON
ON

50
51
52
53

ON
ON
ON
ON

55
60
61
62
63
64
65
66
67
70
71

ON ON
ON
ON ON
ON ON
ON ON
ON ON
ON
ON ON
ON
ON ON
ON
ON ON
ON
ON ON
ON ON ON
ON ON ON

ON
ON
ON
ON
ON
ON

ON ON

Bugcheck (NI & UNIBUS in

M7792/M7793

Transmit Buffer Resource
Allocation Error on Boot

Transmitter Timeout
Receiver Timeout
Buffer Comparison
Byte Count
Receiver Status
CRC Error
Match Bit Error
TDR Error

Transmitter Buffer Address

M7792/M7793
M7792/M7793
M7792/M7793
M7792/M7793
M7792/M7793
M7792/M7793
M7792/M7793

M7792/M7793
M7793
M7793
M7793
M7793
M7793
M7793

Transmitter Timeout
Receiver Timeout
Buffer Comparison
Byte Count

M7793
M7793
M7793
M7793

CRC Error
Runt Packet
ON Minimum Packet Size
Maximum Packet Size
ON Oversize Packet
CRC
ON Collision
Heartbeat
ON Half Duplex
Multicast
ON Address Recognition

M7793
M7793
M7793
M7793
M7793
M7793
M7793
M7793
M7793
M7793
M7793

ON
ON
ON
ON ON

ON
ON

M7792

Transmitter Timeout
Receiver Timeout
Buffer Comparison
Byte Count
Receiver Status
CRC Error

ON
ON
ON ON

ON
ON

M7792
M7792/UNIBUS
M7792
M7792
M7792

M7792/M7793

HALTED STATE) — Internal

ON ON ON ON ON

M7792
M7792
M7792
M7792

Link Memory

Local Loopback

ON ON

ON ON
ON
ON ON
ON
ON ON
ON ON
ON ON
ON ON ON
ON
ON ON ON
ON
ON ON ON

30
31
32
33
34
35
36

PCSRO Lower Byte & Link Mem. DMA
ON PCSR2 & PCSR3

M7792/M7793

Receiver Buffer Address

Receiver Status

3-3

M7793

Code

Table 3-1

DEUNA Self-Test LED Codes (Cont)

Test Name

External Loopback

(Module)

M7793/H4000

Internal Transmit Buffer

M7792/M7793

Resource Allocation

Link Memory Parity Error
ON

Internal Unexpected Interrupt

Internal Register Error
Self Test Done, No Errors

M7792/M7793
M7792/M7793
M7792/M7793

(State =2, DNI set)

NOTE
ON represents a logical ONE (1); OFF represents a

logical ZERO (0). For this table, all LEDs are as-

sumed to be OFF unless noted otherwise.

3.3.2

DEUNA VAX-11 Functional Diagnostic (EVDWB REV *, %)
EVDWRB allows the user to verify the DEUNA functional operation
. It tests all DEUNA hardware functions
the VMS driver is capable of using. It is a VAX/VMS Level 2R (on-line
only) running under the VAX-11
Diagnostic Supervisor (VDS).
EVDWB is compatible with VAX/VMS Version 3.0 or later and the VAX-11
Di agnostic Supervisor Version
6.5 or later.
A summary of the tests performed by the DEUNA VAX-11 Functional Diagnosti

c (EVDWB) is contained in

Table 3-2.

Table 3-2
Test #
|

DEUNA VAX-11 Functional Diagnostic Summary (EVDWB REYV

Name
Read Internal ROM

*.*)

Verifies
The internal 16K byte ROM can be read; there are no CRC
€rTors.

Read/Write Internal

WwCS
3

Internal Link
ADDRESS

Data patterns can be written and read from WCS memory.

All Link Memory locations can be accessed.

Read/Write Internal
Link Memory

Data patterns can be written and read from all Link Memory

locations.
5

Transmit CRC

The Transmit CRC logic functions properly.

Table 3-2 DEUNA VAX-11 Functional Diagnostic Summary (EVDWB) (Cont)
Test #

Name

Verifies

Receive CRC

The Receive CRC logic functions properly.

Promiscuous Address

The DEUNA in the Promiscuous Mode will accept all datagrams regardless of destination address.

Enable All

Multicast

The DEUNA in the Enable All Multicast Mode will accept
all datagrams with multicast destination addresses.

Station Address

The Link Module recognizes the physical, multicast, and
broadcast addresses of the node and discards datagrams with
non-enabled addresses.

Pad Runt Packets

The DEUNA can pad, transmit, receive, and store in host
memory loopback datagrams that are less than 64 bytes
long.

No Receive Buffer

The appropriate error will be flagged if a loopback is
attempted and there are no receive buffers owned by the
DEUNA.

DEUNA Stress

The DEUNA can function properly under heavy traffic loading conditions.

3.3.3 DEUNA PDP-11 Functional Diagnostic (CZUAB¥*)
CZUARB verifies the functional operation of up to eight DEUNAs on a PDP-11 processor. It runs under the

Diagnostic Runtime Services (DRS PDP-11 Diagnostic Supervisor) and only in standalone, off-line environment. The DRS provides APT compatibility for this diagnostic.

A summary of the tests performed by the CZUAB Diagnostic is contained in Table 3-3.

Table 3-3

DEUNA PDP-11 Functional Diagnostic Summary (CZUAB*)

Test #

Name

Verifies

1-4

PCSR Read Access

A device is present at the PCSR addresses specified for the
DEUNA under test.

PCSR?2 Static Bit

All bits in the PCSR2 register can be set and cleared as
specified.

PCSR3 Static Bit

All bits in the PCSR3 register can be set and cleared as
specified.

Table 3-3

DEUNA PDP-11 Functional Diagnostic Summary (CZUAB*) (Cont)

Test #

Name

Verifies

Self-Test

The ROM-based Self-Test can be run successfully when
invoked via SELF TEST Port Command.

Port Command

No errors occur when a Port Command is issued.

Interrupt Logic

A DEUNA interrupt can be generated.

Read Internal ROM

Reads and verifies internal ROM.

Read/Write Internal

WCS

Read/Write Mode
Function

The internal WCS memory can be written and read.

The Read/Write Mode Port Function is operational.

Read/Write Link

Memory

Exercises the internal link memory by reading and writing
patterns throughout the memory.

Internal Loopback

No errors occur when a datagram is transmitted and received

in the Internal Loopback Mode.
15

CRC Checking

The CRC Checking Logic is operational.

Force CRC Error

CRC Error Detection is operational.

Disable Receive

Chaining
18

The Disable Data Chaining Mode is operational.

Transmit Chaining

Error

The Buffer Length Error (BUFL) bit can be set in the
Transmit Descriptor Ring.

No Receive Buffer

A Receive Buffer Error (RBUF) can be generated.

Data Chaining

Transmit and receive data chaining in either internal or
external loopback mode.

Physical Address

The Physical Address detection is operational by attempting

loopbacks with currently enabled and disabled Physical
Address.

Multicast Address

The Multicast Address detection is operational by attempt-

ing loopbacks with currently enabled and disabled Multicast

Addresses.
23

Promiscuous Mode

The DEUNA in the Promiscuous Mode will accept all packets regardless of the destination address.

3-6

Table 3-3

Test #

Name

Enable All

DEUNA PDP-11 Functional Diagnostic Summary (CZUAB¥) (Cont)

Verifies

Multicast

The DEUNA in the Enable All Multicast Mode will accept
all packets with Multicast destination addresses.

Pad Runt Packets

The DEUNA can pad, transmit, receive, and store in host
memory loopback datagrams that are less than 64 bytes
long.

26
27

Half Duplex

The Half-Duplex Mode is operational.

Simultaneous

Operations

The DEUNA can perform several operations at the same
time.

Print Device

Parameters

Prints the Default Physical Address, the microcode revision,
and the switch pack settings.

3.3.4

DEUNA VAX-11 Repair Level Diagnostic (EVDWA REV *_*)

EVDWA is a VAX-11 LEVEL 3 diagnostic that runs in the off-line, stand-alone mode only. It runs under the

VAX-11 Diagnostic Supervisor. It detects and isolates errors to the functional unit or the FRU. It tests all
DEUNA hardware functions that can be tested using diagnostic DCT-11 microprocessor microcode. They
use both the internal and external loopback mode.
Table 3-4 summarizes the DEUNA VAX-11 Repair Level Diagnostic.

Table 3-4

DEUNA VAX-11 Repair Level Diagnostic Summary (EVDWA REV *.*)

Test #

Name

Verifies

1-4

PCSR Read Access

PCSRs 0 through 3 can be read by the host; predetermined
bits appear in the expected bit positions.

Reset

The Reset State for all UNIBUS registers.

RCSR?2 Read/Write

PCSR2 can be read as well as written by the host.

PCSR3 Read/Write

PCSR3 can be read as well as written by the host.

NOP

The DEUNA processor (T11)

can respond to Port

Commands.
9

Self Test

The DEUNA can execute the ROM-based Self-Test and
report results.

Table 3-4

DEUNA VAX-11 Repair Level Diagnostic Summary
(EVDWA REYV *.#) (Cont)

Test #

Name

Verifies

DEUNA ROM Dump

The data path from the DEUNA processor to the UNIBUS
interface is able to transfer data reliably.

Data Dump/Load

The

data

path

the

WCS

using

the

DUMP/LOAD

INTERNAL MEMORY Port Command.

Load and Start

Function

The

Load

and

Start

Microaddress

Port Function

operational.

Comprehensive WCS

The WCS memory is error free by performing functional and
dynamic tests.

Interrupt

The DEUNA will generate an interrupt when enabled, can
generate an interrupt vector, and can arbitrate for control of

the UNIBUS.
15

Microcode Partition
3
Interrupt Bit

Each of the interrupt bits in PCSRO can cause an interrupt.

Timer

The internal timer is operating within normal limits.

Comprehensive Link
Memory

The Link Memory is error free by performing functional and

dynamic tests.
DMA “TO’’ Address

The DMA *‘“TO’’ Address Register is checked by writing
and reading it.

DMA “‘FROM”’ Address

The DMA ““FROM’’ Address Register is checked by writing and reading it.

DMA Block Transfer

The DMA Engine can transfer a data block of maximum size
to host memory.

DMA Ripple

The counting function of the DMA ‘‘TO’’ Address Register

is checked.

3-8

Table 3-4

Test #
16

Name

DEUNA VAX-11 Repair Level Diagnostic Summary
(EVDWA REYV *.*) (Cont)

Verifies

Microcode Partition
4

XMIT Done

The XMIT State Machine will generate a ‘‘Transmit Done’’

Receiver Done

The Receive State Machine is operational and an interrupt

Data Byte Framing

Data is being framed on byte boundaries.

Data Word Framing

Data is being framed on word boundaries.

Data Path Pattern

The Link Module data path has no stuck-at-one/stuck-at-

Status Mux

Verification
Link (Even) Byte

Counter

Link (Odd) Byte

Counter

Link Byte Counter

Maximum

Link FIFO

Addressing

Link Memory

Arbitration

interrupt after completing a diagram transmission.

occurs when a datagram is received.

zero (SAO/SAL1) errors.

The Status Mux is operational.

The byte counters are functioning properly for datagrams
with even number of bytes.

The byte counters are functioning properly for datagrams
with odd number of bytes.

The byte counter will not wrap around if the maximum count
is exceeded.

The address paths through the link address FIFOs are functioning properly.

The Link Memory Arbitration logic is operational.

Microcode Partition
5

Station Address
Pattern

The Link RAM has no SAO0/SA1 errors.

3-9

Table 3-4

DEUNA VAX-11 Repair Level Diagnostic Summary
(EVDWA REV *,*) (Cont)

Test #

Name

Station Address

Rejection

Verifies

1
The Link will not recognize a datagram with a destination

address that is not contained in the Station Address RAM.

Station Address
RAM Position

‘
The Link will recognize the physical address regardless of
where it is located in Station Address RAM.,

Multicast Address

Verifies that the Multicast Address detectlion is operational

by attempting loopbacks with currently enabled and disabled

Multicast Addresses.

Microcode Partition
6

CRC Data Pattern

The CRC circuitry generates the correct CRC residual under
various datagram conditions.

CRC Error

The CRC circuitry can detect an incorrect CRC in a received
datagram.

CRC Pattern Length

Tue receive CRC circuitry can detect incorrect CRCs in
datagrams of different lengths.

Runt

The Receive State Machine can detect and discard datagrams of less than 64 bytes.

Half-Duplex

The DEUNA functions as specified in the Half-Duplex
Mode.

Microcode Partition
7

Collision

The Receive State Machine responds to a collision.

TDR Counter

The TDR counter is capable of counting.

Retry Logic

The Retry logic is functioning properly.

Print Device

Parameters

Prints the Default Physical Address, the microcode revision,
and switchpack settings.
|

3-10

3.3.5

DEUNA PDP-11 Repair Level Diagnostic (CZUAA*)

CZUAA runs in the off-line, standalone mode under Diagnostic Run-time Services (DRS). It detects and iso-

lates errors to the functional unit or the FRU. It tests all DEUNA hardware functions that can be tested using
diagnostic DCT-11 microcode. It uses both the internal and external loopback mode.

Refer to Table 3-5 for a summary of the DEUNA PDP-11 Repair Level Diagnostic (CZUAA¥).

Table 3-5

DEUNA PDP-11 Repair Level Diagnostic Summary (CZUAA*)

Test #

Name

Verifies

1-4

PCSR Read Access

PCSRs 0 through 3 can be read by the host; predetermined
bits appear in the expected bit positions.

Reset

The Reset State for all UNIBUS registers.

PCSR2 Read/Write

PCSR2 can be read as well as written by the host.

PCSR3 Read/Write

PCSR3 can be read as well as written by the host.

NOP

The DEUNA processor (T11)

can respond to Port

Commands.

Self-Test

The DEUNA can execute the ROM-based Self-Test and
report results.

DEUNA ROM Dump

The data path from the DEUNA processor to the UNIBUS
interface is able to transfer data reliably.

WCS Load/Dump

The

data

path

the

WCS

using

the

DUMP/LOAD

INTERNAL MEMORY Port Command.
12

Load and Start

Function

The

Load

and

Start

Microaddress

Port

Function

operational.

Comprehensive WCS

The WCS memory is error free by performing functional and
dynamic tests.

Interrupt

The DEUNA will generate an interrupt when enabled, can
generate an interrupt vector, and can arbitrate for control of

the UNIBUS.
15

PCSRO Interrupt

Bit

Each of the interrupt bits in PCSRO can cause an interrupt.

Timer

The internal timer is operating within limits.

Link Memory

The Link Memory is error free by performing functional and
dynamic tests.

Table 3-5

DEUNA PDP-11 Repair Level Diagnostic Summary (CZUAA¥*) (Cont)

Test #

Name

DMA ““TO’’ Address

Verifies

The DMA *““TO’’ Address Register is checked by writing
and reading it.

DMA ““FROM’’ Address
Register

1
The DMA ““FROM’ Address Register is checked by writing and reading it.

DMA Block Transfer

The DMA Engine can transfer a data block of maximum size
to host memory.

Transmit Done

The Transmit State Machine will generate a ‘‘Transmit
Done’” interrupt after completing a datagram transmission.

Receiver Done

The Receive State Machine is operationél and an interrupt
occurs when a datagram is received.

Data Byte Framing

Data is being framed on byte boundaries.

Data Word Framing

Data is being framed on word boundaries.

Data Path Pattern

The Link Module data path has no struck-at-one/stuck-atzero (SAOQ/SAL1) errors.

Status Mux

Link (Even) Byte

Counter

The Status Mux is operational.

The byte counters are functioning properly for datagrams
with even number of bytes.

Link (Odd) Byte

Counter

The byte counters are functioning properly for datagrams
with odd number of bytes.

Link Byte Counter
Maximum

The byte counter will not wrap around if the maximum count
is exceeded.

Link FIFO

Addressing

The address paths through the link address FIFOs are functioning properly.

Receive Link
Memory Address

The Receive Link Memory Address ]ogicican access all Link
Memory locations.

3-12

Table 3-5

DEUNA PDP-11 Repair Level Diagnostic Summary (CZUAA*) (Cont)

Test #

Name

Transmit Link

Memory Address

Link Memory

Arbitration

Verifies

The Transmit Link Memory Address logic can access all
Link Memory locations.

The Link Memory Arbitration logic is operational.

Station Address

Pattern

The Link RAM has no SAO/SAL1 errors.

Station Rejection

The link will not recognize a datagram with a destination

Physical Address
RAM Position

The link will recognize the physical address regardless of
where it is located in Station Address RAM.

Multicast Address

The Multicast Address detection is operétional by attempt-

address that is not contained in the Station Address RAM.

ing loopbacks with currently enabled and disabled Multicast
Addresses.

CRC Data Pattern

The CRC circuitry generates the correct CRC residual under

CRC Error

The CRC circuitry can detect an incorrect CRC in a received

CRC Pattern Length

The receive CRC circuitry can detect incorrect CRCs in

Receive Buffer

various datagram conditions.

‘

datagram.

datagrams of different lengths.

Recover (Runt)

The Receive State Machine can detect and discard data-

Half-Duplex

The DEUNA functions as specified in the Half-Duplex

Collision

The Receive State Machine responds to a collision.

TDR Counter

The TDR counter is capable of counting.

Retry Logic

The Retry logic is functioning properly.

Print Device

grams of less than 64 bytes.

Mode.

Parameters

Prints the Default Physical Address, the microcode revision,
and the switchpack settings.

3-13

3.3.6 NI Exerciser (CZUAD*/EVDWC REV *.%)
The NI Exerciser determines the ability of nodes on the NI (ETHERNET) to communicate with each

other. It
includes analysis of errors obtained while running the Exerciser to provide the operator with meaningful
error

messages.

Refer to Appendix C for a general description of the NI Exerciser. Refer to the individual diagnostic abstract
for specific information on running each diagnostic.

3.3.7 DEC/X11 DEUNA Module (CXUAC*)
The DEC/X11 DEUNA Module obtains maximum bus activity for a sustained period of time by transmitting
multiple packets on each pass. At the start of each pass, the program allocates a number of transmit buffers

(three to ten depending on a random number). It then calculates varying size buffers for a total byte count of
approximately 1000 bytes. A table is generated for each packet including starting address, byte count, and

expected CRC. Receive buffers are then allocated to align with the transmit buffers, allowing for header

CRC verification.

and

The default loopback made for the test is external. However, internal loopback may be selected by setting a
software switch when configuring the DEUNA DEC/X11 module.

3.4

CORRECTIVE MAINTENANCE

Corrective maintenance of the DEUNA is accomplished by using the ROM-based Self-Test and the diagnos-

tics to isolate the faulty FRU. The FRUs for the DEUNA are:
e

M7792 DEUNA Port Module

M7793 DEUNA Link Module

BCO8R-1 (2) Internal Cables

70-18798-00 DEUNA Bulkhead Cable Assembly

70-18799-00 DEUNA Bulkhead Assembly

Figure 3-2 describes the DEUNA troubleshooting procedure for both the VAX-11 and the PDP-11 systems.

3-14

y
RUN NI EXERCISER

TO ISOLATE
FAILING NODE
AND GO TO THAT

NODE

|
RUN
FUNCTIONAL

DIAGNOSTIC

INST
INSTALL
A

RERUN

TURNAROUND

JAGNOSTIC*

°s

YES

RUN
REPAIR

DIAGNOSTIC

RECONNECT

HARDWARE
TO
NETWORK IF
NECESSARY

REFER PROBLEM
TO NETWORK

SUPPORT

YES

oD
*NOTE: REFERS TO PREVIOUSLY RUN DIAGNOSTIC
TK-8720

Figure 3-2

DEUNA Troubleshooting Procedure (Sheet 1 of 2)

3-15

)
REPLACE
FAILING

FRU

$
RERUN
DIAGNOSTIC

ALL

FRU'S

REPLACED

RECONNECT

REFER

HARDWARE

PROBLEM TO

TO NETWORK

NETWORK

IF NECESSARY

SUPPORT

RUN

EXIT

NI
EXERCISER

REFER

PROBLEM TO
NETWORK

SUPPORT
PROBLEM
STILL
EXIST

Co D

* NOTE: REFERS TO PREVIOUSLY RUN DIAGNOSTIC

TK.9721

Figure 3-2

DEUNA Troubleshooting Procedure (Sheet 2 of 2)

3-16

CHAPTER 4
PROGRAMMING

4.1 INTRODUCTION
'
‘
This chapter contains the information necessary to program the DEUNA. The chapter is divided into
several sections. This section defines the functions of the DEUNA in tabular format. The tables are
separated into functional categories. Each table lists the following:
®

Function name

A brief description of the purpose for the function

A pointer to the appropriate section(s) for more detail

Refer to Tables 4-1 through Table 4-5.
The remainder of this chapter is divided into the following sections:
®

Programming Overview — Provides a brief description of the communication method between
the DEUNA and its host processor.

Control and Status Registers

Port Control Block Functions

Transmit and Receive Descriptor Rings

Transmit and Receive Data Buffers

DEUNA Operation - Describes the interaction between the DEUNA and the Port-Driver.

Exceptional Operations — Describes the DEUNA operations other than the normal transmit and
receive datagram service. These functions include Loopback Message and Remote Console

Operations.

4-1

Table 4-1

DEUNA Control Functions

Reference

Function

Purpose

Interrupt System

Allows the DEUNA to get the attention

Processor

Read/Write
Interrupt Enable
Driver Reset

Section

of the port-driver

Allows port-driver to determine if
interrupts are enabled

Used by the port-driver to place the DEUNA
in the reset state

Table 4-2

Function

Poll

Stop

Get Port Control
Block Base Address
Execute Command

4.3

DEUNA Port Commands

Reference

Purpose

Informs DEUNA

Section

of datagram ready for

transmission or receive buffer is available

4.3

Used by the port-driver to stop transmit
and receive datagram service

4.3

Informs the DEUNA that the Port Control
Base Address has been supplied to it

4.3

Informs the DEUNA that a command is in the
Port Control Block and should be read and

executed

Start

4.3

Used by the port-driver to start the DEUNA
processing datagrams

4.3

Table 4-3

DEUNA Data Functions
Reference

Function

Purpose

Section

Transmit Packet

Transmits data packets over the Ethernet

4.9.6

Receive Packet

Receives data packets from the Ethernet

495

Table 4-4

DEUNA Ancillary Commands
Reference

Function
Read Default

Section

Purpose
Provides port-driver with the unique

Physical Address

physical address of the DEUNA

443

Read/Write
Physical Address

Allows the port-driver to read or change
the physical address currently being
used by the DEUNA

4.4.4

Read/Write
Multicast

Allows the port-driver to read or write
the Multicast address table currently

Read/Write
Descriptor Ring

Allows the port-driver to read or write
the current base address and lengths of

Read/Write Mode

Allows the port-driver to read or write

the current mode of operation of the DEUNA

4438

Read Counters

Used by the port-driver to read internal
maintenance counters

4.47

Read and Clear

The port-driver reads then clears the

Address Table

Format

Counters

being used by the DEUNA

the transmit and receive descriptor rings

maintenance counters

4-3

4.4.5

4.4.6

4.4.7

Table 4-4

DEUNA Ancillary Commands (Cont)
Reference

Function

Purpose

Section

Read/Read and

Allows the port-driver to retrieve the

Clear Status

internal status of the DEUNA

Read/Write

Allows the port-driver to read and write

Internal Memory

the internal memory of the DEUNA

Load and Start

Allows the port-driver to start execution

Microaddress

of WCS-loaded microcode

4.4.9

4.4.10

442

Write System

Used by the port-driver to build the

ID Parameters

system-dependent parameter list

44.11

Write Load
Server Address

Provides DEUNA with the destination
address for Request Program Load message

4.4.12

Table 4-5

Maintenance Functions

Reference

Function

Purpose

Section

Self-Test

Executed by the DEUNA in the reset state

4.3

TDR

Aid in locating network cable faults

4.7

Maintenance

List counters used for network maintenance

Loop

Used by a remote DEUNA to loop a message

Counters

Identification

Down-line Load

Boot

4.4.7

through the local DEUNA

4.10.1

DEUNA response to a Request ID message

4.10.2

Supports down-line load of system or
communications processor

4.10.2.1

Remote or local initiation of boot

4.10.2.1

4-4

4.2 PROGRAMMING OVERVIEW
The operation of the DEUNA is controlled by a program in host memory called the port driver.
Communication between the DEUNA and the host processor is accomplished in two ways: by Port
Commands between the host and the DEUNA’s Control and Status Registers (CSRs) and by Ancillary
Commands through shared data structures in host memory via Port Control Block (PCB) Functions.

The host processor issues a Port Command by writing bits (03:00) of the Port Control and Status Register
0 (PCSR0). The DEUNA responds by executing the Port Command and setting the Done Interrupt
(DNI) or Port Command Error Interrupt (PCEI) bits.

Refer to Sections 4.3 and 4.9.2 for more information on Port Commands.

The host processor issues an ancillary command by writing to a data structure in host memory rather than
directly to the DEUNA PCSRs. Port Functions are used by the port driver program to set up operational
and maintenance parameters for the DEUNA. Refer to Section 4.4 for more information on Port
functions.

The data structure used for Port Functions is called the Port Control Block (PCB). It consists of four 16-

bit words in host memory. The Function Code is written to the low byte of the first word of the PCB. The
rest of the PCB is written with Port Function specific information depending on the Port Function to be

executed. This information can be pointers to other data structures in host memory or data to be used in
executing the Port Function.

Refer to Figure 4-1.

The following sequence is an example of communication between the host’s port-driver program and the
DEUNA using Port Commands and Port Functions.

The port-driver loads the DEUNA with the starting address of the PCB (Get PCB Port
Command).

The port-driver loads the PCB with the appropriate Port Function Code and, if necessary, sets
up other memory data structures.

The port-driver instructs the DEUNA to fetch the Port Function located in the PCB (Get

The DEUNA reads the PCB via DMA and executes the Port Function.

The DEUNA notifies the host of completion of the Port Command via interrupt; either Done
Interrup; (DNI) for successful completion or Port Command Error Interrupt (PCEI) for failure.

Command Port Command).

4-5

ZHOSd —

0HSId_
LHSOd

_£4S0d

TA1ONHMVI0NWdOD

vN 3a

S2TL03HY0LOAN7d8VD

H433Jdd44dnn8g $HS13O4NA3aITv sl AHLINT
H3d4 n8 HLON3T

S1dNYILNI 1831747138

_L3TO0H7LON8dO9D N1OLHONdS NLOIHLONdS AN3AaN3d3d

o]ol-

2131 [-p

ai3id

NOILVNILS3a S3YaQv 3HNOS $s3Haqv Q31d3A1L4 viva

LOHINJISHNIYSVIHA

HL3dO4N3n87 SH34YANQ8V SHBNOLHVYI3S 4H3L4ONn381 HBSNOLYV.L3S NOILVWHO4INI HVLI3LN4SvNVNaH8L

NOILYWHOINI

LSOH AHOW3W

4-6

30HNOS
_

a31d3A1L4 al3id
|

Several other data structures may be used by the port-driver when issuing Port Functions to the DEUNA.
These structures are Port Function dependent and include the following:

UNIBUS Data Block (UDB) - The UDB is a data structure in host memory that is of variable
size and content depending on the Port Function being executed. It contains supporting
information for the Port Function such as pointers to other data structures (see Figure 4-1).
Refer to Section 4.4 for more information on specific UDB formats.

Descriptor Rings — There are two descriptor ring structures: one for transmit and one for
receive. They are variable in length and composed of the address of the data buffer, the length
of the buffer, and status information associated with the buffer. Refer to Sections 4.5 and 4.6
for a more detailed description of the descriptor rings.
Data Buffers - The data buffers are contiguous portions of host memory used for packet
buffering. Refer to Sections 4.7 and 4.8 for data buffer descriptions and formats.

4.3 PORT CONTROL AND STATUS REGISTERS
There are four control and status registers associated with the DEUNA. They reside at addresses in the

UNIBUS I/O page and can be accessed by word or byte operations. The DEUNA accesses PCSR2 and
PCSR3 over the UNIBUS. Tables 4-6 through 4-10 and Figures 4-2 through 4-5 describe the Port
Control and Status registers bit format and bit descriptions.

Table 4-6

PCSR 0 Bit Descriptions

Bits

Name

Description

(15)

SERI

Status Error Interrupt — Indicates the presence of an error condition flagged
in status register accessible by the port command function. Set by the
DEUNA,; cleared by the port-driver.

(14)

PCEI

Port Command Error Interrupt — Indicates the occurrence of either a function
error or a UNIBUS timeout during the execution of a port command. Bit 7
of PCSR1 distinguishes between the two error conditions. Set by the
DEUNA,; cleared by the port-driver.

(13)

RXI

Receive Ring Interrupt — Attention bit for ring updates. Set by the DEUNA;
cleared by the port-driver. When set, indicates that the DEUNA has placed a
message on the ring.

(12)

TXI

Transmit Ring Interrupt — Attention bit for ring updates. Set by the DEUNA;
cleared by the port-driver. When set, indicates that transmission has been
suspended, all messages found on the transmit ring have been sent, or an
error was encountered during a transmission.

1mn

DNI

Done Interrupt — Interrupts when the DEUNA completes a port command.

Table 4-6
Bits

Name

(10)

RCBI

PCSR 0 Bit Descriptions (Cont)

Description

Receive Buffer Unavailable Interrupt — Interrupts when the DEUNA dis-

cards an incoming message due to receive ring buffers being unavailable.
Once set by the DEUNA, RCBI will not be set again until after the DEUNA
has received a PDMD port command and discarded a subsequent message.
Set by the DEUNA; cleared by the port-driver.

(09)

ZERO

(08)

USCI

Unsolicited State Change Interrupt — Interrupts when the DEUNA performs

the following actions:

Fatal Error — A transition into the NI AND UNIBUS HALTED state from
the READY, RUNNING, UNIBUS HALTED, or NI HALTED states. This

state change is caused by the DEUNA detecting an internal fatal error (for
example, internal parity error).

Communication Processor Boot — A transition into the PRIMARY LOAD
state caused by the reception of a remote boot request of the communication
processor (DEUNA microcode).

Communication Processor Boot — A transition into the READY state from
the PRIMARY LOAD state following the reception of the memory load
with transfer address message, as part of a remote boot request.
The three conditions are distinguished by examining the State field of

PCSRI1. Set by the DEUNA; cleared by the port-driver.

(07)

INTR

(06)

INTE

(05)

RSET

Interrupt Summary — The logical OR of PCSRO (15:08). Set by the
DEUNA.
Interrupt Enable — Set or cleared by the port-driver; unchanged by the

DEUNA.

DEUNA Reset — Clears the DEUNA and returns it to the power-up state
when written with a ONE by the port driver. This bit is write-only. After a

successful reset, PCSRO (11) (DNI) = 1, and PCSRO (07) (INTR) = 1.

(04)

ZERO

4-8

Table 4-6

PCSR 0 Bit Descriptions (Cont)

Description

Bits

Name

(03:00)

PORT_-COMMAND
0000

NOOP

DNI bit not set (see Section 4.3.1).

GETPCBB

Instructs the DEUNA to fetch the

001

address of the Port Control Block

from PCSRs 2 and 3. The DEUNA
accesses PCSRs over the UNIBUS,
and retains a copy of the address
internally. If the address of the Port

Control block is changed, this
command must be repeated to
inform the DEUNA.
0010

GETCMD

Instructs the DEUNA to fetch and
execute a command found in the
first word of the Port Control
Block.

The

Control

address of the

Port

Block was obtained

through the Get PCBB command.
0

SELF-TEST

Instructs the DEUNA to enter the
RESET state and execute self-test.

START

Enables transmission and reception

of packets from the port-driver.
This command is ignored by the

DEUNA if it is in the running state.
Clears any current buffer status that
the DEUNA has stored internally;

resets the ring pointers to the base
addresses of the rings.

0101

BOOT

Instructs the DEUNA to enter the
Primary Load state and initiate the

down-line

load

of additional

DEUNA microcode.
0

110

01
1

000

NotUsed

Reserved code; causes a NO-OP.

NotUsed

Reserved code; causes a NO-OP.

PDMD

Polling

Demand — Checks

the

transmit ring for messages to be

transmitted. Polls the receive descriptor ring only if it has not pre-

viously acquired a free buffer.

4-9

Table 4-6

Bits

Name

PCSR 0 Bit Descriptions (Cont)

Description
I

NotUsed

Reserved code; causes a NO-OP,

sets DNI.

Not Used

Reserved code; causes a NO-OP,
sets DNI.

Not Used

Reserved code; causes a NO-OP,

sets DNI.

NotUsed

Reserved code; causes a NO-OP,
sets DNI.

NotUsed

Reserved code; causes a NO-OP,

sets DNI.

1111

Not Used

Reserved code; causes a NO-OP,
sets DNI.

STOP

Suspends operation of the DEUNA
and causes a transition to the Ready

state.

Causes

DEUNA

not

action

the

if the

Running

siate.

SERI [ PCEI [ RXI

| Txt

| DNI

|RCBI|

|usci|INTR]

INTE|RSET

PORT_COMMAND

RwCL|RwcL|RwcL|RwCL|{RwWCLIRwWCL|

|Rrwel|

|RW | w

R/W

00
PCSRO

PORT

DRIVER

ACCESS

wilwlw|w | w/|lw]|lo|lw]|wl!lr/|HR

POWER
upP

STATE

TERMS
RWCL

R/CL

READ ACCESS, WRITE ONE TO CLEAR

READ ACCESS, CLEAR

READ ONLY, IGNORED WHEN WRITTEN

w
u

WRITE ONLY, READ AS ZERO

R/W

READ/WRITE

UNDEFINED
TK-8068

Figure 4-2

PCSRO Bit Format

4-10

Table4-7

PCSR 1 Bit Descriptions

Bits

Name

Description

(15)

XPWR

Transceiver Power OK — A one indicates that a failure exists in
either the transceiver power supply or the circuit breaker on the
bulkhead assembly.

(14)

ICAB

Port/Link Cabling OK — A one indicates that the interconnecting
cable between the Port and Link modules has a seating problem.

(13:08)

SELF-TEST

Self-Test Error Code — The encoded test the DEUNA failed during self-test. A code of zero indicates no failure. Refer to Table
4-8 for self-test failure codes.

O7)

PCTO

Port Command Timeout — A UNIBUS timeout was encountered
while executing a port command (refer to Section 4.9). Valid
only after the PCEI bit of PCSRO is set by the DEUNA. This bit
is used to distinguish between a DEUNA failure to complete a
port command due to a UNIBUS timeout and a function error.

(06:04)

Zeros

(03:00)

STATE

00O00O0

RESET

0001

PRIMARY LOAD

0010

READY

0011

RUNNING

0100

Not Used

0101

UNIBUS HALTED

0110

NIHALTED

0111

NI AND UNIBUS HALTED
Fatal internal error (for example, parity error).

XXX

4-11

An interrupt condition. When the DEUNA is in
this state, the USCI bit of PCSRO is also set.
Cleared by the port-driver setting the RSET bit.
Not used

XPWR|

ICAB

SELF_TEST

PCTO|

STATE

00
PCSR1

PORT
DRIVER

ACCESS

PORT

ACCESS

POWER*

up
STATE

TERMS

RWCL
R/CL
R

READ ACCESS, WRITE ONE TO CLEAR
READ ACCESS, CLEAR
READ ONLY, IGNORED WHEN WRITTEN

WRITE ONLY, READ AS ZERO

UNDEFINED

R/W

*NOTE:

READ/WRITE

THE RESET STATE IS A TRANSITORY STATE. AFTER

SUCCESSFUL RESET, PCSR 1<03:00>=2.
TK-8069

Figure 4-3

Table 4-8
PCSR1 (13:08)
11
10
09

PCSRI1 Bit Format

PCSR 1 (13:08) Self-Test Codes

Test

0
1

Completed — No Errors (state=2, DNI set)

CPU Instruction

0
0

1
0

ROM
Writeable Control Store

1
1

0
0

1
1

1
0

T11 UNIBUS Address Register
Receiver UNIBUS DMA

PCSR1 Lower Byte and Ti11 DMA Read

PCSRO Upper Byte and T11 DMA Write

PCSRO Lower Byte and Link Memory DMA

PCSR2 and PCSR3

1
1

0
0

1
1

0
0

1
0

Timer
Physical Address ROM

Link Memory

1
1

0
0

1
1

|
0

|
1

0
0

1
0

0
|

1
0
1

CRC Error

1
1

0
0

1
0

TDR Error

Local Loopback
Transmitter Timeout
Receiver Timeout
Buffer Comparison
Byte Count
Receiver Status
Match Bit Error

4-12

Table 4-8
PCSR1 (13:08)
11
10
09

0
0
0
0
0
0

1
1
1
1
1
1

1
1
1
1
0
0

1
1
0
0
1
1

1
0
1
0
1
0

0
0
0
0

1
1
1
1

0
0
0
0

1
1
1
1

1
1
0
0

1
0
1
0

Transmitter Buffer Address
Transmitter Timeout
Receiver Timeout
Buffer Comparison
Byte Count
Receiver Status
CRC Error
Receive Buffer Addressing
Transmitter Timeout
Receiver Timeout
Buffer Comparison
Byte Count

0
0

1
0

0
1

1
1

0
1

CRC Error
Runt Packet

0
0
0
0
0

1
1
1
1
0

0
0
0
0
1

1
0
1
0
1

CRC
Collision
Heartbeat
Half-Duplex
Multicast

0
1
0

1
1

1
0
0
|
1
0
0
|
1
0

0
1
0

0
0
0
0

0
0
0
1

0
1
1
0

1
0
1
0

1
1
1

0
0

1
1
1

—

0
0
0
0

[a—

0
0
0
0

0
0

0
0
0

PCSR 1 (13:08) Self-Test Codes (Cont)

Test

Receiver Status

Minimum Packet Size
Maximum Packet Size
Oversize Packet

Address Recognition
External Loopback
Never Got Started
Bug Check (NI & UNIBUS in HALTED State)
Internal Restart Error
Internal Unexpected Interrupt
Link Memory Parity Error
Internal Transmit Buffer Resource
Allocation Error

Internal Transmit Buffer Resource
Allocation Error on Boot
NOTE

If the LEDs display an alternating pattern after the time
required for self-test to run, an unexpected interrupt was
received during self-test.

4-13

01
PCBB <15:01>

00
0

|PCSR2

PORT

R/W

0 | DRIVER
ACCESS

PORT

0 | Access

POWER

jup
STATE

TERMS

RWCL
R

READ ACCESS, WRITE ONE TO CLEAR
READ ONLY, IGNORED WHEN WRITTEN

WRITE ONLY, READ AS ZERO

R/W

READ/WRITE

UNDEFINED
TK-5070

Figure 4-4

Table 4-9

PCSR2 Bit Format

PCSR 2 Bit Description

Bits

Name

Description

(15:00)

PCBB

The low order 16 bits of the address of the Port Control
Block Base.

number.

4-14

The PCBB is read by the Port as an even

PCBS

R/W

|ecsk3

PORT

DRIVER

ACCESS

PORT

honEss

POWER

STATE

TERMS

RWCL
R

READ ACCESS, WRITE ONE TO CLEAR
READ ONLY, IGNORED WHEN WRITTEN

WRITE ONLY, READ AS ZERO

UNDEFINED

R/W

READ/WRITE

TKH071

Figure 4-5

Table 4-10

Bits

Name

(15:02)

(01:00)

PCSR3 Bit Format

PCSR 3 Bit Description

Description
Zeros

PCBB

The high order two bits of the address of the Port Control
Block Base.

4-15

4.3.1 Port Control and Status Register 0 (PCSR0)
Port Control and Status Register 0 (PCSRO0) contains interrupt bits, port command bits, and a device reset

bit.

Refer to Figure 4-2.
1.

Note the following characteristics of PCSRO (refer to Example 4-1).

The upper byte of PCSRO contains error bits, port command completion bits, and data transfer
bits. Any of these bits, when set, cause bit (07) Interrupt (INTR) to set. If bit (06) Interrupt

Enable (INTE) is set, an interrupt is generated. The DEUNA has only one interrupt vector.
Therefore, any interrupt service routine must determine the cause of the interrupt. Also, all bits
that cause interrupts, PCSRO (15:08), are WRITE ONE TO CLEAR.
Avoid using the NO-OP port command (writing 0’s into PCSR (03:00)) except in conjunction
with changing the state of the INTE bit or setting the RSET bit. If a NO-OP command is
issued, 100 us should elapse before issuing another port command.
There is a hardware interlock between the Interrupt Enable (INTE) bit and the Port Command

Field PCSRO (03:00). The DEUNA hardware locks the Port Command Field during write accesses
that change the INTE bit from 1 to 0 or 0 to 1. Therefore, the INTE bit and the Port Command

field cannot be changed with a single write access. It must be done with two write accesses.

The most direct method of writing the Port Command Field is through the MOV(B) instruction.

However, the INTE bit must be overwritten (not changed) to successfully write the Port
Command Field.

The high byte of PCSRO should be cleared using a byte command.
For all Port Commands, except a NO-OP, command execution begins with the getting of
the Port Command bits in PCSR0. Command execution ends with the setting of either the
DNI or PCEI bits in PCSRO. Only one Port Command can be executing at any time.

COMMAND

mov #100, @PCSRO

PCSRO BEFORE

PCSRO AFTER

000002

000102

COMMENT

;s INTE bit changed
sso Port Command

;field does not
jchange

mov #101, @PCSRO

000102

000101

i INTE bit unchanged

;50 Port Command
jfield does change

s;causes GET PCBB
scommand

mov #102, @PCSRO

000101

0oo0102

; INTE bit unchanged

sGET CMD Issued

Example 4-1

Writing Interrupt Bit in PCSRO

4-16

4.4 PORT CONTROL BLOCK FUNCTIONS
The Port Control Block is four words of contiguous data located in host memory. The DEUNA accesses
the Port Control Block through the address (PCBB) contained in PCSRs 2 and 3. The Port Control Block
contains the Port Function to be performed by the DEUNA for the port-driver. It is used by DEUNA
initialization and maintenance operations. See Figure 4-6 and Tables 4-11 and 4-12 for the Port Control
Block formats and bit descriptions.

NOTE
In Tables 4-13 to 4-30 the Port Driver checks are the
expected result, any other result is considered a

Function Error.

PORT FUNCTION DEPENDENT

PORT FUNCTION

00
:PCBB+0

PORT FUNCTION DEPENDENT

:PCBB+2

PORT FUNCTION DEPENDENT

:PCBB+4

PORT FUNCTION DEPENDENT

:PCBB+6

TK-9062

Figure 4-6

Table 4-11

Port Control Block Diagram

Port Control Block Bit Descriptions

Word

Bits

Description

PCBB+0

(15:08)

Interpreting these bits depends upon the Port Function
field.

PCBB+0

(07:00)

Port Function - Used to pass the DEUNA a function.
Written by the port-driver; unchanged by the DEUNA.

PCBB+2

(15:00)

Interpreting these bits depends upon the Port Function

field.
PCBB+4

(15:00)

Interpreting these bits depends upon the Port Function

field.
PCBB+6

(15:00)

Interpreting these bits depends upon the Port Function

field.

4-17

Table 4-12

Function
Code

0
1

Port Control Functions

Reference
Function Name

Section

No-Operation

44.1

* Load and Start Microaddress

442

Read Default Physical Address

443

No-Operation

443

Read Physical Address

444

5
6
7
10

Write Physical Address
Read Multicast Address List
Write Multicast Address List
Read Ring Format

444
4.4.5
4.4.5
4.4.6

Write Ring Format

4.4.6

Read Counters

4.4.7

13
14
15

Read and Clear Counters
Read Mode
Write Mode

4.4.7
4.4.8
4.4.8

Read Port Status

4.4.9

Read and Clear Port Status

4.4.9

* Dump Internal Memory

4.4.10

* Load Internal Memory

4.4.10

* Read System ID Parameters

4.4.11

23
24
25

* Write System ID Parameters
* Read Load Server Address
* Write Load Server Address

44.11
4.4.12
4.4.12

These Port Control Functions are intended for maintenance purposes.

4-18

4.4.1

Function Code 0 — No-Operation

See Figure 4-7 and Table 4-13 for the bit formats and bit descriptions of the No-Operation function. For
more detail refer to Section 4.3.1.

MBZ

:PCBB+0

IGNORED

:PCBB+2

IGNORED

:PCBB+4

IGNORED

:PCBB+6

TKH061

Figure 4-7

Table 4-13

Function Code 0 - No Operation Bit Format

Function Code 0-No-Operation Bit Descriptions

Word

Bits

Field

Description

PCBB+0

(15:00)

OPCODE

Opcode=0- NO-OP

4-19

4.4.2

Function Code 1 - Load and Start Microaddress

This function code is used by the port-driver to instruct the DEUNA to start execution of WCS loaded
microcode. The microcode is loaded via Function Code 21 - Load Internal Memory (refer to Section
4.4.10). Both functions are intended for maintenance purposes such as diagnostic testing. See Figure 4-8
and Table 4-14 for bit format and descriptions.

MBZ

IDBB

:PCBB+0

MBZ | :PCBB+2

IGNORED

:PCBB+4

IGNORED

:PCBB+6

TK-9065

Figure 4-8

Function Code 1 - Load and Start Microaddress

Bit Format

Table 4-14

Function Code 1 - Load and Start

Microaddress Bit Descriptions

Word

Bits

Field

Description

PCBB+0

(15:08)

MBZ

Must be zero.

PCBB+0

(07:00)

OPCODE

OPCODE=1 - Load and Start
Microadddress. Instructs the DEUNA
to start executing from the microaddress
supplied to it. Written by the port-driver, unchanged by the DEUNA.

PCBB+2

(15:01)

IDBB

The word address of the internal data
block the DEUNA is to start executing
from.

PCBB+2

(00)

MBZ

Must be zero.

Port Driver Checks

Resultant Error

(PCBB+0)(15:08)=0
(PCBB+2){00)=0
State # RUNNING

Function Error
Function Error - Write Function Check Only
Function Error

4-20

4.4.3 Function Codes 2 - Read Default Physical Address
Function Code 2 allows you to read the Default Physical Address

from the DEUNA. The DEUNA
Default Physical Address is the address value residing in the Physical
Address ROM on the DEUNA Port
module. The physical address is the unique address value associat
ed with a given station on the network.
The ETHERNET physical address is distinct from all other physical
addresses on all ETHERNETSs. The
physical address used may be changed by using Function Code 5 Write Physical Address (refer to

Section 4.4.5). See Figure 4-9 and Table 4-15 for bit format and descriptions.
15

08
MBZ

:PCBB+0

DPA <15:00>

:PCBB+2

DPA <31:16>

:PCBB+4

DPA <47:32>

:PCBB+6
TK-9066

Figure 4-9

Function Code 2 -~ Read Default Physical Address

Bit Format
Table 4-15

Function Code 2 - Read Default
Physical Address

Word

Bits

Field

Description

PCBB+0

(15:08)

MBZ

Must be zero

PCBB+0

(07:00)

OPCODE

OPCODE=2 - Read default physical
address out of the DEUNA.

OPCODE=3 - No operation. Written
by the port-driver, unchanged by the
DEUNA.

PCBB+2

(15:01)

DPA(15:01)

Address bits (15:01) of the Default Physical Address. Written by the DEUNA
for a read function.

PCBB+2

(00)

DPA(00)

Must be written a zero for physical
addresses.

PCBB+4

(15:00)

DPA(31:16)

The middle order 16 address bits of the
Default Physical Address.
Written by
the DEUNA for a read function.

PCBB+6

(15:00)

DPA(47:32)

The high order 16 address bits of the
Default Physical Address.
Written by
the DEUNA for a read function.

Port Driver Checks

Resultant Error

(PCBB+0)(15:08)=0

Function Error

4-21

4.4.4 Function Code 3 - No-Operation
This function code causes a NO-OP to be executed by the DEUNA (refer to Section 4.4.1).

4.4.5 Function Codes 4/5 — Read/Write Physical Address
Function Codes 4 and 5 read or change the Physical Address the DEUNA is currently using for address
comparison. The DEUNA returns the powerup default Physical Address when read if an address has not

been previously written into it. The DEUNA maintains only one Physical Address. The last write of the
Physical Address replaces all previous writes. Bit (00) of any physical address must always be a value of
zero. See Figure 4-10 and Table 4-16 for bit format and bit descriptions.

08
MBZ

0/1

| :PCBB+0

:PCBB+2

PA <15:00>

PA <31:16>

:PCBB+4

PA <47:32>

:PCBB+6

TK9067

Figure 4-10

Function Codes 4/5 — Read/Write Physical Address

Physical Address Bit Format

4-22

Table 4-16

Function Codes 4/5 — Read/Write Physical

Address Bit Descriptions

Word

Bits

Field

Description

PCBB+0

(15:08)

MBZ

Must be zero. Written by the port-driver;
unchanged by the DEUNA.

PCBB+0

(07:00)

OPCODE

OPCODE=4 - Read physical address
out of the DEUNA.

OPCODE=5 - Write physical address
into the DEUNA.
Written by the port-driver; unchanged
by the DEUNA.
PCBB+2

(15:01)

PA(15:01)

Address bits (15:01) of the Physical
Address. Written by the port-driver for
a write function, written by the DEUNA
for a read function.

PCBB+2

(00)

PA(00)

Must be written
addresses.

PCBB+2

(15:00)

PA(31:16)

The middle order 16 address bits of the
Physical Address. Written by the portdriver for a write function, written by the
DEUNA for a read function.

PCBB+6

(15:00)

PA(47:32)

The high order 16 address bits of the
Physical Address. Written by the portdriver for a write function, written by the
DEUNA for a read function.

zero

Port Driver Checks

Resultant Error

(PCBB+0)(15:08)=0
(PCBB+2)(00)=0

Function Error
Function Error-Write Function Check Only

4-23

for physical

4.4.6 Function Codes 6/7 - Read/Write Multicast Address List
These two Function Codes enable reading and writing of Multicast addresses. A Multicast Address is an
address value that a group of logically related stations respond to. The DEUNA can store a maximum of
ten Multicast addresses. The Read Multicast Address List function provides the port-driver with the
Multicast address table the DEUNA is currently using for address compare. If no previous Write
Multicast address has been done, the UDBB will be unchanged, indicating no Multicast address compari-

son. The Write Multicast address function is used to enable or change the Multicast address comparison.
See Figure 4-11 and Table 4-17 for bit format and bit descriptions.

Each Multicast Address Entry in the Multicast Address Table must have a one in the least significant bit,
LA(00)=1. The UNIBUS Data Block is written by the port-driver and read by the DEUNA for a write
function. The UNIBUS Data Block is read by the port-driver and written by the DEUNA for a read
function (see Figure 4-12).

08
MBZ

|l o]

olo

|on]|pceeo

UDBB <15:01>

MLTLEN

mBz | :pcBB+2

MBZ

o288 | pceB+a

IGNORED

:PCBB+6

TK-9063

Figure 4-11

Function Codes 6/7 — Read/Write Multicast Address
List PCBB Bit Format

Table 4-17

Function Codes 6/7 — Read/Write Multicast
Address List PCBB Bit Descriptions

Word

Bits

Field

Description

PCBB+0

(15:08)

MBZ

Must be zero.

PCBB+0

(07:00)

OPCODE

OPCODE=6 - Read Multicast address
table out of the DEUNA.

OPCODE=7 - Write Multicast address
table into the DEUNA.
Written by the port-driver; unchanged
by the DEUNA.

PCBB+2

(15:01)

UDBB
(15:01)

The low order 15 address bits of the
UNIBUS Data Block Base. Written by
the port-driver; unchanged by the
DEUNA.

PCBB+2

(00)

MBZ

Must be zero.

4-24

Table 4-17

Function Codes 6/7 - Read/Write Multicast

Address List PCBB Bit Descriptions (Cont)
Word

Bits

Field

PCBB+4

(15:08)

MLTLEN

Description
Multicast Address Table length.

The

number of Multicast Addresses read
from or written to the UNIBUS Data
Block expressed as an unsigned integer.
The length in words of the UNIBUS

Data Block is three times MLTLEN.
Written by the port-driver; unchanged
by the DEUNA.
When reading, the Multicast Address
table and the MLTLEN field is less than
the number of Multicast Addresses in
the DEUNA, the DEUNA will return,
without error, a truncated list equal to
the number asked for, starting with the
first address in the list.

When reading or writing the Multicast
Address Table and the MLTLEN field is
greater than the maximum number of

allowable Multicast Addresses, the
DEUNA will abort the command and set
the appropriate error status.

PCBB+4

(07:02)

PCBB+4

(01:00)

MBZ

Must be zero.

UDBB

The high order two address bits of the
UNIBUS Data Block Base. Written by
the port-driver; unchanged by the

(17:16)

DEUNA.
Port Driver Checks

Resultant Error

(PCBB+0)(15:08)=0
(PCBB+2)(00)=0

Function Error

MLTLEN < MAXMLT
MLTLN 0
LA{00)=1

Function Error
Function Error

Function Error - Read Function Check Only
Function Error — Write Function Check Only

4-25

OPCODE =6 — WRITTEN BY THE DEUNA

OPCODE =7 — WRITTEN BY THE PORT DRIVER, READ BY THE DEUNA

LA <15:01>

:UDBB+0

LA <31:16>

:UDBB+2

LA <47:32>

:UDBB+4

|
|
|

<15:01
15:01>

:UDBB+0+

6(MTLEN-1)
:UDBB+2+

31:16

6(MTLEN-1)

LA <31:16>

:UDBB+4+

LA <47:32>

B(MTLEN-1)
TK-9064

Figure 4-12

Function Codes 6/7 - Read/Write Multicast Address
List UDBB Bit Format

4.4.7

Function Codes 10/11 — Read/Write Ring Format

This function provides the port-driver with the current base addresses and lengths of the transmit and
receive descriptor rings. If no previous Write Descriptor Ring Format function has been done, the
DEUNA responds with zeros in all address and length fields. The Write Descriptor Ring Format function
is used to initialize the DEUNA.

Refer to Figure 4-13 and Table 4-18 for PCBB bit format and bit descriptions. For UDBB bit format and
bit descriptions, refer to Figure 4-14 and Table 4-19.

08
MBZ

0/1 | :PCBB+0O

uDBB <15:01>

mBz | :PCBB+2

IGNORED

MBZ

uDBB

<17:15>

:PCBB+4

IGNORED

TK-9060

Figure 4-13

Function Codes 10/11 - Read/Write Ring Format
PCBB Bit Format

4-26

Table 4-18

Function Code 10/11 - Read/Write Ring Format

PCBB Bit Descriptions

Word

Bits

Field

Description

PCBB+0

(15:08)

MBZ

Must be zero.

PCBB+0

(07:00)

OPCODE

OPCODE=10 - Read descriptor ring
specification out of the DEUNA,
OPCODE=11 - Write descriptor ring
specification into the DEUNA.
Written by the port-driver; unchanged

by the DEUNA.

PCBB+2

(15:01)

UDBB
(15:01)

The low order 15 address bits of the
UNIBUS Data Block Base. Written by
the port-driver;
DEUNA.

unchanged

the

PCBB+2

(00)

MBZ

Must be zero.

PCBB+4

(07:02)

MBZ

Must be zero.

PCBB+4

(01:00)

UDBB
(17:16)

The high order two address bits of the
UNIBUS Data Block Base. Written by
the port-driver; unchanged by the
DEUNA.

Port Driver Checks

Resultant Error

(PCBB+0)(15:08)=0

Function Error
Function Error
Function Error

(PCBB+2)(00)=0
(PCBB+4)(07:02)=0

4-27

OPCODE = 10— WRITTEN BY THE DEUNA
OPCODE = 11 — WRITTEN BY THE PORT-DRIVER, READ BY THE DEUNA.

TDRB <156:01>

00
MBZ|

:UDBB+0

TDRB

TRLEN

:UDBB+4

RDRB <16:01>

RELEN

MBZ | :UDBB+6

MBZ

RDRB

<17:16>

RRLEN

| .

:UDBB+10

:UDBB+12

TK-8048

Figure 4-14

Function Codes 10/11 — Read/Write Ring Format UDBB Bit Format

Table 4-19

Function Code 10/11 - Read/Write Ring Format
UDBB Bit Descriptions

Word

Bits

Field

Description

UDBB+0

(15:01)

TDRB
(15:01)

Address bits (15:01) of the Transmit
Descriptor Ring Base.

UDBB+0

(00)

MBZ

Must be zero.

UDBB+2

(15:08)

TELEN

Number of words in each entry in the

Transmit Descriptor Ring.
TELEN
must be greater than 4. Expressed as an
8-bit unsigned integer.

UDBB+2

(07:02)

MBZ

Must be zero.

UDBB+2

(01:00)

TDRB

(17:16)

Transmit Descriptor Ring Base.

UDBB+4

(15:00)

TRLEN

Number of entries in the Transmit
Descriptor Ring. Expressed as a 16-bit
unsigned integer.

UDBB+6

(15:01)

RDRB
(15:01)

Address bits (15:01) of the Receive
Descriptor Ring Base. Written by the

The high order two address bits of the

port-driver; unchanged by the DEUNA.
UDBB+6

(00)

MBZ

Must be zero.

4-28

Table 4-19

Function Code 10/11 — Read/Write Ring Format
UDBB Bit Descriptions (Cont)

Word

Bits

UDBB+10

Field

(15:08)

Description

RELEN

Number of words in each entry in the

TELEN
Transmit Descriptor Ring.
must be greater than 4. Expressed as an
8-bit unsigned integer.

UDBB+10

(07:02)

UDBB+10

{01:00)

UDBB+12

(15:00)

MBZ

Must be zero.

RDRB

The high order two address bits of the

RRLEN

Number of entries in the Receive

Receive Descriptor Ring Base.

(17:16)

Descriptor Ring. Expressed as a 16-bit
unsigned integer. An RRLEN value of 1
is illegal.

Port Driver Checks

Resultant Error

(UDBB+0)(00)=0
(UDBB+2)(07:02)=0
(UDBB+6)00)=0
(UDBB+10)(07:02)=0
(UDBB+12)(15:00)%1

Function Error
Function Error
Function Error
Function Error
Function Error

4.4.8

Function Codes 12/13 - Read/Read and Clear Counters

This function is used by the port-driver to read the counters held by the DEUNA.

Refer to Figure 4-15 and Table 4-20 for the PCBB bit format and bit descriptions. The counter values are
unsigned integers. Counters latch at their maximum values to indicate overflow. Refer to Figure 4-16
and Table 4-21 for UDBB counter format and counter descriptions.

15
MBZ

uDBB <15:01>

0/1 | :PCBB+2
MBZ | :PCBB+2

uDBB | .pcpaea
| wees
Soes_

MBZ

CTRLEN <15:01>

mBz | :PCBB+6

TK-8049

Figure 4-15

Function Codes 12/13 -~ Read/Write and Clear
Counters PCBB Bit Format

4-29

Table 4-20

Function Code 12/13 - Read/Read and Clear

Counters PCBB Bit Descriptions
Word

Bits

Field

Description

PCBB+0

(15:08)

MBZ

Must be zero.

PCBB+0

(07:00)

OPCODE

OPCODE=12 - Read counters out of

the DEUNA.

OPCODE=13 - Read counters out of
the DEUNA and clear counters.

PCBB+2

(15:01)

UDBB

Address bits (15:01) of the UNIBUS

(15:01)

Block Base.

Written by the port-driver;

unchanged by the DEUNA.

PCBB+2

{00)

MBZ

Must be zero.

PCBB+4

(15:02)

MBZ

Must be zero.

PCBB+4

(01:00)

UDBB

The high order two address bits of the

(17:16)

UNIBUS Data Block Base.

the port-driver;
DEUNA.
PCBB+6

(15:01)

CTRLEN

Written by

unchanged

the

Counter List Length — The number of
words allocated in the UNIBUS Data
Block to accomplish the function. Writ-

ten by the port-driver; unchanged by the

DEUNA.

In the DEUNA, CTRLEN has a maximum value of 32 decimal.

When reading the counter list, if the

CTRLEN field is less than 32, the
DEUNA returns the number of words

asked for, starting with the first entry in

the list.

When reading the counter list, if the
CTRLEN field is greater than 32, the
DEUNA returns only 32 words, starting
with the first entry in the list.

PCBB+6

(00)

MBZ

Must be zero.

Port Driver Checks

Resultant Error

(PCBB+0)(15:08)=0
(PCBB+2)(00)=0
(PCBB+4)(15:02)=0
(PCBB+6)(00)=0

Function Error
Function Error

4-30

OPCODE=12— READ COUNTERS

OPCODE=13— READ AND CLEAR COUNTERS
00

UN{BUS DATA BLOCK LENGTH

:UDBB+0

SECONDS SINCE LAST ZEROED <15:00>

:UDBB+2

PACKETS RECEIVED <15:00>

:UDBB+4

PACKETS RECEIVED <31:16>

:UDBB+6

MULTICAST PACKETS RECEIVED <15:00>

:UDBB+10

MULTICAST PACKETS RECE{VED <31:16>

:UDBB+12

<15:03>=0

MLEN FRAM

CRC

:UDBB+14*

PACKETS RECEIVED WITH ERROR <15:00>

:UDBB+16

DATA BYTES RECEIVED <15:00>

:UDBB+20

DATA BYTES RECEIVED <31:16>

:UDBB+22

MULTICAST DATA BYTES RECEIVED <15:00>

:UDBB+24

MULTICAST DATA BYTES RECEIVED <31:16>

:UDBB+26

RECEIVE PACKETS LOST — INTERNAL BUFFER ERROR <15:00>

:UDBB+30

RECEIVE PACKETS LOST — LOCAL BUFFER ERROR <15:00>

:UDBB+32

PACKETS TRANSMITTED <15:00>

:UDBB+34

PACKETS TRANSMITTED <31:16>

:UDBB+36

MULTICAST PACKETS TRANSMITTED <15:00>

:UDBB+40

MULTICAST PACKETS TRANSMITTED <31:16>

:UDBB+42

PACKETS TRANSMITTED/3+ ATTEMPTS <15:00>

:UDBB+44

PACKETS TRANSMITTED/3+ ATTEMPTS <31:16>

:UDBB+46

*PACKETS RECEIVED WITH ERROR BIT MAP

Figure 4-16

TK-9047

UNIBUS Data Block Format for Counter List
(Sheet 1 of 2)

4-31

PACKETS TRANSMITTED 2 ATTEMPTS <15:00>

:UDBB+50

PACKETS TRANSMITTED 2 ATTEMPTS <31:16>

:UDBB+52

PACKETS TRANSMITTED — DEFERRED <15:00>

:UDBB+54

PACKETS TRANSMITTED — DEFFERED <31:16>

:UDBB+56

DATA BYTES TRANSMITTED <15:00>

:uUDBB+60

DATA BYTES TRANSMITTED <31:16>

:UDBB+62

MULTICAST DATA BYTES TRANSMITTED <15:00>

:uDBB+64

MULTICAST DATA BYTES TRANSMITTED <31:16>

:UDBB+66

<15:06>=0

LCOL|MLEN{

TRANSMIT PACKETS ABORTED <15:00>

:UDBB+70*

:UDBB+72

TRANSMIT COLLISION CHECK FAILURE <15:00>

:UDBB+74

<15:00>=0

:UDBB+76

*TRANSMIT PACKET ABORTED BIT MAP

Figure 4-16

JLCAR{RTRY

TK-8059

UNIBUS Data Block Format for Counter List

(Sheet 2 of 2)

4-32

Table 4-21

Function Code 12/13 - Read/Read and Clear
Counters UDBB Descriptions

Word

Name

Description

UDBB+0

UNIBUS Data
Block Length

The number of words written into the UNIBUS Data
Block by the DEUNA to accomplish the read
counter function.

UDBB+2

Seconds Since
Last Zeroed

16 bits for the number of seconds since the counters
were last zeroed.

UDBB-+4

UDBB+6

Packets Received

UDBB+10

Multicast Packets

UDBB+12
UDBB+14

32 bits for the total number of error-free datagrams

received.

32 bits for the total number of error-free multicast

Received

datagrams received.

Packets Received

Bitmap

with Error

Bit

Name

Description

(00)

CRC

(01)

FRAM

Block Check Error - A
datagram failed only the
CRC check.
Framing Error - A
datagram failed the
CRC check and did not
contain an integral multi-

(02)

MLEN

ple of 8 bits.

(15:03)

UDBB+16

Packets Received

Message Length Error -

A datagram was larger
than 1518 bytes.

16 bits for the total number of datagrams received

with one or more errors logged in the bitmap.
Includes only datagrams that passed destination
address comparison.

UDBB+20
UDBB+22

Data Bytes
Received

32 bits for the total number of data bytes received
error free, exclusive of data link protocol overhead.

UDBB+24
UDBB+26

Multicast Bytes
Received

32 bits for the total number of multicast data bytes
received error free, exclusive of data link protocol

UDBB+30

Receive Packets Lost—

16 bits for the total number of discards of an incom-

Internal Buffer Error

overhead.

ing packet due to lack of internal buffer space.
Incoming packets must be error-free to be counted.

4-33

Table 4-21

Function Code 12/13 - Read/Read and Clear

Counters UDBB Descriptions (Cont)
Word
UDBB+32

Name
Received Packets Lost -

Local Buffer Error

Description
16 bits for the total number of problems with a

receive ring data buffer. This counter is incremented
for the following reasons:
¢

Buffer Unavailable — Datagram lost because

there was no available buffer on the receive
ring.
e

UDBB+34

Packets Transmitted

UDBB+36

Buffer Too Small - Datagram truncated
because it was larger than the available buffer
space on the receive ring.

32 bits for the total number of datagrams successfully transmitted, including transmissions in which the
collision test signal failed to assert.

UDBB+40

Multicast Packets

32 bits for the total number of multicast datagrams

UDBB+42

Transmitted

successfully transmitted, including transmissions in
which the collision test signal failed to assert.

UDBB+44
UDBB+46

Packets Transmitted
3+ Attempts

32 bits for the total number of datagrams successfully transmitted on three or more attempts, including
transmissions in which the collision test signal failed
to assert.

UDBB+50
UDBB+52

Packets Transmitted
2 Attempts

32 bits for the total number of datagrams successfully transmitted on two attempts, including transmissions in which the collision test signal failed to assert.

UDBB+54

Packets Transmitted

32 bits for the total number of datagrams successful-

UDBB+56

Deferred

ly transmitted on the first attempt after deferring,
including transmissions in which the collision test signal failed to assert.

UDBB+60

Data Bytes

32 bits for the total number of data bytes successful-

UDBB+62

Transmitted

ly transmitted.

UDBB+64
UDBB+66

Multicast Data
Bytes Transmitted

32 bits for the total number of multicast data bytes
successfully transmitted.

Note: The counter values dealing with the Collision Test Signal are only valid when the DEUNA is connected to an H4000 or
similar tranceiver with a collision test feature and the Enable Collision Test (ECT) bit is set in the DEUNA Mode Register (refer

to Section 4.4.8).

4-34

Table 4-21

Function Code 12/13 - Read/Read and Clear
Counters UDBB Descriptions (Cont)

Word

Name

Description

UDBB+70

Transmit Packets

Bitmap

Aborted

Bit

Name

(00)

RTRY

Description
Retry error,
cessful

16 unsuc-

transmission

attempts.

(01)

LCAR

Loss of carrier.

Retry

error, loss of carrier flag,

and non-zero TDR value
on last attempt.

(02)

Always = 0

(03)

Always = 0

(04)

MLEN

Data Block too long.
The
DEUNA
aborted the transmission

because the datagram
exceeded the maximum
packet length.

(05)

LCOL

Late collision on the last
transmission attempt.

(15:06)

Always = 0.

UDBB+72

Transmit Packets
Aborted

16 bits for the total number of datagrams aborted
during transmission for one of the bitmapped errors.

UDBB+74

Transmit Collision
Detect Failure

16 bits for the total number of times the collision test
signal failed to assert following an apparently successful transmission.

UDBB+76

ZEROS

Note: The counter values dealing with the Collision Test Signal are only valid when the DEUNA is connected to an H4000 or
similar transceiver with a collision test feature and the Enable Collision Test (ECT) bit is set in the DEUNA Mode Register (refer
to Section 4.4.8).

4-35

4.4.9 Function Codes 14/15 — Read/Write Mode
This function is used by the port-driver to read or write the mode register of the DEUNA. The mode
register is used to program the operation of the DEUNA when it is in the RUNNING state. Refer to
Figure 4-17 and Table 4-22 for the PCBB bit formats and bit descriptions.

MBZ

Figure 4-17

[DMNT

MBZ

| 0/1

DTCR|LOOP | MBZ

|HDPX|

:PCBB+0

:PCBB+2

IGNORED

:PCBB+4

IGNORED

:PCBB+6

Function Codes 14/15 — Read/Write Mode
PCBB Bit Format

Table 4-22

Function Code 14/15 ~ Read/Write Mode
PCBB Bit Descriptions

Word

Bits

Name

Description

PCBB+0

(15:08)

MBZ

Must be zero.

PCBB+0

(07:00)

OPCODE

OPCODE = 14 — Read the mode out of the
DEUNA.

OPCODE
= 15 — Write the mode into the
DEUNA. Written by the port-driver;
unchanged by the DEUNA.

PCBB +2

(15)

PROM

Promiscuous Mode — Instructs the DEUNA
to accept all incoming packets regardless of

the destination address field. Written by the
DEUNA for a read. Written by the portdriver for a write. Cleared internally upon
power up.

PCBB +2

(14)

ENAL

Enable All Multicast — Instructs the
DEUNA to accept all incoming packets

with Multicast destinations. Written by the

DEUNA for a read. Written by the portdriver for a write. Cleared internally upon
power up.

4-36

Table 4-22

Function Code 14/15 — Read/Write Mode

PCBB Bit Descriptions (Cont)
Word

Bits

Name

Description

PCBB +2

(13)

DRDC

Disable data chaining mode on received
messages. When the DEUNA is in the

mode, it truncates messages that do not fit
in a single buffer. Status information
remains intact. Written by the port-driver
for a write. Written by the DEUNA for a
read. Cleared internally upon power up.
PCBB +2

(12)

TPAD

Transmit Message Pad Enable — Instructs

the DEUNA to pad messages shorter than
64 bytes long, not including the CRC, for
transmission. The DEUNA pads the data
field only. Written by the port-driver for a
write. Written by the DEUNA for a read.
Cleared internally upon power up.
PCBB +2

(11)

ECT

Enable Collision Test — Instructs the
DEUNA to check for collision test after
each transmission. This bit should only be
used with tranceivers that have the collision
test feature, for example H4000.

PCBB +2

(10)

MBZ

Must be zero.

PCBB +2

(09)

DMNT

Disable maintenance message. Instructs the
DEUNA not to transmit a response to all
incoming loop, boot, request ID, and memory load with transfer address messages. In
addition, the DEUNA will not issue the
system ID message. This bit is an aid in
running on-line diagnostics. Written by the
DEUNA for a read. Written by the portdrive for a write. Cleared internally upon
power up.

PCBB +2

(08:04)

MBZ

Must be zero.

4-37

Table 4-22

Function Code 14/15 — Read/Write Mode
PCBB Bit Descriptions (Cont)

Word

Bits

Name

Description

PCBB +2

(03)

DTCR

Disable Transmit CRC - Instructs the
DEUNA not to append 4 bytes of link generated CRC to the transmitted packet, not

to transmit a response to all incoming loop,
boot, request ID, and memory load with
transfer address messages. In addition, the
DEUNA

will

not

issue

the

system

message.

Written by the DEUNA for a read. Written
by the port-driver for a write. Cleared internally upon power up.

PCBB +2

(02)

LOOP

Internal Loopback Mode - Disables the
DEUNA from the transceiver, and loops

the output of the DEUNA transmitter logic
to the input of the receiver logic. The colli-

sion test fails if enabled during transmissions

with LOOP

set.

Written by the

DEUNA for a read. Written by the portdriver for a write. Cleared internally upon
power up.

PCBB +2

(01)

PCBB +2

(00)

;

MBZ

Must be zero.

HDPX

Half-Duplex Mode — When clear, indicates
that the DEUNA will receive messages

transmitted to itself over the

wire.

Messages received in this manner will not
undergo CRC check use; CRC error status
will be returned with them.

When set, indicates that the DEUNA will
not receive messages transmitted to itself.
However, the DEUNA recognizes the
transmitted message as being addressed to
itself and sets the MTCH bit in the transmit
ring

following the

tranmission

Cleared internally upon power up.

Port Driver Checks

Resultant Error

(PCBB + 0)(15:08)=0
(PCBB +2){(10,08:04,01)=0

Function Error
Function Error — Write Function Check Only

4-38

attempt.

4.4.10

Function Codes 16/17 - Read/Read and Clear Port Status

This function is used by the port-driver to read and clear status from the DEUNA. Function code 17 will
clear the high byte of PCBB+2. Refer to Figure 4-18 and Table 4-23 for PCBB bit format and bit
descriptions.

MBZ

ERRS|MERR

CERR{TMOT

RRNG|TRNG|PTCH|RRAM

00
|

o/1|

RREV

CURMLT

:PCBB+0

:PCBB+2

MAXMLT

:PCBB+4

MAXCTR

:PCBB+6

TK-8072

Figure 4-18

Function Codes 16/17 — Read/Read and Clear
Port Status PCBB Bit Format

Table 4-23

Function Code 16/17 — Read/Read and Clear
Port Status

Word

Bits

Field

Description

PCBB +0

(15:08)

MBZ

Must be zero.

PCBB+0

(07:00)

OPCODE

OPCODE=16 — Read status from the
DEUNA.

OPCODE=17 - Read status

from the

DEUNA and clear status in the DEUNA.

Written by the port-driver; unchanged by
the DEUNA.

PCBB +2

(15)

ERRS

Error Summary — Logical OR of MERR,
RBUF, TMOT, FNER, RRNG, TRNG,
and

LEN.

Written by

the

DEUNA;

unchanged by the port-driver.

PCBB +2

(14)

MERR

Multiple Errors — Multiple ring access
errors encountered while handling buffer
access errors.

Written by the DEUNA;

unchanged by the port-driver.

PCBB +2

(13)

ZERO

4-39

Table 4-23

Function Code 16/17 — Read/Read and Clear
Port Status (Cont)

Word

Bits

Field

Description

PCBB +2

(12)

CERR

Collision Test Error — The transceiver collision circuit has failed to activate following
a transmission. Written by the DEUNA;
unchanged by the port-driver.

PCBB +2

(11)

TMOT

Timeout Error — UNIBUS timeout error
encountered while performing ring access.
Written by the DEUNA; unchanged by the

port-driver.
PCBB +2

(10)

ZERO

PCBB +2

(09)

RRNG

Receiver Ring Error — DEUNA encoun-

tered a ring parsing error while accessing
the receive descriptor ring. Written by the
DEUNA; unchanged by the port-driver.

PCBB +2

(08)

TRNG

Transmit Ring Error — DEUNA encoun-

tered a ring parsing error while accessing
the transmit descriptor ring. Written by the
DEUNA; unchanged by the port-driver.

PCBB +2

(07)

PTCH

ROM Patch — DEUNA WCS contains a
patch for the ROM based operational micr-

ocode. Set by the DEUNA; unchanged by
the port driver.
PCBB +2

(06)

RRAM

RAM Microcode Operational — DEUNA is

executing from RAM rather than ROM
microcode.

Written

the

DEUNA;

unchanged by the port-driver.

PCBB +2

(05:00)

RREV

ROM revision — The revision number of the

DEUNA on-board microcode. Written by
the DEUNA; unchanged by the port-driver.

4-40

Table 4-23

Function Code 16/17 — Read/Read and Clear
Port Status (Cont)

Word

Bits

Field

Description

PCBB +4

(15:08)

CURMLT

The current number of multicast IDs residing in the DEUNA. Zero upon power up.
Written by the DEUNA; unchanged by the
port-driver.

PCBB +4

(07:00)

MAXMLT

Maximum number of multicast IDs the
DEUNA will support: ten. Written by the
DEUNA; unchanged by the port-driver.

PCBB + 6

(15:00)

MAXCTR

Maximum length in words of the data block
reserved for counters. Implies the maxi-

mum number of counters. Written by the
DEUNA; unchanged by the port-driver.
Port Driver Checks

Resultant Error

(PCBB +0)(15:08)=0
(PCBB +2)(13,10)=0

Function Error
Function Error — Write Function Check Only

4.4.11
Function Codes 20/21 - Dump/Load Internal Memory
These functions are used to block move data or microcode between the host memory and the internal
memory (WCS) of the DEUNA. It is used for maintenance purposes such as diagnostics. The data move
is done by the DEUNA. Refer to Figure 4-19 and Table 4-24 for the PCBB bit format and bit
descriptions. Refer to Figure 4-20 and Table 4-25 for UDBB format and bit descriptions.

08
MBZ

0/1

MBZ | :PCBB+2

UDBS8 <15:01>
IGNORED

:PCBB+0

MBZ

IGNORED

UDBB
<17:16>

:PCBB+4

:PCBB+6

TK-9073

Figure 4-19

Function Codes 20/21 — Load/Dump Internal
Memory PCBB Bit Format

4-41

Table 4-24

Function Code 20/21 — Dump/Load Internal
Memory PCBB Bit Descriptions

Word

Bits

Field

Description

PCBB+0

(15:08)

MBZ

Must be zero.

PCBB +0

(07:00)

OPCODE

OPCODE =20 — Dump internal RAM of
DEUNA.

OPCODE=21 - Load internal RAM of
DEUNA.

PCBB +2

(15:01)

UDBB
(15:01)

Address bits (15:01) of the UNIBUS Data
Block Base. Written by the port-driver;
unchanged by the DEUNA.

PCBB +2

(00)

MBZ

Must be zero.

PCBB +4

(15:08)

IGNORED

Ignored by the DEUNA.

PCBB +4

(07:02)

MBZ

Must be zero.

PCBB + 4

(01:00)

UDBB
(17:16)

The high order two address bits of the
UNIBUS Data Block Base. Written by the
port-driver; unchanged by the DEUNA.

PCBB +6

(15:00)

IGNORED

Ignored by the DEUNA.

Port Driver Checks

Resultant Errors

(PCBB + 0)(15:08) =0
(PCBB +2)(00)=0
(PCBB +4)(07:02) =0

Function Error

State# RUNNING

Function Error — Write Function Checks Only

Function Error
Function Error

4-42

FLEN <15:01>

MBZ | :UDBB+0

HDBB <15:01>

MBZ | :uDBB+2
HDBB

MBZ

<17:16>

IDBB <15:01>

:UDBB+4

MBZ | :UDBB+6

TKH074

Figure 4-20

Function Codes 20/21 — Load/Dump Internal
Memory UDBB Bit Format

Table 4-25

Function Code 20/21 — Load/Dump

Internal Memory UDBB Bit Descriptions

Word

Bits

Field

Description

UDBB +0

(15:01)

FLEN

Function length — An unsigned integer indicating the number of words to be trans-

ferred between UDBB and IDBB. Set by
the port-driver; unchanged by the DEUNA.

UDBB+0

(00)

MBZ

Must be zero.

UDBB +2

(15:01)

HDBB
(15:01)

Address bits (15:01) of the Host Memory
Data Block Base. Written by the portdriver; unchanged by the DEUNA.

UDBB +2

(00)

MBZ

Must be zero.

UDBB +4

(15:02)

MBZ

Must be zero.

UDBB +4

(01:00)

HDBB
(17:16)

The high order two address bits of the Host
Memory Data Block Base. Written by the
port-driver; unchanged by the DEUNA.

UDBB + 6

(15:01)

IDBB
(15:01)

Address bits {15:01) of the Internal Data
Block Base. Written by the port-driver;
unchanged by the DEUNA.

UDBB+6

{00)

MBZ

Must be zero.

Port Driver Checks

Resultant Error

(UDBB + 0){(00)=0
(UDBB +2){(00)=0
(UDBB +4)(15:02) = 0
(UDBB +6){00) =0

Function Error
Function Error
Function Error

Function Error

4-43

4.4.12 Function Codes 22/23 - Read/Write System ID Parameters
These functions are used by the port-driver to read or write the System Identification Parameter list of the
DEUNA and verification code for boot functions. Refer to Figure 4-21 and Table 4-26 for PCBB bit

formats and bit descriptions.
descriptions.

Refer to Figure 4-22 and Table 4-27 for UDBB bit formats and bit

MBZ

| o1

UDBB <15:01>

| :pcBB+O

mBz | :PCBB+2
UDBB

MBZ

<1715

PLTLEN

PCBB+4

:PCBB+6

TK8075

Figure 4-21

Function Codes 22/23 — Read/Write System ID
Parameters PCBB Bit Format

Table 4-26 Function Code 22/23 - Read/Write System
ID Parameters PCBB Bit Descriptions
Word

Bits

Field

Description

PCBB+0

(15:08)

MBZ

Must be zero.

PCBB+0

(07:00)

OPCODE

OPCODE =22 - Read system ID parameter list out of the DEUNA.

OPCODE =23 — Write system ID parameter list into the DEUNA.
Written by the port-driver; unchanged by
the DEUNA.

PCBB +2

(15:01)

UDBB
(15:01)

The low order 15 address bits of the
UNIBUS Data Block Base. Written by the
port-driver; unchanged by the DEUNA.

PCBB +2

(00)

MBZ

Must be zero.

4-44

Table 4-26

Function Code 22/23 — Read/Write System

ID Parameters PCBB Bit Descriptions (Cont)
Word

Bits

Field

Description

PCBB +4

(15:02)

MBZ

Must be zero.

PCBB +4

(01:00)

UDBB

The high order two address bits of the
UNIBUS Data Block Base. Written by the
port-driver; unchanged by the DEUNA.

(17:16)

PCBB +6

(15:01)

PLTLEN

System ID Parameter list length. The
length in words of the UNIBUS Data Block
Base. Written by the port-driver;

unchanged by the DEUNA. The maximum
value of PLTLEN is 100 decimal.
When reading the System ID Parameter
list, if the PLTLEN field is less than 100
words, the DEUNA will return, without
error, a truncated list equal to the number
asked for, starting with the first entry in the
list.

When reading or writing the System ID
Parameter list, if the PLTLEN field is
greater than 100 words, the DEUNA will
abort the command and set the appropriate
error status.

Port Driver Checks

Resultant Error

(PCBB +0)(15:08)=0
(PCBB +2){(00)=0
(PCBB +4){(15:02)=0
(PCBB +6){(00)=0

Function Error

27<PLTEN=100 decimal

Function Error

Function Error
Function Error
Function Error

4-45

OPCODE =22

READ SYSTEM ID PARAMETER LIST.

OPCODE =23

WRITE SYSTEM ID PARAMETER LIST.

VC <15:00>

:UDBB+0

VC <31:16>

:UDBB+2

VC <47:32>

:uDBB+4

VC <63:48>

:UDBB+6

MBZ

SOFTID
UNDEFINED

MBZ

:UDBB+10
:UDBB+12

UNDEFINED

:ubDBB+14

UNDEFINED

:UDBB+16

UNDEFINED

:UDBB+20

UNDEFINED

:uDBB+22

UNDEFINED

:UDBB+24

TYPE

:UDBB+26

CCOUNT

:UDBB+30

CODE

:UDBB+32

RECNUM

:UDBB+34

MVTYPE

:UDBB+36

MVVER

MVLEN

:UDBB+40

MVUECO

MVECO

:UDBB+42

FVAL1

FLEN

:UDBB+46

HATYPE <07:00>

FVAL2

:UDBB+50

HATYPE <15:08>

:UDBB+52

FTYPE

:UDBB+44

HALEN
HA <15:00>

:UDBB+54

HA <31:16>

:UDBB+56

HA <47:32>

:UDBB+60

DTYPE
DVALUE

:UDBB+62
DLEN

:UDBB+64

PARAM

:uDBB+66

PARAM

:uDBB+70

PARAM

:UDBB+72

PARAM
TK9057

Figure 4-22

Function Codes 22/23 — Read/Write System ID
Parameters UDBB Bit Format

4-46

Table 4-27

Function Code 22/23 — Read/Write System

ID Parameters UDBB Bit Descriptions

Word

Bits

Field

Description

UDBB +0

(15:00)

VC(15:00)

WordO of the Boot verification code.

UDBB +2
UDBB +4
UDBB +6

(15:00)
(15:00)
(15:00)

VC(31:16)
VC(47:32)
VC(63:48)

Word1 of the Boot verification code.
Word?2 of the Boot verification code.
Word3 of the Boot verification code.
Written by the DEUNA for read function;
written by the port-driver for a write func-

tion. The DEUNA default value of the verification code is VC(63:00) =0.
UDBB+ 10

(15:08)

MBZ

Zeros.

UDBB+ 10

(07:00)

SOFTID

Software Identification — Written by the

UDBB + 12

(15:00)

Undefined

UDBB + 14

(15:00)

Undefined

UDBB+ 16

(15:00)

Undefined

UDBB +20

(15:00)

Undefined

UDBB + 22

(15:00)

Undefined

UDBB +24

(15:00)

Undefined

UDBB + 26

(15:00)

DEUNA for read function; written by the
port-driver during a write function. The
DEUNA default value is SOFTID = 0.

TYPE

ETHERNET Type — Written by the

DEUNA for a read function; written by the
port-driver for a write function.

The

DEUNA default value is 260 hex.

UDBB + 30

(15:00)

CCOUNT

Character Count — Written by the DEUNA
for a read function; written by the port-

driver for a write function. The DEUNA

default value is COUNT = 28 decimal.

UDBB + 32

(15:00)

MBZ

Zeros

4-47

Table 4-27

Function Code 22/23 — Read/Write System
ID Parameters UDBB Bit Descriptions (Cont)

Word

Bits

Field

UDBB + 32

(07:00)

CODE

Description
Code — Written by the DEUNA for a read

function; written by the port-driver for a
write function. The DEUNA default value

is CODE=7.

UDBB + 34

(15:00)

RECNUM

Receipt number — Written by the DEUNA
for a read function; written by the portdriver for a write function. The DEUNA
default value is RECNUM =0.

UDBB + 36

(15:00)

MVTYPE

MOP

Version Type — Written by the
DEUNA for a read function; written by the

port-driver

for a write function. The
DEUNA default value is MVTYPE=1.

UDBB +40

(15:08)

MVVER

MOP Version/Version — Written by the
DEUNA for a read function; written by the
port-driver
DEUNA

UDBB +40

(07:00)

MVLEN

for

write

function.

The

default value is MVVER =3,

MOP Version Length — Written by the
DEUNA for a read function; written by the
port-driver for

write

function.

The

DEUNA default value is MVLEN = 3.

UDBB +42

(15:08)

MVUECO

MOP Version User ECO — Written by the
DEUNA for a read function; written by the
port-driver
DEUNA

UDBB +42

(07:00)

MVECO

for a write function. The
default value is MVUECO =0.

MOP

Version ECO - Written by the
DEUNA for a read function; written by the

port-driver

for

write

function.

The

DEUNA default value is MVECO =0.

UDBB + 44

(15:00)

FTYPE

Function Type — Written by the DEUNA
for a read function; written by the portdriver for a write function. The DEUNA

default value is FTYPE =2.

4-48

Table 4-27

Function Code 22/23 — Read/Write System

ID Parameters UDBB Bit Descriptions (Cont)
Word

Bits

Field

Description

UDBB +46

(15:08)

FVAL1

Function value 1 — Written by the DEUNA
for a read function; written by the port-

driver for a write function. The DEUNA
default value is FVAL1=35.
UDBB + 46

(07:00)

FLEN

Function Length — Written by the DEUNA

for a read function; written by the portdriver for a write function. The DEUNA
default value is FLEN =2.
UDBB + 50

(15:08)

HATYPE

(07:00)

Byte O of the Hardware Address Type —

Written by the DEUNA for a read function;
written by the port-driver for a write function. The DEUNA default value is
HATYPE=7.
UDBB + 50

(07:00)

Function Value 2 — Written by the DEUNA
for a read function; written by the port-

FVAL2

driver for a write function. The DEUNA

default value is FVAL2=0.
UDBB +52

(15:08)

Hardware Address Length — Written by the
DEUNA for a read function; written by the
port-driver for a write function. The

HALEN

DEUNA default value is HALEN =6.
UDBB +52

(07:00)

HATYPE

(15:08)

Byte 1 of the Hardware Address Type —

Written by the DEUNA for a read function;
written by the port-driver for a write function. The DEUNA default value is
HATYPE=0.
UDBB + 54
UDBB + 56
UDBB + 60

(15:00)
(15:00)
(15:00)

HA(15:00)
HA(31:16)
HA(47:32)

WordO of the Hardware Address
Word1 of the Hardware Address
Word?2 of the Hardware Address

Written by the DEUNA for a read function;
written by the port-driver for a write func-

tion. The DEUNA default value is the
default physical address.

4-49

Table 4-27

Function Code 22/23 — Read/Write System
ID Parameters UDBB Bit Descriptions (Cont)

Word

Bits

Field

Description

UDBB + 62

(15:00)

DTYPE

Device Type — Written by the DEUNA for
a read function; written by the port-driver
for a write function. The DEUNA default
value is DTYPE = 64 hex.

UDBB + 64

(15:08)

DVALUE

Device Value — Written by the DEUNA for
a read function; written by the port-driver
for a write function. The DEUNA default
value is DVALUE=1.

UDBB + 64

(08:00)

DLEN

Device Length — Written by the DEUNA
for a read function; written by the portdriver for a write function. The DEUNA
default value is DLEN =1,

UDBB + 66

(15:00)

PARAM

Additional Parameters — Written by the
DEUNA for a read function; written by the
port-driver for a write function.

Port Driver Checks
None

4.4.13

Function Codes 24/25 - Read/Write Load Server Address
Function codes 24 and 25 read or change the Load Server Address used by the DEUNA when in the
Primary Load State (refer to Section 4.10.2.4). If no write function occurs prior to being issued a Read
function, the DEUNA will return the Load Server Multicast address (AB-00-00-01-00-00 hex). Refer to
Figure 4-23 and Table 4-28 for PCBB bit format and bit descriptions.

NOTE
In this Chapter the hex value of the multi-byte fields

will be shown in parentheses (0123) and then the
order of transmission is shown following 23-01 hex
with 23 being the least significant byte. The least

significant bit of the least significant byte (23) is
transmitted first.

4-50

MBZ

0/1

:PCBB+0

LSA <15:00>

:PCBB+2

LSA <31:16>

:PCBB+4

LSA <47:32>

:PCBB+6

TK-8077

Figure 4-23

Function Codes 24/25 — Read/Write Load Server
Address PCBB Bit Format

Table 4-28

Function Code 24/25 — Read/Write Load Server

Address PCBB Bit Descriptions

Word

Bits

Field

PCBB+0

(15:08)

MBZ

Description
Must be zero.
Written by the port-driver; unchanged by

the DEUNA.

PCBB +0

(07:00)

OPCODE

OPCODE =24 -

Read

Load

Server

OPCODE =25 — Write Load

Server

Address.
Address.
Written by the port-driver; unchanged by
the DEUNA.

PCBB +2

PCBB +4

PCBB+6

(15:00)

LSA

The low order 16 address bits of the load

(15:00)

server address.

LSA

The middle order 16 address bits of the load

(31:16)

server address.

LSA

The high order 16 address bits of the load

(47:32)

server address.
Written by the DEUNA for a read function.

Written by

function.

Port Driver Checks

Resultant Error

(PCBB +0)(15:08)=0

Function Error

4-51

the

port-driver for a

write

4.5

TRANSMIT DESCRIPTOR RING ENTRY

The Transmit Descriptor Ring Entry is located in host memory. It tells the DEUNA the attributes of a
data buffer in host memory to be transmitted on the ETHERNET. It also reports back to the host the
status of the packet after it is sent. Refer to Figure 4-24 and Table 4-29 for the Transmit Descriptor Ring
Base Format and bit descriptions.

514

1110

SLEN <15:00>

:TDRB+0

SEGB <15:00>

:TDRB+2

OWN | ERRS [MTCH|MORE| ONE | DEF | sTP | ENP

MBZ

BUFL|{UBTO|

TDR

|LCOL|LCAR|RTRY

<f§:G12>

:TDRB+4
:TDRB+6

RESERVED FOR PORT DRIVER

:TDRB+10

RESERVED FOR PORT DRIVER

:TDRB+12

dh‘

fl-

[~
RESERVED FOR PORT DRIVER

TKL076

Figure 4-24

Transmit Descriptor Ring Entry Format

Table 4-29

Transmit Descriptor Ring Base

(TDRB) Bit Descriptions

Word

Bits

Field

TDRB +0

(15:00)

SLEN

Description
Segment Length — Number of bytes in a
segment. Illegal if the number of bytes in
the transmitted data field is less than 64 or
greater than 1518 unless TPAD is enabled
for a message less than 64 bytes (refer to
Table 4-22).

Set by

the

port-driver;

unchanged by the DEUNA.

TDRB +2

(15:00)

SEGB

The low order 16 address bits of the segment pointed to by the descriptor. Written
by

the port-driver;

unchanged by

the

DEUNA.

TDRB + 4

(15)

OWN

Port ownership - Indicates that the descriptor entry is owned by the port-driver (=0)
or by the DEUNA (=1). Set by the portdriver; cleared by the DEUNA.

4-52

Table 4-29

Transmit Descriptor Ring Base
(TDRB) Bit Descriptions (Cont)

Word

Bits

Field

Description

TDRB +4

(14)

ERRS

Error Summary — The logical OR of BUFL,

(13)

MTCH

TRDB +4

UBTO, LCOL, LCAR, and RTRY as
reported in word TDRB +6. Set by the
DEUNA; cleared by the port-driver.
Station Match — Set by the DEUNA when
the destination address of the transmit message matches one of the addresses of the
DEUNA.

TDRB +4

(12)

Multiple retries needed. Set by the DEUNA
when more than one retry was needed to
successfully transmit a packet; cleared by
the port-driver.

TDRB +4

(1)

ONE

One Collision — Set by the DEUNA when
exactly one retry was needed to transmit a
packet; cleared by the port-driver.

TDRB + 4

TDRB +4

(10)

DEF

STP

Deferred — Set when the DEUNA exper-

ienced no collisions but had to defer while
trying to transmit a packet; cleared by the
port-driver.
Start of packet — Set by the port-driver;
unchanged by the DEUNA. Used for intrapacket data chaining.

TDRB +4

(8)

End of packet — Set by the port-driver;
unchanged by the DEUNA. Used for intra-

ENP

packet data chaining.

TDRB +4

(07:02)

MBZ

Must be zero.

TDRB +4

(01:00)

SEGB

The high order two address bits of the segment pointed to by the descriptor. Written
by the port-driver; unchanged by the
DEUNA.

4-53

Table 4-29

Transmit Descriptor Ring Base

(TDRB) Bit Descriptions (Cont)

Word

Bits

Field

Description

TDRB +6

(15)

BUFL

Buffer length error — One or more of the
following conditions:
1.

The total length of the packet, including chained buffers, is less than the
length of the minimum allowable

packet length. This is 14 bytes if the
DEUNA is in the data padding mode
(TPAD=1). If the DEUNA is not in
the data padding mode, the minimum
length is 64 bytes if the DEUNA is
not in the disable transmit CRC
mode, or 60 bytes if the DEUNA is in
the disable transmit CRC mode
(DTCR =1). The BUFL bit is set in
the transmit descriptor ring entry in
which the packet length overflowed.
THe total length of the packet,
including chained buffers, exceeds
the length of the maximum allowable
packet length; 1514 bytes if the
DEUNA is not in the disable transmit
CRC mode, or 1518 bytes if the

DEUNA is in the disable transmit
CRC mode (DTCR=1). The BUFL
bit is set in the transmit descriptor
ring entry in which the packet length
overflowed.

While searching the ring to find the
beginning of a packet to be transmitted, the BUFL bit is set in each transmit descriptor ring entry it owns but
does not have the STP bit set while
DEUNA is searching for an STP flag.

4-54

Table 4-29

Transmit Descriptor Ring Base

(TDRB) Bit Descriptions (Cont)
Word

Bits

Field

Description

While in the data chaining mode, if
the DEUNA found an entry it owned
with the STP bit set, or encountered a
buffer it did not own while searching

for an entry in which the ENP bit was
set. The BUFL bit is set in the transmit descriptor ring entry before the
entry DEUNA does not own; BUFL

is set in the last entry the DEUNA
owns.

While in the data chaining mode, if

the DEUNA found an entry it owned
with the STP bit set, or encountered
an entry with the STP bit set while

searching for an entry in which the
ENP flag was set. The BUFL bit is set
in the transmit descriptor ring entry

before the entry containing the asserted STP flag.
Packet

transmission

does

not

occur

BUFL is set for one or more of the buffers
that

make

the

packet.

Set

the

DEUNA; cleared by the port-driver.

TDRB +6

(14)

UBTO

UNIBUS timeout — A UNIBUS timeout

was encountered while accessing the buffer
pointed to by the descriptor ring entry.
(Refer to

Section 4.9.8.)

Set by

the

DEUNA; cleared by the port-driver.

TDRB + 6

(13)

Zero

TDRB +6

(12)

LCOL

Late collision — A collision has occurred
after the

slot

time

of the

channel

has

elapsed. Set by the DEUNA; cleared by the
port-driver.

4-55

Table 4-29

Transmit Descriptor Ring Base

(TDRB) Bit Descriptions (Cont)

Word

Bits

Field

Description

TDRB +6

(11)

LCAR

Loss of carrier — Carrier was either not present on the channel during transmission

(indicating a shorted cable) or the carrier
was lost during transmission of a broken

carrier detect circuit. Set by the DEUNA;
cleared by the port-driver.

TDRB + 6

(10)

RTRY

Retry — Transmitter has

failed

attempts to transmit the packet due to colli-

sions on the medium. Set by the DEUNA;
cleared by the port-driver.

TDRB+6

(9:0)

TDR

Time domain reflectometry value — Valid
only when RTRY is set.

Port Driver Checks

Resultant Exrror

(TRDB +4)(07:02)=0

Ring Error

TPAD=1, DTCR=0

Ring Error

14 =< packet length = 1514
TPAD =0, DTCR=0

Ring Error

60 = packet length = 1514

TPAD=0, DTCR=1

Ring Error

64 =< packet length < 1518

4-56

4.6 RECEIVE DESCRIPTOR RING ENTRY
The Receive Descriptor Ring is located in host memory. It tells the DEUNA where to put received
messages and reports the status of those messages to the port-driver. Refer to Figure 4-25 and Table 4-30
for bit format and bit descriptions.

OWN

]

[ERRS |FRAM{OFLO|

BUFL{UBTO|NCHN|

CRC

SLEN <15:01>

MBZ | :RDRB+0

SEGB <15:01>

MBZ | :RDRB+2

STP | ENP

mBZ

SEGB
| :RDRB+4
.
.

<17:16>

MLEN

:RDRB+6

RESERVED FOR PORT DRIVER

:RDRB+10

RESERVED FOR PORT DRIVER

:RDRB+12

RESERVED FOR PORT DRIVER

TK8078

Figure 4-25

Receive Descriptor Ring Entry Format

4-57

Table 4-30

Receive Descriptor Ring Entry

Bit Descriptions

Word

Bits

Field

RDRB +0

(15:01)

SLEN

Description

Segment length — Number of bytes in a segment. Set by the port-driver; unchanged by

the DEUNA.
RDRB +0

(00)

MBZ

Must be zero.

RDRB +2

(15:01)

SEGB

Address bits (15:01) of the segment pointed
to by the descriptor. Written by the portdriver; unchanged by the DEUNA.

RDRB +2

(00)

MBZ

Must be zero.

RDRB +4

(15)

OWN

Port ownership — Indicates that the descriptor entry is owned by the port-driver (=0)

or by the DEUNA (=1). Cleared by the
DEUNA; set by the port-driver. Set by the

DEUNA; cleared by the port-driver.

RDRB +4

(13)

FRAM

Frame Error — Indicates that the incoming

packet contains a non-integer multiple of
eight bits. Set by the DEUNA,; cleared by

the port-driver.
RDRB +4

(12)

OFLO

Message Overflow — The message in the
buffer is longer than the maximum allowable ETHERNET packet. Data chaining was

not attempted; the message was truncated
to fit in the buffer. Set by the DEUNA;

cleared by the port-driver.
RDRB +4

(an

CRC

Cyclical Redundancy Check — Frame check
error, data is not valid. This bit is not valid

for maintenance operations with the DTCR
not set and loopback set, because the CRC
value is not checked during receive. Set by
the DEUNA, cleared by the port-driver.

RDRB +4

(10)

Zero

RDRB +4

STP

Start of packet — Set by the DEUNA,;
unchanged by the port-driver.

Used for

intra-packet data chaining.

RDRB +4

(8)

ENP

the

DEUNA;

unchanged by the port-driver.

End

of Packet —

Set

Used for

intra-packet data chaining.

4-58

Table 4-30

Receive Descriptor Ring Entry

Bit Descriptions (Cont)

Word

Bits

Field

Description

RDRB +4

(07:02)

MBZ

Must be zero.

RDRB +4

(01:00)

SEGB

(17:16)

The high order two address bits of the seg-

ment pointed to by the descriptor. Written
by

the port-driver;

unchanged by

the

DEUNA.

RDRB +6

(15)

BUFL

Buffer length error — Packet is within the

legal length, but the message does not fit
within the current buffer and the DEUNA

does not own the next buffer. The DEUNA
has truncated the message to fit within the
current buffer. Set by the DEUNA; cleared
by the port-driver.
RDRB +6

(14)

UBTO

UNIBUS Timeout — A UNIBUS timeout

was encountered while moving data into
the buffer pointed to by the descriptor
entry. (Refer to Section 4.9.8.) Set by the
DEUNA; cleared by the port-driver.

RDRB +6

(13)

NCHN

No Data Chaining — When set, indicates

when set that the DEUNA was in the nondata chaining mode at the time the buffer
was written. The message may be truncated
to fit in the single buffer. Other status infor-

mation is valid. STP and ENP are also set.
Written by the DEUNA; cleared by the
port-driver.

RDRB +6

(12)

Zero

RDRB +6

(11:00)

MLEN

Message length — The length in bytes of
packet placed in the buffer(s). This field is
valid only in the descriptor entry the ENP

flag is set in. Written by the DEUNA;
cleared by the port-driver.
Port Driver Checks

Resultant Error

(RDRB + 0){00) =0
(RDRB + 2)(00) =0
(RDRB + 0)(07:02) = 0

Ring error
Ring error
Ring error

4-59

4.7

TRANSMIT DATA BUFFER FORMAT
Transmit Data Buffers may begin on arbitrary byte boundaries. Refer to Figure 4-26 for the format of a
Transmit Data Buffer starting on an even byte boundary and Figure 4-27 for a Transmit Data Buffer
starting on an odd byte boundary.

00
FIRST BIT TO BE
TRANSMITTED

DESTINATION ADDRESS FIELD

LOADED BY THE PORT-DRIVER

6 BYTES

SOURCE ADDRESS FIELD

—]

6 BYTES

RESERVED BY THE PORT-DRIVER,
FIELD INSERTED BY THE DEUNA

TYPE FIELD — 2BYTES

_—

LOADED BY THE PORT-DRIVER

DATA FIELD

—

46 — 1500 BYTES

—

LOADED BY THE PORT-DRIVER,
MAY BE AN ODD NUMBER OF BYTES

—

|
i

LLAST DATA BIT TO
BE TRANSMITTED

Figure 4-26

Transmit Data Buffer Starting on an Even
Byte Boundary

4-60

TK-9046

FIRST BIT TO BE

TRANSMITTED

LOADED BY THE PORT-DRIVER

DESTINATION ADDRESS FIELD
6 BYTES

SOURCE ADDRESS FIELD
6 BYTES

RESERVED BY THE PORT-DRIVER,
FIELD INSERTED BY THE DEUNA

TYPE FIELD

LOADED BY THE PORT-DRIVER
TYPE FIELD

LOADED BY THE PORT-DRIVER

DATA FIELD
46 — 1500 BYTES

t_ LAST DATABITTO
BE TRANSMITTED

Figure 4-27

Transmit Data Buffer Starting on an Odd
Byte Boundary

4-61

TK-9066

4.8

RECEIVE DATA BUFFER FORMAT

Receive Data Buffers must begin on an even byte boundary. Refer to Figure 4-28 for the Receive
Data
Buffer Format.

e—-FIRST BIT RECEIVED

—

DESTINATION ADDRESS FIELD

LOADED BY THE DEUNA

6 BYTES

—

SOURCE ADDRESS FIELD

—

LOADED BY THE DEUNA

6 BYTES

TYPE FIELD — 2 BYTES

_—

DATA FIELD

LOADED BY THE DEUNA

—_

46 — 1500 BYTES

LOADED BY THE DEUNA

LLAST BIT RECEIVED
TK-9055

Figure 4-28

Receive Data Buffer Format

4-62

4.9

DEUNA OPERATION

4.9.1

Power On

When power is applied to the DEUNA, the device enters the RESET state.

In this state, the DEUNA

microprocessor initializes the device and executes a self-test. If the DEUNA passes the self-test and is not
enabled to perform a power-up boot sequence, it enters the READY state. The characteristics of the
READY state are:

The physical address of the DEUNA equals the default physical address contained in the

The multicast address list is empty.

The lengths of both the transmit and receive descriptor rings are zero. This indicates that ring

The mode register is clear.

The counters are clear.

The DEUNA responds to Port Commands.

All incoming messages to the DEUNA are discarded, except maintenance messages processed

System ID message is transmitted approximately every 10 minutes.

on-board PROM.

specification is not valid.

within the internal RAM of the DEUNA.

The results of a failure to pass self-test by one or both of the DEUNA modules are shown in Table 4-31.
The DEUNA can distinguish between power-up INIT and software INIT, and can determine if it should
execute a boot sequence if power on boot is enabled.

If the DEUNA passes the self-test and can perform the power-up boot sequence via a hardware switch, the
device enters the PRIMARY LOAD STATE. Refer to Section 4.10 for a description of power-up boot
operation.

Table 4-31

DEUNA Self-Test Failure Results

Failing Unit

Resultant State

Description

LINK/CABLE/TRANSCEIVER

NIHALTED

The DEUNA isolates

PORT/UNIBUS

UNIBUS HALTED

The DEUNA does not

itself from the physical
channel.

become

UNIBUS

master.

LINK/PORT

NI and UNIBUS HALTED

The DEUNA does not
access

the

become
master.

NOTE

If the system UNIBUS arbitor is off, self-test will
fail.
4-63

channel

UNIBUS

4.9.2 Port Command Capability
The primary means of communication between the DEUNA and the Host processor is through the Port

Command facility. Table 4-32 summarizes the DEUNA Port Commands. A more detailed description of
the DEUNA Port Commands can be obtained by referring to Section 4.3.
The Port Command Operation uses three fields in PCSRO:

The Done Interrupt (DNI) bit (11), PCEI

Error Interrupt bit (14), and the Port Command Field bits (03:00). Refer to Figure 4-29 for a description
of the Port Command sequence.

Table 4-32

DEUNA Port Commands

Command

Description

GET PCBB

Fetch the base address of the Port Control Block.

GET COMMAND

Fetch and execute the Port Function specified in the Port Control
Block.

SELF-TEST

Enter RESET State and execute Self Test.

START

Start the Reception and Transmission Processes.

STOP

Stop the Reception and Transmission Processes.

BOOT

Boot DEUNA microcode via down-line load.

POLLING DEMAND

Poll the transmit and receive rings for a new message to transmit
or a new free receive buffer.

4-64

PORT-DRIVER
SETS UP REQUIRED
MEMORY STRUCTURES

PCEI & DNI
BITS CLEAR

CLEAR PCE! &
DNI BITS BY
WRITING ONES

YES

PORT-DRIVER

WRITES PORT
COMMAND CODE
IN BITS <03:00>
PCSRO

y
DEUNA
EXECUTES

COMMAND

ERRORS

DEUNA SETS PCEI

DEUNA SETS DNI

'
END OF PORT

COMMAND
SEQUENCE

NOTE:
PORT DRIVER MUST WAIT
FOR DEUNA TO COMPLETE
COMMAND BEFORE ISSUING
ANOTHER COMMAND
TK-9518

Figure 4-29

Port Command Sequence

4-65

4.9.3

Software Initialization

A sequence of Port Commands must be issued by the port-driver to prepare the DEUNA for datagram

service.

See Figure 4-30 for a description of the DEUNA Initialization Sequence.

POWER

UpP

NOTE:

[

RESET
‘

AFTER SUCCESSFUL RESET PCSRO AND THE LOW

BYTE OF PCSR1 ARE IN THE POWERED UP STATE.

THE LOW BYTE OF PCSR1 SHOULD READ "2" =

READY STATE.

PCSR’s
2 AND 3 ARE UNCHANGED

BY RESET AND MUST BE CLEARED BY WRITING

fiBB

ZEROS.

WRITE
RING

OPTIONAL

START

WRITE
PHYSICAL

WRITE
MULTICAST

ADDRESS

WRITE
MODE

POLLING
DEMAND

INITIALIZATION

COMPLETE
TK-9519

Figure 4-30

4.9.4

DEUNA Software Initialization Sequence

Polling

The DEUNA maintains a set of three pointers to each transmit and receive descriptor ring. They are base,
current, and next address.

Base Address of Receive Descriptor Ring — Points to the lowest addressed receive descriptor
ring entry. This pointer is a constant.
Base Address of Transmit Descriptor Ring — Points to the lowest addressed transmit descriptor
ring entry. This pointer is a constant.

Current Address of Receive Descriptor Ring - Points to the current position in the receive ring.
This pointer is a variable.
Current Address of Transmit Descriptor Ring — Points to the current position in the transmit
ring. This pointer is a variable.
Next Address of Receive Descriptor Ring — Points to the receive descriptor entry following the
Current Address pointer. This pointer is a variable.

Next Address of Transmit Descriptor Ring — Points to the transmit descriptor entry following
the Current Address pointer. This pointer is a variable.
4-66

Upon entering the RUNNING state, the current and next pointers are initialized as in Example 4-2.
Buffer acquisition is defined as the DEUNA reading the first three words of the descriptor entry: Status,
Buffer Length, and Buffer Address (refer to Sections 4.5 and 4.6). If the OWN bit is set the DEUNA is said
to have acquired the buffer. The DEUNA cannot acquire a buffer in which the OWN bit is clear.

Buffer release is defined as the DEUNA writing third and fourth word of a descriptor entry (refer to
Sections 4.5 and 4.6) and clearing the OWN bit. The DEUNA may not write a descriptor entry or the
buffer it points to without first acquiring it .

BEGIN
Current Address := Base Address;

Next Address : = Base Address;
END;
Advancing to the next entry is defined as follows:
BEGIN

Current Address := Next Address;
IF Next Address := last entry in the ring
THEN Next Address := Base Address

ELSE Next Address := Next Address + word length of entry
END;

Example 4-2

Ring Pointer Initialization

4.9.4.1 Receive Polling — Receive polling is the DEUNA acquiring free buffers on the receive descriptor
ring, writing packet data into the buffers, writing status into the descriptor entry, and advancing to the
next entry on the ring.

The DEUNA never advances its Current Address pointer beyond a descriptor entry it has not acquired.
The DEUNA always tries to acquire one free buffer in anticipation of incoming messages. The DEUNA
performs receive polling under the following conditions.

Immediately after being placed in the RUNNING state.

Inresponse to a Polling Demand port command in the RUNNING state when the DEUNA has
not acquired a free buffer.

The DEUNA has received a message and has not acquired a free buffer.

The DEUNA is writing a buffer pointed to by the current descriptor ring entry and has not
acquired the next buffer.

The DEUNA has written a complete message to the receive descriptor ring and has not
acquired a new buffer.

4-67

If the message to be written to the receive ring is larger than the buffer the DEUNA has acquired for it,
the DEUNA attempts to chain that buffer and sequential buffers together to build the message. (Buffer
chaining must be enabled by writing to the mode register; see Section 4.4.8.) The STP flag is set by the
DEUNA in the first descriptor entry; the ENP flag is set in the last descriptor entry to delimit the
message.

While in data chaining mode, the DEUNA tries to acquire the next buffer before releasing the current
buffer. In doing so, the DEUNA is guaranteed an entry in which to report status should the DEUNA run

out of buffers. The DEUNA always sets the ENP flag in the last buffer it releases for a message. The
DEUNA only writes status into the entry in which the ENP flag is set. (Status is only valid in the entry in
which the DEUNA sets the ENP flag.) The DEUNA writes a maximum of one packet in any one buffer.
4.9.4.2 Transmit Polling - Transmit polling is the DEUNA searching the transmit ring, finding and
building messages from it, and reporting the status of the attempted transmission. The DEUNA must be
in the RUNNING state for it to poll. The port driver directs the DEUNA to do transmit polling by
issuing the PDMD port command only. Once the DEUNA starts polling the transmit ring, it continues in
sequential order until it finds an entry in which the OWN bit is clear. At that time, transmit polling is
suspended until it is reinitiated by the port driver issuing the PDMD port command.
The transmit polling sequence is as follows:

The DEUNA is in the RUNNING state and the port driver issues the PDMD port command.

After a conditional poll of the receive descriptor ring, the DEUNA reads the current entry of
the transmit descriptor ring. If the DEUNA is performing the first poll after entering the
RUNNING state, it starts at the base address of the transmit ring.

If the OWN bit is not set, indicating that the DEUNA does not own the descriptor entry, the

If the OWN bit is set, but the STP bit is not set (indicating that the DEUNA owns the entry,
but the entry is not the beginning of a message) the DEUNA reads data in, steps to the next

DEUNA suspends transmit polling.

descriptor entry, and tests the OWN bit.

If the OWN bit is set and the STP bit is set, indicating that the DEUNA has found the
beginning of a message, the DEUNA reads the buffer into its internal buffer.

If the ENP bit is also set in the entry in which the STP bit was set, indicating that the entire
message is contained in the buffer, the DEUNA attempts transmission, writes the status
into the entry, and clears the ownership bit.

Data chaining occurs if the ENP bit is not set in the entry in which the STP bit was set.
Before clearing the ownership bit of the current entry, the DEUNA looks ahead to the next
entry. If the DEUNA owns the next entry, it clears the current entry. The next entry now
becomes the current entry, the data in the buffer is appended to the internal DEUNA
buffer, and the test for ENP is repeated.

This procedure is repeated until the ENP flag is found or an error is encountered. Transmission does not begin until the entire message is resident in the DEUNA internal memory.
After transmission is attempted, the DEUNA writes the appropriate status into the last
entry it has acquired and clears the ownership bit.

4-68

If, while in the transmit data chaining mode, the DEUNA encounters a situation that
prevents acquisition of the entire message, or the message is found to be too large, the
DEUNA writes status into the current entry it owns and clears the OWN bit.

The DEUNA repeats this procedure until it finds an entry it does not own, which causes
transmit polling to cease.

4.9.5 Datagram Reception
Messages arrive at the DEUNA asynchronously. Upon receipt, the DEUNA strips the preamble as it
searches for the start bit. After finding the start bit, the DEUNA compares the next six bytes against its
table of addresses. If the address comparison is not successful, the DEUNA ignores the message. If the
address comparison is successful, the DEUNA stores the message in internal memory. If the message is
shorter than 64 bytes, the DEUNA purges internal memory and retains no status of the message.
Messages longer than 64 bytes are reported to the ring descriptors.
4.9.6 Datagram Transmission
After acquiring and building a transmit packet in link memory, the DEUNA attempts transmission. The
DEUNA transmits only after an interpacket gap has elapsed (during which it sees no activity on the wire).
The format of the outbound data stream is given in Table 4-33.
If a collision occurs during transmission, the DEUNA aborts the transmission, performs a “collision jam,”
reschedules based upon the truncated binary backoff algorithm, and retransmits. The DEUNA will
attempt up to 16 transmissions per message.

Table 4-33

Format of an ETHERNET Data Packet

Message Part

Length (bytes)

Source

Preamble/Start bit

DEUNA

Destination Address

Data Buffer

Source Address

DEUNA

Type

Data Buffer

Data

46-1500

Data Buffer

CRC

DEUNA (optional)

4.9.7 Parameter Alteration
The DEUNA responds to all Port Functions in the READY state. The ability of the DEUNA to respond
to Port Functions while in the RUNNING state varies with the specific function. Table 4-34 summarizes
the impact of the DEUNA executing Port Functions while in the RUNNING state.

4-69

Table 4-34

RUNNING State Parameter Alteration Impact Summary

Function
Code

Function
Description

Impact*

No Operation

None

Load and Start Microaddress

Read Default Physical Address

Port
None
None

No Operation

Read Physical Address

None

Write Physical Address

Link

Read Multicast Address List

None

Write Multicast Address List

Link

Read Ring Format

None

Write Ring Format

Port

Read Counters

Read and Clear Counters

None
None

Read Mode

None

Write Mode

Link

Read Port Status

None

Clear Port Status

Dump Internal Memory

None
None

Load Internal Memory

Port

Read Load Server Address

None

Write Load Server Address

None

Read System ID Parameters

None

Write System ID Parameters

None

Impact:
1.

None — There is no disturbance to the receive or transmit packet throughput. Response to this Port Function is solely a

matter of microprocessor workload.
2.

Link — Response to these Port Functions require the DEUNA to temporarily disengage from the NI while the Link is

being modified.
]

Reception ~ All message activity during the Link modification time is ignored. Messages that completed prior to
Link modification time and resident in the DEUNA internal packet buffers are not discarded during Link
modification.

.
3.

Transmission — Any message being currently transmitted completes before the DEUNA disengages the link.

Port — The DEUNA should not be issued these Port Functions while in the RUNNING state. The DEUNA will execute
a No Operation if issued one of these functions in the RUNNING state and set the PCEI bit of PCSRO.

4-70

4.9.8

Suspension of Operation — Port Command

Suspension of DEUNA operation occurs when the DEUNA is issued a STOP Port Command while in the
RUNNING state. When the DEUNA receives a STOP Port Function:
1.

Any single transmission scheduled from the descriptor ring in the process of transmission is
allowed to complete.
All descriptor ring and buffer reads and writes stop.

All incoming packets are discarded, except for maintenance messages.

NOTE
While the DEUNA is in the running state, datagram
service is suspended for the following UNIBUS error
conditions.
¢

Port Command UNIBUS Timeout

Transmit Ring Error UNIBUS Timeout

Receive Ring Error UNIBUS Timeout

Before restarting datagram service, the port driver must
remove the DEUNA from the running state by issuing a
STOP port command.
4.9.9 Restart of Operation
The DEUNA operation restarts when the DEUNA is issued a START Port Command following a STOP
Port Command. If no Port Functions have been executed which alter the internal state of the DEUNA,
the following parameters remain intact from suspension to restart.
Physical Address

Multicast Address List
Ring Format
Mode

Counters
Status Register

The DEUNA retains no state information about descriptor ring entries; it owns no buffers after a restart.
The Current Address pointers are set to the Base Addresses of the rings after a restart.

4-71

4.9.10

DEUNA States

4.9.10.1

DEUNA State Related Functions - The DEUNA functions may be summarized as follows.
Command Response — The ability of the DEUNA to receive and execute Port Commands from
the UNIBUS conductor.

Datagram Service — The ability of the DEUNA to transmit and receive packets between the NI
and the buffers in UNIBUS memory using ring structures for communication between the
DEUNA and the Host CPU.
Counters - The ability of the DEUNA to maintain counter information relating to the activity
on the NI.
Loop Service - The ability of the DEUNA to receive and transmit special Loop packets
independent of the port-driver.
Remote Console - The ability of the DEUNA to recognize the Request ID and Boot message
and to generate the System ID message independent of the port-driver. The Boot message is
honored only if the DEUNA is Remote Boot Enabled.

Down-Line Load Service — The ability of the DEUNA to generate the Program Request
message and recognize the Memory Load with Transfer Address message independent of the
port-driver.

Table 4-35 summarizes the functions enabled in DEUNA states.
Table 4-35

DEUNA State Function Summary

STATE

Response

Command

Datagram
Service

Counters

Loop

Remote

Down-Line

RESET

LOAD

READY

RUNNING

Service

Console

Load Service

PRIMARY

UNIBUS
HALTED

NI
HALTED
NI AND

UNIBUS
HALTED

D = FUNCTION DISABLED
E = FUNCTION ENABLED

4-72

4.9.10.2

DEUNA State Transition — Table 4-36 summarizes the events that cause the DEUNA to make

a transition from one state to another.

Table 4-36

From State

Reset State

DEUNA State Transition

Transition Event

To State

Power up

Reset State

Self-Test Successful

Ready State

Power Up Flag set

Primary Load State

and Remote Boot

Enable Switch set
NI Halted State

Self-Test Failure
— Link Module

NI and UNIBUS

Self-Test Failure
— Port or Port/Link

Halted State

Module
Reset State

Bus Init,

Port Driver Reset
Primary Load State

State determine by

Successful Boot

down-line loaded

microcode

Unsuccessful System

Primary Load State

Boot
Fatal UNIBUS Error

UNIBUS Halted State

Fatal NI Error

NI Halted State

Fatal Internal Error

NI and UNIBUS

Halted State
Reset State

Bus Init,
Port Driver Reset

Successful Communications

READY State

Processor Boot

Memory Load Timeout on
Communications Processor
Boot

4-73

READY State

Table 4-36

DEUNA State Transition (Cont)

From State

Transition Event

To State

Ready State

Start Command

Running State

Boot Command,
Boot Message, and
Remote Boot Enable
Switch Set

Primary Load State

Fatal UNIBUS Error

UNIBUS Halted State

Fatal NI Error

NI Halted State

Fatal Internal Error

NI and UNIBUS
Halted State

Reset State

Bus Init,
Port Driver Reset

Running State

Stop Command

Ready State

Boot Command,

Primary Load State

Boot Message, and

Remote Boot Enable
Switch set

Fatal UNIBUS Error

UNIBUS Halted State

Fatal NI Error

NI Halted State

Fatal Internal Error

NI and UNIBUS
Halted State
Reset State

Bus Init,
Port Driver Reset

UNIBUS Halted

Boot Message and

State

Remote Boot Enable

Primary Load State

Switch set

Fatal Internal Error

NI and UNIBUS
Halted State

Bus Init,

Reset State

Fatal NI Error,

Port Driver Reset

4-74

Table 4-36

DEUNA State Transition (Cont)

From State

Transition Event

To State

NI Halted State

Fatal UNIBUS Error,

NI and UNIBUS

Fatal Internal Error

Halted State

Bus Init,
Port Driver Reset

Reset State

Bus Init,

Reset State

NI and UNIBUS
Halted State

Port Driver Reset

4.9.10.3 DEUNA State Information Retention — Table 4-37 summarizes the state of the internal
information retained or reset by the DEUNA when making a transition from one state to another.

Table 4-37

State Information Retention Summary

From State

To State(s)

Status of Internal State

Reset State

Primary Load State,
Ready State,
UNIBUS Halted State,
NI Halted State

Reset: Ring Formats
Counters Physical Address
Multicast Address List
Mode Register Status
Register Ring pointers
Internal Memory Load

Server Address System ID
PCSR(s)

Primary Load State

State information retained is a function of the down-line loaded microcode that is executing.
Ready State

Retained: Ring Formats

Primary Load State,
UNIBUS Halted State,

Counters Physical Address
Multicast Address List

NI Halted State

Mode Register Status

Running State,

Internal Memory Load
Server Address System ID
PCSRs

Reset: Ring Pointers

4-75

Table 4-37

From State

State Information Retention Summary (Cont)

To State(s)

Running State

Status of Internal State

Primary Load State,
Ready State,

Retained: Ring Formats
Counters Physical Address

UNIBUS Halted State,
NI Halted State

Multicast Address List
Mode Register Status
Register Ring pointers
Internal Memory Load
Server Address System ID
PCSRs

UNIBUS Halted
State

Primary Load State,
NI and UNIBUS

Retained: Ring Formats
Counters Physical Address

Halted State

Multicast Address List
Mode Register Status

NI Halted
State

NI and UNIBUS
Halted State

Retained: Ring Formats
Counters Physical Address
Multicast Address List
Mode Register Status

4.10

EXCEPTIONAL OPERATIONS

4.10.1

Channel Loopback

The ROM-based microcode of the DEUNA supports Channel Loopback independent of the port-driver.
Loopback messages are recognized by the DEUNA as having the unique Loopback value in the type field

and either the physical address of the DEUNA or the broadcast address in the destination address field.
Refer to Figure 4-31 and Table 4-38 for the Loopback Message format and description. Messages with
multicast addresses other than broadcast are not checked by the DEUNA for the Loopback type. They
are treated as normal datagrams in the Running State only.
There are two types of Loopback messages: Forward and Reply. The Loopback type is determined by the
Function field within the message header.
e

Forward - Forward messages are transmitted by the DEUNA, but are not placed on the receive
descriptor ring.

Reply - Reply messages are placed on the receive descriptor ring, but are not transmitted.
Refer to Figure 4-32 for a detailed description of DEUNA Loopback processing.

4-76

DESTINATION ADDRESS/6 BYTES

SOURCE ADDRESS/6 BYTES

TYPE/2BYTES

SKIP COUNT/2 BYTES

OCTETS TO SKIP/N BYTES

FUNCTION/2 BYTES

FORWARD ADDRESS/6 BYTES

LOOP DATA/38—N TO 1490-N BYTES

CRC/4BYTES

TK-9054

Figure 4-31

Loop Message Format

4-77

Table 4-38

Field

Loopback Message Field Descriptions

Length (Bytes)

Description

INBOUND - The physical address of the

DESTINATION

ADDRESS

DEUNA, or the broadcast address

OUTBOUND — The forward address

SOURCE ADDRESS

INBOUND - The physical address of the
loop requesting station

OUTBOUND - The physical address of the
DEUNA

TYPE

The Loop test message type
Value = (0060) 60-00 hex

SKIP COUNT

INBOUND — The offset of the Function
field
OUTBOUND - The offset plus 8

OCTETS TO SKIP

Encapsulated loop header information (n =

0to 186)

FUNCTION

Reply, value = (0001) 01-00 hex
Forward, value = (0002) 02-00 hex

FORWARD ADDRESS

The physical address the inbound message
is to be sent to (This field does not exist for
areply message.)

LOOP DATA

The Loop test data

1490-8n

CRC

INBOUND - Block check character
OUTBOUND - DEUNA appended block

check character

4-78

DEUNA
IN PRIMARY

LOAD, READY,

RUNNING OR
UNIBUS HALTED
STATE

LOOPBACK
PROCESSING
DISABLED

MESSAGE

RECEIVED

LOOPBACK

VALUE IN
JTYPE FIELD

DMNT
OR DTCR
SET IN MODE
REGISTER

DESTINATION

ADDRESS
PHYSICAL OR

MESSAGE
YES

RUNNING

STATE

DISCARDED
LOOPBACK
PROCESSING

STOPS

MESSAGE TREATED
AS NORMAL DATAGRAM LOOPBACK
PROCESSING STOPS

BROADCAST

TK-9517

Figure 4-32

Loopback Message Processing Flow (Sheet 1 of 2)

4-79

DETERMINE

LOCATION OF
FUNCTION FIELD BY
ADDING VALUE IN
SKIP COUNT TO
LOCATION OF SKIP
COUNT +1

YES

MESSAGE TREATED

FORWARD

AS NORMAL

ADDRESS
PHYSICAL

BACK PROCESSING

MESSAGE DIS-

CARDED LOOPBACK PROCESSING

STOPS

DATAGRAM LOOP-

STOPS

If the Function Value is 2, indicating a message to be forwarded,
and the Forward Address field contains a physical address, the

UNA does the following:

Inserts the contents of the Forward Address field into the
Destination Address field.

Replaces the Source Address field with the physical address
of the UNA.

Adds 8 to the value of the Skip Count.

Strips the last four bytes, the CRC, from the message.

Transmits the resulting message, generating and appending
four bytes of CRC.
TK-9516

Figure 4-32

Loopback Message Processing Flow (Sheet 2 of 2)

4-80

4.10.2 Remote Console and Down-Line Load
The DEUNA ROM-based microcode Remote Console Server supports the following messages:
®

Request ID (Inbound to the DEUNA)

System ID (Outbound from the DEUNA)

Boot (Inbound to the DEUNA)

In addition, the following two dump/load type messages, associated with Boot, are supported by the
DEUNA ROM-based microcode:
®

Program Request (Outbound from the DEUNA)

Memory Load with Transfer Address (Inbound to the DEUNA)

The DEUNA Remote Console Server may be off or disabled. The ROM-based microcode of the
DEUNA only supports the ID and Boot functions of the Remote Console. When it is off, the DEUNA
will not honor the Request ID or Boot messages. The DEUNA Remote Console Server is off under the
following conditions:
®

Reset State

NI Halted State

NI and Unibus Halted State

DMNT (Disable Maintenance Message) bit in the mode register is set

DTCR (Disable Transmit CRC) bit in the mode register is set

The degree of Boot capability of the DEUNA Remote Console Server in the Primary Load, Ready,
Running, and UNIBUS Halted States depends on two on-board switches: the Boot Select Switches. Table
4-39 summarizes the Boot select capability of the DEUNA.

4-81

Table 4-39

Boot Select Capability of the DEUNA

Boot Select Switches
(M7792)
BOOT SEL 1

BOOT SEL 0

Boot Option

Remote Boot Disabled
)

Enabled

Disabled

Port Command System Boot
Remote Comm Processor Boot

Remote System Boot — Remote Load
Remote System Boot — Boot ROM
Power Up Boot

OFF

Remote Boot with System Load
e

Enabled

Port Command System Boot
Remote Comm Processor Boot

Remote System Boot — Remote Load
o

Disabled

Remote System Boot — Boot ROM
Power Up Boot

OFF

Remote Boot with ROM
]

Enabled

Port Command System Boot

Remote Comm Processor Boot
Remote System Boot — Boot ROM

Disabled
Remote System Boot — Remote Load
Power Up Boot

OFF

Remote Boot with Power Up Boot and System Load
°

Enabled
Port Command System Boot

Remote Comm Processor Boot
Remote System Boot — Remote Load
Power Up Boot
o

Disabled

Remote System Boot — Boot ROM

4-82

Boot Options are as follows:

Port Command System Boot - Result of a Boot Port Command. The DEUNA executes a

procedure that down-line loads the system secondary loader into DEUNA WCS microcode.
Note that a Port Command Boot is always honored while the DEUNA is in the Ready state.

Remote Comm Processor Boot — Boot message that down-line loads the DEUNA WCS.
Remote System Boot - Remote Load - Result of a Boot message. The DEUNA halts the
system and executes a procedure that down-line loads the system secondary loader into
DEUNA WCS microcode.

Remote System Boot — Boot ROM - Result of a Boot message. The DEUNA forces the
system boot by invoking the system Boot ROM. (The system Boot ROM is not resident on the
DEUNA.)
Power Up Boot — Result of system power up. The DEUNA halts the system and executes a
procedure that down-line loads the system secondary loader into DEUNA WCS microcode.

The DEUNA honors the Request ID message by sending a System ID message to the requesting station.
Refer to Figure 4-33 and Table 4-40 for Request ID Message format and field descriptions. Refer to
Figure 4-34 and Table 4-41 for System ID Message formats and field descriptions.

DESTINATION ADDRESS/6 BYTES

SOURCE ADDRESS/6 BYTES

TYPE/2BYTES

CHARACTER COUNT/2 BYTES

CODE/1 BYTE

PAD OF ZERO/1 BYTE

RECEIPT NUMBER/2BYTES

PAD DATA/43BYTES

CRC/4BYTES

TK-9053

Figure 4-33

Request 1D Message Format

4-83

The DEUNA also sends a System ID message every eight to ten minutes to the Remote Console Service
Multicast address. The Boot message is ignored when the Remote Console Server is Boot Disabled.
When Remote Boot is enabled, the DEUNA honors the Request ID message and sends the System ID
message as it does when Boot Disabled. In addition, the DEUNA honors the Boot message by entering the
Primary Load State.
I

If Remote Boot is disabled and the DEUNA is in the Running state, the Boot message is passed to the
port-driver as part of the normal datagram service.

Table 4-40

Field

Request ID Message Field Descriptions

Length (Bytes)

Description

ADDRESS

The physical address of the DEUNA

SOURCE ADDRESS

The

DESTINATION

physical

address

of the

requesting

station
TYPE

The Remote Console type
Value = (0260) 60-02 hex

CHARACTER COUNT

The number of bytes following the character count field less pad data and CRC
Value = 04 hex

CODE

The

function

code

for

the

Request

message

Value = 05 hex

PAD OF ZERO

Value = 00 hex

RECEIPT NUMBER

A receipt number to identify the request

PAD DATA

Pad characters, anything to pad the message out to 64 bytes

CRC

Incoming block check character

4-84

|07

00!

DESTINATION ADDRESS/6 BYTES

FUNCTION —~ TYPE/2 BYTES

SOURCE ADDRESS/6 BYTES

FUNCTION — LENGTH/1 BYTE

TYPE/2BYTES

FUNCTION — VALUE 1/1 BYTE

CHARACTER COUNT/2 BYTES

FUNCTION — VALUE 2/1 BYTE

CODE/1 BYTE

HARDWARE ADDRESS — TYPE/2 BYTES

PAD OF ZERO/1 BYTE

HARDWARE ADDRESS — LENGTH/1 BYTE

RECE!IPT NUMBER/2 BYTES

HARDWARE ADDRESS — VALUE/6 BYTES

MOP VERSION — TYPE/2 BYTES

DEVICE — TYPE/2 BYTES

MOP VERSION — LENGTH/1BYTE

DEVICE — LENGTH/1 BYTE

MOP VERSION — VERSION/1 BYTE

DEVICE — VALUE/1 BYTE

MOP VERSION — ECO/1 BYTE

PAD/PARAMETERS/16-144 BYTES

MOP VERSION — USER ECO/1 BYTE

CRC/4BYTES

TK-9052

Figure 4-34

System ID Message Format

4-85

Table 4-41
Field

System ID Message Field Descriptions

Length (Bytes)

Description

DESTINATION
ADDRESS

The physical address of the ID requesting
station

or the Remote

Console

Service

Multicast address Remote Console Service
Multicast

address

value

AB-00-00-02-00-00 hex
(00AB)
(0200)
(0000)

SOURCE ADDRESS

The physical address of the UNA

TYPE

The Remote Console type
Value = (0260) 60-02 hex

CHARACTER COUNT

The number of bytes following the character count field less pad data and CRC.

Value = (001C) 1C-00 to (00AE) AE-00
hex

CODE

The function code for the

System ID

message

Value = 07 hex
PAD OF ZERO

Value = 00 hex

RECEIPT NUMBER

A receipt number of identify the request

MOP VERSION - TYPE

Value = (0001) 01-00 hex

MOP VERSION - LENGTH

Value = 03 hex

MOP VERSION - VERSION

Value = 03 hex

MOP VERSION - ECO

Value = 00 hex

4-86

Table 4-41

Field

System ID Message Field Descriptions (Cont)

Length (Bytes)

Description

MOP VERSION - USER ECO

Value = 00 hex

FUNCTION - TYPE

Value = (0002) 02-00 hex

FUNCTION - LENGTH

Value = 02 hex

FUNCTION - VALUE 1

Value = 05 hex, the maintenance func-

tions supported; Loop, Primary Loader
Value

15 hex, the maintenance func-

tions supported, Loop, Primary Loader,
Boot
FUNCTION - VALUE 2

Value = 00 hex

HARDWARE ADDRESS -

Value = (0007) 07-00 hex

HARDWARE ADDRESS LENGTH

Value = 06 hex

HARDWARE ADDRESS
—

The default
DEUNA

DEVICE - TYPE

Value = (0064) 64-00 hex

DEVICE - LENGTH

Value = 01 hex

DEVICE - VALUE

Value = 01 hex (DEUNA device code)

PAD/PARAMETERS

16-146

TYPE

VALUE

physical

address

of the

Additional parameters supplied by portdriver through the Write System ID port
command. If not supplied, zeros are added
by the DEUNA to pad the message out to

64 bytes.
CRC

Outgoing block check character

4-87

4.10.2.1

Remote Boot - Incoming Boot messages invoke procedures within the DEUNA to down-line

load DEUNA microcode solely, referred to as Comm Processor Boot and System Boot. System Boots
initiated from a remote node may be from the Host system resident Boot ROM or from a Secondary
loader down-line loaded into the DEUNA WCS. Refer to Figure 4-35 and Table 4-42 for the Boot
message format and field descriptions.

DESTINATION ADDRESS/6 BYTES

SOURCE ADDRESS/6 BYTES

TYPE/2BYTES

CHARACTER COUNT/2 BYTES

CODE/1BYTE

VERIFICATION/8 BYTES

PROCESSOR/1 BYTE

CONTROL/1BYTE

SOFTWARE ID/1 BYTE

PAD DATA/32BYTES

CRC/4BYTES

TK-2051

Figure 4-35

Boot Message Format

4-88

Table 4-42

Boot Message Field Descriptions

Field

Length (Bytes)

Description

DESTINATION
ADDRESS

The physical address of the DEUNA.

SOURCE ADDRESS

The physical

address

of the requesting

station
TYPE

The Remote Console type
Value = (0260) 60-02 hex

CHARACTER COUNT

The number of bytes following the charac-

ter count field less pad data and CRC.
Value = (000C) 0C-00 hex

CODE

The function code for the Boot message.
Value = 06 hex.

VERIFICATION

The code to be compared against the portdriver supplied verification code.

The

codes must match before the DEUNA will

honor the boot. If the DEUNA has not been
supplied with a verification code by the
port-driver or supplied with a code of 0, the

DEUNA accepts any value in the boot message verification field.
PROCESSOR

Value = 00 hex; System boot, enter the
Primary Load state.
Value = 01 hex; Boot the DEUNA, enter

the Primary Load state.
CONTROL

Value =

00 hex; Boot from the system

default.

Value = 01 hex; Boot from the requesting
system.

SOFTWARE ID

Value = 00 hex; No ID.
Value = FF hex; Operating system.
Value = FE hex; Diagnostics.

PAD DATA

Pad characters, anything to pad the message out to 64 bytes.

CRC

Incoming block check character.

4-89

In response to a Boot message, the DEUNA performs the following.
1.

A message with remote console type value in its type field and the boot value in the code field is
received into a DEUNA buffer.

If the Remote Console Server is off, the message is discarded.
If the CRC is bad and the DEUNA is in the running state, the message is treated as a normal
datagram and boot processing stops. If the CRC is bad and the DEUNA is not in the running
state, the message is discarded and boot processing stops; otherwise, boot processing continues.
If the DEUNA is in the Primary Load State, executing Loop 1 of the Primary Loader, the message

is discarded. See Primary Loader Section 4.10.2.4 for details.

If the character count, processor, control, and software ID fields are within the expected limits,
boot processing continues. Otherwise, boot processing stops and the message is discarded.
If the Boot Select Switches are configured to allow remote boot, processing continues.
wise, the boot message is discarded.

Other-

The DEUNA compares the verification code in the boot message to the verification code
supplied by the port command. Refer to Section 4.4.11 for a description of the Write System
ID Port command. If they match, processing continues. If the DEUNA has not been supplied
with a verification code by a port command, or the DEUNA has been supplied with a
verification code of value 0, then any incoming verification code will suffice and processing
continues. Otherwise, the boot message is discarded.

The DEUNA decodes the Processor field of the Boot message to determine if the Comm or
System Processor is to be booted.
If the system processor is to be booted, the setting of the boot select switches determines the
action taken by the DEUNA.
a.

If the boot switches are configured to allow a boot from the system boot ROM, the

DEUNA does the following.
e

Asserts ACLO (causing a system power fail trap).

Blocks UNIBUS INIT to itself.

Discards any incoming boot messages for 40 seconds.

Makes a transition to the READY state.

4-90

If the boot switches are configured so that a boot from the system boot ROM is NOT

allowed, or the Comm Processor is to be booted, the DEUNA does the following.
The DEUNA enters the Primary Load State.

If the Comm Processor is to be booted and the DEUNA had not been in the Primary

Load State previously, the DEUNA sets the USCI bit of PCSRO.

If the system processor is to be booted, the DEUNA does the following.
-

Loads the following program into system memory:

2/
4/
6/
10/
12/
14/
16/
20/
2/
24/
26/
30/
32/
34/
-

777
PCSRO ADDRESS
0
12
0
16
0
22
0
30
340
012706
1000
762

Asserts ACLO to halt system processor via a powerfail trap. The DEUNA blocks

UNIBUS INIT to itself.
The DEUNA forms a program request message. Refer to Figure 4-36 and Table 4-43
for the format of the program request message and field descriptions.
The DEUNA copies the Software ID field of the boot message into the Software ID
field of the Program Request message.

If the value 1 is found in the Control field of the Boot message, the DEUNA transfers
the address in the Source Address field of the Boot message to the Destination Address
field of the Program Request message. If the value O is found in the Control field of
the Boot message, the DEUNA Load Server Address is written into the Destination
Address field of the Program Request message. The DEUNA Load Server Address is
supplied by a Port Command. Refer to Section 4.4.12. If the Port Command has not
been issued, the DEUNA uses the Load Assistant Multicast Address.
After the DEUNA completes the formation of the Program Request message, it
executes the Primary Loader. See Primary Loader subsection (4.10.2.4).

4-91

DESTINATION ADDRESS/6 BYTES

l07

SOURCE ADDRESS/6 BYTES

MOP VERSION — USER ECO/1 BYTE

TYPE/2 BYTES

FUNCTION —- TYPE/1 BYTE

CHARACTER COUNT/2 BYTES

FUNCTION — LENGTH/1BYTE

CODE/1BYTE

FUNCTION — VALUE 1/1 BYTE

DEVICE TYPE/1 BYTE

FUNCTION — VALUE 2/1 BYTE

FORMAT VERSION/1 BYTE

HARDWARE ADDRESS — TYPE/1 BYTE

PROGRAM TYPE/1 BYTE

HARDWARE ADDRESS — LENGTH/1 BYTE

SOFTWARE ID/1 BYTE

HARDWARE ADDRESS — VALUE/6 BYTES

PROCESSOR/1 BYTE

DEVICE — TYPE/1 BYTE

MOP VERSION — TYPE/1 BYTE

DEVICE — LENGTH/1 BYTE

MOP VERSION — LENGTH/1 BYTE

DEVICE — VALUE/1 BYTE

MOP VERSION — VERSION/1 BYTE

PAD/PARAMETERS/BYTES

MOP VERSION — ECO/1 BYTE

CRC/4BYTES

TK-8050

Figure 4-36

Program Request Message Format

4-92

Table 4-43
Field
DESTINATION

Program Request Message Field Descriptions
Length (Bytes)

Description

The address supplied by the Write Load
Server Port Function. The default address

is the Load Assistant Multicast address.
Load Assistant Multicast address value =
AB-00-00-01-00-00 hex.
(00AB)

(0001)
(0000)
SOURCE ADDRESS

The physical address of the DEUNA

TYPE

The Dump/Load type
Value = (0160) 60-01 hex

The number of bytes following the character count field less pad data and CRC.
Value = (001D) 1D-00 hex to (00AF)

CHARACTER COUNT

AF-00 hex

CODE

Value = 08 hex

DEVICE TYPE

The device type DEUNA

Value = 01 hex
FORMAT VERSION

Value = 01 hex

PROGRAM TYPE

Value = 00 hex
DEUNA microcode

Value = 00 hex; System boot, enter the

PROCESSOR

Primary Load state.
Value = 01 hex; Boot the DEUNA, enter

the Primary Load state.

MOP VERSION - TYPE

Value = (0001) 01-00 hex

MOP VERSION - LENGTH

Value = 03 hex

MOP VERSION - VERSION

Value = 03 hex

4-93

Table 4-43

Field

Program Request Message Field Descriptions (Cont)

Length (Bytes)

Description

MOP VERSION - ECO

Value = 00 hex

MOP VERSION - USER ECO

Value = 00 hex

FUNCTION - TYPE

Value = (0002) 02-00 hex

FUNCTION - LENGTH

Value = 02 hex

FUNCTION - VALUE 1

Value = 05 hex
Value = 15 hex. The maintenance functions supported; Loop, Primary Loader,

Boot.
FUNCTION - VALUE 2

Value = 00 hex

HARDWARE ADDRESS -

Value = (0007) 07-00 hex

Value = 06 hex

VALUE

The physical address of the DEUNA

DEVICE - TYPE

Value = (0064) 64-00 hex

DEVICE - LENGTH

Value = 01 hex

DEVICE - VALUE

TYPE
HARDWARE ADDRESS -

LENGTH
HARDWARE ADDRESS -

The DEUNA device code
Value = 01 hex

PAD/PARAMETERS

The set of additional parameters supplied
by port-driver through the Write System ID
port command. If not supplied, zeros are

added by the DEUNA to pad the message
out to 64 bytes.

CRC

DEUNA generated block check character.

4-94

4.10.2.2
1.

Local Boot — The following is the DEUNA operation in response to a Boot Port command.
The DEUNA receives the Boot Port Command. If the DEUNA is not already in the Primary

Load State, it enters it and sets the DNI bit of PCSRO.
The DEUNA forms a Program Request message.
¢

The DEUNA writes the Software ID value of the System ID parameter List into the

Software ID field of the Program Request message.
¢

The DEUNA Load Server Address is written into the Destination Address field of the

Program Request message. The DEUNA Load Server Address is supplied by a Port
Command.
If the Port Command has not been issued, the DEUNA uses the Load
Assistant Multicast Address.
After the DEUNA completes the formation of the Program Request message, it executes the
Primary Loader. See Section 4.10.2.4 for details.

Note that the DEUNA does not attempt to halt the system processor for a Boot on Port Command. It is
assumed the system processor will be in the appropriate action after issuing the Port Command.
4.10.2.3
1.

Boot on Power Up - The following is the DEUNA operation in response to a Power Up.
The DEUNA enters the Reset State upon Power Up, UNIBUS INIT, device Reset, or the SelfTest port command.
The DEUNA compares the footprint of the WCS to detect Power Up. If the footprint
compares, indicating not a true power on condition, the DEUNA continues in the Reset State
but does not execute the self-test. If footprint does not compare, indicating a true power on
condition, the DEUNA does the following:
e

The DEUNA writes the footprint.

The DEUNA Tests the Boot Select Switch settings. If Power-up Boot is not selected, the
DEUNA continues in the reset State and executes the self-test.

selected, the DEUNA does the following:
a.

The DEUNA enters the Primary Load State.

4-95

If Power-up Boot is

The DEUNA loads the following program in system memory:

2/
4/
6/
10/
12/
14/
16/
20/
22/
24/
26/
30/
32/
34/

777
PCSRO ADDRESS
0
12
0
16
0
22
0
30
340
012706
1000
762

¢.

The DEUNA asserts UNIBUS ACLO to halt the system processor through the
Powerfail trap. The DEUNA blocks UNIBUS INIT to itself.

The DEUNA forms a Program Request message.
Writes the value — 1 into the Software ID field of the Program Request message.

The Load Assistant Multicast Address is written into the Destination Address
field of the Program Request message.

After the DEUNA completes the formation of the Program Request message,
it executes the Primary Loader. Refer to Section 4.10.2.4.
4.10.2.4

Primary Load State — The Primary Load State of the DEUNA provides for communication

processor boot (down-line load of DEUNA Writable Control Store (WCS) based

boot.

microcode) and system

The DEUNA enters the Primary Load State under three possible conditions.

Reception of an error-free Boot message.

The Remote Console Server is not off and the

DEUNA Boot select switches are configured to honor the Boot message.

The Remote Console Server is not off and a Boot Port command is received from the Port
Driver.
The Remote Console Server is not off following a successful powerup and the DEUNA Boot
Select switches are configured to allow power-up boot.
Once the DEUNA has entered the Primary Load State, it performs the following.
1.

Transmits the Program Request message described under Sections 4.10.2.1 —4.10.2.3.

Waits for a Memory Load with Transfer Address message.

4-96

If, after five seconds, the DEUNA has not received a correct Memory Load with Transfer
Address message, it retransmits the Program Request message. This procedure is repeated for
eight transmissions of the Program Request message. During this time, any incoming Boot
message is discarded. This is Loop 1 of the Primary Loader. Loop 1 of the Primary Loader is
executed regardless of retry faults (collision on 16 attempts).

If after eight timeouts no correct Memory Load with Transfer Address message is received, the
DEUNA takes the following action.
e

If it entered the Primary Load State in response to a Boot message to boot the comm
processor, it exits the Primary Load State, enters the Ready State, and sets the USCI bit
of PCSRO.

If it entered the Primary Load State in response to a Boot message to boot the system
processor, in response to a Boot Port Command, or in response to a Power-Up Boot, the
DEUNA does the following.

Writes the Software ID field to value 0 and the Destination Address field with the

Waits for approximately 40 seconds to receive the Memory Load with Transfer

Load Assistant Multicast Address in the Program Request message and transmits it.

Address message.

If it does not receive it, the DEUNA retransmits the Program

Request message every 30 seconds until it does receive it. During this time, the
DEUNA honors any incoming Boot message. This wait and retransmit time is Loop
2 of the Primary Loader. Loop 2 of the Primary Loader is executed regardless of
retry faults.

The DEUNA receives the Memory Load with Transfer Address message. If the message is
error free, the message is accepted. Refer to Figure 4-37 and Table 4-42 for Memory Load with
Transfer Address Message Format and Field descriptions.

The DEUNA Loads the data image of the Memory Load with Transfer Address message into
its WCS starting at the load address supplied with the message.

If the Memory Load with Transfer Address message was received to boot the Comm Processor,
the DEUNA enters the Ready State and sets the USCI bit of PCSRO.

The DEUNA starts executing microinstructions at the transfer address supplied by the Memory
Load with Transfer Address message.

4-97

00
DESTINATION ADDRESS/6 BYTES

SOURCE ADDRESS/6 BYTES

TYPE/2BYTES

CHARACTER COUNT/2 BYTES

CODE/1 BYTE

LOAD NUMBER/1BYTE

LOAD ADDRESS/4 BYTES

IMAGE DATA/34 TO 1488 BYTES

TRANSFER ADDRESS/4 BYTES

CRC/4 BYTES

TK-9079

Figure 4-37

Memory Load with Transfer Address Message Format

4-98

Table 4-44

Field

Memory Load With Transfer Address Message
Field Descriptions

Length (Bytes)

Description

DESTINATION

ADDRESS

Physical address of the DEUNA.

SOURCE ADDRESS

Physical address of the Load Server

TYPE

The Dump/Load type
Value = (0160) 60-01 hex

CHARACTER COUNT

Number of bytes following the character
count field less pad data and CRC
Value = (002C) 2C-00 to (05SDA) DA-05
hex

CODE

Value = 00 hex

LOAD NUMBER

Value = 00 hex

LOAD ADDRESS

DEUNA microstore load address for storage of the data image

DATA IMAGE

TRANSFER ADDRESS

34 - 1488

Image to be stored in memory

DEUNA microstore starting address of the
data image

CRC

Received block check character

4-99

APPENDIX A

FLOATING DEVICE
ADDRESSES AND VECTORS

A.1

FLOATING DEVICE ADDRESSES

UNIBUS addresses from 760010 through 763776 are floating device addresses, (see Figure A-1). They are
used as register addresses for communication devices interfacing with a PDP-11 or VAX-11 system.
NOTE

Some devices are not supported by VAX-11/780.

777 777

DIGITAL EQUIPMENT

CORPORATION

WORDS

(FIXED ADDRESSES)

770 000

DR11-C

767 777

WORDS

1
USER ADDRESSES

764 000
763 777

WORDS

FLOATING ADDRESSES

760 010

DIGITAL EQUIP CORP (DIAGNOSTICS) | 760
760 006

000

757 777

001 000
000 777

)

VECTORS

FLOATING VECTORS
000 300

000 277

TRAP & INTERRUPT

VECTORS

VECTORS
000 000

MK-2190

Figure A-1

UNIBUS Address Map

A-1

To assign these addresses, a gap of 10g must be left between the last address of one device type and the first
address of the next device type. The first address of the next device type must start on a module 103
boundary. The 10g gap must also be left for uninstalled devices that are skipped in the priority ranking list
(see Table A-1). Multiple devices of the same type must be assigned contiguous addresses. Device types
already in the system may need to be reassigned to make room for additional ones.
Table A-1

Floating Device Address Ranking Sequence
Decimal

Rank

Option

Octal

Modulus

4
8
4
4
4
4

10
20
10
10
10
10

4
4
4
8
4

10
10
10
20
10

4
4

10
10

KMCl11
LPP11
VMV21
VMV31
DWR70
RLI1,RLVil
LPA11-K
KW11-C
Reserved
RX11/RX211

DR11-W

21
22
23
24

DMP11
DPV11
ISB11
DMV11

4
4
4
8

10
10
10
20

27
28
29

DMF32
DMSI11
VS100

16
6
8

40
20
20

1
2
3
4
5
6

7
8

DJ11
DH11
DQI 1
DU11,DUV11
DUPI11
LKI1I1A

DMC11/DMR
*DZ11/DZV11,
DZS11/DZ32

9
10
11
12
13

14
15
16
17

25
26

Size

RXV11/RXV21

DR11-B

DEUNA
UDASO

DZ11-E and DZ11-F are treated as two DZ11s.

4
4

4
8
4

4
2

10 (DMC before DMR)
10 (DZ11 before DZ32)

10 (after first)
20 (after first)
10 (after first)
(RX11 before RX211)

10 (after second)

10 (after first)
4 (after first)

A.2

FLOATING VECTOR ADDRESSES

UNIBUS addresses from 300 to 777 are floating vector addresses. They are used for communication de-

vices interfacing with a PDP-11 or VAX-11 system.

NOTE
Some devices are not supported by the VAX-11/780
system. Vector size is determined by the device type.

There are no gaps in floating vectors unless required by physical hardware restrictions. In data communications devices, the receive vector must be on a zero boundary; the transmit vector must be on a 4(8)

boundary.
Multiple devices of the same type should be assigned vectors sequentially. Table A-2 shows the floating
vector ranking assignment sequence.

Table A-2

Floating Vector Ranking Sequence

Decimal
Size

Octal
Modulus

Rank

Option

DC11

10*

TUS8

10*

2
2

KL11
DL11-A

4
4

10**
10**

DL11-B

10**

DLV11-J

10**

DLV11,DLVI1I1-F

10**

DP11

DMI11-A

DN11

DM11-BB/BA

DH11 modem control

DR11-A,DRVI11-B

9
10

DR11-C,DRV11

PA611 (reader+punch)

11
12

LPDI11
DTO07

4
4

10
10

DX11

DL11-C

DL11-D

DL11-E/DLV11-E

DJ11

DHI11

GT40

VSV1i

*
There is no standard configuration for systems with both a DC11 and TUSS8.
** A KLI1 or DLI11 used as the console uses a fixed vector.

A-3

Table A-2

Floating Vector Ranking Sequence (Cont)
Decimal

Octal

Rank

Option

Size

Modulus

LPS11

DQL11

KWI11-W, KWV11

DU11,DUV1I

DUPI11

DV11+modem control

LK11-A

DWUN

DMCl11

DMR11

10 (DMC before DMR)

DZ11/DZV11,

10 (DZ11 before DZ32)

DZS11/DZ32
28

KMCl11

LPP11

VMV21

VMV31

VTVO01

DWR70

RL11/RLVI11

4 (after the first)

TSI11

4 (after the first)

LPA11-K

IP11/IP300

4 (after the first)

KWI11-C

RX11/RX211

4 (after the first)

RXVI11/RXV21

(RX11 before RX211)

DR11-W

DR11-B

4 (after the first)

DMP11

DPV11

MLI11

4 (MASSBUS device)

ISB11

DMV11

DEUNA (REVQC)***

4 (after the first)

UDASO

4 (after the first)

DMF32

KMS11

PCL11-B

VS100

There is no standard configuration for systems with both a DCI11 and TUSS.

**
A KLI1 or DL11 used as the console uses a fixed vector.
*** DEUNA (REVB) Decimal=4 Octal=10.

A-4

A.3

DEVICE AND VECTOR ADDRESS ASSIGNMENT EXAMPLES

Example 1

The first device requiring address assignment is a DH11 (number 2 in the device address assignment
sequence and number 16 in the vector address assignment sequence).

The devices to be assigned addresses are:
2 DH11
2 DQl1s
1 DUP11

Option

1 DMR11
1 DEUNA

Device
Address

Vector
Address

760010

Comment
Gap left for DJ11 (number 1 on device address

assignment sequence) which is not used

DHI11

760020

300

First DH11

DHI11

760040

310

Second DH11

760060

Gap between last DHI11

‘

device

DQI11

760070

320

First DQ11

DQI11

760100

330

Second DQI11

760110

Gap between last DQI1

used and the next

device
760120

DUPI11

DMR11

760130

Gap left for DUl 1s is not used

340

760140

Gap left between DUP11 and next device

760150

Gap left for LK11-As is not used

760160

350

760170

DEUNA

Only one DUPI11

774510

Only one DMR11
Gap left after the last device with a floating
address assignment (in this case, the DMR11)
to indicate that none follows

120

First DEUNA uses fixed device and vector
addresses

Example 2

The devices to be assigned addresses are:
1 DJ11

2 DUPI11s
2 DMRI11s

1 DH11
2 DQl1s

2 DEUNAs

Option

Device
Address

Vector
Address

Comment

DJ11

760010

300

Only one DJ11

760020

Gap left between DJ11 and the next device

760030

Gap - The next device, a DH11, must start on

an address boundary that is a multiple of 20
DHI1

760040

310

Only one DH11

760060

Gap left between DH11 and the next device

DQt1

760070

320

First DQI1

DQ11

760100

330

Second DQI1

760110

Gap between last DQI11

used and the next

device
760120

Gap left for DUI 1s is not used

DUPI11

760130

340

First DUP11

DUPI1

760140

350

Second DUP11

760150

Gap left between last DUP11 and the next
device

760160

Gap left for LK11-As is not used

DMRI11

760170

360

First DMR11

DMRI11

760200

370

Second DMR11

760210

Gap left between last DMR11 and the next
device

DEUNA

774510

120

First DEUNA uses fixed device and vector
addresses

DEUNA

760450

400

Second DEUNA uses floating device and vector addresses

760460

Gap left after the last device with a floating

address assignment (in this case, the second
DEUNA, to indicate that none follows)

A-6

APPENDIX B

REMOTE BOOT AND DOWN-LINE LOAD

B.1 INTRODUCTION
The remote boot and down-line load features implemented in the DEUNA are used to allow the PDP-11
system in which the DEUNA is installed to be booted and to load a system image into the processor. This
function is useful with systems requiring remote booting and loading of their system images. Figure B-1
shows a basic PDP-11 system with a DEUNA.
For more information on remote boot and down-line load, refer to Section 4.10.2,

/')
DEUNA

PROCESSOR <

PDP-11

UNIBUS

ETHERNET

BOOT

MODULE

v
TK-10023

Figure B-1

B.2

PDP-11 System

SYSTEM CONFIGURATION GUIDELINES

When configuring a system to be remote booted and/or down-line loaded use the following guidelines:
1.

System Processor

When ACLO is asserted on the UNIBUS, the processor must be set up to assert DCLO

When DCLO is asserted, the processor is initialized and then HALTED. For a boot from
ROM function, the processor should start to execute from the boot ROM on the system

(power-fail sequence).

boot module.

B-1

System Boot Module (except for boot from boot ROM)

Disable power-up boot.

Disable system self-test.

NOTE
When configuring a system to meet these guidelines,
refer to the processor and boot module manuals for the
system.

Table B-1 summarizes the system configuration guidelines.

Table B-1
DEUNA Boot Function

Boot with ROM

Remote Boot

Remote and Down-Line Load Configuration Guidelines
Boot Module

Processor

Configure for

ACLO — DCLO

boot from ROM

Boot from ROM

Disable boot on

ACLO — DCLO

power up

Initialize and HALT

Disable system

self-test
Remote/Power-up Boot

Disable boot on

ACLO — DCLO

power up

Initialize and HALT

Disable system

self-test

B.3 REMOTE BOOT DISABLED
Remote boot is disabled when the BOOT SEL switches are configured as follows:

BOOT SEL 0 = ON
BOOT SEL I = ON
When remote boot is disabled, the system processor can only be booted by the DEUNA via a BOOT port
command. It cannot be booted via a boot request from another node on the ETHERNET.
B.4 REMOTE BOOT WITH SYSTEM LOAD
Remote boot with system load is enabled when the BOOT SEL switches are configured as follows:

BOOT SEL 0 = ON
BOOT SEL 1| = OFF
When remote boot with system load is selected, the DEUNA accepts a boot message received on the
ETHERNET, boots the system processor and down-line loads the system image.

B-2

When a boot message for system boot is received from another station on the ETHERNET (NI), the
DEUNA performs the following (see Figure B-2).
1.

Boot message is received by DEUNA.

The DEUNA checks the verification code, message type, etc.

The DEUNA transfers a program from ROM via DMA to system memory.

The DEUNA asserts ACLO. This simulates a power fail to the system.

The DEUNA sends a program request message onto the NI and waits for a memory load with
transfer address. The program request message is sent every five seconds for the first eight

messages, then every 30 seconds until the memory load with transfer address is performed.

The DEUNA checks the memory load message, transfers it to WCS, then executes the
instructions starting at the transfer address.

The program loaded into WCS is the secondary loader. This loader is used to bring a tertiary
loader into system memory. The tertiary loader is used to load the system image.
NI

DEUNA

2007

BOOT MESSAGE

CHECK VERIFICATION
CODE, MESSAGE
TYPE, ETC.
TRANSFER PROGRAM
VIA DMA

ASSERT ACLO
EVERY 5 SECONDS
FOR 8 MESSAGES
EVERY 30 SECONDS

PROGRAM REQUEST

HOST LOADER

AFTER 8TH MESSAGE eNORY \_op;DE . T

*CHECK MESSAGE 4 qiTH TRAN

*TRANSFER TO WCS
*EXECUTE

DEUNA BOOT SWITCH SETTINGS:
BOOTSEL 0=0ON
BOOT SEL 1=0OFF

Figure B-2

TK-10020

Remote Boot with System Load
Functional Flow

B.5 REMOTE BOOT WITH ROM
When remote boot with ROM is selected, the DEUNA accepts a boot
message received on the
ETHERNET, then boots the system via ROM-based instructions contained
on the system boot module.
Remote Boot with ROM is selected when the boot select switches are configure

d as follows:

BOOT SEL 0 = OFF
BOOT SEL | = ON
When a boot message for system boot is received from another station on
the NI, the following sequence
occurs (Figure B-3):
1.

The DEUNA checks the verification code, message type, etc..

The DEUNA asserts ACLO:; thi§ simulates a powerfailure to the system.
The system then performs a power-up boot using the ROM-based boot program.

The boot program, in addition to booting the system, should:
®

Self-test the system

Issue a BOOT port command to the DEUNA

The DEUNA will then enter the primary load state.
PDP-11

DEUNA

NI
‘%Oy

BOOT MESSAGE

CHECK VERIFICATION
CODE, MESSAGE TYPE,

ETC.
ASSERT ACLO

REMOTE BOOT
LOCAL POWER-UP

BOOT

\ SYSTEM BOOT MODULE
*SHOULD EXECUTE

SELF-TEST
*ISSUE BOOT
PORT COMMAND
PR

EVERY 5 SECONDS

MT.

FOR 8 MESSAGES

EVERY 30 SECONDS

HOST LOADER

AFTER 8TH MESSAGE

*CHECK MESSAGE

N\EN‘OR\(

*TRANSFER TO WCS

\_OP\D

ren A0

RES

\1\,\1?\“‘“

*EXECUTE(START
AT TRANSFER ADDRESS)
DEUNA BOOT SWITCH SETTINGS

BOOT SEL 0= OFF
BOOT SEL

1=0N

Figure B-3

TK-10021

Remote Boot with ROM Functional Flow
B-4

B.6 REMOTE BOOT/POWER-UP BOOT WITH SYSTEM LOAD
When the DEUNA is configured for Remote Boot/Power-Up Boot with System Load, the DEUNA can
boot and perform a system load over the ETHERNET in 2 ways:
1.

On system power-up

On receipt of boot message over the ETHERNET

The boot select switches on the port module of the DEUNA are configured as follows:
BOOT SEL 0 = OFF
BOOT SEL 1 = OFF

When the system is powered up, the DEUNA performs the followingr (Figure B-4):
1.

Transfers a program from ROM via DMA to system memory.

Assert ACLO; this simulates a powerfailure to the system.

with the transfer
3. Sends a program request message onto the NI and wait for a memory loaé
first eight messages,
address. The program request message is sent every five seconds for the
then every 30 seconds until the memory load with transfer address is performed.

Checks the memory load message, transfers it to WCS, then executes the instructions starting
at the transfer address.

The program loaded into WCS is the secondary loader. This loader is used to bring a tertiary
loader into system memory. The tertiary loader is used to load the system image.

When the DEUNA receives a boot message from another station on the ETHERNET, it functions in the
same manner as 2 Remote Boot with System Load. Refer to Section B.3 of this appendix for a description
of this function.

DEUNA
TRANSFER PROGRAM
VIA DMA

EVERY 5 SECONDS

PROGRAM REQUEST

FOR 8 MESSAGES

EVERY 30 SECONDS
AFTER 8TH MESSAGE

*CHECK MESSAGE

ASSERT ACLO

HOST LOADER

WEMORY Lol::R ADD\'-\ESS
S

WTH TRAN

*TRANSFER TO WCS
*EXECUTE (START
AT TRANSFER ADDRESS}

DEUNA BOOT SWITCH SETTINGS:
BOOT SEL 0= OFF
BOOT SEL 1=0FF

TK-10022

Figure B—4 Power-Up Boot with System Load
Functional Flow
B-5

APPENDIX C

NETWORK INTERCONNECT EXERCISER

C.1

INTRODUCTION

The Network Interconnect Exerciser (NIE) provides a VAX-11 Level 2R and a PDP-11 standalone diagnostic exerciser for ETHERNET networks. The NIE determines node ability on the network and provides
the operator with error analysis. Node installation, verification, and problem isolation can be performed
using the NIE.
The NIE is divided into two parts:

Default Section (also called operator intervention section) — This section allows the operator to
use the NIE in different modes (for example, size-NI, use loop assist, or full assistance testing of
all nodes). This section is operator driven, with the operator selecting the tests and the testing
parameters.

Unattended Mode - This mode collects a table of node addresses, then tests the nodes selected
using the low level maintenance functions of the DEUNA.

The memory size of the node running the NIE determines how many nodes can be selected for testing at
one time. Only current summary information is maintained to retain the maximum number of physical
addresses.

The total execution time depends on many factors, such as number of nodes on the NI, the response time of
a remote node to a loopback request, message sizes, and other operator-dependent factors.

The VAX-11 version of the exerciser (EVDWC REV *.*) runs on all VAX-11 processors. It is a level 2R
diagnostic and uses the VMS DEUNA Driver and the VAX-11 Diagnostic Supervisor (VDS).
The PDP-11 version of the NIE (CZNID*) uses the Diagnostic Runtime Services (DRS) and runs on any
PDP-11 UNIBUS type processor.

The NIE runs concurrently with DECnet software. The NIE uses two NI protocol types: loopback and
remote console. The operator may be required to run NCP to modify certain DECnet parameters before all
parts of the NIE can be run successfully. Certain other restrictions (for example, buffer size) also apply
when running DECnet.

Running the NIE increases the traffic on the NI. If more than one copy is running simultaneously, normal
operation on the NI could be severely affected.

C-1

C.2 RUN-TIME ENVIRONMENT REQUIREMENTS
The VAX-11 Level 2R NIE (EVDWC REV *.*) runs in the standard environment supported by the

VAX-11 Diagnostic Supervisor.

Hardware Required

VAX-11 processor
256Kb memory

UNIBUS adapter
DEUNA connected to an NI

Software Required

VMS Operating System (Version 3.0)
DEUNA Driver
VAX-11 Diagnostic Supervisor (REV 6.5 or later)

The PDP-11 standalone NIE (CZNID*) runs in the standard environments supported by the PDP-11
Diagnostic Run-Time Services (DRS).
¢

Hardware Required
UNIBUS PDP-11

system

32Kb memory
DEUNA connected to an NI
e

Software Required

Diagnostic Runtime Services (DRS)

C.3

FUNCTIONAL DESCRIPTION

C.3.1

Unattended Mode
The Unattended Mode allows testing of the NI without operator interaction. Default parameters are used
for the tests; the tests share a table of physical addresses of the nodes to be tested.

C.3.1.1

Build - The Build subroutine collects the physical addresses of all DEUNA on the NI.

C.3.1.2

Direct Loop Message Test — The ability of a node to respond to a loopback request is checked. A

single loop request is sent to each of the nodes identified by the operator for testing. This message uses the

minimum size buffer (36 bytes) and waits for a maximum of eight seconds for a reply. Three attempts are

made to contact each node.

The structure of the Loop Message and an example of Direct Loopback testing is shown in Figure C-1. For
direct looping, a Reply Message is encapsulated in a Forward Message. The Forward Message is sent by the
NIE to the target node. The target node receives the Forward Message, extracts the Reply Message, and

sends the Reply Message back to the NIE.

> O

FORWARD

NI/ETHERNET

@ —
NI

EXERCISER

TARGET
NODE

NODE

NOTE: NUMBERS INDICATE SEQUENCE IN WHICH MESSAGES ARE SENT
TK-9722

Figure C-1

Direct Loop Message Test Example

C.3.1.3 Pattern Test - This test sends six different loop direct messages to each node contained in the
node table. Each of the six pattern types is used. During this test, each node will loopback one of the
message types in the defualt section. The operator-directed section allows selection of the pattern to be
used. Refer to Table C-1 for the Message Pattern Test types.

Table C-1

Message Pattern Test Message Types

Message Type

Message Pattern

Alphanumeric

148%& ()*+,-./0123456789:;,(=)"\abc etc.

Ones

e, )
Message of all 1s (TITTTLITITTTT1T coiiiiiiiiiiii

Zeros

Message of all 0s (000000000000000 ..........cooermmrmerurereeermmnrceceennnnnes )

1Alt

Message of alternating 1s and 0s (10101010101010 .........occiieiiiinnniee )

0Alt

Message of alternating Os and 1s (01010101010101 .........ccoiriiiiiiiienns )

CCITT

“CCITT” psuedo-random test pattern

Operator selected*
*

Operator-chosen data pattern of less than 72 characters using A-Z, 0-9,

and spaces (not used in pattern test).

The operator-selected pattern is only available in the operator-directed section.

C.3.1.4

Multiple Message Activity Test - This test uses the direct loop maintenance feature
to create a
large volume of NI traffic. Loopback requests are sent to a subset of the total available
nodes (forexample,
10). Responses are received from all nodes, but to save overhead, the data field
for only one of the nodes is
checked for correctness. Upon successful reception, another node is selected
(from the group of ten) and
testing continues until all nodes from that group have been tested. Then testing
continues with another

group.

NOTE
This test causes multiple collisions on the NI and
could affect the overall performance of the NI while
running,

C.3.2 Operator-Directed Section
Selecting tests and test parameters is controlled by a command line interpreter (CLI). Section

describes the commands an operator can issue when the operator-directed section is started.

C.3.2.1

Operator Conversation — This test uses nodes identified for testing by the operator as target
and
loop assist nodes (node-pair) and performs testing according to operator input or according
to default

parameters.

Using the proper commands, the operator can streamline the exerciser to test a particular

node-pair. The
test could be simple, using the default parameters of message numbers, message length, and data patterns,

or more complex, using several messages, various message lengths, and different data patterns.

Only enough letters to make the command unique need be typed by the operator. Table C-2 summarizes
the available commands.

Table C-2

Command
Helpor?

Operator Command Summary

Description
Displays a brief summary of NIE commands. There are
no arguments.

Format: NIE)Help or NIE)?

On VAX-11 systems, more extensive help information is
available through the Help facility of the Diagnsotic

Supervisor.
On

PDP-11

systems, include more information
(NIE)Help) to the operator-directed interface.
EXIT

Returns the operator to the Diagnostic Supervisor (either

DR) or DS)). No switches or qualifiers.
Format: NIE)Exit

C-4

Table C-2

Command

SHOW

Operator Command Summary (Cont)

Description
Prints physical addresses of nodes selected for testing and

message parameters (either default or operator input).

Format: NIE)Show (argument)

Show Nodes

Lists all nodes in the Node table, including a physical
address and a logical name assigned to the node by the
NIE. Can be referenced by either physical address or the
logical name. Logical names are assigned as N1, N2, N3,
etc. The table also identifies the node as target or assist

node as assigned by the operator. Unassigned nodes
default to target.
Show Message

Lists the message type, message size, and message numbers currently selected.

Show Counters
RUN

Lists the counters of the host node.
Executes the test specified by the argument.

Format: NIE)Run (argument)/Pass=nm
Run Direct/pass=nm

Selects the test described in Section C.3.1.2.

Run Looppair/pass=nm

Selects the test described in Section C.3.2.4.

Run Pattern/pass=nm

Selects the test described in Section C.3.1.3.

Run All/pass=nm

Selects the test described in Section C.3.2.5. Allows the

operator to select the number of passes for the selected
test. If -1 is specified, the test runs continuously.
Default=1.
MESSAGE

Allows the operator to change the default parameters of
message type, message size, and message number.

Format: NIE)Message=type/size=n/copies=n

Table C-2

Command

Operator Command Summary (Cont)

Description

Message/type/size=n/copies=m
Message types are explained in Table C-1.

Message size is variable between 32 and 1466 bytes.
Message copies = number of times the message is to be
transmitted (1 to 10).

NODE

Allows the operator to enter nodes for testing.

Format: NEI)Nodes addr/type

Node adr/Target

Adr argument is the the physical address of the node on

the NL
Node adr/Assist

The type argument can be either target or assist. This
information in used for the Looppair test and is ignored

for the All node test. If this argument is not specified, the
default of target is used.

SUMMARY

Prints the summary message of conditions and errors as a
result of testing (see Section C.3.2.6).
The same summary information can be obtained by typing Summary (VAX-11 system) or Print (PDP-11 system). There are no switches or qualifiers for the Summary

command.

Format: NIE)Summary
BUILD

Builds a table of nodes described in Section C.3.2.2. No
switches or qualifiers. To list the node table built from this
section, use SUMMARY or SHOW NODES.

Format: NIE)Build
CLEAR

Format: NIE)Clear (argument)

Clear Node/adr

Removes a node from the node table.

Clear Node/all

Clears the node table.

Clear Message

Resets the message parameters to the default state.

Clear Summary

Clears the node summary table.

C-6

Table C-2

Operator Command Summary (Cont)

Command
IDENTIFY adr*

Description
Performs a request ID to the address included in the com-

mand line (see Section C.3.2.3). The argument adr should

be a physical address.
Format: NIE)dentify adr
SAVE

Saves the contents of the node table. For VAX-11 version
of the NIE, the table is saved in file NIE.TBL. The
PDP-11 NIE copies the node table into a secondary buffer
within the diagnostic. The primary node table can then be

modified without destroying the secondary node table.
Use UNSAVE to restore the primary table.
Format: NIE)Save
UNSAVE

Restores the contents of the node table. The VAX-11 version reads the most recent version of the file NIE.TBL.

The PDP-11 version reads the node table from the secondary buffer into the primary buffer.

Format: NIE)Unsave
* adr is the physical address of a node on the NI

C.3.2.2

Collect IDs (Build) - DEUNA nodes transmit a system ID message every eight to ten minutes.

It is possible to identify all nodes on the NI and build a table of nodes by listening for the ID messages.

An estimated 40 minutes is required to collect a complete list of nodes on the NI. This test listens for IDs
and builds a configuration table until a new node has not been added for 10 minutes or until the build is
stopped by the operator. The maximum number of nodes in the node table is 100.

~ C.3.2.3

Request ID - In response to the operator-directed command IDENTIFY, a request ID is

generated to the physical address identified as part of the command line.

contact the node, and failure is reported to the operator.
message is reported to the operator.

Three attempts are made to
The information contained in the returned ID

C.3.2.4 Pair-Node Testing — Using the operator-directed interface, the operator enters a pair of nodes
for testing. One node is the target node and the other node is the loop assist node. This test uses the loop
assist function of the DEUNA. This test can be run without running other parts of the NIE. Therefore, it
is necessary to run the full range of loop testing to determine the node with problems. Each node is fully
tested using transmit assist, receive assist, and full assist loopback testing. For examples of these tests and
message formats, see Figures C-2, C-3, and C-4.

NI/ETHERNET

REPLY l FORWARDI FORWARDI

REPLY lFORWARDI

- ©
NI

EXERCISER
NODE

NODE A

NODE B

LOOP ASSIST

TARGET

NOTE: NUMBERS INDICATE SEQUENCE IN WHICH MESSAGES ARE SENT
TKA723

Figure C-2

Transmit Assist Loopback Testing Example

> ©

FORWARD

NI/ETHERNET

FORWARD l

EXERCISER
NODE

REPLY J

NODE A

NODE B

LOOP ASSIST

TARGET

NOTE: NUMBERS INDICATE SEQUENCE IN WHICH MESSAGES ARE SENT
TRO?24

Figure C-3

Receive Assist Loopback Testing Example

FORWARD | FORWARD

FORWARDI

- O

FORWARD | FORWARD

rFORWARDl

O —

NI
EXERCISER
NODE

NODE A

NODE B

LOOP ASSIST

TARGET

NOTE: NUMBERS INDICATE SEQUENCE iN WHICH MESSAGES ARE SENT
TK-9728

Figure C-4

C.3.2.5

Full Assist Loopback Testing Example

NI All Noede Communications Test (End-to-End) — The All node test begins by doing a direct

loop to all nodes in the table. If there is a single failure of this portion of the direct test, the All node test is
aborted. The operator can then remove the offending node from the table, and restart the test.
Testing all nodes contained in the configuration table is performed using default parameters or operator
input parameters. This test provides the most comprehensive testing of the NI. Testing is performed two
nodes at a time by attempting two-way communication with a pair.
It is not possible to identify end nodes of an NI segment. Therefore, a test matrix is developed to assure that
both end nodes have communicated. Testing each pair of nodes in a predetermined sequence assures that
nodes physically positioned at opposite ends of a segment have been tested. This test occupies the longest

test time of the NIE.
The formula for determining the number of subtests required is (n(n-1))/2. Figure C-5 is an example of a
network with eight nodes. The number of subtests is 7(7-1)/2 = 21 (n=7 because it is not necessary to
include the node running the exerciser.) To be certain of covering the entire NI, subtests need to be per-

formed (see Table C-3).

NIE

NI/ETHERNET

[

TK-8727

Figure C-5

Example Test Configuration for All Node
Communications Test

Table C-3

All Node Communications Testing Matrix

1-2

2-3

3-4

4-5*

5-6

1-3

2-4

3-5

4-6

5-7

1-4

2-5

3-6

4-7

1-5

2-6

3-7

1-6

2-7

6-7

1-7
*Complete end-to-end testing occurred at this point; however, there is no way for the NIE to know this happened.

C.3.2.6 Summary Log - A log of events is maintained during testing for both the default and operatordirected sections. The Summary command is used to print the summary under the operator-directed
section. The Summary Log is cleared when a Start or Restart is executed. The information maintained in

the summary section is described in Table C-4.

Table C-4

Summary Information

Name

Description

Node Physical Address

The physical address of the node on the NI.

Receives Not Complete

The number of packets transmitted without a corresponding reply.

Receives Complete

The number of packets transmitted and received successfully.

(Note that messages sent do not always equal messages received if
there are problems with the node or if traffic is high enough to
cause dropped packets.)
Data Length Error

Number of packets with the bytes expected not equaling the number of bytes received.

Data Comparison Errors

Number of bytes received in error.

Bytes Compares

The number of bytes of data compared.

Bytes Transferred

The number of bytes transmitted to a node (data and header).

C-10

APPENDIX D

VECTOR ADDRESS (REVB)
D.1

VECTOR ADDRESS ASSIGNMENT

Assign the DEUNA a vector address from the reserved vector area of memory address space. The first

DEUNA being installed in a system must be assigned the vector 120. For the second, and any subsequent

DEUNA being installed in the same system, the vector address must be selected from the floating vector area
of reserved vector address space. The vector address is assigned by configuring switch pack E62 on the
M7792 port module to the desired vector.

D.1.1

First DEUNA Vector Address (120) — Assign vector address 120 to the first DEUNA in the system

by configuring S1-S6 of switch pack E62, on the M7792 port module, as shown below. Note that this vector
is also used by the XY 11. Refer to Figure D-1 for the location of E62 on the M7792 module.

M7792 - E62

D.1.2

'S5

OFF

Second DEUNA Vector Address (Floating Vector) — Assign a vector to the second (or subsequent)

DEUNA by configuring S1-S6 of switchpack E62, on the M7792 port module, to the desired vector deter-

mined from the floating vector allocation. Refer to Table D-1 for the correlation between switch number and
address bit. The ranking vector address assignment of the DEUNA is forty-seven (47). Refer to Appendix A
for more information on floating vector allocation.

Table D-1

Floating Vector Assignment

MSB

LSB

wlwalwaelnlolele|s|sls]|al3]2]1]o0
ololofololo]o

vol

SWITCH PACK E62

‘

|
|

SWITCH

NUMBER | SB[S5

]S4

|
|
|

|S31S2

OFF|OFF

|
|
|

:
]

151}

OFF|OFF

OFF

orr|orrlorr

OFF

OFF|OFF
OFF
OFF|OFF
OFF|OFF
OFF|oFFJoFF

FLOATING

\ecror
300

310

220
330
340
350

orF|orrlorE|oFF

360

off|orelorF|orF|oFF

370
400

OFF

500

OFF|OFF

600

oFF|oFF|OFF

700

NOTE: SWITCH OFF (OPEN) PRODUCES LOGICAL ONE ON THE UNIBUS.
TK-9761

D-1

SELFTEST

CABLE

MODULE

STATUS
LEDs

VERIFY
LED

INTERCONNECT
CABLE JACKS

ooooooa’fi

Ly
J2

SWITCH PACK E40
SWITCH OFF (OPEN) = LOGICAL 1

SWITCH PACK E62
SWITCH OFF (OPEN) = LOGICAL 1

A12

L —— va

012345678910

o)
F

0
£

LSPAF(E
VECTOR ADDRESS
SELECTION

SELFTEST LOOP
BOOT OPTION SEL 0

DEVICE ADDRESS
E
N
SELECTIO

)

BOOT OPTION SEL 1

TK-9758

Figure D-1

M7792 Port Module Physical Layout

NOTE
An OFF (open) switch produces a logical one (1) on
the UNIBUS circuit,

D.2

BOOT OPTION SELECTION (PDP-11 HOST SYSTEMS ONLY)

The DEUNA provides for remote booting and down-line loading of PDP-11 family host systems. These func-

tions are switch selectable via two boot option select switches located on switch pack E62 on the M7792 port
module.
NOTE

Refer to Appendix B for additional information on
DEUNA remote booting and down-line loading.
When installing a DEUNA in a PDP-11 family host system, configure switches S7 and S8 on switch pack
E62 (M7792 module) for the boot function desired. Table D-2 lists the switch settings and corresponding
boot option functions. Refer to Figure D-1 for the location of E62 on the M7792 module.
When installing a DEUNA in a VAX-11 family host system, set both S7 and S8 on E62 (M7792 module) to
the ON (disabled) postion.
NOTE
An OFF (open) switch produces a logical one (1).

This is the ENABLED state of the switch function.

Table D-2

Boot Option Selection (M7792 E62 - S7 & S8)

BOOT SEL 1

BOOT SEL 0

Function

ON*

Remote boot disabled

OFF

Remote boot with system load

OFF

Remote boot with ROM

OFF

Remote boot with power-up boot and system load

* Switch settings for a DEUNA installed in a VAX-11 system.

D-3

D.3

SELF-TEST LOOP (FOR MANUFACTURING USE)

The self-test loop is provided on the DEUNA for use during manufacture testing. This is a switch selectable

feature that allows the on-board self-test diagnostic program, once it is initiated, to continuously loop itself.

This feature is controlled by S9 on switch pack E62 on the M7792 port module and should be disabled during

installation.

When installing a DEUNA, disable the self-test loop feature by setting S9 on switch pack E62 (M7792 mod-

ule) to the ON (closed) position, as indicated in Table D-3. Refer to Figure D-1 for the location of E62 on the
M7792 module.

Table D-3
Position

ON* (closed)

Self-Test Loop Switch (M7792 E62 - S9)
Function

OFF (open)

* Switch setting for field operation.

DISABLED
ENABLED

APPENDIX E

DEUNA MICROCODE ECO PROCESS

E.1 INTRODUCTION
The microcode ECO process allows for the microcode of the DEUNA to be updated as network improvements are made. The support for microcode ECO’s is as follows:

Microcode ECO’s will be included in system distribution kits and autopatch kits.

Asystem utility will be provided that automatically reloads the patches on: reboot, recovery from power

failures, and software execution of the self-test microcode.
The following sections explain the format of the ECO patch file and the programming steps required to load
the patch into the DEUNA and execute it.

E.2 PATCH FILE FORMAT
The patch file consists of the standard RSX label blocks which are followed by data blocks. The format of the

patch file is as follows:
Two label blocks called LABEL BLOCK 0 AND LABEL BLOCK 1 (Figure E-1).

LABEL BLOCK 0

LABEL BLOCK 1
DATA BLOCK 0

)

)Ip)

DATA BLOCK 1

CcC

DATA BLOCK n

NOTE: BLOCK = DISK BLOCK
TK-10110

Figure E-1

Patch File Format

E-1

The two label blocks are followed by the data blocks. Each data block may contain a number of microcode patches (Figure E-2). The last ‘‘patch’’ of the last data block in the file will contain a Byte Count

of —1 and the DEUNA Start Address.

BYTE COUNT OF TRANSFER

DEUNA INTERNAL
LOAD ADDRESS

DATA

:L, ! BLOCK 0

\
<

BYTE COUNT OF TRANSFER

DEUNA INTERNAL
LOAD ADDRESS
~

DATA

'
ADDITIONAL

DATA BLOCKS

BYTE COUNT OF TRANSFER

)

DEUNA INTERNAL
LOAD ADDRESS

~N
fiu

1
BLOCK

DATA

.
.

DATA

~
hu

( BLOCK n

BYTE COUNT = —1
DEUNA START ADDRESS

~N
Y

.
.

Y
av

0
TK-10111

Figure E-2

Data Block Format

NOTE
No patch can extend over a single block of the file
Data Block. This means that large changes in the

microcode will have to be divided into a series of
smaller changes, so that they each fit into a single

Data Block.
There can be unused space at the end of each Data
Block. This space will be filled with 0’s.

E.3 PATCH PROCEDURE
The procedure for loading and executing a patch to the DEUNA microcode is as follows:

The DEUNA must be in the READY state.

Use the LOAD Ancillary Command (21) to load each patch into the DEUNA. The byte count and Internal load address supplied in each patch are used to set up the LOAD command.

Repeat the previous step until all the patches, contained in the file, are loaded into the DEUNA.

Using the DEUNA Starting Address supplied in the last patch, issue the LOAD and START MICROADDRESS Ancillary Command (1) to execute the patch.

E-3

DEUNA USER’S GUIDE

Reader's Comments

Your comments and suggestions will help us in our continuous effort to improve the quality and

usefulness of our publications.
What is your general reaction to this manual? In your judgment is it complete, accurate, well organized, well
written, etc? Is it easy to use?

What features are most useful?

What faults or errors have you found in the manual?

Does this manual satisfy the need you think it was intended to satisfy?
Does it satisfy your needs?

Why?

Please send me the current copy of the Documentation Products Directory, which contains information
on the remainder of DIGITAL's technical documentation.

Name

‘

Street

Title

City

Company

State/Country

Department

Zip

Additional copies of this document are available from:

Digital Equipment Corporation
Accessories and Supplies Group

P.O. Box CS2008

Nashua, New Hampshire 03061
Attention: Documentation Products
Telephone: 1-800-258-1710

Order No__EK—DEUNA—UG—001