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XX-08757-85

December 1976

122 pages

Original

2.6MB

Document:	PDP-11 Mainframe Troubleshooting Guide
Order Number:	XX-08757-85
Revision:	0
Pages:	122
Original Filename:	http://bitsavers.org/pdf/dec/pdp11/PDP-11_Mainframe_Troubleshooting_Guide_Dec76.pdf

OCR Text

PDP-11 Mainframe
Troubleshooting Guide
(Flows and DECAl OS)

COMPANY CON FIDENTIAL

1st Printing. December 1976

The reproduction of this troubleshooting
guide. in part or whole. is strictly prohibited.
For copy information. contact the Educational Services Department, Digital Equipment
Corporation. Maynard. Massachusetts
01754.

CONTENTS
OECAIO

Contents
Introduction
Troubleshooting Flow Diagrams

AC/OC .LO

Location of AC LO and DC LO signals on CPU
backplanes

BUS

Quiescent Unibus levels
Location of signals on Unibus slot backplane pins

CONSA

Quiescent console light displays

CONSB

PDP-ll/05 console checkout procedure

HELP

What to do if all else fails

INT OPT

List of internal options including modules. location. required jumper and wire changes

LOADER

For paper tape systems: procedures for loading
and running the bootstrap and absolute loader
and for loading the MAINDECs
For disk. DECtape. or magtape systems: procedures for using the hardware and software
bootstrap loaders

MAINDA

List of available CPU. memory. and internal
option MAINDECs

MAINDB

Acceptable times for running MAINDECs

MEMA

Module utilization and jumper configuration and
location for MMll-S. MFll-L(PI. and MFllU(P) memories. and SSYN delay adjustment procedure for parity memory

MEMB

Strobe adjustment procedure for memories using
the Gll0

CONTENTS (Cont)
DECAID

Contents

PROCA05

GPR program. module utilization. SCl clock
adjustment. proc. clock adjustment

PROCA40

Proc. clock adjustment. jumper location and configuration. module utilization

PROCA45

Module utilization. jumper location. and
configuration

PROCB

CPU modules that drive and receive Unibus
signals

PWRB-1

PDP-11/40/45 CPU dc voltage checks

PWRB-2

POP-11/40/45 regulator slot assignments

PWRB-3

POP-11/40/45 crowbar problems

PWRB-4

POP-11/40/45 distribution panel
connectors

PWRB-5

PO P-11 140/45 power harnesses and cables

PWRB-6

POP-11/40/45 reguators' connectors

PWRB-7

POP-11/40/45 procedure for removal of regulators. fuse location

PWRB-8

POP-11/40/45 bulk supply connectors

PWRB-9

PO P- 11 140/45 fuse location on and removal
procedure for bulk supply's power control board

PWRO

POP-11/05/10 power connectors

REMOTE

Remote power control facility

START

Suggestions on what to do before actual hardware troubleshooting

THE PDP-11 MAINFRAME
TROUBLESHOOTING GUIDE

INTRODUCTION
This guide is comprised of two major sections:
1. The Troubleshooting Flowchart
2. The DECAIDs.
It is intended that they be used concurrently by Field Service personnel to aid them in locating and repairing faults in PDP-ll systems that utilize PDP-ll/05/l 0/35/40/45 CPUs.
The guide makes two basic assumptions.
1. The Field Service technician has an excellent supply of
replacement parts (e.g .. modules. power regulators. cables.
etc.).
2. There is a configured copy of DEC/Xll with the system
which has been loaded and run error-free at some time prior
to this failure. That is. the system has already been installed
and was fully operational at one time. The guide does not
provide the necessary information on how to install either
systems or add-ons to a system.

THE TROUBLESHOOTING FLOWCHART
The flows guide the Field Service technician through the steps he
must perform to isolate a fault to either a peripheral device or the
mainframe and if it is found to be in the mainframe. then to either
the Unibus. power system. internal option. memory. or processor.
Once the fault has been isolated. the flows then indicate the steps to
follow to repair the fault on a field-replaceable-unit basis.

The symbology used in the flowchart is as follows:

o
o

(---------)

Circle
An entry from or exit to other pages of the
flows with the pages listed in parentheses
near the circle.

Diamond
A decision point.

Rectangle
A procedure or operation to be performed by
the technician.

Bubble
A reference to one of the DECAl Os that provides the technician with the information
necessary to perform the operation or make
the decision.

The 13 pages of flows are organized as follows:

1.-2. Starting and quick-check: loading and running system
exercisers

3.-4. AC power

5.-6. DC power
7. Mainframes
8. Unibus

9.-10. Consoles
11. Processors

12. Memories
13. Peripherals.

The flowchart is intended to fulfill two primary functions.
1. To aid the technician in determining a logical troubleshooting approach to a system failure.
2. To help the technician develop an effective troubleshooting
technique.

THE DECAIDS
The second section of the quide provides the troubleshooter with all
the information necessary to perform the operations. do the adjustments, and make the decisions to isolate and repair a problem in a
PDP-11 system. These DECAIDs cover all the detailed aspects of
troubleshooting from how to load a diagnostic to the procedure for
adjusting core memory strobes to locating the output pins on a
power regulator's connector.
It is intended that these DECAl Os will be used by the technician on
the job, providing information that is:
1. Much toO detailed to memorize
2. Hidden away in one of more than a dozen manuals and engineering drawings
3. Not available anywhere else.

TROUBLESHOOTING FLOWCHART

NOTES:
IF SOME OF THE FANS ARE TURNING aUT
NOT 01M£R8 IN OTHER BOXES OR CABlN£TI.

CHECK THE REMOTE POWER CONTROL

FACILITY. SEE DECAID REMOTE.
REMEMBER TO CHECK THAT THE POWlR
ON/OFF SWITCH IS NOT ON PANEL LOCK. TRY
A FEW BASIC fUMCTIONS SUCH A8 LOAD
ADDRESS, EXAMINE AND DEPOSIT INTO ALL

BANKS OF MEMORY AND EXAMINE AND
DEPOSIT INTO PERIPHERAL AND REGISTER
ADDRESSES.

TROUBLESHOOTING FLOWCHART

1 WHEN RUNNING A MAINDEC IT IS
SOMETIMES DIFFICUlTTO OETECTWHETHER
IT IS RUNNING PROPERLY OR WHETHER IT tS

HUNG IN A LOOP. READ THE MAINDEC'S
WRITE.UP TO SEE IF YOU CAN USE SUCH
TECHNIOUESAS SETTING UP THE SWITCH
REGISTER TO CAUSE A FRIEQUENT PRINTOUT.

EXERCISING THE CONSOlE TERMINAL'S
"'UHTEA, RUNNING IN SINGLE ITERATION
MODE. ETC.

TROUBLESHOOTING FLOWCHART

~==::::--,

TROUBLESHOOTING FLOWCHART

REPAIR OR
AEPLACE
CABLE
BETWEEN
DISTRIBUTION
PANEl
AND
BACKPLANE

.-..""....""'0"'"
REPLACE
HARNESS
BETWEEN
REGULATOR

A.O
DISTR~BUT10N

PANEL

1>,

Befor. replacing ti1ehlse Or '-slutator_ eh...,.. 10. poliible cauI_ Fulty
compo"."" within the r,guilltor i ••• II-cen c.u •• tha I.... 10 blow. Ch..,k for
scor<:hing 01 the -,ell board 8"dlot componan1!o, Check the b.clcpl ..... to ••
bent pin or. pl_ 01 wi •• which millht ba causing 8 ,hOI1 cir<:ult
II.V ...... I, an 1 '/010/10. check the YOlt8iJtll •• IIIIed In DECAID MRD

TROUBLESHOOTING FLOWCHART

12,131

111

TROUBLESHOOTING FLOWCHART

(1,51

REINSTALL
MEMORY BANKS
ONEATATIME
UNTILTtleDNE
GENERATING
THE8AD
QUIESCENT

L~OE~::J.IS
REPLACe

NOTE
REMEMBER. AC LO AND
DCLOAREALSOPOWER
SUPPLY DEPENDENT

TROUBLESHOOTING FLOWCHART

",II

,..,

_ _ _ TROUBLESHOOTING FLOWCHART

10 _ __

_ _ _ TROUBLESHOOTING FLOWCHART

11.7,9.101

TROUBLESHOOTING FLOWCHART

11,11,121

12 _ __

TROUBLESHOOTING FLOWCHART

12,7,'21

DECAID AC/DC LO _ _ _ _ _ __

LOCATION OF AC LO/DC LO SIGNALS
Signal

ACLO
DC LO

11/40"

11/45"

M726l
M7235
B08Fl
B0602
B08F2
B06Cl
(Very difficult to
scope. Check on tab
connector)

M8l06
C12Sl
C12Ul

11/05

Quiescent levels should be +4.8 V ± 0.2 V

AC LO and DC LO are generated in the above CP modules. the bulk
power supplies. and the power supplies of all peripherals. These are
all connected to the Unibus in a wired OR. The processor receives
them and makes itself and its memories totally inoperative if either
one is true. It. therefore. will be necessary to physically disconnect
the system in a logical fashion to determine which device is faulty .

• The following displays will be seen on the front penel if DC LO is true:
PDP·t 1/45 - The CPU's microaddress will be 200.
PDp·ll/40 - The CONS and AUN lights will ba off and the BUS and
PAOC lights will ba on.

OECAIO BUS

QUIESCENT UNIBUS LEVELS
Normal bus quiescent levels are listed below. Anv level that deviates from
normal should be looked upon as a potential failure. In most cases. this
improper level will be caused bV a defective bus receiver or driver. AC LO and
DC LO are also power-supplV dependent.
Signal

Quiescent Level

BG(7:4). NPG.
BBSY (on PDP-1 1/40)

+0.4V ± 0.4V

ACLO.
DC LO

+4.8 V ± 0.2 V

All others

+3.4 V ± 0.2 V

Procedure
To measure quiescent Unibus levels:

Turn the svstem on with the processor halted. Press the START kev
and release it with HALT down. (On older PDP-1 1/40s it is necessary to LOAD ADRS 000000 to clear the A<17:00> lines.)

Use a calibrated oscilloscope to measure the Unibus signal lines.
(See the following chart of Unibus slot backplane pins.)

To obtain meaningful readings of bus grant lines (BG<7:4> and NPG). thev
should be measured at each device wired to them down the length of the bus.
All buses should be checked in multiple bus svstems.

_ _ _ _ _ _ _ _ OECAIO BUS

UNIBUS SLOT
(Viewed from the Backplane)

+6V

INIT

I~~~ ---t-:O-i.
D02--+'~.

DO'
DO.

-..~+==DOl
00'
DO.

•

D06--+=---_

003

~
DDll~'==~.!

Dl0--+,~.
012

011

013
016

PA-

BBSV(+.4V±.4V ON 11/401
SACK

NPG:===~~9
B.7

:~~==NPB."
• A7

BG.

BA,BG:~-====~~~
AC LO

----,A.,.O,...,---t-:O-i1)
A03 ---t-:~.

A06

A07 ---t-:~.

AO.

All ---t-:~.
A13
A16
A17
SSVN
MSVN

•

BG'
:~~~~~~~B:A'

DCLD

ADO

A02
AD4

.-7-+-- A08

.-=-+---AD9
Al0

---t-:O-i.

.-=-+--:~!
~Al. Cl

:===l~'"

OGND

+3.4±.2V

ED +.4V±.4V

+6V

o +4.IV±.2Y>

~
o

DECAID CONSA

QUIESCENT CONSOLE LIGHT DISPLAY
Press and release the START key with the HALT key down.

PDP-11/40
ADRS = 000000
DATA = 000000
RUN = ON
BUS = ON
PROC = ON
CONSOLE = ON
All the rest = OFF
PDP-11/46
All ADRS = 000000
DISPLAY REG = 000000
BUS REG = 000000
DATA PATHS = Contents of RO
I'ADRS CPU = 170 (200 when START is held down)
KERNEL = ON (OFF when START is held down)
MASTER = ON
All the rest = OFF

DECAID CONSB

PDP·11106 CONSOLE CHECKOUT PROCEDURE
1. Make certain the computer power is off.
2. Disconnect the console cable connector from the M7260 module and
then turn on the computer power.
3. Aher step 2 is completed. the data pattern 177777, should be displayed
on the console lights.

4. At the connector that plugs into the M7260 module. use a piece of small
gauge wire and jumper pin F to the following pins and observe if the
displayed pattern is correct. Remove the jumper each time before pro·
ceeding to the next step.
5. Jumper: GND; Pattern: 000000
6. Jumper: N; Pattern: 125252
7. Jumper: L; Pattern: 146314
8. Jumper: J; Pattern: 170360
9. Jumper: 0; Pattern: 177400
10. Remove the jumper aher completing the procedure.

_ _ _ _ _ _ _ _ DECAtO HELP _ _ _ _ _ _ __

WHAT TO DO WHEN ALL ELSE FAILS
Most of the cases in the flowchart that take you here are for problem symptoms that are very unusual. Make sure you have checked every possibility. If
you have a solid problem and you just don't know where to go, start at NO-OP
on flow page 1.

OECAIO INT OPT

PROCESSOR'S INTERNAL OPTIONS
PDP-ll/06
None
PDP-11/40
KEll-E

Extended Instruction Set
M7238, slot 2
Requires jumper changes; see DECAID PROCA40

KEll-F

Floating Instruction Set
M7239. slot 1
Requires jumper changes; see OECAIO PROCA40

KT11-0

Memory Management
M 7236. slot B
Requires jumper changes; see OECAIO PROCA40

KJll-A

Stack Limit Register
M7237. slot 3E
Requires jumper changes; see OECAIO PROCA40

KW11-L

Line Clock
M7B7. slot 3F
Requires wire change; see OECAIO PROCA40

PDP-11/46
FPll

Floating Point Processor
MBl14. slot 2
MB115. slot 3
MB112. slot 4
MB113. slot 5
No jumper changes required.

KT11-C

Memory Management
MB10B. slot 13
MB107. slot 14
Requires removal of MB 116 from slot 14

KW11-L

Line Clock
M7B7. slot lC
Requires removal of wire between pin COl R2 and pin
C01V2.

_ _ _ _ _ _ _ DECAID LOADER

FOR SYSTEMS EQUIPPED WITH PAPER TAPE
NOTE
In the followinll de.cription., the value XX
reflacta the system's memory .iza a• •hown
below:
Mamory
Size

4K
8K
12K
18K
20K
24K
28K or IIreatar

01
03
06
07
11
13
16

LOAD ADRS ............................................................................................XX7744
DEPOSIT ..................................................................................................016701
000026
012702
000352
005211
105711
100376
116162
000002
XX7400
005267
177756
000765
177560 (nY)
or 177550 (PC11)

DECAID LOADER

Place the Absolute Loader tape in the specified reader with the special bootstrap leader code (ASCII code 3 5t) over the reader sensors.
LOAD AORS ............................................................................................XX7744
START
The Absolute Loader tape will pass through the reader and will stop when the
last frame of data has been loaded into memory.
Place the MAIN DEC tape in the specified reader with blank leader tape over
the reader sensors.
Press CONT or
LOAOAORS ............................................................................................XX75OO
START
The MAINOEC tape will pass through the reader and will stop when completely loaded into memory.
At this time RO which is displayed in the DATA display· will contain all zeros
in the low byte. If not. a checksum error has occurred indicating that some
data was incorrectly loaded. The tape should be reloaded.

FOR SYSTEMS EQUIPPED WITH DISK. DECtape. AND/OR
MAGTAPE
Hardware Bootstrap Loaders
The following table describes the procedures for loading the MAl NDEC monitors. Ensure that your XXDP medium is on drive O.

• For PDP-tt/05: to read RO. load address t77700 and press EXAM switch.

_ _ _ _ _ _ _ DECAID LOADER

ROM

Device

Proceduure

BM792-YB

RK11/RK05

LOADADRS ............... 773100
SWITCH REG .............. 777406
START

TC11ITU56

LOAD ADRS ......... ".".773100
SWITCH REG ............. 777344
START

RKll/RK05

LOAD ADRS ............... 773110
START

TCllITU56

LOAD ADRS ............... 773120
START

TMll/TU10

LOAD ADRS ............... 773136
START

RPll/RP03

LOAD ADRS ............... 773154
START

RKll/RK05

LOAD ADRS ............... 77301O
START

TCllITU56

LOAD ADRS ............... 773030
START

TMllITU10

LOAD ADRS ......., ....... 773050
START

TA11/TU60

LOAD ADRS ............... 773230
START

RPll/RP03

LOADADRS ............... 773100
START

MR11-DB

BM873-YA

_____________ DECAIDLOADER

ROM

Device

Procedure

BM873-YB

RKll/RK05
(unit zero)

LOAD ADRS ............... 773030
START

RKll/RK05
(Unit specified
in Switch
register)

LOAD ADRS ............... 773032
START

TCllITU56

LOAD ADRS ............... 773070
START

TMllITU10

LOAD ADRS ............... 773110
START

TJU16ITU16

LOAD ADRS ............... 773150
START

TA11ITU60

LOAD ADRS ............... 773524
START

RP11/RP03

LOAD ADRS ............... 773350
START

RJPQ4/RP04

LOAD ADRS ............... 773350
START

RJS03/RS03

LOAD ADRS ............... 773000
START

DECAID LOADER

Software Bootstrap Loaders
If the hardware bootstrap doesn't work, try one of the following
software bootstraps depending on your particular syystem
configuration.
Device

Procedure

RK11/RK05

LOADADRS ...
DEPOSIT ...................... .

..010000
.. 012737
000005
177404
000001
LOAD ADRS ........................... 010000
START
Wait 1 second.
LOAD ADRS ............................ 000000
START

TC11ITU56

LOAD ADRS ............................. 777342
DEPOSIT ...................................004003
DECtape will rewind.
EXAMINE
DEPOSIT ...................................000001
LOAD ADRS ............................. 000216
DEPOSIT .................................. 012737
000005
177342
000777
LOAD A DRS ............................. 000216
START

_ _ _ _ _ _ _ DECAID LOADER _ _ _ _ _ __

Device

Procedure

TMll/TU10

LOAD ADRS....
.. .. 010000
DEPOSIT.. ............................... 005137
172524
012737
060011
172522
000777
012737
060003
172522
000777
LOAD A DRS ............................ 010000
START
Wait 1 second.
Press HALT switch.
LOAD A DRS ............................ 010014
START
Wait 1 second.
Press HALT switch.
.. ...... 000000
LOAD ADRS ........
START

_____________ DECAIDLOADER

Device

Procedure

TJU16ITU16

LOAD ADRS ............................. 010oo0
DEPOSIT ...................................012737
001300
172472
012737
177777
172446
012737
000031
172440
105737
172452
100375
012737
177400
172442
005037
172444
042737
000007
172452
012737
000071
172440
105737
172440
000100
000375
000137
000000
LOAD AD RS .............................O10000
START

______________ DECAIDLOADER

Device

Procedure

TA11ITU60

LOAD ADRS ............................. 001 000
DEPOSIT ................................... 012700
177500
005010
010701
062701
000052
012702
000375
112103
112110
100413
130310
001776
105202
100772
116012
000002
120337
000000
001767
000000
000755
005710
100774
005007
017640
002415
112024
LOAD ADRS ....................... ,.....001 000
START

_ _ _ _ _ _ _ DECAID LOADER _ _ _ _ _ __

Device

Procedure

RX11/RX01

LOAD ADRS .............................001 000
DEPOSIT ................................... 005000
012701
177170
105711
001776
012711
000003
005711
001776
100405
105711
100004
116120
000002
000770
000000
005000
000110
000000
000000
000000
LOAD ADRS ............................. 001 000
START

RP11/RP03

LOAD ADRS ............................. 001 000
DEPOSIT ...................................012705
176716
012715
177400
012745
000005
105715
100376
005007
LOAD ADRS ............................. 001000
START

_____________ OECAIOLOADER _____________

Device

Procedure

RJP04/RP04

LOAD ADRS ............................. Ol0000
DEPOSIT ...................................012700
176700
012710
000023
005060
000034
005060
000006
012760
177400
000002
012710
000071
105710
100316
005007
LOAD ADRS ............................. Ol 0000
START

RJS04/RS04
RJS03/RS03

LOAD ADRS ............................. OOI 000
DEPOSIT ................................... 012705
172044
012745
177400
012745
000071
032715
100200
001775
100762
005007
LOADADRS.............................001000
START

_ _ _ _ _ _ _ DECAIDMAINDA _ _ _ _ _ __

MAIN DEC NAMING CONVENTION

-FP

KA-X

MCN level

x
o

= No MCN ever issued
= Initial MCN announcing
latest program version

1-9 latest MCN revision level
A thru Z = revision designation
A thru Z = program designation

o thru 9 = overlay designation
2 digits = option designation
~ A =

11/05. 15. 20 processors .
B = 11/40 processor
C = 11/45 processor
D = 11/05 only
E = 11170 system
Z = all processors
" X = DEC/X 11 exerciser software
D indicates a Diagnostic Program.
and is not used in naming a
program.

DECAID MAINDA

MAINFRAME MAINDECS AND THE PROCESSORS THEY
Run On
Name

Number

CTP Communications
GTPGeneral
T17 4K. CPU. 1/0
11 Family Instruction Exerciser
11/40 and 11/45
Instruction Exerciser
Multiplication-Division
Exerciser
11/40 and 11/45 Processor
Parity
11/45 Console Test
States 11 145
PIRO
Traps 11/45
T14 11 lOS. 20 Traps
T14 11140 Traps
Power Fail 1'1/45
Power Fail 11/05.20.40

DZOCA
DZOGA
DZOKB
DZOKC
DCOKC

X
X
X
X

X
X
X
X
X

X
X
X
X
X,

DCOKA

EIS

DCKBR

PAR

DIV
MUL
ASHC
ASH
11/45 Registers
SPL
Stack Limit
RTT
MARK
XOR
SOB
SXT

DCKBL
DCKBK
DCKBJ
DCKBI
DCKBH
DCKBG
DCKBF
DCKBE
DCKBD
DCKBC
DCKBB
DCKBA

DCKBO
DCKBO
DCKBN
DCKBM
DONC
DBKDM
DCKBP
DZKAO

X
X
X
X
X

EIS
EIS
EIS
EIS

KJ
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X

_ _ _ _ _ _ _ DECAIDMAINDA _ _ _ _ _ __

BASIC MAINFRAME MAINDECs (Run On All Processors)
Name

Number

T1 3 JSR. RTS. RTI
T12Jump
Tll Subtract
Tl0 Add
T9 Bit Set Clear Test
T8 Move
T7 CMP Non-Equality
T6 CMP Equality
T5 Rotate/Shift
T4 Binary
T3 Unary
T2 Con Branch
Tl Branch

DOMA
DOLA
DOKA
DOJA
DOIA
DOHA
DOGA
DOFA
DOEA
DODA
DOCA
DOBA
DOAA

DECAID MAINDA

MEMORY MAINDECS AND THE PROCESSORS THEY RUN
ON
Name

Number

0-124K Memory Exerciser

DZQMB

Memory 1/0 Exerciser

DZQMA

Up-Down Address Test

DZMMK

BK Special

DZMMJ

Random Data

DZMMI

Core Heating

DZMMH

Worst Case Noise

DZMMG

Ones Susceptibility

DZMMF

Moving Ones and Zeros

DZMME

Basic Test Patterns

DZMMD

No Dual Address Test

DZMMC

Basic Address Test Down

D1BA

Basic Address Test Up

D1AA

MAll,MFll, and MSll
Parity Test

DCMFA

PAR

MSll

DCMSB

MOS
BIP

_ _ _ _ _ _ _ OECAIO MAINOA _ _ _ _ _ __

INTERNAL OPTION MAINOECS
POP-11/45 Floating Point - FP11
Name

Number

GTP Overlay
Basic Instruction Exerciser
Division Exerciser
Multiplication Exerciser
Addition and Subtraction Exerciser
LD D/STD Exerciser

DCOOA
DCFPO
DCFPU
DCFPT
DCFPS
DCFPR
DCFPM
DCFPL
DCFPK
DCFPJ
DCFPI
DCFPH
DCFPG
DCFPF
DCFPE
DCFPD
DCFPC
DCFPB
DCFPA

Maintenance
MODF. MODD
LDEXP. STEXP
LDCJX. STCXJ
LDCDF.LDCFD.STCDF.STCFD
CLR. TST. ABS. NEG
DIVF. DIVD
MULF. MULD
CMPF.CMPD
ADDF. ADDD. SUBF. SUBD
LDF. LDD. STF. STD
STS. Illegal Instructions
Basic Test

PO P-11 /45 Memory Management - KT11-C
Name

Number

Exerciser

DCKTG
DCKTF
DCKTE
DCKTD
DCKTC
DCKTB
DCKTA

Abort
MFPD/I
MTPD/I
Keys
Logic 2
Logic 1

_ _ _ _ _ _ _ OECAIO MAINOA _ _ _ _ _ __

POP-11!40 Floating Point - KE11-F
Name

Number

GTP Overlay
Exerciser
Basic Instruction Test

OBKEO
DBKEB
DBKEA

POP-11!40Memory Management- KT11-0
Name

Number

Exerciser
Abort
States
MFPI/MTPI
Keys
Logic

DBKTG
DBKTF
DBKTD
DBKTC
DBKTB
DBKTA

Line Clock - KW11-L
Name

Number

Exerciser

DZKWA

DECAID MAINDB _ _ _ _ _ __

PDP-"
1.

SYSTEMS TESTS

DEC/Xll

2 hours
passes

2. DZQGA

GTP (for non-communication-oriented systems)' or

2 h 0 u rs
passes

0 r

DZQCA

CTP (for communication-oriented systems)'

2 hours
passes

, Mechanical devices. e.g .. TTY. line printers. should onlv be run 5 minutes.

PDP-11/05/10 CUSTOMER ACCEPTANCE DIAGNOSTICS
Central Processor

1. DZQKC

11 Family Instruction
Exerciser. any switch
0-7 up

30 minutes

2. DONC

T14 11/05. 20 traps

2 passes

3. DZQKB

T17 Systems Test. only
console device enabled

10 minutes

4. DZKAQ

Power Fail

.10 power fails

Read/Write Memories
1. DZQMB

0-124K Memory Exerciser. with switch 11 u.11

1 minute/8K

2. DZQMB

0-124K Memory Exerciser. 8K or greater

2 minutesl8K

3. DZMMI

Random Data. for less
than 8K only

5 minutes

_ _ _ _ _ _ _ DECAID MAINDB

PDP-11/35/40 CUSTOMER ACCEPTANCE DIAGNOSTICS
Central Processor
1. DCQKC

11/40 and 11/45
Instruction Exerciser.
any switch 0-7 up

30 minutes

2. DBKDM

T14 11/40 Traps

2 passes

3. DZQKB

T17 Systems Test. only
console device enabled

10 minutes

4. DZKAQ

Power Fail

10 power fails

Read/Write Memories

1. DZQMB

0-124K Memory Exerciser. with switch 11 up

1 minute/8K

0-124K Memory Exerciser. 8K or greater

2 minutes/8K

Parity Test

2 passes

DZQMB

3. DCMFA

Stack Limit Option - KJ11-A
1. DCKBF

Stack Limit Option Test

2 minutes

Extended Instruction Set - KE11-E
1. DCKBIDCKBL

ASH. ASHC. MUL. DIV
Test

2 minutes each

2. DCQKA

MUL. DIV
Exerciser

20 minutes

Random

_ _ _ _ _ _ _ DECAID MAINDB

Floating Instruction Set - KEll-F
1.

DBKEB

KE11-F Exerciser

20 minutes

DBKEO

GTP Overlay

20 minutes

Memory Management - KT1l-D
DBKTG

KT11-D Exerciser

4 minutes/8K

PDP-ll/45/50 CUSTOMER ACCEPTANCE DIAGNOSTICS
Central Processor
DCOKC

11/40 and 11/45
Instruction Exerciser

30 minutes

DZOKB

T17 Systems Test. only
console device enabled

10 minutes

DCKBP

Power Fail

1 pass

Read/Write Memories
1. DZOMB

0-124K Memory Exerciser, with switch 11 up

1 minute/8K

DZOMB

0-124K Memory Exerciser, 8K or greater

2 minutes/8K

DCMFA

Parity Test

2 passes

DCMSB

MOS Memory Test

2 passes

Floating Point Processor - FPll
1. DZFPO

FP11 Exerciser

20 minutes

GTP Overlay, all available devices enabled
except line printer if any

20 minutes

DCOOA

OECAIO MAINOB _ _ _ _ _ __

Memory Management - KT11-C
1. OCKTG

KT11-C Exerciser. all
available devices
enabled except line
printer if any

1 pass

DECAIDMEMA

MM11-S MODULE UTILIZATION

-I---

o
C;

.
N

DECAID MEMA II~~_ _ _ _ _ __

MF11-L(PI MODULE UTILIZATION

~;..

~t
, \;
• I·
A

-f--

N
~

"
"
~

* IF PARITY MEMORY.

DECAIDMEMA
G110 CONTROL MODULE JUMPERS
See the next page for a diagram showing the physical location of
the jumpers.

Device Address Jumpers'
Memory
Bank
(words)

Machine
Address
(words)

0-8K
8-16K
16-24K
24-32K
32-40K
40-48K
48-56K
56-64K
64-12K
12-80K
80-88K
88-96K
96-104K
104-112K
112-120K
120-128K

000000-037776
040000-077776
100000-137776
140000-177776
200000-237776
240000-277776
300000-337776
340000-377776
400000-437776
440000-477 77 6
500000-537776
540000-577776
600000-637776
640000-677776
700000-737776
740000-777776

W6
A14 or
A01t

W4
A15

W3
A16

W2
A11L

In
Out
In
Out
In
Out
In
Out
In
Out
In
Out
In
Out
In
Out

In
In
Out
Out
In
In
Out
Out
In
In
Out
Out
In
In
Out
Out

In
In
In
In

In
In
In
In
In
In
In
In

Out
Out
Out
Out
In
In
In
In
Out
Out
Out
Out

Out
Out
Out
Out
Out
Out
Out
Out

• W5 and W10 must be installed and W9 must be removed (for BK stacks).

t The memory can be interleaved as 16K only, using two adjacent contiguously addressed BK banks. When two BK banks are interleaved, jumpers
W7 and WB must be in the configuration shown by the dotted lines. Bit A01
goes to the device selector gate controlled by jumper W6. One B K bank
must have W6 installed and the other must have W6 removed.
When not interleaved. jumpers W7 and W8 must be in the configuration
shown by the solid lines. Bit A 14 goes to the device selector gate controlled
by jumper W6.
W7

6--n

W7~.Q

' .......

/",

~
Non-Interleaved

" "WB"- "- '

Interleaved

0
(")

CONTROL MODULE G110

COMPONENT 510E
SHOWING PHYSICAL

-I
:JI

LOCATION Of
JUMPERS

...0

3:
0

...

c:
m

m
(")

»
V
NOTES:
1. Jumper WI is for fest purposes only. It must be Installed for normal operation.
2. Jumper WI' should be removed for normal operation.When installed the memory
responds 10 DATI onlY,regordless of slate of control lines COO and COL
3. Jumpers W70nd we must remain in the factory installed positions.
4. When used as on 8k bonk, jumpers W5 and WIQ must be Instolled ond jumper
W9 must betemoved.

5. When used as a 4k bonk,jumperWl0must. be removed and jumper W9mus' be
installed. Jumper W5 determines the locollonof the bonk on the bus.

CONNECTOR EDGE /

DECAID MEMA

MF11-U(PI MODULE UTILIZATION

~
iii

.
50

~
~

;

,iii
I---

.;;;

* IF PARITY MEMORY.

! I

~
~
~

.c;

DECAIDMEMA

M8293 DEVICE ADDRESS JUMPERS

Memory
Bank
(Words)

Machine
Address
(Words).

0-16K
4-20K
8-24K
12-2SK
16-32K
20-36K
24-40K
2S-44K
32-4SK
36-52K
40-56K
44-60K
4S-64K
52-6SK
56-72K
60-76K
64-S0K
6S-S4K
72-SSK
76-92K
SO-96K
S4-100K
SS-104K
92-10SK
96-112K
100-116K
104-120K
10S-124K
112-124K
116-124K
120-124K

000000-077776
020000-117776
040000-137776
060000-157776
100000-1 7777 6
120000-217776
140000-237776
160000-257776
200000-277776
220000-317776
240000-337776
260000-357776
300000-377776
320000-417776
340000-437776
360000-457776
400000-477776
420000-517776
440000-537776
460000-557776
500000-577776
520000-617776
540000-637776
560000-657776
600000-677776
620000-717776
640000-737776
660000-757776
700000-757776
720000-757776
740000-757776

W7
A17

W6
A16

W5
A15

W4 W3
A14 A13

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

IN
IN
IN
IN
IN
IN
IN
IN

IN
IN
IN
IN

IN
IN

OUT

OUT
OUT

OUT

IN
IN

OUT

OUT
OUT

OUT

IN
IN

OUT

OUT
OUT

OUT

IN
IN

OUT

OUT
OUT

OUT

IN
IN

OUT

OUT
OUT

OUT

IN
IN

OUT

OUT
OUT

OUT

IN
IN

OUT

OUT
OUT

OUT

IN
IN

OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

IN
IN
IN
IN
OUT
OUT
OUT
OUT

IN
IN
IN
IN
OUT
OUT
OUT

IN
IN
IN
IN
IN
IN

IN
IN
IN
IN
IN
IN
IN
IN
IN

NOTE: The memory maybe interleaved in 32K increments. using
two contiguously addressed 16K banks.

DECAIDMEMA

In the 16K interleaved memory configuration the following changes
must be made:
WI is cut.
W2 is in.
W8 is in.
W9 is in.
Wl0 is cut.
W9 is cut.
Wl0 is in.

}
}

For one 16K of the interleaved pair
For the other 16K of the interleaved pair

Both interleaved memories should be cut for the same starting
address.

Non-Interleaved
WI is in.
W2, W8, W9, and WI 0 are cut.

____

DECAIDMEMA

_ _ __

M8293 16K UNIBUS TIMING MODULE

W3,W5.

NOTE:
W1. W2, we, W9, AND W10ARE SELECTED
FOR INTERLEAVED OR NON-INTERLEAVED
OPERATION. W3, W4. W5. W6.ANO W7
ARE SelECTED FOR STARTING ADDRESS

DECAIDMEMA

PCl SSYN DlY l ADJUSTMENT PROCEDURE FOR M7269
PARITY CONTROllER
This adjustment sets a 105-ns delay from the leading edge of SSYN
INT BUS L to allow sufficient settling time for the parity checking
logic. Too long a delay will result in increased cycle time and access
time. The waveshapes should be as shown below. Adjust R16 to
obtain the required delay.

SSYN DlY l TIMING RELATIONSHIP

DECAIDMEMA

CSR ADDRESS JUMPER SELECTION FOR M7269 PARITY
CONTROLLER MODULE.
Etch Rev D. CS Rev E
CSRJumpers W4

Bus Address Line A04

A03

A02

A01

X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X

X
X
X
0
0
0
0
X
X
X
X
0
0
0
0
X
X
X
X
0
0
0

X
0
0
X
X
0
0
0
X
0
0
X
X
0
0
X
X
0
0

Lower
Memory
Boundary

CSR Address

OK
4K
8K
12K
16K
20K
24K
28K
32K
36K
40K
44K
48K
52K
56K
60K
64K
68K
72K
76K
80K
84K

772100
772102
772102
772104
772104
772106
772106
772110
772110
772112
772112
772114
772114
772116
772116
772120
772120
772122
772122
772124
772124
772126

X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0

X
0

(Continued)

DECAIDMEMA

CSRJumpers W4

Bus Address Line A04

A03

A02

A01

X
0
0
0
0
0
0
0
0

0
X
X
X
X
0
0
0
0

0
X
X
0
0
X
X
0
0

Lower
Memory
Boundary

CSR Address

88K
92K
96K
lOOK
104K
108K
112K
116K
120K

772126
772130
772130
772132
772132
772134
772134
772136
772136

0
0
0
0
0
0
0
0
0

o = Jumper Removed
X = Jumper Installed
W6: Removed for MF11-LP. installed for MF11-UP

PARITY ERROR INDICATOR

[SABCDEFHJKL

w7ID~Dlw4Dlw2DoD
00
1

<;>

· 1 0 aI-a I a a 010I ~
o 0 0 0 0I DO! OI~Q

JUMPERSCONTROLO~TIONSA~LOWS'
Wl-W4
W5
W6
W7

SELECT CSR ADDRESS
CAPACITOR FOR SSYN DELAY (NEVER USEDI
OUT FOR MF11-lP,IN FOR MF11-UP
OUT TO HANG BUS ON PARITY ERROR

R16
SSYN DELAY ADJUSTMENT

~UI

::aU)
CD "lI

Q:
I\D
o 0 0,0 0 0 D,§@
<;>

inS:
.. -.I

C::a

-::::j

-t
::a

m
0

s:
s:
»

.c
C
r-

DECAIDMEMB

STROBE ADJUSTMENT PROCEDURE
USING THE G110

FOR

MEMORIES

When any module in the memory system is replaced. the strobe
must be adjusted for that system.
To adjust the strobe. use DZQM BC or a higher revision of the
0-124K Memory Exerciser MAINDEC.
Start the diagnostic at AD RS 214. allowing you to enter test parameters. Cycle on the bank to be adjusted while running pattern 1.
Check program procedures for further information.
Attach and sync channell to READ H pin CU2 of the G110 and
channel 2 to STROBE H at test point 1 on the G110. (See the next
page for the location of TP 1.)
Adjust the strobe to the earliest (minimum) setting at which the
memory will cycle error free and allow the test to run for three
minutes.
Adjust the strobe to the latest (maximum) setting at which the
memory will cycle error free; this adjustment is most critical and
there should not be more than 5 ns difference between the failing
and passing points on this adjustment. Allow the test to run at this
setting for three minutes or more.
This window should be 50 ns minimum. If it is not. replace modules
within that bank of memory until it is.
Adjust STROBE H to be 25 ns (leading edge to leading edge) from
the latest (maximum) setting.

READ H
PIN CU2
ON GUO

---l

5 . . . mIn

:-=j

1---- 2. . .

L--

r-l_~
. _ rI_..
r-'
~!..:u="':::..'_ _

STROBEH
TP10NG110----.J

DECAIDMEMB

G110 CONTROL MODULE

STROBe ADJUSTMENT
R1Z0

r---"------:'::~:-::o...c-\=

H I

1~~1,---_-----,18 8
I
CJD CJCJ
I~TP'
CJCJCJc::::::J

_ _ _ _ _ _ _ DECAID PROCA06 _ _ _ _ _ __

PDP-11/06 MAINTENANCE
The PDP-11 /05 has the ability to run a program in its General Purpose registers. Therefore. disconnect all Unibus devices and all
memory from the processor and if the console switches operate
properly. attempt the program shown below.
General Purpose Register (GPR) Program

LOAD ADRS ........................................................................... 177700
DEPOSIT ...... ...................
.....................................000240
000777
LOAD ADRS .......................................................................... 177700
START
The program is now being executed.
The run light should come on.
Press the HALT switch.
The ADDRESS/DATA display should contain either 177700 or
177701.
If a processor problem is indicated. replace the M7260 and M7261
modules. and attempt the failing procedure after each replacement.
Always replace one module at a time to ensure that you don't plug a
module into the wrong slot. If you are not absolutely positive. check
the module utilization diagrams in this DECAID.
After replacing the M7260. it may be necessary to adjust the SCL
clock as shown in this DECAID.
Remember. When you replace the M7261 module. check and if necessary. adjust the processor's clock rate as outlined in this DECAID.

_ _ _ _ _ _ _ DECAID PROCA05 _ _ _ _ _ __

PDP-11/05-JA MODULE UTILIZATION (16K)

PERIPHERAL CONTROLLER

GRANT CONTINUITY CARD G127 {SLOT Oil
UNIBUS TERMINATOR M930
OR EXTERNAL UNIBUS CABLE

I
I
I

MEMORY STACK H213(4K) OR (8K)

MEMORY DRIVER G231

MEMORY CONTROL GUO

UNIBUS TERMINATOR "'930

)

MEMORY STACK H213 14K) OR (8K)

MEMORY DRIVER G231

I
I

MEMORY CONTROL GilD

KDl1-S PROCESSOR M7261

1(011-8 PROCESSOR M7260

CONNECTOR

PDP-11/05-LA MODULE UTILIZATION (SK)

OFtI COMMUNICATIONS
LINE ADAPTER

KMlI

I<Mll

PERIPHERAL CONTROLLER
OR GRANT CONTINUITY CARD G727 (SLOT 01)

PERIPHERAL CONTROLLER

2 ~=:::MA="=T=:~::::=M:::"=NT=~ ~====:::O:::':::G:::":::NT=CO:::N:::":::NU:::IT=Y:::CA:::':::D:::":::2='::!S::LO::T::D::21==~
4

I
I

UNIBUS TERMINATOR M930 OR
EXTERNAL UNIBUS CABLE

OR GRANT CONTINUITY CARD G727 (SLOT 03)

BLANK

PERIPHERAL CONTROLLER
OR GRANT CONTINUITY CARD G127 (SLOT 04)

UNIBUS TERMINATOR M930

PERIPHERAL CONTROLLER

MEMORY STACK H213 (410 OR H214 (810

~1===========ME=M=O'=Y=D="=VE='=G=21=3===========~
,I~===========M=E=MO='=Y=CO=N=T'=O=L="=W===========~
'~I==========='="='-='=P='O=~=S=SO='=M=72=6='====================~

,1L________~------~---'-D1-'--B-P-RO~CE-S-SO-'-.-72-6-0--~------~--------J

...
... ~
~ "-...
'V

H213 14K) O~ H214 18K} MEMORY STACK

I'"
I'"

M930 UNIBUS
TERMINATOR

G231 MEMORY DR I VER

I..
I",

Gl to MEMORY CONTROL
6231 MEMORY DRIVER

~¢

Gll0 MEMORY CONTROL

H213 (4K) OR H214 18K) MEMORY STACK

!:.
~

M930 UNIBUS
TERMINATOR

I'"
I"

M7260 KD11-B PROCESSOR DATA PATHS
KMII-B
MAINT

II
I

KM11-A
MAINT

II
1

M9970 CABLE
CONNECTOR
0

(')

OFII COMMUNICATIONS
LINE ADAPTER

:1"

3: 2
o 3:

::I

::I
a::I

.!!.::!

111

o c:
r-

n
C

'V
:II

.....
2

M7261 KDtl-B PROCESSOR CONTROL LOGIC a MICROPROGRAM

::I

cCJI

.... "V
C
~
...... ~
....
......
~ 0
::I

n
MS293 MEMORY CONTROL MODULE

.930
UNIBUS TERMINATOR*'"

;:r

s:: 0
0 u.
::I s::
E'

.
C

G1I4 SENSE/INHIBIT MODULE

H217-D MEMORY STACK MODULE

'"DI r-c:C

C
m

~ m

G23$ X-V DRIVE MODULE

~
r-

N
;s:.

SPC SLOT i<

M9970 OR M997
SPC SLOT*

CONNECTOR MODULE

-I

(5
Z

SPC SLOT*

I0Il7261 CPU CONTROL MODULE

M7260 CPU DATA PATHS MODULE

M930
UNIBUS TERMINATOR

(')

;s:.
0

_ _ _ _ _ _ _ DECAID PROCA05 _ _ _ _ _ __

M7260 DATA PATHS MODULE
(Etch Rev. C)

NOTES'
1. ARROW ON 51 MUST POINT TO:
I) FOR 110 BAUO. 150 BAUD
4 FDA 300 BAUD

2. RUN A PROGRAM TO PRINT A
CONTINUOUS STREAM OF
CHARACTERS. ADJUST R21 TO
THE CENTRE OF THE RANGE
FOR WHICH SATISFACTORY
CHARACTERS ARE
PRINTED

oO~R21 0 0 0
OO@ODD
000000
PROGRAM TO PRINT A STREAM OF CHARACTERS

600/005000
602/106737

TOGGLE PROGRAM INTO CORE
LOAD ADRS: 500

6041177684

START

506/100375
510/110037
512/177566
514/105200
516/000771

PROGRAM WILL lOOP
CONTINUOUSLY UNTIL
HALTED WITH HALT SWITCH

M7261 CONTROL LOGIC AND MICROPROGRAM MODULE
(Etch Rev. F)

CLOCK ADJUSTMENT
1

DEPRESS HALT SWITCH

3. THEN AD.lUST Rl0

SWITCH REG .... 000500
DEPRESS LOAD ADAS
SWITCH REG <-000001
RAISE DEP
RAISE HALT SWITCH
PRESS Be RELEASE START

fOR A PERIOD OF
310NS.

--l I--

4O-80NS.

I
2. PLACE SCOPE PROBE
ONE55PIN8WHICH
IS THE FIRST PIN
ON THE LEFT ON
THIS lC LOOKING
AT THE BOARD AS IT
IS INSTALLED IN THE
BACKPLANE

J.- 310 NS. --l

c::::J c:::J c::::J

I c::::::J r::=:J c::::::J r::=:J
c:::::J
I
I c::::J
r::=:J
c::::J c:::J

..g.

iii :i:
....
::II

N
CII

~ 0n

z
.!!! -t

::II

CLOCK ADJUSTMENT

:11:~~::G...ooooo1
RAISE HALT SWITCH
PRESS AND RELEASE START

...
...

1. DEPRESS HALT SWITCH
SWITCH REG .....000&00
DEPRESS LOAD ADAS

1--310 NSEC -I

n
n
-.J L--..J L

3. THEN ADJUST ft7 FDA

A PERIOD OF 310 NSEC.

~~O~:;g;~~========~~::~~~~ ~.O~N~.~EC~==k=======~~~~~O~~
CJ=CJ

000000 D

0 .7 c::::J=oii

en
»z
0

LEFT ON THIS Ie LOOKING AT IT AS IT IS
INITALLED IN THE BACKPLANE.

»
0
'11

::II

:i:

::II

'11

::II
2. PLACE SCOPE PROBE ON Ell PIN •
WHICH IS THE SECOND PIN FROM THE

to)

::II

:i:
:i:
0
0

...m
C

_ _ _ _ _ _ _ DECAID PROCA40 _ _ _ _ _ __

PDP-ll/40 MAINTENANCE
The PDP-11/40 processor is comprised of the following modules:
M7231
M7232
M7233
M7234
M7235

SIot4
Slot 3
Slot 5
Slot 7
Slot 6

Always replace one module at a time to ensure that you don't plug a
module into the wrong slot. If you are not absolutely positive where
a module should go, check this DECAID for the module location,
Be very careful that the jumpers on the boards are cut and inserted
correctly for the particular system you are working on. See this
DECAID for a list of jumpers, their locations, and configurations.
When replacing the M7234 module, check and if necessary, adjust
the processor's clock rate according to the following procedure.
Clock adjustment requires a dual-trace oscilloscope with channell
(triggering) on D07P1 and channel 2 on E07L1. The computer
should be in the CONSOLE mode waiting for a switch activation.
This may be forced by a START in the HALT mode. Make sure that
both the RUN and CONSOLE lights are on. The Sl switch (see the
M7234 module diagram in this DECAID for its location) is adjusted
(in 10-ns increments) until the CL 1 interval shown below is:
~140 ns

< 150 ns.

f-CL1 -l
Chan 1 (D07Pl}

Chan 2 (E07l1 J

____~n~_____________

_____________________________________ DECAIDPROCA40 __________________________________________

PDP-11/40 PROCESSOR MODULE'S JUMPERS
Option/
Module

KE11-E

KE11-F

M7231

KJ11

KT11-D

Move: W2*

Move: Wl0

(L-+U)

KW11-L

Parity
Memory

(U-+L)

Cut: WI, W2.
W3. W4. W5.
W6. W7. W8.
W9
M7232
M7233

Cut: WIt

M7234

Move: WI

Move: W2

(U-+L)

(L-+U)

Cut: W5

Insert:
C113. 680 pF
C114. 560 pF
M7235:f:

Move: WI

CutW8

(U-+L)

M7238

Cut: WI.
W2.W3

Backplane

Remove: Wire
between pins
F03R2 and
F03V2

Note: U = upper position and L = lower position between three split pins when looking at the module with the handles at the top. That is:
Upper position

Lower Position
If the KT11-0 is installed along with the KJ 11. cut the jumper out completely.

Also install the three short cables between the M7232 and the M7238 modules.
Connections for W7 through W2 are shown on the module for basic power-up vactor address of 240. On the moudle's etch. the W numbers are
located under these original jumper positions.

"11

..
..
C
~

J!=ii

:<0

.
'a

;

W130.KM1'
MAINTENANCE
BOARD"

~z
gO;
~fl:

nz
o~

z~z
z~

:~
~

<~
~>

of
c~
Cm

!;;.!
~

W130.KM"
MAINTENANCE
BOARD"

sg ~
~
0

.~
g
~

M7239. KE11·F, FIS'

M787.
KW1 l-L
LINE CLOCK

I . I
M7237
...KJ
...
' l-A
STACK
LIMIT

M7232, KD1'-A, U WORD

M7231. KD"-A. DATA PATHS

M7Z33. KDl '-A.IR DECODE

l>
C

c:
::!

:JI

...

M7235. K01 l-A. STATUS

~
-t

~
M7234, KD1'-A, TIMING

0
2

M7238. KT1 ,-D, MEMORY MANAGEMENT'

SMALL PERIPHERAL CONTROLLER"

M9S1,INTERNAL
UNIBUS AND
TERMINATOR

...mc:

~
~

M7238. KE,,-E, EIS'

>\l

-~
>Zm

"11

0
0

_ _ _ _ _ _ _ OECAIO PROCA40 _ _ _ _ _ __

NOTE
As you are powering the mechine on and
off. one of the regulators may crowbar.
You should suspect this if all the symptoms change for no apparent reason. If this
should happen. determine which regulator
has crowbarred. then turn its adjustment
potentiometer a half revolution counterclockwise. and power the machine down
and up. Then. with a scope. readjust the
regulator so that it is producing the correct
output. Remember that the machine must
be powered ·down and up to turn the crowbar circuit off. Just turning the potentiometer down is not enough.

in S
g N.....
::r

::a !:!

CD
~

1:=:::
DDDD DD
L-~

MOVE W2FROM LOWER TO UPPER POSITION
WHEN INSTALLING KJll.
REMOVE COMPLETELY WHEN INSTALLING KT11·D

-t
g »

»"II-t
J:

en
3:

,...c:

MOVE W10 FROM UPPER TO LOWER
POSITION WHEN INSTALLING KT11-D

CUTW1 THROUGH W9WHEN INSTALLING KT11·D

"II

::a
0
n

_ _ _ _ _ _ _ DECAID PROCA40 _ _ _ _ _ __

M7233 IR DECODE MODULE
(Etch Rev. 0)

c:::J
CJ
c:::J

CJ
CJ

c:::J

CJ
CJ

CJ c:::J
CJ

c:::J
CJ c:::J
oo--e WI

c:::J
W2 NOT USED
ALWAYS INSERTED

CUTWl WHEN
INSTALLING KE11·E

M7235 STATUS MODULE
(Etch Rev. 0)

CONNECTIONS FOR W1 THRU W2 ARE SHOWN

FOR BASIC POWER UP ADRS OF 24.
ON ETCH, THE W NUMBERS ARE LOCATED
UNDEATHESEQRIGINALJUMPER POSITIONS

I
I

00000000
W8W7W6 W5

c:::=1o 0 0 0 0 0 0 0 c::::J
W4
W2
O 0 0 0 c::::J
c::::J 0

CUTW8WHEN INSTALLING
PARtTY MEMORY

MOVE Wl FjlOM UPPER TO
LOWER POSITION WHEN
INSTALLING lUll

MOYE W2 FROM L~WER
TO UPPER POSITION
WHEN INSTALLING KT11-0

00 OIODODD D

C
m

n
~
c

INSERT
W3 AND W4 NOT USED
ALWAYS INSTALLED

ROTARY SWITCH USED TO
ADJUST PROCESSOR CLOCK

C113180PFI

AND C1141&80 PFJ
WHEN INSTALLING

KT11-0

MOVE W1 FADM UPPER TO
LOWER POSITION WHEN
INSTALLING KJ11

CUTW&WHEN INSTALLING
PARITY MEMORY

"II
::II

o
~

_ _ _ _ DECAIDPROCA40 _ _ __

M7238 EIS MODULE
(Etch Rev. D)

CUTW1, W2.ANDW3 WHEN INSTALLING THE KE',-f

______________ DECAIDPROCA46 _____________

PDP·11146 MAINTENANCE
The POP·11/45 processor is comprised of the following modules:
M8100
M8101
M8102
M8103
M8104
M8105
M8106
M8116
M8109

Slot 6
Slot 7
Slot 8
Slot 9
Slot 10
Slot 11
Slot 12
Slot 14 (if no Memory Management)
Slot 15

Always replace one module at a time to ensure that you don't plug a
module into the wrong slot. If you are not absolutely positive where
a module should go. check this oECAlo for the module location.
The PDp·11/45 has two 860 Power Controllers (one switched and
one unswitched) or an 861 Power Controller with switched and
unswitched outputs. Therefore. before you replace any modules. be
sure to turn the power off at the power controller(s)' circuit break·
er(s) not just at the front panel key. You might accidentally be
changing a module that still has power applied to it.
When replacing the M8100. copy W1 through W6 from the old
module onto the new module. See this DECAlo for their location.
NOTE
As you are powering the machina on and
off. one of the reulators may crowbar. You
should suspect this if all the symptoms
change for no apparent reason. If this
should happen. determine which regulator
has crowbarred. then rotate its adjustment
potentiometer a half turn counter·
clockwise and power the machine down
and up. Then with a scope. readjust the
regulator so that it is producing the correct
output. Remember. the machine must be
powered down to turn the crowbar off.
Just turning the potentiometer down is
not enough.

~ ~~
~. "Ci ~
-----------------------------------OECAIOPROCA46 __~~~~--~~~~~lt~---______________
'01

t~ fI./

POP·11/46 MODULE UTILIZATION
FLOR70v t;
/'~.IN r "..,c?)"; I

.. ,..

Mg,.
A

M8114

...
•

MI116 MI112
>OM

. . .. "

M1102

01\1') ~. >-"ttlO'

......

}

eF . .
-t--

.o.
- ' 0 +- .~ir*~J:o::l~~

Ua::f

_fu
D

0.3

~ll:!i:

- t!!!

~ti~

~
~ '~

----.* ~ ~ ~

.. " . " " "

... ,... ...

- ""J:! ~ ;
>M~

.
.AI'!

1;;:\··

MEM

M'M

CHrlll

r---- MI'"
G•••

•

~ ~ K ,(
..,

~::t:1-

20
22

~ ~

~ ~ ~I~ ~ ~

~
;.:: ~

."-. ~
'f
o·

I-- r--

0 0

M1200 FOR SINGLE UNIBUS CONFIQ

....
I-

~';:A
Mal11-YA

. ... :-0§
i

I----' ~~

...• .•

aPACE REsIAVED FOR II!MICONDUCTGR
MEMOJIV OPTIONS (SLOTS , . THRU 2&1

.,
§

SPACE RESERVED FDA

~ ~_PERIPHERAL

! :e~

I-:f~

CONTROL\..l!RB

\5J
~

"l
~
1-)

... - - I

"PG~'

., 2

,{. i.. ~

PARITY

il'" ...I
G401YA

~ E~ ~ 5:~
< !:l \i.",
~
""!c!!:
~ ~ ~
ffig ~

. -. .----.

eNTAL

M.'

MillO

... ~ ~ " .

Mll11

~ ~

Mll03 MS104 M8106 MIl"

>xP

M8100 Ma101

. .,

Ma113

ern.'\..

~2~
.. DUIGNATES OPTION

0" pOlltlon. This il

Power to MOS end BIPOLAR memory remains on with the console on/off Iwitch In the
indicated by the LED on the MOS Control Board.

Caution must be observed when Installing the boards Into the bl!ckplane because of non~standerd voltages
praunt in slots 1. 2 end 16 thru 28.

If onlv ons Unibus is used:
The Unibus plugs into slot 28. plug en intemal bUI connector Jumper (MI200) Into slots 28 end 27. snd plug. bus
terminator (MI30) into slot 1.
If two Unibu ... are used:
Unibus A plugs into slot 28. terminetor for Unibus A plugs Into slot 1, Unibus B plugs into slot 27. end termlnetor
for Unibul B plugs into slot 28.

Modules in slots 17·20 must be same type. modules in lIots 22·26 must be same type.

If KT,1 option II present. MS10a goes inslot13. M8107 goes in slot 14. IfnoKT11. M81,llIo•• lnslot 14end
slot 13 is empty.

_ _ _ _ _ _ _ DECAID PROCA45 _ _ _ _ _ __

M8100 DAP MODULE
(Etch Rev. C)

W1 THRU W6 DETERMINE THE POWER

UPVECTDR ADDRESS (USUALLY 24).
COpy FROM ORIGINAL MODULE.

DECAID PROCB

CPU MODULES THAT
SIGNALS

DRIVE AND

RECEIVE

UNIBUS

CPU

Module

Unibus Signal

POP-ll/05

M7260
M7261

0<15:00>
All the rest

POP-11/40

M7231
M7235
M7234

A<17:00>.0<15:00>
AC LO. OC LO.INIT. 0<07:00>
All the rest

POP-11/45

M8104
Mal16
Mal05
MB106

0<15:00>
A<17:00>
BR<7:4>
All the rest

DECAID PWRB-'

BACKPLANE DC VOLTAGE CHECKS
With a calibrated scope. check the voltage levels and ripple on the
backplane at the points indicated in the following tables. Notice that
the tables indicate which regulator is providing the power being
measured so that you can easily locate the correct one to adjust.
(See OECAIO PWRB-2 for the regulators' physical locations.)
Use a good scope probe with as short a ground lead as possible.
Use "flag" type probe tips on both the scope probe and the ground
lead and ground the probe on the backplane (not on the cabinet) as
close as possible to the power point being measured.
CAUTION
Be extra careful that you put the ground
lead on the correct backplane pin. Otherwise you may short something to ground
which could cause considerable damage
to the machine and your pride.
Only the voltage levels can be. adjusted - not the ripple. If the magnitude of the ripple is greater than that specified. the offending regulator must be replaced.

OECAIO PWRB-1
POP-11/40 CPU DC VOLTAGE CHECKS
Voltage
(±5%)

Maximum Ripple
(P-PVolts)

Regulatorl
Slot

009A2
(A01A2)

+5.0

0.20

H744/A

C09U1

+15.0

0.45

H742*

009B2
(C09B2)

-15.0

0.45

H745/E

'No adjustment.

NOTE
If there is an M F11-U memory installed In
the processor box, then all -15 V power
must come from the H745 in slot O. since
slot E contains the H754. Some configurations may have H754s in both slots
o and E and then. of course. there cannot
be anything installed in the box that
requires -15 V. e.g .• many small peripheral
interfaces. MF11-L memories. etc.
POP-11/45 CPU DC VOLTAGE CHECKS

Voltage

Maximum Ripple
(P-PVolts)

Regulatorl
Slot

A02A2

+5.0

0.20

H744/A (FPP)

F09V1

+5.0

0.20

H744/B (CPU)

F15V1

+5.0

0.20

H744/C (CPU)

F26A2

+5.0

0.20

H744/0
(I NT OPT)

E02B2

-15.0

0.45

H745/E(lNT)
(I NT OPT and
CPU)

(Continued)

DECAID PWRB·'

Voltage

Maximum Ripple
(P·PVolta)

Regulator/
Slot

A19A2

+5.0

0.20

H744/H
(Bipolar)

A17V2

+23.2

0.70

H746/H
(MOS)

A17U2

+19.7*

0.60

H746/H
(MOS)

F17Cl

-5.0

0.15

H746/H
(MOS)

A16A2

+5.0

0.20

H744/J
(MOS)

A21A2

+5.0

0.20

H744/K
(Bipolar)

A24A2

+5.0

0.20

H744/L
(Bipolar)

E15Al

+15.0t
(13.5-16.5)

0.45

Top H742
(Switched)

E01Bl

+8.ot
(6.8-9.2)

0.24

TopH742
(Switched)

E16B2
E21B2

-15.0t
( 13.5-16.5)

0.45

Bottom H742
(Unswitched)

• 3 to 4 V less than +23.2.

t Not adjustable.
All voltages are to be adjusted to ±5% except +23.2 V. which is
+3%. -5%.

OECAIO PWRB-l

REGULATOR SPECIFICATIONS

Regulator

Voltage
and
Tolerance

Output
Current
(Maximum)

pop Ripple
(Maximum)

H744

+5Vdc ± 5%

25A

200mV

H745

-15 Vdc ± 5%

lOA

450mV

H746

+23.2 Vdc +3.
-5%

H754

'SA}

+19.7 Vdc

3.3A

-5Vdc

1.6A

+20Vdc ± 5%

700mV

(1)

700mV
150mV

5%} 3)
-5 Vdc ± 5%
H742

1 A-8A

(4)

3A}

(2)

+15Vdc ± 10%
+8Vdc±15%

20-30Vac
(5 outputs)

300 Weach
output,
1 Kw max.
total output.

Notes:
1. Refer to drawing O-CS-H746-0-1. Since the 19.7 V output
is obtained by regulating down from the + 23.2 V level. any
combination of loads on the two outputs is acceptable as
long as the sum does not exceed 5 A.

DECAID PWRB-1

Notes (Conti:
Negative 5 V level is obtained by inserting a 5.1 V zener
diode in series with the +23.2 and +19.7 loads. and using
the zener cathode as GND. Therefore. maximum -5 V load
current is equal to the greater of 1.6 A or the sum of the two
positive load. cu rrents (+ 2 3 and + 19).
2. Total not to exceed 3 A continuously.
3. At backplane. Typical ripple ~ ±3%.

4. Maximum -5 V current is dependent upon 20 V current. It
is equal to 1 A + 1(+20) up to a total of 8 A. (I (+20) is the
amount of +20 V current.)

DECAID PWRB-2

PDP-ll/40 REGULATOR/SLOT ASSIGNMENTS

Regulators
E

H745
-15V
or
H754
+20V
-5V
if
MMll-u/UP

H744' H744 H744
H745
+5V +5V +5V
-15V
or
H754
+20V
-5V
if
more
MMll-U/UP

H742
Bulk
Power Supply
AC LO
DC LO
20-30 Vae

+15V
+8V
LTC

Some earlier versions with small power requirements had no regulator
in slot C.

OECAIO PWRB-2

POP-11/45 REGULATOR SLOT ASSIGNMENTS
(Serial Numbers Beow 2000)
H745

H744

REGULATORS

BULK
SUPPLY A
REGULATORS

+15V

+5V
INTERNAL

+5V

CENTRAL

+5V

CENTRAL

PROCESSOR

OPTIONS

PROCESSOR

CENTRAL
PROCESSOR

FLOATING
POINT

-15V TO
ROWS
1.2.15

A.B.CoE
SWITCHED

+15V TO REGS

E.F

+5V TO
INTERNAL
OPTIONS

-ISV TO

ROWS
26.27.28

+15V TO ROW
13 CONSOLE

ROWS

26.27.28
CONSOLE

+BV TO ROW
1 FOR MAINT
MODULES

SYSTEM
UNITS

-15V TO
5YS

+ sv TO
SYSTEM
UNITS

#1.1'2.#3

UNITS

#1.#2

+5V TO

+SV TO

ROWS
10.11.12.13.14.15

ROWS

1.6.78.9

2.3.4.5

+SV TO

50/60 HZ SIG
(0 TO+5V)
TO ROW 1
FOR ClOCK
MODULE

H742 Upper Power Supply

H744

H744
or

H746

H744

H746

H745

REGULATORS
+5V

+5V

IF BIPOLAR

+5V
IF BIPOLAR

-15V
SYSTEM

MEMORY IS
INSTALLED

UNITS

+sv TO

ROWS
1920

ROWS

+SV

BIPOLAR

MEMORY

BULK
SUPPLY B
REGULATORS
F.H.J K.L
NOT

SWITCHED

+5V TO
ROWS

24.25
19V.23V~5V

+19V +Z3V -5V
IF MOS MEMORY IF MOS MEMORY
IS INSTALLED
IS INST ALLEO

IF MOS MfMORY
IS INSTALLED

MOS VOLTA
10 ROWS

22- 25

16.17.18

+5V

+5V TO

ROWS
2122.23

+5V TO
ROWS
16.17.18.1920.
21222324.25

MOS VOLTAGES
TO ROWS

17-20

-15V TO
SVS UNIT

H742 Lower Power Supply

• REG H
WILL BE
EITHER A
+SV OR MOS
VOLTAGE REG

OECAIO PWRB-2

POP-11/45 REGULATOR SLOT ASSIGNMENTS
(Serial Numbers 2000 and Higher)
H745
or

H754

H744

RE GUI A TOR '0

·1511 TO
SYSTEM UNIT

123

H742
BULK
SUPPLY

-SV
INTERNAL
OPTIONS

-SV
rrNT~Al

PI-IO( ESSOR

-SV
CENTRAL
PROCESSOR

-SV
FLOATING
POINT
• 1SV TO

REGS E F

·5\1 TO
ROWS

ROW

13&'CONSOLE

262728

AClO,DelD

'20'0' SV
AL TERNATE
TO SYSTEM
UNITS

123

-8V TO ROW
1 FOR MAINT

MODULES

·511 TO
SYSTEM
UNITS

50/60 HZ SIG
,0 TO -511)

123
-511 TO
ROWS
10-15

'511 TO

-5V TO

ROWS
16.7,89

2345

ROWS

TO ROW I
FOR CLOCK
MODULE

H742 Upper Power Supply

H744

H746

H744

H745

H746
RE-GUlATORS

+SV
BIPOLAR
MEMORY

H742
BULK
SUPPLY

+sV
IF BIPOLAR
MEMORY IS
INSTALLED

+5V
IF BIPOLAR
MEMORY IS
INSTALU.D

+5\1 TO

ROWS

1920

ROWS
161718

+5V

+19'1 +23'1 -5\1

INTERNAL

IF MOS MEMORY IF MOS MEMORV
IS INST ALLE D
IS INSTALLED

OPTIONS
15'0' TO
ROWS
262728
CONSOLE

+1511
CENTRAL
PROCESSOR

1511 TO
ROWS
1 2 15

+ 5V TO
ROWS
24.25
+19V +23V -5V

IF MOS MEMORY
IS INSTALLED

MOS VOlTAGES
TO ROWS

22 - 25

+5',1 TO
ROWS
21.2223

+5'0' TO
ROWS
16-25

MOS VOL rAGES
TO ROWS

17 - 20

H742 Lower Power Supply

ISV TO
CENTRAL
PROCESSOR

A(LO
DCLO

DECAID PWRB-2

PDP-11/45 VOLTAGE REGULATOR CONFIGURATION DATA
CABINET SERIAL NUMBERS 2000 AND HIGHER

Type

Regulator
Quantity
Name

Location

Comments

Basic System
H744

H745

+5V

-15 V

+5 V to CPU modules
slots 6-9.

+5 V to CPU and
KT11-C modules.
slots 10- 1 5.

+5 V to internal
options, slots 26-28,
system units 1, 2, and
3, and console.

-15 V to CPU and
internal option modules. This supply is
switched, even in the
lower H742, because
it is fed by + 1 5 Vdc
frol)1 the upper H742.

FP11-B Floating Point Processor
H744

+5V

+5 V to FP11 modules, slots 2-5.

DECAID PWRB-2

PDP-ll/46 VOLTAGE REGULATOR CONFIGURATION DATA
CABINET SERIAL NUMBERS 2000 AND HIGHER (CONT)

Type

Regulator
Name
Quantity

Location

Comments

MSll-C Bipolar Memory
H744

+5V

H.J

+5 V to control and
matrix modules if no
MOS memory is
installed. or only 4K is
used. H: slots 16-18;
J: slots 19-20.

K. L

If MOS memory is
also installed. or if
more than 4K of bipolar is used. K: slots
21 -23. L: slots
24-25.

MSll-B MOS Memory
H744

+5V

+5 V to control and
matrix modules. slots
16-25.

H746

MOS

H.L

+19.7 V. +23.2 V.
and -5 V to MOS matrix modules; H slots
17-20; L slots 22-25.

MMll Core Memories and Controls
H745

-15V

-15 V to system units
1-3.

H754

+20.-5V1

20 and -5 Vdc to
MF11-U/UP. No -15
Vdc available for other
system units.

DECAID PWRB-2

PDP-11/46 VOLTAGE REGULATOR CONFIGURATION DATA
CABINET SERIAL NUMBERS LESS THAN 2000

Type

Reguleto
Quantity
Name

Location

Comments

Basic System
H744

H475

+5V

-15V

+5 V to CPU modu·
les, slots 6-9.

+5 V to CPU and
KT11-C modules,
slots 10-1 5.

+5 V to internal
options, slots 26-28,
system units 1, 2, and
3, and console.

-15 V to CPU and
internal option modu·
les and system units 1
and 2.

FP11-B Floating Point Processor
H744

+5V

+5 V to FP11 modu·
les, slots 2-5.

MSll-C Bipolar Memory
H744

+5V

H,J

+5 V to control and
matrix modules if no
MOS memory is
installed, or only 4K is
used. H: slots 16-1 B:
J: slots 19-20.

DECAID PWRB-2

PDP-11/46 VOLTAGE REGLATOR CONFIGURATION DATA
CABINET SERIAL NUMBERS LESS THAN 2000 (CONTI

Type

Regulato
Neme
Quantity
2

Locetion

Comments

K. L

If MOS memory is
also installed. or if
more than 4K of bipolar is used. K: slots
21-23. L: slots
24-25.

MS11-B MOS Memory
H744

+5V

+5 V to control and
matrix modules. slots
16-25.

H746

MOS

H.L

+19.7 V. +23.2 V.
and -5 V to MOS matrix modules; H slots
17-20; Lslots22-25.

MM11 Core Memories and Controls
H745

-15V

-15 V to system unit
3. ;H745 provided in
basic system supplies
system units 1 and 2.
This supply is switched even in the lower
H742. because it is
fed by + 15 Vdc from
the upper H742.

OECAIO PWRB-2

H744. +5 VOC REGULATOR

INPUT/OUTPUT

POWER

INDICATOR
LIGHT

OECAIO PWRB-3

CROWBAR PROBLEMS
As you are powering the machine on and off (or for various other
mysterious reasons). it can happen that one or more of the regulators may crowbar. That is, the regulator short circuits its output to
protect the load. The output of a crowbarred regulator would be
seen as approximately 0 V.
To check for this, first power the machine down. (This is very important: otherwise the crowbar circuit will not reset.) Then rotate the
adjustment potentiometer of the offending regulator(s) counterclockwise a half revolution. Turn the power back on and observing
the voltage level with a scope on the backplane pin, readjust the
potentiometer so that the regulator is providing the correct output.
If you can't adjust the regulator's output to the correct level, then
something else is causing the fault. Continue on the PWRB flows.
If you find that the regulator crowbars again after this procedure,
then you have something connected to the regulator's output that is
causing it to go too high. This is often due to a poor connection in
one of the connectors in the power harness. Work the connectors
firmly into their sockets and manipulate the wires going into the
connectors.
Also look for possibilities such as a loose piece of wire shorting out
a couple of backplane pins or else a backplane pin that is bent and is
touching a neighboring pin.

DECAID PWRB-4

DISTRIBUTION PANEL CONNECTORS
The following diagrams show the locations of the pins carrying the
power and signals into and out of the various distribution panels
used on all models of the PDP-11/40 and PDP-11/45 processors.
Check for these voltages by wedging the scope probe down into the
connectors pin socket so that the probe makes connection with the
pin inside the socket.
Note that the pin layout for the distribution panel supplying power
to the system units on PDP-11 145s with serial numbers 2000 and
higher is the same as the one for distribution panels used on PDP11/40s with serial numbers 6000 and higher.

PDP-11/40 DISTRIBUTION PANEL CONNECTORS
SERIAL NUMBERS 6000 AND HIGHER

<::

FOR

CONSOLE

i)~
LJ~

1.
2.
3.
4.
6.

GND tBlKI
LINE eLK IBANI

DC LO (VIOl
AC LO lYELI
SPARE
SPARE

r-.....,

•

,.
'3

1. +6vIREDI
2. +15V(GRVI
3. +20V lOAN)
4. +&V(REDI
S. GND tBlKJ
6. SPARE
7. GNDIBLKJ
8. ONDIBLKJ
9. GND (BlK)
10. SPARE
OND CBlK)
12. SPARE
13. -16VIBLUI
'4. -&VIBRNJ
15. SPARE

'-..../

(Continued)

DECAID PWRB-4

In the mainframe box's distribution panel there are four groups containing five pairs as shown above. Within a group, all pairs are bussed together pin-for-pin by the distribution panel. Each connector
mayor may not have all the above-listed wires connected to it.
PDP-11/40

DISTRIBUTION

PANEL

CONNECTORS

FOR

SERIAL NUMBERS LESS THAN 6000

<::

CONSOLE

,'0

•

'---J

DC LO (VIO)
AC LO (VEL)

-15V(BLU)

-15V(8LUj

GND (BlK)
GND (eLK)
GND (eLK)
GND (BlK)

•.•.

GNe (BlK)

SPARE
SPARE
LINE eLK(BRN)

+15V(GRY)
+5V (RED)
TO BACKPLANE

-15V(BLU)

2.
3.
4.
5
6.
7

4
5.
6.
7.

•.
•

1
2.
3

SPARE

GND (BlK)

6
7
8.

+5V (RED)

GND (BLK)

+5V (REO)

11.
12.

+15V(VIOJ

SPARE
LINE eLK (BRN!
liNE eLK (BRN)

+15V(VIO)

GND (BLK)
DC LO (VIO)
SPARE
SPARE

DC LO (VIO)

11
12

AC LO (YEL)
AC LO (YEL)

FROM REGULATORS

In the mainframe box's distribution panel. there are three groups
each containing five connectors, that is, the two 12-pin connectors
shown above and three of the 9-pin connectors shown above. Within a group, all three 9-pin connectors are bussed together pin-forpin by the distribution panel. Each connector mayor may not have
all the above-listed wires connected to it.

TO SYSTEM U"IIT5
HAR"IE:5S 7008784
(5/"1 < 2.000}

.,.
~

......
U1

III

:I>

;0:

,...'V

:I>
Z
m

z
m

-I

:Jl
III

:Jl

,i.

(I)

:I>
Z

c
:!!

(I)

DECAID PWRB-4

INSTALLATION OF SYSTEM UNITS, LATER SYSTEMS, PDP11/46 CABINET SERIAL NUMBERS 2000 AND HIGHER

THE PIN lA'tOur FOR THIS DISTRIBUTION PANEL
IS THE SAME AS THE ONE USED ON" 140', WITH
SERIAL NUMBERS 6000 AND HIGt4ER

DECAID PWRB-4

INSTALLATION OF SYSTEM UNITS, EARLY SYSTEMS, PDP-

11/45 CABINET SERIAL NUMBERS LESS THAN 2000

7008784
POWER HARNESS

NOTE

Inoom. ",'em"MS, • ..e~
•• MMll-S,G772ApluU
iMO .'01 C04;o~oIne'
opl1o",. 1103" i ......d

~fc~~ ,:i:~~~!t::,':.'t1e

G772A
PC BOARD

SEE "OTE 1
LINE
CLOCK

(p;n.,dtoISj"t",

u",1 po"" sl.')

DECAID PWRB-5

POWER HARNESSES AND CABLES
Before you replace any of the cables or harnesses. ensure that the
connectors are making a solid electrical connection. Firmly work the
connectors into their sockets and manipulate the wires at the connectors while looking for any changes in the problem symptoms. If
this procedure causes a change. then it may only be necessary to
reset the connectors in their sockets or the pins in their connectors.
If you find that it is necessary to replace any cables. refer to the
following pages of this DECAID to make sure that you obtain the
correct replacement.
Present and future power handling capabilities of the 11/40-11/45
CP expander boxes and H960D. E cabinets have been increased
with the creation of two new main power harnesses.
Along with this comes a whole new set of option cables necessary
to connect our existing options to this new power configuration.
New and old machines may be easily identified by visually
inspecting their serial number affixed to the expander box or by
noting the new main power harness that is installed within the
expander box.
Serial numbers> 6000 indicate a new PDP-11/40 power configuration « = old type).
Serial numbers > 6000 indicate a new H960D. E power configuration « = old type).
Serial numbers> 2000 indicate a new PDP-11/45 power configuration « = old type).
The following tables list the options and CPU power harnesses
affected by this change. Also included are the part numbers for other power cables not affected along with remote sense and intermodule cables used in the PDP-11 world.

DECAID PWRB-6

POWER DISTRIBUTION HARNESS
(Power Supply to Distribution Points)
Description

Cable

PDP-11/15, PDP-11/20

70-6518

8A11-ES

70-5894

PDP-11/05 NC, PDP-11/35
10-1/2-inch box

70-9208

PDP-11/45, PDP-11/50
(Old)

70-8784

PDP-11/40 and H960D/E
(Old)

70-8754

PDP-11/45 and PDP-11/50
(New)

70-9540

PDP-11/40 and H960D/E
(New)

70-9566

• There will be some units between serial number. 6000 and 6542 that will
still have the old configuration.

DECAID PWRB-6

DC DISTRIBUTION TO CPU BACKPLANE
Description

Cable

PDP-ll/05S

70-9918

PDP-ll/05 NC
PDP-ll/10
1O-1/2-inch box

70-9360

PDP-11/35

70-9209

PDP-11/40
(Old)

70-9046

PDP-11/45

N/A

PDP-11/40
(New)

70-9564

PDP-11/35S

70-10113

NOTE
If a new PDP-11/35-PDP-11/40 backplane is ordered (part no_ 70-10230), you
must order 70-9994 cable for new-style
PDP-11/40s. For old-style PDP-11!40s,
use original cable cut to length.

_ _ _ _ _ _ _ DECAID PWRB·5

REMOTE SENSE CABLES
Description

Cable

861 Remote Sense Cable (11/40 to 861)

70·9053

861/860 Remote Sense Cable (861/860
to 861/860)

70·8288

861/860 Remote Sense Cable (861/860
to 1st H720E/F)

70·8964

H720E/F to H720E/F Remote Sense
Cable

70·8288

H720E/F (J2) Remote Sense Terminator
Plug

70·7006·1

H 720E/F (J 1) Local Sense Jumper Plug

70·7006·2

INTER·MODULE CABLES
CPU Type

Description

Cabla

PDp·ll/05
(5·1/4 inch)

Console Cable

BC08R·3

PDp·ll/05
(10·1/2 inch)

Console Cable

BC08R·4

PDp·ll/35
PDp·ll/35·11/4Q

Console to K 1 and K5 (2)
KEll·E
(M7238 to M7232) (3)

BC08R·3
BC08R·l

PDp·ll/4Q
PDP·l1/45

Console to K 1 and K5 (2)
Console Cable (2)

BC08R·6
70·8864

_ _ _ _ _ _ _ DECAID PWRB-5

OPTIONS

CPU Type
Optioo

11/05,11/10
10-112-10.
Box

11/35
10-1/2-10.
Box

11/35S, 11 /05S
BAll-KE/F
10-1/2-10.
Box

AA11-0A
AA11-0B
OAll-F
OBll-A
OC11-A
0011-A
0011-B
OH11-AA
OHll-AB
OHll-AC
OJll-AA
OJ11-AB
OJ11-AC
ON11-AA
OPll-0A
OR11-B
MF11-L
MF11-LP
MF11-U/UP
MMll-S
RHll
RHll-AB
RK11-0
VT11
COll-AiB/E
0011

70-9205
70-9205
70-9099
70-9205
70-9205
70-9205
70-9099
N/A
N/A
N/A
70-9099
70-9099
70-9099
70-9205
70-9205
70-9205
70-9206
N/A
N/A
70-9205
70-9099
70-9099
70-8992
70-9099
70-9099
70-9099

70-9205
70-9205
70-9099
70-9205
70-9205
70-9205
70-9099
N/A
N/A
N/A
70-9099
70-9099
70-9099
70-9205
70-9205
70-9205
70-9206
70-9206
N/A
70-9205
70-9099
70-9099
70-8992
70-9099
70-9099
70-9099

70-9562
70-9562
70-10117
70-9562
70-9562
70-9562
70-10117
70-10118
70-10118
70-10118
70-10117
70-10117
70-10117
70-9562
70-9562
70-9562
70-10114
70-10114
70-10115
70-9562
70-9570
70-10117
70-10116
70-10117
70-10117
70-10117

DECAID PWRB·6 _ _ _ _ _ __
OPTIONS

CPU Type
Option

11/46
(Old)

AAll·DA
AAll·DB
DAll·F
DBll·A
DCll-A
DD11-A

70·8855·1J
70·8855·1J
70·9162
70·8855·1J
70-8855-1J
70-8855

DD11·B
DHll·AA
DHll-AB
DHll-AC
DJ11-AA
DJ11-AB
DJ11-AC
DNll-AA
DPll-DA
DRll-B
MF11-L*
MFll-Lt
MFll-LP*
MF11-LPt
MFll-UlUP:j:
MMll-S
RHll
RH11-AB
RK11-D
VTl1
CDll-A/B/E
DOll

70-9162
N/A
N/A
N/A
70-9162
70-9162
70-9162
70·8855·1J
70-8855-1J
70-8855-1J
70·9242
N/A
70-9242
N/A
N/A
70-8855-2B
70-9162
70·9162
70·8855·1J
70-9162
70·9162
70·9162

t
:I:

11/40
H960D. E
(Old)" "

11/40.11/46
H960D/E
(New)

70·8909·XX
70·8909·XX
70·9099
70-8909·XX
70-8909·XX
70·9177
70·8909-XX
70·9099
70·9466
70·9466
70·9466
70·9099
70-9099
70·9099
70·8909-XX
70·8909-XX
70·8909-XX
70·9103
70-9174
70-9103
70-9174
N/A
70·8909·XX
70·9571
70·9099
70·8992
70-9099
70·9099
70·9099

70·9562
70·9562
70·9563
70-9562
70·9562
70-9562
70-9563
70-9561
70-9561
70-9561
70·9563
70-9563
70-9563
70-9562
70-9562
70-9562
70-9565
70-9560
70·9565
70·9560
70·9535
70-9562
70-9570
70·9563
70-9559
70·9563
70·9563
70·9563

PDP·11/40 only (1st MFll·LlLP).
PDp·11/40 only (2nd MF11·LlLP).
MF11·U/UP cannot be mounted in old style PDP·11/45 CPU box ..
70·8909·XX cable has two variations - 11 inches and 17 inches. Usa
70·9177 if due to new module guide layout; 70·89og·XX cables are too
short.

DECAID PWRB·6
PIN LOCATIONS FOR REGULATOR'S CONNECTORS

~
~~

871554321

••••••••

H744

H746

1. Spare
2. +5 V output (red)
3. GND (black)
4. GND (black)
5. +5 V output (red)
6. 20-30 Vac input (red)
7. 20-30 Vac input (white)
8. Spare

1. -1 5 V output (blue)
2. GND (black)
3. GND (black)
4. + 15 V input (violet or gray)
5. + 1 5 V input (violet or gray)
6. 20-30 Vac input (red)
7. Spare
8. 20-30 Vac input (white)

H754

H746

1. Spare
2. GNO (black)
3. -5 V output (brown)
4. Spare
5. +20 V output (orange)
6. Spare
7. 20-30 Vac input (red)
8. 20-30 Vac input (white)

1. Spare
2. GND
3. -5 V output
4. +19.7 V output
5. +23.2 V output
6. Spare
7. 20-30 Vac input
8. 20-30 Vac input

DECAID PWRB-7

PROCEDURE FOR REMOVAL OF REGULATORS
1. Turn the power off at the circuit breaker on the 860/861 Power
Controller.
2.

Disconnect the connector at the top of the regulator.

Remove the two Phillips screws on top of the regulator which
hold the regulator in the H742 box.

Loosen the finger-tight (usually) screw on the bottom of the
regulator.

5. Slide the regulator out horizontally away from the H742 box.
The following diagram shows the location of the fuse. Usually you
can check it without taking off the clear plastic cover. It is an AGC
15-amp fuse.

+5 V REGULATOR, SIDE VIEW

DECAID PWRB-B
H742 CONNECTORS FOR PDP-ll/40
As seen from the back, the connectors on the H742 Power Supply
are located as shown in the diagram below.

Pl0

The following pages list the functions and locations of each of the
pins on the abo,ve three connectors.
PDP-ll/40 Pin Locations for H742's Connectors

Pin(s)

Function
(Vac)

Color

Dest,

1-2 (new)

20-30

Red, white

Slot B

1-2 (old)

20-30

Red, white

SlotA

3-4

20-30

5-6

20-30

7-8

20-30

Red, white

Slot D

_ _ _ _ _ _ _ DECAID PWRB-8

PDP-11/40 Pin locations for H742's Connectors ICont)

Pin Is)

9 12

811

7 10

Function

Color

Dast.

+8V
2

+15V

Gray or
violet

Cist. Panel

+15V

Gray or
violet

Slot C

GNC

Black

Slot 0

GNO

Black

Slot E

GNC

Black

Cist. Panel

GNC

Black

Cist. Shield

AClO

Yellow or
red

Cist. Panel

CClO

AClO

LINE ClK

Brown or
black

Cist. Panel

CClO

Violet or
clear

Cist. Panel

DECAID PWRB-8
PDP-11140 Pin Locations for H742's Connectors (Conti

Pl0
3

912 15

811 14

710 13

Pin(s)

Function
(Vac)

Color

Dest.

1-2 (new)

20-30

Red. white

SlotA

1-2 (old)

20-30

Red. white

Slot B

8-10

20-30

Red. white

Siote

9-12

20-30

Red. white

Slot E

3-7

115

Red. white

H742 fan

5-6

115

Red. white

Proc. fans

DECAID PWRB-B
UPPER H742 CONNECTORS FOR PDP-11145
As seen from the back. the connectors on an upper H742 Power
Supply are located as shown in the diagram below.

P16

P15

P14

The following pages list the fUnctions and locations of each of the
pins on the above three connectors.

PDP-11/45 Pin Locations for Upper H742's Connectors

P16

Pin(s)

Function
(Vac)

1-2

20-30

3-4

20-30

5-6

20-30

7-8

20-30

Color

Dest.

Red. white

Slot B

Red. white

Slot C

DECAID PWRB-8
PDP-11/45 Pin Locations fOf Uppef H742's Connectors (Cont)
P14

Pin(s)

9 12

B 11

7 10

Function

Col Of

Dest.

+BV

White

Dist. Panel

2 (new)

+15V

Gray

Slot F

2 (old)

+15V

Gray

Slot E

+15V

Gray

Dist. Panel

GND

Black

Slot E

GND

Black

Dist. Panel

GND

Black

Slot F

GND

Black

Dist. Panel

AClO

Yellow

Dist. Panel

AClO

Yellow

Lower H742

9 (new)

DC lO

9 (old)
10

AClO

Yellow

Dist. Panel

AClO

Yellow

lower H742

LINE ClK

Brown

Expn.Dist.

DC lO

Violet

Dist. Panel

_ _ _ _ _ _ _ DeCAID PWRB-B
PDP-11!46 Pin Locations for Upper H742's Connectors (Cont)

P16
3

9 12 15,

811 14

7 10 13

Pin(s)

Function
(Vac)

Color

Dest.

1-2

20-30

Red. white

SlotA

8-10

20-30

Red. white

Slot 0

9-12

20-30

Red. white

SlotE

3-7

115

Red. white

H742 fan

5-6

115

Red. white

Time meter

OECAIO PWRB-8
LOWER H742 CONNECTORS FOR POP-11146
As seen from the back. the connectors on a lower H742 Power
Supply are located as shown in the diagram below.

P24

P23

P22

The following pages list the functions and locations of each of the
pins on the above three connectors.
POP-11/46 Pin Locations for Lower H742's Connectors

P24

8
7

Pinls)

Function
IVac)

Color

Oest.

1-2

20-30

Red. white

SlotJ

3-4

20-30

5-6

20-30

Red. white

SlotH
H746

7-8

20-30

Red. white

SlotH
H744

DECAID PWRB-8

PDP-11/46 Pin Locations for Lower H742's Connectors (Cont)

P22

9 12

811

7 10

Pin(s)

Function

Color

Dest.

GND

Black

Dist. Panel

-15V

Blue

Dist. Panel

GND

Black

Dist. Panel

AC LO

Yellow

Upper H742

DC LO

Violet

Dist. Panel

AC LO

Yellow

Upper H742

DC LO

Violet

Dist. Panel

DECAID PWRB-8

PDP-11/45 Pin Locations for Lowar H742's Connectors (Cont)

P23
3

9 12 15

811 14

7 10 13

Pin(s)

Function
(Vac)

Color

Dest.

1-2

20-30

Red. white

Slot L

8-10

20-30

Red. white

Slot K

9-12

20-30

Red. white

Slot F

5-6

115

Red. white

Proc. fans

3-7

115

Red. white

H742 fan

DECAID PWRB-9

PROCEDURE TO CHECK THE FUSE AND TO REMOVE THE
POWER CONTROL BOARD WITHIN THE H742 POWER
SUPPLY
CAUTION
You are working with 115 Vac. Be very
Sure to disconnect the H742 from the
power source and allow about 1 0 seconds
for the capacitors to discharge before
starting this procedure.
Lift off the H742's top and side cover (one piece) after removing the
two screws located at the front and rear of the power supply box.
Don't pull it away too far as the fan on the cover is conncted to a
terminal board in the box.
Check the fuses (5 amp and 114 amp) on the power control board.
The following diagram shows their locations.
If it is necessary to replace the power control board:
Loosen but do not remove· the two screws indicated in the
diagram.
Remove the screws indicated.
Disconnect the connector from the board.
Remove the other connector from the box.
Slide out the power control board .

• Do not remove these screws because it is very likely that in trying to put
them back in, you will drop them down into the H742 box.

NOTE
LOOSEN DO NOT REMOVE))!

~H~OU

J:
....

IN61~!~~:THIS
SCREW
LAMP FORWARD OUT OF

ITWILLBEEASIERT
PULL THE
H742 BOX,

"lI

1/4AMP FUSE
HERE or HERE

""en

__J

5 AMP FUSE

OOMO~o~

:E
m

fll

:Jl

....

III

DISCONNECT
CONNECTOR

REMOVE
CONNECTOR
FROM H742 BOX

:Jl

J Iffi ......

____...L_--1_L_______

C
m
0

"lI

:Jl
III

REMOVE

DECAIDPWRD

PDP-11/05/10 POWER CONNECTORS
See the next page for a diagram shown in the pin locations.

PDP-11/05/10 5-1/4-INCH BOX

Voltage

Tolerance

Allowabla
Ripple

+15V
+5V
-15 V

±5%
±5%
±5%

750mV
200mV
450mV

PDP-11/05-N, 11/10-N 10-1/2-INCH BOX

Voltage

Tolerance

Allowable
Ripple

Regulator

+15V
+5V
-15 V
+5V

±5%
±5%
±5%
±5%

500mV
200mV
450mV
200mV

5409728
5409728
5409728
H744

The two + 5 V outputs must not be shorted together. The 5409728
regulator provides +5 V to connectors Jl and J2 on the power
distribution board. The H744 provides +5 V to connectors J3, J4.
and J5. The CPU backplane is normally connected to J1.

PDP-11/05-S, 11/105

Voltage

Tolerance

+5V
+15V
+20V
-15 V
-5V

±5%
±10%
±5%
±5%
±5%

Allowable
Ripple

Wire
Color

Pin
Number

200mV

Red
Gray
Orange
Blue
Brown

1.4
2
3
13
14

100 mV
450mV
250mV

ADJUSTMENT POTENTIOMETERS

C
m

)10

c
."

::E

:II

CP·2004

DECAID REMOTE _ _ _ _ _ __

REMOTE POWER CONTROL FACILITY
All PDP-ll computers have provisions to allow the console switch
to control the operation of the cabinet mounted 860/861 Power
Controllers and H720 Power Supplies.
These devices should be connected together with the remote power
control bus which is a 3-wire system with the wires having the
functions shown below:

Q),.
o
o

REMOTE TURN ON ,REOJ

2. EMERGENCY SHUTDOWN (BLK)
3. SIGNAL RETURN (GRNI

POWER CONTROL OPERATION
Connections
Between
Control
lines

Local
Switched
Power Is

Switch Position
Remote
Off
Switched
Switched
Power Is
Power Is

None
1-3
2-3
1-3.2-3

On
On
Off
Off

Off
Off
Off
Off

Off
On
Off
Off

See DECAl D PWR 8-5 for a list of the remote sense cables used to
connect various power components.

DECAID START

SUGGESTIONS ON WHAT TO DO BEFORE ACTUAL
HARDWARE TROUBLESHOOTING
Before you go to the customer's site:
1. Find out as much about the system configuration as you can.
Which CPU
How much memory. what type
What mass storage devices. how many of each
What software
What other peripherals. how many of each
What communications equipment. etc.
2. Read the last few Field Service Reports for this system to
see if the problem is a recurring one or if it may be related to
some work that was done recently.
When you get to the customer's site:
1. Question (gently) the user to find out as much about the
failure as possible.
What was the system doing when it failed?
Was there any smoke. sparks. noises. etc.?
What software was running?
How many users were on the system?
Have there been any recent changes to the hardware or
software?
2. Check the obvious and simple possibilities first.
Power plugs not inserted properly
Cables hanging loose
Physical damage