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EK-DELUA-UG-002

April 1986

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Document:	DELUA User's Guide
Order Number:	EK-DELUA-UG
Revision:	002
Pages:	126
Original Filename:

OCR Text

EK-DELUA-UG-002

Networks - Communications

DELUA User’s Guide

Prepared by Educational Services

of
Digital Equipment Corporation

2nd Edition, April 1986

The information in this document is subject to change without notice and should not be
construed as a commitment by Digital Equipment Corporation. Digital Equipment
Corporation assumes no responsibility for any errors that may appear in this document.

Printed in U.S.A.

The following are trademarks of Digital Equipment Corporation:

PRanasg TM
DATATRIEVE
DEC

DECtape
DECUS
DELUA

Rainbow
RSTS
RSX

DECnet

MASSBUS

VAX

DECsystem-10
DECSYSTEM-20

P/OS
Professional

VT
Work Processor

DECmate

DECset

DIBOL

PDP

UNIBUS

VMS

CONTENTS
INTRODUCTION

Page

ETHERNET OVERVIEW ...ttt
errree e cssner e s sesnrne s

1-1

PHYSICAL DESCRIPTION ....ooiiiie ettt
escereerecsssnvae e s essnsreeses
DELUA SYSTEM OPERATION ...ttt
saabe e s sssaes
Physical Channel FUNCLIONS ...........cccvvvviviiiiiiiieeecireee
e easae
Data Link Layer FUNCHONS.........ccciiiiiiiiieiiicirier
ittt seccerreecceeneeseesssnavneesens
Data EncapSulation .........ccccccoiiiiiiiiiiiieiiiiciiinieeeesenniieseseeesesesssssnseessessssens
Data Decapsulation ........ccceiiieciiiiiiiiiiiee
e errereecerrreeecesansesesssareeessssssseeesensns
Link Management ............ooviiiiiiiiiiiiiiiieicccccniiiere
e sseieesseseeeeessssnsssssssesseessns
DIAGNOSTIC FEATURES .......oi oottt cttnecesreerecessnsesessssnanseessons
INTERNAL HARDWARE OVERVIEW .......iiitieeeecccninrreeeeee
e
MICTrOProCesSOr SUDSYSIEM .....cccvviviviiiciieeeiertieeeesreeeessrrrreesessnreeesssaesesesssnns
MemOry SUDSYStEM .....cccovviiiiiiiiiiiie
i scrrecnreeereesebeeeeeee e s saee e ssnssssasneens
LANCE SUDSYStEML...ccciiiiiiiiiciriie
et
sssree e ceesree s ssarsresessannaesessannnes
Direct Memory Access (DMA) Subsystem .........cooveeeeviveennineenniiennsinenensnees
Port Control and Status Register (PCSR) Subsystem .........c.cccccecevvvereernnneen.
SPECIFICATIONS . ...t revrreereenrreeeeenrraees
RELATED DOCUMENTS ..ottt
csereee s snnseeseessreeessssansesssnssenes

1-2
1-5
1-5
1-6
1-6
1-6
1-7
1-7
1-8
1-8
1-8
1-9
1-9
1-9
1-10
1-11

INSTALLATION
PREINSTALLATION CONSIDERATIONS.......teeeetteeerrerec
e ceeenneeeee

2-1

Backplane ReqUIrEMENLS.........ccocvvvieieieiiiiiiiriiieeeenineeneeecesssnsssssessssssssssssnee
Bus Latency CONStraints .........coccvvveeeeiiiiiiiiinireeeeensiiieereesesssssesseereessssssssssssses
Bus L0ading FacCtor.......c.voviiiiiiiiiiiiiiic
it
ccrre e esnnere s esssrrseesssnnseens
UNPACKING AND INSPECTION......ccottiireeeeecrrrcnrrccineeesvesessiseecsnee
e
PREINSTALLATION PREPARATION ...ttt ccerecnieeennireensreeenns
Backplane Preparations..........cccccceiovvieeeiiiiieeeeienreeeenseeeeeesisseecssssssesesssssnesessns

2-1
2-1
2-1
2-2
2-2
2-4

Device Address ASSIZNMENL........cccccivieiiiiiiiireeiiiierecciieecsiseeeesssrseeeeesssnsees
Boot Option Selection (PDP-11 Host Systems Only).......cccccceevvveeeiveeennnnn,
Loop Selftest Switch (for Manufacturing Use) ........ccocvvveevecrverenrcineerennnnn.
INSTALLATION ..ottt
nireeseesre s e e sensraeessssssaassssesbssssasessassesnssnaens
VERIFICATION CHECKS ...ttt ccrrecnrieecesvneseseneesssnne e seesssaessesnassens

2-4
2-5
2-7
2-7
2-9
2-11

Postinstallation Power ChecK..........cccviviiiiiiiiiiccieieeeecere
e sccvneecsevnne s
Light-Emitting Diode (LED) Checks......c.cccceviviuiriiiririicnrneieireneneessnneeessinnenes
DIAGNOSTIC ACCEPTANCE PROCEDURE..........ccoovtvertiercreecieeesiveennenes

2-12
2-12
2-12

Vector Address ASSIZNMENL ...........cooiveiiiiiiiiiieeeeeiiiiiireereeeeesessereesssssssssssseens

INTRODUCTION ......coiiiiiiiiiiiiiiiiiiiiinitciiienresessatsescsssesseessssssessssessessseons
PORT COMMAND EXECUTION .....ccccovirirririnnrennennnesessnessenssssssssessssssesssons
ANCILLARY FUNCTION EXECUTION........cccoviiimiinnirncinscnnennneissienessnenns

PROGRAMMING OVERVIEW

CHAPTER 3
W

N »—

—

w N —

CHAPTER 2
DD
ND DD DD

B
W
—

N AW
-

CHAPTER 1

3-1
3-1
3-1

CONTENTS (Cont)

3.9

DATA FRAME TRANSMISSION AND RECEPTION.......ccccoovvevrvviveennnnnenn,
3-2
FUNCTIONAL STATES ...ttt
siesssrteesstnscebaesssaeessee s nns
3-3
POWERUP AND RESET ...ttt
csrreeesiessesssreeessssesossasaessnns
3-8
STOP AND RESTART...ttt
e
sseniesesestseesssaassssssasssssnnessans
3-9
ANCILLARY FUNCTIONS THAT INTERFERE WITH MESSAGE
PROCESSING .....ooociiecireeeeecrte
e srtreenreeeeses s bessensseesssesssssesssessssbesssnnees
3-9
SUMMARY OF COMMANDS ...ttt
sneseessets e seresessseessveesasns 3-11

CHAPTER 4

REGISTERS AND COMMANDS

4.1

PORT CONTROL AND STATUS REGISTER 0 (PCSRO).......ccccoovevvirerreennnn.

4-1

4.2
4.3
4.4
4.5
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
4.5.6
4.5.7
4.5.8
4.5.9
4.5.10
4.5.11
4.5.12
4.5.13
4.6
4.7
4.8
4.9

PORT CONTROL AND STATUS REGISTER 1 (PCSR1).....ccovvvvvvererierenens

4-5

PORT CONTROL AND STATUS REGISTER 2 (PCSR2).......ccccccevvvrnvrrnnnnn.
PORT CONTROL AND STATUS REGISTER 3 (PCSR3).....ccccocvvvvvvrvrvrinennns
PORT CONTROL BLOCK FUNCTIONS.........ovteereiectenntee
e eveens
No-Operation, Ancillary Function Code O.........ccccevvevvvviiniviiniineeniieene,
Start Microaddress, Ancillary Function Code 1........ccccovvvevriieecirencirinnnnnne.
Read Default Physical Address, Ancillary Function Code 2........................
No-Operation, Ancillary Function Code 3 .......ccccoovvirvimriiiinernceeneenerenene
Read/Write Physical Address, Ancillary Function Codes 4/5.....................
Read/Write Multicast Address List, Ancillary Function Codes 6/7 ...........
Read/Write Descriptor Ring Format, Ancillary Function Codes 10/11 .....
Read/Read and Clear Counters, Ancillary Function Codes 12/13..............
Read/Write Mode Register, Ancillary Function Codes 14/15 ....................
Read/Read and Clear Status, Ancillary Function Codes 16/17..................
Dump/Load Internal Memory, Ancillary Function Codes 20/21 ................
Read/Write System ID Parameters, Ancillary Function Codes 22/23........
Read/Write Load Server Address, Ancillary Function Codes 24/25 ..........
TRANSMIT DESCRIPTOR RING ENTRY....cccceovviniiniriniicrrinresreenneesree
RECEIVE DESCRIPTOR RING ENTRY ....ccoocioiiiiiiineinretecrecriseeseneseenens
TRANSMIT DATA BUFFER FORMAT ........cooccoiiiniiiiircecrineeseeceeeresneesneas
RECEIVE DATA BUFFER FORMAT ..ottt

4-7
4-7
4-7
4-8
4-9
4-10
4-10
4-11
4-11
4-13
4-15
4-22
4-24
4-26
4-28
4-34
4-34
4-37
4-40
4-42

CHAPTER §

MAINTENANCE OPERATIONS

LU NLLLULLLL U LWL

Page

REMOTE BOOT AND DOWN-LINE LOAD......cccccoovitintinieeeeeereeeeeeeeesesnns
5-1
Remote Boot Disabled............oovveiiiiiniiiiiiicieccecceee
st
eee e s s
5-1
Remote Boot from System Boot ROM .......ccocoovviiiiiieiiiienieeeeeeeeeeeeeeennns
5-1
Remote Boot and System Load..........cccoveiiriiiiiiiiiieeciceeeeeeeee
e
5-2
Remote Boot 0n POWEIUP ......cccueeieieeiieieceictictecct
et
s
5-4
BOOT Port Command...........cccovvivviiiiniiiiicririeieseesreeseese
st eeree e sevesesesees
5-4
BOOT FRAME FORMAT ........cooiiiiiieitie
ettt st eee s seesaeeesasenase
cce
e ens
5-5
REQUEST PROGRAM FRAME FORMAT .....ccccoocvvevevvecveeeannn.e
eerr e
5-7
MEMORY LOAD WITH TRANSFER ADDRESS FRAME FORMAT......... 5-10
INTERNAL AND EXTERNAL LOOPBACK MODE .......ccccouvvveeeeereeneannnn, 5-11
CHANNEL LOOPBACK ...ttt
esteseee e esneesasasesaneeens 5-12
LOOPBACK FRAME FORMAT ..ottt
eae e s e 5-13
REQUEST ID FRAME.......oooiii
ettt
iiiccee
e s e sena s 5-14
SYSTEM ID FRAME FORMAT .....coo
ettt
oiiieeee
eeveeae s e seesere e 5-16
MICROCODE LOADING .......cccoieieiiiteceieeiteecte
et eeeeeeaeaeeeseeesseetesnn
stest 5-18
MICROCODE UPDATE PROCESS .........oooiitieeiiteeteeteee
eeeeeeeeceeeseeesene e 5-19

——
—-— O

000

QNN BRI

Nh
WL —

3.4
3.5
3.6
37
3.8

CONTENTS (Cont)
CHAPTER 6

SERVICE

Page

MAINTENANCE PHILOSOPHY ...ooiiiiiiitiee
ettt csessvivevee s s s sssssennas
TROUBLESHOOTING PROCEDURE.........ivtiiiiiiiiiieiiiiiciieeneeeeeineeeeeeeees
SO St ittt
e e e e e e et e e e
e s e eaasreaares
DELUA VAX On-Line Functional Diagnostic (EVDYB¥*).........ccccuvvveeee.n.
DELUA PDP-11 Functional Diagnostic (CZUAD*).......ccccccovvvviinvrrvinnnnnnn.
DEC/X11 DELUA Test CXUAD ...ttt
NI Exerciser CZUAC*/EVDWOCH . oiiiieeetettetvseveeeeeeeeseeeees
APPENDIX A

6-1
6-1
6-1
6-5
6-6
6-8
6-8

FLOATING DEVICE ADDRESSES AND VECTORS

FLOATING DEVICE ADDRESSES AND VECTOR ADDRESSES...............
FLOATING DEVICE ADDRESSES ...t
ccerinereeee e
FLOATING VECTOR ADDRESSES.........ii e
DEVICE AND VECTOR ADDRESS ASSIGNMENT EXAMPLE .................

A-1
A-2
A-3
A-4

FIGURES

Page

DELUA Component PartS........ccccccoeiiiiiiiiiiiiiiiiiiiieec
et eeeevnree e e e e e s

Large-Scale Ethernet Configuration.............cocoviiviiiiiiiiiiiiiiiee

1-3
1-4

DELUA-to-LAN Block Diagram........cc.cccccciiiiiiiiiiiiiiicccciieeee
e cecirerree e e

1-5

1-6

DELUA Block DIagram .........ccccccoiiiiiiiiiiiicce
e
cesntrenr e essaiaaae e

1-8

DELUA Component PartS.........cccccvviiiiiiiiiiiiieeeesiiieeceririeeessiieeeseessveeessssnnessesnnns
Switch Pack at E106, Device Address ASSIZNMENt .........ccvvvvvieiiviiiiinininneeerinnnnnee.
Device Address and SwitCh POSItIONS..........cocovvvviiiiiiiiiiiriiec it
Switch Pack at E69, Vector Address Assignment...........cccceeeeevviiieeerncnineeeeennvneenn.
Vector Address and Switch PoSItiONs.............ccoovvuvviviiiiviiiiiiee
e
Boot Function SWitChes .........c..ooviiiiiiiiiiere
e
Loop Selftest SWitCh Setting .......cccccovivivieiiiiiiiiie
e
svee e e

2-3

DELUA Installation Procedure...........cccoiviviiiiiiiiiiiiiiieccceiree
s
ee e s s
Loopback TransCeIVET SELUP .......cccccveiiiiiiiriiieeeiiieeeecrie
e ceitreeeeesareeeecssrareeeeenarreesenns
DELUA LEDS...ciiiiiiiiiiiiie ettt
eesetisbae s e e s essanasnasseesssssannes
Bulkhead LED ..ot
ceeirere e cessrnre s e es e

2-9
2-11
2-13
2-13

DELUA PCSRs and Host Memory Data Structures..........ccccceeevveenveveeeeiinninnnee.

3-2

Port Control and Status Register 0 (PCSRO) Bit Format........ccooeevvivveeeiiiiinnnnene.
4-1
Port Control and Status Register 1 (PCSR
1) Bit Format...........ccoeevvvvvevirirennnnnee.
4-5
Port Control and Status Register 2 (PCSR2) Bit Format.........ccccccoevvvriinninnnennnns
4-7
Port Control and Status Register 3 (PCSR3) Bit Format.......ccccoovvveevviveveevennennnn.
4-7
Port Control Block (PCB) Bit FOrmat ............cvvviiieiiiiiiiiiiieciirieeeeeeeeeeeneeessseseens
4-8
No-Operation, Ancillary Function Code 0 Bit Format.........c.cccccccovvvvvereeivniinnnnen.
4-8
Start Microaddress, Ancillary Function Code 1 Bit Format...........ccccovvvreerennnnnn.
4-9
Read Default Physical Address, Ancillary Function Code 2 Bit Format............. 4-10
Read/Write Physical Address, Ancillary Function Codes 4/5 Bit Format.......... 4-11
Read/Write Multicast Address List, Ancillary Function
Codes 6/7 Bit FOrmMat .......ooooivivviviriiiriiirrcisseieiseneeesseseeeesseesteneesreseeseseses 4-12

D 00 ~JON W

—

——

—_— O

O 00

INW

—

NN
NN

—
o

Format of @ Data Frame..........cccccoovoiiiiiiiiiee

Title

e
i O N N N

]
[}
[}
[]
bW N

Figure No.

2-4
2-5
2-6
2-6
2-8
2-8

FIGURES (Cont)
Figure No.

Title

4-11
4-12

Multicast Address List UDB Bit FOrMat...........ccoeveveeemeeeeereeeeeeeeoeeeeoeeoeeoeosesenos 4-13
Read/Write Descriptor Ring Format, Ancillary Function
Codes 10/11 Bit FOIMAL ........covviviuiiieiiet
ee
eeeeeeeeee 4-13
Read/Write Descriptor Ring Format UDB Bit Format............o.oveovemoooomoonnn., 4-14
Read/Read and Clear Counters, Ancillary Function Codes 12/13 Bit Format... 4-16
Read/Read and Clear Counters UDB Bit FOrmat ............o.oovveoeomoooeooooeooono 4-17
Read/Write Mode Register, Ancillary Function Codes 14/15 Bit Format..........
4-22
Read/Read and Clear Status, Ancillary Function Codes 16/17 Bit Format .......
4-24
Dump/Load Internal Memory, Ancillary Function Codes 20/21 Bit Format .....
4-26
Dump/Load Internal Memory UDB Bit FOrmat.............oououoeoeoeeeoeooeooooomoonn 4-27
Read/Write System ID Parameters, Ancillary Function
Codes 22/23 Bit FOrMAL ..........covivvieeeieeereeeeeeeeeee oot 4-29
Read/Write System ID Parameters UDB Bit Format ...........ooovvoeoooooooooon,
4-30
Read/Write Load Server Address, Ancillary Function
Codes 24/25 Bit FOIMAL ......cc.oocuvuiiineieceeeeecereeeeeesesesesese et 4-34
Format of an Entry in the Transmit Descriptor Ring..........ocooevevevveveveeveonn
o. 4-35
Format of an Entry in the Receive DeScriptor Ring.........coocevevevvvevevevevoiens
4-38
Transmit Data Buffer Starting on an Even-Byte Boundary.........ccoovvveevrerennnn,
4-40
Transmit Data Buffer Starting on an Odd-Byte Boundary ..........cccoovvvvveeiennennn.
4-41
Receive Data Buffer FOrMat............ccovviveveeeeeeeeeeereeceee oot
4-42

4-13

4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21

4-22
4-23
4-24
4-25

4-26

WO
D WN —
N —

Troubleshooting FIOWCRArt .............oucuiviuiveeeeeeeeeeee oo
Selftest and Status LEDS ............coovuviee
oo
ueveree
e
eeeeeeee

6-2
6-4

UNIBUS Address Map ...........coouviiuireinieeeeeeeeeeeesesieceesesee oo

A-1

A
s

BoOt Frame FOrMAat........coocuiuii
oo e
eiiiiiicceeee
5-5
Request Program Frame FOrmat .........c.ouvveveeiomeeeemoreeeeeceeeeeeeeeeeeeeeeseeoeeoon
5-7
Memory Load with Transfer Address Frame FOrmat..........o.ovovevemomomoooooonn
5-10
Loopback Frame FOrmat.........c.ccciuiuiiiiiieeeeee
oo
eeeeeeeee
oo
eeeseeeee 5-13
Request ID Frame FOrmat............ovuvveueeeeeeeeeseeeeeeeeeeeeeeeee oo
5-15
System ID Frame FOrmMat ..........couvvevueueeeeeeeeeeeeere oo 5-16
Microcode Patch File FOIMAat .........covvvveereeeeveeenierereeeeeeeeeeoeeeoeeeeeeeeeeeeees
e 5-19
Patch File Data Block FOrmat ..........cooeeueveuemeeeeeeeeeeeeeeeeoeeeeeeeeoeeoeooo
ee 5-20

4-27

Page

TABLES
Table No.

Title

Page

I-1

DELUA SpPeCifiCations .........ccccvereriiuriersrieeeenisiiieeiniinerissisneecsssnssessssnsssnsmssesssssaes
Related Documents...........cccoevvnvviencenenns teeersrereseereeeeerrrraeeeeeesssssnnetessesssiasataeiesseres

1-10
1-11

PR ELLY

FUNCLIONAL SEALES ...vvviiiviii ittt eerre e s erteseetreeessasssseasssasassssnassssnrsssssesssrenes
3-3
Functional State Transition SUIMMATY ........cceeiiiriirnreeeerirrrreereeesierssssnssssssssssanessssns
3-5
State Information Retention SUMMATY......c..covviniiriirinnnnrisisninnneeresiieeemm.
3-7
Ancillary Functions that Interfere with Message Processing...........ccoocevvuieiiinnennns 3-10
DELUA Port Commands..........covviereeeieeirinneeercesssssnnnsssssssssnsssssssssancessssssnsesssssssanes
DELUA ANCIllary FUNCLIONS ......ccccvivieiiiiriniieeieeiniecneieeresssnasnssssnenessssnecssssnssenns
DELUA Maintenance FUNCLONS.........ccoovvviiiiiieiivereeeneninnneesiicsnneieccsnnneeseessnane

3-11
3-11
3-12

Port Control and Status Register 0 (PCSRO) Bit DescCriptions.....c..cocoeeeeeurerrnne
Port Control and Status Register 1 (PCSR1) Bit Descriptions.........ccccccvvuveeinneee
Port Control and Status Register 2 (PCSR2) Bit Descriptions..........ccccceevueeernnee.
Port Control and Status Register 3 (PCSR3) Bit Descriptions.........cccccocrveerrnnnnne
Port Control Block (PCB) Bit DeSCrIPtions .........cccccveeeeeririececssrrrenreseassereessessonsnns
No-Operation, Ancillary Function Code 0 Bit Description .......c.ccccoeeveiirivueeennnnee.
Start Microaddress, Ancillary Function Code 1 Bit Descriptions...........cccoeuueeeen.
Read Default Physical Address, Ancillary Function Code 2 Bit Description.......
Read/Write Physical Address, Ancillary Function ............cccooviiiiiiiiiiiinniinninnnnnn,
Read/Write Multicast Address List, Ancillary Function
Codes 6/7 Bit DESCrIPLIONS.......cccccvuieeriivrerrerreersssieeiornesssinnsisssseesssssansessssaessssns
Read/Write Descriptor Ring Format, Ancillary Function
Codes 10/11 Bit DeSCIIPLONS........cecveeiirerireerireeerierssieessssessseesssneessseessssnssnne
Read/Write Descriptor Ring Format UDB Bit Descriptions............cccoocceiinuennnnen.
Read/Read and Clear Counters, Ancillary Function
Codes 12/13 Bit DesCriptions..........ccccvveereererrnineneinnniensiniesscsssssisssessssserssssnns
Read/Read and Clear Counters UDB Bit Descriptions .........c.ccocvveceviivinnnereennnnns
Read/Write Mode Register, Ancillary Function
Codes 14/15 Bit DeSCriPLiONS. .......cccvvvieeiieriieeeeererrreeereecsseeeeessssssstessosssnesesessnes
Read/Read and Clear Status, Ancillary Function
Codes 16/17 Bit DeSCIIPLIONS. ......c.ccvuiieiiereirireeressnrrreeesssisteessssssesessssssnsessessns

4-1
4-6
4-7
4-7
4-8
4-9
4-9
4-10
4-11

—
o

O 00

—

~N AN

—

S WHN—

Nt?)NN

DELUA Power CONnSUMPLION.........cuuuierrereeeeceeeeiiiniiiiiinnimmmssssmsmissmseeesessesssssssmnnne
2-2
Boot Function Switches (PDP-11 Only)......cccoovveriiiiiiiiiniiiiinnneiinnenennineneenne.
2-7
DELUA PoWer ChecCK.....o.oooiiiiiiiiiieecieriercccccsreeeeseecssssnnneessssssssssennesssssssssanaessees 2-12
DELUA DiagnoStiCS ......uveeeiiiiirreereiieerirereresseseressnsessessssssssnessesssssssrssssssssssssassasanees 2-12

PPEPP
&A&A?A&h&b

1-2

4-11

4-15

4-16
4-17

Dump/Load Internal Memory, Ancillary Function
Codes 20/21 Bit DeSCIIPIONS. .....cccivviiiiieiriiiirieerecesinreresesesaereesssssneesssossannissess
Dump/Load Internal Memory UDB Bit Descriptions............cccccvvviiivinninieiniinnnns
Read/Write System ID Parameters, Ancillary Function
Codes 22/23 Bit Descriptions........ Nererreeeeereeierranrrrateeteettaeasrraaraeaeeeaaesenrnenarrnaeas
Read/Write System ID Parameters UDB Bit Format ..........cccoonvviviiinnnniininnne,
Read/Write Load Server Address, Ancillary Function
Codes 24/25 Bit DeSCIIPLIONS.........cccccuviiiiieieeiierirneirnrerecesssesssoniinnerseesesssssnsnns

4-12
4-14
4-15
4-16
4-18

4-22
4-25
4-27
4-28
4-29
4-31

4-34
Bit Descriptions of a Transmit Descriptor Ring Entry......cccococvvvvinnnnnin. 4-35
Bit Descriptions of a Receive Descriptor Ring Entry........ccccccceviiivininnnnininnn 4-38

Vil

TABLES (Cont)
Title

Page

Boot Frame DESCriPtioN..........cccovriiiieieicieieectc ettt
se n e
Request Program Frame DesCription..........cc.c.c.cveviiiniiriiinneceesiseseeseenessessesaes
Memory Load with Transfer Address Frame Description..........co.ccveveeevveeverennnnn.
Loopback Frame DeSCription ...........cccovveiieiiiiiiiiiciiccetcretseeceeee
eee e sessenas
Request ID Frame DesCription...........cccucivouieiiriiiiiiiieecieeiereteeeeseeseseseesessssesssnes
System ID Frame DeSCriPtion............ccooiiviiiiiviieeeeeeeeeeeeeeeeeeeeesesesseesssesssseessesesenes

5-6
5-8
5-11
5-14
5-15
5-17

Selftest Error and Status Codes...........covvvvvriivieeiinieeieeereieeeee
e eeee e eereseseess e,
DELUA VAX On-Line Functional Diagnostic (EVDYB*) Test Summary .........
DELUA PDP-11 Functional Diagnostic (CZUAD*) Test Summary...................

6-6
6-7

Floating Device Address Ranking SEqQUENCE.........cooveueeeveeveeeeeeeeereeeeeeeeeeresseesaen,

Floating Vector Assignment SEQUENCE.............ccvvveeeeereeeeeeeeeereeeeeeeeereieeseesesessesons
Device and Vector Address ASSIZNMENLS............ccovevvereeeeeeeeeeeeeeeeereereressesseesessons

viii

6-4

A-2
A-3
A-5

CHAPTER 1
INTRODUCTION

The DIGITAL Ethernet large-scale-integration UNIBUS adapter (DELUA) is an Ethernet communica-

tions controller option for VAX and PDP-11 computers.
The DELUA adapter is a follow-on product to the DIGITAL Ethernet UNIBUS network adapter
(DEUNA). The DELUA option performs all the same functions as the DEUNA option, but it offers
higher performance and lower power consumption.

NOTE
For ease of use and reader comprehension, the
DELUA adapter will be referred to as the DELUA
throughout the document. Similarly, the DEUNA

adapter will be referred to as the DEUNA and the
UNIBUS bus as the UNIBUS.

1.1
ETHERNET OVERVIEW
The Ethernet is a local area network (LAN) that provides high-speed data transfer among computers and
other digital devices within a moderately sized geographic area. It is intended for devices requiring brief
bursts of high-speed data transfers, such as terminal access, distributed processing, and office automation.
The primary characteristics of Ethernet include:

Topology - branching bus.
Medium - shielded coaxial cable, Manchester-encoded digital baseband signaling.
Data Rate — 10 million bits per second (maximum).
Maximum Separation of Nodes - 2.8 kilometers (1.7 miles) on one LAN; several LANSs can be
connected with LAN Bridge 100 devices to form an extended LAN.
Maximum Number of Nodes — 1,024 nodes on one LAN; several LANSs can be connected with
LAN Bridge 100 devices to form an extended LAN.

Network Control — multiaccess, fair distribution to all nodes.
Access Control - carrier sense, multiple access with collision detect (CSMA /CD).

Frame Length - 64 to 1518 bytes, including a data field from 46 to 1500 bytes.

The Ethernet is a medium-sized network. It is smaller than long-distance, low-speed networks that carry
data for hundreds or thousands of kilometers and it is larger than specialized high-speed interconnections
that are generally limited to tens of meters.

1-1

An example of a large-scale Ethernet configurations is shown in Figure 1-1. When configuring an Ethernet
local area network you must observe the following rules:
I.

A segment of coaxial cable can be a maximum of 500 meters (1640 feet) long. Each segment

must be terminated at both ends with the characteristic impedance.

Up to 100 nodes can be connected to any segment of the cable. Nodes on a cable segment must
be spaced at least 2.5 meters (8.2 feet) apart.

The maximum length of the transceiver cable between a transceiver and a controller, such as

the DELUA, is 50 meters (164 feet). In the case of the DELUA, the internal cabling between
the DELUA and its bulkhead assembly accounts for 10 meters (33 feet). The DELUA,

therefore, can support up to 40 meters (131 feet) of transceiver cable.
4.

The maximum length of coaxial cable between any two nodes in a single LAN is 1500 meters
(4922 feet). However, the length of cable between two nodes can be greater if part of the
cable
is fiber-optic cable connected by repeaters. Also, this 1500-meter length limitation does
not
apply to nodes on different LANSs of an extended LAN connected by LAN Bridge 100
devices.

A LAN can be extended by connecting two segments with repeaters and a length of fiber-optic
cable. A fiber-optic cable connected to a repeater can be up to 1000 meters (3280 feet)
long.

A maximum of two repeaters can be placed between any two nodes on the same LAN.

LAN Bridge 100 devices can be used to connect LANS to form an extended
LAN. There

is no

limit to the number of LANs that can be connected using LAN Bridge 100 devices,
but
performance may be poor if a message must travel through more than seven bridges before
reaching its destination node.
8.

LAN Bridge 100 devices can be connected using a fiber-optic cable. The maximum length
of
such a cable depends on the type of cable and the number of splices and connectors, but
it can
extend as far as 2000 meters (6560 feet).

1.2 PHYSICAL DESCRIPTION
The DELUA is illustrated in Figure 1-2. The DELUA consists of:
e
)

M7521 hex-height module
UNIBUS Network Adapter (UNA) bulkhead assembly
UNA bulkhead cable assembly

The DELUA kit for non-FCC-compliant cabinets (CK-DELUA-KI) also contains
a bulkhead frame
(74-27292-01).
The UNA bulkhead assembly is connected to the transceiver on the LAN’s coaxial
cable with a transceiver cable.

DELUA controls and indicators consist of two dual in-line package (DIP) switches
and eight light-emitting
diodes (LEDs) mounted on the M7521 module, plus an LED on the UNA bulkhead
assembly. The
switches are used to select DELUA operating parameters and are set before installing
the module. The
LED:s display DELUA selftest error and status information. The function of these switches
and indicators
is described in Chapter 2.

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M75621

BULKHEAD

CABLE

ASSEMBLY

—

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MODULE

BULKHEAD
FRAME

(FOR USE

WITH NON-FCCCOMPLIANT

CABINETS)

MKV85-1838

Figure 1-2

DELUA Component Parts

DELUA SYSTEM OPERATION

1.3

The DELUA controller performs both the data link layer functions and a portion of the physical channel
functions. It also provides the following network maintainability functions:
Loops back maintenance messages from other nodes
Periodically transmits system identification

e
e

Loads and boots its host operating system (PDP-11 only) from another node on the network

The DELUA provides all of the logic necessary to connect VAX and PDP-11 computers to a local area
network (Figure 1-3). The DELUA performs data encapsulation and decapsulation, data link management, and all channel access functions to ensure maximum throughput with minimum host processor
intervention.

BULKHEAD

CABLE

T
TRANSCEIVER

CABLE

DELUA

UNIBUS

M7521

<:> MODULE

UNA

TRANSCEIVER

BULKHEAD
ASSEMBLY

MKV85.0320

Figure 1-3

1.3.1

DELUA-to-LAN Block Diagram

Physical Channel Functions

The DELUA provides the following specific physical channel functions to interface with the transceiver:
During Transmission

Generates the 64-bit preamble for synchronization
Provides parallel-to-serial conversion of the frame
Generates the Manchester encoding of data

Ensures proper channel access by monitoring the presence of another station’s transmission
Monitors the selftest collision detect signal from the transceiver

During Reception

Senses for presence of a carrier from another station
Performs Manchester decoding of the incoming data stream

Synchronizes itself to the preamble and removes the preamble before processing
Provides serial-to-parallel conversion of the frame
Buffers received frames

1.3.2 Data Link Layer Functions
The DELUA provides the following data link layer functions:

Calculates the 32-bit cyclic redundancy check (CRC) value and sends
Attempts retransmission upon detecting a collision

it with the frame

Checks incoming frames for the proper CRC value

Accepts only frames with specified destination addresses

1.3.3 Data Encapsulation
The frame format is shown in Figure 1-4. Each frame begins with
a 64-bit preamble that allows the
receiving node to synchronize exactly to the data rate. Frames are
separated by at least 9.6 us to allow
another node the opportunity to send a message.

DESTI-

PREAMBLE | NaTION [ SOURCE |

Tvee

ADDRESS

FRAME

DATA

CHECK

SEQUENCE

INTERFRAME |
|

_____[

8 BYTES

6 BYTES

2BYTES

46 TO 1500 BYTES

4 BYTES

9.6 us
MKV85-0326

Figure 1-4

Format of a Data Frame

The destination address field contains the address of the node to which
the frame is being sent. This
address may be the address of a particular node, a multicast address associate
d with a group of nodes, or a
broadcast address for all nodes on the network.
The source address field specifies the physical address of the
transmitting node. Each DELUA has a
unique 48-bit physical address built in during manufacture. The
system software can override this value
and assign a different physical address.
The type field is used by high-level network protocols. It indicates
The data field may have between 46 and

how the data field is to be interpreted.

1500 bytes of data. The DELUA can be initialized to

automatically insert null characters, if the amount of data

is less than the minimum 46-byte data size.

The frame check sequence field contains a 32-bit CRC value,
which is determined and inserted by the
DELUA during transmission.
1.3.4 Data Decapsulation
The DELUA continuously monitors the signals received
by its transceiver. After sensing a carrier, the
DELUA uses the preamble sequence of the frame to synchro
nize itself to the data rate of the frame. The
DELUA then processes the destination address field through
a hardware comparator to determine whether
the incoming frame is intended for its node. The DELUA
accepts only frames that have a destination
address matching one of the following types of addresses:

The physical address of the node
The broadcast address for all nodes
One of the ten multicast group addresses that the user may assign
to the DELUA, when desired
Any multicast address, when desired
All addresses, when desired

The DELUA performs a hardware comparison of the 6-byte destination address to determine if thereis a
match with the node’s physical address or one of the user-designated multicast addresses. If the user
desires to receive more than ten multicast address groups, then all multicast addresses can be passed to
higher-level software for discrimination.

To assist in network management functions and to aid in fault diagnosis, the DELUA may operate in a
mode that disregards the address field, thus accepting all frames received from the network. The DELUA
verifies the integrity of the received data by recalculating the 32-bit CRC value and comparing it to the
CRC obtained from the received frame.
1.3.5

Link Management

The method used for channel access is called carrier-sense, multiple-access with collision-detection
(CSMA /CD). The DELUA controls all of the link management functions necessary to send or receive a
frame of data. These functions include:

Carrier Deference - The DELUA monitors the physical channel for traffic. If the channel is

Collision Detection - Collisions occur when two or more controllers attempt to transmit data
simultaneously on the channel. The DELUA monitors the collision sense signal generated by a
transceiver to detect a collision. When it detects a collision, it continues to transmit for a period

busy, the DELUA waits until it is not busy before sending a frame.

of time to ensure that all other nodes detect the collision.

1.4

Collision Backoff and Retransmission — When a controller attempts a transmission and
encounters a collision on the channel, it attempts a retransmission a short time later. The
schedule for retransmission is determined by a controlled randomization process called truncated binary exponential back-off. The DELUA attempts to transmit a total of 16 times (15
times plus the original transmission). If it fails after these 16 tries, it will report an error.

DIAGNOSTIC FEATURES

Microdiagnostics, system, and network diagnostics are used to minimize the time required to isolate and
diagnose a network communication fault. Built-in selftest microdiagnostics automatically test the DELUA
component logic during powerup. These selftest diagnostics report errors by means of LEDs on the edge of
the module.

To eliminate the possibility that the DELUA may monopolize the network after certain logic failures, the
DELUA has a special circuit that limits the frame transmit period.

The DELUA monitors the transceiver’s collision test signal after every frame transmission to verify that
the collision sense circuitry is working properly.

At the request of another node, the DELUA sends a loopback message to the node specified by the
requesting node. This feature allows physical connections between nodes to be verified.

The DELUA detects and tabulates network statistics and error conditions for use by higher-level network
management applications.

1-7

1.5 INTERNAL HARDWARE OVERVIEW
.
The DELUA is a microprocessor device based on the Motorola 68000TM microprocessor. The internal
hardware of the DELUA is divided into the following major subsystems also shown in Figure 1-5.
Microprocessor

Memory
Local Area Network Controller for Ethernet (LANCE)
Direct Memory Access (DMA)
Port Control and Status Registers

MICROPROCESSOR

SUBSYSTEM

l
1

PORT

CONTROL

‘

l 2

—

AND STATUS
REGISTERS

SUBSYSTEM

I ?

[¥2]

LANCE

SUBSYSTEM

TO NETWORK

TRANSCEIVER

&
<

MEMORY

SUBSYSTEM

128KB RAM

16KB ROM

DMA

SUBSYSTEM

.|
MKVBS-1039

Figure 1-5

DELUA Block Diagram

1.5.1
Microprocessor Subsystem
The Motorola 68000 microprocessor has a 400 ns cycle time and supports auto-vectored interrupts.
Each
of the internal subsystems has its own interrupt vector address. The microprocessor also resolves internal
bus (IBUS) arbitration conflicts when two or more internal subsystems try to use the IBUS simultaneousl
y.
1.5.2 Memory Subsystem
The internal memory is made up of 128K bytes of random access memory (RAM) used
for data buffering
and microcode execution, and 16K bytes of ROM containing the microcode. There is also
an 8-byte ROM
containing the Ethernet physical address assigned to the DELUA during manufacturi
ng.

During powerup the DELUA copies its microcode from ROM to RAM because the memory
cycle time of
RAM is faster.

Motorola 68000 is a trademark of Motorola, Inc.

The memory control and status register provides the microprocessor with status information on memory
errors and allows the microprocessor to remap memory at powerup. This register also allows the
microprocessor to disable parity checking and force parity errors for microdiagnostic purposes. Normally,
the left byte of cach word has even parity and the right byte has odd parity. Thus, a failure that produces
data of all ones or all zeros will produce a parity error.

The system timer circuit causes a 300 ns memory refresh cycle every 8 us.
1.5.3

LANCE Subsystem

The LANCE itself is also a microprocessor-controlled device. When the DELUA is initialized, the
DELUA microprocessor provides the LANCE with receive data buffers in DELUA internal memory. The
LANCE watches message traffic on the network and checks the destination address of each frame. If the
address matches the DELUA physical address, a multicast address, or the broadcast address, the LANCE
writes the frame into one of the receive data buffers and interrupts the microprocessor. The LANCE
checks the CRC field of the frame and reports any errors to the microprocessor.

When the microprocessor has a frame to send on the network, it writes an entry in the LANCE transmit

descriptor ring in DELUA memory and then sets the transmit demand bit in the LANCE control and
status register 0. The LANCE waits until there is a pause in the message traffic on the network and then
sends the frame. The LANCE adds the preamble and CRC fields to the frame as it sends it. If the frame

collides with a frame from another node, the LANCE waits and then tries again (up to 16 tries). After
sending the frame, the LANCE writes status into the transmit descriptor ring entry in DELUA memory
and interrupts the microprocessor.

The LANCE mode register provides a number of special features for diagnostic testing. The LANCE can
loop data frames inside the LANCE subsystem or out onto the network cable and back. It can force a
collision to test the collision detection circuitry. It can also disable the CRC generation circuitry. This
allows a diagnostic test to send frames with correct and incorrect CRC fields to test the LANCE CRC
detection circuitry.

1.5.4

Direct Memory Access (DMA) Subsystem

The DMA subsystem transfers data between DELUA memory and host memory. The DMA subsystem
comprises a word mover and a block mover. The word mover transfers one word from host memory to
DELUA memory, or from DELUA memory to host memory. The block mover transfers a block of
contiguous words. The word mover and the block mover can operate simultaneously.
The microprocessor uses the word mover to read ancillary functions, addresses, and pointers from host
memory and to write status words into host memory. It uses the block mover to write frames it has
received on the network into host memory and to read frames from host memory to transmit on the
network.

To transfer a word or a block of words between internal memory and host memory, the microprocessor
writes registers in the DMA subsystem to specify the internal memory address, the host memory address,
the number of words to be transferred, and the direction of transfer. The DMA subsystem interrupts the
microprocessor when the transfer is complete.
1.5.5

Port Control and Status Register (PCSR) Subsystem

The DELUA has four port control and status registers for communication with the host. Inside the
DELUA, the microprocessor has direct access to only PCSRO. PCSR1, PCSR2, and PCSR3 are not
connected to the internal bus. The microprocessor uses the DMA word mover to read and write these
registers by way of the UNIBUS.

1-9

1.6 SPECIFICATIONS
Table 1-1 lists the DELUA specifications.

Table 1-1

DELUA Specifications

Specification

Description

Operating Mode

Half-duplex

Data Format

Ethernet specification

Data Rate (Physical Channel)

10M bits/sec

UNIBUS Loading

1 dc load
4 ac loads

DC Power Requirements

+5+40.25V,8 A
—15 V, 1 A (for transceiver)

Physical Size
M7521 Module

Height (hex): 21.4 cm (8.4 in)
Length: 39.8 cm (15.7 in)

Bulkhead Assembly

Height: 10.6 cm (4.0 in)
Length: 10.6 cm (4.0 in)

Operating Environment
Temperature

10° to 50°C (50° to 122°F)

Relative Humidity

10% to 90% (noncondensing)

Wet-Bulb Temperature

28°C (82°F) maximum

Dew Point

2°C (36°F)

Altitude

Sea level to 2.4 km (8000 ft)

Shipping Environment
Temperature

—40°C to 66°C (—40 to 151°F)

Rate of Change

20°C/hr (36°F/hr) maximum

Relative Humidity

0% to 95% (noncondensing)

Altitude

Sea level to 9 km (30,000 ft)

1-10

1.7 RELATED DOCUMENTS
Table 1-2 lists related documents.

Table 1-2

Related Documents

Title

Order Number

DELUA Technical Description

EK-DELUA-TD

H4000 Technical Description

EK-H4000-TM

The Ethernet, A Local Area Network, Data Link Layer,

AA-K759B-TK

Ethernet Installation Guide

EK-ETHER-IN

Network Interconnect Exerciser User's Guide

AA-HIO6A-TE

Introduction to Local Area Networks

EB-22714-XX

DELUA Maintenance Print Set

MP-01787-01

and Physical Layer Specifications

DIGITAL personnel may order printed documents from:
Digital Equipment Corporation
444 Whitney Street
Northboro, MA 01532
.

Attention: Publishing and Circulation Services (NR03/W3)
Order Processing Section

Customers may order printed documents from:
Digital Equipment Corporation
Accessories and Supplies Group
Cotton Road
Nashua, NH 03060
For information call: 1-800-257-1710.

Information concerning microfiche libraries may be obtained from:
Digital Equipment Corporation

Micropublishing Group (BUO/E46)
12 Crosby Drive
Bedford, MA 01730

CHAPTER 2
INSTALLATION

This chapter provides the information necessary for installing a DELUA in a PDP-11 or VAX host
|

system.

PREINSTALLATION CONSIDERATIONS

2.1

The following factors should be considered before installing a DELUA:
e
e
e

Backplane requirements
Bus latency constraints
Bus loading factor
Backplane Requirements

2.1.1

slot that can be configured for
The DELUA requires one hex-height, small peripheral controller (SPC)(REV
E) or later] can accept a
nonprocessor request (NPR) operations. Any SPC backplane [DD11-B
DELUA module. The DELUA module can be placed anywhere on the UNIBUS system, but before all
UNIBUS repeaters.

Bus Latency Constraints

2.1.2

ssor request
For the DELUA, bus latency is the delay between the time the DELUA raises the nonproce
which allows it

signal,
(NPR) UNIBUS signal line and the time it receives the nonprocessor grant (NPG) when
it is reading and
to transfer a word on the UNIBUS. Excessive bus latency will slow the DELUA
the DELUA is
Since
writing words from the host processor’s memory using direct memory access (DMA).
a very well-buffered device, it is unlikely to lose data due to excessive bus latency.

and, thus, a
A module in a UNIBUS backplane slot closer to the processor has a higher NPRe priority
places the
that
slot
backplan
a
lower bus latency. To obtain optimum DELUA performance, select
optimum
If
.
repeaters
UNIBUS
all
DELUA module before all devices with a lower NPR rate and before
before
UNIBUS
the
on
anywhere
installed
performance is not a requirement, the DELUA module can be
all repeaters.

Bus Loading Factor

2.1.3

Make sure that system loading capacities are not exceeded as a result of installing the DELUA. The
DELUA ac and dc loads on the UNIBUS signal lines are as follow:
°

)

UNIBUS dc loads - 1

UNIBUS ac loads - 4

2-1

The power consumption of the DELUA is shown in Table 2-1.
Table 2-1

DELUA Power Consumption

Power Supply

Allowable Range

Current

Backplane Pin

+5V
—15 V (for transceiver)

+4.75 Vto 525V
~14.25 V to —-15.75V

8 A
1 A

CA2
FB2

2.2 UNPACKING AND INSPECTION
To unpack a DELUA subsystem, remove the equipment from its shipping containers, verify that there are

no missing parts, and inspect the equipment for damage. Report any damage or shortages to the shipper
and notify the DIGITAL representative.
1.

Before opening the shipping containers, check for external damage such as dents, holes, or
crushed corners.

CAUTION
The M7521 module and the UNA bulkhead assembly are easily damaged by static electricity. To avoid
damage, handle these parts only on the VelostatTM
mat. When not in use, store these parts in their

conductive plastic bags.
2.

Open a Velostat static discharge system (CD kit no. A2-W0299-10) and unfold the mat.

Attach one end of the 4.5-meter (15-foot) ground cable to an electrical ground point in the host
computer. Attach the other end to the mat snap fastener.

Attach the wrist strap to your wrist and clip the other end of the cable to the edge of the mat.

Open and unpack the shipping container. Check the contents against the parts shown in Figure

2-1.

NOTE
Keep the packing materials in case you must return
parts.

Inspect each part for shipping damage. Check the modules carefully for cracks, breaks, or loose
components, such as socketed chips.

2.3 PREINSTALLATION PREPARATION
To prepare the DELUA for installation, perform the steps describedin Sections 2.3.1 through 2.3.5.

Velostat is a trademark of the 3M Company.

2-2

M7521
MODULE
Q e 2

HARDWARE

~ CABINET KIT CKDELUA-KI

I/0

PACKAGE

(FOR NON-FCC-COMPLIANT

CABINETS)

——

UNA

S BLe

UNA

QUAD

ASSEMBLY

FRAME

-1
UNA BULKHEAD

CABLE ASSEMBLY
70-18798-08
(8-FOOT CABLE)

”,
|

UNA
BULKHEAD

ASSEMBLY

B. ONE OF THREE < CABINET KIT CKDELUA-KL
CABINETS)
e——

—

UNA BULKHEAD

CABLE ASSEMBLY
70-18798-04
(4-FOOT CABLE)

UNA
BULKHEAD

ASSEMBLY

CABINET KIT CKDELUA-KM

(FOR FCC-COMPLIANT

\. CABINETS)

<
UNA BULKHEAD

CABLE ASSEMBLY
C.

USER'S

70-18798-08

GUIDE

(8-FOOT CABLE)

EK-DELUA-UG

MKV85-0340

Figure 2-1

DELUA Component Parts

2-3

2.3.1

Backplane Preparations

If present, remove the grant continuity module from the slot for the DELUA.

If present, remove the nonprocessor grant (NPG) jumper wire that runs between backplane pins
CA1 and CBI of the slot for the DELUA module.
NOTE
If at a later time you remove the DELUA module, be
sure to either replace the NPG jumper wire and
install a G727 single-height grant module, or install
a G7273 dual-height grant module.

2.3.2

Device Address Assignment

Set the device address of the first DELUA (or DEUNA) being installed in a system to 774510 by setting
the switch pack at E106 as shown in Figure 2-2. For device address assignment purposes, the DELUA and
the DEUNA are equivalent. The DELUA address of 774510 could overlap with the twenty-third DP11
(double-buffered synchronous line controller) if your system has 23 DP11 controllers. If it does, select
another address for the DP11 controller from the floating address space described in Appendix A.

TM\

0000

12345678910
L

AAAMALAAY

1 1A12) - OFF

—— 10 (A3) - OFF

2 (A11) - OFF

9 (A4)
— ON

3 (A10) - ON

8 (A5) — ON

4 (A9) - ON

— OFF
7 (A6)

5 (A8) — OFF

6 (A7)
— ON
MKVES 1321

Figure 2-2

Switch Pack at E106, Device Address Assignment

For the second and any subsequent DELUA (or DEUNA) being installed in the same system, select the
device address from the floating address space. If the system already has a DEUNA, select the DELUA
device address from the floating address space. Figure 2-3 shows the correlation between address bits and
switches in the switch pack at E106. Refer to Appendix A for information on determining the appropriate
floating address.

2-4

LSB

mMSB
15

SWITCH PACK E106
|

SWITCH
NUMBER
OFF

OFF
OFF

OFF
OFF
OFF
OFF

OFF

OFF
OFF

OFF

FLOATING
ADDRESS
760010
760020
760030
760040
760050

760060
/60070
760100

OFF

OFF | OFF
OFF

760200
760300
760400

OFF

OFF
OFF

OFF

QFF

OFF

760500
760600

OFF

760700

761000

OFF
OFF

762000

OFF | OFF

763000

OFF

764000
MKV85-1836

Figure 2-3
2.3.3

Device Address and Switch Positions

Vector Address Assignment

Set the vector address of the first DELUA (or DEUNA) being installed in a system to 120 by setting the
switch pack at E69, as shown in Figure 2-4. For vector assignment purposes, the DELUA and the
DEUNA are equivalent.

For the second and any subsequent DELUA (or DEUNA) being installed in the same system, select the
vector address from the floating vector address space. If the system already has a DEUNA, select the
DELUA vector address from the floating vector address space. Figure 2-5 shows the correlation between
vector address bits and switches in the switch pack at E69. Refer to Appendix A for information on

determining the appropriate floating address.

2-5

AA
N
VT T

4 (VO8) - ON

—

10 (VO2) - ON

5(v07) - ON ——

9 (VO3) — ON

6 (VO6) — OFF

8 (V04) — OFF
7 (VO5) — ON
MKV85-1832

Figure 2-4

Switch Pack at E69, Vector Address Assignment

FLOATING V§CTOR ASSIGNMENT"TABLE fl
13

| 1

1 09

1 08

)

nomeer |

|06

| 05

| 03]

02101

SWITCH PACK E69

l
SWITCH

| 07

S [ 6 | 7]

I
FLOATING

|0 [T

OFF | OFF

OFF

300
304

OFF | OFF

OFF

310

OFF | OFF

314

OFF | OFF

8 | 9

OFF | OFF

f~—u OFF_]

320

OFF | OFF

OFF

OFF | OFF

330

OFF | OFF

OFF

| OFF | OFF

334

OFF

344

OFF | OFF | OFF

OFF

OFF | OFF | OFF

350

OFF | OFF

354

OFF

364

OFF | OFF | OFF | OFF | OFF | OFF

374

OFF

OFF | OFF | OFF

340

OFF | OFF | OFF

OFF | OFF | OFF | OFF

360

OFF | OFF | OFF | OFF
OFF | OFF | OFF | OFF

| OFF

OFF
OFF

324

370

400
OFF

500

OFF | OFF

600

OFF | OFF | OFF

700

MKV85-1833

Figure 2-5

Vector Address and Switch Pogitions
2-6

2.3.4 Boot Option Selection (PDP-11 Host Systems Only)
At the request of another node, a DELUA installedin a PDP-11 host can load the host operating system.
Switch settings on the DELUA module determine whether the DELUA loads the host by transferring the
operating system software across the network from another node, or signals the host to load itself from its
own mass storage system. The DELUA cannot load a VAX host.
The DELUA can be set up to perform a remote boot on powerup with the optional M9312 boot module
and ROM set, order number MR 11K-AE. During powerup, the DELUA loads the host operating system
by transferring the operating system software across the network from another node.
When installing a DELUA into a PDP-11 host system, set switches 2 and 3 of the switch pack at E69 for
the boot function desired. Figure 2-6 shows switches 2 and 3. Table 2-2 lists the switch settings and boot
functions. Section 5.1 provides additional information on remote boot functions.
When installing a DELUA into a VAX host system, set switches 2 and 3 on the switch pack at E69 to the
ON (disabled) position. Figure 2-6 shows switches 2 and 3.

Table 2-2 Boot Function Switches (PDP-11 Only)
Switch 2

Switch 3

Boot Function

ON
ON
OFF
OFF

ON
OFF
ON
OFF

Remote boot disabled
Remote boot from system boot ROM
Remote boot and system load
Remote boot disabled

2.3.5 Loop Selftest Switch (for Manufacturing Use)
Disable the loop selftest feature by setting switch 1 on the switch pack at E69 to the ON position as shown
in Figure 2-7.

Enabling the loop selftest feature does not cause the selftest to start, but once it is started (such as by a
powerup) the selftest will loop continuously.

2-7

r¥

Iooooij

12345678910

3 (BOO
SEL T
1)
-

2 (BOO
SEL T
0)
MKV85-1834

Figure 2-6

Boot Function Switches

B .4

rVe

Co oo fizfi’//////7
0000
|

1 (SELFTEST LOOP) —ON
MKVg5-1835

Figure 2-7

Loop Selftest Switch Setting

2.4 INSTALLATION
Perform the steps shown in Figure 2-8 to install the DELUA.

Plugged Hole

Install the UNA bulkhead cable. Note the
plugged hole in the BergTM connector on the
UNA bulkhead cable. Plug the connector into
J3 on the DELUA module.

Install the DELUA module. Install the
DELUA (M7521) module in the selected backplane slot.

NOTE
Remove the NPR jumper (CA1l to CB1) before
installing the DELUA module. You must reinstall
this jumper if you remove the DELUA module from
the system.

Install the UNA bulkhead (FCC-compliant
bulkhead panel). Remove the blank bulkhead
panel and install the UNA bulkhead assembly.

MKV85-1839

Figure 2-8

DELUA Installation Procedure (Sheet 1 of 2)

Berg is a trademark of Berg Electronics.

2-9

Install the UNA bulkhead (non-FCC-compliant
bulkhead panel).
a.

Locate the two 10-32 screws and u-nuts.

Slip the u-nuts onto the cabinet frame.

|\\5NN\

Secure the I/O bulkhead metal frame to
the cabinet frame.

Install the UNA bulkhead assembly into
the metal frame.

Connect the UNA bulkhead cable to the bulkhead assembly.
a.

Unlock

the

latch

the

cable

connector.

Connect the cable to J2 on the component
side of the UNA bulkhead assembly.

Slide the latch on the D connector to the
locked position.

MKV85-1840

Figure 2-8

DELUA Installation Procedure (Sheet 2 of 2)

2-10

2.5

VERIFICATION CHECKS

Perform the following tests to verify that the DELUA is operating correctly.

For these tests the DELUA must be attached to the network or to an H4080 loopback transceiver as

shown in Figure 2-9. The H4080 loopback transceiver is not included with the DELUA.
NOTE

DIGITAL personnel may obtain the H4080 loopback transceiver through their local DIGITAL Field
Service branch office. Customers may obtain the
H4080 through their local DIGITAL Sales
Representative.

UNA BULKHEAD
ASSEMBLY

DIGITAL ETHERNET
LOOPBACK CONNECTOR

TRANSCEIVER
CABLE

MKV85-0325

Figure 2-9

Loopback Transceiver Setup

2-11

2.5.1
Postinstallation Power Check
Turn on the system power and verify that the voltages at backplane pins CA2 and FB2 are in accordance
with those listed in Table 2-3. If necessary, adjust the power supply voltages.
Table 2-3
Power Supply

Allowable Range

Backplane Pin

+5V

+4.75 Vto 5.25 V
—~14.25 Vto -15.75V

CA2

—15 V (for transceiver)

2.5.2

DELUA Power Check

FB2

Light-Emitting Diode (LED) Checks
I.

Turn on the system power. Note that the DELUA must be connected to the
network or to a
loopback test transceiver.

The LEDs on the DELUA module will cycle indicating that the selftest diagnostic
(see Figure 2-10). The selftest takes about 15 seconds to complete.

is running

When the test completes successfully, LED D8 should be on indicating that the
DELUA is in
the ready state. The activity LED, D5, may also be flickering.

If any other LEDs are on, the selftest has found an error. Table 6-1 shows the LED
3.

status codes.

Check that the UNA bulkhead assembly LED shown in Figure 2-11
is lighted. This LED is
lighted by the —15-volt power supply that powers the transceiver.

2.6 DIAGNOSTIC ACCEPTANCE PROCEDURE
The final step in the DELUA installation procedure is to exercise the DELUA
on the UNIBUS and on the
network.

Run the appropriate diagnostics for the VAX or PDP-11 system as listed
in Table 2-4. To run the PDP-11
diagnostics, CZUAD and CXUAD, the DELUA must be connecte
d to a loopback transceiver. These
diagnostic programs assume that the only messages to and from the
transceiver are the messages they have

sent. If the DELUA is connected to a network and the diagnost
ic receives a message sent by another node
on the network, it reports errors. Run each diagnostic for at least
five passes.

To run the network interconnect exerciser (NIE) program, the DELUA must
be connected to the network.
Refer to the Network Interconnect Exerciser User's Guide (order number
AA-HIO6A-TE) for further
information.
Table 2-4

DELUA Diagnostics

PDP-11

VAX

Diagnostic

Host System

Functional

CZUAD (Stand-Alone)

EVDYB (Level 2R On-Line)

DEC/X-11

CXUAD (Stand-Alone)

None

NIE

CZUAC (Stand-Alone)

EVDWC

2-12

LRI

NERRR

mmm

NOTE: LED D2 IS NOT USED.
MKV8S-1841

Figure 2-10

DELUA LEDs

MKV85.0327

Figure 2-11

Bulkhead LED

2-13

CHAPTER 3

PROGRAMMING OVERVIEW

3.1

INTRODUCTION

The operation of the DELUA is controlled by a program in host memory called the port driver. The port
driver controls the DELUA in two ways: with port commands written to the four control and status
registers, and by ancillary commands written into shared data structures in host memory. Figure 3-1 shows
the DELUA control and status registers and the different data structures in host memory.
3.2 PORT COMMAND EXECUTION
Port commands are used to start and stop the DELUA, to tell it to read and execute an ancillary function
in host memory, and to tell it to transmit a message on the network. The host processor issues a port
command by writing bits (03:00) of the port control and status register 0 (PCSR0). The DELUA
responds by executing the port command and setting the done interrupt (DNI) bit or the port command
error interrupt (PCEI) bit.
3.3 ANCILLARY FUNCTION EXECUTION
The host processor issues an ancillary function by writing to a data structure in host memory called the
port control block (PCB) rather than directly to PCSR0. The PCB consists of four 16-bit words in host
memory.

Ancillary functions are used to read and write various addresses and pointers, and to read counters and
extended status information in the DELUA.
When the DELUA is initialized, the port driver gives the DELUA the starting address of the PCB by
writing a GET PCBB port command to PCSRO.
The following list shows a typical sequence of events when the DELUA executes an ancillary function:
1.

The port driver writes (moves) the ancillary function to the PCB and, if necessary, sets up other
memory data structures.

The port driver instructs the DELUA to fetch and execute the ancillary function by writing a
GET COMMAND port command to PCSRO.

The DELUA uses direct memory access (DMA) to read the PCB and execute the ancillary
function.

When the DELUA has finished, it notifies the host by setting the done interrupt (DNI) bit in
PCSRO.

r———————

mTennuprsT PORT COMMAND | PCSRO l

PORT CONTROL BLOCK ADDRESS | PSCR2 l

STATE | PCSR1

ZEROS

l PCSR3 I

HOST MEMORY

SELF TEST

UNIBUS DATA BLOCK

PORT CONTROL BLOCK

| PorT FuNcTION
PORT FUNCTION

PORT FUNCTION

DEPENDENT

INFORMATION

TRANSMIT DESCRIPTOR RING

RECEIVE DESCRIPTOR RING

BUFFER LENGTH

BUFFER ADDRESS

BUFFER LENGTH

15T

BUFFER ADDRESS

ENTRY

STATUS & ERROR

INFORMATION

[

ENTRY

N TMTM

ENTRY

BUFFER LENGTH

BUFFER ADDRESS

157

BUFFER LENGTH

N TMTM ENTRY

BUFFER ADDRESS

STATUS & ERROR
INFORMATION

TRANSMIT DATA BUFFER

RECEIVE DATA BUFFER

=
|
|
|
I
I
I
I
|
I
|
|
I
I
I
I
- —_——e
2Eo$t’)TngsAsTlo
'

DESTINATION

ADDRESS

SOURCE

RCE

i%%nsss

ADDRESS

TYPE FIELD

——

DATA

FIELD

CRC

MKV85-1837

Figure 3-1

DELUA PCSRs and Host Memory Data Structures

3.4 DATA FRAME TRANSMISSION AND RECEPTION
The DELUA transmits and receives message frames directly between the network and the host’s memory
with DMA operations. The port driver tells the DELUA where to get frames to transmit and where to
place frames it has received by means of transmit and receive descriptor rings in host memory.

The transmit descriptor ring contains a number of entries. Each entry specifies the length and starting
address of a data buffer in host memory. If the ownership bit in one or more of the transmit descriptor ring
entries is set, the DELUA reads the specified data buffers and transmits them on the network.

3-2

Each entry specifies the length and starting
The receive descriptor ring also contains a number of entries.DELUA
receives a frame on the network, it
the
When
.
address of a receive data buffer in host memory
writes the frame into one of these receive data buffers.

writes an entry in the transmit descriptor ring for
When the host has frames for the DELUA to transmit, itand
starting address of the transmit data buffer.
each frame. In each entry the host specifies the length
entry. The host then writes the
The host also sets the ownership bit in the transmit descriptorNGring
DEMAND port command causes the
POLLING DEMAND port command into PCSRO. The POLLI
the DELUA finds an entry with the
DELUA to read the entries in the transmit descriptor ring. asWhen
on the network. The DELUA can
ownership bit set, it transmits the contents of the data buffer a frame
a single longer frame. If the end-ofalso chain together the contents of several transmit data buffers into the
next data buffer to form a longer
frame bit in the descriptor ring entry is not set, the DELUA appends
frame until it encounters a
frame. The DELUA continues appending data buffers into a singlehaslong
transmitted the frame, it writes
descriptor ring entry with the end-of-frame bit set. After the DELUA
DELUA then continues to read entries in
status information into the transmit descriptor ring entry. The
ip bit set. After the DELUA has
the transmit descriptor ring looking for more entries with the ownersh
ted the associated data
found all of the descriptor ring entries with the ownership bit set and transmit
host.
buffers, it sets the transmit ring interrupt bit in PCSRO, which interrupts the

setting the ownership bit in each receive
The host allocates receive data buffers for use by the DELUAthebynetwork
, it writes the frame data into the
descriptor ring entry. When the DELUA receives a frame on
large enough to fit the entire frame, the
next allocated receive data ‘buffer. If the data buffer is not frame.
sets the start-of-frame bit in the
DELUA fills successive receive buffers until it completes the end-of-Itframe
bit in the receive descriptor
receive descriptor ring entry for the first buffer and it sets the bit in the receive
descriptor ring entry and
ring entry for the last buffer. The DELUA clears the ownership
sets the receive interrupt bit in PCSRO, which interrupts the host.
3.5

FUNCTIONAL STATES

1. These states are described in Table
The DELUA reports its functional state with bits (03:00) of PCSR
'

3-1.

Table 3-1
Functional

State

Running

Functional States

Description

port command in
The DELUA enters the running state when it receives the START
following functions:
PCSRO. When in the running state, the DELUA performs the
e

Transmits and receives frames on the network

Responds to port commands from the host

Maintains internal counters

Loops frames when requested by another node

Sends system ID frame

Accepts a remote boot frame from another node if the boot select switch is

enabled

Table 3-1

Functional
State

Functional States (Cont)

Description

Ready

The DELUA enters the ready state after powerup, remote boot, or after receiving a
STOP port command. When in the ready state, it does not transmit or receive
message frames, but it does perform the following functions:

Responds to port commands from the host

Maintains internal counters

Loops frames when requested by another node

Sends system ID frame

Accepts a remote boot frame from another node if the boot select switch is

enabled

Reset

The DELUA enters the reset state during powerup, when it receives the UNIBUS
initialization signal, or when the host sets the RESET bit in PCSRO. During the reset

Primary Load

state, the DELUA clears its internal registers and counters. It also runs its selftest
diagnostic if it has not already successfully run since the last powerup. If selftest is
successful, the DELUA enters the ready state.

The DELUA enters the primary load state when it is requested to load the host
operating system. This happens when the DELUA receives a BOOT port command

in PCSRO or a boot frame from another node. The DELUA transmits a request
program frame and then waits for a memory load with transfer address frame from
another node. The memory load with transfer address frame contains the secondary
loader program that the DELUA loads into its internal memory. When in
the
primary load state, the DELUA also performs the following functions:
e

Maintains internal counters

Loops frames when requested by another node

Sends system ID frame

Accepts a remote boot frame from another node after it has been in the primary

load state for 40 seconds or more
Secondary Load

The DELUA enters the secondary load state when the primary loader has
loaded the
secondary loader program from another node into DELUA internal memory.
The
secondary loader program loads a tertiary loader program from another
node into
host memory and starts it.

Table 3-1
Functional
State

Port Halted

UNIBUS Halted

Functional States (Cont)

Description

port command in
The DELUA enters the port halted state when it receives a HALT
. In the port
PCSRO. The host uses this state to write new microcode into the DELUA
on the network
halted state, the DELUA does not transmit or receive any frames
ds, but the
including maintenance frames. The DELUA responds to port comman
the UNIBUS
only way to get the DELUA out of the port halted state is with
DELUA at an
initialization signal, the RESET bit in PCSRO, or by starting thefunctio
n code 1.
y
ancillar
dress
microad
start
the
with
appropriate microcode routine

error in its
The DELUA enters the UNIBUS halted state when it detects a fatal
internal DMA system. When in the UNIBUS halted state, the DELUA also
performs the following functions.

Responds to the RESET bit in PCSRO

Loops frames when requested by another node

Sends system ID frame

The DELUA only responds to the UNIBUS initialization signal or the RESET bit in
PCSRO.

NI Halted

The DELUA enters the network interconnect (NI) halted state when it detects a fatal
error in its internal LANCE system. The DELUA accepts port commands. It also
responds to the UNIBUS initialization signal or the RESET bit in PCSRO.

NI and UNIBUS
Halted

internal
The DELUA enters the NI and UNIBUS halted state when it detects a fatal
the RESET
error. The DELUA only responds to the UNIBUS initialization signal or
bit in PCSRO.

Table 3-2 provides a summary of the events that cause the DELUA to make a transition from one
functional state to another.

Table 3-2

Functional State Transition Summary

From State

Transition Event

To State

Any State

Powerup

Reset

Selftest ran successfully

Ready

Selftest failure - DMA system

UNIBUS Halted

Reset
Reset

RESET bit in PCSRO set
UNIBUS initialization

Selftest already ran successfully
Selftest failure — LANCE system
Selftest failure — any other type of
internal failure

UNIBUS initialization signal

Ready
NI Halted

NI and UNIBUS Halted
Reset
Reset

RESET bit in PCSRO set

3-5

Table 3-2

Functional State Transition Summary (Cont)

From State

Transition Event

To State

Primary Load

Received memory load with transfer
address frame
Fatal UNIBUS error
Fatal internal error
UNIBUS initialization signal
RESET bit in PCSRO set

Secondary Load
UNIBUS Halted
NI and UNIBUS Halted
Reset
Reset

Port driver START command
Port driver BOOT command

Running
Primary Load

Ready

Boot frame (with remote boot
switch enabled)
Fatal UNIBUS error
Fatal internal error
UNIBUS initialization signal
RESET bit in PCSRO set
Port driver HALT command

Running

Port driver STOP command
Boot frame (with remote boot

Ready

Fatal UNIBUS error

Primary Load
UNIBUS Halted
NI and UNIBUS Halted

switch enabled)

Fatal internal error
UNIBUS initialization signal
RESET bit in PCSRO set

Port driver HALT command

Port Halted

UNIBUS initialization signal
RESET bit in PCSRO set
Start microaddress ancillary
function code 1
Fatal UNIBUS error

Fatal internal error

UNIBUS Halted

Primary Load
UNIBUS Halted
NI and UNIBUS Halted
Reset
Reset
Port Halted

Reset
Reset
Port Halted

Reset
Reset
State entered depends on microaddress
UNIBUS Halted

NI and UNIBUS Halted

Fatal internal error
UNIBUS initialization signal
RESET bit in PCSRO set

Reset

NI Halted

Fatal UNIBUS error
Fatal internal error
UNIBUS initialization signal
RESET bit in PCSRO set

NI and UNIBUS Halted
NI and UNIBUS Halted
Reset
Reset

NI and UNIBUS
Halted

UNIBUS initialization signal
RESET bit in PCSRO set

Reset

NI and UNIBUS Halted
Reset

Reset

Table 3-3 provides a summary of the state of the
internal information retained or reset by the
DELUA
when making a transition from one state to an other.

3-6

Table 3-3

State Entered
Reset

State Information Retention Summary

State Changes
Resets the following:
Ring formats
Counters
Physical address

Multicast address list
Status register
Ring pointers
[nternal memory
Load server address
System 1D
PCSRs
Mode register
Primary Load
State

State information retained depends on the action of the down-line loaded software.

Ready

Retains the following:
Ring formats

Counters
Physical address
Multicast address list
Mode register
Status register
Internal memory
Load server address
System 1D
PCSRs
Running

Retains everything, resets nothing.

Port Halted

Retains the following:
Ring formats
Counters
Physical address
Multicast address list
Mode register

Status register
Internal memory
Load server address
System ID
PCSRs

UNIBUS Halted

Immaterial because you cannot read any status with the UNIBUS halted. All ways
of clearing the UNIBUS halted state involve the reset state.

NI Halted

DELUA only enters the NI halted state after executing selftest. All status is
cleared at this time.

3-7

3.6 POWERUP AND RESET
.
When the DELUA is turned on, it executes its built-in selftest diagnostic. If the DELUA

enters the ready state. If it fails the test, it enters the UNIBUS halted,

passes the test, it

NI halted, or NI and UNIBUS

halted state. It displays the failing error code with the LEDs on the edge of the module
(see Table 6-1) and
also attempts to report the error code in PCSR1.
The DELUA performs a reset operation when the host sets the reset bit

in PCSRO or when it detects the
UNIBUS initialization signal. The DELUA runs selftest only if it failed
selftest the last time it ran. If
selftest passed last time, the DELUA just clears its registers and counters
and enters the ready state.

The following list describes the status of the DELUA registers after powerup
I.

The

The multicast address list is empty.

The lengths of both the transmit and receive descriptor rings are

DELUA physical
manufacturing.

address equals

the default

physical

specification is invalid.

The mode register is clear.

The counters are zeros.

The DELUA responds to port commands.

The DELUA forwards loopback frames to another node.

The DELUA sends its system ID frame.

The DELUA accepts a remote boot frame from another

or reset.
address assigned

during

zero, indicating that the ring

node.

To set up the DELUA to receive and transmit frames
on the network, the the host must perform the
following steps.
1.

The host enables interrupts by setting the interrupt enable

The host writes the base address of the port control

bit in PCSRO.

()

The host writes a GET PCBB port command into
PCSRO. This causes the DELUA to read the
base address of the PCB from PCSR2 and PCSR3.
The DELUA then sets the done interrupt in
PCSRO.

The host clears the interrupt by writing the done

block (PCB) into PCSR2 and PCSR3. The
PCB is used as an extra set of registers in host memory
for issuing ancillary functions to the
DELUA.

The host writes a write descriptor ring format ancilla
ry function code into the PCB. The host
also writes the base address of a structure called the
UNIBUS data block (UDB) into the PCB.

The host writes descriptor ring information into
the UDB. This information includes the base
addresses and the number of entries in the transmi
t and receive descriptor rings.

3-8

interrupt bit in PCSRO with a one.

The host writes a GET COMMAND port command into PCSRO. This causes the DELUA to
read the write descriptor ring format ancillary function from the PCB and store the appropriate
descriptor ring information internally. The DELUA then sets the done interrupt in PCSRO.
The host clears the interrupt by writing the done interrupt bit in PCSRO with a one.

The host assigns a number of receive data buffers for use by the DELUA by writing the
associated entries in the receive descriptor ring. In each entry, the host writes the base address
and length of the receive data buffer and sets the ownership bit.

10.

The host writes a START port command into PCSRO. This causes the DELUA to change from
the ready state to the running state. The DELUA now receives frames addressed to it. The
DELUA also transmits message frames when the host issues a POLLING DEMAND port
command in PCSRO. The DELUA sets the done interrupt in PCSRO to acknowledge the
START port command.

11.

3.7

The host clears the interrupt by writing the done interrupt bit in PCSRO with a one.

STOP AND RESTART

The host can stop the DELUA from transmitting and receiving frames by writing the STOP port
command into PCSRO. This causes the DELUA to change from the running state to the ready state. If the
DELUA is transmitting a frame on the network when it receives the STOP command, it finishes
transmitting the frame. Otherwise, the DELUA does not transmit or receive any frames except system ID,
boot, and loopback MOP frames.

The host can restart the DELUA after a stop by writing the START port command into PCSRO. This
causes the DELUA to change from the ready state to the running state. The following parameters remain

e B

ol ol

unchanged by a stop and restart operation.
Ring formats
Physical address
Multicast address list
Mode register
Status register
System ID parameters

Internal memory microcode
PCSRs

3.8 ANCILLARY FUNCTIONS THAT INTERFERE WITH MESSAGE PROCESSING
Some ancillary functions affect the processing of messages by the DELUA. Table 3-4 shows which
functions affect message throughput.

3-9

Table 3-4

Impact
None*
Portt
None
None
None

Ancillary Functions that Interfere with Messa

ge Processing

Function
Code

Function
Description

No Operation
Load and Start Microaddress
Read Default Physical Address
No Operation
Read Physical Address

1
2
3
4

LANCE#}

None

Write Physical Address

LANCE
None
PORT
None
None
None
LANCE
None
None
None

Read Multicast Address List

7
10
11
12
13
14
15
16
17
20

Port

Write Multicast Address List
Read Ring Format

Write Ring Format
Read Counters
Read and Clear Counters
Read Mode
Write Mode
Read Port Status
Clear Port Status

Dump Internal Memory

None

Load Internal Memory

None
None

Read Load Server Address
Write Load Server Address
Read System ID Parameters

23
24

None

Write System ID Parameters

Explanation of Impact terms:
* None
1 Port

There is no disturbance to the receive or

The DELUA does NOT execute these

state. These functions execute as a

ancillary functions while it is in the runni
ng

NO-OP. The STOP PORT command

before any of these ancillary functions
$ LANCE

transmit frame throughput.

can be executed.

must be issued

Response to these ancillary functions requir
e the DELUA to temporarily disengage
from the network while the mode of the
LANCE chip is being modified. The use
of
these commands can affect the data throu
ghput of the DELUA. Unless it is absol
utely .
necessary,
frequent use of these commands

Reception parameters.

The DELUA

is not recommended.

ignores all

frames while

modifying LANCE

Frames that the LANCE has
already processed and

are in the
internal memory buffers of the DEL
UA are sent to the host memory in
the
normal

manner.

Transmission - The DELUA finish
es transmitting the current frame
before
modifying LANCE parameters.

3-10

3.9

SUMMARY OF COMMANDS

Tables 3-5, 3-6, and 3-7 summarize the DELUA commands and functions.
DELUA Port Commands

Table 3-5

Reference

Command

Description

Section

STOP

The DELUA stops transmitting and receiving frames.

4.1

START

The DELUA starts transmitting and receiving frames.

4.1

GET PORT CONTROL

The DELUA reads the port control block (PCB) base

4.1

EXECUTE ANCILLARY

The DELUA reads the ancillary function from the PCB

4.1

POLLING DEMAND

The DELUA reads frames from host memory and

4.1

BOOT

The DELUA loads its PDP-11 host operating system.

4.1

SELFTEST

The DELUA runs its built-in selftest diagnostic.

4.1

HALT

The DELUA stops all operations and waits for the host

4.1

BLOCK BASE ADDRESS
FUNCTION

address from the host.
and executes it.

transmits them on the network.

to down-line load special microcode.
Table 3-6

DELUA Ancillary Functions
Reference

Function

Description

Section

Read Default

4.5.3

Physical Address

Provides the host with the Ethernet physical address of

the DELUA.

Read/Write

currently being used by the DELUA.

4.5.5

Physical Address

Allows the host to read or change the physical address

Read/Write

table currently being used by the DELUA.

4.5.6

Multicast Address

Allows the host to read or write the multicast address

Read/Write
Descriptor Ring

Allows the host to read or write the current base
address and lengths of the transmit and receive

4.5.7

Read/Write Mode

Allows the host to read or set certain operating features

4.5.9

Table

Format

descriptor rings.

of the DELUA that are used primarily for diagnostic
testing.

3-11

Table 3-6

DELUA Ancillary Functions (Cont)

Function

Description

Reference
Section

Read/Read and
Clear Counters

Allows the host to read and clear the
error and status
counters.

4.5.8

Read/Read and
Clear Status

Provides the host with extended statu

4.5.10

Allows the host to read and modify
the DELUA

4.5.11

s information.

Dump/Load

Internal Memory

microcode.

Start Microaddress

Allows the host to start execution
of the DELUA
microcode at a specified address.

4.5.2

Write System
ID Parameters

Allows the host to specify certain
parameters that the
DELUA sends in its system ID
message.

4.5.12

Write Load
Server Address

Specifies the preferred node from
which the DELUA
should get the operating system,
when it is booting its
PDP-11 host operating system.
Table 3-7

Function

Selftest

DELUA Maintenance Functions

Reference
Section

Description

The DELUA.executes its built-in diag

nostic test when it receives the

4.1

The DELUA loops a frame on
the network when it receives a

5.5

The DELUA sends a system ID
frame on the network when

5.9

SELFTEST port command in PCS

RO.

Loop

loopback frame from another

Identification

requested by another node.

node.

It also automatically sends

frame about every ten minutes.
Boot

4.5.13

The DELUA boots its PDP-1
|

host processor.

3-12

a system ID

5.1

CHAPTER 4

REGISTERS AND COMMANDS
PORT CONTROL AND STATUS REGISTER 0 (PCSR0)

4.1

Figure 4-1 shows the bit format of the PCSRO, and Table 4-1 describes the bit functions.
15

DN! | RCBI |FATL| USCI | INTR | INTE {RSET|

SERI | PCEI | RXI | TXI

IR/CLlR/CL R/CL| R/CL{R/CL|R/CL|R/CL}R/CL

R/W

03
PORT_COMMAND

R/W

NOTE:

R/CL = Read Access/ Write one to clear
R = Read Only
RW = Read/Write

MKV85-1842

W=Write Only

Figure 4-1

Table 4-1
Bit

Name

(15)

SERI

Port Control and Status Register 0 (PCSRO0) Bit Format

Port Control and Status Register 0 (PCSRO0) Bit Descriptions
Description

Status Error Interrupt - Indicates that there is an error bit set in the
DELUA extended status in bits (15:08) of word PCBB+2. Read this
status information with the read and clear status, ancillary function
codes 16/17. Interrupts the host. Cleared by writing with a one.

(14)

PCEI

Port Command Error Interrupt — Indicates a function error or a

UNIBUS timeout during the execution of a port command. PCSR1
(07) distinguishes between the two error conditions. Interrupts the
host. Cleared by writing with a one.

(13)

RXI

Receive Interrupt — Indicates that the DELUA has placed a frame in
a receive data buffer in host memory. Interrupts the host. Cleared by
writing with a one.

(12)

TXI

Transmit Interrupt — Indicates that the DELUA has finished

transmitting all the frames on the transmit ring or an error was

encountered during a transmission. Interrupts the host. Cleared by
writing with a one.

(1)

DNI

Done Interrupt — Indicates that the DELUA has completed a port
command. Interrupts the host. Cleared by writing with a one.

4-1

PCSRO

Table 4-1

Port Control and Status Register 0 (PCSRO0) Bit Descript

ions (Cont)

Bit

Name

Description

(10)

RCBI

Receive Buffer Unavailable Interrupt — Indicates that
the DELUA
has discarded an incoming frame because receive buffers
were
unavailable. This condition occurs when:
1.

The DELUA does not own any more data buffers
in host
memory. The DELUA increments the receive frames
lost —

local buffer error counter in word UDBB+32 of the extende

status information. The host can read this extende
d status
information with the read and clear counters, ancillary function

codes 12/13.
2.

The DELUA has not been able to write receive data

frames
into host memory quickly enough and has run out of internal
data buffers. The DELUA increments the receive frames lost
—
internal buffer error counter in word UDBB+30
of the
extended status information. The host can read this extende
d

status information with the read and clear counters
, ancillary
function codes 12/13.

Interrupts the host. Cleared by writing with a one. When receive
data
buffers are available again, the host must issue
a POLLING
DEMAND port command.

(09)

FATL

Fatal Internal Error — Indicates that the DELUA has detecte
d a fatal
internal error. The status information in PCSR1 is invalid.
Interrupts
the host. Cleared by writing with a one. The host can attempt
to clear
the error condition by setting the reset bit (05).

(08)

USCI

Unsolicited State Change Interrupt — Interrupts when
the following
occur in the DELUA:
1.

Remote boot started — The DELUA receives a boot
frame and
enters the primary load state.

NI halted state — The DELUA detects an error in its
LANCE
subsystem and enters the NT halted state.

These conditions are distinguished by examining
the state field
(03:00) of PCSRI. Interrupts the host. Cleared by
writing with a

one.

(07)

INTR

Interrupt Summary — The logical OR of bits (15:08)
. Interrupts the
host. Cleared by clearing the appropriate error bit(s).

(06)

INTE

Interrupt Enable - When clear, the DELUA does
not interrupt the
host. This bit and the port command field (03:00) cannot
be written
at the same time; two different instructions must be
issued.

4-2

PCSRO

Table 4-1

Port Control and Status Register 0 (PCSRO0) Bit Descriptions (Cont)

Bit

Name

Description

(05)

RSET

Reset — When set, initializes the DELUA. Note that reset also clears

(04)

Zero

Zero.

(03:00)

PORT_COMMAND

The port command field and the interrupt enable bit (INTE) (06)

INTE bit (06).

cannot be written at the same time; two different instructions must
be issued.

NO-OP

Causes no action. Does not set the

GET PCBB

Instructs the DELUA to fetch the
base address of the port control block
(PCB) from PCSR2 and PCSR3.

GET CMD

Instructs the DELUA to fetch and
execute an ancillary function from the
port control block (PCB).

SELFTEST

Instructs the DELUA to enter the
reset state and execute selftest.
Selftest takes about 15 seconds. After
executing selftest, the DELUA
responds by setting the done interrupt
bit (11), the unsolicited state change
interrupt bit (08), or the fatal error

DNI bit (11).

interrupt bit (09).

If selftest passes, the DELUA sets the
done interrupt bit (11).

If selftest fails, but the failure does not
from
DELUA
the
prevent
sets
it
host,
the
with
communicating
the unsolicited state change interrupt
bit {08). In this case, the failing error
code is in PSCR1, and the DELUA
responds to port commands.
If selftest fails, and the failure
from
DELUA
the
prevents
communicating with the host, the
DELUA sets the fatal error interrupt
bit (09). The error code information
in PCSR1 is invalid.

4-3

PCSRO

Table 4-1
Bit

Name

Port Control and Status Register 0 (PCSRO0) Bit Descriptions (Cont)
Description

START

Causes the DELUA to enter the
running state. If the DELUA is
already in the running state, it does
nothing but set the done interrupt bit
(11).

BOOT

Instructs the DELUA to enter the
primary load state and boot the host
system.

NotUsed