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Document:	DECpc 320sxLP/325sxLP Technical Reference Manual
Order Number:	EK-DECSX-TM
Revision:	001
Pages:	287
Original Filename:

OCR Text

DECpc 320sxLP/325sxLP

Technical Reference Manual
Order Number EK-DECSX-TM-001

March 1992
Digital Equipment Corporation

Maynard. Massachusetts

The information in this document is subject to change without notice and should not be

construed as a commitment by Digital Equipment Corporation.

Digital Equipment Corporation assumes no responsibility for any errors that may appear in
this document.

The software, if any, described in this document is furnished under a license and may be
used or copied only in accordance with the terms of such license.

No responsibility is assumed for the use or reliability of software or equipment that is not

supplied by Digital Equipment Corporation or its affiliated companies.

Restricted Rights: Use, duplication, or disclosure by the U.S. Government is subject to
restrictions as set forth in subparagraph (c) (1) (ii) of the Rights in Technical Data and

Computer Software clause at DFARS 252.227-7013.

CHIPS is a Registered trademark of Chips and Technologies. Inc.

IBM, PC, PC/XT. PC/AT, PS/2, VGA, EGA, CGA and MDA are trademarks of
International Business Machines Corporation.

Intel is a registered trademark of Intet Corporation.

Microsoft, MS-DOS, MS 0S/2, and XENIX are registered trademarks of Microsoft
Corporation.

OT1-066. OTI-067 and OT!-069 are t:ademarks of Oak Technology, Inc
Phoenix is a trademark of Phoenix Software Associates Ltd.

ProDriver, AIRLOCK and DisCache are registered trademark, and ProDriver LPS is a trademark of Quantum Corporation.

SIMM is a registered trademark of Wang Laboratories.

FCC Information:
This equipment has been certified to comply with the limits for a Class B computing device. pursuant to

Subpart G of Part 15 of FCC Rules Only peripherals (computer Input/outpul devices. terminals. prints,
etc) certified to comply with the Class B imits may be attached 1o this computer Operatton with noncentified peripherals is likely 10 result in interference to radio and TV reception This equipment generates
and uses radio frequency energy and if not instalied and used properly, that is, in strict accordance with
the manufacturer’'s instructions. may cause interference to radio and television reception li has been

type tested and found to comply with the imits for a Class B computing device in accordance with the
specifications n Subpart G of Part 15 of FCC Rules, which are designed to provide reasonable protection against such interference in a residential installation. However, there 18 no guarantee that interter-

ence will not occur in a particular installation if this equipment does cause interference o radio or
television reception. which can be determined by turning the equipment off and on, you are encouraged

to try to correct the interference using one or more of the following methods
+

Re-ornent the receiving antenna

Relocate the computer or peripheral with respect to the receiver

Move the computer or penpheral away from the receiver

Plug the computer or peripheral into a different outlet so that they are on different branch
circuits than

the

receiver.

i necessary. you should consult the dealer or an experienced radioftelevision techrician for additiona!

suggestions You may find the booklet "How 1o identity and Resolve Radio/TV interference Probiems
prepared by the Federal Communications Commission helpful This bookiet 1s availlable from the U S

Government Printing Office. Washington D C 204C2. Stock No 004-000-00345-4

CORBE, FEIRAGEE

1 FES

ITHHRIFOBE L AMRIISVTERANE A

EEMKTOREBESLEBOE LLBBUELSBERIBESEIR

#itmskEs VCCI

BRI ESLTHVIT.

LorL. REBE 504, FLEL 3 v SERIOAEL TIBRIL 2

RERE

DEEELEZIESEYFT.

RiZEEAEIZIE ~ TIELVENTIVE LT
TFA V.
MA 0347 80 CPG DG

Warning:
Shiglded cables must be used with this equipment If you add or replace any cables the new cables
must have shielding capabitities equal to or hugher than those provided Dy the dealer

Moditving or

tampening with interna! components can cause a matfunction and might invahdate the warranty ang voil
your FCC authorization to operate thiz equipment

Table Of Contents

1. ABOUT THIS MANUAL
1.1

Conventions ................oco
oo

Abbreviations ... 1-3

TP 1-3

Related Documentation ...
... .. .14

2. SYSTEM OVERVIEW
21
22

System Board Specifications......... 21
VGA Video Controlier Spemhcahons
.23

Environmental Specifications... ..

Physical Dimensions ... ...............

Power Requirements.. ...

... .

...

...25

_
il
.25
System Board Current Requ:rements .............................. 2-6

3. SYSTEM BOARD
3.1
311
312
313
314
315
316

DECpc 320sxLP/325sxL.P System Board Features .......... 3-3
B0386SX MiCroprocessor ............ ..o 3-3
82C386SX ISA Bus Chip Set............. UUTUT 3-5
82C712 Universal Peripheral Controller ... 35
OT1-067 Video Graphic Controller ... ... 3-5
DRAM
35
ROM
3-5

317

O POMS

318
319

System Status LED Indicators ... ... ... ... 36
System Board Configuration Setting . .............. ... 3-6

e 35

TABLE OF CONTENTS

4. CENTRAL PROCESSING CORE
4.1
4.2
4.3
44

Central Processing Unit ...........cccooiiiieiiiiciccne
s 4-3
Memory Management Unit ... 4-3
Modes of OpPeration .............ccooieiviieree
e 4-3
Signal Definitions ... 4-3

Signal Description ...

. 4-8

5. 82C386SX ISA CHIP SET
51
51.1
512

513

82C320 System Controller/Data Buffer ........................... 5-3
CPRUINtErface ..o, 5-5
I1SA Bus/System Controller Communication Channel .5-5

DRAM Support SUbsystem ... 5-6

5131

Memory Mapping ..o 5-6

5132
5133
5134
514
515
516
517
518
5181
5182
5183
5184
5185
5186
5187
5188

Paged Mode and Interleaving ............................ 5-9
DRAM Timing Parameters ... 5-12
DRAM Refresh ... 5-13
1/O Control RegiSters ...........cocoeiviii, 5-16
Halt/Shutdown Detection...............cccoe .87
Data Buffer ... 917
Signal Definitions ... 5-17
Signal Description ..o 5-23
CPU Interface Signals ...........ccocoiviiiiie 5-23
On-Board Memory System Interface Signals .....5-26
Coprocessor Signals ... 5-26
Bus Control Signals ..........cccoooeiii 5-27
Peripheral Interface Signals ... 5-29
e 5-29
Bus Interface Signais .........ccoooevviiiin
5-31
.
..
Pin.
TestMode
...
Pins
Power and Ground

5.2
521
5211
5212

82C3311SABus Controller ...
DMA
DMA Controllers ... .o Middie Address Bit Latches ...........................

5214
5215
522
5221

Page RegiSters ..o
Address Generation ... e Interrupt CoNtroller .......oooveeeci
interrupt Controller Registers

5213

DMA Controller Registers ...

TABLE OF CONTENTS vii

5222

523

5231

5232
5233
524
5241
5242
5243
5244

525
526

5261

5262
5263
1
52.

5265
5266

InterruptLevels ..., 5-44

Counter/Timer .......ooooeiiiiie
e
e 544
Counter/Timer QUtpULS ............c.ccooovieieieee 5-46
Real-Time Clock ..o 5-47
Time-Of-Day Registers ................ccoceevvenn, 5-48
Control Registers.............c.ccooveriiiiiiee e, 5-48
Control Register A ..o 5-49
Control Register B ...............c.coooviviiee 5-49
Control Register C ... 5-50
ControlRegister D ... 5-580
Signal Definitions ... 5-51
Signal Description ..o 5-57
CPUInterface ..........ccocoeiieiii 5-57
System Controller Interface ............................... 5-59
ROMInterface ............cc. oo 5-61
Bus Interface ... 561
Peripheral Interface .......... ... 565
Data Buffer Interface ........................co 5-66

5267

TestMode Pin ...

5268

Power and Ground Pins ... 5-68

e 5-68

5. 82C712 UNIVERSAL PERIPHERAL CONTROLLER If
6.1
6.1 1

Serial Communications POMS ...
vt 6-1
Serial Communications Ports Registers ..............
... 6-3

6.1. 1.1

Receive Buffer (RB) ... .

6.1 1.2

Transmit Buffer (TB) ... €6-5

6.1 1.3

interrupt Enabie Register (IER).................... ... 65
interrupt Flag Register (IFR) ... 6-6
Byte Format Register (BFR) ... 6-7
MODEM Control Register (MCR) ....................... 6-2
Line Status Register (LSB).........c...coooooee 6-9
MODEM Status Register (MSR) ......................... 6-11
Scratchpad Register............... oo, 6-12

6.1. 14
6.1. 1.5

6.1. 1.6
6.1 17
6.1 1.8

6.1.1.9
6.1.1.10
219

(o R

6.1.3
6.2

. ... ... €4

Effects of Hardware Reset............................. 6-12
Baud Rate Generation ... 6-13

Serial Communications Header .......................... 6-14
Paraliel Printer Port ... 6-14

6.2.1

Data Latch Register ... 6-15

622

Printer Status Register ... 6-15

6.23

Printer Control Register ...

o 6-16

vin

TABLE OF CONTENTS

624
6.3
6.3.1

631.1
6312

6313
6314
6315

6316
6317
6318
6319

Parallel Printer Port Header ............c..ccccocoievienveicann. 6-17
Integrated Drive Electronics Interface ... 6-17
Hard Disk Registers ..o 6-18
Data Re@iSter .......ccooveviiiiccresrec v 6-19
Ermor Register ........cccooveiiviiiii
e 6-19
Write Compensation Register ... 6-20
Sector Count Register ..........cccooveveiiienecnenn, 6-20
Sector Number Register ...............coocveviinvieenn, 6-20
Cylinder Number Register ...........c.ccccoevirinnn 6-20
DrivefHead Register ..........ccccoovviviiee i 6-20
Status RegISIer ..o 6-21
Command Register ............ccocoooiiii i, 6-21

63.1.10

Fixed Disk Register ... 6-21

631111

Digital input Register Definition ......................... 6-22
Floppy Disk Controller (FDC)........ccccooooiiiiiiieiine 6-22
Floppy Disk Register ... 6-22

6.4

6.4.1

64.1.1

64.1.2

Digital Qutput Register (Drive Control Register) 6-23
Main Status Register..............ccccovii, 6-24

6414

Data Register ... 6-25
Digital Input Register ..., 6-25

6415

~onfiguration Control Register

64.1.3

6.5

6.6

67
6.7.1
672

( - ta Rate Register) ...........cccoovvivviceie
e 6-25
82C712 Configuration ...........c.oocoivoiniiiiiceie e 6-26
Signal Detinitions ... 6-28
e 6-32
Signal DesCription ..o
Host Interface ... 6-32
Parallel Port Controller ... 6-33

675

Serial PortInterface ... 6-35
IDEINterface ..o 6-36
Floppy Interface ... 6-37

676

Power and Ground ... 6-39

673
6.7.4

7. 8042 KEYBOARD/MOUSE CONTROLLER
7.1
7.2

7.3
7.4

e 7-1
Command INVOCALION .......o.oooiiiiie
Status REQISIeN ..o 7-1
e 7-3
Standard COMMANTS .......ooeiiiioee
e 7-5
Extended Commands ...

7.6

Keyboard Controller Command Byte .......................... 7-6
Keyboard COmmands ..........ccoocoviiiiioii 7-8

7.7

Mouse COMMENAS ..o
e 7-9

7.5

TABLE OF CONTENTS ix

8. VGA VIDEO CONTROLLER
8.1
811
812
813
814
815
816
82
821
822
822.1
822.2
822.3
822.4
8225
83
84
85
86
861
8611
8612
86.1.3
8614
86.1.5
862
8621
8622
8623
8624
8625
8626
863
8631
8632
8633

OTI-067 VGA Graphics Controller .............ooceeveevin
i, 8-3
CRT Controller...........ccceeivviieiireii e, 8-3
Attribute Controller ..o, 83
Graphics Controler ...........cocoocovvve
e, 85
SEQUEBNCET ....veieeeeec ettt 8-5
Memory Bufter (FIFO).........cooveieiee
e, 8-5
Bus Interface .......c.cocoovveei i 8-5
OTI-066 Video DAC ...........c........ e 8-6
ANAlog OQULPULS ..o
e 8-9
Microprocessor Interface ..o B-2
Write-mode Address Register ... 8-10
Read-mode Address Register.............c..ccoee.. 8-10
Color Value Register ... 8-11
Pixel Mask Register ...............c.coooeeiiviiieen 8-11
Microprocessor Interface Timing Specifications 8-12
OTI-069 Video Pixel Clock Generator.............c...c.occoeeeie. B8-18
Video BIOS EPROM ......coooiiiiiiiee
e, 8-20
VIO RAM ..o, 8-20
VGA Compatible Registers.................cc.oooeiiiinnen, 8-21
General Registers ... 8-23
Miscellaneous Output Register ......................... 8-24
Input Status O Register ..., 8-25
Input Status 1 Register ..........c.cooeniiinn, 8-26
Feature Control Register ... 8-27
DAC REQISIEIS ..o
e 8-27
Sequencer Registers ..., 8-28
Sequencer Address Register ........................... 8-28
Reset Register ..o
oo 8-29
Clocking Mode Register ..............cccceeiiiii, 8-30
MAP Magk Register ...........ccocovvieeieee
e 8-31
Character Map Select Register ........................ 8-32
Memory Mode Register ..., 8-33
Graphics Controller Registers..............ccoooec e, 8-34
Graphics Address Register ..., 8-34
Set/Reset Register ............ ..o, 8-34
Enable Set/Reset Register ..o, 8-3

8634
8635
5636
86.37

Color Compare Register ..., 8-35
Data Rotate Register ...........c.ccooviiciiiii 8-36
Read Map Select Register................ccccceenin, 8-36
Graphics Mode Register ... 8-37

TABLE OF CONTENTS

8638
86.39
86.3.10
864
864.1
8642
8643
8644
8645
8646
864
8.6.5
8651

Miscellaneous Register ...............c.ccecvvevveiiinnnn 8-39
Color Don't Care Register.............c.c..ccoeeevennn, 8-40
Bit Mask Register...........cccoveeiiiiieiccnin
e 8-40
Attribute Controlier Registers ..................cooovveveennnn. B-41
Attribute Address Register ..o, 8-41
Palette Registers 0- 15 ....... et e 8-41
Attribute Mode Control Register ........................ 8-42
Overscan Color Register ...........cccccoevvevinnann. 8-43
Color Plane Enable Register................ccccoovou. 8-44
Horizontal PEL Panning Register....................... 8-45
Color Select Register .......cc.ccooovieeiiiiiiiiicin
e 8-46
CRT Controller Registers..........c..cccooveerinneccriennn, 8-46
CRT Controller Address Register ..................... B-46

8652
8653
8654
8655
8656

Horizontal Total Register ...........cc.ccoccooo i, 8-47
Horizontal Display Enable End Register............. 8-47
Start Horizontal Blanking Register ...................... B-47
End Horizontal Blanking Register ...................... 8-48
Stant Horizontal Retrace Puise Register ............. 8-48

8657
8658
8659
8.6.5.10
86511
86512
86513
86.5.14
86515
86516
86517
86518
86519
86520
86.5.21
86522
86523
86524
8.6525
8.6.5.26
87
8.7.1
8.7.2
873

End Horizontal Retrace Reqgister ........................ B-49
Vertical Total Register..............c.cccooen, 8-49

CRT Controller Overflow Register....................... 8-50
Preset Row Scan register ... 8-50
Maximum Scan Line Register .......................... 8-51

Cursor Start Register ............cccooeiiiiieeei 8-51
Cursor End Register ..o 8-52
Start Address High Register .................c.coc....... 8-52
Start Address Low Register ... 8-52
Cursor Location High Register .......................... 8-863
Cursor Location Low Register ... 8-53
Vertical Retrace Start Register .......................... 8-53
Vertical Retrace End Register .................coco.... 8-54
Vertical Display Enable End Register ............... 8-54
Offset RegiSter ... B-55
Underline Location Register ... 8-55
Start Vertical Blanking Register ....................... 8-55
End Vertical Blanking Register ........................... 8-56
CRTC Mode Contro! Register .............ccoccoee. 8-56
Line Compare Register..........c.ccocooeiiiiinn, B8-57
Extended Registers ... 8-58
Extension Address Register...........cocoveii 8-58
Scratch Registers 1-3.. ..., 8-59
CRT Control Register ............ccccoovvoiiiciiiiii 8-59

TABLE OF CONTENTS xi

874
875
876
877
878
879

OT! Miscellaneous Register ..............c.ccooevieevieininane. B-60
Backward Compatibility Register............c......o.......... 8-61
NMI Data Cache Register ..............cc.coceevveieveerennann. 8-62
DIP Switch Read Register............c.ccccovnricvnnnnnn 8-62
Segment RegISter .........ccoeeeviiiiiiiiiie 8-63
Configuration Register ............ccccovvevriniiiirnnnn. 8-64

8.7.10

Bus Control Register .........cceevereiiveee i, 8-64

8711
8.7.12
88
89
891
892
893
8.10

OTI Overfiow Register .............ccccecvivviiiniiiee 8-65
Hsync Divided By 2 Start Register ............................ B-65
Supported Screen FOrmats .............ccoocooeeiiiiii
e, 8-66
Signal Definitions ...........c.ccoeiiiiiiiii 8-68
OTI-067 Signal Definitions...................ooooooi, 8-68
OTI-066 Signal Definitions....................coin, 8-74
OTI-069 Signal Definitions..................coo.cooin, 8-75
Signal Description ............cccoviiiiiiie
e 8-76

8101
810.1.1
810.1.2

OTI-067 Signal Description ..., 8-76
CPUBuUs Interface ..o 8-76
BIOSROM Control..........ocoocooe i 8-77

8.10.1.3
81014
81015
81016
81017
8.10.2
8.10.3

Clockinterface ... B-78
CRT And Ramdac Interface ................c.ceei 8-78
Video Memory Interface ... 8-79
MISCRUANBOUS ... 8-80
Powerand Ground ... B-80
OTI1-066 Signal Description .............. e 8-81
OTI-069 Signal Description ................. PUUURRR 8-82

9. POWER SUPPLY
91

115 Watt Power Supply Output Specifications ................. 9-1

APPENDICES
A.

BIOS INTERRUPT ROUTINES
Al
A2

Interrupt Vector Table ... A-1
BIOS SEIVICES ..o
e A-4

xit

TABLE OF CONTENTS

PRODRIVE LPS52/105AT HARD DISK DRIVES
B.1

Physical Specifications ..............ccccocv v B-2

Performance Specifications ..........ccc.oooiviiiin B-4

Functional Specifications ............ccccccoo v B-8

B4
B5
B51

BS52

B53

Power Requirements ..o B-9

Jumper Setting ... B-9
Drive Select (DS) Jumper ... B-10
Stave Present (SP) Jumper ............ccooie
e, B-10
Drive Mode (DM} Jumper ... ... B-11

C . FLEXIBLE DISK DRIVE (FDD)
C1

ci11
c1z2
c13
c2
ce1
cz2
c23

SONY 3.5* 2MB Micro Floppy Disk Drive........................ C-1
Configuration ... C-1
Physical Specifications ..............occoeeii C-1
Performance Specifications ... C-3
TEAC-55GFR-159 Mini Flexible Disk Drive ...................... C-5
GENETA ..ot C-5
Physical Specifications ... C-6
Performance Specifications ... C-9

TABLES
2-1
2-2
2-3

2-4
2-5

2-6

3-1
4-1

5-1

5-2
5-3

5-4
5-5

5-6

System Board Specificalions ... 2-2
VGA Video Controller Specifications ........................... 2-3
Environmental Specifications ... 2-4
Physical DIMEeNSIONS ............cooiiii
i 2-5
Power Requirements ...........cocivirio 2-5
Current REqQUITEMENTS ..o 2-6
Configuration Setting ..o 3-7
80386SX Signal NaMe ..o 4-4

Bus/System Controller Bus Cycle Types .......................... 5-5
DRAM MaPDING coooieeeie e 5-8
RAMMAP (03h RW )Iindexed Configuration Regtster ... 5-8
RAMMOV (04h RAW) Indexed Contfiguration Register ... 58
REMAP Configuration Register Code .................. ... 5-9
RAMSET (05h R/W) indexed Configuration Register ... 5-10

TABLE OF CONTENTS xiii

5-7

Automatic interleave VS. Memory Map ..........oocvvveveeen. 5-11

5-8

RASTMA (07h R/W) and RASTMB (09h RIW) .................. 5-12

5-9
5-10
5-11

CASTMA (08h RW) and CASTMB (OAh RW) ................ 5-13
REFCTL (05h RW) Configuration Register..................... 5-15
Dedicated I/O Control RegiSters ................oc.ooovevereenenn
. 5-16

5-12

80386SX Halt/Shutdown Detection.................................. 5-17

5-13

82C320 Signal Name ..., 5-18

5-14

ROMDMA (81h R/W) Indexed Configuration Register ....5-35

5-15
5-16

DMA Controller Read/Write Address........................... 5-36
612AXS (82h R/W) Indexed Configuration Register ........ 5-37

5-17
5-18

DMA Page Register OptionOne ............................ 5-38
DMA Page Register Option TWo............................. 5-18

5-19
5-20

DMA Addressing for ISA slot Access............................. 5-39
DMA Addressing for System DRAM Accesses ............... 5-40

5-21
5-22
5-23
5-24
5.25
5-26
5-27
5-28
5-29
5-30
5-31

interrupt Controller Write Operations.............................. 5-43
interrupt Controlier Read Operations ............................. 5-43
DECpc 320sxLP/325sxLP System Interrupt Levels ......... 5-44
Counter/Timer Register Addressing ...................c.......... 5-46
Real Time Clock AddressMap ..........................o...... 5-47
Time-of-Day Register Addressing ... 5-48
Control Register A Bit Assignments ............................ 5-49
Control Register B Bit Assignments .............................. 5-49
Control Register C Bit Assignments ... 5-50
Control Register D Bit Assingments ... 5-50
B2C331 Signal Name ..., 5-51

6-1

Addressing of UART Registers.................

6-2

oo 6-4
Receiver Buffer Register Bit Assignment ........................ 6-4

6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15

Transmit Buffer Register Bit Assignment........ ............... 6-5
Interrupt Enable Register Bit Assignment ..................... 6-5
interrupt Flag Register Bit Assignment..................o.. 6-7
UART Interrupt Specifications ...................o oo, 6-7
Byte Format Register Bit Assignment ... 6-8
Modem Control Register Bit Assignment ..................
... 6-9
Line Status Register Bit Assignment ... 6-10
Modem Status Register Bit Assignment ........................ 6-11
Hardware Reset onthe B2C712 UART ... 6-12
Divisors, Baud Rates and Clock Frequencies ................ 6-13
Serial Communications Connector Pinouts ..................... 6-14
LPT Port Status Bit Assignments ... 6-15
LPT Port Control Bit Assignments ..., 6-16

6-16

Paralie! Printer Connector Pinouts ..., 6-17

6-17

IDE Control Signal ........coooviiie

e 6-17

xiv

TABLE OF CONTENTS

6-18
6-19

IDE Register ADAress Map ........c..ocooveiciiniinniieen 6-19
Error Register Bit Assignments ... 6-19

6-20

Drive/Head RegiSter ..........cocverveniieviive
e 6-20
Status Register Bit AsSiQNMeENts ............cccoeceveeeiininne 6-21
Fixed Disk Register Bit Assignments...........c.coccceceeines 6-21
Digital Input Register Definition Bit Assignments ............ 6-22
FDC Register Address Map ......c.....ccccoevninincinnnn. 6-23
Digital Output Register Bit Assignments ........................ 6-23
Drive/MOotor Selection ..........c.ouevivirverrieronie et 6-23
Main Status Register Bit Assignments............................ 6-24

6-21

6-22
6-23
6-24
6-25
6-26
6-27
6-27
6-28

6-29
6-30
6-31

Main Status Register Bit Assignments.......................... 6-25
Configuration Control Register Bit Assignment ............... 6-25
Data Rate and Precompensation Programming Values ..6-26
Parallel Port Address Select ..., 6-26
Primary Serial Port Address Select............................ 6-27

6-33

Secondary Serial Port Address Select ... 6-27
IDE COMION ..ottt 6-27

6-34

FDC CONIOl ..ottt 6-27

6-32

6-35
7-1

72
7-3
7-4

7-5
7-6

8-1

8-2
8-3

8-4

8-5
8-6
8-7
8-8
8-9
8-10

8-11
8-12
8-13
8-14
8-15

8-16
8-17

82C712 Signal Name..........cooervieioiiiiiiiice e 6-28
Status REGISIEN ......ovevieieeieeieeeiei e 7-2
Standard Command Set ..o 7-3
Extended Command Set ..........cooviiiiini 7-5
Keyboard Controfler Command Byte ... 7-7
keyboard COMMANGS .........covereieiieiiicin e 7-8
MoUSE COMMENTS ...eoveiivieireiie et 7-9
Microprocessor Interface Registers ... 8-9
Microprocessor Interface Timing Specifications ............. 8-12
VGA Compatible Register Address Map...................... 8-21
Miscellaneous Output Register Bit Assignment .............. 8-24
Input Status 0 Register Bit Assignment .......................... 8-25
Input Status 1 Register Bit Assignment ........................... 8-26
Feature Control Register Bit Assignment .................... 8-27

DAC Registers Address Map ... 8-27
Sequencer Address Register Bit Assignment ................ 8-28
Reset Register Bit Assignment ... 8-29
Clocking Mode Register Bit Assignment ......................... 8-30
Map Mask Register Bit Assignment ......................... 8-31
Character Map Select Register Bit Assignment .............. 8-32
Memory Mode Register Bit Assignment ......................... 8-33
Graphics Address Register Bit Assignment.................... 8-34

Set/Rest Register Bit Assignment ... 8-34
Enable Set/Reset Register Bit Assignment..................... 8-35

TABLE OF CONTENTS xv

8-18
8-19

Color Compare Register Bit Assignment...............cceee... B-35
Data Rotate Register Bit Assignment ..............ccccecneennne 8-36

8-21

Graphics Mode Register Bit Assignment ................cc.c.... 8-37

8-20

Read Map Select Register Bit Assignment ..................... 8-36

8-22

Miscellaneous Register Bit Assignment .............cccoceee.. B-39

8-23
8-24
8-25

Color Don't Care Register Bit Assignment ...................... 8-40
Bit Mask Register Bit Assignment ..............ccceceeereeenen. 8-40
Attribute Address Register Bit Assignment ..................... 8-41

8-26

Palette Registers 0-15 Bit Assignemnt ................cccceeee, 8-41

8-27
8-28
8-29

Attribute Mode Control Register Bit Assignment.............. 8-42
Overscan Color Register Bit Assignment ....................... 843
Color Plane Enable Register Bit Assignment .................. 8-44

8-30
8-31
8-32
8-33

Horizontal PEL Panning Register Bit Assignment ........... 8-45
Color Select Register Bit Assignment................cccccocee.... 8-46
CRT Controller Address Register Bit Assignment ........... 8-46
Horizontal Total Register Bit Assignment ........................ 847

8-34
8-35
8-36
8-37
8-38
8-39
8-40
8-41
8-42
8-43
8-44
8-45
8-46

Horizontal Display Enable End Register Bit Assignment 8-47
Start Horizontal Blanking Register Bit Assignment.......... 8-47
End Horizontal Blanking Register Bit Assignment........... 8-48
Start Horizontal Retrace Pulse Register Bit Assignment . 8-48
End Horizontal Retrace Register Bit Assignment ............ 8-49
Vertical Total Register Bit Assignment .................c.c.c...... 8-49
CRTY Controlier Overfiow Register Bit Assignment .......... 8-50
Preset Row Scan Register Bit Assignment..................... 8-50
Maximum Scan Line Register Bit Assignment ................. 8-51
Cursor Start Register Bit Assignment ........................... 8-51
Cursor End Register Bit Assignment ... 8-52
Start Address High Register Bit Assignment................... 8-52
Start Address Low Register Bit Assignment.................... 8-52

8-47

Cursor Location High Register Bit Assignment .............. 8-53

8-48
8-49
8-50
8-51
8-52
8-53
8-54
8-55
8-56
8-57
8-58

Cursor Location Low Register Bit Assignment ................ 8-53
Vertical Retrace Start Register Bit Assignment ............... 8-53
Vertical Retrace End Register Bit Assignment .............. B-54
Vertical Display Enable End Register Bit Assignment .....8-54
Offset Register Bit Assignment ... 8-585
Underline Location Register Bit Assignment................. 8-55
Start Vertical Blanking Register Bit Assignment .............. 8-55
End Vertical Blanking Register Bit Assignment............... 8-56
CRTC Mode Control Register Bit Assignment ................. 8-56
Line Compare Register Bit Assignment ........................ 8-57
Extended Register Address Map ... &-58

8-59

Extension Address Register Bit Assignment ................... 8-58

xvi

TABLE OF CONTENTS

8-60
8-61
8-62
8-63
8-64
8-65
8-66
8-67
8-68
8-69
8-70
8-71
8-72
8-73
8-74
8-75

8-76
8-77
9-1
A-1

A-2

A-3
A-4
A-5

A-6
A-7
A-8

A-9
A-10

A-11
A-12
A-13

B-1
B-2
B-3
B-4
B-5
B-6
B-7
B-8
B-9

B-10

Scratch Registers 1-3 Bit Assignment ... 8-59
CRT Control Register Bit Assignment ..............c..cceeeeee 8-59
OTI Miscellaneous Register Bit Assignment .................. 8-60
Backward Compaitibility Register Bit Assignment ........... 8-61
NMI Data Cache Register Bit Assignment ...................... 8-62
DIP Switch Read Register Bit Assignment ...................... 8-62

Segment Register Bit Assignment ..o 8-63
Configuration Register Bit Assignment............................ 8-63
Bus Control Register Bit Assignment .......................... 8-64
OTI Overflow Register Bit Assignment ......................... 8-65
Hsync Divided By 2 Start Register Bit Assignment ......... 8-65
Standard VGA Modes Supported.............cccococoieonn, 8-66
Extended Modes Supported ..........ceeeereiieniici 8-67
Sunc Specifications for Standard VGA Modes................ 8-67

Sync Specifications for OTI Extended Modes ................. 8-68

OTI-067 Signal Name ........cccoeevviiiiiiiiice
e 8-68
OTI-066 Signal Name ..............coceviiioiiiiii
e 8-74
OTI-069 Signal Name ...
e 8-75
115 Watt Power Supply Qutput Specification.................. 941
Interrupt Functionsand Types ...
... A-1
Software INterrupts .........c.ooooeeio A-5
Print SCreen ServiCe ... A-5
VIdE0 SBIVICES ... ... AB
Equipraent List SEIVICE ..o A-10
Memory Size Service ................o. A-10
Diskette SEMVICE ... A-11
Fixed Disk Service ................ccccoeiivii, UV A-11
Serial Commurication ServiCe ... A-12
SYSIEM SEIVICES ... A-12
Keyboard ServiCe .........c.oooovveiniiiiiiii A-13
Paralle! Printer SErvice ... A-13
Time-of-Day ServiCe ...........cccooviieiiiiici i A-13

Environmental Limits ... B-2
Mechanical DImensions ..............coccvii B-3
Heat Dissipation ... 8-3
Vibration and Shock Specifications ... B-4
e B-4
Physical Capacity ..........coooveerireiee
Logical Addressing Format ... B-5
Data Transfer Rates ..o, B-5
Timing SPeCiiiCations ... B-6
Error RAlES ..o e B-7

LPS 52/105AT Functional Specifications ....................... B-8

TABLE OF CONTENTS xvii

B-11

LPS 52/105AT DC Power Requirements ......................... B-9

-1

Mechanical DImensions ..............cc..ocooveoivieeeeee
e, C-1

c-2
C-3

Environmental LIMitS ..o Cc-2
Vibration and Shock Specifications ...........cccoccveevvevvevan.. c-2

C-4

Power Consumption ............ccocoiiiiii
e, C-3

C-8

Timing SPeCfiCatioNS .........ooov e C-4

C-10

Reliability ......... e C-5

Cc-11
c-12
C-13
C-14
C-15
C-16
c-17
c-18
C-19
C-20

Mechanical Dimensions ... C-6
Environmental Limits ..o C-6
Vibration and Shock Specifications .............................. C-7
Power Consumption .............c.ocooiooieie
e c-7
Supply VOREGE ..o c-8
High Density Mode Data Capacity .............c..oo.ooooeeee. c-9
Normal Density Mode Data Capacity ........................... C-10
Disk Rotation Mechanism ... C-1
Track Construction ... C-12
Reliability ..o C-12

C-5
C-6
C-7

Cc-9

Supply VOREGE ..o, C-3
Recording Capability ............c.ccoov oo C-3
Data Transfer Rates ..................cccooeiee
i, C-4

SIUCIUIE ..., C-4

FIGURES
3-1
3-2
4-1

System Board Layout ... RO 3-2
DECpc 320xLP/325sxLP Block Diagram............o.cooveeenen. 3-4
80386SX Pipeline 32-bit Microarchitecture ...................... 4-2

5-1
5-2
5-3
54
5-5
5-6
5-7

82C386SX Functional Block Diagram ............ccc..coceiinn. 5-2
82C320 System Controller Functional Biock Diagram ......5-4
DRAM ReMAP ..o 5-7
-RASBK/-CAS TIMING MODEL ......cc.ooocooviiiiiiinin, 5-14
-CAS START TIME(TCST) TIMIING MODEL .................... 5-14
82C331 Functional Block Diagram Subsection ............... 5-33
DMA Subsection Functiona! Block Diagram .................. 5-34

5-8

Interrupt Controller Block Diagram ..................cooeeeienne. 5-42

59
6-1

Counter/Timer Functional Block Diagram....................... 5-45
82C712 Block Diagram ..........ccccoooviiiiiniiis
e 6-2

8-1
8-2
8-3
8-4

Vido Controller Block Diagram ...
oo 8-2
OTI-067 Block Diagram ..........ccocooovivviiiiiii
e 8-4
OTI-066 Block Diagram ...........ococoovioiiiiiin i 8-7
Video Path timing model ..o 8-8

Xviil

TABLE OF CONTENTS

8-5

Microprocessor Interface Timing Model t........................ 8-13

8-6

Microprocessor Interface Timing Model Il ...................... 8-14
Microprocessor interface Timing Model Hll ................... 8-14
Microprocessor Interface Timing Model IV ..................... 8-15
Microprocessor interface Timing Model V ..................... 8-15
Microprocessor Interface Timing Model VI ..................... 8-16
Microprocessor interface Timing Modei VI .................... 8-16
Microprocessor Interface Timing Model VIH ................... B-17
Microprocessor Interface Timing Model IX ... ................. 8-17
OT1-069 Video Pixel Clock Generator Block Diagram .....8-19

8-7

8-8

8-9
8-10
8-11
8-12
8-13
8-14

ABOUT THIS MANUAL
This 1s a Technical Reference Manual provides a comprehensive hardware description of the major components in the DECpc 320sxLP/325sxLP

computer. Separate chapters in the manual cover the following topics
System Overview
Chapter 2

Contains system and environmental

System Board
Chapter 3

Describes major features of the system

Central Processing Core
Chapter 4

Describes the 80386sx microprocessor

82C386sx Chip Set
Chapter 5

specifications of the system box

main logic board.

Describes operation of the 82C320 system

controller/data buffer and the 82C331
ISA bus controller.

82C712 Universal

Describes operation of the 82C712 Univer-

Peripheral Controlier

sal Peripheral Controller I1. Infarmation

Chapter 6

inciudes Serial & Parallet port descriptions,
floppy disk controliers and an Integrated
Drive Electronics(IDE) interface description.

8042 Keyboard &
Mouse Interface
Chapter 7

Describes the operations of the 8042
keyboard and mouse interface.

Video Controller

Describes operation of the OTI VGA Video

Chapter 8

Controlier

1-1

1.2

ABOUT THIS MANUAL

Power Supply

Chapter 9

Describes the system power supply
output specification.

BIOS interrupt
Appendix A

Lists the interrupt service routines

LPS 52/105AT
Hard Disk Drives

Lists general speciications for the
LPS 52/105AT hard disk drnves

available in the system BIOS.

Appendix B
Floppy Disk
Drive (FDD)
Appendix C

Describes general specifications for the
35", 2MB SONY FDD and the TEAC.
5.25'FDD.

ABOUT THIS MANUAL

1-3

1.1 Conventions
Information that is especially helpful or important is presented as a note, a

caution, or a warning:

NOTE: Provides suppiementary information of general interest.
CAUTION
Provides information dedicated to avoiding the loss or corruption of
data, and/or damage to hardware or equipment.

WARNING

Provides information crucial to preventing personal injury.

.2 Abbreviations
The following abbreviations are used in this manual
Kb = kilobit

KB = kilobyte
Mb = megabit
MB = megabyte
Hz = Hertz
MHz = megahertz
ms = millisecond
ns = nanosecond

SIMM = single in-line memory module

1.4

ABOUT THIS MANUAL

1.3 Related Documentation
The following related documents are available as supplements to the
information provided in this manual.

Document

Part Number

DECpc 320sxLP/325sxL.P User's Guide

EK-DECSX-UG

2
SYSTEM OVERVIEW
This chapter gives information about the technical charactenstics ot the

DECpc 320sxLP/325sxLP. Information includes
System Board Specifications
VGA Video Controller Specifications

Environmental Specifications
Physical Dimensions
Power Requirements
System Board Current Requirements

'.1 System Board Specifications
Table 2-1 lists the system board specifications

2-2

SYSTEiL OVERVIEW

Table 2-1. System Board Specifications

Attribute

Specification

CPU

80386sx

CPU clock speed

20/25 MHz

Master clock speed

40/50 MHz

ISA bus speed

6.67/8/10 MHz

interrupts

Memory addressing
Physica!

16MB

Supported

32MB

ROM BIOS Size

64 KB

DRAM memory

Speed

80 ns or faster

Type

9-bit SIMM

Standard size

2MB

Optional sizes

4,6,8,10,12.16,18,20,24,32 MB

Error Protection

Byte parity

System batteiy

3-year shelf life

Dimensions

8.657 inches by 13 inches

Layers

SYSTEM OVERVIEW 2-3

2.2 VGA Video Controller Specifications
Table 2-2 lists the VGA video controller specifications.

Table 2-2. VGA Video Controller Specifications

Attribute

Specification

Processor

QTi-067 mucroprocessor

Speed

50 MHz

DRAM

512K

Colors

256 from a palette of 256K

2-4

SYSTEM OVERVIEW

2.3 Environmental Specifications
Table 2-3 list the system box environmental specifications.

Table 2-3. Environmental Specifications

Attribute

Specification

Operating temperature

10° to 35°C

Storage temperature

-40°C to 60°C

Operating humidity

20-80% Relative humidity, max wet

bulb @33°C
Non-operating humidity

10-90% Relative humidity, max wet
bulb @35°C

Altitude

To 10,000 teet maximum

Maximum operating noise

44 dB at operator position

Shock .non-operating

30G., 30 ms, 1/2 sine wave

Vibration, operating

0.1G, 1/2 sine wave

5-500-5 Hz, 1 oct/min
sine sweep
Vibration, non-gperating

5-300 Hz. 1 oct/min sine sweep

1.19G, 1/2 sine wave

SYSTEM OVERVIEW 2-5

2.4 Physical Dimensions
Table 2-4 lists the physical dimensions of the system box.

Table 2-4. Physical Dimensions

Attribute

Spacification

Width

i .14 inches (410 mm)

Height

3.54 inches (30 mm)

Length

15.55 inches (396 mm)

Weight

17.08tbs (7.75kg)

2.5 Power Requirements
Table 2-5 lists the power requirements for the system box.

Table 2-5. Power Requirements
Voltage Source

100-120 V ac

220-240 V ac

Maximum Range

88-132V ac

176-264 V ac

Input Current

1.5A

Frequency Limits

47-63 Hz

Power Factor

0.6 min.

0.5 min.

Inrush Current

45A max.

Outlet Rating

2-6

SYSTEM OVERVIEW

2.6 System Board Current Requirements
Tabie 2-6 lists the nominal current requirements for the system board and
the parts that obtain power from the system board.

Table 2-6. Current Requirements

Assemblies

+5.0Vdc -5Vdc

+12.0Vdc -12.0Vdc

MB of system memory

1.68A

0.1A

1.2 MB floppy disk drive

0.46A

0.54A

1.44 MB floppy disk drive

IDE fixed disk drive

0.3A

Per Add-on Slot

0.05A

05A

0.05A

System board with 8

3
SYSTEM BOARD
This chapter provides an overview of the system mamn logic board, which
includes

20MHz or 25MHz 80386sx microprocessor

VLS182C386SX Industry Standard Architecture (ISA) chip set

CHIPS 82C712 Universal Peripheral Controller

e«

Keyboard/Mouse Controlter

VGA Video Controller

80 ns (or faster) Dynamic Random Access Memory (DRAM)

64 KB of Read-only Memory (ROM)

3-1

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SYSTEM BOARD 3-3

In addition, the system boards support:

One 16-bit ISA expansion siot

One 15-pin Video port

Two 9-pin serial ports

One 25-pin parallel

One 34-pin tloppy disk controlier header

One 48-pin IDE header

6-pin (mini-DIN) keyboard and mouse connectors

Three system status LED indicators

One 115 watt power supply

The remainder of this chapter provides a brief description of the hardware
components and major features for each system board.

3.1 DECpc 320sxLP/325sxLP System Board Features
This section provices detailed descriptions relating to the hardware

components and major features of each DECpc 320sxL.P/325sxLP system
board (see Figure 3-2).

3.1.1 80386SX Microprocessor
The B0386SX microprocessor is a 32-bit CPU with a 16-bit external data
bus and a 24-bit externa! address bus. The 80386SX microprocessor
runs at a clock speed of 20/25 MHz, which results in a system speed of
50/40 as per clock cycle.

SYSTEM BOARD

82331
{.S.A. Bus

CONTROLLER

[ eios

EPROM

8042
KEYBOARD

SYSTEM DATA BUS

CONTROLLER

SYSTEM ADDRESS BUS

82320
SYSTEM

SYSTEM CONTROUSTAUS BUS

387SX NPX

{OCAL CPU BUS

386Sx CPU

%
%
%

LOCAL DRAM

3-4

CONTROLLER

82C712
PERIPHERAL

Senal/Parallel
Port, HDC .FDC

OAK 067
VGA
CONTROLLER

High Resolution

6-biVS12K Video
Ram

INDUSTRY STANDARD ARCHITECTURE (ISA) PC/AT EXPANSION BUS

Figure 3-2. DECpc 320sxLP/325sxLP Block Diagram

SYSTEM BOARD 3-5

3.1.2 82C386SX ISA Bus Chip Set
The 82C386SX chip set consists of an 82C331 I1SA bus controller and an
82C320 system controller/data buffer. Together, these components are
responsible for controlling all addressing and data transmissions to and
from the ISA bus.

3.1.3 82C712 Universal Peripheral Controller
The 82C712 provides one printer port, two 16450 UARTs, IDE AT hard

disk interface, and floppy disk controfier .

3.1.4 OTI-067 Video Graphic Controller
The OTI-067 is a single chip Video Grapbhics Controller compatible with

the IBM VGA standard. It provides a high resolution of 800x600 with 256
colors and 1024x768 with 16 colors.

3.1.5 DRAM
The system supports up to 32MB of system DRAM through the use of

eight SIMM sockets located on the main logic board. The SIMM sockets
are divided into four banks (designated as bank 0 through bank 3).
System memory can be implemented using either 1MB or 4MB SIMMs
within each bank. The minimum system memory configuration is 2MB.

1.1.6 ROM
The system board ROM is one 64 KB EPROM. The EPROM contains the

system BIOS, a Power-On Self Test (POST), and the Setup Utility. The
BIOS initializes the DRAM and loads the operating system. The system
BIOS afso contains a shadow option. This option, when enabled, increases system performance by placing ROM instructions into highspeed DRAM. POST tests system hardware and the Setup utility aliows
you to set system configuration parameters.

1.1.7 /O Ports
There are three /O ports: one 25-pin parallel printer port and two 9-pin
serial (RS232) communication ports.

3-6

SYSTEM BOARD

3.1.8 System Status LED Indicators
The DECpc 320sxLP/325sxLP system provides three system status LED
indicators. When on, they indicate power On/Off, Fixed disk activity, and
CPU speed.

3.1.9 System Board Configuration Setting

Jumpers can be configured differently to accommodate different system .
requirements. Table 3-1 defines the jumper settings for the DECpc

320sxLP/325sxLP.

SYSTEM BOARD 3-7

Table 3-1. Configuration Setting
Feature

Description

Jumper Setting

J1: COM2 address

Disable

2 & 3 short, 5 & 6 short

selection

238H

2 & 3 short, 4 & 5 short

2F8H (defauit)

1 & 2 short, 4 & 5 short

J2: On board FDC

Enable (defautt)

14 2 short

Disable

2 & 3 short

J3. COM1 address

Disable

2 & 3short, 5 & 6 short

selection

338H

2 & 3 short. 4 & 5 short

3F8H (defautt)

1 & 2 short, 4 & 5 short

J4. Onboard IDE

J5: LPT1 address
selection

Enabie (detault)

18& 2 shor

Disable

2 & 3 short

Disable

2 & 3shon. 5 & 6 short
1& 2 shon, 5 & 6 short
2 & 3short, 4 8 5shont

378H
3BCH
278H (default)

1 & 2 short. 4 & 5 shont

Display adapter

VGAJEGA/MONO (detault)

1 & 2 short

Setting

CGA

2 & 3 shon

J7: CMOS discharge

Normal (default)
CMOS Discharge

1 & 2 short
2 & 3 short

Color (default)

1 & 2 short

Mono

2 & 3 short

J10: Interlaced/
Non-interlaced

Non-interlaced
Interlaced (default)

2 & 3 short

J11: On board VGA

Enable (default)
Disable

1 & 2 short
2 & 3 short

J17. 387sx coprocessor

Sync {detautt)

1 & 2 shont

Asyn

2 & 3 short

Co-processor Ready

Reserved

Monitor type

clock mode select
W1: Manufacturing

Setting # 1
W2: Manufactuting

Setting # 2

1& 2 short

Selection
PipelineMon-pipeline

Reserved

4
CENTRAL PROCESSING CORE
The following text describes the B0386SX microprocessor's basic archi-

tecture and the two modes of operation. This section concludes with brief
descriptions relating to the signais generated by the microprocessor.
The 80386SX micropracessor is a 32-bit CPU with a 16-bit external data

bus and a 24-bit external address bus
The 80386SX microprocessor consists of a Central Processing Unit, a
Memory Management Unit, and a Bus interface (Sec Figure 4- 1)

4-1

4-2 CENTRAL PROCESSING CORE

Efecs
fiechve Adrees

‘

Registers

and
_l‘> Limit
Attribute
3

Test Unit

Bus
- Contro

Pagwng Unt ,

equritiestz |, _
Prio
;
:;,5
Adder ;
Adder
Descriptor| ¥l Page

Protection

arannpuert
Segr3-I

PLA

Cache

Control &
» Attribute
BLA

gE
i

5 L‘$ Driver
2
§8 PipeContMUXiinerol/ |__
§g
ns- r
conTraers
Pratetcher/
ress |

L—fl ST

on
ShiBahagfteoerr | Sats :> SeqDecuenandodcine g|1 |_|instrDecucti
oder i CheLimicket r
/
- c":m
MuttDiviply
n
ide | Flags L
Register <—:———- Control <: instruction é'_'—_‘ Qc::ee
T} ALY

Control

instruction Pracose

Decwcased ALU Bus

instruction Preteich

Figure 4-1 80386SX Pipeline 32-bit Microarchitecture

CENTRAL PROCESSING CORE 4-3

4.1 Central Processing Unit
The Central Processing Unit (CPU) consists of the execution unit and
instruction unit. The execution unit contains the eight 32-bit general

purpose registers used for both address calculation and data operations.
The execution unit also contains a 64-bit barrel shifter that speeds up

shift, rotate, multiply, and divide operations. The instruction unit decodes
the instruction opcodes and stores them in the decoded instruction queue
for immediate use by the execution unit.

4.2 Memory Management Unit
The Memory Management Unit (MMU) consists nf a segmentation unit

and a paging unit. Segmentation manages the logical address space by
providing an extra addressing component that allows the relocation and

sharing of code and data. The paging unit operates beneath, and I1s
transparent to, the segmentation process to allow physical address space
management.

4.3 Modes of Operation
The 80386SX microprocessor has twe modes of operation: real address

mode (real mode) and protected virtual address mode (protected mode).

In real mode, the B0386SX microprocessor operates as a fast 808¢,,, and

sets up the CPU for protected mode operation. Protected mode provides
access to the sophisticated memory management paging and privilege
capabilities of the microprocessor. In protected mode, software can
execute a task switch and enter into a virtua! 8086 mode.

In this virtual

mode 8086 semantics are used and the application program or operating

system executes as if running on an 8086 microprocessor.

4.4 Signal Definitions
Table 4-1 lists a signal name for the 803865X microprocessor.

4-4

CENTRAL PROCESSING CORE
Table 4-1. 80386SX Signal Name

Pin Number
1

803865X

Signal Name
Do

2
3
4
5

Vss
HLDA
HOLD
Vss

3]
7
8
9

-NA
-READY
Vce
Vee

Vee

11
12
13
14
15

Vss
Vss
Vss
Vss
CLK2

16
17
18
19

-ADS
-BLE
A1
-BHE

21
22

Vece
Vss
M/-10
D/-C
W/-R

24
25

CENTRAL PROCESSING CORE 4-5

Table 4-1. (Cont.) 80386SX Signal Name

Pin Number

80386SX
Signal Name

-LOCK

27
28

NC
-FLT

Vce

RESET

-BUSY

Vss

-ERROR

37
38

PEREQ
NMI

Vce

INTR

Vss

NC
NC

Vce

Vss

4-6

CENTRAL PROCESSING CORE

Table 4-1. (Cont.) 80386SX Signal Name

Pin Number

80386SX
Signal Name

51
52
53
54
55

A2
A3
A4

Vee

58
59
60

A8
AQ
A10

61
62
63
64

At1
A12
Vss
A13

A5
AB

A14

A15

Vss

68
69
70

Vss
Vee
A16

71
72
73
74
75

Vce
A17
A18
A19
A20

CENTRAL PROCESSING CORE 4-7

Table 4-1. (Cont.) 80386SX Signal Name

Pin Number

80386SX
Signal Name

A21

Vss

A22

A23

D15

D14

D13

Vece

Vss

D12

87
88

D11
D10

89
90

Do
D8

Vce

92
93
94
a5

D7
D6
D5
D4

96
a7
98
99
100

D3
Vee
Vss

D2
D1

4-8

CENTRAL PROCESSING CORE

4.5 Signal Description
A23-A1 (Outputs)
Address Bus: Outputs physical memory or port I/O addresses.
-ADS (Active Low; Output)
Address Status: Indicates that a valid bus cycle definition and address

(W/-R, D/-C, M/-IO, -BHE, -BLE, and A23-A1) are being driven at the
MICroprocessor pins.

-BHE, -BLE (Active Low; Outputs)
Byte Enables: Indicate which data bytes of the data bus take part in a bus
cycle.

-BUSY (Active Low; Input)
Busy: Signals a busy condition from a processor extension.
CLK2 (Input)
CLK2: Provides the fundamental timing for the microprocessor

D15-DO (Inputs/Outputs)
Data Bus: inputs data during memory, /O, and interrupt acknowledge
read cycles; outputs data during memory and I/O write cycles

D/-C (Output)
Data/Control: A bus cycle definition pin that distinguishes data cycles.
either memory or 1/O, from control cycles which are: interrupt acknow!-

edge, halt, and code fetch.
-ERROR (Active Low: input)
Error: Signals an error condition from a processor extension.
-FLT (Active Low: Input)
Fioat: An input which forces all bi-directional and output signals, including

HLDA, to the three-state condition.
HLDA (Active High; Output)

Bus Hold Acknowledge: Output indicates that the microprocessor has
surrendered control of its logical bus to another bus master.

CENTRAL PROCESSING CORE 4-9

HOLD (Active High; input)
Bus Hold Request: input allows another bus master to request control of
the local bus.

INTR (Active High; Input)
Interrupt Request: A maskable input that signals the microprocessor to

suspend execution of the current program and execute an interrupt
acknowledge function.
-LOCK (Active Low; Output)
Bus Lock: A bus cycle definition pin that indicates that other system bus
masters are not to gain control of the system bus while it is active.

M/-10 (Output)
Memory/IO: A bus cycle definition pin that distinguishes memory cycles
from input/output cycles.

-NA (Active Low; Input)
Next Address: Used 1o request address pipelining.

NC
No Connect: Should always be left unconnected.

NMi (Active High; input)
Non-Maskable interrupt Request: A non-maskable input that signais the

microprocessor to suspend execution of the current program and execute
an interrupt acknowledge function.

PEREQ (Active High; Input)
Processor Extension Request: Indicates that the processor has data to be
transferred by the microprocessor.

-READY (Active Low; Input)
Bus Ready: Terminates the bus cycle.
RESET (Active High; Input)
Reset: Suspends any operation in progress and places the microprocessor in a known reset state.

4-10

CENTRAL PROCESSING CORE

Vee (Active High; Input)

System Power: Provides the +5 V nominal DC supply input.
Vss (Input)

System Ground: Provides the 0 V connection from which all inputs and

outputs are measured.

W/-R (Output)

Write/Read: A bus cycle definition pin that distinguishes write cycles from
read cycles.

o
82C386SX ISA CHIP SET
The 82C3865X ISA Chip Set contains an 82C320 systern controller/data

This chapter

buffer and an 82331 ISA bus controlier, (see Figure 5-1)
describes each of these in detail.

82C3B6S5X ISA CHIP SET

TCLK2
cLock
TURBO &
BUSOSC

‘ TYYY Y YY VY

CLK2
BUSCLK

DMAHLDA

i 114,

HLDA

HOLD

DMAHRQ
OUT1
-REFRESH

HRQ

ARBITER

M/-I0
D/-C,
W/-R

-CHSO/-MW,
-CHS1/-MR,
CHM/-10

BUS

-BRDRAM
-EALE
-RAMW
-ROMCS

CONTROL

0sC
-CHREADY
-ADS

MA10 - MAO

ADDRESS BANKhQS

A23-A1

BANKRQO p

-CASI7 -CASI0

PHIT/AMISS

l“”i

DECODE

DRAM |

-READYI
-BHE,
-BLE
-IOR.-IOW

®1

CONFIG

D15-D0 «t——p»] REGS
-ERRORNPX,
-BUSYNPX,
PEREQNPX

1
—#>|

-SLP/MISS

LOGIC

DRAMRDY

[

.——’

-RASBK3-RASBKO

-CAS7-CASD

REMAP

-RAS13
CONTROL {.RASIO

1
SWITCH

-SLPMISS

-BUSYCPU.

PEREQCPU.
RESCPU.
RESNPX
-NPCS
tRQ13

-BLKAZ0
RESCPU

NPX
INTFC

A23

A20GATE

-READYO

READY CNTL

5-2

PORT |

RESET

RSTDRV

CNTL

DATA
BUFFER

Figure 5-1. 82C386SX Functional Block Diagram

82C386SX ISA CHIP SET 5-3

5.1 82C320 System Controller/Data Buffer
The 82C320 system controller provides built-in paged mode operation,
two- or four-way interleaving, programmable DRAM timing, system board
and ISA siot retresh, tull EEMS support, shadowing, and provides the bus
clock and signalling interface to the 82C331 ISA bus controller (see
Figure 5-2). The 1/O address of 82C320 index Register and Data Port
Register is ECh and EDh respectively. Each of the 82C320 Indexed

Contfiguration Registers described in the following sections is accessed
first by writing its address to the Inciex Register at {/O address ECh, then

by accessing the data port at /O address EDh.
The system controller/data buffer consists of the following
¢

A CPU interface

AnSA bus/system controller communication channel

A DRAM support subsystem

VO control registers

Halt/shutdown detection

Data Buffer

The foliowing sections describe each of these functions in detail.

5-4

B2C3865X ISA CHIP SET

TCLK2 ]
TURBO —

- CLK2

CLOCK

et BUSCLK

BLSOSC —— Y

-] ARBITER
o~

—> HRQ

M/-10
D/-C,
W/-R
0sC
-CHREADY

BUS

—-]

—- -BRDRAM

> -EALE
-RAMW

—

—i

o—--+—+o-{ ADDRESS | BANKRQS
|

[’ DECODE

-CHSO/-MW,
“CHS1/-MR.
CHM/-I0

_—

CONTROL

-ADS

A23-A1

> DMAHLDA

o] HOLD

’

HLDA
DMAHRQ
ouT
-REFRESH “"’*

Saan

-RASBK3-

—a| DRAM [ac
TM Remae|
> -RASBKOD

| LOGIC
-Rasio

| CONTROL| -

-BHE.

-BLE

D15-D0

DRAMRDY

-READYI

-1OR.-IOW

1 CONFIG |SLPMISS\————%——» READY CNTL

A23
A20GATE

-READYO

-SLPMISS

-BUSYCPU.

PEREQCPU,

—»- RESCPU.

| NPX

—

RESNPX
-NPCS
"3

-BLKA20

INTFC

—

PORT

| RESET
| CNTL

RSTDRV
-RC
-TRI —_—
CLK2IN —_—

2B6/-3865X —_—

-CAS7-CASO

SWITCH

21 Reas

-ERRORNPX,
-BUSYNPX ———
PEREQNPX

MA10 - MAO

CASI7-

PHIT/-MISS

-ROMCS

- RESCPU

DATA
BUFFER

Figure 5-2. 82C320 System Controller Functional Block Diagram

82C386SX ISA CHIP SET 5-5

5.1.1 CPU Interface
The VL82C320 handles the top level control interface between the synchronous local and memary data bus and the asynchronous slot data

bus. Itintercepts the CPU's bus status and address signals, and decodes the bus access. It then decides whether to handle the bus request

itself, or send it off to the VLB2C331 ISA Bus Controller.

5.1.2 ISA Bus/System Controller Communication Channel
The asynchronous interface to the bus controller is handied by the group

of signals listed in Table 5-1. These signals define the type of bus cycle
to be run.

Table 5-1. Bus/System Controller Bus Cycle Types

CHM/-I0

-CHS1

“CHSO

Bus Cycle

-INTA

-IOR

0
0

1
1

0
1

-IOW
Reserved

-REFRESH

-MEMR

-MEMW

Reserved

5-6

82C386SX ISA CHIP SET

5.1.3 DRAM Support Subsystem
The VL82C320 supports up to 32 Mbyte of DRAM on the system board in
four 16-bit banks. Each byte contains its own parity bit for a total of 18

bits per bank. A single bank can consist of 1M or 4M DRAMs.
Both types of DRAM can be mixed between the four memory banks;
however, they cannot be mixed within the same memory bank.
The VL82C320 supports four banks by providing four -RASBK signals and

eight -CAS signals. This allows direct drive with no external buffering.

Several configuration registers internal to the VLB2C320 are used to

control the memory map. interleaving, DRAM timing and page mode.

These features are discussed in the following sections. Since interleaving
requires pairs of banks, various controls described next act on memory in

bank pairs. The short hand notation bank A is used when describing
something that affects DRAM banks 0 and 1 as a set. Similarly, bank B is
used to describe DRAM banks 2 and 3 as a set.

5.1.3.1 Memory Mapping
The memory controlier supports the twelve DRAM memory maps listed in
Table 5-2. The memory column lists the total amount of DRAM available in

each memory map. The RAMMARP (4:0) column indicates the hex value
written in bits four through zero from the RAMMAP indexed configuration
register (refer to Table 5-3). Each combination listed is addressable in

each of the four 16-bit memory banks. Note that memory banks zero
through three are referred to as logical banks when internally addressed
by the VL82C320. The actual system board memory banks, when

accessed internally, might differ depending on the value stored in the

indexed configuration register RAMMOV (refer to Table 5-4). Incase of a

partial or total DRAM bank failure, the remaining function2! DRAMs can
be switched into an alternate, valid iogical memory map by reprograming RAMMOV and RAMMAP together. Table 5-5 shows the sixteen
logical to physical mappings that are available. In the top row of this

chart, the numbers 3, 2, 1 and 0 directly under "DRAM BANK MAPPING’
refer to the four physical DRAM memory banks. In the sixteen rows

beneath, the code that must be programmed into the RAMMOV register
bits 4-0 is shown on the left side of the chart. On the right side 13 shown
the logical bank that is mapped to the corresponding physical bank
shown in the top row. Figure 5-3 shows an example of upgrading frem
one 2MB DRAM bank to two 2MB banks. When RAMMOV =00000, the
default condition, the logical banks are directed to the same physical
.
bank numbers.

82C3865X ISA CHIP SET 5-7

RAMMAP=7

RAMMOV=0

LOGICALBANKO

BANK 0 =2M DRAMS

LOGICALBANK

BANK 1 =2M DRAMS

DRAM

MEMORY
CONTROL

REMAP
CONTROL

LOGICALBANK2

LOGICALBANK3

BANK 2 =EMPTY

Figure 5-3, DRAM Remap

BANK 3 =EMPTY

5-8

B82C386SX ISA CHIP SET

Table 5-2. DRAM Mapping

Bank0

Bank1

Bank2

Bank3

Memory MB RAMMAP (4:0)

1MBx2

iMBx2

1MBx2

iMBx2

1MBx2

1M Bx2

4MBx2
1MBx2

4MBx2

iMBx2

1MBx2

4MBx2

aMBx2

4MBx2

1MBx2

4MBx2

4MBx2
4MBx2

4MBx2

24
32

16
17

4MBx2

Table 5-3. RAMMAP(03h R/W) Indexed Configuration Register
(Default = EOh)

Bit

Function

7:5

Always one

4:0

DRAM memory map code

Table 5-4. RAMMOV(04h R/W) indexed Configuration Register .
(Default = FOh)

Bit

Function

7:5

Always cne

4.0

RAMMOV code

82C3865X ISA CHIP SET 5-9

Table 5-5. REMAP Configuration Register Code

RAMMOYV Code

DRAM
Bank Mapping

0
o

1
1

0
0

O
1

3
2

1
3

0
0

2
1

Physical DRAM Banks

Logical DRAM Banks

5.1.3.2 Paged Mode and interleaving
DRAM operates in paged mode or interleaving. Both options are selected

by programming the RAMMAP and RAMSET indexed configuration
registers (refer to Tables 5-3 and 5-6, respectively). Paged mode is

enabled or disabied for each pair of memory banks independently,
Interleaving requires pairs of memory banks. Two-way interleaving s

automatically enabled whenever both banks of a pair are populated with
like DRAM types. It all four banks are populated with like DRAMs, fourway interleaving automatically occurs when both bank pairs are pro-

grammed to interleave on the same bit. If not, two-way interleaving

occurs. If the four banks are not populated with like DRAMS, two-way
interleaving occurs on pairs that are of the same type. in a machine with

three banks populated, the first two banks two-way interleave if they are of
the same type. The third does not interieave. Table 5-7 shows the
R

e UG

5-10

B2C386SX ISA CHIP SET

Table 5-6. RAMSET(05H R/W) indexed configuration |
(Default = 3Ch)
Bit

Function

7:6

DRAM drive current on MAO-MA10 and -RAMV
00 = 150 pF drive (Default)
01 = 300 pF drive
10 = 450 pF drive
11 = 600 pF dnve

ESTART
0 = Early Start Enable
1 = Early Start Disable (Default)
Always one

Bank A Page mode
0 = disabled
1 = enabled (Default)
Bank B Page mode
0 = disabled
1 = enabled (Default)

Bank A interleave

0 = Interleave on bit 1 for ail DRAMs (Default)
1= Interieave on bit 10 for all DRAMs

Bank B interleave

0 = Interleave on bit 1 for all DRAMs (Default)
1 = Interleave on bit 10 for alt DRAMs

B2C386SX ISA CHIP SET 5-11

Table 5-7. Automatic interleave VS. Memory Map
Bank

Yes No

Bank

BankA Address Mode

BankB Address Mode

Linear

No No

N/A

Yes Yes 2-Way Interleave

No No

N/A

Yes Yes 2-Way Interleave

Yes No

Linear

Yes Yes 2-Way Interleave 0 and 1*

Yes Yes 2-Way Interieave 2 and 3"

This is for the case where Banks A and B contain different types of
DRAMs. For memory maps 0Bh, and 17h all four banks contain the
same DRAM type and four-way interleaving is used if both bank pairs
interleave on the same bit.

5-12

B2C3865X ISA CHIP SET

5.1.3.3 DRAM Timing Parameters
Four configurations registers are used to program the DRAM timing

parameters. RASTMA allows programming of RAS ADDSEL delay, tRCD,
tRP, and tRAS parameters tor banks 0 and 1. RASTMB performs the
same functions for banks 2 and 3. CASTMA allows prograrnming of tCST,
tCP, tCASR, and tCASW for banks 0 and 1. CASTMB performs the same
functions for banks 2 and 3. Refer to Table 5-8 and 5-9 for specific bit
allocations. Figures 5-4 and 5-5 show the relationship between these
programmable timing signals for page and non-page-mode operation.

Table 5-8. RASTMA(07h R/W) and RASTMB(09h R/W)

Configuration Registers (Default = FFh)
Bit

Function
RAS address select

0= 1/2CLK2
= 1

CLKZ (Default)

tRCD

0=1CLK2
1 = 2 CLK2s (Default)
Always one

tRP

00 = 2 CLKZ2s
01 = 3CLK2s
10 = 4 CLKZ2s
11 = 5 CLK2s (Default)

tRAS

010 = 2 CLK?Zs
011 = 3 CLKZs
100 = 4 CLK2s
101 = 5 CLK?2s
110 = 6 CLK?Z2s
111 = 7 CLK2s (Defautlt)

82C3865X ISA CHIP SET 5-13

Table 5-9. CASTMA(08h R/W) and CASTMB (0Ah R/W)

Contiguration Registers (Default = B7h)
Bit

Function

7:6

tCASW

00 =1 CLK2
01=2CLK2s

10 = 3 CLK2s (Default)
11 = 4 CLK2s
5

tCST
0 =3CLK2s

1 = 4 CLK2s (Detfault)

4:3

tCP

00 = 1 CLK2
01 =2CLK2s
10 = 3 CLK2s (Default)
2

Always one

1:0

tCASR

01 =2CLK2Zs

10 = 3CLK2Zs
11 = 4 CLK2s (Default)

00 =5CLK2s

5.1.3.4 DRAM Refresh
The VL82C320 performs on-board DRAM refresh and controls both on-

and off-board refresh timing in alf modes. Refresh may be performed in a
coupled mode or decoupled mode. In coupled mode, refresh timing for
both system board and slot bus refreshes is performed in a synchronous
manner. In decoupled mode, the VL82C320 has complete control over
the timing of on-board DRAM refresh and off-board refresh but the timing

of each is independent. Configuration register REFCTL is used to program the specific modes (refer to Table 5-10). When set to coupled

refresh mode (D7 = 0), the VLB2C320 refresh circuitry controls system
board refresh and slot bus refresh in a synchronous manner. in that

mode, the division specified by bits 2-0 applies to on- and off-board

5-14

B2C386S5X ISA CHIP SET

t—————— AP ——-—-1

msaxx; -

«:p%

—

casxo

‘Ji

Z}ss:

t/—

FIGURE 5-4. -RASBK/-CAS TIMING MODEL

3865

nornf

[ R 7] SN

FIGURES-5. -CAS START TIME(tCST) TIMING MODEL

WNoie : iCST appiies to write cycies only and equals 3 or 4. During
read cycles, CAS start time defaults to zero CLK2's for
pipelined or two CLK2's for non-pipelined SX or 286 mode. Iff
ESTART bit in RAMSET register is programmed inactive (1),
then add one to start times just mentioned for reads only. This
is the earliest time -CAS can start for read cycles. Actual -CAS

start time may be delayed due to -CAS pre-charge or -RASBK
to -CAS delay time not yet met.

82C386SX ISA CHIP SET 5-15

refresh and bits 6-4 have no effect. Only in decoupled mode (D7 = 1), do
the three bits 6-4 of the VLB2C320's REFCTL register apply. In
decoupled mode, the VL82C320 refreshes the on-board DRAM independent of the Bus Controlier's refresh of the slot bus resident memory. It uses
the division rate specified in those bits whiie the siot bus refresh is performed at the rate specified by the code in bits 2-0.

Table 5-10. REFCTL (05h R/W) Contiguration Register
(Default = 00h)
Bit
7

Function
Retresh Control

0 = Coupled Refresh (Default)
1 = Decoupled Refresh
6:4

Slow refresh (system board)
000 = + 1 (Default)

001 =+ 2

D11=+8

100=+ 16

10/16 {/O
0 = full 16-bit decode is performed (Default)
1 = 10-bit decode is performed

2:0

Slow refresh (slots)
000 = + 1 (Default)
00t =+2
010=+4
011=+8
100=+ 16

5-16

82C3865SX ISA CHIP SET

5.1.4 VO Control Registers
Table 5-11 lists the 1/0 port addresses for the system controller registers.
Table 5-11. Dedicated /O Control Registers
Port

Address

Function

E8h
ESh
EAh
EBh
ECh
EDh
EEh

EMS index Register
EMS Active Set
EMS Data Port Low Byte
EMS Data Port High Byte
Configuration index Register
Configuration Data Port
Fast A20

EFh

Fast Reset

FOn

Coprocessor Busy Clear

Fth
Fan
FSh

Coprocessor Reset
Slow CPU

F8h

Coprocessor

Fast CPU

Fah

Configuration Disable

FAR

Coprocessor

FBh

Configuration Enable

FEh

Coprocessor

FCnh

Coprocessor

82C386SX ISA CHIP SET 5-17

5.1.5

Halt/Shutdown Detection
The system controller detects and acts on 80386SX microprocessor halt
and shutdown conditions. The signal levels listed in Table 5-12 determine

the existence of hait and shutdown conditions.
Table 5-12. 80386SX Halt/Shutdown Detection
Mode

Halt
Shutdown

Signal Levels

M/-10

D/-C

W/-R

A1l

5.1.6 Data Buffer
The VL82C320 data buffer functions separates the data bus into three

buses, D bus, SD bus and the XD bus. The D bus is the CPU's local data
bus. The VLB2C320 and numeric coprocessor are connected to the D

bus. BIOS ROMs are connected to the D Bus (16-bit) or the XD bus (8bit). The SD bus is the 16-bit slot bus and the XD bus is an 8-bit bus for
on-board peripherals such as the VL82C320 registers and the I1SA Bus
Controller. These buses can be controlied by either the CPU, a DMA
controller or a bus master.

5.1.7 Signal Definitions
Table 5-13 lists a signal name for the 82C320 .

5-18

82(C3865X ISA CHIP SET

Table 5-13. 82C320 Signal Name
82C320

Pin Number
1

Signal Name
vDD

2
3

CLK2IN
-READYI

HLDA

CLK2

-SLP/MISS

-READYO

8
9
10

HRQ
RESCPU
-BUSYCPU

1
12
13
14

PEREQCPU
D15
D14
D13

D12

D11

D10

18
19

D9
VSS

21
22

PAR1
D7

24
25

D5
D4

27
28

29
30

D2
D1

Do
PARO

82C3865X ISA CHIP SET 5-19

Table 5-13. (Cont.) 82C320 Signal Name

Pin Number

82C320
Signal Name

VSS

vDD

33
34

MA10
MAS

MA8

VSS

MA7

MAGE

MA5

MA4

vDD

VSS

MA3

MA2

MA1

VSS

MAQ

-RAMW

-CAS7

-CAS6

-CAS5

-CAS4

-CAS3

-CAS2

VSS

-CAS1

57
58
59
60

-CASO
vbD
-RASKB3

-RASKB2

5.20

82C3865X ISA CHIP SET

Table 5-13. (Cont.) 82C320 Signal Name
82C320

Pin Number

Signal Name

61
62
63
64
65

-RASKB1
-RASKBO
-ROMCS
-REFRESH
RESNPX

66
67
68
69
70

IRQ13
-NPCS
PEREQNPX

71
72
73

TCLK2
0sC
BUSOSC

vDD

A20GATE

TURBO

77
78
79

-RC
286/-33865X
-TRI

-ERRORNPX
-BUSYNPX

-CHREADY

81
82

VSS
VSS

‘83
84
85

DAMHRQ
OuTH
-IOR

86
87
88
89

-IOW
RSTDRV
SDLH/-HL
-SDSWAP

-XDREAD

82C3865X ISA CHIP SET 5-21

Table 5-13. (Cont.) 82C320 Signal Name

Pin Number

82C320
Signal Name

91
92
93
94
95

-LATLO
-EALE
-CHS0/-MM
-CHS1/-MR
CHM/-10

-BLKA20

97
98
99
100

BUSCLK
DMAHLDA
-BRDRAM
-PARERRC

101
102

xD7
XD6

103

XD5

104

XD4

105

XD3

106
107
108

XD2
XD1
V3S

109

XDO

110

vDD

111
112
113

SD15
SD14
SD13

114
115

SD12
VSS

116
117
118
119
120

SD11
SD10
SD39
SD8
VSS

5-22

b2C386SX ISA CHIP SET

Table 5-13. (Cont.) 82C320 Signal Name

Pin Number

82C320
Signal Name

121

vDOD

122

So7

123

SDS

124

SD5

125

SD4

126

VSS

127

SD3

128

SD2

129

SD1

130

SDo

131

VSS

132

A23

133

A22

134

A21

135

A20

136

A19

137

A18

138

A17

139

A16

140

A15

141

A14

142

A13

143

144

A12
A1

145

A10

146

147

148

149

1560

82C3865X ISA CHIP SET 5-23

Table 5-13. (Cont.) 82C320 Signal Name

82C320

5.1.8

Pin Number

Signal Name

151

152

153

154

155

-BHE

156
157

W/-R

158
159
160

D/-C
M/-10
-ADS

-BLE

Signal Description

5.1.81 CPU Interface Signals
A23-A1 (I-TTL)
Address bits 23 through 1 - When the CPU s bus master and HLDA 1s

active, these signals are driven by the Bus Controller
«BHE (I-TTL)

Byte High Enable, active low - This signal is driven by the CPU or the Bus
Controller. it is used to select the upper byte of a 16-bit wide memory
location.

-BLE (I-TTL)
This signal is used to select the lower byte of a 16-bit wide memaory
location.

W/-R (1-TPU)
This signal is decoded with the remaining control signals to indicate the
type of bus cycle requested.

5-24

82C386SX ISA CHIP SET

D/-C (I-TPU)
This signal is decoded with the remaining control signals to indicate the
type of bus cycle requested.

M/-10 (I-TPU)
Memory active low |/O enable - M/-1O is decoded with the remaining
control signals to indicate the type of bus cycle requested.
-ADS (I-TPU)
Address Strobe, active low - This signal is driven by the 386SX as an
indicator that the address and control signals are valid. 1t is used internally to indicate that the address and command are valid and determine

the beginning of a bus cycle.

CLK21N (I-CMOS)
This is the main clock input to the VL82C320 and it should be connected
to the CLK2 signal that is output by the VL82C320. This signal is used
internally to clock the VL82C320 logic.
TCLK2 (1-CMOS)

This input is connected to a crystal oscillator whose frequency is equal 1o

two times the system frequency. The CMOS level is used to generate
CLK2 output and optionally, bus ciock.

CLK2 (0)
This output signal is CMOS level and generated from TCLK2 signal. It
connects the CPU and other on-board logic for synchronization.

-SLP/MISS (IT-OD)
As a "power on reset” default, this signal is an output that is equal to -

SLEEP[7]. -SLEEP[1]. When configuration register CTRL[O] = 1, this pin
becomes a MISS input for use with a future VLSI product.
-READYO (0O)

Ready Out, active low - This signal indicates that the current cycle is
complete. !t is generated from the internal ORAM controller or the synchronized version of -CHREADY for slot bus accesses. The culmination
of these ORed READY signals is sent to the CPU and is also connected to
the VL82C320's -READYI input. This signal may be combined externally
with other READY sources.

82C3865X ISA CHIP SET 5-25

-READYI (I-TTL)
Ready Input, active low - This signal indicates the current bus cycle is
complete.

HLDA (I-TTL)
Hold Acknowledge, active high - This signal is issued in response to the
FiRQ driven by the VL82C320. When HLDA is active, the memory control
is generated from -CHS1/-MR and -CHSO/-MW.

HRQ (0)
Hold Request, active high - This signal indicates that a bus master, such
as a DMA or AT channel master, is requesting control of the bus. HRQ is

a result of the DMAHRQ input or a coupled refresh cycle. It is synchronized to CLK2 and internal clock.

RESCPU (O)
Reset CPU, active high - This signal is issued in response to the control

bit for software reset located in the Port A, read from |0 port EFh, RC and
RSTDRYV inputs and in response to VLB82C320's detection of a shutdown
command. In all cases it is synchronized to CLK2 and internal clock.
-BUSYCPU (O)

Busy CPU, active low - The state of -BIUSYNPX is always passed through
to -BUSYCPU indicating that the NPX is processing a command. On
occurrenice of an -ERRORNPX signal, it is latched and held active until

occurrence of a write to ports FOh, F1h, or RSTDRV.
PEREQCPU (O)
Processor Extension Request CPU, active high - An output signal generated in response to a PEREQNPX which is issued by the coprocessor to
the VL82C320. PEREQCPU is asserted on occurrence of -ERRORNPX

after -BUSYNPX has gone inactive. A write to FOh returns contro! of the

PEREQCPU signal to directly follow the PEREQNPX input.

5-26

B2C3865X ISA CHIP SET

5.1.8.2 On-Board Memory System Interface Signals
-RAMW (O-TTL)
RAM Write, active low - This signal is active during memory write cycles
and high at all other times.
MA10-MAO (O-TTL)
Memory Addresses 10 through O - These address bits are the row and
column addresses sent to on-board memory. They are buftered and
multiplexed versions of the CPU bus addresses.
-RASBK3 - -RASBKO (O-TTL)
Row Address Strobe, active low - These signals are sent to their respective RAM banks to strobe in the row address buring on-board memory
bus cycles. The active period for this signal is fully programmable

-CAS7 - -CASO0 (O)
Column Address, Strobe, active low - These signals are sent to their
respective RAM banks to strobe in the column address during on-board

memory bus cycles. There is a -CAS signal for upper and lower bytes of
each of the four 16-bit DRAM memory banks The active period for this
signal is completely programmable.

-REFRESH (IC-OD)

Refresh signal, active low - This output is used by the VL82C320 to initiate

an off-board DRAM refresh operation in coupled refresh mode.

decoupled mode. the Bus Controller drives refresh active 1o indicate to

the VLB2C320 that it has decoded a refresh request command and 1s
initiating an off-board refresh cycle.

-ROMCS (0)

ROM Chip Select - This is the on-board system BIOS ROM chip select

5.1.83 Coprocessor Signals
PEREQNPX (I-TPD)

Coprocessor Extension Request NPX, active high - This input signal is
driven by the coprocessor and indicates that it needs transter of data
operands to or from memory. For PC/AT -compatibility, this signal is also
gated with the internal ERROR/BUSY control logic before being output to
the CPU as PEREQCPU during NPX interrupts.

82C386SX ISA CHIP SET 5-27

-ERRORNPX (I-TPU)
Error NPX, active low - An input signal from the coprocessor indicating
that an error has occurred in the previous instruction. This signal is
internally gated and latched with -BUSYNPX to produce IRQ13.

-BUSYNPX (I-TPU)
Busy NPX, active low - An input signal that is driven by the coprocessor to
indicate that it is currently executing a previous instruction and is not
ready to accept another. This signal is decoded internally to produce IRQ

13 and to control PEREQCPU.

RESNPX (O)
Reset NPX - This output is connected to the coprocessor reset input

tis

triggered through an internally generated system reset or via a write 1o

port Fih. In the case of a systemn reset, the RESCPU signal is also activated. Write to port F1h only resets the coprocessor. A software FINIT

signal must occur after an F1h generated reset in a 386SX system,
otherwise, the 387SX is not initialized to the same state that a 287 is
placed in by a hardware reset alone. Optionally, the F1 reset may be

disabled by setting bit 6 of the MISCSET reqister to 1.

iIRQ13 (O)
Interrupt Request, active high - This output is driven to the Bus Controlier
to indicate that an error has occurred with in the coprocessor. This signal
is a decode of the -BUSYNPX and -ERRORNPX inputs.

<NPCS (O)
Coprocessor Chip Select - Provides decoding of the 287 coprocessor's i/

O space. This is the entire F8h to FFh region when Special Features are
disabled. When Special Features are enabled, only I/O accesses to F8h,
FAR, FCh, and FEh cause -NPCS to be active. This signal 1s a no connect
pin for 387SX operation, and reserved for future use in 386SX systems.

5.1.8.4 Bus Control Signals
-CHREADY (I-CMOS)
Channel Ready, active low - An input issued by the Bus Controlier as an
indication that the current channel bus cycle is compiete. This signal 1s

synchronized internally then combined with READY signals from the
coprocessor and DRAM controlier to from the final version of READY O
which is sent to the CPU.

5-28

B2(3B65X ISA CHIP SET

-CHS0/-MW (1-CMOS)
Channel Select 0 or Memory Write, active low - This signal is a de
the CPU's bus control signals and is sent to the Bus Controller. W
combined with -CHS1 and CHM/-IO and decoded, the bus cycle
defined for the Bus Controlier. Activation of HLDA reverses this s
become an input from the Bus Controlier. It is then a -MEMW sig
the DMA or bus master to access system memory.

-CHS1/-MR (I-CMOS)
Channel Select 1 or Memory Read, active low - This signal is a de
the CPU'’s bus control signals and is sent to the Bus Controller. V
combined with -CHS0 and CHM/-I0 and decoded, the bus cycle

defined for the Bus Controller. Activation of HLDA reverses this s
become an input from the Bus Controlier. Itis then a -MEMR sigr
the DMA or bus master to access system memory.

CHMW/-I0 (0)
Channel Memory /O - This signal is a decode of the CPU'’s bus ¢
signals and is sent to the Bus Controller. When combined with -C

and CHS1 and decoded, the bus cycle type is defined for the Bu
troller. Activation of HLDA reverses this signal to become an inp
the Bus Controller. It is then a -MEMR signal for the DMA or bus
access system memory.

-BLKA20 (O)
Block A20, active low - An output driven to the Bus Controller to ¢
vate address bit 20. 1t is a decode of ine A20DATE signal and P
indicating the dividing line of the 1 Mbyte memory boundary. Po

may be directly written or set by a read of I/O port EEh.
BUSOSC (I-TTL)

Bus Oscillator - This signal is supplied from an external oscillator
supplied to the Bus Controller when the VL82C320's internal conf
reqisters are set for asynchronous slot bus mode.

BUSCLK (0)

Bus Clock - This is the source clock used by the Bus Controller tc
the slot bus. It is two times the AT bus siock (SYSCLK). It is a pr
mable division from TCLK2 or BUSOSC.

82C386SX ISA CHIP SET 5-29

DMAHRQ (I-CMOS)
DMA Hold Request, active high - This signal is an input sent by the Bus
Controller. it is internally synchronized by the VL82C320 before used to
generate HRQ.

DMAHLDA (0)
DMA Hold Acknowledge - An output sent to the Bus Controlier which
indicates that the current hold acknowledge is in response to DMAHRQ.

-BRDRAM (0)
Board DRAM, active low - An output to indicate that on-board DRAM s
being addressed.

-EALE (0)
Early Address Latch Enable, active low - In 286 mode, this signal is
generated internally by decode of the CPU status signals. In 386SX
mode, the VL82C320’s -ADS input gated directly to the -EALE output.

ouT1t (I-CMOS)
Indicates a refresh request.

5.1.8.5 Peripheral Interface Signals
A20GATE (I-TTL)
Address Bit 20 Enable - An input that is used internally along with Port A

bit 1 to determine if A20 is passed through or forced low. It also determines the state of -BLKA20.
TURBO (I-TTL)
Turbo, active high - This input to the VL82C320 determines the speed at

whcih the system board operates. It is internally ANDed with a software
settable latch. When high, operation is at full speed. When low, CLKw is

divided by the vaiue coded in configuration register MISCSET[4:3]. Turbo
mode is active only when all TURBO requests are active.
-RC (I-TTL)

Reset Control, active low - The falling edge of this signal causes a
RESCPU signal.

5.1.8.6 Bus Interface Signals
0OSC (I-TTL)
Oscillator - This is the buffered input of the external 14.318 MHz osciliator.

5-30

82C386SX ISA CHIP SET

<IOR (I-TTL)
I/O Read, active low- Indicates that an |/O read cycle is occurring on the
bus.

-IOW (I-TTL)
I/O Write, active low - Indicates that an 1/O write cycle is occurring on the
bus.

RSTDRV (I-TTL)
Reset Drive, active high - This signal is used to reset internal logic and to

derive RESCPU, and RESNPX.
SDLH/-HL (I-TTL)
System Data Bus Low to High/High to Low Swap - This signal is used to
establish the direction of byte swaps.

-SDSWAP (I-TTL)
System Data Bus Byte Swap Enable - This is the qualifying signal needed
for SDLH/-HL.

-XDREAD (I-TTL)
Peripheral Data Bus (XD Bus) Read - This signal determines the direction

of the XD bus data flow. When this signal is high, the XD Bus is output
enabled.

«LATLO (I-TTL)

SD Bus Low Byte Latch - This signal is needed to latch the SD bus low
byte or XD bus to the local data bus until the end of the bus cycle.
D15-D0 (10-TTL)
CPU Data Bus - This is the data bus directly connected to the CPU. Itis
also referred to as the local data bus.
SD15-SD0 (10-TTL)
System Data Bus - This bus connects directly to the slots.

It is used to

transfer data to/from the slot bus.
XD7-XDO (10-TTL)
Peripheral Data Bus - This bus is connected to the Bus Controller and the

VLB82C320. It is used to transfer data to/from on-board 8-bit peripherals

82C3865X ISA CHIP SET 5-31

PAR1,PARO (10-TTL)
Parity Bit Bytes 1 and O - These bits are written to memory along with their
corresponding bytes during memory write operations. During memory
read operations, these bits become inputs and are used along with their

respective data bytes to determine if a parity error has occurred.

-PARERROR (0)
Parity Error, active low - This signal is the result of a parity check on all
reads from on-board memory.

286/-386SX (1-TPV)
286 or 3865X Mode - Tied high or left open for 286 mode and grounded
for use in 3865SX based systems.

5.1.8.7 Test Mode Pin
-TRI (I-TPU)
Three-state - This pin is used to drive all outputs to a high impedance

state. When -TRIl is low, all outputs and bidirectional pins are high impedance.

3.1.8.8 Power and Ground Pins
VDD (PWR)
Power caonnection, nominally +5 volts. These pins should each have 0.1
uF bypass capacitors.
VSS (GND)

Ground connection, 0 volts.

5-32

82C386S5X ISA CHIP SET

5.2 82C331 ISA Bus Controller
The 82C331 provides the functions of DMA, page address register, timer,
interrupt control, port B logic, slot bus refresh address generation, and
real-time clock (see Figure 5-6). The following paragraphs describe each
of these subsections in detail.

5.2.1 DMA
The DMA subsection controls DMA transfers between an 1/O channe! and

on- or off-board memory. DMAs can occur over the full 16M range
available on the slot bus and the 32M range of system board DRAM and
drive the appropriate bus command signais depending on whether the
DMA is a memory read or write(see Figure 5-7). The 1/O address of

82C331 Index Register and Data Port Register is ECh and EDh respectively. Each of the 82C331 Indexed Configuration Registers described in

the following sections is accessed first by writing its address to the Index
Register at 1/0 address ECh, then by accessing the data port at /O

address EDh.

The DMA subsection contains the following:

Two 8237-Compatible DMA controliers

Middle address bit latches

DMA controller registers

o LS612 Page registers
*

Address generation

82C3865X ISA CHIP SET 5-33

DATA CONVERSION

IOCHRDY

|*@—————— -SAD, -SBHE

- XDREAD,

ROMB —————
. |WAITSTATECONTROL |
o ést?nsgffi

LATLO; -LATH!
.

CHMAO,

POWERGOOD

> nei%‘w)
iegus - BALE,
ssggfiém'
CONTROL
RSTDRV

HLDA

XD7-XDO

-MEMR, -MEMW.,

j INTA

~—— .|OR, -IOW.

-SMEMR, -SMEMW

DRQ7-DAQS.

-DACK? - -DACKS,

DRQ3-DROO ————®

IRQ15-1RQ3, IRQ1 ————t-

PE@:?&SCL

" DACK3 - -DACKD
OMAHRO. NMI
—_—_—.—___.

VBAT, PS. RTCOSC —————~
-PCK, 0S5C ————p»

INTR, OUT1

————————— AEN, TC, SPKR
-

]

A19-A1

A25-A17 ~—d

0D a

-EALE fi———-———w~o E

SA19-SA0

D Qe l
. A23LA17

[ 1E
BALE

*
|

BLKAZ) —————————

—
-

E
ADDRESS

DECODE

- -CS8042/
-RTC

-HIDAVE ————ee
TRl oo

Figure 5-6. 82C331 Functional Block Diagram Subsection

5-34

82C3865X ISA CHIP SET

[

EoP

8237

Do
o

DMA

CONTROLLER

AB-AQ

DRQ3-DRQO
-

XD7-XDO

| ADY
[—> HLDA

—

ADSTB1

X07-XDo

8237

XD7-XDO

MIDDLE |——®

ADDRESS

LATCH

EOP

DMA

ADSTB2

“#| CONTROLLER

DRQ7-DRQ5
DMAHLDA

IOCHRDY

‘DMARDY

MEMA
-»|

RDY

-I0R, -IOW —-*
-MEMR, -MEMW

—a=| HLDA

& READY

CONTROL

|—MEMR

L | A16
1 -IOR

Ad-A3

XDO-XD7

! -IOW
1

oLsen

PAGE

Figure 5-7. DMA Subsection Functional Block Diagram

82C3865X ISA CHIP SET 5-35

5.2.1.1 DMA Controllers
The ISA bus controlier supports seven DMA channels using two 8237

DMA controller equivalent megacells. The megacells capabile of running
at SYSCLK or SYSCLK/2 are programmable via indexed configuration
register ROMDMA (Refer to Tables 5-14), DMA controlier one contains
channels zero through three. These channels are used to transfer data
between 8-bit peripherals and 8- or 16-bit memory in pages of 64 KB.
DMA controller two contains channels four through seven. These channels (except channetl four) are used to transfer data between 16-bit /O
adapters and 16-bit memory in pages of 128 KB.

TABLE 5-14. RON.DMA (81h R/W) indexed Configuration Register
(Default = FCh)
Bit

Function

7:6

ROM wait states
00 = 3 wait states
01 = 1 wait state
10 = 2 wait state
11 = 3 wait states (Default)
8-bit DMA wait states

00 = 2 DMA clocks
01 = 4 DMA clocks
10 = 3 DMA clocks

11 = 3 DMA clocks (Default)
16-bit DMA wait states

00 = 2 DMA clocks
01 = 4 DMA clocks
10 = 3 DMA clocks
11 = 3 DMA clocks (Default)
DMA clock
0 = SYSCLK/2 {Default)
1 = SYSCLK

-MEMR timing

0 = -DMAMEMR is active at the same time as in the
original design (Detault)
1 = the falling edge of -DMAMEMR occurs one

DMACLK eartier

5-36

82C3865X ISA CHIP SET

5.2.1.2 Middle Address Bit Latches
The middle address bits are latched to an internal 8-bit register when the

DMA controlier writes a specified value onto an internal bus and by
issuing an address strobe. The DMA controller issues the address strobe

at the beginning of a DMA cycle and each time the lower 8-bit address
increments across an 8-bit subpage boundary during block transfers
The middie DMA address bits register cannot be written to or read from
externally and can only be loaded from the address strobe signals

5.2.1.3

DMA Controller Registers
Table 5-15 lists the addresses of all registers that can be read or written
to DMA controlier one and two.

Table5-15. DMA Controller Read/Write Address
DMA2

DMA1

Function

00COn
00C2h

0000h
0001h

Channel zero base and current address register
Channel zero base and current word count register

0002h
0003h
0004h
0005h
00068h
0007h
0008h

Channel one base and current address register
Channel one base and current word count register
Channel two base and current address register
Channel two base and current word count register
Channel three base and current address register
Channel three base and current word count register
Read status register/write command register

00D2h
00D4n
0oD6h

0009h
000Ah
000Bh

Write request register

Write single mask register bit
Write mode register

00DCh
00DEh

000Eh
000Fh

Clear mask register
Write all mask register bits

00C4h
00Ceh
00C8h
00CAh
00OCCh
DOCEh
00DOh

00D8h
00DAh

000Ch
000Dh

Clear byte pointer flip-flop
Read temporary register/write master clear

82C3865X ISA CHIP SET 5-37

3.2.1.4. Page Registers
An extended megaceli is used in the 1SA bus controller to generate the

page registers for each DMA channel. These page registers provide the
upper address bits during DMA cycles and are programmed by the
612AXS indexed configuration register(Refer to Table 5-16). Bit 7 enables
the extended DMA functions when set to 1 by allowing access to the two
required upper address bits, A24 and A25. When bit 7 = 0, the extended
functionality is disabled. Any previously stored values for A24 and A25
are disabled and both bits are forced to 0. When bit 7 =1, the extended
mode is enabled. A24 and A25 can be set in tf - memory mapper page
register by setting bit O of this register to 1 and writing the data to the

same address used for the lower page register byte. Resetting bit 010 0
allows access to the lower page registers. Bit 6 enabies EISA {/O access
compatibility when set to 1 by allowing access to the upper DMA page

address bits at /0 addresses 4XX where XX = the same address as the
lower page register byte. When set to 1, it also enables the extended
DMA system and allows the contents of the upper page register's A24
and A25 to be used. Bit O allows access via the same /O addresses to
the lower address bits, A16-A23 of the DMA page register when set to 0
or to the upper address hits A24 and A25 when setto 1. The state of this
bit has no effect unless bit 7 of this register has been previously setto 1.
Tables 5-17 and 5-18 list the available page register options.

Table 5-16. 612AXS(82h R/W) Indexed Configuration Register
(Default = 3Eh)

Bit

Function

Enable FF

4xx enable

5:1

Always one

FF PTR

5-38

B82C3865X ISA CHIP SET

Table 5-17. DMA Page Register Option One

Addresses

DMA
0

A25:24 (B6 = 1)

A23:16 (B6 = x)

Channel

0487h

0087h

0483h

0083h

0481h
0482h
048Bh

0081h
0082h
008Bh

2
3
5

04838h

0088h

048Ah

008Ah

048Fh

008Fh

-REFRESH

Table 5-18. DMA Page Register Option Two

Addresses

DMA

A25:24 (B0 =1, B7 =1)

A23:16 (B0 =0,B7 =1)

Channel

0087n

0087h

0083h
0081n
0o82n
008Bh
0089h

0083h
0081h
0082h
008Bh
0083h

1
2
3
5
6

00BAh

008AhN

008Fh

-REFRESH

5.2.1.5 Address Generation
DMA addressing for the ISA siot and system DRAM is made up of upper,
middle, and lower address portions. The page registers for each DMA
controller generate the upper address portion and must be set up by the

80386SX microprocessor prior to any DMA operation. The DMA controllers generate the middle address portion at the beginning of a DMA
operation and each time a DMA address increments or decrements

through a block boundary. The DMA controllers also generate the lower

address portion during DMA operations. Tables 5-19 and 5-20 list the
DMA addressing for the ISA slot and system DRAM.

B2C386SX ISA CHIP SET 5-39

Table 5-19. DMA Addressing for ISA Siot Access

Middie

Page

Address

8237

Registers

8-Bit

Latches

16-Bit

Megacell

DMA

LA23

M6
M5

LAZ2
LA21

LAZ22
LA21

S/ILA20

S/LA20

S/LA1S

S/LA19

S/LA18
SILA17

S/LA18
S/LA17

M9
M8

SA16
D7

SA15

SA16

SA14
SA13

SA15
SA14

D5
D4

SA12

SA13

SA11

SA12

SA10

SA11

SA9

SA10

SA8

SAQ

SA7

SA8B

SAB

SA7

SAS

SAB

SA4

SA5

SA3

SA4

SAZ

SA3

SA1

SA2

SAQ

SA1

VSS
-A0
VSS

SAO
-SBHE
-SBHE

5-40

82C3B6SX ISA CHIP SET

Table 5-20. DMA Addressing for System DRAM Accesses
Middle

Page

Registers

Address
Latches

8237

Megacell

8-Bit

16-Bit

DMA

M8
M7

A23

A22

A21

A20

A19

A18

A17

A16
D7

A15

A16

Al4

A15

Al13

Al4

A12

A13

A1l

A12

A10

A1l

A10

5S4

A2
Al

A4
A3

82C3865X ISA CHIP SET 5-41

5.2.2 Interrupt Controller
The interrupt controller consists of two 8259 programmable interrupt
controlier equivalent megacells with eight interrupt request lines each.
The two 8259s are cascaded inside the ISA bus controller with two of the
interrupt request inputs connected to internal circuitry. This allows a total
of 13 external interrupt requests (see Figure 5-8).

5-42

B2C386SX ISA CHIP SET

L naz 8259 INT
{

1 WR O NTERRUPT

-lowW

—»-|

XD7-XDO

1IRQ7-1RQ3,
IRQ1, IRQO

CONTROLLER

CASO

CAS1

— -

- INTA

CAS2 _}

XD7-XDO

INT

8259

-INTA

—@-|

-RD

—»-| -WR
> A0

XD7-XDO
IRQ 15-IRQ8

SP/EN |—T VoD

»| .AD

-I0R

| -INTA
L

SP/EN
INTERRUPT

CONTROLLER

CAS0

CAS1

CAS2 |—

Figure 5-8. Interrupt Controller Block Diagram

] Vs

INTR

82C3865X ISA CHIP SET 5-43

5.2.2.1 Interrupt Controller Registers
The internal registers of the 8259 megacelis are written to in the same
manner as the standard 8259 chip. However, before normal operation
begins, each megacell must foliow an initialization sequence. The se-

quence starts by writing Initialization Command Word one (ICW1). Once
written, the megacelis expect the following sequence:

ICW2, ICW3, and

ICWA (if required). Operation Control Words (OCWs) are written any time
after initialization (refer to Tables 5-21 and 5-22).

Table 5-21. Interrupt Controller Write Operations

INT1

INT2

XD4

XD3

0020n

00AQh

Write ICW1

0021h

Q0A1h

Write ICW2

0021h
0021h
0021h
0020h
0020n

00A1h
Q0A1h
00A1h
00AOh
00AOCh

X
X
X
0
0

X
X
X
0
1

Write ICW3
Write ICW4
Write OCW1
Write OCW2
Write OCW3

Table 5-22. Interrupt Controller Read Operations

INT1

INT2

0020h

00ADA

Interrupt Request Register (IRR),
In-Service Register (ISR).or
Poll Command (PC)

0021h

00Ath

Interrupt Mask Register (IMR)

5-44

B82(C3B6SX ISA CHIP SET

5.2.2.2 Interrupt Levels
Table 5-23 lists the interrupt levels for the DECpc 320sxLP/325sxLP.
Table 5-23. DECpc 3208xLP/3258xLP System Interrupt Levels

interrupt

Controller

Number

Interrupt Source

IRQO

Timer tick

IRQ1

Keyboard controlier

IRQ2

Cascade interrupt

3
4

2
2

IRQ8
IRQ9

Real-time clock (RTC)
Reserved

5
6

2
2

IRQ10
IRQ11

Reserved
Reserved

IRQ12

Mouse interrupt

8
9

2
2

IRQ13
IRQ14

Numeric coprocessor
Hard disk drive

10
11

2
1

IRQ15
IRQ3

Reserved
COM2

IRQ4

COM1

IRQ5

Reserved

IRQ6

Floppy disk drive

IRQ7

LPTH

Priority

5.2.3 Counter/Timer
This timer subsection consists of one 8254 programmable counter/timer

equivalent megacell with three internal independent counters. The clocks
for each of the internal counters are tied to a 14.318 MHz oscillator

through a divide-by-twelve counter. The gate inputs of counters zero and
one are tied high to enable them at all times. The gate input of counter
two is tied to bit zero of the port B register inside the ISA bus controlter
(see Figure 5-9).

82C3865X ISA CHIP SET 5-45

Voo

8254
~—-! CLKO

0scnz

|————m=] GATO

OuTo

TO INTERRUPT

CONTROLLER

| CLK1

b1 GATY

OUT1 ——————————»

OUT1

| CLK2
PORT B, 0

—n=] GAT2

-iowW

-WR

-IOR

-RD

XD7-XDo

Al AD

“

ouT2

_D—-» SPKR

COUNTER

TIMER

PORT B, 1

Figure 5-9. Counter/Timer Functional Block Diagram

5-46

82C386SX ISA CHIP SET

5.2.3.1 Counter/Timer Qutputs
The timer consists of one 8254 counter/timer megacell (see Figure 5-9).
One of the outputs s directly available at an external pin. Th2 output of

counter zero is connecied to input IRQO at interrupt controller one. The
output of counter one is directly connected to pin OUT1. The output of
one counter is tied to one of the inputs of an AND gate; the other AND
gate input is connected to bit-one of the port B register inside the ISA bus
controlier. Table 5-24 lists the addressing for each of the counter/timer's
internal registers.

Table 5-24. Counter/Timer Register Addressing

Address

-IOR

-1IOW

0040nh

Write initial count to counter

0040h

Read count/status from counter zero

0041h

Write initial count to counter one

0041h

Read count/status from counter one

0042h

Write initial count to counter two

0042h

Read count/status from counter two

0043h

Write control word

0043h

No operation

82C386SX ISA CHIP SET 5-47

5.2.3.2

Real-Time Clock
The Real Time Clock (RTC) contains a 146818A RTC equivalent megacell.
This megacell consists of 10 RAM bytes (for the time, calendar, and alarm
data), four control and status bytes, and 114 general purpose RAM bytes
(refer to Table 5-25).

Table 5-25. Real Time Clock Address Map
Address

Function

Range

-7Fh
0Dh
0Ch
0Bh
0AR
09h
08h
07h
06h
05h
04n

User RAM (Standby)
RTC Register D
RTC Register C
RTC Register B
RTC Register A
Year
Month
Date of Month
Day of Week
Hours (Alarm)
Hours (Time)

04h
03h
02h

Hours (Time)
Minutes (Alarm)
Minutes (Time)

1-12;12 Hour Mode
0-59
0-59

01h

Seconds (Alarm)

0-59

00h

Seconds (Time)

0-59

(Readonly)

(Read-only)
(Read/Write)
(Read/Write)
0-99
1-12
1-31
1-7
0-23
0-23.24 Hour Mode

5-48

B82C3865X ISA CHIP SET

5.2.3.3 Time-Of-Day Registers
The contents of the time-of-day registers can be binary or BCD. The

addressing for these registers are listed in Table 5-26.

Table 5-26. Time-of-Day Register Addressing

Address

BCD Mode

Binary Mode

Function/Time

09
08
07
06
05
05
04

99:0
12:1
311
71
12:1
92:81
12:1

63:0h
0C:1h
1F:1h
7:1h
0C:01h
8C:81h
0C:01h

Year
Month
Date
Day-of-week
Hours alarm (AM)
Hours alarm (PM)
Hours (AM)

92:81

8C:81h

Hours (PM)

59:0

3B8:00h

Minutes alarm

02
01

59:0
59:0

3B:00h
3B:00h

Minutes
Seconds alarm

590

3B:00h

Seconds

5.2.4 Control Registers
The 146818 megacell contains four control registers: A.B,.C, and D. All

four registers are accessible by the 803865SX microprocessor and are fully
accessible during update cycles (refer to Table 5-25).
All 128 bytes c.an be directly read and written by the 8B0386SX microproc-

essor except for the following:
Registers C and D (read-only)

Bit seven of register A (read-only)

82C3865X ISA CHIP SET 5-49

5.2.4.1 Control Register A
This register contains control bits for selecting periodic interrupts, input

divisors, and an update-in-progress status bit. Refer to Table 5-27 for

control register A bit assignments.

Table 5-27. Control Register A Bit Assignments

Bit

Description

Abbreviation

Update in progress

UIP (Read-only)

6
5
4

Divisor bit two
Divisor bit one
Divisor bit zero

pv2
DV1
Dvo

3
2
1

Rate select bit three
Rate select bit two
Rate select bit one

RS3
RS2
RS1

Rate select bit zero

RSO

5.2.4.2 Control Register B
This register contains command bits to control various modes of operation
and interrupt enables for the RTC. Refer to Table 5-28 for control register
B bit assignments.

Table 5-28. Control Register B Bit Assignments

Bit

Description

Abbreviation

Set command

SET

6
5
4

Periodic interrupt enable
Alarm interrupt enable
Update end interrupt enable

PIE
AlE
UIE

Reserved

Data mode (binary or BCD)

24/12 mode

24/12

Daylight savings enable

DSE

5.50

82C386SX ISA CHIP SET

5.2.4.3 Control Register C
This register contains status information relating to interrupts and the

internal operation of the RTC. Refer to Table 5-29 for control register C bit
assignments.

Table 5-29. Control Register C Bit Assignments

Bit

Description

Abbreviation

IRQ pending flag

IRQF

6
5

Periodic interrupt flag
Alarm interrupt flag

PF
AF

Update ended flag

3:0

Reserved (read as 0)

5.2.4.4 Control Register D
This register contains a bit indicating the status of the on-chip standby

RAM. Refer to Table 5-30 for control register D bit assignments

Table 5-30. Control Register D Bit Assignments

Bit

Description

Abbreviation

Valid RAM data and time

VRT

6:0

Not used (read as 0)

82C3865X ISA CHIP SET 5-51

2.5 Signal Definitions
Table 5-31 lists a signal name for the 82C331.

Table 5-31. 82C331 Signal Name
Pin Number

82C331
Signal Name

SA6

-DACK2

SA5

T/IC

SA4

BALE

SA3

8
9

SA2
0sC

VSS

SA1

SAO

-MEMCS16

-SBHE

-I0CS16

LA23

IRQ10

LA22

vDD

VSS

5-52

82C386SX ISA CHIP SET

Table 5-31.(Cont.) 82C331 Signal Name

82C331
Pin Number

Signal Name

IRQ 11

22
23

LA21
IRQ12

LA20

IRQ15

LA19

IRQ14

LA18

-DACKO

VSS

LA17

DRQO

-MEMR

34
35

-DACK5
-MEMW

36
37
38

DRQ5
-DACK6
DRQ6

-DACK7

VSS

DRQ7

-MASTER

A25

A24

A23

A22

A21

A20

A19

A18

82C3865X ISA CHIP SET 5-53

Table 5-31.(Cont.) 82C331 Signal Name

Pin Number

82Ca31
Signal Name

Al6

A15

Al14

A13

A12

A1l

A10

59
60

vDD
V3S

66
67
68
69

A4
A3
A2
-BE3

71
72
73
74

-BHE
A0
(C286)-386DX
HLDA

INTR

76
77
78
79

NMI

-CHSO0/-MW
-CHS1/-MR

vDD
VSS

5-54

B2C3865X ISA CHIP SET

Table 5-31.(Cont.) 82C331 Signal Name

82C331
Pin Number

Signal Name

VSS

CHM/-IO

-EALE

-BRDRAM
-CHREADY

85
86

BUSCLK

-BLKA20

DMAHLDA

89
90

OuT1

XD7

XDe

VSS

XD5
XD4

DMAHRQ

xD3

xXD2

XD1

XDo

100

vDD

101

-SDSWAP

102

SDLH/-HL

103

-XDREAD

104

-LATLO

105

-LATHI

106

VSS

107

SPKR

108

-CS8042/-RTC

109

IRQ1

110

IRQ13

82C386SX ISA CHIP SET 5-55

Table 5-31.(Cont.) 82C331 Signal Name
Pin Number

82C331
Signal Name

-PCK

112

-ROM8

113

-HIDRIVE

114

-TRI

115

POWERGOOD

116

VBAT

117

PS/-RCLR

118

XTALIN

119

XTALOUT

120

VSS

121

-IOCHK

122

RSTDRV

123

IRQ9

124

DRQ2

125

-WS0

126

IOCHRDY

127

-SMEMW

128

AEN

129

-SMEMR

130

VSS

131

SA19

132

-IowW

133

SA18

134

-IOR

135

SA17

136

-DACK3

137

SA16

138

DRQ3

139

vDD

140

VSS

5.56

82C3865X ISA CHIP SET

Table 5-31.(Cont.) 82C331 Signal Name
82C3n

Pin Number

Signal Name

141
142
143

SA15
-DACK1
SA14

144

DRQ1

145

SA13

146
147
148
149
150

-REFRESH
SA12
SYSCLK
SA11
VSS

151
152
153
154
155

IRQ7
SA10
IRQ6
SAQ
IRQ5

156
157
158
159
160

SA8
IRQ4
SA7
IRQ3
VSS

82C3865X ISA CHIP SET 5-57

2.6

Signal Description

2.6.1 CPU Interface
A25, A24 (O-TS)
Address bus- These pins are outputs during DMA, master, or standard
refresh modes. They are high impedance at all other times. A25 and A24
are driven from the altermate 612 regis:ars during DMA and refresh
cycies and are driven low during master cycles.

A23-A2 (10-TTL)
Address bus- These pins are outputs during DMA. master, or standard
refresh modes. They are inputs at all other times. As inputs, they are

passed to the SA and LA buses and A15-A2 are used to address /O
registers internal to the bus control chip. As outputs, they are driven from

different sources depending on which mode the VL82C331 is in. While in
refresh mode, these pins are driven from the 612 and refresh address

counter. While in DMA mode, they are driven from the 612 and DMA
controller subsection. If the VL82C331 is in master mode, the pins A23A17 are driven from tne inputs LA23-LA17 and the pins A16-A2 are driven

from the inputs SA16-SA2.

-BE3 (10-TPU)
Byte Enable 3, active iow- This pin is an output during DMA, master, or
standard refresh modes. Itis an input at all other times. As an input in
386DX mode, it is decoded along with the other byte enable signals to

generate SA1, SAOQ and-SBHE. As an output in 386DX mode SA1,SAQ,
and-SBHE are used to determine the value of-BE3. This pin should be left
unconnected when using this part in 286/386SX mode.
A1 (IO-TTL)
This pin is an output during DMA, master, or standard refresh modes. ftis

an input at all other times. It is interpreted as address A1 and passed to
SA1.As an output it is driven from the SA1 input.
-BHE (1O0-TTL)
This pin is an output during DMA, master, or standard refresh modes. Itis

an input at all other times. It is interpreted as -BHE and passed to -SBHE.
As an output it is driven from the -SBHE input.

5-58

82C3865X ISA CHIP SET

A0 (10-TTL)
This pin is an output during DMA, master, or standard refresh modes. Itis

an input at all other times. it is interpreted as AQ and passed to SAD. As

an output it is driven from the SAQ input.
(C286)-386DX (I-TPU)
CPU is 286/386SX or 386DX- This pin defines the type of address bus to
which the bus controlier chip is interfaced. If the pin is tied high, the
address bus is assumed to be emulating 286/386SX signals. In this
mode, A25, A24, and -BE3 would be left unconnected. The pins -BE2

(A1), -BH1 (-BHE) and -BEO (A0) would take on the 286/386SX functions. ‘
If the pin is tied low, A25, A24 can be used to generate up to 64 Mbyte

addressing for DMA, and the byte enable pins will take on the normal
386DX addressing functions. This pin has an internai pull-up to cause the
chip to default to 286/3865X mode if left unconnected. This pinis a hard
wiring option and must not be changed dynamically during operation.

When strapped for 286/386SX mode, the VL.82C331 is assumed to be
interfaced to the VLB2C320 System Controller which in turn may be

strapped for 286 or 386SX operation.

HLDA (-TTL)

Hold Acknowledge- This is the hold acknowledge pin directly from the
CPU. 1tis used to control direction on address and command pins.

When HLDA is low, the VL82C331 is defined as being in the CPU mode.
In the CPU mode, the local address bus (A bus) pins are inputs. The
system address bus (SA and LA) pins along with the command pins (MEMR, -MEMW, -IOR and -I0W;} are outputs. When HLDA is high, the

VL82C331 can be in DMA, refresh, or master modes. In both DMA and
refresh modes, the commands and all address buses (A, SA and LA) are

outputs. In master mode, the commands and system address bus (SA .
and LA) pins are inputs and the local address bus (A bus) pins are
outputs. The SA bus is passed directly to the A bus except bits 17,18,
and 19 are ignored. LA23-LA17 is passed directly to A23-A17.
INTR (O)

interrupt Request - INTR is used to interrupt the CPU and is generated by
the B259 megaceils any time a valid interrupt request input is received.

82C386SX ISA CHIP SET 5-59

NMI (0)
Non-Maskable interrupt- This output is used to drive the NMI input to the

CPU. This signal is asserted by either a parity error (indicated by -PCK
being asserted after the ENP ARCK bit in Port B has been asserted), or an
I/0 channel error (indicated by -IOCHCK being asserted after the
ENIOCK bit in Port B has been asserted). The NMi output is enabled by
writing a 0 to bit D7 of I/O port 70h. NM! is disabled on reset.

5.2.6.2 System Controller interface
-CHSO0/-MW (I0-TTL)

Channel Status 0 or active low Memory Write - This input is used along
with -CHS1 and CHM/-IO to determine what type of bus cycle the Bus

Controller is to perform. This input has the same meaning and timing
requirements as the SO signal for a 286 microprocessor. -CHSO going
active indicates a write cycle unless -CHS1 is also active. When both
status inputs are active it indicates an interrupt acknowiedge cycle. This
input is synchronized to the BUSCLK input. Activation of CPUHLDA
reverses this signal to become an output to the System Controlier. It is
then a -MEMW signal for DMA or bus master access to system memory.

-CHS1/-MR (10-TTL)

Channel Status 1 or active low Memory Read - This input is used along
with -CHSO0 and CHM/-0O to determine the bus cycle type. This input has
the same meaning and timing requirements as the S1 signal for a 286
microprocessor. -CHS1 going active indicates a read cycle unless -CHSO
is also active. When both status inputs are active it indicates an interrupt

acknowledge cycle. This input is synchronized to the BUSCLK input.
Activation of CPUHLDA reverses this signal to become an output to the

System Controller. It is then a -MEMR signal for DMA or bus master
access 1o system memory.

CHMW/-IO (I-TTL)

Channel Memory or active low /O select - This input is used along with CHSO0 and -CHS1 to determine the bus cycle type. This input has the
same meaning and timing requirements as the M/-10 signal for a 286/
386SX microprocessor. CHM/-10O is sampled anytime -CHS0 or -CHS1 is
active. If sampled high, it indicates a memory read or write cycle. If
sampled low, an I/O read or write cycle should be executed. This input is
synchronized to the BUSCLK input.

5-60

82C386SX ISA CHIP SET

-EALE (I-TPU)
:
Early Address Latch Enable, active low - This input is used to latch the
A23-A2 and Byte Enable signals. The latches are open when -EALE is
low and hold their value when -EALE is high. The latched addresses are

fed directly to the LA23-LA17 bus to provide more address setup time on

the bus before a command goes active. The lower latched addresses are
latched again with an internal ALE signal as soon as -CHSO or -CHS1 is

sampled active and fed to the SA19-SA0 and -SBHE outputs. In a 386DX
system, this input is connected directly to the -ADS output from the CPU.
In a 286/3B6SX system, this input is connected to the -EALE output from
the VL82C320 System Controller.
-BRDRAM (I-TTL)
On-board DRAM, active low- An input from the System Controller indicating that the on-board DRAM is being addressed.

-CHREADY (O)
Channel Ready, active low- This output is maintained in the active state
when no bus accesses are active. This indicates that the VL82C331 is

ready to accept a new command. During normal bus accessed,
-CHREADY is negated as soon as a valid bus requested is sampled on

the -CHS0 and -CHS1 inputs. It is asserted again to indicate that the
VL82C331 is ready to complete the current cycle. The bus command
signals are then terminated on the next falling edge of the BUSCLK input.

BUSCLK (I-CMOS)
Bus Clock- This is the main clock input for the VL82C331. [t runs at twice
the frequency desired for the SYSCLK output. All inputs are synchronous
with the falling edge of this input.
-BLKA20 (I-TTL)

Block A20, active low - This input is used while CPUHLDA is low to force
the LA20 outputs low anytime it is active. When -BLKA20 is negated
LA20 is generated from A20.

DMAHRQ (O)
Hold Request - This output is generated by the DMA controlier any time a

valid DMA request is received. It is connected to the DMAHRQ pin on the
System Controller.

82C3865X ISA CHIP SET 561

CMAHLDA (I-TTL)
DMA Hold Acknowledge - An input from the System Controller which
indicates that the current hold acknowledge state is for the DMA controller

or other bus master.

OouT1 (0)
Output 1-Indicates a refresh request to the System Controller. This is the
15 psec output of timer chennel 1.

5.2.6.3 ROM Interface
-ROMS (I-TPU)

8/16 bit ROM seiect - This input indicates the width of the ROM BIOS.
if -ROM8 is low, the VLB2C331 chip generates 8-to 16-bit conversions for
ROM accesses. Data buffer controls are generated assuming the ROM is

on the MD bus. If -ROM8 is high, data buffer controls are generated
assuming 16-bit wide ROMs are on the MD bus.

5.26.4 Bus Interface
-iOR (IO-TTL)

I/O Read, active low - This signal is an input when CPUHLDA is high and
-MASTER is low. Itis an output at all other times. When CPUHLDA is iow,
-IOR is driven from the 288 bus controlier megacell. When CPUHLDA is
high and -MASTER is high, it is driven by the 8237 DMA controlier
megacells. This pin requires an extrnal 10K ohm pull-up resistor.

-IOW (I0-TTL)
11O Write, active low - This signal is an input when CPUHLDA is high anr
-MASTER is low. It is an output at all other times. When CPUHLDA 5+,

-IOW is driven from the 288 bus controller megacell. When CPUHLDA s
high and -MASTER is high, it is driven by the 8237 DMA controller
megacells. This pin requires an external 10K ohm pull-up resistor.

-MEMR (IO0-TTL)
Memory Read, active low - This signal is an input when CPUHLDA is high
and -MASTER is low. itis an output at all other times. When CPUHLDA is
low, -MEMR is driven from the 288 bus controller megacell. When

CPUHLDA is high and -MASTER is high, it is driven by the 8237 DMA
contraller megacells. This signal does not puise low for DMA address
above 16 Mbytes. DMA above 16 Mbytes is only performed to the system
board, never to the slot bus. This pin requires an external 10K ohm puliup resistor.

5-62

B82C386SX ISA CHIP SET

-MEMW (I0-TTL)
Memory Write, active low - This signal is an input when CPUHLDA is high

and -MASTER is low. It is an output at all other times. When CPUHLDA is
low, -MEMW is driven from the 288 bus controller megacell. When
CPUHLDA is high and -MASTER is high, it is driven by the 8237 DMA
controller megacells. This pin requires an external 10K ohm pull-up
resistor.

-SMEMR (O-TS)
Memory Read, active low - -SMEMR is asserted on memory read cycles to

addresses below 1 Mbyte and all refresh cycies. It is three stated for all
addresses above 1 Mbyte. This pin requires an external 10K ohm puli-up
resistor.

-SMEMW (0-TS)
Memory Write, active low - -SMEMW is asserted on memory write cycles

to addresses below 1 Mbyte. It is three stated for all addresses above 1
Mbyte This pin requires an external 10K ohm puil-up resistor.

LA23-LA17 (1O0-TTL)
Latchable Address bus - This bus is an input when CPUHLDA is high and

-MASTER is low. It is an output bus at all other times. When CPUHLDA is
low, the LA bus is driven by the latched values from the A bus

When

CPULDA is high and -MASTER is high, the LA bus is driven by the 612
memory mapper for DMA cycles and normal reiresh. The LA bus 1s
latched internally with the -EALE input.

SA19-SA17 (O-TS)
System Address bus - This bus is three stated when CPUHLDA 1s high
and -MASTER is low. It is an output bus at all other times. When
CPUHLDA is low, the SA bus is driven by the latched values from the A
bus. When CPUHLDA is high and -MASTER is high, the SA bus is drniven
by the 8237 DMA controller megacells or refresh address generator. The
SA bus will become valid in the middle of the status cycle generated by
the -CHSO0 and -CHS1 inputs. They are latched with an internally generated ALE signal.

82C3865X ISA CHIP SET 5-63

SA16-SAC (IO-TTL)
System Address bus - This bus an input when CPUHLDA is high and MASTER is low. It is an output bus at all other times. When CPUHLDA is
low, the SA bus is driven by the latched values from the A bus. When

CPUHLDA is high and -MASTER is high, the SA bus is driven by the 8237
DMA controlier megacells or refresh address generator. The SA bus will
become valid in the middle of the status cycle generated by the -CHS0

and -CHS1 inputs. They are latched with an internally generated ALE
signal.

-SBHE (I0-TTL)
System Byte High Enable, active iow - This pin is controlled the same way
as the SA bus. Itis generated from a decode of the -BE inputs in CPU
mode. It is forced low for 16-bit DMA cycles and forced the opposite

vaiue of SAO for 8-bit DMA cycles.
-REFRESH (IT-0D)
Refresh signal, active low - This 1/O signal is pulied low whenever a
decoupled refresh command is received from the System Controller. It is

used as an input to sense refresh requests from external sources such as

the System Controller for coupled refresh cycles or bus masters, Itis

used internally to clock the refresh address counter and select a location
in the memory mapper which drives A23-A17. -REFRESH is an open drain
output capable of sinking 24 mA.
SYSCLK (0)

System Clock - This output is half the frequency of the BUSCLK input.
The bus control outputs BALE and the -IOR, -IOW, -MEMR and -MEMW
are synchronized to SYSCLK.
OSC (I-TTL)
Osciliator - This is the buffered input of the external 14.318 MHz oscillator.
RSTDRV (O)
Reset Drive, active high - This output is a system reset generated from the
POWERGOOD input. RSTDRV is synchronized to the BUSCLK input.

BALE (O)
Buffered Address Latch Enable, active high - A pulse which is generated

at the beginning of any bus cycle initiated from the CPU. BALE s forced
high anytime CPUHLDA is high.

5-64

82C3B6SX ISA CHIP SET

AEN (O)
Address Enable - This output goes high anytime the inputs CPUHLDA
and -MASTER are both high.
T/C (O)
Terminal Count - This output indicates that one of the DMA channels

terminal count has been reached. This signal directly drives the system
bus.

-DACK? - -DACKS, -DACK3 - -DACKO (O)

DMA Acknowledge, active low - These outputs are the acknowledge
signals for the corresponding DMA requests. The active polarity of these
lines is set active low on reset. Since the B237 megacells are internally
cascaded together, the polarity of the -DACK signals must not be
changed. This signal directly drives the system bus.
DRQ7-DRQ5,DRQ3-DRQO (I-TSPU)
DMA Reguest - These asynchronous inputs are used by an external
device to indicate when they need service from the internal DMA controllers. DRQO-DRQ3 are used for transters from 8-bit I/O adapters toffrom
system memory. DRQ5-DRQ7 are used for transters from 16-bit 1/O
adapters to/ffrom system memory. DRQ4 is not available externally as it 1s
used to cascade the two DMA controllers together.
IRQ15-IRQ9,IRQ7-IRQ3,IRQ1T (I-TTL)
Interrupt Request - These are the asynchronous interrupt request Inputs

for the 8259 megacells. IRQ0 and IRQ2 are not available as external
inputs to the chip, but are used internally. IRQO is connected to the

output of the 8254 counter 0. IRQ2 is used to cascade the two 8259

megaceils together. All IRQ input pins are active high.

-MASTER (I-TTL)

Master, active low - This input is used by an external device to disable the
internal DMA controliers and get access to the system bus. When asseried it indicates that an external bus master has controi of the bus.
-MEMCS16 (I-TTL)
Memory Chip Select 16 bit - This input is used to determine when a 16-bit
to 8-bit conversion is needed for CPU accesses. A 16 to 8 conversion is

done anytime the Sytem Controlier requests a 16-bit memory cycle and MEMCS16 is sampled high.

82C3865X ISA CHIP SET 5-65

-10CS16 (I-TTL)
I/O Chip Select 16 bit - This input is used to determine when a 16-bit to 8bit conversion is needed for CPU accesses. A 16 to 8 conversion is done
anytime the System Controller requests a 16-bit I/O cycle and -IOCS16 is
sampled high.

-JOCHK (I-TTL)
1/O Channel Check, active low - This input is used to indicate that an error
has taken place on the I/O bus. If I/O checking is enabled, an -IOCHK
assertion by a peripheral device generates an NMI to the processor. The
state of the -IOCHK signal is read as data bit D6 of the Port B register.
{OCHRDY (I-TTL)
I/O Channe! Ready - This input is pulled low in order to extend the read or
write cycles of any bus access initiated by the CPU, DMA controllers or
refresh controller. The default number of wait states for cycles initiatede

by the CPU are tour wait states for 8-bit peripherals, one wait state for 16bit peripherals and three wait states for ROM cycles. One DMA wait state
is inserted as the default for ali DMA cycles. Any peripheral that cannot
present read data, or strobe-in write data in this amount of time must use

-IOCHRDY to extend these cycles.
-WSO0 (I-TTL)

Wait State 0, active low - This input is pulled low by a peripheral on the S
bus to terminate a CPU controlled bus cycle earlier than the default
values defined internally on the chip.

POWERGOOD (I-TSPU)
System power on reset - This input signals that power to the board 1s
stable. A schmitt-trigger input is used. This ailows the input to be connected directly to an RC network.

5.2.6.5 Peripheral Interface
8042/-RTC (O)
Chip Select for 8042, active low - This output is active any time an SA
address is decoded at 60h or 64h. It is intended to be connected to the
chip select of the keyboard controlier. If BUSCTL[6]=1, this pin is also
active for RTC accesses at 70h and 71h. This is for use when the internal
RTC is disabled and an external RTC is used.

5-66

82C386SX ISA CHIP SET

XTALIN (-CMOS)
Crystal input - An internal oscillator input for the real time clock cry
requires a 32.768 KHz external crystal or stand-alone oscillator.

XTALOUT (0)
Crystal Qutput- An internal oscillator output tor the real time clock
See XTALIN. This pin is a no connect when an external oscillator |
PS/-RCLR/-IRQ8 (I-TSPV)

Power Sense, active high - Used to reset the status of the Valid R/

Time (VRT) bit. This bit is used to indicat¢ that the power has faile
that the contents of the RTC may not be valid. This pin is connect

external RC network. When BUSCTL[6]=1, this pin becomes -IRG
for use with an external RTC.
VBAT ()

Voltage Battery - Connected to the RTC hold-up battery.
SPKR (0)

Speaker - This output drives an externally buffered speaker. This
created by gating the output of timer 2. Bit 1 of Port B. 61H. s usi
enable the speaker output, and bit 0 is used to gate the output of
timer.

5.2.6.6 Data Buffer interface
XD7-XDO (I0-TTL)
Periipheral data bus - The bidirectional X data bus outputs data o

INTA cycle or I/O read cycle to any valid address within the VL82
is configured as an input at alt other times.

-SDSWAP (0)

System Data Swap, active low during some B-bit accesses - It inc
that the data on the SD bus must be swapped from low byte to hi
or vice versa depending on the state of the SDLH/-HL pin. -SDS\
active for 8-bit DMA cycles when an odd address access 0CCurs
more than one byte wide. For non-DMA accesses, -SDSWAP is ¢
any bus cycle to an 8-bit peripheral! that is addressing the odd by

82C3865X ISA CHIP SET 5-67

SDLH/-ML (0)
System Data Low to High, or High to Low - This signal is used to determine which direction data bytes must be swapped when -SDSWAP is

active. When SDLH/-HL is high, it indicates that data on the low byte
must be transferred to the high byte. When SALH/HL is low, it indicates
that data on the high byte must be transferred to the low byte. SDLH/-HL
is low for 8-bit DMA memory read cycles. For non-DMA accesses, SDLH/

HL is low for any memory write or I/O write when -SBHE is low. SDLH/-HL
is high at all other times.

-XDREAD (0)
Peripheral Data Read - This output is active low any time an INTA cycle

occurs or an 1/O read occurs to the address space from 0000h to O0F7h,
which is defined as being resident on the peripheral bus.

-LATLO (O)
Latch Low byte - This output is generated for all /O read and memory
read bus accesses to the low byte.

It is active with the same timing as the

read command and returns high at the same time as the read command.

This signal latches the data into the data buffer chip so that it acn be
presented to the CPU at a later time. This step is required due to the

asynchronous interface between the System Controller and VL.82C331.

-LATHI (O)
Latch High byte - This output is generated for all I/O read and memory
read bus accesses to the high byte.

It is active with the same timing as

the read command and returns high at the same time as the read command. This signal latches the data into the data buffer chip so that it can

be presented to the CPU at a later time. This step is required due to the
asynchronous interface between the System Controller and VL82C331.
-PCK (I-TPU)
Parity Check input, active low with pull-up - indicates that a parity error

has occurred in the on-board memory array. Assertion of this signal (if
enabled) generates an NMI to the processor. The state of the -PCK signal
is read as data bit D7 of the Port B register.

-HIDRIVE (I-TPU)
High Drive Enable - This pin is a wire strap option. When this input is low,

all bus drivers defined with an I0L spec of 24 mA will sink the full 24 mA
of current. When this input is high, all pins defined as 24 mA have the
output low drive capability cut in half to 12 mA.

5-68

82C3865SX ISA CHIP SET

5.2.6.7 Test Mode Pin
-TRI (I-TPU)
Three-state - This pin is used to control the three-state drive of all outputs
and bidirectional pins on the chip. If this pin is pulled low, all pins on the
chip except XTALOUT are in a high impedance mode. This is useful
during system test when test equipment or other chips drive the signals or
for hardware fault tolerant applications. -TR! has an internal pull-up.

5.2.6.8 Power and Ground Pins
VDD (PWR)
Power connection, nominally +5 voits. These pins should each have 0.1
uF bypass capacitors.

VSS (GND)
Ground connection, 0 volts.

6
82C712 UNIVERSAL PERIPHERAL

CONTROLLER I

The 82C712 Universa! Peripheral Controtier Il (UPCI) 15 a 100-pin integrated chup

1Its primary function is to provide periphera! support for the

DECpc 320sxLP/325sxLP system (see Figure 6-1)

Supported peripher-

als include
*

Two 16450 UARTs (COM1 and COM2)

One parallel port (LPT1)

Integrated Drive Electronics (IDE) AT hard disk interface

Floppy disk controlier

6.1 Serial Communications Ports
The peripheral controlier contains two software-compatible 16450 UARTs

designated as COM1 and COM2

6-2

B82C712 UNIVERSAL PERIPHERAL CONTROLLER I’

vee

-GAMECS

vss
-ACK,PE -ERROR

CONFIG | |
REGISTER

DECODER

BUSY.SLCT
PDO7.PCF0.PCF1

PARALLEL
PORT

-STROBE -INT
-SLCTIN
-AUTOFD

MOTHER/

SERIALT |=T[ S1CF0.S1CF1
RXD1.-CTS1.-Ri1

ADAPTER

-10R.-IOW

-DSR1.-DCO1

AEN RESET
AD-A9

BUS

D0-D7
INTR

S2CF0,S2CF1

cLock

'/F

SERAL2 || RXD2.-CTS2
-RI2
—a

-DSR2 -0CD2

DRQ,-DACK

MODSEL

DC/ADS

F'_'v—']
[

r—

—Ll
o

X1.2

INDEX

RPMRVI

FILTER

IDED7

\DRV1,DRV2
-MTRO-MTR?
HDSEL

-TRKO
DSKCHG
WRPRT
WGATE
AVDD

DIR-STEP
-WDATA
-RDATA
PREN
AVSS

FGNDS00
FGND250
DRVIYP
SETCUR
FDCCF

-HDCS!
-HDCSO
IOCS16
IDECF

Figure 6-1. 82C712 Block Diagrem

82C712 UNIVERSAL PERIF-ERAL CONTROLLER II 6-3

6.1.1 Serial Communications Ports Registers
Addressing of the accessible UART registers is shown in Table 6-1. The

base address of all registers is determined during the configuration
sequence (see section 6.5 "82C712 Configuration’). UART registers are
located at sequentially increasing addresses above this base address.

The following registers used by the serial Communication ports:

Received Buffer Register
*

Transmit Buffer Register

Interrupt Enable Register

Interrupt Flag Register

Byte Format Register

Modem Control Register

Line Status Register

Modem Status Register

Scratch Pad Register

Divisor LSB

Divisor MSB

6-4

82C712 UNIVERSAL PERIPHERAL CONTROLLER Il

Table 6-1. Addressing of UART Registers

Oftset

DRAB

4h
5h
6h

X
X
X

Oh
1h
2h
3h

7h
oh
1h

VO Function
Read

0
0
X
X

Write
Read/Write
Read/Write
Read/Write

Transmit Buffer Register
Interrupt Enable Register
interrupt Flag Register
Byte Format Register

X
1
1

Read/Write
Read/Write
Read/Write

Scratch Pad Register
Divisor LSB
Divisor MSB

Read/Write
Read
Read/Write

Modem Control Register
Line Status Register
Modem Status Register

Where:
X
= Don't Care

DRAB = Divisor Register Address Bit (Bit 7 of Byte Format Register)

6.1.1.1 Receive Buffer (RB)
Offset = Oh, Read only, DRAB =0
This register holds the incoming data byte. Bit O is the least significant bit,
which is transmitted and received first. Double buffering 1s supported by
the 82C712. This scheme uses an additiona! shift register (the Receive
Shift Register: not user accessible) to assemble the incorming byte before
it is loaded into the Receive Buffer. Refer to Table 6-2 for bit assignment.
Table 6-2. Receiver Buffer Register Bit Assignment
Bit

Function

7: 0

Databit7:0

82C712 UNIVERSAL PERIPHERAL CONTROLLER Il

6-5

6.1.1.2 Transmit Butfer (TB)
Offset=oh Write only, DRAB=0
This register holds the data byte to be sent. Bit 0 is the least significant
bit, which is transmitted and received first. Double buffering is supponed

by the 82C712. This scheme uses a shift register (the Transmit Shift
Register, not user accessible) which is loaded from the Transmit Buffer.
The transmitted byte is then shifted out of the Transmit Shift Register to
the TXD pin. Refer to Table 6-3 for bit assignment.

Table 6-3. Transmit Buffer Register Bit Assignment
Bit

Function

7:0

Databit7:0

6.1.1.3 Interrupt Enable Register (IER)
Offset=1h, Read/Write, DRAB =0
The low order 4 bit of this register control the enabling of each of the four

possible types of interrupts. Setting a bit 1o a fogic 1 enables the corresponding interrupt. It is possible to enable all, none, or some of the
interrupt sources. Disabling all interrupts means that the interrupt flag

register content is not valid and that none of the interrupt signals output
by the 82C712 can be triggered by a UART. Aii other portions of the

UART are unaffected by the disabling of interrupts. Refer to Table 6-4 for
bit assignment.

6-6

82C712 UNIVERSAL PERIPHERAL CONTROLLER I

Table 6-4. Interrupt Enable Register Bit Assignment
Bit

Function

7:4

Always Zero

A logic 1 here causes an interrupt when one of the bits in

the MODEM Status register changes state
2

A logic 1 here causes an interrupt when an error (Overrun,
Parity, Framing or Break) has been encountered. The line

Status register must be read to determine the type of error.
1

A logic 1 here causes an interrupt when the Transmit Bufter
1S empty

A logic 1 here causes an interrupt when the Receive Buffer
contains valid data

6.1.1.4 Interrupt Flag Register (IFR)
Offset = 2h Read/Write, DRAB = X
When accessed, this register reports the highest pending interrupt. By
reading it, the CPU can determine the source of the interrupt and can act

accordingly. The Interrupt Flag Register (IFR) records the highest
pending interrupt in bits 0 through 2. Other interrupts are temporarily
disregarded (they are internally saved by the 82C712) until the highest
priority one is serviced. Four levels of prioritized interrupts exist. In

descending order of priority they are: 1. Line Status (highest prionty).

2. Receive Buffer full; 3. Transmit Buffer empty; 4. MODEM Status
(lowest priority). Refer to Table 6-5 for bit assignment. Refer to Table 6-6
for UART interrupt specification.

82C712 UNIVERSAL PERIPHERAL CONTROLLER Il 6-7

Table 6-5. Interrupt Flag Register Bit Assignment

Bit

Function

7:3

Always Zero

2:1

Interrupt ID bit 2 : 1

Zero it interrupt pending

Table 6-6. UART Interrupt Specifications
Bit2 Bit1 Bit0 Priority Type
0

Source

Servicing
The Interrupt

NO INTERRUPT PENDING
Highest

LineStatus

Overrun Error or

Read Line Status

Parity Error or

Framing Error
of Break Interrupt
1

Second

Receive

Recewve Data

Read Receive

Bufter Full

Thirg

Transmit

Transmit Butfer

Bufter Empty

Fourth

Read IFR or Write
transmit butfer

MODEM

Clear to Send or

Read MODEM

Status

Data Set Ready

Status Register

or Ring Incicator
or Carrier Detect

6.1.1.5 Byte Format Register (BFR)
Offset = 3h, Read/Write, DRAB = X
This read/write register contains format information for the serial line.

Since it can be read, a separate copy of its content need not be kept In
system memory. Refer to Table 6-7 for bit assignment.

6-8

82C712 UNIVERSAL PERIPHERAL CONTROLLER Il

Table 6-7. Byte Format Register Bit Assignment
Bit

Function

Divisor Register Address Bit (DRAB)
0 = access to all other internal UART registers
1 = access to the Divisor Registers

Set break
0 = set break

1 = clear break

Stick parity
0 = sum is used to determined parity
1 = force parity bit

Even parity select
0 = odd parity
1 = even parity
Parity enable

0 = disable parity generation and checking
1 = enable parity generation and checking
No. of stop bits

0 = 1 stop bits
1 = 1 1/2 stop bits (5 Bits Word Length)

1 = 2 stop bits (6 Bits Word Length)

1 = 2 stop bits (7 Bits Word Length)
1 = 2 stop bits (8 Bits Word Length)
1:

Word length

0 0 = 5 Bits Werd Length
1 0 = 6 Bits Word Length
0 1 = 7 Bits Word Length
1 1 = 8 Bits Word Length

82C712 UNIVERSAL PERIPHERAL CONTROLLER 11 6-9

6.1.1.6 Modem Control Register (MCR)
Offset = 4h, Read/Write, DRAB = X
This byte-wide register is used to manage the connection to an external

MODEM or data set. Refer to Table 6-8 for bit assignment.
Table 6-8. Modem Control Register Bit Assignment

Bit

Function

7:5

Always Zero

Loopback

This bit is used to enable an interrupt (OUT2 pin of UART).
When QUT2=0 (default), the serial interrupt is forced into
high impedance. When OUT2=1 the serial interrupt output
iS enabled.

This bit is used to control the QUT1 bit. It does not have an
output pin associated with this bit. It can be read or written
by CPU.

Request to send

0 = force -RTS to inactive state
1 = force -RTS to active state

Data terminal ready
0 = force -DTR to inactive state
1 = force -DTR to active state

6.1.1.7 Line Status Register (LSR)
Offset = 5h, Read Only, DRAB = X
This byte-wide register supplies serial link status information to the CPU.
A Receive Line Status interrupt is caused by one of the conditions flagged
by Bits 1 through 4 of this register. It is read only. Writes to it are used at
the factory for testing purposes and are not recommended. Refer to Table
6-9 for bit assignment.

6-10

82C712 UNIVERSAL PERIPHERAL CONTROLLER II

Table 6-9. Line Status Register Bit Assignment
Bit

Function
Always Zero
Transmitter empty

0 = transmit buffer and transmit shif register not empty
1 = transmit buffer and transmit shif register empty
Transmit buffer empty

0 = write to transmit buffer
1 = character is loaded from the transmit buffer into the
transmit shift register
Break interrupt
0 = reading LSR
1 = break interrupt
Framing error

0 = reading LSR
1 = no stop bit
Parity error

0 = reading LSR
1 = parity error detected

Qverrun error

0 = CPU read LSR
1 = overrun occurs

Data ready

0 = reading the receive bufter
1 = character has been transferred from the receive shift
register to the receive buffer

82C712 UNIVERSAL PERIPHERAL CONTROLLER li

6-11

6.1.1.8 MODEM Status Register (MSR)

Offset = 6h, Read/Write, DRAB = X
This byte-wide register holds the current value of the MODEM control
lings. It also sets a bit (to a logic 1) each time one of these control lines

changes state. Reading the MSR resets all of the Change bits to 0. a
MODEM Status Interrupt is generated (if it is enabled) when Bit 0, 1,20r 3
is setto a 1. Refer to Table 6-10 for bit assignment.
Table 6-10. Modem Status Register Bit Assignment

Bit

Function

Data carrier detect; It is the complement of the -DCD pin. In

diagnostic loopback mode, it is controlled by Bit 3 of the
MCR.
6

Ring indicator; 't is the complement of the -R! pin. In
diagnostic loopback mode, it is controlled by Bit 2 of the
MCR.

Data set ready; It is the complement of the -DSR pin. When
in diagnostic loopback mode, this bit is identical to the

-DTR bit in the MCR.

Clear to send; It is the complement of the -CTS pin. When
in diagnostic loopback mode, this bit is identical to the

-RTS bit in the MODEM Contro! Register (MCR).

Delta data carrier detect; It is settoa 1 if the -DCD line has

Trailing edge ring indicator; It is set to a 1 if the -Ri line has

changed state since the last time the MSR was read.

changed from a logic 0 to a logic 1 since the last time the
MSR was read.

Delta data set ready; It is set to a 1 if the -DSR line has
changed state since the last time the MSR was read.

Delta clear 10 send; It is set to a 1 if the -CTS line has
changed state since the last time the MSR was read.

6-12

82C712 UNIVERSAL PERIPHERAL CONTROLLER II

6.1.1.9 Scratchpad Register
Offset = 7h, Read/Write, DRAB = X
This byte-wide register has no effect on the UART within which it is lo-

cated. It can be used for any purpose by the programmer.

6.1.1.10 Effects of Hardware Reset
Table 6-11 details the eftect of a hardware RESET on the UART located in

aBg2C712.
Table 6-11. Hardware Reset on the 82C712 UART
Register

Cause of Reset

Reset State

interrupt Enable Register

Hardware RESET

All bits = logic 0

Interrupt Flag Register

Hardware RESET

Bit 0 = logic 1

Other bits = logic 0
Byte Format Register

Hardware RESET

All bits = logic 0

MODEM Control Register Hardware RESET

All bits = logic 0

Hardware RESET

Bits 5.6 = iogic 1

Line Status Register

Other bits = logic 0
MODEM Status Register

Hardware RESET

Bits 0-3 = logic 1
Bits 4-7 = Input Signal

Receive Line Status

Hardware RESET
or Read LSR

logic O (low)

Receive Buffer Full

Hardw..e RESET

logic O (low)

Interrupt

or Read RB

Interrupt

Transmit Buffer Empty

Hardware RESET

Interrupt

orRead TB

MODEM Status interrupt

Hardware RESET
or Read MSR

logic O (low)

82C712 UNIVERSAL PERIPHERAL CONTROLLER Il 6-13

6.1.2 Baud Rate Generation
The UART contains a programmable Baud Generator. The 24 MHz
crystal osciltator frequency input is divided by 13 to provide a frequency
of 1.8462 MHz. This is sent to the Baud Rate Generator and divided by
the divisor for the UART. The output frequency of the Baud Rate Generator is 16 x the baud rate. Table 6-12 lists decimal divisors to use with a
crystal frequency of 24 MHz.

Table 5-12. Divisors, Baud Rates and Clock Frequencies
1.8462 MHz Clock

Divisor

Decimal

Percent

Baud Rate

Bivisor for
16 X Clock

Error
(Note)

2304

0.001

1536

110

1047

1345

857

150

768

300

384

600

192

1200

1800

2000

2400

3600

4800

7200

9600

19200

38400
56000

3
2

115200

0.004

0.005

0.030

NOTE : The percent error for all Baud Rates, except where indicated
otherwise, is 0.002%.

6-14

82C712 UNIVERSAL PERIPHERAL CONTROLLER Il

6.1.3 Serial Communications Header
The COM1 and COM2 provide the serial communications channels for the

DECpc 320sxLP/325sxLP system. Table 6-13 lists the pinouts for COM1
and COM2.
Table 6-13. Serial Communications Connector Pinouts
Pin No.

Function

Data carrier detect

Receive data

Transmit data

Data terminal ready

Ground

Data set ready

Request to send

Clear to send

Ring indicator

6.2 Parallel Printer Port
The parallel printer port contains the functionality of a 16C452 printer port.
The parallel printer port uses the following registers

Data Latch - Port A
Printer Status - Port B

Printer Control - Pont C

82C712 UNIVERSAL PERIPHERAL CONTROLLER I 6-15

6.2.1 Data Latch Register
This read/write register is located at an offset of 00h from the base ad-

dress of the parallel port. Data written to this regster is transmitted to the
printer. Data read from this port is the data which is on the connector.

6.2.2 Printer Status Register
This read-only register is located at an offset of 01h from the base agd-

dress of the parallel port. This register contains real-time status for the
LPT connector pins (Refer to Table 6-14).

Table 6-14. LPT Port Status Bit Assignments
Bit

Function
The state of the BUSY input pin
0 = the printer is busy and cannot accept data
1 = the printer is ready 1o accep! data.

The state of the -ACK input pin
0 = the printer has received a character and is
ready to accept another.
i =1t 15 still reading the last character sent or

data has not been received.

The state of the PE input pin

0 = the presence of paper.
1 = a paper end condition.

The state of the SLCT input pin

0 = printer i1s not selected.
1 = printer is online.

The inverted state of the -ERROR input pin
0 = an error condition has been detected
1 = no errors.

2:0

Reserved

6-16

82C712 UNIVERSAL PERIPHERAL CONTROLLER Il

6.2.3 Printer Control Register
This read/write register is located at an offset of 02h from the base address of the parallel port. This register controls the printer control lines
driven from the port (Refer tc Table 6-15).

Table 6-15. LPT Port Control Bit Assignments
Bit

Function

Reserved

IRQEN:; used to enable or disable interrupts

resulting from the printer -ACK signal.
0 = IRQ is disabled
1 = generates interrupts when ACK changes
from active to inactive

-SLCTIN; used to drive the -SLCTIN output pin
0 = the printer is not selected
1 = selects the printer

-INIT; used to control the -INIT output pin.

0 = initializes the printer

-AUTOFD; used to control the -AUTOFD output pin
0 = no autofeed

1 = causes the printer to generate a line feed
after each line is printed

-STROBE; used to control the -STROBE output pin
0 = no strobe

1 = generates the active low pulse(0.5 us pulse

minimum) which is required to clock data
into the printer

82C712 UNIVERSAL PERIPHERAL CONTROLLER Il

6-17

6.2.4 Parallel Printer Port Header
Header LPT1 provides the paralle! printer port channel for the DCEpc

320sxLP/325sxLp. Table 6-16 lists header pinouts.

Table 6-16. Parallel Printer Connector Pinouts

Pin No.

Signal

Function

1
2:9
10
11
12
13
14
15

-STROBE
PDO-PD7
-ACK
BUSY
PE
SLCT
-AUTOFD
-ERROR

Strobe
Printer data bit zero-seven
Acknowledge
Busy
Paper end
Select
Auto feed
Error

-INIT

Initialize printer

-SLCTIN

Select input

6.3 Integrated Drive Electronics Interface
THE 82C712 provides the controf signals for the IDE interface and the IDE
buffers as Table 6-17.
Table 6-17. IDE Control Signal

Signal

Function

-HDCS0

Primary Hard Disk Chip Select used to access the Task
File Registers decodes 1F0h-1F7h

-HDCS1

Secondary Hard Disk Chip Select, decodes 3F6h3F7h

-I0CS516

When active it indicates 16 bit /O transfer

-IDED7

D7 of the IDE interface should be connected to this pin

6-18

82C712 UNIVERSAL PERIPHERAL CONTROLLER Il

6.3.1 Hard Disk Registers
Twelve hard disk registers control IDE operations. They are accessed
between addresses 1FOh-1F7h, 3F6h and 3F7h. Table 6-18 lists the IDE
register 1/O addresses, specifies the 1/O tunction required to access the

registers. The following registers control IDE operations in AT mode:

Data Register

Error Register

Write Compensation Register

Sector Count Register

Sector Number Register

Cylinder Number Register

Drive/Head Register

Status Register

Command Register

Fixed Disk Register

Digital Input Register

82C712 UNIVERSAL PERIPHERAL CONTROLLER Il 6-19

Table 6-18. IDE Register Address Map

Address

/O Function

1FOh

Read/Write

Data Register

1F1h

Read

Error Register

1F1h
1F2h
1F3h
1F4h
1F5h
1F6h

Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write

Write Compensation Register
Sector count Register
Sector Number Register
Cylinder Number Register(Low Byte)
Cylinder Number Register(High Byte)
Drive/Head Register

1F7h

Read

Status Register

3F7h

Read

Digital Input Register

1F7h
3F6h

Write
Write

Command Register
Fixed Disk Register

3.3.141 Data Register
Read and Write to sector buffer. Accessed only when Read or Write
command is executed.

3.3.1.2 Error Register
Thus register contains the status of the last executed command
Table 6-19 for bit assignment.

O =MW

[

Table 6-19. Error Register Bit assignments
Function

Set 1 if bad biock detect.
Set 1if Data ECC error.
Not used.

Set 1it 1D is not found.
Not used.

Set 1 if command is aborted.
Set 1 if track O is errof.
Set 1 if Data Address Mark not found.

Reter to

6-20

82C712 UNIVERSAL PERIPHERAL CONTROLLER I

6.3.1.3 Write Compensation Register
This register contains the starting cylinder vaiue divided by 4.

6.3.14 Sector Count Register
This register contains the number of sectors during a Verity, Read, Write

or Format command. Note that a O value means 256 sector transfer

6.3.1.5 Sector Number Register
This register contains the target's logical sector number of Read. Write
and Verify commanad.

6.3.1.6 Cylinder Number Register

(1F4h = Low Byte, 1F5h = High Byte)

These registers contain LSB and MSB of the first cylinder number where .
the disk is to be accessed for Read, Write, Seek and Venify command

6.3.1.7 Drive/Head Register
Table 6-20. Drive/Head Register

Bit

Function

Setto 1

Setio 0

Setto 1

Drive select.

0 = Primary
1 = Secondary

3:0

head number (bit 3:MSB and bit 0:LSB)

82C712 UNIVERSAL PERIPHERAL CONTROLLER I

6-21

6.3.1.8 Status Register
This register contains the status of the drive. Refer to Table 6-21 for bit
assignments .

Table 6-21. Status Register Bit Assignments

Set to 1 if the drive is busy.
Set to 1 if the drive is ready to accept
command.

=2WbHsEwm

Function

Set to 1 if write fault condition occurred.

Bit

Set to 1 if error occur from last command.

Set to 1 if seek command is completed.
Set to 1 if drive is ready to transfer data.
Set to 1 it data correction is successful.
Set to 1if index mark is detected.

5.3.1.9 Command Register
This register contains command op code for fixed disk operation.

5.3.1.10 Fixed Disk Register
Table 6-22. Fixed Disk Register Bit Assignments

Bit

Function

7:4

Not Used

HEADS3EN

RESET
0 = Normal operation (Default)
1 = Generate reset to HDC

-IRQEN
0 = Enabled interrupt
1 = Disable interrupt {Default)

Reserved

6-22

82C712 UNIVERSAL PERIPHERAL CONTROLLER 1!

6.3.1.11 Digital Input Register Definition
Table 6-23. Digital Input Register Definition Bit Assignments

Bit

Function

Diskette Change

6
5

Write Gate (HDC)
Head Select 3/Reduced Write Current (HDC)

Head Select 2 (HDC)

2
1

Head Select 0 (HDC)
Drive Select 1 (HDC)

Head Select 1 (HDC)

Drive Select 0 (HDC)

6.4 Floppy Disk Controller (FDC)
The 82C712 contains a fully compatible NECuPD72065B Floppy Disk

Controller (FDC), an on-chip precision Anatog Data Separator (ADS). The
XT/AT bus interface circuitry is completely integrated with the 82C712 and
requires no external logic when interfaced with the XT/AT bus. The
licensed 765 core guarantees the compatibility. The on-chip Data

Separator supports 250/300/500 Kb/s and 1Mb/s. Depending on the
selected data rate, up to 3 external filters are automatically switched.

6.4.1 Floppy Disk Register

Five general registers control FDC operations. They are accessed at

addresses 3F2h.3F4h,3F5h, and 3F7h. Table 6-24 lists the FDC register
I/O addresses, specifies the /O function required to access the registers
The following registers contro!l FDC operations in AT mode:

Digital Output Register

Main Status Register

Data Register

Digital Input Register

Configuration Control Register

82C712 UNIVERSAL PERIPHERAL CONTROLLER Il 6-23

Table 6-24. FOC Register Address Map

Address

VO Function

3F2h

Write

Digital Output Register

3F4h

Read

Main Status Register

3F7h

Read

Digital Input Register

3F7h

Write

Contiguration Control Register

3F5h

Read/write

Data Register

3.4.1.1 Digital Output Register (Drive Control Register)
This writer register contains the motor enable bits, a DMA gate bit. a reset

bit, and drive selection bits. Refer to Table 6-25 for bit assignments. Refer
to Table 6-26 for drive/motor selection.

Table 6-25. Digital Output Register Bit Assignments

Bit

Function

7:4

Motor enable 3: 0

enable DMA (DRQ and -DACK) and interrupt (IRQ)

Reset floppy controller

1:0

Drive select 1:0

Table 6-26. Drive/Motor selection

1
1

Driver

6-24

82C712 UNIVERSAL PERIPHERAL CONTROLLER Ii

6.4.1.2 Main Status Register
This read only register controls the data input and output mod
passes ready information to the 80386SX. Refer to Table 6-27
assignments.

Table 6-27. Main Status Register Bit Assignmen
Bit

Function
Request for master; This bit indicates that the d
is ready to send or receive data to or from the (

bits DIO and RQM should be used to perform ti
handshaking function of “ready” and “direction

CPU.

Data Direction (DIO); This bit indicates the dire:
transfer between the FDC and the data register

then data is transferred from the data register t
D10=0, then transfer is from the CPU to the dat
Execution Mode (EXM); This bit is set only wher
execution phase is in the non DMA mode Whe
goes low, the execution phase has ended and
phase has begun. This bit operates only in the
mode.

Command in process; Set high when the Read
command is in progress. The FDC will not acce
command.
Drive 3 Seeking; Set high when drive 3 is in the
The FDC will not accept any other command.

Drive 2 Seeking; Set high when drive 2 is in the
The FDC will not accept any other command.

82C712 UNIVERSAL PERIPHERAL CONTROLLER Il 6-25

Table 6-27. (Cont.) Main Status Register Bit Assignments
Bit

Function

Drive 1 Seeking; Set high when drive 1 is in the Seek mode.
The FDC will not accept any other command.

Drive 0 Seeking: Set high when drive 0 is in the Seek mode.
The FDC will not accept any other command.

6.4.1.3

Data Register
Trus read/write register is aiso the FIFQO. All data and command information passes through the data register.

6.4.1.4 Digital Input Register
This read only register senses the state of the DSKCHG at bit 7. All other
bits are tristated

6.4.1.5 Configuration Control Register (Data Rate Register)
This write only reqister sets the data rate. Refer to Table 6-28 for bit
assignments. Refer to Table 6-29 for data rate selection.

Table 6-28. Configuration Control Register Bit Assignments
Bit

Function

7:2

Reserved

1:0

Data rate selection 1 : 0

6-26

82C712 UNIVERSAL PERIPHERAL CONTROLLER il

Table 6-29. Data Rate and Precompensation Programming Values
DID0O

DRVTYP Data Rate
Pin
MFM

Normal
Alternate FGND pin RPM/LC
Precomp® Precomp* Enabled
Pin

(Kb/s)

(ns)

Level

500

125

FGNDS500

High

250

125

250

FGND2z50

Low

300

208

FGND250

Low

250

125

250

FGND250

Low

1.0

250

125

250

FGND250

Low

1000

None

High

1000

None

Low

Normal values when PUMP/PREN pin set low;

Alternate values when PUMP/PREN pin set high

6.5

DO and D1 are Data Rate Controi Bits.

82C712 Configuration
The 82C712 is configured by hardware Two senal ports, parallel port. IDE

AT and FDC are available in this mode. Aliso, IRQ 1s active high only. The
port addresses and enabling/disabling are determined by the jumper

selects. (Refer to Table 6-30 through 6-34)

Table 6-30. Paralle! Port Address Select
PCF1

PCFO

Function

Disabled

0
1

1
0

LPTA
LPTB

3BCh
378h

LPTC

278h

82C712 UNIVERSAL PERIPHERAL CONTROLLER Il

Table 6-31. Primary Serial Port Address Select

S1CF1

S1CF0

Function

Disabled

0
1

1
0

COoM3
COoM2

338h
2F8h

com

3F8h

Table 6-32. Secondary Serial Port Address Select
S1CF1

S1CFo0

Function

Disabled

COoM4

238h

COM1

3F8h

COomM2

2F8h

Table 6-33. iDE Control
IDECF

Function

IDE Disabled

IDE Enabled

Table 6-34. FDC Control

FDCCF

Function

FDC Disabled

FDC Enabled

6-27

6-28

82C712 UNIVERSAL PERIPHERAL CONTROLLER Il

6.6 Signal Definitions
Table 6-35 lists a signal name for the 82C712.
Table 6-35. 82C712 Signal Name
82C712

Pin Number

Signal Name

RPM/LC

-MTRO

3
4

-DRV1
-DRVO

-MTR1

VSS

DIR

8
9

-STEP
-WDATA

-WGATE

11
12
13
14

HDSEL
-INDEX
-TRKO
-WRTPRT

vCC

16
17
18
19
20

-RDATA
DSKCHG
PREN
DRVTYP
X1/CLK

21
22

X2
IDED7

23
24
25

S1CF1
S1CF0
-HDCS0

82C712 UNIVERSAL PERIPHERAL CONTROLLER Il 6-29

Table 6-35.(Cont.) 82C712 Signal Name
.

82C712

Pin Number

Signal Name

26
27

-HDCS1
-l0CS16

-DACK

SSPIRQ

38
39

PSPIRQ
PINTR

FINTR

-IOR

AEN

VSS

6-30

82C712 UNIVERSAL PERIPHERAL CONTROLLER I

Table 6-35.(Cont.) 82C712 Signal Name
82C712

Pin Number

Signal Name

56
57

D7
RESET

52
53
54
55

FDRQ
D4
D5
D6

58
59

-GAMECS
SLCT

61
62
63
64
65

BUSY
-ACK
PD7
PD6
PD5

66
67
68
69

PD4
VSS
PD3
PD2

PD1

71
72
73
74
75

PDO
VCC
-SLCTIN
-INIT
-ERROR

82C712 UNIVERSAL PERIPHERAL CONTROLLER Il

Table 6-35.(Cont.) 82C712 Signal Name

Pin Number

82C712
Signal Name

-AUTOFD

-STROBE

RXD1

PCFO

-DSR1

PCF1

82
83

-CTS1
IDECF

RI1

-DCD1

R12

87
88

-DCD2
RXD2

89
90

-DSR2

91
92

S2CF0
-CT82

S2CF1

FGND500

FGND250

96
97

FILTER
RvVI

98
99

AVSS
SETCUR

100

AVCC

FDCCF

6-31

6-32

82C712 UNIVERSAL PERIPHERAL CONTROLLER i1

6.7 Signal Description
6.7.1 Host Interface
PSPIRQ (Primary Serial Port Interrupt)
PSPIRQ is a source of Primary Serial Port (PSP) interrupt. Externaily, it
should be connected to either IRQ3 or IRQ4 via jumpers.
SSPIRQ(Secondary Serial Port Interrupt)

SSPIRQ is a source of Secondary Serial Port (SSP) interrupt. Externally. it
should be connected to either IRQ3 or IRQ4 via jumpers.

FINTR (Floppy Controller Interrupt Request, T)
Fioppy Controller Interrupt Request (programmable polarity), 24 mA

driver. This interrupt is enabled/disabled via bit 3 of the Drive Control
Register. The active output is used to get the attention of the CPU. The
required action depends on the current function of the controller.
PINTR (Parallel Port Interrupt Request, T)

Paralle! Port Interrupt Request (programmable polarity). 24 mA driver. The
interrupt is enabled/disabled via bit 4 of the Parallel Control Register. If
enabled, the interrupt is generated following the -ACK signal input.
A0-A9 (VO Address, I)

Host address bit 0-9. These address bits are tatched mternauy at the
beginning of -IOR or-IOW.

AEN (Address Enable, 1)

Active high Address Enable indicates DMA activity. Normally. this signal .
is used with AQ-A9, -IOW, -IOR to decode I/O address ports.

-JOR (VO Read, 1)
Active low I/O read from host.

-IOW (/O Write, 1)
Active low /O write from host.

82C712 UNIVERSAL PERIPHERAL CONTROLLER Il

6-33

RESET (Master Reset, IS)
Active high Reset from host (Schmitt-trigger input). RESET has to be valid
for a minimum of 500 nanosecond. The effect of hardware reset is shown

in the functional description of each port. The configuration registers are

not affected. They come up in the default condition only on power up.
The falling edge of RESET will latch the jumper configuration. The jumper
select pin must be valid prior to this edge.

D0-D7 (Data Bus, VOH)
Host data bus, 24 mA driver. This bi-directional data bus is used to
transfer information between the CPU and the 82C712.

-DACK (DMA Acknowledge, |)

Active low input to acknowledge
'the DMA request. This signal normally is
used to enable DMA read or write.
FDRQ (FDC DMA Request, OH)
Active high DMA request output signal to the host, 24 mA driver.

TC (Terminal Count, 1)
Active high input signal indicates termination of DMA transfer. qualified by

-DACK before use on chip.

3.7.2 Parallel Port Controller
PD0-PD7 (Port Data, VOH)

The bi-directional parallel data bus is used to transfer information be-

tween CPU and peripherals. These signals have high current drive and
capable of sinking 24 mA @0.5V.
-STROBE (Data Strobe, OC)
This active low output indicates to the peripheral that the data at the
paraliet port is valid. This pin has high current drive and is capable of

sinking 24 mA @0.5V.
-SLCTIN (Select Input, OC)
This active low output selects the printer when it is low. This pin has high

current drive and is capable of sinking 24 mA @0.5V.
~INIT (Initialize, OC)
This active low output initialized (resets) the printer when it is fow. This pin

has high current drive and is capable of sinking 24 mA @0.5V.

6-34

82C712 UNIVERSAL PERIPHERAL CONTROLLER Il

-AUTOFD (Automatic Feed, OC)
When this output is low the printer automatically adds one line feed after

each line is printed. This pin has high current drive and is capable of
sinking 24 mA @0.5V.
-ACK (Acknowledge, 1)
Active low Acknowledge input. Low indicates that data has been received
and the printer is r3ady to accept more data.
BUSY (Printer Busy, 1)
Active high Busy input. The high input signal indicates the printer can not
accept additional data.

PE (Paper End, 1)
Active high Paper End input. The high input signal indicates the printer is
out of paper.

SLCT (Select, )
Active high device Select input. The input is set high by the printer when it
is selected.

-ERROR (Error, 1)
Active low Error input. This input is set low by the printer when it detects
the error.

PCFO (1)

Parallel Port Configuration Control 0 in 82C712. Input during hardware
RESET to select address for parallel port. (NOTE 1)
PCF1(1)

Parallel Port Configuration Control 1 in 82C712. input during hardware
RESET to select address for parallel port. (NOTE 1)

82C712 UNIVERSAL PERIPHERAL CONTROLLER Il

6-35

.7.3 Serial Port Interface
-CTS1, -CTS2 (Clear to Send, |)
Active low Clear to Send inputs for Primary and Secondary serial ports.
Handshake signal which notifies the UART that the MODEM is ready to
receive data. The CPU can monitor the status of -CTS signal by reading

bit 4 of Modem Status Register (MSR). A -CTS signal state change from
low to high after the last MSR read will set MSR bit

0to a 1. If bit 3 of

interrupt Enable Register is set, the interrupt is generated when -CTS

changes state. The -CTS signal has no effect on the transmitter. Note:Bit 4
of MSR is the complement of -CTS.

-DSR1, -DSR2 (Data Set Ready, 1)
Active low Data Set Ready inputs for Primary and Secondary serial ports
Handshake signal which notifies the UART that the MODEM is ready to

establish the communication link. The CPU can monitor the status of -DSR
signal state change trom low to high after the last MSR read will set MSR

bit 1to a 1. if bit 3 of Interrupt Enable Register is set, the interrupt is
generated when -DSR changes state. Note: Bit 5 of MSR is the comple-

ment of -DSR.

-DCD1, -DCD2 (Data Carrier Detect, i)
Active low Data Carrier Detect input for Primary and Secondary serial
ports. Handshake signal which notifies the UART that carrier signal is

detecied by the MODEM. The CPU and monitor the status of -DCD signa!
by reading bit 7 of Modem Status Register (MSR). A -DCD signal state
change from iow to high after the last MSR read will set MSR bit 3toa 1. if
bit 3 of interrupt Enable Register is set, the interrupt is generated when
-DCD changes state. Note: Bit 7 of MSR is the complement of -DCD.

-RI1, -Ri2 (Ring Indicator, 1)
Active low Ring indicator input for Primary and Secondary serial ports.
Handshake signal which notifies the UART that the telephonre ring signal
is detected by the MODEM. The CPU can monitor the status of Rl signal

by reading bit 6 of Modem Status Register (MSR). A -Rl signal state
change from low to high after the last MSR read will set MSR bit2toa 1. if
bit 3 of Interrupt Enable Register is set, the interrupt is generated when
-RI changes state. Note: Bit 6 of MSR is the complement of -Ri.

RXD1, RXD2 (Receive Data, 1)
Active high receive serial data input from communication link.

6-36

82C712 UNIVERSAL PERIPHERAL CONTROLLER 1i

S1CFO (1)
Primary Serial configuration 0in 82C712 . Input during hardware RESET
to select address for secondary serial port. (NGTE 1)

S1CF1 ()
Primary Serial configuration 1in 82C712 . Input during hardware RESET
to select address for secondary serial port. (NOTE 1)

‘

S2CFO0 (1)
Secondary Serial Port Configuration Control 0 in 82C712. input during
hardware RESET to select address for secondary serial port. (NOTE 1)

S2CF1 (1)
Secondary Serial Port Configuration Control 1 in 82C712. input during
hardware RESET to select address for secondary serial port. (NOTE 1)

6.7.4 IDE Interface
-10CS16 (16 bit VO Indication, i)
Active low 16 bit {/O indication whife in the AT hard disk node. The hard

disk interface generates I0CS16 to inform the host and the 82C712 that
16 bit /O transters are about to begin. IOCS16 is active only when transferring data words in AT mode. Low = 16 bit, high = 8 bit (AT mode)

IDED7 (IDE Data Bit 7, VOH)
IDE Data Bit 7 while in the AT hard disk mode. IDED7 transfers data at /O

addresses 1FOh-1F7h (R/W). 3F6h (R/W), 3F7h(W). IDED7 should be
connected to the iDE data bit 7. Normally, the B2C712 functions as a

buffer, transferring data bit 7 between the IDE device and the host. During
read of /0 address 3F7h, IDED7 is FDC Disk Change bit 7. In the XT hard
disk mode, IDE7 is no used.

-HDCSO0 (Hard Disk Chip Select 0, OH)
Active fow Hard Disk Chip Select 0 for IDE interface in either AT/XT hard
disk modes. This decodes the address space 1FOh-1F7h (default) if

configured in At mode (CR#00h<1> = 1) or 320h-323h if configured in XT
mode (CR#00h<
1> =0).

-HDCS1 (Hard Disk Chip Select 1, OH)
Active low Hard Disk Chip Select 1 for IDE interface, in either AT/XT hard

disk modes. This decodes the address space 3F6h-3F7h.

82C712 UNIVERSAL PERIPHERAL CONTROLLER Il

6-37

IDECF (1)
IDE configuration control in 82C712. Input during hardware RESET to
enabie/disable IDE. (NOTE 1)

i.7.5 Floppy Interface
-RDATA (Read Data, IS)
The active low signal reads raw data from the disk. This is a Schmitt input.

~WDATA (Write Data, OD)
This aci
e low signal writes precompensated serial data to the selected

drive. This is & high open current drain output and is not gated internally
with the write gate.

-DRVO,1 (Drive, OD)
These active open drain outputs select drives 0-3. Two drives can be

supported directly. An external decoder (2 to 4) is needed to select four

drives.

DSKCHG (Disk Change, IS)
This Diskette Change signal notifies the FDC that the disk drive door has

been opened. This Schmitt latched input is inverted and read via bit 7 of
I/O address 3F7h.

-WGATE (Write Gate, OD)
This active low open drain signal enables the head to write onto the disk.

DIR (Direction, OD)
This open drain output signal controls the head movement direction. {Low

= Step in; High = Step out)

-STEP (OD)
This active low output signal supplies the step puise. at a programmable
rate, to move the head for seek operation.

HDSEL (Head Select, OD)
This open drain output selects the head on the selected drive. {Low =

side 0; High = side 1)

-TRKO (Track 0, IS)
This active low Schmitt input indicates that the head is in track O of the
selected drive.

6-38

82C712 UNIVERSAL PERIPHERAL CONTROLLER Il

WRPRT (Write Protect, IS)
This active low Schmitt input indicates that the disk is write-protected. Any
Write command is ignored.

<INDEX (IS)
This active low Schmitt input indicates the beginning of a track.
-MTRO,1 (Motor, OD)
This active low open drain output selects motor drivers 0-3. Two drivers

are supported directly. An external decoder (2 to 4) is needed to select

four motor drivers. The motor enable bits are sottware controllable via the ‘
Digital Output Register (DOR).
FILTER (/O)
This signal is the output of the charge pump and the input to the VCO.
PLL filter circuitry is connected to this pin (FGND250, FGND500 and
analog ground).

FGNDSO00 (Fiiter Ground 500 Kb/s, OL)

This low iImpedance output signal is connected to 500 Kb/s (MFM) PLL

filter circuitry.

FGND250 (Filter Ground 250 Kb/s, OL)
This low impedance output signal is connected to 250 Kb/s (MFM) PLL
filter circuitry.

PREN (Precompensation Enable, 1)
This input selects precompensation mode: Low = Normal, High = Alternate. Precompensation values (shown in Floppy section) depend on the

selected data rate and precompensate mode.

DRVTYP (Drive Type, 1)
When this input is low, the dual speed spindie motor driver is used. If
300Kb/s is selected vie Data Rate register, the PLL actually runs at
250Kb/s. When this input is high (standard AT), the single speed spindle
motor driver is used. The PLL runs at 300Kb/s when data rate is selected

at 300Kb/s.

82C712 UNIVERSAL PERIPHERAL CONTROLLER Il 6-39

SETCUR (Set Current, )
This signal is connected to the Analog ground via an external resistor to

set the charge pump current for PLL filter.
RPM/LC (Revolutions per Minute/l.ow current, OD)

Depending on DRVTYP input, this open drain output signal can function in
two modes:

When DRVTYP is LOW (dual! speed spindle), this output selects either
300RPM or 360RPM. This output is low when 250/300Kb/s is selected
and high when 500Kb/s selected

2. When DRVTYP is HIGH (single speed spindie), the output goes high
when 500Kb/s is sélec.ed (high density media). It Is also used to0
indicate when to reduce write current.

RV1 (1)
An external resistor connects this pin to Analog ground for PLL filter.
FDCCF (1)
FDC Configuration control in 82C712. Input during hardware RESET to

enable/disable FDC. (NOTE 1)

6.7.6 Power and Ground
Vee (2) (Power)
+5VDC Digital supply.

X1/CLK (Crystal Clock)
The external connection for senes resonant 24 MHz crystal input. ACMQOS
compatibie oscillator is required if a crystal is not used.
X2 (Crystal, O)

24 MHz crystal. If an external clock is used, this pin should not be
connected.

-GAMECS (GAMECS, 0)
it will be low when /O address 201h s selected.
Vss (Ground)

0V Reference for the FDC digital, CPU interface, senal ports, parallel port,
and disk interface output drive circuitry, respectively

6-40

82C712 UNIVERSAL PERIPHERAL CONTROLLER Il

AVcc (Analog Power)
Analog +5VDC for the PLL.

AVss (Analog Ground)
Analog Ground for the PLL.
Buffer Types:
I

=TTL input

= High current open drain output

= Schmitt-trigger input

= Low current open drain output

O
=TTL output
OH = High current TTL output
OC =QOpen Drain

T
= Tri-state TTL output, 24 mA
Oclk = Clock Input

NOTE 1 : The external 27K ohm resistor is used to pull these pins to
the required signal levels.

7
8042 KEYBOARD/MOUSE CONTROLLER
The Keyboard/Mouse controlier ROM contains the program required to

support the PS/2 command set and 128 bytes of conversion code. Serial
I/0 1s handled with receiverfiransmitter hardware implementations that

depend on an 8-bit imer for time-out detection

7.1 Command Invocation
The system writes commands to Port 64h and the data associated with

the command to Port 60h. The system reads al! keyboard and mouse data
at Port 60h. The system reads the 8042 status at Port 64h Keyboard
commands and data are wnitten to Port 60h. Mouse commands are written

to Port 60h after the Write mouse (0D4h) command The mouse data
tollows the same procedure. The 8042 Status Register (read of Porn 64h)
indicates if the B042 1s ready to accept another command or it data is
ready from the last command. The system can only send data or a command to the 8042 if the 1BF (Input Buffer Fuli, bit 1 of the Status Reg:ster)

flag 1s false The data is only valid from the 8042 if the OBF (Output Buffer
Full, bit O of the Status Register) flag 1s true. Before issuing a command o

return data, the OBF and IBF should be faise. After waiting for the OBF
flag to go true, the data is read from Port 60h.

7.2 Status Register
The status register is an eight bit read only register accessed via Port
64h. An IN on Port 64h provides the status shown in Table 7-1

7-2

8042 KEYBOARD/MOUSE CONTROLLER

Table 7-1. Status Register

Bit

Function
Receive parity error

0 = normal
1 = parity error

General time-out
0 = normal
1 = time-out occurred

Mouse Output Bufter Full

0 = empty
1 = full
Keyboard enable

0 = disabled
1 = enabled

Command/data (F1)
0 = data or idle
1 = command or active

System flag (FO)
Value = value of the system flag (bit2) in the

Keyboard Controller Command Byte

input buffer full (IBF)
0 = empty
1 = full

Output buffer full (OBF)
0 = empty
1 = full

8042 KEYBOARD/MOUSE CONTROLLER 7-3

7.3 Standard Commands
The Keyboard/Mouse Controller supports a Standard Command Set
described in Table 7-2.

Table 7-2. Standard Command Set

ADDRESS

DESCRIPTION

COh-1Fh

Read the contents of the designated RAM locations
(20h-3Fh) and send it to the system.

20h-3Fh

Read from RAM

40h-5Fh

Get a byte of data from system and write into one of
locations (20h-3Fh)

60h-7Fh

Write to RAM

Adh

Test Password
Returns OFAh if password is loaded.
Returns OF 1h if password is not loaded.

A5h

Load Password
Loads Password until a ‘0’ is received from the
system,

A5h

Enable Password
Enables the checking of keystrokes for a match with
the password.

A7h

Disable Mouse

A8h

Enable Mouse

ASh

Test Mouse Clock and Data

7-4

8042 KEYBOARD/MOUSE CONTROLLER

Table 7-2.(Cont.) Standard Command Set
ADDRESS

DESCRIPTION

AAh

8051 Self Test

ABh

Test Keyboard Clock and Data lines.

ACh

The Diagnostic Dump is not implemented

ADh

Disable Keyboard

AEh

Enable Keyboard

Coh

Returns 55h if successful self test.

Emulate reading the input port (P1) and send data to
the system

Cih

Continuously puts the lower four bits of Port 1 into the
STATUS register.

Ceh
DOoh

Continuously puts the upper four bits of Port 1 into
the STATUS register.

Send Port 2 value to the system (emulates data since
there's no real P2)

Dih

Only set/reset GateA20 line based on the system
data bit 1.

D2h

Send data back to the system as if it came from the
keyboard.

D3h

Send data back to the system as it it came from the
mouse.

D4h
.

Output next received byte of data from system to
the mouse.

EOh

FXh

Reports the state of the test inputs.

Pulse only P2.0 (the reset line) low for Gus if
Cormmand byte is even.

8042 KEYBOARD/MOUSE CONTROLLER 7-5

7.4 Extended Commands
The Keyboard/Mouse Controller supports an extended command set
described in Table 7-3.
Table 7-3. Extended Command Set
ADDRESS

DESCRIPTION

B8h

Setup Phoenix extended memory access INDEX

BSh

Get current Phoenix extended memory access
INDEX

BAh

Get current Phoenix extended memory referenced

by INDEX
BBh

Write Phoenix extended memaory referenced by

INDEX

BCh/BDh

Read/Write RAM @VPointer

C7h

Sets Port 1 bits corresponding bits to system data
bits that are set.

Csh

Clears Port 1 bits corresponding bits to system data
bits that are set.

Coh

Sets Port 2 bits corresponding bits to system data
bits that are set.

CAh

D3n/D4h

Clears Port 2 bits corresponding bits to system data
bits that are set.
Set/Ciear Fast GateA20
Acknowledge (OFAh) is sent to the system upon

completion of the command.

D5h

Read Phoenix Version Number (2 bytes).

Déh

Read Version Information (2 bytes)

7-6

8042 KEYBOARD/MOUSE CONTROLLER

Table 7-3.(Cont.) Extended Command Set

ADDRESS
D7h

DESCRIPTION
Read Model number (2 bytes) and then read the

customer’'s model number (1 byte).

D8h/DSh

Set/Clear Fast GateA20

Acknowledge (OFAh) is sent to the system upon
completion of the command.

EXh

The Phoenix extended Odd EXh commands sets
P2.1,2 or 3 based on command bits 1,2 and 3. Even

EXh commands clears P2.1,2 or 3 based on
command bits 1,2 and 3.

7.5 Keyboard Controller Command Byte
The interna!l status is defined by the Keyboard Controlier Command Byte
{KCCB). The KCCB resides in RAM at location 20h. The KCCB can be
read/written with the special commands listed in Table 7-4.

NOTE: The KCCB is read with a 20h command and written with a 60h

command.

8042 KEYBOARD/MOUSE CONTROLLER 7-7

Table 7-4. Keyboard Controlier Command Byte
Bit

Function

Reserved (always zero)

Keycode conversion
0 = Scan Code no conversion

1 = Scan Code conversion enabled
5

Disable Mouse
0 = enabled
1 = disabled

Disable Keyboard
0 = enabled
1 = disabled

Reserved (always zero)

System flag
0 = hot reset did not occur
1 = hot reset occurred

Enable Mouse OBF interrupt

0 = disabled
1 = enabled

Enable Keyboard OBF interrupt
0 = disabled
1 = enabled

7-8

8042 KEYBOARD/MOUSE CONTROLLER

7.6 Keyboard Commands
Any command/data written to Port 60h is automatically transmitted to the
keyboard by the 8042 if 8042 is not in a waiting for data mode. Refer to

Table 7-5 for Keyboard Commands.
Table 7-5. Keyboard Commands

COMMAND

DESCRIPTION

EDh
EEh
EFh
FOh

Set LEDs
Echo
Invalid command
Select alternate scan code set

Fih

invalid command

Feh
F3h

Read 1D bytes
Set typematic delay and rate

Fah

Enable keyboard

F5h
Féh
F7n

Disable keyboard and set defaults
Set defaults
Set all keys typematic
Set all keys make/fbreak

F8h
Foh
FAh
FCh
FDh
FEh

Set all keys make only
Set alt keys typematic/make/break
Set key type typematic
Set key type make/break
Set key type make only
Resend the last transmission

FFh

BAT, Reset the defaults and buffers

FBh

NOTE: Commands F7 through FD are normally used for Character
Set 3.

8042 KEYBOARD/MOUSE CONTROLLER 7-9

.7 Mouse Commands
The mouse command sequence is as follows:
1.

Write an 8042 command D4h (Write Mouse) to Port 64h.

Write command/data to Port 60h.

Refer to Table 7-6 for Mouse Commands.
Table 7-6. Mouse Commands

COMMAND

DESCRIPTION

E6h
E7h

Set Scaling

E8h

Set Resolution

ESh
EAh
EBh
ECh
EDh

Status Request
Set Stream Mode
Read Data
Reset Wrap Mode
Invalid Command

EEh
EFh

Set Wrap Mode
Invalid Command

FOh

Set Remote Mode

F1ih

Invalid Command

Reset Scaling

F2h

Read Device Type

F3h

Set Sampling Rate

F4h

Enable Mouse

F5h

Disable Mouse

Feh

Set Default Values

F7h - FDh

Reserved

FEh

Resend

FFh

Reset

8
VGA VIDEO CONTROLLER
The DECpc 320sxLP/325sxLP system board contains an Extended High

Resolution Video Controller. Figure -1 shows the major VGA Video
controller hardware components. Components include
*

OTI-067 VGA Graphics Controller

OTI-066 Video DAC

OTI-069 Video Pixel Clock Generator

Video BIOS EPROM

Video RAM

8-1

8-2 VGA VIDEO CONTROLLER

OTI-067

VGA GRAPHMICS
CONTROLLER

MICROPROCESSOR
INT ERFACE

DO-D7 «ap————— SDO-507

800-807

08-D15 ~uf————n] SDA.SD5

#0-P7

————— SAQ-SA18

DACW

AQ-A19

OTi-086
HIGH SPEED
VIDEOQ DAC

00.07

RED |
-RD

-DACR
50 MH2

MCLK

0sc

GREEN e
SAQ

OTI-069
VIDEO PIXEL

Rsy

SA1

BLUE

—

14.218 MH2 :J

F50

FSt

FS2

CSELO

PCLK

CLOCK GENERATOR
CSEL)

CSEL2

BLANK

RLANK

[
FOUT

VCLK

VIDEO RAM
MDG-MD15

DO-D1S

MAD-MA15

AQ-AS

EPROM
DO-D15

Aot

AG-AS

Figure 8-1. Video Controller Block Diagram

ANALOG
VIDEO

OUTPUTS

VGA VIDEO CONTROLLER 8-3

3.1 OTI-067 VGA Graphics Controller
The OTI-067 is a highly integrated. single chip Video Graphics

Controller. Frgure 8-2 shows a block diagram of the OTI-067.
The following sections briefly describe the following major
components.

CRT Controller (CRTC)

Attribute Controller

Graphics Controller

Sequencer

Memory Buffer

Bus Interface

1.1.1 CRT Controller
The CRTC generates horizontal and vertical timing signals, ad-

dresses for the dynamic RAM display bufter. and cursor and underline

timing

signails.

..1.2 Attribute Controller
The attribute controlier receives video memory data from the

graphics controller and formats the data for display un the CRT. The
attribute controller also controls blinking, underhning. cursor
insertion, and

pixel (bit) panning.

8-4

VGA VIDEO CONTROLLER

MDJ[15:0)

MDI[15:0]

Sequancer

CRT

Controlier

opso 4 >

D[15:0)
it

MDI[15:0
[ )

Memory
Butter

MDI[15:0]

MDO[15:0]
I

DO[15:0]

D[15:0]

Graphic

Controlier

APA[7.0]| ATR[7:0] | FNT[7:0]
|

————P

System
Bus

Bus
interface

DBW-O]?

D[15:0]

D[15:0)

Aftribute
Controlier

RA[14:12

[14:12) \/

External
BIOS ROM

Figure 8-2. OTI-067 Block Diagram

= x;g;%

VGA VIDEQ CONTROLLER 8-5

3.1.3 Graphics Controller
The graphics controller handies the data flow between the display
memory and the attribute controller during the active display period.
Further it supports data flow between the host processor and the display

memory. During the active display time, memory data is fetched from
memory to fill the FIFO which is then used to supply data to the attribute
controller as required. In APA (All-Points-Addressable) modes, sometimes
referred to as graphics mode, parallel memory data is converted to serial
bit-plane data before sending it to the attribute controlier. in A/N modes,
sometimes referred to as Alphanumeric mode, the parallel memory data is
sent to the attribute controller without conversion. During video memory
read or write operations, the graphics controller can perform logical
operations on the parallel memory data.

8.1.4 Sequencer
The sequencer generates basic DRAM timing signals and all clock and
reset signals. It also arbitrates access to video memory between the
system microprocessor and the CRTC during active display intervals by inserting system microprocessor memory cycles between
display memory cycles, and provides memory mapping of the video
memory. Map mask registers can be used to protect entire memaory
maps from being altered.

8.1.5 Memory Buffer (FIFO)
The memory buffer or FIFO (First-In-First-Out) provides an
interface between video memory and the Graphics Controller during
active display time, which improves the system microprocessor video
memory access bandwidth.

8.1.6 Bus Interface
The bus interface decodes memory addresses and /O addresses to the
video memory or VGA registers, generates all handshake signals to
the system microprocessor, controls the backward-compatible iogic
(NM1), and controls the internal data bus.

8-6

VGA VIDEO CONTROLLER

8.2 OTI-066 Video DAC
The OTI-066 is a monolithic triple 6-bit video digital to analog converter

(DAC) with 256 x 18 color palette for high-speed video applications. With
this color palette, 256 color combinations out of 256K possible colors can
be selected for display. A pixel mask is incorporated to allow for fast
update of video information in a single cycle. The DAC on chip is capable
of driving 75Q or 37.5Q standard loads at pixel rates of 65 MHz. All
microprocessor interface |/ are TTL-compatible. Figure 8-3 shows a
block diagram of the OTI-066 Video DAC.
An 8-bit value read on the Pixel Address inputs is used as a read address
for the look-up table. This data is partitioned as three fields of 6 bits. Each

field is applied to the inputs of a 6-bit DAC. An externally generated blank

signal can be input to the OTI-066. This signal acts on all three of the
analog outputs. The -BLANK signal is delayed internally so that it appears
at the analog outputs with the correct relationship to the pixe! stream. The
contents of the look-up table are accessed via an 8-bit wide interface to
the OTI-067. The use of an internal synchronizing circuit allows color
value accesses to be totally asynchronous to the video path. A pixel word

mask is included to ailow the incoming pixe! address to be masked. This
permits rapid changes to the effective contents of the color look-up table
to facilitate such operations as animation and flashing objects. The pixe!
mask register is directly in the pixel stream, thus operations on the con-

tents of the mask register should be synchronized to the pixel stream.
Pixel address and -BLANK inputs are sampled on the rising edge of the

Pixe! Clock. Their effect appears at the analog outputs after three further
rising edges of the Pixel Clock (see Figure 8-4).

VGA VIDEQ CONTROLLER 8-7

fa——— VCC

PCLK

—*

Timing

Memory Array

Gen.

256 deep
16 bits wide

Pixel

—7~*|

Latch

Po-P7

\\m

je—— VSS

Address

D0-D7

Micro-

WR ——

sor

proces

18-Bit

Inter-

Rsp

—— face

RS1

Data

& Mask

Latch

—» RED
18

3 DAC
x 6-bit

—» BLUE

[
4\

-BLANK
IREF

Figure 8-3. OTI-066 Block Diagram

[ GREEN

8-8

VGA VIDEO CONTROLLER

PCLK

PO-P?

*BLANK

RED

GREEN

BLUE

Y
blank

Figure 8-4 Video Path timing model

VGA VIDEO CONTROLLER 8-9

8.2.1 Analog Outputs
The outputs of the DACs are designed to be capable of producing 0.7volt peak white amplitude with an IREF of 8.88 mA when driving a doubly

terminated 759 load. This corresponds to an effective DAC output loading (R effectiv e) of 37.5Q. The -BLANK input to the OTI-066 acts on all three

of the analog outputs. When the -BLANK input is low, a binary zero is
applied to the inputs of the DACs. The expression for calculating IREF
with various peak white voltage/output loading combinations is:

vpeak white

IREF =

2.058 xR

effective

Note that for all values of IREF and output loading.

Vauackieve, =0
8.2.2 Microprocessor interface
There are three microprocessor interface registers accessed using RSO
and RS1 that control addressing, color value, and pixel masking features
(Refer to Table 8-1).

Table 8-1. Microprocessor interface Registers

RS1

RSO

Size (Bits)

Address (write mode)

Address (read mode)

Color Value

Pixel Mask

8-10

VGA VIDEO CONTROLLER

8.2.2.1 Write-mode Address Register
To set a new color definition, a value specifying a location in the color
look-up table is first written to the Write-mode Address register (RS0=0,
RS1=0). The values for the red, green, and blue intensities are then
written in succession to the Color Value register. After blue data is written

to the Color Value register, the new color definition is transferred to the
color look-up table. The Address register is automatically incremented.
Since the Address register increments after each new color definition has

been transferred from the Color Value register to the color iook-up table, it

is simple to write a set of consecutive locations with new color definitions.
First, the start address of the set of locations is written to the write mode

Address register. Then, the color definitions for each location are written

sequentially to the Color Value register.

8.2.2.2 Read-mode Address Register
To read a color definition, a value specifying the location in the iook-up

table to be read is written to the Read-mode Address register. After this

vaiue has been written, the contents of the iocation specified are copied

to the Color Value register. The Address register is automatically
incremented. The red, green, and blue intensity values can be read by a

sequence of three reads from the Color Value register. After the biue
value has been read, the location in the look-up table currently specified
by the Address register is copied to the Color Value register and then
sequentially reading the color definitions for each location in the set
Whenever the Address register is updated, any furnished color definition
read or write is aborted and a new one may be begin.

VGA VIDEO CONTROLLER B-11

3.2.2.3 Color Value Register
The Color Value register is internally an 18-bit wide register used as a
buffer between the microprocessor interface and the color look-up table.
A value can be read from or written 10 this register by a sequence of
three-byte transfers at this register address. When a byte is written, only
the least significant six bits (D0-D5) are used. When a byte is read, only
the least significant six bits contain information. The most significant two
bits will be zero. The sequence of data transfer is RED, GREEN, then

BLUE. After writing three values to this register, its contents are written to
the location in the color look-up table specified by the Address register.
The Address register then increments. After reading three values from this
register, the contents of the location in the color look-up table specified by

the Address register are copied into the Color Value register. The Address register then increments. Each transter Letween the Color Vaiue
register and the color look-up table replaces the normal pixel mapping

operation of the OTI-066 tor a single pixel.

3.2.2.4 Pixel Mask Register
The Pixel Mask register can be used to mask selected bits of the Pixel

Address value applied to the Pixel Address inputs (PO-P7).

A'1"ina

position in the mask register leaves the corresponding bit in the Pixel
Address unaltered. A ‘0’ sets the corresponding bit to zero. The Pixel
Mask register does not affect the Address generated by the Microprocessor Interface when the look-up table is being accessed through that same
intertace.

8-12

VGA VIDEO CONTROLLER

8.2.2.5 Microprocessor Interface Timing Specifications
Table 8-2 shows the microprocessor interface timing specifications.

See Figure 8-5 through 8-13 for the timing modeis.

Table 8-2. Microprocessor Interface Timing Specifications
Symbol

Parameter

tWLWH
tRLRH

Max.

Min

Units Notes

-WR pulse width low

-RD pulse width low

tSVWL

tSVRL
tWLSX
tRLSX

10
10
10

nS
nS
nS

tDVWH

Write data set-up time

tWHDX

Write data hold time

tRLQX
tRLQV
tRHQX
tRHQZ
tWHWL1
tWHRL1

Output turn-on delay
Read enable access time
Output hold time
Output turn-off delay
Successive write interval
Write followed by read interval

5
40

tRHRL1

Successive read interval

4t
4t

nS
nS
nS
nS
ns
nS

tRHWL1

Read followed by write interval

tWHWL2

Write after color write

tWHRL2
tRHRL2
tRHWL?2
tWHRL3

Read atfter color write
Read after color read
Write after color read
Read after read address write
Write/Read enable transition time

20
41

1
3

3
3

2.3

4t
7t
7t
7t

nS
nS
nS
nS
nS

2.3
2.3
2.3
2.3

NOTES:

Measure 200 mV from steady state output voltage.

This parameter aliows for synchronization between operations on
the microprocessor interface and the pixel stream being
processed by the color look-up table.

1=PCLK period (tCHCH)

VGA VIDEO CONTROLLER 8-13

BASIC WRITE CYCLE
wh

RSO RS

Do.D?

BASIC READ CYCLE

o\,
AD

AS0 ASY

Do-D?

Figure 8-5. Microprocessor Interface Timing Model

8-14

VGA VIDEO CONTROLLER

S
T

e
s
X

o
S
7

Figure 8-6. Microprocessor Interface Timing Model Il

Read from:
a) pixel mask register
b) pixel address register (read mode)

c) pedel address register (write mode)

Figure 8-7. Microprocessor Intei face Timing Model ill

VGA VIDEQ CONTROLLER 8-15

.wn—\"'/lml B R I el
I

U 2

o [T\

S /L X

o087 — D~
Figure 8-8. Microprocessor Interface Timing Model IV

WR _\___/i'vm e

“RD

\__/

0007 —— o

\J U

\_/

NN/

e W\_

\_/

NSNS
X

o o<

Figure 8-9. Microprocessor Interface Timing Model V

8-16

VGA VIDEQ CONTROLLER

il B

BB X

-RD

=\ _ /7

N[\

[

DO-D7MHG~.:>——-<3:“9
Figure 8-10. Micropracessor Interface Timing Moc

O\ [\

[\ [T

DD
Figure 8-11. Microprocessor Interface Timing Mod

VGA VIDEO CONTROLLER 8-17

-WR

[

w T

T\
Note1

Note 1: The timing for raacing from address 0.0 is identica! to that for reacing from address 1.1

Figure 8-12. Microprocessor Interface Timing Model Viil

R
.

Y
o

/0 O N_ AN/

AL
i

an N e,

R
——

[

7o\

w007 (T
Note t. The timung for reading from address 0.0 is identical lo that for reading from address 1.1

Figure 8-13. Microprocessor interface Timing Model IX

8-18

VGA VIDEO CONTROLLER

8.3 OTI-069 Video Pixel Clock Generator
The OTI-069 Pixel Clock Generator is an integrated circuit specifically
designed for generating the video pixel frequencies required by OTI-067.
Phase-locked-ioop circuitry permits rapid, glitch-free transitions between
clock frequencies. A 14.31818 MHz series-resonant crystal with no
additional external components is all that is required for generating the
video pixel frequencies. A 6 MHz bandwidth CMOS op-amp, included in

the device, permits fast frequency acquisition and decreases phase jitter
and susceptibility to externally generated noise Figure 8-14 shows a
block diagram of the OTI-069 Video Pixel Clock Generator.
On-Chip teatures include:

Advanced PLL-low phase jitter

High frequency operation for extended video modes

Fast acquisition of selected frequencies

VGA VIDEO CONTROLLER 8-19

FS0

FS1

£S2

m || row

Fs3 ®+

saxm

XTAL 1 @ — xial
XTAL 2 @ —

Osc [TMTM1

input

Divder

. Phase 1 Crage (
|
1)
Comp

!
!

|
i

’—__—_-.—_.)

oPOUT

OP(-) (:)-———— -

OP-AMP

(16

’

Pump

CPSEL @

or(+)

VCOIN

;

veo
Output | FOUT

MUX

FREOO @

FREO1 @

Figure 8-14. OTI-069 Video Pixel Clock Generator Block Diagram

8-20

VGA VIDEO CONTROLLER

8.4 Video BIOS EPROM
The OTI-067 provides the necessary control and decodes to support a 16

or 8 bit BIOS ROM data path. in 8-bit BIOS ROM mode, the video memory
and I/0 space is still accessed in 16-bit mode. If set for 16-bit BIOS ROM
mode, the internal circuitry will automatically detect whether the adapter is
interfaced to an 8 or 16 bit PC bus. Upon Power-up reset, the ROM

paging feature is enabled by reading the preset configuration into the
configuration register.

8.5 Video RAM

The OTI-067 supports 256Kx4 DRAM in all modes. it supports

512 KBytes of DRAM by using four 256Kx4 DRAM chips. The OTI067 provides all the necessary control signals and address/data
lings to access the video memory in page mode. For a 45 MHz memory

clock, DRAMS with an access speed of 80 ns are required, 70ns DRAMs
are required for a 50 MHz memory clock. In extended modes with 256

colors, the video memory is organized in a packed pixel mode; 1 byte

from 1 plane as a pixel. This requires programming of an OT| extended
register. For 16 color extended modes, the video memory is organized as
planar mode (1 bit from each of 4 planes).

VGA VIDEO CONTROLLER 8-21

8-6 VGA Compatible Registers
The following sections describe the VGA Compatible registers. Table 8-3
lists the register |/O address the I/O function required to access the
register.

Table 8-3. VGA Compatible Register Address Map
Address
Mono Port

Color Port

3CCh/3C2n

3CCh/3C2h

VO Function

Read/Write

Miscellaneous

3C2h
3BAh

3C2h
3DAh

Read
Read

Output
tnput Status O
input Status 1

3CAR/3BAN

3CAh/3BAh

Read/Write

Feature Control

3C7n
3C4ah

3C7h
3C4n

Read
Read/Write

DAC
Sequencer Address

3C5h
3CEh
3CFh
3CFh
3CFh
3CFh
3CFh
3CFh
3CFn
3CFh
3CFh

3C5h
3CEh
3CFh
3CFh
3CFh
3CFh
3CFh
3CFh
3CFh
3CFh
3CFh

Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write

3C5h
3Csh
3C5h
3C5h

3C5h
3C5h
3Csh
3C5h

Read/Write
Read/Write
Read/Write
Read/Write

Reset
Ciocking Mode
MAP Mask
Character Map
Select

Memory Mode
Graphics Address
Set/Reset
Enable Set/Reset
Color Compare
Data Rotate
Read Map Select
Graphics Mode
Graphics Misc.
Color Don't Care
Bit Mask

index

00h
0th
02h
03h
04h
00h
01h
02h
03h
04h
05h
06h
07h
08h

8-22 VGA VIDEO CONTROLLER

Table 8-3. (Cont.) VGA Compatible Register Address Map
Address

VO Function

Index

3C0h
3C0Oh

Read/Write
Read/Write

Attribute Address
Color Palette

00-0Fh

3Con
3C0h
3C0h
3C0h

3C0h
3C0h
3COh
3COh

Read/Write
Read/Write
Read/Write
Read/Write

Mode Control
Overscan Color
Color Plane Enable
Horizontal Pixel

3C0Oh
3B4h
385h
3B5h

3C0oh
3D4h
3D5h
3D5h

Read/Write
Read/Write
Read/Write
Read/Write

Color Select
CRTC Address
Horizontal Total
Horizontal Display

Mono Port

Color Port

3Coh
3C0On

10h
11h
12h
13h

Panning

14h
-

00h

01h

Enable End

3B5h

3D5h

Read/Write

Start Horizontal

02h

Bianking

3B5h

3D5h

Read/Write

End Horizontal

03h

3B5h

3D5h

Read/Wrnite

Start Horizontal

04h

Blanking

Retrace Pulse

3B5h

3D5h

Read/Write

End Horizontal

05h

Retrace

3B5h
3B5h
3B5h

3D5h
3D5h
3D5h

Read/Write
Read/Write
Read/Write

3B5h

3D5h

Read/Write

3B5h
3B5h
3B5h
3B5h
3B5h

3D5h
3D5h
3D5h
3D5h
3D5h

Read/Write
Read/MWrite
Read/Write
Read/Write
Read/Write

3B5h
3B5h

3D5h
3D5h

Read/Write
Write

3B5h

3D5h

Write

Vertical Total
Qvertlow
Preset Row Scan

Maximum Scan Line
Cursor Start
Cursor End
Start Address High

06h
07h
0sh

Start Address Low

09h
OAh
0Bh
0Ch
oDh

High

OEh

Cursor Location Low
Vertical Retrace
Start
Vertical Retrace End

OFh

Cursor Locatiori

10h
11h

VGA VIDEO CONTROLLER 8-23

Table 8-3. (Cont.) VGA Compatible Register Address Map

Address
Mono Port

Color Port

3B5h

3D5h

VO Function

Reglster

Index

Read/Write

Vertical Display

12h

3B5h
3B5h
3B5h

3D5h
3D5h
3D5h

Read/Write
Read/Write
Read/Write

3B5h

3D5h

Read/Write

Enable End

Offset
Underline Location
Start Vertical
Blanking

End Vertical

13h
14h
15h
16h

Blanking

3B5h
3B5h

3D5sh
3D5h

Read/Write
Read/Write

CRTC Mode Control
Line Compare

17h
18h

3B5h

3D5h

Read

Readback CRT

22h

Latches

8.6.1 General Registers
General registers control miscellaneous output, input status, feature, DAC
operations in VGA compatible mode. The bit definitions for these registers are listed in Table 8-4 through 8-8.

8-24

VGA VIDEO CONTROLLER

8.6.1.1 Miscellaneous Output Register
Table 8-4. Miscellaneous Output Register Bit Assignment
Bit

Function
Vertical Sync Polarity
0 = Positive Vertical Retrace
1 = Negative Vertical Retrace

Horizontal Sync Polarity

0 = Positive Vertical Retrace
1 = Negative Vertical Retrace

Page Bit For Odd/Even
0 = Low 64K page of memory
1 = High 64K page of memory

0 = Reserved
3.2

Clock Select - These two hits, CSELO and CSEL1, are used
with 3DF index D bit 5 as follows:

CSEL2 CSEL1 CSELO CLOCK
0

25.175 Mhz

28.322 Mhz

65 Mhz

44
9 Mhz

14.161Mhz (derived trom 28.322)

18 Mhz (derived from 36 Mhz)

40 Mhz

36 Mhz

VGA VIDEO CONTROLLER 8-25

Table 8-4. (Cont.) Miscellaneous Output Register Bit Assignment
Bit

Function

Enable RAM
0 = Disable Video RAM address decode from the system
microprocessor

1 = Enable Video RAM to the system microprocessor
Input/Qutput Address Select
0 = Monochrome emulation with CRTC addresses set to

3Bxh, Input Status 1 reqister set to 3BAh
1 = Color emulation with CRTC addresses set to 3Dxh,
input Status 1 register set to 3DAh

8.6.1.2 Input Status 0 Register
Table 8-5. Input Status 0 Register Bit Assignment
Bit

Function

CRT interrupt
0 = Vertical retrace interrupt is pending
1 = Vertical retrace interrupt is cleared

Reserved

Switch Sense
0 = Selected sense switchisoff or 0
1 = Vertical retrace interrupt is on or 1

3.0

Reserved

8-26

VGA VIDEO CONTROLLER

8.6.1.3 Input Status 1 Register
Table 8-6. input Status 1 Register Bit Assignment

Bit

Function

Reserved

Diagnostic Usage - Reports the status of two of the eight
VGA attribute controller outputs. The values set into the
Video Status MUX field of the Color Plane Enable Register
determine which colors are input to these two diagnostic
bits

Color Plane Register

Input Status Register 1

Bit4

BitS

Bit4

BitS

Vertical Retrace
0 = Video information is being displayed
1 = A vertical retrace interval is in progress

Reserved

Display Enable
0 = The display of video data i1s enabled
1 = The display is in horizontal or vertical retrace mode

VGA VIDEQ CONTROLLER 8-27

8.6.1.4 Feature Control Register
Table 8-7. Feature Control Register Bit Assignment
Bit

Function

7:4

Reserved

Vertical Sync Select

0 = This bit should always be set to 0 to enable normal
vertical sync output to the monitor

1 = The vertical sync output is the logical OR of vertical
sync and vertical display enable
20

Reserved

8.6.1.5 DAC Registers
Table 8-8. DAC Registers Address Map

Port

Read/Write

3Ceh

Read/Write

PEL Mask

3C7n

Read

DAC State Register

3C7h

Write

PEL Address (Read Mode)

3C8h

Read/MWrite

PEL Address (Wnte Mode)

3C9h

Read/Write

PEL Data Register

8-28

VGA VIDEO CONTROLLER

8.6.2 Sequencer Registers
Sequencer registers control sequencer address reset, clocking
plane mask, character map select and memory mode operation

compatible mode. The bit definitions for these registers are liste
8-9 through 8-15.

8.6.2.1 Sequencer Address Register
This register is a pointer register located at address 3C4h. it is |
with a binary value that points to the Sequencer Data register wt

is to be written. This value is referred to as the index

Table 8-9. Sequencer Address Register Bit Assignme
Bit

Function

7:3

Reserved

Sequencer Address - A binary value pointing to ti
where data is to be read or written.

VGA VIDEO CONTROLLER 8-29

.6.2.2 Reset Register
This is a read/write register pointed to when the value in the Sequencer
Address register is 00h .

Table 8-10. Reset Register Bit Assignment

Bit

Function

7:2

Reserved

Synchronous Reset

0 = Synchronous clear and halt the sequencer
1 = Bit 1 and 0 must be 1 to aliow the sequencer to operate

Asynchronous Reset
0 = Asynchronous clear and halt the sequencer. This may

cause data loss in the dynamic RAMs
1 = Bit 1 and 0 must be 1 to allow the sequencer to operate

8-30

VGA VIDEO CONTROLLER

8.6.2.3 Clocking Mode Register
This is a read/write register pointed to when the value in the Sequencer
Address register is 01h .

Table 8-11. Clocking Mode Register Bit Assignment

Bit

Function

7.6

Reserved

Screen Off
0 = Normat screen operation

1 = Turns off the video screen and assigns the maximum

memory bandwidth to the system CPU
4

Shift 4

0 = The video serializers are reloaded every character

clock

1 = The senalizers are loaded every fourth character clock.
This is useful when 32 bits are fetched per cycle and

chained together in the shift registers

Dot Clock
0 = Select normal dot clocks derived from the sequencer
master clock input

1 = The master c.ock will be divided by 2 to generate the

dot clock. This is used for 320 and 360 horizontal PEL
modes

Shift Load
0 = If bit 4 is set to 0, also, the video serializers are
reloaded every character clock
1 = The video serializers are reloaded every other

character clock, this mode is useful when 16 bits are
fetched per cycle and chained together in the shift load
registers

Reserved

VGA VIDEO CONTROLLER 8-31

Table 8-11. (Cont.) Clocking Mode Register Bit Assignment
Bit

Function

8/9 dot Clocks - The 9 dot mode is for Alphanumeric
modes only. The ninth dot equals the eighth dot for ASCil

codes CO through DF hex. Also, see the Line Graphics

Character Code bit in the Attribute Mode Control register
section.

0 = Directs the sequencer to generate nine dot wide
character clocks
1 = Generate eight dot wide character ciocks

1.6.2.4 MAP Mask Register
This is read/write register pointed to when the value in the Sequencer
Address register is 02h.

Table 8-12. Map Mask Register Bit Assignment
Bit

Function

7.4

Reserved

3.0

Map Mask - For odd/even modes, maps 0 and 1, and maps
2 ad 3 should have the same map mask value. When chan
4 mode is selected, all maps should be enabled. Thisis a
read-modify-write operation.

0 = Disable memory write to the corresponding map
1 = Enables the system to write to the corresponding map.
If ali four bits are set to 1, the system CPU can
perform a 32-bit operation with only one memory cycle

8-32

VGA VIDEO CONTROLLER

8.6.2.5 Character Map Select Register
This is a read/write register pointed to when the value in the Sequencer
Address register is 03h.

Table 8-13. Character Map Select Register Bit Assignment
Function

Reserved

Character Map Select High Bit A

Character Map Select High Bit B

Character Map Select A

Bit3

Bit2

Map

Yable Location

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
1
2
3
4
5
6
7

1st 8k of Map 2
3rd 8k of Map 2
5th 8k of Map 2
7th 8k of Map 2
2nd 8k of Map 2
4th 8k of Map 2
6th 8k of Map 2
8th Bk of Map 2

Table Location

=0
-0
=20
O

- =00
OO

Bit0

Bit 1

—_—

-3

Character Map Select B

Ao 420000 1

1:0

Bit5

NO O A WN-O E

Bit

1st 8k of Map 2

3rd 8k of Map 2
5th 8k of Map 2

7th 8k of Map 2
2nd 8k of Map 2
4th Bk of Map 2

6th 8k of Map 2
8th 8k of Map 2

VGA VIDEQO CONTROLLER 8-33

.6.2.6 Memory Mode Register
This is a read/write register pointed to when the value in the Sequencer
Address register is 04h.

Table 8-14. Memory Mode Register Bit Assignment

Bit

Function

Reserved

Chain 4
0 = If bit 2 is set to 1, this bit enables the system CPU to
address data sequentially within a bit map by use of

the Map Mask register
1 = Causes two low-order address bits to select the map

that will be accessed as follows:

Map Selected
0

Odd/Even
0 = Directs even CPU addresses to access maps 0 and 2,
and odd CPU addresses to access maps 1 and 3
1 = If bit 3is setto O, this bit causes system CPU
Addresses to sequentially address data within a bit
map

Extended Memory
0 = No extended memory present. Display memory is less
than 64 Kbytes
1 = Extended memory is present. Display memory is
greater than 64 Kbytes. If set to 1 the VGA is permitted

to use the 256k bytes ot video memory. This also
enables character map selection

Reserved

8-34

VGA VIDEO CONTROLLER

8.6.3 Graphics Controller Registers
Graphics Controller registers control graphics set/rest, color compare,
data rotate, read map select, and bit mask operations in VGA compatible
mode. The bit definitions for these registers are listed in Table 8-15
through B-24.

8.6.3.1 Graphics Address Register
Table 8-15. Graphics Address Register Bit Assignment

Bit

Function

7.4

Reserved

3.0

Graphics Address Bits - These bits are used to point to the
other registers in the graphics section.

8.6.3.2 Set/Reset Register
Tab!e 8-16. Set/Rest Register Bit Assignment

Bit

Function

7.4

Reserved

3.0

This field represents the value written 1o all 8 bit of the
respective memory map when the system CPU does a
memory write with write mode 0 selected and Set/Reset
mode is enabled for the corresponding map. However, in
write mode 3, enable Set/Reset register has no effect.

VGA VIDEO CONTROLLER 8-35

.6.3.3 Enable Set/Reset Register
Table 8-17. Enable Set/Reset Register Bit Assignment

Bit

Function

7:4

Reserved

Enable Set/Reset
0 = If write mode is O and Set/Reset is not enabled on a
map, that map is written with the value of the system
CPU
1 = If write mode is O and Set/Reset is enabled on a map.

the respective memory 1s written with the vaiue of the
Set/Reset register

6.3.4 Color Compare Register
Table 8-18. Color Compare Register Bit Assignment

Bit

Function

7.4

Reserved

4-bit color value 1o be compared

8-36

VGA VIDEO CONTROLLER

8.6.3.5 Data Rotate Register
Table 8-19. Data Rotate Register Bit Assignment

Bit

Function

Reserved

4:3

Function Select

2.0

Bit4

Bit3

Function

Data unmodified

Data ANDed with latch data

Data ORed with latch data

Data XORed with latch data

Rotate Count - This field represents a binary encoded value
of the number of positions to right-rotate the system CPU
data bus during system CPU memory writes. This rotation
occurs before any other logical operation on the data takes
place. This operation is done when write mode is 0. To

write non-rotated data the system CPU must select a count

of 0.

8.6.3.6 Read Map Select Register
Table 8-20. Read Map Select Register Bit Assignment

Bit

Function

7.2

Reserved

1.0

Map Select - This field represents a binary encoded value

of the memory map number from which the system CPU
reads data. This register has no effect on the color compare read mode. In odd/even modes the value may be 00
or 01 (10 or 11) for chained maps 0.1 (2,3).

VGA VIDEO CONTROLLER 8-37

8.6.3.7 Graphics Mode Register
Table 8-21. Graphics Mode Reglster Bit Assignment
Bit

Function
Reserved

256 Color Mode
0 = Allows bit 5 to control the loading of the Shift registers
1 = Causes the Shift register to be loaded in a manner that

supports the 256-color mode
Shift Register
Odd/Even

0 = Normal VGA mode
1 = Selects the odd/even addressing mode used to

emulate the IBM CGA compatible modes
Read Type

0 = The system microprocessor reads data from the

memoary map selected by the Read Map Select
register. Read Map Select register has no effect if bit 3

of the Sequencer Memory Mode register eguals 1.
Bit O of the Read Map Select register has no effect if
bit 4 of the Graphic Mode register equals 1.
1 = The system microprocessor reads the results of the

comparison of the 4 memory maps and the Color
Compare register.
Reserved

8-38

VGA VIDEO CONTROLLER

Table 8-21. (Cont.) Graphics Mode Register Bit Assignment

Bit

Function

1.0

Write Mode

Bit1 Bit0 Function
0

Each memaory map is written with the
system CPU data rotated by the number of

counts in the Rotated register, unless
Set/Reset is enabled for the map. Maps for
which Set/Reset is enabled are written with
8-bits of the value contained in the
Set/Reset register for that map.

Each memory map is written with the
contents of the system CPU latches. These
latches are loaded by a system CPU Read
operation.

Memory map n (0-3) is filled with 8-bits of
the value of data bit n.

Each map is written with 8-bits of the value
contained in the Set/Reset register for that
map (Enable Set/Reset register has no
eftect). Rotated system CPU data is
ANDed with the Bit Mask register data 1o
form an 8-bit value that performs the same
function as the Bit Mask register does In

write modes 0 and 2

VGA VIDEO CONTROLLER 8-39

8.6.3.8 Miscellaneonus Register
Table £-22. Miscellaneous Register Bit Assignment

Bit

Function

Reserved

Memory Map

Bit3

Bit2

Functiop

Hex A0OOO for 128K bytes

Hex ADQDO for 64K bytes

Hex BOOO0O for 32K bytes

Hex BB0O0DO for 32K bytes

Odd/Even
0 = Standard VGA addressing
1 = Replace system CPU address bit 0 with a higher-order

address bit and select odd/even maps with odd/feven
values of the system CPU AQ bit, respectively
0

Graphics Mode

0 = Selects text mode operation
1 = Selects graphics mode. When this mode is selected,

the character generator address latches are disabled

8-40

VGA VIDEO CONTROLLER

8.6.3.9 Color Don’t Care Register
Table 8-23. Color Don't Care Register Bit Assignment
Bit

Function

7:4

Reserved
Map 3

0 = Don't participate in the color compare cycle
1 = Participate in the color compare cycle

Map 2

0 = Don't participate in the color compare cycle
1 = Participate in the color compare cycle

Map 1

0 = Don't participate in the color compare cycle
1 = Participate in the color compare cycle

Map O

0 = Don't participate in the color compare cycle
1 = Participate in the color compare cycle

8.6.3.10 Bit Mask Register
Table 8-24. Bit Mask Register Bit Assignment
Bit

Function

7:0

Bit Mask
0 = Any bit set to 0 causes the corresponding bit n in each
map to be immune to change, provided that the
location being written was the last location read by the

system CPU
1 = Bits set to 1 allow unimpeded writes to the
corresponding bits in the maps

VGA VIDEOC CONTROLLER 8-41

8.6.4 Attribute Controller Registers
Attribute Controlier registers control color palette, overscan, color plane

enable, horizontal pixel panning and color select operations in VGA
compatible mode. The bit definitions for these registers are listed in Table
8-25 through 8-31.

8.6.4.1 Attribute Address Register
Table 8-25. Attribute Address Register Bit Assignment

Bit

Function

7:6

Reserved

Palette Address Source

Attribute Address

8.6.4.2 Palette Registers 0 - 15
Table 8-26. Palette Registers 0-15 Bit Assignment

Bit

Function

7.6

Reserved

Palette

8-42

VGA VIDEO CONTROLLER

8.6.4.3 Attribute Mode Control Register
Table 8-27. Attribute Mode Control Register Bit Assig
Bit
7

Function

P5,P4 Select

0 = P5 and P4 are the outputs of the Palette re
1 = P5 and P4 are bits 1 and 0 of the Color Sel
PEL. Width

0 = All modes except for mode 13 hex
1 = The video pipeline is sampled so that 8-bit
able to select a color in the 256-color mod
PEL Panning Compatibility
0 = Line compare has no effect on the output
Panning register

1 = A successful line compare in the CRT cont

the output of the PEL Panning registers to
+VSYNC occurs, at which time the output |
programmed value. This bit allows a selec
the screen to be panned
Reserved

Enable Blink/Select Background Intensity
0 = Selects the background intensity of the att
which was available on the Monochrome ¢
adapters

1 = Enables the blink attribute in text modes a
graphics modes

VGA VIDEO CONTROLLER 8-43

Table 8-27. (Cont.) Attribute Mode Control Register Bit Assignment
Bit

Function

Enabie line Graphics Character Codes
0 = The ninth dot will be the same as the background
1 = Enables the special line graphics character codes for
Monochrome emulation mode. When enabled, this bit
forces the ninth dot of a line graphic character to be

identical to the eighth dot of the character. The line
graphics character modes tor the Monochrome

emulation mode are CO hex through DF hex. For
character fonts that do not use the line graphics

character codes this range, bit 2 should be setto 0.
Otherwise, unwanted video information will be
displayed on the CRT screen
1

Mono Emulation
0 = Color emulation mode is set
1 = Monochrome emulation mode is set

Graphics/Alphanumeric Mode
0 = Selects alphanumeric mode
1 = Selects graphics mode

8.6.4.4 Overscan Color Register
Table 8-28. Overscan Color Register Bit Assignment
Bit

Function

7:0

Overscan Color

8-44

VGA VIDEO CONTROLLER

8.6.4.5 Color Plane Enable Register
Table 8-29. Color Plane Enable Register Bit Assignme

Bit

Function

Reserved

Video Status MUX
Color Piane Register

3.0

Input Status Register

BitS

Bit4

BitS

Bitg

Enable Color Plane

VGA VIDEO CONTROLLER 8-45

8.6.4.6 Horizontal PEL Panning Register
Tabie 8-30. Horizontal PEL Panning Register Bit Assignment

Bit

Function

7:4

Reserved

Horizontal PEL Panning - This register selects the number
of picture elements (PELs) to shift the video data harizontally to the left. PEL panning is availabie in both graphics
and text modes. in monochrome emulation text modes and

modes 0+, 1+, 2+, 3+, the image can be shifted a maximum of 8 PELs. Mode 13 allows a maximum shift of 3 PELs.
Programming 1,3,5, or 7 into the PEL Panning register
during mode 13 will cause a color change on the display.
All other modes, the image can be shifted a maximum of 7
PELs. The sequence for shifting the image is as follows

PEL Panning

Number of PELs Shifted 1o the jeft
0+.1+2+.3+.7.7+

All Other modes Mode 13

8-46

VGA VIDEO CONTROLLER

8.6.4.7 Color Select Register
Table 8-31. Color Select Register Bit Assignment
Bit

Function

7:4

Reserved

3.2

S_color 7,6

S_color 5,4

8.6.5 CRT Controller Registers
8.6.5.1 CRT Controller Address Register
This register is a pointer register located at 3B4h for Monochrome emuta-

tion modes or 3D4h for Color emulation modes depending on bit 0 of the
Miscellaneous output register at address 3C2h. The CRT Controller
Addresses register 1s loaded with a binary value, or index, that points to

the CRT Controller Data register where data is to be written. Ali CRT
controller registers are read/write registers.

Table 8-32. CRT Controller Address Register Bit Assignment
Bit

Function

7:6

Reserved

Test

4:0

CRT Controller Address

VGA VIDEO CONTROLLER 8-47

.6.5.2 Horizontal Total Register
Table 8-33. Horizontal Total Register Bit Assignment
Bit

Function

7:0

Horizontat Total

.6.5.3 Horizontal Display Enable End Register
Table 8-34. Horizontal Display Enable End Register Bit Assignment
Bit

Function

7.0

Horizontai Display Enable End

.6.5.4 Start Horizontal Blanking Register
Table 8-35. Start Horizontal Blanking Register Bit Assignment
Bit

Function

7.0

Start Horizontal Blanking

8-48

VGA VIDEO CONTROLLER

8.6.5.5 End Horizontal Blanking Register
This register determines when the horizonta! blanking output signal

becomes inactive.

Table 8-36. End Horizontal Blanking Register Bit Assignment

Bit

Function

Test

Display Enable

Bit6

Skew

Zero character clock skew

One character clock skew

Two character clock skew

Three character clock skew

End Horizontal Blanking

8.6.5.6 Start Horizontal Retrace Pulse Register
Table 8-37. Start Horizontal Retrace Puise Register Bit Assignment
Bit

Function

7.0

Start Horizontal Retrace Pulse

VGA VIDEO CONTROLLER 8-49

.6.5.7 End Horizontal Retrace Register
This register specifies the character position at which the Horizontal

Retrace Pulse becomes inactive.

Table 8-38. End Horizontal Retrace Register Bit Assignment

Bit

Function

End Horizonta! Blanking

6:5

Horizonta! Retrace Delay

4.0

Bit6

BitS

Amountof Skew

Zero skew

One skew

Two skew

Three skew

End Horizontal Retrace

6.5.8 Vertical Total Register
Table 8-39. Vertical Total Register Bit Assignment

Bit

Function

7.0

Vertical Total

8-50

VGA VIDEO CONTROLLER

8.6.5.9 CRT Controller Overflow Register
Table 8-40. CRT Controller Overflow Register Bit Assignment
Bit

Function

Vertical Retracer Start
Vertical Display Enable END
Vertical Total

Line Compare

Start Vertical Blank

Vertical Retrace Start
Vertical Display

Vertical Total

8.6.5.10 Preset Row Scan Register
Table 8-41. Preset Row Scan Register Bit Assignment
Bit

Function

Reserved

Byte Panning Control

4:0

Preset Row Scan {(PEL Scrolling)

VGA VIDEO CONTROLLER 8-51

3.6.5.11 Maximum Scan Line Register
Table 8-42. Maximum Scan Line Register Bit Assignment

Bit

Function

200 to 400 Line conversion

Line Compare

Start Vertical Biank

Maximum Scan Line

.6.5.12 Cursor Start Register
Table 8-43. Cursor Start Register Bit Assignment
Bit

Function

Reserved

Cursor Off

0 = Turns on the cursor
1 = Turns off the cursor
4:0

Cursor Start

852

VGA VIDEO CONTROLLER

8.6.5.13 Cursor End Register
Table 8-44. Cursor End Register Bit Assignment

Bit

Function

Reserved

6:5

Cursor Skew

Bit6 Bit5 Function

Zero-character clock skew

One-character clock skew

Two-character ciock skew

Three-character clock skew

Cursor End

8.6.5.14 Start Address High Register
Table 8-45. Start Address High Register Bit Assignment

Bit

Function

7.0

Start Address High

8.6.5.15 Start Address Low Register
Table 8-46. Start Address Low Register Bit Assignment
Bit

Function

7.0

Start Address Low

VGA VIDEO CONTROLLER 8-53

3.6.5.16 Cursor Location High Register
Table 8-47. Cursor Location High Register Bit Assignment

Bit

Function

7.0

Cursor High

8.6.5.17 Cursor Location Low Register
Table 8-48. Cursor Location Low Register Bit Assignment
Bit

Function

7:0

Cursor Low

8.6.5.18 Vertical Retrace Start Register
Table 8-49. Vertical Retrace Start Register Bit Assignment
Bit

Function

7:0

Vertical Retrace Start

8-54

VGA VIDEO CONTROLLER

8.6.5.19 Vertical Retrace End Register
Table 8-50. Vertical Retrace End Register Bit Assignment

Bit

Function

Protect RO-7
0 = Enables writing to CRTC registers 0-7
1 = Disables writing to CRTC registers 0-7. The line
compare bit 4 in register 07 hex is not protected

Select 5 Refresh Cycles
0 = Selects three refresh cycles. The BIOS sets thisbit to 0
during a mode set, a reset, or power on

1 = Selects five refresh cycles per horizontal line. This allow
the use of the VGA chip with slow sweep rate displays
(15.75 kHz)

Enable Vertical Interrupt
0 = Enables a vertical retrace interrupt (on IRQ2) This
interrupt level may be shared so the Input Status
register 0, bit 7 should be checked to find out is the

VGA caused the interrupt 10 occur
1 = Disable the vertical retrace interrupt

Clear Vertical Interrupt

0 = Clears the vertical retrace interrupt flip-flop
1 = Allows the vertical interrupt to be set at the start of the
next vertical retrace interval

3.0

Vertical Retrace End

8.6.5.20 Vertical Display Enable End Register
Table 8-51. Vertical Display Enabie End Register Bit Assignment
Bit

Function

7:0

Vertical Display Enable End

VGA VIDEC CONTROLLER 8-55

8.6.5.21 Offset Register
Table 8-52. Oftset Register Bit Assignment

Bit

Function

7:0

Offset

8.6.5.22 Underline Location Register
Table 8-53. Underline Location Register Bit Assignment
Bit

Function

Reserved

€

Doubleword Mode
0 = Normal word addressing mode
1 = Memory addresses are doubleword addresses

Count By 4
0 = Normal clocking
1 = The memory address counter is ciocked with the

character clock divided by 4
40

Underiine Location

8.6 5.23 Start Vertical Blanking Register
Table 8-54. Start Vertical Blanking Register Bit Assignment
Bit

Function

7.0

Start Vertical blank

8-56

VGA VIDEO CONTROLLER

8.6.5.24 End Vertical Blanking Register
Table 8-55. End Vertical Blanking Register Bit Assignment

Bit

Function

7:0

End Vertical Blank

8.6.5.25 CRTC Mode Control Register
Table 8-56. CRTC Mode Control Register Bit Assignment
Bit
7

Function
Hardware Reset
0 = Forces horizontal and vertical retrace to clear
1 = Forces horizontal and vertical retrace to be enabled

Word Mode or Byte Mode
0 = The word mode shifts all memory address counter bits
down one bit, and the most-significant bit of the
counter appears on the least-significant bnt of the
memory address outputs

1 = Selects the byte address mode

Address Wrap
0 = Selects MA13. This is selected in applications where
only 64K memory is present
1 = Selects MA15. This should be selected in odd/even
mode since 256K of video memory is instalied on the

system board
4

Reserved

Count By Two

0 = The memory address counter is clocked with the
character clock input
1 = Clocks the memory address counter with the character
clock input divided by 2

VGA VIDEO CONTROLLER 8-57

Table 8-56. (Cont.) CRTC Mode Control Register Bit Assignment
Bit

Function

Horizontal Retrace Select
0 = Selects normal horizontal retrace as the clock that
controls the vertical timing counter
1 = Selects horizontal retrace divided by 2 as the clock that

controls the vertical timing counter. Therefore, the
vertical resolution is doubled to 2048 honzontal scan
lines

Select Row Scan Counter

0 = Selects row scan counter bit 1 for CRT memory ad
dress bit MA14
1 = Selects MA14 counter bit for CRT memory address bit

MA14

Compatibility Mode Support
0 = Row scan address bit 0 is substituted for memory
address bit 13 during active display time
1 = Enables memory address bit 13 to appear on the
memory address output bit 13 of the CRT controller

8.6.5.26 Line Compare Register
Table 8-57. Line Compare Register Bit Assignment

Bit

Function

Line Compare

8-58

VGA VIDEO CONTROLLER

8.7

Extended Registers
There are fourteen extended registers that occupy two /O ports at ad-

dress 3DEh and 3DFh. Table 8-58 list the register /O address, the /O
function, index and bits. The bit definitions for these registers are listed in
Table 8-59 through 8-70.

Table 8-58. Extended Register Address Map

Port

VO Function

3DEh
3DFh
3DFh
3DFh
3DFh

Read/Write
Read/Write
Read/Write
Read/Write
Read/MWrite

Read/Write

Extension Address Register
Scratch Register 1
Scratch Register 2
Scratch Register 3
CRT Control Register
OTI Miscellaneous Register

3DFh

Read/Write

Backward Compatibility

3DFh

Read

3DFh

Read

3DFh

Index

Bits

9
A
B
C
D

5
8
8
8
8

NMI Data Cache Register

DIP Switch Read

Read

Configuration Register

3DFh

Read/Write

Bus Control Register

3DFh

Read/Write

OTI Overflow Register

3DFh

Read/Write

HSYNC/2 Start Register

3DFh

Read/Write

Segment Register

8.7.1 Extension Address Register
Table 8-59. Extension Address Register Bit Assignment
Bit

Function

4:0

5-bit index pointer to the extension
data registers

VGA VIDEO CONTROLLER 8-59

8.7.2 Scratch Registers 1-3
Table 8-60. Scratch Registers 1-3 Bit Assignment

Bit

Function

8 scratch bits

3.7.3 CRT Control Register
Table 8-61. CRT Control Register Bit Assignment

Bit

Function

In CGA/Hercules emulation mode

Vertical SYNC test

Attribute test

A logic 1 selects 64 internal latches for fully 16 bit operation

I/Q write test

When set to 1, the Maximum Scan Lineregister bitQto 4
are write protected

When set to 1, the following registers inCRT Controlier area
are write protected

When set to 1, the following registers in CRT Controller area
are write protected

8-60

VGA VIDEO CONTROLLER

8.7.4 OTl Miscellaneous Register
Table 8-62. OTI Miscellaneous Register Bit Assignment

Bit

Function

DRAM configuration

Reserved

Clock select bit 2 (CSEL2)

CSEL2 CSEL1 CSELO CLOCK

4:3

2:0

25.175 Mhz

28.322 Mhz

65 Mhz

449 Mhz

14.161Mhz (derived from 28.322)

18 Mhz (derived from 36 Mhz)

40 Mhz

36 Mhz

Extended graphics mode selection

Bit4

Bit3

Mode Selection

Non extended graphics modes

640x480 256 colors, 800x600 256 coors

1024x768 4 colors

1024x768 16 colors

FIFO depth control

VGA VIDEO CONTROLLER 8-61

8.7.5 Backward Compatibility Register
Table 8-63. Backward Compatibility Register Bit Assignment

Bit

Function

Graphics Latch read mode
CRT test
When this bit and bit 0 are both set to 1. it enables the NMI
function
It enables 64K address mapping at BOOOO when set this bit
to 1

Page select during Hercules mode

2:1

Bit3

Page

Backward Compatibility Mode
Bit2
Bit1 Mode

VGA

EGA

CGA

HERCULES & MDA

When both this bit and bit 5 are set to 1, the NM! based 1O
trap is enabled for downward compatibility emulation

8-62

VGA VIDEO CONTROLLER

8.7.6 NMI Data Cache Register
Table 8-64. NMI Data Cache Register Bit Assignment

Bit

Function

7.0

The address of the trapped I/O

8.7.7 DIP Switch Read Register
Table 8-65. DIP Switch Read Register Bit Assignment

Bit

Function

JP2 (OFF/ON)

JP1 (OFF/ON)

DIP Switch 6 (Reserved)

DIP Switch 5 (Reserved)

DIP Switch 4

DIP Switch 3

DIP Switch 2

DIP Switch 1

VGA VIDEO CONTROLLER 8-63

7.8 Segment Register
Table 8-66. Segment Register Bit Assignment

8it

Function

Reserved

6.4

Write segment for CPU memory write

Reserved

Read segment for CPU memory read

1.7.9 Configuration Register
Table 8-67. Configuration Register Bit Assignment
Bit

Function

HSYNC

VSYNC

CSELO-2

RA14

RA13

RA12

8-64

VGA VIDEO CONTROLLER

8.7.10 Bus Control Register
Table 8-68. Bus Control Register Bit Assignme
Bit

Function

0=8-bit memory access
1=16-bit memory access

0=8-bit /O access
1=16-bit /O access

O=Enable video BIOS ROM access
1=Disable video BIOS ROM access

O=Enabie 8-bit video BIOS ROM interface
1=Disable 16-bit video BIOS ROM interface
31

Recerved

0=Enable access of C6000 to C67FF address

1=Disable access of C6000 to C67FF address

VGA VIDEO CONTROLLER 8-65

.7.11 OTI Overflow Register
Table 8-69. OTi Overflow Register Bit Assignment

Bit

Function

Enable interlaced display

Page select for video memory access

Page select for CRT display

High Order Cursor Location Bit 8

High Order Start Address Bit 8

Vertical Retrace Start Bit 10

Vertical Blank Start Bit 10

Vertical Total Bit 10

.7.12 Hsync Divided By 2 Start Register
Table 8-70. Hsync Divided By 2 Start Register Bit Assignment
Bit

Function

This 7 bit value indicates when the vertical retrace will start
in every odd frame during interlaced mode

8-66

VGA VIDEO CONTROLLER

8.8 Supported Screen Formats

Table 8-71. Standard VGA Modes Supportec

MODE Type

COLXROW

Colors

Pages Map A

00h
01h
02h
03h

Text
Text
Text
Text

40x25
40x25
80x25
80x25

16
16
16
16

B
8
8
8

B80O
B800
B800!
BBOO

00h*

Text

40x25

B8O

01h*

Text

40x25

B800

80x25
BOx25
40x25
40x25
80x25
80x25
80x25
80x25
320x200
320x200
640x200

16
16
16
16
16
16
2
2
4
4
2

8
8
8
8
B
8
8
8
1
1
1

B80O
B800
B800
B800
B8O
8800
B0OOO
B0OOO
B800
B800
8800

02h"
Text
03h"
Text
00h+ Text
01h+ Text
02h+ Text
03h+ Text
07h
Text
07h+ Text
04h
Graphics
05h
Graphics
06h
Graphics

0Dh

Graphics

320x200

186

AQO!

OEh
OFh

Graphics
Graphics

640x200
640x350

16
2

4
2

AQO
AQ00

10h

Graphics

640x350

AQ0C

11h

Graphics

640x480

AQOC

Graphics

640x480

2
16

12h

AD0C

13h

Graphics

320x200

256

AQO!

NOTES:

Modes marked with * or + are Expanded Character (
of the original modes.

Mode 3+(color) or 7+(monochrome) is the default m
up.

VGA VIDEO CONTROLLER 8-67

Table 8-72. Extended Modes Supported

MODE Type

COLxROW

Colors

Pages Map Addr CharCell

4Fh

Text

132x60

B800h

8x8

50h
51h
52h

Text
Text
Graphics

132x25
132x43
800x600

16
16
16

4
2
1

B800h
B800h
AQ00h

8x14
8x8

53h

Graphics

640x480

256

ADOOh

8x16

54h

Graphics

800x600

256

AD0Ch

B8x16

55h
56h
57h

Graphics
Graphics
PORTRAIT

1024x768
1024x768
768x1024

4
16
4

1
1
1

AQ0Oh
A00Ch
AQ0Oh

8x16
8x16

8x16

Table 8-73. Sync Specifications for Standard VGA Modes
Dot Clk (MHz)

Hsync (KHz)

Vsync (Hz) Mode

25172

315

25172

315

11,12
0.1.0.1,2.3.2".3.4,5
6.D E.F 10, 1 3

28.322

315

O+, 1+. 2+, 3+. 7. 7+

8-68

VGA VIDEO CONTROLLER

Table 8-74. Sync Specifications for OTI Extended Modes

Dot Clk (MHz)

Hsync (KHz)

Vsync (Hz)

Mode

25.175
28.322
36.000
40.000
40.000
44 900
44 900
65.000
65.000

31.47
2227
35.16
31.25
31.25
35.62
46.77
48.08
59.74

5994
59.22
56.16
59.64
69.60
43.32
43.15
59.80
55.22

53
50m, 51m
52, 54
4F
50, 51
551, 561
57i
55, 56
57

NOTES:

m : multifrequency
i: Interlaced

8.9 Signal Definitions
8.9.1 OTI-067 Signal Definitions
Table 8-75. OTI-067 Signal Name

-CAS

MB1

OOWWwND®

b WM
—

OTI-067
Signal Name

Pin Number

-RAS
-WE23
MBO

MB2
MB3

GND
MB4
MB5

VGA VIDEO CONTROLLER 8-69

Table 8-75. (Cont.) OTI-067 Signal Name
OTI-067

Pin Number

Signal Name

MB6

mB7

MB8

vCC

MDO

MD1

MD2

MD3

MD4

MD5

GND

22
23
24
25

MDé
MD7
MD8
MD9

26
27
28
29
30

MD10
MD11
MD12
MD13
GND

MD14

MD15

SD15

34
35

SD14
SD13

36
37
38
39

sD12
SD11
SD10
SD9

sD8

8-70

VGA VIDEQO CONTROLLER

Table 8-75. (Cont.) OTI-067Signal Name

Pin Number

OTI-067
Signal Name

41
42
43
44
45

GND
LA17
LA1B

LA21

LA22

48
49
50

LAZ3
-BHEN

51
52
53
54
55

-M16
GND
BDO
BD1
BD2

56
57
58
59
60

BD3
vCC
BD4
BDS
BD6

61
62

BD7
VCC

64
65

67
68
69
70

LA19
LA20

-1016

-ROMENL
RA12
RA13

RA14

SAD
SA1
SA2
SA3

VGA VIDEO CONTROLLER 8-71

Table 8-75. (Cont.) OTI-067 Signal Name
OTI-067

Pin Number

Signal Name

SA4

SA5

73
74
75

SA6
SA7
SA8

76
77
78
79
80

SA9
SA10
SA11
SA12
SA13

a1
82
83
84
85

SA14
SA15
SA16
SA17
SA18

86
87
88
89
90

SA19
AEN
-RFSH
-IOR
-IOW

N
92
a3

GND
-MRD
-MWR

VCC

SDO

96
97
98
99
100

SD1
SD2
SD3
SD4
SDSs

8-72

VGA VIDEO CONTROLLER

Table 8-75. (Cont.) OTI-067 Signal Name
OTi-067
Pin Number

Signal Name

101

GND

102

SD6

103

SD7

104

-CINT

105

-NMI

106

RSET

107

RDY

108

-RDSW

109

VSYNC

110

HSYNC

111

PCLK

112

-BLANK

113

-DACR

114

-DACW

115

116

117

GND

118

119

120

121

122

123

124

GND

125

SWSENSE

126

VSETUP

127

ENVGA

128

VvCC

129

MCLK

130

VCLK

VGA VIDEO CONTROLLER 8-73

Table 8-75. (Cont.) OTi-067 Signal Name
OoTI-067

Pin Number

Signal Name

131
132
133

CSEL2
CSEL1
CSELO

134

MAO

135

MA1

136
137
138
139
140

MA2
MA3
MA4
GND

141
142

MA6
WAz

143
144

MA8
-WEO1

MAS

8-74

VGA VIDEO CONTROLLER

8.9.2 OTI-066 Signal Definitions
Table 8-76. OTI-066 Signal Name
OTI-066

Pin Number

Signal Name

1
2

RED
GREEN

BLUE

IREF

6
7
8
9
10

P1
p2
P3
P4

12
13
14

P7
PCLK
VSS

VCC

RS1

17
13
19

RSO
-WR
D7

21
22
23
24
25

D5
D4
D3
D2
D1

26
27
28

Do
-BLANK
-RD

VGA VIDEO CONTROLLER 8-75

8.9.3 OTI-069 Signal Definitions
Table 8-77. OTI-069 signal Name
Pin Number

OTi-069
Signal Name
FS3

STROBE
vDD
FREQ1

XTALA1
XTF L2

FREQO

VSS
FOUT

CPSEL

out
AVDC
VCO(IN)

OP(OUT)

OP(-)
OP(+)
AVSS

FSO
FS1
FS2

8-76

VGA VIDEO CONTROLLER

8.10 Signal Description
8.10.1 OTI-067 Signal Description
8.10.1.1 CPU Bus Interface
AEN
ADDRESS ENABLE. This signal is used to qualify the video me

access from CPU. When it is active high, the DMA controller h
the address bus, data bus, and command lines.

-RFSH
REFRESH. This signa! is used to qualify the video memory acc
CPU. When it is active low, it indicate a memory refresh cycle.
-10R

IO READ. Thus is an active low /O read strobe, asserted in 8/
read cycle.

-1OW

IO WRITE. This i1s an active iow /O write strobe, asserted in 8
write cycle

-MRD

MEMORY READ. This is an active low memory read strobe, at
16 bit memory read cycle.

-MWR

MEMORY WRITE. This is an active iow memory write strobe, ¢
16 bit memory write cycile.

REST

RESET. Active high system reset signal. This input signal will
OTI-067 and initizlize the configuration register based on the

on CSELO-2, RA[14:12], HSYNC, and VSYNC pins at power-u
RDY

CUP READY. An open collector active high output to signal p
it is ready for memory access. This signal is used to add wait

bus cycle during video memory access. It is pulled low by O
after the video memory access request by CPU to allow addi
finish the memory cycle.

VGA VIDEQ CONTROLLER 8-77

-NMI

NON MASKABLE INTERRUPT. An active low open collector signal. This
signal is used to activate the interrupt-driven programs.
-CINT
CRT INTERRUPT REQUEST. An interrupt request is generated when
vertical retrace occurs if it is enabled by bit § in the Vertical Retrace End
register. It is an active low open collector output.
-M16

16-BIT MLMORY. It is an active low open collector ouiput signal used to
indicate to the system that the present data transfer is a 16-bit memory
cycle. It is denved from the decode of LA17 through LA23.
<1016

16-Bit I/O. It is an active low open collector output signal used to indicate

to the system that the present data transfer is a 16-bit 1/O cycie. Itis
derived from an address decode.
-BHEN

BYTE HIGH ENABLE. When the OTI-067 is in 16 bit mode, this active low

signal indicates a transfer of data on the high byte of the data bus (SD[158)]).

SD[15:8]
DATA LINE 15-8. CPU data bus bit 15-8.
SD[7:0}

DATA LINE 7-0. CPU data bus bit 7-0.

SA[19:0]
ADDRESS LINE 19-0. CPU address bus bit 19-0.
LA[23:17)]

UNLATCHED ADDRESS LINE 23-17. CPU unlatched bus fine 23-17.

8.10.1.2 BIOS ROM Control
-ROMENL

ROM LOW BYTE ENABLE. An active low signal to enable/control the low

byte of BIOS data to CPU data bus in 16 bit BIOS mode In 8 bit BIOS
mode, this pin is not used.

8-78

VGA VIDEO CONTROLLER

RA[14:12]
ROM ADDRESS LINE 14-12. This signal is output to the add

of BIOS ROM as a final address input.

BD[7:0)
DATA LINE 7-0. Data bit 7-0 of BIOS high byte data in 16 bit

or single byte data in 8 bit BIOS mode. Also, data bit of DAC
dipswitch.

8.10.1.3 Clock Interface
VCLK

VIDEQ CLOCK. This is the master input dot clock for VGA cl
MCLK

MEMORY CLOCK. This is a direct input clock used for DRAI

timing

CSELOD-2

CLOCK SELECT 0-2. Clock select line 0-2.

8.10.1.4 CRT And RAMDAC Interface
HSYNC

HORIZONTAL SYNC. Horizontal synchronization puise to th

monitor. The polarity of the pulse is determined by bit 6 of tt
ous Output Register. (Bit 7 of 3DF index 12)
VSYNC

VERTICAL SYNC. Vertical synchronization pulse to dispiay |

polarity of the pulse is determined by bit 7 of the Miscellane
Register. (Bit 6 of 3DF index 12.)

-BLANK

BLANK. Active low output signal to RAMDAC to blank the p

the display monitor.
P[7:0]

PIXEL DATA. Pixel data bit 7-0, output to external color pale
mapping.

VGA VIDEO CONTROLLER 8-79

-DACR

RAMDAC READ. An active low 1/O read signal generated for reading
external color palette registers.

-DACW
RAMDAC WRITE. An active low /O write signal generated for writing

external color palette registers.
PCLK
PIXEL CLOCK. Pixel clock output to DAC to latch the pixel data P7-P0. it
is derived from the current dot clock rate of operating mode.

1.10.1.5 Video Memory Interface
MA[8:0]

MEMORY ADDRESS. Memory address line 8-0 for memory maps 0. 1
(bank A).

MB([8:0]
MEMORY ADDRESS. Memory address line 8-0 for memory maps 2. 3

(bank B).

MD[15:0]
MEMORY DATA. Memory data line 15-0 With 2 DRAMS bits 0-3 are for
maps 0,1 and bits 4-7 are for maps 2,.3. With 4 DRAMS bits 0-3, 8-11 are
for maps 0.1 and bits 4-7, 12-15 are for maps 2.3.

-RAS
ROW ADDRESS STROBE. Active low output signal to all video memory
maps.

-CAS
COLUMN ADDRESS STROBE. Active low output signal to all video
memory maps.

-WEO01
WRITE ENABLE. Active low write enable pulse to memory map 0 and 1
-WE23

WRITE ENABLE. Active low write enable pulse to memory map 2 and 3.

8-80

VGA VIDEO CONTROLLER

8.10.1.6 Miscellaneous
ENVGA
ENABLE VGA. This active high input signal enables 1/0 and video
memory access. Valid only for motherboard implementations. For adapter
card implementations, pull high or low. See section on adapter card/
motherboard configuration.
VSETUP
VGA SETUP. An active low input signal puts VGA in setup mode. During

setup mode, only internal port 102 can be accessed. A writing logic 110
port 102 awaken the OTI-067 after power up. Valid only for motherboard
implementations. For adapter card implementations, pull high or low. See
section on adapter card/motherboard configuration.
-RDSW

READ DIP SWITCH. An active low read puise enables to read the DIP
switch setting.

SWSENSE
SWITCH SENSE. An input signal used to auto detect the monitor type.

8.10.1.7 Power and Ground
vCC
Power: +5V

GND
Ground

VGA VIDEO CONTROLLER 8-81

.10.2 OTI-066 Signal Description
RED, BLUE, GREEN
These are the analog outputs of the 6-bit DACs. The RGB (red, blue,
green) voltage will be developed at this output pin with the current

flowing from this point into the terminating resistors. Each DAC is

composed of 63 current sources. The output of these current sources is
summed together based on the 6-bit binary value from the static RAM
{able.

IREF
The reference current forced out of this pin determines the current

sourced by each of the 63 current sources in each of the 6-bit DACs.

Each current source produces 1/30 of IREF when activated by the 6-bit
digital code.

PO-P7
These are high-speed Pixel Address inputs. The address is latched and
masked by the Pixe Register. It is used for addressing the Color Palette

RAM and generating the final color value.
PCLK
This is the high-speed Pixed Clock signal. The rising edge samples and
latches the Pixed Address and Blanking inputs. It controls progress of

these values through the three-stage pipeline of the Color Palette and
through the DACs to outputs.
VSS
Power supply ground.

-RD"
Active low Read bus control signal. Enables Data 1/O lines D0-D7.-RD and

-WR shouid not be active at the same time.
-BLANK
Active iow signal forces zero voltage at the DAC outputs. When -BLANK is

asserted,the Color Palette can still be updated through DO-D7.
D0-D7

Bi-directional data lines to read or write information for the OTI-066
internal registers. During the write cycle, the rising edge of -WR latches

the data into the selected register. The rising edge of -RD determines the

8-82 VGA VIDEO CONTROLLER

end of the read cycle. When -RD and -WR go high, the Data I/O lines will
be in a tri-state mode.

-WR
Active low Write signa! controls the timing of the write operations on the

microprocessor interface inputs DO-D7. When asserted, the rising edge of
-WR will sample and latch data into internal registers. -RD and -WR
signals should not be asserted at the same time.

RS0, RS1
Register Select inputs. These two inputs are sampled during the faling

edges of the enabile signals (-RD or -WR) and select one of the three
internal registers.

vCcC

Positive power supply pin. It is normally connected to +5V and bypassed
with a 10uF tantalum capacitor and a 0.1uF chip capacitor.

8.10.3 OTI-069 Signal Description
FSO

Frequency Selcet input, TTL compatible (LSB)
FS1

Frequency Select input, TTL compatible (LSB)
FS2

Frequency Select input, TTL compatible (LSB)
FS3

Frequency Select input, TTL compatible (MSB)
STROBE

Negative edge clock for select input, TTL compatible
FREQO

Externally generated frequency input
FREQ1

Externally generated frequency input

VGA VIDEO CONTROLLER 8-83

FOUT

Clock output, TTL compatible
XTAL1
Crystal interface / External oscillator input
XTAL2

Crystal interface
vDD

5-Valt ¢ yital power pin

AVDD
5-Volt analog power pin

VSsS
Digital ground
AVSS
Analog ground

CPSEL
Phase comparator polarity select (pull up to VDD if left open)
ouT
Phase comparator output

VCO(IN)
voitage-conitrolled oscillator input

OP(OUT)
Op-amp output
OP(-)

Op-amp negative input

OP(+)

Op-amp positive input (AVDD referenced, it open)

9
POWER SUPPLY
This chapter describes the specifications of the DECpc 320sxLP/325sxLP
power supply. The power supply 1s a 115 Watt power supply.

9.1

115 Watt Power Supply Output Specifications
Table 9-1 hists the output specifications for the 115 Watt power supply.

Table 9-1. 115 Vvatt Power Supply Output Specitication
PARAMETER

QUTPUT VOLTAGE

LOAD RANGE

RIPPLE & NOISE

REQUIREMENT
MIN.
TYP.
MAX.

UNITS

VOLTS

+5V

+4 80

+5.00

+5.25

+12V

+1140

+1200

+12 60

-12V

-1140

-1200

-1260

-5V

-47%

-50C

-525

+5V

120

+12V

40m

472

-12V

-5v

+5V

+12V

100

-12V

-5V

HOLD-UP TIME

AMPS

150
100

-2

POWERSUPPLY

NOTE:

1. Noise Test: Use 20 MHz bandwidth frequency oscilloscs
2. Add 0.1uF/10uF capacitor at output connector terminals
Ripple & Noise measurements.

3. +12V output should withstand 5.0A surge current for 15
seconds during this period the +12V regulation toleranc
should be +7%,-6%.

A-4

BIOS INTERRUPT ROUTINES

A.2 BIOS Services
All calls to the BIOS are made through software interrupts (that is, by
means of assembly-language “INT x * instructions). Each 1/Q device is
provided with a software interrupt, that transfers execution to the BIOS

service routine. Input parameters to BIOS routines are normally passed in
CPU registers. Similarly, output parameters are generally returned from
these routines to the caller in CPU registers. To execute a BIOS call, load
the registers with input parameter. (When a BIOS service is capable of
running more than one function, functions are selected by placing the
proper tunction number in the AH register. Subfunctions are selected via

either the AL register or the BL register.) Then issue the interrupt given for

the call. For example, the following can be used to read a character from
the keyboard:

MOV AH.D
INT 16h

Upon return, AL contains the ASCH character and AH contains the
keyboard scan code.

Note: All registers except those used to return parameters to the

caller are saved and restored by the BIOS routines.

Table A-2 is a quick reference list of software interrupts for all device /O
and system status services. Tables A-3 through A-13 briefly define each
BIOS service and list each BIOS function and subfunction.

A-2

BIOS INTERRUPT ROUTINES

Table A-1. (Cont.) interrupt Functions and Types

INT

Function

Type

Vector

07h

Math coprocessor not present

Hardware

08h
08h

Double exception error
System timer (IRQ 0)

Hardware
Hardware

FFEA5h

09h

Keyboard (IRQ 1)

Hardware

FE987h

09n

Math coprocessor segment

Logical

overrun

0OAh

IRQ 2 cascade from second

Hardware

programmable interrupt

controller

0An

invalid task segment state

0Bh

Serial communications {COM2)

Logical

Hargware

OBh

Segment not present

(IRQ 3)
Logical

0Ch

Serial communications (COM1)

Hardware
(IRQ 4)

0Ch
0DF

Stack segment overflow
Parallel printer (LPT2)

Logical
Hardgware

0Dh

General protection fault

Logical

OEh
OEh

IRQ 6 diskette
Page fault (80386 only)

Hargware
Logical

OFh
10h

Paralie! printer (LPT1) IRQ7
Video

Hardware
Software

10h

Numeric coprocessor fault

Logical

11h

Equipment list

Software

FF84Dh

12h
13h
14h
15h
16h
17h
18h

Memory size
Fixed disk/diskette
Serial communication
System services
Keyboard
Parallel printer
Process boot failure

Software
Software
Software
Software
Software
Software
Software

FF841h
F7FE5Sh
FE7389h
FF858h
FEB2EN
FEFD2N
F79A%h

19h

Bootstrap loader

Software

FEGF2Nh

1Ah
1Bh

Time-of-day
Keyboard break

Software
Software

FFEGER
FFF53h

1Ch

User timer tick

User

FFF53n

1Dh

Video parameter table

BIOS Tahle

C7898h

(IRQ5)

FEFSTN

C17BDnh

BIOS INTERRUPT ROUTINES A-3

Table A-1. (Cont.) Interrupt Functions and Types

INT

Function

Type

Vector

1Eh

Diskette parameter table

BIOS Table

FEFC7h

1Fh
20hto

Video graphics characters
Reserved for DOS

User

C572Ah

40h

Diskette BIOS revector

Software

FECS59h

41h

Fixed disk parameter table

BIOS Table

004COh

42n

EGA detault video driver

BIOS Tabie

43h

Video graphics cnaracters

User

44n to

Reserved

3Fh

45nh

46h

Fixed disk parameter table

47hto

Reserved

BIOS Table

FE401h

49h
4Ah

User alarm

4Bh to

Reserved

User

58h

5Ah
5Bh to

Cluster adapter

Reserved

5Fh

60h to

Reserved for user program

66h

Interrupts

67h

LIM EMS driver

68h to

Reserved

6Fh
70h
71h

User

73h
74h
750
76h
77n
78hto 7Fh

Real-time clock (IRQ 8)
IRQ 2 redirect (IRQ 9)
Reserved (IRQ 10)
Reserved (IRQ11)
Reserved (IRQ 12)
80287 exception (IRQ 13)
Fixed disk (IRQ 14)
Reserved (IRQ 15)
Reserved

Hardware
Hardware
Hardware
Hardware
Hardware
Hardware
Hardware

80h to

Reserved for BASIC

BASIC

Fihto

Reserved for user program

User

FFh

interrupts

72h

FOh

FCCEDN
FD179h
FD182h
FD182h
FO25Ah
FD16AN
F7FCBh
FFF53h

A-4

BIOS INTERRUPT ROUTINES

A.2 BIOS Services

Ali calis to the BIOS are made through software interrupts (tr

means of assembly-language “INT x * instructions). Each 1/O
provided with a software interrupt, that transfers execution to

service routine. Input parameters tc BIOS routines are norme
CPU registers. Similarly, output parameters are generally ret

these routines to the caller in CPU registers. To execute a Bi

the registers with input parameter. (When a BIOS service is ¢

running more than one function, functions are selected by pl
proper function number in the AH register. Subtunctions are

either the AL register or the BL register.) Then issue the inter
the call. For exampie, the foliowing can be used to read a ct
the keyboard:

MOV AH,0
INT 16h

Upon return, AL contains the ASCII character and AH co
keyboard scan code.

Note: All registers except those used to return paramete!

caller are saved and restored by the BIOS routines.
Table A-2 1s a quick reference list of software interrupts for

and system status services. Tables A-3 through A-13 briefly
BIOS service and list each BIOS function and subfunction.

BIOS INTERRUPT ROUTINES

Table A-2. Software interrupts

Service

Software Interrupts

Print Screen

05hn

Video Display

10h

Equipment List

11h

Memory Size

12h

Diskette

13h

Fixed Disk

13h

Serial Communications

14 h

Mutti-Tasking Support

15h

Joystick

15h

Microsecond Delay

15h

Extended Memory

15h

Virtual Mode

15h

Mouse

15h

Keyboard

16h

Paraliel Printer

17h

Time - of - Day

1Ah

Table A-3. Print Screen Service
INT

Parameter

Function

05h

None

Print screen

A-5

A-6

BIOS INTERRUPT ROUTINES

Table A-4. Video Services

INT

Function

10h

00h

Set video mode

0th

Set text mode cursor size

02h

Set cursor position

03h
04h
05h

06h
07h
08h
0%h
OAh
0Bh
0Ch
0Dh
OEh
OFh

Read current cursor position
Read light pen position
Select active video page

Scroll active page up

Scroll active page down
Read character/attribute from scraen
Write character/attribute to screen
Write character only to screen
Set color palette
Write pixel
Read pixel
Write teletype to active page
Return video status

BIOS INTERRUPT ROUTINES A-7

Table A-4. (Cont.) Video Services
INT

Function

10h

Set palette/color registers:
Parameter

Subfunction

AL = 0Ch

Set single palette
Set overscan register
Set all palette registers and

AL = 01h

AL = 02h

overscan

AL =03h

Toggle mtensify/blinking bit

AL = 04h-06h

Reserved

AL = 07h

Read individual palette
register

AL = 08h

Read overscan register

AL = 09h

(border color)
Read all palette registers and
overscan register (border
color)

AL = 10h
AL = 11h

AL = 12h
AL = 13h

Set indvidual color register
Reserved
Set block of color registers
Select color paging mode (not
valid for mode 13h)

BL = 00h
BL = 01h
AL = 14h
AL = 15h

AL = 16h
AL = 17h
AL = 18h-19h

AL = 1Ah
AL = 1Bh

Select paging mode
Select page
Reserved
Read single DAC color register
Reserved
Read block of color registers
Reserved

Read color paging status

Sum color values to gray
shades

A-8

BIOS INTERRUPT ROUTINES

Table A-4. (Cont.) Video Services
INT

Function

10h

11h

Load character generator:

Parameter

Subfunction

AL = 00h

Load user text mo

AL =01h

Load ROM 8x14 te
Load ROM 8x8 do
mode font
Set block specifie!
only)

AL = 02h

AL =03h
AL = 04h
AL = 10h

Load 8x16 ROM te
Load user text mo

(after mode set)

AL =11h
= 12h
AL

= 14h
AL

Load ROM 8x14 1

(after mode set)
Load ROM 8x8 dc
mode font (after
Load 8x16 ROM t
(after mode set)

AL = 20h

Set user graphics

= 21h
AL

pointer at INT 1Fh
Set user graphics
at INT 43h

AL =22h

Use ROM 8x14 fo
graphics

= 23h
AL

Use ROM 8x8 dou
for graphics

= 24h
AL

Use ROM 8x16 fo
graphics

AL = 30h

Get font pointer ir

BIOS INTERRUPT ROUTINES A-9

Table A-4. (Cont.) Video Services

INT

Function

10h

12h

Alternate select:

Parameter

Subfunction

BL = 10h

Return configuration
information

BL = 20nh

Switch to alternate print
screen routine

BL = 30h

Select scan lines for text
modes

BL =31h

Enable/disable default palette
loading during set mode

BL = 32h
BL = 33h

Enable/disable video
Enable/disable summing to
gray shades

BL = 34h
BL = 35h
BL = 36h
13h

Enable/disable cursor scaling
Switch display
Video screen off/on

Write string:

Parameter

Subfunction

AL = 00h
AL =01h

Cursor not moved

AL = 02h

Cursor is moved
Cursor not moved (text modes
only)

AL = 03h

Cursor is moved (text modes
only)

A-10

BIOS INTERRUPT BOUTINES

Table A-4. (Cont.) Video Services
INT

Function

10h

14h-19h

Reserved

1Ah

Read/wnie display combination code:

Parameter
AL = 00h

Subfunction
Read display combination
code

AL =0th

Write display Combination
code

1Bh

Return functionality/state information

1Ch

Save/restore video state

1Dh-FFh

Reserved

Table A-5. Equipment List Service

INT

Parameter

Function

11h

None

Read equipment list

Table A-6. Memory Size Service

INT

Parameter

Function

12h

None

Read memory size

BIOS INTERRUPT ROUTINES A-11

Table A-7. Diskette Service

INT

Function

13h

00h
01h
02h

Reset diskette system
Read diskette status
Read diskette sectors

03h
04h

Write diskette sectors
Verity diskette sectors
Format diskette track

05h
06h-07h
08k
03h-14h
15h

Reserved
Read drive parameters
Reserved
Read drive type

16h

Detect media change

17h
18h
19h-FFh

Set giskette type
Set media type for format
Reserved

Table A-8. Fixed Disk Service
INT

Function

13h

Reset diskette(s) and fixed disk

01h
02h

Read fixed disk status
Read sectors

03h

04h

Write sectors
Verify sectors

05h
J8h
0%h
QAh

Format cylinder
Read drive parameters
Initialize drive parameters
Read long sectors

0Bh

Write long sectors

0Ch
ODh
10h
11h
14h
15h

Seek to cylinder
Alternate fixed disk reset
Test for drive ready
Recalibrate drive
Controller internal diagnostic
Read fixed disk type

16h-FFh

Reserved

A-12

BIOS INTERRUPT ROUTINES

Table A-9. Serial Communication Service

INT

Function

14h

00h

Initialize serial communication:

01h
02h
03h
04h to FFh

Send character
Receive character
Read serial port status
Reserved

Table A-10. System Services

INT

Function

15h

04h to 4Eh
4Fh
50h to 7Fh

Reserved
Keyboard intercept
Reserved
Device open

80h
81h
82h

83h
84h
85h
86h

87h
88h

89h
8Ah to 8Fh
90h

Device close
Program termination
Set event wait interval
Joystick support

System request key
Wait
Move block

Read extended memory size
Switch processor to protectec
Reserved
Device busy

91h

Interrupt complete

97h to BFh
CCh

Reserved
Return system configuration |
———

BIOS INTERRUPT ROUTINES

Table A-11. Keyboard Service

INT
16h

Function

00h

Read keyboard input

O1h

Return keyboard status

02h
03h
05h
06h to OFh

Return shift flag status
Set typematic rate and delay
Store key data
Reserved

10h

Read extended keyboard input

11h

Return extended keyboard status

12h

Return extended shift flag status

13h to FFh

Reserved

Table A-12. Parallel Printer Service
INT

Function

17h

00h

Print character

01h

Initialize printer

02h

Read printer status

03h to FFh

Reserved

Table A-13. Time-of-Day Service

INT

Function

1Ah

00h
01h
02h
03h
04h
05h
06h
07h

Read system timer time counter
Set system timer time counter
Read real time clock time
Set real time clock time
Read real time clock date
Set real time clock date
Set real time clock alarm
Reset real time clock alarm

A-13

APPENDIX B
PRODRIVE LPS 52/15AT
HARD DISK DRIVES
Thg LPC EDMNEAT hard dick drive features arn embedded AT dive

controller and uses AT commands 1o optimize system performance
Because the drive manages media defects and error re:covery internatly,
these operations are fully transparent to the user The LPS 52AT hard disk
drive provides 52 megabytes of formatted capacity on one disk, with two
read/write heads; while the LPS 105AT hard disk drive provides 105

megabytes on two disks, with four read/write heads

NOTE: As defined by Quantum, a megabyte (MB) is 1,000,000 bytes.
Key teatures of the LPS 52/105AT hard disk drive inciude

Formatted storage capacity of 52 or 105 megabytes

Low-profile, 1-inch height

Industry-standard 3 1/2 inch form factor

Data-transfer rate of up to 4.0 megabytes/second, using programmed VO

Average seek time of 17 milliseconds

Proprietary 64K, look-ahead, programmable DisCache

48-bit, computer-generated, cyclic Error Correcting Code (ECC),

\ 4

with 11-bit burst correction

Automatic retry on read errors

Transparent media-defect mapping

High-performance, in-line defective sector skipping

B-2

PRODRIVE LPS 52/15AT HARD DISK DRIVES

Reassignment of defective sectors discovered in the field,
out reformatting

Patented AIRLOCK automatic shipping lock and dedicated
ing zone

1:1 interleave on read/write operations

Ability to daisy-chain two drives on the interface

B.1 Physical Specifications
Table B-1. Environmental Limits

Attribute
Ambient Temperature, Non-operating

Specifications
-40°F 10 140°F {-40°C to 6
42°F/hr (20°C/hr) gradient

Ambient Temperature. Operating

39°F to 122°F (4°C to 50
23°F/nr (10+C/hr) gradient

Ambient Relative Humidity, Non-operating

5% to 95%. without conde
Maximum wet bulb. 115

Ambient Relative Humidity. Operating

8% 10 85%, without conds

Maximum wet buib

70°F

Altitude (relative to sea level), Non-operating

-200 (-60M) to 40.000 1t (

Altitude (relative to sea level), Operating

-200 (-60M) to 10.000 tt {

FRODRIVE LPS 52/15AT HARD DISK DRIVES

Table B-2. Mechanical Dimensions

Attribute

Specifications

Height

1.0in (25.4 mm)

Width

4.0in (101.6 mm)

Depth

5751n (146.2 mm)

Weight

1.05 Ib (0.48 kg)

NOTE: All dimensions are exclusive of the faceplate.

Table B-3. Heat Dissipation

Attribute

Specifications

Average Power Consumption (ready, on frack idle)

5.5 Watts

Typica! Power Consumptior: (random read/write)

6 5 Watts

NOTE: Quantum defines random read/write as:
40% random seeks

40% read/Write (1 write pius 10 reads)
20% ready (idie)

B-3

B-4

PRODRIVE LPS 52/15AT MARD DISK DRIVES

Table B-4. Vibration and Shock Specifications

Attribute

Specifications
Operating
Nonoperating

Vibration:

5-500 Hz sine wave (peak-to-peak) 1.0G

2.00G

1 oct/min sine sweep

Shock:
1/2 sine wave of 11 msec duration

{10 hits maximum)

6 G (no soft errors)

60 G

10G (1 soft error/block)

NOTE: When packed in its shipping container, the LPS 52/105AT can
withstand a drop from 36 inches, onto a concrete surface-on

any of its surfaces, six edges, and three corners. The drive
can withstand vibration applied to the container of 0.5 G,
5-100 Hz (0-to-peak) and 1.5 G, 100-500 Hz (0-to-peak).

B.2 Performance Specifications
Table B-5. Physical Capacity

Attribute

Physical capacity (MB)

Number of 512-byte sectors

Specifications
LPS 52AT

LPS 105AT

105

102,171

205.561

NOTE: The LPS 52/105AT receives a low-level format at the factory,
which creates the actual tracks and sectors on the drive.
Formatting done at the user level, for operation with DOS,
UNIX, or other operating systems, will result in less capacity
than the physical capacity shown,

PRODRIVE LPS 52/15AT HARD DISK DRIVES

Table B-6. Logical Addressing Format

Attribute

Specifications
52AT

Logical Cylinders

105AT

751

755

Logical Heads

Logical Sectors/Track

102,136

205.360

Total Number Logical Sectors

NOTE: A low-level format is not required.

Table B-7. Data-Transfer Rates

Attribute

Specifications

Bufter 1o AT Bus

Up to 4 0 MB/sec, using programmed |/O

Disk to Buffer

Up to 1.75 MB/sec in burst

B-5

B-6

PRODRIVE LP5 52/15AT HARD DISK DRIVES

Table B-8. Timing Specifications
DESCRIPTION

NOMINAL CONDITIONS

TYPICAL

WORST-CASE
CONDITIONS

MAXIMUM

Single-Track Seek (msec)

Average Seek (msec)
Third-Stroke Seek (msec)
Full-Stroke Seek (msec)

17
18
33

19
21
38

21
23
43

Average Rotational Latency (msec)
Sequential Head Switch (msec)
Power-Up Time (sec)

8.2
20
8

B.2
2.0
10

82
20
10

NOTE:

Defined as the time required for the actuator to seek and settie on
track, seek time is measured by averaging 1000 seeks of the
indicated length. Seek time includes head settling time, but not
command overhead or rotational-latency delays.
Average seek time is the average of 1000 random seeks. Wheri a

seek error occurs, recovery for that seek may take up to seven
seconds.

Sequential head-switch time is the time required for the head to
move from the end of the last sector on a track, to the beginning of
the next sequential sector-which is on the next track in the same
cylinder. Track skewing determines the sequential head-switch time.
See Appendix A.

Power-up time is the time elapsed between the supply voltages
reaching operating range and the drive being ready to accept all
commands.

An ambient temperature of 25+C, nominal supply voltages, and no
applied shock or vibration constitute nominal conditions. Worst-case
extremes of temperature and supply voltages constitute worst-case
conditions.

PRODRIVE LPS 82/15AT HARD DISK DRIVES

B-7

Table B-9. Error Rates

Attribute

Specifications

Random Data Errors

1 per 10 bits read (maximum)

Defect Data Errors

1 per 10" bits read (maximum)

Unrecoverable Data Errors

1 per 10" bits read (maximum)

Seek Errors

1 per 108 seeks (maximum)

NOTE: Error rates are defined as:
Data Error: A data error occurs whenever the drive fails to read or
write a sector of data correctly. Data error rates are average rates
measured over at least 1000 different sectors, under any
specified operating conditions, except applied shock or

vibration.

Random Error: An error that does not exhibit a repeating error
pattern-that is, the error does not occur successively within a
specified number of retry reads. The default is eight. Retries
terminate once the drive reads the data correctly. The drive does
not automatically reallocate the sectors, because the error is

probably not due to media defects. See Appendix B for
information about defect handing.

Defect Errors: Errors that exhibit a repeating error pattern-that is, the
error occurs successively within eight retry reads, before the

drive can read the sector successfully. Such errors are likely due
to media defects.
Unrecoverable Errors: Errors with a final retry error pattern that is
uncorrectable using ECC. The drive terminates retry reads either
when a repeating error pattern occurs or after eight unsuccessful retries.

Seek Error: A seek error occurs when the actuator fails to reach or
remain on the requested cylinder, or the drive requires the
execution of the full recalibration routine to locate the requested
cylinder. A full recalibration takes approximately seven seconds.

B-8

PRODRIVE LPS 52/15AT HARD DISK DRIVES

B.3 Functional Specifications
Table B-10. LPS 52/105AT Functional Specific:

Attribute

Specifications
LPS 52AT

LP!

Nominal Rotational Speed (RPM)

3662102%

3.6

Maximum Recording Density (bpt)

29,307

29.

Maximum Flux Density (fci)

19,538

19,

Track Density (tpi)

1,330

1.3

Data Tracks
Data Sectors/Track
Zone 0
Zone 1
Zone 2
Data Tracks/Cylinder
Zone 0
Zone 1
Zone 2
Data Cylinders (total)

2.438

4.8

49
42

2
2

4
4

2
1,219

4
1,2

Zone 0
Zone 1
Zone 2
Snare Sectors/Cylinder
Read/Write Heads
Disks 1

454
382
383
1

45¢
38
38!
1

Encoding Scheme

RLL 2,7

PRODRIVE LPS 52/15AT HARD DISK DRIVES

B-9

3.4 Power Requirements
Table B-11. DC Power Requirements

REQUIREMENT
Maximum Tolerance

DC VOLTAGES
+12V
+5V
+10%
5%

Current:
Ready (on track idie)

0.32A

Random Read/Write

0.41A

0.31A

Maximum (at power on)

1.0A (£10%)

0.31A

100 mv

50 mv

Ripple and Noise

{(maximum peak-to peak)

NOTE: random read/write are defined as:
40% random seeks
40% read/write (1 write plus 10 reads)

20% ready (idle)

3.5 Jumper Setting
This section describes hardware options that should be set prior o

installation. The configuration of three jumpers controls the drive's mode

of operation:

DS - Drive Select

SP-Slave Present

¢+

DM - Drive Mode

B-10

PRODRIVE LPS 52/15AT HARD DISK DRIVES

B.5.1 Drive Select (DS) Jumper
You can daisy-chain two drives on the AT-bus interface. When daisychaining two drives, use their Drive Select (DS) jumpers to configure one
drive as the Master and the sther as the Slave. To configure a drive as the
Master (Drive 0), instail a jurmper at the DS pins. Quantum ships ProDrive
52AT and 105AT hard disk drives from the factory with the DS jumper
installed - that is, configured as Drive 0. To configure a drive as the Slave
(Drive 1), remove the DS jumper.

NOTE: The order in which drives are connected in a daisy chain has '
no significance.

B.5.2 Slave Present (SP) Jumper
In combination with the current DS jumper setting. the Slave Present (SP)
jumper implements one of two possibie configurations:

« When the drive is configured as a Master-that is, with the DS

jumper installed-the SP jumper indicates to the drive that a Slave

‘

drive is present. The SP jumper should be instailed on the Master
drive only if the Slave drive does not use the Drive Active/Slave

Present (DASP) signal to indicate its presence.
»

When the drive is configured as a Siave-that is, withoui the DS
jumper installed-the SP juinper enables the seif-seekiesi. When1

power is applied io the dGrive with the seif-seek iesi enabled, the

drive execuies seeks in bufierily paiiern.
_

_During the sali-seek test, the LED remains on while the test

proceeds without error. If the test encounters a seek error, the

test terminates and the LED flashes continuously until the SP
jumper is removed.

{

PRODRIVE LPS 52/15AT HARD DISK DRIVES

B-11

B.5.3 Drive Mode (DM) Jumper
When the Drive Mode (DM) jumper is installed, the drive is in the ProDrive
40/80AT compatible mbde and can communicate with a ProDrive 40/80AT
hard disk drive. in this mode, the drive does not use the PDIAG signal to

control Master/Slave communications. The configuration of the DS and
SP jumpers determines whether the drive is the Master or the Slave.

APPENDIX C
FLEXIBLE DISK DRIVE (FDD)
DECpc 320sxLP/325sxLP computer supports up to four disk drives This
2

TEAC FD-55GFR. 5.25" flexible disk drive'which are instalied in DECpc
320sxLP/325sxLP

C-1 SONY 3.5" 2MB Micro Floppy Disk Drive
C-1-1 Configuration
The drive consists of Read/Write heads. a head positioning mechanism.a

spindle motor circuit board, a Read/Write interface and 10gic contro!
circult board, and a 1" high front panel

C-1-2 Physical Specifications
Table C-1. Mechanical Dimensicns

Attribute

Specifications

Height

254 mm {1.0inch)

Width

1016 mm (4.0 inches)

Depth

9 1inches)
150.0 mm (5

Weight

425

(0.94 pound)

C-2

FLEXIBLE DISK DRIVE (FDD)

Table C-2. Environmental Limits

Attribute

Specifications

Operating temperature

5°C to 50°C ambient (40"
{no condensation)

Non-Operating temperature

-40°C to 60°C (-40°F to 1
(no condensation)

Opvurating relative hurnidity

8% to 80%, with a wet b
29°C and no condensati

Non-Operating relative

5% to 95%. with a wet bt

humidity

29°C and no condensatx

Table C-3. Vibration and Shock Specific:

Attribute

Specificat
Operating
|

Vibration

10Hz to 500 Hz

0.5G max

continuous vibration

Shock
1/2 sine wave for 11 msec

5.0G max

FLEXIBLE DISK DRIVE (FDD)

C-3

Table C-4. Power Consumption

Attribute

Specifications

Stand-by

0.1W max

Operation (Read/Write mode)

1.1W typ.

NOTE: Stand-by is specified under the conditions
1. The drive is NOT selected.

2. The DIRECTION and the HEAD SELECT lines are low.
The other lines are false (high).

Table C-5. Supply Voltage

Voltage

Max. Ripple

+50V+10%

0.1Vpp

Current
20 mA max. (Standby)
220 mA typ.

(Read/Write)
680 mA max (Motor Stans)

890 mA max. (Step during motor rotation)

C-1-3 Performance Specifications
Table C-6. Recording Capability

Attvibute

Specifications
2MB mode

1MB mode

Recording Capacity
(unformatted, MFM)

2Mbytes/disk
1Mbytes/disk

1Mbytes/suriace
0.5Mbytes/surface

Recording density

17.434 BPI

8.717 BPI

(Side 1, Track 79)

C-4

FLEXIBLE DISK DRIVE (FDD)

Table C-7. Data Transfer Rates
Burst transfer rate

500Kbits/sec for MFM (2MB n
250KDbits/sec for MFM (1MB

Table C-8. Timing Specifications
Description

Timing Specifications

Track to Track slew Rate

3 msec

Head Setting Time

15 msec max.

Average Access Time

94 msec

Motor Start Time

500 msec max.

Rotational Latency

100 msec ave.

Rotation Speed

300 rpm

The continuous speed variation is within £1.5%
The instantaneous speed variafion is within +1.5%

Table C-9. Structure

Atftribute

Specifications

Track Density

135 TPI

Number of Cylinders

Number of Tracks

160

R/W Heads

FLEXIBLE DISK DRIVE (FDD)

C-&

Table C-10. Reliability

Attribute

Specifications

Mean Time Between Failure (MTBF)

30,000 POH

Mean Time To Repair (MTTR)

30 minutes

Preventive Maintenance (PM)

Not Reguired

Component life

5 years or 15,000 POH

Error Rate:
Soft Read Error

1 per 10° bits read

2. Hard Read Error

1 per 10'? bits read

3. Seek Error

1 per 10° seeks

C-2 TEAC-55GFR-159 Mini Flexible Disk Drive
C-2-1 General
The FDD 1s equipped with an input signat for switching high/mormal

densities. It can read and write the data of 5.25", 96tp:. single/double
sided flexible disks, and it can also read the data of conventional 5.25",
48tp1. single/double sided disks

For the normal density mode, two disk rotational speeds are offered for

selection using internal switching strap. One is 300rpm which 1s currently
used in 5.25" FDDs and the other is 360rpm which is the same speed as
in hugh density mode.

C-6

FLEXIBLE DISK DRIVE (FDD)

C-2-2 Physical Specifications
Table C-11. Mechanical Dimensions

Attribute

Specifications

Height

41.3

mm (1.€3 in), Nom.

Width

146

mm (5.75 in), Nom.

Depth

203

mm (7.99 in), Nom.

Weight

1.00

kg (2.20 Ibs), Nom.

1.10

kg (2.43 Ibs), Max.

Table C-12. Environmental iimits

Attribute

Specifications

Operating Temperature

4°C to 46°C ambient (40°F to 115°F)

Non Operating - Storage

-22°C to 60°C (-8°F to 140°F)

Transportation
Operating relative humidity

-40°C to 65°C (-40°F to 149°F)
20% to 80% ( no condensation) with max
wet bulb temperature of 29°C.

Non-operating Storage

10% to 90 ( no condensation) with max

wet bulb temperature of 40°C.

Non-operating
Transportation

5% to 95% ( no condensation) with max.
wet bulb temperature of 45°C.

FLEXIBLE DISK DRIVE (FDD)

Table C-13. Vibration and Shock Specifications

AttributeSpecifications

Operating

Transportation

Vibration:

less than 55Hz

0.5G max.

55 - 500Hz

0.25G max.

less than 100Hz

2G max.

Shock:

less than 11 msec
Altitude:

5.0G max.

50G max.

less than 5,000m

less than 12,000m

(16,500 feet)

(40.000 feet)

Table C-14. Power Consumption

Attribute

Specifications

Waiting

1.0W typ.

Operating

4.0W typ.

C-7

C-8

FLEXIBLE DISK DRIVE (FDD)

Table C-15. Supply Voltage

Voltage

Max. Ripple

Current

DC + 12V

200mVpp

operating

tolerence
RW £ 5%
others £ 10%

220 mA typ. Read/Write
540 mA max. average
1.0 A max. 400msec, max.
at spindie motor start

waiting

10 mA typ. Spindie motor

off

20 mA max. spindie motor

off

DC + 5V

100mVpp

operating

tolerence £ 5%

280 mA typ. Read/Write
350 mA max. average
430 mA Peak

waiting

180 mA typ
230 mA max

‘

FLEXIBLE DISK DRIVE (FDD)

C-9

C-2-3 Performance Specifications
Table C-16. High Density Mode Data Capacity
Recording method

MFM

Data transfer rate (K bits/sec)

250

500

Tracks/disk

154 (160)

Innermost track bit density (bpi)

4823 (4935)

9646 (9870)

Innermost track flux density (frpi)

9646 (9870)

(Kbytes/track)

5.208

10.416

(Kbytes/disk)

802.0(833.3)

1604

Formatted 26 . (Kbytes/sector)

0.128

0.256

sectors/track (Kbytesftrack)

3.328

1604.1 (1666.6)

(Kbytes/disk)

512.£(532.5)

1025.0(1065.0)

(Kbytes/sector)

0.256

0.512

3.840

7.680

(Kbytes/disk)

5914(614.4)

1182.7 (1228.8)

(Kbytes/sector)

0512

1.024

4.096

8.192

630.8 (655.4)

1261.6(1310.7)

Data capacity
Unformatted

Formatted 15

sectorsftrack (Kbytesftrack)

Formatted 8

sectors/track (Kbytes/track)

(Kbytes/disk)
NOTE:

Up to 80 cylinders are available for the FDD. The table in the
blackets are for 80 cylinder’s operation (160 tracks).

C-10

FLEXIBLE DISK DRIVE (FDD)

Tabie C-17. Normal Density Mode Data Capacity
Recording method

MFM

Dual speed (300rpm)

125

Single speed (360rpm)

250

150

300

Tracks/cisk

160

Innermost track bit density (bpi)

2961

5922

Innermost track flux density (frpi)

5922

(Kbytes/track)

3125

- E2n

(Kbytes/disk)

500 .

vs)

(Kbyies/secior)

0128

0.256

Data transfer rate (Kbits/sec)

Data capacity
Unformatted

- Formaited 16_

_ -

sectorsitrack_(Kbytesfirack)

Formatted 9

2.048

4.096

{Kbyies/disk)

32768

655.36

(Kbytes/sector)

0.256

0512

2.304

4.608

368.64

737.28

sectors/track (Kbytesftrack)
(Kbytes/disk)

FLEXIBLE DISK DRIVE (FDD)

C-11

Table C-18. Disk Rotation Mechanism
Attribute

Specifications

Spindle motor

Direct DC brushless motor

spindle motor speed

Dual speed

360rpm (high density) /300rpm
(normal density)

Single speed

360rpm (high and normal
densities)

Motor servo method

Frequency servo by AC
tachometer and ceramic oscillator

Start Time,

360rpm

less than 500 msec

300rpm

less than 400 msec

Average latency,

360rpm

83.3 msec

300rpm

100 msec

Speed change time (360rpm7* 300rpm) less than 400msec (only for dual
speed mode)

C-12

FLEXIBLE DISK DRIVE (FDD)

Table C-19. Track Construction

Attribute

specifications

Track Density

96 TPI

Number of Cylinders
high density mode

normal density mode

Number of Tracks
high density mode

154

normal density mode

160

Magnetic head (Read/Write)

2 sets.

Table C-20. Reliability

Attribute

Specifications

Mean Time Between Failure (MTBF)

20,000 POH

Mean Time To Repair (MTTR)

30 minutes

Preventive Maintenance (PM)

Not Required

Component life

5years

Error Rate:

1. Soft Read Error

1 per 10° bits

2. Hard Read Error

1 per 102 bits

3. Seek Error

1 per 108 seeks

Safety standard

Complying with UL

INDEX

A
Abbreviation

Direction keys

1-3

1-1

About this manual
Auto Voltage Select

3-7

Disk drive coniroller

Disk drives bays

2-2

Auxihary AC output connector

2-2

2-1

Diskette dnive activity indicator

Diskette eject button
Diskette insertion

B
Basic operations

3-8

Battery replacing

6-13

Diskette types

Display setting

4-9

extended memory

4-8

4-4

fixed disks
memory

4-8

keyboard

4-10

3-10
3-10

4-9

Drive specification

4-4

display

3-9

standard-capacity

Configuration
diskettes

3-9

high-capacity

BIOS

3-6

4-6

E
EMS (Expanded Memory Specification)
5-9

Enable EMS

4.18

error messages C-1

setup

4-1

4-20, 8-1

Bus Clock

Fixed disk activity indicator
Front panel

Function keys

Chassis lock

Convention

notes

G
3-1

1-2

CPU reset button

6-5, 6-6

Getting started

|-2

1-2

warnings

3-7

2-2

Configuration Setting
cautions

3-4

3-6

Hardware installation

3-2

High resolution driver

5-7

INDEX

Installation overview
Installing

6-1

Power indicator

3.5" diskette drive
3.5" fixed disk

6-17

6-19

5.25" diskette drive
adapter card

Power cord requirements

6-15

Power on password

4-13

Power on/off button

3-6

Power-on/Power-off

3-8

6-11

math coprocessor

6-7

optional hardware

6-1

Integrated Drive Electronics (IDE)

J
Jumper

3-2

3-4

2-2

Resetting the computer

3-10

ROM base setup 4-8

6-5.6-6

Setting CPU speed
Setup screen 4-5

4-11

SIMM

Keyboard

install

6-9

direction keys

3-7

numeric keys

3-7

Site consideration

function keys

3-7

Special function keys

special function keys

typewriter keys
Key
evboard lavout

remove

3-7

3-7
3-8

(8o 8- 2084

Keyboard password uiility

S$-11

6-9
3-1

1.2MB diskette drive

8-6

1.44MB diskette drive

8-3

environment

8-2

fixed disk dnve

humidity

Math coprocessor

2-3

Memory
configuration

6-10

upgrade path

6-11

Modem

2-3

Motherboard layout

N
Numeric keys
Numiock

4-9

O
Options

2-3

3-7

6-4

3-7

Specifications

8-7

8-2

keyboard and mouse connector

parallel /O printer port
peripheral interface

8-2

power requirements

8-2

power supply

processor

8-2

§-1

RS-232C serial port
dimensions

8-1

systern unit

8-]

weight

8-3

8-2

8-1

Standard expansion slot
Standard features

2-1

System worksheet

9-1

2-2

INDEX

042, 7-1
30386sx, 3-3
2C712. 6-1
2254, 5-44

1259, 5-43
1237, 5-32

C
Central Processing Unit (CPU), 4-3
Conventions, 1-3

Counter/Timer. 5-44
CPU
modes of operation. 4-3

12C320. 5-1

signal, 4-3

20331, 5-32

architecture. 4-2

CRT and RamDAC Interface. 8-78

CRT Controller Register. 8-59

\bout this manual. 1-1
\bbreviations. -3

CRT Controller, 8-3

\ddress Generation, 5-38

\nalog Output. 8-9

Data Buffer. 5-3. 5-17

\utomatic interleave VS metnory map,

5-11

Digital to Analog Converter (DAC). 8-6
Diskette Service, A-1]

DMA controller registers, 5-36

DMA. 5-32, 3-5

jaud Rate Generation. 6-13

DRAM
subsystem. 5-6

$asic Input/Output System (BIOS), A-}

memory map. 5-6

3IOS Service

mapping. 5-8

software interrupts, A-5

Timing Parameters, 5-12

print screen, A-5
video. A-6

memory size, A-10

equipment list, A-10
disk. A-1]

refresh, 5-13

DRAM. 3.5
Drive Mode (DM). B-11

fixed disk, A-11

serial communication. A-12

Embedded Memory System (EMS). 5-16

systemm, A-12

keyboard. A-13

parallel printer, A-13
time of day. A-13

INDEX 3

INDEX

Input Buffer Full (IBF), 7-2

F
First-In-First-Out (FIFO), 8-5
Fixed Disk Service, A-11
Floppy Disk Controller (FDC), 6-22
Floppy Ni<k Drive (FDD)
3.5:r.h, C-1
5.25 inch, C-§

Integrated Drive Electronics (IDE), 6-17,
6-1
Imerrupt Controller Register, 5-43

Interrupt Controller, 5-41
Interrupt Levels, 544

Interrupt
vector table, A-1

reliability, C-5, C-12

type, A-l

performance, C-3, C-9
power, C-3, C-7

data transfer, C-4, C-9, C-10

Functional
DMA, 5-32

function, A-1

ISA Bus Controller, 5-32

ISA Bus, 5-5

counter/timer, 5-44

RTC, 5-47

Keyboard Commands, 7-8

DRAM. 5-6

Keyboard Service, A-13

Interrupt, 5-41

Keyboard/Mouse Controller, 7-1

CPU, 4-3
ROM. 3-5
FDD. C-1

BIOS. A-1

L
LPT, 6-15

power supply, 9-1
DAC. 8-6
IDE, 6-17

M
Memory Management Unit. 4-3
Memory Size Service, A-10

Middle Address Bit Latches, 5-36

Graphic Controller. 8-5

H
HALT/SHUTDOWN detection,
5-3, 5-17

Hard Disk Drive (HDD)
performance, B-4

data transfer rate, B-5
error rate, B-7

power. B-9

Modem Control Register, 6-9

Mouse Commands, 7-9

(0]
OTI1-067 VGA Graphic controller,
g-1

OTI-066 Video DAC, 8-1
OTI1-069 Video Pixel Clock
Generator, 8-1

Output Buffer Full (OBF). 7-2

Hard Disk Register, 6-18

P
1

Page mode and interleaving, 5-9

VO control Registers. 5-16

Page registers, 5-37

/O Ports. 3-5

Paralle! Printer Service, A-13

INDEX &9

Parallel Printer Port, 6-14

Pixel

clock generator, 8-18
mask register, 8-11

Power Supply, 9-1

System Controller, 5-5

T
Time of Data Register, 5-48

Time of Day Service, A-13

Power-On-Self-Test (POST), 3-5
Printer Screen Service, A-5

Transmit Buffer (TB), 6-5

Real Time Clock (RTC), 5-47

Universal Asynchronous Receive/
Transmit (UART), 6-3

Receiver Buffer (RB), 6-4

Refresh, 5-13

Universal Peripheral Controller (UPC),
6-1