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Document:	Firefox Workstation Q-Bus Adapter Module Functional Specification
Order Number:	MISC-68363C15
Revision:	0
Pages:	13
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OCR Text

Firefox Workstation Q-Bus Adapter Module
Functional Specification
Revision 3.0

Eugene Yu (DECWSE: :YU)
Michael Nielsen (DECWSE::NIELSEN

Workstation Systems Engineering
Digital Equipment Corporation
100 Hamilton Avenue
Palo Alto, CA 94301

415-853-6779

December 28, 1987

RESTRICTED DISTRIBUTION

Copyright 1986, 1987 by Digital Equipment Corporation
The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for
any errors that may occur in this document. This specification does not describe any program or product
currently available from Digital Equipment Cmporation. Nor does Digital Equipment Corporation commit
to implement this specification in any product or program. Digital Equipment Corporation makes no commitment that this document accurately describes any product it might ever make.

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Table of Contents

11. Firefox Q-Bus Adapter Module

11.1. Functionality ....... ... .. .. ........ .. ..... .. ....... .......... .. ... .. ... .. .. ... .. ... .. ..... .. ..... .. ... .. ... .. .. ... .. ... .... ....

11.1.1. M-Bus Interface ................................................................................................
11.1.2. Q-Bus Interface .................................................................................................
11.1.3. Diagnostic ROM ...............................................................................................
11.1.4. Status Indicators .... .... ... .. ..... .. .... .... .. .. ... ....... .. ... ....... .. ... .. ... .... ... ....... ..... .. ... .. .. ... .
11.1.5. External Connection . ... ...... . .. ... .. ... .. .. .. . .. ... .. .. .. . .. ... .. .. ... ..... .. .. ... ... .. .. ..... .. .......... .

1
1
1
2
2

11.2. Implementation . .... . .. .. ... .. .. . .. .. .. . .. .. . .. .. .. ... ....... ... .. ... .. .. ... .. ... .. .. ... .. ... .. .. ... .. .. . .. .. ... .. ... .. .. .. ..

11.2.1. M-Bus Interface ................................................................................................

11.2.1.1. Device Features . .. .. ... .. ... .... ... .. ... .. ..... .. ... .. .. ... .. ... .... ... .. ... .. ..... .. ... .. .. ..... ... .. .. ....
11.2. i .2. Busses ...... .......... .. .. ............ ... ............ ......... ... ........................ .............. ...........
11.2.1.3. Intemipts ........................................................................................................
11.2.1.4.Reset ............................................
...................................
11.2.1.5. FBIC Address Map ........................................................................................

2
3
3
3
4

11.2.2. Q-Bus Interface .................................................................................................

11.2.2.1. Device Features .............................................................................................
11.2.2.2. Busses ............................................................................................................
11.2.2.3. Intemipts ........................................................................................................
11.2.2.4. Reset . .. ... .. .. ... ..... .... ... .. ..... .. .......... .. .......... .............. ................. ... ....... ......... ....
11.2.2.5. CQBIC Address Map .....................................................................................

4
4
5
5
5

11.2.3. Oocks ...............................................................................................................
11.2.4. Status Indicators ................................................................................................
11.2.5. Bus Driver-Disable Circuit ...............................................................................

5
5
6

11.3. Programming .................................................................................................................

11.3.1. Locating Modules .............................................................................................
11.3.2. Addressing ........................................................................................................
11.3.3. Initialization ......................................................................................................
11.3.4. FQAM Module Restriction ...............................................................................
11.3.5. FQAM ROM .....................................................................................................
11.3.6. FQAM Access Restrictions ............ ..... .............................................................

6
6
7
7
7
7

iii

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Revision History

Date
11Dec87

Version
3.0

14 Aug 87

2.1

Design review update

01May87

2.0

Implementation description update

30 Jan 87

1.0

First external release

12 Jan 87

0.0

Preliminary draft

Content/Changes
Change status indicators from 6 to 5;
move BOM and timing to Engineering specification

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11. Firefox Q-B·us Adapter Module

1hls functional specification for the Firefox Q-bus adapter module describes the functionality of the
module, presents the specific implementation that achieves that function, and lists required software initialization and programming guidelines.
The Firefox Q-bus adapter module (FQAM), which is optional for a Firefox workstation, implements an
M-bus-to-Q-bus adapter in a single L-series-quad module. The module functions are the following:

•
•
•
•

M-bus interface
Q-bus interface
Diagnostic ROM
Status indicators

If an FQAM is present in a Firefox workstation, it must be in M-bus slot 0. There can be no more than one
FQAM per workstation.

11.1. Functionality
In this section, the functionality of the FQAM is defined without specific reference to actual implementation.
11.1.1. M-Bus Interface

The FQAM implements an M-bus interface that conforms to the Firefox M-Bus Specification. In addition to
satisfying the M-bus interface requirements, the M-bus interface supports the following:
•

Slave access to the control and status registers of the Q-bus interface

•

Slave access to the diagnostic ROM and status indicators

•

Master access to the M-bus for Q-bus interface DMA

•

Generation and acknowledgement of interrupts for the Q-bus interface

The Q-bus 4-Mbyte memory space and the adapter diagnostic ROM reside in the 32-Mbyte I/0-space
region associated with the M-bus slot of the FQAM module. The Q-bus interface control and status registers reside at a fixed addresses in I/0 space.
11.1.2. Q-Bus Interface

The FQAM implements a Q-bus interface that conforms to the DEC STD 160 Q22-Bus Specification in the
following ways:

•

The Q-bus interface supports only the arbiter role on the Q-bus.

•

The Q-bus interface supports a scatter/gather map for the 4-Mbyte Q-bus memory space into
the first 512 Mbytes of M-bus memory space.

•

The Q-bus interface supports forwarding of Q-bus interrupts onto the M-bus and M-bus
interrupt-acknowledge cycles onto the Q-bus.

11.1.3. Diagnostic ROM

The FQAM implements 256 Kbytes of socketed ROM for use by diagnostics. The ROM is accessible to
software via I/0-space references.

l l. l.4. Firefox Q-Bus Adapter Module

December 28, 1987

Firefox System Specification 1

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11.1.4. Status Indicators

The FQAM implements status indicators that convey five bits of information via red LEDs. The state of
the status indicators is cleared at system reset, resulting in all LEDs illuminated. The state of the status
indicators can be modified from software via I/0-space references.
11.1.5. External Connection

The FQAM connects to both the Q-bus and the M-bus through the AfB backplane connectors.

11.2. Implementation
The FQAM, which is implemented in a single L-series-quad module, implements an M-bus interface, a Qbus interface, diagnostic ROM, and status indicators. Figure 11-1 shows a block diagram of the FQAM.
Q-bus

Q-bus
interface

ROM

M-bus
interface

M-bus
Figure 11·1:

Firefox Q.Bus Adapter Module Block Diagram

11.2.1. M-Bus Interface

The M-bus interface consists of the Firefox Bus Interface Chip (FBIC), seven 74F245 M-bus transceivers,
one 74F244 M-bus driver, one 74AS760 open collector M-bus driver and one 74F244 status indicator
driver.
11.2.1.1. Device Features

The FBIC, currently under design by the WSE group in Palo Alto, is a multipwpose, bus interface and
cache controller that connects a CVAX pin-bus to the M-bus and supports an optional snoopy cache. The
chip functions as both a CVAX pin-bus master and CVAX pin-bus slave, depending on the needs of the
particular module on which it resides. On the FQAM, it is the default C-bus master and controls arbitration
of that bus. The FBIC also supports the M-bus write-back snoopy cache protocol defined in the Firefox
M-Bus Specification for an internal single-entry cache or for an optional external cache. The FQAM does
not use the external-cache option of the FBIC.
The chip contains two separately clocked, synchronous-state machines. The CVAX pin-bus state machine
monitors and initiates transactions on the CVAX pin-bus. The M-bus synchronous-state machine monitors
and initiates transactions on the system M-bus.
The FBIC implements all of the M-bus interface functions necessary to access FQAM control and status
registers and ROM from the M-bus. It allows the Q-bus interface to access memory via the M-bus, connects the C-bus interrupt request signals from the Q-bus interface to the M-bus, and forwards M-bus

2 Firefox System Specification

December 28, 1987

Firefox Q-Bus Adapter Module 11.2. l. l.

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interrupt acknowledge· cycles onto the C-bus. In addition, the FBIC controls the 32-bit diagnostic ROM
and a 5-bit status indicator.
A detailed description of the FBIC's operation and the format of its control and status registers can be
found in the Firefox FBIC Functional Specification.
11.2.1.2. Susses

The FBIC connects to both the M-bus and the C-bus and forwards transactions between the busses as
appropriate. Table 11-1 lists the FBIC response to C-bus transactions. The other possible CVAX pin-bus
transaction types--request D-stream read, external IPR read, interrupt acknowledge, request I-stream read,
demand D-stream read modify intent, and external IPR write--are never generated on the FQAM.
Table 11-1:

FBIC Response to CVAX Pin-Bus Transactions

CV AX Pin-bus Transaction
Demand D-stream read
Write

FBIC Response
Internal-cache read/M-bus read
Internal-cache write/M-bus write

Because the FBIC is the default C-bus master, it monitors DMR and asserts DMG as appropriate. The Cbus transactions listed in Table 11-2 can be initiated only after the bus has been acquired from the FBIC via
DMR/DMG. When the FBIC is not the C-bus master, it monitors the C-bus and services transactions that
reference it 01 the ::\1-bus.

Table 11-2 lists the FBIC's response to M-bus transactions. For I/0-space transactions, a reference is in
range if it is in the 32-Mbyte region assigned for the slot or if the FBIC address decoder matches. The
address decoder is used to access the Q-bus interface and must be programmed after every workstation
reset to match M-bus addresses 8000XXXX#l6 and 8008X:XXX#l6 (VAX addresses 2000X:XXX#l6 and
2008XXXX#16). For interrupt-acknowledge transactions, a C-bus interrupt-acknowledge transaction is initiated if the IRQ signal for the specified interrupt level is asserted on the C-bus.
Table 11-2:

FBIC Response to M-Bus Transactions

M-Bus Transaction
Memory read
Memory write
I/0 read
I/O write
Interrupt acknowledge

FBIC Response
Supply cache data if shared and dirty
Update cache if shared
C-bus I/0 read if in address range
C-bus I/0 write if in address range
C-bus interrupt acknowledge ifIRQ<n>

To avoid Q-bus/M-bus deadlocks, if a C-bus transaction in progress requires use of the M-bus at the same
time as an M-bus transaction requires use of the C-bus, the M-bus transaction will receive a retry termination status.
11.2.1.3. Interrupts

The FBIC monitors the C-bus IRQ signals, and if enabled via the FBIC IRQMASK CSR, asserts the
corresponding 11IRQ signals. When an M-bus interrupt-acknowledge transaction for an asserted IRQ signal occurs, the FBIC generates a C-bus interrupt-acknowledge transaction that. in tum, generates a Q-bus
interrupt-acknowledge transaction.
11.2.1.4. Reset

The FBIC is reset when the MRESET signal is asserted. The RESET function of the FBIC can be used as a
software controlled I/0 reset. That is, internal reset is the OR of MRESET and FBIC RESET.

11.2. l.5. Firefox Q-Bus Adapter Module

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Firefox System Specification 3

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11.2.1.5. FBIC Address Map

Table 11-3 lists the address offsets of the FBIC control and status registers. All registers are longword
aligned. For example, to read the MODTYPE CSR, a VAX issues a longword read to address
31FFFFFC#l6. Because the FQAM must be in backplane slot 0, the base address is always VAX address
30000000#16.
Table 11-3:

FBIC CSR Offsets

Name
MODTYPE
BUSCSR
BUSCTL
BUSADR
BUSDAT
FBI CSR
RANGE
IPDVINT
WHA...MI
CPUID
IADRl
IADR2
SAVGPR

Address
01FFFFFC#l6
01FFFFF8#16
01FFFFF4#16
01FFFFF0#16
01FFFFEC#l6
01FFFFE8#16
01FFFFE4#16
OIFFFFE0#16
01FFFFDC#l6
01FFFFD8#16
01FFFFD4#16
0 IFFFFDO#l 6
01FFFFC4#16

Read/Write
Read
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read
Read/Write
Read/Write
Read/Write

Description
Module type register
M-bus error status register
M-bus error control signal log register
M-bus error address signal log register
M-bus error data signal log register
FBIC control status register
I/0 space range decode register
Interprocessor/device interrupt register
Unique software ID register
Unique hardware ID register
Interlock-I address register
Interlock-2 address register
Scratch register for halt code

11.2.2. Q-Bus Interface

The Q-bus interface consists of the CVAX Q-Bus Interface chip (CQBIC), four termination resistor SIPs,
one wake-up capacitor, one 5.6K 1 percent bias resistor, and open-drain output pull-up resistors.
11.2.2.1. Device Features

The CQBIC implements a CVAX pin-bus to Q-bus interface, a 16-entry cache of the 8192-entry
scatter/gather map, control and status registers, interrupt logic, and Q-bus transceivers.
The CQBIC supports byte, word, and longword transfers from the CVAX pin-bus to the Q-bus and internal
registers, 16-word writes from the Q-bus to system memory via the CV AX pin-bus, and quadword reads
from the system memory to the Q-bus via the CVAX pin-bus. On its CVAX pin-bus side, the CQBIC
issues longword read/write, quadword read/write, and octaword write transactions to service scatter/gather
map lookups and Q-bus transactions. Q-bus instruction types supported are DATI, DATIB, DATO,
DATOB, DATIO, DATIOB, DATBO, and DATBI.
The CQBIC supports operation as both the Q-bus arbiter and a Q-bus auxiliary. The FQAM supports only
operation as the Q-bus arbiter.
The CQBIC supports doorbell interrupt requests and Q-bus interrupt-acknowledge cycles.
For a detailed description of the chip's operation and the format of its control and status registers, see
Appendix H, CQBIC Specification, in the Firefox Designers' Guide.
11.2.2.2. Busses

The CQBIC connects to both the C-bus and the Q-bus and forwards transactions between busses as
appropriate. It also generates C-bus transactions to service caches misses to its scatter/gather map.

4 Firefox System Specification

December 28, 1987

Firefox Q-Bus Adapter Module 11.2.2.3.

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11.2.2.3. Interrupts

The CQBIC connects the Q-bus interrupt request signals to the C-bus interrupt request signals. The FBIC
conditionally connects the C-bus interrupt request signals to the M-bus interrupt request signals. The
CQBIC MEMERR signal connects to the FBIC device interrupt request signal (DEVIRQ<3>) to conditionally generate M-bus interrupts.
11.2.2.4. Reset

The CQBIC is reset when either l\1RESET or the FBIC RESET signal is asserted. During reset, the CQBIC
tristates its 1/0 pins and initializes its internal registers.
11.2.2.5. CQBIC Address Map

Table 11-4 lists the addresses of the CQBIC control and status registers.
Table 11-4:

CQBIC CSR Addresses

Name
DBRO
DBRl
DBR2
DBR3
DBR4
DBR5
DBR6
DBR7
SCR
DSER
MEAR
SEAR
MAP_BASE
MAP_START
MAP_END
Q22_IO_START
Q22_IO_END
Q22_MEM_START
Q22_MEM_END

M-Bus Address
80001F40#16
80001F42#16
80001F44#16
80001F46# 16
80001F48#16
80001F4A#l6
80001F4C#l6
80001F4E#l6
80080000#16
80080004#16
80080008#16
8008000C#l6
80080010#16
80088000#16
8008FFFF#l6
80000000#16
80001FFF#16
90000000#16
903FFFFF#l6

VAX Address
20001F40#16
20001F42#16
20001F44#16
20001F46#16
20001F48#16
20001F4A#16
20001F4C#16
20001F4E#l6
20080000#16
20080004#16
20080008#16
2008000C#l6
20080010#16
20088000#16
2008FFFF#l6
20000000#16
20001FFF#l6
30000000#16
303FFFFF#l6

Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read
Read
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write

Description
Arbiter doorbell register
Auxiliary #1 doorbell register
Auxiliary #2 doorbell register
Auxiliary #3 doorbell register
Auxiliary #4 doorbell register
Auxiliary #5 doorbell register
Auxiliary #6 doorbell register
Auxiliary #7 doorbell register
System configuration register
DMA system error register
DMA master error address register
DMA slave error address register
Scatter/gather-map base register
Start of scatter/gather map
End of scatter/gather map
Q-bus 1/0 space start
Q-bus 1/0 space end
Q-bus memory space start
Q-bus memory space end

11.2.3. Clocks

The FQAM requires the following clocks:
•

10-:MHz, two-phase clocks for the FBIC

•

40-:MHz clock for the CQBIC

The CVAX Clock chip (CCLOCK) supplies the two-phase clock to the FBIC. It also provides synchronization for the CRDY and CERR signals, thus allowing the CQBIC chip to operate asynchronously.
A single oscillator will be used to generate the 40-:MHz and 10-:MHz clocks.
11.2.4. Status Indicators

The FBIC status indicator outputs drive 4 red and 1 green LED indicators mounted at the FQA.i.\.1 module
edge.

11.2.5. Firefox Q-Bus Adapter Module

December 28, 1987

Firefox System Specification 5

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11.2.5. Bus Driver-Disable Circuit

A driver-disable circuit is implemented in the FQAM to prevent damage to a module inadvertently plugged
into a wrong slot. The FQAM will disable its M-bus drivers when it is not in M-bus slots 0-7 and disable
the Q-bus drivers when its not in M-bus slot 0. Likewise, all other M-bus modules implement similar circuits to disable their drivers if they are not in their designated slots.

11.3. Programming
In this section, required initialization of the FQAM is described and some programming guidelines are
listed. The examples used herein are based on an FQAM in M-bus slot 0; all addresses are VAX physical
addresses.
11.3.1. Locating Modules

After a workstation reset (M-bus 'MRESET asserted), console and diagnostic software must determine the
workstation configuration. The FBIC saves, in its BUSCTL register, the value of the M-bus MBRQ signals
during 'MRESET. Software can use this as a module-present indication to identify backplane M-bus slots
that contain Firefox modules. To intetpret the BUSCTL<MBRM> bits, a module must first determine its
own M-bus slot by reading its FBIC CPUID<MID> register field. Table 11-5 lists the intetpretation of
BUSCTL<.MBRM> as a function of a module's M-bus slot (from its CPUID<l\.1ID>). Software must use
or save the value of B USCTL<MBRM> before it enables FBIC error logging, or the information will be
lost.
Table 11-5:

Interpretation of FBIC BUSCTL<MBRM> Field

CPUID<MID>
0
1
2
3
4
5
6
7

<6>
7
7
7
7
7
7
7
6

<5>
6
6
6
6
6
6
5
5

<4>
5
5
5
5
5
4
4
4

<3>
4
4
4
4
3
3
3
3

<2>
3
3
3
2
2
2
2
2

<1>
2
2
1
1
1
1
1
1

<0>
1
0
0
0
0
0
0
0

For example, if a module reads its CPUID<MlD> register field and obtains 4, it is in M-bus slot 4. If it
then reads its BUSCTL<6:0> register field and obtains 1011001#2, there are modules in M-bus slots 0, 3,
5, and 7.
To confirm the presence of a module in each slot, software should read the MODTYPE register of each of
those slots. In the example just given, the MODTYPE registers would be at VAX addresses
31FFFFFC#l6, 37FFFFFC#l6, 3BFFFFFC#l6, and 3FFFFFFC#l6. Reading the FQAM's MODTYPE
register will return the value 01010001. FQAM ROM should have a known location that more precisely
identifies it as the FQAM.
11.3.2. Addressing

The CQBIC registers and scatter/gather map are at fixed addresses as defined by the CQBIC. Because the
FQAM can only be in M-bus slot 0, the FBIC base address is always 30000000#16.

6 Firefox System Specification

December 28, 1987

Firefox Q-Bus Adapter Module 11.3.3.

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11.3.3. lnltlallzation

After workstation reset (M-bus :MRESET asserted), the FQAM requires initialization of the FBIC before
normal operation can commence. Software must generate the following register writes:
1.

MOVL FFFFFFFF#l6 (31FFFFF8#16), to write the FBIC BUSCSR register to enable error logging.

MOVL OOFF003E#l6 (31FFFFE8#16), to write the FBIC FBICSR register to connect the CVAX
pin-bus CIRQ signals to the M-bus MIRQ signals for CQBIC interrupts and enter normal operating
mode.

MOVL 80088008#16 (31FFFFE4#16), to write the FBIC RANGE register to make the CQBIC
accessible.

MOVL 0002VVVV#l6 (31FFFFE0#16), to write the FBIC IPDVINT register to enable device
interrupts from CQBIC memory errors, where VVVV is the desired interrupt vector.

11.3.4. FQAM Module Restriction

Because of the electrical connection between the M-bus and Q-bus on the backplane, only one FQAM is
allowed in a Firefox Workstation system.
11.3.5. FOAM ROM

The FQAM ROM is intended for FQAM self-test code and workstation Q-bus disk/tape/network bootstrap
code. Access to the ROM from other modules is relatively slow, typically two microseconds per access. It
is recommended that frequently used or time-critical code be copied to memory.
11.3.6. FQAM Access Restrictions

Because of a CQBIC implementation constraint, operating system software must restrict access to the Qbus and CQBIC to a single processor. Interlock transactions to the FQAM are not supported, except those
to the FBIC registers.

11.3.6. Firefox Q-Bus Adapter Module

December 28, 1987

Firefox System Specification 7