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EK-DCJ11-UG-PRE

October 1983

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Document:	DCJ11 Microprocessor User's Guide
Order Number:	EK-DCJ11-UG
Revision:	PRE
Pages:	262
Original Filename:

OCR Text

EK-DCJ11-UG-PRE

DCJI11
Microprocessor

User's Guide

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PRELIMINARY

2020020

EK-DCJ11-UG-PRE

DCJI11
Microprocessor

User’s Guide

PRELIMINARY

Prepared by Educational Services

of
Digital Equipment Corporation

Preliminary, October 1983

The material in this manual is for informational purposes and is
subject to change without notice.

Digital Equipment Corporation assumes no responsibility for any

errors which may appear in this manual.

Printed in U.S.A.

The following are trademarks of Digital Equipment Corporation:
DEC
DECnet
DECUS

EduSystem
IAS
MASSBUS

DECSYSTEM-20

OM. RUS

025050

POT

DECsystem-10
DECwriter
DIBOL

RSTS
RSX
TOPS-10

MI! 'C-11

TOPS-20

0S/8
PDP

VAX
VMS

UNIBUS

CONTENTS

Page

PREFACE

3
PROCESSOR STATUS WORD...:ecevoeenens
Processor Modeso..Q.......O.‘.......Q..............
3 .1l
3 .2
Priority Levels.0.........'0.0.............
®

The Trace/Trap Bit.iceeseeecesesssccoscssscsssncccss
Condition COdeS.ceeeeoceoscccosssscsnssssssscssscscscsce
Processor Status (PS) ProtectioN..cceceecececccecses

INTERRUPTS AND TRAPS . v coveeesoceesocscscssssssosesossos

5
6

HALTING
PROGRAM

CPU ERROR REGISTER.:ccceoeescsovsescssosvscssosvcsos
STACK PROTECTION...vcceecovcocoss
FLOATING-POINT PROCESSING
..... cecevsescrssre
s ss

DIRECT-MEMORY ACCESS

CHAPTER

(DMA)

MECHANISM......

DESCRIPTION
®

NNNUNAOAAAAAAAT
VUL DOBEDLHELEDWWWWWWINN

Upper Data/Address Lines (DAL<21:16>)..cecceccccses
2.1
Lower Data/Address Lines (DAL<15:00>).ccceececccces
2.2
SYSTEM CONTROL LINES . . ¢tecesetoecsoscsosscscssscscsoscsscsscsssncsese
.
Bank Select (BS<l:0>) .eieeceesooescsossosnosssssncss
3.1
Address Input/Output (AJO<3:0>).ceeeresecccoscanoes
3.2
Buffer Control (BUFCTL) veeeecoocoosossosccsossssssesee
3.3
Continue (CONT)..eeeoses 6t esoecesscesecseesssssesssess
.3.4
3.5
Data Valid (DV).oevoe cec oo ee e cecsesesesessssssense
o
o
o
®

Vb
w N

e
o
e

Address Latch Enable (ALE) ¢t vveevoevocsosssoocsoscscss
Stretch Control (SCTL).ovee.n ceeeceevsccsssanns
e
Strobe (STRB) tcceteeens se oo c oo eesccs s s sssecsase
CloCK 1 (CLK) ¢eeeeeecoonssossessossossosssssscossasse
Clock 2 (CLK2) toeeeevoonvnersnseossssnssssssssoscasssscass

@
o
o
o

o
W

e«

e
L]

DW=

STATUS

s s s s e e s .o

START/STOP CONTROL..... cece
e rees s e e e s e s s s cs s s s v oo s
Initialize (INIT) ceevesvoscsosossscsonssesssccsosscos

N -

o
o
L]

. e ceeeevocsonscosse e s s ee o
TIMING SIGNALS

Halt

(HALT) ¢ e e voeeo ss e s tsavssss ¢ & ¢ & 5 0 0 ¢

000

SIGNALS . ¢ ¢ cesccoesoesssssossscsessscscnscsscsosstsssssse

Cache MisSsS (MISS) teveeeroessocsossosososssssosssccsscscss
Parity Error (PARITY) .cuceeereccccnscs

Abort

1-17

(ABORT) .eceeeeesoes

Map Enable (MAP) ... ceeereececosossoscssscescssacsccssss
Predecode (PRDC) cveeeotorescnoscosooscsocssosssccnssscs

INTERRUPT AND DMA CONTROL.:¢teeeewe ctisesscesssesanos
e e .
Interrupt Request (IRQ<3:0>).ccses.
Direct-Memory Access Request (DMR).
.
Power FAail (PWRF) ceeeeceoeessosscosssnsoncscsnnsces coee
iii

2
2

2
2
2~
2=
2=
2=
2=
2=

.11

.10 MEMORY SYSTEM REGISTERS..........;.....................

NN EBLERWNODNDNDND N

8
9

DCJ1l OPERATION...cceesoeoss
INTERRUPT REQUEST REGISTER.....................

OOV I

3 .3
3 .4
3 .5

ldh‘thkflthfi‘HrdhfldhflH
1
I

T
~]

INTRODUCTION ......... o ¢ & 0 ¢ &6 6 0 o
GENERAL-PURPOSE REGISTERS.....

ot = =
HEEOAOAONROOWNDE
~Noo
o o ot

ARCHITECTURE

1
2

NNNMNNNN(})NNMMNNNM
|
1
|
I
I
|
|

CHAPTER

Reserved

N
w

[

Error

.
.
.
.
.

[
.

N o~

@
.

®
L

BB W N

[}

R -

oo
o

OO DWWN

W
@

Memory Management Reglster #0

e
¢«

FAULT RECOVERY REGISTERS.....

BitS..eei oo

INTERRUPT CONDITIONS UNDER WEMORY MANAGFMENT

= O

UJW&UUJ$LQquI

Cache......iviirivvecsnnencncns

Page Length Field (PLF ) .
Page Written..........
Expansion Direction (ED).
Access Control Field.......coc0 .o

Flags.

ceco v

Read Only

Abort -- Non-Resident..
Abort -- Page Length....
Abort

Reserved Bits..... e e e e s e
e
Processor Mode...v.eee
Page Address Space....
Page Number....eceeeee
Enable RelocationN........
Memory Management Register #1
. ..
Memory Management Register 42 (MMR2)
(MMR3)
. . .
Register
#3
ent
Memory Managem
Reserved Bits...
¢

(MMR1) . . .

Enable I/O Map"...Q...l'...........
iv

DRV
WN

L
N

=W O OWOWODOOENINIII

e
.

[}

Bypass

J\wb'u)(\.)i—‘

. 2.

REGISTERS.........

Page Address Registers (PARs)
Page Descriptor Registers (PDRs). ......

*
®
L

- O

MANAGEMENT

LJ
L]
.
&

N
1
L

\l\l\l\l\l\l\l\l\l\l\]\J\J\I\J\IJ\UI\DJ‘IJ‘U\J\U‘IJ\'\DJ}U)(\JH

)
.

eveesnn
CE.
..o
SPACE AND D SPA

CONSTRUCTION OF A PHYSICAL ADDRESS..........

MEMORY MANAGEMENT

eoosccsenacs
TION
., . coeeeee
INTRODUC
s
G.
sassnscoe
SIN
e cesvsosos
ADDRES

o
¢«

0 DMA REQUESTS AND GRANTS....¢e0c00

READ CYCLF...
WRITE CYCLE.

INTERRUPT ACKNOWLEDGE CYCLE.

(GP)
(GP)

GENERAL-PURPOSE
GENERAL-PURPOSE

e 2.

BUS CYCLE PARTS..vevveeenonsns
NON-I/O (NIO) CYCLE..::oooesos
BUS READ CYCLE...veeueeenoonnns
BUS WRITE CYCLE...... e

DURATION OF BUS CYCLES........

A
- N
[
1

®
¢
e

WO -JIHhIN
L& WwN

w WwWwiw W
W

W
W

nonses
ION
v v vovnsoon
. ¢ v UCT
INTROD

CHAPTER 4
bbbbbbb-fibbbbbbbbbbbbbbbb&-&bbbb

L]
*

BUS CYCLES

CHAPTER 3

L]
[]

Ground (GND) ceeveeecossece
10.2
11 PIN DESCRIPTION SUMMARY....ceceoe oo

®
L]
L]
.
L]
L]
*
*
*

L]
e

e
L]

[]

(VCC)lieessersooonnns

Power

.10.1

XTALI and XTALO Generation

e e e s e e e
S
.. ceseeco
POWER PIN

9.1

ce s e s s un

(TEST1).

[

Test 2 (TEST2) ceveveesooos
OSCILLATOR PINS..¢eesceesoosene

Test 1

8
9

[]

.
*

PINS...O.I..0.C..l.'....l..‘.'l".....

TEST

e = OO OO OO O ®

(EVENT)..'.'.....'..

Event

NN(T)(\)(\)N{ l\')N(T)NN

Floating-Point Exception (FPE).........

Enable

22-Bit Mapplng..........................

Enable Call To Supervisor Mode Instruction.....
Kernel, Supervisor, and User Mode D Space Bits.
Instruction Back-Up/Restart RecCOvVery..coceeeseesscs
Clearing Status Registers Following Abort........

Stack MemoOry PaAgeS..ceicececsccecscscsccssnns

Non-Consecutive

Multiple Faults...
ss
ON.
ccccccccsss
TATI
. v coescsccesc
IMPLEMEN
..
Typical Memory Page....
Memory

PageS.cceceecocscns

TransparencCy.....

©&

L
*
.
5

.
.

W
L

(RCSR)

Interface...

Receiver

Control/Status Register

Receiver

Buffer

Transmitter Control and Status Register

123)

Processor Status Word...

(ASCII

107)

GOueeresnsssssscscsesssns

Console ODT Output Sequence...ceesecnse
Console ODT Command Set.ceesseoscsccscoscons
(ASCTI 057) Slash.e.:veeeeoesccecosonscs
o
<CR> (ASCII 01l5) Carriage Return voo
<LF> (ASCII 012) Uine Feed...ceevocees
S (ASCII 044) Or R (ASCII 122)ceevecses

(ASCII

5-12
5-13
5-14
5-14
5-15

5-15
5-16

5-16
5-17

P (ASCII 120) Proceed.
Control-Shift-S (ASCII 023)....
Address Specification.
General RegisSterS...ceesocscscccsesans

Ld
L
*

(XSCR)

Transmitter Buffer Register (XBUF)...
Console ODT OperationN..iceesecsccocsconcnse
Console ODT Initialization.....eeoeeee

(RBUF).....

.
.
.

5-17

5-18
5-18

Stack POINtErS.iu
. ieesessessesssssossss

Floating-Point Accumulators...........
Entering Octal DigitS...eceeeeeecssasosens

5-18
5-19
5-19
5-20
5-21

ODT Timeout...... Gt s
e e
s esesesss
e s
e
Invalid CharactersS..cieescevscsscsscssccscs

DCJ11 PIPELINE PROCESSING..:.veccecececsccascsccs
Pipeline Flow Example..cciceveeesscsscnnvsos

CHAPTER

ADDRESSING

6.1

INTRODUCTION.
..

6.2

ADDRESSING

MODES
&

MODES..

AND

BASE
9

INSTRUCTION
0

SET
D

H WO
= YOO
NN o o

L]
[]

*
L
*

|
[
T
I
I
wununnfiwmunuwwuru1mgnu1wunur
P

.
.
Ll .
W

.
.
.
.
°

Implementation..iceecececessosscsccsasonsns

ODT...covvven

Terminal

[
.
.

w N~

W
DD

Sample

.
)
L]
¢

Cache Memory In A Multiprocessor Environment.....

CONSOLE

(R/W)..

Force Cache MisSsS (R/W) eeseeecsanns
Uninterpreted Bits.
Hit/Miss Register......
General Overation...
®

qmm»bbbwwwwwwwwwmwwt—w—'l—'t—dt—a

bbwwwwwwwwwwwwwwwwwwwwwuwwu

Unconditional Cache Bypass

[]

[]
e
®

LJ
L
L]

INTRODUCTION

CACHE MEMORY STATUS AND CONTROL REGISTERS.
Cache Control RegisSter..cececeeeccocccs

(520
)

FEATURES

]
Ll
*

SPECIAL

[]
L]
[]

CHAPTER

UNIT

MEMORY MANAGEMENT

IR
NN HE bbb
WN -

OISO

*
LJ

L[]
[]

Logicalioo0.0l.............‘...................
Program Control InsStructionS...ceececececceccccccns
BranChesS..eeeseeecesossssssnccossssossscsssssssse

]

[]

]

Signed Conditional Branches...cccteeececsccssnas
Unsigned Conditional BrancheS....eeeeseccessssce
Jump and Subroutine InstructionS....cccceececoe

DIV

.1l

Reserved
Trace

OSSO

Instruction TrapS..cceecesescecsocccsss

Trap....

Special Cases Of The T-Bit..eeeceececessone
Miscellaneous INStruUCti
. ceeeceeeecrsocossanonnses
oNS.
Condition Code OperatoOrS..icececcscccccccccssssoscsnss
FLOATING-POINT

ARITHMETIC

INTRODUCTION. s st o eeseesassoscscsoscsossossscscocsacooosssssss
FLOATING-POINT DATA FORMATS ..t coesessscvsosscssscssosccces

Non-Vanishing Floating-Point Numbers...cceceeeoeeceoeo

.2
.3
4

Floating-Point Zer0...ceceecesecsee coossnsscccccss
Undefined Variables..... et eccecrrsetcecs
ot
n 0o
Floating-Point Data..c.iceeeeeeesecoessoocencsancsnsos
FLOATING-POINT STATUS REGISTER.:ececeeecsscccocssscsssoe
FLOATING EXCEPTION CODE AND ADDRESS REGISTERS..:¢scese.
FLOATING-POINT INSTRUCTION ADDRESSI
.. ceceseeccso
NG.
ccsses

ACCU
.. ceeoveencsn
RACY
cnnne
FLOATING-POINT INSTRUCTIONS

CHAPTER 8
8.1

INTERFACING

INTRODUCTION..00........O.I..i........l.'...l.'.......‘

[]

Traps

‘Miscellaneous Program CONtrol....eeeesscecocooss

JWN

L]
L[]
°
[]
®
®
L]
L]
[]
[]
®
[]
L]

[]

=00

WWWWWWwWwWwWwwWwwWwwWwww wWwwwwuww ww

L]
*
L]
*

L
L[]
[}
|]
L]
L]

]

[]

AAARATRAARAAAN AN

PS Word OperatorS. ® © 8 & 0 6 6 0 5 6 OO SO O PO OO ST O 00 s s 0o
Double-Operand INStruCtionNS..ceececssoscccsscscconsce
Generalo.O...l..0....C.......................Q.

General...l.'...Q..............................
Shifts and Rotates. ® & @ & & 6 0 & 0 6 0 0 0 O O PSS O OO 0 NS O 0o
MUItiple—PreCiSiono ® & & & O 5 & VOO O OBO S SO OO PSSO PO N O S SO

CHAPTER

[

Byte INStruCtionS..icieceeeeesscnssocecsscssancccsssocs
List of InstructionsS.ceeeeeceecsccosscsececoooccscss
Single-Operand INStruCtioNS.cecececsocccocoscccocse

INSTRUCTION SET ¢.eececocssesssscsoscecsossssscoocssocssass
Instruction FOIMAatS..ieeeceetscccccocossscccsonasss

L[]

HE=OONOOUDWW

Autodecrement MOde@...ceeeesocsccsscoscocoonnnos
IndeX MOAE. . ceeeeoeeccsosscssossscsosssosscsosscsnsses
Deferred (Indirect) AQAressSing..ccceeececsccececcsns
Use of the PC As a General-Purpose Register........
Immediate Mode. ® & & & & ¢ & 0 O 0 B OO OO DO OS OGNS G OO NS SO S 0o
Absolute AddreSSing- e & 0 & 0 & 0 . * 0 @ ‘. *® O O 9 &0 0 09 0 0 0 0 s o0
Relative AddressSing....ccceececeescccscccccscses
Relative-Deferred Addressing.cceecoceceee
Use of the Stack Pointer As a General-Purpose
Register.........

G\O\O\O\O\?O\O\O\O\

S W N

B W N

[]

oD NN
NN

L]
L]
[]
[]
[]
L4
®
L]
L]
®
[]
L
ANV NN s WWWWWwNoE
L]
L
[}
e
L
[]
*
]

e ) Jo, Boy)

[)
.

[]

leaWe W e Mo We Wo \ Jo o W Yo e

Single-operand AddreSSingoofoooooooo..ooooooo.ooooo
DOUble-operand Addressing.l........................
Direct AAAressSing....cccecceccecssccccecscoccooccnss

8.2
GENERAL-PURPOSE (GP) CODES. © @ & ¢ & @ & 4 0 0 0 0 06 0 0 0 6 O 0 O O O S e O G 0 o0
8.3
POWER UP AND INITIALIZATION»..Q....l....‘......‘.......
8.3.1
Initialization Timing..seeeeeeeeeecscoscocscccsnsess
8.3.2
Initialization Microroutine.....vveeeeeoecoeesaness
8.3.3
Power-Up Configuration.v.eicieeececececosccsccsccsoces
803.4
Power-Up Circuit....O..00.0.0......................
8.4
OTHER MICROROUTINESQ...'. ...... OQ...........O....?......
APPENDIX

CHARACTERISTICS

APPENDIX

CHARACTERISTICS

APPENDIX

HARDWARE

APPENDIX

INSTRUCTION

APPENDIX

GLOSSARY

AND

SOFTWARE

8-1
8-2
8-2
8=2
8=6
8_8
8-8

DIFFERENCES

TIMING

INDEX

FIGURES

Figure

Page

1-1

DCJll

1-2
1-3

DCJll

BlOCk Diagram
® & & & 6 6 ¢ & & 0 0 0 O 0 O O O O OO OO PO
N E SO 0
General
Purpose Reglsters........................
Processor Status Word.......... e

1-2

1-4
1-5
2-1

PIRQ Reglster......’.. ..... O o o @ & o & & 0 & ¢ O 0 O 6 6 S GG e OO ® 0
CPU Error Register..l....Q'1’......................l....
DCJll PinAssignments...00.00..0......0.........0.....0

l-ls
1-15
2-1

2-2
3-1
3-2

Typical XTALI and XTALO GeneratioON...ceesescccsaccceses
Non-Stretched Non-I/O CYCle.cveeececcsoccscccosssssssss
Stretched Non-I/0O CYCle...coeteeecconcossosscssosasocsosse

2=9
3=3
3=4

3-3
3-4
3-5

Non-Stretched Bus Read CyCle..cceeeesescsssscsssssscsss
Stretched Bus Read CyCle..iieeeeeseecscncsscsscssocsnse
Bus Write CyCle.iiiciierersoeovoossosceososcsosssscssonecnse

3=5
3=5
3=7

3-6
3-7
3-8

General-Purpose (GP) Read CyCle..ceeeeececsccsncccesssece
General-Purpose (GP) Write CYCle.iiceesecescsoscsccssss
1Interrupt Acknowledge CYCle..ccceeeecocoecocssseoccosss

3-8
3-9
3-10

4-1
4-2
4-3

Virtual Address Mapping Into Physical AddresS....ccee..
Interpretation Of A Virtual AddressS....cceeecesccossses
Displacement Field Of Virtual AdAresSS..eeceeececcecsccces

4-3

4-4
4-5
4-6

Construction Of A Physical AdAressS...cceesesccesscncess
Active Page Registers........... ceccsescsesrsrssesescses
Page Address Register..... ceeeceseccssssssssesssescssess

4-7
Page Descriptor Register
(PDR)...eeeeeesceosossscossnnee
4-8
Memory Management Register #0 (MMRO) e veveoesovocvcoceccess
4-9
Memory Management Register #1 (MMR1) ..vveeeoeoeseocoess
4-10 Memory Management Register #3 (MMR3)...ceesecesccossess
4=11 16-Bit MappPing..e:veeeieeeevoeoeeeneronsesocnnsosansess
4-12 18-Bit MapPPiNg.eeeeeetrveeevesosssessensoosesancsoossoes

1-1
£

4-2

4=4

4-4
4=6
4=6
4=7

4=9
4=11
4=11
4=12
4=12

4-13
4-14
4-15

22-Bit Mapping.......... ceevaee e
Typical Memory Page.
ceetneen Y
Non-Consecutive Memory Pageé...........................

A
e
4-17

4~1¢

Typical

4-18

Stack Memory

Page.....o.. teesecsscsescscsaceseses

vii

Cache Entry......

Cache Entry With Parity.ecceeeestencsssscocccccccoces

Sample Cache Control Register.......covevnvaccccccnns
Receiver Control/Status Register (RCSR).cieevecccccsn

(RBUF) ...ciceeecssecsccsocane

Receiver Buffer Register

Transmitter Control/Status Register

(XCSR)...eeeeenen

Transmitter Buffer Register (XBUF)....cooeeeeccccccns
Pipeline Filling ProCesSS...ccceesesscosssccscsscssocce
Single-Operand Addressing...c.ceeeeeeecrsossccccasonne
e
e sss
Double-Operand Addressing.......... s esersss
Mode
Mode
Mode

Ceetecaear e
O Register...eeeeeeccenocennns
2 Autoincrement...cceeecosossossosososocscnnssosccsen
4 Autodecrement....cceceveeccessscscssccosssosos

Mode

A
T
T
Increment....... cevee

IndeX..eeoens .

INC R3
c e s e s e s s s e
v e e v s e e e .
ADD R2,R4 Add...veve..n
e e
ceress
e
cesesao
.......
COMB R4 Complement Byte.
e s us
eere
e
s
s
s
e
eses
s
e
e
ns
CLR (RS5)+ Clear...cceveeeseave
s
s
e
et
e
c
ssossn
CLRB (R5)+ Clear Bytee.iceeeevoesrsao
e
s
eeeesee
s
s
s
et
e
s
e
et
s
e
ee
e
ADD (R2)+ R4 Add...
cesssesss e
INC -(RO) Increment....cceeceeoocceeos
ceseees e
e
e
ce
..
INCB - (R0O) Increment Byte.......

ADD -(R3),R0O Add...vccveeeeecennss ceee e Gt e
CLR

200(R4)

ce e
e st sseen
Clear..... cee

e
e cececses as

COMBR 200 (R1l) Complement Byte...vieeeesescocscooncasos
s et eses e eesss e
ADD 30(R2),20(RS) Add...cceeesns e st

Mode
Mode
Mode
Mode

1 Register-Deferred......... s e e e e cresecssenens
3 Autoincrement-Deferred......ceieevcvecocsncs
e
5 Autodecrement-Deferred........ C et esesessseee
R
Ceteseaes
....
ferred..
7 Index-De

mc\a\ma\f\mmmmm

Physical Address Partitioning For Cache Memory.

gy ooy
oy
DA
N HAAIITIITAAARADNNIDHIHN
|
|
1
1
i
|
i
T
i
VW
WNOHREFROMNDDS
DN
= == OO O ORI I,
O~
0O 0
NN o o

— O

T
N
TN O
OO

bW o

UL IR S R VL VLRV LR L Ly

TR N

TR T
A
O
D W

AR ARA MR AR AN NRC

[
N T
N
T
== OO~

AR A AR AR
e

Cache Control Re gister.......
Hit/Miss Register..ceeceeeessns ce

h=12

GRS Clea@r.cesessscsossossoscnsnsssssos ceeecasessense
@(R2)+ Increment...ceeeecvcosnoscssoconsocs e s e e
@-(RO) Complement...ccecveeveeoceocnns cessssees e

6-23
6-24

s e

h-14

s
.. :eeeesecceconocsossosns e e e
e
CLR Q#1100 Clear.ceeeeseessososoanenossanossas Ceresesn
.
ADD @#2000 Add.....cccveeun et e e e e e e e
oo
s es e
e e
o
INC A Increment.....c... s o e o oo
ceeer e soee
cea s e s e e e e e
CLR QA Clear.......

6-15
h-16
6-16
6-17
h-18
6-19
A=-20
h-20
6-20
5-20

CLR
INC

COM
ADD
ADD

@1000(R2),R1l Add....... C e e st s esscaeses

#10,R0O

Add.

e Ceee e oo
Single-Operand Group ....... e et
cessrsnen e s
Double-Operand Group l.......00c00 .
ceee sesseees
Double-Operand Group 2.....ve00 “ o

Program Control Group Branch..... P
Program Control

Group JSR.......cccuevn teeres s s e

6-13

Program Control Group RTS........ v ee e s ces e s
cesrssass e
Program Control Group TrapS....... “ o

6-20
6-20
h-21

MALK .o oooeoososoosocsossssnsssosssssossescssssncessocsesns

h-21

Program Control Group Subtract.

.« o

Cr et e

Call To Supervisor MOAe..v.eet
oot osonseoossoroncssnns
Set Priority Level....oeeeeeeeeeeoerssensscsoscsscscaso
Operate

Group........................................

Condition

Group.

*®

Move To And From Previous Instructlon/Data Space Group.
Byte

Instruction S

e o @ O ¢ o o

viili

6-21
h=-21
6-21
h=-21
6-22
=22

8-1
8-2
8-3
8-4
8-5
8-6

2”s Complement Format..
Floating-Point Status Register..
Floating-Point Addressing Modes.
Initialization......eccevecccens
Initialization Sequence.....cse.
Power-Up Configuration Register.
Power-Up Circuit..... Ceeee “oo
e

[

ooooo

Power-Down SequenCe....cceeevosse
Console ODT Start Seguenceé......

Voltage Waveforms....... cerenen
o
e
Chcecrrsasen
Clock Timing.
Three State Dlsable Test Circuit,
B-3
TTL Output Test Circuit.....oeee
B-4
MOS Output Test Circuit........o
B-5
Non-Stretched Bus Read Timing...
B-6
Stretched Bus Read Timing.......
B-7
Bus Write Timing...coeecoosenoeos
B-8
General-Purpose Read Timing.....
B-9
General-Purpose Write Timing.....
B-10 Interrupt Acknowledge Timing....

mmmmulnmmm
I
B |

A-1
B-1
B-2

B-11

pond

7-5

7-3

W Wl

Format..

R
L L L.

Format..

Double-Precision

NNV
LD BWEEHEOOIWN -

Single-Precision

PPPPOOOODOD QNN NN

7-1

Interrupt Timing........ cesee e

5-2
5-3
7-1
8-=1

Console ODT Commands....
cereseees
e
Pipeline Flow........ ce e s s s es s s esesnoe e
FPS Register BitS..iiseeeeeeesocsosccccscnss
GP Codes and FUnCctionS..e.eeeeosocescscsss

C-1

DCJ1l

Bit

OperationS......... .

ceesus

Hit/Miss OperationS..ccceeeececceses

Programming

DifferencesS..eeeecsocese

D
N
T

WO
O

Typical

Mode

5-1

4-2

1IRQ<3:0> Interrupt Request Levels.........
AIO Codes for Bus Cycles..... C etses e en s
General-Purpose Read Codes...... ceeseseses
General-Purvose Write CodesS..cceeocccossnns
Interrupt Acknowledgement......ccececocoene
I and D Space ReferenCing..ceecececeececas

3-1
3-2
3-3
3-4
4-1

AR AMNNHWHWHEHONOOL WHRFRFWOJIONW,M

Device Selection..... ceerreensesaes ee
e .
e e c
o vensans ceereasraca
e
Decode.
Interrupt Requests on IRQ<3:0>....... ceene

([

AIO

Instructions...

RTT

2-3
2-4

RTI,

PS Protection For MTPS Instruction........
PS Initialization During Power-Up....cceso
Interrupts, Traps, and Aborts..... cece e

2-2

Protection For

Explicit Accesses cesenn
Traps And Interrupts....

2-1

Protection For
Protection For

RN |

1-6
1-7
1-8

PS
PS

1-5

1-3
1-4

Influenced By Processor Modes.

LevelS...ieveeeececsssceccocossnnce

Priority

TR N

Instructions

1-2

[

1-1

NOJUVUTUNE DBWWWWNNN N O

Table

L el sl el el

-U
1))
O
o

TABLES

PREFACE

This user”s guide is intended to
familiarize the reader
with
the
hardware
and software characteristics of the
DCJ11 microprocessor
CPU chip.
It is assumed that the reader has
had
some
experience
with
microprocessor
design.
Readers
should
also
have
some
familiarity with PDP-11 architecture.
The

book

organized

Chapter

provides

Chapter

describes

follows:

architectural

the

function

Chapter 3
provides

describes the various
an
overview
of
the
and outputs during these

inputs
Chapter

integral
Chapter
to

provides
DCJll:

includes

cache

and

Chapter

describes

Chapter

describes

instruction
8

external

are

the

set.

provided.

some
the

operation

three

special

registers

base

and

integral

ODT

wunit

and

circuits

contains

summary
of

the

DCJ1l

characteristics.

Appendix

contains

summary

the

DCJ1l

characteristics.

Appendix

summarizes

DCJ1l

and

Appendix

between
Appendix

the
also

and

describes

floating-point
Appendix

contains

the DCJ11

instruction.

the

hardware

PDP-11/44
a

other
how

Timings

for

instruction

contains

brief

and

differences

(2)

summary

the DCJ11
of

the

processors

determine

the

both

set

are

the base

(1)

the

software

the PDP-11
duration

the

PDP-11/70.
differences

family.
of

DCJ1l1

instruction set and

provided.,

glossary

between:
and

some

DCJ1l

its

interfacing

initialization

Appendix

also

(also

set.

information

Power-up

DCJ1ll’s

description

floating-point

introductory

the

console

inStfuction

integral

DCJ11l.

cycles
and
among DCJ11

features

(this

processing.

provides
logic

and

considerations),

the DCJ1l

pin.

cycles.

pipeline

the DCJ1l.

types
of
DCJ11l
bus
timing
relationships

memory

design

each DCJ11l

unit.

information

memory

architecture

cache

micro-ODT),

Chapter

the

memory management

the

called

describes

overview

terms.

the

CHAPTER

ARCHITECTURE

1.1

INTRODUCTION

This chapter
DCJ1ll

Figure

provides

a brief introduction to the architecture

microprocessor.

The

DCJ1l

1-1.

r—

1is

organized

shown

’_oL
XX —JEPS———
'

A AN

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STATE

aR~rv — o

SECUENCE

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DATA CHIP
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ABOAY

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LOGIC

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SHIFTER

$6us328'T

———

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t——

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‘J\: NPT

FHS3IPALT

B et n

ouTruT

EXFCOTION

CONTROL

—

ISH'”

SHIFT
COND'TION

—

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MULIPLEXER

——

m—

FALE 1CONTAING

o—

DATA 7781

——

DAL 21-00

CONTHOL

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e

EXECUTION

PARF

avERayueY

ABDRY

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LOGIC

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ADDRESS

QTER

1DAL

NAE

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T
.

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arp

cnt

I\.;IC:OQ?“?’{

GF'L RATOR

CONTROL

As shown
data

chip

mnn

Figure 1-1

The
all

s;snvrrr

SERVICE

—

1DAL BUS 16 8 °

EVEST e
BN

At
RALT
TS

sam

A BUS
32 BIT

in Figure 1-1,
and

control

—

SR
| R

——

MANALGEMENT
S

CONTROL CHIP

DCJ1l1 Block Diagram

the DCJ11

microprocessor

chip.

consists

data chip
data and

used
path,

for
the

performs all arithmetic and logic functions, handles
address transfers, and generates most of the signals
system timing.
1In addition to the primary execution data

sequencer,

data
and

chip

contains

floating-point

memory
and

management

cache

control

logic,

I/O

registers.

state

The controllchip directs the operation of the data chip with
The major components of the control chip are
microinstructions.
the microprogram control store

and

the

microprogram

sequencing

logic.

A detailed description of the data chip and control chip and the
interface between them is beyond the scope of this book. We will
consider the data chip and control chip as one functional unit and
only those portions of this unit that are
describe
will
architecturally significant to the design engineer.

The remainder of this chapter briefly describes each of the major
components

the

000000

major topics:

DCJ1l

architecture.

The chapter covers six

General-purpose registers
Processor status word

Traps and

interrupts

Floating point processing
Memory system registers
DMA mechanism

1.2

GENERAL-PURPOSE REGISTERS

As shown in Figure 1-2, the DCJ1l has a dual set of Ssix registers
RO through R5 and RO” through R5”, three stack pointers (R6)
corresponding to the three processor modes (see Paragraph 1l.3.1),
and a program counter (R7). RO through RS is also referred to as
register set 0 and RO” through R5° is also called register set 1.
These registers are called general-purpose because’ they can be
used in a variety of ways. General-purpose registers serve as
registers,
autoincrement
registers,
index
accumulators,
autodecrement

registers,

storage of data.

stack

pointers

Arithmetic operations can be

for

performed

temporary

between

between
or
another
and
register
general-purpose
one
general-purpose register and memory or an I/0 device register.

Figure 1-2

KSP

RY’

sSSP

uspP

RJ’

R4’

RS’

PSW

DCJ1l General-Purpose Registers

At any given time, either register set RO through R5 is used or
register set RO0” through R5” is used. The two sets can not be
used

simultaneously.

organized

These

general-purpose

registers

are

two sets to increase the speed of context switching

and some types of real-time data handling.

indicates
common

used

the

last

entry

temporary

the

hardware

areas

the

with

stack

pointer

appropriate
LIFO

stack

1last

(SP),

(the

1in,

which

stacks

first

are

out

characteristics).
There are three stack pointers:
a kernel stack
pointer (KSP), a supervisor stack pointer (SSP), and a user
stack
pointer
(USP).
Each stack pointer is associated with a different

processor

occurs,

the

mode

the

stack

Paragraph

CPU

indicated

1.4

stack-based

(see

current

for

1.3.1).

state

(PC

the

also

PS)

&an

interrupt

information

architecture

When

and

interrupt

trap

interrupts

facilitates

automatically

trap

pushed

vector

and

(see

traps).

The
programming.

reentrant

Register R7 is used as the program counter
- (PC).
The PC
contains
the
address
of
the
next
instruction
to be executed;
thereby
controlling the order of execution of instructions.
The PC
1is
a

general-purpose

the

sense

that

directly

accessible by all single- and double-operand
instructions.
Much
of the power of the DCJ1l instruction set is achieve
d by utilizing
the PC in conjunction with various addressing modes.
The
PC
is
not

normally

1.3
As

used

PROCESSOR

STATUS

accumulator

for

arithmetic

WORD

shown

in Figure 1-3, the processor status
word
condition
codes describing the arithmetic or

the
of

the

last

instruction,

processor

priority,

located

a
(used

instruction

The

is
15

14
]

]

and

trace

for

the

current

physical

bit that
program

}

0
‘r

{

forces a trap at
debugging),
the

(PS)
contains
logical results

processor

17777776.

and

address

]

operations.

)

—

c
"

CURRENT
MODE

CONDITION
CODES

PREVIOUS
MODE

TRACE

BIT

PRIORITY

UNUSED

Figure 1-3
BIT

15:14

NAME

Carrent Mode
(RW, protected)

Processor Status Word
FUNCTION

Current

processor

mode:

Bits
15 14
0

0
l1
1

1
O
1

Mode
Kernel
Supervisor
Illegal
User

11042

the end
current
modes.

13:12

Previous Mode

protected)

Previous processor mode; same
encoding as for bits <15:14>.

General register set select:
register set 0 (RO--RS).
0

The bits are unused and are always
zeroes.

read

Reserved

This

bit

(RW)

DIGITAL

Priority
(RW, protected)

Processor

Trace Trap

(RW, protected)

for

future

interrupt priority level:

NWHE U

COFHMHFHFOOHKMFO®O

reserved

Priority Level
OHORFROKHFOFHWUV,

Bits

is
use.

Unused
(Read only)

CQOOOHKHFHFN

10:9

(RW,

Also called the T-bit.

When set,

the processor traps to location 14

the end of

the current

This bit cannot be
instruction.
set directly by writing data to the
PS. This bit is typically set by the

Trace trap is
RTI/RTT instruction.
disabled when this bit is zero.
3:0

Condition Codes
(RW)

Processor condition codes:
N:

Set if the result of the
previous operation was negative.

Set if the result of the
previous operation was zero.

Set if the previous operation
resulted

in an ar_thmetic

overflow.

Set if the previous operation
resulted in a carry of
significant bit.

its most

1.3.1

Processor Modes - Three processor modes

(user,

supervisor,

and
kernel)
permit
a
fully
protected
environment
for
a
multiprogramming system by providing the
programmer
with three
distinct
sets of processor stacks and memory management
registers
for memory mapping.
In addition, certain PDP-11 instructions
are
privileged
in that their operation is inhibited in supervisor
and
user

modes.

processor

For

will

instructions

and

the

wvector

mode,
the

the

1-1

HALT

and

instruction

address

will

supervisor

RESET

execute

processor

Table

1in

the

virtual

processor

effects

provided

example,

ignore

all

modes

user

(Set

will

cause

kernel

data

various

Influenced

mode,

the

Priority

Level)

trap

through

space.

instructions.

1-1.

Instructions

SPL

kernel
summary
of

instruction

Processor

types

Modes

Instruction
or

Instruction

Type

Operation

Kernel

HALT

WAIT,

RESET,

Executes

SPL

RTI,

RTT,

Can

Mode

Traps

vector

through
at location 4
data space.

Executes

NOP.

alter

Can

PS<7:5>

Stack

Checked

Reference

for

Priority

contained

determine

which

Levels
bits

-‘'The

<7:5>

interrupts

not

alter

Not

checked
overflow.

stack
overflow,

1-2.

in
Supervisor/User

kernel

1.5)

specified

MPTS

Table

Operation

Depends on
halt option
selected
(see
Paragraph

1.3.2

Mode

PS<7:5>

for

stack

priority

the

will

1level
and

processed,

(mask
used

bits)

software

indicated

Table

1-2 Priority Levels

Octal Value
of PS<7:5>

Interrupt Level
Acknowledged

""" 7

None

1.3.3 The Trace/Trap Bit - The trace/trap bit (bit 4) is used for
program debugging, enabling single-step execution of instructions
for

step-by-step monitoring.

1.3.4 Condition Codes - The four condition codes N, Z, V, and C
contain information about the result of the last CPU operation.

These bits are set as described

in Paragraph 1.3.

1-5,
1-4,
1.3.5 Processor Status (PS) Protection - Tables 1-3,
1-6, and 1-7 summarize how the PS is protected under a variety of
conditions. The PS is initialized at power-up (the value to which

1initialized depends on power-up options) and is cleared at
is
it
The RESET instruction does not affect the PS.
console start.

Table

PS
D

1-3

Bit(s)
G

e exp EE

Protection For

User
D

Super

Kernel

Condition
Codes
PS <3:0>

loaded
from
source
-—

Trap Bit

Explicit Accesses

oMt

wwe

un-

<4>

Processor

loaded

Priority

loaded

from

source

loaded
from

source

<7:5>

«<11>

Mode

loaded
from

source

«13:12>

Current

loaded

Mode

from

loaded
from

source

«<15:14>

Table

1-4

PS Protection For Traps and Interrupts

TRAPS

Eettenteed
&

ity

INTERRUPTS

Super

Kernel

loaded

vector

loaded

from

<4>

vecto

from

Processor

loaded

1oaded

loaded

<7:5>

vector

loaded

from

vector

Previous
Mode

copied
from

PS
<15:14>)

PS
<15:14>|

PS
<15:14>

Current
Mode

loaded
from

vector

PS Bit(s)

User

Condition
PS

Codes

<3:0>

Trap Bit
PS

Priority
PS

Select

<11»>

<13:12>

<15:14>

from

vector

from

vector

from

loaded

1-8

Table

1-5

Protection For
________ | -

——

RTI,

RTT

| ———
e
-

RTT

PS Bit (s)

User

Super

Kernel

Condition

loaded
from
stack

loaded

from

loaded
from

stack

Codes
PS <3:0>

Trap
PS

Bit

<4>

Processor

un-

Priority

loaded

changed|

from

<7:5>

stack

ORed
from

stack*

from
stack

Previous
Mode

ORed
from

ORed

loaded

from

stack¥*

stack*

stack

Current

ORed

Mode
PS <15:14>

ORed

loaded

from

stack*

stack

«<1ll>

<13:12>

"ORed

Instructions

from

cannot

stack"

popped

from

clear

these

bits

loaded

means

that

the

stack

PS<15:11>
have

been

when

the

old

(restored),

the

set.

1-9

current

Table 1-6

Bit(s)

Condition
Codes
PS <3:0>

Trap Bit
PS

PS Protection for MTPS Instruction

<4>

Processor

Priority
PS <7:5>
Register
Select
PS «11l>

loaded
from
source

un-

changed
un-

un-—

<15:14>

un-

un-=

un-

changed

Previous
Mode
PS <13:12>
Current
Mode

un-

changed

un-

Table

1-7

Initialization During Power-Up

’I POWER-UP

Bit(s)

Condition
Codes
PS <3:0>

cleared

Trap Bit
PS <4>

cleared

Processor

depends

Priority

on
up

<7:5>

Cleared

Previous
Mode
PS

poweroption

cleared

<13:12>

Current

cleared

Mode
PS <15:14>

i.e.,
kernel
mode

1.4

INTERRUPTS AND TRAPS

This

paragraph

traps

and

and traps.
timing and

provides

a brief overview of DCJ11
interrupts
and
user-visible registers related to interrupts
conditions
are
also
covered.
For
detailed

describes

Abort
bus information,

see Chapter

Interrupts
and
traps
are
requests
temporarily
suspend
the
execution
provide service for
the device
or

interrupt
interrupts

caused

The DCJ1ll

interrupt

or
are

trap.
initiated

conditions

operates

trap

than the DCJ11”s
to
this
is
a
independently of

- Bus

Cycles.

that
cause
the
DCJ1l
the
current program
condition
that
caused

affects

the

levels

Interrupts
differ
from
traps
in
by some external event, while
traps

internal

any

DCJ11l.

the DCJ1l

priority.

1In

its priority

and

the

that
are

general,

is greater

priority as indicated by PS<7:5>.
The
exception
non-maskable
interrupt
or
trap,
which
occurs
the processor priority.
Note
that
non-maskable

interrupts and traps have a priority structure amongst themselves.
t PS and PC are
When an interrupt or trap occurs, the curreninterr
upted program.
the
to
return
a
preserved in order to allow
ed from two
fetch
are
PS
The new contents of the PC and the
of the
first
The
r.
vecto
consecutive memory words called atrap service routinewordstart
ing
or
vector contains the interrupt
ns the new PS.
address (the new PC), and the second word contai
user defined.
are
or
DCJ11l
the
by
ined
predef
Vectors are either
User defined vectors are vectors associated with interrupts
occuring on IRQ<3:0>.
-

1-8.

The predefined vectors are shown
'

Table

specifically, for an interrupt or trap, the following seguence

events

occurs:

PS --> templ

PC --> temp2
0

--> PS<15:14>

M[V] =-->
M[V+2] -->
templ<l5:14> =->
SP-2 -=->
templ -->
Sp-2

-->

PC
PS
PS<13:12>
SP
M[SP]
SP

temp2 --> M[SP]
-

ssave PS, PC in temporary

sscratchpad locations

;force kernel mode

sfetch PC from vector, data space
sfetch PS from vector, data space
;set previous mode
spushed stack selected by new PS
;push old PS on stack, data space

;push old PC on stack, data space
s then execute interrupt service
sroutine

an
After the interrupt or trap service routine has been completed,
ction
instru
Trap)
From
(Return
RTT
or
pt)
RTI (Return From Interru
The top two words of the stack are
is typically executed.
PS,
automatically popped off the stack and placed in the PC andupted
interr
the
of
state
the
ing
restor
y
respectively, thereb
program.,

The DCJ1l also responds to a variety of conditions which can abort
An abort is similar to an interrupt or
the current operation.
to point to a service routine.
used
is
vector
a
trap in that
Aborts differ from traps and interrupts in that the DCJ1ll services
an abort immediately rather than waiting until the end of the
Aborts generated by the DCJ1ll itself
current macroinstruction.
and address errors. Aborts which must
include memory management
be

generated by external logic include bus timeouts, non-existent

memory accesses, and parity aborts.

The signal ABORT is

to indicate the presence of an abort condition.

asserted

associated
DCJ11l interrupts, traps, and aborts (with their
ts and
interrup
For
priorities) are summarized in Table 1-8.
t or
interrup
aborts, the name of the signal which initiates the
ness,
complete
appears in .the last column. For
(if any)
abort
Table 1-8 also lists several instructions that result in traps.
These instructions are mutually exclusive and have no priority
structure.

Table 1-8 Interrupts, Traps,

and Aborts

Interrupt,
Trap,

Description

Red

stack violation
(CPU error register,

bit

(CPU

error

management

Timeout/non-existent
memory

(CPU

Parity

Signal

Abort

250

Abort

ABORT

Interrupt

114

error

bits

<5:4>)

error

Trace

bit)

PARITY,

ABORT
14

stack violation
error register,

Trap

fail

Interrupt

PWRF

Interrupt

244

FPE

Trap

244

Trap

240

Interrupt

IRQ7

Interrupt

100

EVENT

Trap

240

Interrupt

UuD

IRQ6

Trap

240

bit

Yellow

set

Abort

Trap

(PSW,

Power

Priority
Level

Abort

violation (MMRO,
bits <15:13>)

bit

Address

Memory

(CPU

Vector

Address

bit

Abort

(PWRF)

Floating

point
exception (FPA

present)

Floating

point

exception

(no

FPA)

PIR

(PIRQ,

Interrupt

bit

level

15)

EVENT

PIR 6

(PIRQ,

Interrupt
PIR

bit 14)

level

(PIRQ,

bit

6
13)

Interrupt level 5

Interrupt

PIR 4 (PIRQ, bit 12)

Trap

Interrupt level 4

IRQ5

240

Interrupt

IRQ4

PIR 3 (PIRQ, bit 11)

Trap

240

PIR 2 (PIRQ, bit 10)

Trap

240

TRAP Instruction

Trap

-—

.EMT Instruction

Trap

IOT Instruction

Trap

- Illeqgal Instruction

Trap

PIR 1 (PIRQ, bit 9)

240 |

Trap

NM = Non-maskable

UD = User-defined
--

= None

1.5

HALTING DCJ1l OPERATION

A halt operation differs from a interrupt, trap, or abort in that
there is no vector associated with it. It is similar, however, in
the DCJ11.
the sense that it interrupts the usual operation theof DCJll
are to:
of
ion
operat
the
The two main means of halting
ction.
instru
HALT
a
(1) assert the HALT line or (2) execute
The HALT line has a lower priority than any

trap,

interrupt,

However, it has the highest priority during vector reads.
abort.
infinite
This is to allow the user to break out of potential vector
is
a
if
example
for
occur
could
loop
An infinite
loops.
not properly mapped during a memory management operation.

Execution of the HALT instruction performs different operations
depending upon the CPU operating mode and the halt option
currently selected. See Chapter 8 - Interfacing for more details
a trap

on halt options. 1In kernel mode, a halt option of 1 causes
through laecation 4 and sets bit 7 of the CPU e~ror register whenIf the halt option is 0 in kernel mode,
HALT is executed.
execution of the HALT instruction causes the DCJ1l into console
ODT. Execution of the HALT instruction in user or supervisor mode
causes a trap through location 4 and sets bit 7 of the
register.

1-14

CPU

error

1.6

PROGRAM INTERRUPT REQUEST REGISTER

The program

interrupt

request

(PIRQ)

provides

seven

levels
of
software
interrupt
(i.e.,
trap)
capability.
An
interrupt request is queued by setting one of bits
<15:9>,
which

correspond

interrupt

priority

levels

through

(respectively).
Bits <7:5> and <3:1> are set-by the DCJ1ll to
the
encoded
value
of
the highest pending request.
When the program
interrupt request is granted, the processor traps through a
vector
at
wvirtual location
240.
It
is
the
responsibility
of
the
interrupt service routine to clear the approp
riate bit in the PIRQ
before exiting.
The format of the PIRQ is as shown in figure 1-4,
15

PIR7|{PIR6|{PIRS|{PIR4|PIR3|PIR2]|PIR
|N

REQUESTLEVELS——;]

0
[

”

0
| N—

PRIOR!TY ENCODED VALUE OF BITS <15.9>

Figure

1-4

PIRQ Register

MR.9013

Bits <15:9> can be read or written.
Bits
<7:5>
and
<3:1>
are
read-only.
The remaining bits are always read as zeros.
PIRQ is
cleared by a
console
start,
by
a
RESET
instruction,
and
at

power-up

1.7

time.

The

PIRQ

physical

address

17777772.

CPU ERROR REGISTER

The CPU error register
the
source
of a trap
is located at physical

error

resides

assists

the operating system by identifying
location 4.
The CPU error register
17777766.
The format
of
the
CPU

through
address

shown

Figure

ofo]

of|

ofofoo

1-5.

ILLEGAL HALT

ADDRESS ERROR

NON-EXISTENT MEMORY
1/0 BUS TIMEOUT

YELLOW STACK VIOLATION

RED STACK VIOLATION
MR.822¢

Figure

1-5

CPU Error

Bit

Name

Description

<15:8>

Unused

These bits are unused and are always
read

zeros.

ion
Set when execution of a HALT instruct
,
mode
or
rvis
supe
is attempted in user or
is
on
opti
HALT
the
or in kernel mode when
in
ons
opti
r-up
powe
enabled (refer to the

Illegal HALT
(Read only)

Paragraph 8.3.3).

Set when a word access is made to an odd
byte address, or when an instruction
fetch from an internal register is

Address Error
(Read only)

attempted.

Memory

Set when reference is made to a
non-existent memory address.

I/0 Bus
Timeout

Set when reference is made to a
non-existent I/0 page address.

Yellow Stack

Set when a yellow zone stack

Non-Existent
(Read only)

(Read only)

overflow

Trap

trap occurs.

(Read only)

Red Stack Trap
(Read only)

These bits are unused and are always

Unused

<1:0>

The CPU error
itself,

set when a red stack trap occurs.

read

zeros.

to
reference
write
any
by
cleared
is
register
ET
RES
The
start.
ole
cons
a
by
Or
power-up,
a

instruction has no effect on this register.

1.8

STACK PROTECTION

The
ection for the kernel stack.
The DCJ1l provides hardwareks prot
may
but
are
hardw
by
cted
prote
are not

supervisor

and

user

stac

be checked by memory man agement

mode is provided by defining yellow anda
Kernel stack references are checked against

Stack protection in k ernel
red

stack

traps.

fixed 1limit of 400

and appropriate software,

.
(octal)

If the virtual address of a kernel
than 400 (octal), a yellow stack trap

1is
reference
stack
ruction. A stack ¢trap
occurs at the end of the current inst
rence, which is defined as:
only

less

occur on a kernel stack refe

stack, a JSR

instruction

can

any

el
trap or interrupt push on the kern
e 1 mode using addressing Mode 4
kern
in
nce
re fere
kernel mode, oar

The

DCJ1l

with

trap,

push

also

initiates

red
2

and

DCJ1l

kernel
If

stack
0

stack

abort

trap,

trap
2,

the CPU

FLOATING-POINT

The

for

interrupt,

bit

selected

sequences.

locations

setting

1.9

the

checks

abort

during

vector

aborts
is

abort

creating

vectoring

error

during

caused

interrupt,
kernel

sequence,

the

stack

DCJ11

emergency stack

through

1location

at
and

PROCESSING

contains
an

integral

floating-point processor which
can
double-precision floating-point operations.
User-accessible
architecture
associated
with
floating-point
processing
includes:
six
64-bit
floating-point
accumulators
perform

single-

(ACO0--ACS),

floating-point

and

floating-point

exception

floating-point

status

address

(FEA)

exception code (FEC) register.
detail
and
provides
information
floating-point instructions.
these

Memory

SYSTEM

system

memory

cache

and

system

control

The

memory

include
(PDRs),

and

MMR1,

MMR2,

Memory

Management.

1.11
An

external
of

device
a

(DAL<21:00>).
asserting
the
place

high

management
These

detail

(DMA)

microcycle.

microcycle

The

DCJ11l

with

0,
in

acknowledges

performs

the

DMA

Special

management

registers

and

detail

the

(HMR).

(MMRO,

Chapter

MECHANISM

version

asserting

memory

are

descriptor

memory

Chapter

with

DMA

the

control
DCJ1l.

in a high impedance state
impedance
state via external

the

cache

page

described

A device requests
DMR
input to the

current

describes

cache

hit/miss

(PARs),

registers

are

typically

buffered

end

programming

(1)

with
the

associated

DAL«15:00>

and

registers

DIRECT-MEMORY ACCESS

control

for:

associated

registers

MMR3).

used

(CCR)

described

address

memory

are

memory management.

registers

are

system

page

(2)

These registers
Features,

and

REGISTERS

registers

implementation
The

Chapter

1.10* MEMORY

(FPS) ,

of
This

request

DCJ11’s
by

taking

data/address

the
DAL
lines
causes the DCJ11

(DAL<21:16>
buffers) and

responsibility

the

transfer

DCJ1ll”’s

CONT

asserting

by
to

placed
extend the

external

input.
its

bus

MAP

logic

output

See Chapter 3 - Bus Cycleg for the
at the appropriate time.
specific timing involved. This also causes the current microcycle
to extend until CONT is asserted.

A DMA request may be acknowledged and granted for all types of
DMA
microcycles except bus writes and GP writes. The lack of a fgom
grant, however, does not necessarily prevent external logic
performing a DMA transfer during these cycles.

A buffered version

of the DAL for example could be used for a DMA transfer when SCTL
is asserted (the DAL itself would not be used since it carries the

write data during this portion of the cycle).
NOTE

It
is
possible
to
acknowledge
a
DMA
request
between
the
read
and
write
portions
of
a
bus
locked
Read-Modify-Write
cycle
(see
Paragraph
3.2).
If this is not desirable, external
logic
should
be designed to disable DMA
requests at this time.

1-18

CHAPTER
PIN

2.1

INTRODUCTION

This chapter describes
The pins, and thus the

000000000

DESCRIPTIONS

the functions performed by each DCJ11
pin.
chapter, are divided into nine groups:
Data/address lines (DAL<21:00>)
System control lines (BS<1:0>, AIO<3:0>, BUFCTL, CONT,
DV)
Timing signals (ALE, SCTL, STRE, CLK,. CLK2)
Start/stop control (INIT, HALT)
:
Status signals (MISS, PARITY, ABORT, MAP,
PRDC)
Interrupt

and

Test

(TEST1,

pins

Oscillator
Power

pins

DMA control

pins

(XTLI,

(Vcc,

GND)

both

DMR,

pin
assignments
associated with a

(bidirectional).
TEST1
AIO0 0O

PWET
FPE

EVENT

- 4
-2

60 o>
59 les

—»{6

55 jae

—{ 7

DAL 10

54 e

DAL 11

—e! g

53 jen

DAL 12

—{

pon

DAL

IRQ

—{

DAL 14

FARTTY

—s! 14

GND

— 15

Voe

—e

BS §

BS 1

-4 18

47 la
1

46 —

DAL
3
Vee

a5~

oND

DAL
4

Lep

43 len

S
DAL

VAP

- 19

< 20

41 |

DAL 21

BUFCTL

-1 21

40 >

E .

DAL 19

DAL

SCTC

XTALO

AEGRT

DAL 17
DAL 16
T

42 pa—

-1 25
- 26
—a{ 27

XTALI

36 fu—
35 lae

CLK

of
pin

DALG6
DAL
7

HALT

PWRF,

CLK?2

FEDC

- 29

32 ju—

CONT

NOT USED

—30

31—

TEST2
MR 8BBS

Figure

2-1

DCJ1l

FPE,

EVENT)

XTLO)

Figure 2-1 illustrates
the
indicates
whether
a signal

output,

(IRQ<3:0>,

TEST2)

Assignments

the
DCJ11
and
is an input, an

2.2

DATA/ADDRESS LINES (DAL<21:00>)

ss information.
There are 22 pins associated with data and addre
ss (or DAL) lines.
These are usually referred to as the data/addre
groups: the upper
The DAL lines are functionally divided into two outpu
t only and the
data/address lines (DAL<21:16>) which areare bidir
ectional.
lower data/address lines (DAL<15:00>) which

six
(DAL<21:16>) - These
Lines
Data/Address
2.2.1 Upper
6
icant
signif
time-multiplexed output lines constitute the most carri
wvalid
es
DAL<21:16>
ss.
bits of a 22-bit physical addreevery
cycle. Internal status
bus
of
ning
begin
the
at
n
informatio
part of every bus
d
is asserted on these lines during the secon
cycle for manufacturing test purposes only.

(DAL<15:00>) - These
Lines
Data/Address
2.2.2 Lower
t data and address
16-bi
the
time-multiplexed 1I/0 lines constitute
involves an 1I/0
that
cycle
bus. During the first part of a
s, an interrupt

transfer, the DAL 1lines carry a physical addres
(GP) code,
acknowledge priority level, or a general-purpose Chapte
r 3 (see
med
perfor
being
depending upon the type of cycle
Bus
a
During
.
types)
cycle
on
ation
inform
Bus Cycles for more
of a
Read or Bus Write cycle, DAL<15:00> carries the lower 16 bits
DAL<3:0>
physical address. During an Interrupt Acknowledge cycle, During
a
1level.
ledged
acknow
the
of
ty
carries the priori
0>
General-Purpose Read or General-Purpose Write cycle, DAL<7:
carries

the GP code.

r,
During the second part of a cycle that involves an I/0 transfe
,
cycles
read
the DAL 1lines carry 8 or 16 bits of data. During
only
DCJ11
the
If
external logic places data onto the DAL.
ignores
requires a byte of information, it reads a full word but carrie
s
DAL
the
either the upper of lower byte. For write cycles,
s
involve
cycle
the
r
whethe
8 or 16 bits of data, depending upon
the writing of a byte or a word.

2.3

SYSTEM CONTROL LINES,

There are nine pins

associated

AIO<3:0>, BUOFCTL, CONT, and DV.

with

system

control:

BS<1:0>,

time-multiplexed
2.3.1 Bank Select (BS<l:0>») - These
information.
access
cache
and
select
signals transmit bank
BS signals
the
cycle,
Write
Bus
or
Read
Bus
a
beginning of
the

DAL

type

output
At the
define

of device being accessed by the physical address on the

shown

in Table

2-1.

Table
BS1

BSO

2-1

Device

DESCRIPTION

Internal register A memory-addressable register that
within the DCJ1l. Included are the

processor

the
and
are
are

Selection

status

word,

all

MMU

resides

registers,

PIRQ register, the CPU error register
the cache hit/miss register. Excluded
the general-purpose registers, which

not

memory

External

I/O

Any

device
DCJ11l that

addressable.

device

the

address in the upper 8K bytes of the
physical address range (17760000 to
17777777).
Excluded are system regis
(BS

code

0l)

and

internal

11).

ters

registers

(BS

System
A

the

address range 17777740 to 17777750.
Always included as a system register
the DCJ11”s internal cache control
register (CCR).

The CCR

NOTE

implemented

the

only

system

in the DCJ1l. Accesses to
the CCR generate the same BS code as
for

the other system registers mentioned
above. This facilitates the creation
of
"shadow" read-only copies of the CCR on
cache based systems.

Memory
-

reference

to any location in physical
space in the range 00000000 to
177577717.

address

During
cache

the second part of an I/0 cycle, BS1
is
memory
(if present)
is to be bypassed.
cycle, BSO is asserted whenever a cache

the
required.

2.3.2

Address

the
type
typically

Input/Output

of
cycle
latches and

(AIO«<3:0>)

asserted
1In

the
memory

when

the

second

part

force

miss

- The AIO outputs

identify

currently
being
executed.
External logic
decodes these signals.
Table 2-2
specifies
the AIO code associated with each cycle
type.
See Chapter 3 - Bus
Cycles for detailed information on
the various cycle types.

OOHOOOOHKKFK

AIO1l

AIOO
HRHOHOHOHOM

AIO2

oeooowwoowp

AIO3
COOH
I HHKF M

Table 2-2 AIO Decode

CYCLE TYPE

NIO (internal operation only, no I/0)
GP (General-Purpose) read
Interrupt acknowledge, vector read
Instruction-stream request read
Read/Modify/Write - no bus lock
Read/Modify/Write - bus lock
Data-stream read

Instruction-stream demand read

GP word write
Bus byte write
Bus word write

BUFCIL output defines whether
2.3.3 Buffer Control (BUFCTL) - The
L is
receiving data on the DAL. BUFCT
the DCJ11 is driving or logic
data
of
to control the direction
typically used by external
When
l.
data to the DCJ1l
passing through buffers that sendDCJ1l
is not driving data on
the
that
asserted, BUFCTL indicates
(1) during the portion of a read cycle
the DAL. This occurs:
and (2) during the stretched
when data is being driven on the DAL, BUFCT
L is deasserted when the
portion of any nonwrite cycle.
DCJ1l is driving data or an address on the DAL.

input is asserted by external
2.3.4 Continue (ZONT) - The CONT cycle
after it has finished using
logic to _terminate a stretched
the DAL. OONT is so named because it enables the DCJ1l to
continue on to the next cycle.

typically asserted by
2.3.5 Data Valid (DV) - The DV input is DCJ1l
the DAL. When
external logic to latch data into thedata whenfrom
L and SCTL
BUFCT
asserted, DV causes the DCJll to latch
non-write cycles.

that 1is, during stretched
asserted,
are
ensure that DV is not asserted during DMA
must
External logic
gransactions, since this would cause the latching of unpredictable
ata.

2.4

TIMING SIGNALS

There are five pins associated with

ALE, 3CTL, 3TRE, CLK, and CLK2.

timing

and

synchronization:

2.4.1
that
data.

Address Latch Enable

(ALE)

- ATE

when

asserted

indicates

DAL<21:00>,
AIO<3:0>,
BS<1:0>,
and
MAP all contain valid
The leading edge of ALE is typically used by external logic
to latch_addresses, AIO codes, bank select (BS) codes, and the
map
enable (MAP) control signal.

2.4.2
Stretch Control (8CTL) - The SCTL
output,
when
asserted,
identifies the stretched portion of a cycle.
During write cycles,
the leading or trailing edge of SCTL
can
be
used
for
latching
data.
During
read cycles, the trailing edge of SCTL can be used
for latching data.
5CTL
can
also
be
used
to
determine
when

externally

generated

aborts

may

occur.

2.4.3
Strobe (STRB) - The assertion of the STRB output occurs one
clock
period after the assertion of ALE.
The deassertion of STRB
identifies the end of one microcycle and the beginning of another.

STRE

system

is a general-purpose strobe signal and is typically used for
bus

control.

2.4.4
Clock
1
diagnostic
wuse
state

the
to

the

DCJ11”s

frequency
the

XTALI

internal
state.

.7Vcc,

2.4.5

Clock
Like

the

and

is
wusually
a
clock
wused as an output, CLK

internal

clock.

The

crystal

oscillator

pins.

disabled
CLK

tyr

(CLK2)

CLK,

CLK
When

external

case,

tyg =

XTALO

this

CLK.

clock
1In

(CLK)
only.

can

TESTZ2

and CLK

serve

ns)

driven

reflects

the

reflects

CLK

circuit

asserted,

placed

the

equals

the

DCJ1ll’s

high-impedance

MOS

input

external

clock.

the

frequency

has

state

clock

for
the

connected

- The CLK2 output

CLK2

frequency

output

(Vrr,

same

the DCJ1l”s

.3Vcc,

internal

and is disabled by the assertion of TEST2.
Unlike CLK, CLK2
is
typically
used as a system clock or master clock for external
logic.
CLK and CLK2 have minimal skew when loaded equally.

2.5

START/STOP CONTROL

There are
operation

2.5.1

two

pins
associated
with
starting
the DCJ1l:
INIT and HALT.

1Initialize

initializes

(INIT)

(resets)

procedure.

The

Paragraph

8.3.2.

the

power-up

- The

DCJ1l

INIT
by

sequence

input,

forcing
1is

and

stopping

when

through

described

the

asserted,

a power-up
detail

es the
input, when asserted, forc
2,5,2 Halt (HALT) - The HALT
HALT is
.
(i.e., initiates console ODT)
DCJ11 into console mode
vector
ng
rrupt except duri
the lowest priority nonmaskable inte
est
high
the
or read cycles, HALT becomesesca
read cycles. During vect
fgom
pe
rrupt. This alloltws from programming
priority non-maskableloopinte
which could resu
ing
potential infinite
the CPU
, HALT is unaffected byture
able
mask
errors. Since it is non- 7:5>. See
.fgr a
itec
ter 1 - Arch
priority specified by pPS<interrupts Chap
es.
riti
prio
tive
and their rela
list of the non-maskable
ODT.
See Chapter 5 - Special Features for a description of console
2.6

STATUS SIGNALS

There are five pins associated with
WMTZT, PARITY, ABORT, MAP, and PRDC.

indicating

DCJ1ll

status:

is generated by external
2.6.1 Cache Miss (MISS) - The MISS inputoratin
g cache memory. The
incorp
s
logic in DCJ1ll based system
the current memory
that
tes
indica
lly
assertion of MISS typica
If MISS is asserted
miss.
memory
cache
a
in
reference resulted
is stretched.

during the first part of a bus read cycle, the cycle

of the PARITY. input
2.6.2 Parity Error (PARITY) - The assertion error.
PARITY is used

indicates the occurrence of a memory parity
If PARITY 1is
to generate parity aborts and parity interraupts.
parity error abort is
asserted and ABORT is also asserted, then
ed
generated. The DCJ1l immediately traps through a vector 1locat
tion.
at virtual address 114 without completing the current instrucparity
1f PARITY is asserted but ABORT is not asserted, thenthe a current
At the end of
interrupt 1is generated.
error
through the vector located
ed
servic
is
rupt
inter
instruction, the
at virtual address 114. Note that PARITY is sampled only during
the stretched portion of a cycle.

or an output of
2.6.3 Abort (ABORT) - ABGRT can serve as an input
open-collector
an
in
ured
ABORT is typically config
the DCJ1ll.
l logic
externa
either
by
driver circuit such that aborts generated
OR
wired
a
(i.e.,
ed
assert
or the DCJ1l can cause ABORT to be
Note that the DCJ1l1 pulls ABORT high internally.
The DCJ1l asserts ABORT during the first part of an I/0 cycle if a
arrangement).

memory

management

error

address error occurs,

For a memory

located at
management error, the DCJ1ll traps
s error,
addres
an
For
space.
data
virtual address 250 in kernel
4 1in
address
virtual
at
located
vector
a
the DCJ1l traps through
CPU
the
in
bit
riate
approp
the
sets
DCJ1ll
The
kernel data space.
error

through

vector

such
ABORT can also be asserted by external logic in the event of parity
nce,
refere
conditions as a bus timeout, non-existent memory
2-6

error, etc.
External logic must ensure that:
(1)
the
cycle
is
stretched
and that AB
is asserted during the stretched portion

(i.e.,

when SCTL

asserted)

a__non-1/0
cycle.
If
T by external logic
virtual
address
4
in
specifies

the

cause

asserted,

the

located

virtual

2.6.4

DCJ1l

Map Enable

and

the

KBORT is not asserted during

abort.

immediately

address

(MAP)

(2)

PARITY
is not asserted, the assertion of
causes a trap through a vector located
at
kernel data space.
The CPU error register

114

- MAP

PARITY

performs

virtual

trap

address

and

are

through

vector

output.

The

space.

is a time-multiplexed

assertion
of
MAP during the first part of a cycle indicates that
the I/0 map has been enabled (the I1/0 map is
enabled
by
setting
bit
5 of MMR3 to 1).
The assertion of MAP during the second part
of a cycle acknowledges the assertion of the DMR
input.
.
The

NOTE
I/0 map, if needed, is implemented
circuitry external to the DCJ11l.

2.6.5
Predecode
(PRDC) - The
PRDC
output,
when
indicates
that the contents of the prefetch buffer
(PB)
decoded as the
next
macroinstruction.
"This
implies
contents

the

prefetch pipeline, the
5 - Special Features.

2.7

valid.

of
-

The

which

part

explained

control

the

DCJ11l

Chapter

INTERRUPT AND DMA CONTROL

There

are

interrupts

EVENT.

2,7.1

are

operation

asserted,
are being
that
the

eight

and

1Interrupt

pins

DMA

associated

transfers:

Request

with

the

IRQ<3:0>,

(IRQ<3:0>)

DOMR,

IRQ<3:0>

BPWRF,

are

program

FPE,

four

and

input

lines
that
correspond
to
four
different
levels
of
external
interrupt requests.
Interrupt
requests
at
any
of
these
four
levels
can
be
masked
by PS<7:5>.
1In order to be serviced, the

requesting device must have an inter
rupt priority higher than
priority indicated by PS<7:5>.
Interrupt requests on IRQ<3:0>
blocked or allowed as summarized in Table
2-3:

2=-7

the
are

Table 2-3 Interrrupt Requests on IRQ<3:0>
CPU

Priority
Level

PS<7:5>
111
110
101
100
Oxx

Blocked
Allowed
Allowed
Allowed
Allowed

6
5
4

3-0

IRQO

IRQ1

IRQ2

IRQ3

Blocked
Blocked
Blocked
Allowed
Allowed

Blocked
Blocked
Allowed
Allowed
Allowed

Blocked
Blocked
Blocked
Blocked
Allowed

x = Irrelevant

is associated with a
From Table 2-3, it is seen that each IRQ line
in Table 2-4.
different interrupt level, as summarized

Table 2-4 IRQ<3:0> Interrupt Request Levels
Interrupt

Request Level
U

IRQ Line
IRQ3

IRQ2
IRQ1
IRQO

2.7.2

Direct Memory Access Request ( PMR) - The DMR input

device wants
DCJ11 when asserted typically means that an external DCJ1l1l at
the
by
led
samp
is
to perform a DMA transaction.
a write
start

of
operation,

all

state, and

(3)

cycle

the

cycles.

does not involve

the DCJ1l responds to the assertion of DMR by: ance
the high- imped
stretching the cycle, (2) placing DAL<15:00> in
second

the

during

asserting
by
request
involves
cycle
the
If
cycle.
the

acknowledging the
part

write operation, the cycle is

DMA

stretched

but

DAL<15:00>

placed in the high-impedance state and MAP is not asserted.

2.7.3

Power Pail (PWRF) ~ PWRF

interrupt

input

vector located
External

logic

nonmaskable
high-priority
through a
trap
a
es
forc
asserted,

that, when
virtual address

kernel

occurrence
typically asserts PWRF to indicate the

The trap vector points to an
user-defined power fail service routine.

of an AC power failure.

2.7.4

Ploating-Point Exception

(FPE) - FPE

that,
input
interrupt
nonmaskable
ess
through a vect or located at virtual addr
space,

indicate
vector

FPE

would

244

when asserted,

appropriate

high-priority

forces a trap
kernel

data

be asserted by an external FPA coprocessor to

the occurrence o £
point to an
would

exception service routine.

a floating-point exception.
appropriate user- defined floating-point

2-8

2.7.5

BEvent

level
6
than 6).
performs

(EVENT)

- The EVENT

input

maskable

priority

interrupt
(i.e.,
it is acknowledged if PS<7:5> is less
When EVENT is
asserted
(and
not
masked),
the
DCJ11
a trap through a vector located at virtu
al address 100 in

kernel data space,

line

time clock

2.8

TEST PINS

E%ENT is typically used by external logic as a

(LTC)

There are two pins
These
signals
connection with

interrupt

associated

input.

with

testing,

disable
DCJ11
functions
board-level testing.

and

TESTI
are

and
are

TESTZ.
used

2.8.1
Test 1 (TESTL) - The TEZTI input (when assert
ed by external
logic)
disables
all
DCJ1l1
outputs
by
placing
them
in
the
high-impedance state.
This permits external logic to
operate
on
the

data

and

interference

2.8.2

Test 2

control

from

1lines

connected

the DCJ11.

(TE3T2)

the

DCJ1l”s

2.9

OSCILLATOR PINS

internal

- The TEST?

input,

when

the

DCJ1l1

asserted,

without

disables

clock.
The CLK and CLK? pins are placed in
the high-impedance state.
Board level
in-circuit
testing
logic
can
be
designed
such
that
when TEST? is asserted, an external
clock drives the DCJ1l clock circuitry
through the CLK pin.

(XTALI,

XTALO)

The

XTALI and XTALO pins are used to connect
an
external
circuit to the DCJ1l.
The recommended crystal circuit is
Figure 2-2.

crystal
shown in

68pF

)}*

XTAL!

crysTaL T

J_____é}
»

XTALO

68pF
MR 9379

Figure

2.10

2-2

Typical

XTALI

and

XTALO Generation

POWER PINS

There are four pins associated
and two for ground (GND).

with

power:

two

for

+5VDC

(Vce)

called Vcc, which
e are two pins, both+5VD
2.10.1 Power (Vcc) t- Ther
C is supplied by
l.
C to the DCJ1
are used to inpu +5VD
within = 5%.
to
ed
tain
is typically main
external circuitry and

ence
GND pins provide a ground refer
2.10.2' Ground (GND) - The two
d
groun
the
to
cted
conne
are
pins
for the DCJ1l. Typically, these
reference of external logic.

2.11

PIN DESCRIPTION SUMMARY

PIN NO. PIN NAME

INPUT
OR

DEFINITION

OUTPUT

TEST1

Test 1

Input

2-5

AIO<3:0>

Address

Output

Input/Output

FUNCTION

Disables all DCJ1ll

outputs.

1Indicate the type of

cycle currently béing
executed
read,

(e.g.,

GP write,

bus

IACK,

etc.)

PWRF

Power Fail

Input

A high-priority nonmaskable interrupt
that forces a trap

through vector
location 24.
Indicates an AC power
failure.

FPE

Floating-Point

Exception

Input

A high-priority nonmaskable interrupt

that forces a trap
through vector

location

244,

Typically generated
by a floating-point
coprocessor

indicate an exception

condition,

EVENT

Event

Input

A maskable interrupt
that forces a trap
through vector
location 100.
Typically used as a
line time clock.

HALT

Halt

Input

low-priority

maskable
that

forces the
into console

DCJ1l
OoDT.

10-13

IRQ<3:0>

Interrupt
Request

Input

Four

non-

interrupt

maskable

interrupt
lines.

requecst

PARITY

Parity Error

Input

Indicates a memory
parity error.

GND

Ground

Input

Ground

reference.

Vece

Power

Input

power

17-18

BS<1:0>

Bank

Output

Multiplexed.
Either
define the type of
physical address on
the DAL or indicate
if a cache memory
bypass or force miss
should occur.

Output

Multiplexed,

Map

Select

Enable

VDC

input.

indicates that
the I/0 map is
enabled

request has
granted.

I1/0

Abort

either

DMA
been

Indicates

the

occurrence

abort

condition,

i.e.;

a memory

management

error,

timeout,

bus

address

non-existent memory,
or parity error.

21-26

DAL<21:16> Data/Address
Lines

Output

Most significant six
bits of the time
multiplexed data and

address

DMR

Direct Memor Yy
Access

Reque st

Input

Forces

bus,.

the

cycle to be
and causes
asserted

second

cycle,

current

extended

during

part

the

MISS

Caéhe Miss

Input

the

Indicates whether

current memory

reference resulted in
a cache hit or miss.

PRDC

Not Used

TEST2

Predecode

Test

Output

Indicates when the
contents of the
prefetch buffer are
being decoded as the
next macroinstruction.

Input

Disables the clock
outputs. Permits
external logic to

drive the DCJ1ll”s
internal

clock

circuitry through the

CLK pin.
32

CONT

Continue

Input

Terminates

INIT

Initialize

Input

Initializes or resets
the system by forcing
it through a power-up
procedure.

CLK?2

Clock

Output

Clock output with the
same frequency as CLK.

stretched

cycle.

Typically used
system clock.
35

CLK

Clock

Output

Clock output
diagnostic

for

use

only.

XTALI

Crystal

Input

Oscillator

input

XTALO

Crystal

Output

Oscillator
line.

output

SCTL

Stretch
Control

Output

Indicates
is

g g

that a cycle
stretched.

The edges can be
to

being

line.

strobe

used

data.

Strobe

Output

General-purpose
strobe.

Address Latch

Output

Typically used to
latch addresses, AIO
codes, and the map

Enable

enable

and

signals.

control

BUFCTL

Buffer Control

Output

Indicates the
direction of data on
the DAL. Asserted when
the DCJ1l is not
driving the DAL.

Data Valiad

Input

Causes the DCJ1ll to
to latch data from the
DAL.

DAL<15:00>

47-60

Data/Address
Lines

I/0

Lower 16 bits of the
time multiplexed
data and address bus.,

Ground

Input

Ground

reference.

Power

Input

+5 VDC

power

Vecce

input.

CHAPTER 3
BUS CYCLES

3.1

INTRODUCTION

This chapter describes the various types of DCJ1l bus
cycles.
A
bus
cycle
1is
a sequence of events which defines the activity on
the DCJ11”°s I/0 bus.
Bus cycles are also sometimes referred to as
"microcycles",
since
each
bus
cycle
1is
associated
with
the
execution of one
microinstruction.
The
execution
of
a
DCJ1ll

macroinstruction such as ADD, JMP, etc., can involve the execution
of several bus cycles.
The type
of
bus
cycle
that
the
DCJ11
performs
to

depends

complete

Sometimes
no

bus

non-I/0

the

upon

the DCJ1l

cycle.

this

bus

activity

bus

cycles

fall

into

internal
1is

Non-I/0

Bus

Bus Write

General-Purpose

General-Purpose Write

.Interrupt Acknowledge

The

deassertion

six

(if

any)

required

which

requires

microinstruction.

the

cycle

operation
case,

broad

the DCJ11l

(described

3.4)
is the only type of bus cycle
transfer of information over the DCJ11”s

DCJ11l

end)

An NIO bus

Paragraph

the

type

performs

activity.

(NIO)

the

execution

that

I/0

in
does

executes

detail
not

involve

bus.

categories:

Read

bus

Read

the

signal

cycle.

ALE

STRB

marks

(asserted

deasserted) can be used by external logic
information
on
AIO<3:0>
specifies
the
performed according to Table 3-1:

the

beginning

shortly

after

(and

the

&8TRB

to latch AIO<3:0>.
type of bus cycle

The
being

Table 3-1 AIO Codes for Bus Cycles

AIO<3:0>
1111

Description

Bus Cycle Type

Non-1/0 operation

Non-1/0

GP read
Interrupt acknowledge/

1110
1101

read

vector

1100

Instruction stream

Bus Read

Read-Modify-Write,

Bus Read*

request

1011

bus

read

lock

Read-Modify-Write,

Bus Read¥*

1001
1000

Data stream read
Instruction stream

Bus Read
Bus Read

GP word write
Bus byte write

General-Purpose Write
Bus Write

bus

lock

read

demand

0001

Bus word write

* Note that the AIO codes for

identified as Bus Read cycles.
the cycle

cycle
a

1010

0101
0011

General-Purpose Read
Interrupt Acknowledge

(i.e.,

Bus Write

read-modify-write cycles are

This refers to the first part

the "read" part). The second part of

the "write" part)

different AIO code.

the

will be a Bus Write cycle with

DURATION OF BUS CYCLES

3.2

The length of a bus cycle is usually
expressed
as
a
number
of
periods
of
the
DCJ11l”s master clock (CLK).
All bus cycles last

for a minimum of four
<clock
periods.
However,
cycles
may
be
extended
or
"stretched" beyond this minimum by an internal event
or by external logic.
When a cycle is
stretched,
it
1is
always
stretched for a minimum of four additional clock periods.
A cycle
can continue to be stretched in increments of two periods and
can
remain
stretched indefinitely.
Stretched cycles are ended by the
assertion of the signal CONT.
CONT is sampled by the DCJ1l1l on the

first

falling

edge of T4.

edge

T4 and on every other succeeding falling

A bus cycle will be stretched unless either of
|
groups of conditions exists:

the

following

two

A Bus Read cycle is executed and BS<1l:0> = 00
throughout
the
involves a memory read and does not
<cycle
the
(i.e.,
cycle

involve a cache bypass or force miss) and DMR and MISS are not

asserted
during
the
cycle
(no
DMA
grant
or cache miss).
Furthermore, ABORT must not be asserted if the cycle
involves
an

instruction

A Non-1/0 cycle
cycle.

stream demand

read.

is executed and DMR is not asserted during

the

Timing diagrams for both stretched and
provided in the paragraphs that follow.

3.3

non-stretched

cycles

are

Bus Cycle Parts

Reference

is sometimes made to the "first"
(or "early")
part
and
the
"second" (or "later") part of a bus cycle.
The first part of
a bus cycle is defined as the duration
of
the
first
¢two
clock
periods, shown as T0O and Tl in the bus cycle timing
diagrams.
The
second

part

bus

cycle

defined

the

duration

the

remaining
clock
periods in the cycle.
A non-stretched cycle has
only two clock periods in its second part.
These are shown as
T2
and T3 in the bus cycle timing diagrams.
A stretched cycle has at
least six clock periods in its second part.
These are shown as T2
through T7 in the bus cycle timing diagrams.
Note that if a cycle
is stretched for more than six clock periods
in its
second
part,
T4 is repeated in pairs.

3.4

NON-I/O

(NIO)

CYCLE

When the DCJ11
executes
a
microinstruction
which
involves
no
interaction
with
external
logic
(i.e.,
requires
no
I/0
bus
activity), it performs a Non-I/0 (or
NIO)
«cycle.
Non-stretched
and
stretched
Non-I/0
cycles are illustrated in Figures 3-1 and
3-2, respectively.
|

cLk F\j‘\_/&\_,’?—’\_f‘z‘\_/fi\_)—pi,—\_
D)D)

Alo

TTIAN

)Y
(C

T o
MR-11484

Figure

3-1

Non-Stretched Non-I/0 Cycle

3-3

174

)

. T4

—@C

]

A10

JI - ~ococe

)

22"&55%,//

suFCTT
.

TONT

‘ '

CONTINUE

‘

MHA 11456

Figure 3-2

Stretched Non-I/O Cycle

The deassertion of STRB marks the beginning of the cycle, which_is

assertion
the
by
afterwards
shortly
followed
typically latches the AIO
code
which
identifies

non-I1/0.

The

ALE
ALE.
of
the
cycle
as

DAL, BS<l:0>, MAP, and ABORT outputs are undefined

and should be ignored by external logic.
assert ABORT
during
an NIO
cycle.
request (DMR) is granted, the cycle
1is

BUFCTL are asserted.

not
External logic must
If a direct memory
access
stretched
and
L
and

As shown in Figure 3-1, a non-stretched NIO cycle
1is
four
clock
a DMA request is received during the
If
duration.
in
periods
first part of

clock

periods

the cycle

is stretched to

eight

(note the assertion of DMR during the first part of

in Figure 3-2).

Otherwise,

the cycle does not

stretch.

If the NIO cycle is stretched, BUFCTL and SCTL are asserted during

the stretched part of the cycle.
The time-multiplexed signal
MAP
asserted
during
the second part of the stretched cycle indicates
the granting of the
DMA
request.
The
cycle
continues
to
be
stretched
in
increments
of two clock periods (T4) until CONT is
asserted.

3.5

BUS

READ CYCLE

The different types of bus read cycles which the DCJ11l can perform
include instruction-stream request or demand reads, data-stream
reads, and the read portion of a read/modify/write cycle. The AIO
code defines which -of these is selected. The types of devices
from which information can be read include memory, I/O devices,
and explicitly addressable registers. During the first part of
All read
the cycle, BS<1l:0> defines which of these is selected.
needs
DCJ1l
the
If
involve the reading of a full word.
cycles
only a byte,

it reads a word and ignores the unused byte.
3-4

Note

the

request

distinction
read

occurs

between
when

request

the

DCJ1l

reads

and

demand

prefetching

reads.

information.

1If

illustrated

an abort occurs at this time, it does not
affect
macroinstruction
flow
(i.e.,
aborts
are
ignored).
All other types of reads are
demand reads, during which aborts are recogn
ized and serviced
via
the service vectors shown in Table 1-8.

Non--stretched and stretched Bus Read
Figure

3-3

and

3-4,

cycles

respectively.

cLk /

'_-\_./

DAL

are

L‘_-\_&; oH

SUBSYSTEM

)

Db HEK

PHYSICAL ADDRESS

| DAL

W omA

DMR

REQUEST

DAL

\W\I/O BANK SELECT

)))((}(

Figure
i

3-3

CACHE HIT

‘10

Q&%

Bus

MA-8910

Read Cycle

'Ta

/
PHYSICAL ADDRESS
—

DAL

géc\;«EESSussvsrw

are

_
.
CACHE STATUS /7))

Non-Stretched

omagranT \\\

MMU ABORT STATUS

BUFCTL

CLK

8[|

1/0 MAP ENABLE

DMA REQUESTI

DAL

DMA REQUEST-

1000y

DRIVES DAL -

—

S
‘

TN owacrant

W{( cacHE sTaTUS
.

W({

;

.
.

y//

ICACHE MISS

MMU ABORT STATUS

:
AN

MMU AND SYSTEM AB‘ORE STATUS

’

clommue

|
C

CACHE HIT

MISS

AEORT

—

1/0 BANK SELECT—

SvsTEM llNTERFACE

1/0 MAP ENABLE

,
i

fl//l

|
MH

Figure

3-4

Stretched Bus

Read Cycle

ALE can be used to latch the AIO code, the physical address on the
data/address 1lines (DAL), the Bank Select (BS) information, and
(MAP)

1/0 Map Enable

information.

conditions

following

A Bus Read cycle will stretch if any of the

exist:

BS<1l:0> does not equal 00 during the first part of

the

cycle

BS<1l:0> does not equal 00 during the second part of the

cycle

MAP is asserted during the second part of

(anything other than a memory reference)

(a cache memory force miss or a cache bypass)

DMA

cycle

the

grant)

cache

instruction

stream

MISS is asserted during the second part of the cycle

miss)

ABORT is asserted by the DCJ1ll during

demand read, data stream read, or read-modify-write cycle

Otherwise, a Bus Read cycle will execute in four clock periods.
synchronously

For non-stretched Bus Read cycles, the read data is

latched

Figure

into the DCJ1l only on the rising edge of T3, as shown in

3-3.

For stretched Bus Read cycles, data is latched into the DCJ1ll both
and when DV is asserted during the
edge of T3
rising
the
at
read
if
Thus
3-4).
(see Figure
cycle
the
of
stretched portion
time
that
at
latched
is
it
T3,
of
edge
rising
the
at
valid
data is
the
at
not wvalid
1is
1If the read data
and DV is not required.
of T3, DV is required to latch the valid data.
edge
rising
that DV should be inhibited if the stretched Bus Read is due
to

a DMA

grant,.

A stretched cycle lasts at least eight clock periods.
stretched
the

in increments of two clock periods

assertion

Note
only

(T4)

A cycle

Iis

and is ended by

CONT.

internally generated abort condition

such as an MMU error or

she DCJ1l asserts ABORT during the first
exists,
error
address
If this type of abort occurs, the DAL, BS, and
part of the cycle.

MAP
information should be ignored for the remainder of the cycle.
timeout,
bus
as
(such
generated
externally
is
abort
an
If

non-existent
stretched

3.6

memory

portion of

reference,

etc.),

it must occur during the

the cycle.

BUS WRITE CYCLE

Bus Word Write
There are two different types of bus write cycles:
cycles and Bus Byte Write cycles. The AIO code defines which of
The types of devices to which information can
these is selected.
and bus addressable
I/0 devices,
include memory,
be written

registers.

During the first part of the
3-6

c¢ycle,

BS<1l:0>

defines

which of

these is selected.

Bus Write cycle timing is illustrated in Figure
Bus Write cycles are always stretched cycles.
LTO

oaL

e ——{{{{(0

ATE

it2

|13

)

Jll/,omaA GRANT

()

ABORT

MMU ABORT STATUS

BUFCTL

—1/0 BANK SELECT

;

:
|

;

MMU AND SYSTEM ABORT\STATUS
-

;

CONTINUE

‘

that

;

1 Te

iTs

Note

‘T4

‘

L (/0 MAP ENABLE |

|T4

DDXCUOXEAXA((( Daraout

LPHYSICAL ADDRESS

|74

3-5.

|
MR APL2

Figure

3-5

Bus Write Cycle

ALE typically latches the AIO code, the physical memory address on
the DAL,

SCTL

the BS

information,

asserted

during

the

and

the I/O map enable

stretched

portion of

signal

the

(MAP).

cycle.

The

write
data
is
valid
when
38CTL is asserted and the leading and
trailing
edges of S5CTL can be used by external logic to latch this

data. gUFCTL is not asserted during Bus Write cycles.
If

an MMU error

address

error

ABORT
during
the
first part of
aborts must cause
ABORT
to
be
portion of

abort

occurs,

the

DCJ1ll

asserts

the cycle.
Externally generated
asserted
during
the
stretched

the cycle.
NOTE
If an abort occurs during the first
of
the
<cycle,
the
DAL,
BS,
and
information should
be
ignored
for

remainder

the

During Bus Byte Write cycles,

part
MAP
the

cycle.

all

16 bits of DAL<15:0>

If
the
address is even, the correct data
the address is odd, the correct data is on
data on the unused byte is unspecified.

is on
the

are driven.

the low byte.
high
byte.

1If
The

Since a Bus Write cycle is always stretched, CONT must be asserted
to

end

the

cycle.

‘

3-7

(GP)

GENERAL-PURPOSE

3,7

READ CYCLE

General-purpose read cycles allow the DCJ1l to read data from
non-PDP-11
addressable
external
logic.
A general-purpose read

cycle involves the driving of an address on DAL<7:0>
(called
the
general-purpose
or
GP code) which external logic must decode and
respond to.
General-purpose read cycles involve the reading of
a

If the DCJ1l requires only a byte, it reads a word and

full word.

ignores the unneeded byte.
is

shown

in Figure

Timing for General-Purpose Read cycles

3-6.

/_\_f_\_f_\m/_\_f_\_f_\_f—\_f_\_f_\_/_\_/—\_/_\_j—\_J_\

cLK

on. | ———C G cooe I)——TD
e

—

AN/

‘

typically

(which

DAL<7:0>

used

the

DAL<21:8>

should

summarized

Table

the

first

Table

3-2

{

latch

the

source

part

ignored.

the

read

General-Purpose

Reads FPA

data

(if FPA

data)

and

driven

this

read

the

stretched
The
GP

onto

time,

codes

are

the

exists).
HALT

and

address,
and clears FPA”s

rPS.

Note

code

Read Codes

Reads the power-up mode,
option, FPA option, POK,

003

]

is always
periods.

The general-purpose

Reads the power-up mode, HALT
option, FPA option, POK, and
boot address.
See Chapter 8
- Interfacing for further
details.

boot

EQ&_4__

]

3-2.

000

002

/.
;
!

]

cycle.

Function

—

CONTINUE

AIO

Code

001

code
on
the DAL,
A GP Read
lasts a minimum of eight clock

specifies

during

;

General-Purpose Read Cycle

Figure 3-6
general-purpose
and thus always

code

]

SCTT

SUFCTT

ALE

!T6

Acknowledges FPE and reads FEC
(floating exception code)
register (if FPA exists).

that

Read

data

latched

into

3-8

the

DCJ1l

both

rising

edge

1latch

and when DV is

asserted during

the stretched

portion of the cycle (see Figure 3-6).
Thus if the data is
wvalid
at the rising edge of T3, it is latched at that time and DV is not
required.
If the data is not valid at the rising edge of
T3,
DV

required

stretched,

must

the valid data.

ended

by the

Since a GP Read cycle

assertion

NOTE
General-Purpose Read cycles
aborted
by
the DCJ11l and
aborted by external logic.

3.8

GENERAL-PURPOSE

the

driving

external

code)

cycles

logic.

address

which

allow
A

CLK

‘7O

on DAL<7:0>

external

the

‘T2

DCJ1l

logic

(called

must

' T4

| T4

|74

the

BUFCTL

write

data

cycle

involves

general-purpose

and

respond

|TS

]

——
i

to.

of
either
a
word
or
a
byte.
cycles is shown in Figure 3-7.

——{T oF oot TR
o2 oot

ATt

not

Write

decode

M/—\J—\_/—\_ .

not

should

General-Purpose

write cycles involve the writing
Timing for General-Purpose Write
‘

can

CONT.

(GP) WRITE CYCLE

General-Purpose Write
non-PDP~-11

{

]

—

CONT

Figure

ALE

typically

general-purpose

and
code

used

always lasts
(which specifies

onto DAL<7:0>

during

General-Purpose Write Cycle

code

thus

3-7

;

latch
DAL.

the
A

AIO

«code

and

always

stretched

periods.
write data)

The
GP
is driven

Write

of eight
destination of

clock

minimum

the
the

to
the

first

DAL<21:8>
should be ignored.
GP Write codes.
See Chapter 8

part

the

8819

cycle.

this

the

time,

Table 3-3 provides a summary of the
- Interfacing for further details.

3-9

Table 3-3 General-Purpose Write Codes
Code

Function

003
014
034

Writes FPA 16-bit data
Asserts bus reset signal
Indicates exit from console ODT

100
140
214

Acknowledges assertion of EVENT
Acknowledges Power Fail
Negates bus reset signal

Reserved for future use

040

220
224
230
234

Microdiagnostic
Microdiagnostic
Microdiagnostic
Indicates entry

test 1 passed
test 2 passed
test 3 passed
into console ODT

SCTL is asserted during the stretched portion of the GP Write
cycle. The write data is valid (and can be latched) on the rising
The write data 1is driven onto
or falling edges of 8CTL.
Since a GP Write cycle is always stretched, it must
DAL<15:00>.
be ended by the assertion of CONT.
NOTE

General-Purpose Write cycles can not be
the DCJ11 and should not be
aborted by
aborted by external logic.

3.9

INTERRUPT ACRNOWLEDGE BUS CYCLE

An Interrupt Acknowledge cycle

Interrupt

(also called

Vector

1is performed to service an interrupt request from
Read cycle)
Acknowledge timing is illustrated in Figure
Interrupt
IR0<3:0>.
Note that the ' interrupt request on IRQ<3:0> must be
3-8.
the cycle.

deasserted by the end of

SYSTEMINTERFACE
DAL

DRIVESDAL

INTERRUPTLEVEL

//[[/

:
!

sUFCTL

;

SCTT

;
|

!
|

.
AL

.
|
L
L
\\\ SYSTEM ABORT STATUS

W7 W

CONT

E
'

|
~

L
;
!

i
)

CONTINUE

I
i

bv
MR 8913

Figure 3-8

1Interrupt Acknowledge Cycle

3-10

ALE is typically used by external logic to latch the AIO code

the
acknowledged
interrupt
level.
acknowledged is driven onto DAL<3:0> at
as

shown

the

table

Table

below.

3-4

Interrupt Acknowledgement

DAL<3:0>
0001

this

and

The
interrupt
level
the beginning of the cycle

IRQ

level

acknowledged
4
'

0010
0100

5
6

1000

time DAL<21:4>=0.

As shown in Figure 3-8, the interrupt vector -address is placed
the
DAL
by the interrupting device during the second part of
cycle.
An Interrupt Acknowledge cycle
1is
always
stretched

consists

1least

asserted,

which

time

increments of

eight

two clock periods
the

«clock periods.

(T4)

cycle

until

the

on
the
and

stretched

CONT

input

|is

ended.

Note that the interrupt vector is latched into the DCJ1l
both
at
the rising edge of T3 and when DV is asserted during the stretched
portion of the cycle.
Thus if the interrupt vector
1is
valid
at
the
rising
edge
of T3, it is latched at that time and DV is not
required.
If the interrupt vector is not valid at the rising edge
of

T3,

latch

it.

Interrupt.Acknowledge

cycle

can

portion

required

the cycle

if ABORT

aborted

DCJ11l does not assert ABORT during the first
Acknowledge
«cycle.
If
an
abort
occurs,
interrupt request and continues execution.

3.10

during

the

asserted by external

stretched

logic.

The

part of an
Interrupt
the DCJ1ll ignores the
'

DMA REQUESTS AND GRANTS

If external
(1)
cause

logic needs to use the DAL to transfer data, it
the
DCJ1l to put the DAL in the high-impedance

must:
state,
and (2) stretch the cycle currently
in
progress
while
external
logic makes use of the DAL,
This is accomplished by asserting the
DMR input during the firsf part of a cycle.
1In response, the
DMA
request
will
be
acknowledged
and
except Bus Write and GP Write cycles.

granted
for all cycle types
During Write cycles
(which
are
always
stretched),
the
DAL
carries
write data during the
second part of a cycle, during which time the DAL is not placed in
the
high-impedance
state.
External logic could be designed such
that DMA transfers could occur during Write cycles as long as
the
DMA transfer did not use the DAL coming directly from the DCJ1l1l (a
buffered version of the DAL could
be
used
instead).
In
other
words,
external
1logic
1is
not
prevented
from performing a DMA
operation simply because a DMA grant does not occur.
A DMA request is acknowledged by asserting MAP during
part
of
a
«cycle.
A cycle involving a DMA transfer

and

thus

lasts

a minimum of

eight

clock periods.
3-11

the
second
is stretched

It will continue

the CONT
of two clock periods until
to be stretched in increments
end
not
does
DMR
of
that the deassertion

input is asserted. Note

the cycle.

CHAPTER 4
MEMORY MANAGEMENT

4.1

INTRODUCTION

The

DCJ1l contains a memory management unit (MMU)
which
provides
the
user
with
the
hardware necessary to effect complete memory
management and protection.
The MMU is designed to provide
access
to
all of physical memory and is an important part of multi-user,
multiprogramming systems where memory
protection
and
relocation
facilities are necessary.
'
The MMU

is used to assign segments of memory
called
pages
to
a
program
and
prevent
that
user
from
making unauthorized
accesses to pages outside his
assigned
area.
A
user
1is
thus
prevented from accidental or willful destruction of any other user
user

program

the

system

executive

program.

The MMU is usually used in conjunction with a supervisory
program
which
determines
how the MMU is to operate.
1In multiprogramming
environments this supervisory program controls
the
execution
of
the
various
wuser
programs, manages the allocation of memory and

peripheral
system

O00000000O0

The

device

whole

and

control

careful

safeguards
of

basic characteristics of the DCJ1l
16 kernel mode memory pages
16 supervisor mode memory pages

16 user
8 pages
8 pages

each

Page

lengths

Each

page

mode

from

provided

Transparent

Memory

the

each

integrity

user

the

unit

are:

program.

memory management

mode memory pages
in each mode for instructions

for

data

8192

bytes

with

full

protection

and

relocation

operation

access

The remainder
detail.

4.2

resources,

this

million

chapter

bytes

explains

these

characteristics

ADDRESSING

When the MMU is active, a 16-bit address
is interpreted as a virtual address (VA)

referenced
containing

in
a
program
information to
be used in constructing a new 22-bit physical address
(PA).
The
~information
contained
in
the
wirtual
address is combined with
relocation information contained in a
register
called
the
page
address
register
(PAR)
to
vyield
the
22-bit physical address.
Using the MMU,
memory
can
be
dynamically
allocated
in
pages
composed

Figure

4-1

from

illustrates

the

128

contiguous

relocation

blocks

wvirtual

bytes

each

addresses

physical addresses via page address registers.

PHYSICAL

ADDRESS SPACE
PAGE 5

17777777

VIRTUAL

INSTRUCTION/DATA

PAGE 6

ADDRESS SPACE
1777177

PAR 7

PAR 6

PAGE 7

PAR S
PAR 4

PAR 3

PAR 2

PAGE 4

PAR 1

PAR O

PHYSICAL ADDRESS

PAGE ADDRESS REGISTERS

VIRTUAL ADDRESS
(16 BITS)

(22 8ITS)

PAR = PAGE ADDRESS REGISTER
MR.-11482

Figure 4-1 Virtual Address Mapping Into Physical Address
integral
The starting physical address for each page isum an
of 8192
size
maxim
a
has
multiple of 64 bytes, and each pagewithin the 22-bit physic
al
re
anywhe
bytes. Pages may be located
address

space.

are

Only one set of eight page address registers

illustrated

are
Figure 4-1. Actually, six such sets of page address registers ers
regist
page
of
set
which
of
used by the MMU., The determination
mode of"
is enabled at any given time depends on the current CPU
r the
whethe
and
mode)
user
or
operation (i.e., kernel, supervisor,
.
space)
D
(into
data
or
space)
I
MMU is mapping instructions (into
'

Refer to Paragraph 4.5 for further details.

4.3

I SPACE AND D SPACE

into either
When the MMU is active, all addresses are mappedis used
for all
instruction (I) space or data (D) space. I space
te
instruction fetches, index words, absolute addresses and immediaand
space
I
D space is used for all other references.
operands.
D space each have 8 PARs in each mode of

supervisor,
(MMR3),

and

space

user).
can

Using

memory

disabled

such

CPU

operation

(kernel,

all

references

management
that

(instruction and data) are mapped through I space.

I and
Table 4-1 defines how memory references are mapped intor thea memory
Note that the determination of whethe
D spaces.
the
s on:
reference gets mapped into I space or D space depend
er
regist
the
and
mode,
sing
type of instruction, the addres
selected.

Table 4-1 I and D Space Referencing
(first/second/third memory references)

Address Mode
and Reg Select

Normal
Instruction
(not MTPI, MFPI
MTPD,

00 10 17
20-27
30 37
40 47
50 57
60 70 -

67
77

4.4

CONSTRUCTION OF

07
16

MTPI,
MFPI
(PS<15:12>

MFPD)

not

na
D
I
D
I
D/D
I/D
D
I
D/D
I/D
I1/D
I1/D/D

26
36
46

MTPD ,MFPD,
MFPI
(PS<15:12>

1111)

na
I
I
I
I
D/1
1/1
I
I
D/1
I1/1
I1/1
I/D/1

1111)

na
D
D
D
D
D/D
I1/D
D
D
D/D

I/D
I/D
I1/D/D

A PHYSICAL ADDRESS

The basic information needed for the construction
of
a
physical
address comes from the virtual address (illustrated in Figure
4-2)
and the appropriate PAR set.

]

APF
!

]

\.—fi

]

| W—

—

ACTIVE PAGE

DISPLACEMENT FIELD

FIELD
MR 11049

Figure
The

virtual

4-2

Interpretation

address

consists

The active page field'

which of eight page
be used to form the

lengths

into

two

fields

Address

of:

(APF).

This

address registers
physical address.

The displacement field
address
relative
to
page

of
a Virtual

3-bit
(PARO

(DF).
This 13-bit
the
beginning of a
8K bytes.
The
DF
is
shown in Figure 4-3.

field

determines

through PAR7)

will

field
contains
an
page.
This permits
further
subdivided

]

1
M

Dis
1

]

i
—

IN BLOCK
DISPLACEMENT

8LOCK NUMBER

MA-11080

Displacement Field of Virtual Address

Figure 4-3

consists of:

(DF)

The displacement field

This 7-bit field is interpreted as the

The block number (BN).

The displacement in block (DIB).

block number within the current page.

the

field contains

6-bit

This

displacement of the address within the block specified by

the block number.

The remainder of the information needed to construct the physical
address comes from the 16-bit page address field (PAF) (i.e. the
contents of the page address register (PAR)) that specifies the
starting address of a particular memory page. The PAF is actually
a block number in physical memory, e.g., PAF = 3 indicates a
starting address of 192 (3 x 64 bytes per block) decimal or 300
octal

in physical memory.

The formation of the physical address

ADDRESS

SELECTS

PLUS———J

physical

address

—

00N

—

Figure

06 08

13 12

16
VIRTUAL

1illustrated

PAR

——

N
]
EQUALS

‘

06 05

r;‘
PHYS!ICAL

ADDRESS

Figure 4-4

The logical sequence involved in constructing a
is

follows:

Select a set of page address registers depending

mode

(kernel,

reference

.4494

Construction of a Physical Address

supervisor,

or D

user)

the

CPU

and the type of memory

space).

Use the active page field (APF) from the virtual address to
select one of eight page address registers (PARO through

.
PAR7)

The page address field (PAF)
of
the
selected
page
address
register
(PAR) contains the starting address of the
currently
active page as a block number in physical memory.

The

block

page

number

address

physical

(BN)

field

memory

which

constructed.

The
the
to

4.5

from
to

the

virtual

yield

the

will

contain

the

displacement
in block (DIB) from
wvirtual
address is appended to

yield

true

MANAGEMENT

22-bit

DCJ11

address
number

Physical

added
the

the

block

address

being

the
the

physical

displacement field of
physical block number
address.

REGISTERS

The DCJ11 MMU implements three sets
of
32
shown in Figure 4-5.
One set of registers
another

is
of

supervisor

mode,

and

the

other

16-bit
registers
as
used in kernel mode,
in

user

mode.

The

choice
of
which
set to be used is determined by the current
CPU
mode contained in the processor status regist
er
(PS).
Each
set
consists
of "two
groups
of 16 registers.
One group is used for
references to instruction (I) space and
one
to
data
(D)
space.
The
I
space
group
is
used
for all instruction fetches, index
words, absolute addresses, and immediate
operands.
The
D
space
group

used

for

been disabled
by
contains - 8
pairs

all

other

memory

references,

providing

space

has

not

management
register
$3.
Each
group
of 16-bit registers.
Half of the registers in
each group are page address registers, which
operate as
explained
previously.
The
other
registers
are page descriptor registers
(PDRs).
PARs and PDRs are always selected in
pairs.
A
PAR/PDR
pPair
contains all the information needed to descri
be and locate a
currently

Each

of
located
(see

active

the

memory

page.

memory
management
registers described
above
are
the
uppermost 8K bytes of the physical address space

Paragraph

4.9).

PROCESS STATUS WORD ;

KERNEL (00)

SUPERVISOR (01)

USER (11)

PARO | PDRO

PARO | PORO

t SPACE

PAR?

POR7

PAR?

POR?

PART

PARO

PDRO

PARO | PORO

PDR7

PARO | PDRO

D SPACE

PAR7

PART

POR7

PAR? | POR?

POR?

)
LBRL

Figure 4-5 Active Page Registers

Figure 4-6,
4.5.1 Page Address Registers (PARs) - As shown in addres
s field
page
each page address register contains a 16-bit
a block
(PAF) which specifies the starting address of a page

number

in physical memory.
15
1

]

{

]

Figure 4-6

]

PAF

Page Address Register

MA11083

s field
The page address register which contains the page addres
tion
reloca
a
ning
contai
r
registe
tion
reloca
a
may be thought of as
\

constant, or as a base register containing a base address.

descriptor
(PDRs) =- Page
Registers
Descriptor
4.5.2 Page
registers (PDRs) contain information on page expansion direction,

page length, and access control.

Refer to Figure 4-7.

PAGE LENGTH FIELD (PLF)

]

PAGE LENGTH FIELD

ACF

BYPASS CACHE

0’

00
0

\—1,._0

PAGE WRITTEN

EXPANSION DIRECTION
—

ACCESS CONTROL FIELD

MR.B920

Figure 4-7

4.5.2.1
bypass

can

Page Descriptor Register

Bypass Cache - Bit

mechanism.

bypass

cache

set,

memory

(PDR)

implements

references

present

cache

the

conditional

selected

the

cache

virtual

page

system.

4.5.2.2
Page Length Field (PLF) - This 7-bit field occupying bits
<l4:8>
of
the
PDR specifies the block number, which defines the
boundary of that page.
The block number of the virtual address is
compared
against
the
page length field to detect length errors.

error

greater

the

occurs

than

block

when

the

expanding

page

number

length

less

upwards

field

and

the

page

than

the

when

block

expanding

length

number

downwards

field.

4.5.2.3
Page Written - Bit 6 (the W bit) indicates whether or
this
page has been modified (i.e., written into) since either

PAR

PDR

was

loaded

The

means

the
applications

W
bit
1is useful in
and memory overlays.
It is used
been
modified and hence must be
pages have not been modified and

Note

that

modified

the

bit

(written

reset

been
modified).
involve disk swapping

their

simply

whenever

into).

the

has

which
determine

saved
can

page

not

which

new

pages

form

and

overlaid.

either

PAR

have

which

PDR

4.5.2.4
Expansion
Direction
direction
the
page
expands.
from block number 0 to include
ED

= 1
blocks

program
space.

(ED) - Bit
3
specifies
in
which
If ED = 0 the page expands upwards
blocks with higher
addresses;
if
the page expands downwards from block number 127 to include
with lower addresses.
Upward expansion is usually used for
space

while

downward
|

expansion

usually

used

for

stack

d, occupying bits
Field - This 2-bit fiel
4.5.2.5 Access Control
ts
ains the access righthe
descriptor register s cont
<2:1> of the page
ify
spec
s"
"key
or
access code
of a particular page. The
and whether or not a givenA
be accessed
may
page
a
h
manner in whic
current operation.
the
t of
abor
access should result in an caus
by
es an abort must not be completedpage
h
whic
ence
refer
memory
sing
"mis
h
catc
to
the system interface. Aborts are, used
etc.
faults", prevent illegal accesses

term "write" 1is used to
In the context of access controlructthe
h modifies the contents
whic
ion
indicate the action of any inst
ymous with what is
synon
"Write" 1is
of any addressable byte.
fy" in many computer systems.
sometimes called a "store" or "modi

The modes of access are as follows:

non-resident

abort all accesses

unused

abort all accesses

abort on write attempt

read-only

access

read/write

are
7, 5, 4, and 0 are spare andfutur
4.5.2.6 Reserved Bits - Bits bits
e
ble
possi
are reserved for
These
always read as O.

expansion.

INTERRUPT CONDITIONS UNDER MEMORY MANAGEMENT CONTROL
rupt vectors are
With the MMU enabled, all trap, abort, and inter
ss space. When a
addre
al
considered to be in kernel mode virtu
d according
trans
is
ol
trap, abort, or interrupt occurs, contr processor ferre
word (PS)
s
statu
and
to a new program counter (PC)
gh the
throu
ated
reloc
is
contained in a two-word vector that
pushed
is
PS
and
PC
old
The
set.
kernel page address register
PS (00 =
onto the R6 stack specified by bits <15:14> of the4> new
determine
also
<15:1
Bits
.
kernel, 01 = supervisor, 1l = user)
l mode
kerne
a
for
ble
possi
is
it
r
the new PAR set. In this manne
for all
s
nment
assig
ce
servi
over
ol
program to have complete contr
d in
locate
is
vector
upt
interr
interrupt conditions since the
of a
ce
servi
the
n
assig
may
am
progr
l
The kerne
kernel space.
mode
trap, abort, or interrupt condition to a supervisor or user
4.6

program by simply setting bits <15:14> of the new PS.
4.7

FAULT RECOVERY REGISTERS

red through kernel wvirtual
Aborts generated by the MMU are vecto
registers #0, #1, $2, and #3 are
location

250.

Memory management

used to determine why the

abort

occurred,

and

allow

for

easy

Note - that an abort to a location which is
program restarting.
Thus the
itself an invalid address will cause another abort.
s 250 is
addres
l
virtua
kernel program must insure that kernel will occur which
will
loop
mapped to a valid address, otherwise a
4-8

require console

intervention.

4.7.1

Memory Management Register #0

Figure

4-8.

flags,
various

the
page
number
whose
other status flags.
The
15

ABORT

NON-RESIDENT

(MMR0O)

- MMRO contains

error

reference
caused the abort, and
register is organized as shown in

-06

)

ABORT PAGE
LENGTH ERROR

ABORT READ-ONLY

PAGE MODE

ACCESS VIOLATION

PAGE NUMBER

PAGE ADDRESS

SPACE /O

Figure

4-8

Memory Management Register

ENABLE RELOCATION

(MMRO)

4.7.1.1
Error Flags - Bits <15:13> are error flags.
They may
be
considered
to be in a "priority queue" in that flags to the right
are less significant and should be ignored if a higher bit is set.
That

1is,

and access
would

non-resident

control

ignore

access

fault

service

routine would

faults. A page length
control

Bits <15:13> when set

fault

ignore

service

length

routine

faults,

(error conditions)

the
contents
of
MMRO
bits
facilitate error recovery.

<6:1>,

cause the MMU

MMR1l,

and MMR2.

This

freeze
is

Bits <15:13> may be written under program control.
No abort
will
occur, but the contents of the memory management registers will be
frozen as in an abort.
Bits
RESET

<15:13>

are

cleared

power-up,

a console

start,

instruction.

4.7.1.1.1

Abort -- Non-Resident - Bit

set by attempting

access
a
page
with an access control field key equal to 0 or
It is also set by attempting
to
use
memory
relocation
with
processor mode of 2 (i.e., the illegal processor mode).

2.
a

4.7.1.1.2

¢to

Abort -- Page Length - Bit 14

is set by

attempting

access
a
location in a page with a block number (virtual address
bits <12:6>) that is outside
the
area
authorized
by
the
page
length
field of the PDR for that page.
Bits 14 and 15 may be set
simultaneously by the same access attempt.
Bit 14 may also be set
by attempting to use memory relocation with a processor mode of 2.

4-9

set by attempting to
4.7.1.1.3 Abort -- Read Only - Bit 13 is pages
have access keys of
write in a "read-only" page. Read-only
01.

4.7.1.2

as 0.

read
Reserved Bits - Bits <12:7> are spare and are always
on.

These bits are reserved for possible future expansi

4.7.1.3

Processor

the

indicate

<6:5>

Mode - Bits

mode

CPU

g an
(kernel, supervisor, or user) associated with the page causin
=
mode
illegal
11,
=
user
abort (kernel = 00, supervisor = 0l,
If an illegal mode is specified, bit 15 is set.

10).

4.7.1.4
(I

of mapping
Page Address Space - Bit 4 indicates the type
(0 = I space, 1

or D) the MMU attempted when an abort occurred
with

bits

<«3:1>, page

Page Number - Bits <3:1> contain the

page

number

= D space).

It is used

conjunction

number.

4.7.1.5

Enable Relocation - When bit 0 is set to a 1, the MMU

Note that pages, like blocks, are

reference causing an MMU abort.

numbered from 0 upwards.

4.7.1.6

enabled and
the MMU 1is

protected.

performs address relocation. When bit 0 is cleared,
1inoperative and addresses are not relocated or

Bit

0 is cleared at power-up, by a console start, or
'

by a RESET instruction.

4.7.2

Memory Management Register

(MMR1l) - MMR1l

(see

Figure

the
PC.
This information is necessary to recover from an error resulting
in an abort. MMR1 is cleared at the beginning of each instruction
Whenever a general-purpose register is autoincremented or
fetch.
of
autoincrement/autodecrement
any
records
4-9)
the
through
s
reference
including
general-purpose registers,

autodecremented, the

number

and

the

amount

(in

2°s

complement notation) by which the register was modified is written
It is
into MMR1. The low order byte of MMR1l is written first.
not possible for a DCJ1ll instruction to autoincrement/decrement
more than two general-purpose registers per instruction before an
"abort-causing"

reference.

It is up to the software to determine which set of registers
(kernel/supervisor/user =-- deneral set 0/general set l) was
modified, by determining the CPU and register modes as contained
in the PS at the time of

the abort.

]

AMOUNT CHANGED

(2°'S COMPLEMENT)

]

L
-

AMOUNT CHANGED

NUMBER

(2'S COMPLEMENT)

NUMBER
MR 8924

Figure

4.7.3
the

4-9

Memory Management Register

current

instruction
is the

MMR2

4.7.4

16-bit

wvirtual

fetch.

MMR2

virtual

program

MMR3

22-bit

output

MAP

enables
mapping
(pin

19
13

read-only;

the

- MMR2

loaded

beginning

can

not

(MMR3)

- As

the

use

shown

space

data

the

with
each

written.

PARs

Figure
and

PDRs
time-multiplexed

DCJ1ll).
10

the

counter.

controls

#1 (MMR1)

(MMR2)
at

disables

and

$#2

address

Memory Management Register

4-10,
and

Memory Management Register

00
v

MODE
|

ENABLE I/O MAP

ENABLE 22-BIT MAPPING
ENABLE CSM INSTRUCTION
KERNEL

SUPERVISOR

USER

Figure

4.7.4.1
as

bits

are

Bits

<15:6>

reserved

Enable I/0 Map - Bit

DCJ11l.

unasserted.

4.7.4.3
enabled

Memory Management Register

Reserved Bits These

4.7.4.2

the

4-10

bit

for

MAP

initialization,

are

spare

possible

set

is
MMR3

and

future

assert

asserted.
is

’

L LE 1]

(MMR3)

1If

are

always

read

expansion.

the MAP output
bit

MAP

of
is

cleared.

Enable 22-Bit Mapping - If bit 4
=
0
and
the
MMU
is
(bit
0
of MMRO = 1), the DCJ1l uses 18-bit mapping.
If
bit 4 = 1 and the MMU is enabled, the DCJ1l uses
22-bit
mapping.
If
the
MMU
1is
disabled, bit 4 is ignored and 16-bit mapping is
used.
Figures 4-11, 4-12, and 4-13 illustrates the
three
mapping
alternatives available.
'

1
n
110
PAGE

17760000

177

60000 0V o
1572277

ooooc0

—

/
00157777

—

00000000

INCOMING VIRTUAL

PHYSICAL

ADDRESS (16 B1TS)

ADDRESS SPACE
(22 BITS)

— = RELOCATION

NOT ACCESSIBLE IN THIS MODE
------ NO ADDRESS AELOCATION

Figure 4-11

IRRFIYY

16-Bit Mapping
117711
/0

PAGE
17760000

00757277

1711717

MEMORY/

MANAGEMENT

000000

DO000000

INCOMING VIRTUAL

PHYSICAL

ADDRESS (16 BITS)

ADORESS SPACE

(22 BITS)
—————g RELOCATION

NOT ACCESSIBLE (N THIS MODE
T REY" V)

Figure 4-12

18-Bit Mapping

mnnn
110
PAGE
17760000
17718271717

'/‘
Y777

MEMORY
MANAGEMENT

7
000000

00000000

INCOMING VIRTUAL
ADDRESS (16 BITS)

PHYSICAL

ADDRESS SPACE

(22 BITS)

RELOCATION
ME Vies

Figure

4.7.4.4

used

4-13

22-Bit Mapping

Enable Call To Supervisor Mode

enable

a CSM

instruction.

(CSM)

CSM instruction will execute.
1If bit 3 =
will cause a trap through vector locat
ion

4.7.4.5
1,

and

Kernel,
0

are

Supervisor,

the

kernel,

1If

Instruction -

bit

0,
10.

set

CSM

Bit

to a

and

user

instruction

And User Mode D Space Bits - Bits

supervisor,

mode D

space

bits,

respectively.
These bits determine whether
D
space
mapping
is
enabled
or disabled for each CPU mode.
When D space is disabled,
all memory references use the I space
registers; when D space
is
enabled,
both
the
I
space
and the D space registers are used.
When a mode bit is set, D space is enabl
ed;
when a
mode
bit
is
clear, D space is disabled (see Table 4-2).

Table

4-2

BIT

STATE

Mode

Bit Operations
OPERATION
Disable

kernel

space

Enable

0
1

Disable supervisor D space
Enable supervisor D space

0
1

Disable user D space
Enable user D space

4-13

kernel

space

Recovery - The process of
4,7,% Instruction Back-Up/Restart
"backing-up" and restarting a partially completed instruction
involves:

to
tasks
management
Performing the appropriate memory (e.g.,
g
missin
a
g
loadin
alleviate the cause of the abort

.
page)

ated in MMR1l to
Restoring the general-purpose registers indicthe
instruction by
of
start
the
their original contents at
in MMRI1.
subtracting the "modify value" specified

g R/ with the
Restoring the PC to the "abort time"TM PC by loadin
virtual PC
the
of
value
the
ins
conta
contents of MMR2, which
at the time the instruction generating the abort was fetched.
the
that
assumes
Note that this back-up/restart procedure progr
segment will
general-purpose register used in the abortedThis is amautom
atically
ne.
routi
ery
not be used by the abort recov
register
al
gener
rent
diffe
a
uses
am
the case if the recovery progr
3.

set.

wing Abort - At the end of
4.7.6 Clearing Status Registers Follo
must be set to 0 to
an abort service routine, bits <15:13> of y MMRO
following the
resume error checking. On the next memor referenceement
registers
clearing of these bits, the various memory manag
tions.
opera
will resume monitoring the status of the addressing
will
MMR1
MMR2 will be loaded with the next instruction address,
status
store register change information, and MMRO will

log

MMU

information.

any
occurred,
has
abort
4.7.7 Multiple Faults - Once an
the
of
the state
subsequent errors that occur will not affect
1in
saved
ation
The inform
memory management status registers.
abort
first
the
to
MMRO, MMR1l, MMR2, and MMR3 will always refer
that was detected.

4.8

MMU IMPLEMENTATION

It can
The MMU is a very general purpose memory management tool.
It can
d.
desire
as
ate
intric
be used in a manner as simple or as
very
a
to
device
ion
be anything from a simple memory expans
complete memory management facility.

is assumed that control over
protection resides 1in a
their
page assignments and
memory
at the nucleus of a CPU’s
es
operat
supervisory type program which
further assumed that this
is
It
.
mode)
l
executive (i.e. in kerne
such a way as to
kernel mode program would set access keys in ental
destruction by
from willful or accid
itself
protect
Facilities are also
supervisor mode or user mode programs.
provided so that the nucleus can dynamically assign memory pages
In most normal applications,

4-14

of varying

sizes

response

system needs.

4.8.1
Typical Memory Page - When the MMU is enabled,
the
kernel
mode
program,
a supervisor mode program, and a user mode program
each have eight active pages (described by
the
appropriate
PARs
and PDRs) for data, and eight for instructions.
Each page is made
up of from 1 to 128 blocks and is pointed to by the
page
address
field of the corresponding PAR as i{llustrated in Figure 4-14.
VA 157777

PA 331777

//, 8LOC
1115 (2110lK
74

7////BLOCK 176g (11210)

_
VA 144777

PA 316777

BLOCK 47g (394!

BLOCK 1
BLOCK O

PAR 6

PA 312000

3120

PAF

VA 140000

3910

ACF

ons (P
7

| Figure 4-14
The memory segment
attributes:
l.

Page

length:

[}

w
o>

Physical

Virtual

Nothing

address

Read-only

Typical Memory Pagé

illustrated

address

has

PLF

in Figure

4-14

has

the

following

blocks.

range:

140000

range:

been modified

protection.

312000
(i.e.,

144777.
-

316777.
written)

this

page.

Upward expansion.

Cache (if present in the system) is not bypassed.

These

scheme:

1.
2.

attributes

were

according

determined

PAR6 and PDR6 were selected by the active page

virtual address.

the

following

field

the

(Bits <15:13> of the virtual address = 110)

page
fThe initial address of the page was determined from the blocks
(octal)
3120
=
(octal)
0
(31200
address field of PAR6.
ns the PAF
x 64 (octal) bytes). Note that the PAR whichas contai
register
base
a
constitutes what is often referred to
ning
contai
containing a base address or a relocation register
a relocation constant.

was
The page length (47 (octal) + 1 = 40 (decimal) blocks) Any
PDR6.
determined from the page length field contained in page will
attempts to reference beyond the 40 blocks in this
cause a page length error which will result in an abort,
vectored through kernel virtual address 250.

addresses

were

constructed

according

the

The physical

The W bit (W = 0) indicates that no locations 1in this page
have been modified (i.e., written). If an attempt is made to
l
modify any location in this particular page, an access contro
a
in
d
involve
were
violation abort will occur. 1If this page
be
would
bit
W
disk swapping or memory overlay scheme, the
used to determine whether it had been modified and thus

scheme illustrated in Figure 4-4.

required saving before overlay.

This page is read-only protected, i.e. no locations in this
page may be modified. The mode of protection is specified by
the access control field of PDR6.

The direction of expansion is upward (ED = 0). 1If more blocks
are required in this segment, they will be added by assigning
blocks with higher relative addresses.

The Bypass Cache bit (bit 15) = 0 which means that cache
memory is not bypassed during this relocation operation.

Note that the various attributes which describe this page can all
be determined under software control. The parameters describing
the page are all loaded into the appropriate PAR and PDR under
In a normal application it is assumed that the
program control.
itself contains these registers would be
which
particular page

assigned to the control of a supervisory type program operating in
kernel

mode.

)

4.8.2
MNon—-Consecutive Memory
Pages - It
should
be
noted
that
although
the correspondance between virtual addresses and PAR/PDR
pairs is such that higher VAs have higher PAR/PDRs, this does
not
mean
that
higher
wvirtual
addresses
necessarily
correspond to

higher

of
in

physical

the
lower

addresses.

is quite

simple

to set up the

PAFs

PARs so that higher virtual address blocks may be located
physical address blocks as illustrated in Figure 4-15.
VA 037777

PA 467777

H
[}
[]

PAR 7

VA 020000

PA 460000

VA 0177717

PA 560777

[]
]

]
1

PAR 1

PAF

PAR 0

FAF

Figure
Note

that

wm
4-15

although

contiguous
consecutive
assignment.

Non-Consecutive Memory Pages
single

memory
address
memory
pages

physical

MA 11085

memory

locations,
physical

non-overlapping

address

page must consist of a block of
pages do not have to be located in
1locations.
Also
note
that
the
1is
not
1limited
to
consecutive
locations.

4.8.3
Stack Memory Pages - When constructing DCJ1l1
programs,
it
is
often
desirable to isolate all program variables from program
instructions by placing them on a register-indexed
stack.
These
variables
can
then be pushed or popped from the stack as needed.
DCJ1ll stacks expand linearly downward to lower addresses when data
is
pushed
onto
them.
Thus, when a memory page which contains a
stack

needs more room, it must expand downward.
Blocks with lower
addresses
relative
to the current page must be added.
This mode
of operation is specified.by setting the expansion direction
(ED)
bit
of
the
appropriate
PDR
to a 1.
Figqure 4-16 illustrates a
typical stack memory page.

VA 157777

PA 331777
BLOCK 177g {12740)

BLOCK 176g (12610)

VA 157500

BLOCK 175g (12510)

PA 331500

7
4

VA 140000

PAR 6

POR6 {BC

PAF

PLF

ED ACF%

MR 11458

Figure 4-16 Typical Stack Memory Page
This page will have the following parameters:
PAF = 3120

PAR6:

o
o

ED =1
W= 0orl

PDR6:

PLF = 175 (octal) or 125 (decimal)

o ACF = n (to be
dictates)

Note:

determined

the

(128 - 3).

programmer

the

need

the W bit is set by internal chip hardware.

In this case the stack begins 128 blocks above the relativeof origin
three
of this memory page and extends downward for ah length
l
virtua
kernel
throug
ed
blocks. A page length error abort vector when an attempt
made
is
MMU
the
by
address 250 will be generated
when the
to reference any location below the assigned area, i.e. page
length
the
than
less
is
block number from the virtual address
field of the appropriate PDR.

‘

ation memory
4,8.4 Transparency - In a multiprogramming applic
m seems to
progra
ular
partic
a
that
such
pages can be allocated
tion, a
reloca
Using
n.
uratio
config
y
have a complete 64K memor
kernel mode supervisory type program can easily perform all memory

arent to a supervisor
management tasks in a manner entirely transp
a DCJ1ll system can be
t,
effec
In
am.
progr
mode or user mode
response to a variety
configured to provide maximum throughput and
of users each of which seems to have a powerful system all to
himself.

4.9

MEMORY MANAGEMENT UNIT -- REGISTER MAP
REGISTER

Memory Management Register
Memory Management Register
Memory Management Register
Memory Management Register

ADDRESS

$0
$1
$2
43

(MMRO)

17777572

(MMR1)
(MMR2)
(MMR3)

17777574
17777576
17772516

User

Space

PDRO

17777600

User

Séace PDR7

17777616

User

Space

PDRO

17777620

User

Space

PDR7

17777636

USer I

Space

PARO

17777640

-Uset I

Space

PAR?7

17777656

User

Space

PARO

17777660

PAR7

17777676

User

Space

Supervisor

Space PDRO

17772200

Supervisor

Space

PDR7

17772216

Supervisor

Space PDRO

17772220

Supervisor

Space

PDR7

17772236

Supervisor

Space

PARO

17772240

Supervisor

Space

PAR7

17772256

Supervisor D Space PARO

Supervisor D Space PAR7

17772260

17772276

Kernel I Space PDRO

17772300

Kernel I Space PDR7

17772316

Kernel D Space PDRO

17772320

Kernel D Space PDR7

17772336

Kernel I Space PARO

17772340

Kernel I Space PAR7

17772356

Kernel D Space PARO

17772360

Kernel D Space PAR7

17772376

CHAPTER 5
SPECIAL FEATURES

5.1

INTRODUCTION

This chapter discusses three special
features
the
DCJ11l:
cache
memory
status and control
ODT, and pipeline processing hardware.

5.2

CACHE MEMORY STATUS

AND CONTROL

REGISTERS

The DCJ11l contains hardware that allows the
cache memory into his system.
This hardware

control

and

the

hit/miss

incorporated
into
registers, console

user
to
incorporate
consists of the cache
This

hardware

allows

for
a
broad
spectrum
of cache implementations and the user has
considerable flexibility in designing a cache
memory scheme to fit
his application.
The paragraphs that follow not only describe
the
cache memory status and
control
registers
in
detail
but
also

present

some

memory

into

general

implementation
application of

5.2.1

DCJ1l1

considerations

based

is
- also
presented
the cache memory status

Cache Control

contains
information
which
cache memory.
It is accessed

Only

Bits
as

bits
<10:0>

zeroes.

are

and

involved

system.

1is
by

The

to
and

cache

designing

sample

cache

memory

illustrate
a
typical
control registers.

control

(CCR)

used to control the operation of
referencing
location 17777746.

<3:2> of the CCR are interpreted
read/write bits.
Bits <15:11,8> are

the DCJ11.

always

read

In order for the uninterpreted read/write bits
(bits
10,
<8:4>,
and
<1:0>
to
be used by external logic, the user must include a
"shadow register"TM (write only) in his DCJ11
design.
The
shadow
register
simply
retains
a
hardware
accessible copy of the CCR
information.
Although theé DCJ1l allows the reading and writin
g of
CCR<10:0> and the writing of CCR<15:11>, changi
ng bits <15:11>, 8,
<7:4>, and <1:0> will have no hardware effect
on the DCJ11l.

CCR

bits

<15:11> are uninterpreted and always read
as
zeroes
by
DCJ1ll
(see
sample
implementation in Paragraph 5.2.5).
The
user typically designs an external register for these
bits if they
must
be
interpreted.
The
format of the CCR is shown in Figure
5-1.
the

[Te]

(@]

)

UNINTERPRETED l

{

) (——

{READ AS ZEROES)

UNINTERPRETED
(READ/WRITE])
UNCONDITIONAL

CACHE BYPASS

UNINTERPRETED
(READ AS ZERQ}*

UNINTERPRETED
(READ/WRITE)
FORCE CACHE MISS

UNINTERPRETED
(READ/WRITE}
MR 11436

*Written as a logic 1 at power-up or when console ODT is started
Figure 5-~1 Cache Control Register

5.2.1.1
all
1,

Unconditional Cache Bypass (R/W) - When bit 9 is set to
memory references access main memory, and all cache hits

5.2.1.2

Force Cache Miss (R/W) - When either of bits <3:2> is set

are

invalidated.

to main memory and all cache
forced
are
references
all
1,
to
This in effect disables the cache system.
activity is suspended.

Uninterpreted Bits - Bits <15:10>,
5.2.1.3
10,
Bits
the DCJ1l.
by
uninterpreted
read/write bits and bits <15:11>

are always

are
<1:0>
<8:4>, and
<1:0> are
and
<8:4>,
read as zeroes.

indicates
(HMR)
5.2.2 Hit/Miss Register - The Hit/Miss Register
in
resulted
references
memory
CPU
recent
most
six
the
whether
referencing
by
accessed
1is
It
misses.
cache
or
cache hits
Bits <15:6> are always
Refer to Figure 5-2.
17777752.
location
from
enter
Bits
bits.
read-only
are
Bits <5:0>
read as zeroes.
one
logical
A
leftward.
shifted
are
and
0)
bit
(at
right
the
This
miss.
cache
a
indicates
zero
a
indicates a cache hit, and
register is used to help diagnose the cache system.
15

*-————F LOW
MR 8899

Figure 5-2 Hit/Miss Register

5-2

5.2.3

General Operation -

memory

that

buffers

memory

access

memory

first.

between

the

system

looks

occurs,

from the cache and
found
(a
miss),

Cache memory

data

found

hit),

the

execution proceeds
the
data
must be

write-through
causes

memory.

This

immediately.

write-through

cache

system

data

insure

data

PDP-11

that

systems

technique.

Typical hit/miss operations
summarized in Table 5-1.

Table

5-1:

data

both

high-speed

memory.
the

When

fast

with

cache

are

Hit/Miss

and

cache

into

always

main

updated

normally

a write-through

If not
to main

data

cache

written

to write
the

stores

use

the

system

are

Operations

What Happens
———————

read

request
to

both

Typical

————————————

main

at the fastest rate.
read from or written

a CPU

written

typically
and

for

memory.

memory

CPU

:—--—l-—----

—--—-—------

—---———

CACHE

MAIN

READ

MEMORY

hit

miss

change

updated

no change

updated
no change

updated
updated

WRITE

“hit
miss

typical

program,

READs

occur

updated.

The

85-90%

WRITEs
the

I/0

page
of
physical
typically
cached.
This

status

registers

information.
When

occur

time.

only

Thus,

memory

1is

10-15%
READ

(the
because the

whi
when
ch,
read,

must

misses

top

time
the

bytes)

I/0 page

always

the
cause

1is

contains

convey

and
cache

the

not

device
latest

DMA

device writes to a
cached
location,
the
overwritten
entry
is typically invalidated.
The cache system monitors
transactions to determine if this action is
needed.

cache
DMA

There

are several design parameters that must be
constructing a cache memory, cache size and block
two.

detailed

discussion

cache

design

considered
size

beyond

when

name

but

the

scope

this
document,
but
an
introduction
to the subject is found in
Section VI of the KB11l-C Processor Manual (EK-KB11C-TM).
An 8
KB
direct
mapped
cache is presented as an implementation example
in

Paragraph

5.2.5.

a
onment - In
5§,2,4 Cache Memory In A Multiprocessorsor Envir
cache
own
1its
has
proces
each
where
system
multiprocessor
was
memory, care

caching

avoid

taken

must

data

that

A simple
by another processor ("stale" data).
invalidated
address
shared
Any
n.
situatio
this
prevent
can
software method
memory,
main
to
go
must
e
referenc
the
i.e.,
cache,
must bypass the
and if the address was previously cached, the entry must be
The DCJ1ll provides three bypass mechanisms: an
invalidated.
a
unconditional bypass in which every reference is bypassed;
basis;
conditional bypass in which bypassing is on a page-by-page
and finally, a selective bypass in which the bypassing is done
during operand references. The unconditional bypass is selected
by setting bit 9 of the Cache Control Register (see Paragraph
The .conditional bypass is selected when bit 15 of the
5.2.1).

(see
currently selected Page Descriptor Register PDR 1is set
operand
the
Paragraph 4.5.2). The selective bypass occurs during
references of the instructions used in multiprocessing functions
(TSTSET, WRTLCK and ASRB).

5.2.5 Sample Implementation - The following is a description of
the operation of an 8 Kb direct mapped cache with a block size of
This 1is only
two bytes as implemented on a DCJ1ll based system.

one of many possible implementations.

A direct mapped cache is organized such that each physical memory
address 1is associated with a particular "block" of memory in the
cache. 1In this case we have an 8 KB cache with a block size of
This means there are 4K blocks in the cache. Each
two bytes.

word in physical memory is associated with one of these 4K blocks.
Consider each physical address as being made

three

parts

(see Figure 5-3). The first part is bit zero. Bit zero specifies
which of the two bytes in a two-byte block is to be accessed. The
next part, bits <12:1>, is called the cache index and specifies
which of the 4K blocks in the cache is to be accessed. The third
One cache tag per
1is called the cache tag.
<21:13>,
bits
part,
memory
block is stored in the cache to uniquely identify physical
locations.

0100

1312

21
U

WD UL UGN

SN-UU VU S

CACHE TAG-j
CACHE INDEX

J \

VI SN S

17T

VvV 1

BYTE WITHIN BLOCK
MA 11437

Figure 5-3 'Physical Address Partitioning for Cache Memory
cache
10002477,
at the cache tag
number
block
cache
- associated with the information currently in
the
<21:13>),
(bits
400
is
tag
cache
this
If
<12:1>).
(bits
1237
the DCJ1l accesses location
if
For example,
looks
user)
the
by
(designed
1logic
control

cache control logic sends both bytes in that block to the DCJ1ll.
Since bit 0 is a 1, the DCJ1ll automatically selects the high byte
5-4

(the low byte is ignored).
If the stored cache tag
is
not
400,
the
control
1logic
fetches
two
bytes from memory (10002476 and
10002477), sends 10002477 to the DCJ1l
, loads the two
bytes
into
cache block 1237, and changes the cache
tag of that block to 400.
Any

location

1237

logic
whose

whose cache index is 1237 will be loade
d
into
block
of
cache
memory.
This is the only place the cache contr
ol
has to look if the DCJ1l accesses the data
from
a
location
cacheTMindex is 1237.

Figure 5-4 illustrates a format for each
cache block.
The 9-bit
cache
tag
1is
stored
in
bits <24:16> and the two bytes of data
which comprise the block are stored
in bits <15:0>.
Bit 25
is
a
Valid Bit which indicates whether or not
this cache block contains
valid data.
Data would be invalid for example
immediately
after
power-up,

this

and

the

cache

control

case.
2524

would

16 15
LANNE

SENR SNEN RN |

lllll

VALID BIT

logic

0807

clear

the

valid

bit

00
r

77T

TAG FIELD
DATA BLOCK - BYTE 1
DATA BLOCK - BYTE O
MR 114038

Figure
Notice
cache

identify

location.

The cache

stored
its

in block
address set

index need

1237

desired,

shown

Cache Entry

that only the cache tag of a location
need be stored
in
a
entry
because
only
the cache tag is required to uniquely

anything
<12:1> of
If

5-4

cache entries
in Figure 5-5,.

(for
1237.

can

also

282726

include

181716

L.l

LANE

MR A

BN S

[

]

Lol

PARITY 2 —

)

compared

known

parity

0908 07
T

[
[

not

example)

because

have

information

bits

LML

D S

1.4

NN |

—

{

‘f

VALID BIT

TAG FIELD

PARITY 1
DATA BLOCK
- BYTE 1

PARITY O
DATA BLOCK - BYTE 0

Figure

5-5

Cache Entry With Parity

The Parity 0 Bit stores parity infor
mation
1
Bit
stores parity information for byte

stores

parity

information

The Cache Control

for

the

cache

this
5-5

for
1,

byte

the

Parity

and

the

tag/valid

Parity

bit

combination.

example

configured

Bit

shown

in Figure

5-6.

WRITE WRONG TAG PARITY

BYPASS CACHE

FLUSH CACHE
WRITE

WRONG DATA PARITY

FORCE MISS

DISABLE CACHE TRAPS
MR

Figure 5-6
BIT

<15:11>

Sample Cache Control Register
FUNCTION

NAME

Not Used
(read as

11440

zeroes)

These bits are not used in this
example. The DCJ1l1l will ignore
any data written to these bits and
will always read these bits as
zeroes.

Write Wrong Tag

Parity

(read/write)

This

bit,

when

set,

causes

the

cache tag parity bit (Parity 2) to
be written with wrong parity when
a cache entry is updated (i.e.
upon CPU

read

misses

and

write

hits). This causes a cache tag
parity error on the next access
a location referenced by the

entry.

Bypass

Cache

(read/write)

This

bit, when set, forces all CPU
memory references to go directly
to main memory. Read or write hits
will result in invalidation of
accessed locations in the cache.

Flush

Cache

Setting

(read

contents of the cache to be
declared invalid.
Writing a "O"
into this bit will have no effect.

zero)

Not Used

(read/write)
Write Wrong
Data Parity

(read/write)

This bit
example.

this

bit

not

causes

used

the

entire

this

This bit, when set, causes the
parity bits of the two data bytes
(Parity 0 and Parity 1) to be
written with wrong parity when

5-6

updated (i.e. upon CPU read misses
and write hits). This causes a
cache parity error to occur on the
next access to a location
referenced by the entry.
<5:4>

<3:2>

Not Used

These

(read/write)

example.

Force Miss

(read/write)

All

read

the

CCR<0>

The

cache

from

the

accessed

this

These bits are not used in this
example.

bit, when set, disables cache
parity interrupts.
When this bit
1s cleared, an interrupt occurs
when a parity error is
encountered.
are

causes

checked

the

for

parity.

following

CPU

parity

responses:

Action

Interrupt

Force
cleared

used

This

cache

word

1
CCR is
unaffected

The

Disable Cache Traps
(read/write)

error

not

force all DCJ1ll memory references
to go directly to main memory.
Unlike cache bypasses, force
misses have no effect on cache
entries. Enabling force miss
effectively removes cache memory
from the system.

(read/write)

words

are

These bits, when either is set,

Not Used

bits

a RESET

response

through

miss

vector

114

console

and

force miss.

only.

power-up

start.

instruction.

matrix

for

this

5-7

example

would

be:

|is

Read cached
data

Read

Write thru
cache to

Write

Read

memory

bypass

Write

bypass

Write
memory

Invalidate
cache &
read mem

Read

Invalidate
cache &
write mem

Write

memory

Read forced
miss

Read

memory

Write forced
miss

Write

memory

not

Read

& allocate
cache

memory

Read

applicable

5-8

Invalidate
cachg &
write mem

Write

3.3

CONSOLE ODT

The console octal debugging technique or console
ODT
‘allows
the
DCJ1l
to
respond
to
commands
and
information
entered
via a
user-designed console terminal interface.
The interface bus
uses

addresses

ODT.

17777560

These

addresses

changed,
Console
debugging programs.
via
a
stream
of

DCJ11

as
commands

console

used

through
are

17777566

generated

to communicate with console
the

DCJ1l

and

cannot

ODT
is
a
very
useful
aid
in
running and
Communication between the user and
DCJ1ll
1is
ASCII
characters which are interpreted by the

commands. These commands
in DIGITAL”s ODT-11 software

are

for

a
subset
of
minicomputers.

the

5.3.1
Terminal
Interface - The
minimum
optional
hardware
requirements
for
an
interface
permitting
communication
with
console ODT are outlined in
the
paragraphs
that
follow
(these
requirements
are
met
by
the
DLART
DL-compatible asynchronous
receiver/transceiver
peripheral
chip
DIGITAL
Part
No."
DC319-aA).
.

5.3.1.1
(Figure

Receiver
5-7) must

console

ODT.

Control/Status
exist at address

Console

ODT

does

not

execute

output

this
address;
therefore the RCSR only needs to
bus cycles.
System software may
affect
certain
Interrupt Enable (bit 6), but console ODT ignores

Figure 5-7

Receiver Control/Status Register

Bit

cycles

to input
such
as

- Address 17777560

Description

<15:8>

Unused.
These bits
does not use them.

<7>

Done

flag.

the receiver

set

Done

<6:0>

(RCSR)

bus

respond
bits,
this,

flag

After

must

Unused.

These

use

When
be

a character

buffer

does

not

may

state

received

(RBUF),

the character

cleared

bits

any

may

them.

5-9

and

console ODT

exists

the Done flag must
read

hardware.

any

since

state

from RBUF

since

console ODT

(Figure 5-8)
Register (RBUF) - The RBUF
§,3,1.2 Receiver Buffer
console ODT.
to
t
inpu
r
acte
17777562 for char

must exist at address
bus cycles since
This register only needs to respond tto businput
to this address.
s
cycle
outpu
console ODT does not executearly,
ostics may
diagn
AL
DIGIT
but
System software operates simil
rly.
cause output cycles and thus may not operate prope

Receiver Buffer Register (RBUF) - Address 17777562

Figure 5-8

Description

Bit

<15:8>

Unused.

These bits can be in any state since console

ODT does not use them.

<7:0>

ASCII character.

These eight bits are read by the

processor and interpreted as a console ODT command.
When bit 7 of RCSR is a 1, the processor reads data
from the RBUF. After the input cycle, the hardware
must clear bit 7 of RCSR to 0.

ter (XCSR) - The XCSR
5.3,1.3 Transmitter Control And Status Regis
character output
(Figure 5-9) must exist at address 17777564 t for
bus cycles to this
from console ODT. ODT does not execute outpu
to input bus
therefore, the XCSR only needs to respondaffec
address;
t certain
t cycles to
cycles. System software may cause outpu
this.
s
bits, such as Interrupt Enable, but console ODT ignore
08

MR -BHO0

Figure 5-9 Transmitter Control/Status Register (XCSR) - Address 17777564

Description

Bit

<15:8>

Unused.

<7>

Done flag.

These bits may be in any state since console ODT

does not use them.

1In the idle state, this bit is a1l indicating

that the XBUF is ready to receive a character. After an
output cycle to the transmitter buffer register (XBUF) by
the processor, this bit-must be cleared to 0 by the
hardware. When the XBUF is ready to receive another
character, the hardware sets this bit to 1.

<6:0>

Unused.

These bits may be in any state since console oDT

does not use them.

Note that these bits may be

meaningful to other DIGITAL interfaces.

5.3.1.4
Transmitter Buffer
Register
(XBUF) - The
XBUF
(Figure
5-10)
must
exist
at address 17777566 for character output from
console ODT.

cycles

This

since

address.

diagnostics

only

console ODT

does

may

System

software

cause

needs

not

execute

operates
input

respond

input

and

output

cycles

similarly

cycle

but

bus

this

DIGITAL

thus may not operate

properly.

Figure

bus

5-10

Transmitter

Bit

Buffer Register

(XBUF)

- Address

17777566

Description

<15:8>
:

<7:0>

Unused.

These

ODT

not

does

ASCII

output

$5.3.2

use

with
to

any

eight

ASCII

bits

interface

are

character

since

console

the

written

output

processor

the

by ODT.

may perform

When

XBUF.

Console ODT Operation - Console ODT

terminal

state
'

These

the

XCSR is

cycle

may

them.

character.

processor

bit

bits

half-duplex

operates

mode.

the

console

Communication

between

console ODT and the interface is accomplished via
programmed
1I/0
techniques rather than interrupts.
When console ODT is outputting

characters using the transmit side of the
side
of
the
interface is not monitored

interface,
the
receive
for incoming characters.

Any

lost.

not

characters

check

coming

for

error

bits

is at the other end of
within
the
format
characters
should
be

this

time

the

are

interface.

Console

ODT

another

processor

does

the interface, that processor must
operate
of
half-duplex
transmission.
No
input
sent
until
console
ODT
has
finished

outputting.

5.3.2.1
Console ODT
1Initialization initiated by any of the following:

Console

kernel

Execution

is
2.

of
enabled).

instruction

Assertion of the HALT signal on the system
must
be
asserted
1long
enough
so
that
processor

a HALT

the

end

the

current

ODT

mode

operation

(if

bus.
it

1is

kernel

HALT

The

signal

seen

the

macroinstruction

At.power-up, if the appropriate power-up option is selected.

Console

ODT

Input

Sequence

The Console ODT entry sequence is as follows:
1.

Output <CR><LF> to XBUF.

2.
3.

Output the contents of PC in six digits to XBUF.
(May be
Read and ignore character in RBUF.

Output <CR><LF> to XBUF.

5.,

6.
7.

program

character.)

Output the prompt character, Q, to XBUF.

Enter a wait loop for input. The Done flag, bit 7 in RCSR, is
If it is 0, the test continues.
tested.
If RCSR bit 7 is a 1, then the low byte of RBUF is read.

5.3.2.2

Console ODT Output Sequence -

Console ODT does the following when it has a character

ready

for

output:

1.
2.

Test XCSR bit 7 (Done flag) and if a 0, continue testing.
TIf XCSR bit 7 is a 1, write character to low byte of XBUF
(high byte should be ignored by interface).

5.3.3 Console ODT Command Set - The console ODT command set isOnlya
subset of ODT-11 and uses the same command characters. inputs
specific characters are recognized as valid inputs; other
invoke a "?" response. The commands are summarized in Table 5-2.
The word "location,“ as used in the paragraphs that follow refers
to

memory

location,

device

I/0

processor register, or the processor status word (PS).

internal

Table

Command

5-2

Console ODT Commands

Symbol

Slash

Function

Opens the specified
location (n) and outputs
its contents. n is an

octal

number.

Carriage Return

<CR>

Closes

Line Feed

<LF>

Closes an open location
and then opens the next
contiguous location.

Internal Register
Designator
-

Processor

or Rn

Status

Opens a specific processor
register (n). n is an
integer from 0 to 7 or the
character S.

Word Designator

Opens

Proceed

an open location.

$§

the

must

or R command.

Starts program execution.
Resumes

execution of

program.

Binary Dump

Control-Shift-S

Manufacturing

use

only.

The parity bit (bit 7) on all input characters is
ignored
(i.e.,
not
stripped)
by
console ODT.
If an input character is echoed,
the state of the parity bit is copied to the output buffer (XBUF).
Output
characters
internally
generated (e.g., <CR>) by ODT have
the parity bit equal to 0.
All commands
are
echoed
except
for
ASCII
codes
in
the
range
0-17 (octal).
Where applicable, the
upper- and lowercases of command characters are recognized.
NOTE

In the examples that
from
the
processor

the user”s
inputs

entry

is not.

address

are not required.
outputs

$5.3.3.1

memory
or

(ASCII

location,

processor

status

which
specify
- the contents of
space

for

(ASCII

either

057)

I/O

new data

The

word

the

zeroes

addresses

and

DCJ1ll,

octal

user

leading

Slash - This command

device

and

After

for

When

data,

however,

data words.

a
1location.
the location
40).

digit

digit octal

follow, the response
is underlined, while

must

1In

printing

that

preceded

response

(i.e.,

six
is

used

processor

to /,

other

a valid

open

characters

console ODT

characters)

complete,

location or
5-13

internal

and

prints

then

console ODT

waits

close command.

€001000/012525<SPACE>

Example:

where:

console ODT prompt character.

001000

octal location desired by the user
(leading 0s are not required).

012525

<SPACE>

command to open and print contents of

location.

contents of

octal

location 1000.

space character generated by console
ODT.

5.3.3.2
<CR> (ASCII 015) Carriage Return - This command
is
used
to
close
an
open
location.
If a location®s contents are to be
changed, the user should precede the <CR> with the new
data.
If

change

its

contents.

1is

desired,

<CR> closes the location without altering

@R1/004321<SPACE>

Example:

<CR>

Processor register Rl was opened and no change was desired so
the
user
issued<CR>.
In
response
to the <CR>, console ODT printed
<CR><LF>@.

Example:

@R1/004321<SPACE>
@

this case

entered

data

the user

before

the open

desired

issuing

1234

to change Rl,

the <CR>.

location and

<CR>

so new data,

1234,

was

the

user

Console ODT deposited the new

then printed <CR><LF>@.

Console ODT does not directly echo the <CR> entered
but instead prints a <CR>, followed by an <LF>, and

by
@.

5.3.3.3
<LF> (ASCII 0l12) Line
Feed - This
command
1is
used
to
close an open location and then open the next contiguous location.
Memory locations and processor registers are incremented by 2
and

1
respectively.
If
the PS is open when a <LF> is issued, it is
closed and a <CR><LF>@ is printed;
no new location is opened.
If
the
open
location’s
contents
are
to
be changed, the new data
should precede the <LF>.
If no data is entered, the
1location
is

closed

without

being

altered.

Example:

BR2/123456<SPACE>
R3/054321<SPACE>

<LF>

In this case,

the user entered <LF> with no data preceding
5-14

it.

1In

response,
console
ODT closed R2 and then opened R3.
has the last register, R7, open,
and
1issues
<LF>,
opens

the beginning

RO.

@R7/000000<SPACE>

Example:

R0O/123456<SPACE>

<LF>

When a user
console
ODT

Unlike with most other commands, console ODT
does
not
echo
the
<LF>.
Instead
it
prints
<CR>,
then
<LF>,
so
that terminal
printers operate properly.
In
order
to make
this
easier
to

decode,

console ODT does not echo ASCII characters in the range 0

5.3.3.4

8
(ASCII
044)
Or
R
(ASCII
122)
1Internal
Register
Designator - Either character when followed by a register
0 to 7, or PS
designator,
S,
will
open
that
specific

(octal).

number,

processor

The $ character

recognized to be compatible with ODT-11l.

The R

character was introduced because it can be conveniently typed with

one key stroke and because it is an easily remembered symbol for a
register.

Example:

@$0/000123<SPACE>
or

@R7/000123<SPACE>
>
R0/054321<

<LF>

If more than one character is typed after the R or §, console
uses the last character typed as the register designator.

5.3.3.5

(ASCII 123) Processor Status Word - This designator

ODT

for
opening
the PS
(processor status word) and may be employed
only after the user has entered an R or $ register designator.
BRS/100377<SP

Example:

The

trace

bit

0 <CR>

NOTE
(bit <4>)

the PS

cannot

be modified by the user.
This is done so
that PDP-11 program
debugging
utilities
(e.g.,
ODT-11),
which use the T bit for
single-stepping,
are
not
accidentally
harmed by the user.

If the user issues a <LF> while the PS is open, the PS

and ODT prints

<CR><LF>@.

No new location

5-15

is opened

closed

this case.

5,3,3.6 G (ASCII 107) Go - This command is used to start program
execution at a location entered immediately before the G. This

Example:

START

switch

echoing

the

command

8200G<NULL><NULL>

The console ODT sequence
character,

and

ADDRESS

LOAD

the

function is equivalent

sequence on other PDP-1ll consoles.

for

follows.

Print two nulls
character
from

after

This is intended to prevent the G
(ASCII 0).
getting flushed during the bus initialization

sequence that follows, assuming a double-buffered UART chip is

used

in the console terminal

Load R7

is used.

interface.

(PC) with the entered data.

(In the above example, R7

where program execution begins.)

If no data is entered,

is set to 200, and that is

The PS, MMR0<15:13,0>, MMR3, PIRQ, CPU Error Register,
Memory
System
Error
Register,
Cache Control Register, and Floating
Point Status Register

are cleared

The cache, if present,

is flushed

The system bus

The service state is entered by the
are processed.
requests
service

zero.

(if so implemented).

initialized by the processor.

Any outstanding
DCJ1ll.
If the bus HALT signal is

asserted, the processor reenters the console ODT state.
This
a system without starting a
initialize
to
used
1is
feature

program

(R7

altered).

5.3.3.7
P (ASCII 120) Proceed - This command is
wused
to
resume
execution
of
a program and corresponds to the CONTINUE switch on
other PDP-11 consoles.
No
programmer-visible
machine
state
1is
altered

using

this

command.

Example:

Program execution resumes at the address pointed to by R7.
After
the
P
is
echoed,
the
DCJ1ll
1immediately
fetches
the
next
instruction.
After
the
instruction
1is
executed,
outstanding
interrupts,
if
any,
are
serviced.
If
the HALT bus signal is
asserted, it is recognized at the end of the instruction, and
the

DCJ1ll

the

enters

(R7)

the

1is

single-instruction
on

the

terminal.

console ODT

printed.
step

through

state.

this

Upon entry,

fashion,

the content of

the

a program and obtain

user

a PC

can

"trace"

5.3.3.8
used

for
command.

Control-Shift-S

manufacturing

(ASCII

023)

test

purposes

Binary Dump - This command
is

and is not a normal user
It is described here to explain the processor’s response
if
accidentally
invoked.
It
1is
intended
to more efficiently
display a portion of memory compared to using
the
"/"
and
<LF>
commands.
The protocol is as follows.

After

prompt

control-shift-S

character,

command

and

console

echoes

ODT

receives

it.

The
two

host system at the other end of the serial line must
send
8
bit
bytes
which console ODT interprets as a starting
address.
These two bytes are not echoed.

The

first

second

byte

specifies

After

the

outputs

second
ten

previously
ODT prints
If

user

address

starting address
forced
to
be
0;

<21:16> are always
restricted to the first
3.

starting

specifies

32K

address

bytes

specified.
<CR><LF>Q.
accidentally

words

byte

prompt

character

the

address

has

been

received,

line

starting

When

the

enters

this

command,

printed.

the
bits

command

1is

space.

serial

output

and

Address

dump

the

in order to exit from the command that
100) be entered as a starting address.

<15:08>

<07:00>.

console
at

the

finished,

ODT

address

console

recommended

two @ characters (ASCII
After the binary dump,
‘

5.3.4
Address
Specification - All
I/0
addresses
(17760000
to
17777777)
must be entered by the user with all 22 bits specified.

For

example, if a user desires
serial interface he must enter

5.3.4.1

General

console

ODT,

specified
general

user

bit

access

Registers - Whenever

they

specific
to

the

access

the

zero

set

and

set

one,

PS<ll>

then

zero

has

been

set

the

and

must

through

set
RS

general

Similarily,

references

currently

operating

halted

accessed.

set

console

777560.

referenced

program
is

to RO-RS

the

commands

program
has
been
halted,
the
be restored in order to continue

000000

€R4/052525<SPACE>
R4

zero

desired,

value,

can be used.
If
an
operating
original
value
of
PS<1ll>
must
execution.
|
PS

one,.

appropriate

Example:

are

the

(PS<ll>

set

RO-R5

g¢general

(PS<1ll>).

set

opened, register
1is
operating in

to open the
RCSR
of
17777560, not 177560,

<CR>

opened.
5-17

@RS/000000<SPACE> 4000 <CR> <CR><LF>

@R4/177777<SPACE>
@RS/004000<SPACE>

The PS was
In this case, R4 in register set one was desired.
Then R4 was
one).
set
(register
1
to
set
and PS<ll> was
opened,
restored,
was
PS<ll>
of
examined and closed. The original value
command.
P
and the program was continued using the

5.3.4.2

ODT,

8tack Pointers - Whenever R6
accesses

the

referenced

console

stack pointer specified by the PS current

mode bits (PS<15:14>). If a program operating in kernel mode
1is halted and R6 is opened, the kernel stack
(PS<15:14> = 00)
pointer is accessed. Similarly, if a program is operating in
supervisor

or user mode, R6 accesses the supervisor or user stack
'

pointers.

set by
If a specific stack pointer is desired, PS<15:14> must be
to the appropriate value and then the R6 command can be
the user
If an operating program has been halted, the original value
used.
of PS<15:14> must be restored in order to continue execution.
Example:

140000

@R6/123456<SPACE> <CR> <CR><LF>
The user mode stack pointer has been opened.
@RS/140000<SPACE> 0 <CR>

@R6/123456<SPACE> <CR> <CR><LF>
@RS/000000<SPACE>

140000<CR>

<CR><LE>
.

The PS
In this case, the kernel mode stack pointer was desired.
R6
Then
mode).
(kernel
and PS<15:14> were set to 00
opened,
was
was
PS<15:14>
wvalue of
The original
was examined and closed.
restored, and then the program was continued using the P command.

point
floating
Accumulators - The
Point
5.3.4.3 Floating
floating
Only
ODT.
console
from
accessed
accumulators cannot be

point instructions can access these registers,

5.3.5

Entering Octal Digits - When

the

user

1is

specifying

console ODT will use the last eight octal digits if more
address,
data,
specifying
than eight have been entered. When the user is
use the last six octal digits if more than six
console ODT will
either
The user need not enter leading Os for
have been entered.
If an odd
console ODT forces 0s as the default.
address or data;

address is entered, console ODT responds to the error by

?<CR><LF>@.

printing

5.3.6

ODT Timeout - If the user specifies a

causes

parity

error,

console ODT

nonexistent

responds

the

address

error

printing ?<CR><LF>@.

5.3.7

1Invalid Characters - Console ODT will

recognize

upper-

lowercase
characters as commands.
Any character that console ODT
does not recognize during a particular sequence is echbed
(except

for ASCII characters
prints ?<CR><LF>@.

the

range

(octal)),

and console ODT

5.4

DCJ1l1 PIPELINE PROCESSING

the

user.

and
The DCJ11l gets much of its performance from its prefetch
and
h
prefetc
The primary benefit of
mechanisms.
predecode
predecode is that memory references are overlapped with internal
operations, and the need for explicit instruction fetch and decode
ions are
cycles is minimized. The prefetch and predecode operat
d by
altere
be
cannot
and
chip
performed automatically by the DCJ11l
A primary function of the prefetch mechanism 1is ¢to fill four
information and replenish theé registers as
with
registers
r
required. These four registers, the virtual program counte
buffer
ch
prefet
the
(PPC),
r
counte
(VPC), the physical program
ed
(pB), and the instruction register (IR) are collectively referr
the
in
ers
regist
of
ts
conten
The
to as the prefetch pipeline.
ts of
beginning of the pipeline are used to determine the conten
,
filled
is
ne
pipeli
the
When
ne.
pipeli
the
registers further down
Four
the prefetch mechanism is said to be in steady state.
5-11
Figure
ne.
pipeli
empty
an
fill
to
ed
requir
microcycles are
illustrates the process of filling the pipeline.

Microcycle 1

Microcycle 2

Microcycle 3

Microcycle 4

VPC <-- PC

PPC <-- MMU(VPC)
VPC <-- VPC + 2

PB <-- M[PPC]
PPC <-- MMU(VPC)

IR
PB

<-- PB
<=-- M[PPC]

VPC

<-- VPC +

<-- PC +

MMR2

<--

Figure 5-11

VPC

<-- VPC +

PPC <-- MMU (VPC)

Pipeline Filling Process

In microcycle 1, the VPC is is simply set to the same value as the
In microcycle 2, the VPC is sent through the MMU and the
PC.
The VPC 1is
resulting physical address is loaded into the PPC.
VPC and PPC
valid
a
have
we
by 2. At this point
then incremented
s while
Sometime
zed.
synchroni
and the pipeline is said to be

executing a macroinstruction, the pipeline is synchronized but not
filled. In that case, only microcycles 3 and 4 need be performed
for

the next macroinstruction.

In microcycle 3, the word in memory addressed by the PPC is
The PPC is updated with the relocated
fetched 1into the PB.
(mapped) VPC and the VPC is incremented again. In microcycle 4,
sent to the IR and 1is decoded as the next
is
PB
the
macroinstruction (note that the DCJ1l asserts PDRC at this time)..
The new contents of the PB are fetched from the memory location
The PPC is again updated with the
referenced by the PPC.
relocated (mapped) VPC and the VPC is updated (incremented) once
again. Also during microcycle 4, the original PC is loaded into
MMR2

(if MMRO<15:13> = 000)

and is incremented by 2.

the IR
is complete),
In steady state (i.e., when microcycle 4
the
contains
PB
contains the macroinstruction being executed, the

data from the memory location pointed to by the PC, the PPC
contains the physical address of the next word to be prefetched,
5-20

and

the VPC contains

Once

only

steady

state,

registers

microcycle

(i.e.,

the
a

incremented value of
stream of

may

microcycle

the PC.

macroinstructions

executed

4).

the

While one

that

rate

operate

instruction

one per

being

executed,
the next one is being decoded, and the following one is
being prefetched into the
PB.
As
illustrated
in
Figure
5-11
during
microcycle
4:
the
contents
of the prefetch buvffer are
loaded into the IR, the word addressed by the PPC is
1loaded
1into
the
PB, the VPC is relocated
and loaded into the PPC, and the VPC
is incremented by 2.
This maintains the
steady
state,
allowing
the

next
also

Note

The

macroinstruction to be executed in the
the DCJ1ll bus is kept busy 100% of

next microcycle.
the time.

that

instructions

that

operate

immediate

data

and

also make maximum use of the prefetch mechanism.
At steady state,
a stream of these macroinstructions
execute
in
two
microcycles
(microcycles 3 and 4).
During microcycle 3, the data in the PB is
moved to a scratch register.
During microcycle 4,
the
operation
is
performed.
In
both cycles, the steady state of the prefetch
mechanism is maintained by prefetching the next instruction stream
word.
The

The DCJ1ll

prefetch

bus

pipeline

a
prefetch fault
PC, or any of the

again

kept

refilled

occurs.
memory

busy

100%

after
a power-up

Prefetch faults occur
management
registers

prefetch
fault
invalidates
only
the
PB.
pipeline
remains
synchronized
and
can
be
microcycles.

5.4.1

Pipeline

Flow

the

Example - Consider

time.
sequence

when
are

This means
refilled

the

the PS, CCR,
written.
A

following

that
in

the
two

example

program:

Virtual
‘Address

Symbolic
Representation

Octal
Code

1000
1002

MOV
BIS

R2,R3
#1,R3

010203
052703

1004
1006
1012

ADD R1,R3
CLR RO
.
ADD R3,RO

000001
060105
005000
060300

The flow of
Table 5-3.

information

through

the

pipeline

occurs

shown

Table 5-3 Pipeline Fldw
Pipeline

Microcycle

n+l

n+2

n+3

n+4

n+5

1010

1012

1014

ADD

CLR

1002

1004

1006

MOV

BIS

PB
PPC

VPC

(010203)

(052703)

BIS

000001

ADD

(052703)

(060105)

CLR

(005000)

ADD

(005000)

(060300)

ADD

(060300)

MMU (1004) MMU (1006) MMU(1010) MMU(1012) MMU(1014) MMU (1016)

1006

1010

1012

* Instruction at location 1014

1014

1016

1020

the
Note that the example starts at microcycle n, by whichis time
steady
in
ne
pipeli
the
(i.e.,
prefetch pipeline has been filled
state). All the instructions in the example executees inin one
two
microcycle except the BIS instruction, which execut
microcycles.

CHAPTER

ADDRESSING MODES AND BASE

6.1

INSTRUCTION SET

INTRODUCTION
-

The

first

part of

this

chapter

divided

into

six major

sections:

Single-Operand Addressing
specifies
the registers;
for locating the operand.

Double-Operahd Addressing -- One part of the instruction

wgrd

Direct Addressing

the

specifies
information

selected

the
for

-- One part of the instruction
word
the other part provides information
|

registers;
the
remaining
locating two operands.

=--

The

operand

the

parts

provide

content

Deferred (Indirect) Addressing -- The contents of the selected

Use of the PC as a
General-Purpose
Register
-The
PC
is
different
from
other
general-purpose
registers
in
one
important
respect.
Whenever
the
processor
retrieves
an
instruction,
it
automatically
advances
the
PC
by
2.
By
combining this automatic advancement of the PC
with
four
of
the
basic
addressing
modes,
we produce the four special PC
modes -- immediate, absolute, relative, and relative-deferred.

Use of

the

address

the Stack Pointer

General-purpose

The

second

the DCJ11l

6.2

part

registers

this

the

General-Purpose

can

used

chapter

instruction

operand.

describes

for

stack

each

the

instructions

set.

ADDRESSING MODES

Data stored in memory must
be
accessed
and
manipulated.
handling
1is
specified
by
a DCJ1l instruction (MOV, ADD,
which usually specifies the:

operations.

Function

General-purpose
operand, and/or

Addressing mode,
are to be used.
large

portion

performed

(operation code).

which

the

Data
etc.),

specifies

how

the

selected

source

registers
'

data

handled
by a

6-1

computer

structured

etc.). The DCJ11 addressing
(in charadter strings, arrays, lists, le
ured
handling of struct
modes provide for efficient and flexib
.
data.

A general-purpose register may be used with an instruction in

any

of the following ways.

As an accumulator -- The data to be manipulated resides in the

As a pointer -- The contents of the register is the address of

ons
As a pointer that automatically steps through memory locati
tive
consecu
through
forward
g
steppin
ically
Automat
-y
locations is known as autoincrement addressing; automaticall
sing.
addres
t
cremen
autode
as
known
is
rds
stepping backwa

.
an operand, rather than the operand itself.

These modes are particularly useful for processing tabular

array data.

As an index register -- In this instance, the contents of the
register and the word following the instruction are summed to
produce the address of the operand.
to variable entries in a list.

This allows

easy

with

the

(RO--RS

and

considered

An important DCJ1l feature, which should be

addressing modes, is the register arrangement.

o
o

Two

six

sets

RO“~=R57)

general-purpose

registers

access

A hardware stack pointer (SP) register (R6) for each processor

mode

(kernel,

supervisor,

user)

o A program counter (PC) register (R7)

Registers RO--R5 and R0O“--R5° are not dedicated to any specific
their use 1is determined by the instruction that is
function;
decoded.

used

for

operand

storage.

They can contain

the

address

They can

They can be used as index registers for

They can be

contents

For

example,

the

two registers can be added and stored in another

pointers to the address of an operand.
features.

program

wused

for

the

operand

autoincrement

serve

autodecrement

convenient

data

and

access.

The DCJ1l also has instruction addressing mode combinations that
facilitate temporary data storage structures. These can be used
for convenient handling of data that must be accessed frequently.

stack manipulation. The register that keeps
known as
1is
This
(SP).
track of stack manipulation is known as the stack pointer
6-2

Any register can be used as a stack pointer under program control;
however, certain instructions associated with
subroutine
1linkage
and interrupt service automatically use register R6 as a "hardware
stack pointer." For this reason, R6 is frequently referred
to
as
the

SP.

The stack pointer

(SP)

stack.

keeps track
of the latest entry on

the

’

The stack pointer moves down as items are added to
the
and
moves
up
as
items
are
removed.
Therefore, the
pointer always points to the top of the stack.

The
to

hardware stack is used during
store
information,
‘allowing

interrupted

stack
stack

trap or
interrupt
handling
an
orderly
return
to the

progranm.

Register R7 is used by the processor as its program counter
(PC).
It
is
recommended
that
R7
not
be
used as a stack pointer or
accumulator.
Whenever an instruction is fetched from memory,
the
program

counter

the

instruction

automatically

incremented

two

point

6.2.1
8ingle-Operand Addressing - The instruction format
single-operand
instructions
(such
as CLR, INC, TST) is

shown

type

Figure

06
R

{

Bits <15:6>
instruction

6-1

DESTINATION ADDRESS

specify the operation
to be executed.

Bits <5:3>
indicate

Double-Operand
(such

instructions

that

format

Bit

addressing.

Addressing - Operations
ADD,

specify

for

the

of the 8 general-purpose
instruction word.

SUB,

MOV,

and

two addresses.

called
the
source operand;
the second
operand.
Bit assignments in the source
fields
may
specify different modes and

instruction

defines

called
the
destination
address
field consists of two subfields:

(indirect)

Bits <2:0> specify which
to be referenced by this

operands

code

specify the destination mode.

deferred

MA B4se

Single-Operand Addressing

Bits <5:0> form a
6-bit
field
field.
The destination address

6.2.2

OP CODE

Figure

all

00
)4

MODE

for

6-1.
1

word.

double

operand
6-3

CMP)

The

that
are

first

set

registers

imply
handled

operand

two
by

is called the destination
and
destination
address
different registers.
The

instruction

shown

Figure 6-2.

]

MODE

OpP CODE

RAn

DESTINATION ADDRESS

SOURCE ADDRESS

Figure 6-2

Double-Operand Addressing

MR 5459

to select the source operand (the
The source address field is used ion
is used similarly, and locates
operand).

first

The

destinat

the second operand and the result.
A,

ADD

For example,

the

instruction

A to the
B adds the contents (source operand) of locationutio
B
n,

tion B. After exec
contents (destination operand) of loca
tion and the contents of A will

will contain the result of the addi
be unchanged.

the
the rest of the chapter useof the
Examples in this paragraph andruct
ions. (A complete listing
following

sample DCJ1ll inst

DCJ11l instructions appears in Paragraph 6.3.)

Octal Code
Mnemonic Description
0050DD
Clear. (Zero the specified destination.)
CLR
Clear byte. (Zero the byte in the specified 1050DD
CLRB
‘destination.)

INC

Increment. (Add one to contents of the

0052DD

Increment byte. (Add one to the contents of

1052DD

ents of the
Complement. (Replace the cont
complement;

0051DD

destination.)

INCB
COM

the destination byte.)

destination by its logical
each 0 bit is set and each one bit is
cleared.)

COMB

contents of
Complement byte. (Replace thelogic
al
the destination byte by its

complement; each 0 bit is set and each
1 bit is cleared.)

Add. (Add the source operand to the

ADD

destination operand and store the result

n
n

()

at the destination address.)

1051DD

destination field (six bits)
source field

contents of

(six bits)

06SSDD

6.2.3

modes

Direct Addressing - The following summarizes the four

used

with

Direct Modes

Mode
0

direct

(Figures

addressing.

6-3

basic

6-6)

Name

Assembler
Syntax

Function

contains

operand.

OPERAND

INSTRUCTION

MA- 5460

Figure

Mode

6-3

Mode

Name

Assembler
Syntax

Autoincrement

(Rn)+

INSTRUCTION

Function
Register is used as a pointer
to sequential data and then
incremented.

ADDRESS

OPERAND

+2 FORWORD,
+1

Figure

Mode

6-4

Mode

Autoincrement

Assembler
Syntax

Name
Autodecrement

INSTRUCTION

Function

- (Rn)

FOR BYTE

ADDRESS

-2 FORWORD

and

OPERAND

-1 FORBYTE

Figure 6-5

Modé

Mode 4 Autodecrement

Name

Assembler
Syntax

Index

X (Rn)

INSTRUCTION

Function
Value X
produce
Neither

ADDRESS

“,:O—- S

Figure

6-6

is added to (Rn) to
address of operand.
X nor (Rn) is modified.

Mode

6
6-5

Index

6.2.3.1

registers

as simple accumulators, with the operand

used

may

the ‘general

any

Since they are hardware
contained in the selected register.
registers operate at
general
the
),
processor
the
(within
registers

The assembler interprets and

variables.

accessed

frequently

operating

for

high speeds and provide speed advantages when used

assembles instructions of the form OPR Rn as register mode
Rn represents a general register name or number and
operations.
mnemonic.
instruction
to represent a general
used
OPR is

Assembler
follows.

that a general register be defined as

requires

syntax

RO = %0

(% sign indicates register definition)

Rl
R2

etc.

=
=

%1
%2,

Registers are typically referred to by name as RO, Rl, R2, R3, R4,
R5, R6, and R7. However, R6 and R7 are also referred to as SP and
PC,

respectively.

OPR

(Figures 6-7 to 6-9)

Increment

005203

INC R3

redister

general-purpose

Add one to the contents

Operation:

Instruction Name

Octal Code

Symbolic

R3.

06
T

| REGISTER

N
.
A
.

DESTINATION FIELD

OP CODE (INC(0052))

o
|

R4
RS
R6 (SP)

R7 (PC)

Figure

Symbolic
ADD

R2,

Operation:

6-7

1INC

Octal
R4

Add

Increment

Code

060204

the

contents

MA-sa67

Instruction Name
Add

6-6

the

contents

R4.

BEFORE

AFTER

000002

000004

000006

MR- 5468

Figure
3.

ADD R2,R4

Symbolic

Octal

COMB R4

105104

Operation:
registers

i.e.,

6-8

byte

Add

Code

Instruction Name

Complement byte

1°s complement bits <7:0> (byte) in R4.
are used, byte instructions operate only
0 of the register.)
BEFORE
R4

(When general
on bits <7:0>;

AFTER

022222

022155

MA-65469

Figure

6.2.3.2

6-9

COMB

Autoincrement

Mode

Complement

[OPR

(Rn)+]

Byte

- This

mode

(mode

sequential
location.
useful for array processing

The
and

provides
for
automatic
stepping of a pointer through sequential
elements of a table of operands.
It assumes the contents
of
the
selected
general-purpose
register
to
be
the
address
of
the
operand.
Contents of registers
are
stepped
(by
one
for
byte
instructions,
by
two for word instructions, always hy two for R6

and
R7)
to
autoincrement

address
mode
is

stack

processing.

step

the

Although
general

OPR

pointer

most
and

will

useful

may

the
next
especially

for

used

table
for

element

the

handling,
variety

this

table

operand

mode

and
the

then
table.

completely

purposes.

(Rn)+

Autoincrement
1.

Mode

Examples

Symbolic

Operation:

Clear

Use
selected

two.

contents

BEFORE

the

address
increment the

ADDRESS SPACE

030000

6-12)

Instruction Name

AFTER

Clear

RS as
and then

20000 |

005025

30000 |

000000

the
operand.
contents of RS by

030002

30000 |

1111116

Figure
Symbolic
CLRB

Code

operand

005025

6-10

005025

ADDRESS SPACE
20000 |

(Figures
Octal

CLR (RS)+

access

address

(RS5)+

6-10

CLR

(R5)+

Octal

Code

105025

6-7

MR.5464

Clear

Instruction Name
Clear

byte

the operand.
Operation: Use contents of RS> as the address of conten
ts of RS
Clear selected byte operand and then increment the
by

one.

BEFORE

RS |

20000 | 105025

AFTER

| 000
30000 | 111

16
|
30000 | 111

Figure 6-11

30002

rRs | 030001

105025

20000 |

030000
]

T r

ADDRESS SPACE

CLRB

MR 5485

(R5)+ Clear Byte

Symbolic

Octal Code

Instruction Name

ADD (R2)+,R4

062204

Add

Operation: The contents of R2 are used as the address of the
operand, which is added to the contents of R4. R2 is then
incremented by two.

AFTER

BEFORE

ADDRESS SPACE
10000

062204

REGISTERS
R2

100002

010000

ADDRESS SPACES
10000

100002 | 010000

062204

100002

REGISTERS
R2

100004

r4 |

020000

010000
MR .5470

Figure 6-12

6.2.3.3

ADD

(R2)+,R4 Ad4d

mode

Autodecrement Mode [OPR-(Rn)] - This

were

not

(mode

a list in reverse direction. The
useful for processing data in
purpose register are decremented
generalselected
contents of the
by two for word instructions) and
ons,
instructi
byte
for
one
(by
of
The choice
the operand.
of
address
the
as
then used
postincrement,

arbitrary

predecrement

decisions,

but

features

were

hardware/software stack operations.

for

the

intended

DCJ1l

= to

facilitate

OPR- (Rn)

Autodecrement Mode Examples
1.

(Figures 6-13 to 6-15)

Symbolic

Octal Code

Instruction Name

INC - (RO)

005240

Increment

The contents of RO are decremented by two and used as
Operation:
the address of the operand. The operand is incremented by one.

6-8

BEFORE

AFTER

ADDRESS SPACE

REGISTERS

005240

1000

017776

1000

005240

017774

]

000001

17774

000000

17774

ADDRESS SPACE

MR 5466

Figure 6-13
2..

-(RO)

Increment

Symbol ic

Octal Code

Instruction Name

INCB

105240

Increment

- (RO)

Operation:

used

INC

as
one.

byte

The

contents of RO are decremented
by
one
address of the operand.
The operand byte is
BEFORE
AFTER

the

ADDRESS SPACE

1000

105240

ADDRESS SPACE

017776

1000

increased

105240

017775

|
17774 | 000

000

i
L

17776

|
1

Figure
3.

INCB

001 ; 000

17776

;

- (RO)

Symbolic

Octal

ADD

064300

- (R3),RO

Operation:
used

6-14

17774

Increment

Code

contents

contents of R3 are
pointer to an operand

(destination

Instruction Name

‘Add

The

decremented
(source),

77774

064300

000020

077776

ADDRESS SPACE

10020

000050

77774

1Index Mode
of

the

064300

0000070

077774

l
000050

77776

Figure

6.2.3.4

two
is added

AFTER
REGISTER

77776

contents

by
which

operand).

BEFORE
ADDRESS SPACE

10020

MR 5471

Byte

the

6-15

[OPR
selected

ADD

- (R3),R0

X(Rn)]

- In

Add

this

MR 8472

mode

(mode

general-purpose register, and an index
word following the
instruction
word,
are
summed
to
address of the operand.
The contents o f the selected register may
be used as a base for calculating
a
series
of
addresses,
allowing
random
access
to
elements
of
data
structures.
selected re gister can then be modif
ied by program to
access
in
the
table.
Index addressing instructions are of the form
OPR

6--9

1location

X (Rn), where X is the indexed word located in the memory

general-purpose register.
OPR

selected

the

X (Rn)

(Figures 6-16 to 6-18)

Index Mode Examples

1is

and

word

instruction

the

following

Symbolic
CLR 200 (R4)

Octal Code

Instruction Name

005064

Clear

000200

The address of the operand is determined by adding 200
Operation:
The operand location is then cleared.
to the contents of R4.
AFTER

BEFORE

1020 |

005064

1022

000200

1000

1024

ADDRESS SPACE

1020 |

005064

1022

G00200

1024

+200

‘*

1200

000000

1200

1777177

1200
1202

Figure 6-16

Symbolic

COMB 200 (R1)
Operation:

adding

200

CLR 200(R4)

Clear

Octal Code

Instruction Name

105161

Complement byte

000200

The contents of a location, which

the

contents

logically complemented).

1020

105161

1022

20176

determined

of Rl, are 1°s complemented

(i.e.,

AFTER

BEFORE

1020

105161

000200

1022

000200

o011 | ooo

20176

166
| 000

20200

ADDRESS SPACE

are

012727

MR 4T

Figure 6-17

COMB

200(Rl)

Complement Byte

Symbolic

Octal Code

Instruction Name

ADD

066265
000030

Add

30(R2),20(RS5)

000020

Operation:

The contents of

a location,
6-10

which

are

determined

adding
30
to
the contents of R2, are added to the contents of a
location that is determined by adding 20 to the
contents
of
RS.
The result is stored at the destination address, that is, 20 (RS) .
BEFORE

AFTER

ADDRESS SPACE

1020

066265

1022

000030

1024

000020

1130

2020

1020

066265

1022

000030

1024

000020

000001

1130

000001

2020

000002

1100

ADDRESS SPACE

001100

002000

001100

002000

2000

+30

+20

1130

2020
MR 5475

Figure

6.2.4
also
the

Deferred

6-18

ADD

(Indirect)

30(R2),20(R5)

Addressing - The

be
wused with deferred addressing.
operand
1is
the
contents
of
the

mode

Add

the

contents

modes

may

Whereas in register
selected
register,

four

mode
in

the

basic

selected

operand.

In the three other deferred modes, the contents
of
the
register
select
the address of the operand rather than the operand itself.
These modes are therefore used when a table consists of
addresses
rather
than
operands.
deferred addressing is @
following summarizes the
Deferred Modes

Mode

(Figures

The
assembler
syntax
for
indicating
[or
() when this is not ambiguous].
The
deferred versions of the basic modes.
6-19

6-22)

Assembler
Syntax

Name

Function

Registerdeferred

@Rn

INSTRUCTION

(Rn)
'

the

address

ADDRESS

OPERAND

MR 5476

Figure

6-19

Mode

Name

Mode

Assembler

AutoincrementDeferred
-~

Syntax

@(Rn)+

Function

6-11

first

used

pointer to a word containing
the address of the operand and
then incremented (always by

two, even for byte
instructions).
>

ADDRESS

INSTRUCTION

OPERAND

ADDRESS

MRA.5477

Figure 6-20

Mode 3 Autoincrement-Deferred
Assembler

Name

Mode

Syntax

Function

@~ (Rn)

Autodecrement--

deferred

by two,

even for

byte

instructions) and then used as
a pointer to a word containing
the address of the operand.

INSTRUCTION

-2

ADDRESS

»f

OPERAND

t
MA.-5478

Figure 6-21

Mode 5 Autodecrement-Deferred
Assembler

Mode

Function

Syntax

Name

Value X

Index-deferred @X(Rn)

(stored in a word

following the instruction) and
(Rn) are added; the sum is used
as a pointer to a word
containing the address of the
operand. Neither X nor (Rn) is
modified.

INSTRUCTION

ADDRESS

:
ADDRESS

Figure 6-22

OPERAND

Mode 7 Index-Deferred

The following examples illustrate the deferred modes.
Register-Deferred Mode Example (Figure 6-23)
Symbolic
CLR

@R5

Octal Code

Instruction Name

005015

Clear

6-12

MR-5479

Operation:

The

contents

location

specified

BEFORE
REGISTER

1700

are

cleared.

AFTER

ADDRESS SPACE

1677

in RS

ADDRESS SPACE

001700

1677

000100

1700

000000

@R5

Clear

001700

MR.6480

Figure

6-23

CLR

Autoincrement-Deferred Mode Example
Symbolic
INC

‘

Octal

@(R2)+

Operation:
address

contents

(Mode

Code

are

The

incremented

operand

ADDRESS SPACE

010300

000025

the

one;

the

1010

010302

000026

1012

10300

001010

10300

Figure

6-24

1INC

Autodecrement-Deferred Mode

Symbolic

@(R2)+

Example

001010

Increment

(Mode

(Figure

6-25)

Octal Code

@- (RO)

005150

Operation:
The contents of RO are
used as the address of the address

1°s complemented

(i.e.,

decremented
by
of the operand.

logically complemented).

BEFORE

10100

012345

two
The

and
then
operand is

AFTER

ADDRESS SPACE

10774

1012

10102

address

increased
AFTER

ADDRESS SPACE

COM

the

two.

BEFORE

1010

6-24)

Increment

The contents of R2 are'used
operand.

(Figure

Instruction Name

005232

the

010776

ADDRESS SPACE
10100

165432

010774

10102

010100

10774

10776

010100

10776
MR .6482

Figure

6-25

COM

@-(R0)

Complement

6-13

Index-Deferred Mode Example (Mode 7) (Figure 6-26)

Symbolic

Octal Code

Instruction Name

ADD @1000(R2),R1

067201

add

001000

summed to produce the
Operation: 1000 and the contents of R2 areoperan
d, the contents of
source
address of the address of the
is stored in
result
the
which are added to the contents of Rl;
R1l.

AFTER

BEFORE

ADDRESS SPACE

1020

067201

001234

1020

067201

001236

1022

001000

000100

1022

001000

000100

1050

000002

1050

000002

1100

001050

1100

001050

1024

1000
+100

1100
MR 5482

Figure 6-26

ADD @1000(R2),Rl Add

6.2.5 Use Of The PC As A General-Purpose Register - Although
register 7 1is a general-purpose register, it doubles in function

as the program counter for the DCJ1l. Whenever the processor uses
the program counter to acquire a word from memory, the program

counter is automatically incremented by two to contain the address
of the next word of the instruction being executed or the address
of the next instruction to be executed.

(When

the

program

uses

the PC to locate byte data, the PC is still incremented by two.)

The PC responds to all the standard DCJ1ll addressing modes.
However, with four of these modes the PC can provide advantages

for handling position-independent code and unstructured data.
When utilizing the PC, these modes are termed immediate, absolute
The
(or immediate-deferred), relative, and relative~-deferred.

modes are summarized below.

Mode

Name

Assembler

Syntax

Function

Immediate

Operand follows instruction.

Absolute

Absolute address of operand
follows

instruction.

Relative

Relative-

Relative address (index value)
follows the instruction.

Index value (stored in the word

deferred

after the instruction)

is the

relative address for the
addrecs of the operand.

When a standard program is available for different

users,

|is

often helpful to be able to load it into different areas of memory
and
run
it
1in
those
areas.
The
DCJ1ll
can
accomplish
the
relocation
of
a
program
very
efficiently
through
the use of
position-independent code (PIC), which is written by using the
PC

addressing modes.
If an instruction and its operands are moved in
such a way that the relative distance between them is not altered,
the same offset relative to the PC can be used in all positions in
memory.
Thus, PIC usually references locations
relative
to
the
current

location.

The PC also greatly facilitates the handling of unstructured data.
This is particularly true of the immediate and relative modes.

- Immediate mode

N,DD]

[OPR

Immediate Mode

6.2.5.1

(mode

|is

equivalent
in
wuse
to
the
autoincrement
mode with the PC.
It
provides time improvements
for
accessing
constant
operands
by
including
the
constant
in
the
memory
location
immediately
following

QPR

the

instruction

word.

#n,DD

Immediate Mode Example

(Figure

6-27)

Symbolic

Octal

ADD #10,R0

062700
000010

Operation:

The value

Code

Instruction Name
Add

located

the

second

word

the

instruction
and is added to the contents of RO.
Just before this
instruction is fetched and executed, the PC points
to
the
first

word of the instruction.
The processor fetches the first word and
increments
the
PC
by
two.
The
source
operand
mode
is
27
(autoincrement
the
PC).
Thus,
the
PC is used as a pointer to
fetch the operand (the second word of the instruction)
before
it
is incremented by two to point to the next instruction.
AFTER

BEFORE
ADDRESS SPACE

1020

062700

\RO

1022

000010

1024

000020

ADDRESS SPACE

1020

062700

1022

000010

1024

’///

000030

MR.-5484

Figure

6-27

ADD

#10,R0
6-15

Add

3) is the
6.2.5.2 Absolute Addressing [OPR @ A] - This mode (moderred
using
t-defe
cremen
equivalent of immediate-deferred or autoin
ction
instru
the
ing
the PC. The contents of the location follow
are

the

taken

address

Immediate data is

operand.

the

interpreted as an absolute address (i.e., an address that

constant

executed).

matter

remains

where in memory the assembled instruction is

OPR @#A

Absolute Mode Examples (Figures 6-28 and 6-29)

Symbolic
CLR @#1100

Operation:

Octal Code

Instruction Name

005037

Clear

001100

Clear the contents of location 1100.
AFTER

BEFORE

ADDRESS SPACE

ADDRESS SPACE
20

005037

001100

005037

| 001100

1100

000000

—

1100

177777

1102

CLR @#1100 Clear

Figure 6-28

Symbolic
|

ADD @42000,R3
Operation:

Ar//

MAR-5485

Octal Code

Instrucfion Name

063703

Add

002000

Add contents of location 2000 to R3.
BEFORE

ADDRESS SPACE

063703

002000

AFTER

000500

2000

063703

002000

2000

000300

001000

ADDRESS SPACE

000300

MR.-3406

Figure

6-29

ADD

@4#2000 Add

6.2,5.3

Relative Addressing

[OPR

OPR

X(PC))

- This

mode

(mode
6)
1is
assembled
as index mode using R7.
The base of the
address calculation, which is stored in the second
or
third
word
of
the
instruction,
is
not the address of the operand, but the
number which, when added to the (PC), becomes
the address
of
the
operand.
This
mode
is
wuseful for writing position-independent
code since the location referenced is always fixed
relative to the
PC.
When
instructions are to be relocated, the operan
d is moved
by the same amount.
OPR A or OPR
instruction)

Relative

X(PC)

Addressing

Example

Symbolic
INC

the

1location

(Figure

Octal

relative

Code

Increment

To increment location A, contents of

immediately
following
instruction
word
are
produce address A.
Contents of A are increased
BEFORE

ADDRESS SPACE

005267

1022

000054

AFTER

memory

added
by

location
(PC)

one.

ADDRESS SPACE

1020

0005267

1022

000054

"1024

1024

1026

1100

the

Instruction Name

005267

1020

6-30)

000054

Operation:

000000

1024

f—pC

1100

000001

1100
MR.5487

Figure

6.2.5.4
This
second

6-30

INC

Increment

Relative-Deferred Addressing

mode

word

(mode

instruction,

address
of the
the operand.

the

address

similar

the

to
when

[OPR
added

operand,

OPR @A or OPR @X(PC)
(X is the location
A, relative to the instruction)

(Figure

~-17
i

Example

Relative-Deferred Mode

relative mode,
to

rather

the

6-31)

ex(peC)]
that

the

contains

the

PC,

than

containing

OPR
except
the

the

address

Symbolic
|

CLR €A

Octal Code

Instruction Name

005077

Clear

000020

Operation: Add second word of instruction to updated
produce address of address of operand. Clear operand.
005077

1022

000020

ADDRESS SPACE -

.\\\

é€.2.6

(PC = 1022) 1024

1024

1044

1020

005077

1022

000020

1024

+20

1044

010100

1044

10100

100001

10100

Figure 6-31

AFTER

BEFORE

ADDRESS SPACE

{PC = 1020} 1020

010100

000000

CLR @A Clear

Use Of The Stack Pointer As

General-Purpose

The processor stack pointer (SP, register 6) is in most cases the
general register used for the stack operations related to program
Autodecrement with register 6 "pushes" data onto the
nesting.
stack and autoincrement with register 6 "pops" data off the stack.
Since the SP is used by the processor for interrupt handling, it
has a special attribute: autoincrements and autodecrements are
always done in steps of two. Byte operations using the SP in this

way leave odd addresses unmodified.

6.3

INSTRUCTION SET

The rest of this chapter describes the

DCJ11“s

instruction

set.

the instruction’s
includes
explanation
instruction®s
- Each
the format of
showing
diagram
a
code,
mnemonic, octal code, binary
n and.
executio
its
ng
describi
the instruction, a symbolic notation
effect on the condition codes, a

and

description,

special

comments,

examples.

When
Each instruction”s explanation is headed by its mnemonic.
also
mnemonic
byte
the
nt,
equivale
byte
a
has
ion
instruct
word
the
appears.

The diagram that accompanies each instruction shows the octal op
[Note that in byte
and bit assignments.
code, binary op code,
instructions the most significant bit (bit 15) is always a one.]
Symbols:

src

source

dst

destination

loc

location

<--

becomes

< > e >

"is

popped

from

stack"

"is

pushed

onto

stack"

contents

]

boolean OR

exclusive

boolean
or

REG

Byte

B
+

boolean AND

()

for

address

not

word,

for

detailed

information.

Single-Operand

(Figure

byte

concatenated

6.3.1
Instruction Formats - The
instructions
wused in the DCJ11l.

for

address

6-32)

Group:

following
formats
Refer to individual

CLR,

CLRB,

COM,

DEC,
SBC,
ROL,

COMB,

DECB,
SBCB,
ROLB,

INC,

NEG,
TST,
ASR,

INCB,

JMP,

NEGB,
TSTB,
ASRB,

SWAB,

ADC,
ROR,
ASL,

MFPS,

ADCB,
RORB,
ASLB,

TSTSET,

WRTLCK,

15
L4

{

j —

MTPS,

Figure
2.

}

6-32

SXT,

XOR
05
¥

{

OP CODE
R

include
all
instructions

DD(SS)
i

Single-Operand Group

Double-Operand Group:
a.

Group

(Figure

6-33)

BIT,

BITB,

ADD,

SUB, MOV,

BIC,

BICB,

MOVB,

BIS,

CMP,

BISB,

CMPB

OP CODE

MR 5192

Double-Operand Group 1

Figure 6-33

ASH, ASHC, DIV, MUL

b. Group 2:

(Figure 6-34)

00
1

MR 11554

Double-Operand Group 2

Figure 6-34
3.

Program Control Group:

Branch (all branch instructions)

OP CODE
5

]

——

(Figure 6-35)

OF FSET

}

MR 5193

Figure 6-35

15 .

;

)
S

Program Control Group JSR

(Figure 6-37)

Subroutine Return (RTS)

Figure 6-36

(Figure 6-36)

Jump to Subroutine (JSR)

Program Control Group Branch

2
o

- 03

MA-5195

Program Control Group RTS

Figure 6-37

Traps (breakpoint, IOT, EMT, TRAP, BPT) (Figure 6-38)
00
) §

OP CODE
e

MRA.5196

Figure 6-38

Program Control Group Traps

Subtract 1 and Branch (if = 0)

(SOB)

(Figure 6-39)

MR.5197

Figure

6-39

Mark

Program Control

(Figure

Group Subtract

6-40)

Figure
g.

Call

6-40

Supervisor

V1548

Mark

Mode

(CSM)

(Figure

6-41)

15
[

0
| —

]

6-41

Call

Set

15 :

{

}

Figure

]

{

to Supervisor Mode

Priority Level

(SPL)

(Figure 6-42)

03
|S

00
1

{

MR-11880

Figure
4.

6-42

Operate Group:
(Figure 6-43)

Set

HALT,

Priority

WAIT,

Level

RTI,

RESET,

RTT,

NOP,

MFPT

15
00

OP CODE

Figure 6-43
5.

Figure
6.

(all

condition

6-44

code

lon

Condition Group

Move To/From
Previous

Instruction/Data

Space Group:

MTPD,

MTPI,
6-21

MFPD,

'
MR 8198

Operate Group

Condition Code Operators
(Figure 6-44)

MFPI

instructions)

| v

|¢

(Figure 6-45)
T

{

DD(SS)
]

MAR-1158)

a Space Group
Figure 6-45 Move To And From Previous Instruction/Dat

l complement of
DCJ11l includes .a fulSinc
tructions - The
6.3.2 Byte Insthat
e all DCJ1ll
manipulate byte operands

instructions
essing is
d, byte manipulation addr
addressing is byte-orienteinst
ructions with autoincrement or

Byte
straightforward.
ified register to be
essing cause the specbyte
autodecrement directto addr
of data. Byte
point to the next
modified by one
of the
access the low-order byte
operations in register modee prov
orm
perf
to
l
isions enable the DCJ1 me for word
Thes
specified register. byte
sche
g
processor. The numberin
as either a word or
6-46.
and byte addresses in memory is shown in Figure
WORD OR BYTE

HIGH BYTE

ADDRESS

002001

BYTE 1

BYTE O

002000

002003

BYTE 3

BYTE 2

002002

MA-5201

Figure 6-46

Byte Instructions

The most significant bit (bit 15) of the instruction word
to indicate a byte instruction.

Example:

Symbolic

Octal Code

Instruction Name

CLR
CLRB

0050DD
1050DD

Clear word
Clear byte

1is set

6.3.3
List Of Instructlons - The
instruction set.

follOW1ng

list of

SINGLE-OPERAND

General
Mnemonic

CLR (B)
COM (B)
INC (B)

Instruction

Op Code

Clear destination
Complement destination
Increment destination

DEC (B)

Decrement

destination

NEG (B)
TST (B)

Negate

WRTLCK

Read/lock destination,
write/unlock RO into
destination

Shift

B 053DD
@ 054DD
B 057DD

destination
destination

Test

TSTSET

B 050DD
W 051DD
B 052DD

Test

destination,

set

low

bit

0073DD
0072DD

and Rotate

Mnemonic

Instruction

ASR (B)
ASL (B)

Arithmetic
Arithmetic

ROR (B)
ROL (B)
SWAB

Rotate

right

Rotate

left

Swap

Op Code

shift
shift

right
left

bytes

W 062DD
W 063DD
B 060DD
B 061DD
0003DD

Multiple-Precision
Mnemonic

Instruction

Op Code

ADC (B)
SBC (B)
SXT

Add

W 055DD

Word

Mnemonic

carry

Subtract

Sign

carry
extend

B 056DD
0067DD

Operators
Instruction

Op Code

MFPS

Move

byte

MTPS

from

Move

byte

1067DD
1064SS

DOUBLE-OPERAND

General
Mnemonic

Instruction

Op Code

MOV (B)
CMP (B)
ADD

Move source to destination
Compare source to destination
Add source to destination

B 1SSDD

6-23

B 2SSDD
06SSDD

the DCJ11

SUB
ASH
ASHC

Subtract source from destination
Arithmetic shift
Arithmetic shift combined

16SSDD
072RSS
073RSS

MUL

Multiply
Divide

070RSS
071RSS

DIV

Logical
Mnemonic

Instruction

Op Code

BIT (B)

Bit test
Bit clear
Bit set
Exclusive OR

B 3SSDD
B 4SSDD

BIC (B)

BIS (B)
XOR

PROGRAM

#l 5SSbD

07 4RDD

CONTROL

Op Code
or

Mnemonic

Instruction

Base Code

Branch

BVS

Branch
Branch
Branch
Branch
Branch
Branch
Branch

if minus
if overflow
if overflow

BCC

Branch

carry

BCS

Branch

carry

BR
BNE

BEQ
BPL
BMI

BVC

Signed Conditional

(unconditional)
if not equal (to zero)
if equal (to zero)
if plus

is
is

clear
set
clear
set

000400
001000
001400
100000
100400
102000
102400
103000
103400

Branch
Op Code
or

Mnemonic

Instruction

BGE

Branch if
(to zero)
Branch if

BLT
BGT

BLE

Base Code

greater

than

equal

less than (zero)
Branch if greater than (zero)
Branch if less than or equal
(to zero)

Unsigned Conditional

002000
002400

003000
003400

Branch
Op Code
or

Mnemonic

Instruction

BHI

Branch
Branch

if
if

higher
lower or

Branch
Branch

if
if

higher
lower

BLOS
BHIS
BLO

Base Code

same
same

101000
101400

103000
103400

Jump

and

Subroutine

Op Code
Mnemonic

JMP
JSR
RTS

Base Code

Jump

Jump to subroutine
Return from subroutine
Subtract one and branch

SOB

Trap

Instruction

and

(if

0001DD
004RDD
00020R
077R00

Interrupt

Op Code
or

Mnemonic

Instruction

EMT
TRAP

Trap

BPT

Breakpoint

I0T

Input/output trap
Return from interrupt

RTI

RTT

Emulator

Return

Miscellaneous

Base Code

trap

104000
104400

trap

from

104377
104777

000003
000004
000002

interrupt

000006

Program Control
Op Code

Mnemonic

Instruction

CSM

Call

MARK

Mark

SPL

Set

Base Code

supervisor

Priority

- 0070DD

mode

006 4NN

Level

00023N

MISCELLANEOUS
Op Code
Mnemonic

Instruction

Base Code

HALT

Halt

WAIT

Wait

for

RESET

Reset

MFPT

external bus
processor type
.
to previous data space
to previous instruction

000000
000001

interrupt

MTPD

Move
Move

MTPI

Move

MFPD

Move

from previous

data

Move

from

instruction

space

MFPI

space

CONDITION

CODE

space

000005
000007
1066SS
0066SS
0065SS

1065SS

OPERATORS
Op Code

Instruction

CLC
CLV
CLZ

Clear
Clear
Clear

CLN

Clear

FAS RN

Mnemonic

Base Code

000241
000242
000244
000250

cccC

Clear all CC bits

000257

Set 2
Set N
Set all CC bits

000264
000270
000277

000261
000262

Set C
Set V

SEC
SEV

SEZ
SEN
sCC

NOP

No operation

6.3.4

involve

000240

Single-Operand Instructions - The DCJ1ll'
only

one

operand

are

described

instructions

that

in the paragraphs that

follow.

CLR
CLRB
CLEAR DESTINATION

805000

06
T

|
1

00
1

L
MR 11504

Operation:

(dst)

Condition Codes:

Description:

cleared

set

V:
C:

cleared
cleared

Word:

The contents of

Byte:

Same.

are

Example:

<--

replaced with 0s.

the specified destination
|

CLR Rl
Before

After

(R1) = 177777

(R1) = 000000

NZVC
1111

NZVC
0100

COM

COMB
COMPLEMENT DST

15
0/1

:
O<

05100

,
0

.
0

06
1

Operation:

(dst)

Condition Codes:

<=-=-

set if

(dst)

most

significant
6-26

bit

result

set;

Description:

Z:
V:

cleared otherwise
set if result is 0;
cleared
.

set

cleared

.
otherwise

Word: Replaces the contents of the destination
address by their logical complement.
(Each bit
equal to 0
Ccleared.)
Byte:

Example:

COM

set

and

each

bit

equal

Same.

Before
(RO)

After’
013333

(RO)

NZVC

0110

1001

164444

INC

INCB
INCREMENT DST

n0520D

Operation:

;

Condition Codes:

Description:

Example:

(dst) <--

(dst) + 1

set

result

Z:
V:

set
set

if
if

not

affected

‘

is < 0; cleared otherwise
result is 0; cleared otherwise
(dst) held 077777; cleared otherwise

Word:

Add

Byte:

Same.

INC

the

contents

the

destination.

Before
(R2)

After

000333

(R2)

NzZVC

NZVC

0000

000334

DEC

DECB
DECREMENT DST
1¢

05300

Operation:

(dst)

Condition Codes:

set

<=-

(dst)

-1

result

6-27

0:;

C;D

cleared

otherwise

set if result is 0;

V:
C:
Description:

set
not

if (dst) was
affected

Word: Subtract
destination.
Byte:

Example:

DEC

cleared otherwise

100000;

from

cleared otherwise

the contents

the

Same.

Before

(R5)

After

000001

(RS)

NZVC

000000

NZVC

1000

0100

NEG

NEGB
NEGATE DST

15 .

0/1

0054DD

Operation:

(dst)

Condition Codes:

N:
Z:
V:
C:

Description:

Word:

<--

;

(dst)

set if result is < 0; cleared otherwise
set if result is 0; cleared otherwise
set if result is 100000; cleared otherwise
cleared if result is 0; set otherwise

Replaces the contents of the destination
address by its 2°s complement. Note that 100000
is replaced by itself. (In 2°s complement
notation the most negative number has no
positive counterpart.)
Byte:

Example:

Same.

NEG RO

Before
(RO)

After

000010

(RO)

NZVC

177770

NzZVC

0000

1001

TST
TSTB

TEST DST

05700

16
0/1

Operation:

.
0

(dst)

06
0

<--

(dst)

00
DD

Condition Codes:

Description:

2:
V:

set if result
set if result
cleared

cleared

Word:
to

Sets

the

contents

Byte:

Example:

TST

the

contents
of

condition

dst

cleared

otherwise
otherwise

codes N

and

the

destination

remain

unmodified.

Same.

according

address;

the

Before
(R1)

After

012340

(Rl)

NZVC

012340

NZVC

0011

0000

WRTLCK
READ/LOCK DESTINATION

WRITE/UNLOCK RO INTO DESTI
NATION

007300

15
T

0
|S

(dst)

Condition Codes:

set

Operation:

Description:

<--

)

}

)

if RO
cleared

unchanged

)
MR 11498

(RO)

= 0

Writes contents of
bus lock.
If mode

RO
is

into destination
0, traps to 10.

using

TSTSET
TEST DESTINATION AND SET LOW BIT

007200

15
1

o]
L

0
1

1
1

Operation:

(RO)

Condition Codes:

N:
Z:

Description:

{

<=-

set
set

)

cleared

gets

RO
RO

<
=

00
I

)

(dst),

if
if

(dst)

<--

(dst)
V 000001

(octal)

O
0

contents

destination

bit

Reads/locks destination word and stores it
in RO.
Writes/unlocks (R0O) V 1 into
destination.
If mode is 0, traps to 10.

6-29

two

Shifts And Rotates - Scaling data by factors

6.3.4.2

accomplished by the shift instructions:

|is

ASR -- Arithmetic shift right
ASL -- Arithmetic shift left

shifts to
The sign bit (bit 15) of the operand is reproduced inshifts
to the
The low-order bit is filled with 0s in
the right.
left. Bits shifted out of the C bit, as shown in the
instructions,

following

are lost.

The rotate instructions operate on the destination word and the C
bit as though they formed a 17-bit "circular buffer."” These
instructions facilitate sequential bit testing and detailed bit

manipulation.
ASR

ASRB
ARITHMETIC SHIFT RIGHT

006200

MA 11502

Operation:

(dst) <-- (dst) shifted one place to the right

Condition Codes:

N: set if high-order bit of result is set
72:
V:

cleared otherwise

0);

(result <

set if result = 0; cleared otherwise
loaded from exclusive OR of N bit and C bit
(as set by the completion of the shift

operation)

loaded from low-order bit of destination

Word: Shifts all bits of the destination right

Description:

one place.

The C bit is

Bit 15 is reproduced.

loaded from bit 0 of the destination.

ASR

performs signed division of the destination by
2.
Byte:

Same.

Example:

BYTE:

00D ADDRESS
T

‘

EVEN ADDRESS

n
MA 5200

ASL
ASLB

ARITHMETIC SHIFT LEFT

#063D0D

MR 11510

Operation:

(dst)

Condition Codes:

<--

set

(dst)

high-order

(result
Z:

set

if
loaded

(as

shifted

0);

Description:

place

result

bit

cleared

set

loaded

the

left

set

= 0; cleared otherwise
exclusive OR of N bit and

the

with

otherwise

result

with

completion

operation)

one

,
bit

high-order

the

bit

shift

destination

Word: Shifts all bits of the destination left
one place.
Bit
0 is loaded with a 0.
The C bit

the status word
significant bit of

is loaded from the most
the destination.
ASL

performs a signed multiplication of the
destination by 2 with overflow indication.

Byte:

Same.

Example:
WORD.
15

jpo—
A

-0

j —

}

j —

BYTE.
15

ODD ADDRESS

of
L

EVEN ADDRESS

jo—

-0

J E——

]

[ —

MA 521

ROR
RORB
ROTATE RIGHT
060DD

15
T

0
i

0
|

0
{

]

0
1

[¢
|

]

{

Operation:

(dst)

Condition Codes:

set if high-order bit
(result < 0); cleared

Z2:

set if all
otherwise

C:
Description:

<--

(dst)

rotate

bits

one

of result
otherwise

result

11500

place

set

cleared

loaded

with exclusive OR of N bit and C
(as set by the completion of the rotat
e
operation)
loaded with low-order bit of destinatio

bit

Word: Rotates all
place.
Bit 0

one

the

right

bits of the destination right
is loaded into the C bit and

contents

6-31

the C

bit

are

loaded

into bit 15 of the destination.
Same.

Byte:

Example:
WORD:

15
c

{

|—

BYTE:

{

oDO
-l

))

;

[
07

EVEN
1

i
MR 521)

ROL
ROLB

s06100D

ROTATE LEFT

0/1

0
{

)

DD
MRA.11509

(dst) <-- (dst) rotate left one place

Operation:

condition Codes:
-

N: set if high-order bit of result word is set
(result < 0); cleared otherwise
2: set if all bits of result word = 0; cleared
otherwise

V: loaded with exclusive OR of the N bit and C
bit

Description:

operation)

loaded with high-order bit of destination

Word: Rotates all bits of the destination left

Bit 15 is loaded into the C bit of
one place.
the status word and the previous contents of the
C bit are loaded into bit 0 of the destination.
Byte:

Example:

(as set by the completion of the rotate

Same.

WORD:

D5T
i

jo—o
-

]

BYTE:

15
T

j—

ODD
d

07
T

EVEN
i

MR.5215

SWAB
SWAPBYTES

0003DD

15
1

{

Sma—

)

[

MR.11508

Operation:

byte

1/byte

Condition Codes:

set if high-order bit of low-order byte
7) of result is set; cleared otherwise

set

<--

byte

low-order

byte

otherwise
V: cleared

Description:

Example:

high-order

the

destination

word

address.)

SWAB

(R1)

6.3.4.3

byte

word.

077777

example,

two

(R1)
NZVC

1111

0000

operations

operands

cleared

low-order

destination

and

words

added

may

6--33

byte
must

of
be

177577

sometimes

considered

special provision
(add
carry)
and

16-bit

word

and

(The

NZVC

bytes.
The DCJ1ll makes
the
instructions
ADC
their byte equivalents.
For

After

Multiple-Precision -

double-precision

result

(bit

Before

arithmetic

cleared

Exchanges
|

0/byte

for
SBC

do
or

such operations with
(subtract carry) and

combined

subtracted

necessary

as multiple words

into

shown

32-bit

below.

32.8IT WORD
.

(

OPERAND

)

(
OPERAND

31
B1

A
.

RESULT

MR.5217

Example:

The addition of -1 and -1 could be performed as follows.
-1 = 37777777 777

(R1) = 177777

(R2)

(R3)

= 177777

(R4)

177777
ADD

R1,R2

ADC
ADD

R3
R4 ,R3

After (R1l) and (R2) are added, 1 is loaded into the C bit.
The ADC instruction adds the C bit to (R3); (R3) = 0.

2.
3
4

The
The

(R3) and (R4) are added.
result is 37777777776, or =2.

ADC
ADCB
ADD CARRY

805500

15
01

.
0

Operation:

(dst)

Condition Codes:

N:
Z:

06
1

<--

(dst)

00
DD

(C bit)

set if result < 0; cleared otherwise
set if result = 0: cleared otherwise
set if (dst) was 077777 and (C) was 1;
cleared otherwise
set if (dst) was 177777
cleared otherwise
6-34

and

(C)

was

Description:

Word: Adds the contents of the
C bit to the
destination.
This permits the carry from the
addition of the low-order words to be carried
the high-order result..

Byte:

Example:

Same.

Double-precision addition may be done with
following instruction sequence.
ADD
ADC
ADD

AQ0,BO
Bl
Al,Bl

the

sadd low-order parts
sadd carry into high-order
;add high-order parts

SBC
SBCB
SUBTRACT CARRY

15 1
on

T
0

805600

L
0

Operation:
Condition

A8
0

1
1

1
0

(dst)
Codes:

T
1

<=-=-

06
1

(dst)

(C)

set

result

Z:
V:
C:

set
set
set

if
if
if

result = 0; cleared otherwise
(dst) was 100000; cleared otherwise
(dst) was 0 and C was 1l; cleared

cleared

otherwise

otherwise
Description:

Word:
the

Subtracts

the

destination.

the subtraction
subtracted from

contents

This

permits

the C
the

bit

carry

of two low-order words
the high-order part of

from
from

to be
the

result.
Byte:

Example:

Same.

Double-precision
SUB

A0,BO

SBC
SUB

Bl
Al,Bl

subtraction

done

by:

SXT
SIGN EXTEND

006700
06
T

MR.11574

Operation:

(dst)
(dst)

Condition Codes:

N:
Z:

not
set

cleared

not

affected

the

condition

Description:

<-<--

0
1

if N
if N

affected
if N bit

bit
bit

6-35

is
is

clear
set

clear

code

bit N

set,

-1

laced in the destination operand; if the N bit

is clear, a 0 is placed in the destination
This instruction is particularly
operand.
useful in multiple-precision arithmetic because
it permits the sign to be extended through

multiple words.
A

SXT

Example:

Before

After

(A) = 012345

(AYy = 177777

NZVC

1000

PS Word Operators -

6.3.4.4
MFPS

10670D

MOVE BYTE FROM PROCESSOR STATUS WORD

15
1

lower

dst

Condition Codes:

00
1

<-- PS

(dst)

Operation:

8 bits

N: set if PS <7> = 1; cleared otherwise

72: set if PS <7:0> = 0; cleared otherwise
cleared

not affected

The 8-bit contents of the PS are moved to the

Description:

If the destination is
effective destination.
mode 0, PS bit 7 is sign-extended through the
The destination
upper byte of the register.
operand address is treated as a byte address.
MFPS RO

Example:

After

Before

RO
PS

[0]
[000014]

RO
PS

[000014]
[000000]

MTPS
MOVE BYTE TO PROCESSOR STATUS WORD

—_—

10645S

'
MA-11498

Operation:

<=--

(src)
6-36

Condition Codes:

Set according
<3:0>

to effective SRC operand

Description:

The eight bits of

the effective operand

replace

the current contents of the lower byte of the
PS.
The source operand address is treated as a
byte address.
Note: The T bit (PS bit 4)
cannot be set with this instruction.
The SRC
operand remains unchanged.
This instruction can
be used to change the priority bits (PS bits
/

Example:

<7:5>)

kernel

mode,

MTPS

the PS only in
PS

bits

kernel mode.

<7:5>

cannot

not

changed.

Before
(R1)
(PS)

6.3.5

bits

=
=

After
000777
XXX000

(R1)
(PS)

NZVC

0000

1111

Double-Operand

=
=

000777
XXX357

Instructions - Double-operand

save
instructions
(and
time)
since they eliminate
"load"
and
"save"
sequences
such
as
those
accumulator-oriented machines.

instructions

the need
used

for
in

MOV
MOVB
MOVE SOURCE TO DESTINATION
15

12
Y

0
G

0
"

«1SSDD

06
T

00
Y

MR-11497

Description:

set

cleared

not

(src¢)
(src)

(src¢)
OO

Condition Codes:

<--

-e

(dst)

Operation:

cleared
cleared

otherwise
otherwise

affected

Word: Moves the source operand to the
destination location.
The previous contents of
the destination are lost.
Contents of the
source address are not affected.
Byte: Same as MOV.
The MOVB to a register
(unique among byte instructions) extends the
most significant bit of the low-order byte (sign

6-37

Otherwise, MOVB operates on bytes

extension).

exactly as MOV operates on words.

sloads register 1

MOV XXX,Rl

Example:

with the contents of
memory location; XXX
a

represents

programmer-defined
to

mnemonic used

a memory

represent

location

:1loads the number 20

MOV %#20,R0

. into register 0; #
indicates that the
value 20 is the
operand

spushes the operand

MOV @#20,-(R6)

stack

a stack and moves it
into memory location
177566 (terminal
print buffer)

;performs an

MOV R1l,R3

MOVB

the

;pops the operand off

(R6)+,@#177566

MOV

onto

location

contained

inter-register
transfer

@#177562,0%#177566

smoves a character

from the terminal
keyboard buffer to
the terminal printer
buffer

CMP
CMPB
825SDD

COMPARE SRC TO DST

{

]

)

(310)

0
4

MR.11562

Operation:

(src)

Condition Codes:

2:
V:

(dst)

set if result < 0;

cleared otherwise

set if result = 0; cleared otherwise
set if there was arithmetic overflow; that
is, operands were of opposite signs and the
sign of the destination was the same as the
sign of the result; cleared otherwise

cleared

there was

a carry

from

result’s most significant bit;

6-38

the

set otherwise

Description:

Compares

the

sets

condition

the

source

for

arithmetic

Both

operands

set

and

destination operands and
which may then be used
logical conditional branches.
codes,

and
are

not

affected.

The

the condition codes.

customarily followed by a
instruction. Note: Unlike

only

action

The compare

conditional

branch

the subtract
instruction, the order of operation is
(src) - (dst), not (dst) - (src).

ADD
ADD SRC TO DST

)

(dst)

Condition Codes:

set

result

cleared

Z2:

set

result

set

cleared

there

(src)

result

operands

was
set

Adds

(dst)

otherwise

otherwise
arithmetic overflow as a
operation; that is, both
of the same sign and the result

was

the
were

of
if

the opposite sign; cleared otherwise
there was a carry from the result’s
significant bit; cleared otherwise

most

Description:

MR- 11583

Operation:

<--

the

operand

source
and

operand

stores

the

result

destination
at

the

destination

address.
The original contents
of the
destination are lost.
The contents of
source

are

not

affected.

addition is performed.
equivalent byte mode.
Example:

Two”s

Note:

the

complement

There

Add

to register:

ADD

20,RO

Add

ADD

Rl ,XXX

Add

ADD

R1l,R2

Add

memory

ADD

@#17750,XXX

XXX

memory

memory:

programmer-defined

location,

mnemonic

for

SUB
SUBTRACT SRC FROM DST
16

Operation:

’
1

16SSDD
.

(dst)

<--

(dst)

6-39

(src)

. get if result < 0; cleared otherwise
. set if result = 0; cleared otherwise
. set if there was arithmetic overflow as a

Condition Codes:

result of the operation; that is, if operands
were of opposite signs and the sign of the
source was the same as the sign of the
result; cleared otherwise

C: cleared if there was a carry from the

result’s most significant bit; set otherwise

Subtracts the source operand from the
destination operand and leaves the result at
the destination address. The original
contents of the destination are lost. The
contents of the source are not affected. 1In
double-precision arithmetic the C bit, when
set, indicates a "borrow." Note: There is no

Description:

equivalent byte mode.

SUB R1,R2

Example:

ASH

Before

After

(R1) = 011111
(R2) = 012345

(R1) = 011111
(R2) = 001234

NzVC
1111

NZVC
0000

072RSS

ARITHMETIC SHIFT
15

]

MR- 11660

Operation:

R <-- R shifted arithmetically NN places to
the right or left where NN = (src)

Condition Codes:

N:
2:

set if result < O
set if result = 0

V: set if sign of register changed during shift
C: loaded from last bit shifted out of register
Descriptions:

The contents of the register are shifted right
or left the number of times specified by the
source operand. The shift count is taken as the
low-order six bits of the source operand. This
number ranges from -32 to +31. Negative is a
right shift and positive is a left shift.

ASHC

ARITHMETIC SHIFT COMBINED

s073RSS
09

MA.11661

Operation:.

R, RV1<--R, RV
1

The double word is shifted NN places
right or left where NN = (src)

Description:

A<
TM

Condition Codes:

set
set

if
if

result
result

set

sign bit changes during

<
=

the

0
0

shift

loaded with high-order
bit when left shift;
loaded with low-order bit when right shift
(loaded with the last bit shifted out of
the 32-bit operand)

The contents of the register and the register
ORed with 1 are treated as one 32-bit word.
R v 1l (bits<15:0>) and R (bits<31:16>) are

shifted right or left the number of times
specified by the shift count.
The shift count
is taken as the low-order six bits of the

source

to
is

operand.

This

+31.
Negative
a left shift.

When the
register
same.

number

ranges

right

shift

this

case,

the

right

from

and

=32

positive

odd number, the
with 1 are the
shift

becomes

rotate.,
The 16-bit word is rotated right the
number of times specified by the shift count.

MUL
MULTIPLY

070RSS
C9
I

06
I

00
1

{

Operation:

Condition Codes:

N:
Z:
V:
C:

RVv1l

(src)

set if product < 0
set if product = 0
cleared
set if the result is
Oor

Description:

«<==-

greater

1157,

than

less

equal

than
to

-2

**]15

The

contents of the destination register and
source taken as 2°s complement integers are
multiplied and stored in the destination
register and the succeeding register, if R is

even.

is stored.
(Note that

which

odd,

only

Assembler
the actual

reduces

the

low-order

syntax is: MUL
destination is

just R when R

6-41

product

S,R.
R, R

odd.

DIV
071RSS

DIVIDE

1§

Operation:

RV1

Condition Codes:

N: set if quotient < 0

<-- R,

{

RV1/(src)

set if quotient = 0
set if source = 0 or if the absolute value
of the register is larger than the absolute
value of the instruction in the source. (In
this case the instruction is aborted because
the quotient would exceed 15 bits.)
set if divide by zero is attempted.

Z:
V:

The 32-bit 2°s complement integer in R and
R v 1l is divided by the source operand.
The
gquotient is left in R; the remainder is of the
same sign as the dividend.
R must be even.

Description:

6.3.5.2 Logical - These instructions
have
those
in
the
double-operand
arithmetic

operations on data

the

bit

level.

the
same
format
a
group.
They
permi

BIT
BITB
BIT TEST

]

15
on

12
0

(src) /\ (dst)

Condition Codes:

N:
Z:
V:
C:

Description:

Operation:

set

00
DD

if high-order

otherwise
set if result

a3SSDD

bit of

result

set;

cleared

cleared otherwise

cleared
not affected

Performs

logical AND comparison of

the source

and destination operands and modifies condition

codes accordingly.
Neither the source nor the
destination is affected.
The BIT instruction

may be used to test whether

any of

the

corresponding bits set in the destination are
also set in the source, or whether all
corresponding bits set in the destination are
clear in the source.

Example:

BIT

#30,R3

stest bits
to

000

see
011

three
both

and

are

four

of R3

off.

000

Before

After

NZVC
1111

NzZVC
0001

'BIC
BICB
8IT CLEAR

84SSDD

(dst)

Condition Codes:

set

<-=-

(dst)

high-order

otherwise
set if result

cleared

not

Clears

“(src)

bit

the

result

cleared

set;

each

original

bit
to

otherwise

bit

the

contents

The

contents

BIC

R3,R4

destination

set

the

that

source.

destination

source

Before

are

not

are

(R3)

001234

(R3)

001234

(R4)

001111

(R4)

000101

NZVC

1111

0001
(R3)
= 0
= 0

000

001
001

010
001

011l
001

001

(R4)

000

001

000

001

(R4)

After:

000

100

BIS

BISB
BIT SET

e5550D

Operation:

(dst)

<--

(src)

6-43

(dst)

The

lost.

affected.

After

Before:

cleared

affected

corresponds

Example:

Operation:

Description:

Condition Codes:

N: set if high-order bit of result set; cleared
2:

Description:

otherwise

set if result = 0;

cleared

not

cleared otherwise

affected

Performs an inclusive OR operation between the
source and destination operands and leaves the
result at the destination address; *hat is,

corresponding bits set in the source are set in
The contents of the

the destination.

destination are lost.
Example:

RO,R1

BIS

Before

After

(RO) = 001234
(R1) = 001111l

(RO)
(R1)

NZVC

= 001234
= 001335

0000

Before:

(R1)

0
0

000 001 010 01l 100
000 001 001 001 001

(R1)

000 001 011 011

(RO)

After:

101

XOR
074RDD

EXCLUSIVE OR

00
¥

MR.1186¢

<-=

#
(reg)

(dst)

Operation:

(dst)

Condition Codes:

N: set if result < 0; cleared otherwise
2: set if result = 0; cleared otherwise

Description:

cleared

not affected

The exclusive OR of the register and destination

operand is stored in the destination address.
The contents of the register are not affected.

The assembler format is XOR R,D.
XOR

RO,R2

After

Before

NzZVC
1111

(RO)
(R2)

= 001234
= 001111

(RO)
(R2)

Example:

NzVC

0001

= 001234
= 000325

Before:

(RO)

0
0

(R2)

After:

6.3.6

Program

Control

6.3.6.1

Branches - These

the

The
PC,

instructions

current
1.

The

contents
branch

sum

the

word

Although

the

offset

the

program

instruction

is conditional and
testing the condition

011
001

100
001

following

that affect

instructions

the

offset is the number
forward or backward.

point

010
001

Instructions - The

the DCJ1l

defined

001
001

(R2) = 0 000 000 011 010 101

describe

location

000
000

program

cause

offset

counter

paragraphs

control.

branch

(multiplied

unconditional.

the conditions
codes (NZVC).

the

expresses

branch

and

if:

are

met

after

of words from the current contents
Note that the current contents of

following

byte

instruction.

address,

the

of the
the PC

expressed

in
words.
The
offset
is automatically
multiplied
by
2 and
sign-extended to express words before it is added to the PC.
Bit
7 is the sign of the offset.
1If it is set, the offset is negative
and the branch is done in the backward direction.
If
it
is
not
set,

the

offset

positive

and

direction.

the

branch

done

the

forward

The 8-bit offset allows branching in the backward direction by
(octal)
words
(400
octal bytes) from the current PC, and in
forward direction by 177 (octal) words (376 octal bytes) from
current

and

the

PC.

The DCJ11 assembler'typically handles address arithmetic
user

200
the

computes

instructions

and

the

assembles

the

form:
Bxx

proper

offset

field

for
for

the

branch

loc

Bxx is the branch instruction and loc
branch
1is to be made.
The assembler
the instruction if
the
permissible

is the address
gives an error
branch
range

to which
the
indication in

is
exceeded.
Branch
instructions
have
no
effect
on
condition
codes.
Conditional branch instructions where the branch condition is
not
met

are

treated

NOPs,

BR
BRANCH (UNCONDITIONAL)

0
A

0
i

0
1

000400
PLUS OFFSET

0
g

0
1

1
J

OFFSET
4

-t

-y

MR 523

Operation:

PC <-- PC +

Condition Codes:

Not

Description:

offset)

affected

Provides a way of transferring program control

within a range of -128 to +127 words with a

one word

instruction.

New PC address = updated PC + (2 X offset)

Updated PC = address of branch ihstruction +2
With the branch instruction at location 500, the

Example:

following offsets apply.-

Offset Code

New PC Address

001000 PLUS OFFSET

BRANCH IF NOT EQUAL (TO ZERO)

o o

-2
-1
0
+1
+2

376
377
000
001
002

476
500
502
504
506

375

474

BNE

Offset (decimal)

OFFSET

Opefation:

PC <-- PC + (2 X offset) if 2 = 0

Condition Codes:

Not affected

Description:

Tests the state of the 2 bit and causes a branch

BNE is the complementary
if the 2 bit is clear.
used to test: (1)
is
It
operation of BEQ.

(2) that some bits

inequality following a CMP,

set in the destination were also in the source
following a BIT operation, and (3) generally,

that the result of the previous operation was

not

Example:

Branch to C if A ¢ B
CMP
BNE

A,B
C

;jcompare A and B
sbranch if they are not equal

Branch to C if A + B # 0
ADD A,B

BNE C

t;add A to B

sbranch if the result is not
equal

to 0

BEQ
BRANCH IF

EQUAL (TO ZEROI

001400
PLUS OFFSET

08
T

<--

00
T

OFFSET

MR 52233

Operation:

Condition Codes:

Not

Description:

Tests the state of the 2 bit and causes a branch
if 2 is set. It is used to test:
(l) equality
following a CMP operation,
(2) that no bits set
in the destination were also set in the source

affected

following a BIT
that the result

Example:

offset)

operation, and (3) generally,
of the previous operation was

Branch to C if A = B

(A - B = 0)

CMP

A,B

;compare

and

BEQ

sbranch

they

Branch

ADD
BEQ

A,B
C

)

B
are

equal

sadd A to B
sbranch if the

result

BPL
BRANCH IF PLUS

100000
PLUS OFFSET

’

OFFSET

Operation:

PC <-- PC + (2 X offset) if N = 0

Condition Codes:

Not

Description:

Tests the state of the N bit and causes a branch

affected

clear

(positive

result).

complementary

if N

operation

BPL

the

BMI.

BMI
BRANCH
IF MINUS

100400 PLUS OFFSET

Condition Codes:

Not

Description:

<==

00
B

OFFSET

1
ke

0
1

Operation:

offset)

MR 5235

affected

Tests the state of the N bit and causes a branch
if

set.

6-47

used

test

the

sign

(most

significant bit) of the result of the previous
BMI is the
operation), branching if negative.
complementary function of BPL.

BVC

102000 PLUS OFFSET

BRANCH IF OVERFLOW IS CLEAR

15
1

)

]

)

-1

]

OFFSET

MR.5236

(2 X

if V=20

offset)

Operation:

PC <-- PC +

Condition Codes:

Not

Description:

Tests the state of the V bit and causes a branch

affected

is clear.

the V bit

operation

BVC

is complementary

to BVS.

BVS

102400 PLUS OFFSET

BRANCH IF OVERFLOW !SSET

00
1

OFFSET
.

MR 5237

<-- PC +

if Vv

offset)

Operation:

Condition Codes:

Not

Description:

Tests the state of the V bit (overflow) and
causes a branch if V is set.
BVS is used to
detect arithmetic overflow in the previous

affected

operation.

BCC
103000 PLUS OFFSET

BRANCH IF _CARF\Y iI5SCLEAR
08
1

07
T

)

OFFSET

(2 X

<-- PC +

MR 5238

if C =

offset)

Operation:

Condition Codes:

Not

Description:

Tests the state of the C bit and causes a branch
if

affected

clear.
BCC
of BCS.

the complementary

operation

BCS

103400 PLUS OFFSET

IS SET
IF CARRY
BRANCH

15
1

1
4

1
!

{

OFFSET
w

MR 5239

Operation:

Condition Codes:

Not

Description:

Tests

<-=-

6.3.6,2
the

offset)

the C

bit

C=1

the

state

set.

result

used

and causes

test

These

instructions

complement)
that

code

bits

are

instructions

which

the

are

the

sense

signed

branch

combinations

signed

test

the

comparisons

the

were

carry

with

used

operands

values.

unsigned
comparisons
in
arithmetic the sequence of
largest
.
077777
positive
077776

tested

for

operation.

Bigned Conditional Branches - Particular

condition

branches.

Note

affected

if C
the

considered

differs

that
in signed, 16-bit,
values is as follows.

conditional

results

signed

from

2°s

that

(2°s

complement

000001

000000
177777
177776

smallest

iOOOOl

negative

Whereas,
considered

highest

100000

in
to

unsigned,
be:

177777

000002

lowest

000001
000000

16-bit

arithmetic,

the

sequence

BGE

002000 PLUS OFFSET

BRANCH IF GREATER THAN OR EQUAL
(TO ZERO)

00
hj

}

OFFSET

)

MR 5240

Operation:

PC <-- PC + (2 X offset) if NXAL V =0

Condition Codes:

Not

Description:

Causes a branch if N and V are either both clear

affected

BGE is the complementary operation

or both set.

of BLT. Thus, BGE will always cause a branch
when it follows an operation that caused
BGE will also
addition of two positive numbers.
cause a branch on a 0 result.

BLT

BRANCH IF LESS THAN (ZERO)

15 1

07 T

{

002400 PLUS OFFSET
T

OFFSET

Operation:

PC <-- PC + (2 x offset) if

Condition Codes:

Not

NJAL V =1

MR 240

affected

Causes a branch if the exclusive OR of the N and
V bits is one. Thus, BLT will always branch
following an operation that added two negative
In
numbers, even if overflow occurred.

Description:

particular, BLT will always cause a branch if it

follows a CMP instruction operating on a
negative source and a positive destination (even
if overflow occurred). Further, BLT will never

cause a branch when it follows a CMP instruction
operating on a positive source and negative
destination. BLT will not cause a branch if the
result of the previous operation was 0 (without
overflow).

BGT

003000 PLUS OFFSET

BRANCH IF GREATER THAN (ZERO)

15
o

M—

Operation:

OFFSET
1

]

MR 5242

PC <-- PC + (2 X offset) if 2 \/ (N \f V)

affected

Condition Codes:

Not

Description:

Operation of BGT is similar to BGE, except that

BGT will not cause a branch on a 0 result.
6-50

BLE
BRANCH IF LESS THAN OR EQUAL (TO ZERO)

003400 PLUS OFFSET
00
L

-y

OFFSET

Operation:

<~-- PC +

-l

(2 X offset)

if 2 \/

(N )£ V)

MR §$243

Condition Codes:

Not

Description:

Operation is
will cause a

affected

6.3.6.3

similar to BLT, but in addition
branch if thé result of the

operation

was

Unsigned Conditional Branches - The unsigned

branches
provide a
operations in
which

means
for
testing
the
operands
are

the result
considered

conditional
of comparison
as
unsigned

values.
BHI

BRANCH IF HIGHER

101000
PLUS OF FSET

15
Y

[

OFFSET

MA 5244

Operation:

Condition Codes:

Not

Description:

Causes a branch if the previous operation caused
neither a carry nor a 0 result.
This will
happen in comparison (CMP) operations as long as
the source has a higher unsigned value than the
destination.

<==-

(2 X

offset)

C =0

and

affected

BLOS
BRANCH IF LOWER OR SAME

101400 PLUS OFFSET

15
T

0
o

0
"

0
{

o1
Fl

<-- PC +

3§

[

OFFSET

X offset)

C\/ 2

MR.-B3245

Operation:

Condition Codes:

Not

Description:

Causes a branch if the previous operation caused
either a carry or a 0 result.
BLOS is the
complementary operation of BHI.
The branch will

affected

occur in comparison operations as
source is equal to or has a lower
than the destination.

6-51

long as the
unsigned value

BHIS

103000 PLUS OFFSET

BRANCH IF HIGHER OR SAME
15

4‘

{

OFFSET

}

MR 5246

Operation:

Condition Codes:

Not

Description:

‘

<-- PC +

(2 X

offset)

if C =0

affected

BHIS

mnemonic

the same
is

instruction as BCC.

included

for

This

convenience caly.

BLO
BRANCH IF LOWER
15

103400 PLUS OFFSET
\J

0]
o

0
e

-t

1§

-y

OFFSET

MR 5247

Operation:
Condition

PC
Codes:

<== PC +

Not

Description:

(2 X offset)

if C =1

affected

BLO is the same instruction as BCS.
This
mnemonic is included for convenience only.

6.3.6.4
Jump And Subroutine Instructions - The subroutine call in
the
DCJ11l
provides
for
automatic
nesting
of
subroutines,
reentrancy, and multiple entry points.
Subroutines may call other
subroutines (or indeed themselves) to any level
of nesting without
making special provision for storage of return addresses
at
each

level

subroutine call.

The

subroutine calling mechanism does

not modify any fixed location in memory,
reentrancy.
This
allows
one
copy of
among several interrupting processes.

and
thus
provides
for
subroutine to be shared

JMP
Jump

0001DD

06
T

)

0
1

)

0
L

00
T

]

MR 11558

Operation:

<=--

(dst)

Condition Codes:

Not

Description:

JMP provides more flexible program branching
than the branch instructions do.
Control may

affected

transferred

any

location

limitation) and can
full flexibility of
the

exception

memory

(no

range

be accomplished with the
the addressing modes, with

6-52

mode

Execution

jump with mode 0 will cause an "illegal

instruction"
to

trap

condition,

vector

and will cause

address

four.

the CPU

(Program

control cannot be transferred to a register.)
Register-deferred mode is legal and will cause
program control to be transferred to the address
held in the specified register.
Note that
instructions are word data and must therefore be
fetched from an even-numbered address.
Deferred-index mode JMP instructions permit
transfer of control to the address contained
a

selectable

element

a table

dispatch

vectors.

Example:

First:

JMP

FIRST

stransfers

to FIRST

JMP

@LIST

stransfers to location
pointed
to at LIST

List:

FIRST

;pointer

JMP

stransfer to location
pointed to by the top of
the stack, and remove the
pointer from the stack

@ (SP)+

to FIRST

JSR
JUMP TO SUBROUTINE

15 .
]

004ROD

.
0

Operation:

09
0

(tmp)

<--

(dst)

<--

(tmp is an internal processor

reg

(Push

reg

contents

onto

processor

stack)

reg <-- PC (PC holds location
address now put in regq)
PC <=- (dst)
destination)

Description:

(PC

execution of

now points
-

the JSR,

following JSR;

this

subroutine

the 0ld contents of

the

specified register (the "linkage pointer") are
automatically pushed onto the processor stack
and new linkage information is placed in the
register.
Thus, subroutines nested within
subroutines

any

6-53

depth

may

all

called

with

the same linkage register.
There is no need
either to plan the maximum depth at which any
particular subroutine will be called or to
include instructions in each routine to save and
restore the linkage pointer.
Further, since all
linkages are saved in a reentrant manner on the
processor stack, execution of a subroutine may
be interrupted. The same subroutine may be
reentered and executed by an interrupt service
routine,
Execution of the initial subroutine
can then be resumed when other requests are
satisfied.
This process (called "nesting") can
proceed to any level.
'

‘A subroutine called with a JSR reg,dst
instruction can access the arguments following
the call with either autoincrement addressing,
(reg) +, if arguments are accessed sequentially,
or by indexed addressing, X(reg), if accessed in
random order.
These addressing modes may
be deferred, @(reg)+ and @X(reg), if the

parameters

operands
JSR

PC,

are

operand

addresses

rather

also

than

the

themselves.
dst

special

case

the

DCJ1l1l

subroutine call suitable for subroutine calls
that transmit parameters through the general
registers.
The SP and the PC are the only
registers that may be modified by this call.
Another special case of the JSR
JSR PC,@(SP) +, which exchanges
of the processor stack with the
program

counter.

This

instruction

is
the top element
contents of the

instruction

allows

two

routines to swap program control and resume
operation from where they left off when they
recalled.

Return

Such

from

routines

are

subroutine

called
done

are
"coroutines."
the

RTS

instruction.
RTS reg loads the contents of
into the PC and pops the top element of the

processor

stack

into

the

specified

reg

Example:
-

SBCALL:
SBCALL+4:

SBCALL+2+2M:
CONT:

SBR:

JSR
ARG

R5,SBR
1

ARG

R6
n

R7
SBCALL

Instruction

#$1

CONT

MOV
MOV

(R5)+,dst
(RS5)+,dst

SBCALL+4

n-2

SBR

1
2

MOV (RS)+,dst M
Other Instructions
RTS RS

EXIT:

SBCALL+2+4+2M
CONT
'
CONT

n-2

EXIT

JSR R5, SBR

JEFORE.

(PC)

STACK
SBR

JSR PC.

SBR

(SP)

\FTER.

BEFORE:

DATA O

(PC)

(SP)

R'6

LS8R .

AFTER:

DATAO

DATA O

DATA
O

PC+2

n-2

STACK

MAR.82800

PC+2

RTS

RETURN FROM SUBROUTINE

’

00020R

15
T

0
i

0
1

g
MA 115857

Operation:

PC <-- (regq)
(reg) <-- (SP)

Description:

Loads the contents of the register into PC and
pops the top element of the processor stack into
the specified register.
Return

from a nonreentrant subroutine is
typically made through the same register that
was used in its call.
Thus, a subroutine called

with a JSR PC, dst exits with a RTS PC and a
subroutine called with a JSR R5, dst, may pick
up

parameters

X(R5),
RS.

Example:

RTS

with

@X(R5)

addressing

and

finally

modes

(R5)

exits,

with

an RTS

RTS R5

BEFORE:

{PC)

STACK

SBR

DATAO

(SP)

n+2

AFTER.

DATAO

MR.-5$282

SOB
SUBTRACT ONE AND BRANCH (IF = 0)
15

077RNN

!
B

!
4

1
L

L
|

!
1

1
I

R
1

OFFSET
L

| W

MA 11882

Operation:

(R)

<-=-

<--

(R)

= 1;

if this result # 0, then PC

x offset);

(R)

then PC

<--

Condition Codes:

Description:

Not

affected

The register

is decremented.

the contents

does not equal 0, twice the offset is subtracted
from the PC (now pointing to the following
word).
The offset is interpreted as a 6-bit
positive number.
This instruction provides a

fast, efficient method of loop control.
The
assembler syntax is SOB R,A where A is the
address to which transfer is to be made if the
decremented R is not equal to 0. Note: the SOB
instruction cannot be used to transfer control
in the forward direction.

6.3.6.5
Traps - Trap instructions provide for calls
1/0
monitors,
debugging packages, and user-defined

to emulators,
interpreters.

A trap is effectively an interrupt generated by software.
When
a
trap
occurs, the contents of the current program counter (PC) and
processor status word (PS) are pushed onto the processor stack and
replaced
by the contents of a 2-word trap vector containing a new
PC and new PS.
The return sequence from a trap involves executing
an RTI or RTT instruction, which restores the 0ld PC and old PS by
popping them from the stack.
Trap instruction vectors are located
6-56

permanently

assigned

fixed

addresses.

EMT

104000104377

EMULATOR TRAP

12 Y

Operation:

Condition Codes:

<«<-- PS

(SP)

<-- PC

Description:

(SP)

PS <--

All
EMT

MR.5254

(32)

loaded
loaded
loaded
loaded

from trap vector
from trap vector
from trap vector
from trap vector

operation codes from
instructions and may

104000 to 104377 are
be used to transmit
information to the emulating routine (e.q.,
function to be performed).
The trap vector for
EMT is at address 30.
The new PC is taken from
the word at address 30; the new processor status
(PS)
is taken from the word at address 32.
CAUTION:
system

for

EMT

software

general

use.

)

PS1
.

PC
1

used
and

frequently
is

therefore

STACK

BEFORE:

AFTER:

DATA 1

{32)

{30)

DATA 1
PS1

PC1

MRA.5265

DIGITAL

not

recommended

TRAP

104400104777

TRAP

00
A

)

Operation:

Condition Codes:

<--

PS
<-- PC

Qoo

V:
C:

(34)
(36)

loaded from trap
loaded from trap
loaded from trap
loaded from trap

vector
vector
vector
vector

Operation codes from 104400 to 104777 are TRAP

Description:

TRAPs and EMTs are identical in

instructions.

except that the trap vector for TRAP

operation,
is

address

34.

NOTE: Since DIGITAL software makes frequent use
of EMT, the TRAP instruction is recommended for
general

use.

BPT
B_REAKPOlENT TRAP

000003

15
0

<-- PS
<=-- PC
(14)

(16)

<--

loaded

(SP)

from trap vector

loaded

from

trap

vector

V:
C:

loaded
loaded

from
from

trap
trap

vector
vector

Performs a
address of

Description:

(SP)
PC <--

Operation:

Condition Codes:

0
]

trap sequence with a trap vector
14.
Used to call debugging aids.

The user is cautioned against employing code
000003 in programs run under these debugging
aids. (No information is transmitted in the low
byte.)
I0T
INPUT/OUTPUT TRAP

0
&

Operation:

0
d

000004

0
4

0
1

(SP)
(SP)

0
1

0
4

0
N

0
1

1
L

0
2

00
0

MR 5258

<-- PS
<--

PC
6-58

PC <=

(20)

<--

loaded

from

Z:
V:

loaded
loaded

from
from

loaded

from

Condition Codes:

Description:

(22)

Performs

trap vector
trap vector
trap vector
trap vector

trap

sequence

address of 20.
the low byte.)

(No

with

information

trap

vector

transmitted

RTI
RETURN FROM INTERRUPT

‘

000002

15
T

1§

Codes:

<--=

(SP)

<--

(SP)

from
from

loaded
loaded

processor

from

stack

from

processor
processor

stack
stack

from

exit

the

executing

executed

mode

kernel.

can

and

processor

current

the

trace

bits

was

TRAP

restored

the

trap

RTI

will

mode,

the
mode

user.

RTI

already

set.

the

user

the

prior

When

and

cannot

mode,

cannot

sets

current

restored
bits

service

(popped)

occur

instruction.

executed

only

are

stack.

PS,

When

stack

interrupt
PS

supervisor

and

processor

from

The

the

bit

0
-

Hn o299

loaded

)

Z2:

‘routine.

}§

Used

C:
Description:

‘

Operation:

Condition

1§

the

restored

clear

bit

RTT
RETURN FROM TRAP
000006
15
0

00
0]

| R

Operation:

Condition Codes:

{

’

| S—

<--

(SP)

<--

(SP)

0
4

0
'

loaded
loaded

from

loaded
loaded

from processor
from processor

stack

RTI

inhibits

from processor

trace

trap.

]
'

MA.-8260

Operation

)

Description:

processor

stack
stack

stack

the

same

trace

trap

whereas

the

6-59

new

except

has

RTI

the

that

permits

bit

it
a

set,

a trap will occur after execution of the first
instruction after RTT.
When executed in

supervisor mode, the current and previous mode
bits in the restored PS cannot be kernel.
When executed in user mode, the current and
previous mode bits in the restored PS can only

be user.
already

6.3.6.6

RTT cannot clear PS bit

set.

it was

Miscellaneous Program Control -

MARK
0064NN
06

MR- 11566

Operation:

Condition Codes:

Description:

Example:

SP
PC
RS5

<=-<=<--

PC + 2
RS
(SP)+

number

x NN

unaffected

Z2:
V:
C:

unaffected
unaffected
unaffected

parameters

Used as part of the standard subroutine return
convention. MARK facilitates the stack clean-up
procedures involved in subroutine exit.
Assembler format is: MARK N.
MOV

R5,-(SP)

;place

MOV
MOV

P1l,-(SP)
P2,-(SP)

;jplace N parameters on
;the stack to be used

old

MOV

PN,- (SP)

MOV

=MARKN,-(SP)

; there

MOV

JSR

;place

by
the

the

stack

subroutine

instruction

;MARK N

SP,R5

;set

address

PC,SUB

;instruction
;jump to subroutine

the

stack
at MARK

At this point the stack is as follows:
OLD R5
P1

MARK
N

OoLDPC

And

the

program

beginning

6-60

MR 118669

the

address SUB

subroutine.

which

SUB:

RTS

iexecution of the
jsubroutine itself
sthe return begins:
;this causes the contents

;0f

:PC

which

; the

placed

then

results

execution

the

;instruction MARK N.

rcontents

rare

placed

the

the
in

The

old

RS.

MARK

N causes:
(1) the stack pointer to be
adjusted to point to the old RS value
;
(2) the
value now in R5
(the old PC) to be placed in
the PC; and (3) contents of the old
R5 to be
popped into R5 thus completing the
return from
subroutine,
NOTE

memory

must

management

mapped

execute

through

the

MARK

use,

both

the

and

instruction.

stack
space

SPL
SET PRIORITY LEVEL

00023N

Operation:

PS bits <7:5> <-(priority = N)

Condition Codes:

unaffected

Description:

unaffected

kernel

mode,

priority

the

least

significant

three bits of the instruction are
loaded
into the processor status word (PS)
bits
<7:5>, thus causing a changed prior
ity.
The o0ld priority is lost.
In user or
supervisor

Assembler

modes,

SPL

syntax

is:

executes

SPL

NOP.

CSM
CALL TO SUPERVISOR MODE

)

007000

15
I

]

{

]

)

]

00
I

{

|
MR

6-61

11468

Operation:

If MMR3

bit

3 =

mode = kernel
supervisor SP

1 and current

then
<-- current

mode SP

temp<l5:4> <-- PS<15:4>
temp<3:0> <-- 0

PS<13:12>
PS<15:14>

<-<--

PS<15:14>
01

PS 4 <-- 0
- (SP) <-- temp
- (SP) <~-- PC
- (SP) <-- (dst)
PC <=-- (10)
otherwise, traps

kernel

mode.

Condition Codes:

N:
Z:
V:
C:

unaffected
unaffected
unaffected
unaffected

Description:

CSM may be executed in user or supervisor
mode, but is an illegal instruction in kernel
mode.
CSM copies the current stack pointer
(SP) to the supervisor mode, switches to
supervisor mode, stacks three words on the
supervisor stack (the PS with the condition
codes cleared, the PC, and the argument word
addressed by the operand), and sets the PC to
the contents of location 10
(in supervisor
space).
The called program in supervisor
space may return to the calling program by
popping the argument word from the stack and
executing RTI.
On return, the condition codes
are determined by the PS word on the stack.
Hence,

may

the

called

control

the

program

condition

supervisor

code

values

space

following

return.

6.3.6.7
to

Reserved

execute

Instruction Traps

instruction

codes

- These

reserved

are

caused

for

future

attempts
©processor

expansion (reserved instructions)
or
instructions
with
1illegal
addressing
modes
(illegal
instructions).
Order
codes
not
corresponding to any of the .instructions described are
considered

to
be
reserved
instructions.
JMP
and
JSR with register mode
destinations are
1illegal
instructions;
they
¢trap
to
wvirtual
address
4
1in
kernel
data space.
Reserved instructions trap to
vector

address

6.3.6.8
causes

kernel

Trace Trap - Trace

will

vector

processor

instruction

bit

debugging

that

traps

proceed

executed
to

address

14.

aid

and

data

space.

trap

the

end

bit

instruction

after

the

instruction

that

the

completion

‘lote

enabled
of

transparent

and

then

trap

trace

the general

6-62

the PS

and

execution.

that

set

through

¢trap

the

programmer.

The

trap

system

NOTE

Bit
4
of
indirectly

the
PS
can
only
be
by
executing
a
RTI
or
instruction with the desired
PS
on

set
RTT
the

stack.

6.3.6.8.1
cases

Special
the T

Cases Of The T Bit -

bit.

NOTE
traced instruction
after the one that set

The

‘An
the

The

the

the T

following

traced
set.

instruction

that cleared the T bit -- Upon
instruction, an internal flag, the

The

trap

will

still

occur

instruction’s execution.
The status
however, will have a clear T bit.
An instruction that set
already set, setting it
will occur.
instruction

the T
again

bit
has

that

caused

word,

the

bit

special

bit.

instruction

was

are

the

word
'

fetching
trace flag,

end

the

this

stack,

-- Since the T bit was
no effect.
The trap

instruction

trap

The

instruction trap is performed and the entire
routine for
the service trap is executed.
If the service routine
exits with an RTI, or in any other way restor
es the

stacked

status

instruction
and,

unless

previously,
An

trace

instruction

instruction
overflow

following

loaded

pushed

and

this

into

not

the

time

special

stack

execution

cause

and

trap.

and

Stack

trap

set

again,

instruction
cases

the

noted

executed,

occurs.

caused

stack.

the

trap

completes

does

onto

one

that

the traced

overflow --

usual.

The

trace

the old

overflow

made.

The

stack

trap

and

occurs

vector

are

again,

An interrupt between setting of the
T-bit and fetch
of the traced instruction -- The entir
e interrupt
service routine is executed and then
the T-bit is
set

again

executed

and,
a

unless

trace

the

(if
it

exiting

there
is

RTI.

have

special

case

trap.

Interrupt

trap

priorities

The

traced

been no other

6-63

noted

See Table

instruction

interrupts)

above,

1-8.

causes

Miscellaneous Instructions -

6.3.7
HALT

000000

HALT

]

Operation:
|

(SP)
(SP)

<-- PS
<-- PC

<--

340

ma 5261

restart address

<--

.
,

0' o

o0
L

]

Condition Codes:

Not

affected

Description:

The effect of HALT depends upon the CPU
operating mode and the halt option
currently selected. See Chapter 8 Interfacing for more details on halt
options. In kernel mode, a halt option of
1 (external logic driving a 1 on DAL3 in

response to a GP Read with a GP code of 000)
causes a trap through location 4 and sets
bit 7 of the CPU error register when HALT is
executed. If the halt option is 0 in kernel

mode,

the HALT instruction

execution of

causes the DCJ1l into console ODT.

Execution of the HALT instruction in user or
supervisor mode causes a trap through
location

and

sets

bit

the CPU

error

200001

WAIT FOR INTERRUPT

o
15

}

Condition Codes:

Not affected

Description:

In WAIT,

the next

-r

)

MR.5262

in all

instructions,

instruction

following

the PC points
the WAIT

Thus, when an interrupt causes the
instruction.
PC and PS to be pushed onto the processor stack,
the address of the next instruction following
The exit from the interrupt
the WAIT is saved.

routine (i.e., execution of an RTI instruction)
will cause resumption of the interrupted process
at the instruction following the WAIT.
If not
in kernel mode, WAIT executes as a NOP.

RESET
RESET EXTERNAL BUS

000005

15
B

j —

]

|§

Condition Codes:

Not affected

Description:

The

L§

]

MR 5263

following

sequence

events

occurs:

(1)

a GP Write cycle is performed and a GP code
of 014 is generated,
(2) operation is delayed
for 69 microcycles,
(3) a GP Write is
performed and a GP code of 214 is generated,
(4) operation is delayed for 600 microcycles
delay. If not in kernel mode, RESET operates
as

a NO°P,

MFPT
MOVE FROM PROCESSOR TYPE WORD

000007

15
T

[}

0
']

0
1

1
) —

Operation:

Condition Codes:

Not

Description:

The number 5 is placed in RO, indicating to the

<--

5§

me e

affected

system

software

that

the

processor

type

DCJ1l.

MTPD/MTPI
MOVE TO PREVIOUS DATA SPACE
MOVE TO PREVIOUS INSTRUCTION SPACE

806600

[

]

Operation:

(temp) <=-- (SP)+
(dst) <=- (temp)

Condition Codes:

N:
Z2:

set
set

cleared

Z2:

unaffected

Description:

if
if

the
the

source
source

<
=

0
0

The instruction pops a word off the current
stack determined
by PS bits <15:14> and stores
that word into an address in the previous space
(PS bits <13:12>).
The destination address is
computed using the current registers and memory
map.

MFPD/MFPI

6-65

MOVE FROM PREVIOUS DATA SPACE
MOVE FROM PREVIOUS INSTRUCTION SPACE

Operation:

Condition Codes:

]

® 06555

]

(temp) <-- (src)

(temp)

- (SP) <--

N: set if the source < 0

72: set if the source = 0

Description:

)

cleared

unaffected

k from an
Pushes a word onto the current stacrmin
ed by
dete
e
address in the previous spac
uted
comp
is
ess
addr
PS<13:12>. The source

using the current registers and memory map.
mode

ious
When MFPS is executed and both prev
ion functions
ruct
inst
the
,
current mode are user
as though it were MFPD.

6.3.8
CLN
CLZ
CLV
CLC
CCC

Condition Code Operators -

SEN
SEZ
SEV
SEC
sCC

0002 X X

CONDITION CODE OPERATORS
T
_

Description:

le
Set and clear condition code bits. Selectab
or
red
clea
combinations of these bits may be esponding se
to
corr
together. Condition code bits ator
>
<3:0
s
(bit
oper
bits in the condition code
4,
bit
of
e
are modified according to the sens
ator; i.e., set th
the set/clear bit of the oper
or 3, if bit 4 =
2,
bit specified by bit 0, 1,
bit 4 = 0.
if
1. Clear corresponding bits
OP Code
Operation
Mnemonic
CLC
CLV
CL2
CLN
SEC
SEV
SEZ
SEN
SCC

Clear C
Clear V
Clear 2
Clear N
Set C
Set V
Set 2
Set N
Set all CCs
6-66

000241
000242
000244
000250
000261
000262
000264
000270
000277

cce
NOP

Clear all CCs

Clear V and C
No operation

000257
000243
000240

Combinations of the above set or clear
operations may be ORed together to form combined
instructions.

6-67

CHAPTER 7

FLOATING-POINT ARITHMETIC

7.1

INTRODUCTION

The
The DCJ1l executes forty-six floating-point instructions.
instruction set is compatible with the FP1l
floating-point
and
singleBoth
computers.
instruction set for PDP-1l1
with
double-precision floating-point capabilities are available
and
floating-to-integer
including
features,
other
:

integer-to-floating conversion.

7.2

PFLOATING-POINT DATA FORMATS

Mathematically, a floating-point number may be defined as having
the form (2 ** K) * f, where K is an integer and f is a fraction.

For a nonvanishing number, K and f are uniquely determined by
imposing the condition 1/2 ¢ £ < 1. The fractional part (f) of

the number is then said to be normalized.

For the number 0, f

assigned the value 0, and the value of K is indeterminate.

The floating-point data formats are derived from this mathematical
Two types of
numbers.
floating-point
for
representation
or
sion,
single~preci
In
floating-point data are provided.
or
ision,
double-prec
1In
long.
bits
32
is
data
floating mode, the
double mode, the data is 64 bits long. Sign magnitude notation is
,

used.

7.2.1 Nonvanishing Floating-Point Numbers - The fractional part
is assumed normalized, so that its most significant bit must
(f)

be 1.

it is not stored explicitly in

This 1 is the "hidden" bit:

the data word, but the microcode restores it before carrying out
arithmetic operations. The floating and double modes reserve 23
and 55 bits, respectively, for f. These bits, with the hidden
bit, imply effective word lengths of 24 bits and 56 bits.

Eight bits are reserved for storage of the exponent K in excess
200 notation (i.e., as K + 200 (octal)), giving a biased exponent.
Thus, exponents from -128 to +127 could be represented by 0 to 377
(base 10). For reasons given below, a
(base 8), or O to 255

biased exponent of 0 (the

true

floating-point

exponent

reserved

for

octal) or,

in excess 200 notation,

-200

Therefore,

(octal)),

exponents

are

+177

The remaining bit of the floating-point word is the sign bit.
‘
number is negative if the sign bit is a 1l.

The

restricted to the range -127

+127

inclusive

1 to 377.

(-177

7.2.2
Floating-Point
Zero - Because
fractional
part
1is
not
available

of
the
hidden
bit,
¢to distinguish between
fractional
part
is
exactly

nonvanishing
numbers
whose
Therefore,
the
DCJ1l
reserves
a
biased
purpose, and any floating-point number with

exponent
a biased

of 0 for
exponent

the
and
1/2.
this
of 0

either
traps or is treated as if it were an exact 0 in arithmetic
operations.
An exact or "clean" 0 is represented by a word
whose
bits
are
all
O0s.
A "dirty" 0 is a floating-point number with a
biased exponent of 0 and a nonzero fractional part.
An arithmetic
operation
for
which
the
resulting
true
exponent
exceeds 277
(octal) is regarded as producing a floating overflow;
if the true
exponent
is
less than -177 (octal), the operation is regarded as
producing a floating underflow.
A biased exponent of 0
can
thus
arise
from
arithmetic
operations
as a special case of overflow
(true exponent = -200 octal).
(Recall that only
eight
bits
are
reserved
obtained

7.2.3

for
from

the biased exponent.) The fractional part
such overflow and underflow is correct.

Undefined Variables - An

pattern with a sign bit
"undefined variable" is

undefined

variable

1is

of 1 and a biased exponent of
used, for historical reasons,

results

any

bit

0.
to

The term
indicate
corresponding

that
these
bit
patterns
are
not
assigned
a
floating-point arithmetic value.
Note that the undefined variable
is frequently referred to as -0 elsewhere in this chapter.

A design objective was to assure that the undefined variable would
not
be
stored as the result of any floating-point operation in a
program run with the overflow and underflow
interrupts
disabled.
This
1is achieved by storing an exact 0 on overflow and underflow,
if
the
corresponding
interrupt
1is
disabled.
This
feature,
together
with
an
ability
to
detect reference to the undefined
variable
(implemented
by
the
FIUV
bit
discussed
later),
is
intended
to provide the user with a debugging aid:
if -0 occurs,
it did
not
result
from
a
previous
floating-point
arithmetic
instruction.

7.2.4
words

Floating-Point
Data - Floating-point
memory as illustrated in Figures 7-1

F FORMAT

stored

7-2.

FLOATING POINT SINGLE PREC!SION

MEMORY +Q

data
and

FRACTION

15C.>

EXP
i

FRACT <22 16>
1

)

L
MA

Figure

7-1

Single-Precision Format

604

D FORMAT, FLOATING POINT DOUBLE PRECISION

FRACTION <15 0>
AL
L
i

FRACTION <31 16>

—l

15
FRACTION <47 32>

MEMORY +0

EXP

FRACT <54:48>
A1

S = SIGN OF FRACTION

EXP = EXPONENT IN EXCESS 200 NOTATION, RESTRICTED TO 1 TO 377 OCTAL
FOR NON-VANISHING NUMBERS

FRACTION = 23 BITS IN F FORMAT 55 BITS IN D FORMAT + ONE HIDDEN

8IT (NORMALIZATION). THE BINARY RADIX POINT IS TO THE LEFT.

Double-Precision Format

Figure 7-2

The DCJ11 provides for conversion
of
floating-point
to
integer
format
and vice-versa.
The processor recognizes single-precision

integer (I) and double-precision integer long (L)
numbers,
which
are stored in standard 2°s complement form.
(See Figure 7-3.)
| FORMAT INTEGER SINGLE PRECISION

15
S

NUMBER <156.0>
A
d
1

L FORMAT, DOUBLE PRECISION INTEGER LONG

NUMBER <30:16>

MEMORY +0 | S

15
+2

]

NUMBER <1%:0>

]

WHERE S = SIGN OF NUMBER

NUMBER = 15 BITS IN | FORMAT, 31 BITS IN L FORMAT.

Figure 7-3

7.3

2°s Complement Format

FLOATING-POINT STATUS REGISTER (FPS)

This
register
provides
mode
and
interrupt
control
for
the
currently
executing
floating-point instruction and also reflects
conditions
resulting
from
the
execution
of
the
previous
instruction.
(See
Figure 7-4.) In this discussion a set bit =1
and a reset bit = 0.
Three bits of the FPS register
control
the

modes

operation.

7-3

Single/Double -- Floating-point numbers can
or double-precision.

Long/Short --

Chop/Round -- The

Integer

numbers can be

result of

either

16 bits or

single-

bits.

floating-point operation can

either "chopped" or "rounded." The term "chop" is used instead
of "truncate" in order to avoid confusion with
truncation
of
series used in approximations for function subroutines.
16

0?7

RESERVED

RESERVED
MR- 3807

Figure
The FPS

7-4

bits):

Floating-Point

contains

carry,

analogous

The DCJ1l

recognizes

error

overflow,

the CPU condition

the

six

floating-point

presence

and

four

and

condition

negative,

codes

which

are

codes.

Detection of

Floating

overflow

Floating

underflow

Failure of

floating-to-integer

Attempt

divide

Illegal

floating

flag

zero,

Status

the

exceptions:

undefined

variable

in memory

conversion

code

For

the first four of these exceptions, bits in the
FPS
register
available
to individually enable and disable interrupts.
An
interrupt on the occurrence of either of the last
two
exceptions
can
be disabled only by setting a bit that disables interrupts on
all six of the exceptions, as a group.
are

the

FPS

bits,

are

set

part

the

output

floating-point
instruction:
the error flag and condition codes.
Any of the mode and interrupt control bits may be set by the user;
the
LDFPS
instruction
is
available
for
this
purpose.
These
thirteen bits are stored in the FPS register as
shown
in
Figure
7-4.
The FPS register bits are described in Table 7-1.
Table

Bit

Name

Floating
.

7-1

FPS

Bits

Description
Error

(FER)

The FER
if:

7-4

bit

set

the DCJ11l

division

illegal

any one of
point

zero

code

the

occurs.

remaining

exceptions

corresponding

occurs.

occurs

interrupt

floating
and

Note that the above action is
independent of whether the FID
is set or clear.

the

enabled.

bit

Note also that
resets the FER

the DCJ1ll never
bit.
Once the FER bit
is set by the DCJ1l, it can be
cleared only by an LDFPS instruction
(note the RESET instruction does not
clear the FER bit).
This means that
the FER bit is up-to-date only if
the most recent floating-point
instruction produced a floating-point
exception.

Interrupt
(FID)

Disable

If the FID bit is set, all floatingpoint interrupts are disabled.
NOTE

The FID bit is primarily a
maintenance feature.
It should
normally be clear.
1In particular,
it must be clear is one wishes to
assure that storage of -0 by the
DCJ1l is always accompanied by
an interrupt.

Throughout the rest of the chapter
assume that the FID bit is clear
in all discussions involving
overflow, underflow, occurrence of
-0, and integer conversion errors.

Reserved

for

future DIGITAL

use.

Reserved

for

future DIGITAL

use.

Interrupt

Undefined Variable
(FIUV)

An interrupt occurs if FIUV is set
and a -0 is obtained from memory as
an operand of ADD, SUB, MUL, DIV,
CMP, MOD, NEG, ABS, TST, or any LOAD
instruction.
The interrupt occurs
before execution on all instructions.
When FIUV is reset, -0 can be loaded
and used in any floating-point
operation.
Note
not activated by
in an AC operand

instruction;
7-5

that the interupt is
the presence of -0
of an arithmetic

particular,

trap on

-0

never

occurs

in mode 0.

A result of -0 will not be stored
without the simultaneous occurrence
of an interrupt.
10

Interrupt on
Underflow (FIU)

When the FIU bit is set, floating
underflow will cause an interrupt.
The fractional part of the result
of the operation causing the
interrupt will be correct.
The
biased exponent will be too large
by 400, except for the special case
of 0, which is correct.
An exception
is discussed later in the detailed
description of the LDEXP instruction.

Interrupt on
Overflow (FIV)

When the FIV bit is set, floating
overflow will cause an interrupt.
The fractional part of the result
of the operation causing the overflow
will
will

be
be

correct.
The biased
too small by 400.

exponent

If the FIV bit is reset and overflow
occurs, there is no interrupt.
The
DCJ1l1l returns exact 0.
Special cases of
discussed in the

descriptions of
instructions.
8

Interrupt on
Integer Conversion
Error

(FIC)

overflow
detailed

are

the MOD and LDEXP

When the FIC bit is set and a
conversion to integer instruction
fails, an interrupt will occur.
If
the interrupt occurs, the destination
is set to 0, and all other registers
are left untouched.
If

the

FIC

the

operation

detailed

bit

above,

reset,

will

but

the

result

the

same

interrupt

will

occur.

The

conversion

instruction

fails

it generates an integer with more
bits than can fit in the short or
long integer word specified by the
FL bit.

Floating DoublePrecision Mode (FD)

The FD bit determines the precision
that is used for floating-point
calculations.
When set, doubleprecision is assumed; when reset,
single-precision is used.

7-6

Floating LongInteger

Mode

(FL)

The FL bit is active in conversion
between integer and floating-point
formats.
When set, the integer
format assumed is double-prec151on

2°s complement (i.e., 32 bits).
reset, the integer format is

‘When

assumed to be single-precision 2°s

complement

Floating Chop Mode

(FT)

(i.e.;

bits).

When the FT bit is set, the result
of any arithmetic operation is
chopped (truncated).
When
the result is rounded.

reset,

Reserved for future DIGITAL use.
Floatlng Negative
(FN)
.

FN is set if the result of the
last floating-point operation
was negative; otherwise it is
reset.

Floating

Zero

(FZ)

Floatlng

Overflow

Carry

(FC)

7.4

FV is set if the last floating-

point operation resulted in an
exponent overflow; otherwise it
'1s reset.

(FV)

Floatlng

FZ is set if the result of the
last floating-point operation was
0; otherwise it is reset.

set

the

last

floating-

point operation resulted in a
carry of the most significant
bit.
This can only occur in
floating double-to-integer
conversions.

FLOATING EXCEPTION CODE AND ADDRESS REGISTERS

interrupt
vector
1is
‘take
care
of
assigned
to
floating-point exceptions (location 244).
The six possible errors
are coded in the 4-bit floating exception code (FEC)
register
follows.

One

4
6
8
10
12

Floating op-code error

Floating divide by zero
Floating-to-integer or double-to-i
nteger
Floating overflow
Floating underflow
Floating undefined variable

conversion error

The address of the instruction producing the exception
in the floating exception address (FEA) register.
The

FEC

and FEA

registers

are

updated
7-7

only

when

is
:
one

stored

the

following

occurs.

Division

Illegal

Any

the

interrupt

zero.
code.
other

four

exceptions

with

the

corresponding

enabled.

This implies that only when
registers updated.

the FER bit

set

are

the FEC

and FEA

NOTE

one

the

last

corresponding

not
2.

four

exceptions

interrupt

disabled,

occurs
the FEC

updated.

1If an exception occurs, inhibition
of
the
FID
bit does not inhibit updating

with
and

the

FEA

are

interrupts
of the FEC

by
and

FEA.

The FEC
occurs.

and

FEA

This

instruction will
the

most

recent

are

not

means

updated

that

return

the

current

floating-point

STST

7.5

Unlike the
FPS,
no
storage into the FEC

(store

instruction

FLOATING-POINT

Floating-point
central

is
-of

specified

INSTRUCTION

instructions

processor

instructions
and

use

FEA

exception

information

exception.

are

status)

only

produced

provided

if
an

for

registers.

ADDRESSING
the

instructions.

same
A

type

source

addressing

destination

the

operand

by designating one of eight addressing modes and
one
eight
<central
processor
general registers to be used in the
specified mode.
The modes of addressing are the same as those
of
the central processor, except in mode 0.
In mode 0 the operand is
located in the
designated
floating-point
processor
accumulator
rather than in a central processor general register.
The modes of
addressing are as follows.

Floating-point accumulator
Deferred
Autoincrement
Autoincrement-deferred
Autodecrement
Autodecrement-deferred
Indexed
Indexed-deferred

l
2

=
=
3 =
4 =
5 =
6 =
7 =

Autoincrement

decrements

and

In
mode
0
accumulators

autodecrement

for F

users

format

and

operate

can

make

use

AC5)

their

(ACO

(octal)

increments

for D

all

and

format.

six

floating-point

source

destination.

Specifying floating-point accumulators AC6 or
AC7 will
result
in
an
1illegal
op
code
trap.
In
all
other modes, which involve
transfer of data to or from memory or the genera
l registers, users
are
restricted to the first four floating-point accumul
ators (ACO
= AC3).
When reading or writing a floating-point number
from
or
to

memory,

the

low

memory

of the floating-point
significant word.

7.6

word

number,

contains

and

the

high

most

significant

memory

word

the

word

1least

ACCURACY

General comments on
instructions
are

the
accuracy
of
presented
here.

the
The

DCJ11l
floating-point
descriptions
of
the

individual
instructions
include
the
accuracy
at
operate.
An
instruction
or operation is regarded
the result
involving

is
the

operands

operand

whose

enabled

For

all

that

the

if
the
division
For

identical
to
an
same
operands.

thus

and

the

All

infinite
precision
calculation
The
a
priori
accuracy
of the

arithmetic

exponent

operand

arithmetic
instruction

-0, in
operations,

instructions

exact

floating~point

normalized.

mode

and

two

guard

guarantee

double

mode,

FIUV

is
case an interrupt occurs).
except DIV, a 0 operand implies

which

operands,

contains

treat

(unless

is exact.
The same statement
0
operand
is
the
dividend.
But if it
is undefined and an interrupt occurs.

nonvanishing

binary

ignored.

biased

which
they
as "exact" if

bits

the

holds

the

fractional

bits

for

for
DIV
divisor,

part

floating

respectively.
For ADD, SUB, MUL,
and
DIV,
are necessary and sufficient for the general
case
return of a chopped or rounded
result
identical
to

bits

the
corresponding infinite precision operation choppe
d or rounded
to the specified word
1length.
Thus,
with
two
guard
bits,
a
chopped
result
has
an
error bound of one least significant bit
(LSB);
a rounded result has an error bound
of
l/2
LSB.
These

error

bounds

the

lost
of a

rest

are

realized

this

nonvanishing

in chopping is
rounded result

chapter,

bits

the

would

DCJ11

arithmetic

lost

all

instructions.

result

by chopping.

called

The

referred to as the "rounding” bit.
is related to the chopped result as

exact

first

bit

The
value
follows.

1.
2.

If the rounding bit is 1, the rounded result

result

incremented by an LS5B.

the rounding bit

is 0,

identical.
follows

the

chopped

the rounded and chopped results

are

that:

result

is exact:

rounded value = chopped value = exact

value,

If the result

is not exact,

decreased

its magnitude
is:

always

chopping.

decreased

rounding

the

rounding

bit

increased

rounding

the

rounding

bit

Occurrence
of floating-point overflow and underflow
1is
an
error
condition:
the
result
of
the
calculation cannot be correctly
stored because the exponent is too large to
fit
into
the eight
bits reserved for it.
However, the internal hardware has produced

the correct answer.
For the case of underflow, replacement of the
correct
answer by 0 is a reasonable resolution of the problem for
many applications.
This is done by the
DCJ1l1l
if
the
underflow
interrupt
1is
disabled.
The error incurred by this action is an
absolute rather than a
value)
by
2 ** -128,
case of overflow.
The
disabled, is described

relative error;
it is bounded (in absolute
There is no such simple resolution for the
action taken, if the overflow interrupt
is
under FIV (bit 9) in Table 7-1.

The FIV and FIU bits (of the floating-point status
word)
provide
users
with an opportunity to implement their own correction of an
overflow or underflow condition.
1If such a condition
occurs
and
the
corresponding
interrupt is enabled, the microcode stores the
fractional part and the low eight bits
of
the
biased
exponent.
The
interrupt will take place and users can identify the cause by
examination of the FV (floating overflow) bit or the FEC (floating
exception)
register.
The reader can readily verify that (for the
standard arithmetic operations ADD, SUB, MUL, and DIV) the
biased
exponent
returned by the instruction bears the following relation
to the correct exponent.
1.

overflow,

too

small

400

(octal)

On underflow, if the biased exponent is
the biased exponent is not 0, it is too

0, it
large

is correct.
If
by 400 (octal).

Thus, with the interrupt enable, enough information
is
available
to
determine the correct answer.
Users may, for example, rescale
their variables (via STEXP and LDEXP) to continue
a
calculation.
Note that the accuracy of the fractional part is unaffected by the

occurrence of

underflow or

overflow.

7-10

7.7

FLOATING-POINT INSTRUCTIONS

Each

instruction

that

references

floating-point

number

can

operate
on
either single- or double-precision numbers, depending
Similarly, there is a
mode
bit
on the state of the FD mode bit.
FL
that
determines whether a 32-bit integer (FL = 1) or a 16-bit
integer
and
integer (FL =
0)
is
wused
in
conversion
between

floating-point
representations.
FSRC
and FDST
7-5);
floating-point addressing modes (see Figure

operands

and

operands use CPU addressing modes.
DOUBLE-OPERAND ADDRESSING
1B

05
FOC

oC
4

)

FSRC.FDST.SRC,OST

AC
-

-l

SINGLE-OPERAND ADDRESSING
15

00
FSRC, FDST, SRC, DST
- -

OC = OPCODE =17
FOC = FLOATING OPCODE

AC = FLOATING POINT ACCUMULATOR (ACO-AC3)

FSRC AND FDST USE FPP ADDRESSING MODES
SRC AND DST USE CPU ADDRESSING MODES
MA.JS08

Figure 7-5
Terms Used

Floating-Point Addressing Modes

Instruction Definitions_

ocC

= opcode =

FOC

= floating opcode

= contents of accumulator,
field of instruction,

specified

by AC

fsrc = address of floating-point source operand
fdst

address

fraction

= largest fraction that can be represented:
l
l

XLL

XUL

operand

FD
FD

=
=

(;
1;

single-precision
double-precision

smallest

number

that

not

can

identically

=zero

(-128)

largest

destination

(=-24),
(-56),

2
2

floating-point

**
**

number

(127)

largest

that

represented

integer

that

can

7-11

represented:

use

DST

(15)
(31)

1;
1;

0;
l;

FL
FL

short integer
long integer

ABS

(address)

absolute value

EXP

(address)

biased

.LT.

"less

than"

LE.

"less

than

.GT.

.GE,

LSB

"greater

than"

"greater

than

least

exponent

equal

(address)

to"

equal

significant

(address)

to"

bit

Boolean Symbols

/\
= AND

inclusive OR

.;VL

exclusive OR

NOT

ABSF/ABSD

MAKE ABSOLUTE FLOATING/DOUBLE
12

1706 FOST

MR.11467

Format:

ABSF

Operation:

(FDST)

EXP(FDST)

Description:-

<=--

<==

FZ
FN

<-<=-=

0,
=

other

(FDST)
0,

<=--

(FDST)

cases,

=-(FDST).
<--

(FDST)

exact

<--

(FDST).

Condition Codes:

all

(FDST)

For

FDST

else FZ

<--

Sét the contents of FDST to its absolute value.

Interrupts:

If FIUV is
execution.

Accuracy:

These instructions are exact.

enabled,
Overflow

7-12

trap on -0 occurs before
and underflow cannot occur.

ADDF/ADDD
ADD FLOATING/DOUBLE

172(ACIFSRC

Format:

ADDF

Operation:

Let

FSRC,AC
SUM =

(AC)

(FSRC)

If underflow occurs and FIU
<=-- exact

Condition Codes:

Description:

exact

For

all

<--

<-=<-<--

and FIV

is not enabled,

if
if
if

cases,

<--

SUM,

overflow occurs, else FV
(AC) = 0, else FZ <-- 0
(AC) < 0, else FN <-- 0

<-=

Add the contents of FSRC to the contents of AC.
The addition is carried out in single- or
double-precision and is rounded or chopped in
accordance with the values of the FD and FT bits
in the FPS register.
The result is stored in AC
except

l.
2.

For

for:

Overflow with interrupt disabled.
Underflow with interrupt disabled.

these exceptional cases,

stored

Interrupts:

1
1
1

others
0

is not enabled,

overflow occurs

<--

FV
FZ
FN

11408

in AC.

an exact 0

If FIUV is enabled, trap on -0 in FSRC occurs
before execution. If overflow or underflow
occurs, and if the corresponding interrupt is
enabled, the trap occurs with the faulty result
in AC.
The fractional parts are correctly

stored.
The exponent part is too. small by 400
for overflow.
It is too large by 400 for
underflow, except for the special case of 0,
which is correct.
Accuracy:

Errors due to overflow and underflow are
described above.
If neither occurs, then:
oppositely signed operands with exponent

for

difference of 0 or 1, the answer returned is
exact if a loss of significance of one or more
bits can occur.
Note that these are the only
cases for which loss of significance of more
than one bit can occur.
For all other cases the

7-13

result
1.

Comment:

inexact with error bounds of:

LSB in chopping mode with either single- or
double-precision.
1/2 LSB in rounding mode with either single-

Special

double-precision.

The undefined variable -0 can occur only in
conjunction with overflow or underflow.
It
be stored in AC only if the corresponding
interrupt is enabled.

will

CFCC

COPY FLOATING CONDITION CODES
15

12
T

170000

00
T

Format:

CFCC

Operation:

Description:

<--

<==

<--

Copy the floating-point condition
the CPU”s condition codes.

codes

into

CLRF/CLRD
CLEAR FLOATING/DOUBLE
15
1

o—

1704 FOST

CLRF

Operation:

(FDST)

Description:

Interrupts:

00
i

[

FOST

| -

{

FDST

<--

exact

FC <-- 0
FV

<-=

<=--1

<--

Set FDST to 0.
other condition

Set FZ condition
code bits.

interrupts will

cannot

Accuracy:

Format:

Condition Codes:

These

occur.

instructions
7-14

are

code

Overflow and

exact.

and

clear

underflow

CMPF /CMPD
COMPARE FLOATING/DOUBLE
12

173({AC+4)FSRC
11

MA-11471

Format:

CMPF

FSRC,AC

Operation:

(FSRC)

Condition Codes:

FC
FV

0
0

<-<=-=-

(AC)

else FZ <-- 0
else FN <-- 0

0,
0,

=
<

(FSRC)
(FSRC)

FZ <-- 1 if
FN <-- 1 if

Compare the contents of FSRC with the
Set the appropriate floating-point
accumulator.
FSRC and the accumulator are
condition codes.
left unchanged except as noted below.

Description:

If FIUV

Interrupts:

is enabled,

execution.

trap on -0 occurs before

Accuracy:

These

Special

An operand that has a biased exponent of 0 is
treated as if it were an exact 0.
In this case,
where both operands are 0, the DCJ1l will

Comment:

instructions

store

an exact 0

are exact.

in AC.

DIVF/DIVD

174(AC+4)FSRC

DIVIDE FLOATING/DOUBLE

0
|

Format:

DIVF FSRC,AC

Operation:

If EXP(FSRC)
instruction

{

<--

= 0,

(AC)

aborted.

(AC)

underflow occurs

<--

(AC)

and the

<-- exact 0.

let QUOT =
and FIU

(AC)/(FSRC).

is not enabled,

exact O.

If overflow occurs and FIV
<=--

FSRC

For all other cases,
If

)

If EXP(AC)

exact

is not enabled,

For

Condition Codes:

Description:

all

FC
FV

<-<--

<--

others

0
1
1
1

cases,

overflow

(AC)

<--

QUOT.

occurs,

else FV
<-=- 0

else FZ
else FN

<-=-

<-=

If either operand has a biased exponent of 0, it
is treated as an exact 0.
For FSRC this would
imply division by 0; in this case the
instruction

aborted,

the FEC

to 4, and an interrupt occurs.
Otherwise,
quotient is developed to single- or

double-precision with
rounding.

The

accordance
in the FPS

with

bits

rounded

for

correct

chopped

Overflow with interrupt disabled.
Underflow with interrupt disabled.

2.
For

these

stored
Interrupts:

in
the values of the FD and FT bits
register.
The result is stored in
except for:

the AC
l.,

two guard

quotient

exceptional

FIUV

cases,

enabled,

trap

before

execution.

attempt

divide

exact

AC.

-0

(FSRC)

FSRC

occurs

interrupt

overflow

underflow occurs, and if the corresponding
interrupt is enabled, the trap occurs with
faulty result in AC.
The fractional parts

correctly

small

Errors

due
in

for

is
to

correct.
overflow

above.
the

chopping

1If

quotient

mode

and

none

underflow

will

Comment:

these

1/2

mode.

Special

bounded

LSB

are

occurs,
by

The undeflned variable -0 can occur only in
conjunctlon with overflow or underflow.
It will
be stored in AC only if the corresponding
interrupt is enabled.

LOAD AND CONVERT FROM DOUBLE-TO-FLOATING
AND FROM FLOATING-TO-DOUBLE
15
1

the
LSB

rounding

LDCDF/LDCFD

the
are

The exponent part is too
overflow.
It is too large by
underflow, except for the special case

described
error

traps
or

stored.

400

400 for
of 0, which
Accuracy:

set
the

08
1

177(AC+4)FSRC
Q7

06
1

00
L

FSRC

MR-1147)

Format:

‘

LDCDF FSRC,AC

Operation:

If EXP(FSRC)
If FD =1,
overflow,
In

all

= 0,

FT
AC

«<--

other

AC <-- exact O.
FIV = 0

exact

cases,

and

rounding

causes

<-=-

Cxy(FSRC),

where Cxy

specifies conversion from floating mode x to
floating mode y.

x =D,

y
Condition Codes:

Description:

y=V¥

=F,

if FD =

y=D

FC
FV

<-<--

0
1

<--

F2
FN

<-<--

1 if
1 if

if FD =

(single)

|
conversion produces

(AC)
(AC)

=
<

0,
0,

LDCDF

(double)

else FZ
else FN

LDCFD

overflow,

<-<--

else

0
0

If the current mode is floating mode (FD = 0),
the source is assumed to be a double-precision
number and is converted to single-precision.
1If
the floating chop bit (FT) is set, the number is
chopped; otherwise, the number is rounded.
If the current mode is double mode (FD = 1), the
source is assumed to be a single-precision
number and is loaded left-justified in AC.
The
lower half of AC is cleared.

Interrupts:

If FIUV is enabled,

execution.

trap on -0 occurs before

Overflow cannot occur

A trap occurs

if FIV is enabled,

for LDCFD.

and

rounding

with LDCDF causes overflow.
AC <-- overflowed
result.
This result must be +0 or -0. Underflow
cannot

Accuracy:

occur.

LDCFD is an exact instruction.
Except for
overflow, described above, LDCDF incurs an error

1 LSB in chopping mode and by 1/2 LSB
bounded by
in

rounding mode.

LDCIF/LDCID/LDCLF/LDCLD

LOAD AND CONVERT INTEGER OR LONG INTEGER
TO FLOATING OR DOUBLE-PRECISION
15

]
1

1
1

|
1

177{AC)SRC

i
1

1]
1

08
0

{

AC
i

1§

SRC
[

}

Format:

LDCIF

SRC,AC

Operation:

AC <-- Cjx(SRC), where Cjx specifies conversion
from integer mode j to floating mode v.
7-17

Condition Codes:

<~<==

Conversion

from a

(AC)
(Ac)
is

2°s

=
<

0,
0,

L
D

% L

if
if

<-<=~

0
0
1
l

if FL
if FD

FV
FN

Description:

else FZ
else FN

performed

complement

if FL
if FD

<-<--

the

0
0

contents

SRC

integer with precision j

to a floating-point number of precision x.
Note
that j and x are determined
by the state of the
mode bits FL and FD.

32-bit

integer is specified
(L mode) and
has an addressing mode of 0 or immediate
addressing mode is specified, the 16 bits of the
source register are left-justified and the
remaining 16 bits loaded with 0s before
conversion.
(SRC)

In the case of LDCLF, the fractional part of
floating-point representation is chopped or
rounded to 24 bits for FT = 1 or 0,
respectively.

Interrupts:

None;

SRC

cannot
Accuracy:

not

floating-point,

occur.

LDCIF, LDCID, and LDCLD are
The error incurred by LDCLF

in chopping
mode.

mode

and

trap

the

-0

exact

1/2 LSB

instructions.
bounded by 1 LSB

rounding

LDEXP

LOAD EXPONENT

176(AC+4)SRC
12

MR.11475

Format:

LDEXP

SRC,AR

Operation:

NOTE:

177

and

200,

numbers.

If
the

-200
< SRC
rest

appearing

200,
is

EXP(AC)

unchanged.

below,

<-- SRC +

If (SRC)
[ (SRC) +

> 177 and FIV
200]<7:0>.

enabled,

disabled,

(SRC)

177

and

FIV

are

octal

200 and

EXP(AC)

<--

exact

If (SRC) < =177 and FIU is enabled, EXP(AC) <-[ (SRC)

200)<7:0>.

If (SRC) < -177 and FIU is disabled, AC <--

exact

Condition Codes:- FC
FV
F2
FN

Description:

<=--

<-<-<~--

1
1
1

if
if
if

(SRC) > 177, else FV <== 0
(AC) = 0, else FZ <-- 0
(AC) < 0, else FN <-- 0

Change AC so that its unbiased exponent = (SRC).
That is, convert (SRC) from 2°s complement to
excess 200 notation and insert it into the EXP
This is a meaningful operation
field of AC.
only

if ABS(SRC)

LE 177.

If SRC > 177, the result is treated as overflow.
If SRC < =177, the result is treated as
underflow.
Interrupts:

trap on -0

in AC occurs,

even

if FIUV

enabled. If SRC > 177 and FIV is enabled, trap
on overflow will occur., If SRC < -177 and FIU is
enabled, trap on underflow will occur.

Errors due to overflow and underflow are
described above.
If EXP(AC) = 0 and (SRC) =
=200, AC changes from a floating-point number
treated as 0 by all floating arithmetic
operations to a non-0 number.
This happens
because the insertion of the "hidden" bit in the
microcode implementation of arithmetic
instructions is triggered by a nonvanishing

Accuracy:

value

EXP.

For all other cases, LDEXP implements exactly
the transformation of a floating-point number (2
**x K) * £ into (2 ** (SRC)) * f where 1/2 .LE.
ABS(f)

.LT.

LDF/LDD
LOAD FLOATING/DOUBLE

172(AC+4)FSRC

MR 11476

Format:

LDF

Operation:

Condition Codes:

FSRC,AC

<--

(FSRC)

<-=-

0
0

<--

(AC)

<--

else

(AC)

FZ2

<--

else

<--

Description:

Load

Interrupts:

If FIUV is
is loaded.

single-

Accuracy:

These

Special

These

Comment:

double-precision

enabled,

Overflow

instructions

enabled

and

into AC,

trap on -0 occurs before AC
and underflow cannot occur.

are

exact.

instructions permit
subsequent floating-point

not

number

(FSRC)

use

of -0 in a
instruction if FIUV

-0.

LDFPS

LOAD FLOATING-POINT PROG
RAM STATU

15
T

1§

[E—

1701 SRC
06

]

00
)

SRC

) S—

A
MR-

Format:

LDFPS

Operation:

FPS

Description:

Load

Special Comment:

Users

SRC

<--

not

(SRC)

floating-point

for

V1427

status

from SRC.

are

cautioned not to use bits 13,
12, and
their own purposes, since these
bits are

recoverable

by.the

STFPS

instruction.

MODF /MODD

MULT
AND SEPARATE
'PLY
INTEGER

AND FRACTION FLOATING DOUBLE
15

171(AC+4)FSRC
08
0

00
T

FSRC

Format:

Description
~and Operation:

MODF

This
two

11478

FSRC,AC

instruction

generates

floating-point

product

the

operands,

product

separates

its

the

into integer and fractional
parts, and
then stores one or both part
s as floating-point
numbers.
Let

PROD

(AC)

Floating-point:

(FSRC)

ABS (PROD)

7-20

that

gK)

where

1/2 .LE.£ .LT. 1, and
=

EXP (PROD)

(200 + K)

Fixed-point binary: PROD = N + g, where
N = INT(PROD)

integer part of PROD,

g = PROD - INT(PROD)

and

= fractional part of

Both N and g have the same sign as PROD.

They

as follows:
returned

are

If AC is an even-numbered accumulator (0 or
2), N is stored in AC+l (1 or 3), and g is
stored

in AC.

is an odd-numbered accumulator, N is

If AC

not stored and g is stored in AC.

The two statements above can be combined as
follows:

is returned to AC \/ 1 and g is returned

to AC,.

Five special cases occur, as indicated in the
following formal description with L = 24 for
floating mode and L = 56 for double mode.

1. If PROD overflows and FIV is enabled, AC \/
1 <-- N, chopped to L bits, AC <-- exact 0.

Note that EXP(N) is too small by 400 and
that -0 can be stored in AC \/ 1.

If FIV is not enabled, AC \/ 1 <-- exact 0,

AC <-- exact 0, and -0 will never be stored.
2.

If 2 ** 1,

,LE, ABS(PROD)

and no overflow,

AC \/ 1 <-- N, chopped to L bits, AC <-- exact

The éign and EXP of N are correct, but
low-order

If 1

bit

information

.LE. ABS(PROD)

.LT.

is lost.

2 ** L, AC \/ 1 <--

The fractional
The integer part N is exact.
part g is normalized, and chopped or rounded

Rounding may cause a
in accordance with FT.
return of + unity for the fractional part.
For I, = 24, the error in g is bounded by 1
LSB in chopping mode and by 1/2 LSB in
rounding mode.
For L = 56, the error in g
increases from the above limits as ABS (N)
increases above 8 because only 59 bits of
7-21

PROD

are

generated.

If 2 ** p .LE. ABS(N)
.LT.
p > 2, the low order p - 2
in error.
If

ABS(PROD)

<--

exact

2 **
bits

(p + 1), with
of g may be

.LT. 1 and no underflow,
and AC <-- g.

There

is no error in the integer part.
The
error in the fractional part is bounded by 1
LSB in chopping mode and 1/2 LSB in rounding
mode.
Rounding may cause a return of + unity
for the fractional part.

PROD

underflows

<--

Errors

will

exact

are

stored

Condition Codes:

<--

For

this

part

FIUV

Interrupts:

<==
<-=
<=-<-=-

before

0
1
1
1

4008

(if EXP

Interrupt

will

occur

not

FIU

enabled,

exact

case

less

if
if
if

enabled,

case

AC.

except

that EXP (AC)

the

discussed

above.

Accuracy:

Discussed

above.

Applications:

-0

can

<--

error

the

(-128).

exact

is
be

fractional

PROD overflows, else FV
(AC) = 0, else FZ <-- 0
(AC) < 0, else FN <-- 0
enabled,

and

than

execution.

<-- g.

and

and FIU

and AC

large

too

correct).

trap

Overflow

-0
and

<--

FSRC

occurs

underflow

are

Binary-to-decimal conversion of a proper
fraction.
The following algorithm, using
MOD, will generate decimal digits D(1l), D(2)
.
« . from left to right.
Initialize:

<--

<-=

number

ABS (X)

While

X #

Begin

PROD

<--

D(I)

<--

converted;

do
<--

10;

1;
INT(PROD);

PROD

INT (PROD);

End;

This algorithm is exact.
It is case 3 in the
description because the number of
nonvanishing bits in the fractional part of
7-22

PROD never exceeds L, and hence neither
nor rounding can introduce error.
chopping

2. To reduce the argument of a trigonometric
function,

ARG * 2/PI = N + g. The low two bits of N
identify the quadrant, and g is the argument
The accuracy

reduced to the first gquadrant.

of N + g is limited to L bits because of the
factor 2/PI. The accuracy of the reduced
argument thus depends on the size of N.

To evaluate the exponedtial function e ** x,
= N + g,

(log e base 2)

obtain x *

then e ** x =

(g * 1ln 2)).

(e **

(2 ** N)

The reduced argument is g * 1n2 < 1 and the

factor 2 ** N is an exact power of 2, which
may be scaled in at the end via STEXP, ADD N
The accuracy of N + g is
to EXP and LDEXP.
limited to L bits because of the factor
The accuracy of the reduced
e base 2).
argument thus depends on the size of N.

(log

MULF/MULD

171{AC)FSRC

MULTIPLY FLOATING,’DOUBLE
15
1

I
B

Format:

MULF FSRC,AC

Operation:

Let PROD =

1
AC

(AC) *

T
FSRC

(FSRC)

If underflow occurs and FIU is not enabled, AC

<=~

exact

Tf overflow occurs and FIV is not enabled, AC

Condition Codes:

Description:

<--

exact

For

all others cases, AC

<--

<-- PROD.

FV <=- 1 if overflow occurs, else FV <-- 0
FZ <-- 1 if (AC) = 0, else FZ <-- 0
FN <-- 1 if (AC) < 0, else FN <-- 0

I1f the biased exponent of either operand is 0,
For all other cases PROD is
(AC) <-- exact 0.

generated to 48 bits for floating mode and 59
The product is rounded or
bits for double mode.
chopped for FT = 0 or 1, respectively, and is
stored

in AC except
7-23

for:

l.
2.

Overflow with interrupt disa
bled.
Underflow with interrupt disa
bled.

For

these

stored

Interrupts:

exceptional

cases,

AC.

If FIUV is enabled, trap
on -0
before execution. If over
flow

occurs,

and

enabled,

the

in AC.

The

the

trap

exact

fractional

with

parts

in FSRC occurs
or underflow

corresponding

occurs

interrupt

the

faulty

result

are correctly

Stored.
The exponent part i's too
small by 400
for overflow.
It is too large by 400
for
underflow, except for
the special case of 0,
which is correct.
Accuracy:

Errors

due

overflow

and

underflow

described above.
1If neither
incurred is bounded by 1 LSB

and

Special

Comment:

1/2

LSB

rounding

mode.

are

occurs, the error
in chopping mode
|

The undefined variable
-0 can occur only in
conjunction with overfl
ow or underflow.
It will
be stored in AC only if
the corresponding
interrupt is enabled.

NEGF/NEGD
NEGATEFLOANNG/DOUBLE
15
1

1707 FOST

NEGF

Operation:

(FDST)
(FDST)

Description:

Interrupts:

{

SETD

]

{

FOST

|—

FDST

<--

exact

<--

(FDST)

else

<--

(FDST)

else FZ2

<--

else

<--

single-

Negate

the

store

result

FIUV

execution.

Accuracy:

{

Format:

Condition Codes:

y —

These

same

enabled,
Overflow

instructions

double-precision

location

trap on
and

are

-0

(FDST) .

occurs

underflow

exact.

number;
'

before

cannot

occur.

SET FLOATING DOUBLE MODE
15

)

170011

{

}

MR 11461

Format:

SETD

Operation:

Description:

Set the DCJ1ll in double precision mode.

<--1

SETF

170001

SET FLOATING MODE
15

)

}

{

ju.

MRA. 11482

Format:

SETF

Operation:

Description:

Set the DCJ1ll in single-precision mode.

<--

SETI

SET INTEGER MODE
15

|
12

00
1

0
i

177002

11
|

Format:

SETI

Operation:

Description:

Set the DCJ1ll for short-integer data.

<--

SETL

177012

SET LONG-INTEGER MODE
16

]

)

[

L
MR

Format:

SETL

Operation:

<=-=

0
11484

Description:

Set

the DCJ1l

for

long-integer

data.

STCFD/STCDF

STORE AND CONVERT FROM FLOATI
NG-TC DOUBLE
AND FROM DOUBLE-TO-FLOATING
12

‘

V6(ACIFDST

MA.11488

Format:

STCFD

AC,FDST

If FD

Operation:
1,

overflow,

(FDST)

FIV

<-=-

and

exact

rounding

causes

In all other cases, (FDST) <-- Cxy(A
C), where
Cxy specifies conversion from float
ing mode x
floating mode v.

~Condition Codes:

Description:

Xx=F,

y=D

y=PF

(single)

STCFD

(double)

STCDF

=D,

<-=

<--

<-=-

0
if

conversion

<--

(AC)

<--

else

(AC)

<--

else

<--

the

current

lower

the

half

current

contents

mode

the

Trap on
enabled

-0

will

because

Underflow

for

trap

occurs

overflowed

STCFD

overflow,

chopped
and

not

occur

FSRC

the
FDST

even

and

the

converted

rounded

stored

else

depending

FDST.

FIUV

accumulator.

occur.

Overflow

cannot

occur

FIV

enabled,

and

rounding

overflow.

result.

This

<=-

-0.

Except

for

must

above,

STCDF

chopping

(FDST)

instruction.

described

bounded by 1 LSB in
in rounding mode.

STCFI/STCFL/STCDI/STCDL

are

causes

exact

double-precision,

FT,

cannot

STCDF

accumulator

STCFD.

with

single-precision,

left-justified

cleared.

mode

the

state

stored

single-precision,

Accuracy:

overflow,

accumulator

Interrupts:

produces

the

mode

incurs

and

error

1/2
-

LSB

STORE AND CONVERT FROM FLOATING OR DOUBLE
TO INTEGER OR LONG INTEGER
12

175(AC+4)DST

MA. 11486

Format:

STCFI

Operation:

(DST) <-- Cxj(AC) if -JL - 1 < Cxj(AC) < JL + 1,
else (DST) <-- 0, where Cjx specifies conversion
from floating mode x to integer mode j.

'JL

Condition Codes:

Description:

AC,DST

I
F

the

if FL
if FD

=
=

0,
0,

largest

L' if FL
D if FD

j
x

integer.

‘2

for

for FL

C,
C,

<--

-JL

1
1

Cxj(AC)

‘

<--

(DST)

else

<--

(DST)
<

else N,

<--

Conversion

performed

representation

integer

else

the

from

data

representation.

floating-point
the

accumulator

If the conversion is to a 32-bit word (L mode),
and an addressing mode of 0 or immediate
addressing mode is specified, only the most

significant
destination

16 bits are
register,.

stored

If the operation is out of the
selected by FL, FC is set to 1
of the DST are set to 0.

the

integer

and

the

range
contents

Numbers
to be converted are always chopped

(rather
This is
cleared
Interrupts:

than rounded) before they are converted.
true even when the chop mode bit FT is
in the FPS register.

These instructions do not interrupt if FIUV is
enabled, because the -0, if present, is in AC,
not in memory. If FIC is enabled, trap on

conversion
Accuracy:

failure

will

These

occur.

instructions store the integer part of the
floating-point operand, which may not be the
integer most closely approximating the operand.
They are exact if the integer part is within the
range

implied

by FL.

7-27

STEXP

STORE EXPONENT
15

175(AC)DST
12

08
T

Format:

STEXP

AC,DST

Operation:

(DST)

<-- EXP(AC)

Condition Codes:

<--

OST

200

(DST)

else

<--

Description:

Convert AC”s exponent
to 2°s complement and

Interrupts:

This instruction will not trap on -0.
and underflow cannot occur.

Accuracy:

This

instruction

from excess 200 notation
store the result in DST.
Overflow

exact.

STF/STD

STORE FLOATING/DOUBLE

174(AC)FDST

MRA.11488

Format:

STF

Operation:

(FDST)

<--

Condition Codes:

AC,FDST

F2Z

C =

Description:

Store

Interrupts:

These

single-

double-precision

number

from

instructions do not interrupt if FIUV is
enabled, because the -0, if present, is in AC,
not in memory. Overflow and underflow cannot
occur.
-

Accuracy:

These

instructions

are

Special

These

instructions

permit

Comment:

exact.

storage

-0

memory from AC.
which -0 can be

There are two conditions in
stored in an AC of the DCJ11l.

One

occurs when underflow or overflow is present
and the corresponding interrupt is enabled.
A
second occurs when an LDF or LDD instruction is
executed and the FIUV bit is disabled.

STFPS

STORE FLOATING-POINT PROGRAM STATUS
15
i

¢]

1702 DST
06

]

) S—

DST

Operation:

(DST)

<--

FPS

Description:

Store

the

floating-point

Special

Bits
bits

12,
the

DST

STFPS

13,
are

Format:

Comment:

status

)

and 4 are loaded with
corresponding bits in

in DST.

0.
All other
the FPS.

STST

STORE FPP'SSTATUS
15
i

1703 DST
12

Format:

Operation:

0
4

STST

Store

1§

0
L

0
-

00
1

{

DST
-

DST

(DST)

(DST
Description:

<=--

FEC

<-- FEA

the FEC

and FEA

in DST

and DST+2.

Note

the

following.
l.

SUBF/SUBD

If the destination mode specifies
register or immediate addressing,
FEC is saved.

a general

only

The information in these registers is
only if the most recently executed
floating-point instruction caused a
floating~-point exception.

the

current

SUBTRACT FLOATING/DOUBLE

.
08

FSRC

173(ACIFSRC

FSRC,AC

Format:

SUBF

Operation:

Let DIFF

(AC)

(FSRC)

If underflow occurs and FIU
<-=

11491

exact

is not enabled,

If overflow occurs and FIV is not enabled, AC

Condition Codes:

Description:

<=--

exact

For

all

others

FC
FV

<-<=--

0
1

FZ
FN

<-<--

1
1

if
if
if

cases,

<--

DIFF.

overflow occurs, else FV
(AC) = 0, else FZ <-- 0
(AC) < 0, else FN <-- 0

<--

Subtract the contents of FSRC from the contents
of AC.
The subtraction is carried out in
single- or double-precision and is rounded or
chopped

and FT

bits

stored

accordance with

in AC

the FPS

except

the

values

The

for:

the FD

result

1. Overflow with interrupt disabled.

Underflow with

interrupt disabled.

For these exceptional
stored in AC.
Interrupts:

exact

If FIUV is enabled, trap on -0 in FSRC occurs
before execution. If overflow
or underflow
occurs, and if the corresponding interrupt is
enabled, the trap occurs with the faulty result
in AC.
The fractional parts are correctly
stored.
The exponent part is too small by 400
for overflow.
It is too large by 400 for

underflow,

which
Accuracy:

cases,

except for

the special case of 0,

correct.

Errors due to overflow and underflow are
described above.
1If neither occurs: for
like-signed operands with exponent difference of
0 or 1, the answer returned is exact if a loss

significance of

Note

that

these

are

one or more

bits

the

only

cases

LSB in chopping mode
double~-precision.

with

either

can occur.
for

which

loss of significance of more than one bit can
occur.
For all other cases the result is
inexact with error bounds of:
1.

7-30

single- or

2. 1/2 LSB in rounding mode with either singleor double-precision.

Special Comment:

The undefined variable -0 can occur only in
It will
conjunction with overflow or underflow.
corresponding
the
if
only
be stored in AC
interrupt

enabled.

TSTF/TSTD
TEST FLOATING/DOUBLE

15
1

1705 FDST

Format:

TSTF FDST

Operation:

(FDST)

Condition Codes:

Description:

<-=-

FV
FZ

<-<--

0
1

<--

Set
to

the
the

if
if

(FDST)
(FDST)

0,
0,

]

else FZ2
else FN

<-<--

0
0

floating-point condition codes
contents

FOST

according

of FDST.

Interrupts:

If FIUV is set, ftrap on -0 occurs before
execution. Overflow and underflow cannot occur.

Accuracy:

These

instructions

7-31

are

exact.

CHAPTER 8
INTERFACING

8.1

INTRODUCTION

This chapter covers topics related to the interfacing of
to

logic

8.2

external

the DCJ1ll.

GENERAL-PURPOSE

(GP)

CODES

An important means of communicating with external logic is through
the use of GP Reads and Writes (see Chapter 3 - Bus Cycles). GP
Reads and Writes are associated with codes that specify the
External
the GP Read or Write cycle.
function performed during
Table
logic interprets these codes to implement system functions.
8-1 summarizes

the GP codes.

Table 8-1 GP Codes and Functions
GP Code

(octal)

000

GP Read

or Write

Function

Reads the power-up mode, HALT

Read

option,
boot

FPA option,

POK,

and

address.

Reads FPA data (if FPA exists)
Reads the power-up mode, HALT

001
002

Read
Read

003

Read

exists) clears the FPA“s FPS.
Acknowledges FPE and reads the FEC

003

Write

Writes FPA 16-bit data

040
100

Write
Write

Reserved for future use
Acknowledges EVENT

014
034

140
214
220

224
230
234

option, FPA option, POK, and
boot address, and (if an FPA

(floating exception code)

(if FPA exists)

Asserts bus reset signal
Signals exit from console ODT

Write
Write

Write
Write
Write

Acknowledges power fail
Negates bus reset signal
Microdiagnostic test 1 passed
Microdiagnostic test 2 passed

Write
Write
Write

Microdiagnostic test 3 passed
Signals entry into console ODT

Specific external logic designs

may

need

interpret

only

For example, a minimal system with no FPA
have
only
would
signal
reset
and no need for POK or a bus
of power-up
reading
the
with
identify
GP
associated
configuration data during the DCJ11”s initializtion sequence.
subset of

the GP

codes.

shown in the flowchart in Paragraph 8.3.2, this is GP code 002.

8.3

POWER-UP AND INITIALIZATION

The DCJ1ll

performs

when

1is

specific

initialized.

sequence

These

of events
initialization

at
power-up
or
microroutines are

described in this paragraph.
Also,
during
power-up
the
DCJ11
reads
the
contents
of a configuration register to determine its
initial mode of operation.
This configuration
register
1is
also
described.
A typical power-up circuit is also provided.

8.3.1
1Initialization Timing - Initialization timing is
shown
in
Figure
8-1.
When external logic asserts INIT for a minimum of 25
clock periods, the DCJ1ll is forced into a power-up
initialization
sequence,
As shown in Figure 8-1, the DCJ1l asserts SCTL shortly
after the assertion of INIT.
SCTL
1is
deasserted
approximately
five clock periods after INIT is deasserted.

{OFFSET) _/—\_/_

INIT o
SCTL

MCLKXD

CLK

\w—-—'mww-—-l/

tIND —

tSCTLLH

’Il
MR 9380

Figure

8~1

1Initialization

8.3.2
1Initialization
Microroutine - The
microroutine
that
~executed
when
the DCJ1l is powered up or initialized is shown
Figure 8-2.
Note that GP codes that indicate some event (such
the

logic

passing

light

a
LEDs

microdiagnostic test) can
for a visual indication of

the

used

by
event.

in
as
external

DCJ11-AA
OPERATION

BUS CYCLE

NOTES

EXTERNAL LOGIC

ASSERTS INTT FOR
A MINIMUM OF
25 CLK PERIODS

GP WRITE

GENERATE

SYSTEM IS NOT

034

MODE

GENERATE GP

SET SYSTEM RESET
FLIP-FLOP

GP CODE OF

GP WRITE

CODE OF

IN CONSOLE ODT

014
~

4
DELAY QOPERATION
FOR 69

NIO

MICROCYCLES

GENERATE
GP CODE OF

GP WRITE

214

NIO

CLEAR MMRO

NIO

CLEAR MMR3

NIO

DELAY OPERATION
FOR 600

CLEAR SYSTEM RESET
FLIP-FLOP

)

MICROCYCLES

CLEAR

PIRQ REGISTER

BUS WRITE

(LOC. 17777772)

CLEAR FPS

NIO

MA. 11446

Figure

8-2

Initialization Sequence

BUSCYCLE

GP READ

DCJ- 11 AA

NOTES

OPERATION

GENERATE
GP CODE OF

READ POWER-UP CONFIGURATION
DATA THAT 1S DRIVEN ON DAL
B8Y EXTERNAL LOGIC.

!
CLEAR CPU

NIO

ERROR REGISTER

(LOC 17777766)

POK
ASSERTED

WRITE 400 TO

BUS WRITE

THE CCR

(LOC 17777746)

BUS WRITE

WRITE 2ZEROES TO
THE MSER

(LOC 17777744)

SET BIT 8 OF THE CCR, WHICH 1S
TYPICALLY IMPLEMENTED BY

THE USER AS THE FLUSH CACHE

BIT (IN CACHE SYSTEMS). CLEAR
THE OTHER CCR 8ITS.

CLEAR THE MEMORY SYSTEM
ERROR REGISTER, WHICH MAY
OR MAY NOT BE IMPLEMENTED
8Y THE USER.

WRITE 177766
TO THE CPU

NIO

ERROR REGISTER
(LOC 17777766}

:
BUS READ

READ THE CPU
ERROR REGISTER
{LOC 17777766)

WRITE ZEROQES
TO THE CPU

N1O

ERROR REGISTER
{(LOC 17777766}

Figure

8-2

Initialization

Sequence

(Continued)

11447

BUS CYCLE

NOTES

DCJ-11-AA
OPERATION

DATA
READ FROM

CPU ERRORREG =
177766

TEST 1 PASSED. CPU ERROR REGISTER

GENERATE
GP CODE OF 220

GP WRITE

WRITTEN AND READ CORRECTLY.

BUS READ

READ MEMORY

LOCATION
00000000

YES

NXM
ABORT

DETERMINE IF EXTERNAL LOGIC THINKS
LOCATION O IS IN NONEXISTENT MEMORY

{IT SHOULD NOT]). IF |T DOES, EXTERNAL
LOGIC TYPICALLY GENERATES AN ABORT.

BUS READ

READ MEMORY

LOCATION
17777700

NXM

ABORT

DETERMINE IF EXTERNAL LOGIC THINKS
LOCATION 17777700 1S IN NONEXISTENT
MEMORY (IT SHOULD). IF IT DOES,

EXTERNAL LOGIC TYPICALLY GENERATES

AN ABORT.
YES

GP WRITE

TEST 2 PASSED. NXM ABORT NOT
GENERATED BY REFERENCE TO

GENERATE GP CODE
OF 224

LOCATION 0 BUT WAS GENERATED

8Y REFERENCE TO LOCATION
17777700.

READ MEMORY

BUS READ

LOCATION
17777560

READ RECEIVER CONTROL

‘

AND STATUS REGISTER (RCSR)

MA. 11440

Figure

8-2

Initialization

Sequence

(Continued)

BUS CYCLE

DCJ-11-AA

NOTES

OPERATION

[

DETERMINE IF EXTERNAL LOGIC
THINKS LOCATION 17777560 (THE
RCSR) 1S IN NONEXISTENT MEMORY

{{T SHOULD NOT). IF IT DOES,

EXTERNAL LOGIC TYPICALLY
GENERATES AN ABORT.

GP WRITE

GENERATE GP CODE

TEST 3 PASSED. NXM ABORT NOT

OF 230

GENERATED BY REFERENCE TO RCSR.

YES

POWER-UP

OPTION

PC
« M{24]

TRAP THROUGH

PS — M[26]

LOCATION 24

BEGIN EXECUTING CODE

POWER-UP

YES

OPTION

1
ENTER CONSOLE QDT

PS «0

POWER-UP

YES

OPTION

PC + 173000
NO

PS «

PC<15:9> «— USER
PC<8:0> -0

340

BEGIN EXECUTING CODE

BOOT

PS - 340

BEGIN EXECUTING CODE
MR

Figure

8.3.3

Power-Up

specified

8-2

Initialization

Configuration - The

setting

bits

Sequence

(Continued)

power-up

configuration

external

(via the DAL) during
the
DCJ1ll’s
initialization
specifies
various
user-defined initial conditions.

shown

in Figure 8-3.

11466

which

is
sequence.

The

read

It
register

800T ADDRESS
FPA HERE
UNUSED -

HALT OPTION

POWER UP MODE
POK

MR.11450

Figure 8-3 Power-Up Cohfiguraton Register
Bit(s)

Name

<15:9>

Boot Addresé

Description
Contains
~seven

the most

bits

(bits

user-defined

significant
<15:9>)

boot

address

used

in power-up mode 3. The lower
bits of the boot address (bits
<8:0>) are zeroes.
FPA

Here

Indicates the presence of an
optional floating-point
accelerator (FPA) when set.
When cleared, the FPA is
not

<7:4>

<2:1>

present.

Unused

These bits are
by the DCJ1l.

Halt Option

Indicates how a HALT instruction
will execute in kernel mode.
1If
set, the DCJ1ll traps through
location 4 and sets bit 7 of the
CPU error register when HALT is
executed.
If cleared, the
DCJ11l enters console ODT when
HALT is executed.

Power-Up Mode

Indicates one of
up mode options,

Bits
2
1

POK

0
1

1
0

not

interpreted

four

power-

Mode

Trap through location
Enter console ODT
Power-up to 17773000

Power-up to the
user-defined address

Indicates
8-7

specified by bits

<15:9>

whether

supply

the power

is operating within

Set

when
value.

8.3.4
Power-Up Circuit - A
8-4 can be used to power-up
INIT

is
a

provided

latched
GP

Read

this

by
of

000

simple

power-up

the

DCJ1ll

002

application,

configuration

power-up

that

normal

range.

acceptable

logic

shown

and

The decoder

being

executed.

only

DAL<8,3:0>

its

circuit such
the DCJ11l.

assertion of ALE.
or

power

The

are

the

PFigqure

AIO

code

indicates

whether

affected

the

configured

indicate that no FPA is present, power-up
mode
0
(trap
through
location
24)
1is
selected,
and
power is always OK.
The DAL is
driven with configuration data when BUFCT
L is asserted
and
a GP

Read

with

code

000

002

occurs.

POWER
UP
REGISTER
74152444

0 t——{>——
+V —o-

—o—t+—r—
3>

GND

TDT
<>

P
<1>

DCJ11

‘

POWER | pup

A10<3:0>

LOGIC

TONT

NIT

AID

AND

)

GP CODE
8
.

F Cc

DAL

<8>

—{D>—F—
<>

GP READ

(20R
0

DECODER

::::>>____

BUFCTL

MR.)11449

Figure

8.4

8~-4

Power-Up Circuit

OTHER MICROROUTINES

Figures 8-5 and
operation
can

microroutine
command,

and

8-6
be

the

illustrate
monitored
by

console ODT

two
other
microroutines
whose
external logic:
the power-down

response

8-8

entering

the

"go"

DCJ11.AA
BUS CYCLE

OPERATION
POWE
R DOWN

GP WRITE

GENERATE

GP CODE
OF
140

2 BUS READS
2 BUS WRITES

TRAP THROUGH
LOCATION 24

HALT\ NO
>'—

INSTRUCTION

EXECUTE
NEXT POWER

FETCHED

DOWN SERVICE
ROUTINE

INSTRUCTION

GP READ

GENERATE
GP CODOF
E

000

SETBIT?

fisgggL

OF CPU ERROR

:>___.

TRAP

THROUGH

LOC
4

POK

ASSERTED

HALT

YES

:>___.

START

INITIALIZATION

SEQUENCE

SETBIT
7
YES

OPTION ~ >——4l
BITSET

OF CPU ERROR

ENTER

CONSOLE
00T
MA-1145)

Figure 8-5

Power-Down

8-9

Sequence

BUS CYCLE

DCJ11-AA

NOTES

OPERATION
TYPE IN G WHILE

IN CONSOLE ODT
MODE

!
GENERATE
GP CODE OF
034

GP WRITE

SYSTEM IS NOT
IN CONSOLE ODT

MODE

]
GENERATE GP

GP WRITE

SET SYSTEM RESET

COOE oF

FLIP-FLOP

014

!
DELAY OPERATION

NIO

FOR 69
MICROCYCLES

i
GENERATE

GP WRITE

NIO

GP CODE OF
214

CLEAR SYSTEM RESET
FLIP-FLOP

—

:
L CL&ARlMMRO j

NIO

CLEAR MMR3

'
DELAY OPERATION

NI1Q

FOR 600
MICROCYCLES

:
CLEAR
PIRQ REGISTER

8US WRITE

{(LOC17777772)

!
CLEAR

N1Q

FPS

MR. 11452

Figure

8-6

Console

Start

Sequence

BUS CYCLE

DCJ-11-AA

QPERATION

NOTES

/
GENERATE

READ POWER-UP CONFIGURATION

GP CODE OF

DATA THAT IS DRIVEN ON DAL

002

BY EXTERNAL LOGIC

:
CLEAR CPU
ERROR REGISTER

(LOC 17777766)

POK

NC)_J

ASSERTED

YES

.
3

BUS WRITE

SET BIT 8 OF THE CCR, WHICH

Tt copl TO

IS TYPICALLY IMPLEMENTED BY

(LOC17777746)

THE USER AS THE FLUSH CACHE

WRITE ZEROES TO

BUS WRITE

BIT (IN CACHE SYSTEMS). CLEAR

THE OTHER CCR BITS.

CLEAR THE MEMORY SYSTEM

THE MSER

ERROR REGISTER, WHICH MAY OR.

(LOC 17777744)

MAY NOT BE IMPLEMENTED BY

THE USER.

WRITE ZEROES TO

BUS WRITE

LOC 17777744

NIO

CLEAR PS

]

BEGIN EXECUTING CODE

Figure

8-6

Console

Start

Sequence

11453

(Continued)

APPENDIX

CHARACTERISTICS

Absolute Maximum Rating
Storage Temperature

Range:

-65 C
C

Active Temperature Range:
Supply Voltage:
Input or Output Voltage

Electrical

-55

v
\Y

\Y
\Y

Min.

High level

70% V

MOS input

IHT

TTL input

ILT

rTL input

current except

ILL

IOH

Low

level

High level

Low

I oL

+0.3V

to +70

+4.75V

leakage

Vcec

+4.75V

Max.

+5.25V

Vss

+70

(except

Units

noted)

Test

Condition

cc
30% Vcc

2.2

level

Input

0.8

-10.0

10.0

0V5VI

0.1

5.0

-2.0

Vcc

2.0

0.4V

< Vee

inputs

(note

Input

current

(note

TEST inputs
Output
at

=-0.3V

Vce

Temperature

Parameter

TEST

Vss

Characteristics

Conditions

Symbol

C
C

+7 .0V

Applied:

Specified Temperature Range
Specified Voltage Range
Test

to +150
+125

high

current
level

Output

current

level

low

0.4V

Symbol

Parameter

I:OHT

Output

OSH

Min.

Max.

Units
mA

-2.0

current

at high TTL
level

High level
sustainer

Test Condition
Vo

2.4V

Voo

1.0V

current

(note
OSL

Low level
sustainer
current
(note 1)

0.2

0.6

Output

-10.0

10.0

ov < Vo

leakage

current
(notes 1,2)

I ccse

Static
supply
(notes

power
current
1,3)

Input

capacitance
(note 4)

Input/output

capacitance
(note 4)
Output

capacitance
(note

DCJ11l

plus

capacitance
external

capacitance
NOTES

Tested

at Vcc

Only

With TEST1

applies

circuit,

Sampled
apply

5,25V,

the

high

impedance

and TEST2 asserted, all
and all other inputs equal

and guaranteed,

to TEST1

TEST2.

but not

condition.
outputs
to Vcc.

tested.

Does

open

not

$Vee

SIGNAL

SUMMARY

TYPE

TTL INPUT

NAME

APPLICABLE DC TEST

IRQ<3:0>, HALT, PWRF,

Viar + Vour 0 T1

EVENT, Ffii"r'%fifinv,
MIs3, CONT,
INIT, FPE

TTL

OUTPUT

DAL<21:16>, AIO<3:0>,

ALE, BUFCTL, SCTL,
STRE, BS<1l:0>, MAP,

Io * Tour + oz

PRDC

MOS

INPUT

TEST1,

TEST2

CLK2

Vg r Vo v T 1L
Ion' Iorr 1oz

MOS OUTPUT

CLK,

TTL I/0

ABORT*

Vivrr Toor Tour

TTL I/0

DAL<15:00>

Vigr Viprr Tonr ! OHT ' I 0z

Power

Vec

T ccsB

Toz° IOSH

* ABORT must be driven with an open collector driver because the

DCJ1l has

a pull-up device that supplies IOSH°

L—‘en
90%

VYou

ety

HI Z

10%

VoL

fo—len
VoM

90%

Hi 2

HI 2

VoL

Vig

10%

H TIHT

REFERENCE

CLK (MOS)

OUTPUT

DVITTL)

VoL

MIRTR,

--‘u" (QUTPUT)

ot y—{ (QUTPUT)

MOS, TTL

-7{

VoL

Vi Vier

Vor

v ViKT

Vie Vet

e (INPUT)

--Q 1) be=
VonVowT

VoL
=+ '

—

pe—(INPUT)

(INPUT)

VgV
tH
YINT
Vit Vier

Vi Vimt

e (INPUT)

VOH - VCC -.04

VoL

tg® DELAY TIME

YoH Your

1= SETUP TIME

th = HOLD TIME

ten” ENABLE TIME
tgis * DISABLE TIME

VoL

IS
MR 8430

Figure A-1

Voltage wWaveforms

APPENDIX B

AC CHARACTERISTICS

Test Conditions:

Temperature
=

Vecc

+4.75V

CMAX =
Requirements

Symbol

Parameter

Min

tINITW

INIT pulse width

t SCTLLH

Initialization

DVDS

(except

Max

Units
clock

periods

225

interval

DAL<15:00>
with
T3

setup,

respect

hold,

respect

'DAL<15:00> setup,
with

respect

DVDH

DAL<«15:00> hold,
with respect to
DV

DVW
DVF
t

DVH

DVS

Pulse

DV Fall

width
time

DV deassertion
with respect to

DV deassertion

with

respect

-0

T4.

MISS

setup

MISS hold

IRQ<3:0>, HALT,

FPE,
PWRF,
VENT setup

(see

note)

noted)

50 pF

Timing

= +70 C

Vss

Symbol

Parameter

IRQ<3:0>,

Min

Units

PARITY setup

PARITY

hold

t.ABS

ABORT

drive

t‘ABD

ABORT

delay

t ABW

ABORT width

40 + tCLKH

CONT setup

CONT

hold

DMR setup

DMR hold

SVCH pRRF, FPE,

HALT,

Max

EVENT hold
(see note)

t
t

PARS

(see note)

PARH

(see note)

CNTS

(see note)

CNTH

(see note)

DMRS

DMRH

(see note)

Note:

Setup

and

sample

Timing

hold

requirements

only

guarantee

recognition

Responses

Symbol

Parameter

‘tCYCLE

CLK

cycle

time

'tCLKH

CLK

high

width

<tCLKL

CLK

low

width

CLK

rise

time

t!,

CLK

fall

time

'tPCYC

CLK2

cycle

CLK2

high

PCLKH

are

point,.

Min

Figure
Max

Units

References

B-1,

B-4

B-1,

B-4

B-1,

B-4§

B-1,

B-4

B=-1,

B-4

time

B-1,

B-3

width

B-1,

B=3

Min
28

Max

Units
ns

Figure

References
B-1, B-3

Symbol
t pCLRL

Parameter
CLK2 low width

t pr

CLK2 rise time

B-1, B-3

t oF

CLK2 fall time

B-1, B-3

t pCcLKD

CLK2 valid delay

tbs

B-1, B-3

t varD

MAP delay

B-1, B-3

t sp

Strobe active

' ns

B~3

Strobe inactive

B-3

t s1p

delay

t p1s

DAL output disable

. B-2

t pALD

DAL valid delay

B-3

t bALH

DAL valid h‘old

B-3

t op

PRDC valid delay

B-3

tp1D

PRDC invalid

B-3

AIO<3:0>

B-3

t AIOD

delay

'n— tPCLKL
MR- 11492

Figure B-1

Clock Timing

"A A

vce

OUTPUT

RIS SELECTED TO PROVIDE

loL OF 2MA AT 0.4 VOLTS

UNDER o—

‘[

TEST

:F"(

/ , N

OUTPUT
UNDER
TES

-0 TEST POINT

SOPF

ALL DIODES ARE EITHER
ING18 OR INJ064
:

=
MA 9422

Figure B-2
Three

Disable

CLOAD * Chax =411 PIN CAPACITANCE

State

Test

Figure B-3

Circuit

TTL

Cutput

ouUTPUT

UNDER oTEST

Test

TEST
POINT

CLoaD T

Figure B-4
MOS

CLK

Output

T2/T6

T3/T?

Test

Circuit

tAI10D
t

- PID

THM—
S Ja
'SO pa—n

-o

MAP

'DMRS o ~ " la—
—

HMH

|e-t5p

OMRH

|
tgp

BS<1:0>

—) N
ts

—»

- ¢

| BYP/FORCE

—

)

\ESD

je-t5p

'0S

= t5D

Jl
""tDH
-

DAL

DALD

'DALH -

DS
-

FAST

READ

A DATA

ADDRESS

MA.11878

Figure B-5

Non-Stretched Bus Read Tim
ing
B-4

Circuit

NA paZe

<—1A10D —*

A10

NN
--lpn-»

5D He—e!

—

tSD—->

h—

—

a— 1D~

le—

1SD -

BYP/FORCE

-—

lg1p—+

w-l5p

CONT

BUFCTL

DAL

TSD—

le—

’

tSIDe

tABS—

" j

|-—

— te—
tABD
y

‘

_—\.L___?‘—’l TCNTH —

‘—

tCNTs—‘Aaw

15D

\___/__\
:
;

toaLD >

—

-—
ISIp—> [—e
e
tgp—

pig

a—

N
—» =—'ABD

ABORT

’

{

- 1sD

—>

{)

;

Loob

|‘

ScTL

N
' —

___"
gD

= 15D

XXX

STREB

IDMRS + ~ TM “* 'DMARH

DR
AL

“—

o
__

LAIQD (1) e——

. e—eliD

PRDC

T2:T6 1377

tsiD

SLOW

—t

READ

9”“

—— 1015
'

'DVH

MA 11582

Figure B-6

cux
AIO

ADC

T2/T6

TI/T7

,
we— TAIOD —

|
:
;r-tpo-l_

i
-~

BUFCTL

ABORT

conT

‘—a

re— g

|
r.—

'SD—

WaAP

~a—ISD

—wlla—1DALH

1SD—

;

—e

e lSD

-—

TABD—

BYP/FORCE

4—

DMG

T ABW

1
Figure B-7

‘SlD"'""I

—+

|
& 'sio

‘

fe—1aBS

—ei

—»

TCNTS

TN
onT

Bus Write Timing
B-5

]

— 'SD

> 8510

_
BUS WRITE DATA

—

o= DALD

pe—

—

tgp—e

MAP

N |

N\ /"\_/'\_F\_/"\J—\._
= TAIOD (1)

_—=

—

Tt T tgp—e

' SD —»
BS

—

>
=-1p|D
i

—oie ‘DALH

le—|

IDALD—»

':_':.'{TFADDRES ><

STRB

— Tt

DAL

Stretched Bus Read Timing

\____

le—'ABD

—

NMit

15Ty

T2/76

T3/7T7

cLx

()

'AIOD

—

\ — [\

[

o prs

_’L-

PROC

- |
1SD le—s

" le—

fe— tpID |

‘—o{

|la—1t5p

AP
tOMRS
o

'a100 (1)

AIO

MAP

’—\_f_\_/_
\__/"\__/_\__/_\_/—\r_/—\__fl
.

DMG

'DMRH

DMR

»
ALE

—*

T7 s

—

]

#'-.\". 'sp

STRB

fe— tsi0

'
SCTL

—

ABORT

o 15D

—=

}4—150
/]

ICNTS

—
CONT

15D —

tsp —
IDALD je
DAL

------

“

|Je=t5p
\

ICNTH

!-p—

—tso

—

DAL H-»{je—

}o—‘suo

GP DATA

—| 6pcooE

t \}

GP DATA

pa—

oo
'
4 tovF
r——— lpyg
———

Figure

T2:T6

cLx

TIT?

General-Purpose Read Timing

'AIOD =+

L\t

IDALD =

tpr

"?'D

e [*lop*
e

'—»

a-tgp

-'1*- 'DALH
GP WRITE DATA

1510~
i

- -

.
Lot

’}._
'siD

NGO

tSD —o

-—

'SD—

MAP

—

)—
i

SCTL
1

e tDALD

D¢

VAN U A U A W A U o W

;

—f-tDALH =%

———<__
GPCOoDE

STRB

F
BUFCTL

> 00D (1)
'PS |

PRDC

DAL

B-8

be—t5p

‘,

OMG

ABORT

N
--

CONT

Figure B-9

General-Purpose Write Timing
B-6

1188

11580

T2/T6

T3/77

AIO

}

S [

'AIOD

4-‘PD:’

MISS

'sD

'p1D e

ISD—

MAP

~—

tA1OD (1)

RS,
tpH-u_—‘E >

PRDC

VeS U

‘

e tivn

tHMS

MAP

DMG

IDMRS # TMo [* IDMRH

DMR

'sD
AL

—

'SID-*

’

151D~

STRB

—

SCTL

—

tgp —

'sp

t510—

—»

ABORT

_taps—»

- 'ABD

|e—

t
'ABD
—

[

ICNTS
— 'ABW
tg D —
BUFCTL

—

==&

‘

]

51D

INTERRUPT

VECTOR

tDALD—»

foa—

=]
TTE e s

INTERRUPT

915.:;: 'DALH

iDVDS—:""— -— !
DH
‘
DV

INTERRUPT VECTOR

LEVEL

(SLOW)

(FAST)

P e

DVW, !

D
G

—

re——1pvs

Figure

CLK
IRQ< 30>
HALT, PWRF,

'sves

T2T6é

'svCH

B-10

TIT?

sves

Interrupt

e lsves
0
!
T

FPE, EVENT

ey e SVCs
»

4 svcs
-

|
T

'sveH
T

'PARS

PARITY

YIGH

Acknowledge Timing

'PARH

TS5

'svcs

'SVCH

'SVCH
1

'PARS|'PARH

-. csssmcossnasaphhemges

i
R

EE)
MR 17494

Figure

B-11

Interrupt Timing

B-7

APPENDIX

DCJ11

C.l1

HARDWARE

DIFFERENCES

The DCJ1l may

however,
features:

replace

does

not

HARDWARE

BETWEEN THE

the

Memory

Switch Register

The

DCJ11l

System

does

Error

contain

Dual

general

SPL,

MTPS,

The

following

11/44

and

Address

17777776

additional

MFPS,

list

applications;

PDP-11/44

(17777750}

hardware

17777754)

(17777744)

(17777570).

11/44:

DIFFERENCES

PDP-11/44

'certain

following

o Cache Data and Maintenance Registers
O

SOFTWARE

DCJ11 AND THE

PDP-11/44

contain

AND

functionality

present

the

between

the

set

TSTSET,

WRTLCK

summarizes

the

the DCJ1l1:

Function

not

instructions.

hardware

differences

Differences

Added

set

bit<ll>.
17777772

PIRQ

17777766

CPU

17777754

Cache

17777752

Hit/Miss

No
Error

difference.

Unibus monitoring
not implemented.

Data

Not
,

select

implemented.
difference.

bits

17777750

Maintenance

Not

17777746

Cache Control

Hardware specific changes
(see Paragraph 5.2.1).

17777744

Memory

Not

Error

17777676

implemented.

No difference.

User

Data

User

Instruction

17777640

PAR

User

Data

No difference.

Instruction’

PAR

17777660

17777656

17777636
to

PDR

difference,

17777620

17777616

difference.

MMR
2

difference.

17777574

MMR1

difference.

17777572

MMRO

Eliminated
mode.

17777570

Switch Register

Not

17772516

MMR3

difference.

User

17777600

PDR

17777576

maintenance

implemented.

17772376
to

Kernel

Data

PAR

Kernel

Instruction

difference.

Kernel

Data

difference.

Kernel

Instruction

difference.

17772360
17772356
to

17772340

PAR

17772336
to

PDR

17772320

17772316
to

17772300

PDR

17772276
to

17772260

Supervisor

Data

PAR

17772256

Supervisor

17772240

No difference.

Instruction

PAR

Supervisor

Data

‘

17772236
to

,
PDR

17772220

difference.

17772216
to

Supervisor

17772200

C.2

Instruction PDR

HARDWARE DIFFERENCES BETWEEN THE DCJ11 AND THE PDP1l1l/70

The DCJ1l may
replace
however,
it
does
not
features:

the

PDP-11/70
in
certain
applications;
contain
the following PDP-11/70 hardware

Stack

Limit Register

(17777774)

Micro

Break

(17777770)

System

Size

Maintenance Register

Memory

Physical

Switch Register

The DCJ1ll
11/70:

Bypass

cache

following

and

17777762)

(17777750)
Register

(17777744)

(17777740,

17777742)

(17777570).

MFPT,
bit

list

(17777760,

Address Registers

contain

MTPS, MFPS,

11/70

Error

does

(17777764)

Registers§

System

The

additional

CSM,
in

TSTSET, WRTLCK

not

present

the

between

the

instructions

PDRs.

summarizes

the DCJ11l:

functionality

the

hardware

differences

Function

Differences

17777776

Added suspended
bit <8>.

17777774

Stack Limit

Not

17777772

PIRQ

17777770

Micro Break

Not

17777766

CPU

17777764

System

17777762

System Size

Not implémented.

17777760

System Size

Not

17777752

Hit/Miss

17777750

Maintenance

Not

17777746

Cache Control

Hardware specific changes
(see section 5.2.1).

17777744

Memory

Error

Not

implemented.

17777742

High Error Address

Not

implemented.

17777740

Low Error

Address

Not

implemented.

User

Data

PAR

difference.

User

Instruction PAR

difference.

User

Data

Address

Error

17777676
to

implemented.
difference.

Not

instruction

implemented.

implemented.
difference.

implemented.

17777660

17777656
to

17777640

17777636
to

PDR

17777620

Added bypass cache,
eliminated access flags
and access modes other

than

and

17777616
to

User

17777600

Instruction PDR

Added

bypass

cache,

eliminated

access

and access
than 0, 2,

modes
and

17777576

MMR2

difference.

17777574

MMR1

difference.

flags
other

17777572

MMRO

Eliminated traps,
maintenance mode, and
instruction complete.

17777570

Switch Register

Not

17772516

MMR 3

Added CSM

implemented.

17772376
to

Kernel

17772360

17772356

Data

Kernel

17772340

bit

<3>,

PAR

difference.

enable

Instruction

PAR

‘

17772336
to

Kernel

17772320

Data

PDR

Added

bypass

cache,

eliminated

access

and

modes

access

than

and

flag
other

17772316
to

Kernel

17772300

17772276

Instruction

PDR

Added

bypass

eliminated
and access
than 0, 2,

‘
Supervisor

17772260

Data

cache,

access flag
modes other

and

'
PAR

difference.

17772256
to

Supervisor

17772240

PAR

,
difference.

Instruction

Data

Added

17772236
to

Supervisor

17772220

PDR

bypass

cache,

eliminated access flag
and access modes other
than 0, 2, and 6.

17772216
to

Supervisor

17772200

C.3

PDR

SOFTWARE

Table C~1
language
PDP-11

Instruction

Added

bypass

eliminated
and access
than 0, 2,

cache,

access flag
modes other
and 6.

DIFFERENCES

summarizes the programming differences
(at the
assembly
level) between
the
DCJ1l
and other processors in the

family.

C-5

PROCESSORS
23/24

Table

C-1

DCJ11

ITEM

LSH11

05/10 15/20 35/40

1. OPR %R, (R) +; OPR %R, — (R) using
the same register as both source and
destination: contents of R are incremented (decremented) by 2 before being
used as the source operand.

OPR %R, (R) +; OPR %R, — (R) using the
same register as both register and destination: initial contents of R are used as
the source operand.

2. OPR %R, @ (R) +; OPR %R, @ — (R)
using the same register as both source
and destination: contents of R are incremented (decremented) by 2 before being
used as the source operand.

OPR %R, @ (R) +; OPR %R, @ — (R)
using the same register as both source
and destination: initial contents of R are

9-0

used as the source operand.

3.0PRPC, X (R); OPRPC, @ X (R); OPR
PC, @ A; OPR PC, A: location A will contain the PC of OPR +4.
OPR PC, X (R); OPR PC, @ X (R), OPR

PC, A; OPR PC, @ A: location A will contain the PC of OPR +2.

4. JMP (R) + or JSR reg, (R) +: contents
of R are incremented by 2, then used as
the new PC address.
JMP (R) + or JSR reg, (R) +: initial contents of R are used as the new PC.

Programming

Diffenences

VAX

ITEM

23/24

LSI1

05/10 15/20 35/40

5. JMP %R or JSR reg, %R traps to 10

J-1

T-11

VAX
NA

(iflegal instruction).

JMP %R or JSR reg, %R traps to 4 (illegal
instruction).

6. SWAB does not change V.
SWAB clears V.
7. Register addresses (177700-177717)
are valid program addresses when used

by CPU.
Register addresses (177700-177717)

time out when used as a program
address by the CPU. Can be addressed
under console operation.

8. Basic instructions noted in PDP-11

Floating Point instructions in bas

machine.

ASH, ASHC, DIV, MUL, XOR

-S0OB, MARK, RTT, SXT instructions*

processor handbook.
>

MFPT Instruction.
The external option KE11-A provides

MUL, DIV, SHIFT operation in the same
data format.
* RTT instruction is available in 11/04 but is different than other implementations.

! Register addresses (177700-177717) are handled as regular memory addresses in the 1/0 page.
2 All but MARK.

ITEM

23/24

LSI11

05/10 15/20 35/40

VAX

60.

The KE11-E (Expansion Instruction Set)
provides the instructions MUL, DIV, ASH,
and ASHC. These new instructions are
11/45 compatible.

The KE11-F (Floating Instruction Set)
adds unique stack ordered oriented point
instructions: FADD, FSUB, FMUL, FDIV.

MFP, MTP instructions

SPL |nstruction

The KEV-11 adds EIS/FIS instructions

CSM Instruction

9. Power fail during RESET instruction is
not recognized until after the instruction

is finished (70 milliseconds). RESET
instruction consists of 70 millisecond
pause with INIT occurring during first

20 milliseconds.
Power fail immediately ends the RESET
instruction and traps if an INIT is in
progress. A minimum INIT of 1 micro-

second occurs if instruction aborted.
PDP11-04/34/44 are similar with no

minimum INIT time.
Power fail acts the same as 11/45

(22 milliseconds with about 300 nanoseconds minimum). Power fail during
RESET fetch is fatal with no power
down sequence.

ITEM

23/24

LSI1

05/10 15/20 35/40

J-11

-1

VAX

RESET instruction consists of 10 microseconds of INIT followed by a 90 microsecond pause. Reset instruction consists of a minimum 8.4 microseconds
followed by a minimum 100 nanosecond

pause. Power fail not recognized until
the instruction completes.

10. No RTT instruction
if RTT sets the “T" bit, the “T" bit trap

occurs after the instruction following RTT.
111t RTI sets “T” bit, “T” bit trap is

acknowledged after instruction following
RTI.
If RTI sets “T” bit, “T” bit trap is

6--0

acknowledged immediately following RTI.
12.if an interrupt occurs during an
instruction that has the “T” bit set, the

NA!

“T" bit trap is acknowledged before the
interrupt.

If an interrupt occurs during an instruc-

tion and the “T” bit is set, the interrupt is
acknowledged before “T” bit trap.
13. “T” bit trap will sequence out of WAIT
instruction.

“T" bit trap will not sequence out of WAIT
instruction. Waits until an interrupt.
Yinterrupts not visible to VAX compatibility mode.

ITEM

23/24

14. Explicit reference (direct access) to

PS can load “T" bit. Console can also
load “T" bit.

Only implicit references (RTI, RTT, traps
and interrupts) can load “T” bit. Console
cannot load “T" bit.

15. Odd address/non-existent references
using the SP cause a HALT. This is a
case of double bus error with the second
error occurring in the trap servicing the

first error. Odd address trap not implemented in LSI-11, 11/23 or 11/24.

Odd address/non-existent references
using the stack pointer cause a fatal trap.
On bus error in trap service, new stack

01-0

created at 0/2.

16. The first instruction in an interrupt
routine will not be executed if another
interrupt occurs at a higher priority level

than assumed by the first interrupt.

The first interrupt in an interrupt service
IS guaranteed to be executed.

17. Single general purpose register set
implemented.
Dual general purpose register set
implemented.

1 Odd address/non-existent references using SP do not trap.

2 0dd address aborts to native mode.

LSI1

05/10 15/20 35/40

VAX

ITEM

23/24

LSI1

05/10 15/20 35/40

T-11

VAX

18. PSW address, 177776, not implemented; must use instructions MTPS
(move to PS) and MFPS (move from PS).

PSW address implemented, MTPS and
MFPS not implemented.
PSW address and MTPS and MFPS
implemented.

19. Only one intérrupt level (BR4) exists.
Four interrupt levels exist.

20. Stack overflow not implemented.
Some sort of stack overflow implemented.

21. Odd address trap not implemented.
Odd address trap implemented.

IT~-0

22. FMUL and FDIV instructions implicity
use R6 (one push and pop); hence R6
must be set up correctly

FMUL and FDIV instructions do not
implicitly use R6.

23. Due to their execution time, EIS
instructions can abort because of a
device interrupt.

EIS instructions do not abort because of
a device interrupt.

24. Due to their execution time, FIS
instructions can abort because of a

device interrupt.

3 Can reference PSW only from native mode.

ITEM

23/24

LSI1

05/10 15/20 35/40

VAX

25. Due to their execution time, FP11
instructions can abort because of a

device interrupt*
NA

FP11 instructions do not abort because

of a device interrupt.

26. EIS instructions do a DATIP and
DATO bus sequence when fetching
source operand.

EIS instructions do a DATI bus sequence

when fetching source operand.
27. MOV instruction does just a DATO
bus sequence for the last memory cycle.
MOV instruction does a DATIP and DATO

¢1-C

bus sequence for the last memory cycle.

28. If PC contains non-existent memory
and a bus error occurs, PC will have
been incremented.

If PC contains non-existent memory

address and a bus error occurs, PC will
be unchanged.

29. If register contains non-existent
memory address in mode 2 and a bus
error occurs, register will be incremented.

Same as above but register is unchanged.

* Integral floating point assumed on 11/23 and 11/24; FP11E assumed for 11/60.

' Implementation dependent.

2 MOV instruction does a DAT! and a DATO bus sequence for last memory cycle.
3 Does not support bus errors.

ITEM
30. If register contains an odd value in

mode 2 and a bus error occurs, register

23/24]

34 | LSH1[05/10|15/20|35/40|

60 | J-11 | T-11 | VAX

will be incremented.

If register contains an odd value in mode

2 and a bus error occurs, register will be
unchanged.

31. Condition codes restored to original
values after FIS interrupt abort (EIS
doesn’t abort on 35/40).
'

Condition codes that are restored after
EIS/FIS interrupt abort are indeterminate.
32. Opcodes 075040 through 075377
unconditionally trap to 10 as reserved

X
X

-1

opcodes.

If KEV-11 option is present, opcodes

€T-O

75040 through 07533 perform a memory
read using the register specified by the
low order 3 bits as a pointer. If the

address, a trap to 4 occurs. If the
register contents are an existent address,
a trap to 10 occurs.

33. Opcodes 210 thru 217 trap to 10 as
reserved instructions.

Opcodes 210 thru 217 are used as a
maintenance instruction.

3Does not support bus errors.
4 Unpredictable.
! Traps to native mode.

X
\

ITEM

23/24

LSIN

05/10 15/20 35/40

J-1

T-11

VAX

34. Opcodes 75040 thru 75777 trap to
10 as reserved instructions.
If KEV-11 options is present, opcodes

75040 thru 75577 can be used as
escapes to user microcode. If no user

microcode exists, a trap to 10 occurs.

35. Opcodes 170000 thru 177777 trap to
10 as reserved instructions.
Opcodes 170000 thru 177777 are
implemented as floating point instructions.

Opcodes 170000 thru 177777 can be
used as escapes to user microcode. |f
no user microcode exists, a trap to 10
oCCurs.

p1-0

Opcode 076600 used for maintenance.

36. CLR and SXT do just a DATO
sequence for the last bus cycle.

CLR and SXT do DATIP-DATO sequence
for the last bus cycle.

37. MEM MGT maintenance mode MMRO
bit 8 is implemented.
MEM MGT maintenance mode MMRO bit

8 is not implemented.

38. PS<15:12>, non-kernel mode, nonkernel stack pointer and MTPx and
MFPx instructions exist even when MEM
MGT is not configured.
1 Traps to native mode.

' Unpredictable.
2 CLR and SXT do DATI-DATO.

ITEM

23/24

PS<15:12>, non-kernel mode, non-

LS1

05/10 15/20 35/40

J-11

-1

VAX
NA

kernel stack pointer, and MTPx and
MFPx instructions exist only when MEM
MGT is configured.

39. Current mode PS bits <15:14> set
to 01 or 10 will cause a MEM MGT trap
upon any memory reference.

Current mode PS bits <15:14> set to 10
will be treated as kernel mode (00) and

not cause a MEM MGT trap.

Current mode PS bits <15:14> set to 10
will cause a MEM MGT trap upon any
40. MTPS in user mode will cause MEM
MGT trap if PS address 177776 not
mapped. If mapped, PS <7:5> and
<3:0> affected.
MTPS in non-user mode will not cause
MEM MGT trap and will only affect
PS <3:0> regardless of whether PS
address 177776 is mapped.

ST-O

memory reference.

41. MFPS in user mode will cause MEM
MGT if PS address 177776 not mapped.
If mapped, PS <7:0> are accessed.

MTPS in user mode will not trap regardless of whether PS address 177776 is

mapped.

1 Unpredictable.
2 CLR and SXT do DATI-DATO.

ITEM

23/24

LSI11

05/10 15/20 35/40

42. Programs cannot execute out of
internal processor registers.

Programs can execute out of internal
processor registers.

43. A HALT instruction in user or super-

visor mod_e will trap thru location 4.

A HALT instruction in user or supervisor
mode will trap thru location 10.
44. PDR bit <0> implemented.
PDR bit <0> not implemented.
45. PDR bit <7> (any access)
implemented.

9T1-0

PDR bit <7> (any access) not
implemented.

46. Full PAR <15:0> implemented.
Only PAR <11:0> implemented.
47. MMR0O <12> —trap-memory
management—implemented.

< 12> not implemented.
MMRO0

< 2:0>—D space enable—
48 MMR3
implemented.

MMR3< 2:0> not implemented.

49. MMR3<5:4> —IOMAP, 22-bit
mapping enabled—implemented.

MMR3<5:4> not implemented.

> + 40.
1 HALT pushes PC & PSW to stack, loads PS with 340 and PC with < powerup address

2Traps to native mode.

J-11

T-11

VAX

ITEM

23/24]

34 | LSI11]05/10]15/20|35/40

J-1

T-11

VAX

50. MMR3<3>—-CSM enable—
implemented.
MMR3 <3> not implemented.

51. MMR2 tracks instruction fetches and
interrupt vectors.

MMR2 tracks only instruction fetches.

52. MFPx %6, MTPx when PS<1 3:12>=

10 gives unpredictable results.

MTPx %6, MTPx %6 when PS<13:12> =

10 uses user stack pointer.

LT-D

' HALT pushes PC & PSW to stack, loa ds PS with 340 and
PC with < powerup address> + 40.
2 Traps to native mode.

APPENDIX
INSTRUCTION

The

execution

instruction

time

for

executed,

the type of
memory
execution
time
1is

time

plus

the

instruction

(2)

the

being
the

referenced.

sum

operand(s)

depends

the mode of

the

address

base

on:

(1)

addressing

TIMING

the

used,

type

and

(3)

In
general,
the
total
instruction fetch/execute

calculation/fetch

time.

The

tables in this appendix can be used to calculate
the length of
instruction
in terms of microcycles (MC).
1In the first group
tables, the first column specifies the
number
of
microcycles
required
to
fetch/execute
the base instruction.
The R/W column
specifies how many of these microcycles are
read
microcycles
and
how
many
are
write
microcycles
(any remaining microcycles are
an
of

NIO).

1If

the

instruction

operands,

destination

table)

1is

source/destination

source/destination
many

these

are

read

The

write

read

must

four
memory

time.

for

periods.

write

are

minimum

(no

based

NIO

eight CLK

Any

and

one

source

The

microcycles

also

the

specifies

(again,

the
four

any

how

remaining

added

will

execution
will vary

the

clock

and

total

clock

times are
depending

memory

lasts

slower

instruction

state of

periods,

periods.

increments

NIO

caused

first wait

four

that

periods,

states

last

two

occur

assumption
CLK

periods,

wait

required,

cycle

cycles

Floating-point instruction
The
actual execution time
being operated on.

increments

stretched

takes

column(s).

many

microcycles

DMA).

are

table

last
how

minimum

must

the

states

read

calculation/fetch
of

separate

reveal

transfer

wait

continue

states

last

DMA

non-stretched

can

tables

the

periods
a

must

last

CLK

made

the

calculation/fetch

are NIO).

numbers

tables

microcycles

memory

involves

reference

and

Further

wait

two

clock

given as
a
on the type

range.
of data

Here

are

Example

two

examples

long

Step
.

does

a MOV

use

system,

RO,@#2044

the

stretched
To

find

S1l,

thereafter

the

may

least

operand

stretched.

increments

refer

again,

into

one of

which

remaining

which

write

microcycle

the

type

account.

stretched

Table

that

the

time

the

for

From

periods.
the
Table

0 calculate/fetch
the operand is already
register file).

1If

cycle

CLK

periods

CLK

periods.

For

the

and

read microcycle

microcycle.

Note

and

that

the

stretched,

the

an NIO microcycle.
Once
memory in the system must be taken

the

lasts

read

cycle

least

be stretched thereafter in
periods.
The write microcycle

The

so,

and may

two CLK

S1.

may

Example

To find the operand calculation/fetch time
for the
destination operand (the contents of
memory location
2044), refer to Table D3.
From Table D3, it is seen
that a mode
3 register 7 calculate/fetch takes 3

one

calculation/fetch

(R0),

microcycles,

Step

last?

eight CLK periods

seen that a mode
microcycles.
Note
availablto
e the DCJ1l (in
takes

tables:

instruction

microcycle

lasts

source operand

Step

the

From the tables, the execution time for
the MOV base
instruction is found to be 1 microcycle
(MC), or four
CLK periods. This consists of one read
and no write
microcycles.
Depending upon the type of memory in the

microcycle

how

1l:

How

Step

may

eight

CLK

periods

and
of two CLK
least eight

increments

lasts at
stretched in increments

two

determination

of the minimum time required, total
microcycles. In this example, It is 1
+ 0 + 3,
or 4 microcycles (which is 16 CLK periods
if no microcycle
stretching occurs).

source

and destination tables for floating
point instructions
negative number in the MC column for
certain mode 2
register 7 operations. This examp
le shows a timing calculation
for one of these.

show

How

long

Step

1l:

does

The

CLRD

#2000

base instruction
microcycles.

instruction

time

for

last?

the CLRD

instruction

Step

From Table F2, the calculation/fetch tim? for the
operand (a mode 2 register
7 reference) is shown as
(-1). This means that one microcycle should be subtracted

from the base instruction time.
for the memory write operation.
cycles

Step

Total

to
up

minimum

account
the

for.

microcycles:

(assumes

However, add one microcycle
There are no memory read

no cycle

stretching).

microcycles

TIMING

SINGLE OPERAND

Mnemonic

Instruction

Execution Source
R/W Table
MC

Dest

Table

General

CLR(B)

Clear

INC (B)
DEC(B)

Increment
Decrement

CcaM(B)

NEG (B)

TST(B)

Complement (1's)

Negate (2's complement)
Test

1
1
1
1
1
1

1/0
1/0
1/0
1/0
1/0
1/0

1
1
1
1

1/0
1/0
1/0
1/0

D4
D4

1
1
1

1/0
1/0
1/0

D4
D3

171

1/1

D3
D4
D4
D4

‘D4
D4

Rotate and Shift

ROR (B)
ROL (B)

Rotate right
Rotate left

SWAB

Swap bytes

ASR(B)

Arithmetic shift right

D4
D4

Multiple-Precision
ADC (B)
SBC(B)

SXT

Add carry
Subtract carry

Sign extend

Multiprocessing

TSTSET

WRTLCK

Test and set

(low bit interlocked)
Wwrite interlocked

TIMING

DOUBLE OPERAND

Mnemonic

Instruction

Execution
R/W
MC

Source

Dest

Table

Sl
Sl

D3
D2

General
MOV (B)

Move

ADD
SUB

Add
Subtract

Q¥P (B)

Compare

1
1
1
l

1/0
1/0
1/0
1/0

1
1

1/0
1/0

Sl
Sl

D2
D4

1/0

Logical

BIT (B)
BIC(B)
BIS (B)

Bit test (AND)
Bit clear
Bit set (OR)

Multiply

DIV

Divide

34 1/0
4
1/0
5
1/0
1
1,0

‘Shift automatically

ASH

Arith shift combined
Exclusive (OR)

ASHC
XOR

1/0

—

Dl
D]l

—

(Note 13)

TIMING

Mnemonic

Instruction

Branch

Not Taken

Taken
MC
RMW

R/W

Branch

Br
Br
Br
Br

BEQ

BPL
BMI

BVC

(unconditional)

if not equal (to 0)
if equal (to 0)
if plus
if minus

Br if overflow is clear
Br if overflow is set
Br if carry is clear
Br if carry is set

BVS
BCC

BCS

SIFSE SH SESESESESY
N

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

4
4

2/0
2/0

4
4

2/0
2/0

4
4

2/0
2/0

4
- 4

2/0
2/0

2/0

(SIS
B N 8]

Branches

BNE

1/0
1/0

2/0
2/0

1/0
1/0

4
4

2/0
2/C

Signed Conditional Branches

BLT

BGT
BLE

Mnemonic

if greater or equal (to 0)
Br if less than (0)
Br if greater than (0)
Br if less or equal (to 0)

Instruction

Br anch

Branch

Not Taken

Taken
MC
R/MW

R/W

BGE

1/0
1/0
1/0
1/0

Unsigned Conditional Branches

BLO

SOB

Branch if higher
Branch if lower or same
Branch if higher or same

Branch if lower

BLOS
BHIS

Subtract 1 and branch

BHI

(if # 0)

1/0

2/0
2/0

4
4

2/0
2/0

2/0

Instruction

JMP

Jump

JSR

Junp to subroutine

Return from subroutine
Stack cleanup

= un

JUMP and SUBROUTINE

Mnemonic

RTS

MARK

5,11)

D1 (Notes 6,7,12)

_—
—-_—

BRANCH

(Notes

DST Table

)

(Note

1l4)

TIMING

TRAP and INTERRUPT

Execution

Mnemonic

Instruction

EMT
TRAP

Emulator trap
Trap

20
20

10T

Input/output trap

BPT

RTI

4/2

Return from interrupt

4/0

CONDITION CODE OPERATORS

)

4/2
4/2

Breakpoint trap

Return from interrupt

RTT

RMW

4/2

4/0

TIMING

Execution

Mnemonic

Instruction

CLC

Clear C

1/0

Clear all CC bits
Set C

3
3

1/0
1/0

Set Z

1/0
1/0
1/0

CLV
CLZ
CLN

Clear V
Clear Z
Clear N

3
3
3

SEV

Set V

1/0

Set N

1/0

ccc
SEC
SEZ

SEN

Set all CC bits

SCC

1,0

1/0

TIMING

MISCELLANEOUS

Execution

Mnemonic

Instruction

HALT

Halt

NOP

(No operation)

WAIT
RESET

SPL

wWait for interrupt
Reset external bus

Set priority level to N

1/0

Move to previous data space

2/0
1/1
2/0

Move from processor (R0<7:0><proc code

1/0

MFPI
MTPI
MFPD

Move from previous instr space
Move to previous instr space
Move from previous data space

MTPS
MFPS

Move byte to PSW PS <€ (svc)
Move byte from PSW (dst) € PS <7:0>

MTPD

MFPT
cSM

R/W

Call to supervisor mode

5
3
5
8
1

Dest

Table

1/0

1/1

1/0
1/0
3/3

Dl
D3
Dl

D3
D3

FLOATING POINT

Mnemonic

Instruction

ABSD

Make Absolute

TIMING

Execution (MC)
Min
Typ Max

ABSF
ADDD

Add

ADDF
CFCC

Add
‘
Copy Floating Condition Codes

CLRD

CLRF
QMPD
QMPF
DIVD
DIVF

LDCDF

Clear
Clear

Compare

Compare
Divide
Divide
Ld&C fromD to F

LDCFD

[d & C from F to D

LDCID
LOCIF
LDCLD

Ld & C Integer to D
Id & C Integer to F
Ld & C Long Integer to D
Ld & C Long Integer to F
Load

LOCLF
LDD
LDEXP
LDF
LDFPS
MODD

Load Exponent
Load
Load FPP Program Status
Multiply and Separate

MODF

Integer and Fraction

MULD
MULF

Multiply
Multiply

NEGD

Negate

NEGE

~ Negate

SETD
SETF
SETI
SETL

STCDF
STCDI

STCDL
STCFD
STCrI
STCFL

STD
STECP
STF

STFPD
STST
SUBD
SUBF
TSTD
TSTF

23
19
41
31

Make Absolute

Set Floating Double Mode
Set Floating Mode

Set Integer Mode

Set Long Integer Mode
St & C from D to F
St & C from D to Integer
St & C from D to Long
St & C from F to D

Integer

St & C from F to Integer
St & C from F to Long Integer
Store
Store Exponent

20
119
102

48
35

5
14

12
24

12
25

18
160
59
24

19
167
63
26

20
31

21
42

26
31

36
52

26
16
17
12

17
18
13

6
202

217

82
165
56
22
18
6

6
268
115
173

61
23
19
6

6
6
6
17

6
20

26
26

38
54

19
23

23
12

Sl
12

6
6

Store
Store FPP Program Status
Store FPP Status

16
8

Subtract
Subtract

9
7

Test
Test

_Table

5
14

37
1l
9

Non

Mode O

122
104

Fl
Fl

12
10

Fl
Fl

'SOURCE AND DESTINATION TABLES:

Table Sl

Source Address Time:

Read

Memory

Microcode

Source

All Double Operand

Mode

Cycles

0-7

Read Only Single Operand

Destination Address Time:

Table D1

1
1
1
2
2
1
2 (Note 1)
2
3 (Note 1)
2
3

2
2
1
4
3
3
6
5
8
4
6

0-7
0-6
7
0-6
7
0-6
7
0-6
7
0-7

1
2
2
3
3
4
4
5
5
6
7

Read

Microcode

Destination

Destination
Register

Cycles

0-7

0-6

Mode

0-7

0-6

Table D2

Cycles

0-6
7
0-7

5
5
6

Memory

0-7

2
3
2

5
9
4
6

Destination Address Time:

(Note 2)
(Note 3)

Read Only Double Operand
Read

Destination
Mode

Destination
Register

Microcode
Cycles

Memory
Cycles

0=-7

1
1
1

7
0-6

4
4

2
1

(Note 2)

5
6

7
0-7

10
5

3
2

(Note 3)

1
2

0-7
0-6

0-6

3
4

0-6
0-7

3
3

Table D3

Destination Address Time:

Destination

Write Only

Destination

Microcode

Cycles

Memory Cycles
Read
Write

0-6

0
1

7
0-6
7

2
6

0-6
7
0-6
7
0-6
7

0
1

1
1

2
6
4
3
3
7

0
1

1
1

1
1.
0
1

1
1
1
1

1
2

1
1

1
2

1
1

-Mode

1
2
2
3

3
4
4
5

0-6

5
6

7
0-7

0-7

Read

Modify Write

Microcode

Memory

Cycles

Read

Write

Table

Destination
Mode

Destination Address

Destination
Register

Time:

Microcode
Cycles

(Note

JMP

Memory Cycles
Read

Write

0-7

2
3

0-7
0-7
0-7

6
5
S

0-7
0-6
7
0-7

0
0

6
6
5
7

3
2
3
3
3
4

4
5
6
6
7

(Note

P i

-0 O

Dest4nation

Destination
Mode

WRHOWONENDNDNFNDFHEFEO

Time:

NOHAOLELONIWIWWN
O

Destination Address

CONONOUOJOuYO
9O
i
)
i
\
|
l
o
1)
o)
o)}
o)
(o))

SNAUUN
LS
WWNNNNHEOO

Table

0
0
0
0

Table

Destination

Address Time:

JSR

Microcode

Memory Cycles

Cycles

Read

Destination

0-7

0-6

0-7

0-6

0-7

Mode
2

Write

0-7

Table Fl

10
10

Floating Source Modes 1-7
Single

Precision

Microcode

Cycles

Memory

3
4

Mode

Write
0

0-6

7
0-7

3
4

3
2

0
0

0-7

Double

Precision

Microcode

Memory

Mode

Cycles

Read

Write

0-7

2
2
3
3
4
5
6

0-6
7
0-6
7
0-7
0-7
0-7

5
0 (Note 15)
6
5
6
7
6

4
1
5
5
4
5
5

0
0
0
0
0
0
0

0-7

Table P2

Floating Destination Modes 1-7
Single Precision
Microcode

Mode

Cycles

0-7

2
2

0-6
7
0-6
7
0-7
0=7
0-7
0-7

3
1
4
3
4
5
4
6

3
3
4
5

6
7

Memory
Read

Memory
Write

0
0
0
1
1
0
1
1

2
2
1

2
2
2
T2

Memory

Double_PteCision
Mode

0-7

2
2

0-6
7

3
3
4
5
6
7

0-6
7
0-7
0-7
0-7
0-7

Table

Microcode
Cycles

Read

5
5
(=1) (Note 15)
6
5

Write

0
0
O

4
4
1l

1
1
0

4
4
4

7
6
8

1
1
2

4
4

Modify Write

Modes

Floating

Read

Single

Precision

Microcode

Memory

Mode

Cycles

0-7

0-6

3
3

1l (Note 15)

0-6
7

4
5

0-7
0-7
0-7
0-7

6
5
6
7
6
8

2
1

3
3
2

2
2
2

3
3

2
2

6
7

1-7

D-11

Read

Write

Table F3

Floating Read Modify Write Modes 1-7
Double Precision

Mode

Microcode
Cycles

Memory

Read

Write

0=-7

2
2
3
3

0-6
7

9
(=2) (Note 15)

4
1

0-6
7

10
9

5
5

4
4

0=-7

5
6
7

0-7
0-7
0-7

11
10
12

5
S
6

4
4
4

Table F4

Integer Source Modes 1-7
Integer

Microcode

Memory

Read

Write

Mode

Cycles

0-7

2
2

0-6
7

2
0 (Note 15)
3

3
4
5
6
7

7
0-7
0-7
0-7
0-7

2
3
4
3
5

2
1
2
2
3

0
0
0
0
0

Memory
Read

Memory
Write

0-6

Long

1
1

0
0

Integer

Mode

Microcode
Cycles

0-7

2
2
3
3

0-6
7
0-6
7

4
0 (Note 15)
5
4

2
1
3
3

0
0
0
0

0=7
0-7
0-7

6
5
7

3
3
4

0
0
0

5
6
7

0=-7

D-12

Table

Integer

Destination Modes

1-7

Integer

Mode

0-7

2
2

0-6

3
3

4
5
6
7

0-6
7
0-7
0-7
0-7
0-7

Microcode
Cycles

Memory
Read

Memory
Write

2
2
2
3
2
3

0
0

1
1

0
1

1
0

1
1

4
3

1
1

Microcode
Cycles

Memory
Read

Memory
Write
2
2

Long

Mode

1
1

Integer

0-7

2
2
3
3
4
5

0-6
7
0-6
7
0-7
0-7

6
7

4
4
2
5
4
5
6

0-7
0-7

0
0
0
|
1
0
1

5
7

2
2
2
2
2

D-13

NOTES

h sourceY and
one read ifif botWRI
rocycles (MC)creand
Subtract 2 mic
TE-ONL or
t PC, oI
modes autode or men
destination WRI
17 is used.
READ-MODIFY- TE mode 07
47
tination mode kD-MODIFY-WRITE D des
READ-ONLY andualREA
For boothe
rations. ..or
m 3 REA isopeacc
s act lyoneperofforthe
referencepur
in
ted
oun
Ds
REA
poses,
keeping
EXECUTE, FETCH TIMING.
on mode 57
TE destinati
D-MODIFY-WRIREA
READ-ONLY andualREA
kD operations. For inboothe
m 4
references act ly perfor
the READs is accounted for
one of
keeping purposes,
NG TIMING.
EXECUTE, FETCHI

Subtract 1 MC if the link register is PC.

Add 1 MC if the source operand is negative.

subtract 1 MC if the source mode is not zero
Add 1 MC if the quotient is even.

ination
the PC is used as a dest
Add 5 MC and 1 read if rce
|
.
used
mode 47 or 57 is not
register, but only if sou

Add 2 MC if overflow occurs.

Add 1 MC per shift.

Add 1 MC if source operand <15:6> is not zero.

10.
11l.

12.

13.

Subtract 1 MC if one shift only.

as a destination
Add 4 MC and 1 read if themodPCe 47is orused
57 is not used.
register, but only if source
Divide by zero executes in 5 MC (see note 6).

1 MC if a left shift. es(No8,tes10,8, 9,
Timing for no shift.MC Add
11
for a right shift. (Not
11 apply.) Add 2
apply.)

14.

15.

Add one MC if a register other than R7 is used.

d operands. The
only access single wor
Mode 27 references ted
has been compensated in order to

execution time 1listhe total execution time.
accurately compute

D-14

APPENDIX

GLOSSARY

Bus lock An indication to memory to prevent or "lock" out other accesses to
that location until it is unlocked.
This occurs during an RMW
read bus microcycle with the bus lock control bit asserted. Memory
is automatically unlocked by the following Bus Write microcycle by

that

processor.

Cache bypass Unconditionally
the cache entry

bypass cache and access main memory
is valid, typically invalidate it.

directly.

1If

Cache force miss :
Unconditionally bypass cache and access main memory directly.
the cache entry is valid, typically do not invalidate it but

1If

ignore

Data

it.

stream

bus

Any microcycle
microcycle.

cycle

which

a Read,

Read/Modify/Write

Demand abort An abort during

demand

bus

Write

microcycle.

Instruction stream bus cycle Any microcycle which is a prefetch microcycle.

Internal

registers -

These

explicitly

MMR1,

MMR2,

addressable

registers

Hit/Miss,

CPU Error,

MMR3,

are

the PS,

PARs,

PIRQ,

MMRO,

and PDRs.

Predecode An indication to decode the next PDP-11 instruction. This occurs
during a microcycle in which the DCJ1l1l asserts PRDC and decodes
the prefetch buffer contents as the next PDPll instruction.

Read/Modify/Write
Two

consecutive

microcycle and the
microcycles access
Request

abort

abort
or

operation in

which

the

first

second is a Bus Write microcycle.
the same location.

Bus

Read

Both

during

management

(RMW)

microcycles

request

address

bus

abort,

microcycle.,
it

will

not

stretch

is
the

a memory
microcycle.

INDEX

Abort (ABORT) 1line,
Aborts, 1-12, 1-13
AC characteristics,

through

Address

2-6,

Cache memory

2-11

through 5-8

B-1

B-7

input/output

(AIO)

line,

latch enable
2-5, 2-12
Addressing modes

(ALE)

line,

2-3,

2-10

Address

direct
direct
direct

select

(BS)

6-7
6-8

6-3

lines,

2-13

cycles
AIO
bus
bus

codes for, 3-2
read, 3-4 through 3-6
write, 3-6 through 3-7

duration
of, 3-2
general-purpose read,
general-purpose

write,

3-8
3-9

interrupt acknowledge,
non-1/0 (NIO), 3-3
parts

Bus

of,

write

3-3

cycle,

3-6

through

cache

control

bits,

3-7

environment,

floating-point accumulators
5-18

and,

general

references,

_
go command, 5-16
initialization, 5-11
invalid characters, 5-19

line feed command, 5-14
octal notation for, 5-18
output sequence, 5-12
proceed command, 5-16
processor status word
designator, 5-15
receiver control/status
register (RCSR), 5-9

5-10

(RBUF),

slash command, 5-13
stack pointer references,
5-18

terminal

interface,

5-9

5-19

transmitter control/status
register

(XSCR),

buffer

transmitter

(XBUF),

5-10

5-11

Continue (CONT) line,
Control chip, 1-1
CPU error

5-2

5-1 through 5-2
general operation, 5-3
in multiprocesing

5-17

control-shift-S command,

timeout,

Cache control register
force cache miss bit, 5-2
unconditional cache bypass
bit, 5-2

uninterpreted
Cache memory

5-17

receiver buffer

3-10

read cycle, 3-4 through
non-stretched, 3-5
stretched, 3-5

5-12 through

command set,

5-15

control (BUFCTL)
2-4,

Bus

Clock 1 (CLK) line, 2-5, 2-12
Clock 2 (CLK2) line, 2-5, 2-12
Console start microroutine,

internal

2-2,

2-11

Buffer

2-6’

2-12

ConsOle ODT, 5-9 through 5-19
address specification, 5-17
carriage return command, 5-14

direct index, 6-9 through
6-11
deferred, 6-11 through 6-14
double-operand, 6-3 through
6-4
general, 6-1 through 6-3
PC relative, 6-14 through

Bank

line,

(MISS)

Cache miss

5-4

8-10 through 8-11

6-18
single-operand,

(continued)

sample implementation,

2-4,

2-12

1-15

througt

lines,

2-2'

1-16

(CCR)
,

Data/address
2-11,

(DAL)
2-13

lower, 2-2
upper, 2-2
Data chip, 1-1
Data valid (DV)

5-4

'Index-l

line,

2-4,

2-13

characteristics,

A-1

through

Floating point

DCJ11l
DCJ1l

block
pin

diagram,

1l-1

assignments,

2-1

Direct memory access (DMA)
mechanism, 1-17
Direct memory access (DMA)
requests

3-11
memory

Direct

(DMR)
Event

(EVENT)

line,

7-2

2-10

zero,

numbers,

7-1

Floating-point exception (FPE )
line, 2-8, 2-10
Floating point instructions
7-12

7-12

ADDF,

7-13

ADDD,

7-13

CFCC,

7-14
7-14

CLRF,

CLRD,

7-14

CMPF,

CMPD,

7-15
7-15

DIVF,

7-15

DIVD,

7-15

LDCDF,

7-16

LDCIF,

7-17

LDCID,

7-17

LDCLF,

7-17

LDCLD,
LDEXpP,

7-17

LDF,

MULD,

7-23

NEGF,

7-24.

NEGD,

7-24

SETF,

7-25

SETI,

7-25

SETL,

7-25

STCFD,

7-26

STCDF,

7-26

7-3

through

processing,

(GP)
read

1-17

codes,
cycle,

3-8

space

and

space,

(INIT)

2-12
Instruction set

ADC,

ADCB,

6-34

ADD,

6-39

ASH,

6-40

ASHC, 6-41
ASL, 6-31

ASLB, 6-31
ASR, 6-30
ASRB, 6-30
BCC,

6-48

BCS,
BEQ,

6-48
6-47

BGE,

6-50

BGT,

6-50

BHI,

6-51

BHIS,

6-52

BIC, 6-43
BICB, 6-43
BIS,

Index-2

8-1

‘General-purpose registers, 1-2
General-purpose write cycle, 3-9
Ground (GND) pins, 2-10, 2-11,

Initialize

7-19

7-20

7-31
7-31

2-24

4-2

through 4-3
Initialization microroutine,
through 8-6

7-19
LDFPS,
7-20

7-20
7-23

7-29

TSTF,
TSTD,

General-purpose
General-purpose

LDD,

MODF,

7-29

SUBD,

Halt line, 2-6, 2-11
Halting DCJ1ll operation,

7-18

MODD,
MULF,

7-29
7-29

STST,
SUBF,

2-13

7-16

LDCFD,

7-28
7-28
7-28

7-7
Floating-point

undefined variables, 7-2
Floating-point exception code
(FEC) register, 7-7

ABSD,

7-26
7-26

1-2

ABSF,

STCDI,
STCDL,

accuracy, 7-9 through 7-10
addressing, 7-8 through 7-9
Floating-point status (FPS)

through

7-3

nonvanishing

7-26

STFPS,

arithmetic

formats,

7-26

STCFL,

STF,
STD,

grants,

2-9,

STCFI,

STEXP,

access request
line, 2-8, 2-11

Floating-point
data

and

instructions

(continued)

A-4

6-43

line,

2-5’

8-2

BIT,

6-43
6-42

SBC,

BITB,

6-42

SBCB,

BISB,

BLE,

6-51

BLO,

6-52

BLOS,

6-35
6-66

SEN,

6-66
6-66
6-66

SEV,
SEZ,

6-51

6-35

SEC,

BLT,

6-50

BMI,

6-47

SCC,

6-66

BNE,

6-46

SPL,
SUB,

6-61
6-39

BPL,

6-47

BPT,

6-58

BR,

SWAB 6-33
SXT, 6-35
TRAP, 6-58

6-45

BVC,

6-48

BVS,

6-48

TST,

CCC,
CLC.
CLN,

6-66
6-66
6-66

WAIT,

CLV,
CLZ,
CLR,

6-66
6-66
6-26

CLRB,

6-28
TSTB, 6-28
TSTSET, 6-29
6-64
WRTLCK, 6-29
XOR, 6-44

byte instructions, 6-22
formats, 6-19 through 6-22
list, 6-23 through 6-26

6-26

COM, 6-26
COMB, 6-26
cCMP,

symbols,

CMPB,

6-38

CSM,

6-61

DEC,

6-27

DECB,

2-7
interrupt
2-7,

request (IRQ) lines,
2-11
direct memory access request

6-27

DIV,

6-42

EMT,

6-57

power

HALT, 6-64
I0T, 6-58
INC,

6-52

JSR,

6-53

MARK,

6-60

MFPS,

6-36

MFPT,

MOV,

event

6-27

JMP,

6-37
6-65

MFPI,

6-65

MTPD,

6-65

Map

NOP,

RORB,

interrupt
multiple

6-65

6-31

RTS,

6-55

RTT,

6-59

and

with,

6-67

6-59

space

4-18
instruction

6-28

RTI,

line,

Index-3

2-7,

2-11

4-8
4-2

space,

4-3

implementation,

ROL, 6-32
ROLB, 6-32
ROR,

(MAP)

through

6-28

RESET,

2-10

management

addressing, 4-1
fault recovery,

6-65
MTPS, 6-36
MUL, 6-41

NEG,

2-9,

request

enable

Memory

MTPI,

NEGB,

2-10

(IRQ) lines,
2-7, 2-11
Interrupts and traps,
1-11
through 1-14

6-65

MFPD,

(EVENT),

Interrupt

6-37

MOVB,

(DMR), 2-8, 2-11
fail
(PWRF), 2-8,

floating-point exception
(FPE), 2-8, 2-10

6-27

INCB,

6-18 through 6-19
acknowledge cycle, 3-10
and DMA control lines,

Interrupt
Interrupt

6-38

4-14

through

back-up/restart
4-14

conditions,

4-8

page

faults, 4-14
address registers

page
-~

(PARs), 4-6
descriptor registers
(PDRs), 4-6

physical
4-3
register

address construction
through 4-5
#0
(MMRO), 4-9

(MMR1),

4-10

(MMR2),

4-11

Memory

management

Power-up

(continued)

enable

relocation

error flags,
page address

bits,

initialization,

4-10

4-9
space

bits, 4-10
page number bits, 4-10
processor mode bits, 4-10
reserved
Memory

bits,

4-10

management

Memory

management

(MMR2)
,

enable

mode

mapping

space

bits,

Memory

system

Non-I/0

(NIO)

Program ‘interrupt
register,

Receiver

Stack

bit,

instruction

1-5

protection, 1-7 through 1-10
priority level bits, 1-5
trace/trap bit, 1-6

bit,

I/0 map bits, 4-11
supervisor, and user

reserved

1-11
bits,

buffer

request
(PIRQ),

1-15

(RBUF)

5-10

4-13

Kernel,

mode

2-1.
1-3

control/status
register (RCSR),

5-9

4-11

22-bit

4-11
enable CSM

processor

Receiver

4-11

(MMR3),
enable

8-6

8-8

Predecode (PRDC) line, 2-7,
Processor status word (PS),
through 1-11
condition code bits, 1-6

4-5

management register
(MMRO)
, 4-9

configuration,

through

bits,

4-13

4-11

registers,

1-17

bus

3-3

protection,

1-16

Start/stop control lines, 2-5
halt (HALT), 2-6, 2-11
initialize (INIT), 2-5, 2-12
Status signals, 2-6
abort (ABORT), 2-6, 2-11
cache miss (MISS), 2-6, 2-12
map enable (MAP), 2-7, 2-11
parity error (PARITY), 2-6,
2-11

pins,

predecode (PRDC), 2-7, 2-12
Stretch control
(SCTL) line,

2-9

XTALI,

2-9,

2-12

XTALO,

2-9,

2-12

Strobe
System

2-5, 2-12
(STRB) line, 2-5, 2-12
control lines,
2-2

address
Page

address

Page

descriptor

registers,

access

control

bypass

cache

expansion

page
page

bank

field,

bit,

4-8

4-7

direction

bit,

4-7

length field, 4-7
written bit,
4-7

reserved

Parity

4-6

registers

bits,

4-8

error

(PARITY) line, 2-6,
2-11
Pin description summary, 2-10
through 2-13
Pipeline processing, 5-20
through 5-22

Power-down

microroutine,

Power

fail
(PWRF)
2~10

Power

pins,

ground

line,

2-13
power

Power-up

(Vcc),

2-10,

data

valid

(DV),

circuit,

2-11

2-13

Test

(TEST1l)

line,

2-9,

Test

(TEST2)

line,

2-9,

Test pins, 2-9
test 1
(TEST1l),
test

(TEST2),

2-10

2-9,

2-10

2-9,

2-12

Timing signals, 2-4
address latch enable
clock
clock

2-8,

(ALE),

1
2

2-12
(CLK), 2-5, 2-12
(CLK2), 2-5, 2-12

control

2-12
strobe
(STRB),

2-11,
2-11,

2-2,

buffer control (BUFCTL), 2-4
2-13
continue (CONT), 22-12

stretch
2-10,

(AIO),

2-5,

8-9

2-9

(GND),

input/output

2-3, 2-10
select
(BS),

[
=

Oscillator

cycle,

2-13

8-8

Index-4

(SCTL),
2-5,

2-5,

2-12

Transmitter buffer register
(XBUF), 5-11

Transmitter control/status
register (XSCR), 5-10

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