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EK-CIBCI-UG-001

October 1986

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Document:	CIBCI Adapter User/Installation Guide
Order Number:	EK-CIBCI-UG
Revision:	001
Pages:	160
Original Filename:

OCR Text

EK-CIBCI-UG-0001

Prepared by Educational Services

of
Digital Equipment Corporation

1st Edition, October 1986

The information in this document is subject to change without notice and should
not be construed as a commitment by Digital Equipment Corporation. Digital
Equipment Corporation assumes no responsibility for any errors that may
appear in this document.

Printed in U.S.A.

This document was set on a DIGITAL DECset Integrated Publishing
System.

Class B Computing Devices:

Notice: This equipment generates, uses, and may emit radio frequency energy.
The equipment has been type tested and found to comply with the limits for a

Class A computing device pursuant to Subpart J of Part 15 of FCC Rules, which
are designed to provide reasonable protection against such radio frequency interference
when operated in a commercial environment. Operation of this equipment in a
residential area may cause interference in which case the user at his own
expense may be required to take measures to correct the interference.
The following are trademarks of Digital Equipment Corporation:

dlifalilt]al e
DEC
DECmate
DECset
DECsystem-10
DECSYSTEM-20
DECUS
DECwriter

DIBOL
MASSBUS
PDP
P/OS
Professional
Rainbow
RSTS

RSX

Scholar
ULTRIX
UNIBUS
X
VA
VMS
VT
Work Processor

................

CONTENTS

INTRODUCTION

SCOPE ...t
GENERAL DESCRIPTION.......cooiiiiieeee et

W D —
DN

Go Lo Lo W

W
st

SEISANE

o
ek
ok
o
ok
e
o
P

Page

COMPONEIILS ...t

ok ok foed

ok ok

CHAPTER 1

B WWWwwwwwio
N NN —

PREFACE

1-1
1-1

e e et
e e e e e e e e e e e e e e e e e e e nnnnnans

1-1

FEALUTES ..o
et e e et e e e e e raaaas

1-2

CONFIGUIALIONS ....oviviiiiiiiitieceeee
e et e e e e e e e e e e e e e e e e e ee e
enes
GENERAL SPECIFICATIONS ...

1-3
1-4

Environmental SpecifiCations .......cccooeeeeiiiiiiiiiiiiiiiiccciee e,

1-4

Mechanical SpecifiCationS ..........ocooiiiiiiiiiiiiceee

1-5

Electrical SpecCifiCatiOns ........eeeeeiiiiiiiiiiiiiieeeee e
VAXBI Bus SpecCifications..........ccceeeviiiiiiiiiiiieieeceeeeeiieee e
CIPA Bus SpecifiCations...........cceeveeeeeiiiiiiiiiiiiieeeeeeee e,
CI Bus Specifications...........ccoeoiiiiiiiiii
REFERENCE DOCUMENTS (Table 1-2) ..o
PHYSICAL HARDWARE DESCRIPTION ....ooviiiiiiiiieeeeeeeeee
Host Processor Interface Hardware ...........cccooooeiiiiiiiiiiiiiiiiie,

Computer Interconnect Interface Hardware.............ccooooeiiiiiiiiiiiiin,
CI Port Adapter Assembly..........oooooiiiiiiiiie
CIPA Cabinet ......oooviiiiiiiiiiicceeeee

1-5
1-6

1-6

1-7
1-8
1-9
1-9
1-12
1-12

1-13

INTRODUCTION ..ottt
OPERATING ENVIRONMENT ...
Physical EIEmMents ..........uuvviiiiiiiiiiee
e
Environmental Elements.................c.ccooooo
Grounding Elements..........ooooviiiiiiiiiii
e
CIBCI SYSTEM CONFIGURATIONS. ..o
UNPACKING AND INVENTORYING ...
VAX 8200/8300 SYSLEIMIS ...eoeeeiieiiiieeeieeeeeeeeeeeeeeee e,

2-1
2-1
2-1
2-1
2-2
2-2
2-2
2-2

CHAPTER 2
2.1
2.2

2.2.1

2.2.2
2.2.3

2.3
2.4

2.4.1

2.4.1.1

Verifying Shipment Inventory ............ccccccviiiiiiiiiiiiiiiiiieeeeeeeeeee,L

2-2

2.4.1.2

Unpacking the Shipping BoXeS...........cccciiiiiiiiiiiiceee

2-3

Unpacking the H9642 CIPA Cabinet Carton..........c..cooeeeeeeevieeeneeennnn.
VAX 8500/8550/8700/8800 SYStEIMS......ccevvvvveeieeeeiiiereieeeeeeeeeeiiieeeee
e,
Verifying Shipment INVENtOrY .......ccooeeiiiiiiiiiiieiiiieeee e
Unpacking the Shipping BoXeS............ooiiiiiiiiiiiiieceeeeeeeeee,
Unpacking the H9652 Expander Cabinet.............cccocveeeeiiiiiiiiiiinnn.en.

2-5
2-7
2-7
2-8
2-8

2.4.1.3

2.4.2
2.4.2.1
2422
2.4.2.3

i1l

CONTENTS (Cont)
Page
2.5

2.5.1

2.5.1.1

2.5.1.2
2.5.2
2.5.3
2.6
2.6.1

2.6.2
2.7

2.7.1

2.7.2
2.7.3

MECHANICAL INSTALLATION (System Level)....ccccoocoiiiiiiiiiiis,
VAX 8200/8300 SYSLEITIS ..veeevveeeirreeriiieeiirieeiiieeeiiereseee st
CPU Cabinet Preparation.........oc..eeeevieiiiiiiiireiiiiiie i
H9642 CIPA Cabinet Preparation.........ccccovviiimmiiiiiinnnnnnneneeceiiiiiieenean
VAX 8500/8550 SYSLEITIS ..vveevreeeriiireiiieiiiiirireiiieeesiia s
VAX 8700/8800 SYSLEIMS ...uvvreeeiriieeriiiiiiiiiiieeeeiiree ettt
MECHANICAL INSTALLATION (Add-On Level)...ccccccccceeiiiiiiiiiiieee
VAX 8200/8300 SYSTEITIS ...eeevrereirieeeieieiiiieeiiiieeeirereeiree e
VAX 8500/8550/8700/8800 SYSLEMS.....cevvurririiiiirieniiiieeeniicee i
ELECTRICAL INSTALLATION AND CONFIGURATION ......cccccoiiiinnnne.
T1017 and T1018 Module Installation..........coceevimiiiiiiiiiiiiiii
CIPA Backplane Jumpers Verification..........coooviremiiiiiniieeiniii,
ee
Node Address Switch Verification ............ceeeeeeieeiiiiiiiiiniiiiiii

2-10
2-10
2-10
2-14
2-23
2-28
2-38
2-41
2-45
2-48
2-48
2-54
2-58

e e e e e e e r s e e esesns
tt
e e e et
e ettt
INTRODUGCTION ..ot
o
..
ION
VERIFICAT
POWER SETUP AND
snre
eireeeisee
et
eriiiiiirie
eririeeniei
..ecvveeere
SYSLEITIS
VAX 8200/8300
n,
iiiieeeiicneniiine
iiiimiiiiiiiiiiene
SyStemsS.......cuv
00/8800
VAX 8500/8550/87
.t
..
ION
VERIFICAT
DIAGNOSTIC
ssntee
e
VAX 8200/8300 SYSLEITIS ..vvreruvreerieeeenirieiiiireiineeesiieeesire
t
e
ee
....coovvvreeeiiiiee
SETUD
Preliminary
Loading the Diagnostic Supervisor Program.........ccccccoeviiiiiiiennniiinn,
e
Repair Level Testing......ccceevvuiiiiiiiiiiiiiiiieiie
CI Bus €Cable TeStiNg......cooviiiiiiieeeeeeieieeeeeeeeeceeeiee e
Functional Level TeStINg ......ovvuveeiiiiieieeeeiiiiiiiiiiiiiiiie e
VAX 8500/8550/8700/8800 SYSLEIMS......cuvvviiiiiiiniiiiieeiiiiiine e,

3-1
3-1
3-1
3-4
3-5
3-6
3-6
3-6
3-17
3-13
3-13
3-16

(O iSO
I\ B

(T SR USRS
I

EoGRUS IS I VSR VS IRV I S I VS SR VS SRS IR VS SR USSR US SR US I 0O B o0 B |0

CHAPTER 3

CHAPTER 4
4.1

4.1.1
4.2
4.2.1

4.2.2
4.2.3
4.3

4.3.1

4.3.2
4.3.3

4.3.4
4.3.5

Preliminary SETUP ....coicvriereiiiee e
Loading the Diagnostic Supervisor Program...........cccccceiniiiiinin,
Repair Level Testing......cccoeeriiiiiiiiiiiiiiiieiiiiesiie e
e
CI Bus €Cable TeStINg......coiiiiiiiiieeeeeeeeeeeeeeeeeee
e
Functional Level Testing ......ooovviiiiiiiiieeeiiiiiiieiee
MAINTENANCE VERIFICATION ...t

3-16
3-17
3-17
3-23
3-23
3-27

VAXBI ADDRESS SPACE ... oo
VAXBI I/O Address SPacCE .....cccueeeeueiiiiiriiiiiiiieniieesice et
CIBCI ADAPTER NODE. ... oottt
AQATESSIIIE ...eeveeevie ettt ettt
RPP
PP PS ST SPPIIE
OO P S URRUUUPPPPPYPPRRVPPTOPRT
L8 (0] 1111V
TR
tt
REEISTETS .. vvevieeveeneeeeee sttt ee e ea et
VAXBI REQUIRED REGISTERS ...,
Device Type Register (DTR) ..ccoooviiiiiiii
VAXBI Control and Status Register (BICSR).....cccccccoiiiiiiii

4-1
4-1
4-1
4-1
4-4
4-4
4-4
4-6
4-6

Bus Error Register (BER).....coooiiiiiiiiiii 4-9
Error Interrupt Control Register (EICR) ..., 4-11

Interrupt Destination Register (IDR)........ooooiiiii 4-12
1v

CONTENTS (Cont)
Page
4.3.6
4.4

4.4.1
4.4.2
4.5

4.5.1
4.5.2
4.5.3

4.5.4

4.6

4.6.1
4.6.2

4.6.3
4.6.4

4.6.5
4.6.6
4.6.7

4.6.8
4.6.9
4.6.10

4.6.11
4.6.12
4.6.13

4.6.14
4.6.15
4.6.16

4.6.17
4.6.18

4.6.19
4.6.20

Inter-Processor Interrupt Mask Register (IPIMR).......................l,
BIIC SPECIFIC DEVICE REGISTERS ... e ———
BCI Control Register (BCICR)......oovviiiiiiiee
e
User Interrupt Control Register (UICR) .......ooovmiiiiiiiiiiieeeeeeeee
e
BIIC USER PORT REGISTERS ...
BCIA Configuration Register (CNFGR).......coooeiiiiiiiiiiieiieeee
e,
BICA Address Register (BCAR) ....cooiiiiiiiiieee
e,
BICA Command/Byte Mask Register (BCMR).........ccoovviiiiiiiiiiiien
DMA Register File (DMAF) ..o
CIPA REGISTERS. ...t
Port Maintenance Control/Status Register (PMCSR)...........ooovvvvvvivivinnnnn...
Maintenance Address Register (MADR)........coviiiiiiiiiiieee
Maintenance Data Register (MDATR) .....ooovviiiiiiiiee,
Port Status Register (PSR ......ooiiiiiiiie
e
Port Queue Block Base Register (PQBBR) .......ccooviiiiiiiiiiiiiiieee
Port Command Queue 0 Control Register (PCQOCR).......ccooeeeieveieninnnl
Port Command Queue 1 Control Register (PCQICR).....ccoovvvvvveieiiiiinnnnn...
Port Command Queue 2 Control Register (PCQ2CR)......cccoeeviviviiieiiiiinnnnn,
Port Command Queue 3 Control Register (PCQ3CR).....coeviiiiiiiiiiiie
Port Status Release Control Register (PSRCR).........oooovvviiiiiiiiiiie
Port Enable Control Register (PECR) ..o
Port Disable Control Register (PDCR) ......oovvvimiiiiiiieeee
e
Port Initialize Control Register (PICR)........cccooovveiiiiiiiiiieieeeeeeeeeee
Port Datagram Free Queue Control Register (PDFQCR)....................
Port Message Free Queue Control Register (PMFQCR)......cccoooeeiiil.
Port Maintenance Timer Control Register (PMTCR) ...l
Port Maintenance Timer Expiration Control Register (PMTECR)..............
Port Failing Address Register (PFAR)...........cccoirmimiiee

4-27
4-29
4-29
4-29
4-32
4-32
4-33
4-33
4-34
4-34
4-35
4-35
4-36
4-36
4-37
4-37
4-38

Port Error Status Register (PESR) ....coooiiiiiiiiiiieeeeeeeeeeeeeeeeee
Port Parameter Register (PPR)........coooiiiiiiie
e

4-39
4-40

APPENDIX A

(I TERMINATION

APPENDIX B

(I BACKPLANE JUMPER

4-12
4-13
4-14
4-15
4-17
4-18
4-20
4-22
4-23
4-23
4-25

B.1

BOOT TIMER PARAMETERS ...

B.2

EXTENDED HEADER/TRAILER (W5) ..o,

B-1

B.3

ALTER DELTA TIME (W6) ..o,

B-1

B.4

DISABLE ARBITRATION (W7) ..o
EXTENDED ACKNOWLEDGEMENT TIMEOUT (W8).....ooovvviiiiiieeeeennn,

B-2

B.5

INDEX

B-1

FIGURES

S
A
S

S
N

Pt et et et \O
W N = O

]

W2 DO e

00
-

= N RO N

.
[\ O NGO~

RO RO et et it b et e e

NN NN

= \D 0O~ O\ N N

NG RS

]

UO RN NS

Figure No.

Title

Simplified CIBCI Adapter Connection ..........cocviiirinierniiiniieniieiiini
Simplified CIBCI Interface Block Diagram..........cccooiiiiiiin,
Hardware Components of the Host Processor Interface............cccoociiiiiinin
Hardware Components of the CIPA Mounting BOX ........cccoviiii,
Single CIBCI Adapter Configuration — VAX 8200/8300 .......ccccevvvnininieinnnnnnn.
Single CIBCI Adapter Configuration — VAX 8800 .....c.ccocevnieeniiniiii,
Dual CIBCI Adapter Configuration — VAX 8200/8300 ........ccooviiiiiniinniennnnnn
Unpacking the H9642 Cabinet .........ccoooviiiiiiiiiniiiis
Removing the H9642 Cabinet from the Shipping Pallet ...
Unpacking the HI652 Cabinet ..o
Removing the H9652 Cabinet from the Shipping Pallet ............ccoccooiininn,
Accessing the BA32 CPU Mounting Box Hardware Components........................
e
CPU Cabinet End Panel Removal.........oueiiiiiiiiiiiiiiiiiii
oocooii,
.....c.cccc
Removal....
CIPA Cabinet — Front and Rear Panel
CIPA Cabinet — Expansion Panel Removal .............coooi,

Page

1-1
1-10
1-11
1-12
2-3
2-4
2-5
2-6
2-7
2-9
2-10
2-12
2-13
2-14
2-15

CIPA Cabinet — RFI Shield Panel Removal .......ccccooooiiiiii 2-16
RFI Shield Panel — Knockout Plug Removal.........ccoooooii 2-17
RFI Shield Panel — Waveguide Installation.........cccccooooiiiiiiiiiini 2-18
e 2-19
H9642 Cabinet — Rear Interior VIEW .....oooveiviiiiiiiiiii
e 2-21
ieeeeee
e
iiiiiee
i
oeiiiii
.....co
CPIA Bus Cable ROULINE
2-22
nnene
reneieeeeeececne
iiiiiiiiiiiiiiie
vviiirieiieiieii
MatiNg........co
CPU and CIPA Cabinet
2-23
iiiniiees
eiiiiniiini
.....ccccoo
Mating.....
Cabinet
CPU and Expansion
2-29
s
iniiiiiiinn
vveemiiiereimiiiin
Mating.......cooev
Cabinet
CPU and Front-End
2-38
t
e
ieeee
....vvviiiieieeiiiii
ROULINE
CIPA Bus €Cable
2-39
iiiiiis
iiiiiiiin
coccoiiii
es......c
DIfferenc
Box
CIPA Mounting
Mounting Box Installation Within An H9642 Cabinet .............ccccoiiiinniiinen. 2-41
Mounting Box Installation Within An H9652 Cabinet ........c..ccccoooiiniininne. 2-45
VAXBI Backplane — Module Installation ..., 2-49
VAXBI Backplane — BCI Cable Connections........c.coooveeniereiciniiiiiiie 2-51
VAXBI Backplane — CIPA Bus Cable Connections..........oceevveeniiiniiinnininnn 2-52
CIPA Mounting BoOX — ACCESS....ceiiiruiiiiiiiiiiiiiei ittt 2-54
CIPA Mounting Box — Backplane JUmpers. ... 2-57
CIPA Mounting Box — Module ACCESS .....cceeiiiiiimiiiiiiiiiiieeni i 2-58
e 3-2
Control Panel Switches and LEDS ......ooooiiiiiiiiii
Diagnostic Loopback Cable COnneCtions ........c.oovieeiiiniiniiiiimiiiicies 3-6
Diagnostic Loopback Cable Connections ..........ccceeveennennn e ——————————a 3-16
VAXBI Physical Address SPace .......cccvoiiieiiiiiininiiciiiiii 4-2
VAXBI Physical I/O Address SPace.........cccovuieiienienieniiiiiiiiiiiiecce 4-2
VAXBI NOGE SPACE ....vvieiiiieeeiieeeite ettt 4-3
30-Bit I/O Address Bit Map .....ccoooeioiieiiiiiiiiiiiiiieieni e 4-3
CIBCI Address NOGE SPACE......oeieiieeieeieiiiiiie it 4-5
CIBCI Adapter Register Address SPace........ccveeverirenieiiiiiiiniiiiieen 4-5
VAXBI Interface Registers and Adapter Registers........ccoooeviiiiiniin., 4-6
VAXBI Required REGISTErS . ..coouvieueiiiiiiiiiiiiiiii et 4-6
Device Type Register Bit Map......cocooiiiiiiiiiniii 4-7
VAXBI Control and Status Register Bit Map.......ccooooiiiiiiiiiiis 4-7

Bus Error Register Bit Map ....cccocoiiiiiiiiiiii i 4-9
Error Interrupt Control Register Bit Map .......ccoooiiiiiin, 4-11
Interrupt Destination Register Bit Map ... 4-13
Vi

FIGURES (Cont)
Figure No.
4-14
4-15

4-16

4-17

4-18
4-19

4-20

Title

Page

Inter-Processor Interrupt Mask Register Bit Map.......ccoooviviiiiiiiiiiiiiiin,
VAXBI Specific Device RegIStErS....cccovvvuiiiiiiiiiiiiiee
e
BCI Control Register Bit Map.......ooooiiiiiiiii
e,
User Interrupt Control Register Bit Map ......cooooiiiiiiiiiiii
e,
BI User Port REZISTETS ..couniiiiieieee e,
BICA Configuration Register Bit Map ........cooooeiiiiiiiiiiiieee
e
BICA Address Register Bit Map .......ooooiiiiiiiiiiiiicccceeee
e

4-13
4-13
4-14
4-16
4-17
4-18
4-20

4-21

BICA Command/Byte Mask Register Bit Map ........oocovveeiiiiiiiiiiiiei
s

4-22

DMA Register File Bit Map ..o

4-22
4-24

4-23

CIPA Adapter REGISTEIS ...cooviveiiiiieeee e

4-24

Port Maintenance Control/Status Register Bit Map.......cccccoeeviiiiiiiiiiiiiiiiiiiiieee,
Maintenance Address Register Bit Map .......cocooiiiiiiiiiiiiiiiec
e
Maintenance Data Register Bit Map ...........oovviimmiiiiiee,
Port Status Register Bit Map..........ooiiiiiiiiiiiiee
e
Port Queue Block Base Register Bit Map ........coeeiiiiiiiiiiiiiiiieee
e,
Port Command Queue 0 Control Register Bit Map.......cccoooviiiiiiiiiiiiiniiinn,
Port Command Queue 1 Control Register Bit Map......cccccoveveeveveeiiiiiiiiiiiiiininnee,
Port Command Queue 2 Control Register Bit Map.......ccccoovveeeeeieiiiii,
Port Command Queue 3 Control Register Bit Map.........cccooovvivveeieiinn,
Port Status Release Control Register Bit Map............ovvvviiiiviieeiieiiiiiiiiiiiiie,
Port Enable Control Register Bit Map ...........coooovvviiiiiiiieieeee,
Port Disable Control Register Bit Map...........ocveeeiiiiiiiiiiiiiiiieeeceeieee
e,
Port Initialize Control Register Bit Map ........oovvviiiiiiiiiiiee
e,
Port Datagram Free Queue Control Register Bit Map .......cccoooooiiiiiiiiiceinnninnne,
Port Message Free Queue Control Register Bit Map.......ccccoooeeiiiiiiiiiiiinniinne,
Port Message Control Register Bit Map..........cccooeeiiiiiiiiiiiie
e,
Port Maintenance Timer Expiration Control Register Bit Map.........cccccoeeeviivnnnn,
Port Failing Address Register Bit Map......cccooovvvviiiiiiiiiiiiiieeeeee
e,

4-38

Port Error Status Register Bit Map....ccoooooioiiiiiiieeeeeee
e
e,

4-40

4-25

4-26
4-27

4-28
4-29
4-30
4-31

4-32

4-33
4-34
4-35
4-36

4-37

4-38
4-39
4-40

4-41
4-47
4-43

Port Parameter Register Bit Map....ccoooooiiiiiiiiiiiiii

4-25
4-28

4-29
4-30
4-31
4-32
4-32
4-33
4-33
4-34
4-34
4-35
4-35
4-36
4-36
4-37
4-37

4-39

EXAMPLES
Title

Page

Trace Printout for Repair Diagnostic EVCKA ...

3-8

Trace Printout for Repair Diagnostic EVCKB......ccoooooiiiiiieceee
Trace Printout for Repair Diagnostic EVCKC ...,
Trace Printout for Repair Diagnostic EVCKD .......coooviiiiiiiiiii
e,

3-9
3-10
3-11

Trace Printout for Repair Diagnostic EVCKE............ccooocciiiiiiiiiiic
e

3-12
3-12
3-14

Trace Printout for Functional Diagnostic EVGAB ...,

Trace Printout for Repair Diagnostic EVCKE ...,
Trace Printout for Functional Diagnostic EVGAA ...

Trace Printout for Repair Diagnostic EVCKA ...,

Ptk
— O

I ON U

WO DD

wwwwwtfawwwww

Example No.

Trace Printout for Repair Diagnostic EVCKB.......ccoooooviiiiiiiiiiiiiiinnne, rvvreeseerens

3-19

Trace Printout for Repair Diagnostic EVCKC ...

3-20

Vil

3-15
3-18

EXAMPLES (Cont)
Page

Trace Printout for Repair Diagnostic EVCKD ...
Trace Printout for Repair Diagnostic EVCKE........cooooiiis
Trace Printout for Repair Diagnostic EVCKE ...
Trace Printout for Functional Diagnostic EVGAA ...,
Trace Printout for Functional Diagnostic EVGAB ...,

TABLES

prd

iN ] N ]

]

ek pend ek et e

]

GO ~J

I-P%%%Jfi;-{;
W N

(.:J().)L}.)[\)P-—*k——‘)-d
W DN = =t D DI

Title

CIBCI HardWare VATIAtIONS «.ceevvueeeiieeeeeeeeiiiiieeaeeeeeettiaimnnaeassesssetsiaenessessnaaiinaeees

e
Related CIBCI Adapter Documentation.........ooiuiireiieeeniiieiiiiiiiininee
.
.
.
Adapter
Hardware Components of the CIBCIL
e
Node Address SWitCh SEtHINES ...coovvvvrreeeeiiiiiiiii
iiiiiiemniiiiin
..cccoov
........
Programs
List of the CIBCI Diagnostic
.
.
.
Hierarchy
Testing
Summary of the Diagnostic

Summary of the Functions of VAXcluster System Maintenance and

Management TOOIS......coueuiiiiiiiiii e
Node Space Address ASSIZNMENTS ......ooiiiiriraieniiniii et

VAXBI Control and Status Register Bits .......oooviiimmiiiiiinees

Bus Error ReGIStEr BILS .....ooiiiiiiiiiiiiiiiiiieeiis ettt

Error Interrupt Control Register BIts ..o
BCI Control Register Bits .......ccociiiiiiiiiiiiiiiiiiiie

User Interrupt Control Register Bits.........ooiiiiiiiin
BCIA Configuration Register Bits .......cccoooiiiiiiiiieii
BCIA Address Register Bits......oooiiriioiiiiiiiiiiii i

BCIA Command/Byte Mask Register BIts .......ooooimiiiiiini
Port Control and Status Register Bits......cccooiiiiiiiiis
s
Maintenance Address Register Bits.......cccociiiii

et e et aeeeraa e e e een et e ara e
Port Status Register Bits........... e
Port Failing Address Register BitS........ccooiiiiiiniin
Port Error Status Register Bits ......cooooiiiiiiiiiii
i
Port Parameter RegiSter BitS ......cooviiiiiiiiiiiiiiiii

viii

3-21

3-22
3-22
3-25

3-26

PREFACE

INTENDED READER

This document provides an introduction to Digital Equipment Corporation’s computer interconnect hardware adapter option (CIBCI). It presents information required by the user for the configuration, installation, and acceptance verification of the CIBCI hardware on a VAX 8000-Series system incorporating the
VAX backplane interconnect (VAXBI)* bus architecture.
NOTE

Throughout this manual the term “VAX 8000Series” shall be used to represent the following
processors that support the CIBCI hardware: VAX
8200, VAX 8300, VAX 8500, VAX 8550, VAX
8700, and VAX 8800.
GUIDE STRUCTURE

Chapter 1 — Describes the CIBCI hardware and lists its specifications.

Chapter 2 — Describes the procedures for installing the hardware on a VAX 8000-Series system.

Chapter 3 - Describes the procedures for verifying the functionality of the hardware.
Chapter 4 — Provides a reference section describing the programmer visible registers.
Appendix A — Provides information on CI termination.
Appendix B - Provides information on the CI backplane jumpers.

VAXBI is a trademark of Digital Equipment Corporation.

CHAPTER 1

INTRODUCTION

1.1

SCOPE

This chapter introduces the reader to the computer interconnect hardware adapter option (CIBCI) used on
the VAX 8000-Series systems that incorporate a VAX backplane interconnect (VAXBI) bus architecture.
The chapter also contains a physical description and the specifications of the hardware. Additional
documents are listed for the user who wishes more information concerning VAXclusters.
1.2
1.2.1

GENERAL DESCRIPTION
Components

VAXBI BUS

The computer interconnect adapter is shown in Figure 1-1 and is designated the CIBCI adapter. It is
centrally controlled by a single, on-board data processor to provide buffered parallel-to-serial communications between two corporate interconnect bus architecture protocols: the VAX backplane interconnect
(VAXBI) bus of the VAX 8000-Series host processor and the dual-path computer interconnect (CI) bus.

CIBCI PORT

ADAPTER

Cl BUS

STAR
COUPLER

MKV85-2546

Figure 1-1

Simplified CIBCI Adapter Connection

As a buffered communications port, the CIBCI adapter completes high-level computer communications,
thereby reducing software processing overhead. This is accomplished with hardware that provides all of
the necessary data buffering, address translation, and serial data encoding/decoding. The CIBCI uses
queue structures provided by the VAX/VMS operating system to transfer packet messages and to initiate
the transfer of blocks of data between the VAX 8000-Series host memory system and/or other nodes
within the VA Xcluster.

1-1

The CIBCI adapter is partitioned into two separate hardware interfaces: one host processor interface and
one computer interconnect port adapter interface. These interfaces consist of the following major
components:

Two Eurocard T-series modules

Adapter control module (BAC) T1017
Adapter data module (BAD) T1018
Three extended hex L-series modules
Link interface module (ILI) LO100

Packet buffer module (IPB) L0101
Data path module (CDP) L0400
1.2.2

Features

VAX backplane interconnect design

2M bytes/s performance at 40K packet transmission rate

3M bytes/s performance at 90K packet transmission rate
Diagnostic data loopback (internal/external) capability
Data integrity via cyclic redundancy checking

Round-robin arbitration at heavy loading
Contention arbitration at light loading
Packet-oriented data transmission
Operational modes:
Disabled
Enabled

Uninitialized

Disabled /maintenance
Enabled /maintenance

Uninitialized /maintenance

1-2

1.2.3

Conflguratlons

The CIBCI adapter is available in either a single or a dual configuratlon The single configuration i1s
available without a star coupler, whereas the dual configurationis available with or without a star coupler.

Table 1-1 lists the model variations available with the CIBCI. The model variations are specified according
to the host system type, electrical requirements, configuration type, and the major hardware components.
NOTE

The CI bus cables and SC008 star coupler are separately ordered options. They are NOT included as
part of the bill of materials for all CIBCI adapter
models.

Configuraton

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1.3

GENERAL SPECIFICATIONS

Priority arbitration

Light loading
Heavy loading

Round-robin
Contention

Parity

Cyclic redundancy check

Data format

Manchester-encoded serial packet

Data transfer rate

5M bytes/s maximum

Data throughput

2M to 3M bytes/s (typical sustained)

Operational modes

Disabled
Disabled/maintenance
Enabled
Enabled /maintenance

Uninitialized
Uninitialized /maintenance
1.3.1

Environmental Specifications

Temperature

Operating

10°C to 40°C (50°F to 104°F) ambient temperature with a gradient of
10°C (18°F)/hr

Storage/shipping

—40°C to 70°C (—40°F to 158°F) ambient temperature with a gradient of
2°C (36°F)/hr

Relative humidity
Operating

10% to 90% with a maximum wet bulb temperature of 28°C (82°F) and a
minimum dew point of 2°C (36°F) with no condensation

Storage/shipping

5% to 95% with no condensation

Altitude

Operating

Sea level to 2.4 km (8,000 ft)

Maximum operating temperatures decrease by a factor of 1.8°C/1000 ft
(1° F/1000 ft) for operation above sea level
Storage/shipping

Up to 9.1 km (30,000 ft) above sea level (actual or effective by means of
cabin pressurization)

1-4

Shock

5 g peak at 7 to 13 ms duration in three axes mutually perpendicular

(maximum)

Heat dissipation

Cooling
Noise level
1.3.2

External forced air cooling at 2 m/s (400 linear ft/min)
53 dBat 1 m

Mechanical Specifications

CI Box Assembly

Height
Width
Depth
Weight

44.5 cm (17.5 in)
66.7 cm (26.25 in)
86.4 cm (34.0 in)
37.5 kg (82.5 Ib)

CI Cabinet

Height
Width
Depth
Weight
1.3.3

106.1 cm (40.6 in)
53.9 cm (21.2 in)
76.2 cm (30 in)
98.8 kg (200 Ib)

Electrical Specifications

Power consumption

Host processor interface:

T1017 module
T1018 module

+5.0 Vdc at 3.74 A, 19.6 W
+5.0 Vdc at 3.75 A, 19.7T W

CI interface:

Mounting box

90 — 128 Vac, 47-63 Hz at 7.5 A
180 — 240 Vac, 47-63 Hz at 4.2 A

Plug type

120 Vac
220-240 Vac

H7202-B power
supply rating

NEMA 5-15P
NEMA 6-15P

+5.0 Vdc at 60.0 A
—5.3 Vdc at 10.0 A
+12.3 Vdc at 2.0 A

1-5

Interface modules

L0100 module

+5.0 Vdc at 10.0 A, 500 W

L0101 module

+5.0 Vdc at 10.5 A, 52.5 W

1.0400 module

+5.0 Vdc at 12.5 A, 62.5 W

1.3.3.1

—~5.3 Vdcat 5.3 A, 27.6 W

VAXBI Bus Specifications —

Bus characteristics

Type

Synchronous

Width

32 data bits

Cycle time

200 ns

Priority arbitration

Distributed embedded arbitration

Parity

Odd

Data transfers

Block mode (masked)
Longword
Quadword
Octaword

Transmission characteristics
Bandwidth

Master port
Slave port

11.4M bytes/s
13.3M bytes/s

Length (maximum)

1.5 m (5 ft)

Bus loading (maximum)

16 logical nodes

1.3.3.2

CIPA Bus Specifications -

Bus characteristics

Type

Synchronous

Width

16 data bits

Cycle time

400 ns

Data parity

Odd

Data transfers

Packet

1-6

Transmission characteristics

Bandwidth

2M to 3M bytes/s

Length (Maximum)

4.5 m (15 ft)

Bus loading (maximum)

Impedance

120 Ohms

1.3.3.3

CI Bus Specifications -

Bus characteristics

Type

Synchronous

Width

Serial

External length (maximum)

45 m (147.64 ft) radius

(from the star coupler)

Data transfer rate

70M bits/s (maximum)

Bus loading (maximum)

16 logical nodes

Cable type

Shielded coaxial

(BNCIA-XX)

Cable impedance

50 Ohms

1-7

1.4

REFERENCE DOCUMENTS (Table 1-2)

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1-8

1.5

PHYSICAL HARDWARE DESCRIPTION

Refer to Table 1-3 and Figure 1-2 for an overview of the hardware components for the host processor and
computer interconnect port adapter interfaces.
S

1.5.1

Host Processor Interface Hardware

Refer to Figure 1-3. The host processor interface consists of two T-series type modules. The T-series
modules are housed in two adjacent slots within an H9400-A VAXBI cardcage of the VAX 8000-Series
host system. These modules are used to interface the host system’s VAXBI bus to the CIPA bus.
The Adapter Control Module

The adapter control module (BAC), part number T1017, contains the VAXBI protocol and the
control logic in addition to the CIPA control logic.

VAXBI

The Adapter Data Module

The adapter data module (BAD), part number T1018, is the major interface to the CI port adapter
(CIPA) bus and consists of transaction buffers between the VAXBI and CIPA buses.
BCI Cables
The four BCI cables, part numbers 17-01029-01 and 17-01029-02, are used to electrically interconnect the
T1017 and T1018 modules. Each cable consists of two 30-pin female connectors and two pull tabs or
loops. The cables are mated to cable connectors located on the VAXBI cardcage corresponding to zones C
and D of the modules. Two short cables (17-01029-02) complete the innermost electrical connection while
two longer cables (17-01029-01) complete the outermost electrical connection between zones C and D of
the two modules.

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Figure 1-3

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1-11

1.5.2

Computer Interconnect Interface Hardware

1.5.2.1 CI Port Adapter Assembly — Refer to Figure 1-4. The CI (computer interconnect) port adapter
interface hardware is housed in a dedicated but universal mounting box is designated the CI box assembly.
This CI box assembly is also referred to as the CIPA mounting box. It may reside either within the H9642
free-standing cabinet of a VAX 8200/8300 system or within the H9652 expander cabinet of a VAX
8500/8550/8700/8800 system.

LO100 MODULE (SLOT 3)

LO101 MODULE (SLOT 4)
LO400 MODULE (SLOT 5)

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P/N 17-01027-01

—— POWER

SUPPLY
MKV85-1687

Figure 1-4

Hardware Components of the CIPA Mounting Box

The Power Supply

The CI box assembly uses a model H7202-D switching power supply to power the three L-series modules:
the data path, packet buffer, and the CI link interface. The power supply receives its ac power from a
power controller located within the H9642 free-standing cabinet or the H9652 expander cabinet.
The CIPA Cardcage

The CIPA cardcage, housed within the CI box assembly, is a five slot backplane used to house the three
I -series modules: the data path, the packet buffer, and the CI link interface modules.
The Data Path Module

The data path module, part number L0400, provides the necessary arithmetic and logical processing of
general port functions, as well as local storage for the port. It also provides transceivers and buffer registers
as the interface for the CIPA bus.
The Packet Buffer Module

The packet buffer module (IPB), part number L0101, contains the port control store microcode and two
transmit and receive CI packet buffers. Each CI packet buffer has a storage capacity of 1K bytes.

The CI Link Interface Module

The CI link interface module (ILI), part number L0100, is the actual interface to the CI bus and is capable
of servicing dual CI paths. The module provides the necessary serialization and deserialization of data,
data validity, CI bus protocol handling, and distributed priority arbitration. In addition, the module only
permits transmission and reception of data packets over one CI data path at any given time. However,
when four or more CI ports exist in the cluster, both CI data paths may be in use simultaneously. For
example, node 0 to node 1 uses CI data path A while node 2 to node 3 uses CI data path B.
All data packets are appended with header and trailer information. The header information identifies the
source and destination of the packet. Node address switches provide the node with an address on the CI
cluster. The packet header contains this address as a source ID. The trailer information serves to keep the

node receiver locked up while the last data bytes in the packet are being processed.
The CI Port Adapter Bus

The CI port adapter (CIPA) bus cable assembly, part number 17-01027-01, is a control and data bus used
for backplane-to-backplane communication between the VAXBI and CIPA cardcages. The cable assembly

consists of two 64.5 m (15 ft) flat ribbon cables separated by a foam material and contains a total of six
female electrical connectors, two 40-pin connectors for connection to the CIPA backplane and four 30-pin
connectors for connection to the VAXBI backplane.
1.5.2.2 CIPA Cabinet — When the CI mounting box assembly is mounted in a free-standing cabinet, the
cabinet is identified as the CIPA cabinet. The CIPA cabinet is mounted immediately adjacent to the VAX

8200/8300 host system’s VAXBI cabinet where the T-series type modules are housed. Contained within
the CIPA cabinet are the power controller, CIPA mounting box assembly, and two CI bulkhead connector
panels.
The Power Controller

The CIPA cabinet uses a model 877 (/D for 60 Hz or /B for 50 Hz), single-phase, ac power controller to
provide electrical isolation and ac power for the CIPA mounting box assembly.
The CI Bulkhead Connector Panel

The CIPA backplane assembly is connected internally from the backplane to two CI bulkhead connector
panels via two pairs of coaxial cables. The CI bulkhead connector panels provide the electrical isolation for

the system by creating an EMI/RFI shield without compromising signal integrity. The panels are mounted
in the cable connector openings located on the rear inside I/O panels of the cabinet. Two pairs of doubleshielded coaxial cables connect the CI paths of the node from the CI bulkhead connector panels to the star
coupler. One cable of each pair is for transmitting data; the other is for receiving data. Each cable pair
connects to one CI bulkhead connector panel assembly.

CHAPTER 2

SITE PREPARATION AND INSTALLATION

2.1

INTRODUCTION

Chapter 2 contains information on site preparation and mstallatlon including:

Operating Environment — Verifying that the CIBCI adapter hardware meets all of the minimum physical,
environmental, and grounding specifications

System Configuration — Illustrating the various CIBCI adapter hardware configurations supported on a
VAX 8000-Series system

Unpacking and Inventorying — Unpacking and verifying that the shipment is complete and undamaged
Mechanical Installation (System Level) — Installing an H9642 or H9652 cabinet onto a VAX 8000-Series
system

Mechanical Installation (Add-on Level) — Installing a 10.5 inch CIPA mounting box into an existing
cabinet

Electrical Installation — Installing the CIPA bus cable and configuring the node address of the CIBCI

adapter hardware

2.2

OPERATING ENVIRONMENT
Physical Elements

2.2.1

The CIBCI adapter hardware requires adequate floor space and/or mounting space for the following:

2.2.2

H9642 CIPA cabinet (VAX 8200/8300 system)

H9652 expander cabinet (VAX 8500/8550/8700/8800 system)

CI mounting box within either the H9642 or H9652 cabinet
Environmental Elements

A VAX 8000-Series system and its associated computer interconnect port adapter hardware are designed
to operate in a “Class B” environment.

2.2.3

Grounding Elements

Careful grounding is essential in order to avoid ground loops and poor noise rejection. To eliminate ground
loops and to have proper noise rejection, ensure the following:

VAX 8000-Series system, expander cabinets, and all equipment share a common ac power
source.

Earth ground for the VAX 8000-Series system and expander cabinets are common.

No electrically noisy equipment shares the same ac power source.

Systems connected by the CI bus should not be connected for grounding unless another reason
requires it.
CAUTION

The chassis for a VAX 8500/8550/8700/8800 system is isolated and floating, whereas the VAX
8200/8300 system chassis is grounded. Both affect
the grounding constraints listed above.

2.3

CIBCI SYSTEM CONFIGURATIONS

Refer to Figures 2-1 through 2-3 for the VAX 8000-Series system configurations.
NOTE
Ensure that the CIBCI hardware and microcode
revision level is consistent with the revision level of
the cluster, and vice versa.

2.4

UNPACKING AND INVENTORYING

The CIBCI hardware is shipped in corrugated cartons and mounted on a pallet. Customers are responsible
for the actual moving of the equipment to the installation site.
2.4.1

VAX 8200/8300 Systems

2.4.1.1

Verifying Shipment Inventory —

Procedure:

Inventory all equipment against the shipping list accompanying the equipment.

Notify the customer of any opened cartons or boxes and document this fact on the installation
report.

Notify the field service unit manager of any missing or incorrect items.

Request that the customer contact the shipping carrier to locate any missing items.

Request that the field service unit manager check with the Digital Equipment Corporation
Traffic and Shipping Department if the shipping carrier does not have the missing items.

Check all boxes for external damage (dents, holes, or crushed corners).

Notify the customer of all damages and list all damages on the installation report.

2-2

~ CPU CABINET

CIPA CABINET

MKV85-1526

Figure 2-1

2.4.1.2

Single CIBCI Adapter Configuration - VAX 8200/8300

Unpacking the Shipping Boxes —

Procedure:

Locate the box marked “OPEN ME FIRST”.

Open all boxes and inventory the contents against the shipping/accessory list in the “OPEN
ME FIRST” box.

Inspect the equipment for damage. Report any damage and note it on the the installation report.

If damage is extensive, notify Digital Equipment Corporation for instructions on how to
proceed.

“FRONT-END
CABINET

MKV85-1609

Figure 2-2

Single CIBCI Adapter Configuration — VAX 8300

" CPU CABINET

CIPA CABINET

Y CPU CABINET
MKV85-1688

Figure 2-3

2.4.1.3

Dual CIBCI Adapter Configuration - VAX 8200/8300

Unpacking the H9642 CIPA Cabinet Carton —

Procedure:

Refer to Figure 2-4 and cut the two polyester straps.

Remove the cap, two ramps, and the cardboard spacer from the packaging container.

Lift and remove the cardboard tube and plastic bag covering the cabinet.

Refer to Figure 2-5 and with a 9/16 inch open-end wrench, remove the four shipping brackets
located at the bottom of each corner of the cabinet.

Loosen the locking nuts on the four leveler feet located on the bottom corners of the cabinet and
raise the leveler feet until the cabinet is resting on its casters.

2-5

LIFT
AND
REM
OVE
N

CAP

RAMPS

CARDBOARD
SPACER

B
[
CARDBOARD
TUBE

Cl1750

CABINET

_ PLASTIC
BAG

SHIPPING

SKID

POLYESTER

STRAPS

MKV85-1542

Figure 2-4

Unpacking the H9642 Cabinet

2-6

Allow a 3 m (10 ft) clearance from the back of the shipping pallet to remove the cabinet.

Attach the two ramps to the back of the shipping pallet by sliding the large end of the ramp into
the groove of the pallet.

Ensure that the ramps are straight and secure. Then, gently roll the cabinet down the ramps.

2.4.2

VAX 8500/8550/8700/8800 Systems

2.4.2.1

Verifying Shipment Inventory —

Procedure:
1.

Inventory all equipment against the shipping list accompanying the equipment.

Notify the customer of any opened cartons or boxes and document this fact on the installation
report.

Notify the field service unit manager of any missing or incorrect items.

SHIPPING

__—R\\
BRACKETS \

SHIPPING SKID —

SHIPPING
> BRACKETS

RAIL

RAMPS

MKV85-1540

Figure 2-5

Removing the H9642 Cabinet from the Shipping Pallet

2-7

Request that the customer contact the shipping carrier to locate any missing items.

Request that the field service unit manager check with the Digital Equipment Corporation
Traffic and Shipping Department if the shipping carrier does not have the missing items.
6.

Check all boxes for external damage (dents, holes, or crushed corners).

Notify the customer of all damages and list all damages on the installation report.

2.4.2.2

Unpacking the Shipping Boxes -

Procedure:
1.

Locate the box marked “OPEN ME FIRST”.

Open all boxes and inventory the contents against the shipping/accessory list in the “OPEN
ME FIRST” box.

Inspect the equipment for damage. Report any damage and note it on the the installation report.
If damage is extensive, notify Digital Equipment Corporation for instructions on how to
proceed.

2.4.2.3

Unpacking the H9652 Expander Cabinet -

Procedure:
1.

Refer to Figure 2-6 and cut the two polyester straps.

Remove the cap, two ramps, and the cardboard spacer from the packaging container.
Lift and remove the cardboard tube and plastic bag covering the cabinet.

Refer to Figure 2-7 and with a 9/16 inch open-end wrench, remove the four shipping brackets
located at the bottom of each corner of the cabinet.

Loosen the locking nuts on the four leveler feet located on the bottom corners of the cabinet and
raise the leveler feet until the cabinet is resting on 1ts casters.

Allow a 3 m (10 ft) clearance from the back of the shipping pallet to remove the cabinet.

Attach the two ramps to the back of the shipping pallet by sliding the large end of the ramp into

the groove of the pallet.

Ensure that the ramps are straight and secure. Then, gently roll the cabinet down the ramps.

G LIFT AND
REMOVE
——

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RAMPS

CARDBOARD

CARDBOARD
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Cl1750
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BAG

SHIPPING

SKID

POLYESTER

STRAPS

MK V85-1542

Figure 2-6

Unpacking the H9652 Cabinet

2-9

SHIPPING

BRACKETS

SHIPPING SKID

.
» BRACKETS

_RAIL

MKV85-1540

Figure 2-7

2.5

Removing the H9652 Cabinet from the Shipping Pallet

MECHANICAL INSTALLATION (System Level)

2.5.1

VAX 8200/8300 System

The system is shipped from the manufacturer with the T1017 and T1018 modules, the VAXBI node plug,
and the four BCI cables already installed in the VAXBI cardcage.

The remaining CIBCI hardware residesin the H9642 CIPA cabinet. The CIPA cabinet may be configured
either to the left or right of the processor cabinet. The procedures forjoining the two cabinets are detailed
in Sections 2.5.1.1 and 2.5.1.2.

For a CIBCI-FA/FB/HA /HB installation, repeat Steps 1 through 6 for the other VAX 8200 or VAX
8300 system.

2.5.1.1

CPU Cabinet Preparation —

Procedure:

Refer to Figure 2-8 and then face the front of the cabinet. Carefully slide the BA32 mounting
box fully outward from the cabinet.

CAUTION

Extend the stabilizer bar before sliding the BA32

mounting box from the cabinet. Failure to do so may
cause personal injury if the cabinet tips forward
when BA32 mounting box is fully extended.
Exercise care when extending the mounting box.
Pass through the primary safety lock mechanism
until the secondary safety lock mechanism is
reached.

Remove the module access cover of the VAXBI cardcage by loosening the holding screws and
lifting the cover.

Place the BA32 mounting box in a 90 degree position (see Figure 2-8) by grasping and pulling
the slide-rail release mechanism, and then by rotating the mounting box up and towards the rear
of the cabinet until it is securely locked into place.
Remove the bottom access cover (see Figure 2-8) by removing several holding screws and then
by lifting the cover. Replace the screws in their holes for safekeeping.

—w

ACCESS

REMOVAL

SAFETY LOCK

MODULE

MECHANISM

ACCESS COVER

MKV85-1689

Figure 2-8

Accessing the BA32 CPU Mounting Box Hardware Components (Sheet 1 of 2)

BOTTOM

ACCESS

RELEASE

MECHANISM
90° POSITION

REMOVAL

BOTTOM

ACCESS COVER
MKV85-1539

Figure 2-8
5.

Accessing the BA32 CPU Mounting Box Hardware Components (Sheet 2 of 2)

Face the front of the cabinet and remove the end panel (the side where the H9642 CIPA
cabinet will be joined) by grasping the panel at the front and rear, lifting it approximately 2.5
cm (1 in), and pulling it away from the cabinet (see Figure 2-9).
NOTE

If the cabinet is NOT resting on its wheels, loosen
the locking nuts on the four leveler feet located at
the bottom corners of the cabinet and raise the leveler feet until the cabinet is resting on its wheels.

2-12

Remove one of the two knockouts from the RFI shield panel by using a knife and cutting away
the copper foil to expose the knockout opening.

MKV85-1603

Figure 2-9

CPU Cabinet End Panel Removal

2-13

2.5.1.2 H9642 CIPA Cabinet Preparation — The CIPA (computer interconnect port adapter) hardware
is housed in a shielded cabinet that, like the processor cabinet, has been specially designed to attenuate
electromagnetic interference (EMI) and radio frequency interference (RFI) signals by absorbing radiated
energy. Therefore, attention to the details of the mechanical installation procedure is vital when installing
the CIPA hardware onto a VAX 8200 or VAX 8300 system.

For a CIBCI-FA /FB/HA/HB installation, repeat Steps 1 through 14 for the opposite side of the H9642

CIPA cabinet.
Procedure:

Using a 5/32 inch Allen wrench, remove the front and rear doors (see Figure 2-10).

Remove the expansion panel attached to the side of the cabinet that will be joined to the system
cabinet by grasping it at the front and back and then lifting it up and away from the chassis (see
Figure 2-11).

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'; " FRONT DOOR

MKV85-1535

Figure 2-10

CIPA Cabinet — Front and Rear Panel Removal

2-14

EXPANSION
PANEL

MKV85-1536

Figure 2-11

CIPA Cabinet — Expansion Panel Removal

2-15

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MKV85-1611

Figure 2-12

CIPA Cabinet - RFI Shield Panel Removal

Remove the RFI shield panel from the side of the cabinet where the H9642 CIPA cabinet will

be joined (Figure 2-12), as follows:

NOTE

Bypass this procedural step if the knockout plug on
the RFI shield panel is made of copper foil. The
copper foil is removed using a knife.
CAUTION

Exercise care when handling the RFI shield panel to
avoid damage to the RFI gasket springs located on
its front and rear edges.

Remove and save the two round-head screws with lock washers.

Remove and save the four key-button screws.

Grasp the top of the RFI shield panel and pull it away from the chassis approximately .3 m

Lift the RFI shield panel up and away from the unit until the projecting legs located at the

(1 ft).

bottom of the panel are clear of the chassis.

Remove one of the two knockouts from the RFI shield panel (Figure 2-13), as follows:
NOTE

Bypass this procedural step if the knockout plug is
made of copper foil. The copper foil is removed
using a knife.

Place two wooden blocks (removed from the shipping pallet) on the floor and lay the RFI
shield panel down with the knockouts positioned over the wooden blocks.

Using a hammer and a flat-blade screwdriver, break the upper edge of each knockout free

Lift the RFI shield panel off the wooden blocks and push inward on the upper edge of each

of the RFI shield panel.

knockout until the lower edges break free.

RFI

SHIELD

KNOCKOUT
PANELS

WOODEN BLOCKS
MKV85-1538

Figure 2-13

RFI Shield Panel — Knockout Plug Removal

2-17

| I

NRFI

SHIELD

WAVEGUIDES

MK V85-1537

Figure 2-14

RFI Shield Panel — Waveguide Installation

Install one of the two waveguides onto the RFI shield panel (see Figure 2-14).

a.
b.

Place one of the waveguides from the waveguide/joiner bar kit (P/N H9544-JE) over a
knockout hole on the outside of the RFI shield panel.

Align the screw holes in the waveguide with the screw holes in the RFI shield panel. The

waveguide lip should be positioned into the knockout hole.

Insertsix 8-32 x 1/4 inch screws into the waveguide screw holes from the inside of the RFI
shield panel and then tighten the screws.

Place the RFI shield panel in an upright position and carefully lean it against the side of the
cabinet where the H9642 CIPA cabinet will be joined. Install the RFI shield panel back onto
the side of the H9642 CIPA cabinet by reversing the procedure detailed in Step 3.
CAUTION

Avoid damage to the RFI gasket springs on the
shield panel. Use care when inserting the projecting
legs of the shield panel over the lower part of the
chassis frame at the front and back.

2-18

TInstall the expansion panel on the side of the cabinet where the CPU cabinet will be joined by
reversing the procedure detailed in Step 2.

CAUTION

Be sure to use the expansion panel shipped with the
CIBCI option. This has a single (upper) locking bar.
Do NOT use an expansion panel that has both upper
and lower locking bars.

NOTE

The longer set of key slots on the expansion panel
should be attached to the H9642 CIPA cabinet.

8.
9.

Move the cabinet adjacent to the CPU cabinet. Leave approximately 1 m (3 ft) between the

cabinets to allow access to the facing sides.

From the rear-inside of the H9642 CIPA cabinet, locate the free end of the flat ribbon CIPA
bus cable (see Figure 2-15).

CABLE
MANAGEMENT
ARM

CABLE PORTS

S CABLE

CIPA BU

—

(P/N17-01027-01)

MKV85-1534

Figure 2-15

H9642 Cabinet — Rear Interior View

2-19

10.

Refer to Figure 2-16 and perform the following:
d.

Carefully move the H9642 CIPA cabinet alongside the CPU cabinet. Take care that the
CIPA bus cable does not bunch up between the cabinets.

Route the CIPA bus cable through the RFI shield panel knockout hole and waveguide,
and then through the RFI shield panel knockout hole of the CPU cabinet.

Route the CIPA bus cable up through the interior of the CPU cabinet to the bottom of the
BA32 mounting box and then outward from the cabinet. If necessary, move the H9642
CIPA cabinet closer to the CPU cabinet to allow the CIPA bus cable to reach.
Remove the cable strain relief clamp on the BA32 mounting box.

Route the CIPA bus cable through the I/O cable slot located in the lower rear of the
BA32 mounting box.

11.

Refer to Figure 2-17 and, working from the exterior of the H9642 CIPA cabinet:
a.

Raise the expansion panel on the side of the H9642 CIPA cabinet approximately 2.5 cm
(1 in).

While holding the cabinets together, push the expansion panel down slightly until key slots
just begin to engage the upper buttons on both cabinets at the front and rear.
Push down firmly on the expansion panel to securely lock the cabinets together.
Bolt the cabinets together at the front using one of the joiner bars provided.
Bolt the cabinets together at the rear using the second joiner bar.

Install the end panel previously removed from the CPU cabinet onto the open side of the

H9642 CIPA cabinet by reversing the procedure used in Step 5.
12.

Route and connect the 70-08288-06 power control bus cable between the CPU and H9642
CIPA cabinet power controller assemblies.

13.

Place the power controller’s local/remote switch in its remote position.

14.

Route, but at this time do NOT connect the BNCIA-xx coaxial (CI bus) cables. Refer to the

Star Coupler User’s Guide.

2-20

2-21

2Ind1g91-7 vdIDsng9[qedsunoy
L-G8AJN GO9S

EXPANSION
\_
PANEL

penes

FRONT AND REAR
JOINER BAR

MKV85-15633

Figure 2-17

CPU and CIPA Cabinet Mating

2-22

REMOVAL/INSTALLATION

FRONT AND REAR DOORS

arouno

DOOR LATCH DETAIL
CPU CABINET

(2 PLACES)

(REAR V,EW)
Figure 2-18

MKV86-1369

CPU and Expansion Cabinet Mating (Sheet 1 of 5)

2.5.2 VAX 8500/8550 Systems
The system is shipped from the manufacturer with the T1017 and T1018 modules, the VAXBI node plug,
and the four the BCI cables already installed in the VAXBI cardcage.
The remaining CIBCI hardware resides in an expansion cabinet. The expansion cabinet always mounts to
the right of the processor cabinet. The procedures for joining the two cabinets are detailed below.
Procedure: (Refer to Figure 2-18)

Remove the CPU cabinet front door by removing a single hex screw that secures the door’s
ground strap to the cabinet frame, pulling the release mechanism on the two door hinges, and
then lifting the door off its hinges.

Remove the CPU cabinet rear door by removing a single hex screw that secures the door’s
ground strap to the cabinet frame, pulling the release mechanism on the two door hinges, and
then lifting the door off its hinges.

2-23

Working from the rear of the CPU cabinet, remove the top cabinet cover by removing the two
screws located on the underside of the top cover.

REMOVAL
TOP COVER

0000

COVER DETAIL

OOOOOOOOOOOOOOOOOOOOOOOOOOO

CPU CABINET
(REAR VIEW)
MKV86-1373

Figure 2-18

CPU and Expansion Cabinet Mating (Sheet 2 of 5)

2-24

REMOVAL
END PANEL

6J
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o]

am
g

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END PA

NEL

amm

8L’

1&3

“2‘

:
|

12 TOTAL

‘

CPU CABINET
(REAR VIEW)
MKV86-1377

Figure 2-18

CPU and Expansion Cabinet Mating (Sheet 3 of 5)

Remove the rear-left end panel from the CPU cabinet by removing the twelve kepnuts (six on
each side).
Open the front and rear doors of the H9652 expansion cabinet.
Install the CPU end panel on the far side of the H9652 expansion cabinet by securing twelve
kepnuts (six on each side).

2-25

Join the two cabinets by aligning the twelve studs and holes on the cabinet frames, and then by
replacing the twelve kepnuts (six on each side).

Working from the rear of the CPU cabinet, replace the top cabinet cover by inserting two
screws on the underside of the top cover.

Replace the CPU cabinet front door by pulling the release mechanism on the two door hinges
and by lifting the door onto its hinges. Then, insert the single hex screw that secures the door’s
ground strap to the cabinet frame.

JOINING CABINETS

EXPANDER
FRAME

EXPANDER CAB
a4

CPU CABINET

1Le]
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12 TOTAL

REAR VIEW
MKV86-1381

Figure 2-18

CPU and Expansion Cabinet Mating (Sheet 4 of 5)

2-26

REPLACE

[+X=)

00000000000000000000000000

TOP COVER

COVER
DETAIL

————-—--"'-'_h_m

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ROUTE CIPA
BUS CABLE

REAR VIEW
MKV86-1385

Figure 2-18

10.

CPU and Expansion Cabinet Mating (Sheet 5 of 5)

Replace the CPU cabinet rear door by pulling the release mechanism on the two door hinges
and by lifting the door onto its hinges. Then, insert the single hex screw that secures the door’s
ground strap to the cabinet frame.

11.

Route the CIPA bus cables from the H9652 expansion cabinet to the VAXBI cardcage located
in the left-rear of the CPU cabinet.

12.

Refer to the VAX 8500/8550 Installation Guide, part number EK-8500I-IN, for additional
intracabinet cabling.

2-27

VAX 8700/8800 Systems

2.5.3

The system is shipped from the manufacturer with the T1017 and T1018 modules, the VAXBI node plug,
and the four the BCI cables already installed in the VAXBI cardcage.

frontThe remaining CIBCI hardware resides in either a front-end cabinet or an expansion cabinet. The to
the
mounts
always
cabinet
expansion
The
cabinet.
processor
the
of
left
the
to
end cabinet always mounts
right of the processor cabinet. The procedure for joining the cabinets is detailed below.
Procedure: (Refer to Figure 2-19)
1.

Remove the appropriate CPU cabinet front door by removing a single hex screw that secures
the door’s ground strap to the cabinet frame, pulling the release mechanism on the two door
hinges, and then lifting the door off its hinges.

Remove the appropriate CPU cabinet rear door by removing a single hex screw that secures the
door’s ground strap to the cabinet frame, pulling the release mechanism on the two door hinges,
and then lifting the door off its hinges.

Working from the rear of the CPU cabinet, remove the top cabinet cover by removing the two
screws located on the underside of the top cover.

Remove the appropriate end panel from the CPU cabinet by removing the twelve kepnuts (six
on each side).

Open the front and rear doors of the H9652 cabinet.

Install the CPU end panel on the far side of the H9652 cabinet by securing twelve kepnuts (six
on each side).

Join the two cabinets by aligning the twelve studs and holes on the cabinet frames, and then by
replacing the twelve kepnuts (six on each side).

Working from the rear of the cabinet, replace the top cabinet cover by inserting two screws on
the underside of the top cover.

Replace the appropriate CPU cabinet front door by pulling the release mechanism on the two
door hinges and by lifting the door onto its hinges. Then, insert the single hex screw that secures
the door’s ground strap to the cabinet frame.

10.

Replace the appropriate CPU cabinet rear door by pulling the release mechanism on the two
door hinges and by lifting the door onto its hinges. Then, insert the single hex screw that secures
the door’s ground strap to the cabinet frame.

11.

Route the CIPA bus cables from the H9652 cabinet to the VAXBI cardcage located in the left-

12.

Refer to the VAX 8800/8700 Installation Guide, part number EK-8800I-IN, for additional

rear of the CPU cabinet (see Figure 2-20).
intracabinet cabling.

2-28

REMOVAL

(CPU CABINET)
LEFT-FRONT
DOOR

MKV85-1614

Figure 2-19

CPU and Front-End Cabinet Mating (Sheet 1 of 9)

2-29

REMOVAL
(CPU CABINET)

RIGHT-REAR
DOOR

MKV85-1615

Figure 2-19

CPU and Front-End Cabinet Mating (Sheet 2 of 9)

2-30

'\f\

__ JL,_—--m

:I;_-—--—m

L’QLLL‘L

-LH

REMOVAL

(CPU CABINET)
TOP COVER
MKV85-1622

Figure 2-19

CPU and Front-End Cabinet Mating (Sheet 3 of 9)

2-31

REMOVAL

(CPU CABINET)
END PANEL
MKV85-1621

Figure 2-19

CPU and Front-End Cabinet Mating (Sheet 4 of 9)

2-32

DOOR OPENING
FRONT-END
CABINET

MKV85-1620

Figure 2-19

CPU and Front-End Cabinet Mat ing (Sheet 5 of 9)

2-33

SIDE-WALL

KEPNUTS

A
I
(NN

mmmmmm
nmmnmmmme
y

“mm”mHmWmMmMmMmWMmWmMmMHmI)

MMMWWWMMNMWM

CABINET

CPU

CABINET

(REAR-VIEW)

Fi gure 2-19

CPU and Front-End Cabinet Mating (Sheet 6 of 9)

2-34

REPLACEMENT
TOP COVER

— ‘“‘

\,\.

L - —e

___'L““’“‘m

| ‘ ‘ l=

M
|[ IT Ffifi; g I

]

(REAR-VIEW)
MKV85-1691

Fiigure 2-19

CPU and Front-End Cabinet Mating (Sheet 7 of 9)

2-35

REPLACEMENT

(CPU CABINET)
LEFT-FRONT

DOOR

MKV85-1625

Figure 2-19

CPU and Front-End Cabinet Mating (Sheet 8 of 9)

2-36

REPLACEMENT

(CPU CABINET)
RIGHT-REAR

DOOR

MKV85-1626

Figure 2-19

CPU and Front-End Cabinet Mating (Sheet 9 of 9)

2-37

N\ |
A-|

l”””””HH!HIHHHHHHHIHIIH
HIHHHIHHHHHHHHHHIH[UIHLII0uEH

mmmmmmmmmmwm

|
Im“ll””””l“””li
it

ZONE C

ZONEE

VAXBI'
CARDCAGE

(P/N17-01027-01)
MKV85-1618

Figure 2-20

2.6

CIPA Bus Cable Routing

MECHANICAL INSTALLATION (Add-On Level)

An existing VAX 8000-Series system can easily be upgraded and configured for operation in a cluster
environment. The upgrade process requires that the host system cabinetry contain sufficient space to
accommodate a 10.50 inch mounting box.

There are two styles of CIPA mounting boxes. The style can be distinguished by the type of cable
assembly, retractor or guidance, which is affixed at the rear of the mounting box (see Figure 2-21). A
cable retractor assembly is employed when configuring to either VAX 8200 or VAX 8300 systems, and a

cable guidance assembly is employed when configuring to either VAX 8500/8550 or VAX 8700/8800
systems.

Procedures for installing either mounting box are detailed in Sections 2.6.1 and 2.6.2.

2-38

CABLE GUIDANCE ASSEMBLY

MKV86-1361

Figure 2-21

CIPA Mounting Box Differences (Sheet 1 of 2)

2-39

CABLE RETRACTOR ASSEMBLY

MKV86-1357

Figure 2-21

CIPA Mounting Box Differences (Sheet 2 of 2)

2-40

[—

VAX 8200/8300 Systems

2.6.1

Procedure:

Using a 5/32 inch Allen wrench, remove front and rear doors of the CIPA cabinet.

Refer to Figure 2-22 while performing the following:

Attach the chassis slide-track containing a ground strap to the front-right vertical rail

Attach the free end of the ground wire to the vertical rail with a 10-32 screw and 10-32

(front to rear) by inserting a 10-32 screw into the bar nut and tightening.

nut and tighten.

Attach the other chassis slide-track to the front-left vertical rail (front to rear) by inserting
a 10-32 screw into the bar nut and tightening.

IDENTIFICATION
CHASSIS SLIDE TRACK

63>

FRONT RIGHT SLIDE TRACK

FRONT LEFT SLIDE TRACK

MKV86-1365

Figure 2-22

Mounting Box Installation Within an H9642 Cabinet (Sheet 1 of 3)

2-41

Extend each chassis slide-track outward from the cabinet by exerting pressure on the two

Lift the mounting box parallel with the slide-tracks. Insert the 6-32 screws into the slide-

release mechanisms.
tracks and tighten.

CAUTION

Lifting and handing the mounting box requires the
assistance of at least two individuals or a mechanical
lift device.

From the rear-inside of the cabinet, locate the free end of the flat ribbon CIPA bus cable.

Route the CIPA bus cable through the RFI shield panel knockout hole and waveguide and then
through the RFI shield panel knockout hole of the CPU cabinet.

Route the CIPA bus cable up through the interior of the processor cabinet to the bottom of the
BA32 mounting box and then outward from the cabinet.

Remove the cable strain relief clamp on the BA32 mounting box.

Route the CIPA bus cable through the I/ O cable slot locatedin the lower rear of the BA32
mounting box.

Place the power controller’s local/remote switch in its remote position.

Connect the power cord of the mounting box into the power controller’s switched receptacle (J8
for unit #1 or J9 for unit #2).

10.

Install the coaxial cable set assembly to either the bulkhead I/O panel or to the star coupler.

11.

Route, but do NOT connect at this time, the BNCIA-xx coaxial (CI bus) cables. Refer to the

12.

Star Coupler User’s Guide.

Perform the electrical installation detailed in Sections 2.7.1 through 2.7.3 of this manual.

2-42

INSTALL

PPOOD
P&
TTT"X"K_-J

CHASSIS SLIDE TRACK

@figxz;:,/jit’g
||

§i

LAl

/@@@b@@@@@

BRACKET DETAIL

Figure 2-22

MKV86-1397

Mounting Box Installation Within an H9642 Cabinet (Sheet 2 of 3)

INSTALL

MOUNTING BOX

e
DETAI L

—

_—

RELEASE

LATCH

SDCoo0O0 O

‘

TM~

CoM@? oMo oooooOcCccecoos oc:‘ N

(STOP )

4 TOTAL

MKV86-1358

Figure 2-22

Mounting Box Installation Within an H9642 Cabinet (Sheet 3 of 3)

2-44

2.6.2

VAX 8500/8550/8700/8800 Systems

Procedure:

Remove front and rear doors of the front-end cabinet or expansion cabinet by removing the
single hex screw securing the door’s ground strap to the cabinet frame, pulling the release
mechanism on each door hinge, and then lifting the door off its hinges.
Refer to Figure 2-23 while performing the following:

Attach the chassis slide-track containing a ground strap to the front-right vertical rail
(front to rear) by inserting a 1/4-20 screw into the 1/4-20 isolation mount and tightening.

Attach the free end of the ground wire to the vertical rail with a 10-32 screw and 10-32
nut, and tighten.

IDENTIFICATION

CHASSIS SLIDE TRACK

ISOLATION
MOUNT

PLASTIC
ST

‘

STRAP
STRAP

-Jr-nj

FRONT-RIGHT SLIDE TRACK

FRONT-LEFT SLIDE TRACK
MKV86-1362

Figure 2-23

Mounting Box Installation Within an H9652 Cabinet (Sheet 1 of 3)

2-45

Attach the other chassis slide-track onto the front-left vertical rail (front to rear) by

inserting a 1/4-20 screw into the 1/4-20 isolation mount and tightening it.
NOTE

To comply with Section 2.2.3 of this manual, visually inspect for the presence of:

1) A U-shaped gasket on both slide stiffeners of

each chassis slide-track.

2) A two inch U-shaped gasket at the front right
vertical rail of the cabinet and equally centered at
the mounting box latching mechanism.

3) Two small rubber bumper feet affixed to the cabinet’s front vertical rails in the vicinity of the chassis
slide-track.

d.
e.

Extend each chassis slide-track outward from the cabinet by exerting pressure on the two

release mechanisms.

Lift the mounting box parallel with slide-tracks, insert the 6-32 screws into the slidetracks, and tighten.

CAUTION

Lifting and handling the mounting box requires the
assistance of at least two individuals or a mechanical
lift device.

Route the CIPA bus cables from the cabinet to the VAXBI cardcage located in the processor
cabinet.
NOTE

Refer to the appropriate Installation Guide (EK8500I-IN or EK-8800I-IN) for additional intra-cabinet cabling.
R

Connect the power cord of the mounting box into the power controller’s switched receptacle.
Install the coaxial cable set assembly to the bulkhead I/O panel.

Route, but do NOT connect at this time, the BNCIA-xx coaxial (CI bus) cables. Refer to the
Star Coupler User’s Guide.

Perform the electrical installation detailed in Sections 2.7.1 through 2.7.3 of this manual.

2-46

INSTALL

\ \@

N
\

/ \ \\

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CHASSIS SLIDE TRACK

//| N

—

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.////2 ‘i

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gfiy@'%U

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19
0

N
BRACKET

DETAIL
MKV86-1366

Figure 2-23

Mounting Box Installation Within an H9652 Cabinet (Sheet 2 of 3)

2-47

INSTALL

MOUNTING BOX

DETAIL

(STOP)

1]
§0

U-SHAPE

L~ GASKET

SISECEE) olo o ols) o " oo o0 oo o ok

—_—
RELEASE

4 TOTAL

'RUBBER
BUMPER

L
MKV86-1370

Figure 2-23 Mounting Box Installation Within an H9652 Cabinet (Sheet 3 of 3)
2.7
2.7.1

ELECTRICAL INSTALLATION AND CONFIGURATION
T1017 and T1018 Module Installation
CAUTION

Use a static discharge system (VelostatTM Kit P/N
29-11762-00) when handling the T1017 and T1018
modules to prevent damage due to electrostatic
discharge.

NOTE

Proceed directly to Step 3 if the VAXBI cardcage
already contains the T1017 and T1018 modules and
the BCI cables.

* VelostatTM is a trademark of the Minnesota Mining and Manufacturing Co.

2-48

Procedure:

Carefully insert the T1017 and T1018 modules into any two unoccupied but adjacent module
slots within the VAXBI cardcage (see Figure 2-24).
CAUTION

When installing the modules, the T1017 must be
positioned to the left of the T1018 module.

VAXBI

CARDCAGE
(FRONT)

T1017 MODULE

—

T1018 MODULE -

Figure 2-24

MKV 85-1692

VAXBI Backplane — Module Installation

2-49

Refer to Figure 2-25 while carefully connecting the BCI cables to the VAXBI cardcage

connectors, as follows:
a.

Attach a 3 inch cable (P/N 17-01029-02) at zone C between the innermost connectors of

the T1017 and T1018 modules.

Attach a 3 inch cable (P/N 17-01029-02) at zone D between the innermost connectors of
the T1017 and T1018 modules.

Attach a 3.75 inch cable (P/N 17-01029-01) at zone C between the outermost connectors
of the T1017 and T1018 modules.

Attach a 3.75 inch cable (P/N 17-01029-01) at zone D between the outermost connectors
of the T1017 and T1018 modules.

Refer to Figure 2-26 while carefully connecting the CIPA bus cable to the VAXBI cardcage

connectors, as follows:

CAUTION

Orientate the marker stripe on the cable assembly
toward zone A of the VAXBI cardcage.

Attach connector P6 of the CIPA bus cable (P/N 17-01027-01) to the side 2 connector of
the T1017 module at zone E.

Attach connector P5 of the CIPA bus cable (P/N 17-01027-01) to the side 1 connector of
the T1017 module at zone E.

Attach connector P4 of the CIPA bus cable (P/N 17-01027-01) to the side 2 connector of
the T1018 module at zone E.

Attach connector P3 of the CIPA bus cable (P/N 17-01027-01) to the side 1 connector of

the T1018 module at zone E.

2-50

Figure 2-25

VAXBI Backplane — BCI Cable Connections

2-51

71018

MODULE

Tot7
MODULE
P6

!
P5

pg4

ZONE E

ZONE D

ZONE C

VAXBI
CARDCAGE

—>§

MARKER
STRIPE

(TRANSITION-HEADER

CONNECTORS)

ZONE D

o mm‘[
||

[

ZONE C J
L

P/N 17-01027-01
MKV86-1368

Figure 2-26

VAX 8200 or VAX 8300 Systems

VAXBI Backplane — CIPA Bus Cable Connections (Sheet 1 of 2)

2-52

MARKER ——f
STRIPE

-, \

T1018

MODULE

VAXBI

CARD CAGE

(TRANSISTION-HEADER

r———

T“I

]

r ZONE C

CONNECTORS)

ZONE D

ZONE E

P/N 17-01027-01
MKV86-1364

VAX 8500/8550/8700/8800 Systems

Figure 2-26 VAXBI Backplane — CIPA Bus Cable Connections (Sheet 2 of 2)

2-53

2.7.2

CIPA Backplane Jumpers Verification

Eight jumpers (W1-W8) are used on the CIPA backplane to control certain operating parameters on the
data path (L0400) and link interface (1L0100) modules. These jumpers are configured at the factory for
normal operation, which is jumpers out.
Procedure:

Refer to Figure 2-27 while performing the following:

Remove the shipping screws that secure the CIPA mounting box to the cabinet frame.

REMOVE

SN
MKV86-1379

Figure 2-27

CIPA Mounting Box — Access (Sheet 1 of 3)

2-54

Release the safety latch located on the front of the mounting box at the upper-right corner
and slide the mounting box, on its rails, part way out of the cabinet.

SLIDE

RELEASE
MKV86-1376

Figure 2-27

CIPA Mounting Box — Access (Sheet 2 of 3)

2-55

Release the latches on the sides of the slide rails and pull the mounting box out to the full
extension of the rails.

EXTEND

MKV86-1360

Figure 2-27

CIPA Mounting Box - Access (Sheet 3 of 3)

2-56

O
AT

Y
O
T

AR I TR

DO\

CO>

ANRRTRRRE

§A

AR g
AR AN

eHESLOHOQ

| —t
c

B WO AN ERa SRRE S

| N1

i ——

ACCESS PANEL
LATCHES

JUMPER

Figure 2-28
2.

CIPA Mounting Box — Backplane Jumpers

Unlatch and open the CIPA backplane access cover located on the left of the CIPA mounting
box for access to the jumpers (see Figure 2-28).
NOTE

For additional information on the CIPA backplane

jumpers, refer to Appendix B.

2-57

2.7.3

Node Address Switch Verification

Two dual-inline switchpacks on the CI link interface module (L0100) provide the host system with a
unique Cl-node address within the VAXcluster. This address is typically a number from 0 to 15. To assign
a CI-node address, the switches on each of the switch packs (S1 and S2) must be set to the binary value of
the assigned number.
Procedure:

Remove the top access cover of the CIPA mounting box by removing the cover fasteners (see
Figure 2-29).

Loosen the two screws that secure the CIPA cardcage to the chassis.

REMOVAL

TOP ACCESS

COVER

COVER FASTENERS

(1 OF 14)

N
MKV86-1387

Figure 2-29

CIPA Mounting Box — Module Access (Sheet 1 of 4)

2-58

Raise the CIPA cardcage to its upright position (see Figure 2-29) by lifting the cardcage all the
way up until the safety latch button locks the cardcage in its upright position.
Determine the CI-node address to be assigned.

For CIBCI installations that create a new VAXcluster, select a CI-node address within the

range of the number of CI bus ports being installed.

For CIBCI installations that add a CI node to an existing VAXcluster, choose a node

address not currently assigned.

RAISE

CIPA

CARDCAGE

UNLATCH
CIPA

CARDCAGE

MKV86-1380

Figure 2-29

CIPA Mounting Box — Module Access (Sheet 2 of 4)

2-59

Configure the Cl-node address switches by setting S1 and S2 to the selected address. The on
position of each switch represents a logical zero and the off position a logical one (see Table 21).

Lower the cardcage by holding the cardcage with one hand and pulling the safety latch button

Tighten the two screws to secure the CIPA cardcage to the chassis.

with the other hand.

CONFIGURE
NODE ADDRESS

SWITCHES

o |W

e oA
NODE ADDRESS SWITCHES

MKV86-1363

Figure 2-29

CIPA Mounting Box — Module Access (Sheet 3 of 4)
2-60

LOWER

CIPA

CARDCAGE

l\\w

\gi\

&;
5

MKV85-1546

Figure 2-29

CIPA Mounting Box — Module Access (Sheet 4 of 4)

2-61

8. Locate the correct node address identification label. This label is part of a set (PN 3619264-17)
shipped with the star coupler hardware.

NOTE

Refer to the Star Coupler User’s Guide (EKSC004-UG or EK-SC008-UG) for additional
information.

2-62

Remove the paper backing from the address label. Place it on the outside of the CPU cabinet’s
back door (in a visible location).

10.

Replace the top access cover. Then, lower and retract the CIPA mounting box and replace the
cabinet front and rear doors.

NOTE

Do NOT install the BNCIA cables between the
CIBCI and the star coupler hardware at this time.
11.

Proceed to Chapter 3 for acceptance testing.

2-63

CHAPTER 3

ACCEPTANCE VERIFICATION

3.1

INTRODUCTION

Chapter 3 contains information on acceptance verification, including:

Power Setup and Verification — Applying ac power to the system and verifying proper dc power in the

CIPA mounting box.

Diagnostic Verification - Verifying the functionality of the CIBCI hardware by running diagnostic tests

with the system in a stand-alone environment.

Maintenance Verification — Facilitating VA Xcluster maintenance by describing the tools that are required

and /or provided for individual nodes or options within a VAXcluster system.
ATION

POWER SETUP AND VERIFIC
or buses and ac
Each CIBCI option is shipped with internal and external BNCIA-xx cabling (CIPAthisbuscabling,
effect the
Verify
cabinet.
CIPA
or
box
g
mountin
power cables) completed within the CIPA
in the
given
sequence
the
in
on
verificati
system
the
complete
necessary inter/intracabinet cabling, and

3.2

following two sections.

CAUTION

Ensure that the front panel keylock switch of the
VAX 8200 or VAX 8700 is in the off position before
system modules and cables are installed.
NOTE

It is assumed here that the cabinet doors of the
CPU(s) and the CIPA are still off as part of the
cabinet mating procedure discussed in Sections 2.5.1
|

and 2.5.2.

3.2.1

VAX 8200/8300 Systems

Procedure:

1. Switch the main circuit breakers on all ac power controllers to their OFF positions.
7. Place the remote/local switches on all ac power controllers in their remote positions.

3. Connect the ac power cable from the CIPA cabinet’s ac power controller to an external ac
power source.

4 Switch the main circuit breakers on all ac power controllers to their ON positions.

3-1

Insert a plastic switch-key into switch S2 (the lower switch) on the control panel and turn the

key clockwise to the halt enable (HALT EN) position (number 2 if you have the international

control panel), as shown in Figure 3-1.

Insert a second plastic switch-key into switch S1 (the upper switch) on the control panel and
turn the key clockwise to the enabled position (the symbol 1 1 if you have the international
control panel), as shown in Figure 3-1.

Standby

@R\m

Enable

@Bu?tery

Update
Halt

Auto Start |[®==8]| Restart

MKV85-1543

Figure 3-1

Control Panel Switches and LEDs

Verify the CIPA mounting box dc voltages by checking the LEDs on the top of the power

supply. All LEDs should be lit (on).

Turn off electrical power to the system by placing the plastic switch-key located in switch S1 on
the control panel to its most counterclockwise position.

Carefully lower the CIPA cardcage cover into the CIPA mounting box and secure it to the
chassis.

10.

Replace the top cover on the CIPA mounting box and slide the box back into the cabinet.

11.

Replace the front door on the H9642 CIPA cabinet and check that the door makes positive
contact with each RFI gasket spring on ALL edges.
NOTE

Do NOT replace the rear door on the H9642 CIPA
cabinet at this time.

12.

Replace all covers, doors, and panels on the VAX 8200/8300 system cabinets.

13.

Turn the plastic switch-key located in switch S1 (the upper switch) on the control panel
clockwise to the enabled position (the symbol 1 1 if you have the international control panel), as
shown in Figure 3-1.

14.

Observe that the red status fault indicator located on the control panel is on, indicating that the
CPU is performing its self-test routines.

If the CPU successfully passes its self-test, you will see the following display on the console
terminal:

#ABCDEFGHI JKLMN#
or

#ABCDEFGHI JK.MN#

If the CPU fails its self-test, consult the VAX 8200 Owner’s Manual or VAX 8300 Owner’s
Manual.

15.

Observe the successful completion of system-wide hardware initialization by verifying that the
red status fault indicator is turned off, and that the terminal contains a hexadecimal and periods
display.

If the red status fault indicator remains on, and one or more of the hexadecimal digits in the
display has a minus sign before it, an adapter hardware self-test failure was detected. Consult
the VAX 8200 Owner’s Manual or VAX 8300 Owner’s Manual.

3-3

VAX 8500/8550/8700/8800 Systems

Procedure:
1.

Switch the main circuit breakers on all ac power controllers to their OFF positions.
Place the remote/local switch on all ac power controllers in the remote position.
Switch the main circuit breaker on all ac power controllers to their ON positions.
Place the power on/off switch of the PC380 console system in its ON position.

Observe that a DIGITAL logo is displayed on the console video terminal screen. This display
indicates that the PC380 console system is performing its internal self-test routines.
NOTE

If the PC380 console system successfully passes its
self-tests, you will observe the console prompt (>>>)
on the screen. Otherwise, an image of the failure
problem will be displayed. In the case of a failure,
consult the PC380 Console User’s Guide.

Apply power to the system by entering the POWER ON console command language (CCL)
command. Use the PC380 console system keyboard as follows:
>>> POWER ON

Verify the CIPA mounting box dc voltages by checking the LEDs on the top of the power

supply. All LEDs should be lit (on).

Disconnect power to the system by entering the POWER OFF console command language
(CCL) command. Use the PC380 console system keyboard as follows:
»>>> POWER OFF

Carefully lower the CIPA cardcage cover into the CIPA mounting box and secure it to the
chassis.
10.

Replace the top cover on the CIPA mounting box and slide the box back into the cabinet.

11.

Replace the front door on the H9652 expander cabinet and check that the door makes positive
contact with each RFI gasket spring on ALL edges.
NOTE

Do NOT replace the rear door on the H9652
expander cabinet at this time.
12.

Replace all covers, doors, and panels on the system cabinetry.

13.

Reapply power to the system by entering the POWER ON console command language (CCL)
command. Use the PC380 console system keyboard as follows:
>>> POWER ON

3.3

DIAGNOSTIC VERIFICATION

To determine if the CIBCI adapter hardware is functioning properly, eight level 3 diagnostic programs
must be executed. These diagnostic programs, along with the their appropriate diagnostic supervisor
program, are contained on separate RX50 floppy diskettes.

Six of the eight level 3 diagnostic programs are executed with the system operating in a stand-alone
environment (not connected to a VAXcluster and not running under the VMS operating system). This 1s
referred to as repair level testing.

Two of the eight level 3 diagnostic programs are then executed in order to test the functionality of the
hardware. This is referred to as functional level testing. (See Tables 3-1 and 3-2.)

3-5

VAX 8200/8300 Systems

3.3.1

3.3.1.1 Preliminary Setup — Before running the diagnostics, make the following CI bus loopback
connections on the CI bulkhead connector panel located at the back of the CIPA cabinet (see Figure 3-2).
Procedure:

Using one of the attenuator pads (P/N 12-19907-01) and two of the modularity cables (P/N
70-18530-00) supplied in the CIxxx control distribution (CD) kit (A2-W0865-10), connect

transmit A (J22) to receive A (J24).

Perform the same connection for path B using the other attenuator and two modularity cables
from the Clxxx control distribution (CD) kit, part number A2-W0865-10. Connect transmit B

(J21) to receive B (J23).

For more information on CI bus termination, refer
to Appendix A.

MODULARITY
CABLE
P/N 70-18530-00

TRANS B | | TRANS A
RECV B

ATTENUATOR

RECV
A

PAD

+--1

P/N 12-19907-01

MODULARITY
CABLE
P/N 70-18530-00
MKV85-1607

Figure 3-2
3.3.1.2

Diagnostic Loopback Cable Connections

Loading the Diagnostic Supervisor Program -

Procedure:

Insert the RX50 diskette containing file EBSAA.EXE into the console RX50 disk drive unit 0.

Load the diagnostic supervisor program into physical memory by entering the following CCL

command at the console terminal:
>>> B
%

DIAGNOSTIC SUPERVISOR

Identify the CIBCI adapter and its node configuration parameters to the diagnostic supervisor
program, as follows:
DS> ATTACHCIBCI HUBPAAO 6 4 0

Select the CIBCI adapter as the unit under test, as follows:
DS> SELECT PAAO

Show the unit selected, as follows:
DS> SHOW SELECT

3.3.1.3 Repair Level Testing — A minimum of five (5) successful passes of each diagnostic program must
be completed to satisfy acceptance testing requirements. Examples 3-1 through 3-6 provide trace printouts
for diagnostics EVCKA through EVCKF, respectively.

NOTE

Help files are available under the diagnostic supervisor for all diagnostic programs including the supervisor program itself.

Procedure:

Remove the RX50 diskette from the console RX50 disk drive unit O.

Insert the RX50 diskette containing files EVCKA.EXE through EVCKF.EXE into the console
RX50 disk drive unit O.

Load the EVCKA diagnostic program, as follows:

DS» L'OAD EVCKA (first repair level diagnostic)

Set the desired diagnostic supervisor control flags to enable printing of the number and title of
each test before it is executed and to halt on a detected error. Set the flags as follows:
DS» SET FLAGS TRACE, HALT

Start the diagnostic program, as follows:
DS>» START/PASS:5

Repeat steps 3 through 5 to load and execute the remaining repair level diagnostics (EVCKB

through EVCKF).

3-7

EVCKA

DS»

LOAD

DS»

START/PASS:5

DS> SET FLAGS TRACE, HALT
DS> SET EVENT FLAGS 4

..Program: CIBCI - EVCKA Repair level, revision 1.0, 28 tesis,
at

00:24:40.75.

_PAAOD

Tesling:

SET EVENT FLAG 4 FOR REV LEVEL OF BIIC IN TEST 3
ERROR INTERRUPT CONTROL TEST
1:
Test
DEVICE TYPE REGISTER TEST
2:
Test
SELF TEST
BC AND CIBCI
3:
Test
REVISION LEVEL OF BIIC CHIP ON CIBCI IS: 0
Test
Test
Test

4
5
©6:

CNFGR - L WRITE ACCESS TEST
CNFGR - L READ ACCESS TEST
R/W TEST OF DIAG BIT IN CNFGR

Test

PORT DATA REGISTER - R/W TEST - SOURCE IS Bf

Test
Test

Test

Test
Test

Test

Test
Test

Test

CNFGR - L READ ACCESS TEST - AFTER DISABLING UCSREN IN BCICR
CNFGR - L READ ACCESS TEST - AFTER DISABLING STS IN BCICR

7:
8:

10:

11:
12:

13:

14:

BICA ADDRESS REGISTER TEST

25:

Test

R/W TEST OF CNFGR,BCAR AND BCMR TAKEN ALTOGETHER

19:

18:

Test

RECEIVED COMMAND DATA PATH TEST

17:

20:

Test

R/W TEST OF BCMR
R/W TEST OF DMA REGISTER

SIZE OF TRANSFER TEST
DMA FILE - R/W COUNTER TEST
DMA FILE - COUNTER SEQUENCE TEST

15:
16:

Test

Test
Test
Test
Test

R/W TEST OF BUFFERED COMMAND ADDRESS REGISTER (BCAR)

R/W TEST OF BCAR AND BCMR USING THE MASTER SEQUENCER
STOP TEST

CIPA DATA PATH TEST
R/W TEST OF BCAR
R/W TEST OF DMA REGISTER
TEST (CIPA BUX READ TEST)

21:
22:
23:
24:

PORT DATA REGISTER WITH DIAG BIT CLEAR,
WITH DIAG BIT CLEAR,
CIPAPD REGISTER READ

26:

NUACK TEST FOR NODE ADDRESS 200

27:

28:

L READ ACCESS TEST OF LS AFTER DISABLING UCSREN IN BCI CONTROL REG
L READ ACCESS TEST OF LS AFTER DISABLING STS IN THE BICSR
USER INTERRUPT CONTROL TEST

.End of run, 0 errors detected, pass count is 1,
time

15-JUL-1985 00:24:52.74

DS»>

Example 3-1

Trace Printout for Repair Diagnostic EVCKA

3-8

EVCKB

DS»

LOAD

DS»

SET

DS»

START/PASS:5

FLAGS

CIBCI

.Program:
at

TRACE,

HALT

- EVCKB Repair

level,

revision 1.0,

00:25:58.39.
~PAAD

Testing:
Test

Test

G5:

Test

BUSIB/IB IN DATA PATHS TEST
PMCSR ACCESS TEST
PMCSR - BIT READ/WRITE TEST
INITALIZE

Test

10:

Test

11:

Test

12:

Test

13:

Test

14:

Test

15:

Test

16:

Test

17:

Test

18:

Test

19:

Test

20:

Test

21:

Test

22:

Test

23:

Test

24:

Test

25:

Test

26:

Test

27:

.End of run,
time

TEST

MADR/BUS MD DATA PATHS TEST
LOCAL STORE DUAL ADDRESS TEST
LOCAL STORE READ/WRITE RAM TEST
LOCAL STORE DYNAMIC MEMORY TEST
INTERLOCKED READ/WRITE TEST
VCDT - READ/WRITE RAM TEST
VCDT DUAL ADDRESS TEST
VCDT DYNAMIC MEMORY TEST
CONTROL STORE - DUAL ADDRESS TEST

CONTROL STORE - READ/WRITE RAM TEST
CONTROL STORE RAM DYNAMIC MEMORY TEST
CONTROL STORE ROM INSERTION TEST

REGISTER DUAL ADDRESS TEST
BUSIB SOURCE=LIT DEST=LSILITI
BUSIB SOURCE EQUALS ALU
BUSIB DESTINATION IS VCDTILITI
BUSIB SOURCE EQUALS LSILITI
BUSIB SOURCE EQUALS VCDTILITI
BUSIB DESTINATION EQUALS LSIINDEX]
INDEX REGISTER SA0/SA1 CHECK
BUSIB SOURCE LSIINDEX]I
BUSIB DESTINATION EQUALS LSIXLATE]
BUSIB SOURCE EQUALS LSIXLATE]

0 errors detected,

15-JUL-1985

pass countl

1is

00:29:37.92

DS»

Example 3-2

Trace Printout for Repair Diagnostic EVCKB

3-9

27 tests,

LOAD

DS>»

DS»
DS»

EVCKC

SET FLAGS TRACE,
START/PASS:5

HALT

.Program: CIBCI - EVCKC Repair level, revision 1.0, 33 tests,
at 00:30:00.96.
Testing: _PAAD

Test

2911 SEQUENCER JUMP TEST

#2901 ALU FUNCTION TEST

CONTROL STORE PARITY ERROR TEST
©2901' RAM DUAL ADDRESS TEST
w2901 RAM/Q STUCK BIT TEST
©"2901" RAM/Q REGISTER SHIFT

Test
Test
Test
Test

2:
3:
4:
G5:

Test
Test
Test
Test

7:
8:
9:
10:

Test

Test
Test

Test

11:
12:

13:

#2901
w2901
w2901
m29(01"

CODE
CODE
CODE
CODE

CONDITION
CONDITION
CONDITION
CONDITION

Z
N
V
C

BRANCH
BRANCH
BRANCH
BRANCH

2911 SEQUENCER UPC+1 TEST
2911 SEQUENCER JSR TEST
POP!?

MICROSTCK

1B<00>
1B<08>»
I1B¢12>
1B¢<15>
1B¢<20>
1B«¢21>
1B<24>
1B¢31>

BRANCH
BRANCH
BRANCH
BRANCH
BRANCH
BRANCH
BRANCH
BRANCH

TEST
TEST
TEST
TEST
TEST
TEST
TEST
TEST

TEST.
TEST.
TEST.
TEST.

Test
Test
Test
Test
Test
Test
Test
Test

14:
15:
16:
17:
18:
19:
20:
21:

BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS

Test
Test

26:
27:

BUS IB¢19> <¢18> ¢17> <16> BRANCH TEST
MAINTENANCE TIMER DISABLE BRANCH TEST

Test
Test
Test
Test

Test

Test
Test

Test

Test
. Test

22:
23:
24:
25L:

28:

29:
30:

31:

32:
33:

BUS
BUS
BUS
BUS

IB¢<10>
IB¢14>
1B«¢26>
1B«¢26>»

BRANCH
BRANCH
BRANCH
BRANCH

<¢09>
<13>
<22>
<«25>

TEST
TEST
TEST
TEST

TICK BRANCH TEST

XBOR - PORT INITIATED WRITE TEST

BICA CMMD ADDR REG - PORT INITIATED WRITE TEST
BYTE MASK - PORT INITIATED WRITE TEST

.End of run, 0 errors detected, pass count is 1,
time

15-JUL-1985 00:32:56.24

DS»

Example 3-3

Trace Printout for Repair Diagnostic EVCKC

3-10

DS>

LOAD

DS>»

SET

EVCKD

DS>»

START/PASS:5

FLAGS

.Program:
at

TRACE,

CIB CI

HALT

EVCKD Repair

level,

revision

1.0,

tests,

00:33:15.20.

Testing:
Test

Test

TEST
Test
TEST
Test

TEST

-PA AOD

IGNORED
10

IGNORED
11:

IGNORED

Test

12:

Test

14:

Test

15:

EXTERNAL BUS LONGWORD WRITE TO MEMORY TEST
LOCAL STORE PARITY ERROR TEST
DYNAMIC LOCAL STORE MOVING INVERSIONS
DYNAMIC VCDT MOVING INVERSIONS
EXTERNAL BUS LONGWORD READ TO MEMORY TEST
EXTERNAL BUS INTERLOCK READ TO MEMORY TEST

EXTERNAL BUS INTERLOCK WRITE TO MEMORY TEST
EXTERNAL BUS LONGWORD WRITE TO NXM TEST
CORRECTABLE READ DATA TEST FOR VAX-11/750
FOR

THIS

PROCESSOR

SUBSTITUTE

READ DATA
FOR

THIS

FOR

VAX-11/750

SUBSTITUTE TEST FOR VAX

READ DATA
FOR

TEST

PROCESSOR

THIS

8700

PROCESSOR

CORRECTABLE READ DATA TEST FOR VAX 8200
READ DATA SUBSTITUTE TEST FOR VAX 8200
EXTERNAL BUS EXTENDED WRITES TEST
EXTERNAL BUS EXTENDED READS TEST
EXTERNAL BUS MASK REGISTER TEST

Test

16:

Test

17:

INTERRUPT

Test

18:

MTE

Test

19:

CIPA BUS

Test

20:

SUSPEND

TEST

INTERRUPT TEST
PARITY ERROR (CBPE)X

DURING

AND

EXECUTE

TEST

PACKET BUFFER UUT/IN REG LOOPBACK TEST
21:
Test
.End of run, 0 errors detected, pass couni is 1,
time is 15-JUL-1985 00:34:43.62
DS»

Example 3-4

Trace Printout for Repair Diagnostic EVCKD

EVCKE

LOAD

DS>»

DS»
DS»

HALT

SET FLAGS TRACE,
START/PASS:5

.Program: CIBCI - EVCKE Repair level, revision 1.0,

13 testis,

00:34:59.99.

-PAAOD

Testing:

PACKET BUFFER SELECT TEST

QONOUTD
WN —

Test
Test
Test

Test

Test
Test
Test
Test
Test

OUTPUT PARITY ERROR TEST GENERATED BY PBIR

TRANSMIT BUFFER '"A*TM PATH/ADDR CHECK
TRANSMIT BUFFER *"B*TM PATH/ADDR CHECK
RECEIVE BUFFER "A* PATH/ADDR CHECK
RECEIVE BUFFER "B*" PATH/ADDR CHECK

Test

Test
13:

Test

.End of run,

0 errors detected,

15-JUL-1985

time

TRANSMIT BUFFER TMATM SA1/SA0
TRANSMIT BUFFER *"B" SA1/SA0
RECEIVE BUFFER '"ATM SA1/SA0
RECEIVE BUFFER TMB" SA1/SA0
FORCE RECEIVE BUFFER PARITY ERROR
RECEIVE BUFFER TMA' OVERFLOW TEST
RECEIVE BUFFER "B'" OVERFLOW TEST

pass counl

00:36:29.06

DS»

Trace Printout for Repair Diagnostic EVCKE

Example 3-5
DS»

LOAD EVCKF

DS»

START/PASS:5

DS>

SET FLAGS TRACE,

HALT

.Program: CIBCI - EVCKF Repair level, revision 1.0, 14 tests,
at

00:39:31.19.
~_PAAD

Testing:

INTERNAL MAINTENANCE LOOP TEST

CONOUTD
WM —

Test

Test
Test
Test

Test
Test

INTERNAL MT LOOPBACK WHILE LOADING XMIT BUFFER TEST
INTERNAL MT LOOP TEST WITH ONE RCV BUF AVAILABLE
INTERNAL MT LOOP TEST WITH NO REV BUF’S AVAILABLE
INTERNAL MAINT LP WITH SWAP NODE ADDRESS

TRANSMIT BUFFER PARITY ERROR TEST

ALTERNATING PACKET BUFFER UNLOAD TEST
ARBITRATION TEST N+I+1

EXTERNAL MAINT.
EXTERNAL MAINT.

Test

EXT.
EXT.

Test

Test
14:

Test

time

LOOP *"RECEIVERS DISABLED®"
LOOP "ABORTNG TRANSMISSION®

BACKNOWLEDGE TIMEOUT®TM TEST

Test

.End

MAINT.
MAINT.

LOOP PATH '"A"TM
LOOP PATH "BTM

EXTERNAL BUS LONGWORD WRITE TO ITSELF (LOCAL STORE)D

0 errors detected, pass counil
15-JUL-1985 00:40:26.82

run,

1is

DS»

Example 3-6

Trace Printout for Repair Diagnostic EVCKF

3-12

3.3.1.4 CI Bus Cable Testing — After successfully completing five passes of each of the six repair level
diagnostics, remove the attenuator pads and modularity cables from the CI bulkhead connector panels
(J21-J24) and perform the following steps:
Procedure:
1.

Verify that this CIBCI port has a unique node address within the VAXcluster before connecting
any cables.

Locate the set of four CI bus coaxial cables (BNCIA-xxx) and connect one end of each cable to
the appropriate CI bulkhead connector panels.
NOTE

The coaxial CI bus cables may be connected or
removed from the CI bulkhead connector panels
without powering down either the system or the
CIPA cabinet. DO NOT unroll or route the CI bus
cables at this time.

Connect the two attenuator pads to the free ends of the coaxial CI bus cables. Be sure to
connect transmit A to receive A, and transmit B to receive B.

Run five passes of the external loop section of the diagnostic program EVCKF to test the CI bus
cables, as follows:
DS>» RUN EVCKF/SECTION:EXTM_LOOP/PASS:5

3.3.1.5 Functional Level Testing — With the CI bus cables and attenuator pads providing signal loopback, load and run the CI functional diagnostics EVGAA and EVGAB. A minimum of five passes of each
diagnostic must be completed to satisfy acceptance testing requirements. Examples 3-7 and 3-8 show trace
printouts for diagnostics EVGAA and EVGAB, respectively.
Procedure:
1.

Ensure that the RX50.diskette containing files EVGAA.EXE and EVGAB.EXE is installed in

the console RX50 disk drive unit O.

Load the EVGAA diagnostic program, as follows:

DS> LOAD EVGAA (first functional diagnostic)
Set event flags 1 and 2 to reload the CI microcode and output the port queue entries. This is
always required after running the repair level diagnostics. Set the event flags as follows:
DS>» SET EVENT FLAG 1, 2

Set the desired diagnostic supervisor control flags to enable printing of the number and title of

each test before it is executed and to halt on a detected error, as follows:
DS>» SET FLAGS TRACE, HALT

3-13

DS>
DS»

LOAD EVGAA
SET EVENT FLAGS

DS»

START/PASS:5

DS» SET FLAGS TRACE,

HALT

.Program: EVGAA - CI FUNCTIONAL PART I, revision 2.5, 17 testis,
at 00:48:21.95.
Testing: _-PAAD
1:

FLAG

EVENT

DIAGNOSTIC WILL LOAD CI

RAM UCODE

FROM THE DEFAULT LOAD PATH.
EVENT

FLAG

EVENT

FLAG

OQUTPUT THE PORT QUEUE ENTRIES.

INVOKES THE REQUEST ID LOOP FUNCTION.

WCS REVISION = 4

ROM REVISION = 3

CLUSTER CONFIGURATION

Test

CLUSTER CONFIGURATION -- PATH A
*******************************

NOTE:

YOU CANNOT DIFFERENTIATE BETWEEN A CI780 AND CI1750 REMOTELY.

NODE #

DEVICE TYPE

ROM/WCS REV.

CI7X0

PORT FUNCTIONALITY

PATH

TYPE

FFFFFFOOCX)

DUAL

PATH

PORT FUNCTIONALITY

PATH

TYPE

FFFFFFOO0(X)

DUAL

PATH

CLUSTER CONFIGURATION -- PATH B
R R R A B RS
R R R E R B EEEE
Y YEYEEEZE

NODE #

DEVICE TYPE

ROM/WCS REV.

CI7XO0

Test

Test
Test

Test

SETCKT TEST WITH VARIOUS MASKS AND M_VALUES

SETCKT TEST FOR EACH VALID PORT
SETCKT TEST FOR NVALID PORT

3:
4:

REQGID TEST

b5:

REQID TEST WITH 6 PACKETS ON DGFAQ

Test

Test
Test

10:
11:

Test

Test
Test

Test
Test
Test
Test
Test

DATAGRAM DISCARD TEST

SEND DATAGRAM -SNDDG- TEST

RESPONSE QUEUE AVAILABLE INTERRUPT TEST

12:

13:
14:
15:
16:
17:

.End of run,
time

SNDMSG TEST WITH NOVIRTUAL CIRCUIT TEST
SEND MESSAGE TEST, CROSSING PAGE BOUNDARY

MESSAGE LENGTH TEST

PACKET SIZE VIOLATION TEST
SEND LOOPBACK -SNDLB- TEST
SNDLB TEST, FULL BUFFER PATH A
SNDLB TEST, FULL BUFFER PATH B
SNDLB TEST, BOTH PATHS

0 errors detected, pass counil 1is5 1,

15-JUL-1985

00:50:40.36

DS»>

Example 3-7

Trace Printout for Functional Diagnostic EVGAA
3-14

Start the EVGAA diagnostic program, as follows:
DS>» START/PASS:5

After five successful passes, remove the console floppy diskette, insert the diagnostic floppy
diskette, clear event flags 1 and 2, and then load and run the EVGAB diagnostic program

(second functional diagnostic) for five successful passes.

8. Turn off the electrical power to the system by placing the VAX 8200 control panel keylock
switch (upper switch) in the OFF position.

DS>
DS>»

LOAD EVGAB
CLEAR EVENT

DS»

FLAG 1, 2
SET FLAGS TRACE, HALT

DS»

START/PASS:5

.Program: EVGAB - CI FUNCTIONAL PART II, revision 2.5,

12 tests,

00:50:54.31.
Testing: _-PAAD
at

WCS REVISION = 4

ROM REVISION = 3

Test
Test

Test
Test
Test
Test
Test
Test

Test
Test
Test
Test

SEND DATA TEST, WITH OFFSET COMBINATIONS
REQUEST DATA TEST, WITH OFFSET COMBINATIONS

1:
2:

INVALIDATE TRANSLATION CACHE TEST
SNDMDAT TEST, ENABLED/MAINTENANCE STATE

3:
4:
b5:
6:
7:
8:

9:
10:
11:
12:

.End of run,
time

SNDMDAT TEST, ENABLED STATE
REQMDAT TEST, ENABLED/MAINT STATE
REQMDAT TEST, ENABLED STATE
SEND RESET TEST IN ENABLED STATE
QUEUE CONTENTION TEST
BUFFER READ ACCESS TEST
BUFFER WRITE ACCESS TEST
WRITE TO GLOBAL BUFFER TEST
0 errors detected, pass count is 1,

15-JUL-1985

00:52:29.92

DS»>

Example 3-8

9.
10.

Trace Printout for Functional Diagnostic EVGAB

Replace the rear door on the CIPA cabinet and check that the door makes positive contact with

each RFI gasket spring on all edges.

Disconnect the attenuator pads from the ends of the CI bus cables in preparatlon for routing

and connecting the cables to the star coupler.
NOTE

For information on connecting the coaxial CI bus
cables to the star coupler, refer to the SC004 or
SC008 Star Coupler User’s Guide.

3-15

VAX 8500/8550/8700/8800 Systems

3.3.2

3.3.2.1 Preliminary Setup — Before running the diagnostics, make the following CI bus loopback
connections on the CI bulkhead connector panel located at the back of the system cabinet (see Figure 3-3).
Procedure:

Using one of the attenuator pads (P/N 12-19907-01) and two of the modularity cables (P/IN

70-18530-00) supplied in the CIxxx control distribution (CD) kit (P/N A2-W0865-10), connect

transmit A (J22) to receive A (J24).

Perform the same connection for path B using the other attenuator and two modularity cables
from the generic Clxxx control distribution (CD) kit, part number A2-W0865-10. Connect

transmit B (J21) to receive B (J23).

MODULARITY
CABLE
P/N 70-18530-00

PAD
P/N 12-19907-01

MODULARITY
CABLE
P/N 70-18530-00
MKV85-1607

Figure 3-3

Diagnostic Loopback Cable Connections
NOTE

For more information on CI bus termination, refer
to Appendix A.

3-16

Loading the Diagnostic Supervisor Program -

3.3.2.2

Procedure:

Insert the RX50 diskette containing file EZSAA.EXE into the PC380 console system’s RX50

disk drive unit O.

Load the diagnostic supervisor program resident on the PC380 console system disk into physical
memory by entering the following CCL command. Use the PC380 console system keyboard as
follows:

>>> DIABOO
%%

DIAGNOSTIC SUPERVISORP .1e1a;D5>

Attach the CPU to its memory and NBI adapters, as follows:
DS>» ATTACH KAAAA HUB KAOD YES
DS>» ATTACH KAAAA HUB KA1 NO
DS>» ATTACH MSAAA HUB MS0
DS» ATTACH NBIA HUB NBIAO 0

DS> ATTACH NBIB NBIAO NBIBO 0 0
DS>» ATTACH NBIB NBIAO NBIB1 10
DS>» ATTACH NBIA HUB NBIA1 1
DS» ATTACH NBIB NBIA1 NBIBO 0 0
DS» ATTACH NBIB NBIA1 NBIB1 10

Identify the CIBCI adapter and its node configuration parameters to the diagnostic supervisor

program, as follows:

DS» ATTACH CIBCI NBIB0O PAA0O 6 4 0

Select the CIBCI adapter as the unit under test, as follows:
DS» SELECT PAAOD

Show the unit selected, as follows:
-

DS> SHOW SELECT

3.3.2.3 Repair Level Testing — Use the following procedure to load and run the repair level diagnostics in
sequence from 1 to 6. A minimum of five (5) successful passes of each diagnostic program must be
completed to satisfy acceptance testing requirements. Examples 3-9 through 3-14 provide trace printouts
for diagnostics EVCKA through EVCKF, respectively.

NOTE

HELP files are available under the diagnostic supervisor for all of the diagnostic programs.

3-17

Procedure:

Remove the RX50 diskette from the PC380 console system’s RX50 disk drive unit 0.

Insert the RX50 diskette containing files EVCKA.EXE through EVCKF.EXE into the PC380

console system’s RX50 disk drive unit 0.

Load the EVCKA diagnostic program, as follows:

DS> LOAD EVCKA (first repair level diagnostic)

DS»

DS»
DS»
DS»

LOAD

EVCKA

SET FLAGS TRACE,
SET EVENT FLAG 4

HALT

START/PASS:5

. .Program: CIBCI - EVCKA Repair level, revision 1.0, 28 testis,
at

00:24:40.75.
_-PAAOD

Testing:

SET EVENT FLAG 4 FOR REV LEVEL OF BIIC IN TEST 3
ERROR INTERRUPT CONTROL TEST
1:
Test
DEVICE TYPE REGISTER TEST
2:
Test
BC AND CIBCI SELF TEST
3:
Test
REVISION LEVEL OF BIIC CHIP ON CIBCI IS: O

Test
Test
Test

4
5
6:

CNFGR - L WRITE ACCESS TEST
CNFGR - L READ ACCESS TEST
R/W TEST OF DIAG BIT IN CNFGR

Test

PORT DATA REGISTER - R/W TEST - SOURCE IS Bf

Test
Test

Test

Test
Test

Test

Test
Test

Test
Test
Test
Test

Test
Test

CNFGR - L READ ACCESS TEST - AFTER DISABLING UCSREN IN BCICR
CNFGR - L READ ACCESS TEST - AFTER DISABLING STS IN BCICR

7:
8:

R/W TEST OF BUFFERED COMMAND ADDRESS REGISTER (BCAR)

10:

R/W TEST OF BCMR

11:

R/W TEST OF DMA REGISTER
RECEIVED COMMAND DATA PATH TEST

12:
13:

R/W TEST OF CNFGR,BCAR AND BCMR TAKEN ALTOGETHER

14:

SIZE OF TRANSFER TEST

15:

16:
17:

DMA FILE - R/W COUNTER TEST
DMA FILE - COUNTER SEQUENCE TEST

19:

BICA ADDRESS REGISTER TEST

R/W TEST OF BCAR AND BCMR USING THE MASTER SEQUENCER

18:

STOP TEST

20:

21:
22:
23:
24:

PORT DATA REGISTER - CIPA DATA PATH TEST
WITH DIAG BIT CLEAR, R/W TEST OF BCAR

26:

NUACK TEST FOR NODE ADDRESS 200

28:

USER INTERRUPT CONTROL TEST

WITH DIAG BIT CLEAR, R/W TEST OF DMA REGISTER
CIPAPD REGISTER READ TEST (CIPA BUX READ TEST)

L READ ACCESS TEST OF LS AFTER DISABLING UCSREN IN BCI CONTROL REG

25:

L READ ACCESS TEST OF LS AFTER DISABLING STS IN THE BICSR

27:

.End of run,
time

0 errors detecied, pass count is 1,

15-JUL-1985 00:24:52.74

Example 3-9

Trace Printout for Repair Diagnostic EVCKA

3-18

Set the desired diagnostic supervisor control flags to enable printing of the number and title of
each test before it is executed and to halt on a detected error, as follows:
DS» SET FLAGS TRACE, HALT
DS> SET EVENT FLAG 4

Start the diagnostic program, as follows:
DS» START/PASS:5

Repeat steps 3 through 5 to load and execute the remaining repair level diagnostics (EVCKB
through EVCKF).

DS»

LOAD EVCKB

DS»

START/PASS:5

DS»

SET FLAGS TRACE,

HALT

.Program: CIBCI - EVCKB Repair level, revision 1.0, 27 testis,
at 00:25:58.39.
Testing: _-PAAD

Test

BUSIB/IB IN DATA PATHS TEST

PMCSR - BIT READ/WRITE TEST

Test

PMCSR ACCESS TEST
INITALIZE TEST

Test
Test
Test
Test
Test
Test
Test
Test
Test
Test

b5:
©6:
7:
8:
9:
10:
11:
12:
13:
14:

Test
Test
Test
Test
Test
Test
Test
Test
Test

17:
18:
19:
20:
21:
22:
23:
24:
25:

REGISTER DUAL ADDRESS TEST
BUSIB SOURCE=LIT DEST=LSILIT]
BUSIB SOURCE EQUALS ALU
BUSIB DESTINATION IS VCDTILITI
BUSIB SOURCE EQUALS LSILITI
BUSIB SOURCE EQUALS VCDTILITI
BUSIB DESTINATION EQUALS LSLINDEX]
INDEX REGISTER SA0/SA1 CHECK
BUSIB SOURCE LSI[INDEX]

Test

27:

BUSIB SOURCE EQUALS LSIXLATE]

Test
Test

Test

15:
16:

26:

CONTROL STORE RAM DYNAMIC MEMORY TEST
CONTROL STORE ROM INSERTION TEST

BUSIB DESTINATION EQUALS LSIXLATE]

.End of run, 0 errors detected, pass count is 1,
time

15-JUL-1985 00:29:37.92

DS»>

Example 3-10

Trace Printout for Repair Diagnostic EVCKB

3-19

EVCKC

DS>

LOAD

DS>»

SET

DS»

START/PASS:5

FLAGS

CIBCI

.Program:
at

TRACE,

HALT

level,

- EVCKC Repair

revision

1.0,

tests,

00:30:00.96.

Testing:

_-PAAD

2911 SEQUENCER JUMP TEST
CONTROL STORE PARITY ERROR TEST
“2901" RAM DUAL ADDRESS TEST
w2901 RAM/Q STUCK BIT TEST
#2901" RAM/Q REGISTER SHIFT
#2901 ALU FUNCTION TEST
#2901 CONDITION CODE Z BRANCH TEST.
“2901* CONDITION CODE N BRANCH TEST.
#2901 CONDITION CODE V BRANCH TEST.
2901 CONDITION CODE C BRANCH TEST.
2911 SEQUENCER UPC+1 TEST
2911 SEQUENCER JSR TEST

Test
Test
Test
Test
Test
Test
Test
Test
Test
Test
Test
Test

1:
2:
3:
4:
5:
6:
7:
8:
9:
10:
11:

Test

13:

Test
Test

14:
15:

POPt!t! MICROSTCK
BUS 1B¢<00>» BRANCH
BUS 1B<08> BRANCH

TEST
TEST

Test
Test
Test

Test
Test
Test
Test
Test
Test
Test

16:
17:
18:
19:

BUS
BUS
BUS
BUS

IB¢12»
IB¢15»
[IB¢20>»>
IB¢21>»

BRANCH
BRANCH
BRANCH
BRANCH

TEST
TEST
TEST
TEST

20:
21:
22:
23:
24:
25:

BUS
BUS
BUS
BUS
BUS
BUS

IB¢<24>»
1B¢31»
IB¢10>
IB¢14>
1B«¢26>
1B«¢26>

BRANCH TEST
BRANCH TEST
<09>» BRANCH TEST
<¢13>»> BRANCH TEST
<22> BRANCH TEST
<25 BRANCH TEST

Test
Test

26:
27:

BUS IB¢19>» <¢18> <17 <16> BRANCH TEST
MAINTENANCE TIMER DISABLE BRANCH TEST

Test
Test
Test
Test

28:
29:
30:

TICK BRANCH TEST
REGISTER WRITTEN
REGISTER WRITTEN

12:

XBOR

32:
Test
33:
Test
.End of run,
time

PORT

BRANCH T1
BRANCH T2
INITIATED WRITE

TEST

BICA CMMD ADDR REG - PORT INITIATED WRITE TEST
BYTE MASK - PORT INITIATED WRITE TEST
0 errors detected, pass count is 1,

15-JUL-1985

00:32:56.24

DS»

Example 3-11

Trace Printout for Repair Diagnostic EVCKC

3-20

DS»

EVCKD

LOAD

DS»

SET FLAGS TRACE,

DS»

START/PASS:5

HALT

.Program: CIBCI - EVCKD Repair level, revision 1.0, 21 testis,
at

00:33:15.20.
_PAAD

Testing:
Test
Test
Test
Test
Test
Test
Test

Test
Test
TEST

EXTERNAL BUS LONGWORD WRITE TO MEMORY TEST

DYNAMIC LOCAL STORE MOVING INVERSIONS

S:
6:
7:
8
9:

EXTERNAL BUS LONGWORD READ TO MEMORY TEST
EXTERNAL BUS INTERLOCK READ TO MEMORY TEST
EXTERNAL BUS INTERLOCK WRITE TO MEMORY TEST
EXTERNAL BUS LONGWORD WRITE TO NXM TEST
CORRECTABLE READ DATA TEST FOR VAX-11/750

LOCAL STORE PARITY ERROR TEST

DYNAMIC VCDT MOVING

INVERSIONS

FOR THIS PROCESSOR
IGNORED
G

10:

READ DATA SUBSTITUTE TEST FOR VAX-11/750

11:
12:

READ DATA SUBSTITUTE TEST FOR VAX 8700
CORRECTABLE READ DATA TEST FOR VAX 8200

11:

READ DATA SUBSTITUTE TEST FOR VAX 8200

Test

14:
15:
16:

EXTERNAL BUS EXTENDED WRITES TEST
EXTERNAL BUS EXTENDED READS TEST
EXTERNAL BUS MASK REGISTER TEST

Test

17 :

Test
TEST
Test

TEST
Test
Test

Test
Test
Test

IGNORED FOR THIS PROCESSOR

INTERRUPT TEST

MTE DURING

20:

SUSPEND AND EXECUTE TEST

19:

21:
.End of run,
Test

time

INTERRUPT TEST

18:

CIPA BUS PARITY ERROR (CBPE) TEST

PACKET BUFFER UUT/IN REG LOOPBACK TEST
0 errors detected, pass counil is 1,

15-JUL-1985

00:34:43.62

DS»>

Example 3-12

Trace Printout for Repair Diagnostic EVCKD

3-21

EVCKE

DS>»

LOAD

DS»
DS»

SET FLAGS TRACE,
START/PASS:5

13 tests,

revision 1.0,

level,

- EVCKE Repair

CIBCI

.Program:

HALT

00:34:59.99.

~PAAD

Testing:

PACKET BUFFER

DAONOO
DL WMN -

Test
Test
Test
Test
Test
Test
Test

Test

TRANSMIT BUFFER '"A®TM PATH/ADDR CHECK
TRANSMIT BUFFER 'B"TM PATH/ADDR CHECK
RECEIVE BUFFER TMA' PATH/ADDR CHECK
RECEIVE BUFFER "B'" PATH/ADDR CHECK
TRANSMIT BUFFER "A"TM SA1/SA0
TRANSMIT BUFFER *"B" SA1/SA0
RECEIVE BUFFER TMATM SA1/SA0

Test

Test
Test
13:

Test

.End

run,

time

SELECT TEST

OUTPUT PARITY ERROR TEST GENERATED BY PBIR

RECEIVE BUFFER "B" SA1/SA0
FORCE RECEIVE BUFFER PARITY
RECEIVE BUFFER "A"TM OVERFLOW
RECEIVE BUFFER *B"TM OVERFLOW

errors

15-JUL-1985

detected,

pass

ERROR
TEST
TEST
count is 1,

00:36:29.06

DS»

Example 3-13
DS»

DS>»
DS»

EVCKF
SET FLAGS TRACE,
START/PASS:5

LOAD

CIBCI

.Program:
at

Trace Printout for Repair Diagnostic EVCKE

HALT

- EVCKF Repair

level,

revision

1.0,

14 tests,

00:39:31.19.
~PAAD

Testing:

INTERNAL MAINTENANCE

CONOUTDHE
WM =

Test
Test

Test

Test
Test
Test
Test
Test
Test
Test

Test
Test
14
:

.End of
time

TEST

INTERNAL MAINT LP WITH SWAP NODE ADDRESS
TRANSMIT BUFFER PARITY ERROR TEST
ALTERNATING PACKET BUFFER UNLOAD TEST
ARBITRATION TEST N+I+1
EXTERNAL MAINT. LOOP PATH TMATM
EXTERNAL MAINT. LOOP PATH TM"B*
EXT. MAINT. LOOP "RECEIVERS DISABLED"
EXT. MAINT. LOOP "ABORTNG TRANSMISSION*
“ACKNOWLEDGE TIMEOUT®TM TEST

Test

LOOP

INTERNAL MT LOOPBACK WHILE LOADING XMIT BUFFER TEST
INTERNAL MT LOOP TEST WITH ONE RCV BUF AVAILABLE
INTERNAL MT LOOP TEST WITH NO REV BUF’S AVAILABLE

run,

EXTERNAL BUS LONGWORD WRITE TO ITSELF
0 errors detected, pass count is 1,

15-JUL-1985

(LOCAL STORE)D

00:40:26.82

DS»

Example 3-14

Trace Printout for Repair Diagnostic EVCKF

3-22

3.3.2.4 CI Bus Cable Testing — After successfully completing five (5) passes of each of the siX repair
level diagnostics, remove the attenuator pads and modularity cables from the CI bulkhead connector
panels (J21-J24) and perform the following steps.
Procedure:
1.

Verify that this CIBCI port has a unique node address within the VAXcluster before connecting

any cables.

Locate the set of four CI bus coaxial cables (BNCIA-XX) and connect one end of each cable to

the appropriate CI bulkhead connector panel.
NOTE

Connect the two attenuator pads to the free ends of the coaxial CI bus cables. Be sure to
connect transmit A to receive A, and transmit B to receive B.

Run five passes of the external loop section of diagnostic program EVCKEF to test the CI bus

cables, as follows:

DS> RUN EVCKF/SECTION:EXTM_LOOP/PASS:5

3.3.2.5 Functional Level Testing - With the CI bus cables and attenuator pads providing signal loopback, load and run the CI functional diagnostics EVGAA and EVGAB. A minimum of five passes of each
diagnostic must be completed to satisfy acceptance testing requirements. Examples 3-15 and 3-16 show
trace printouts for diagnostics EVGAA and EVGAB, respectively.
Procedure:
1.

Insert the RX50 diskette containing EVGAA.EXE and EVGAB.EXE into the PC330 console

system’s RX50 disk drive unit 0.

Load the EVGAA diagnostic program, as follows:

DS»> LOAD EVGAA (first functional diagnostic)

Set event flags 1 and 2 to reload the CI microcode and output the port queue entries. This 1s

always required after running the repair level diagnostics. Set the flags as follows:
DS>

SET EVENT FLAGS

Remove the diagnostic floppy diskette and insert the console floppy diskette that contains the
CI780.BIN file.

Set the desired diagnostic supervisor control flags to enable printing of the number and title of
each test before it is executed and to halt on a detected error. Set the flags as follows:
DS»

SET FLAGS TRACE,

HALT

3-23

Start the EVGAA diagnostic program, as follows:
DS»

START/PASS:5

After five successful passes, remove the console floppy diskette, insert the diagnostic floppy
diskette, clear event flags 1 and 2, and then load and run the EVGAB diagnostic program

(second functional diagnostic) for five successful passes.

Disconnect power to the system by entering the POWER OFF console command language

(CCL) command using the PC380 console system keyboard, as follows:
»>>

POWER

OFF

Replace the rear door on the CIPA cabinet and check that the door makes positive contact with

each RFI gasket spring on ALL edges.
10.

Disconnect the attenuator pads from the ends of the CI bus cables in preparation for routing
and connecting the cables to the star coupler.
NOTE

For information on connecting the coaxial CI bus
cables to the star coupler, refer to the SC004 or
SC008 Star Coupler User’s Guide.

3-24

DS»

EVGAA

LOAD

DS>»
DS>»

SET EVENT FLAGS 1, 2
SET FLAGS TRACE, HALT

DS»

START/PASS:5

.Program: EVGAA - CI FUNCTIONAL PART I, revision 2.5,

17 tests,

00:48:21.95.

_-PAAD

Testing:
EVENT

FLAG

EVENT

FLAG

EVENT

FLAG

DIAGNOSTIC WILL LOAD CI RAM UCODE
FROM THE DEFAULT LOAD PATH.
QUTPUT THE PORT QUEUE ENTRIES.

INVOKES THE REQUEST

ROM REVISION

WCS REVISION = 4

= 3

CLUSTER CONFIGURATION

Test

ID LOOP FUNCTION.

CLUSTER CONFIGURATION -- PGTH A
N

EE R R E K B K & B B,
EEEEEE
I EEEEEEA

:
NOTE

YOU CANNOT DIFFERENTIATE BETWEEN A CI780 AND CI750 REMOTELY.
ROM/WCS REV.

DEVICE TYPE

NODE #

PATH

TYPE

FFFFFFOOCX)

DUAL

PATH

PORT FUNCTIONALITY

PATH

TYPE

FFFFFFOOCX)D

DUAL

PATH

CI7X0

PORT FUNCTIONALITY

CLUSTER CONFIGURATION

PATH B

E K E E B B & NN
R R R R B R EEEEEEE
I'SEYYTEIEEXEE

Test
Test

SETCKT TEST WITH VARIOUS MASKS AND M_VALUES

SETCKT TEST FOR EACH VALID PORT
SETCKT TEST FOR NVALID PORT

3
4

REQID TEST

REQID TEST WITH 6 PACKETS ON DGFQ

Test

Test
Test

10:
11:

Test

Test
Test
Test
Test
Test

DATAGRAM DISCARD TEST

SEND DATAGRAM -SNDDG- TEST

RESPONSE QUEUE AVAILABLE

12:

13:
14:
15:
16:
17:

.End of run,
time

CI7X0

0
Test
Test

ROM/WCS REV.

DEVICE TYPE

NODE #

INTERRUPT TEST

SNDMSG TEST WITH NOVIRTUAL CIRCUIT TEST
SEND MESSAGE TEST, CROSSING PAGE BOUNDARY

MESSAGE

LENGTH TEST

PACKET SIZE VIOLATION TEST
SEND LOOPBACK -SNDLB- TEST
SNDLB TEST, FULL BUFFER PATH A
SNDLB TEST, FULL BUFFER PATH B
SNDLB TEST, BOTH PATHS

0 errors detected,

15-JUL-1985

00:50:40.36

pass couni

DS»

Example 3-15

Trace Printout for Functional Diagnostic EVGAA
3-25

EVGAB

DS>»

LOAD

DS>»

START/PASS:5

DS> CLEAR EVENT FLAG 1, 2
DS> SET FLAGS TRACE, HALT

.Program: EVGAB - CI FUNCTIONAL PART II, revision 2.5, 12 tests,
at 00:50:54.31.
Testing: _PAAD

WCS REVISION = 4

ROM REVISION = 3

Test
Test
Test
Test

1:
2:
3:
4:

SEND DATA TEST, WITH OFFSET COMBINATIONS
REQUEST DATA TEST, WITH OFFSET COMBINATIONS
INVALIDATE TRANSLATION CACHE TEST
SNDMDAT TEST, ENABLED/MAINTENANCE STATE

Test
Test
Test
Test

9:
10:
11:
12:

QUEUE CONTENTION TEST
BUFFER READ ACCESS TEST
BUFFER WRITE ACCESS TEST
WRITE TO GLOBAL BUFFER TEST

Test
Test
Test
Test

b5:
©6:
7:
8:

.End of run,
time

SNDMDAT TEST, ENABLED STATE
REGMDAT TEST, ENABLED/MAINT STATE
REQMDAT TEST, ENABLED STATE
SEND RESET TEST IN ENABLED STATE

0 errors detected,

15-JUL-1985

00:52:29.92

pass count

DS»

Example 3-16

Trace Printout for Functional Diagnostic EVGAB

3-26

3.4

MAINTENANCE VERIFICATION

A number of software system tools are required in order to facilitate VAXcluster maintenance. These
software tools allow isolation of a potential failure to an individual node or option within a VAXcluster

system. Refer to Table 3-3.

3-27

CHAPTER 4
REGISTER SUMMARY

This section presents the interface conventions which allow programmer access to the CIBCI adapter
functions. Access to the CIBCI adapter functions is gained via addressable hardware and software registers
that are used to control and monitor the operation within the CIBCI adapter itself. Entry to these registers
is accomplished through the VAXBI address space area. The addressable hardware and software registers
and their bit map format are discussed in Section 4.3.
4.1

VAXBI ADDRESS SPACE

The physical address on the VAXBI is 30 bits long, thereby providing a VAXBI physical address space of
one gigabyte. A programmer accesses this physical address space whenever making reference to a CIBCI
adapter’s hardware or software register.

The VAXBI physical address space consists of two parts: memory space and 1/0O space. Selection of
memory space and I/O space is determined by address bit 29 of a read or write VAXBI bus transaction.
The first 512 megabytes (addresses 0000 0000 through 1FFF FFFF hexadecimal) are physical memory
space addresses. The last 512 megabytes of the VAXBI physical address space (addresses 2000 0000
through 3FFF FFFF hexadecimal) are I/O space addresses. Figure 4-1 illustrates the physical partitioning
of the VAXBI physical address space.
4.1.1

VAXBI 1/0 Address Space

As shown in Figure 4-2, the 512 megabyte VAXBI I/O address space is organized into several categories:
map window, multi-broadcast space, and node space. Only the VAXBI node space 1s used by the CIBCI
|

adapter.

The VAXBI node space (Figure 4-3) is organized into sixteen 8 kilobyte address blocks. The CIBCI
adapter hardware is assigned to one of these address blocks. This address block 1s referred to as the CIBCI
adapter node. It is accessed whenever a CIBCI adapter’s hardware or software register is referenced.
4.2
4.2.1

CIBCI ADAPTER NODE
Addressing

The address area of the CIBCI adapter node is calculated by taking a base address representing the
VAXBI 1/0 address space ( 2000 0000 hexadecimal) and adding 8K times the node ID, plus the offset
address of the device register. For simplicity, this calculated address is represented by bb+ whenever a
reference is made to any of the forthcoming register bit maps. Figure 4-4 illustrates the format structure
of a 30-bit 1/O address. Table 4-1 lists the starting addresses of the 16 VAXBI node spaces.

4-1

DURING THE C/A CYCLE ON VAXBI D<31:00>:

31 30 29

L’V_J\

LENGTH

30-BIT ADDRESS

)

0= MEMORY SPACE
1=1/0 SPACE
L

~—

r“

1/0 SPACE

~~~ 2000 0000
1

B12M BYTES

MEMORY SPACE

3FFF FFFF

1FFF FFFF

~
|

0000 0000

1 GIGABYTE ADDRESS SPACE
MKV85-2551

Figure 4-1

VAXBI Physical Address Space

RESERVED

MAP WINDOW

NODE PRIVATE
MULTI-BROADCAST
SPACE

VAXBI NODE SPACE
MKV 85-2552

Figure 4-2

VAXBI Physical I/O Address Space

| VAXBI NODE 15

RESERVED

MAP WINDOW

NODE PRIVATE

CIBCI ADAPTER NODE

MULTI-BROADCAST
SPACE

VAXBI NODE SPACE

T
J

TI U AXE! NODEO

VAXBI ADDRESS SPACE

MKV85-2550

VAXBI Node Space

Figure 4-3

DURING THE C/A CYCLE ON VAXBI D<31:00>:

3130.29

—

LENGTH

30-BIT ADDRESS

29 28

‘

17 16

13 12

NODE ID

/0 ADDRESS SPACE
Figure 4-4

ADDRESS WITHIN 8KBYTES OF NODE SPACE

30-Bit I/O Address Bit Map

4.2.2

Partitioning

As shown in Figure 4-5, the CIBCI node space is divided into two segments: VAXBI CSR space and user
CSR space. The VAXBI CSR space occupies the first 256 byte locations and is used by the VAXBI
protocol and VAXBI control logic of the CIBCI adapter hardware. The user CSR space occupies the
remaining locations of the address block. Only a portion of these addresses are used by the CIBCI adapter.
Reading or writing to an unused register address produces unpredictable results.
7~ [ vaxsi NODE 15
VAXB| NODE 14

RESERVED
MAP WINDOW

USER CSR SPACE

s
P

)

NODE PRIVATE

VAXBI ADDRESS SPACE

{

VAXBI CSR SPACE

)

{

VAXBI NODE SPACE

)

CIBCI NODE SPACE

MULTI-BROADCAST
SPACE

VAXBI

\«...

NODE 1

VAXBI NODE O
MKV85-2553

Figure 4-5

CIBCI Address Node Space

4-4

4.2.3

Registers

As shown in Figure 4-6, the first 256 bytes of the CIBCI node space are reserved for the VAXBI CSR
registers. VAXBI required registers and specific device registers fall into the category of VAXBI CSR
registers. The VAXBI required registers are used by all VAXBI nodes including the CI. The specific
device registers are special purpose VAXBI registers used to control the VAXBI device window area, and
V AXBI data transfer control and interrupt control. The remaining addresses of the CIBCI node space are
reserved for user CSR registers. The adapter registers fall into the category of user CSR registers and are
used for initializing and controlling the CIBCI adapter hardware. All of these registers are accessed using
longword addresses. (See Figure 4-7.)

NOTE

The CIBCI adapter hardware only issues longword
or quadword VAXBI bus transactions. It does NOT
respond to byte, word, or quadword VAXBI bus
transactions.

VAXBI NODE 15

CiB

T
E VAXB! NODE 0
~

VAXBI SPECIFIC

T
l

VAXBI NODE SPACE

USER CSR SPACE

CIBCI NODE SPACE

—

DEVICE REGISTER
VAXBI REQUIRED
REGISTERS

VAXBI CSR SPACE

001C

0014
0010

0000

MKV8b-2548

Figure 4-6

CIBCI Adapter Register Address Space

4-5

4.3

VAXBI REQUIRED REGISTERS

Figure 4-8 presents a more detailed diagram of the VAXBI required registers.

bb+00 ,j;
)

—VAXB!I REQUIRED REGISTERS

bb+1C
bb+20

:E;BIIC SPECIFIC DEVICE REGISTERS

bb+EC

bb+100

CONFIGURATION REGISTER

bb+110

PORT MAINTENANCE CONTROL/STATUS REGISTER

bb+114

MAINTENANCE ADDRESS REGISTER

bb+118

MAINTENANCE DATA REGISTER

bb+124

BICA ADDRESS REGISTER

bb+128

BICA COMMAND/BYTE MASK

bb+12C

DMA REGISTER FILE
MKV85-2555

Figure 4-7

VAXBI Interface Registers and Adapter Registers

bb+00

DEVICE TYPE REGISTER

bb+04

VAXBI CONTROL/STATUS REGISTER

bb+08

BUS ERROR REGISTER

bb+0C

ERROR INTERRUPT CONTROL REGISTER

bb+10

INTERRUPT DESTINATION REGISTER

bb+14

INTER-PROCESSOR INTERRUPT MASK REGISTER
MKV85-2556

Figure 4-8

4.3.1

VAXBI Required Registers

Device Type Register (DTR)

Address Offset = 00 Hexadecimal

The device type register, field bits <15:00>, is used to identify the type of node for use by the VMS
operating system’s device driver software. The device type assigned to the CIBCI adapter is 10B (hexadecimal). (See Figure 4-9.)

4-6

16 15

Device Type

bb+00

MKV 85-2540

Figure 4-9

4.3.2

Device Type Register Bit Map

VAXBI Control and Status Register (BICSR)

Address Offset = 04 Hexadecimal

The VAXBI control and status register contains control and status information. It also contains the BIIC
type and the node ID, and specifies the mode of arbitration. Figure 4-10 illustrates the register format. The
bit assignments are described in Table 4-2.

423

BIIC Type

bb+04

ARB

03
NODE ID

R/W

s
SES
INIT
BROKE
STS

SST
MBZ

UWP
HEIE

SEIE
MKV85-2539

Figure 4-10

VAXBI Control and Status Register Bit Map

4-7

vTahEe
42 VAXBE C@nimi ami Stams Regnster Bits;

~ Mnemonic

Indicates the type of BH‘C éhipau’sedFor example,' o

ITYPE

BIIC type

it should read 0000 0001 (hexademmal) for the

Lo fourth 1mplementatmn

"Indzcates thatoneor more of the hard error bltsm

Hard error

| the bus error reglster are set .

.. summary

o ‘Eniiia}:izs -

<13>

the bus error reglster are sei;

BRQKE

- Broke

The CIBCI has th yet completed 1ts 1mtzahzatlon
.
,
. ;lprocess

~ INIT
V

e Indmates that one or more Gf the soft error bltSin

Soft error summary : SES

Indwates that the BHC chlp has not successfufly

te completed 1ts internal self—test mutmes

- Indicates the BIIC chip has successfully passed 1ts

it Selftest status

~ mternal self test mmmes

- | i V;Instructs the BHC chip to begm 1ts mtemalself—testjfs _y‘fflf’f":

Start self-test

e ,.;,j'*routmes

A successful read lock transacnon has been

e ,completed and there has n@t yet been a SubSGQuent ‘ :"

o pending

~
.

Hard error
interrupt enable

. .",'."wrlte unlock command

HEIE

g@neratsd When
, Enables an mtermpt on error; to be

~ a hard error conditlon (nonrecaverable error);g o
o
o
o
o
; detected

, <96> i Soft error

. Enabies an mterrupt on errorm begeneratedwhenjj
a hard error condztmn(r@coverabls ermr)is

_interrupt enable

. _detected

| <05:04>

~ Arbitration control

~ ARB

. Spemfies the m@de Of arbltratmn m beusedbythe
.
- CIBCI adapter VMS sets ARB to z2 ero.
.,".Descrxptwne

.
~

,Reund mbm arbltratmn
.
Fixed-high arbitrateprwnty

Fixed-low arbitrate prmmy
>
o ;Disable arbztratisn o L

4-8

4.3.3

Bus Error Register (BER)

Address Offset = 08 Hexadecimal
NOTE

VMS clears all errors by writing a logical 1 to those

bits which contain a logical 1.

The bus error register provides bus error status information resulting from VAXBI bus or internal
loopback transactions. Figure 4-11 illustrates the register format. The bit assignments are described in
Table 4-3.

1615

bb+08

UPEN —I

MTCE
CTE

MPE

0403020100

R/W

\PE

CRD

—

NPE

ISE
TDF
IVE

CPE

SPE
RDS

RTO

STO
BTO
NEX
ICE

HARD ERROR BITS — <29:16>
SOFT ERROR BITS — <02:00>
STATUS BIT - <03>
MKV85-2538

Figure 4-11

Bus Error Register Bit Map

. nememc

. wer.

f;fThe BIIC data received from theVAXBI doesnot

terror. CIE ..

Th@ CIBCE detected a deas&erteé state on theVA}:’[V».V

match the transmmeddata 0f theVA.XBI mastc—:r

. . N.ARB VAXBI BSY or VAX’QI‘»}CNF <.2 .O>
signal, in a cyc}e inWthh n: wasattemptzn1o asse
e

SPE

vthe szgnal

“i',
The CEBCIfldapt@f did notcarre
o an .
tion ‘ cflyrecexve

o mterrupt vectorcenfzrma

,’

Apamty
error

was detec
ted

on th
e

bus

,,durmg a non~arb1trat10n tmnsactlon CYCI’""’ -

,!,;.»:.;'pantyerror durmgthedata »tran

- -»;'_Ctntamsthe: RDScade

v fcre than4096» cmsecutwe retry cycles w

. ;f;_*_'»executed
for agwentransactmn

» ,

The stali code was asserted for greater than 27

4-10

4.3.4

Error Interrupt Control Register (EICR)

Address Offset = 0C Hexadecimal

The error interrupt control register controls the operation of the interrupts initiated by a BIIC detected bus
error (which sets a bit in the bus error register) or by setting the force bit in this register. An error interrupt
request is the logical OR of all the BER register bits with the force bit and error interrupt enable bits set in
the VAXBI control and status register. This register is set up by the software if the SEIE bit is set in the
VAXBI control and status register.

Figure 4-12 illustrates the register format. The bit assignments are described in Table 4-4.

24 23

16 15

LEVEL

bb+0C

13
VECTOR

INTRAB -J
INTRAC

SENT
FORCE
MKV86-1374

Figure 4-12

Error Interrupt Control Register Bit Map

Tfibfi@ 4-4 f Ei‘mf , Mtfei'm?t 'i??CQaMWE Register Bits
<z4> ~

Comment/Function

Mnemonic

~ Name
Interrupt abort

A NOACK or ILLEGAL confirmafion was

INTRAB

| rccewed for an initiated INTR semmand ané

| subsequemly the INTR commandwas abort@d

t was =23 »imt’:rmptmmpleteg__ - INTRAC e The vecmr for a BAXBE ermr mtermp
command*vf'»'_

iNTR
@SSquy transmitted or an rfiglsterhas
S ,SUCC
been
tms
@f
mntm}
the
sen*: under

<2§> - hiérfrum Sfiflt j

’ INTR SENT

. Foreeinterrupt.

INTR FORCE

<19:16> Interrupt level
o
T

An ENTR cgmmand has been successfufly ssnte

;;and an IDENTAR''vcycleisexpectfid

LEVEL

‘-’._VM'F@rces an ermr mtermpt requestin ‘thfisame

_manner as anybus error mgzswr ’bit @x@@p‘tthai«" .,

G the request is notquahfied byth@ HEEE and
.
.
"lSHE mg .

ey Specxfles the level(s) at thh ENTR commands ,
under control of this register are transmitt@d
over the VAXBI bus. Also, theCIBCI usesthis
,
levelfield to determinewhether 1t wfli rsspmd

02>

4.3.5

Neetor

o+ ...

toan EDENT cc}mmand

VECTOR

Interrupt Destination Register (IDR)

Address Offset = 10 Hexadecimal

The IDR indicates which nodes on the VAXBI are to be targeted by interrupt commands. The destination
is sent out during the INTR command andis monitored by all nodes to determine whether to respond.
Figure 4-13 illustrates the register format.

NOTE

IDR is loaded by VMS with the decoded ID information of the system interrupt fielding node.

4.3.6 Inter-Processor Interrupt Mask Register (IPIMR)
Address Offset = 14 Hexadecimal

The IPIMR indicates which nodes are permitted to send IPINTRs to this CIBCI node. If a bit in the
IPINTR mask field is a one, IPINTRs directed at this node from the corresponding node will cause
selection. If the bitis a zero, IPINTRs from that node do not cause selection. Figure 4-14 illustrates the
register format.

4-12

16 15

Interrupt Destination

bb+10|

R/W

MKV85-2536

Figure 4-13

bb+14

Interrupt Destination Register Bit Map

IPINTR MASK
MKV85-2535

Figure 4-14

Inter-Processor Interrupt Mask Register Bit Map
NOTE

The CIBCI adapter does not use inter-processor
interrupts. Therefore, VMS clears the interrupt
mask field so that an inter-processor interrupt is not
acknowledged.

4.4

BIIC SPECIFIC DEVICE REGISTERS

Figure 4-15 presents a more detailed diagram of the VAXBI specific device registers.

bb+28
bb+40

CONTROL REGISTER

USER INTERRUPT CONTROL REGISTER

MKV85-2534

Figure 4-15

VAXBI Specific Device Registers

4-13

4.4.1

BCI Control Register (BCICR)

Address Offset = 28 Hexadecimal

The BCI control register enables various functions between the BIIC chip and the user’s port to occur.
Figure 4-16 illustrates the register format. The bit assignments are described in Table 4-5.
08 07

1615

0302

bb+28

BURSTEN
IPINTR/STOP FORCE
BSEN
BDCSTEN

STOPEN
RSVDEN

IDENTEN
INVALEN

WINVALEN

UCSREN
BICSREN

INTREN

IPINTREN
PNXTEN

RTOEVEN
MKV85-2533

Figure 4-16

BCI Control Register Bit Map

nemonic

Comment/Function

~ Clearebyd VMS fornormal operation.

4-14

Mnemonic

normal operation to allow
~ Set by VMS for SEL
L and the appropriate

,,Stopenable S

assertion of BCI
SC<02:00> code foflewmg the receipt of a
INIT command or lwpba@k request direm@d
at this CEBCE nod@

<l1> Wentification enable

IDENTEN

i Cleared by VMS for normai

Op@ration;

. "Ci@ared byVMS f@r‘ mrmal op@mwm.

Cieamd by VMS f@r mrmafiGp@rafion'y{i

Wme
mvahdaté
enableWIN VALEN . , "C}:@ar@d by ‘VMS f()r nm‘ma}; Qp@fatmnfi_. .

‘f:‘::UserCSR spaceenable" |

UCSREN e

| Set by VMS f@r mrmai opemtmn m aflcw .
assertion of BCI SEL L and the appropriate
SC<02:00> codewhen the user C‘SR space -

.;Tsp'aéé"eyné;b‘le

-Cfieared by VM% fflr normafi Qp@mtmn

~ BICSREN

'fi;,»“_flnterruptenable =
<()S>

‘Inter-pmcessar .

is accessed fmm the VAXBE

‘Cleared by VMS for normal Qpemtmn

_ IPINTREN

‘ Cifiafmd by VMS 'fOF mrmal ofperafion,_ e

.ln
ter
rup
t
en
ab
le
|

<()4> V"‘;'v”";"f’PipelmeNXT @nable -

if?fi$§ 7 RTOEfifmmme~'

PNXTEN
~ RTOEVEN

Set by VMS f«:}r normai @peratmn m @nabie

- the output RTO codein place of the RCR
event code f@fi@‘wmg ‘the reoccurrence of a
’retry txmmut

4.4.2

User Interrupt Control Register (UICR)

Address Offset = 40 Hexadecimal

The UICR controls the operation of interrupts initiated by assertion of the BCI INT<07:04> L lines, or by
setting any of the force bits. The operation of the BCI INT<07:04> L lines and the force bits are
essentially identical. In the following descriptions, interrupt request indicates BCI INT<07:04> or force
bits set. The CI adapter asserts only INT<07:04>, but dlagnquCS may set the force bits. Figure 4-17
illustrates the register format. The bit assignments are describedin Table 4-6.

4-15

31
bb+40

R/W

VECTOR

FORCE

SENT

INTRAB | INTRAC

02 01 00

16 15 14 13

2019

24 23

28 27

EX VECTOR ——J
MKV86-1367

Figure 4-17

User Interrupt Control Register Bit Map

L A status field correspondmg to the four mterwpt
f'f,j,f.f‘ij,;,f:':7',‘515"‘;.3if:levels An interruptabort bitis set if an INTR

,,_'&command sent under cantml of this regxster 1S

. 'i‘;v-};u;,f»’;;,",-ffabort@

d because a NACK or ELLEG
AL

f»‘:.,:,,}5‘¢5,,,.;conf1rmatmn codewas recewed

v';thefffammtermpt ieveisVMS ciems these bais (af set}*

=0704> Interruptcomplfite

,A"statuys field cOrreSpondifigto the four ifitermpt

INTRC

~levels. An interrupt complete bitis set when the

~ vector for an m‘terrupt has been successfufly
'transmitted or if an INT

R command sent undsrfflf’"y

o ~control of this regzster is aborted because a

,’NOACK or ILLEGAL confirmaflon cade was

{.;,<2320>f’f;.';.;‘f;., nterruptsent

SENT

was succ:sssfully sem and an
correspondmg level
es
b

. IDEN

T ARB cycleis

19:16: Frcelnterrupt

<1302> Vecter

‘

VECTOR

expected.

. __Cleared by VMS for normal Operatmn

‘,“','Contams the vectordurmg user mterrupt

~ sequences. The vector is transmitted when the S
CIBCI adapter wins an IDENT ARE cycle on

4-16

4.5

BIIC USER PORT REGISTERS

The BIIC user port registers consist of those registers which reside on the T-series modules of the CIBCI
adapter option. These registers consist of:
1.

One (1) configuration register

One (1) address register

One (1) byte mask/command register

Four (4) register file registers

Figure 4-18 shows the location of BIIC user port registers, part of the adapter registers, in the CIBCI
adapter node space.
NOTE

Writing to BIIC user port registers under system
operation may erase valid data for the operation in
progress.

bb+100

CONFIGURATION REGISTER

bb+124

ADDRESS REGISTER

bb+128

COMMAND/BYTE MASK REGISTER

bb+12C

DIRECT MEMORY ACCESS REGISTER FILE
MKV85-2531

Figure 4-18

BIIC User Port Registers

4-17

4.5.1

BCIA Configuration Register (CNFGR)

Address Offset = 100 Hexadecimal

adapter
The CNFGR contains the port status bits, error bits, and adapter code bits for the CIBCI
4-7.

hardware. Figure 4-19 illustrates the register format. Each register bit is describedin Table
23 22

1615

2019

BCMR FOR READS

bb+100

R/W

NO CIPA

CIPA DCLO
DIAG

PUP
PDN

BBE
BIPE

BAPE

CPPE
MKV86-1372

Figure 4-19
Med]

BICA Configuration Register Bit Map

AC@nfigumtmn Register Bits

- Name

<31>

CIPA BUS

~ parity error

Mnemonic

C@mmem/fiuncfi@n b

CPPE

A parity error was detected on efiher the CEPA

<30>

- <29>
<28>.
|

data) was detected on the BICA data path.Thls
mterruptportwaassert CEPA BUS ERRR

VAXBI BSY error

PGW@T] dflwfl

A data path parlty error (VAXBEaddre&s 01’*

BAPE

VAXEE parity error
|

interrupt port will assert CIPA BUS ER_';’RL

which sets the MTE bitin the CEPA"i and
- causes an mterrupton the ’VAX ,

BIC Adapter
parity error
Gl

bus, on the BICA, or in the BIIC chxp The

" Represems the logicai OR Qf event cofesvtha,t

BIPE

drive CIPA BUS ERROR. This mtfirmpt_ pm"t

WIH assert CEPA BUS ERRR’?

BBE

| PDN

The VAXBI hardwamd@tected.
;md@ This mt@rrum port wfl} ass

‘

ERROR

| Th@ CEBCE adapt@r hardwa,r@is powermzldewn L

0
4-18

OPADCID .

s MalfltfinamfiGO .

CIBADOID

MAINTGO

!'Imtlates
aDMA transfer wl

mamtenance m

. ,‘1;’_’_ 5<19m> |

ECMR

to Bfl;s <15”:9
|
ertes

CIICEadapterhardware.

4-19

> no eltect
.

on the

4.5.2

BICA Address Register (BCAR)

Address Offset = 124 Hexadecimal

initiated VAXBI
The BCAR contains the address to be driven onto the VAXBI bus for CIPA hardware
e control using
macrocod
under
or
bus
CIPA
the
transactions. It is loaded under microcode control using
bus is only
CIPA
the
because
necessary
are
register
the VAXBI protocol. The HI and LO portions of this
format.
register
the
illustrates
4-20
Figure
time.
a
16 bits wide and, therefore, can load only 16 bits at
Each register bit is described in Table 4-8.

NOTE

VMS will not normally write into this register.
Reading and writing to location bb+124 is treated
differently. This difference affects diagnostics and
NOT the VMS port driver software.
16 15

ADDRESS LO REGISTER

ADDRESS HI REGISTER

bb+124
g

LENGTH

28 27

bb+124

CMD

16 15

ADDRESS HI REGISTER

ADDRESS LO REGISTER

WO
MKV85-2529

Figure 4-20

BICA Address Register Bit Map

4-20

hardware:

<3128> - ‘ _ C@mmmd

o REA n MASK
.
. WRITEMASK
~ INTLK READ MASK
~ INTLK WRITE MASK

, EXTENEDREAD MASK

EXTENED WRH‘E MASK

i ‘Addr‘ess HI
AddreSSLO

Léngth

| Spemfles the hlgh ord@raddress bzts <2918> of the ;

ADRS HI

DMA. transaction over the VAXBE bus

~ ADRS LO

SIZE

. Qpemfi@s th@ Eew ord@faddress b1ts <1702> Qf th@ :
DMA transac:tmn over the VAXBI bus VAXBE

e 00> of a DMA transaction are aiways cleared
.

C@ntams the Eength of th@ VAXBI bus transacmon o
e
.
~
o in bytes

f<;32‘1:39>5

ngm '_ s
: Reserved

- Longword (4 bthS)

- Quadword(8 byt€S)

,cta.werd (16byt@s}

Address .

ADRS

CHI/LO

Contains the PhYchaI memmy addressof
CMD/ADDR ‘VAXBK tmnsfcr

4-21

theel

4.5.3

BICA Command/Byte Mask Register (BCMR)

Address Offset = 128 Hexadecimal

The byte mask portion of BCMR specifies which byte(s) of data are written during CIPA hardware
initiated DMA write transactions. Figure 4-21 illustrates the register format. Each register bit is described
in Table 4-9.

NOTE

Reading and writing to BCMR is treated differently.
This difference affects the diagnostics and NOT the
VMS port driver software.

0403

08 07

MASK1 | MASKO | WO

bb+128|

10 09

14 13

CMD

bb+128

06 05

MASKO

MASK1

00
(0|0}

LENGTH
MKV85-2528

Figure 4-21

BICA Command/Byte Mask Register Bit Map

MASKO

Specifies

which byte(s) are to be

macrocodvia
e the

. <i514> Length SIZE

written

DMAwrite transact
longword of a CIPA
be written by the CIPA hardware micr
VAXBL

how many bytes of data ar

Specifies

4-22

C@mman@ e

<i3§@>

patkREy

. UNLOCK WRITE MASK
WRITEMASKE

06> Maskl

MASKI Same bits written into tho write portion of BCMRR bits

02> Mask0

MASKO

4.5.4

‘Same bits written into the write portion of B MR
e

DMA Register File (DMAF)

Address Offset = 12C Hexadecimal

The DMAF is a 4 by 32 bit (longword) dual port RAM which holds an octaword’s worth of data for a
CIPA initiated write. The octaword storage allows overlapped quadword transactions for higher performance. Reading and writing are completely independent operations. As such, it is important to keep track of
where the read address pointer and write address pointer are pointing.

The register is divided into high and low so that the 16-bit CIPA bus can write this 32-bit register. Figure
4-22 illustrates the register format.

NOTE

VMS will not normally write into this register.
4.6

CIPA REGISTERS

The CIPA registers consist of those registers which reside on the [-series modules within the CIPA
cabinet. Figure 4-23 is a detailed illustration of the CIBCI adapter registers.
NOTE

Both the CIPA bus and CIPA hardware must be in
working order to read and write these registers.
Except as noted, the CIPA hardware must be in the
uninitialized or uninitialized/maintenance state to
read or write to these registers.

4-23

16 15

bb+12C

FIRST LONGWORD HI

FIRST LONGWORD LO

bb+12C

SECOND LONGWORD Hl

SECOND LONGWORD LO

bb+12C

THIRD LONGWORD HI

THIRD LONGWORD LO

bb+12C

FOURTH LONGWORD Hi

FOURTH LONGWORD LO

MKV85-2557

Figure 4-22

DMA Register File Bit Map

bb+110

PORT MAINTENANCE CONTROL/STATUS REGISTER

bb+114

MAINTENANCE ADDRESS REGISTER

bb+900

PORT STATUS REGISTER

bb+904

PORT COMMAND QUEUE 0 CONTROL REGISTER

bb+908

PORT QUEUE BLOCK BASE REGISTER

bb+90C

PORT COMMAND QUEUE 1 CONTROL REGISTER

bb+910

PORT COMMAND QUEUE 2 CONTROL REGISTER

bb+914

PORT COMMAND QUEUE 3 CONTROL REGISTER

bb+918

PORT STATUS RELEASE CONTROL REGISTER

bb+91C

PORT ENABLE CONTROL REGISTER

bb+920

PORT DISABLE CONTROL REGISTER

bb+924

PORT INITIALIZE CONTROL REGISTER

bb+928

PORT D»ATAGRAM FREE QUEUE CONTROL REGISTER

bb+92C

PORT MESSAGE FREE QUEUE CONTROL REGISTER

bb+930

PORT MAINTENANCE TIMER CONTROL REGISTER

bb+934

PORT MAINTENANCE TIMER EXPIRATION CONTROL REGISTER

bb+938

PORT FAILING ADDRESS REGISTER

bb+93C

PORT ERROR STATUS REGISTER

bb+940

PORT PARAMETER REGISTER

MKV85-2558

Figure 4-23

CIPA Adapter Registers

4-24

4.6.1

Port Maintenance Control/Status Register (PMCSR)

Address Offset = 110 Hexadecimal

The PMCSR contains CIPA hardware error flags, interrupt, and CI bus initialization control bits. Figure
4-24 illustrates the register format. Each register bit is described in Table 4-10.
NOTE

Bits 14:08 cause the MTE bit in the port status
register (PSR) to set, which generates an interrupt

on the VAXBI and leaves the port in an uninitialized
state.

16 15

bb+110

—

CSPE
LSPE
RBPE
XMPE
CBPE
OPE
XBPE
UNIN
PSA
RSVD

MIF

MIE
MTD
MKV86-1375

Figure 4-24

Port Maintenance Control/Status Register Bit Map

4-25

Comment/Function

Mnemonic

Bt Name

A pamy error was detected readmg PRM (}ruR

u‘f:'»!.’f,fCQntr{)}smre . CSPE
,;v»,;'.-_f?amty
error

,T_

'centml

"Jliz.Transmlt buff@r o

'{‘,A panty error was datectsd whfie readmgth""

XMPE

S A parity error wasydst@med “whx‘levtheimk 'mfldui@

L
o

'iecsai stor@or ths ertual cwcmt degcnptm“mble

parif@y fifi‘Of '}~’ e

store.

'}f@ver thfi: CH’A Bus(fmm BECA toCEPA)

OPE

Aparity

error was detea‘t@don the

CPmodulfi

,_ _;¢,v,v'__whfle iransferrmg da‘ta from CEPA toEICf:'

while the e
detected
r wasm@dul
ty errostore
A
e (EP%) was unleadmg theC}vz.:,»‘;_@';::,»;:»
control
andpari

. g‘ibus transmit buffer
. Unimtialized . UNIN .
e

;,The CEBCI18 in. the ummtxahzad statfi The

-mxcmcadeis not running and the port will not

- respond to CI bus commands. Et 1S setby HINET!I“
: SSTin the BECSR orMTEin %he PSR

06>

PSA
ngrammable stamngadéress .

| i18 cieared bywntmg a 1 to thePIC bit inthe

port initialize control regzster (PECR) or afiefabmt

,.'tlmeoutClcarmg UNIN starts the mmmmde

Wh@n set, mstmcts thfi: mwmmdeto start at t |
address specifiedin the MADR, afterthePIC blt (

thfi PICR regzsters set to a 1 or afiera bmt -

VV\‘»Whenclear mstructs the mlcmmi‘emstart vatz
PROM looanonzero.

4-26

.
|

","

f,f

i‘f

cau

smg
an
mt
er
mp
t

. Whe
ncle

ar the bcotan‘d

i\
4.6.2

sa»‘

;:'*""';'7,Thisbitis not used by the‘C BC Ipertand }Sf@ad

Maintenance Address Register (MADR)

Address Offset = 114 Hexadecimal

VMS uses this register to load CIPA control store microcode. The address loaded into the MADRis used
as a pointer address to access control store. Control store is organized as 3K by 48 bits under the control of
the CIPA hardware, in the initialized state. In the uninitialized state, the control store appears as 6K worth
of addresses each containing 32 bits of data. The MADR is only effective when the CIPA is in the
uninitialized state.

Figure 4-25 is a diagram of control store addresses. Each register bit is described in Table 4-11.
NOTE

Register contents are valid only when the port is in
the uninitialized state. MADR may be used as the
start of the CIPA control store microcode address if
the microcode is started with PMCSR PSA bit=1.
Also, the control store PROM area is read only with
the exception of microcode bit 47 which is the synchronous bit that allows tracking of which PROM
locations are used.

4-27

R/W

ADDRESS

bb+114 |

00
ADDR=0FFF

ADDR=1FFF

NOT

USED

ADDR=1C00

ADDR=0CO00

ADDR=1BFF

ADDR=0BFF

RAM

ADDR=1400

ADDR=0400

ADDR=13FF

ADDR=03FF
PROM

ADDR=0000

ADDR=1000

MKV85-2560

Figure 4-25

Maintenance Address Register Bit Map

- :Ia:bifex 4—?1 ; M.@imeflamge Address Register Bits
~

. <12>

Mnemonic

.e o

Comment/Function

Selectsa segmentfthe control store word asf@flows

0= seleéts microcode bItS<31OO>—"‘»

ol se!ects mlcrocade bitS <4732> o

<1 110>

AMAlO "

L | . Selects a IK bank w1th1n the control store as f@llews

L AlL . ,AI-O_'_; Bank Sefiemd
e 0 (OOO~3FFPR'M'mmrocode)
1 (400-7FF RAM mlcmcode)

4-28

4.6.3

Maintenance Data Register (MDATR)

Address Offset = 118 Hexadecimal

VMS uses this register to load CIPA control store microcode. The data in MDATR is loaded into CIPA
control store locations specified in the previous description of MADR. Again, only microcode bit 47 in the
PROM area can be written. Control store bits 47:32 appear on MDATR bits 15:00 respectively for a read,
and likewise contain the data for a write. Figure 4-26 illustrates the register format.
NOTE

DATA

bb+118

R/W
MKV85-2562

Figure 4-26
4.6.4

Maintenance Data Register Bit Map

Port Status Register (PSR)

Address Offset = 900 Hexadecimal

The PSR contains the status flags that indicate the cause of a port generated interrupt. The PSR contents
are fixed once the port issues an interrupt, and are not changed until the VMS port driver software releases
PSR by writing the PSRC bit of the PSRCR to a 1. Therefore, it is valid only during that interval. Figure
4-27 illustrates the register format. The bit assignments are described in Table 4-12.
NOTE

This register is used by the VMS port driver
software and is valid only when the operational port
microcode is loaded and running.

4.6.5

Port Queue Block Base Register (PQBBR)

Address Offset = 904 Hexadecimal

This register contains the physical address of the base of the port queue block. Figure 4-28 illustrates the
register format.

NOTE

The PQBBR is a read/write register, however, writing to the PQBBR is permitted only when the port is
in the disabled or disabled/maintenance state.

4-29

0O
R/W

bb+900

MISC

—J

MSE
DSE

PIC
PDC

MFQE
RQA
MKV85-2563

Figure 4-27

Port Status Register Bit Map

. 07> - Miscellancous error.

Samty timer expiration

4-30

The mxcrocode halts

00>is mvahd)
- ,;fi._-<\06

3 An interruptisgencrated on the BI(PS?_.;

1 ucture, for example;
°

Queuc entry

Page table

~ Values out of range

Zem bl‘ts thatare not zem _,

'Th@CE.CI perthas complcte"fl litializ

the localsmre
Vzrtuaimrcmt

descmpt.r

and mternal data structures

'yTheCIBCIpOrt zs in tha

o disabled/mamtenanceordisa
bied state

- Thean cmgrthasstppedresmndmg to:
Encammg CI transmzssmns (exoept
mamtenance class 1f enable{);
.

-The port is in thedxsabled Gr

o dlsabled/ mamtemnce state

queuefimmy

| MFQE o

Thc CIBCI port has attempt@d to remove a
’, "_entry
from the message free fi}_ufiue
and fo_;,

;The CIBCI
porthas mserted mto an cnt’

> Q1 ueavaflab}.e
-

an empty respflnse queue

31 30.29
bb+904

09 08

PQB BASE <29:09>
MKV85-2564

Figure 4-28

Port Queue Block Base Register Bit Map

4-31

4.6.6

Port Command Queue 0 Control Register (PCQOCR)

Address Offset = 908 Hexadecimal

After the VMS port driver software inserts one or more entries 1nto the empty command queue O, it will
write a 1 into bit 00 of the PCQOCR to initiate port processing of command queue 0. Figure 4-29
illustrates the register format.

NOTE

The port processor ignores PCQOCR if it is in the
uninitialized /maintenance, disabled/maintenance,
uninitialized, or disabled state.

bb+908

MKV85-2565

Figure 4-29

4.6.7

Port Command Queue 0 Control Register Bit Map

Port Command Queue 1 Control Register (PCQ1CR)

Address Offset = 90C Hexadecimal

After the VMS port driver software inserts one or more entries into the empty command queue 1, it will
writea 1 into bit 00 of PCQICR to initiate port processing of command queue 1. Figure 4-30 illustrates
the register format.

NOTE

The port processor ignores PCQICR if it is in the
uninitialized/maintenance, disabled/maintenance,
uninitialized, or disabled state.

MKV85-2566

Figure 4-30

Port Command Queue 1 Control Register Bit Map

4-32

4.6.8

Port Command Queue 2 Control Register (PCQ2CR)

Address Offset = 910 Hexadecimal

After the VMS port driver software inserts one or more entries into the empty command queue 0, it will
write a | into bit 00 of the PCQ2CR to initiate port processing of command queue 2. Figure 4-31
illustrates the register format.
NOTE
The port processor ignores PCQ2CR if it is in the
uninitialized /maintenance, disabled/maintenance,
uninitialized, or disabled state.

bb+910 .

MKV85-0857

Figure 4-31
4.6.9

Port Command Queue 2 Control Register Bit Map

Port Command Queue 3 Control Register (PCQ3CR)

Address Offset = 914 Hexadecimal

After the VMS port driver software inserts one or more entries into the empty command queue 0, it will
write a 1 into bit 00 of the PCQ3CR to initiate port processing of command queue 3. Figure 4-32
illustrates the register format.
NOTE

The port processor ignores PCQ3CR if it is in the
uninitialized /maintenance, disabled/maintenance,
uninitialized, or disabled state.

bb+314

MKV85-0798

Figure 4-32

Port Command Queue 3 Control Register Bit Map

4-33

4.6.10

Port Status Release Control Register (PSRCR)

Address Offset = 918 Hexadecimal

After the VMS port driver software has received the interrupt issued by the port processor, and has read
the PSR, CNFGR, and BER registers, it returns control of the PSR (port processor is able to write PSR)
back to the port processor by writing a 1 to the PSRC bit. Figure 4-33 illustrates the register format.
NOTE

The port processor ignores PSRCR if it is in the
uninitialized /maintenance, disabled/maintenance,
uninitialized, or disabled state.

bb+918|

MKV85-2561

Figure 4-33
4.6.11

Port Status Release Control Register Bit Map

Port Enable Control Register (PECR)

Address Offset = 91C Hexadecimal

The VMS port driver software places the port processor in the enabled or enabled/maintenance state by
writing a 1 into bit 00 of the PECR. Figure 4-34 illustrates the register format.
NOTE

The port processor ignores PECR if it is in the
enabled, uninitialized, uninitialized/maintenance, or
enabled /maintenance state.

bb+91C

MKV 85-0799

Figure 4-34

Port Enable Control Register Bit Map

4-34

4.6.12

Port Disable Control Register (PDCR)

Address Offset = 920 Hexadecimal

The VMS port driver software places the port processor in the disabled or disabled/maintenance state by
writing a 1 into bit 00 of the PDCR. When the port processor is disabled (the microcode having completed
a disable sequence), it requests an interrupt by setting the PDC bit set in the PSR. Figure 4-35 illustrates
the register format.

|
NOTE
The port processor ignores PDCR if it is in the
uninitialized /maintenance, disabled/maintenance,
uninitialized, or disabled state.

bb+920|

MKV 85-0800

Figure 4-35
4.6.13

Port Disable Control Register Bit Map

Port Initialize Control Register (PICR)

Address Offset = 924 Hexadecimal

The VMS port driver software places the port processor in the initialized state by writing a 1 into bit 00 of
the PICR. When the port processor completes initialization, it sets the PIC bit in the PSR, requests an
interrupt, and enters the disabled or disabled/maintenance state. Figure 4-36 illustrates the register
format.

NOTE

The port processor ignores PICR if it is in the disabled/maintenance or disabled state. The port
processor goes to the disabled/maintenance or disabled state if it looses processing status.

bb+924

MKV85-0855

Figure 4-36

Port Initialize Control Register Bit Map

4-35

4.6.14

Port Datagram Free Queue Control Register (PDFQCR)

Address Offset = 928 Hexadecimal

The VMS port driver software sets the DFQC bit in PDFQCR if the datagram free queue is empty. Figure
4-37 illustrates the register format.

NOTE

The port processor ignores PDFQCR if it is in the
uninitialize /maintenance, disabled/maintenance,
uninitialized, or disabled state.

bb+928|

MKV85-0856

Figure 4-37

4.6.15

Port Datagram Free Queue Control Register Bit Map

Port Message Free Queue Control Register (PMFQCR)

Address Offset = 92C Hexadecimal

The VMS port driver software sets the MFQC bit in PMFQCR if the message free queue is empty. Figure
4-38 illustrates the register format.

NOTE

The port processor ignores PMFQCR if it is in the
uninitialized, disabled, uninitialized/maintenance, or
disabled/maintenance state.

bb+92C

MKV85-0853

Figure 4-38

Port Message Free Queue Control Register Bit Map

4-36

4.6.16

Port Maintenance Timer Control Register (PMTCR)

Address Offset = 930 Hexadecimal

The PMTCR allows the VMS port driver software to control the expiration time of the boot and sanity
timers. Both timers are reset to their initial value whenever a 1 is written into bit 00 of the PMTCR. If
PMTCR is not written before the expiration time, then the port will request an SE interrupt (SE bit of the
PSR is set) and enter the uninitialized/maintenance state. Figure 4-39 illustrates the register format.
NOTE

PMTCR is ignored if the maintenance timers are
disabled through either the MTD bit being set in the
PMCSR, or the port entering the uninitialized state.

bb+930|

MKV85-0854

Figure 4-39

Port Maintenance Control Register Bit Map

4.6.17 Port Maintenance Timer Expiration Control Register (PMTECR)
Address Offset = 934 Hexadecimal

The VMS port driver software forces a maintenance timer expiration interrupt by setting bit 00 of the
PMTECR. Figure 4-40 illustrates the register format.

NOTE

PMTECR can be written only when the MTTD bit in
PMCSR is clear, and the port is in the enabled,
enabled /maintenance, disabled/maintenance, or disabled state.

01 00

bb+934
MTEC
MKV85-0850

Figure 4-40 Port Maintenance Timer Expiration Control Register Bit Map

4-37

4.6.18

Port Failing Address Register (PFAR)

Address Offset = 938 Hexadecimal

The PFAR contains the memory address at which a failure occurred after a memory system error (MSE)

or data structure error (DSE) interrupt, or after a response with a buffer memory system error status
(type=6 in the response status field of VMS issued port commands). The failing address may be the exact
address, an address in the same page as the failing address, or, in the case of DSE interrupts, an address in
some part of the data structure.

Figure 4-41 illustrates the register format. The bit assignments are described in Table 4-13.
NOTE

The PFAR is used by the VMS port driver software
and is valid only when the operational port
microcode is loaded and running.

The contents of the PFAR register are only valid when the MSE or DSE bit of the PSR is set (first error
logged), or there is a response with a buffer memory system error (last error logged).

31
bb+938

FAILING ADDRESS
MKV85-0851

Figure 4-41

Port Failing Address Register Bit Map

4-38

4.6.19

Port Error Status Register (PESR)

Address Offset = 93C Hexadecimal

The PESR indicates the type of error which resulted from a DSE interrupt (DSE bit in the PSR being set).
Figure 4-42 illustrates the register format. The bit assignments are described in Table 4-14.
NOTE

This register is used by the VMS port driver
software and is valid only when the operational port
microcode is loaded and running, and only after a
DSE interrupt has occurred.

ERROR CODES

bb+93C

R/W
MKV85-0852

Figure 4-42

Port Error Status Register Bit Map

4-39

4.6.20

Port Parameter Register (PPR)

Address Offset = 940 Hexadecimal

The PPR contains the port number and other port parameters. It is set up by the CIPA control store
microcode during the port initialization process and is valid in any state except the uninitialized state.
Figure 4-43 illustrates the register format. The bit assignments are described in Table 4-15.
NOTE

PPR is a read/write register but writing to the PPR
will destroy the port state with unpredictable results.
This register is used by the VMS port driver
software and is valid only when the operational port
microcode is loaded and runmning.

3130

2827

1615

LENGTH

R/W

MKV85-2554

Figure 4-43

Port Parameter Register Bit Map

. When clear mdxcatesthat the:reisa

allowed on theCI.When set indica

o204 nodeswailowed on the system

?ndmatesfi?fithe
mzaoft" ‘;‘*flefinternai. bu
anddatatransfers. It is preset to 1016,

4-40

APPENDIX A
CI TERMINATION

NOTE

Only one unterminated pair of cables are permitted
per data path on the CI bus. The above rule allows
for the following:

Power removal and restoration for an individual node.

Removal of the L0100 module while the node is
fully cabled.

Disconnection of any or all cables at any point
between a node backplane and the star coupler.

The procedures listed below will not disrupt the operation of properly configured nodes on the same data
path in an on-line situation.

When testing the CI, the L0100 module should always have proper termination. This implies using

either the star coupler or proper attentuator pads for termination.

If using the star coupler, be aware that diagnostics do not expect collisions on the CL. Diagnostic

errors can occur if the node being tested is attached to a “live” star coupler.

The attentuator pad may be used either at the bulkhead panel assembly of the Cl port with
modularity cables or at the end of the CI cables at the star coupler end.

A-1

APPENDIX B

CI BACKPLANE JUMPER

B.1

BOOT TIMER PARAMETERS

Time
Sec

0000

0100

0200

0300
0400

0500

IN
IN

0600

0700

0800
0900

1000

1100

1200

1300
1400

1500

B.2

EXTENDED HEADER/TRAILER (W5)

= Extended header/trailer
Out = Normal header/trailer
In

B.3

ALTER DELTA TIME (W6)

= Long delta time
In
Out = Short delta time

B.4

DISABLE ARBITRATION (W7)

= Disable normal arbitration
Out = Allow normal arbitration
In

B.5

EXTENDED ACKNOWLEDGEMENT TIMEOUT (W8)

= Long timeout
In
Out = Short timeout
NOTE

Jumper W8 must be in whenever jumper W5 is in.

B-2