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EK-CAB16-TM-002

December 1989

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Document:	CXA16/CXB16 Technical Manual
Order Number:	EK-CAB16-TM
Revision:	002
Pages:	156
Original Filename:

OCR Text

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EK-CAB16-TM-002

CXA16/CXB16
Technical Manual

Prepared by Educational Services

of
Digital Equipment Corporation

1st Edition, December 1986
2nd Edition, September 1989

* Digital Equipment Corporation i 986, 1989
All Rights Reserved

The information in this document is subject to change without notice and should
not be construed as a commitment by Digital Equipment Corporation. Digital

Equipment Corporation assumes no responsibility for any errors that may appear
in this document.

Printed in U.S.A.

Book

production

was

done

Educational

Services

Development and

Publishing in Merrimack, NH.

The following are trademarks of Digital Equipment Corporation:

DEC

DIBOL

Scholar

DECmate

MASSBUS

ULTRIX

DECset

PDP

UNIBUS

DECspell

P/OS

VAX

DECsystem-10

Professional

VMS

DECSYSTEM-20

Rainbow

DECwrter

aSx

dilglilt]al|

CONTENTS

PREFACE

C e N
e

General DeSCriptiON cececssessesscsssassancsssssnsssnsss
1
Self"TeSt FaCility....................e.-.......-.-..

1.2

DiagnostiC

ProgramsS

.c.ceeesessessccssacsnssssscnsensses

1.3
Preventing Data LOSS .eccosscssosscvsssescsssscsscscscna
2
Physical DesCription ceececeeececcccsscsacesscsccsscvsssss
2-1
On_Board SWitChpaCkS
® 0 005 0 008 6606600 0006060000080 e sewe
3

ConfiguratioNS

COoNNECLIiONS
SPECIFICATION

.s.ececsccescconcesssssancnscssscansonnsas
sesececsrsascsscescsscsesaassssssscsacssacsonsas

® 2 8 2 8 8 8 ¢ 8 8 58 8 85 ¢ 0 80P P B T

T S8

NSO O

1
Environmental ConditioNnS....ceeesesccesscssssscnnossssse
2
Electrical RequirementsS ..cscevscecsccsscssssscssascssses
2.1
O-bus LO@dS
...t rececassssocassncssenasassscsnsssscas
3
PerformancCe scnseecsscseosssasasessnansssssnsscsscnsssscas
3

RAtES

et eeseacccanscscnssssasccanassasssnssssoscsa

4.1

Throughput ...c.cececcesnoscsssssssssssssssssaccsnnsas
RIAL INTERFACES .ccvoscessscsocoscnsencscansansens
Interface StandardS ...ccecessscssssccsssccsosssscsnscas

.4.2

Speed and

c4.,3
4.4

Line RECELVEILS ..veceancssssscscscssssoncscsssssscsassnnsns
Line TranSMitterS .eeececcecsesscsessscsscsesssscssnsocssa

T BN

Datd

FUNCTIONAL
1l

General

Distance ConsiderationsS

DESCRIPTION

.cccecescesssscsssccs

ccececcoesossoscsescsoccasssnscnsss

...eecencescecescscocccscacesssonsosssccntssssscasns

2
CXAl6/CXB16 Main FUNCLIiONS seccscesosscnsonsssssoncncnss
2.1
TranSmiSSiON s.seeeecsesscecscscsscscecscscsssasnsnssnsss
2.2
RECEPLION t.eeeeeccnccsnsvssnssasssovsosssosssssasccanse
3
Control ChiP
ceeeecooccsscccostssessnscsassssscsccscccnsnane
4
OCTART Chip & B 8 B 0 0 O % 5 O & B OO 8 P C O 0O O O S S QO S PO e s P e a b oo
CHAPTER

SCOPE

INSTALLATION
LR A A I A A I A A B A B B A

B B

UNPACKING

AND

INSPECTION

PREPARING

THE

CXAl6/CXB16

Y B

Y I

N A I S B B A B R A A A A N N

R R N

..ctccccococscsosssossssscnsoaccos

MODULE

Address

DHV1l

getting

the

Address SwitCheS

..civecccsccccsssssocsoccee

Setting

the

Vector SWitChesS

..icievecssescsccscsonnsosss

and Vector Assignment

cecececescsoscocscsessosnscs

DHUll

Programming

iii

....cceceesssccccnsconsscs

Mode

Selection

..aseececscses

= OWS WO

E S "

W o

et an s s

G 00t 6

OO s

ot e bt et bt fd e Pt ped el
R
T
L
L
L
]
OO
~IU UNWIWWIWHF

1
1

o & 8 O 9 & 9 A 8 5 ¢85 605 T 0D O OSSP

9 6 5 0 8 0 0 9 8 5 08 0 00 P OO S SR S S S0 O 2t e PO N S TSSO

b e bt et bt e bt el pd et e

SCOPE

OVERVIEW

INTRODUCTION

[S—

CHAPTER

4.1
S5

CONTINUITY

Bus

Grant

PRIORITY

eeececscnsscocancssnsasscsossssososasscssssnnsses

Continuity

SELECTION

5.1

RecommendationS

5.2

DMA

Request

CXAl6/CXB16

INSTALLATION

JUMPErS

cceescccsossscscnnscssssnsas

eoveecevecsccsccconsssssenasscssonscescascss

.seceescescscsscocccssosssacscsassssnsscs

Priority

cuevesesesescossssoscssacassasasssocs

INSTALLATION
TESTING

Installation Tests

..tceececcsssssscecscscscensscsscs

® 9 6 5 5 0 0 &5 0O PO P ST S H PTG

OGNS

..ccevccecoes

MicroPDP-1]1

SystemsS

S e

8
8

LOOPBACK

1
2

H3101
H3103

CHAPTER

TEST

CONNECTORS

Loopback
Loopback

® © 5 060 & 0 & 0 9 00 008 O ¢ w S oS S 0 9O

CONNECLOr
CONNECLOr

S S

P EDN

..ecsecavsssonccosascsoscsssascos
...c.ceceeasssssessnssscnscases

SCOPE

REGISTERS

eSO CEOEETDN

3-1

tuceetascscsacanssasscscasososscostssncssacsoncsnsses

3~1

3=1

® 9 2 8 8 0088005 S0 0L 0B 0N 0L 000 R L PSS ES LIS EE S

REJISter

ACCESS

Bit

Definitions

..ceceeesescsecesccacnsacsecncse

3=4

and Status Register (CSR) .ccivceeceonsssssss
Buffer (RBUF)
tieetecoscssccessasenssoscsosses

3~4
3=9

1
2
3

Transmit-Character

Receive

Line-Parameter

2
2

6
7

FIFO
FIFO

2
2

8
9

2
2

10
11

Line-Status ReEgiSter ...ieevecseccsessccscnnnnassecsss
Line-Control REQIStEr s.eeseesccevsecescasnnsoscnsnesss
Transmit
Transmit

(LPR)

.c.ceveecesccscscsssssens

(FIFODATA):
(FIFOSIZE):

DHUll

mode

DHUll

mode

only

.....
only......

Buffer
Buffer

TransmMitting
N
W

@
o
«

3-19

3=-20
3=21
3-25
3-26
3-28

teveesoeeocacsoncsocssoesossncsencncses
teeseessoosssescssosnscososssosocsnsossoassss

3—20

...eeseeseeseasoccconncossosonnscncsansaa

3=30

3—29

3=30
3-31
3=32
3=32
3~33

Auto XON and XOFF
0 8 8 0 5 00 88 000G S 0O E SN0
N e AT T E LT eSS PESTS
E.ror Indication .ceuieeseeseececasescessvsecsoasesnasensee

3—34

Maintenance

.eseeeeceoscseescococcsososcsssss

3=37

sevvseeeseaseoncecnnsossosoooscassasens

3=37

Diagnostic
8

3~14

3-17

4ttt enooreesassossoossoeceasonsnanasoanssnsss
Control ® 5 % 0 0 5 80 0B "G S S P06 0SS SE G E SN
et e

Interrupt

3-1
3-1

Address Register Number 1 (TBUFFADl)
Address Register Number 2 (TBUFFAD2)
Buffer Counter (TBUFFCT)
tcceveosencese

seeeceeseaeeesesoosocssacssscosscssscnssses
DMA TransfersS ...ceeescscrsonsosssassnossassccccssssnsss
Programmed I/0 (DHVI1l MOd€)
.evveecoconcnoscnnsosoeases
Programmed I/0 (DHUll MOd€)
.veceevesssnsceccencsannae

RECEIVING

o
e
®
*

3
3

Configuration

EENPSIN
Ol

3
3

Data
Size

INit1aliZAtiON

3
3

OO YOOI
U
W
W
N R

3
3

Timer

12
Transmit DMA
PROGRAMMING FEATURES

Control
Receive

cuveeecssosscsossscosssnscaconncensnnsoes

2
2
2

2—14

PROGRAMMING

2
3

NN [e— —

BUS

NN
N
1
i
1
P OO

NN
DN DD

Programming

COdeS

Self-Test DiagnosticC COGES .eeeeesoeceacenasscnnansss
Interpretation of Self-Test CodeS .eevesvecscecvesoes

SKipping Self-TeSt
Background Monitor

3—33

3=36

3=37
3=37

.iieiesesacrsoscascnnseoansenssssss

3—=38

Program

3~39

(BMP)

....ceescoccensccsses

PROGRAMMING EXAMPLES

3-39
3—-40
3-41
3-42

Programmed Transfer (DHUll Mode) ec.csvsccesvscssscss
Single-Character Programmed Transfer (DHV11l Mode) ...
DMA TranSfer R RN EE RN
I I I I AR O I N BN B BN S RS R RN B R )
Aborting a Transmission ..cecececcescnsccncccscsnscssas
ReceiVing 6 9 9 2 00 8 8 000860080080 ASSS S S SIS ISESEETSEOSIOSITEGSE
AutO XON and XOFF © 90 00 8 8 B 00 EE0CB OO0 NEOOLGEOESESEERRESEPREOEOETESES
Checking Diagnostic COGeS c.ceececessccssscccssssssssss
TROUBLESHOOTING
s a0 b

s s s e0e

INTERNAL

DIAGNOSTICS

.c.ceececscocsonsecsosonsasscessscsoccesn

3!1
Self"TeSt ® 0 5 © 0 @5 9 6 8 ¢ 8OO S O S B QOO OO e AT S S OO0 NG OO H OSSN 0 B0
3.2
Background Monitor Program (BMP) ..ccccecescccscosscsce
4
MicrOPDP-ll DIAGNOSTICS R R R E R EE R
N
N YN I I I I A B Y B R I )
4
User—MOde DiagnostiCS R EEEE R
N I I I N I N RS B RN I R

4
5
5.1
6

Running User-Mode TeStS

..cevcesssscsascossccsscsocsss

icroVAX II DIAGNOSTICS cvecesocascoscsnsensnssancsascsssoscasss
User-Mode TeStS .csssssssssssssssssnssssssnssssonsannsos
MicroPDP~11 SERVICE-MODE DIAGNOSTICS cccecsencossessnanccas

SERVICE~-MODE

Configuration TEStS

DIAGNOSTICS

iscsvecesressevcases

teeiescsecsassssscsccccsasseassesnss

.7.2
Field Service Functional TeStS ..cceescsscesscssnsssess
.7.3
Field Service Exerciser TeSEtS c.esossvsnscscsrsccsscsss
9 |4
Utilities ® 4 8 8 8 580 6089 98¢ 508 0SSN PSSR SEEISEBSEOeOEENDN
.8
FIELD_REPLACEABLE UNITS (FRUS) R R R R R R
N N I
B O A
9

CHAPTER

TECHNICAL

SCOPE

RAM

FUNCTIONAL BLOCKS

S 8 5 8 2B B S OO S S8

OCTART

L PSS 0 0G0 NBE

® 28 0 B B S P SN S BSOS 0P DS

CxAlG/CxBle

OSSO

@ ®© 5 00 9 25 5 5 O 0P S GOS ST S eSS0 S

OO P E O H O

® 0 0 0 2 3 0 9 00 ¢ S S0 2RO S

NGB0 S SEeIEEENINEPEEROE OSSO

OO S 0E SO S 00 E PO ENEY
L LSO N OGO GO0

NS A0

S S 0SS G0 s

0NN eSS

Rs e

1
2

Control~Chip InterfaCe .cecceccersescccscccsssssascanns
Line~Parameter RegiSter ...ceeeeesscscscscsssnssossnscs

Loop-Around CoOnNtrol
Baud-Rate Generator

4-11
4-12
4-12
4-13

DESCRIPTION

OVERVIEW

4-11

,...ceeocsescsossscccsssssssncsaans
..csccccsssevsesosscssasessosssssssnse

LflU‘Wtfl?‘mlflUTm

MicroVAX

7.1

)

6 .1.2
Loopback CONNECtOrS ..cesecovssccsncssnscccscasnsnsassnsses
6 l2
DECX].I Object MOdule 9 % 8 5 © 5 0 0 0 00 8 00 P OGO OO O EE N eO NGO e

6 .1
MicroPDP-11 Functional DiagnoStiC .cceeeccceosscccocnss
6 elel
TesSt SUMMALIES veeescscosvsessassenssnssncscssssssssssns

[

S B E P TS O 0O S 000 0SS0

S G S S S G

.cccccoeasvaosncsscsscnsncsssssascsssassssssscs

AN
W W
-

Preventive MaintenanCe ..esceescasecccsscsssssssssoassa
Troubleshooting ProCceduUresS .cceesscccscscsanosssessssssessae

2 .2

® 8 8 £ 5 0 2 B S

SCOPE

TROUBLESHOOTING

- N

1
2

3—42
3-43
3-44
3-46
3-47
3—49
3-51

|
|
=N
UTE B R
e b

CHAPTER

2 .1

R R R R

.1
.2
.3
.4

N R N NN A N I RN I N R R S S R N R WY

Resetting the CXAl6/CXBl6 .ucevescacssccssasassossanses
Configuration ' EEENENEENENIENE N NI I I I S I B A SN BN B K N Y S N BB B N R RN I N B R Y ]
Transmitting S 9 00 e 0020 Et 0 s8R sseRStOsOEROIBSROSESEBSIRSSsRSDOOUEGSTNRSBGS

(DMF)
(DIO)

.cccceccecsacccccaossnscanse
ceeeeccccvccsccnsscsccncnsonsasn

UART Fast Sequencer (UAF) .c.eececccssscascscsscansss
UART Slow Sequencer (UAS) ..ceveacecacssccsansoenscnsas
RAM Arbitrator (RARB) .ciececesescocecsncscossasscanss

Switchpack and Shift RegisSters
Q-bus

Drivers

and

Line INterfacesS
Power Converter

...cseessecsesceracsnnce

.eeisececssssnscesscnscncas

..ceesccccccsensccssessesssanscncsnssssos
(CXAI6 Only)
..eceeccececsacanscncssasnas

5"15

5—15
95=15
2—15
D—16

GO CSERBSRBESSD S

Data Flow for Character Reception .ceceececsccecssensss
Data Flow for Character TransmissSioOn ..c.ecseeescacseaeee
o1
DMA Operation ..cececccssssccssssssenssasnsssssonssnses
.2
Programmed I/0 Operation ...ceessccceccsscssnssssssccees

® 8 6 8 8 025 % 00 PSS

SELY S E S S S

S S S O S0

FLOW

RECEIVErS

DMA Fast Sequencer
Data I/0 Sequencer

seeeeescessccsvsancsnsesscnsses

(DMS)

Sequencer

YUY

..svsecesesncnsvsensaasss

2 % 0 08 #0688 08 0 RSSO s Gt P eEe

SEQUENCEr

(QIF)

Slow

Test

Interface

(S NV NG IV RV IU LI 0 JEV O G TG RV R
{
1
|
f—t ot e == AO 00 00 Q0 QO )~
WWwwo
o

WAL
W
-

W
W W

W W
W

W
W

W
L

U D

Q-bUS
DMA

RAM

LW W W

eecceescosccsosessoscscnccensancannssnssases

and

ChipP

Timer

DATA

gttty
gt
gl anan

Control

CXAl6/CXB16

APPENDIX

FLOATING

Q-BUS CONNECTIONS

APPENDIX A

AUTOMATIC

OVERVIEW

CONTROL

TRANSMITTED

CONTROL

RECEIVED

.3.2
.3.3

ctiivieecesncssnsoatsstsscccsonsosnssesonnssassences

C—1

.itececescssscssossssassenssesnss

C=3

Flow Control by the Level of the Receive FIFO ....e¢c¢.
Flow Control by Program InitiatioOn ..eeeececescccenasss
Mixing the two Types of Received-Data Flow Control ....

C=3

D‘]-

SCOPE

D-2

GLOSSARY

APPENDIX

LI BN

SCOPB

DATA

C=1

.ttt ceesocacassccancsscsansassss

APPENDIX

FLOW CONTROL

.3.1

0N S0
e

FLOATING DEVICE ADDRESSES S 8 5 08 ¢ 000 0 Q0 s a0t s a9 st eOB
FLOATING VECTORS ® 8 & @ 2 9 8 5 0005 000 00t S OB PSSO S0 S SO0 St

APPENDIX

ADDRESSES

Bl
B-2

DATA

GLOSSARY

TERMS

A A

B B

Y B R BN RN B R I I

® 8 8 & 90 6 57 S 6 PSS S E OSSO
CONTROL

CHIP

Y B B

AN BN R Y Y A I B Y I I

E 00 S0 eSS

B A

eE FEDE S SO0

CONTROL

E.3
L]

OCTART

CHIP

Y B )

D—l

0000t

D—l

a0 s e

AND OCTART

® 0 9 &8 6 4 8 8 B SR S 000 PSSP OGN S B D S B SR SR G AE SO0 P00

El2

A B IR NI

8 @ 88 8 & 2 8 P TS E LO S EE L O S EE G DO S BE 60D S PEEC P08 psePe

® 8 & % 4 900 0 856 ¢ 8385

C=5
C-6

BB SN

SO S S 00 S 00 G

INDEX

as AR e S e Pt e

E—z
E-4

w
w
v

)
le}
4]

and

Shift

Converter

..sceccase

,.cceccsescaccccsscsoscssssscssns

Receive Character Data FlOW ..cececcssscnccanns
Transmit Character Data FlOW ..ecsececcensscscs

[

Transmitted Data Flow Control ....ccecesncenns
Receive FIFO-Level Flow Control ..ccesceccsess
Program-Initiated Flow CONtrol ..ccecececsssnss

TN D
oW
o

QO WD = = = OV U B G e

TABLES

No.

Title

Page

1-1

3-1

“eri1al Line Connections for the 36-pin
CONNECLOL cevesssesvsoscnsssnsasessonssnssacsans
CXAi6/CXBl6 Registers in DHV11l Mode ....ee000¢

1-13
3-2

3-2
3-3

CXAl6/CXB16 Registers when in DHUll Mode .....
Data RALES civeceossescsasncoennsanssnsosssssee

3-3
3-17

3-4
A-1
B-1
B-2
E-1
E-2

CXA16/CXB16 Self-Test Error Codes ...eeeeesees
CXAl6/CXB16 Q-bus ConnectionNS ...ceeececcesses
Fleoating Device Address Assignments ..e.......
Floating Vector Address AssignmentsS ..seee-0..
Interface Signals ..ceevescccscccsacsscssnscasse
OCTART Signals eeeeeveecescsoccsssssssasacanssss

3-37
A-l
B-1l
B-4
E~2
E=D

1-2

Maximum Distance Guidelines

WYY

Table

.aeeeesecsssscsnscane

® 8 9 0 % & 8 B & 00 0 5 88 S e 0 B s E S 0w O Ss sO 2SO SO0 S oD

Switchpack
Power

Diagram

...ceecceccecssassacoassscssoss

00~
b =

OCTART

Block

AsSsignment

et = U o

W
= ~JR U
F~dRN N B WRN
W

]

v
v
v
v

RAM

e DO e b

|
[

CXA16/CXB16

[

CVMUUTUVTna
MmO

v
v
v
v

H3101 Loopback Test Connector ...ceceeesseccsas
Line Loopback Test CoONnector ..c..cccscececscces
Cable LOOpPbhACKS csvsevasssccscessosscasssassssse

CXAl6/CXB16 Module LaAayoOUt .c.eecscccaccsscnnsnse
Example of CXAl6 Configuration ...cc.cceccescsce
CXAl16/CXBl6 CONNECtiONS ccaescacccvssssanssocs
CXAl6/CXB16 Functional Block Diagram ..c.ecccee.
Location of the SwitchpackS cieececccacsnceaces
Setting the Device AdAress ece..ccecosssccccascs
Setting the Vector AJAress ...eecceccecsscscsoasns
Bus Grant Continuity FlOW .eccceeesccsccscsncns
CXAl16/CXB1l6 Installation .eeeeeecccsccsascsnns

Title

)
Onowmwmmmm?mmwwwmw»flp—-p—-»—|
.
1
|
]
[
|
|

No.

Wi —

—

Figure

v
v
v
v

FIGURES

vii

for CXAl6/CXBl6

1-10

PAGE

INTENTIONALLY LEFT BLANK

PREFACE

The CXAl6/CXBl6é Technical Manual provides reference information
on
physical
layout,
system configuration,
installation and testing,
pregramming characteristics,
and maintenance;
it also includes
a
technical
description
of the CXAl6/CXBl6é.
There is a glossary of
technical terms generally used in DIGITAL technical manuals,
and a
name
index
for
easy
topic
reference.
The Technical Manual is
divided

into

five

chapters

follows:

CHAPTER 1 INTRODUCTION.
This chapter gives a physical
description
of
the
CXAl6/CXBl6,
explains
how it can be configured,
and it
explains how it interfaces wich the
system
bus
and
serial
data
lines.

CHAPTER

INSTALLATION.

CXA16/CXB16 option,
address

and

selection,

testing after

This

chapter describes

with detailed

how

install

backplane positioning,

cables

and

connectors,

installation.

CHAPTER 3 PROGRAMMING.
This chapter describes CXAl6/CXBl6é
registers.
Some programming examples are also included.
CHAPTER

strategy
module.

TROUBLESHOOTING.

and
A

how

simple

use

This

assumed

the

that you have

APPENDICES.

These

chapter

explains

diagnostic programs

troubleshooting

flowchart

CHAPTER 5 TECHNICAL DESCRIPTION.
description

information on device and vector

maintenance

to locate a

gives

technical

asynchronous multiplexer.

some knowledge of Q-bus operations.

expand on

APPENDIX A - CXAl6/CXB16

topics

discussed

BUS CONNECTIONS

APPENDIX

FLOATING ADDRESSES

APPENDIX

AUTOMATIC

APPENDIX

GLOSSARY

TERMS

APPENDIX

CONTROL

CHIP

AND

FLOW

CONTROL
OCTART

faulty

included.

This chapter

CXAl6/CXBlé

control

this manual:

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CHAPTER

INTRODUCTION

1.1

SCOPE

This chapter gives an
overview
of
the
CXAl6/CXB1l6
asynchronous
multiplexer,
describes the facilities it offers,
and defines its
physical parameters and electrical requirements.
1.2

OVERVIEW

1.2.1
General Description
The CXAl6/CXB16
is
a
serial-line

full-duplex

serial

data

channels

interface

for use

which

provides

in BA213/BA2l4-based Q-bus

systems.

The CXAl16/CXB16

can be used in many applications,
including
data
concentration,
real-time
processing,
and
interactive terminal
handling.
It has two programming modes:
DHV1l1
and
DHUll.
The
register
sets
in these two modes are compatible with those of the
DHV1l

the

and

DHUll

respectively.

mode.

The

main

The

preferred

features

mode

operation

the CXAl6/CXBl16

are

follows.

Sixteen

full-duplex asynchronous data-only

The CXAl6
supports

supports
DEC422

DEC423

channels

connections,

and

the

CXBlé6

connections
NOTE

DEC422 is a term used
in
this
manual
to
indicate
a
data-leads-only implementation
of the RS-422-A standard.
DEC423 is a term
used
in
this
manual
to
indicate a
data-leads-only
implementation
of
the
RS-423~-A standard.

]

For

each

line:

DMA

transfers,

l-character

transmit

transfers

buffer

64-character

A 256-entry
FIFO
buffer
diagnostic information

and

program

DHV1l

transmit

for

FIFO

received

transfers

mode,
in

DHUll

program
mode

characters,

and

For CXAlé,

standards
interface

the
are
does

electrical

characteristics
and
signaling
compatible
with RS-423-A.
As the physical
not
wuse
a
37-way
subminiature
D-type

connector,
it
RS-449 standards
®

For

CXBl6,

the

standards

are

interface

does

connector,
RS—-449

not

comply with

characteristics

compatible

with

not

use

does

not

total

module

B8-bit
kbaud

throughput
both

flow

character

reporting

Self-test

and

Switch

Addresses

°®

DHV11

All

the

The

module

Signal

and

The

CXAl6/CXB16

modems

other

modem

supported

physical

subminiature

D-type

the

characters

all

channels

reception

and

receive

per

second,

operating

transmission

transmitted data,
the

<can

with

FIFO,

XON/XOFF
enabled

testing

vectors

programming mode
are

selected

suppressors

surge

program

a data

all

serial

lines

for

static

protection.

device and

Wide

Area

two

not

Network

program modes are referred
control
signals
supported
by
the

1line

handle
forms
part
of
the
system
bSulkhead.
distribution is through
two
36-way
connectors

surge

the

signaling

selecting:

functions

discharge

with

through

for

and

Transient

although

the

for each

50,000

background monitor

or DHUll

other

rates

character

control

functions

characters,

for

Automatic

and

standards

section

comply with this section of

RS-422-A.

37-way

The transmit and receive baud
individually programmed

38.4

this

electrical

using

the

does

CXAl6/CXBl6.

1-2

intended

for

equipment.

connection
Note

to as DHV11l and
these
devices

that,
DHU1l1,
are NOT

1.2.1.1
Self-Test Facility =-- The
CXAl6/CXB1l6
incorporates
self-tes. sequencers which operate independently of the host.
They
test

the

diagnostic

device

power-up

information to the host.

initialization,

and

report

1.2.1.2
Diagnostic Programs -- A full range of diagnostic programs
is
available.
These run under the PDP-11 diagnostic sSupervisor or
MicroVAX II maintenance system.
Diagnostic
information
1is
also
provided to the
host
system
through
the
receive
FIFO
buffer,
Loopback
test connectors are not needed when running the user-mode
diagnostics.
A maintenance kit with service-mode
diagnostics
and
loopback
connectors
is
available
from
DIGITAL.,
A
green
LED
indicates GO/NO-GO

status

for the device.

1.2.1.3
Preventing Data Loss -=— The CXA1l6/CXB16 can be
programmed
for
automatic XON and XOFF operation,
to prevent the loss of data
at high throughput.
The reporting of received XON/XOFF
characters
to the software driver can be enabled or disabled.
1.2.2

Physical

Description

The CXAl6/CXBl6 is based on
a
standard
quad-height
module
10.4
inches
(26.4
cm)
1long and 8.4 inches (21.3 cm) wide.
Figure 1-1
shows the layout.
The spacing of the backplane
slots
into
which
the

module
connects is physically different from a standard Q-bus
backplane,
although
they
are
electrically
compatible.
The
serial-line interface is through two 36-way connectors,
J1 and J2,
mounted on the module
handle.
This
handle
forms
part
of
the
BA213/BA214
bulkhead.
Connections
to
terminals
and
other
peripheral devices from these connectors are made
by
two
36-wire
cables

(BC16D-25)

and H3104

cable

concentrators.

[] LED

N
LINES

LINES

8-15

0-7

OCTART

CONTROL
CHIP

Ls2 |

]

[s]

MKVB9-0563

Figure

1-1

CXAl16/CXB16

1-4

Module

Layout

1.2.2.1 On-Board Switchpacks -- The CXAl6/CXBl6 has two
switchpacks to select the following device functions.
e

Ten-position switchpack (S2)

Switch

position 1

selects DHUll

open, or DHV1l mode when closed.

Switch positions
e

on-board

programming

mode

when

2 to 10 select the device Q-bus address.

Eight-position switchpack (S1)

This
Switch position 1 enables the on-board oscillator.
and must be closed for
test switch,
is a manufacturing
The device will not function with the
normal operation.
switch open.

indicator
Switch position 2 selects the external loopback
and
switch,
test
g
manufacturin
a
is
This
for self-test,

must be open for normal operation.

Switch positions 3 to 8 select the device-interrupt vector
address.

1.2.3

Configurations

different
many
in
used
be
can
The CXAl6/CXBl6
.
application
typical
a
shows
1-2
Figure
configurations.

system

DEVICE

H8571A
PASSIVE

ADAPTER

HOST

Q-BUS

BC16E-10
CABLE

ROCESSOR
PROCESSO

TERMINAL
CABLE

CONCENTRATORY)\

‘

PASSIVE

‘

CONNECTION

H3104 B=—x>
—

BC16D-25

CABLE

H3104 CABLE

=
===

CONCENTRATOR

}

ACTIVE
CONNECTION

TERMINAL

BC16E-XX

CABLES

R HAH

BC16E-XX

CABLE

)

PATCH BLOCK

SATELLITE
EQUIPMENT

ROOM

ACTIVE

ADAPTER

HB8571A
PASSIVE
JADAPTER

BC16E-10

CABLE

TERMINAL

PASSIVE

CONNECTION
ACTIVE

MM.J

‘

[

TERMINAL

SURFACE MOUNT

SOCKET

INSERT

CONNECTION

FACEPLATE AND

MOUNTING BOX

\v
BC16E-XX

CABLE

ACTIVE

BUILDING DATA

ADAPTER

CABLING

Figure

H3105

1-2

Example

1-6

CXAl6

Configuration

1.2.4

Connections

The CXAl6/CXBl6

module

1is

connected

the

system

backplane.

Figure 1-3 shows the interconnections and test arrangements.

| e S g

B nen B v B s

e SO

H3104

CABLE CONCENTRATOR

~H3101 LOOPBACK

CONNECTOR

CXA16

BC16D-25

ars v

CABLE

Figure

1-3

CXAl6/CXB16 Connections

1,3

SPECIFICATION

1.3.1
Environmental Conditions
Environmental
constraints
for

CXAl6/CXBl16

are as

storage

and

operation

the

follows.

Storage temperature within the range -40 degrees
degrees C (-40 degrees F to 151 degrees F)

Operating
degrees C

temperature within the range
(41 degrees F to 140 degrees

Relative

humidity
within
the
non-condensing,
temperature of 32 degrees C and

range
10
percent
to
95
a
maximum
wet-bulb
a minimum
dew
point
of 2

percent,
degrees

DIGITAL

5 degrees
F)

normally

defines

the

operating

temperature

range

for

system
as 5 degrees C to 50 degrees C (41 degrees F to 122
F);
the 10 degrees C difference between the
upper
1limits
allows for the temperature gradient within the system box.

degrees
quoted

The maximum

operating

degrees

C/1000 m

degree F/1000

temperatures must

ft)

1.3.2
Electrical Requirements
The CXAl16/CXB16 needs the following
backplane).
e

5 V dc plus or
1.4 A typical

12 V dc
typical

The

CXAlé

generates
®

1.3.2.1

-10

or minus
(CXAl6 only).
an

-10
V

OQ-bus

plus

has
a

minus

on-board

V supply

plus

Loads

3.0

loads

1.5

loads.

derated

electrical

percent

2.1

1.8

the

minus

loads

supplies

power

following

maximum

the

supply,

Q-bus

are:

the

current,

characteristics:

percent

applied

sites.

(from

135 mA maximum,

switch-mode

with

The

for operation at high-altitude

110

which

The EIA-232-D/CCITT V.24/V.28

standard was originally

specify
was not

designed

the
connection between a local interface and a modem.
intended to be used for connecting to terminals
over
specified
cable length is 50 ft (15 m).
maximum
distances.,
The
the
requirements
Shielded cable must be used in order to meet
FCC and VDE Radio Frequency Interference (RFI1) regulations,
greater
than
50
£t
can
with
Although cable
1lengths
used
cable
capacitance,
noise,
and
ground
reasonable
success,
potential difference restrict
the
line
speed
as
the
distances
increase,.
Consequently,
the
performance
of
long-distance
communications to a terminal using EIA-232-D often
not
meet
today's requirements for terminal wiring.
DEC423
has
a

is a superset of the
different grounding

EIA-232-D,
chips.
DEC423

as well

uses

RS-423-A/CCITT V.10 standard.
RS-423~A
and signal return path arrangement from

using

different

line

driver

and

receiver

driver
and
receiver
chips
which
have
better
tighter
level
tolerances
than those specified by
addition,
DEC423
devices
include
transient
suppressors
for
electrical
overstress
(EOS)
and
electrostatic
discharge (ESD) protection.
DEC423 devices may also
be
connected
with unshielded cable.

filtering
RS-423-A.

The

line

and
In

features

provided

communication

over

See

9600

baud.

Table

1-1

DEC423

increased
Table

Maximum

1-1

for

DEC423

EIA-232-D

DEC422

1000

9.6

f¢t

distance

300

250

200

ft
m

1000

300 m

DEC422

maximum

reliable

1000

(300

guidelines,

for CXAl6/CXBl6

4.8

provide

typically

Distance Guidelines

DEC423

devices

distances,

19,2 Kb

38.4

1000

500

300 m

150m

4000

1200

1-10

=
w
W
W
O
W
T
O

D-type

connectors defiased

in RS-449.

DEC423 is signal compatible with the EIA-232-D standard
when
used
for
data-leads-only
interconnection,
in
that
interconnection
between
devices
using
the different
standards
is
possible,
However,
the restrictions on speed and distance of EIA-232-D will
still

apply.

DEC423

should always be used

terminal

EIA-232-D terminals can be connected to the

CXAl6
using
either
of the following:
an
H852]1 passive terminal adapter or an
H3105
active
terminal
adapter.
An H3105 active
terminal adapter is necessary when using an
EIA-232-D terminal with a DEC423 interface,
if the longer cable lengths obtainable with
DEC423

9D
@
9
9
U

direct

NOTE

are

required.

A
terminal
may
be
connected
directly
to
the
H3104
cable
concentrator,
The
recommended
cable is BCl6E~xx,
which has MMJ
plugs at both ends,
and is available
in
lengths
up
to
100
f£¢t

(3¢ m).

The cable

is also available without MMJ connectors in 1000

ft (300 m) reels,
part number H8240,
MMJs are available in
packs
of
50,
part number H8220,
There are many other DEC423 connection
components available.
For more information,
contact
your
local
sales

office.

O
©
@
O
T
©
©
@
0
@
@

in preference to EIA-232-D for

connection over extended distances.

DEC423 is for data-leadsonly connections
to
terminal
equipment,
an.
1is
not
suitable
or connection to modems or other Wide Area
Netwvork equipment.
Th
standard
also
specifies
the
use
of a
modified
modular jack (MMJ) connector,
instead of the much larger

NOTE

DEC423

and

EIA-232-D

connections

are

intended
for
local
communication.
in
general,
communication devices can
become
non-operational
or be damaged if the total
cable length exceeds 1000 ft
(300
m)
for
DEC423
devices,
or
300
ft
(100 m) for
EIA~232-D devices.
The cable should not be
run
outside
the
building,
and
the
low-voltage data wiring must
be
separated
from
ac power wiring.
The installation or
site
may
require
additional
devices
to
correct problems

in communication.

NOTE

Under

ideal

conditions,

DEC423

devices

can

drive
cables
considerably longer than the
1000 ft
maximum
stated
above.
However,

differences
1in
ground potential,
pick=-up
from mains ac power cabling,
and
risk
of
induced
interference
1limits
the
maximum
distance
for
reliable
communications
in
most
DEC422

also

drivers

Note

that

devices

for

receivers.

while

protection

makes

and

ideal

RS-422

standard

compatible

for

use

between

not

DEC422

recommended

and

DEC423/EIA-232-D

supported

DIGITAL

product.
cable

lengths

4000

(1200

all

speeds.

1.4.3
Line Receivers
CXAl6/CXBl6é
module

The

convert

the

OCTART.

Signals

l1.4.4

EOS, ESD

This

connection

feasible,

supports

supported

< tuations.

environments.

this

DEC422

incorporates

and

high-noise

practical

Line

input

octal

serial-line

TTL

levels

inverted

the

receivers.

receivers,

suitable

for

use

which
by

the

Transmitters

The CXAl6 module
uses
quad
1line
the
OCTART
signals are

are

uses

signals

uses

octal

drivers.

serial-~line transmitters, and the CXBlé
convert the TTL level signals from

These

to DEC423 or DEC422
levels
inverted by the transmitters.

Table 1-2
shows
CXAl6/CXBlé6.

connections

1-12

the

36-pin

the

data

connectors

lines.

used

The

the

Serial Line Connections for the 36~Pin Connector

1
2

Blu/Wht
Org/wht

Line 0 Transmit +
Line 0 Receive +

19 wht/Blu
20 Wwht/Org

Line O Transmit Line 0 Receive -

3
4

Grn/Wwht
Brn/Wht

Line 1 Transmit +
Line 1 Receive +

21 Wwht/Grn
22 Wht/Brn

Line 1 Transmit Line 1 Receive -

5
6

Slt/Wht
Blu/Red

Line 2 Transmit +
Line 2 Receive +

23 Wht/Slt
24 Red/Blu

Line 2 Transmit Line 2 Receive =-

Org/Red

Line

3 Transmit

Grn/Red

Line

3 Receive

9
10

Brn/Red
S1t/Red

Line
Line

11
12

Blu/Blk
Org/Blk

13
14

25 Red/Org

Line

26 Red/Grn

Line 3 Receive -

4 Transmit +
4 Receive +

27 Red/Brn
28 Red/Slt

Line
Line

4 Transmit -~
4 Receive -

Line
Line

5 Transmit +
5 Receive +

29 B1k/Blu
30 Blk/Org

Line
Line

5 Transmit 5 Receive -

Grn/Blk
Brn/Blk

Line
Line

6 Transmit +
6 Receive +

31 Blk/Grn
32 B1k/Brn

Line
Line

6 Transmit 6 Receive -

15
16

51t/Blk
Blu/Yel

Line
Line

7 Transmit +
7 Receive +

33 Blk/Slt
34 Yel/Blu

Line
Line

7 Transmit 7 Receive -

17
18

oOrg/Yel
Grn/Yel

Spare
Spare

35
36

Spare
Spare

1.5
1.5.1

FUNCTIONAL

General

The CXAl6/CXB1l6
the
functions

functional blocks are shown in Figure 1-4.
are
provided by three chips:
one control

Most of
chip and

two OCTART chips.

O-bus

buffering

uses

six

DC021

bidirectional

buffers.

Serial-line

interface
buffering
uses two octal line receivers
and
two octal
line
transmitters
for the CXAl6é,
and two octal EIA receivers and
four

quad

line

transmitters

for

the CXBl6.

A
2k x 8
static
RAM
chip
provides
the
Switchpacks
provide vector address,
module
ming mode

selection.

W
W
W
@

Yel/Org
Yel/Grn

3 Transmit -

DESCRIPTION

Table 1-2

1-13

memory requirements.
address, and program-

AAM

DATA

CONTROL CHIP

Q-BUS
L

—

RAM

ADDRESS

)

——
e
RAM

ARBITRATOR

DMA

SEQUENCER

[T 1= =77

r____._._.ir__————l
BIDIRECTIONA!

BUFFERS

..'.
L
F

]
OCTART

LINES
107
0710

INTERFACE

- - = —~ A

2 T
]

‘

4 R
i

|
16
| CHANNELS

Q-BUS

INTERFACE

- -

OCTART

P’STA
SEQUENCER
- — - - —{
_____

2K x B

RAM

- — —

‘

LINES

8TO 15

- — — — -

OCTART

B T

e Rx

L_J

SELF-TEST
SEQUENCERS
e
= —

—

SWITCHPACKS
AND SHIFT

REGISTERS

MK VEI 0564

Figure 1-4

CXAl6/CXBl6 Functional Block Diagram

1.5.2

CXAl6/CXBl6 Main Functions

1.5.2.1

Transmission -- In the preferred programming mode

(DHUll),

characters may be either written directly to the transmit data FIFO
(programmed transfer),
or may be transferred from the host
memory
to the transmit data FIFO using DMA transfers.
In

DHV11l

programming

mode,

only

single

characters

can

transmitted
using
programmed
transfers.
Characters can also be
transferred by DMA as in DHUll programming mode.
1.5.2.2

Reception -- Received

characters

OCTART
and
transferred
to
a
such
area
per
1line)
by
the

are

deserialized

the

four-character area in the RAM (one
control
chip
OCTART
interface,

following an interrupt from the OCTART.
The OCTART interface later
removes characters from the bottom of this 4-character
FIFO,
and
places it in the 256 x 16 receive FIFO,
which can be read
by
the
host.

1.5.3
Control Chip
The control chip contains

the

following

functional

blocks.

O-bus Interface -- Matches
addresses,
generates
vector
addresses,
and handles interrupts.
It also interfaces the
O-bus signals to other functional blocks.

DIO Contrcl

©®

OCTART

Interface -- Transfers data between the OCTARTs

and

RAM,

and

the

operation

handles
of

the

host access

flow

control.

to device registers.

also controls

OCTART.

Self-Test/Power-Up Sequencer -- This section powers up
the
module
to & fixed set of initial conditions,
such as 9600
baud

-- Controls

rate

all

lines;

DMA Sequencer --

Initiates

transfers

module.

RAM

the

also handles

and

Arbitrator =-- Provides RAM

various

sequencers.

manages

and OCTART

self-test.

all

bus

DMA

access

data

the

1.5.4

This
and

OCTART

Chip

chip contains eight
serial-to-parallel

UARTs,
which
perform
data
conversions.
It

parallel-to-serial
interfaces with the

control

chip through
eight registers.
Four are read-only and four
are
write-only.
An
index
register is used to access individual
lines.,
The OCTART chip shares the RAM bus with the
control
chip,
the
RAM
1itself,
and a second OCTART chip.
The OCTART chip also
includes:

Receive and transmit

control

°®

Interrupt

interfacing with the control chip

°®

All

Diagnostic

Modem status multiplexers,

logic

16-output

for

baud-rate

necessary

generator

line-parameter

loopback

blocks

logic

1-16

registers

33
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CHAPTER 2
INSTALLATION

2.1

SCOPE

the
installation of
This chapter describes the preparation and
1If the option was ordered as part
as add-on options.
CXA16/CXBl16

of a system,
it will be already installed,
and you
should
refer
This chapter contains the
system unpacking instructions.
the
to
following

sections.

Unpacking

Preparation

Installation

)

Testing.

The procedures described in this section are designed for use
by qualified service engineers.
2.2

UNPACKING AND

INSPECTION

only

There are two options available, the CXAl6-AA and the CXB16-AA. The
contents of each option are as follows.

Quantity

Item

Part number

CXAl6 module

M3118-YA

Cable concentrator
Cable
Loopback connector
User Guide
Labels

H3104
BCl16D-25
H3101
EK-CAB16-UG

2
2
1
1
1

CXB16 module

M3118-YB

2-1

CXAl6-AA

CXB16-AA

1
2
2
1
1
1

Undo each package and examine the
contents
for
physical
damage.
Check
that
the contents of each package are complete.
Report any
damaged or missing items to the shipper and to
the
1local
DIGITAL
office.
Do not dispose of the packing material until the unit has
been installed and is operational.
2.3
PREPARING THE CXAl6/CXB16 MODULE
Three parameters must be defined before
address

Q-bus

base

Q-bus

interrupt

DHV11l

or DHUll

These

are

selected

2.3.1

Address

Switchpack
vector

for

factory
vector

S1
the

options,

vector

programming mode.

using

switchpacks

the CXA16/CXB16

module.

and Vector Assignment

and Switchpack
CXA1l6/CXB16

settings
options

installation.

are

or more

are only

S2 determine

module

correct

no other

installed

than

CXAl6/CXB16,

one

the device

respectively.

The

floating

the microsystem,

you

rules

must

and

address
have

other

check
your host system
and vector settings
is not
available,
applied;
these are given in

manuals;
they
may give recommended addresses
for the different options. If this information
the
full
assignment
Appendix B,

address

CXAl6/CXBl6's

NOTE

Some systems have
additional
restrictions
on module addresses and on slot locations.

10 POSITION

8 POSITION

SWITCHPACK SWITCHPACK

]

|
MRG0

Figure

2.3.2
DHV1l or
The CXAl6/CXBl6

2-1

DHUll

offers

Location

the

Switchpacks

Programming Mode

two

Selection
separate programming modes,

DHV11

DHUll.
The mode selected depends on the device driver used
system.
The
mode
1is
determined
by
switch
position 1
l10-position switchpack S2 (see Figures 2-1 and 2-2).

in
of

and
your
the

NOTE

DHUll
programming
mode
generally
gives
better
performance
because of reduced CPU
overhead
transferring
characters
to
and
from
the
device.
The
Software
Product
Description states
whether
the
operating
system
supports
DHUll
programming
mode.
DHUl]l programming
mode
is
the
preferred
mode of operation.,

2.3.3
The

Setting

device

the Address

address

for

the

Switches
CXAl6/CXBl6

set

the

10-position

switchpack S2.
The
location of this switchpack is shown in Figure
2~1.
Figure 2-2 shows
how
to
set
the
device
address
on
the
switchpack.
The
example
shown
1is
for the address of 17760440
(octal).

(Switch

ming-mode

the

switchpack

for

DHV11/DHUll

program-

selection.)

DHV- DHU MQDE SELECTION

LEGEND

PART OF SWITCHPACK S2

DEVICE ADDRESS SELECTION

{DHU MODE SELECTED)

D = SWITCH OFF (BINARY 0

PART OF SWITCHPACK S2

l = SWITCH ON (BINARY 1,

EXAMPLE

SETTING

=17760440

INTERPRETED

AS ALL ONES

]

)

]

I
1

]

'
|

DEcoDEd
BY DEVICE

SEE NOTE

BIT NO

2vj20]|

1918

[

DEVICE

ADDRESS

]r7|1el1s|1afjr13f12]11]10]lo9]oslorioefos]oa]l0aloz]

VRN

——

.’

VRS-

oo
/

EACH GROUP IDENTICAL

> ~

]

\\'/

NOTE

0]-86

olojo]=0

USE THE BLANK ROW TO

i1j1}=3

PENCIL-IN THE ADBAESS

PATTERN YOU NEED

= ;

11ojo]l=a
1ol

1]=58

1]1]o]|=8
tprfr

MKVE88-2053

Figure

2-2

Setting

2-4

the

Device

Address

2.3.4
Setting the Vector Switches
The six high-order bits of the interrupt vector address are set
on
the
eight-position
switchpack
S1.
Figure 2-1 shows the location
of this switchpack.
Figure 2-3 shows an example of these
switches
set
to
300 (octal).
(Switch positions
1
and
2 are used during
manufacture,
switch position 1 must be
closed,
and
switch position 2 must be open for correct operation of the CXAl6/CXBl6.)

MANUFACTURING TEST SWITCHES SW1 MUST Bt ON

VECTOR ADDRESS SELECTION
PART OF SWITCHPACK S1

SW2 MUST BE OFF
PART OF SWITCHPACK S1

LEGEND

r] . . fl rl

EXAMPLE

LJ LJ

=S:E;oo G

I—*- SWITCH OFF

L] sinarvo)

SWITCH ON

‘

(BINARY 1)

INTERPRETED

}

AS ALL ZEROES — 1

1s|1a

13|12

;

—7

TTIN

DECODED

BY DEVICE

SEE NOTE

8IT NO

(SN

VECTOR
ADDRESS

]|10|osjos]or]os]os|oajo3zjo2]or|oo
_J

]

—~—

’

BOTH GROUPS IDENTICAL
_

NOTE

T ——

USE THE BLANK ROW TO

olole¢ |

PATTERN YOU NEED

vlol=2

PENCIL-IN THE ADDRESS

VI R|

oltol

11=1
1v}=13

1]ojol|=a

1]ol1]=5s
1]1]o0}=8

MKVBS8- 2054

L 2

EE"

Figure

2-3

Setting the Vector Address

2.4

BUS CONTINUITY

Bus grant continuity
slots to provide bus
2.4.1

Bus

Grant

jumper cards
continuity.

are

used

In Q/CD backplanes,
through

the

bus
A

grant

signals

connectors

Lines AM2 and AN2 (BIAK),
grant signals.
Figure 2-4

backplane

Continuity Jumpers

The
CXAl6/CXB16
uses
the
Q/CD
backplane,
connectors,
user-defined signals on C and D,

module

vacant

each

pass
bus

Q-bus

through each

ox
OB

7))
7]
W

a |IC

Figure

2-4

Bus

Grant

and B

installed

slot.

and AR2 and AS2
BDMG),
carry
shows the bus grant routing.

Continuity

Flow

the

bus

W
WTM
W

PRIOCRITY SELECTION

VUV

VvV

VvV 'V

VWV

VvV

2.5

The CXAl16/CXB1l6 uses the BIRQ4 line to request
interrupt
service.
1t
does
not
monitor
any
of
the higher-level interrupt request
lines.
Because
of
this,
both
the
interrupt-request
and
DMA
(non-processor
request) priorities of the CXAl6/CXBl6 are selected
by the position of the CXAl6/CXBl6 on the bus.
Devices closest
to
the processor module have the highest priority.
The bus (backplane) position may be a compromise
between
DMA
and
interrupt
priority requirements.
As a general rule,
consider DMA
request priorities first,
then interrupt (bus) requests.
2.5.1

Recommendations

In general the CXAl6/CXB16 bus position is not critical.
However,
it
1is recommended that you place the module after any mass-storage
interfaces
and
high-speed
synchronous
communications
options;
these

The

are more sensitive

following

list

to bus position.

shows the recommended module sequence:

CPU

Memory modules

Synchronous communication modules -

General-purpose 1/0 ports

Line printer

interface

Asynchronous

communications modules -

no silo

Asynchronous

communications

silo

Synchronous

Communications module

10.

modules

communicaticn modules
-

smart

no silo

DMA

Asynchronous communicatiors modules (e.g. CXA16/CXB16).

2,5.2

DMA Request

Priority

sooner

than

ones.

silo/DMA

DMA request priority is usually assigned according
to
throughput.
Faster
devices
(higher
throughput)
usually
have
priority over
slower DMA devices;
for example,
disk
has
priority
over
tape,
which
itself
has
priority
over communications devices.
This is
because fast devices usually reach overrun or
underrun
conditions
slower

2.6
CXAl6/CXB16 INSTALLATION
This section gives a step-by-step guide to installing
the
option,
Figure 2-5 shows how the parts of the option connect together.
1.

Before you begin the installation, check that the system
operating correctly by running appropriate diagnostics.

Turn

the

system

power

off.
WARNING

Shut off the system
power
and
disconnect
the
main
system
power
cord
before
performing any procedure in this chapter.
ATTENTION

Avant d'effectuer 1'une des
ce
chapitre,
tension
et
d’'alimentation.

mettez
le
debranchez

procédures

systéme
hors
le
cordon

VORSICHT!

Schalten Sie das
das
Netzkabel,

Kapitel
ausfihren,

System ab,
bevor
Sie

beschriehenen

und ziehen Sie
die in diesem

Answeisungen

ATENCION

Apague

sistema

dgsconecte

cable

pringipal de alimentacion antes de realizar
ningun procedimiento de este capitulo.

LIy IT]

¥
w

wv w

Remove the module blanking plate at the chosen position

the system box and the grant card if fitted.

Make sure
that
bus
grant
continuity
is
from the CPU to the last module
maintained

NOTE

into

the

backplane.
|

module

NOTES

the

module
shag
to
not
careful
Be
1.
ccmponents
on
the card guides or adjacent

Insert

bus.

modules.

the

Ensure
2.
antistatic

29-11762-00.

installation.

W
v

no test

Run the user-mode diagnostics® to test the module;
connectors

an
wearing
part
number

are
that you
vwriststrap,

Turn the power
on.
After
two
seccnds
check
that
the
self-test
LED
is
on;
this
indicates
a
successful
self-test*.
Correct any problems
before
proceeding
with
the

are

required.

Connect the BCl16D-25 cables to J1

and

the

module

bulkhead.

Connect the other ends of each
cable

BCléD

<cable

H3104

concentrator,.

The self-test and diagnostics used to test the
installation
of
the
CXP16/CXB16
are
briefly described in Section 2.7,
and in
more

detail

Chapter

H3104 CABLE CONCENTRATOR

1
;

BC16D-25
CABLE

Figure

2-5

W
Ld
d
d
d

BC16D-25
CABLE

CXAl6/CXB16

2-10

Installation

H3104 CABLE

CXA16

CONCENTRATOR

WTM

—

pu—

[
————

2.7

INSTALLATION TESTING

This

section details

the diagnostics used to test

the option during

and
after
installation.
The
diagnostics
are also used to test
other Q-bus modules in the same family,
for example,
DHV1l,
The
diagnostics will automatically ‘size’ the option to determine which
one is being tested.
The CXAl6/CXBl6 can be tested
in
either
of
its two programming modes.
Both PDP-11 and
MicroVAX
1II
diagnostics
are
described.
After
successful
completion
of
the
appropriate
system
test,
the
CXAl6/CXBl6
may
be
connected
to
external
equipment.
Further
information on the diagnostics is given in Chapter 4.
2.7.1

1Inst2llation Tests on MicroPDP-11

To verify that the MicroPDP~11l
are

functioning

Systems

system and

the

CXAl6/CXB16

module

correctly:

Check

that

module

the grezen

self-test

LED

the

CXAl6/CXBlé

on,

Boot the MicroPDP-11 Customer Diagnostic media.
Refer
your MicroPDP-11 System Manual for further information.

Type

'I’'

identify

the main menu

the

new

allow

module and add

the

diagnostics

to the configuration

file.
NOTE

Look

make
If

the

list

not

instal’ation

Type

have

run

Field

XXDP+
is

switches

the main

repeat

DIGITAL

and

Kit

diagnostic
confiqure

functional
XDHV**_,OBJ.

the

been

the

set

system

tests,

These

an error occurs,

call

Service.

Maintenance

individual

module

and

included.

and make sure that

complete without error;

monitor,

The

'T'

included,

should

A MicroPDP-11

run

devices displayed,

sequence,

the
module
correctly.
4.

sure that the new module

available,

programs
and

run

diagnostic

under

allows

you

the

XXDP+

system

test

programs.

VHQA**.,BIN,

and

the DECX1l

DECXll

1is

which

diagnostic

2.7.2

Testing

To verify
are

in MicroVAX

that

the MicrovAx

functioning
1.

Check

Systems

system and

that

the

green

self-test

the MicroVAX Maintenance
MicrovAX I1 System Manual for

Type
and

CXAl6/CXBl16

module

LED

the

CXAl6/CXBl6

is on.

Boot

the

correctly:

module
2.

'2'

the main menu

System media.

Refer
information.

further

to show the

your

system configuration

devices.
NOTE

Look at the

list of devices displayed,

and

make
sure that the new mocile is included.
If
it
is
not
included,
repeat
the
installation
sequence,
and make sure that
the
module
switches
have
been
set
correctly.
4,

Type

'l'

should
DIGITAL

2.8
Two

and

2.8.1

the

H3101

H3103;

main

and

36-way

run

error;

the

cables,

that

they

2-6

connector

loopback

test

the

are

type

the

H310l1

system

1if

an error

for

two

female

connector.

module

echoed

shows

the

tests,

These

occurs,

call

CXAl6/CXBl6,

the

shipped with

the

option.

Connector

consists

cabling

Figure

only

Loopback

loopback

pa~kage,
male

the

LOOPBACK TEST CONNECTORS
loopback connectors are available

H3101

The

complete without
Field Service.

loopback

36-way
It

can

bulkhead,

characters

the

wiring

(refer

H3101

the

screen

connectors

loopback

inserted

cable

one

and

into

concentrator.

keyboard

and

to Chapter

loopback

connector

make

4).

connector.

the

To
sure

-Rx 2 o—d UUSSEEDDNNOOTT
e

——

Il! -Tx Rx- -Tx

Rx- Ta- Rx- Tx Rx- fil- Rx-

-Ra

- Te

— e

————

Ax+

Rx+

.u‘l.‘wl:*

1LINE

L3INE

it i

Tu4 Rx+ T+

————

Tx+ Rx+ Te+

USEDNOT——340~

Ax-

- Tx

UUSEDSED NOTNOT

—

4 LINE

L1INE LINED

L7INE L6INE L&INE

rvll_dw.rl‘&m:.v

FLoi2HCogp3n-ub1eacr0t6coe1kr

MALE CONNECTOR

{ {

i |

5 LINE

2-13

L6INE
IR

{

L3INE

{{

1T-9x

w w = g - w Q Q 2 2 [ Q ~&

LSINE

+4RAx

——————0O 1 NOT USED

Figure 2-7 shows the wiring of the H3103 loopback connector.

part of the maintenance kit.

H3103 Loopback Connector

[:::244Rx-

3Tx-

0 2Tx+

+
O
5 Rx
————

e
e

O 6 NOT USED
L

2.8.2

The H3103 loopback connector is used during maintenance diagnostic
testing
to
test each line from the CXAl6/CXBl6 at the output from
the H3104 cable concentrator.
This connector is only available
as

Figure

2-7

VLine

Loopback Test Connector

2-14

HERKHARKEHKARREARRARREARAARRKEREXARNARKX
R KA AREARRNRE X
ERRAEURKARAEARRKEURA
AR RAR R XA R RAARA KRR AR UMK RAARAAXR

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CHAPTER 3
PROGRAMMING

3.1

SCOPE

and how they
This chapter describes the program control registers,
The chapter
and monitor the CXAl6/CXBl6.
to control
used
are
covers:

The bit functions and format of each register

Programming features available to the host.

Some programming examples are also included.
NOTE

preferred
is the
DHU1ll programming mode
The
mode of operation for the CXAl6/CXB16.
the
use
that
development of user drivers
programming mode is
DHV11l
in
CXAl6/CXB16
not recommended.

REGISTERS

3.2

The host

system

controls

and

monitors

the

through several Q-bus—addressable registers.

CXAl6/CXB16

module

Command words or bytes written to the registers are interpreted and
Status reports and data are also
sequencers.
by the
executed
transferred
3.2.1

through

the

registers.

Q-bus
of
bytes)
(16
8 words
registers occupy
CXAl6/CXBl6
Some of these registers perform several
space.
1/0
memory-mapped
functions,

selected

through bits

the CSR.

is
registers
The base physical address of the eight CXAl6/CXBl6
be
must
selected
address
The
module.
the
on
by switches
selected
in

the

peripheral

I/0

space.

Tables

3-1

and

addresses
that there

3-2

1list

the

CXAl6/CXBl6

registers

(in
DHV1l
mode
and DHUll mode).
The suffix
are eight of these registers,
one
for
each

When

an
(I) register is accessed,
the address
is indexed by the contents of CSR<3:0> to select
the appropriate channel,

The

term

'base’'

to say,

means

the

four

when

lowest

I/0

low-order

given

the

address on the
address

bits

and

their

(I) means
channel.

in the table
register
for

module;

that

NOTE

Before indexed (I) registers are
accessed,
the
channel
number must be written to the
CSR.

Table

3-1

CXAl6/CXB1l6 Registers

in DHV11l

Address

Control

and

Receive

Buffer

Status

(CSR)

Transmit Character
Line-Parameter Register
Line

Status

Line

Control

Mode

(Octal)

Type

Base

Read/Write

(RBUF)

Base+2

(TXCHAR)
(LPR)

Base+2
Base+4

(1)
(I)

Write Only
Read/Write

Read

Only

(STAT)

Base+6

(I)

Read Only

(LNCTRL)

Base+10(I)

Read/Write

Transmit

Buffer

Address

(TBUFFAD]l)

Base+12(I)

Read/Write

Transmit

Buffer

Address

(TBUFFAD2)

Base+l14({(I)

Read/Write

Transmit

Buffer

Count

{TBUFFCT)

Base+16(1I)

Read/Write

NOTE

DHV]1]l

the
host

write

line-status
register.
However,
should not write to this register.

mode

possible

the

3-2

CXAl6/CXB1l6

Registers when

in DHUll Mode

Address

Control and Status Register
(CSR)
Receive Buffer
(RBUFF)
Receive Timer*
(RXTIMER)
Line-Parameter Register
(LPR)
FIFO Data
(FIFODATA)
FIFO Size
(FIFOSIZE)
Line Status
(STAT)
Line Control
(LNCTRL)

Base
Base+2
Base+2
Base+4 (I)
Base+6 (1)
Base+6 (I)
Base+7 (I)
Base+10(1)

Read/Write
Read
Write(byte)
Read/Write
Write
Read(byte)
Read(byte)
Read/Write

Transmit
Transmit

(TBUFFAD1)
(TBUFFAD2)

Base+12(I)
Base+14(1)

Read/Write
Read/MWrite

(TBUFFCT)

Base+l6(I)

Read/Write

Buffer Address
Buffer Address

1
2

Transmit Buffer Count

* Only

accessible

(Octal)

Type

when CSR<3:0>=0000.

There are 16 line-parameter registers,
only 1 of which is accessed
at any one time.
The register which is accessed is associated with

the

line

For example,
the following

using

used on

all

;READ THE

sWRITE

@#BASE+4,R0

#CHAN, @#BASE

the

above

However,

read-modify-write

registers except CSR and

to read the line-parameter
register
I/0 commands would be executed:

example,

CHAN

bit

the

RXIE

the

MASTER,RESET

0011

channel

number

CHANNEL NUMBER
LINE

(SEE

PARAMETER

the

bit

3
NOTE

Not all
action,

Os.

undefined.

read

action,

unused

bits

channel

BELOW)

CSR

(which would

RBUF.

Oer000ll(binary)

T
T
W
Y
N
T
W
T
&

CSR<3:0>,

MOVB

Where

MOVB

selected

instructions may

Table 3-2

are

CSR

3.2.2

Registers

which

3-1.

Figure

are

modified

reset

sequences

are

coded

shown

CLEARED BY MASTER RESET

SET BY MASTER RESET

—

lL_4

B8UT

Figure

3.2.2.1

Control

CLEARED 8Y BINIT
NOT BY MASTER RESET

3-1

and Status

Registur Coding

(CSR)

CSR (BASE)
15

7
-

RIAWl

ACTION

RCVE

SKIP

DIAGNOSTICS |

TRANSMIT

FAILURE

&TABL ¢

LINE NUMBER

RXIE

;

rh?;\héi:\:gl_[{ TRANSMIT
DMA ERROR

R]R|R|[R|AWIRWRWIRWIRWIRW|RW

|
TM

[

INDIRECT ADDRESS REG POINTER
(CHANNEL NO)

RCVE DATA

MASTER

AVAILABLE

RESET

*DHU11 MODE ONLY

UNUSED IN DHV11 MODE

3-4

Bit

Name

Description

TX.ACTION

This bit is set by the

(Transmitter Action)

when:

(R)

CXAl6/CXBl6

1.
The last
character
of
buffer has left the OCTART.

DMA transfer has been

DMA

transfer

DMA

aborted.

has

been

CXAl6/CXB16 because
by
terminated
addressed,
non-existent memory was
parity
memory
a
of
because
or
error,

4.
In
DHV11
single-character

accepted,

been

has

mode
when
a
programmed output

character taken

that

is,

from TX.BUFF.

5.
In
DHUll
mode,
following a
the
transfer,
data
programmed
module has emptied a transmit FIFO.

The

bit

the

host

FIFO has become
empty,
To
reports,
TX.ACTION
losing

avoid
the

reads

the

cleared

CSR after the TX.ACTION

than 16
more
let
not
must
host
reports
accumulate.
It
is
until
CSR
the
read
advisable to

TX.ACTION

becomes

clear.

upper

NOTE

TX.ACTION reports may be

byte

read of

TXIE

Interrupt
(R/W)

the

lost

the

CSR is discarded following a

the CSR.

(Transmit

Enable)

the
allows
bit
this
set,
When
interrupt the host
to
CXAl6/CXBl6
becomes
(TX.ACTION)
CSR<15>
when
set.

The bit
not

is cleared by

by MASTER,RESET.

BINIT,

but

Description

Bit

When

DIAG.FAIL

(Diagnostic
(R)

Fail)

set,

this

CXA16/CXBl6
have
the

bit

indicates

internal

that

diagnostics

detected an error,
either
self-test diagnostic or by

by
the

bit

the

BMP.

This

1is

associated

with

diagnostic-passed
LED.
When it
set,
the LED will be off.
When
is cleared,
the LED will be on.

is
it

The bit is set by MASTER.RESET.
It
is
cleared
after
the
internal
diagnostic programs have
been
run
successfully.
It is valid only after MASTER.RESET
bit CSR<5> has been cleared.
12

TX.DMA,ERROR

(Transmit
(R)

also

DMA Error)

this

bit

set,

set

and TX.ACTION

either

the

indicated by CSR<11:8>

channel

has

failed

to
transfer
DMA
data
within
10
microseconds (in DHV1l
mode),
or
20
microseconds
(in
DHUll mode),
of bus request being
acknowledged,
or

memory

parity

error

exists.

The TBUFFAD1 and TBUFFAD2 registers
will contain
the
address
of
the
memory
location at which the error
occurred.
<11:8>

TX.LINE

Line

(Transmit

Number)

(R}

(Received
Available)

Data
(R)

will

If TX.ACTION is
set,
hold the TX.ACTION line
When

RX.DATA,AVAIL

TBUFFCT

set,
a received
The bit is
FIFO

The

bit

cleared.

these
bits
number.

this bit indicates
that
character is
available.
clear when
the
receive
empty.

request

receive
set

used

interrupt,

after

MASTER,RESET

because the receive
FIFO
diagnostic information.

contains

Description

(Receiver
Interrupt
(R/W)

the
allows
bit
this
set,
When
CXAl16/CXB16 to interrupt
the
host
when
RX.DATA.AVAIL
is
set.
An
interrupt is
generated
under
the
following conditions.

Name

.' " @ QO U U U UV VUV U VYUV VYUV VUV UV VYU VU U UV VU UV VP Vv

Bit

RXIE

Enable)

RXIE

placed
2.

set

and a character

into the empty receive FIFO.

The

receive

FIFO

or
more
characters,
changed from 0 to 1,
by BINIT
5

MASTER.RESET
Reset) (R/W)

(Master

This

but
set

reset when
set while
self-test
performs

not
by

contains

one

and RXIE is
It is cleared

by MASTER,RESET,.

the host

order to

in DHV1]l mode.
1t stays
the
CXAl6/CXB16
runs a
sequencer,
and
then
an
initialization

sequence.
The bit is
to tell the host that
is complete.

then
the

cleared
process

This
bit
1is
set
by
BINIT
(bus
initialization
signal),
or by the
host processor setting CSR<5>,
If the CSR is
written
to
while a
MASTER.RESET
sequence
is
in
progress,
the
MASTER.RESET
bit
must

3-7

cleared.

Bit

Description

Name

SKIP
(RW)

(Skip

Self-Test)

In DHU1ll mode, this bit is used
to
shorten
the
reset/initialization
time to about 30 milliseconds.
The host program must only set this
bit
at
the
MASTER.RESET.

the bit,

but must wait at least

microseconds

same
time as it sets
It must
then
clear

before

recommended that

doing

so.

20
It

the host always

set SKIP when setting MASTER.RESET.
The
CXAl6/CXBl6é
will
execute the
full
self-test,
regardless
of
whether
SKIP
is
set or not.
The
1.7

seconds

delay

during

MASTER.RESET
is
purely
for DHUII
hardware compatibility.
In
DHV1l
mode,
this
bit
1is
ignored
for
compatibility reasons.
<3:0>

IND.ADDR.REG

(Indirect
Register)

Address

For
indexed
select one of

(R/W)

3-8

registers, these
16 channels,

bits

W
W
W

character

in bit

RBUF (READ BASE + 2)

3.2.2.2
Receive Buffer (RBUF) -- A READ
from
base
+
2
s
interpreted
by the CXAl16/CXB16 hardware as a READ from the receive
FIFO.
Therefore,
RBUF
is
a
256-character
register
with a
single~word
address.
The
least-significant
bit
(LSB)
of
the

(1L

T T1TTT]

RECEIVED

DATA

FRAMING

VALID

ERROR

RECEIVE

CHAR.‘\CTER

LINE NUMBER

DIAGNOSTIC INFO

OVERRUN

PARITY

ERROR

VWV

VvV

VUV

VvV

E£RROR

Bit

Name

DATA.VALID
{Data Valid)

Description

(R)

This bit is set if there
the receive FIFO,

is data in

When
this
bit
is
clear,
are
RBUF<14:0>
of
contents

the
not

valid.

diagnostic
self-test,
After
the
into
loaded
is
information
this bit
Therefore,
receive FIFO,
is
always
set
after a successful
master

reset

sequence.

Description

Bit

Name

OVERRUN.ERR (Overrun

This bit 1s

Error)

(R)

set

one

characters of

the channel

indicated by bits <11:8> were

1lost

because of a full receive FIF0O,
failure

service the UARTs

or
(see

alsc RX.CHAR).
NOTE

The

'all

1s'

reserved.

RBUF<7:0>
13

FRAME .ERR
Error)

code
This

holds
{Framing

for

bits

code

diagnostic
This

1is

PARITY.ERR
Error)

(Parity

(R)

set

the received

not detected

is
that

information.

bit

bit of

(R)

<14:12>

indicates

This bit
a

enabled

parity

indicated

stop

was

(also sse RX.CHAR),

is set if

has

the first

character

this

error,
for

character
and

the

by bits <11:8>

parity
channel

(also see

RX.CHAR).
<11:8>

RX.LINE
Line Number)

(Receive
(R)

These bi1ts hold the

binary

the

character
received.

3-10

channel
of

number

which

RBUF<7:0>

the
was

Bit

<7:0>

Description

Name

RX.CHAR

(Received

If RBUF<14:12> = 000,

Character)

(R)

bits
contain
the oldest character
in the receive FIFO.
The character
is good.

If RBUF«<14:12>

001,

these

olo0,

eight

011,
these eiglt bits contain the
oldest
character
in
the
receive
FIFO,
but the character is bad.
If

RBUF<14:12>

RBUF<7:1>

contains

111,

then

diagnostic

information.

If there is an
overrun condition,
the
UART data
buffer
for
that
channel will be cleared.
This data
will
be lost.
A null character is

placed in the
RBUF<14> is

receive

FIFO,

and

set.

The CXAl6/CXBl6
does
not
have a
break-detect
bit.
A line break is
indicated to the program as a
null

character

with FRAME.ERR set,

OVERRUN.ERR clear.

and

3.2.2.3

Transmit Character Register

Single~-character

programmed

c¢naracter register.

Bit

(TXCHAR)

transfers

(DHV11l Mode Only)

are made through

function is as follows:

=--

the

transmit

TXCHAR (WRITE BASE + 2.DHV11 MODE)
15

wilwliwlwl|lwlwlwl]lw

TRANSMIT

TRANSM;T

DATA VALID

CHARACTER

Bitc

Name

Description

TX.DATA,.VALID

(Transmit
Valid)

When set,

Data

(W)

this bit

CXAl6/CXB1lé6

character

held

instructs

transmit
bits

<7:0>,

the

the
The

bit
1is
sensed by the CXAl6/CXB16,
which then transfers the character,

clears

the

bit,

and

sets

the

character

TX.ACTION.
TX.DATA.VALID

written

separate

<7:0>

TX.CHAR
Character)

(Transmit
(W)

and

tcgether,

MOVB

can

instructions.

This byte sets the character to
be
transmitted,
The
LSB
is
bit O,
For
7-,
6-,
or S5S-bit characters,
unused

3-12

bits

must

the

receive

timer.

It can be used by the host to delay the receive

interrupt.

3.2.2.4
Receive Timer Register (RXTIMER) (DHUll Mode Only) =-- The
indirect address register (CS5R<3:0>) must = 0000 in order to access

Rx TIMER (WRITE BASE+2.DHU11 MODE)
15

01 00

Bit

Name

Description

<7:0>

RX,TIMER

The

timer)
(W BYTE)

loaded
into
receive FIFO.

VvV

will
be
conditions

is normally

Infinite

the previously empty
number
binary
The

RXTIMER modifies
follows.

this

This timeout
overridden
by
the

timeout.

below.

2
to
255
Timer
delay
in
milliseconds.
The
timer
is
FIFO
receive
the
overridden when
full
three~quarters
becomes
(critical).
Set

VUV
VOV
9O
O
9
U
O

3-13

interrupt

1 = No timeout.
The interrupt will
be raised immediately.

VvV

loaded
into
procedure as

(Receive

receive

raised when a received character is

VUV

“C‘“CIMLL“’ wWlw) mIIMI

to value

by MASTER.RESET.

3.2.2.5
Line-Parameter Register (LPR)
configure
its
associated
channel.

-- This register is used
to
Bit
function is as follows:

LPR (BASE + 4)

rwlrw]lrwlrwlrwlrRWIrRW[RWIRW|RW|RW|RW|RW]|RW]RW|RW

TRANSMIT

sTOoP

SPEED

DIAGNOSTIC

ENABLE

EVEN

SPEED

PARITY

CODE

RECEIVE

CODE *

CHARACTER

PARITY

DISABLE

LENGTH

REPORTS

* 00 = NORMAL OPERATION
01 = SCREEN RECEIVED XON."XOFF CHARACTERS

FROM ENTRY INTO RECEIVER BUFFER IF

0 AUTO IS SET

Bit

Name

Description

<15:12> TX.SPEED
{Transmitted
Rate)

<11:8>

Data

(R/W)

RX.SPEED
Data Rate)

(Receive
(R/W)

STOP.CODE

(Stop

Code)

(R/W)

This
is
MASTER.RESET

set
(9600

defines
the
(Table 3-3).

transmit

This
is
MASTER.RESET
defines
the

set
to
1101
(9600
bits/s).
receive
data

This

bit

defines

transmitted

stop

stop bit

B-bit

to
1101
bits/s).

the

data

length of

rate

by
It
rate

the

bit.

for

5-,

6-,

1-,

7=,
stop

or
bits

characters

1 = 2
8-bit
for

stop bits for
6-,
characters,
or 1.5
5-bit characters

The

bit

3-14

by
It

cleared

by MASTER.RESET.

Description

Bit

Name

EVEN.PARITY
Parity) (R/W)

(Even

If LPR<5> is set,
this bit defines
the type of parity.
1
0

=
=

Even parity
0dd parity

The bit

PARITY.ENAB
(Parity
Enable) (R/W)

This causes
a
parity
generated on transmit,
on

receive,

1
0

=
=

The
<4:3>

CHAR.LGTH

Length)

(Character

(R/W)

is cleared by MASTER.RESET.

Parity
Parity

bit

This

bit
to
be
and checked

enabled
disabled

is cleared

defines

by MASTER.RESET.

the

length

include
not
does
It
characters.
start,
stop,
and parity bits.
00

bits

10
11

=
=

6
7

bits
bits

bits

The

MASTER.RESET.

3-15

set

Bit

<2:1>

Name

Description

DIAG

(Diagnostic

Code)

(R/W)

These

are

They

diagnostic

are

used

control

the

codes.

host

follows.
00
01

=
=

Normal operation
Causes
the

Background

Monitor Program (BMP) to report the
CXAl6/CXBl16 status to
the
receive
FIFO,
<0>

DISAB.XRPT

XON/XOFF

(Disable

Reporting)

XON

and

reported

XOFF

all

characters

are

channels.

(R/W)
1

LNCTRL<4>

also

particular
characters are

channel,
filtered

received

stream,

data

the

host

initialization,

cleared.

to this

the

need

order

bit,

XON

code

XOFF

other

interface.

code

021(octal) =
= 023(octal)

codes

are

3-16

DCl

= DC3
specified

read

CSR<3:0>

these
from
the
to relieve

this
to

NOTE

for

to do so.

zero.

set

CTRL/Q.

= CTRL/S.
for
the

bit
or

must

write

equal

-~
ww
-w
w
W
w
W
W
w

Data Rates

Maximum
Error (%)

Data Rate
(Bits/s)

0000
0001
0010
0011

50
75
110
134.5

0.01
0.01
0.08
0.07

0100
0101
0110
0111

150
300
600
1200

0.01
0.01
0.01
0.01

1000
1001
1010
1011

1800
2000
2400
4800

0.01
0.19
0.01
0,01

1100

7200
9600
19200
38400

0.01

1101
1110
1111

0.01
0.01
0.01

VvV

WwVvV

wvVv

3=-3

Code

Table

3.2.2.6
FIFO Data
Register
(FIFPODATA)
(DHUll
Mode Only) -- To
write
a
character
or
characters
to
a transmit FIFO,
the host
writes
the
character(s)
to
the
FIFO
data
register
of
the
appropriate
channel.
To make
sure
that
there
1is room in the
transmit FIFO,
the host should first read the associated FIFO size
register.
1f single characters are sent,
they must be written to
the

low

byte

FIFODATA (BASE +6. DUHII MODE ONLY)

———

TX DATA CHARACTER

VvV

TX DATA CHARACTER

W
w

IWIWIWIWIWIWIWIWIWIWIWIW]|W]|W]|W

A _4

FIFODATA.

3-17

Bit

<15:0>

Description

FIFODATA<K15>

This

word

(FIFO

contains

Data

for

transmit

FIFO).

action

two

transfer

this

(W)

are

FIFO.

The

least-significant
8.

are

Unused

bits

FIFODATA

bits

byte

the

bits

must

cleared.
This

the

and
then
transferred to

the

and

After a write-word

FIFODATA<7:0>
FIFODATA<15:8>

characters

cleared

MASTER.RESET.

<7:0>

FIFODATA<T>

This

(FIFO

character
for transfer
the
transmit
FIFO,

(W BYTE)

write-byte

Data

byte

FIFODATA

contains

action
<7:0>

to
is

transferred

FIFO.

The

least-significant
1is

Unused

bits

must

The

byte

MASTER.RESET.

3-18

bit

FIFODATA

single

to
After
a
this register,

the

character

through

of
bit

the
0.

cleared,

cleared

W
W
W

available

O w

3.2.2.7
FIFO Size
low~-byte
register
in

the

(FIPOSIZE) (DRU1ll Mode Only) -- This
number
which
indicates
the space

transmit FIFO.

FIFCSIZE (READ BASE +6. DHUII MODE ONLY)
15

10D0DDDDDD
|

ALWAYS 0
L

DHUIND

FIFO SIZEO TO 64

SET TO 1. DHUII MODE

MDL SET TO 1. MODEM SUPPORT NOT PROVIDED

Bit

Name

Description

<9>

(MDL

Modem

Support

<8>

Low)

(DHUID

(R)

provided.

This

bit

- Modem support

allows

distinguish

software

between

DHU1ll mode.

<7:0>

FIFOSIZE

This

(FIFO Size)

space

(R BYTE)

transmit

DHV11l

is always

byte

indicates

(in

mode

to
and

in DHUll

the

available

characters)

FIFO.

The

00000000(binary)

the

range

01000000 (binary)
64 (decimal)).
should
be
read

(0(decimal)
to
This
register
before
sending a

character,

characters,
register.

The

characters

VvV
VUV
VW
W
W

mode

U
Tv
Vv
UV
VUV
VUV

Bit)

not

VWV

Always set
(R)

Identification

WV W

VT v

O Trv

LiRALE]

3-19

sequence

the

byte

FIFO
set

MASTER.RESET.

data
to

3.2,2.8

Line-Status Register

(STAT)

(DHV1l mode only) -~

STAT (READ BASE +6. DHVI1 MODE ONLY)
15

[
DHUID

SET TO 0. DHV11 MODE

MDL

SET TO 1. MODEM SUPPORT NOT PROViIDED
ALl

Bit

<9>

Name

(MDL

Description

Modem

Support
<8>

Low)

Always

(R)

(DHUID
Identification

(R)

set

Modem

support

not provided.
This

Bit)

bit
distinguish
DHUll mode,

mode.

3-20

allows

software
to
between DHV11l mode and
It is always 0 in DHV11

w
w
W
T

main

function

LNCTRL (BASE + 10}

3.2,2.9
Line-Control Register (LNCTRL) -- The
this register is to control the line interface.

DMA

MAINTENANCE | OAUTO | RX

MODE

ENABLE

LINK

FORCE.

TYPE

XOFF

BREAK

ABORT

IAUTO

Bit

Name

<7:6>

MAINT

(Maintenance

These
to

test

the

coding

written

programs,

the

in order

channel.

Normal
=

or test

follows:

operation

Automatic

echo

mode

Received data is looped back to the
terminal
(regardless
of the state
of
TX.ENA)
at
the
data
rate
selected
for
the
receiver.
The
received characters
are
processed
normally
and placed in the receive
FIFO.
Any
data
that
the
host
attempts
to
transmit
on
this

channel will

OCTART.

The

U
©
©
©
0

3-21

discarded

RX.ENA bit must

when operating

U U

The

bits can

driver

(R/W)

Mode)

Description

(SET TO 0)

this mode.

the
set

Bit

Name

£7:6>

MAINT

Description

10
=
Local
transmitted

(cont.)

loopback
the host is

Data
looped

back to the receive
buffer.
Data
received
from
the
terminal
is
ignored,
and
the
transmit
data
line to the terminal is held in the
mark
condition,
The
data
rate
selected
for
the
transmitter
is
used

for

both

transmission

reception.
The
TX.ENA
controls transmission in
The

RX.ENA

bit

Remote

mode,
terminal
terminal

still
mode.

ignored.

1loopback

data
1is
at

bit
this

and

=--

1In

this

received
from
the
1looped
back
to
the
a clock rate egual to

the

received

is
The

not placed in the
state ‘of
TX.ENA

clock

The

RX.ENA- bit

must

rate.

The

data

receive FIFO.
1is
ignored.
set

this

channel.
FORCE
. XOFF

XOFF)

(R/W)

(Force

This bit can
to
indicate

be set
that

by the
program
this channel is

congested at the host
system
(for
example,
if
the typeahead buffer
is full).
When it
sees
this
bit
set,
the CXAl16/CXB16 will send an
XOFF

code.

XOFFs

Until

will

the
sent

alternate
character
this
channel.
When
reset,
IAUTO

3-22

an
1is

XON will be
set and the

critical.

bit

is
after

reset,
every

received
the
bit

on
is

sent
unless
receive FIFO

Description

OAUTO

Flow)

(Outgoing Auto

(R/W)

This bit

bit

the

auto-flow

control

for outgoing characters.

set,

if RX.ENA is also

CXAl6/CXB1l6
respond
to

set,

When
the

will
automatically
XON
and
XOFF
codes

received
from
a
channel.
The
.ENA
bit
1in
CXAl16/CXB16 uses the TX

TBUFFAD2

flow.

stop

and

If DISAB.XRPT

XON/XOFF
codes
are
the receive FIFO,.

BREAK
Control)

(R/W)

(Break

not

start

the

also
set,
entered in

If
set,
this
bit
forces
the
transmitter
of this channel to the
spacing state.

Transmission is
hit is cleared.

restarted when

the

NOTE

If the line is idle,
there may be a
delay
of up to 200 microseconds
between
writing
If
the bit and the channel changing state.
a character is already being transmitted by
the
OCTART,
the
BREAK
signal
will
be
transmitted immediately afterwards.

RX.ENA

Enable)

(Receiver

(R/W)

If set,

this receiver

enabled.

If reset when this

assembling

character

The bit
%]

3-23

channel

channel
OCTART
that
character,

lost.

cleared by MASTER.RESET.

&
channels with

the

XOFF

code

this bit

set.

1If

a character is
received,
an
will
be sent when the receive
becomes less than half full.

XON
FIFO

This
bit
1is
set
by
the
driver
program
to halt data transmission.
I1f a DMA transfer was in
progress,
the DMA address and count reqgisters
(TBUFFAD1,
TBUFFAD2,
and TBUFFCT)
will
be
updated
to
reflect
the
number
of
characters
which
have
been transmitted.
The transfer can
be
continued
by
clearing
TX.ABORT,
and
then
setting
TX.DMA.START
in
TBUFFAD2.
No
characters will be lost.
DMA

following
DHV11l

mode

DHUll

mode

transmit
Because of
possible
characters
actioned.

cannot

1in

=--

FIFO

progress,

will

the

occur:

action

characters

will

1in

the

be discarded.

sequencer delays,
it is
to
transmit
a
few
before
the
abort
is
Therefore,
the
host

determine
have

been

how
lost.

many

&6 6

characters

not

actions

686 &
send

full,

becomes

FIFO

three—-quarters

transmitting

receive

CXAl6/CXB16 will

codes.

the

than

characters
XOFF

and

incoming

for incoming characters.
If it
is
set,
the CXAl6/CXB16 will control
XON

TX.ABORT
(Transmit
Abort) (R/W)

bit

the auto-flow control

1is

This

Auto

(Incoming
(R/W)

IAUTO
Flow)

Description

Name

3-24

Bit

Name

Description

TX.ABORT

When an

(cont.)

abort

completed,
set

sequence

the

has

been

CXAl6/CXBl6

will

the TX.ACTION bit

the

CSR.

If
the
transmitter
interrupt
is
enabled,
the
program
will
be
interrupted at the transmit vector.
The program
must
make
sure
that
TX.ABORT
is
clear
before setting
TX.DMA.START.
Otherwise,
the

transfer will be aborted before any
characters are transmitted.
The

3.2.2.10

bit

cleared

by MASTER.RESET.

Transmit Buffer Address Register Number 1

(TBUFFADl)

TBUFFAD1 (BASE + 12)

RWIRWIRW]IRWI[RWIRW|RW|RW|RW|RW|RW]|RW]RW]|RW|RW]|RW

]

TXMIT DMA ADDRESS
(BITSO
TO 15)

Bit

Name

Description

<15:0>

TBUFFAD<K15:0>

Bits

(Transmit

Address

[Low])

Buffer

(R/W)

3-25

<15:0>

the

DMA address.

3.2.2,11

Transmit Buffer Address Register Number

(TBUFFAD2)

=--

TBUFFAD2 (BASE + 14)
15

R'W

RWIRW|RW]RW[RW|RW

DMA

TXMIT DMA ADDRESS

TXMIT

ENABLE

START

_/]

(BITS 16 TO 21)

Bit

Name

Description

TX.ENA

(Transmitter

When

Enable)

(R/W)

CXAl6/CXBlé6

this

bit

will

set,

the

transmit

all

characters.
When
only

cleared,
transmit

flow-control

The
In

bit
the

used

characters.

set

OAUTO

the CXAl6/CXBl16 will
internally generated

MASTER.RESET.

mode,

this

the CXAl6/CXBl6

outgoing

characters.

TX.DMA.START

This

‘s

(Transmit DMA Start)
(R/W)

start
a
CXAl6/CXBl6

bit

before

The

set

DMA
will

the

After

setting

<7:0>

until

this

TBUFFCT,

cleared

the

host must

TBUFFAD1l,

the TX.ACTION

returned.

3-26

The
bit

returning TX.ACTION.

bit

bit,

host

transfer,
reset
the

by MASTER.RESET.

NOTE

write

bit

to control

report

not

or TBUFFAD2
has

been

Bit

Name

Description

<5:0>

TBUFFAD<21:16>
Buffer
{Transmit

Bits <21:16> of the DMA address.

{High]))

TBUFFAD]
transfer,
DMA
Before a
and
the
low
byte of TBUFFAD2 are
of
address
start
loaded with the
will
This address
the DMA buffer.
changing during a
continuously
be

DMA transfer and
has
no
mearning.
returned,
been
has
TX.ACTION
Once
the register contains the final DMA
transfer

wvwv

v 2w

Address
(R/W)

3-27

address.

3.2.2.12

Transmit DMA Buffer Counter

(TBUFFCT)

=--

TBUFFCT (BASE + 16)
15

RWIRW|R W]RW R'W
Wa
Ve
Vs
Vs

[ |
Ll

R'W

R-'W

RWIRW|RWIRW|RW|RW|RW]|RW|RW

L
L L Ll I LI

DMA CHARACTER COUNT
(WHEN VALID HOLDS NO. OF CHARS STILL TO BE SENT)

<15:0>

TX.CHAR,.CT
Character
(R/W)

Description

(Transmit
Count)

This word is loaded with the number
of
characters to be transferred by
the DMA,
The

number

specified
integer.
After

DMA

characters

1lé-bit

transfer

unsigned

has

been

aborted,
this
1location will hold
the number of characters
still
to
be transferred,.
See

3-28

also the

NOTE.

Name

Bit

3.3

PROGRAMMING FEATURES

Initialization
3.3.1
The CXAl16/CXB16 is initialized by

its on-board sequencers.

Initialization takes place after a bus reset sequence,
host sets CSR<5> (MASTER.RESET).

or when the

run a
the on-board diagnostics
Before starting initialization,
eight
by
reported
The results of this test are
self-test program.
The CXAl6/CXBl6

state,

after

successful

self-test,

Eight diagnostic codes are placed in the receive FIFO

The diagnostic fail bit

All

channels

Send and receive 9600 bits/s

data

(CSR<13>)

is reset

for:

bits

One stop bit

d.
e.
f.

No parity
Parity odd
Auto-flow off

g.
h.
i.

Receive disabled
Transmit enabled
No break on line

DMA

m.
n.
o.

The

Eight

set

WV
T
VvV
Vv
VUV
VUV
VUV
W
V¥V
WV
W
W

follows:

diagnostic bytes in the receive FIFO.

loopback
character

counter

zero

DMA start address register zero

TX.DMA.START cleared
TX.ABORT cleared
AUTOFLOW REPORTS enabled

CXAl16/CXBl16

clears

the

MASTER.RESET

initialization and self-test are complete.

bit

(CSR<5>)

when

3.3.2
Configuration
After CXAl6/CXBl6
self-initialization,
the
driver
program
configure the CXAl6/CXBl16 as needed.
This is done through the
and LNCTRL registers.

can
LFR

The line characteristics for a channel can be set up by writing
to
the
LPR
and LNCTRL registers associated witl, this channel.
These
are:

)

Transmit

speed

Receive

Number of stop bits

Parity

Character

Flow control

Normal

Receiver enable/disable

speed

type or parity disabled
length

characteristics

or maintenance mode

NOTE

RX.ENA

character
character

is
will

3.3.3
Transmitting
Each CXA16/CXB16 channel
by

DMA

module

for
under

reset

can

transmission,

while

being
be lost.

set

3-30

received

that

to transfer

or characters

program control.

assembled,

can

the

characters

transferred

the

TM
w+w&W-s@w
T
W
W
W
W
WV
W
W
VvV
v
UV VYV VUV
U
VU
W
OV
VOV
O
O
O
¢
©
O
O
O
o

3.3.3.1
DMA Transfers =-- Before setting up the transfer of
a
DMA
buffer,
the program should make sure that TX.DMA.START is not set.
TBUFFCT,
TBUFFAD1l,
and TBUFFAD2
should
not
be
written
unless
TX.DMA.START

clear.

Transmission starts when the program sets TX.DMA.START.
DMA buffer
size
and
start address can be written to TBUFFCT,
TBUFFADl1l,
and
TBUFFAD2 in any order.
However,
TBUFFAD2
contains
TX.ENA
and
TX.DMA.START,
so it is probably simpler to write to TBUFFAD2 last.
By using byte operations on this register,
TX.ENA and TX.DMA.START
can

separated.

The CXA16/CXB16 will perform the transfer and set TX.ACTION when it
is
complete,
If TXIE is set,
the program will be interrupted at
the
transmit
vector.
Otherwise,
TX.ACTION
must
be
polled.
TX.ACTION is not returned until the UART has completely transmitted
the

last

character of

the DMA buffer.

To abort a DMA transfer,

the
program
must
set
TX.ABORT.
The
CXAl6/CXB16 stops transmission and updates TBUFFCT,
TBUFFADl,
and
TBUFFAD2 <7:0> to reflect the
number
of
characters
transmitted.
TX.DMA.START
will
be
cleared.
If
interrupts the program at the
transmit

clears TX.ABORT and sets TX.DMA.START,

without

loss of

TXIE
1is
vector.

transfer can

failing

continued

characters.

If
a
DMA
transfer
fails
because
of
a
transmission
will be terminated.
TBUFFAD]l
to the

set,
TX.ACTION
If
the
program

location.

TBUFFCT will

memory
error,
the
and TBUFFAD2 will point

be cleared.

3.3.3.2
Programmed I/0 (DHV1l Mode) -- Single
trensferred
through a channel TX.CHAR register.
the DATA.VALID bit must be written as defined in

characters
are
The character and
Section
3.2,2.3,

Note

can be written

that

the

separate MOVB

character

and

the DATA.VALID bit

instructions.

The CXAl6/CXBl6

returns

TX.ACTION

character from TX.CHAR.

when

the

module

removes

This will generate an interrupt

the

if TXIE

set.

NOTE

single-character

returned

when

character,

mode,

TX.ACTION

the CXAl6/CXB16 accepts the
not

when

has

been

transmitted.
Each channel can buffer up to
three characters.
Therefore,
if
line

parameters

are

changed

immediately after

the last TX.ACTION of a message,
the
end
of
the
message could be lost unless three
null characters are added
to
the
end
of
each

single-character

programmed transfer

message.

3.3.3.3
or

Programmed I/0

sequence

(DHUll Mode)

characters

should read the FIFOSIZE
the transmit FIFO.
If

there

character)
write,

enough

or words

FIFODATA

write,
FIFODATA

space,

to the

-~- Before writing a
FIFODATA register,

characters

(two characters)

<7:0>

can

that

there

transferred

the

FIFO.

returns TX.ACTION when

the

space

(one

low-byte

After

transmit

bytes

After

FIFODATA
<7:0>
is
transferred to the FIFO,
<i5:8>,
High-byte writes to FIFODATA are not

The CXAl6/CXB16

the program

be written

to FIFODATA,

character

word

followed
allowed.

FIFO

becomes

empty.
An
interrupt
will
also be generated if TXIE is set.,
As
distinct from DMA
mode,
in
programmed
1/0
mode
TX.ACTION
is
returned when the CXAl6/CXBl6 transfers the last character from the
transmit FIFO to the OCTART,
not when
it
has
been
transmitted,
Thus,
if
1line
parameters are changed immediately after the last
TX.ACTION

program
end

can
each

message,

avoid

the

this

programmed

end

loss

transfer

the

adding

FIFO

3-32

message

could

two null

message.

lost.

characters

The

the

3.3.4

Receiving

Received

characters,
tagged
with
the
channel
number,
error
information
and
DATA.VALID,
are
placed
in
the
receive FIFO,
RX.DATA.AVAIL is clear when the
receive
FIFO
is
empty.
When a
character is put into the empty receive FIFO,
the CXAl6/CXBl6 sets
RX.DATA.AVAIL.
A receive interrupt is generated if
RXIE
is
set,
RX.DATA.AVAIL
stays
set
while there is valid data in the receive
FIFO.
It
is
recommended
that
the
receive
character
routine
continues to read characters from the receive FIFO until DATA.VALID
is

clear.
NOTE

The interrupt is dynamic.
RX.DATA.AVAIL
1is
RXIE is set after

interrupt
routine
does
receive FIFO,
RXIE
must
raise
another
interrupt.
the interrupt is generated
(set by RX.TIMER).

RXIE

prevent
3.3.5

is not set,
data

is raised

set
after
RXIE,
or as
RX,.DATA.AVAIL.
If
the

the program must

not
be

empty
the
toggled
to
In DHUll mode,
after
a
delay

poll

RBUF

often

enough

loss.

1Interrupt Control

The CXA16/CXB16 provides one of two vector addresses during
a
bus
interrupt
sequence.
The receive vector addresc is the address set

up on the vector address switches.
the

receive

vector

The

receive

interrupt

is set

and

RXIE

receive

RXIE

contains

address

The transmit vector address

generated when

character

pliced

into

empty

FIFO

changed
one

from

or more

and

the

characters.
NOTE

In DHU1l

mode an

either

immediately,

set

interrupt

generated

or after the delay

RX.TIMER,

3-33

receive

FIFO

The

transmit

interrupt

TXIE

set

TXIE

changed

vector

and

is generated when:

TX.ACTION
frcm

becomes
to

set

while TX.ACTION

set

NOTE

The

TX.ACTION

FIFO

reports,

can

hold

but

only generated when
the
FIFO
TX.ACTION
after
being
empty.

is recommended that your

interrupt

receives
a
Therefore,

program

reads

the
CSR
until
the
TX.ACTION bit becomes
clear.
Reports will be lost if
more
than
16 have accumulated.
At

the

two

vectors,

the

routines

DHUll

mode,

interrupt

put

into

3.3.6
XON

empty

XOFF

characters

communications

receive

FIFO,

channel

characters

using
until

must

the

provide

above

the

addresses

conditions.

generated

either

after

hardware

control

receives

CXAl6/CXBl16

commonly

flow

received data sends
receive more data,

programmed

are

channels.

suitable decoding

The

with

immediately

a delay,

set

data

RX.TIMER.

data

flow

Auto XON and XOFF

and

have

deal

host

suitable

wuse

that

control

facility,

interfaces

must

software.
receives

XOFF

stops

sending

an XON.
A channel becoming overrun by
It sends an XON when
it
can
safely

XOFF.

flow control

automatically

accordingly

used

this

enabled.

controls

(auto-flow).

function:
o

TAUTO

LNCTRL<1>

FORCE.XOFF

LNCTRL<5>

]

OAUTO

LNCTRL<4>

]

DISAB.XRPT

LPR<O>

3-34

Four

character
bits

flow

when

control

this

W
w
W
Vv
W
W
Vv
T
'
VvV
Vv
VY
IV
V'V
VUV
V

incoming characters.

IAUTO is an

bit
which
allows the level of the receive FIFO to control
the generation of XOFF and XON characters.
The FORCE.XOFF bit is a
direct
command
from
the
program
to
control
the incomimg data
stream,

The CXAl16/CXBl16

hardware

recognizes when

is three—-quarters full and half
states for auto-flow control.
Each channel

has

a separate

full.

the

receive

The

logic

uses

there

are

IAUTO bit.

FIFO
these

191

more
characters
in
the re<cive FIFO,
and a character is
received on a channel with IAUTO set,
an XOFF character is
sent.
If
the
channel does not respond to the XOFF,
the
CXAl6/CXB16 will send another XOFF
in
response
to
every
alternate character received.
An XON will be sent when the
receive FIFO contains less than 128 characters,
unless the
FORCFE.XOFF bit for that channel is set.
XONs are only sen:
to channels to which an XOFF has previously been sent.

By inserting XON and XOFF characters into the data
stream,
the
program
can
perform flow control directly.
However,
if the CXA16/CXBl6 is In IAUTO mode,
the results
will
be
unpredictable.
In

TAUTO mode,

will be
When

FORCE.XOFF

then

acts

(was

than half

RX.ENA

transmitted even

critical
sent

the

set,

the

program

XON

1is

receive

FIFO

set

sets

and

reset,

critical

OAUTO,

sends

the

XOFF

and

the receive FIFO is

and

to XON and
by clearing

characters

is cleared.

full,

FORCE.XOFF

automatically
respond
channei.
It does this

and XOFF

the CXAl6/CXBl16

IAUTO

When

set,

if TX.ENA

three~quarters

full).

unless

and

not

yet

less

an XON will be
IAUTO

set.

CXAl6/CXB16

will

XOFF characters from the
or
setting
the
TX.ENA

bit.

The program may also control the TX.ENA bit,

1in

this

case

received

XON

and

XOFF

always

reported

important

keep

Received

through

XON

the

set,

program,

the

and XOFF

receive

characters

FIFO,

possible,
for

unless

during

the

will

the

DISAB.XRPT

read-mcdify-write

CXAl16/CXBl16

change

bit

|is

operations
the

TX.ENA

bit
between
the
read
and
the
write actions.
For this
reason,
if DMA transfers are started while OAUTO
1is
set,
it is advisable to write to the low byte of TBUFFAD2 only.

UV
U
T

track

characters.

VvV

VUV

IAUTO and FORCE.XOFF both control

enable

3-35

received

set

and OAUTO

NOTES

The CXAl16/CXBl16 may change the state of

TX.ENA

for

microseconds

after

OAUTO is cleared by the program.

guarantee

overrun

O Ny

not

absolutely

will

not

occur.

transmission

and

reception

errors

WYY

Auto flow-control does

2.
When
checking
for
flow~control
characters,
the
CXA16/CXBl6
only checks
characters
which
do
not
contain
transmission
errors,
The
parity
bit is
stripped,
and
the
remaining
bits
are
checked
for
XON
(21(octal))
and
XOFF
(23(octal)) codes.

CSK1i2>,

PARITY.ERR

RBUF<12>,

FRAME .ERR

RBUF<13>.

OVERRUN.ERR

RBUF<14>,

code.

diagnostic

identify

also

may

errors.

program

YWY

the

TX .DMA .ERR

RBUF<14:12>

Indication

inform

WYy

Error
bits

3.3.7

These
errors
may
still
occur
if
the
transmitting
devices do not respond to the
XOFF immediately.

Four

UGy

or XOFF
characters
When DISAB.XRPT
filtering is enabled.

this

XON

discarded,

YWYy

are

3-36

control whether
channel

If DISAB.XRPT is clear,
XON and XOFF
characters
will
processed as- normal characters and entered into the receive
FIFO.
DISAB.XRPT allows the individual line OAUTO bits to

3.3.8
Maintenance Programming
The host can set bits 7 and 6 of

LNCTRL to allow each channel

to be

configured in normal,
automatic echo,
1local loopback,
and remote
loopback modes.
These modes allow an individual data channel to be
looped
back
to the host,
or to be looped back to the terminal to
assist

isolating

communication problems,

The host must provide

3.3.9

suitable software

to use

these modes.

Diagnostic Codes

3.3.9.1

Self-Test Diagnostic Codes -- After

bus

reset

master

reset,
the
CXAl16/CXBl6
executes
a self-test and initialization
sequence.
During the sequence,
eight diagnostic codes are put
in
the

receive FIFO,

and RX.DATA.AVAIL

is set.

After
an
error-free
‘diagnostic
passed’

test,
DIAG.FAIL
LED
will
be
on.

DIAG.FAIL

and

will

set

the

LED will

will
be
reset
If an error is

and
the
detected,

be off.

3.3.9.2
Interpretation of Self-Test Codes -- The
high
byte
of
diagnostic
codes in RBUF can be interpreted as in Section 3.2.2.2,
except that bits <11:8> are not the line rumber.
They indicate the
sequence
of the diagnostic byte,
that is to say,
0 = first byte,
1 = second byte,
and so on.
Table 3-4 shows the meaning
of
each
of

the

error

codes.

Table 3-4

Code

CA{Al6/CXBl16 Self-Test Error Codes

Test

(Octal)

bits<7:0>

201

Self~test

null

203

Self-test

skipped

211

Low OCTART

error

213

High OCTART

225

RAM

error

codes

All

other

code

(used as

treated

filler)

error

should

undefined

error

If bit 7 = 0 and
circuit revision
3it

that

always

the

reads

circuit

Bit

control,

bit 0
=
1,
information

indicates
1

for

contains
to which
=

OCTART

the

then bits

<5:2>

CXAl6/CXB16,

and

control
chip

the

and OCTART

contain

indicates

chips

information

refers:;

After self-test,
the eight FIFO codes consist
of
six
diagnostic
codes
and
two circuit revision codes.
1If there are less than six
errors to report,
null codes (201(octal)) fill the unused places.
After an error-free test,
codes will be returned.

six

Self-test

to shorten

Section

may

'skipped’'

null

codes

and

the

two

circuit

revision

initialization cycle

(see

3.3.9.3).

The module is still tested,
even if
self-test
1is
skipped.
The
reset
delay
is
much shorter,
but test coverage is not affected;
therefore skipping self-test is advantageous.

After 'skip seif-test’ self-test,
the eight FIFO codes consist
six
diagnostic codes and two circuit revision codes.
If there
less

than

six

errors

report,

203(octal)

codes

fill

of
are
unused

the

places.

After an
revision

error-free
codes will

3.3.9.3

Skipping Self-Test

set

SKIP

(CSR

simultaneously,
SKIP
was

must
set,

sequence

can

mode

DHV1]l

method

that

not
SKIP

test,
six 203(octal)
be returned.

be
must

bit
is,

DHUll

write

cleared

and

mode only,

and

two

the

MASTER.RESET

60(octal)

until

cleared

circuit

method

(CSR

the

CSR

least

microseconds

the

host

that

DHUll

the

bit

after

master

reset

complete,
(this

also

preferred)

the

The

program

The

program waits

works

following

resets

The

self-test

then

checks

finds

the

reset
found,

code,

delay
1is
the reset

or -

but

the

waits

until

052525(octal)

the

DIAG.FAIL

code

bit

after

issuing

throughout
next 4 ms.

1is

ms
in

reset,

the

after
common

cleared,

control

reset,
RAM,

and
1If

and

shortened
to
30 ms.
If the code is
delay is between one and two seconds.
NOTE

The

used:

ms)

052525(octal)
CSR) within the

sequencer
for

mode,

method

the CXAl6/CXBl6.

10 ms

and
then
writes
registers {(not the
3.,

codes

program must

not

write

the CSR,

to
the
control
registers,
during
the
period starting 15
ms
after
reset,
and
ending
when
the
MASTER.RESET
bit
is
cleared.
Writing during this period
could
cause a diagnostic fail condition.

3-38

it
the

not

305(octal)

307(octal)

=--

CXAl6/CXB16

running

CXAl16/CXBl6 defective (also LED off)

A single diagnostic word is returned to the receive FIFO.
byte contains the diagnostic code.

The

low

OVERRUN,ERR,

BMP normally only reports when it finds an
error.
However,
the
program
can
get
a
BMP
report
at
any
time
to
validate the
CXAl6/CXBl6,
This is done by
setting
DIAG
(LPR
<2:1>)
of
any
channel to 01.
The line number returned is that of the LPR used to
request

the

report.

On completing the

should

not

check,

BMP clears

write to the LPR of

the 01

code

that channel

in DIAG.

until DIAG

The host

is cleared

to 00.
3.4

PROGRAMMING EXAMPLES

This section contains programming examples of the CXAl6/CXB16
used
in
DHUI1l
mode.
Programs
for
DHVI1
mode
are included.
These
programs are not presented as the only way of driving
the
option,
and

are

neither guaranteed nor

supported.

UVYU
UYU
VU
U
UV UV
U
U
O
QO
QO

1In the high byte,

FRAME.ERR,
and PARITY.ERR are all set to indicate that
bits <7:0>
do not hold a normal character.
The line number (RBUF<11:8>) = 0.

VUV Y

VU WU

UV WU

3.3.9.4
Background Monitor Program
(BMP) -~ The CXAl6/CXBl16
BMP
logic
performs
background
self-tests
by
checking
for
OCTART
interrupts.
One or two codes are returned to the receive FIFO:

3-39

3.4.1

Resetting the CXA16/CXBl6

following example:

the

DIAG is a
routine
to
check
the
diagnostic
codes.
returns with CARRY set if it detects an error code.
The loop at
15
can
take
up
to
2.5
seconds,
programmer could poll by using a timer or poll at

so
the
interrupt

zero.

A ROUTINE TO RESET THE CXAl6/CXB16 AND CHECK THAT

level

FUNCTIONING

»s

CORRECTLY.

CXARES::

#40,@#CXACSR

BIT
BNE
BIT

#40, @¥CXACSR
1%
#20000, @#CXACSR

BNE

DIAGER

50B

R5,2$

RTS

%
W9
WY

DIAGER

BCS

PC,DIAG

@#RBUFF,RO

JSR

BIT.

NOTE:TEST
NO TX.ACTS

MOV

INTERRUPT

ENABLES.

SET

GET

PROCESS

INSTRUCTION

BECAUSE THERE

ARE

PENDING.

A COUNT.

2S5:

#8.,R5

CLEAR

WAIT FOR MASTER.RESET TO
CLEAR.
CHECK THE DIAGNOSTICS FAIL

MOV

SET MASTER.RESET AND

1$:

MOV

DIAGNOSTIC

CARRY SET
AN ERROR.
GO

BACK

MUST

HAVE

FOR

CODE.

CARD

CXAl6/CXB16

THE

HAS

FAILED TO

SERVICE

RESET

PROPERLY,

ENGINEER.,

FI ELD

DIAGER:

HALT

DIAGER

3-40

SO HALT

BEEN

RESET.

“e

RETURN

CODE.

IT.

AND WAIT

FOR

3.4.2

Configuration

MOV

$#052560,@4LPR

MOV
MOVB

#4,@$LNCTRL
#200, @¥#TBFAD2+]

RTS

LOAD INDEX REG
WITH CHANNEL NO.
DATA RATE, STOP BITS,
PARITY AND LENGTH.

#1,84#CXACSR

MOV

SETUP::

Transmit and receive at 300 bits/s
Seven data bits with even parity and one stop bit
Transmitters and receivers enabled
No automatic flow control.

.
.
.
.

oW
N -

This routine sets the characteristics of channel 1 as follows:

ENABLE THE RECEIVER.
ENABLE THE TRANSMITTER.

RETURN - CHANNEL

DONE.

3.4.2

Transmitting

3.4.3.1
Programmed Transfer (DHUll Mode)
program to send a message on channel 1.

=-- The

following

The CSR is polled for TX.ACTION reports,
could also be used.

but a TX.ACTION

is a

interrupt

This program would

function on a CXAl6/CXB16 with only this channel
active,
Otherwise
it
would
1lose
TX.ACTION
reports
of other
channels.
However,
a program to control all channels would be too
big to use as an example.

A ROUTINE TO WRITE A MESSAGE TO CHANNEL

MODE

USING

FIFO OUTPUT

(PROGRAMMED TRANSFERS).

FIFOUT::

MOV

1$:

#1,8#CXACSR

POINT TO CHANNEL WE WISH

TO TALK TO.

POINT TO MESSAGE.
PUT COUNT IN.

MOV
MOV

#MESS,RO
#MESIZE,R1

:
s

TSTB

G4#FIFOSIZE

CHECK THAT THERE IS SPACE 1IN

BEQ
MOVB

18
(RO)+,@#FIFODATA

:
:

THE FIFO.
MOVE CHARACTER TO TRANSMIT

SOB

R1,15

GO BACK FOR NEXT CHARACTER.,

MOV

@#CXACSR,R2

WAIT

BPL

25
s+

ISOLATE CHANNEL NUMBER.

:
:

IGNORE THE TX.ACT IF IT IS
NOT OURS (SHOULD NOT HAPPEN).

MESSAGE

FIFO.

2S:

BIC

#170377,R2

CMP
BNE

#000400,R2
2S

RTS

MESS:

.ASCII

/A TRANSMIT

MESIZE

«~MESS

FOR TX.ACT.

SENT,

FIFO MESSAGE FOR CHANNEL

. EVEN

3-42

3.4.3.2

sSingle-Character Programmed Transfer (DHV1l Mode) -~ This
is a program to send a message on channel 1.
The message (MESS) is
an A5CII string with a null character as terminator.
Polling

is used,

but

a TX,ACTION

interrupt could also be

used.

This program would function on a CXAl6/CXBl16 with only this channel
active.
Otherwise
it
would
1lose
TX.ACTION
reports
of other
channels.
However,
a program to control all channels would be too
to use as an example.

MODE.

USING SINGLE-CHARACTER

A ROUTINE TO WRITE A MESSAGE TO CHANNEL 1

big

LOAD INDEX REG WITH

CHANNEL

MOV

#MESS,RO

SINGOT
: :

MOV

#1,@8CXACSR

POINT

MOVB

(RO)+,@#TXCHAR

MOVE CHARACTER TO TRANSMIT

NO.

MESSAGE.

15:

BEQ

BUFFER.

GO RETURN

GONE,.

IF ALL CHARACTERS

MOVB

#200, @#TXCHAR+1

SET

DATA VALID BIT TO START.

MOV
BPL

@#CXACSR,R1
28

;

WAIT

BIC
CMP
BNE

#174377,R1
#000400,R1

ISOLATE CHANNEL

IGNORE THE TX.ACT IF
NOT OURS (SHOULD NOT

;:
;
;

GO BACK

FOR NEXT

RTS

MESSAGE

SENT,

.ASCIZ

/A SINGLE-CHARACTER MESSAGE

2S5:

TXI

FOR TX.ACT

NUMBER.

3$:

MESS:

FOR CHANNEL

IT IS
HAPPEN)

CHARACTER.

THE MESSAGES ARE TRANSMITTED USING DMA MODE,
USED TO SIGNAL TRANSMISSION COMPLETION.

AND INTERRUPTS

ARE

THIS PROGRAM SENDS A MESSAGE OUT ON EACH LINE OF THE CXAl6/CXBl6
AND HALTS THE MACHINE WHEN ALL TRANSMISSIONS HAVE COMPLETED.

INC
SOB

R1
RO,1$

wma
we

ZERO.

SELECT THE REGISTER BANK.
SET LENGTH OF MESSAGE.

SET

START

ENABLED

(ASSUME

BITS ARE

ZERO).

W2
wg

#100200, @4TBFAD2

LINE

MOV

LINES TO START.

MOV

R1,Q@#CXACSR
#DMAS1Z, @#TBFCNT
#DMAMES
, @#TBFADI

MOV

START

B¢

MOVB

SIXTEEN

SET UP THE INTERRUPT VECTORS.
INTERRUPT PRIORITY FOUR.

LOWER

16 ADDRESS BITS.

DMA WITH

CLR

MOV

POINT

MOV

NT
, @$TXVECT
#TXI
#200,@#TXPSW
$16.,R0O

MOV

DMAINT::

REPEAT

TO NEXT

TRANSMITTER

UPPER ADDRESS

CHANNEL.

FOR ALL

LINES.

CLR
MOVB

£100, @#CXACSR+1

ENABLE TRANSMITTER

CMP

#16.,R5
25

WAIT

25
BNE

USED BY

FOR ALL

INTERRUPT

LINES TO

3s:
BR

-e

HALT

3-44

ALL

DONE,

STOP.

ROUTINE.

INTERRUPTS.

FINISH.

wP
we

ROUTINE.

R5 IS

INCREMENTED AS EACH LINE COMPLETES.

-f

TRANSMITTER INTERRUPT

TXINT::

MOV

BIT
BEQ
BIT
BNE

@#CXACSR,RO
#100000,RO
45

#010000,R0O

; GET LINE NUMBER OF FINISHED LINE.
; CHECK FOR (ANOTHER) TX.ACTION.
;

IF NOT, GO RETURN AND WAIT.

;

CHECK FOR DMA FAILURE.

;

GO HALT - MEMORY PROBLEM.

INC

;

FLAG THAT ANOTHER LINE HAS FINISHED.

TXINT

;

MEMORY PROBLEM.

; NOT USED IN DHV11 MODE.

RTI

58:
HALT

:
DMAMES

+ASCII

<15><12><7><7><7>/SYSTEM CLOSING DOWN NOW/
.-DMAMES

DMASIZ

.EVEN

Aborting a Transmission --

ROUTINE IS CALLED TO ABORT A
TRANSMISSION
FROGRESS
ON A SPECIFIED LINE.
THIS
1IN

(RATHER RASH)
PROGRESS
.

ASSUMFPFTION THAT THERE ARE

(EITHER
OMA
OR
ROUTINE MAKES THE

OTHER

TRANSFERS

ENTRY,

RO CONTAINS THE

NUMBER OF THE

LINE TO

BE ABORTED.

TMe

FIFO)

THIS

3.4.3.4

ASSUMPTION WAS WRONG!)
CLEAR
FOR

BUFFER

DMA

REGISTERS

THE

CXA16/CXB16

DOWN THE

LINE,

NOT

ABORT

(OUR

FLAG

NEXT TIME.
COMPLETELY

DMA WAS

ABORTED,

PROGRESS,

REFLECT

THE

WHERE

HAD GOT TO.

IGNORE

IS OUR

RTS

#1,8#LNCTRL

3-46

BIC

-e

RO,R1
1s

BNE

CMP

CHECK

-e

$177760,R1

BIT,

FOR THE TX.ACT.

BiC

WAIT

SWAB

1$
R1

ABORT

@#CXACSR,R1

BPL

THE TRANSMIT

MOV

1S:

POINT TO THE CHANNEL TO BE ABORTED.
SET

RO, @#CXACSR
#1,@#LNCTRL

BIS

MOV

TXABRT::

Receiving

THIS ROUTINE PROCESSES RECEIVED CHARACTERS UNDER INTERRUPT CONTROL.
IF AN XOFF IS RECEIVED, THE TRANSMITTER FOR THAT CHANNEL IS TURNED
OFF. IF AN XON IS RECEIVED, THE TRANSMITTER IS TURNED BACK ON.
ALL
OTHER CHARACTERS ARE IGNORED.

wWE

3.4.4

ENABLE

STARTING AT CHANNEL
SELECT THE

"0
WTME

#16.,R0
R1

SET UP THE INTERRUPT VECTORS.
INTERRUPT PRIORITY FOUR.

NT
, @#RXVECT
#RXI
#200, @#RXPSW

ZERO.

SELECT

SET

NOT USED IN DHV1l MODE.
ENABLE THE RECEIVER
RETURN

W
-e

#0, @#CXACSR
$20,,@#RXTIMR

MOV

MOVB

RO, 1S

MOVB

#100,Q@#CXACSR

RTS

LINE.

ENABLE THIS RECEIVER.
SET POINTER TO NEXT CHANNEL.

SOB

BIS

-e

INC

R1l, @#CXACSR
#4,Q#LNCTRL
R1

MOVB

-e

W
WV
v
v
VUV
UV
vV
U
VvV
v
U
Vv
Vv
U9
O
VvV
P

ALL THE RECEIVERS,

16:

MOV
MOV
CLR

MOV

‘up

RXAUTO:
:

CHANNEL ZERO,
DELAY TO 20MS.

INTERRUPTS.

INTERRUPTS

DO THE

RESET.

INTERRUPT

ROUTINE TO

DO THE MAIN TASK,

RKINT
::
-e

RO
@#RBUFF,

GET THE CHARACTER.

BPL
MOV

RXIEND

$107777,(SP)+

BNE

RXNXTC

BIC

$#170200,R0

SWAB

BIS

#100,R0O

Movse

RO, @#CXACSR
RO
#21,R0
1$

e
we
w8

BISB

#200,24TBFAD2+1

RXNXTC

BNE

cMPB

SWAB

BIC

wme

MOV

RO,-(SP)

SAVE CALLER'S

MOV

RXNXTC:

#23,R0

BNE

RXNXTC

DATA VALID,

- JUST

HAVE

FINISHED,

IGNORE THEM

(BAD PRACTICE).

REMOVE

UNNECESSARY BITS.
POINT TO THIS CHARACTER'S

(ADD THE INTERRUPT

LINE.

ENABLE BIT.)

PUT CHARACTER BACK IN LOWER
WAS IT AN "XON"?
NO - GO CHECK FOR AN "XOFF"

BYTE.

ENABLE THE TRANSMITTER.,
GO CHECK FOR MORE CHARACTERS.

CMPB

CHECK FOR ERRORS AND
DIAGNOSTICS CODES.

WAS

-y

1$6:

REGISTERS,

IT
~

"XOFF"?

GO CHECK

BICB

#200,@#TBFAD2+1

DISABLE

RXNXTC

MOV

(SP)+,R0O

RESTORE THE

CHECK

FOR

CHARACTERS.

THE TRANSMITTER,

FOR MORE

CHARACTERS.

RXIEND:

RTI

3-48

DESTROYED

Wy
WE
WE
WE
WE

THE MESSAGES ARE TRANSMITTED USING DMA MODE, AND INTERRUPTS ARE
USED TO SIGNAL TRANSMISSION COMPLETION.

AUTOMATIC FLOW CONTROL IS ENABLED ON THE OUTGOING DATA.

MOV

INT
, @#TXVECT
#ATO
#200, @#TXPSW
#16.,R0

CLR

MOVB

R1,@#CXACSR

BIS

#24,@4LNCTRL

MOV

#AUTOSZ, @#TBFCNT
1
S
, @#TBFAD
#AUTOM

INC
SOB

R1
RO, 1$

CLR

W
WE

#100200,@#TBFAD2

SET LOWER

16 ADDRESS

POINT TO

NEXT CHANNEL.
FOR ALL LINES.

R5 IS USED BY INTERRUPT ROUTINE.
ENABLE TRANSMITTER INTERRUPTS.

WAIT

ALL

FOR ALL LINES TO

3S:
HALT
BR

BITS.

START DMA WITH TRANSMITTER
ENABLED (ASSUME UPPER ADDRESS
BITS ARE ZERO).

-e

BNE

SELECT THE REGISTER BANK.
ENABLE AUTOMATIC FLOW CONTROL
ON THE TRANSMITTED DATA.
SET LENGTH OF MESSAGE.

REPEAT

#100, @#CXACSR+1

CMP

SIXTEEN LINES TO START.
START AT LINE ZERO.

-9

MOVB

28:

SET UP THE INTERRUPT VECTORS.
INTERRUPT PRIORITY FOUR.

WME

MOV

W
v

MOV

UV
UV

1S:

MOV

-y

TXAUTO:
:

AND HALTS THE MACHINE WHEN ALL TRANSMISSIONS HAVE COMPLETED.

Auto XON and XOFF

THIS PROGRAM SENDS A MESSAGE OUT ON EACH LINE OF THE CXA16/CXBl6

3.4.5

DONE,

SO STOP.

FINISH.

we
w3
we

INTERRUPT

ROUTINE.

R5 IS INCREMENTED AS EACH LINEVCOMPLETES.

wmEg

TRANSMITTER

ATOINT
: :

MOV

Q@¥CXACSR,RO

;

GET LINE NUMBER OF FINISHED LINE.

BPL

NOT

RETURN

1F NGQG MORE TX.ACTIONS.

USED IN DHV11 MODE.

BIT
BNE

#10000,RO
4

;s
;

CHECK FOR DMA FAILURE,.
GO HALT - MEMORY PROBLEM.

INC

FLAG THAT

;

CHECK

NOT

;

MEMORY

ATOINT

ANCTHER

FOR MORE

LINE

HAS

TX.ACTIONS.

USED IN DHV11l MODE.

2S:
RTI

4S5
HALT

PROBLEM

AUTOMS:

.ASCII

<15><12><7><7><7>/SYSTEM CLOSING

AUTO0SZ

.—=AUTOMS

.EVEN

3-50

DOWN

NOW/

FINISHED,

.4.6

Checking Diagnostic Codes

THIS ROUTINE CHECKS THE DIAGNOSTICS CODES RETURNED FROM THE
CXAl16/CXB16 ON ENTRY,

RO CONTAINS THE CHARACTER RECEIVED FROM THE

DIAGEX

CMPB

#203,R0

BEQ

DIAGEX

CMPB

#305,R0

BEQ

DIAGEX

#201,R0O

BEQ

SEC

DIAGXX:

VYV

VUV

VvV

VFV

DIAGEX:

VvV

DIAGXX

-e

DIAGEX

-e

BEQ

CMPB

-e

#200,R0O

BITB

-e

(sP),R0O

MOV

IF NOT,
GET THE

-e

DIAGEX

CHECK FOR ROM VERSION

L1}

BNE

CHECK THAT

SELF-TEST

#107776 ,RO
#070001,R0O

SAVE THE CODE

SELF-TEST

-e

BIC

CMP

RO,-(SP)

MOV

FAILURE.

CXA RUNNING CODE,

~-e

FOR

ALL THE REST ARE ERRO:l CODES.

e w3

SET

WTM

CXAl6/CXB16, ON EXIT, THE CARRY BIT WILL BE CLEAR FOR SUCCESS,

FOR LATER.

IS A DIAG.

JUST

EXIT NORMALLY.

CODE

BACK.

MOV

(SP)+,R0O

RTS

NUMBER.

NULL CODE.

SKIPPED CODE.

AN ERROR CODE WAS RECEIVED,
SET THE

CARRY

EVERYTHING OK,

CLC

CODE,

FLAG.

SO CLEAR CARRY.

RESTORE THE CHARACTER/INFO.

ARXAXRAARXXARRAARXAARXRRARXRXRXXRXARKAXXXAKAXXXARNXKXXRA
ARRAXRXARRRX LKA AR RAA XA XXX X AR R AR KX XX AR XX ARRXXKRAX

AARKARXKX XXX ARKARRXARXKXX XX AR X UARXAXXAXRAXRXARXXXXX
AA
AAXR XXX XRAXAXXX
RXAXRERA
ERXKAXAAAKXARKAKRKAKHXXAAR
AARRXRRXX XXX KXARREXRAA XK XXX XARKXRXAXXAXXKXXXX
XXX XX X
AAXRKERAAR KKK XARAAARAAAXAAKXKXXXXARX
XX
ARARA
K XRARARRA XXX RRAARKXAAXXK
ARXARKK
XARUR
AXRXAAAXXRKAXK
AR UX XX XXX XXX KXRXRAAXXARR
AN XX
KARAAXRXAXXARXRKXRXAXRARRAXRAXAXARX
AEAAXARXXXXAXRRARXXAARXAAXX
XXX XARKK X

KARXRA XX AXREURAAXRUXXRRXAXXRKXAXR
AARKXXAREAXKXKARRKARXAARAXAXXXAAXXX
AAXAXARKR
XXX AREAAXXAXKE XX XAK
XARXKXXARXAUAXAURKKAKXXXAXAXRAX
AAXRXKXARLKAX
AKX RXXAXXAXKXXX

AERXAXRXXAAREAARXAXXXKRX
XKXARXAXKXRXXXAXXXAEALX
AERXAXAXXARXAREXXR
XK AXRX
XARXXXEAAXXX

132 2932334882
AAAXAAXARAXAR

AXXRXXXKRKX
XHXARKX

;

AAXXX
XXX

XXX
XXXXX

AXEXEAXX
ARXAXAXXAX

AXXXXXXXKXX
XAXXXAXAXXXAX

XXX
AAX
XXX
XXXXXX
AAXXXAXXAXRAXXAAX
ARXARXXAXRXARKXXXAXX
XXXXXARXKAAXXXXXRAXXXAX

EARXARXAAAXAXKAXXKXXXXXKX

XX
XXXXRKAAXKARXXAXRXKXRXAXXKX
KAAXXARXXAXXXRXRAXXRARKAXXXAX
XXRUXRRXXXXARXALXXAXXRXKARLXRLAEX
LUAA
XX KXLXXAXXAXX
REXRAXRXARARAARX

RXX
XXX ARXAXRKAXXAXX
ARARXXARKEUAXRRKAAXE

AXARARXARXERXKEXRKERKXXRAARXAXAXARXXXXX

X
RRARXXARKXAR
R ARRARXRXR
EXARAARRARXARXXAAXXLX

X
AARKX
XXX XXXAAXKA
KXXXARXARXXXRXARXRXXXXXX
X
ARK
AARRARKA
R
R
XURXX
XXX
EAXRARARXRXRXAXKARXR

E
XXXX
AXX
RKXXRXA
HXR
RXXXXAA
AXX
XX RXAARKX
KAXXXXXXX
HEXXARAXXXXXXXRXXAARXXXRXARAXXXARRXARXXXXXXAXKXXX
X
KXXK
RXXXR
XA XKXXXXX
ARXKA
XXX
AAXRXAXXXRKXARARXXAXXXRXA
X
XRXR
AXXKXXXRKX
AKX
XXAXRR
XA
AXAXXR
REAXKX
KXXRAX
XARXXX
ERXARX
K
RXAX
XRXXXXXXA
XAR
XAXKXXXRX
RXX
XXRXHXARX
XXX
XXRXRAXRX
XX
RXXRAX

CHAPTER 4
TROUBLESHOOTING

4.1

SCOPE

This chapter explains how to isolate the cause of a
communications
problem
between
the
CXAl6/CXBl16 and the equipment to which it is
connected.
4.2

TROUBLESHOOTING

4.2.1

Preventive Maintenance

No preventive maintenance
should always ensure that
all

the

Make

connectors

sure

easily
is

are

that all

identify

secure.

cables

are clearly

which channel

assnciated with

4.2.2

is needed for this option.
However,
you
all cables are clear of danger,
and that

each

that

you

can

terminal.

Troubleshooting Procedures

Troubleshooting procedures are to
caused

identify whether the

problem

by:

)

The module

The

terminal

First,

decide whether
of

channels,

If all channels
module.
Also
CXAl6/CXBl6.,

group

cabling.

labeled,

number and which CXA16/CXB16 module

the

all

is associated with one

channel,

channels.

are faulty,
run the user diagnostics to
test
the
check
whether
your
software has a driver for the

group of eight

between

the problem

module

channels
and

the

cable

faulty,

check

concentrator.

the BCl6D-25

cables

For single-channel
Check

for

Verify

problems:
loose

that

necessary,

cables and

the

swap

connectors.

terminal

1is

working

correctly.

Verify that the signals from the terminal are reaching
CXA16/CXB1l6 by using the H3101 test connector,.

it with another one.
the

Check which CXA16/CXBl6 line is suspect and
disconnect
the
appropriate
36-way
connector
at the CXAl6/CXB16
bulkhead.
NOTE

This

interrupts

the other

seven

lines

using

that connection.

Connect
Figure

Type

the cable to the H3101

loopback

connector

(see

4-1).

characters

the

terminal

connected

suspect
line.
I1f characters are echoed back when
H3101
is
connected,
the
cable
and
terminal

the
the
are

working.

Rectify

the cable
not,
make
sure
run
correctly,
selected
for
characteristics.

terminal fault,
if there is one.
If
that the user diagnostics for the module
and
that
the
communication
parameters
that
channel
match
the
terminal's

4-2

H3103 w LOOPBACK
CONNECTOR
o
D
rMvYPYP r1 OO

H3104

CABLE CONCENTRATOR

H3101 LOOPBACK

CONNECTOR

CXA16

BC16D-25
CABLE

Figure

4-1

Cable

4-3

Loopbacks

A
reset.,

immediately after the Q-bus or module has

It performs a comprehensive

internal logic test,

been

but does

not
test the Q-bus interface or serial-line drivers and receivers,
The self-test gives a GO/NO-GO indication via the DIAG.FAIL bit and
the
'diagnostics
passed'
LED
on the module.
The self-test also
reports error or status information to the
host
via
the
receive

Self-test provides a high level of confidence that the majority
of
the
module
1logic
is
working.
The user diagnostics must also be

the
host
via
the
'diagnostics passed’
By

writing

cause
has

that

the

not

the

codes
BMP

been

error

receive
LED.

FIFO,

the

report

detected.

option

This

BMP

carries

the

and

switches

line-parameter
the

the

also

BMP

out

reports

OFF

the

tasks,

detected,

module.

the

(BMP)

doing other

status

facility

the
is

the
even

the

host

unavailable.
NOTE

More information on the self-test
and
diagnostics
is
given in Chapter 3 of
manual.

host
if

can
error

suspects

A~QA

Program

not

tests

switch

BMP
this

Background Monitor
the CXA16,/CXBl6

the

4.3.2
When

that

used to test
the
Q-bus
interface
and
verify
settings on the module switchpacks are correct.

two seconds.

exceed

not

will

interface.
The LED is turned off while the self-test sequencer is
executing.
The OFF period varies depending
on
whether
DHV11
or
DHUll
mode was selected,
and on whether the self-test was invoked
using the self-test skip feature of the program interface;
but
it

completed successfully
if
the
LED
is
ON
two
self-test has been initiated,
either by powering
by
resetting
the
module
through
the
program

has
the
or

The self-test
seconds after
up the module

FIFO,

AAAAaq

4.3.1
Self-Test
The self-test starts

INTERNAL DIAGNOSTICS

4.3

Internal diagnostics run without intervention
from
the
operator.
There
are
two
tests:
the
self-test and the background monitor
program (BMP),

4.4

MicroPDP-11

DIAGNOSTICS

4.4.1
User-Mode Diagnostics
These tests can be used by an
untrained
operator
to
verify
the
basic
operation
of
the option.
User-mode tests do not cause any
disruption to data networks or devices to which the CXA16/CXB16 may
be
connected.
Such
networks
and
devices
do
not
have
to be

disconnected

from

MicroPDP-11
diagnostics.
4.4.1.1

CXAl6/CXBlé6

manuals

describe

Running User-Mode Tests

selection

are booted.
4.5

the

system

from

the

-- All

how

the

tests.

1load and

user-mode

tests

run

are

The

these

run

for more details.

DIAGNOSTICS

for MicroVAX II

systems

all

Maintenance System (MMS).
The MicroVAX II
how to load the MMS into the
MicroVAaX II,
diagnostics.
All
the tests can be
menus displayed when MMS is booted.
4.5.1

test menu displayed when the user diagnostics

See Chapter 2

MicroVAX II

Diagnostics

during

run

run by

under

the

system manuals
and
how
to

MicroVAX

selection from

describe
run
MMS
the

test

User-Mode Tests

These tests can be used by an
untrained
operator
to
verify
the
basic
operation
of
the option.
User-mode tests do not cause any
disruption to data networks or devices to which the CXAl6/CXB16 may
be
connected.
Such
networks
and
devices
do
not
have
to be
disconnected from the CXAl6/CXB16 during the tests.
See
Chapter 2
for

4.6

details.

MicroPDP-~11

4.6.1

SERVICE MODE

MicroPDP-11

DIAGNOSTICS

Functional

Diagnostic

The functional diagnostic for a MicroPDP-11
also tests other modules in the same family,
After

booting,

hardware

the

program

configuration;

CSR

Vector

address

Active

line

Loopback

address

bitmap

type

asks

these

are:

you

four

is
VHQA** ,BIN,
This
for example,
DHVII.
questions

about

the

The diagnostic will then 'size’ the option to
determine
operating
mode (DHU11/DHV11),
modem or data-leads only,
8 or 16 lines,
and
then print this information.,
The control chip and OCTART
revision
levels
are
also
printed.
Always
check
that
the unit 'sizes’
correctly.

4.,6.,1.1

Test

MicroPDP-11

Summaries ~-- The

functional

following

diagnostic

can

read

and

1list

summarizes

the

tests.

test

verifies that

write to the unit under test.

the

OQ-bus

DHUll/DHV11

mode.

MASTER.RESET Test

within
3.

5 seconds.

verifies

that

master

reset

clears

DHUl1l/DHV11 mode.

MASTER.RESET (skip self-test) Test
master
reset clears in approximately

verifies
that
the
30 milliseconds when

the

DHU1l1/DHV1l1 mode.

skip self-test sequence

is used.

RX.CHARACTER Field Test - verifies that the data
the
codes
in
the
receive FIFO after a master
skip self-test are
consistent
with
the
skip
codes,
DHUl1l/DHV11l mode.

RX.FLAG Field Test - verifies that the three
data
status
bits
(overrun,
framing,
and parity error bits) are all
set on each of the skip self-test codes in the FIFO
after

master

reset and skip self-test sequence.

bits
of
reset and
self-test

DHUll/DHV11

mode.

RX.DATA.AVAIL Test - verifies that the
RX.DATA,AVAIL
is set when the skip self-test codes are in the FIFO,

that

it clears after

they

have

been

read.

bit
and

DHU11/DHV11

mode.

RX.DATA.VALID Test

bit

is set for all
the codes have

all

RX.LINE

are

- verifies that the
RX.DATA.VALID
the codes in the FIFO,
and clear after
been read.
DHU11/DHV11 mode.

FIELD Test

correct

for

verifies

the

skip

that

the

self-test

RX.LINE

line

codes.

DHUll/DHV11

fields

mode.
9.

BMP

Check

Test

verifies

that

the

unit

does

immediately
fail the background monitor program,
may invalidate further tests.
DHUll1/DHV11 mode,
10.

Skip

Self-test

Test

verifies

that

the

self-test in the time allowed,
and that
the correct codes after its completion.

4-6

unit

not

this

skips

the

the FIFO contains
DHUll/DHV11l mode.

—

DIAGNOSTIC.FAIL Test - verifies that
by
using
the
skip
self-test
sequence,
the
DIAG.FAIL
bit sets and clears
with the allowed times.

11.

12,

Self-test
Test
-~
verifies
that
the
unit's
self-test
executes
within
the
correct time,
and that the correct

codes are returned

DHU11/DHV11l
13.

mode.

the

FIFO

after

its

completion.

Self-test Fail Test - verifies that the unit
will
report
errors when it is forced to fail by using the special fail
self-test
sequence
(decimal
146314
written
to
the
transmit-buffer
count register).
The DIAG.FAIL bit sets,
and at least one self-test failure
code(231)
is
in
the
receive FIFO.,

DHUll/DHV11 mode.

14.

Chip Version Number
verifies
that
the
chip
version
numbers
are
reported
correctly,
and,
if
requested,
prints them out.
DHUl1l/DHV11 mode.

15.

CSR<4> (Skip Self-tes’.) Test - verifies that when this bit
is set (at the same
time
as
master
reset),
the
unit
remains
inactive with the master reset bit set;
and when
CSR bit 4
1is
subsequently
cleared,
the
unit
becomes
active and reports six skip~self-test codes in the receive
FIFO.
Any BMP codes found in the FIFO
are
saved
to
be
reported

16.

later.

DHUll

mode only.

Word Access Read/Write Test - verifies that the
registers
respond correctly to read and write accesses.
DHUll/DHVI1l
mode.

17.

Word Access Read~Modify-~Write Test - verifies
that
the
registers
will
respond
correctly
to
read-modify-vrite
accesses.
DHU11l/DHV11l mode.

18.

Byte Access Read/Write Test - verifies that the
will
respond
correctly
to
byte
read/write
DHU11/DHV11l

registers
accesses,

mode.

19.

Bvte Access Read-Modify-Write - verifies

that
the
-egisters will respond correctly to byte read-modify-write
accesses.
DHUl1/DHV11l mode.

20.

TX.DATA Invalid Test - verifies that
if
a
character
is
written to the transmit character register(TXCHAR) without
TX.DATA.VALID<K15> set,
no TX.ACTION report occurs.
DHVII]
mode

only.

21.

TX.DATA Valid Test verifies
that
if
a
character
is
written
to
the transmit character register (TXCHAR) with
TX.DATA.VALID<15> set,
a TX.ACTION
occurs.
DHV11l
mode
only.

on that
23.

24.

(Inactive) Test - verifies that
when
bit
is clear,
transmission will not

line.

DHUl1/DHV11l mode.

TX.ENABLE

(Active)

TX.ENABLE
that line.

bit
1is
set,
transmission will
DHUl1/DHV11 mode.

DMA

Start Test

Test

- verifies

verifies that

initiate a DMA transmission on
25,

DMA

Abort Test

verifies

DMA

Error Test

verifies

CSR
reports
DMA
DHU11/DHV11 mode.
27.

28,

FIFO

Data Test

verifies

Test

30.

XON-XOFF

and

Interrupt

Test

reception
DHU11/DHV11

OAUTO

are
not
mode.
-

and
mode.

XOFF

verifies
flow

Filtering Test

(LPR<O>)

characters
DHU11/DHV11
31.

verifies

that

4-8

hold
the

unit

256

overrun

will

not

that

unit

the

characters

verifies

transmission

will
that

occur.

when O,AUTO

that

(LNCTRL<4>)

verifies

they

characters

control

placed

bit

when

the

correctly to incoming
DHU11/DHV11l mode.

will

the

DMA.ERROR

OAUTO

OAUTO Active

bit

the

correctly

and

will

and

that

XON and
mode.

bit

DMA.ABORT

FIFO

to incoming
DHUl1/DHV11l

line's

return
a
TX.ACTION,
DHUl1l/DHV11 mode.

the

Inactive Test

take place on

DHUl1l/DHV1l mode.

characters
without corrupting data,
set is clear.
DHUl1/DHV11l mode.

respond
clear.
29.

when

DMA.START

line.
each

that

errors

that

efcach

that

stop
a
DMA
transmission,
successfully restart the DMA.
26.

a
line's
take place

the

are

the

wunit

responds

when

set,

will

active.

DISAB,XRPT

receive

interrupts

XON=-XOFF
silo.

generate

correctly.

TX.ENABLE
TX.ENBLE

22.

32,

Diagnostic Field (BMP) Test - verifies that a

request

the unit to report BMP status codes is complied within the

All active lines are tested.

specified time.

DHUll/DHV1l

mode.

33.

34.

transmit
Break Generation Test - verifies that all serial
in the
bit
lines can generate a Break by setting the BREAK
DHUll/DHV11 mode.
associated LNCTRL register.
test
No Overrun Error Test - verifies that the unit under
overrun errors when they do not
report data
not
will
DHU11l/DHV11 mode.

occur.

35,

report
wunit will
Overrun Error Test - verifies that the
received.
are
characters
data overrun errors when 261
DHU11/DHV11

Modem Tests - skipped for CXAl6/CXBl6,

36 to 45.
44,

mode.

Transmit Line Test - verifies that the transmit lines

receive

cables,

Executed

working

are

only

if external mode is selected.

Lines

Interaction

distribution

panel,

and

correctly through the device

lines

and

loopback

connectors.

DHUll/DHV1l

mode.
45,

46.

Transmit

Test

looks

for

any

Executed only if one of the
lines.
between
interaction
DHUl1l/DHV11 mode.
external loopbacks is selected.
for
timer
hold-off
the
verifies that
=~
RXTIMER Test
and that the
1is operating correctly,
interrupts
receive
DHU mode
three-quarters full level overrides the timer.
only.

47.
48,

Modem Test - skipped for CXAl6/CXBl6.

hold 64
Transmit FIFO Test - verifies that the FIFO will
for
occurs
interrupt
one
only
that
and
unique characters,
all

49,

64 characters.

the
DMA Address Test - verifies that the unit can access
is on the machine through DMA access.
which
memory
full
DHU11/DHV11

51.

DHUll mode only.

mode.

terminal
Keyboard Echo Test - allows the operator to test
attached
are
which
links),
ns
communicatio
other
(or
links
1links,
the
of
ends
remote
from
ports,
to unit serial
DHU11/DHV11l

mode.

Single Character Test
receive
and
transmit

various line parameters.

that the unit will
verifies
correctly using non-DMA mode at

4-9

DHUl1l/DHV1l mode.

53.

DMA Mode Test - verifies that the unit will

54.

Framing Error Test - verifies that forced

receive
correctly
DHU11/DHV11 mode.

using

are reported correctly.

DMA at various

H3101

transmit

and

line parameters,

framing

loopback only.

errors

DHUll/DHV1l

mode.

55.

Parity Error Tesi - verifies that

reported

correctly.

H3101

forced parity errors are

1loopback

only.

DHUll/DHV11

mode.

56.

Split Speed Test - verifies that the
unit
will
function
correctly
using
different transmit and receive speeds on

each active line.

57.

H3101

Report BMP Codes Test -

loopback only.

this pseudo-test

DHUll/DHV1l mode.
reports the

32 characters which were discovered in the
execution of the other tests.
This avoids
the other tests by these codes if they are
the performance of the tests.
DHUll/DHV11
4.6.1.2

Loopback

available

Connectors -- Two

FIFO during the

interruption of
not critical to
mode.
connectors

are

for the CXAl6/CXBl6;

H3101l:

Eight-line loopback

H3103:

Single-~line

4.6.2

loopback

first

(loops 0 to 0,

1 to 1

...)

loopback.

DECX1l1l Object Module

The CXA16/CXBl16 Object
XDHV** ,0OBJ.

Module

the

same

module

for

the

DHV1l:

NOTE

Early
versions
of
this
support the CXAl6/CXBl6,
The minimum parameters

The

which must

DVA

(Device Address)

VCT

(Vector Address)

DVC

(Device

Count),

default operating mode
9600 baud.

is with

4-10

NOT

specified are:

than

all

one.

lines

looped

back

internally

4,7

MicroVAX II SERVICE MODE DIAGNOSTICS

The CXAl16/CXBl6 uses the same diagnostic module as for
NADHA*,

DHV1l,

Configuration Tests

The module is °‘sized’' to check the number of lines (8 or 16),
and
whether
it
supports
modems
or
is
data-leads-only.
This
information,
together with the control chip
and
OCTART
revision
levels,
is added to the system configuration file.
service
test,
the
setup
procedure
for the CXAl6/CXBl6 diagnostic is executed.
You will be
prompted to attach any loopback connectors or cables (for instance,
bulkhead
loopback
connectors).
On pressing the RETURN key,
all
ports are sized to see to which ports (on the same controller)
the
loopbacks
are
attached.
This information is then displayed,
and
the field service test are started.
This setup
procedure
is
run
only once after configuration of the diagnostic system.
TEST

TEST

This test
uses
loopback
connectors
and
cables
sized
during
the
setup procedure to send single characters in
programmed output mode over port 0,
using baud rates
of
300,
1200,
9600,
and 38.4k bauds,
and with various
data lengths,
stop bit sizes,
and parity
options.
It
should be noted that,
due to execution time constraints,
this is the only test,
other than the utilities,
which

this
test,
the
CXAl16/CXBl6é
is
initialized
addressability checks are made on various registers.

exercises

TEST

VTV

W
W

4.7.2 Field Service Functional Tests
Before the
diagnostic
runs
a
field

4.7.1

the

the entire

and

range of character options,

This test performs extensive DMA testing through loopback
connectors
and
cables sized during the setup procedure,

TEST

This
test
uses internal loopback connectors
and cables
sized
during
the set-up procedure to perform
extensive
flow-control
testing.
OAUTO,
IAUTO,
and
FORCE.XOFF
functions
are
exercised.
The break signal function is
also

tested.

VUV

using different
buffer
sizes,
All
ports
are
tested
simultaneously
at
19.2Kbytes/s.
FIFO
overrun and DMA
abort are tested.
1In addition,
if a port is
determined
to
be
connected
to
a
port other than itself,
a more
thorough test of outgoing data flow-control is performed.

4-11

TEST

(DHU1l mode only) This test uses loopback connectors
and
cables
sized during the setup procedure to loop back the
data from the transmit FIFO to
the
receiving
channels,
to
verify
that
the
transmit
FIFO
buffer can hold 64
characters without corrupting the data.

4.7.3
Field Service Exerciser Tests
The Field Service exerciser performs each of

tests
setup.

the

functional

service

to
5,
using loopback connectors and cables found during
All applicable ports are tested,
but only at 19.2Kbytes/s,.

4.7.4
OUtilities
The three utilities provide simple routines to run echo
tests
and
terminal tests on specific lines.,
They can be used to locate cable
faults,
using the loopback connectors to loop
data
back
to
the
module,
or
to
check
that a terminal,
or remote equipment,
is
correctly transmitting and receiving characters.
Utility

This

utility

permits

staged

testing

the

CXAl6/CXBl6

and
associated
cables/connectors.
The
diagnostic
requests configuration parameters
from
the
operator,
and then repeatedly tests the port(s) for data loopback
integrity.
The operator may,
by strategically placing
loopback
connectors
at
various
points
in
the
communications path,
isolate
defective
units.
The
operator
is
not
prompted
as
to
where to place the
loopback connectors,
nor does the diagnostic interpret
the
Utility

This

results
utility

devices.
loopback
port

the

tests.

permits

testing

The
diagnostic
maintenance mode.

will

echoed

back

remote

communications

puts
all ports into remote
All characters sent to
any
to

the

sender,

baud

rates

up
to
9600
baud.
No
operator
configuration
is
necessary.
Because
of inherent CXAl16/CXB16 buffering
limitations,
characters may be lost if transmitted too
rapidly by the terminal.
Utility

This

utility

sends

test

strings

the

port(s)

specified
by
the
operator to aid diagnoses of remote
communications devices.
The operator
may
choose
any
baud
rate or character specifics.
The port under test
is
configured
with
auto~flow
control
for
outgoing
characters.

4-12

4.8
The

FIELD-REPLACEABLE UNITS

(FRUs)

FRUs are:

Reference No.

Item

M3118-YA
M3118-YB
BC16D-25
H3104

CXAl6 module

CXB16 module
36-wire cable
Cable concentrator

4-13

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CHAPTER 5
DESCRIPTION

SCOPE

CXAl6/CXBl16,
and each block identified in the diagram is described
in
this
chapter.
While
reading
this chapter,
you may find it
useful to have
access
to
a
CXAl6/CXBl6
printset
(part
number

.«2
OVERVIEW
Figure 5-1 shows a block diagram of the
broken down into the fcllowing sections.
)

RAM

stores

control

CXAl6/CXBl6.

information

and

OCTARTs
=-each
OCTART
receiver/transmitters,

interface

Line

)

Power Converter -- provides
positive
supplies for the line interface (CXAl6

VU
U

Each

Section

Interface

these

5.4

eight
asynchronous
generators,
and

Drivers
and
Receivers
interface to the QO-bus

VUV

data

OCTART.

the

Q-bus

VUV

the

contains
sequencers
and other
1logic
to
the
functions of the CXAl16/CXBl6
outside

provides

can

logic

Control Chip -implement
all

)

contains
baud-rate

Switchpack and Shift
address and vector,

buffers

)

of
the
CXAl6/CXBlé6
block diagram of the

MP-02381).

5.1

This chapter gives
a
technical
description
asynchronous
multiplexer.
Figure 5-~1 shows a

TECHNICAL

blocks

describes

converts

described

the

flow

signals

data

provide

and

from

device

electrical

line

levels

and
negative
only).

detail

through

the

Section

module.

5.3.

HAM

SHIF T
AND
REGISTERS

SWITCHPALRS

CONTROL CHIP

<
PR

ADDR
RWRI1

SHF TH

AND

LOEL

RAM ARBITRATOR

{RARH)

ADDRESS

AND DATA

]

SLQUFNCER
(DS,

UART

DATA

C15<2 0>

(DME)

SEQUENCER]
(UAF)

‘

CONTROL

‘

UART

SEQUENCER

—%1 CONVERTER

+12 VOC

POWER

MODEM

LATCHES

‘E&

WMDL

ADDRESS DATA

o113

1INY

FAST

1o
SEQUENCER
(10}
[

SEQUENCER

< }

(

DSR<7 0>

nMA
FAST

¢> CONTROL

{

DMA

01R

R00s
e

SLOW

2?2

)

}

L WAL

[ 3

@ v

SDO <7 03

Wi R
RECEVERS

‘-."

'@
—01 <7 05}
OCTART

ANDRESS
}
1T/

RAM TEST SEQUENUER

DRILERE

DATA

‘

ROEL

R (TTR) AND
IIMI

(RS

(1]

‘

RIS <7.0>

OTR<2-0>

{

1
|
)
\

{

+10voC ’1

Zlovoc )
MKVB8-2055

Figure 5-1

CXAl16/CXB16 Block Diagram

5.3

CXAl6/CXB16 FUNCTIONAL BLOCKS

5.3.1

The way
shown
vided

RAM

in which the RAM is assigned to the
various
functions
is
Two Kbytes of RAM are used.
This RAM is di-

in
Figure 5-2.
into three main

sections:

The top 1 Kbyte contains
one per channel.

the 64-character

transmit

FIFOs,

The next 512 bytes contain the 256-word receive FIFO.
The
low
byte
of each word contains a received character,
and
the high byte contains status information,
such as channel
number

The

and

bottom

error

512

status.

bytes contain the

32-byte

control

areas,
one per channel.
These registers control the data
flow through the CXAl6/CXB16,
through
the
sequencers
in

U@OUC

the

control

chip.

OCTAL
CHANNEL 15 TX FIFO
13
1"

=lwio

(=} § SN RN N

|=]

o—-——-—--——--—-—-—------——--

3777

————

STATUS

DATA
256 WORD
RX FIFO
{512 BYTES)

1000

CONTROL

“lllmlli”

(LG

CHANNEL 15
'
i
1
]

'
'
]

1
1

|
'
l
i

j«— CHANNEL 0

0000

Figure

5-2

RAM

Assignment

5.3.2

OCTART

Each

OCTART

contains

asynchronous

receiver/transmitters,

sixteen-output
baud-rate
generator and interface logic.
They are
compatible from a serial-line viewpoint
with
those
in
the
2681
DUART.
Each channel has only a single buffer on both transmit and
receive.
The UART fast sequencer on the control chip (see
Section
5.3.3.6),
together
with
the RAM,
provides double buffering for

the

thus

transmitters and a

4-word-per-line

completing compatibility with the

The OCTART

shown

greater

detail

| EIGHT

FIFO

2681

for

DUART,

Figure

each

receiver,

5-3,

CONTROL-CHIP
INTERFACE

RECEIVERS

‘

LOOPAROUND

RECEIVER READY.

CONTROL

TRANSMITTER READY
_INTL

SERIAL

DATA IN
010 7)

SERIAL

DATA OUT

SCANNER

(0T0
7)

tClLB{LA

EIGHT

“““““ ]

TRANSMITTERS

TIMING

A1-0

OEL

e e e eA o o

WRL

INDEX

——

e ]

LINE-PARAMETER

REGISTERS

IC1IB{IA

Figure

5-3

OC{ART

SYSTEM

TIMER

5.3.2.1
Control-Chip Interface -- This
sources of information for the OCTARTs:

manages

Receiver/Transmitter~Ready Scanner
together with

the

Index Register

receive

ready

two

separate

bits

L<C:A>,

bit

bits I<KC:A>,

The scanner logic scans each channel in turn
until
it
locates
a
channel
needing
servicing.
It then asserts the interrupt line to
the control chip.
A channel is ready for servicing when either
it
is free to accept a character for transmission,
or a character has
been received,
as indicated by the receiver-ready bit.
During the
servicing
of
this interrupt by the control chip,
the L<C:A> bits
tell the control chip which channel has interrupted.
If
it
is
a
receive
interrupt,
the
received
character
is presented on the
D<7:0> lines.
1If it is a transmit
interrupt,
the
control
chip
will
either
present
a
character on D<7:0>,
or performs a dummy
transfer.
Note
that
the
receivers
are
given
priority
over
transmitters.
Register

bits

access.,

I<KC:A>

Address

associated with
5.3.2.2

one

A<1:0>

channel.

eight

channels

select

one

Each

line

Line-Parameter Register --

line-parameter
LNCTRL

that

select

lines

derived

from

5.3.2.4

four

registers

has

its

the Q-bus-addressable

own

LPR

and

registers.

5.3.2.3
Loop-Around Control =-- This implements
the maintenance mode bits (see Section 3,2.2.9).

baud

during

Baud-Rate Generator -- This

rates

for

transmit

independent
from
the
interdependency between

and

provides

receive.

receive
channels.

the

Transmitter

rates,

and

functions

independent
baud

rates

are

there

5.3.3
Control Chip
The control chip contains all the necessary logic and
sequencers
to
control
the
operation
of
the
CXAl6/CXBl6.
The functions of the
control
chip
can
be
broken
down
into
seven blocks:
e

Timer and RAM test sequencer

Q-bus

°®

DMA slow sequencer (DMS)

DMA fast sequencer

(DMF)

Data I/0 sequencer

(DIO)

UART

sequencer

(UAF)

UART slow sequencer

(UAS)

RAM arbitrator

interface

fast

(TTR)

(QIF)

(RARB).

5.3.3.1
Timer
and
RAM
Test
Sequencer
(TTR) -- This
sequencer
controls
the
power-up
sequence of the module.
On power-up,
the
TTR:

Resets

the OCTARTs

Clocks the switchpack settings into the control chip.
RAM
address
lines
are
used
to
select
the
shift
register
operation,

and RWR.L

shift register
°

sequencer

control

5.3.3.2
handle
The

used

clock

the

information)

3.3.1.

also

generates

internal

timing

signals

for

the

logic

chip.

0Q-bus Interface
data

1/0

QIF

also

A special

and

includes

response

Tests the RAM (which takes 26 ms) and leaves the RAM
in
a
defined state,
which reflects the power-up state described
in Section

The

(RAM write)

(see Section 5.3.4 for more

(QIF)

-- This block

interrupt
other

functions,

DOUT handler,
time without

contains the

operations.
such

as:

so that the Q-bus

having

to wait

is given a

fast

for RAM access

Logic to handle interrupt
request
generation
and
vector
assertion (using data read from the switches at power-up).

Some device register bits are also

implemented

in this

block,

such

as:

[

Indirect address

Interrupt enable

bits.

$5.3.3.3
DMA Slow Sequencer (DMS) -- DMA operations are
controlled
by
a combination of the DMF (DMA-Fast) sequencer in this block and
also the DMS (DMA-Slow) sequencer (described in Section 5.3.3.3).

This sequencer has three

independent
transfer by

functions.

e¢

To handle a DMA

)

To report a TX.ACTION at the end of a DMA
operation
(this
includes
successful
operations,
aborted operations,
and
operations terminated after a bus error)

To scan the
operation.

handle an ABORT

controlling

the DMF sequencer

request

channels

until

detects

the

need

for

DMA

5.3.3.4
DMA Fast Sequencer (DMF) -- The
function
of
the
DMF
sequencer
1is
to become Q-bus master,
and then acquire characters
from the Q-bus at maximum Q-bus speeds.
At an average
rate
of
1
word
every
850
ns
in
block-mode DMA,
the DMF acquires up to 8
words (16 characters) during
its
bus
mastership.
In
non-block
operations,
up
to
4
words are acquired while it is bus master,
These characters are transferred to the
transmit
FIFO
under
the
control
slave to

of
the

the
DMS

DMS
sequencer,
sequencer,

The

DMF

sequencer

operates

5.3.3.5
Data I/0 Sequencer (DIO) -- This
sequencer
waits
in
idle
1loop
wuntil signals from the Q-bus (through the QIF) cause

to do data

1/0 operations

=-- DATI,

DATO(B),

an
it

and DATIO(B).

This sequencer also detects operations
on
certain
registers
and
takes appropriate action.
For example,
after a write operation to
a LPR or LNCTRL register,
it sets a bit in the
RAM
control
area
for
may

that
have

channel

indicate

the

UAS

sequencer

that

the

contents

changed.

5.3.3.6
UART Fact Sequencer
interrupts from the OCTARTs.
UAF

reads

the

and

whether

OCTART

(UAF)
When

status

receive

-- This
sequencer
handles
an interrupt is
received,
the

transmit

interrupt.

5-8

find

the

channel

number,

=
O YY" OTBDV
VTV
VvV
VvV
VTV
T

transmit

ready

the

RAM

character

RAM

UAF

directly

(low

transfers

For a

been

read

to the

(high

byte).

receive

from

byte).

previously

FIFO

having checked

the

to the OCTART.

FIFO

the

there

is a

character

character directly

interrupt,

the OCTART

Then

from

that

the

the UAF

the

top of

the

error

status,

OCTART

status

from

transfers
the

4-word

which
is

had

written

5.3.3.7
UART Slow Sequencer (UAS) -- This sequencer scans
all
channels
(in
160
microseconds,
to
guarantee
operation on
channels at maximum possible data rates).
For each
channel,

16
all
the

UAS:

Moves

received

characters

FIFO
in
RAM
into
the
also recognizes and acts

from

the

bottom

the

4-word

256-word shared receive FIFO.
It
upon
received
XON/XOFF
control

characters.

Implements

priority
channel:

TV O TV

one

the

order)

following

bPbefore

Line-parameter

whether

this

five

repeating

written

has

actions
step

check

been

(listed
for

the

changed

in
next

checks

the

DIO

sequencer

)

Line-parameter

previous
changed,

]

change

during

the

pass it detected that this register had been
it now updates the OCTART registers with the

new

information

BMP

Report

generates

Background

Monitor

Program

report

W
W

interrupt,

transmit,

the

VTG

For a

Transmits
or

®
The

single

transmits

Transmits

UAS

block

also

Receive

TX.ACTION

FIFO

RX.TIMER

logic

)

Background

XON

from

character

the

XOFF

from

the

TXCHAR

characters

transmit

FIFO.

includes:

FIFO

control

control
(only

Monitor

used

Program

DHUll

(BMP)

programming

logic.

mode)

5.3.3.8
RAM Arbitrator (RAPB) -- This arbitrates hetween
the
six
RAM
access sequencers described in sections 5.3.3.1 and 5.3.3.3 to
5.3.3.7,
giving one of them access to
the
RAM/OCTART
data
bus,
depending on the priority scheme described here.

The TTR sequencer has the top priority so that
it
gets
100%
RAM
access
for
the
first 26 ms after power-up.
This guarantees that
the RAM will be powered—-up to an operational state before any other
sequencer can begin.
After 26 ms this sequencer idles.
Although it cannot gain access to RAM during
the
26
ms
power-up
time,
the
DIO
sequencer still operates.
This is needed for CSR
access and SKIP SELF-TEST operations from the
0-bus
(see
Section
3.2.2.1).
To ensure that the progress of each sequencer is predictable,
RAM
access
1is alternated between the two UART sequencers (UAF and UAS)

and the two CPU sequencers (DIO and DMS).
During
‘'CPU-time’
only
CPU
sequencers
are
granted
access.
During
‘'UART-~time',
UART
sequencers have priority,
but if neither UART
sequencer
requires
access,
a
CPU seguencer can steal the cycle.
The overall effect
of

this

that:

The UART sequencers progress at a predictable
rate.
This
guarantees service to each channel at a rate fast enough to
maintain maximum throughput while still allowing a required
minimum time between OCTART write operations

Access by the CPU sequencers is maximized (and hence
O-bus
BRPLY
delay
times
minimized) by allowing them RAM access
during unused UART cycles,
along with normal CPU cycles.

'UART-time',

the

UAF

has priority over

the UAS

to make sure

all

data
transfers
to
and
from
the
OCTART
are done as quickly as
possible.
Of the CPU sequencers,
the DIO has
priority
over
the
DMS

to get

5.3.4

the minimum delay

in asserting BRPLY,

Switchpack and Shift Registers

The TTR sequencer shifts—-in the contents
of
the
shift
registers
after
the module has been reset (by BINIT or MASTER.RESET).
Since
the switchpack contents are only examined at this time,
the module
must

reset

(BINIT

or MASTER.RESET)

5-10

in order

to set

new values,.

The TTR sequencer in the control chip has been designed for use
in
several
different
applications,
and therefore needs to determine
whether the module has 8 or 16 channels,
and whether it is a Q-bus

or UNIBUS application (the CXAl6/CXBl6 is set up for 16 channels on
Q-bus).
Figure 5-4 shows a simplified diagram
of
the
switchpack
and shift register logic.
vCC

vCC

___ADO1

SWITCHPACK

O
AD10 =———4—0

SHFT LD CLR|

SERIAL INPUT

CHIP

al2HETHo 76 conTROL

DRvL

—O\G

D5
AL

L O

|
|
|

D3 REGISTER

L o0 T o-

-—

AD9 >——————o\o————$
—0

O-

___ADOO

—45““t>——1

SASL

SHFT LD cm__l
Q

L 0
—0

O
O

i
i

| DS
104 sier

O-

'
I

L 6

RWR

SWITCHPACK

DO
SERI

]

PART OF S1

SLOO PL

=
oND

MKVB893-0450

Figure

5-4

Switchpack

and Shift Register Logic

First,
the switch settings connected to the D<7:0> inputs
of
the
shift registers are synchronously loaded into both shift registers.
This is done by holding ADOO and ADOl low while pulsing RWR.L.
The
switch
settings
are
clocked
into
both shift
registers
by the
trailing
edge of
RWR.L.
ADO9 and
AD10 are
held low during this
first
operation to
ensure that
the respective D7 settings (DHV.L
and SAS5.L) are loaded in the same way as all the other switches.
After
this
present at

load,
the
the
SHFT.H

internally
with
ADOO

first
bit
(D7
of
shift
input to the control chip,

by the TTR sequencer.
and
ADO1l
high (this

Then 16
selects

remaining bits in the shift register
control chip and latched by the TTR,
setting
(SERI input) to
the B shift
total

are
thus
clocked
into
the
including the last shifted-in
register (SLOOP.L), making
a

settings need to be determined.

Whether the device supports
or

RWR.L pulses are
applied
the shift function).
The

bits.

Two further

lines

(as does

CXAl6/CXBl6)

lines

Whether

the

device

CXA16/CXBl16)

or on

operates

the

Q-bus

(as

After the 17 switch settings have been latched,
the
control
sets
ADO9
and AD10 high.
It then selects the load function
and ADC1 low!) and pulses RWR.L.
Because of the high level on
and AD10,

high

level

regardless

the

switch

The

control

supports

the CLR

and

ADOB

chip

now

1lines,
If

the

input
low

tries

to
is

device

latched

into D7

both shift

chip
(ADOO
ADO09

registers,

settings.

ADC8

to try

does

the UNIBUS.

clear

these

connected

operates

shift

the

clear

two bits.
to

the

UNIBUS,

The control

registers.

CLR

the

input

ADO2

device
of

shift

connected

chip pulses AD02
the

CXAl6/CXB16,

neither of these connections is made
(both
CLR inputs
are simply
pulled
high); therefore
the registers
dJdo not clear.
The control
chip can
now test
the
state
of
the
SHFT.H
line and determine
(since
SHFT.H is
high) that
the CXAl6/CXBl6
has sixteen
lines.
After applying eight RWR.L pulses, a second test cf the SHFT.H line
shows
that the CXAl6/CXBl6
operates
on
(Q-bus (SHFT.H
1is
again
high)
.

5-12

5.3.5
OQ-bus Drivers and Receivers
Six DCO021 Q-bus driver/receiver
chips

(transmit or receive)

are

used.

of each is controlled

The

direction

signals

from

the

two

control
chip.
Bus
contention
1is avoided while the direction is
being changed by disabling the transceivers,
using
enable
inputs
ENl.L

and

EN2.L.

5.3.6

Line

octal

1line

levels

Interfaces

The interface to the serial lines on the CXAlé
receiver chips and two octal

is provided

line driver chips,

and on

the CXB16 by
two
octal
line
receiver chips
and four quad line
drivers. These
are inverting
buffers
which convert
between line
J1 and J2 ccnnectors,

and TTL levels at the OCTART.

output.

Switching

5-5).

This

uses

pulses

pulse-width

from

modulation

the modulator

switch

regulate

the

transistor

=10

(Ql)

transferred

via

the

now

forward—-biased

diode

¢to

the

smoothing

capacitors.
As current is transferred to the output,
the voltage
at X rises until the diode is cut off again.
The circuit will stay
in this state until the next switching pulse turns Ql on.
The

inset

With

switched

off

again.

With

inductor

Figure

5-~5

on,

shows

switched

maintains

current

transferred to
more the power

typical

current

the output.
transferred

rises

off,

flow

inductor

linearly

the

which

The wider the
to the output.

W
Vv
v
W
W
W
w

convert
a dc input to a pulsed dc current in an inductor.
When Ql
is switched on,
point X becomes positive,
causing current to flow
through
L.
During
this period energy is stored in the inductor.
When Q1 is switched off,
the polarity of the
voltage
across
the
inductor
is
inverted,
and
the energy stored in the inductor is

OWVwWw

W
W

5.3.7 Power Converter (CXAl6 only)
The CXAl6 line drivers
require
+
and
10
V
dc.
The
Q-bus
backplane
supplies only +12 V dc.
A nominal +10 V is generated by
dropping down the +12 V across two diodes.
The -10
V
is
derived
from
+12
V
by a voltage converter.
This device uses switch~mode
power-supply techniques to
generate
the
negative
voltage.
The
circuit
is
built
around
a TL494 switching regulator (see Figure

the

5-13

current

until

collapsing

reduces

waveforms.

field

linearly

switching

switched
in

pulses,

the

is
the

+12 V SUPPLY

VIN

(g ;)

PULSES

SWITCHING

vece
!REF

”

Vv ouT

o2V

~TsmooTHING

T68

CAPACITOR

PULSE-WIDTH

MODULATOR
/REGULATOR

VAR

TL494

[ —

OVER

CURRENT

(Vacrl)

-—c

PROTECTION
=

FEEDBACK

= POWER TRANSFERRED TO O/P

Figure

5-5

Power Converter

5-14

Feedback from the output is compared with a reference voltage.
If
the
output is too high,
the pulse width is reduced;
if it is too
low,
the pulse width is increased.
This feedback action maintains
output
voltage
regulation for varying loads.
This same method of
comparison is
used
to
implement
over-current
protection.
The
inductor
current
1is
sensed
across Rc.
If this.exceeds a preset
limit,
the
switching
pulse
width
is
reduced.
The
switching
frequency
(60 kHz) is selected by Rs and Cs.
If the oscillator is
working,

sawtooth waveform can

seen at

5.4
This

DATA FLOW
section
describes
the
general
flow
of
data
CXAl6/CXBl16
between
the Q-bus and the serial lines,
receive and the trancsmit operations,
5.4.1

Data

Flow

Data

clocked

has

completed

interrupt
The
UAF
FIFO
for

through

the

for

the

both

for Character Reception
into
the

the OCTART

serial

serial-to-parallel

form.

When

conversion,

the

OCTART

generates

(LINT.L or HINT.L) to the control chip
(see Figure 5-6).
sequencer
quickly
transfers the data into the four-word
the
appropriate
channel
in
RAM,
and
sets a

receive-Jata-available
flag.
The UAS sequencer sees this flag and
processes ithe character by moving it,
together
with
the
channel
number
and
error
information,
to the top of the 256-word shared
receive

FIFO.

The

accesses

CPU

This

the

bottom of

transfer

the

receive

handled

FIFO

the

DIO

5.4.2
Data Flow for Character Transmission
Characters to be transmitted are handled either
1/0 operations (see Figure 5-7).
5.4.2.1
the

writing
and

DMA Operation

start

address

the

then

DMA,.START

transmit

number
setting

being

FIFO

set

with

-- The

for
of

CPU

the

characters

the
and

the

starts

channel
to

DMA.START
begins

aid

the

DMF

DMA

transmitted
The

the

RBUF

normal

writing

operation

into TBUFFAD]

bit.
DMA

reading

sequencer.

DMS

transfer

into

TBUFFAD2,
TBUFFCNT,

sequencer

sequencer.

and

the

The

detects

appropriate

UAS

sequencer

reads the status of that
channel's
transmit
FIFO,
removes
the
character (assuming there is one) from the bottom of
the
transmit
F1FO,
places it in the Transmit Holding Register (THR),
and sets
the

transmit-character—-available flag
in RAM as an element of the

contained
The

OCTART

transmit

interrupts

the

control

chip

The

UAF

character.

transmit-character-available

for

the

control
when

channel.
register
is

able

sequencer

The THR

area.
to

handle

reads

the

flag and,
if it
1is
set,
transfers
the
character
from the THR to the OCTART.
The OCTART converts it
to serial format,
and transmits it to the line drivers.

5-15

5.4.2.2
Programmed I/0 Operation =—- There
programmed 1/0 operation:
DHUll and DHVI1.

are

two

modes

In DHUll mode the CPU first reads the
FIFOSIZE
register
for
the
appropriate channel to find whether the transmit FIFO has space for
transmit characters.
If there is space,
the
CPU
writes
a
word

(two

characters)

byte

(one

character)

directly into the

FIFODATA register.
If the CPU has further characters to
transmit,
it
can
continue
to
write
successive characters to the FIFODATA
register without having to read the FIFOSIZE
register
up
to
the
number
previously
read from the FIFOSIZE register.
This transfer
is handled by the DIO sequencer,
which writes
the
characters
to
the
top
of
the
transmit FIFO
for
the
particular
channel.
Characters are
processed
by
the
UAS
and
UAF
sequencers,
as
described for the DMA transfers above.
In DHV1l mode the host writes a
single
character
to
the
TXCHAR
register
and
sets
the TX.VALID bit.
This transfer is handled by
the DIO sequencer.
The UAS sequence. removes this
character
from
the
TXCHAR
register,
places it in the THR,
clears the TVD bit,
and sets TX.ACTION,
Transfer to the serial line then continues
as
described above for DMA transfers.

Subsequent TXCHAR

transfers

TX.ACTION

set

has

been

for

must

only

the previous

5-16

initiated

transfer,

after

the

FAE ____________________________ -}
4 DEEP

'-:::’ TOP

FIFO

(
{
(
{
{

]

256 DEEP

SHARED

PER-LINE

FIFQ

]

TOP

|
|
!
|
|

BOTTOM

LT-S

OCTART

RECEIVERS

RECEIVER

UAS

N war

)
)
1
HINT LALINT L

oo |

|
|
|

)

) G-8US
INTERFACE |

Figure

l
|

a-8us

SERIAL IN
B

{\/7

Rt2aa?

5-6

Receive Character Data Flow

| WOL108_BHL— \

“Pn|N
YING

]

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APPENDIX A

CXAl6/CXB16 Q~bus CONNECTIONS

Table A-1

CXAl6/CXBl6 Q-bus Connections