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Document:	BM873 Restart/Loader
Order Number:	EK-BM873-TM
Revision:	004
Pages:	34
Original Filename:

OCR Text

BM873
restart/loader

dlilgliltiall

EK-BM873-TM-004

BM873
restart/loader

digital equipment corporation - maynard. massachusetts

Ist Edition, January 1974

2nd Printing (Rev), April 1974
3rd Printing (Rev), October 1974

4th Printing (Rev), February 1975

The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no respon-

sibility for any errors which may appear in this
manual.

Printed in U.S.A.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:

DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

UNIBUS

CONTENTS

CHAPTER 1

DESCRIPTION

1.1

INTRODUCTION

1.2

GENERAL DESCRIPTION

1.3

FUNCTIONAL DESCRIPTION

CHAPTER 2

INSTALLATION AND CHECKOUT

2.1

INSTALLATION

oooooooooooooooooooooooo

ooooooooo

oooooooooooooooooooooooo

........................

2.1.1

Start Address Selection

2.1.2

Jumper Selection

2.1.3

CPU Addressing with Volatile Memory

2-1

oooooooooooooooooooooooooooooooooooo

oooooooooooooooooooooooo

2-2
2-2
2-3

2.2

CHECKOUT

CHAPTER 3

PROGRAMMING

3.1

POWER FAIL PROGRAMMING

3.2

CHAPTER 4

OPTIONS

4.1

USER CUSTOMER PROGRAM FOR THE BM873-YA

CHAPTER 5

INTERFACE

CHAPTER 6

ENGINEERING DRAWINGS

APPENDIX A

DEVICE STARTING ADDRESSES

oooooo

oooooooooooooooooooooooo

3-1

4-1

ILLUSTRATIONS

Figure No.

Title

Page

1-1

Remote Start Timing

1-2

Memory Read Timing

1-4

2-1

External Interface Circuit Diode Matrix

4-1

Sample ROM Program Data Sheet

1-3

oooooo

TABLES
Table No.

Title

1-1

Description of BM873 Versions

1-2

BM873 Specifications

oooooooooooo

oooooooooooooooooooooooo

4-2

CHAPTER

DESCRIPTION

1.1

INTRODUCTION

This manual describes the operation and theory of the BM873 Restart/Loader. This option is intended for use with
the PDP-11 family of processors. The BM873

serves as general purpose loader for processors of the 11 family,

contains bootstrap loaders for all common devices,

provides the capability of loading with a “hidden console”,

permits starting from several sources e.g., pushbutton, Watchdog Timer, MODEM control, power fail,
etc.,

gives PDP-11 systems an initial program load capability,

contains at least four starting addresses, and

permits the calling of a special user ROM program.

It is assumed that the reader is thoroughly familiar with the operation of the PDP-11 processor with which this
option is used.

1.2

GENERAL DESCRIPTION

The BM873 option is contained on a quad-height, extended length module that plugs into a small peripheral

controller (SPC) slot. There are four versions of the BM873: YA, YB, YC, and YD. They are described in Table 1-1.

The programs contained in the BM873 can be loaded either from the processor console (Load Address and Start), by
a JMP instruction in the program, or by an external contact closure or voltage level. An 8-pin Mate-N-Lok connector
is used for the external interface. BM873 specifications are listed in Table 1-2.

1.3

FUNCTIONAL DESCRIPTION

The BM873 consists of two basic sections: the Restart Sequencer and the ROM.

Figure 1-1 shows the remote start timing. The Restart Sequencer takes contact closures or voltage levels and, after
filtering and delaying, sets one of four Start Address Select flip-flops. The setting of one of the flip-flops causes the
Begin Load Sequence flip-flop to set; this, in turn, initiates two one-shots to create a BUS AC LO/BUS DC LO

1-1

Table 1-1

Description of BM873 Versions

Version

ROM

Designation

Size

BM873-YA

BM8&73-YB

Description

128 words

Contains bootstrap loader programs

(256 words

for

optional)

(RF11,RK11,TC11, etc.).

256 words

Contains bootstrap loader programs

several

peripheral

devices

for the devices contained in the YA
version,

plus

programs

for

the

Massbus devices.

BM873-YC

256 words

Contains bootstrap loader programs
for the devices contained in the YA
version, plus the program for the

DU11 Synchronous Interface.

BM8&73-YD

256 words

Contains bootstrap loader programs
for

the

TC11

DECtape,

RHI11/RP04 Disk, and the DTE20
10/11 Interface.

Table 1-2

BMS873 Specifications
Capacity

BM8&73-YA

128 words, read only
(256 words optional)

BM873-YB, YC, YD

256 words, read only

Word length

16 bits

ROM cycle time

500 ns

Voltage requirements

+5V £5%

-15V £5%

IO Amax@+5V

Current requirements

20mAmax@-15V
Operating temperature

10° to 50° C

Humidity

20% to 95%

1-2

sequence. The processor responds to the sequence by performing its normal power-down and power-up trap

routines. Prior to the power-up sequence, however, the BM873 option asserts 773000 on the Unibus Address Lines.

As a result, when the Program Counter (PC) and Processor Status Word (PSW) are restored, the data is taken from
locations 773024/26 (nonvolatile memory systems) or from locations 773224/26 (volatile memory systems). Both
of these addresses are locations within the BM873 option. The data from 773*24 is 173000; the data from 773*26
is 340, establishing a priority level of 7.

The data read from 773*24 (173000) will have an offset address ORed onto Offset Address bits 8 through 1, giving
a range of 173000 to 173776. The offset address bits are enabled by one of the four Start Address Select flip-flops

via a diode matrix (Paragraph 2.1.1). Each bootstrap loader program has its own starting address, and it is this
address that is selected via the offset address bits.

the

BM873-YB,

some

of the bootstrap loader programs have two starting addresses. The first address

automatically selects unit zero and the second address selects the unit specified in the switch register. See Appendix
A for device starting addresses for all versions.

/,.--.

/---

SWITCH %

’

{

START ADR SELECT

%L"’
-

BEGIN LOAD SEQ

fl__l

BUS INIT L

]

ASSERT ADR 773000

{

g K

BUSDCLO L

BUS ACLO L

‘

T‘ -

STRB SW

]

beeeme
e -t

—_

CLR DLY

e «LT T‘ -wr -r

REC 1

(

CPU DLY

FETCH 773024/26 ——-rrd

PWR UP TRAP

CPU-BEGIN EXECUTION

OF ROM PROGRAM

11-2408

Figure 1-1

Remote Start Timing

1-3

The following sequence of operations would be typical:
®

Close external switch and wait for switch filter delay.

Assert AC LO; wait 6 ms.

Assert DC LO for 6 ms; then wait 8 ms.

Drop AC LO and assert address 773000.

Wait for INIT to finish.

The processor enters power-up routine.

The BM873 option recognizes the fetch of address 773024 or 773224 and asserts 173XXX plus the 8-bit

offset address to the data lines.

The processor reads location 773026 or 773226 which is always 000340 (priority level 7).

The processor fetches the next instruction from the ROM in address range 773000—773776. From this

point, the bootstrap loader program contained in the ROM has control. (In the PDP-11/35 and
PDP-11/40 systems, the PSW is fetched before the PC.)
If an actual power fail occurs in a nonvolatile memory system, the BM873 option does nothing, and the power-down

and power-up traps work in the normal manner. If an actual power fail occurs in a volatile memory system, the
power-up jumpers in the processor are set for 173224. During power-up the processor will fetch from 173224; the

combination of address 773224 and no external lines asserted will cause the BM873 option to assert line 1 as a
default case. Thus, in this case, the offset address selected for line 1 becomes the bootstrap loader call for power fail.
Data is read from the ROM in two bytes. Address bits 7 through 1 are present at all times via the bus receivers.
Address bit O is generated on the module. AO is always clear prior to a read cycle. The setting of AO clocks the first
byte into a holding register and simultaneously changes the address to gate the second byte to the output drivers.

After a delay of about 200 ns, the output gates are enabled and the ROM data is placed on the Unibus. SSYN is
asserted about 150 ns later, completing the read cycle. Figure 1-2 illustrates memory read timing.

ADR 8 CONTROL __l—

MSYN (READ)

AY (1) H

RDDOLY (@) H

200ns )

DATATO BUS (I)H

BUS SSYNL

—]

[ 500 ns

OR LESS

I50ns

[ DEPENDENT ON
BUS LENGTH

1-2407

Figure 1-2

Memory Read Timing

CHAPTER

INSTALLATION ANDCHECKOUT

2.1

INSTALLATION

Normally the BM873 Restart/Loader is installed at the factory and
this option is added to an existing system, it may be necessary to

no further installation is required. However, if
add wiring to make the AC LO and DC LO signals

available. These signals are provided on the PDP-11/05 and PDP-11/45
processors, and on the DD11-B. On the

PDP-11/15, PDP-11/20, PDP-11/35, PDP-11/40, and the DDI1-A
it is necessary to ensure that the SPC slot
containing the BM873 has BUS AC LO and BUS DC LO wiring available

as follows:

Pin CV1 to BOIF1 or BO4F1 (BUS AC LO)

Pin CN1 to BO1F2 or BO4F2 (BUS DC LO)
If the wiring is not present, it must be added by hand-wiring,

backplane wiring.

using a wire color different from that of the existing

NOTE

The BM873 option must be on the CPU side
2.1.1

of any bus buffer.

Start Address Selection

Each of the four external interface circuits has an associated
address which must be specified for that circuit to be
addressed. Each address consists of a fixed high-order portion
(773XXX) and a low-order portion (bits 8 through 1)
that is selected by adding or cutting diodes (Figure 2-1).
With the diode in, a 1 is placed on the Unibus. With the

diode out, a 0 is placed on the Unibus. When adding diodes,

a low-wattage iron should be used and care should be

taken with the plated mounting holes, so that the plating
is not lifted from the

(DEC type 664 or IN3606) should be positioned so that their cathodes

laminate by the heat. The diodes

point toward the gold fingers of the module.

Appendix A lists starting addresses for various devices used
with the BM873-YA, -YB, -YC and -YD Restart/Loaders.
The three rightmost digits of the address represent the low-order
portion to be selected via diodes.

The diagnostic program for this option contains a listing of

the loader program in the comments portion of the Data
Compare section. That diagnostic will be updated to contain the
starting addresses and listing of future variations.

2-1

8-PIN
MATE-N-LOK

CONNECTOR

L
1 >

2 =9
3->Q

4 >C

5 >
6 >0

750
8 >C

A
REARAT!

IR RNY]

(RENRERY

[

BM873 MODULE

11-2406

Figure 2-1

2.1.2

External Interface Circuit Diode Matrix

Jumper Selection

The BM873 module contains three jumpers that are marked with the numerals 1, 2, and 3. Jumpers 1 and 2 are used
to compensate for differences between the PDP-11/40 and 11/35 and all other PDP-11 family processors. Jumper 1
should be installed when the option is used with either the PDP-11/40 or the PDP-11/35. Jumper 2 should be
installed for use with any other processor in the PDP-11 family. For the BM873-YD, jumper 1 is always installed and
jumper 2 is always removed. Resistor R3 is also removed on the BM873-YD.
Jumper 3 controls access to an extra 128 words of ROM. When this jumper is cut, additional addresses from 773400
to 773776 become available. For the BM873-YB, -YC, and -YD versions, this jumper is always cut.

2.1.3

CPU Addressing with Volatile Memory

When this option is used in computers with volatile memory, the power fail trap address must be jumpered to
773224 if automatic reloading is desired.
For a PDP-11/45 CPU, install jumpers W6, W3, and W1 on the M8100 board. This will provide an address of 773224.
For a PDP-11/40 CPU, connect jumper W7 on the M7235 board for a binary 1. This jumper will provide an address
of 7732XX. The last two digits are provided by jumpers 4 and 2.

2-2

2.2

CHECKOUT

The diagnostic program for the BM873 option is MAINDEC-11-DZBMD-D. This program starts with a dialogue and

is self-explanatory. As new ROM programs are implemented, this diagnostic may be modified. However, the basic
version may be used on all option variations as long as the user visually checks the ROM data following the first pass.
The diagnostic contains the instructions for its own operation. The opening dialogue establishes which option
variation (-Y
A, -YB, etc.) is being tested.

2-3

CHAPTER

PROGRAMMING

This device is a Read-Only Memory and requires no programming. However, certain factors must be considered in
system programming as the following paragraphs explain.
3.1

POWER FAIL PROGRAMMING

With the BM873 option installed, the power-down/power-up routines may require modification, depending on the

bootstrap used. Use of the external interface causes the power-fail sequence in the CPU when AC LO is detected
going low; the power-up trap program is not used, and, therefore, not restored.

This is not a problem when a bootstrap loads into core and overwrites location 24, because the new program will set
up the power-fail routine. However, if the new program does not reload location 24, the next power-fail sequence
(may be real) will find the power-up restore program instead of the power-down routine.

This condition can be resolved by the power-fail routine testing this option with any DATI instruction. The
combination of this option and a real power-fail will cause the DATI to perform in a normal manner. The

combination of this option and the external interface active (causing the AC LO and trap) will cause a nonexistent
device trap (no SSYN) to location 4.

MOV

#1S,@#4

; TRAP CATCHER

CLR

@+#6

TST

@#173000

; DEV BLIND?

#PWRUP @#24

; REAL PWR FAIL

NOP

2S:

MOV
(SAVE ROUTINE)

1S:

HALT
Example 1

The above program works because this option goes “blind” (will not return SSYN) when it has been activated by an
external interface signal. This condition continues from the assertion of AC LO until the release of DC LO.
3.2

There are no registers in this device. There are four flip-flops that can be loaded for diagnostic purposes but they
cannot be read.

3-1

CHAPTER

OPTIONS

4.1

USER CUSTOM PROGRAM FOR THE BM873-YA

Two etched circuit positions on the BM873-YA board provide an extra 128 words of ROM. To add this extra
memory capacity, Jumper 3 must be cut, permitting address recognition of all 256 words.
Figure 4-1 is a sample ROM program data sheet that can be helpful in programming the ROMs. Columns 1 and 2

contain the PDP-11 program listing. From the address data in column 1, the ROM starting address can be determined
and the offset diodes cut (diode = 1; no diode = 0). The data in column 2 must be expressed in binary form as in

columns 3 and 4. (Note that byte 1 is moved to the line below that of the original entry.) The eight binary digits for
each byte are then shifted into columns 5 and 6 under the ROM B and ROM A headings, respectively. Columns 7
and 8 contain the resulting ROM address in binary and decimal form, respectively. Column 8 consists of four
columns of decimal addresses, distinguished by the configuration of the 2 MSB of the binary address. Each program
data sheet contains 64 ROM locations (32 words), hence four sheets are required to encode all 128 words.
Therefore, only one of the four subcolumns of decimal addresses actually applies for each sheet, and the other three
should be crossed out to avoid confusion. The 2-column checklist between columns 7 and 8 can be used for checkoff
purposes, e.g., checking off ROMs as they are blasted.

A blank program data sheet is included in Chapter 6 to assist the user in programming the read-only memory of the
BM873.

Customers who wish to create their own programs can purchase PROMs from integrated circuit vendors or
distributors. Some distributors have programming capabilities so that programmed ROMs can be purchased. The
following PROMs have been found acceptable:
Intersil type 5603
A

Monolithic Memories Inc. type 6300

The following PROMs have not been tested but according to the manufacturer’s data should be acceptable. Any
PROM that is specified to be “pin compatible with the 74187 should work in this application.
National Semiconductor type DM8573

Signetics type 82526

4-1

_!_

__|

4-2

CHAPTER

INTERFACE

The external interface consists of four separate high-impedance receivers with 4.7-kilohm resistors in series with each

one. A -15 V source is provided through 10 kilohms to facilitate the use of contact closures. The external interface
also accepts single-ended voltage inputs. A signal of 0.5 mA at -4V or greater will cause a Restart sequence. The
maximum permissible input is £25 V.

These inputs are filtered with RC networks and Schmitt triggers and have a time delay of approximately 10 to 15
ms. The signal must remain for at least 150 ms. Only one external line may be active at a time; two or more active at

the time of the sample will cause a race condition until one wins, but the result will be indeterminate.

The interface connector is an 8-pin male Mate-N-Lok (DEC Part Number 12-09340-01). Five pins (DEC Part Number
12-09378) are required for connection--placed as shown in Figure 2-1.

5-1

CHAPTER

ENGINEERING DRAWINGS

This chapter contains the 4-sheet engineering drawing of the BM873 (D-CS-M873-0-1)
and a blank program data
sheet for use in programming the read-only memory of this option. Use of these sheets
is described in Chapter 4 of
this manual.

6-1

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APPENDIX A

DEVICE STARTING ADDRESSES
BM873-Y
A Starting Addresses

Address

773000

Device Type

RF11 DECdisk

773010

RK 11 Disk

773020

Transfer to address contained in switch register

773030

TC11 DECtape

773050

TM11 DECmagtape

773100

RP11 Disk Pack

773144

RC11 Disk

773210

KL11/DC11 Console TTY Reader

773230

TA11 Cassette

773312

PC11 Paper Tape Reader

BM&873-YB Starting Addresses

Address

Device Type

773000

RH11/RS03 /RS04 Disk (Unit zero)

773002

RH11/RS03 /RS04 Disk (Unit specified in switch register)

773030

RK 11 Disk (Unit zero)

773032

RK 11 Disk (Unit specified in switch register)

773070

TC11 DECtape

773110

TM11 DECmagtape

773136

RF11 DECdisk

773150

RH11/TU16/TMO02 Tape Drive

773212

RC11 Disk

773230

RH11 Device Combination (Unit zero)*

773231

RH11 Device Combination (Unit specified in switch register)

773320

RH11/RP04 Disk (Unit zero)

773322

RH11/RP04 Disk (Unit specified in switch register)

773344

Transfer to address contained in switch register

773350

RP11 Disk Pack (Unit zero)

773352

RP11 Disk Pack (Unit specified in switch register)

773510

KL11/DL11 Console TTY Reader

773524

TA11 Cassette (Unit zero)

773526

TA11 Cassette (Unit specified in switch register)

773620

PC11 Paper Tape Reader

*If the TM02/TU16 is selected, the value in the console switch register is the position of the
TMO02 on the RH11, instead of the unit number on the TU16 drive. The slave unit number
(number on TU16) should still be zero.

A-1

BM873-YC Starting Addresses

Address
773000

Device Type
RF11 DECdisk

773010

RK11 Disk

773020

Transfer to address contained in switch register

773030

TC11 DECtape

773050

TM11 DECmagtape

773100

RP11 Disk Pack

773144

RC11 Disk

773210

KL11/DC11 Console TTY Reader

773230

TA11 Cassette

773312

PC11 Paper Tape Reader

773400

DUI11 Synchronous Interface

BM873-YD Starting Addresses

Address

Device Type

773000

Transfer to address contained in switch register

773014

TC11 DECtape

773304

RH11/RP04 Disk

773534

DTE20 10/11 Interface

A-2

Reader’s Comments
BM873 RESTART/LOADER
EK-BM873-TM-004

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