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AH-9047F-MC

April 1978

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Document:	CZQMCF0 MS11 0-124K MEMORY EXERCISER 16K APR 1978 bw
Order Number:	AH-9047F-MC
Revision:	000
Pages:	206
Original Filename:	CZQMCF0__MS11__0-124K_MEMORY_EXERCISER_16K__AH-9047F-MC__APR_1978_bw.pdf

OCR Text

0-124K MEMORY EXERCISER 16K

CZQMCFO

AH-9047F-MC

FICHE1OF1

APR 1

MADE IN USA

BO1
CIESICPORIC M..

~“8033C

RN o'

P-RED G,

SSTTXIBESEEBEZET

fa.l..7

LLE.

BR_ILIT emvE.

SoICFD O-i2w MEM ErEF 5

1S-FEBRURR
- 1978

2 - QOWSF ~-MC

IeTE.

R INTRINER:
“re

ard

:m10°mation

3%0uld

-srgeratiar,
13

nct

anyg er-ers

“ne

this

that

oas

subject

ore

may

appee-

change

witheutl

notice

o Commitment by Digitel Equipment

this

assumes

document.

raesponsibility

18 assumed foar the use or reliabilaty
of software on
not suppliad by Digitel or 1ts affilleted companies.

.c) 1978,

feiicuing

document

conttrued

cl!lili Equipment Corporation

e responsability
equipment thatl 13

Copgraght

CIAGNOSTIC ENGINEERING

1978 by Digital Equipment Corporation

toademarks

Sidva

PDF

UNIBUS

s 3

CEC.S

OECTRPE

of Digital Equipment Corporation:
MRSSBUS

]I
i L

ISSMCFS C-l2% MEM EXER

COl

Pags

REVISION HMISTORY

Revisior
Revision

Revision
Pevision
Revision

Re-3810r

MmO
o W D

SEZZEZZZIZXREXZTZXE

Mey

1975

October

1978

October

1976

June

1977

December

1977

Fetruary

1978

cce

DO1

Page 3

SCQMIFC J3-124 MEM ENER 1be

NEWhu-0)

CONTENTS

GENERAL PROGRAM INFORMATION.
Program Purpose

(Rbsiract)

Sgs'cm Requirements

Related Documents and Standards
Diagnostic Hierarchy Prerequisites
Rssumptions

OPERATING INSTRUCTIONS
Loading
and Starting Procedure

Spccxa? Environments

WWW

()

PERFORMANCE

DEVICE INFORMATION TRBLES
CORE PARITY REGISTER
PARITY

PROGRESS

REFCORTS

ut Luifue L)

)
[

MOS

MSII-K CSR

ARND

SUB-TEST SUMMARIES
Section ]l: Rddress Tests
Section 2: Worst Case "'o13¢ Tests
Section 3: Ingtruction Execution Tests
Section 4: MOS Tests
Special Toggle 1n Tests

mEeEeEeoeor

ERROR INFORMATICN
Error Reporting
Error Halts

Program Options
Exefution Times

we-03

L Whus-rN)

TUUTUTURY

~eredepetrer

TARBLE

PROGRAM

FUNCTIONAL

PROGRAM LISTING

FLOW

CHARTS

SES 2CO3

EOL

Page 4

SOQMCFQY J-124k MEM EXER l6h
1.3

GENERAL PROGRAM INFORMATICON.

Program Purpose

This

(Rbstract)

program has

the

abilit

000006 to address 7S7777.
A.

Unique

MWorse

addressing

case

Instruction

There

address

noise

The

12tent

any

test

and

special

routine

tests

provided

memory

from

address

all

wunibus

technigues

gattcrns.

thruout

also

address

Yt does 30 usirg:

execution

rcnvcs which

do not

this

program

general

designs

they

other

addressing

memory.

timeout,

type

as well

section 6.1

test

out

this

two(2)

toggie

document.

compr.hcns:vcl‘

possible
all
memory
systems
manufactured
by
DEC wilhout
conccnlratln, on any one system.
Rlthough the
tests
relate

E.G.”
tc

may

completely

test

regquired.

the

This

worst

complete

for

certain

systems.

run

11-L on up need no

case

patterns

also

notl

with

MS11-K MOS memory

test

test of
the memory.
Other
problems that this test 1s

Any core memory from %hc 8K

tests that
unable to.

another

intended
I/0 may

but
to

have

order

diagnostic

100%

find

memory

memory.

System Requirements
R.

Hardware
PCP1l

Requiremenis

family

cptiaonal...

Any

parily

processor

memory

control

Software
The

treap,

(6K

Requirements

smallest

HK.

module.

KTYI memory management.
B.

minimum

that

unit

any

entire

memory

address
bank

this

program

memory

bank
1s

will

causes

1gnored

recognize

timg
by

cut

the

program.

The program 13 designed 1o exercise the vector porticn cf
memory
(locations
"0-776)
1in exactly the same manner as
the rest of
memory.
To
make
this
possible,
without
requiring
memo-y
management,
no software traps are used

rot

the program.

"This means

that

1{ memor

management

avairlable or 1s disabled (SW12=1), 1, the program 13

reiccated out of bank O,
1! location 0-776
are
selected
for
test, and 1f an unexpected hardwuare trap occurs,
the
results will be unpredictable.

SEQ 0004

FO1

Page S

SDOMCFD D-134k MEM EXER 16b
The program
has
the
gropcr
rurning
wunder
the
automated
system - RCT1I and RPT,
()

Reiated

B.
C.
D.
.

Documents

Progremming

and

Practices - Document No.

Hierarchy

irstruction

175-003-009-01

Prerequisites

aiso

CPU diagnostic should
be
run
of
1ne
processor and PDP-11

set.

memory management

should

run

PDP-11-20
PDP-11-/34
PDP-11-40

OR
PDP-11/45 -~
PDP-11/60 KT11-C
KT11-D
-

before

this

used,

then

the

program.

MAINDEC-11-DZGKC
KTH
MAINDEC-1
-11-DF
1MAINDFC-11-DBQER
MAINDEC-11-DCQKC
MAINDEC-11-DCGKC
MAINDEC-11-DGKDA
MAINDEC-11-DCKTR
MRINDEC-11-DBKTR

n
mn
n

ce.d

i.c

CPERATING

THRU DCKTF
THRU DBKTF

Lcading

the

CPU

and,

INSTRUCTIONS

and

Starting

Procedures

voad the program using any standard absolut+ loader.
Slarting

asddress

program

Starting

Slarting

“estar!

200:

execution.

address

Allows the
first
and
to be used
Ll

diagnostic

Rssumptions

armal

KT1l

This grogram assumes the correct operation
used, the memory management option.

allow
line

Standards

Before running
this program, a
to
verify
the
functionality

to
test

PDF-1} NflI&DEC SYSMAC Package - MAINDEC-11-DZQAC-C2-D
The applicable Memory
System Maintenance Manual
The aspplicable C:rcu?t chematics

Diagnostic

interface
code
manufacturing

204:

operator
to
1nput,
last addresses to be
1n tests b and 7.

Address

program

via
teletydpe
exercised,
dnd

conversation,
data patiern

210:

using

previcusly

selected

pakameters.

<E% 003S

CZAMCFO O-124k MEM EXER i6h
2.i.t

Starting Rddress 214:

Restore

relocatin

locaders
the

was halted

and

halt.

program back

while running
procedures

the

This

top

required

routine

barks O and

two banks

for

this

are

special

AR.

11 memor
addresses
0-1000
have
e1ther through parameter selection

with

SWOS=1l,

then:

%ood Rddress
ress START,
B.

running

capatle

the

of memory.

nol
been
(SR=204) or

program

There

exercised,
by running

214,

without

memory

management,

then:

relocated),
Press START.

the

progrem

1t runnnn' with memory
management and the unibus has
not
been
1nilialized
(via
reset i1nstruction, startl switch,
etc.),

then:

Load Rddress
Depos.t 214

Press

running

777707

with

1~1ti1alized:

memor; management

(Example:

Load Address
Deposit
Load Rddress
Jeposit

Press

Starting

Byte

address

oddress

(PC)

CONTinue

Lcad Address
Deposyt

€. 1.t

situation.

Load Address <21M+relocation factor>
(Relocation factor
1s
typed
when

and

the

772340
(KIPRRO)
<(relocation factor)

unibus

100>
Relocation factor=S40000,
dc;osxt 00S400)
777572
(SRO)
000001
7?7737
(PC)
2l4
Continue

has

been

then

220:

memor

typeout

routine.

This

routine

gerforms DATI, DATIP,” Batc¥®’snd DATOB ‘on 1l possibie
dddresses, and types the ranges of
addresses
which
do
not
cause & timeout ‘rap.

c.2

Special
iy

the

“PT1l

Environments
program

tne”

run

program

quick

verify

mode

wunder

13 done after t*c first pass.

RCT1l

Rliso, the

GO1

Page &

2098

HO1

Page

SOQMIFJ J-124k MEM EYVER 16k

1al]

program dces

rot

ralocate

the

lower

SEG 00C7

of memory.

Program Options

-SWIS = 1 OR UP....

HALT ON ERROR

Skil4 = 1 OR UP....

LOOP ON TEST

Swl3 =1 OR UP....

INHIBIT ERROR TYPEOQUT

SWi2 = 1 OR UP....

INHIBIT MEMORY MANARGEMENT

(INITIAL

ONLY)

START

SWIl = 1 OR UP. ...

INHIBIT SUBTEST ITERRTION

SWIC =1

OR UP....

RING BELL ON ERROR

SW3

OR UP....

LOOP CN ERROR

SWB8

OR UF....

LOOP ON TEST

SWe

OR UP....

INHIBIT PROGRAM RELOCARTION

SWe

OR UP....

INHIBIT PRRITY ERROR DETECTION

NOTE:

With parity error detection enabled, o
memory
failure
while
running
the worse case noise tests (non-parity)
con cause a parity error.
The
error
rintgut
on
"a

gari1ty
drop or
to

run

then,

SWE

test

error
pickup
the

restart

does
will

not
noct

grogron
the

type the
be typed

for

program

OR UP....

IN SWR<4:0

pass

with

good data.
Thus
as such.
It
is
with

parity

parlt!

enabled.

b1l
best

disabled,

INHIBIT EXERCISING VECTOR ARER
(LOCATIONS

0-1000).

EXECUTION TIMES
Execution

memory.
o.

time

dependent

type

MWorse case run times ul*

memory,

For Non-Parity Mermory
First Pass:
65
seconds
seconds for each additional! 1Bk.

for

Full

seconds

first

pass

Pass:

3 minutes

for

Iteration

Inhibited:

5° °ar1t¥
First Fas

ecach

Memcr4

3 minutes

additional
same

and

amount

900ns memorys are:

16k.

first

seconrds

for

per

15k

first

1lbk.

¢+

lbk

I01

Page 8

SoSMCFQ O-12%w MEM EXER 16%

Iteration

Inhiti1ted:

same

lBFK

per

B minutes

Full Pass:

first

pass

ERROR INFORMATION
Error Reporting
Thers are a total of 31(B) tggcs
by the proirnn.
Some
' the
key
descr.bed

below

for

Program

ty:

Counter

error

detection

Virtual Program Counter.
This
detection code can be found in

F PC =
TRP PC

v BCaPPC)

v P2

of error
reports
generated
column heading mnemonics are

thsxccl Program Counter.
delection code 13 actually
=

Physical

Program

Courter

code.

13
where
the
arror
the program listing.

This 18 where
the
located 1n memory.
the

code

which

error

caused

trap.

RES

=
=

Memory

Rddress

Parity

Processor

address.

Status

word.

ILY

Iagtruction

€SB

Khat

contents

Should

WAS

What

contents

WAS.

Error

Under

Test.
Be.

Haills

With the "HALT ON ERROR' switch
(SW1S)
not
several programmed "HALYS' 1n the program:
4.

In the
vector

error _trap tervice
4.
This one will

before the
be printed

erroout.

report

In_

the

relocation

code

was

not

relccated

In
to

back

able

the-e

routine for urexpected
occur 1f a 2nd trap to

for

routine

the

set

first

the

first

the

transferred

the case of errnr reporting and
allow tre 1nformation transfer.

has

had

program

memory

and

properly.

there

traps to
4 occurs
chance to

the

are

being

program

terminal

JO1

Page 9

SCQMCFQO 0-124k MEM EXER léIn

the

stoarted

power

complete

€.

fa1!

before

1tself.

the Memory

control

routine

the

mapping

routines,

power

the

down

routine

failures

wup

power

sequence

{ind

any

sequence

had a chance

the

a meaningful

was

address

map.

PERFORMANCE AND PROGRESS REPURTS

Not

applicable

DEVICE

INFORMATION TRBLES

Tre following 13 & picture view of a
parat
registers,
which
will show bit assignments
to

provide

a»

handy

reference:

control
status
and definitiors,

CORE PRRITY REGISTER

514131211
E1t

1009 08 07 06 05 04 03 02 01

assignmerts

BITiS

BITS

are

defined

follows:

PRARITY ERROR

11-E

BITO2

ERROR AODDRESS

HIGH
ORDER _ RDDRESS
OF
ADDRESS
OF
gggs
(BITS
ITY _ ERROR
17-11 OF ADDRESS)

WRITE WRONG PARIT:

NORMAL
PARITY
CLERR;
WHEN

(0DP)
OTHER

PRRITY (EVEN) WHEN SET

BITCC

ACTION ENRBLE

MGS PRRITY

NO ACTION
70
TRAP
AHEN SET

1111111 1711171.711.1

'PEY

aupY

1
1S

1009 08 07 O6 05 C4 03 02 O!

0OC

WHEN
CLEAR
114
JECTOR

SEG 0009

KOl

Page 10

co@MCFO O-12% MEM ENER 16k
BIT ASSIGNMENTS RRE DEFINED RS FOLLCOWS:
BITIS

PARITY ERROR

NORMAL

WRITE WRONG PARITY

BITO2

WHEN

(0DD)

PARITY

OTHER

CLEAR:

PARITY (EVEN) WHEN SET

BITOO

RCTICN ENRBLE

NO RCTION

WHEN

TRAP
10
WHEN ST

VECTOR

CLEARR
114

MS11-K CSR
P

;

RDDRESS

isszxp DCIEC'EE!

15 14 13 12 11

10 09 08 07 Oe 0S5 O4 03 02 01 OO

BIT RASSIGNMENTS RRE DEFINED RS FOLLOWS:
BITIS

OOUBLE ERROR

BIT

SET

INHIBIT MODE

W HEN

T0 R

IS BIT

GSET

ENRBLES THE
I IT POQINTER
_TO
MO

M
DE
THE
EITHER
1 N M IB 17
F R
_lb¥¢
SECOND
OR
IRST
'3
gvsn
GOING INTO
ROM
0
OR
THd
CHECK
DIA
EC c D1 S RABLE MODE.
“

BITS

::-C

ERROR ADORESS

W H EN
BITO2
CLERRED
ORDER
HIGH
C 0 NTRINS

OF
B ) TS
P
A RITY
1 7 -11

ADDRESS
OF
ERROR(BITS

WHEN

CONTQINS

SE
8 1 1S FOR ECC.
BITCH

SINGLE ERROR

SET
WHENEVER
ERROR OCCURS

BIT03

INHIBIT MODE POINTER

THE
INHIBIY
POINTER
WORKS

BIT02

CHECK

SINGLE

MODE
IN
CONJUNCTION
WITH
THE
INHIBIT MODE BIT
SET

EN BIT

nsnokv

13 IS SET

710

A 1sx PORTION OF

INHIBITTED

FROM
opznnr:nc IN THE
OR
MODE
DISABLE
EcC

oo,

See 0010

Page 1.

CZaIMCFO 0-124% MEM EYER 1B

DIAGNOSTIC CHECK

MODE.

THE
INHIBIT
MODE
POINTER
INCICATES
WHICH
16K
1S5
BEING

INHIBITED,
. ,BIT 3 =I

THE
SECOND
1BK
OF
MEMORY
:S INWIBITTED.

WHEN BIT 13 IS SET
TC
R
0,
BIT
3
BECOMES

INOPERATIVE.

BITC2

DCIARGNOSTIC CHECK

WHEN

SET

READ-WRITE

BITS(SEE BITS

ENRBLES
CHECK

11-5)

BITGL

CISABLE ERROR CORRECTION

EPROR
NO__
SET
WHEN
CORRECTION TAKES PLRCE

BITOO

DOUBLE ERROR ENRBLE

WHEN SET ENRBLES
T0

VECTOR

DOUBLE ERROR.

114

TRAP

SUB-TEST SUMMARIES
6.1

Section
These

TEST

Rddress

tests

verify

HWraites

Rddress

1nto

and

that

Tests.
the

uniqueness

reads

Memory

the

every

value

location.

RAfier

written, all locations 2rc checked again.
TEST 2
MWrites the byte
location and checks
1t.

TEST 3

cach

address

each

word

the

complement

TEST 4
UWrites
and checks 1t.

the

and

checks

1t.

bank

number

mple men*

ghccks 1l

Section 2:
These

types

TEST &
select

Worst

are_intended
of

POP-11

and
&

“€ST

Case
‘o

cure

7 Are

single

Noise
apply

1nto
the

ecach

bank

addrass.

memory

has

MWord

been

1nto

that

byte

address

1nto

that

byte
number

that
1nto

bank
each

Tests.
maximum

memories.

word

e¢ach

all

value

ULrites

location

memory

supplied
data

stress

allow

the

pattern

(SA=204)

the

various

ap ¢~ator
an ¢ SCOPE

to
on

SE% 0011

MOl

Page

cIOMCFO O-l124k MEM EXER &b

they the writing

*éST ;

that

doa

TEST 10

Writes

TEST

Writes

all

ncnor' with

TEST

Writes
¢

1
ali

memory

TEST

:3,14,15,

AND 16

TEST

the po’x y delec tion

patterns which

“RipplesTM
“RipplesTM

and

are

“0"

through

that

skipped

checks

2.3

for

series

they

bit

a nd

then

with O°s

i1n

overy

bit

o nd

then

memory.

each
byte
of
logic works.

Instruction Executlion

Tests,

TEST 23
DRTOB on

Executes
the high

an 1nstruction
byte.

which

TEST

Ezxecutes

which

does

TEST 25
DATOB on

Executes an i1nstruction which
the low byte.

TESYT

EXECUTES

DRTO.

CATOB
.-

Section

the

byte

Mos

memory

INSTRUCTION

byte.

WHICH

DRTI

an d

and

under
Chacks

DARTO

does

DARTI

and

does

DAT]

and

DRTIP

and

does

DRTIP

and

DOES

DRTIP

and

through

memor

test.

Tests

TESY 27

~Writes

pattern

addressing

upward

conglnncnta

sddressing

Jpward

fFatterrns

which

under

1nstruction

high

instruction

does

Ezxecutes

low

memory

the
maemory
and finally ,

TEST 22

the

which

and
m emor
This t,st 1s

through

correctly.

TEST 21
Executes an 1nstruction
on the memory under test.

DRTOB on

compleme nts when

pattern which

code

executed

word

every

Qnr:t‘

“randomTM

single

This group of tests place 1nstructions 1n
test,”
then
executes
the
instructions,
that

parity memory.

program

1t.

Section 3:

stress
1°s

Write

non-parity

MWrite

BIT 9 complaments.

MWrites wron

checks

1l.

through

address BIY 3'xOR

TEST 20

then

designed

(DRTI)

the reading

an TEST & or

(DATO)

f..

addressing

and

000377

downward,

compliments

’inallg

downward.

comfi

the

iments

compliments

third

this

{he

then

new

pattern
new
RB

SEw 0012

NO1

Page 13

cZOMCFO 0O-124K MEM EXER 16n
TESY 30-31
MWrite a checkerboard through memory
then
fcr 2 seconds and then verifies no data has changed.
Toggle

[L4]

Specia!

6. S. 4

stalls

Tests

Toggle-in-prcgram

The following 13 & toggle 1n memory address test.
This
test
18
yseful
Wwhen
an
address
selection failure 1s suspected
involving
the first BK of mamory.
This
oprogram
writes
the

value

limit

have

and

each

beer

iontcn}t
ower

address

continuing
written

.each

::ortxng with

nto Yt:clf starting

the

upper

address

upper

limit.
1s

11mit

After

checked

and

with the lower
all

for

addresses

the

corract

continuing

the

lam:t,

LOCATICN CONTENTS
10
0127C0

MNEMONIC
MOV 8S0,RO

COMMENT
;GET_FIRST RDDRESS

MUv RO,RI
MP RO,3#SWR

; (EXAMPLE START ADDRESS:
i SRAVE IN Rl
;CHECK UPPER LIMIT

;BRANCH IF RT UPPER LIMIT
;LOAD VALUE INTO ADDRESS

LI ¥

00G0Sso

14
16

010001
020037

ae
24

001403
010010

BEG 2%
MOV RO,

30
32
34
*+ 3t

000772
010004
020001
001767

BR 1%
MOV RO,RY
CMP RO R!
BEQ 1S

“c
<y

301774
0000Ccao

1$:

17?7570

065720

2%:
33.

ae4030

(RO)

TST (RO)+

CMP

-(R0O)Y,RO

BEQ 3$
HALT

0ogrze

program

; (IN SWITCH REGISTER)

; STEP TO_NEXT RDDRESS

;LOOP UNTIL DONE
; SAVE UPPER LIMIT
;CHECK IF AT LOWER LIMIT
;BRANCH IF DONE
;CHECK

;BRANCH
; ERROR
:LOOP

WRITTEN

BRCK

toggling

"Z7ES:

The upper
limit
address
obtained
from
registar
may
be
changed
during
program
However occasionally the program may
halt

BOUNCE".

LRA=i0%%set

DRTR

~f+ar

"SWITCH

the

; TO TEST

t{The

best

upper

limiias,

procedure

start

the
switch
operation.
because
of

when

changin

1£]

limits 18 to stoT
the
program
make
the
change
an
continue.)
The
lower Jimit address (12) may be patched
to any desired address.

Toggle-1n-Program

The following 18 also & togale 1n
program
to
toggle-in-program 8! for more complete address
prcgram

writes

the

complement

value

e¢ach

be
used
testing.
address

with
This
into

1tself
startan
with
the upper limit and continuing to the
lower limit.
RAYter all
addresses
have
been
writien
each
address 13 checked for the correct contents starting with the

£ 0013

BOe

Fage .=

IZa.FD J-.3we Nt ECER L
ccr!.»..»!
#-4d
addass
scn€" Jim,t
i39:e 1% the foi.cwming patctes 3 the

Trese

8-a

'he

patitas

COCRTION
s

82
€
Sk

are

the

905 142
020201
061375

020204
061755
010203
0051063
020322
001772

000770

000000

PROGRAM FUNCTIONRL

PROGRAM _ISTING

Attached

Résached

BEQ 4$

additions

CONTENTS
010402

6G
62
[
66
=
~2

toggle-in-grogrem

MNEMONIC

COCARTION CONTENTS
G
i0C
001404
k)
Trhese

4§:

the
to
progroam

wppe:
adove.

8i:

COMMENT
: CHANGE
LOWER iTMI°
:BRANCH TO PROGRAM 87

toggle-in-program #1:

MNEMONIC
MOV RY,Re

COMMENT
:GET UPPER LIMITY

BNE SS

:LOOP UNTIL DONE

58: COM -(R2)
CMP R2,RI

68: CMP R2,RY
BEQ 1S
MOV R2,R3
COM R3
CMP R3, (R2)+
BEG 6§
HAL T

BR 6%
FLOW CHARTS

: COMPLEMENT RDDRESS
‘CHECK IF AT LOWER LIMIT
:CHECK IF AT UPPER LIMI”
:GO TO PROGRAM | IF DONE
:GET VALUE OF ADDRESS
: COMPLEMENT VALUE
:CHECK ADDRESS
:BRANCH IF OK
: ERROR

160 CHECK NEY¥~ ARDDRESS

coe

16+

FLOW CHART

FRRRRRRFFRBRIRAD

CZQMCFC

D-124k

MEM EXER

16K

FEFRBERBEIRELRES

DECFLC VER

00.07 20-FEB-7B 07:S8

PA&GE A

MEM ENER

D-1324+

SSQMCFT

J-124k MEM EXER 16k

DO2

TABLE OF CONTENTS

FRRBRTRRARERIRIIRES

PRSE O1

DEFINITIONS.

PAGE

RESTART AND RESTORE

PAGE

0Ou

POWER

PRGE

COMMON

PAGE

SETUP

PAGE

MAP

PAGE

MEMORY

PAGE

MAP PRRITY REGISTERS

PAGE

MAP PRRITY MEMORY

PAGE

TEST

PAGE

USER PARAMETER SELECTION SECTION

PAGE

START1:

PAGE

SECTION

PAGE

TEST

PAGE

TEST

PARGE

TEST

PAGE

TEST S

PAGE

SECTION

PAGE

TEST

FAGE

TEST

PAGE

TEST

PAGE

TEST

PAGE 27

TEST

i3:

3 XOR 9

PAGE

TEST

14:

XOR 9

PRSE

TEST

18:

XCR

FAIL

TRAP CATCHER,

STARTING ADDRESSES.

ROUTINES